diff --git a/README.md b/README.md
index a38127a3..9ace27a4 100644
--- a/README.md
+++ b/README.md
@@ -17,7 +17,7 @@ A few tests are executed by running the SBSA ACS Linux application which in turn
 
 
 ## Release details
- - Code Quality: REL v3.1
+ - Code Quality: REL v3.2
  - The tests are written for version 6.0 of the SBSA specification.
  - PCIe RCiEP tests for Appendix E of SBSA 6.0 specification are also included.
  - The compliance suite is not a substitute for design verification.
@@ -146,7 +146,7 @@ On an emulation environment with secondary storage, perform the following steps:
 
 ### Emulation environment without secondary storage
 
-On an Emulation platform where secondary storage is not available, perform the following steps:
+On an emulation platform where secondary storage is not available, perform the following steps:
 
 1. Add the path to 'Sbsa.efi' file in the UEFI FD file.
 2. Build UEFI image including the UEFI Shell.
@@ -178,8 +178,8 @@ The details of the hardware or Verification IP which enable these exerciser test
 
    Below exerciser capabilities are required by exerciser test.
    - MSI-X interrupt generation.
-   - Incoming Transaction Monitoring(order, type).
-   - Initiating transacions from and to the exerciser.
+   - Incoming Transaction Monitoring (order, type).
+   - Initiating transactions from and to the exerciser.
    - Ability to check on BDF and register address seen for each configuration address along with access type.
 
  - SBSA Test 403 (Check ECAM Memory accessibility) execution time depends on the system PCIe hierarchy. For systems with multiple ECAMs the time taken to complete can be long which is normal. Please wait until the test completes.
@@ -188,7 +188,7 @@ The details of the hardware or Verification IP which enable these exerciser test
 SBSA ACS is distributed under Apache v2.0 License.
 
 
-## Feedback, contributions and support
+## Feedback, contributions, and support
 
  - For feedback, use the GitHub Issue Tracker that is associated with this repository.
  - For support, send an email to "support-enterprise-acs@arm.com" with details.
@@ -197,4 +197,4 @@ SBSA ACS is distributed under Apache v2.0 License.
 
 --------------
 
-*Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.*
+*Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.*
diff --git a/baremetal_app/SbsaAvs.h b/baremetal_app/SbsaAvs.h
index 3f38e989..6d4ef25f 100644
--- a/baremetal_app/SbsaAvs.h
+++ b/baremetal_app/SbsaAvs.h
@@ -21,7 +21,7 @@
 
 
   #define SBSA_ACS_MAJOR_VER  3
-  #define SBSA_ACS_MINOR_VER  1
+  #define SBSA_ACS_MINOR_VER  2
 
   #define SBSA_MIN_LEVEL_SUPPORTED 3
   #define SBSA_MAX_LEVEL_SUPPORTED 6
diff --git a/baremetal_app/SbsaAvsMain.c b/baremetal_app/SbsaAvsMain.c
index 9b77316c..c868971f 100644
--- a/baremetal_app/SbsaAvsMain.c
+++ b/baremetal_app/SbsaAvsMain.c
@@ -91,7 +91,8 @@ createTimerInfoTable(
 {
   uint64_t   *TimerInfoTable;
 
-  TimerInfoTable = val_memory_alloc(sizeof(TIMER_INFO_TABLE) + (2 * sizeof(TIMER_INFO_GTBLOCK)));
+  TimerInfoTable = val_memory_alloc(sizeof(TIMER_INFO_TABLE)
+                   + (PLATFORM_OVERRIDE_TIMER_COUNT * sizeof(TIMER_INFO_GTBLOCK)));
 
   val_timer_create_info_table(TimerInfoTable);
 }
@@ -102,7 +103,8 @@ createWatchdogInfoTable(
 {
   uint64_t *WdInfoTable;
 
-  WdInfoTable = val_memory_alloc(sizeof(WD_INFO_TABLE) + (2 * sizeof(WD_INFO_BLOCK)));
+  WdInfoTable = val_memory_alloc(sizeof(WD_INFO_TABLE)
+                + (PLATFORM_OVERRIDE_WD_TIMER_COUNT * sizeof(WD_INFO_BLOCK)));
 
   val_wd_create_info_table(WdInfoTable);
 }
@@ -115,11 +117,14 @@ createPcieVirtInfoTable(
   uint64_t   *PcieInfoTable;
   uint64_t   *IoVirtInfoTable;
 
-  PcieInfoTable = val_memory_alloc(sizeof(PCIE_INFO_TABLE) + (1 * sizeof(PCIE_INFO_BLOCK)));
+  PcieInfoTable = val_memory_alloc(sizeof(PCIE_INFO_TABLE)
+                  + (PLATFORM_OVERRIDE_NUM_ECAM * sizeof(PCIE_INFO_BLOCK)));
   val_pcie_create_info_table(PcieInfoTable);
 
-  IoVirtInfoTable = val_memory_alloc(sizeof(IOVIRT_INFO_TABLE) + (4 * sizeof(IOVIRT_BLOCK))
-                                                               + (16 * sizeof(ID_MAP)));
+  IoVirtInfoTable = val_memory_alloc(sizeof(IOVIRT_INFO_TABLE)
+                    + ((IOVIRT_ITS_COUNT + IOVIRT_SMMUV3_COUNT + IOVIRT_RC_COUNT
+                    + IOVIRT_SMMUV2_COUNT + IOVIRT_NAMED_COMPONENT_COUNT + IOVIRT_PMCG_COUNT)
+                    * sizeof(IOVIRT_BLOCK)) + (IOVIRT_MAX_NUM_MAP * sizeof(ID_MAP)));
   val_iovirt_create_info_table(IoVirtInfoTable);
 }
 
@@ -130,11 +135,12 @@ createPeripheralInfoTable(
   uint64_t   *PeripheralInfoTable;
   uint64_t   *MemoryInfoTable;
 
-  PeripheralInfoTable = val_memory_alloc(sizeof(PERIPHERAL_INFO_TABLE) +
-                                        (1 * sizeof(PERIPHERAL_INFO_BLOCK)));
+  PeripheralInfoTable = val_memory_alloc(sizeof(PERIPHERAL_INFO_TABLE)
+                        + (PLATFORM_OVERRIDE_PERIPHERAL_COUNT * sizeof(PERIPHERAL_INFO_BLOCK)));
   val_peripheral_create_info_table(PeripheralInfoTable);
 
-  MemoryInfoTable = val_memory_alloc(sizeof(MEMORY_INFO_TABLE) + (PLATFORM_OVERRIDE_MEMORY_ENTRY_COUNT * sizeof(MEM_INFO_BLOCK)));
+  MemoryInfoTable = val_memory_alloc(sizeof(MEMORY_INFO_TABLE)
+                    + (PLATFORM_OVERRIDE_MEMORY_ENTRY_COUNT * sizeof(MEM_INFO_BLOCK)));
   val_memory_create_info_table(MemoryInfoTable);
 }
 
@@ -282,4 +288,3 @@ ShellAppMainsbsa(
 
   return 0;
 }
-
diff --git a/docs/Arm_SBSA_Architecture_Compliance_User_Guide.pdf b/docs/Arm_SBSA_Architecture_Compliance_User_Guide.pdf
index 789d5df6..99796a3c 100644
Binary files a/docs/Arm_SBSA_Architecture_Compliance_User_Guide.pdf and b/docs/Arm_SBSA_Architecture_Compliance_User_Guide.pdf differ
diff --git a/docs/Arm_SBSA_Architecture_Compliance_Validation_Methodology.pdf b/docs/Arm_SBSA_Architecture_Compliance_Validation_Methodology.pdf
index 72ef07bb..f85dfc68 100644
Binary files a/docs/Arm_SBSA_Architecture_Compliance_Validation_Methodology.pdf and b/docs/Arm_SBSA_Architecture_Compliance_Validation_Methodology.pdf differ
diff --git a/docs/Exerciser_porting_guide.md b/docs/Exerciser_porting_guide.md
new file mode 100644
index 00000000..27eb372a
--- /dev/null
+++ b/docs/Exerciser_porting_guide.md
@@ -0,0 +1,156 @@
+# Exerciser Porting Guide
+This document gives details of the various PCIe capabilities that exerciser device supports and how the exerciser is supposed to behave.
+
+## Introduction to PCIe Exerciser Endpoint Device
+PCIe Exerciser is a client device wrapped up by PCIe Endpoint. This device was created to meet SBSA (Server Based System Architecture) requirements for various PCIe capability validation tests.
+
+### Generating DMA
+- Before triggering DMA all the required DMA attribute fields like DMA bus address, DMA length, exerciser instance fields should be correctly set <br/>
+**pal_exerciser_set_param(Type, Value1, Value2, Bdf)** <br/>
+Type - DMA_ATTRIBUTES<br/>
+Value1 - Buffer containing the data or the Buffer where the data to be copied<br/>
+Value2 - Size of the data<br/>
+BDF - BDF of the exerciser<br/>
+- Trigger the DMA to/from the buffer<br/>
+**pal_exerciser_ops(Ops, Param, Bdf)**<br/>
+Ops - START_DMA<br/>
+Param - EDMA_TO_DEVICE or EDMA_FROM_DEVICE<br/>
+Bdf - BDF of the exerciser<br/>
+<br/>
+
+### Generating DMA with PASID TLP Prefixes
+- Program exerciser to start sending TLPs with PASID TLP Prefixes. This includes setting PASID Enable bit in exerciser PASID Control register and the implementation specific PASID Enable bit of the Root Port.<br/>
+**pal_exerciser_ops(Ops, Param, Bdf)**<br/>
+Ops - PASID_TLP_START<br/>
+Param - Substream ID<br/>
+Bdf - BDF of the exerciser<br/>
+**pal_exerciser_set_param(Type, Value1, Value2, Bdf)**<br/>
+Type - DMA_ATTRIBUTES<br/>
+Value1 - Buffer containing the data or the Buffer where the data to be copied<br/>
+Value2 - Size of the data<br/>
+BDF - BDF of the exerciser<br/>
+- Trigger the DMA to/from the buffer<br/>
+**pal_exerciser_ops(Ops, Param, Bdf)**<br/>
+Ops - START_DMA<br/>
+Param - EDMA_TO_DEVICE or EDMA_FROM_DEVICE<br/>
+Bdf - BDF of the exerciser<br/>
+- Disable exerciser to stop sending TLPs with PASID TLP Prefixes.<br/>
+**pal_exerciser_ops(Ops, Param, Bdf)**<br/>
+Ops - PASID_TLP_STOP<br/>
+Param - Substream ID<br/>
+Bdf - BDF of the exerciser<br/>
+<br/>
+
+### Generating DMA with No Snoop TLP
+- Program exerciser hierarchy to start sending/receiving TLPs with No Snoop attribute header. This includes disabling No snoop bit in exerciser control register.<br/>
+**pal_exerciser_ops(Ops, Param, Bdf)**<br/>
+Ops - TXN_NO_SNOOP_DISABLE<br/>
+Param - Null<br/>
+Bdf - BDF of the exerciser<br/>
+**pal_exerciser_set_param(Type, Value1, Value2, Bdf)**<br/>
+Type - DMA_ATTRIBUTES<br/>
+Value1 - Buffer containing the data or the Buffer where the data to be copied<br/>
+Value2 - Size of the data<br/>
+BDF - BDF of the exerciser<br/>
+- Trigger the DMA to/from the buffer<br/>
+**pal_exerciser_ops(Ops, Param, Bdf)**<br/>
+Ops - START_DMA<br/>
+Param - EDMA_TO_DEVICE or EDMA_FROM_DEVICE<br/>
+Bdf - BDF of the exerciser<br/>
+<br/>
+
+### ATS Request
+- Before starting an ATS request, untranslated input address for ATSRequest must be written onto Bus Address Register<br/>
+**pal_exerciser_set_param(Type, Value1, Value2, Bdf)**<br/>
+Type - DMA_ATTRIBUTES<br/>
+Value1 -  Untranslated input address<br/>
+Value2 - Size<br/>
+BDF - BDF of the exerciser<br/>
+- Send an ATS Translation Request for the VA<br/>
+**pal_exerciser_ops(Ops, Param, Bdf)**<br/>
+Ops - ATS_TXN_REQ<br/>
+Param - VA<br/>
+Bdf - BDF of the exerciser<br/>
+- Get ATS Translation Response<br/>
+**pal_exerciser_get_param(Type, Value1, Value2, Bdf)**<br/>
+Type - ATS_RES_ATTRIBUTES<br/>
+Value1 - Buffer to store translated address<br/>
+Value2 - Null<br/>
+Bdf -  BDF of the exerciser<br/>
+<br/>
+
+### Generating DMA with Address Translated(AT)
+- Configure Exerciser to issue subsequent DMA transactions with AT(Address Translated) bit Set<br/>
+**pal_exerciser_set_param(Type, Value1, Value2, Bdf)**<br/>
+Type - CFG_TXN_ATTRIBUTES<br/>
+Value1 - TXN_ADDR_TYPE<br/>
+Value2 - AT_TRANSLATED<br/>
+BDF - BDF of the exerciser<br/>
+**pal_exerciser_set_param(Type, Value1, Value2, Bdf)**<br/>
+Type - DMA_ATTRIBUTES<br/>
+Value1 - Buffer containing the data or the Buffer where the data to be copied<br/>
+Value2 - Size of the data<br/>
+BDF - BDF of the exerciser<br/>
+- Trigger the DMA to/from the buffer<br/>
+**pal_exerciser_ops(Ops, Param, Bdf)**<br/>
+Ops - START_DMA<br/>
+Param - EDMA_TO_DEVICE or EDMA_FROM_DEVICE<br/>
+Bdf - BDF of the exerciser<br/>
+<br/>
+
+### Trigerring MSI
+- Trigger the interrupt for this Exerciser instance<br/>
+**pal_exerciser_ops(Ops, Param, Bdf)**<br/>
+Ops - GENERATE_MSI<br/>
+Param - MSI index<br/>
+Bdf - BDF of the exerciser<br/>
+<br/>
+
+### Trigerring Legacy Interrupts
+-  Clear any pending interrupts<br/>
+**pal_exerciser_ops(Ops, Param, Bdf)**<br/>
+Ops - CLEAR_INTR<br/>
+Param - Legacy interrupt IRQ<br/>
+Bdf - BDF of the exerciser<br/>
+- Trigger the interrupt for this Exerciser instance<br/>
+**pal_exerciser_ops(Ops, Param, Bdf)**<br/>
+Ops - GENERATE_L_INTR<br/>
+Param - Legacy interrupt IRQ<br/>
+Bdf - BDF of the exerciser<br/>
+<br/>
+
+### Transaction Monitoring
+- Transaction monitoring capabilities in the exerciser provides the ability to record the incoming transactions, for both config and memory transactions. This includes,<br/>
+	-   config read and write transactions serviced in PCIe endpoints.<br/>
+	-   memory transactions serviced in PCIe endpoint BARs.<br/>
+	-   memory transactions which are forwarded from PCIe endpoint to device(like exerciser).<br/>
+- To start transaction monitoring<br/>
+**pal_exerciser_ops(Ops, Param, Bdf)**<br/>
+Ops - START_TXN_MONITOR<br/>
+Param - CFG_READ<br/>
+Bdf - BDF of the exerciser<br/>
+- After the transactions are performed, stop the transaction monitoring<br/>
+**pal_exerciser_ops(Ops, Param, Bdf)**<br/>
+Ops - STOP_TXN_MONITOR<br/>
+Param - CFG_READ<br/>
+Bdf - BDF of the exerciser<br/>
+- Read the transaction trace<br/>
+**pal_exerciser_get_param(Type, Value1, Value2, Bdf)**<br/>
+Type -<br/>
+	- CFG_TXN_ATTRIBUTES: Indicates transaction attributes. cfg or mem transaction<br/>
+	- TRANSACTION_TYPE: Indicates transaction type. Read or Write transaction<br/>
+	- ADDRESS_ATTRIBUTES: Config or memory address<br/>
+	- DATA_ATTRIBUTES: Transaction data read or written to<br/>
+Value1 - Requested transaction data<br/>
+Value2 - Null<br/>
+Bdf -  BDF of the exerciser<br/>
+<br/>
+<br/>
+
+## License
+Arm SBSA ACS is distributed under Apache v2.0 License.
+
+--------------
+
+*Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.*
+
diff --git a/linux_app/sbsa-acs-app/include/sbsa_app.h b/linux_app/sbsa-acs-app/include/sbsa_app.h
index f70a5549..390a1301 100644
--- a/linux_app/sbsa-acs-app/include/sbsa_app.h
+++ b/linux_app/sbsa-acs-app/include/sbsa_app.h
@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2016-2020, 2022 Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -21,7 +21,7 @@
 
 
 #define SBSA_APP_VERSION_MAJOR  3
-#define SBSA_APP_VERSION_MINOR  1
+#define SBSA_APP_VERSION_MINOR  2
 
 #include "sbsa_drv_intf.h"
 
diff --git a/platform/pal_baremetal.mk b/platform/pal_baremetal.mk
index 42c00929..fa4f98b7 100644
--- a/platform/pal_baremetal.mk
+++ b/platform/pal_baremetal.mk
@@ -35,7 +35,8 @@ CC = $(GCC49_AARCH64_PREFIX)gcc -march=armv8.2-a -DTARGET_EMULATION
 AR = $(GCC49_AARCH64_PREFIX)ar
 CC_FLAGS = -g -Os -fshort-wchar -fno-builtin -fno-strict-aliasing -Wall -Werror -Wextra -Wmissing-declarations -Wstrict-prototypes -Wconversion -Wsign-conversion -Wstrict-overflow
 
-DEPS = $(SBSA_ROOT)/val/include/pal_interface.h
+DEPS = $(SBSA_ROOT)/platform/pal_baremetal/FVP/include/platform_override_fvp.h
+DEPS += $(SBSA_ROOT)/val/include/pal_interface.h
 
 FILES   += $(foreach files,$(SBSA_DIR)/,$(wildcard $(files)/*.S))
 FILES   += $(foreach files,$(SBSA_DIR)/,$(wildcard $(files)/*.c))
diff --git a/platform/pal_baremetal/FVP/include/platform_override_fvp.h b/platform/pal_baremetal/FVP/include/platform_override_fvp.h
index 66f70b31..a8d7223a 100644
--- a/platform/pal_baremetal/FVP/include/platform_override_fvp.h
+++ b/platform/pal_baremetal/FVP/include/platform_override_fvp.h
@@ -21,7 +21,7 @@
 /** Begin config **/
 
 /* Settings */
-#define PLATFORM_OVERRIDE_SBSA_LEVEL   0x3     //The permissible levels are 3,4,5 and 6
+#define PLATFORM_OVERRIDE_SBSA_LEVEL   0x4     //The permissible levels are 3,4,5 and 6
 #define PLATFORM_OVERRIDE_PRINT_LEVEL  0x3     //The permissible levels are 1,2,3,4 and 5
 
 /* PCIe BAR config parameters*/
@@ -137,6 +137,11 @@
                                                  (PLATFORM_OVERRIDE_TIMER_PHY_FLAGS_1))
 #define PLATFORM_OVERRIDE_TIMER_CNTFRQ         0x0
 
+/* Define the Timeout values to be used */
+#define PLATFORM_OVERRIDE_TIMEOUT_LARGE         0x100000
+#define PLATFORM_OVERRIDE_TIMEOUT_MEDIUM        0x10000
+#define PLATFORM_OVERRIDE_TIMEOUT_SMALL         0x100
+
 /* Watchdog platform config parameters */
 #define WD_MODE     INTERRUPT_IS_LEVEL_TRIGGERED
 #define WD_POLARITY INTERRUPT_IS_ACTIVE_HIGH
@@ -167,6 +172,10 @@
 #define PLATFORM_OVERRIDE_PCIE_START_BUS_NUM_0    0x0
 #define PLATFORM_OVERRIDE_PCIE_END_BUS_NUM_0      0xFF
 
+#define PLATFORM_OVERRIDE_PCIE_MAX_BUS      256
+#define PLATFORM_OVERRIDE_PCIE_MAX_DEV      32
+#define PLATFORM_OVERRIDE_PCIE_MAX_FUNC     8
+
 /* Sample macros for ECAM_1
  * #define PLATFORM_OVERRIDE_PCIE_ECAM_BASE_ADDR_1  0x00000000
  * #define PLATFORM_OVERRIDE_PCIE_SEGMENT_GRP_NUM_1 0x0
@@ -190,7 +199,7 @@
 #define PLATFORM_PCIE_DEV0_DMA_COHERENT  0
 #define PLATFORM_PCIE_DEV0_P2P_SUPPORT   1
 #define PLATFORM_PCIE_DEV0_DMA_64BIT     0
-#define PLATFORM_PCIE_DEV0_BEHIND_SMMU   0
+#define PLATFORM_PCIE_DEV0_BEHIND_SMMU   1
 #define PLATFORM_PCIE_DEV0_ATC_SUPPORT   0
 
 #define PLATFORM_PCIE_DEV1_CLASSCODE     0x6040000
@@ -204,7 +213,7 @@
 #define PLATFORM_PCIE_DEV1_DMA_COHERENT  0
 #define PLATFORM_PCIE_DEV1_P2P_SUPPORT   1
 #define PLATFORM_PCIE_DEV1_DMA_64BIT     0
-#define PLATFORM_PCIE_DEV1_BEHIND_SMMU   0
+#define PLATFORM_PCIE_DEV1_BEHIND_SMMU   1
 #define PLATFORM_PCIE_DEV1_ATC_SUPPORT   0
 
 #define PLATFORM_PCIE_DEV2_CLASSCODE     0x6040000
@@ -218,7 +227,7 @@
 #define PLATFORM_PCIE_DEV2_DMA_COHERENT  0
 #define PLATFORM_PCIE_DEV2_P2P_SUPPORT   1
 #define PLATFORM_PCIE_DEV2_DMA_64BIT     0
-#define PLATFORM_PCIE_DEV2_BEHIND_SMMU   0
+#define PLATFORM_PCIE_DEV2_BEHIND_SMMU   1
 #define PLATFORM_PCIE_DEV2_ATC_SUPPORT   0
 
 #define PLATFORM_PCIE_DEV3_CLASSCODE     0xED000001
@@ -232,7 +241,7 @@
 #define PLATFORM_PCIE_DEV3_DMA_COHERENT  0
 #define PLATFORM_PCIE_DEV3_P2P_SUPPORT   1
 #define PLATFORM_PCIE_DEV3_DMA_64BIT     0
-#define PLATFORM_PCIE_DEV3_BEHIND_SMMU   0
+#define PLATFORM_PCIE_DEV3_BEHIND_SMMU   1
 #define PLATFORM_PCIE_DEV3_ATC_SUPPORT   0
 
 #define PLATFORM_PCIE_DEV4_CLASSCODE     0xED000001
@@ -246,7 +255,7 @@
 #define PLATFORM_PCIE_DEV4_DMA_COHERENT  0
 #define PLATFORM_PCIE_DEV4_P2P_SUPPORT   1
 #define PLATFORM_PCIE_DEV4_DMA_64BIT     0
-#define PLATFORM_PCIE_DEV4_BEHIND_SMMU   0
+#define PLATFORM_PCIE_DEV4_BEHIND_SMMU   1
 #define PLATFORM_PCIE_DEV4_ATC_SUPPORT   0
 
 #define PLATFORM_PCIE_DEV5_CLASSCODE     0x1060101
@@ -260,7 +269,7 @@
 #define PLATFORM_PCIE_DEV5_DMA_COHERENT  0
 #define PLATFORM_PCIE_DEV5_P2P_SUPPORT   1
 #define PLATFORM_PCIE_DEV5_DMA_64BIT     0
-#define PLATFORM_PCIE_DEV5_BEHIND_SMMU   0
+#define PLATFORM_PCIE_DEV5_BEHIND_SMMU   1
 #define PLATFORM_PCIE_DEV5_ATC_SUPPORT   0
 
 #define PLATFORM_PCIE_DEV6_CLASSCODE     0x1060101
@@ -274,7 +283,7 @@
 #define PLATFORM_PCIE_DEV6_DMA_COHERENT  0
 #define PLATFORM_PCIE_DEV6_P2P_SUPPORT   1
 #define PLATFORM_PCIE_DEV6_DMA_64BIT     0
-#define PLATFORM_PCIE_DEV6_BEHIND_SMMU   0
+#define PLATFORM_PCIE_DEV6_BEHIND_SMMU   1
 #define PLATFORM_PCIE_DEV6_ATC_SUPPORT   0
 
 #define PLATFORM_PCIE_DEV7_CLASSCODE     0xED000000
@@ -288,7 +297,7 @@
 #define PLATFORM_PCIE_DEV7_DMA_COHERENT  0
 #define PLATFORM_PCIE_DEV7_P2P_SUPPORT   1
 #define PLATFORM_PCIE_DEV7_DMA_64BIT     0
-#define PLATFORM_PCIE_DEV7_BEHIND_SMMU   0
+#define PLATFORM_PCIE_DEV7_BEHIND_SMMU   1
 #define PLATFORM_PCIE_DEV7_ATC_SUPPORT   0
 
 #define PLATFORM_PCIE_DEV8_CLASSCODE     0xED000000
@@ -302,7 +311,7 @@
 #define PLATFORM_PCIE_DEV8_DMA_COHERENT  0
 #define PLATFORM_PCIE_DEV8_P2P_SUPPORT   1
 #define PLATFORM_PCIE_DEV8_DMA_64BIT     0
-#define PLATFORM_PCIE_DEV8_BEHIND_SMMU   0
+#define PLATFORM_PCIE_DEV8_BEHIND_SMMU   1
 #define PLATFORM_PCIE_DEV8_ATC_SUPPORT   0
 
 #define PLATFORM_PCIE_DEV9_CLASSCODE    0x6040000
@@ -316,7 +325,7 @@
 #define PLATFORM_PCIE_DEV9_DMA_COHERENT 0
 #define PLATFORM_PCIE_DEV9_P2P_SUPPORT  1
 #define PLATFORM_PCIE_DEV9_DMA_64BIT    0
-#define PLATFORM_PCIE_DEV9_BEHIND_SMMU  0
+#define PLATFORM_PCIE_DEV9_BEHIND_SMMU  1
 #define PLATFORM_PCIE_DEV9_ATC_SUPPORT  0
 
 #define PLATFORM_PCIE_DEV10_CLASSCODE    0x6040000
@@ -330,7 +339,7 @@
 #define PLATFORM_PCIE_DEV10_DMA_COHERENT 0
 #define PLATFORM_PCIE_DEV10_P2P_SUPPORT  1
 #define PLATFORM_PCIE_DEV10_DMA_64BIT    0
-#define PLATFORM_PCIE_DEV10_BEHIND_SMMU  0
+#define PLATFORM_PCIE_DEV10_BEHIND_SMMU  1
 #define PLATFORM_PCIE_DEV10_ATC_SUPPORT  0
 
 #define PLATFORM_PCIE_DEV11_CLASSCODE    0x6040000
@@ -344,7 +353,7 @@
 #define PLATFORM_PCIE_DEV11_DMA_COHERENT 0
 #define PLATFORM_PCIE_DEV11_P2P_SUPPORT  1
 #define PLATFORM_PCIE_DEV11_DMA_64BIT    0
-#define PLATFORM_PCIE_DEV11_BEHIND_SMMU  0
+#define PLATFORM_PCIE_DEV11_BEHIND_SMMU  1
 #define PLATFORM_PCIE_DEV11_ATC_SUPPORT  0
 
 #define PLATFORM_PCIE_DEV12_CLASSCODE    0x6040000
@@ -358,7 +367,7 @@
 #define PLATFORM_PCIE_DEV12_DMA_COHERENT 0
 #define PLATFORM_PCIE_DEV12_P2P_SUPPORT  1
 #define PLATFORM_PCIE_DEV12_DMA_64BIT    0
-#define PLATFORM_PCIE_DEV12_BEHIND_SMMU  0
+#define PLATFORM_PCIE_DEV12_BEHIND_SMMU  1
 #define PLATFORM_PCIE_DEV12_ATC_SUPPORT  0
 
 #define PLATFORM_PCIE_DEV13_CLASSCODE    0x1060101
@@ -372,7 +381,7 @@
 #define PLATFORM_PCIE_DEV13_DMA_COHERENT 0
 #define PLATFORM_PCIE_DEV13_P2P_SUPPORT  1
 #define PLATFORM_PCIE_DEV13_DMA_64BIT    0
-#define PLATFORM_PCIE_DEV13_BEHIND_SMMU  0
+#define PLATFORM_PCIE_DEV13_BEHIND_SMMU  1
 #define PLATFORM_PCIE_DEV13_ATC_SUPPORT  0
 
 #define PLATFORM_PCIE_DEV14_CLASSCODE    0xED000000
@@ -386,7 +395,7 @@
 #define PLATFORM_PCIE_DEV14_DMA_COHERENT 0
 #define PLATFORM_PCIE_DEV14_P2P_SUPPORT  1
 #define PLATFORM_PCIE_DEV14_DMA_64BIT    0
-#define PLATFORM_PCIE_DEV14_BEHIND_SMMU  0
+#define PLATFORM_PCIE_DEV14_BEHIND_SMMU  1
 #define PLATFORM_PCIE_DEV14_ATC_SUPPORT  0
 
 #define PLATFORM_PCIE_DEV15_CLASSCODE    0xED000000
@@ -400,7 +409,7 @@
 #define PLATFORM_PCIE_DEV15_DMA_COHERENT 0
 #define PLATFORM_PCIE_DEV15_P2P_SUPPORT  1
 #define PLATFORM_PCIE_DEV15_DMA_64BIT    0
-#define PLATFORM_PCIE_DEV15_BEHIND_SMMU  0
+#define PLATFORM_PCIE_DEV15_BEHIND_SMMU  1
 #define PLATFORM_PCIE_DEV15_ATC_SUPPORT  0
 
 #define PLATFORM_PCIE_DEV16_CLASSCODE    0xFF000000
@@ -414,7 +423,7 @@
 #define PLATFORM_PCIE_DEV16_DMA_COHERENT 0
 #define PLATFORM_PCIE_DEV16_P2P_SUPPORT  1
 #define PLATFORM_PCIE_DEV16_DMA_64BIT    0
-#define PLATFORM_PCIE_DEV16_BEHIND_SMMU  0
+#define PLATFORM_PCIE_DEV16_BEHIND_SMMU  1
 #define PLATFORM_PCIE_DEV16_ATC_SUPPORT  0
 
 #define PLATFORM_PCIE_DEV17_CLASSCODE    0xFF000000
@@ -428,7 +437,7 @@
 #define PLATFORM_PCIE_DEV17_DMA_COHERENT 0
 #define PLATFORM_PCIE_DEV17_P2P_SUPPORT  1
 #define PLATFORM_PCIE_DEV17_DMA_64BIT    0
-#define PLATFORM_PCIE_DEV17_BEHIND_SMMU  0
+#define PLATFORM_PCIE_DEV17_BEHIND_SMMU  1
 #define PLATFORM_PCIE_DEV17_ATC_SUPPORT  0
 
 #define PLATFORM_PCIE_DEV18_CLASSCODE    0xFF000000
@@ -442,7 +451,7 @@
 #define PLATFORM_PCIE_DEV18_DMA_COHERENT 0
 #define PLATFORM_PCIE_DEV18_P2P_SUPPORT  1
 #define PLATFORM_PCIE_DEV18_DMA_64BIT    0
-#define PLATFORM_PCIE_DEV18_BEHIND_SMMU  0
+#define PLATFORM_PCIE_DEV18_BEHIND_SMMU  1
 #define PLATFORM_PCIE_DEV18_ATC_SUPPORT  0
 
 #define PLATFORM_PCIE_DEV19_CLASSCODE    0xFF000000
@@ -456,7 +465,7 @@
 #define PLATFORM_PCIE_DEV19_DMA_COHERENT 0
 #define PLATFORM_PCIE_DEV19_P2P_SUPPORT  1
 #define PLATFORM_PCIE_DEV19_DMA_64BIT    0
-#define PLATFORM_PCIE_DEV19_BEHIND_SMMU  0
+#define PLATFORM_PCIE_DEV19_BEHIND_SMMU  1
 #define PLATFORM_PCIE_DEV19_ATC_SUPPORT  0
 
 #define PLATFORM_PCIE_DEV20_CLASSCODE    0x6040000
@@ -470,10 +479,12 @@
 #define PLATFORM_PCIE_DEV20_DMA_COHERENT 0
 #define PLATFORM_PCIE_DEV20_P2P_SUPPORT  1
 #define PLATFORM_PCIE_DEV20_DMA_64BIT    0
-#define PLATFORM_PCIE_DEV20_BEHIND_SMMU  0
+#define PLATFORM_PCIE_DEV20_BEHIND_SMMU  1
 #define PLATFORM_PCIE_DEV20_ATC_SUPPORT  0
 
 /* PERIPHERAL platform config parameters */
+#define PLATFORM_OVERRIDE_PERIPHERAL_COUNT 3  //UART + USB + SATA
+
 #define UART_ADDRESS                     0xF9750000
 #define BASE_ADDRESS_ADDRESS_SPACE_ID    0x0
 #define BASE_ADDRESS_REGISTER_BIT_WIDTH  0x20
@@ -495,6 +506,11 @@
 #define IOVIRT_ADDRESS               0xF9780000
 #define IORT_NODE_COUNT              3
 #define IOVIRT_ITS_COUNT             1
+#define IOVIRT_SMMUV3_COUNT          1
+#define IOVIRT_RC_COUNT              1
+#define IOVIRT_SMMUV2_COUNT          0
+#define IOVIRT_NAMED_COMPONENT_COUNT 0
+#define IOVIRT_PMCG_COUNT            0
 #define IOVIRT_SMMUV3_BASE_ADDRESS   0x4F000000
 #define IOVIRT_SMMU_CTX_INT_OFFSET   0x0
 #define IOVIRT_SMMU_CTX_INT_CNT      0x0
@@ -575,6 +591,7 @@
 #define PCIE_CAP_DIS_MASK   0xFFFEFFFF
 #define PCIE_CAP_EN_MASK    (1 << 16)
 #define PASID_EN_MASK       (1 << 6)
+
 /* PCIe Config space Offset */
 #define BAR0_OFFSET        0x10
 #define COMMAND_REG_OFFSET 0x04
diff --git a/platform/pal_baremetal/docs/Arm_SBSA_ACS_Bare-metal_User_Guide.pdf b/platform/pal_baremetal/docs/Arm_SBSA_ACS_Bare-metal_User_Guide.pdf
index a9d94cac..40318ec0 100644
Binary files a/platform/pal_baremetal/docs/Arm_SBSA_ACS_Bare-metal_User_Guide.pdf and b/platform/pal_baremetal/docs/Arm_SBSA_ACS_Bare-metal_User_Guide.pdf differ
diff --git a/platform/pal_baremetal/src/pal_misc.c b/platform/pal_baremetal/src/pal_misc.c
index ae910ff4..45cabdc7 100644
--- a/platform/pal_baremetal/src/pal_misc.c
+++ b/platform/pal_baremetal/src/pal_misc.c
@@ -334,7 +334,6 @@ pal_mem_alloc(uint32_t Size)
   return malloc(Size);
 }
 
-
 /**
   @brief  Allocates requested buffer size in bytes with zeros in a contiguous memory
           and returns the base address of the range.
diff --git a/platform/pal_baremetal/src/pal_pcie_enumeration.c b/platform/pal_baremetal/src/pal_pcie_enumeration.c
index a38db4d2..bcff2148 100644
--- a/platform/pal_baremetal/src/pal_pcie_enumeration.c
+++ b/platform/pal_baremetal/src/pal_pcie_enumeration.c
@@ -470,6 +470,12 @@ pal_clear_pri_bus()
 
 void pal_pcie_enumerate(void)
 {
+    if (g_pcie_info_table->num_entries == 0)
+    {
+         print(AVS_PRINT_TEST, "\nSkipping Enumeration", 0);
+         return;
+    }
+
     print(AVS_PRINT_TEST, "\nStarting Enumeration \n", 0);
     pal_pcie_enumerate_device(PRI_BUS, SEC_BUS);
     pal_clear_pri_bus();
diff --git a/platform/pal_baremetal/src/pal_peripherals.c b/platform/pal_baremetal/src/pal_peripherals.c
index e9579b19..761a4a98 100644
--- a/platform/pal_baremetal/src/pal_peripherals.c
+++ b/platform/pal_baremetal/src/pal_peripherals.c
@@ -100,7 +100,7 @@ pal_peripheral_create_info_table(PERIPHERAL_INFO_TABLE *peripheralInfoTable)
              if ((reg_value & PCIE_ECAP_CIDR_MASK) == ECID_PASID)
              {
                   pal_pcie_read_cfg(curr_seg, curr_bus, curr_dev, curr_func, pasid_cap_offset + PASID_OFFSET, &max_pasid);
-                  per_info->max_pasids = (max_pasid >> PASID_NUM_SHIFT) && PASID_NUM_MASK;
+                  per_info->max_pasids = (max_pasid >> PASID_NUM_SHIFT) & PASID_NUM_MASK;
                   break;
              }
              pasid_cap_offset = ((reg_value >> PCIE_ECAP_NCPR_SHIFT) & PCIE_ECAP_NCPR_MASK);
@@ -155,7 +155,7 @@ pal_peripheral_create_info_table(PERIPHERAL_INFO_TABLE *peripheralInfoTable)
              if ((reg_value & PCIE_ECAP_CIDR_MASK) == ECID_PASID)
              {
                   pal_pcie_read_cfg(curr_seg, curr_bus, curr_dev, curr_func, pasid_cap_offset + PASID_OFFSET, &max_pasid);
-                  per_info->max_pasids = (max_pasid >> PASID_NUM_SHIFT) && PASID_NUM_MASK;
+                  per_info->max_pasids = (max_pasid >> PASID_NUM_SHIFT) & PASID_NUM_MASK;
                   break;
              }
              pasid_cap_offset = ((reg_value >> PCIE_ECAP_NCPR_SHIFT) & PCIE_ECAP_NCPR_MASK);
diff --git a/platform/pal_baremetal/src/pal_smmu.c b/platform/pal_baremetal/src/pal_smmu.c
index 5fe1a2ee..703291f3 100644
--- a/platform/pal_baremetal/src/pal_smmu.c
+++ b/platform/pal_baremetal/src/pal_smmu.c
@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -63,10 +63,8 @@ pal_smmu_max_pasids(uint64_t smmu_base)
 {
   uint32_t reg = pal_mmio_read(smmu_base + SMMU_V3_IDR1);
   uint32_t pasid_bits = (reg >> SMMU_V3_IDR1_PASID_SHIFT) & SMMU_V3_IDR1_PASID_MASK;
-  if(pasid_bits == 0)
-     return 0;
 
-  return (1 << pasid_bits);
+  return pasid_bits;
 }
 
 /**
diff --git a/platform/pal_uefi/include/platform_override.h b/platform/pal_uefi/include/platform_override.h
index 96c5a2db..ec00b2c9 100644
--- a/platform/pal_uefi/include/platform_override.h
+++ b/platform/pal_uefi/include/platform_override.h
@@ -35,6 +35,11 @@
 #define PLATFORM_OVERRIDE_CNTBASE_N      0x2a830000
 #define PLATFORM_OVERRIDE_PLATFORM_TIMER_GSIV 58
 
+/* Change OVERRIDE to 1 and define the Timeout values to be used */
+#define PLATFORM_OVERRIDE_TIMEOUT        0
+#define PLATFORM_OVERRIDE_TIMEOUT_LARGE  0x10000
+#define PLATFORM_OVERRIDE_TIMEOUT_MEDIUM 0x1000
+#define PLATFORM_OVERRIDE_TIMEOUT_SMALL  0x10
 
 #define PLATFORM_OVERRIDE_EL2_VIR_TIMER_GSIV  28
 
@@ -51,6 +56,11 @@
 #define PLATFORM_OVERRIDE_PCIE_ECAM_BASE       0x0 //0x40000000
 #define PLATFORM_OVERRIDE_PCIE_START_BUS_NUM   0x0
 
+#define PLATFORM_OVERRIDE_MAX_BDF           0
+#define PLATFORM_OVERRIDE_PCIE_MAX_BUS      256
+#define PLATFORM_OVERRIDE_PCIE_MAX_DEV      32
+#define PLATFORM_OVERRIDE_PCIE_MAX_FUNC     8
+
 /* Change OVERRIDE_SMMU_BASE to non-zero value for this to take effect */
 #define PLATFORM_OVERRIDE_SMMU_BASE        0x0 //0x2B400000
 #define PLATFORM_OVERRIDE_SMMU_ARCH_MAJOR  3
diff --git a/test_pool/io_virt/test_i007.c b/test_pool/io_virt/test_i007.c
index d786fe2d..ea54b109 100755
--- a/test_pool/io_virt/test_i007.c
+++ b/test_pool/io_virt/test_i007.c
@@ -42,7 +42,8 @@ payload(void)
   while (num_smmu--) {
       if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) {
           if (g_sbsa_level > 3) {
-              val_print(AVS_PRINT_ERR, "\n       SMMUv3 should be supported Level %x", g_sbsa_level);
+              val_print(AVS_PRINT_ERR, "\n       SMMUv3 should be supported Level %x",
+                                                                                  g_sbsa_level);
               val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01));
               return;
           }
diff --git a/test_pool/pcie/test_p010.c b/test_pool/pcie/test_p010.c
index c8948d3d..709a925c 100644
--- a/test_pool/pcie/test_p010.c
+++ b/test_pool/pcie/test_p010.c
@@ -24,7 +24,7 @@
 #define TEST_NUM   (AVS_PCIE_TEST_NUM_BASE + 10)
 #define TEST_DESC  "PASID support atleast 16 bits     "
 
-#define MIN_PASID_SUPPORT (1 << 16)
+#define MIN_PASID_SUPPORT 16
 
 static void
 payload(void)
diff --git a/test_pool/pcie/test_p012.c b/test_pool/pcie/test_p012.c
index 5f7e52cc..1fe5496a 100644
--- a/test_pool/pcie/test_p012.c
+++ b/test_pool/pcie/test_p012.c
@@ -104,29 +104,33 @@ payload (void)
             val_print (AVS_PRINT_ERR, "\n       Unknown error", 0);
         break;
       }
-    }
 
-    /* Compare IRQ routings */
-    if (!status) {
-      while (current_irq_pin < LEGACY_PCI_IRQ_CNT && status == 0) {
-        while (next_irq_pin < LEGACY_PCI_IRQ_CNT && status == 0) {
-
-          for (ccnt = 0; (ccnt < irq_map->legacy_irq_map[current_irq_pin].irq_count) && (status == 0); ccnt++) {
-            for (ncnt = 0; (ncnt < irq_map->legacy_irq_map[next_irq_pin].irq_count) && (status == 0); ncnt++) {
-              test_skip = 0;
-              if (irq_map->legacy_irq_map[current_irq_pin].irq_list[ccnt] ==
-                  irq_map->legacy_irq_map[next_irq_pin].irq_list[ncnt]) {
-                status = 7;
-                val_print (AVS_PRINT_ERR, "\n       Legacy interrupt %c routing", pin_name(current_irq_pin));
-                val_print (AVS_PRINT_ERR, "\n       is the same as %c routing", pin_name(next_irq_pin));
+      /* Compare IRQ routings */
+      if (!status) {
+        while (current_irq_pin < LEGACY_PCI_IRQ_CNT && status == 0) {
+          while (next_irq_pin < LEGACY_PCI_IRQ_CNT && status == 0) {
+
+            for (ccnt = 0; (ccnt < irq_map->legacy_irq_map[current_irq_pin].irq_count)
+                 && (status == 0); ccnt++) {
+              for (ncnt = 0; (ncnt < irq_map->legacy_irq_map[next_irq_pin].irq_count)
+                 && (status == 0); ncnt++) {
+                test_skip = 0;
+                if (irq_map->legacy_irq_map[current_irq_pin].irq_list[ccnt] ==
+                    irq_map->legacy_irq_map[next_irq_pin].irq_list[ncnt]) {
+                  status = 7;
+                  val_print (AVS_PRINT_ERR, "\n       Legacy interrupt %c routing",
+                                             pin_name(current_irq_pin));
+                  val_print (AVS_PRINT_ERR, "\n       is the same as %c routing",
+                                             pin_name(next_irq_pin));
+                }
               }
             }
-          }
 
-          next_irq_pin++;
+            next_irq_pin++;
+          }
+          current_irq_pin++;
+          next_irq_pin = current_irq_pin + 1;
         }
-        current_irq_pin++;
-        next_irq_pin = current_irq_pin + 1;
       }
     }
   }
diff --git a/test_pool/pcie/test_p013.c b/test_pool/pcie/test_p013.c
index a1c66f7e..7f5ddb8e 100644
--- a/test_pool/pcie/test_p013.c
+++ b/test_pool/pcie/test_p013.c
@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2016-2018, 2022 Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -70,8 +70,9 @@ payload (void)
       data = val_pcie_is_devicedma_64bit(dev_bdf);
       if (data == 0) {
           if(!val_pcie_is_device_behind_smmu(dev_bdf)) {
-              val_print (AVS_PRINT_ERR, "\n       WARNING:The device with bdf=0x%x doesn't support 64 bit addressing", dev_bdf);
-              val_print (AVS_PRINT_ERR, "\n       and is not behind SMMU. The device is of type = %d", dev_type);
+              val_print (AVS_PRINT_ERR, "\n       Device with bdf=0x%x doesn't support", dev_bdf);
+              val_print (AVS_PRINT_ERR, "       64 bit addressing and is not behind SMMU", 0);
+              val_print (AVS_PRINT_ERR, "       The device type is = %d", dev_type);
               val_set_status (index, RESULT_FAIL (g_sbsa_level, TEST_NUM, 1));
               return;
           }
diff --git a/test_pool/pcie/test_p016.c b/test_pool/pcie/test_p016.c
index f4d3b02e..9b3e3bde 100644
--- a/test_pool/pcie/test_p016.c
+++ b/test_pool/pcie/test_p016.c
@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2016-2018,2021 Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2016-2018,2021-2022 Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -80,6 +80,11 @@ static void payload(void)
                 }
             }
         }
+
+        else {
+            /* bar_data is zero, so considered as 32 bit BAR */
+            status = 1;
+        }
     }
 
     if (!status)
diff --git a/test_pool/pcie/test_p048.c b/test_pool/pcie/test_p048.c
index 5c138246..3f812e64 100644
--- a/test_pool/pcie/test_p048.c
+++ b/test_pool/pcie/test_p048.c
@@ -166,7 +166,7 @@ payload(void)
            {
                val_print(AVS_PRINT_ERR, "\n Memory range for bdf 0x%x", bdf);
                val_print(AVS_PRINT_ERR, " is 0x%x", read_value);
-               val_print(AVS_PRINT_ERR, "\n Out of range addr 0x%x", (new_mem_lim + MEM_OFFSET_SMALL));
+               val_print(AVS_PRINT_ERR, "\n Out of range 0x%x", (new_mem_lim + MEM_OFFSET_SMALL));
                val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03));
            }
         }
@@ -175,7 +175,8 @@ payload(void)
         /*Write back original value */
         if ((mem_lim >> MEM_SHIFT) > (ori_mem_base >> MEM_SHIFT))
         {
-            val_pcie_write_cfg(bdf, TYPE1_NP_MEM, ((mem_lim & MEM_LIM_MASK) | (ori_mem_base  >> 16)));
+            val_pcie_write_cfg(bdf, TYPE1_NP_MEM,
+                                           ((mem_lim & MEM_LIM_MASK) | (ori_mem_base  >> 16)));
         }
 
         /* Memory Space might have constraint on RW/RO behaviour
diff --git a/test_pool/pcie/test_p049.c b/test_pool/pcie/test_p049.c
index 43fe5250..fa07515f 100644
--- a/test_pool/pcie/test_p049.c
+++ b/test_pool/pcie/test_p049.c
@@ -195,7 +195,7 @@ payload(void)
                val_print(AVS_PRINT_ERR, "\n Memory range for bdf 0x%x", bdf);
                val_print(AVS_PRINT_ERR, " is 0x%llx", updated_mem_base);
                val_print(AVS_PRINT_ERR, " 0x%llx", updated_mem_lim);
-               val_print(AVS_PRINT_ERR, "\n Out of range addr 0x%llx ", (new_mem_lim + MEM_OFFSET_SMALL));
+               val_print(AVS_PRINT_ERR, "\n Out of range 0x%llx", (new_mem_lim + MEM_OFFSET_SMALL));
                val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03));
            }
         }
@@ -213,7 +213,7 @@ payload(void)
          * So not checking for Read-Write Data mismatch.
         */
         if (IS_TEST_FAIL(val_get_status(pe_index))) {
-          val_print(AVS_PRINT_ERR, "\n       Failed exception on Memory Access For Bdf : 0x%x", bdf);
+          val_print(AVS_PRINT_ERR, "\n     Failed exception on Memory Access For Bdf : 0x%x", bdf);
           val_pcie_clear_urd(bdf);
           return;
         }
diff --git a/test_pool/peripherals/test_d003.c b/test_pool/peripherals/test_d003.c
index d0788507..9f36e1ff 100755
--- a/test_pool/peripherals/test_d003.c
+++ b/test_pool/peripherals/test_d003.c
@@ -214,7 +214,7 @@ payload1(void)
           val_print_raw(l_uart_base, g_print_level,
                         "\n       Test Message                      ", 0);
 
-          while ((--timeout > 0) && (IS_RESULT_PENDING(val_get_status(index)))){
+          while ((--timeout > 0) && (IS_RESULT_PENDING(val_get_status(index)))) {
           };
 
           if (timeout == 0) {
diff --git a/test_pool/power_wakeup/test_u001.c b/test_pool/power_wakeup/test_u001.c
index 63ab430e..c50ebaa9 100755
--- a/test_pool/power_wakeup/test_u001.c
+++ b/test_pool/power_wakeup/test_u001.c
@@ -228,7 +228,7 @@ payload4(void)
              Test will be consider as failure in case WD interrupt
              failed to fire.
           */
-          if (! (g_wd_int_received || g_failsafe_int_received)) {
+          if (!(g_wd_int_received || g_failsafe_int_received)) {
             val_gic_clear_interrupt(intid);
             val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM4, 1));
           }
diff --git a/test_pool/test_pool.mk b/test_pool/test_pool.mk
index fb5d485d..c24882db 100644
--- a/test_pool/test_pool.mk
+++ b/test_pool/test_pool.mk
@@ -33,6 +33,8 @@ CC = $(GCC49_AARCH64_PREFIX)gcc -march=armv8.2-a -DTARGET_EMULATION
 AR = $(GCC49_AARCH64_PREFIX)ar
 CC_FLAGS = -g -O0 -fshort-wchar -fno-builtin -fno-strict-aliasing -Wall -Werror -Wextra -Wmissing-declarations -Wstrict-prototypes -Wno-error=conversion -Wno-error=sign-conversion -Wno-error=strict-overflow -Wno-type-limits
 
+DEPS = $(SBSA_ROOT)/platform/pal_baremetal/FVP/include/platform_override_fvp.h
+
 OBJ_DIR := $(SBSA_ROOT)/build/obj
 LIB_DIR := $(SBSA_ROOT)/build/lib
 OUT_DIR = $(SBSA_ROOT)/build
@@ -54,6 +56,8 @@ create_dirs:
 	@mkdir ${LIB_DIR}
 
 
+$(OBJ_DIR)/%.o: $(DEPS)
+	$(CC)  -c -o $@ $< >> $(OUT_DIR)/compile.log 2>&1
 $(OBJ_DIR)/%.o: $(SBSA_DIR)/exerciser/%.c
 	$(CC) $(CC_FLAGS) $(CFLAGS) -c -o $@ $< >> $(OUT_DIR)/compile.log 2>&1
 $(OBJ_DIR)/%.o: $(SBSA_DIR)/io_virt/%.c
diff --git a/uefi_app/SbsaAvs.h b/uefi_app/SbsaAvs.h
index 8706c4c2..749558c4 100644
--- a/uefi_app/SbsaAvs.h
+++ b/uefi_app/SbsaAvs.h
@@ -21,7 +21,7 @@
 
 
   #define SBSA_ACS_MAJOR_VER  3
-  #define SBSA_ACS_MINOR_VER  1
+  #define SBSA_ACS_MINOR_VER  2
 
   #define G_SBSA_LEVEL  4
   #define SBSA_MIN_LEVEL_SUPPORTED 3
@@ -29,7 +29,8 @@
   #define G_PRINT_LEVEL AVS_PRINT_TEST
 
   #define PE_INFO_TBL_SZ         8192 /*Supports maximum 400 PEs*/
-  #define GIC_INFO_TBL_SZ        239616 /*Supports maximum 832 gic info (GICH, CPUIF, RD, ITS, MSI, D)*/
+  #define GIC_INFO_TBL_SZ        239616 /* Supports maximum 832 gic info */
+                                        /* (GICH, CPUIF, RD, ITS, MSI, D) */
   #define TIMER_INFO_TBL_SZ      1024 /*Supports maximum 2 system timers*/
   #define WD_INFO_TBL_SZ         512  /*Supports maximum 20 Watchdogs*/
   #define MEM_INFO_TBL_SZ        32768/*Supports maximum 800 memory regions*/
diff --git a/val/include/pal_interface.h b/val/include/pal_interface.h
index d0e0e2af..cd8fad96 100644
--- a/val/include/pal_interface.h
+++ b/val/include/pal_interface.h
@@ -25,6 +25,14 @@
 #ifdef TARGET_LINUX
   typedef char          char8_t;
   typedef long long int addr_t;
+#define TIMEOUT_LARGE    0x1000000
+#define TIMEOUT_MEDIUM   0x100000
+#define TIMEOUT_SMALL    0x1000
+
+#define PCIE_MAX_BUS   256
+#define PCIE_MAX_DEV    32
+#define PCIE_MAX_FUNC    8
+
 #elif TARGET_EMULATION
 #include <stdlib.h>
 #include <stdint.h>
@@ -32,6 +40,15 @@
   typedef uint64_t addr_t;
   typedef char     char8_t;
   typedef uint64_t dma_addr_t;
+
+#define TIMEOUT_LARGE    PLATFORM_OVERRIDE_TIMEOUT_LARGE
+#define TIMEOUT_MEDIUM   PLATFORM_OVERRIDE_TIMEOUT_MEDIUM
+#define TIMEOUT_SMALL    PLATFORM_OVERRIDE_TIMEOUT_SMALL
+
+#define PCIE_MAX_BUS    PLATFORM_OVERRIDE_PCIE_MAX_BUS
+#define PCIE_MAX_DEV    PLATFORM_OVERRIDE_PCIE_MAX_DEV
+#define PCIE_MAX_FUNC   PLATFORM_OVERRIDE_PCIE_MAX_FUNC
+
 #else
   typedef INT8   int8_t;
   typedef INT32  int32_t;
@@ -43,11 +60,27 @@
   typedef UINT64 uint64_t;
   typedef UINT64 addr_t;
 
+#if PLATFORM_OVERRIDE_TIMEOUT
+    #define TIMEOUT_LARGE    PLATFORM_OVERRIDE_TIMEOUT_LARGE
+    #define TIMEOUT_MEDIUM   PLATFORM_OVERRIDE_TIMEOUT_MEDIUM
+    #define TIMEOUT_SMALL    PLATFORM_OVERRIDE_TIMEOUT_SMALL
+#else
+    #define TIMEOUT_LARGE    0x1000000
+    #define TIMEOUT_MEDIUM   0x100000
+    #define TIMEOUT_SMALL    0x1000
 #endif
 
-#define TIMEOUT_LARGE    0x1000000
-#define TIMEOUT_MEDIUM   0x100000
-#define TIMEOUT_SMALL    0x1000
+#if PLATFORM_OVERRIDE_MAX_BDF
+    #define PCIE_MAX_BUS    PLATFORM_OVERRIDE_PCIE_MAX_BUS
+    #define PCIE_MAX_DEV    PLATFORM_OVERRIDE_PCIE_MAX_DEV
+    #define PCIE_MAX_FUNC   PLATFORM_OVERRIDE_PCIE_MAX_FUNC
+#else
+    #define PCIE_MAX_BUS   256
+    #define PCIE_MAX_DEV    32
+    #define PCIE_MAX_FUNC    8
+#endif
+
+#endif
 
 #define ONE_MILLISECOND 1000
 
@@ -621,7 +654,7 @@ uint16_t pal_mmio_read16(uint64_t addr);
 uint32_t pal_mem_page_size(void);
 void    *pal_mem_alloc_pages(uint32_t num_pages);
 void     pal_mem_free_pages(void *page_base, uint32_t num_pages);
-void *pal_aligned_alloc(uint32_t alignment, uint32_t size);
+void    *pal_aligned_alloc(uint32_t alignment, uint32_t size);
 
 uint32_t pal_mmio_read(uint64_t addr);
 uint64_t pal_mmio_read64(uint64_t addr);
diff --git a/val/include/sbsa_avs_pcie.h b/val/include/sbsa_avs_pcie.h
index 656fc0b5..c7b7e523 100644
--- a/val/include/sbsa_avs_pcie.h
+++ b/val/include/sbsa_avs_pcie.h
@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2016-2021, Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2016-2022, Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -33,10 +33,6 @@
 
 #define GET_DEVICE_ID(bus, dev, func) ((bus << 8) | (dev << 3) | func)
 
-#define PCIE_MAX_BUS   256
-#define PCIE_MAX_DEV    32
-#define PCIE_MAX_FUNC    8
-
 #define PCIE_BUS_SHIFT 8
 #define PCIE_CFG_SIZE  4096
 
diff --git a/val/include/val_interface.h b/val/include/val_interface.h
index bfc4f6ac..0d3bfe0c 100644
--- a/val/include/val_interface.h
+++ b/val/include/val_interface.h
@@ -178,6 +178,7 @@ void     val_pcie_create_info_table(uint64_t *pcie_info_table);
 uint32_t val_pcie_create_device_bdf_table(void);
 addr_t val_pcie_get_ecam_base(uint32_t rp_bdf);
 void *val_pcie_bdf_table_ptr(void);
+uint32_t val_pcie_get_max_bdf(void);
 void     val_pcie_free_info_table(void);
 uint32_t val_pcie_execute_tests(uint32_t enable_pcie, uint32_t level, uint32_t num_pe);
 uint32_t val_pcie_is_devicedma_64bit(uint32_t bdf);
diff --git a/val/src/avs_pcie.c b/val/src/avs_pcie.c
index 60c4ae85..8b062d81 100644
--- a/val/src/avs_pcie.c
+++ b/val/src/avs_pcie.c
@@ -770,7 +770,7 @@ val_pcie_device_driver_present(uint32_t bdf)
   uint32_t dev  = PCIE_EXTRACT_BDF_DEV (bdf);
   uint32_t func = PCIE_EXTRACT_BDF_FUNC (bdf);
 
-  return (pal_pcie_device_driver_present(seg, bus, dev, func));
+  return pal_pcie_device_driver_present(seg, bus, dev, func);
 }
 
 /**
diff --git a/val/src/avs_pgt.c b/val/src/avs_pgt.c
index 82a0ac4b..98b9afea 100644
--- a/val/src/avs_pgt.c
+++ b/val/src/avs_pgt.c
@@ -169,9 +169,9 @@ uint32_t val_pgt_create(memory_region_descriptor_t *mem_desc, pgt_descriptor_t *
 
     for (mem_desc_iter = mem_desc; mem_desc_iter->length != 0; ++mem_desc_iter)
     {
-        val_print(PGT_DEBUG_LEVEL, "      val_pgt_create: input addr = 0x%llx     ", mem_desc->virtual_address);
-        val_print(PGT_DEBUG_LEVEL, "      val_pgt_create: output addr = 0x%llx     ", mem_desc->physical_address);
-        val_print(PGT_DEBUG_LEVEL, "      val_pgt_create: length = 0x%llx\n     ", mem_desc->length);
+        val_print(PGT_DEBUG_LEVEL, "val_pgt_create: i/p addr 0x%llx", mem_desc->virtual_address);
+        val_print(PGT_DEBUG_LEVEL, "val_pgt_create: o/p addr 0x%llx", mem_desc->physical_address);
+        val_print(PGT_DEBUG_LEVEL, "val_pgt_create: length 0x%llx\n ", mem_desc->length);
         if ((mem_desc->virtual_address & (uint64_t)(page_size - 1)) != 0 ||
             (mem_desc->physical_address & (uint64_t)(page_size - 1)) != 0)
             {
@@ -250,11 +250,11 @@ uint64_t val_pgt_get_attributes(pgt_descriptor_t pgt_desc, uint64_t virtual_addr
         tt_base_virt = (uint64_t*)val_memory_phys_to_virt(tt_base_phys);
         val64 = tt_base_virt[index];
 
-        val_print(PGT_DEBUG_LEVEL, "\n      val_pgt_get_attributes: this_level = %d     ", this_level);
-        val_print(PGT_DEBUG_LEVEL, "\n      val_pgt_get_attributes: index = %d     ", index);
-        val_print(PGT_DEBUG_LEVEL, "\n      val_pgt_get_attributes: bits_remaining = %d     ", bits_remaining);
-        val_print(PGT_DEBUG_LEVEL, "\n      val_pgt_get_attributes: tt_base_virt = %llx     ", (uint64_t)tt_base_virt);
-        val_print(PGT_DEBUG_LEVEL, "\n      val_pgt_get_attributes: val64 = %llx     ", val64);
+        val_print(PGT_DEBUG_LEVEL, "\nval_pgt_get_attr: this_level = %d     ", this_level);
+        val_print(PGT_DEBUG_LEVEL, "\nval_pgt_get_attr: index = %d     ", index);
+        val_print(PGT_DEBUG_LEVEL, "\nval_pgt_get_attr: bits_remaining = %d     ", bits_remaining);
+        val_print(PGT_DEBUG_LEVEL, "\nval_pgt_get_attr: tt_base_virt %llx", (uint64_t)tt_base_virt);
+        val_print(PGT_DEBUG_LEVEL, "\nval_pgt_get_attr: val64 = %llx     ", val64);
         if (this_level == 3)
         {
             if (!IS_PGT_ENTRY_PAGE(val64))
diff --git a/val/src/avs_test_infra.c b/val/src/avs_test_infra.c
index 4d4e80b7..5bd87653 100644
--- a/val/src/avs_test_infra.c
+++ b/val/src/avs_test_infra.c
@@ -43,20 +43,20 @@ val_print(uint32_t level, char8_t *string, uint64_t data)
 void
 val_print_test_end(uint32_t status, char8_t *string)
 {
-  pal_print("\n      ",0);
+  pal_print("\n      ", 0);
 
-  if (status != AVS_STATUS_PASS){
+  if (status != AVS_STATUS_PASS) {
       pal_print("One or more ", 0);
       pal_print(string, 0);
       pal_print(" tests failed or were skipped.", 0);
   }
-  else{
+  else {
       pal_print("All ", 0);
       pal_print(string, 0);
       pal_print(" tests passed.", 0);
   }
 
-  pal_print("\n",0);
+  pal_print("\n", 0);
 
 }
 
diff --git a/val/sys_arch_src/smmu_v3/smmu_v3.c b/val/sys_arch_src/smmu_v3/smmu_v3.c
index 6fb75342..533af811 100644
--- a/val/sys_arch_src/smmu_v3/smmu_v3.c
+++ b/val/sys_arch_src/smmu_v3/smmu_v3.c
@@ -636,8 +636,8 @@ static void dump_cdtab(uint64_t *ctx_desc)
 static void smmu_cdtab_write_l1_desc(uint64_t *dst,
                       smmu_cdtab_l1_ctx_desc_t *l1_desc)
 {
-    uint64_t val = (l1_desc->l2desc_phys & (CDTAB_L1_DESC_L2PTR_MASK << CDTAB_L1_DESC_L2PTR_SHIFT)) |
-          CDTAB_L1_DESC_V;
+    uint64_t val = (l1_desc->l2desc_phys &
+          (CDTAB_L1_DESC_L2PTR_MASK << CDTAB_L1_DESC_L2PTR_SHIFT)) | CDTAB_L1_DESC_V;
 
     *dst = val;
 }
diff --git a/val/val.mk b/val/val.mk
index 334560b3..c602ccef 100644
--- a/val/val.mk
+++ b/val/val.mk
@@ -37,6 +37,7 @@ CFLAGS    += -I$(SBSA_ROOT)/val/sys_arch_src/gic/v2
 ASFLAGS   += -I$(SBSA_ROOT)/val/src/AArch64/
 
 DEPS = $(SBSA_ROOT)/val/include/val_interface.h
+DEPS += $(SBSA_ROOT)/platform/pal_baremetal/FVP/include/platform_override_fvp.h
 
 OUT_DIR = $(SBSA_ROOT)/build/
 OBJ_DIR := $(SBSA_ROOT)/build/obj