From 397e679f18d76574b15d1bc6ed4d925cc78ae359 Mon Sep 17 00:00:00 2001 From: Rajat Goyal Date: Thu, 12 Jan 2023 15:59:29 +0530 Subject: [PATCH 1/8] SBSA Test Changes - Added RuleID to all the tests. - Test Order Change for Few tests. - Rearranged some of the test to OS view. Signed-off-by: Rajat Goyal --- platform/pal_uefi/include/pal_uefi.h | 7 + platform/pal_uefi/src/pal_pe.c | 1 + platform/pal_uefi/src/pal_peripherals.c | 27 +- test_pool/exerciser/test_e001.c | 10 +- test_pool/exerciser/test_e002.c | 9 +- test_pool/exerciser/test_e003.c | 9 +- test_pool/exerciser/test_e004.c | 10 +- test_pool/exerciser/test_e005.c | 9 +- test_pool/exerciser/test_e006.c | 9 +- test_pool/exerciser/test_e007.c | 9 +- test_pool/exerciser/test_e008.c | 9 +- test_pool/exerciser/test_e009.c | 10 +- test_pool/exerciser/test_e010.c | 9 +- test_pool/exerciser/test_e011.c | 9 +- test_pool/exerciser/test_e012.c | 9 +- test_pool/exerciser/test_e013.c | 9 +- test_pool/exerciser/test_e014.c | 9 +- test_pool/exerciser/test_e015.c | 9 +- test_pool/exerciser/test_e016.c | 10 +- .../gic/{ => operating_system}/test_g001.c | 11 +- test_pool/gic/operating_system/test_g002.c | 121 ++++++ test_pool/gic/test_g002.c | 74 ---- test_pool/gic/test_g003.c | 68 ---- test_pool/gic/test_g004.c | 98 ----- test_pool/io_virt/test_i001.c | 86 ----- test_pool/io_virt/test_i002.c | 79 ---- test_pool/io_virt/test_i004.c | 88 ----- test_pool/io_virt/test_i005.c | 76 ---- test_pool/io_virt/test_i006.c | 69 ---- test_pool/io_virt/test_i008.c | 93 ----- test_pool/io_virt/test_i010.c | 135 ------- test_pool/io_virt/test_i011.c | 105 ------ test_pool/io_virt/test_i012.c | 100 ----- test_pool/io_virt/test_i015.c | 107 ------ test_pool/io_virt/test_i016.c | 105 ------ .../memory_map/operating_system/test_m001.c | 77 ++++ test_pool/nist_sts/test_n001.c | 9 +- test_pool/pcie/test_p001.c | 9 +- test_pool/pcie/test_p002.c | 9 +- test_pool/pcie/test_p003.c | 9 +- test_pool/pcie/test_p005.c | 9 +- test_pool/pcie/test_p006.c | 9 +- test_pool/pcie/test_p007.c | 9 +- test_pool/pcie/test_p008.c | 9 +- test_pool/pcie/test_p009.c | 147 -------- test_pool/pcie/test_p010.c | 9 +- test_pool/pcie/test_p011.c | 9 +- test_pool/pcie/test_p012.c | 9 +- test_pool/pcie/test_p013.c | 9 +- test_pool/pcie/test_p014.c | 9 +- test_pool/pcie/test_p015.c | 9 +- test_pool/pcie/test_p016.c | 9 +- test_pool/pcie/test_p017.c | 9 +- test_pool/pcie/test_p018.c | 9 +- test_pool/pcie/test_p019.c | 9 +- test_pool/pcie/test_p020.c | 9 +- test_pool/pcie/test_p021.c | 9 +- test_pool/pcie/test_p022.c | 9 +- test_pool/pcie/test_p023.c | 9 +- test_pool/pcie/test_p024.c | 9 +- test_pool/pcie/test_p025.c | 9 +- test_pool/pcie/test_p026.c | 9 +- test_pool/pcie/test_p027.c | 9 +- test_pool/pcie/test_p028.c | 9 +- test_pool/pcie/test_p029.c | 9 +- test_pool/pcie/test_p030.c | 9 +- test_pool/pcie/test_p031.c | 9 +- test_pool/pcie/test_p032.c | 9 +- test_pool/pcie/test_p033.c | 9 +- test_pool/pcie/test_p034.c | 9 +- test_pool/pcie/test_p035.c | 9 +- test_pool/pcie/test_p036.c | 9 +- test_pool/pcie/test_p037.c | 9 +- test_pool/pcie/test_p038.c | 9 +- test_pool/pcie/test_p039.c | 9 +- test_pool/pcie/test_p040.c | 9 +- test_pool/pcie/test_p041.c | 9 +- test_pool/pcie/test_p042.c | 9 +- test_pool/pcie/test_p043.c | 9 +- test_pool/pcie/test_p044.c | 9 +- test_pool/pcie/test_p045.c | 9 +- test_pool/pcie/test_p046.c | 9 +- test_pool/pcie/test_p047.c | 9 +- test_pool/pcie/test_p048.c | 11 +- test_pool/pcie/test_p049.c | 9 +- test_pool/pcie/test_p050.c | 9 +- test_pool/pcie/test_p051.c | 9 +- test_pool/pcie/test_p052.c | 9 +- test_pool/pcie/test_p053.c | 9 +- test_pool/pcie/test_p054.c | 9 +- test_pool/pcie/test_p055.c | 9 +- test_pool/pcie/test_p056.c | 9 +- test_pool/pcie/test_p057.c | 15 +- test_pool/pcie/test_p058.c | 10 +- test_pool/pcie/test_p059.c | 6 +- test_pool/pcie/test_p060.c | 10 +- .../test_c001.c} | 11 +- .../test_c002.c} | 11 +- .../test_c003.c} | 18 +- test_pool/pe/operating_system/test_c004.c | 83 ++++ .../test_c005.c} | 11 +- test_pool/pe/operating_system/test_c006.c | 65 ++++ .../test_c007.c} | 11 +- .../test_c008.c} | 11 +- .../test_c009.c} | 11 +- .../test_c010.c} | 11 +- .../test_c011.c} | 11 +- .../test_c012.c} | 11 +- .../test_c013.c} | 11 +- .../test_c014.c} | 11 +- test_pool/pe/operating_system/test_c015.c | 93 +++++ test_pool/pe/operating_system/test_c016.c | 126 +++++++ .../test_c017.c} | 11 +- .../test_c018.c} | 11 +- .../test_c019.c} | 11 +- .../test_c020.c} | 11 +- .../test_c021.c} | 11 +- .../test_c022.c} | 11 +- .../test_c023.c} | 11 +- test_pool/pe/operating_system/test_c024.c | 59 +++ .../test_c025.c} | 12 +- .../test_c026.c} | 11 +- .../test_c027.c} | 11 +- test_pool/pe/operating_system/test_c028.c | 59 +++ test_pool/pe/operating_system/test_c029.c | 59 +++ .../pe/{ => operating_system}/test_c030.c | 23 +- test_pool/pe/operating_system/test_c031.c | 59 +++ test_pool/pe/operating_system/test_c032.c | 60 +++ test_pool/pe/operating_system/test_c033.c | 60 +++ test_pool/pe/operating_system/test_c034.c | 68 ++++ test_pool/pe/operating_system/test_c035.c | 60 +++ test_pool/pe/operating_system/test_c036.c | 61 +++ test_pool/pe/operating_system/test_c037.c | 60 +++ test_pool/pe/test_c001.c | 65 ---- test_pool/pe/test_c002.c | 62 --- test_pool/pe/test_c005.c | 59 --- test_pool/pe/test_c006.c | 69 ---- test_pool/pe/test_c007.c | 59 --- test_pool/pe/test_c008.c | 61 --- test_pool/pe/test_c011.c | 110 ------ test_pool/pe/test_c012.c | 62 --- test_pool/pe/test_c013.c | 60 --- test_pool/pe/test_c014.c | 74 ---- test_pool/pe/test_c015.c | 279 -------------- test_pool/pe/test_c017.c | 60 --- test_pool/peripherals/test_d001.c | 92 ----- test_pool/peripherals/test_d002.c | 92 ----- test_pool/peripherals/test_d003.c | 270 ------------- test_pool/peripherals/test_m001.c | 127 ------- test_pool/power_wakeup/test_u001.c | 355 ------------------ test_pool/power_wakeup/test_u002.c | 275 -------------- .../operating_system/test_i001.c} | 13 +- .../operating_system/test_i002.c} | 14 +- test_pool/smmu/operating_system/test_i003.c | 100 +++++ test_pool/smmu/operating_system/test_i004.c | 100 +++++ .../operating_system/test_i005.c} | 11 +- .../operating_system/test_i006.c} | 11 +- .../operating_system/test_i007.c} | 34 +- .../operating_system/test_i008.c} | 12 +- .../operating_system/test_i009.c} | 10 +- .../operating_system/test_i010.c} | 12 +- .../operating_system/test_i011.c} | 12 +- .../operating_system/test_i012.c} | 12 +- test_pool/smmu/operating_system/test_i013.c | 108 ++++++ test_pool/smmu/operating_system/test_i014.c | 120 ++++++ .../operating_system/test_i015.c} | 24 +- test_pool/smmu/operating_system/test_i016.c | 137 +++++++ test_pool/timer_wd/test_t001.c | 65 ---- test_pool/timer_wd/test_t002.c | 88 ----- test_pool/timer_wd/test_t003.c | 88 ----- test_pool/timer_wd/test_t004.c | 94 ----- test_pool/timer_wd/test_t005.c | 105 ------ test_pool/timer_wd/test_t006.c | 71 ---- test_pool/timer_wd/test_t007.c | 162 -------- test_pool/timer_wd/test_t008.c | 128 ------- test_pool/timer_wd/test_w001.c | 105 ------ test_pool/timer_wd/test_w002.c | 128 ------- .../operating_system/test_w001.c} | 13 +- uefi_app/SbsaAvs.inf | 144 +++---- uefi_app/SbsaAvsNist.inf | 132 +++---- val/include/pal_interface.h | 2 + val/include/sbsa_avs_common.h | 11 +- val/include/sbsa_avs_memory.h | 8 +- val/include/sbsa_avs_pe.h | 6 +- val/include/sbsa_avs_val.h | 4 +- val/include/val_interface.h | 2 + val/src/avs_gic_support.c | 8 +- val/src/avs_memory.c | 46 ++- val/src/avs_pe.c | 81 ++-- val/src/avs_pe_infra.c | 6 +- val/src/avs_peripherals.c | 5 + val/src/avs_status.c | 34 +- val/src/avs_test_infra.c | 15 +- 193 files changed, 2672 insertions(+), 5445 deletions(-) rename test_pool/gic/{ => operating_system}/test_g001.c (84%) create mode 100644 test_pool/gic/operating_system/test_g002.c delete mode 100644 test_pool/gic/test_g002.c delete mode 100644 test_pool/gic/test_g003.c delete mode 100644 test_pool/gic/test_g004.c delete mode 100644 test_pool/io_virt/test_i001.c delete mode 100644 test_pool/io_virt/test_i002.c delete mode 100644 test_pool/io_virt/test_i004.c delete mode 100644 test_pool/io_virt/test_i005.c delete mode 100644 test_pool/io_virt/test_i006.c delete mode 100644 test_pool/io_virt/test_i008.c delete mode 100644 test_pool/io_virt/test_i010.c delete mode 100644 test_pool/io_virt/test_i011.c delete mode 100644 test_pool/io_virt/test_i012.c delete mode 100644 test_pool/io_virt/test_i015.c delete mode 100644 test_pool/io_virt/test_i016.c create mode 100644 test_pool/memory_map/operating_system/test_m001.c delete mode 100644 test_pool/pcie/test_p009.c rename test_pool/pe/{test_c004.c => operating_system/test_c001.c} (90%) rename test_pool/pe/{test_c003.c => operating_system/test_c002.c} (85%) rename test_pool/pe/{test_c010.c => operating_system/test_c003.c} (74%) create mode 100644 test_pool/pe/operating_system/test_c004.c rename test_pool/pe/{test_c019.c => operating_system/test_c005.c} (86%) create mode 100644 test_pool/pe/operating_system/test_c006.c rename test_pool/pe/{test_c020.c => operating_system/test_c007.c} (86%) rename test_pool/pe/{test_c021.c => operating_system/test_c008.c} (86%) rename test_pool/pe/{test_c024.c => operating_system/test_c009.c} (86%) rename test_pool/pe/{test_c022.c => operating_system/test_c010.c} (90%) rename test_pool/pe/{test_c026.c => operating_system/test_c011.c} (86%) rename test_pool/pe/{test_c027.c => operating_system/test_c012.c} (88%) rename test_pool/pe/{test_c025.c => operating_system/test_c013.c} (86%) rename test_pool/pe/{test_c023.c => operating_system/test_c014.c} (86%) create mode 100644 test_pool/pe/operating_system/test_c015.c create mode 100644 test_pool/pe/operating_system/test_c016.c rename test_pool/pe/{test_c018.c => operating_system/test_c017.c} (88%) rename test_pool/pe/{test_c033.c => operating_system/test_c018.c} (86%) rename test_pool/pe/{test_c034.c => operating_system/test_c019.c} (86%) rename test_pool/pe/{test_c036.c => operating_system/test_c020.c} (86%) rename test_pool/pe/{test_c028.c => operating_system/test_c021.c} (86%) rename test_pool/pe/{test_c035.c => operating_system/test_c022.c} (86%) rename test_pool/pe/{test_c029.c => operating_system/test_c023.c} (88%) create mode 100644 test_pool/pe/operating_system/test_c024.c rename test_pool/pe/{test_os_c018.c => operating_system/test_c025.c} (82%) rename test_pool/pe/{test_c031.c => operating_system/test_c026.c} (86%) rename test_pool/pe/{test_c032.c => operating_system/test_c027.c} (86%) create mode 100644 test_pool/pe/operating_system/test_c028.c create mode 100644 test_pool/pe/operating_system/test_c029.c rename test_pool/pe/{ => operating_system}/test_c030.c (75%) create mode 100644 test_pool/pe/operating_system/test_c031.c create mode 100644 test_pool/pe/operating_system/test_c032.c create mode 100644 test_pool/pe/operating_system/test_c033.c create mode 100644 test_pool/pe/operating_system/test_c034.c create mode 100644 test_pool/pe/operating_system/test_c035.c create mode 100644 test_pool/pe/operating_system/test_c036.c create mode 100644 test_pool/pe/operating_system/test_c037.c delete mode 100644 test_pool/pe/test_c001.c delete mode 100644 test_pool/pe/test_c002.c delete mode 100644 test_pool/pe/test_c005.c delete mode 100644 test_pool/pe/test_c006.c delete mode 100644 test_pool/pe/test_c007.c delete mode 100644 test_pool/pe/test_c008.c delete mode 100755 test_pool/pe/test_c011.c delete mode 100644 test_pool/pe/test_c012.c delete mode 100644 test_pool/pe/test_c013.c delete mode 100644 test_pool/pe/test_c014.c delete mode 100755 test_pool/pe/test_c015.c delete mode 100644 test_pool/pe/test_c017.c delete mode 100644 test_pool/peripherals/test_d001.c delete mode 100644 test_pool/peripherals/test_d002.c delete mode 100755 test_pool/peripherals/test_d003.c delete mode 100644 test_pool/peripherals/test_m001.c delete mode 100755 test_pool/power_wakeup/test_u001.c delete mode 100755 test_pool/power_wakeup/test_u002.c rename test_pool/{io_virt/test_i007.c => smmu/operating_system/test_i001.c} (89%) mode change 100755 => 100644 rename test_pool/{io_virt/test_i003.c => smmu/operating_system/test_i002.c} (89%) mode change 100755 => 100644 create mode 100644 test_pool/smmu/operating_system/test_i003.c create mode 100644 test_pool/smmu/operating_system/test_i004.c rename test_pool/{io_virt/test_i013.c => smmu/operating_system/test_i005.c} (90%) rename test_pool/{io_virt/test_i014.c => smmu/operating_system/test_i006.c} (90%) rename test_pool/{io_virt/test_i009.c => smmu/operating_system/test_i007.c} (76%) rename test_pool/{io_virt/test_hyp_i005.c => smmu/operating_system/test_i008.c} (87%) rename test_pool/{io_virt/test_os_i005.c => smmu/operating_system/test_i009.c} (90%) rename test_pool/{io_virt/test_os_i006.c => smmu/operating_system/test_i010.c} (89%) rename test_pool/{io_virt/test_os_i007.c => smmu/operating_system/test_i011.c} (89%) rename test_pool/{io_virt/test_os_i008.c => smmu/operating_system/test_i012.c} (90%) create mode 100644 test_pool/smmu/operating_system/test_i013.c create mode 100644 test_pool/smmu/operating_system/test_i014.c rename test_pool/{io_virt/test_os_i009.c => smmu/operating_system/test_i015.c} (82%) create mode 100644 test_pool/smmu/operating_system/test_i016.c delete mode 100644 test_pool/timer_wd/test_t001.c delete mode 100644 test_pool/timer_wd/test_t002.c delete mode 100644 test_pool/timer_wd/test_t003.c delete mode 100644 test_pool/timer_wd/test_t004.c delete mode 100644 test_pool/timer_wd/test_t005.c delete mode 100644 test_pool/timer_wd/test_t006.c delete mode 100755 test_pool/timer_wd/test_t007.c delete mode 100644 test_pool/timer_wd/test_t008.c delete mode 100755 test_pool/timer_wd/test_w001.c delete mode 100755 test_pool/timer_wd/test_w002.c rename test_pool/{timer_wd/test_w003.c => watchdog/operating_system/test_w001.c} (90%) diff --git a/platform/pal_uefi/include/pal_uefi.h b/platform/pal_uefi/include/pal_uefi.h index 4e36e3db..bb37a96e 100644 --- a/platform/pal_uefi/include/pal_uefi.h +++ b/platform/pal_uefi/include/pal_uefi.h @@ -18,6 +18,11 @@ #ifndef __PAL_UEFI_H__ #define __PAL_UEFI_H__ +/* include ACPI specification headers */ +#include "Include/Guid/Acpi.h" +#include +#include "Include/IndustryStandard/Acpi.h" + extern VOID* g_sbsa_log_file_handle; extern UINT32 g_print_level; extern UINT32 g_print_mmio; @@ -99,6 +104,7 @@ typedef struct { UINT32 attr; ///< PE attributes UINT64 mpidr; ///< PE MPIDR UINT32 pmu_gsiv; ///< PMU Interrupt ID + UINT32 gmain_gsiv; /* GIC Maintenace Interrupt */ }PE_INFO_ENTRY; typedef struct { @@ -415,6 +421,7 @@ typedef enum { MEMORY_TYPE_NORMAL, MEMORY_TYPE_RESERVED, MEMORY_TYPE_NOT_POPULATED, + MEMORY_TYPE_PERSISTENT, MEMORY_TYPE_LAST_ENTRY }MEM_INFO_TYPE_e; diff --git a/platform/pal_uefi/src/pal_pe.c b/platform/pal_uefi/src/pal_pe.c index e3c5ebea..5ab15bda 100644 --- a/platform/pal_uefi/src/pal_pe.c +++ b/platform/pal_uefi/src/pal_pe.c @@ -215,6 +215,7 @@ pal_pe_create_info_table(PE_INFO_TABLE *PeTable) Ptr->mpidr = Entry->MPIDR; Ptr->pe_num = PeTable->header.num_of_pe; Ptr->pmu_gsiv = Entry->PerformanceInterruptGsiv; + Ptr->gmain_gsiv = Entry->VGICMaintenanceInterrupt; sbsa_print(AVS_PRINT_DEBUG, L" MPIDR %x PE num %x \n", Ptr->mpidr, Ptr->pe_num); pal_pe_data_cache_ops_by_va((UINT64)Ptr, CLEAN_AND_INVALIDATE); Ptr++; diff --git a/platform/pal_uefi/src/pal_peripherals.c b/platform/pal_uefi/src/pal_peripherals.c index bf0e3fe6..643f6d4d 100644 --- a/platform/pal_uefi/src/pal_peripherals.c +++ b/platform/pal_uefi/src/pal_peripherals.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2020-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2020-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -191,6 +191,25 @@ IsDeviceMemory(EFI_MEMORY_TYPE type) switch(type) { case EfiMemoryMappedIO: case EfiMemoryMappedIOPortSpace: + return TRUE; + default: + return FALSE; + } +} + +/** + @brief Check if the memory type is persistent + + @param EFI_MEMORY_TYPE - Type of UEFI memory. + + @return true if memory is persistent + false otherwise +**/ +BOOLEAN +IsPersistentMemory(EFI_MEMORY_TYPE type) +{ + + switch(type) { case EfiPersistentMemory: return TRUE; default: @@ -261,7 +280,11 @@ pal_memory_create_info_table(MEMORY_INFO_TABLE *memoryInfoTable) if (IsDeviceMemory ((EFI_MEMORY_TYPE)MemoryMapPtr->Type)) { memoryInfoTable->info[i].type = MEMORY_TYPE_DEVICE; } else { - memoryInfoTable->info[i].type = MEMORY_TYPE_NOT_POPULATED; + if (IsPersistentMemory ((EFI_MEMORY_TYPE)MemoryMapPtr->Type)) { + memoryInfoTable->info[i].type = MEMORY_TYPE_PERSISTENT; + } else { + memoryInfoTable->info[i].type = MEMORY_TYPE_NOT_POPULATED; + } } } } diff --git a/test_pool/exerciser/test_e001.c b/test_pool/exerciser/test_e001.c index 133d3b64..3782c30d 100644 --- a/test_pool/exerciser/test_e001.c +++ b/test_pool/exerciser/test_e001.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2018-2019, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2018-2019, 2022-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,7 +24,7 @@ #define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 1) #define TEST_DESC "Enhanced ECAM Memory access check " - +#define TEST_RULE "" static void @@ -93,14 +93,14 @@ e001_entry(void) uint32_t num_pe = 1; uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* Get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/exerciser/test_e002.c b/test_pool/exerciser/test_e002.c index 2c720d92..4415f4ee 100644 --- a/test_pool/exerciser/test_e002.c +++ b/test_pool/exerciser/test_e002.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2018,2021-2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2018,2021-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -26,6 +26,7 @@ #define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 2) #define TEST_DESC "PCIe Memory access check " +#define TEST_RULE "" #define TEST_DATA 0xDEADDAED static const ARM_NORMAL_MEM ARM_NORMAL_MEM_ARRAY[] = {NORMAL_NC, NORMAL_WT}; @@ -166,14 +167,14 @@ e002_entry(void) uint32_t num_pe = 1; uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* Get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/exerciser/test_e003.c b/test_pool/exerciser/test_e003.c index c37a5720..bfe3c184 100644 --- a/test_pool/exerciser/test_e003.c +++ b/test_pool/exerciser/test_e003.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2018-2021, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2018-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,6 +29,7 @@ #define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 3) #define TEST_DESC "PCIe Address translation check " +#define TEST_RULE "" #define TEST_DATA_NUM_PAGES 4 #define TEST_DATA 0xDE @@ -270,14 +271,14 @@ e003_entry(void) uint32_t num_pe = 1; uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* Get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/exerciser/test_e004.c b/test_pool/exerciser/test_e004.c index 8f5a4a11..a162f545 100644 --- a/test_pool/exerciser/test_e004.c +++ b/test_pool/exerciser/test_e004.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2018-2021, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2018-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -27,7 +27,7 @@ #define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 4) #define TEST_DESC "Generate MSI(X) interrupts " - +#define TEST_RULE "PCI_MSI_2,ITS_DEV_6" static uint32_t irq_pending; static uint32_t lpi_int_id = 0x204C; @@ -191,15 +191,15 @@ e004_entry (void) uint32_t num_pe = 1; uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test (TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) { val_run_test_payload (TEST_NUM, num_pe, payload, 0); } /* Get the result from all PE and check for failure */ - status = val_check_for_error (TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status (0, SBSA_AVS_END (g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/exerciser/test_e005.c b/test_pool/exerciser/test_e005.c index 0b757fa7..a1ae015a 100644 --- a/test_pool/exerciser/test_e005.c +++ b/test_pool/exerciser/test_e005.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2018-2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2018-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,6 +29,7 @@ #define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 5) #define TEST_DESC "Generate PASID PCIe transactions " +#define TEST_RULE "PCI_PAS_1, RE_SMU_4" #define TEST_DATA_NUM_PAGES 2 #define TEST_DATA 0xDE @@ -393,14 +394,14 @@ e005_entry(void) uint32_t num_pe = 1; uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* Get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/exerciser/test_e006.c b/test_pool/exerciser/test_e006.c index 56f752af..3ab40bb2 100644 --- a/test_pool/exerciser/test_e006.c +++ b/test_pool/exerciser/test_e006.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2018-2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2018-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,6 +24,7 @@ #define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 6) #define TEST_DESC "Generate PCIe legacy interrupts " +#define TEST_RULE "PCI_LI_02" static uint32_t instance; static uint32_t e_intr_line; @@ -188,15 +189,15 @@ e006_entry (void) uint32_t num_pe = 1; uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test (TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) { val_run_test_payload (TEST_NUM, num_pe, payload, 0); } /* Get the result from all PE and check for failure */ - status = val_check_for_error (TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status (0, SBSA_AVS_END (g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/exerciser/test_e007.c b/test_pool/exerciser/test_e007.c index 7f8bff71..3e86013e 100644 --- a/test_pool/exerciser/test_e007.c +++ b/test_pool/exerciser/test_e007.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2018-2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2018-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -45,6 +45,7 @@ #define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 7) #define TEST_DESC "Check PCI Express I/O Coherency " +#define TEST_RULE "PCI_IC_01, PCI_IC_03, PCI_IC_06, PCI_IC_07, PCI_IC_08" #define TEST_DATA_BLK_SIZE (4*1024) #define KNOWN_DATA 0xDE @@ -234,15 +235,15 @@ e007_entry (void) uint32_t num_pe = 1; uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test (TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) { val_run_test_payload (TEST_NUM, num_pe, payload, 0); } /* Get the result from all PE and check for failure */ - status = val_check_for_error (TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status (0, SBSA_AVS_END (g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/exerciser/test_e008.c b/test_pool/exerciser/test_e008.c index b54d0134..71b28a1d 100644 --- a/test_pool/exerciser/test_e008.c +++ b/test_pool/exerciser/test_e008.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2019-2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -27,6 +27,7 @@ #define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 8) #define TEST_DESC "Check BME functionality of RP " +#define TEST_RULE "" #define TEST_DATA_NUM_PAGES 1 @@ -195,14 +196,14 @@ e008_entry(void) uint32_t num_pe = 1; uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* Get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/exerciser/test_e009.c b/test_pool/exerciser/test_e009.c index c3be7156..87781a80 100644 --- a/test_pool/exerciser/test_e009.c +++ b/test_pool/exerciser/test_e009.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2019-2021, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -27,7 +27,7 @@ #define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 9) #define TEST_DESC "Check RP Sec Bus transactions are TYPE0" - +#define TEST_RULE "PCI_IN_11" static void @@ -102,14 +102,14 @@ e009_entry(void) uint32_t num_pe = 1; uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* Get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/exerciser/test_e010.c b/test_pool/exerciser/test_e010.c index 42bf5042..aae1d14e 100644 --- a/test_pool/exerciser/test_e010.c +++ b/test_pool/exerciser/test_e010.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2019-2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -27,6 +27,7 @@ #define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 10) #define TEST_DESC "Check RP Sub Bus transactions are TYPE1" +#define TEST_RULE "PCI_IN_10" #define MAX_BUS 255 #define BUS_SHIFT 16 @@ -196,14 +197,14 @@ e010_entry(void) uint32_t num_pe = 1; uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* Get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/exerciser/test_e011.c b/test_pool/exerciser/test_e011.c index 0227766e..adbc02aa 100644 --- a/test_pool/exerciser/test_e011.c +++ b/test_pool/exerciser/test_e011.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2018-2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2018-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,6 +29,7 @@ #define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 11) #define TEST_DESC "ATS Functionality Check " +#define TEST_RULE "" #define TEST_DATA_NUM_PAGES 1 #define TEST_DATA 0xDE @@ -330,14 +331,14 @@ e011_entry(void) uint32_t num_pe = 1; uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* Get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/exerciser/test_e012.c b/test_pool/exerciser/test_e012.c index 934bfd85..bf5a76a0 100644 --- a/test_pool/exerciser/test_e012.c +++ b/test_pool/exerciser/test_e012.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020-2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -28,6 +28,7 @@ #define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 12) #define TEST_DESC "Check P2P ACS Functionality " +#define TEST_RULE "PCI_PP_04" static uint32_t @@ -309,14 +310,14 @@ e012_entry(void) uint32_t num_pe = 1; uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* Get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/exerciser/test_e013.c b/test_pool/exerciser/test_e013.c index 952ff810..57fe8645 100644 --- a/test_pool/exerciser/test_e013.c +++ b/test_pool/exerciser/test_e013.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020-2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,6 +29,7 @@ #define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 13) #define TEST_DESC "Check ACS Redirected Req Valid " +#define TEST_RULE "PCI_PP_04" static uint32_t @@ -462,14 +463,14 @@ e013_entry(void) uint32_t num_pe = 1; uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* Get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/exerciser/test_e014.c b/test_pool/exerciser/test_e014.c index acab46ca..17fd3851 100644 --- a/test_pool/exerciser/test_e014.c +++ b/test_pool/exerciser/test_e014.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2018-2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2018-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -35,6 +35,7 @@ #define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 14) #define TEST_DESC "Check PCIe Software Coherency " +#define TEST_RULE "PCI_IC_04, RE_ORD_4" #define TEST_DATA_BLK_SIZE (4*1024) #define NEW_DATA 0xAD @@ -219,16 +220,16 @@ e014_entry (void) uint32_t num_pe = 1; uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test (TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) { val_run_test_payload (TEST_NUM, num_pe, payload, 0); } /* Get the result from all PE and check for failure */ - status = val_check_for_error (TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status (0, SBSA_AVS_END (g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/exerciser/test_e015.c b/test_pool/exerciser/test_e015.c index b9b1a20f..eb704c43 100644 --- a/test_pool/exerciser/test_e015.c +++ b/test_pool/exerciser/test_e015.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -27,6 +27,7 @@ #define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 15) #define TEST_DESC "Arrival order & Gathering Check " +#define TEST_RULE "PCI_IC_05, RE_ORD_1, RE_ORD_2" /* 0 means read transction, 1 means write transaction */ static uint32_t transaction_order[] = {1, 1, 0, 1, 0, 0, 0, 0}; @@ -342,14 +343,14 @@ e015_entry(void) uint32_t num_pe = 1; uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* Get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/exerciser/test_e016.c b/test_pool/exerciser/test_e016.c index 1923ed3e..05637f11 100644 --- a/test_pool/exerciser/test_e016.c +++ b/test_pool/exerciser/test_e016.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2021, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -27,7 +27,7 @@ #define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 16) #define TEST_DESC "ARI forwarding Rule " - +#define TEST_RULE "PCI_IN_17" static void @@ -184,14 +184,14 @@ e016_entry(void) uint32_t num_pe = 1; uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* Get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/gic/test_g001.c b/test_pool/gic/operating_system/test_g001.c similarity index 84% rename from test_pool/gic/test_g001.c rename to test_pool/gic/operating_system/test_g001.c index c9804b9c..f346f19a 100644 --- a/test_pool/gic/test_g001.c +++ b/test_pool/gic/operating_system/test_g001.c @@ -21,6 +21,7 @@ #include "val/include/sbsa_avs_gic.h" #define TEST_NUM (AVS_GIC_TEST_NUM_BASE + 1) +#define TEST_RULE "S_L3GI_01" #define TEST_DESC "Check GIC version " static @@ -35,7 +36,9 @@ payload(void) val_print(AVS_PRINT_INFO, "\n Received GIC version = %4d ", gic_version); if (gic_version < 3) { - val_print(AVS_PRINT_ERR, "\n GIC version is %3x ", gic_version); + val_print(AVS_PRINT_ERR, + "\n GIC version is %3x, expected GICv3 or higher version", + gic_version); val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); return; } @@ -52,15 +55,15 @@ g001_entry(uint32_t num_pe) num_pe = 1; //This GIC test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/gic/operating_system/test_g002.c b/test_pool/gic/operating_system/test_g002.c new file mode 100644 index 00000000..a749ffc0 --- /dev/null +++ b/test_pool/gic/operating_system/test_g002.c @@ -0,0 +1,121 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_gic.h" +#include "val/include/sbsa_avs_pe.h" + +#define TEST_NUM (AVS_GIC_TEST_NUM_BASE + 2) +#define TEST_RULE "S_L5PP_01" +#define TEST_DESC "Check Reserved PPI Assignments " + +/* PPI IDs 1056-1071 and 1088-1103 are reserved for future SBSA usage */ +#define IS_PPI_RESERVED(id) ((id > 1055 && id < 1072) || (id > 1087 && id < 1104)) + +static +void +payload() +{ + + uint32_t intid; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 5) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* Check non-secure physical timer interrupt */ + intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID, 0); + if (IS_PPI_RESERVED(intid)) + { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + val_print(AVS_PRINT_ERR, "\n Interrupt ID is reserved for future SBSA usage ", 0); + return; + } + + /* Check non-secure virtual timer interrupt */ + intid = val_timer_get_info(TIMER_INFO_VIR_EL1_INTID, 0); + if (IS_PPI_RESERVED(intid)) + { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + val_print(AVS_PRINT_ERR, "\n Interrupt ID is reserved for future SBSA usage ", 0); + return; + } + + /* Check for EL2 virtual timer interrupt */ + intid = val_timer_get_info(TIMER_INFO_VIR_EL2_INTID, 0); + if (IS_PPI_RESERVED(intid)) + { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03)); + val_print(AVS_PRINT_ERR, "\n Interrupt ID is reserved for future SBSA usage ", 0); + return; + } + + /* Check non-secure EL2 physical timer interrupt */ + intid = val_timer_get_info(TIMER_INFO_PHY_EL2_INTID, 0); + if (IS_PPI_RESERVED(intid)) + { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 04)); + val_print(AVS_PRINT_ERR, "\n Interrupt ID is reserved for future SBSA usage ", 0); + return; + } + + /* Check GIC maintenance interrupt */ + intid = val_pe_get_gmain_gsiv(index); + if (IS_PPI_RESERVED(intid)) + { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 05)); + val_print(AVS_PRINT_ERR, "\n Interrupt ID is reserved for future SBSA usage ", 0); + return; + } + + /* Check Performance monitor interrupt */ + intid = val_pe_get_pmu_gsiv(index); + if (IS_PPI_RESERVED(intid)) + { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 06)); + val_print(AVS_PRINT_ERR, "\n Interrupt ID is reserved for future SBSA usage ", 0); + return; + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + +} + +uint32_t +g002_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This GIC test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/gic/test_g002.c b/test_pool/gic/test_g002.c deleted file mode 100644 index 76d5189a..00000000 --- a/test_pool/gic/test_g002.c +++ /dev/null @@ -1,74 +0,0 @@ -/** @file - * Copyright (c) 2016-2018,2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/val_interface.h" - -#include "val/include/sbsa_avs_gic.h" -#include "val/include/sbsa_avs_pcie.h" - -#define TEST_NUM (AVS_GIC_TEST_NUM_BASE + 2) -#define TEST_DESC "If PCIe, then GIC implements ITS " - -static -void -payload(void) -{ - - uint32_t data; - uint32_t num_ecam = 0; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - num_ecam = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); - - if (num_ecam != 0) { - data = val_gic_get_info(GIC_INFO_VERSION); - if (data < 2) { - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); - return; - } - - data = val_gic_get_info(GIC_INFO_NUM_ITS); - - if (data == 0) { - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - return; - } - } - //If PCIe is not present, just Pass the test - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); -} - -uint32_t -g002_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL; - - num_pe = 1; //This GIC test is run on single processor - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} diff --git a/test_pool/gic/test_g003.c b/test_pool/gic/test_g003.c deleted file mode 100644 index 9ec07625..00000000 --- a/test_pool/gic/test_g003.c +++ /dev/null @@ -1,68 +0,0 @@ -/** @file - * Copyright (c) 2016-2018,2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/val_interface.h" - -#include "val/include/sbsa_avs_gic.h" - -#define TEST_NUM (AVS_GIC_TEST_NUM_BASE + 3) -#define TEST_DESC "GIC number of Security states(2) " - -static -void -payload(void) -{ - - uint32_t data; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - data = val_gic_get_info(GIC_INFO_VERSION); - if (data < 3) { - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 1)); - return; - } - - data = val_gic_get_info(GIC_INFO_SEC_STATES); - - if (data != 0) { - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 1)); - return; - } - - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 1)); -} - -uint32_t -g003_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL; - - num_pe = 1; //This GIC test is run on single processor - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} diff --git a/test_pool/gic/test_g004.c b/test_pool/gic/test_g004.c deleted file mode 100644 index 890e4d71..00000000 --- a/test_pool/gic/test_g004.c +++ /dev/null @@ -1,98 +0,0 @@ -/** @file - * Copyright (c) 2016-2018,2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/sbsa_avs_common.h" -#include "val/include/val_interface.h" - -#include "val/include/sbsa_avs_gic.h" -#include "val/include/sbsa_avs_gic_support.h" - -#define TEST_NUM (AVS_GIC_TEST_NUM_BASE + 4) -#define TEST_DESC "GIC Maintenance Interrupt " - -static uint32_t int_id = 25; - -static -void -isr(void) -{ - uint32_t data; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - /* We received our interrupt, so disable Maintenance interrupt from generating further interrupts */ - data = val_gic_reg_read(ICH_HCR_EL2); - data &= ~0x7; - val_gic_reg_write(ICH_HCR_EL2, data); - - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - val_print(AVS_PRINT_INFO, "\n Received GIC maintenance interrupt ", 0); - val_gic_end_of_interrupt(int_id); - - return; -} - -static -void -payload(void) -{ - - uint32_t data; - uint32_t timeout = 0x100000; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - data = val_gic_get_info(GIC_INFO_VERSION); - if (data < 3) { - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); - return; - } - - val_gic_install_isr(int_id, isr); - - // Write to GIC registers which will generate Maintenance interrupt - data = val_gic_reg_read(ICH_HCR_EL2); - data |= 0x7; - val_gic_reg_write(ICH_HCR_EL2, data); - - while ((--timeout > 0) && (IS_RESULT_PENDING(val_get_status(index)))); - - if(timeout == 0){ - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - return; - } - return; -} - -uint32_t -g004_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL; - - num_pe = 1; //This GIC test is run on single processor - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} diff --git a/test_pool/io_virt/test_i001.c b/test_pool/io_virt/test_i001.c deleted file mode 100644 index 387165a6..00000000 --- a/test_pool/io_virt/test_i001.c +++ /dev/null @@ -1,86 +0,0 @@ -/** @file - * Copyright (c) 2016-2018, 2020, 2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/val_interface.h" - -#include "val/include/sbsa_avs_smmu.h" - -#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 1) -#define TEST_DESC "Check 64KB Granularity support " - -static -void -payload(void) -{ - - uint64_t data; - uint32_t rev; - uint32_t num_smmu; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); - - if (num_smmu == 0) { - val_print(AVS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); - return; - } - - while (num_smmu--) - { - rev = val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu); - if (rev == 2) { - data = val_smmu_read_cfg(SMMUv2_IDR2, num_smmu); - if (!(data & BIT14)) { - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - return; - } - } - - if (rev == 3) { - data = val_smmu_read_cfg(SMMUv3_IDR5, num_smmu); - if (!(data & BIT6)) { - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - return; - } - } - } - - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - -} - -uint32_t -i001_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL; - - num_pe = 1; //This test is run on single processor - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} diff --git a/test_pool/io_virt/test_i002.c b/test_pool/io_virt/test_i002.c deleted file mode 100644 index 3187fd9e..00000000 --- a/test_pool/io_virt/test_i002.c +++ /dev/null @@ -1,79 +0,0 @@ -/** @file - * Copyright (c) 2016-2018,2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/val_interface.h" - -#include "val/include/sbsa_avs_smmu.h" - -#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 2) -#define TEST_DESC "All SMMUs have same Arch Revision " - -static -void -payload(void) -{ - - uint32_t num_smmu; - uint32_t smmuv2_flag = 0, smmuv3_flag = 0; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); - - if (num_smmu == 0) { - val_print(AVS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); - return; - } - - while (num_smmu--) - { - if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { - smmuv2_flag = 1; - } else { - smmuv3_flag = 1; - } - } - if ((smmuv2_flag) && (smmuv3_flag)) { - val_print(AVS_PRINT_ERR, "ALL SMMUs are not of the same Architecture version \n", 0); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - return; - } - - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); -} - -uint32_t -i002_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL; - - num_pe = 1; //This test is run on single processor - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} diff --git a/test_pool/io_virt/test_i004.c b/test_pool/io_virt/test_i004.c deleted file mode 100644 index 93f08580..00000000 --- a/test_pool/io_virt/test_i004.c +++ /dev/null @@ -1,88 +0,0 @@ -/** @file - * Copyright (c) 2016-2018, 2020, 2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/val_interface.h" - -#include "val/include/sbsa_avs_smmu.h" -#include "val/include/sbsa_avs_pcie.h" - -#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 4) -#define TEST_DESC "If PCIe, Check Stall model " - -static -void -payload(void) -{ - - uint64_t data; - uint32_t num_smmu; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - data = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); - - if (data == 0) { - val_print(AVS_PRINT_WARN, "\n PCIe Subsystem not discovered ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); - return; - } - - num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); - - if (num_smmu == 0) { - val_print(AVS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); - return; - } - - while (num_smmu--) { - if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { - val_print(AVS_PRINT_WARN, "\n Not valid for SMMU v2 ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); - return; - } - - data = val_smmu_read_cfg(SMMUv3_IDR0, num_smmu); - if (((data >> 24) & 0x3) == 0x2) { - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - return; - } - } - - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - -} - -uint32_t -i004_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL; - - num_pe = 1; //This test is run on single processor - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} diff --git a/test_pool/io_virt/test_i005.c b/test_pool/io_virt/test_i005.c deleted file mode 100644 index 9d20f60a..00000000 --- a/test_pool/io_virt/test_i005.c +++ /dev/null @@ -1,76 +0,0 @@ -/** @file - * Copyright (c) 2016-2018, 2020, 2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/val_interface.h" - -#include "val/include/sbsa_avs_iovirt.h" -#include "val/include/sbsa_avs_smmu.h" - -#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 5) -#define TEST_DESC "SMMUv2 unique intr per ctxt bank " - -static -void -payload(void) -{ - uint32_t num_smmu; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); - - if (num_smmu == 0) { - val_print(AVS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 3)); - return; - } - - while (num_smmu--) { - if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 3) { - val_print(AVS_PRINT_WARN, "\n Not valid for SMMU v3 ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 2)); - return; - } - - if(!val_iovirt_check_unique_ctx_intid(num_smmu)) { - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 1)); - return; - } - } - - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 0)); -} - -uint32_t -i005_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL; - - num_pe = 1; //This test is run on single processor - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} diff --git a/test_pool/io_virt/test_i006.c b/test_pool/io_virt/test_i006.c deleted file mode 100644 index 84ad1bdd..00000000 --- a/test_pool/io_virt/test_i006.c +++ /dev/null @@ -1,69 +0,0 @@ -/** @file - * Copyright (c) 2016-2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/val_interface.h" - -#include "val/include/sbsa_avs_iovirt.h" -#include "val/include/sbsa_avs_smmu.h" - -#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 6) -#define TEST_DESC "Unique stream id for each req id " - -static -void -payload(void) -{ - int num_rc; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - num_rc = val_iovirt_get_pcie_rc_info(NUM_PCIE_RC, 0); - if(!num_rc) { - val_print(AVS_PRINT_ERR, "\n No Root Complex discovered ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 3)); - return; - } - while(num_rc--) { - if(!val_iovirt_unique_rid_strid_map(num_rc)) { - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 1)); - break; - } - } - if(num_rc < 0) - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 0)); -} - - -uint32_t -i006_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL; - - num_pe = 1; //This test is run on single processor - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} diff --git a/test_pool/io_virt/test_i008.c b/test_pool/io_virt/test_i008.c deleted file mode 100644 index 982bc3c9..00000000 --- a/test_pool/io_virt/test_i008.c +++ /dev/null @@ -1,93 +0,0 @@ -/** @file - * Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/val_interface.h" - -#include "val/include/sbsa_avs_smmu.h" -#include "val/include/sbsa_avs_pcie.h" - -#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 8) -#define TEST_DESC "Check SMMU 16 Bit VMID Support " - -static -void -payload(void) -{ - - uint64_t data; - uint32_t num_smmu; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - if (g_sbsa_level < 6) { - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); - return; - } - - data = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); - - if (data == 0) { - val_print(AVS_PRINT_WARN, "\n PCIe Subsystem not discovered ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); - return; - } - - num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); - - if (num_smmu == 0) { - val_print(AVS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); - return; - } - - while (num_smmu--) { - if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { - val_print(AVS_PRINT_WARN, "\n Not valid for SMMU v2 ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 04)); - return; - } - - data = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR0, num_smmu), 18, 18); - - if (data != 1) { - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - return; - } - } - - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); -} - -uint32_t -i008_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL; - - num_pe = 1; //This test is run on single processor - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} diff --git a/test_pool/io_virt/test_i010.c b/test_pool/io_virt/test_i010.c deleted file mode 100644 index 43797626..00000000 --- a/test_pool/io_virt/test_i010.c +++ /dev/null @@ -1,135 +0,0 @@ -/** @file - * Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/val_interface.h" - -#include "val/include/sbsa_avs_smmu.h" -#include "val/include/sbsa_avs_pcie.h" -#include "val/include/sbsa_avs_pe.h" - -#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 10) -#define TEST_DESC "Check SMMU Granule Support " - -static -void -payload(void) -{ - - uint64_t data; - uint64_t data_pe_mmfr0, data_smmu_idr5; - uint32_t is_gran4k = 0; - uint32_t is_gran64k = 0; - uint32_t num_smmu; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - if (g_sbsa_level < 6) { - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); - return; - } - - data = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); - - if (data == 0) { - val_print(AVS_PRINT_WARN, "\n PCIe Subsystem not discovered ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); - return; - } - - num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); - - if (num_smmu == 0) { - val_print(AVS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); - return; - } - - data_pe_mmfr0 = val_pe_reg_read(ID_AA64MMFR0_EL1); - - while (num_smmu--) { - if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { - val_print(AVS_PRINT_WARN, "\n Not valid for SMMU v2 ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 04)); - return; - } - - data_smmu_idr5 = val_smmu_read_cfg(SMMUv3_IDR5, num_smmu); - - /* If PE Supports 4KB Gran, (TGran4 == 0) or (TGran4 == 0x1) - * or (TGran4_2 == 0x2) or (TGran4_2 == 0x3) */ - if (((VAL_EXTRACT_BITS(data_pe_mmfr0, 28, 31) == 0x0) || - (VAL_EXTRACT_BITS(data_pe_mmfr0, 28, 31) == 0x1)) || - ((VAL_EXTRACT_BITS(data_pe_mmfr0, 40, 43) == 0x2) || - (VAL_EXTRACT_BITS(data_pe_mmfr0, 40, 43) == 0x3))) { - is_gran4k = 1; - if (VAL_EXTRACT_BITS(data_smmu_idr5, 4, 4) != 1) { - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - return; - } - } - - /* If PE Supports 16KB Gran, (TGran16 == 0x1) or (TGran16 == 0x2) - * or (TGran16_2 == 0x2) or (TGran16_2 == 0x3) */ - if (((VAL_EXTRACT_BITS(data_pe_mmfr0, 20, 23) == 0x1) || - (VAL_EXTRACT_BITS(data_pe_mmfr0, 20, 23) == 0x2)) || - ((VAL_EXTRACT_BITS(data_pe_mmfr0, 32, 35) == 0x2) || - (VAL_EXTRACT_BITS(data_pe_mmfr0, 32, 35) == 0x3))) { - if (VAL_EXTRACT_BITS(data_smmu_idr5, 5, 5) != 1) { - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); - return; - } - } - - /* If PE Supports 64KB Gran, (TGran64 == 0) or (TGran64_2 == 0x2) */ - if ((VAL_EXTRACT_BITS(data_pe_mmfr0, 24, 27) == 0x0) || - (VAL_EXTRACT_BITS(data_pe_mmfr0, 36, 39) == 0x2)) { - is_gran64k = 1; - if (VAL_EXTRACT_BITS(data_smmu_idr5, 6, 6) != 1) { - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03)); - return; - } - } - - /* If 4K & 64K Granule Not Supported */ - if (!(is_gran4k && is_gran64k)) { - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 04)); - return; - } - } - - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); -} - -uint32_t -i010_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL; - - num_pe = 1; //This test is run on single processor - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} diff --git a/test_pool/io_virt/test_i011.c b/test_pool/io_virt/test_i011.c deleted file mode 100644 index e88fe85a..00000000 --- a/test_pool/io_virt/test_i011.c +++ /dev/null @@ -1,105 +0,0 @@ -/** @file - * Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/val_interface.h" - -#include "val/include/sbsa_avs_smmu.h" -#include "val/include/sbsa_avs_pcie.h" -#include "val/include/sbsa_avs_pe.h" - -#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 11) -#define TEST_DESC "Check Large Virtual Addr Support " - -static -void -payload(void) -{ - - uint64_t data; - uint64_t data_va_range, data_vax; - uint32_t num_smmu; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - if (g_sbsa_level < 6) { - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); - return; - } - - data = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); - - if (data == 0) { - val_print(AVS_PRINT_WARN, "\n PCIe Subsystem not discovered ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); - return; - } - - num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); - - if (num_smmu == 0) { - val_print(AVS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); - return; - } - - data_va_range = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR2_EL1), 16, 19); - if (data_va_range == 0) { - val_print(AVS_PRINT_WARN, "\n Large VA Not Supported by PE ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 04)); - return; - } - - while (num_smmu--) { - if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { - val_print(AVS_PRINT_WARN, "\n Not valid for SMMU v2 ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 05)); - return; - } - - data_vax = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR5, num_smmu), 10, 11); - - /* If PE Supports Large VA Range then SMMU_IDR5.VAX = 0b01 */ - if (data_va_range == 1) { - if (data_vax != 1) { - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - return; - } - } - } - - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); -} - -uint32_t -i011_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL; - - num_pe = 1; //This test is run on single processor - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} diff --git a/test_pool/io_virt/test_i012.c b/test_pool/io_virt/test_i012.c deleted file mode 100644 index 711c2d0a..00000000 --- a/test_pool/io_virt/test_i012.c +++ /dev/null @@ -1,100 +0,0 @@ -/** @file - * Copyright (c) 2020-2022, Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/val_interface.h" - -#include "val/include/sbsa_avs_smmu.h" -#include "val/include/sbsa_avs_pcie.h" -#include "val/include/sbsa_avs_pe.h" - -#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 12) -#define TEST_DESC "Check SMMU 52 Bit OAS Support " - -static -void -payload(void) -{ - - uint64_t data; - uint64_t data_pa_range, data_oas; - uint32_t num_smmu; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - data = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); - - if (data == 0) { - val_print(AVS_PRINT_WARN, "\n PCIe Subsystem not discovered ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); - return; - } - - num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); - - if (num_smmu == 0) { - val_print(AVS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); - return; - } - - data_pa_range = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR0_EL1), 0, 3); - if (data_pa_range != 0x6) { - val_print(AVS_PRINT_WARN, "\n Large PA Not Supported by PE ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 04)); - return; - } - - while (num_smmu--) { - if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { - val_print(AVS_PRINT_WARN, "\n Not valid for SMMU v2 ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 05)); - return; - } - - data_oas = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR5, num_smmu), 0, 2); - - /* If PE Supports Large PA then SMMU_IDR5.OAS = 0b110 */ - if (data_pa_range == 0x6) { - if (data_oas != 0x6) { - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - return; - } - } - } - - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); -} - -uint32_t -i012_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL; - - num_pe = 1; //This test is run on single processor - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} diff --git a/test_pool/io_virt/test_i015.c b/test_pool/io_virt/test_i015.c deleted file mode 100644 index 4fc8c5ce..00000000 --- a/test_pool/io_virt/test_i015.c +++ /dev/null @@ -1,107 +0,0 @@ -/** @file - * Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/val_interface.h" - -#include "val/include/sbsa_avs_smmu.h" -#include "val/include/sbsa_avs_pcie.h" -#include "val/include/sbsa_avs_pe.h" - -#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 15) -#define TEST_DESC "Check SMMU Endianess Support " - -static -void -payload(void) -{ - - uint64_t data; - uint64_t data_pe_endian; - uint32_t num_smmu; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - if (g_sbsa_level < 6) { - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); - return; - } - - data = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); - - if (data == 0) { - val_print(AVS_PRINT_WARN, "\n PCIe Subsystem not discovered ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); - return; - } - - num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); - - if (num_smmu == 0) { - val_print(AVS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); - return; - } - - /* Check the current endianness setting of SCTLR.EE */ - if (val_pe_reg_read(CurrentEL) == AARCH64_EL2) { - data_pe_endian = VAL_EXTRACT_BITS(val_pe_reg_read(SCTLR_EL2), 25, 25); - } else if (val_pe_reg_read(CurrentEL) == AARCH64_EL1) { - data_pe_endian = VAL_EXTRACT_BITS(val_pe_reg_read(SCTLR_EL1), 25, 25); - } - - while (num_smmu--) { - if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { - val_print(AVS_PRINT_WARN, "\n Not valid for SMMU v2 ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 04)); - return; - } - - data = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR0, num_smmu), 21, 22); - - if ((data_pe_endian == 1) && ((data == 1) || (data == 2))) { - /* If PE supports big endian */ - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - return; - } else if ((data_pe_endian == 0) && ((data == 1) || (data == 3))) { - /* If PE supports little endian */ - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); - return; - } - } - - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); -} - -uint32_t -i015_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL; - - num_pe = 1; //This test is run on single processor - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} diff --git a/test_pool/io_virt/test_i016.c b/test_pool/io_virt/test_i016.c deleted file mode 100644 index 84e124c2..00000000 --- a/test_pool/io_virt/test_i016.c +++ /dev/null @@ -1,105 +0,0 @@ -/** @file - * Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/val_interface.h" - -#include "val/include/sbsa_avs_smmu.h" -#include "val/include/sbsa_avs_pcie.h" -#include "val/include/sbsa_avs_pe.h" - -#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 16) -#define TEST_DESC "Check SMMU DVM Capability Support " - -static -void -payload(void) -{ - - uint64_t data; - uint64_t data_pe_tlb, data_ril; - uint32_t num_smmu; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - if (g_sbsa_level < 6) { - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); - return; - } - - data = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); - - if (data == 0) { - val_print(AVS_PRINT_WARN, "\n PCIe Subsystem not discovered ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); - return; - } - - num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); - - if (num_smmu == 0) { - val_print(AVS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); - return; - } - - data_pe_tlb = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR0_EL1), 56, 59); - if (data_pe_tlb != 0x2) { - val_print(AVS_PRINT_WARN, "\n TLB Range Invalid Not Supported ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 04)); - return; - } - - while (num_smmu--) { - if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { - val_print(AVS_PRINT_WARN, "\n Not valid for SMMU v2 ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 05)); - return; - } - - data_ril = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR3, num_smmu), 10, 10); - - /* If PE TLB Range Invalidation then SMMU_IDR3.RIL = 0b1 */ - if (data_pe_tlb == 0x2) { - if (data_ril != 0x1) { - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - return; - } - } - } - - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); -} - -uint32_t -i016_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL; - - num_pe = 1; //This test is run on single processor - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} diff --git a/test_pool/memory_map/operating_system/test_m001.c b/test_pool/memory_map/operating_system/test_m001.c new file mode 100644 index 00000000..670fa181 --- /dev/null +++ b/test_pool/memory_map/operating_system/test_m001.c @@ -0,0 +1,77 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_common.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_peripherals.h" +#include "val/include/sbsa_avs_memory.h" + +#define TEST_NUM (AVS_MEM_MAP_TEST_NUM_BASE + 1) +#define TEST_RULE "S_L3MM_01, S_L3MM_02" +#define TEST_DESC "Check peripherals addr 64Kb apart " + +static void payload(void) +{ + uint32_t pe_index; + uint32_t peri_index, peri_index1; + uint64_t peri_count, addr_diff; + uint64_t peri_addr1, peri_addr2; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + peri_count = val_peripheral_get_info(NUM_ALL, 0); + + /* check whether all peripheral base addresses are 64KB apart from each other */ + for (peri_index = 0 ; peri_index < peri_count; peri_index++) { + for (peri_index1 = peri_index + 1; peri_index1 < peri_count; peri_index1++) { + + peri_addr1 = val_peripheral_get_info(ANY_BASE0, peri_index); + peri_addr2 = val_peripheral_get_info(ANY_BASE0, peri_index1); + + addr_diff = (peri_addr1 > peri_addr2) ? + peri_addr1 - peri_addr2 : peri_addr2 - peri_addr1; + + if (addr_diff < MEM_SIZE_64KB) { + val_print(AVS_PRINT_ERR, + "\n Peripheral base addresses isn't atleast 64Kb apart", 0); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + } + } + + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t m001_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + /* run on single PE */ + num_pe = 1; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/nist_sts/test_n001.c b/test_pool/nist_sts/test_n001.c index d61b2f67..b0939fe3 100644 --- a/test_pool/nist_sts/test_n001.c +++ b/test_pool/nist_sts/test_n001.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020, 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -25,6 +25,7 @@ #include "val/include/sbsa_avs_nist.h" #define TEST_NUM (AVS_NIST_TEST_NUM_BASE + 1) +#define TEST_RULE "S_L7ENT_1" #define TEST_DESC "NIST Statistical Test Suite \n " #define BUFFER_SIZE 1000 @@ -261,15 +262,15 @@ n001_entry(uint32_t num_pe) num_pe = 1; //This NIST test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ -// status = val_check_for_error(TEST_NUM, num_pe); +// status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); -// val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); +// val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p001.c b/test_pool/pcie/test_p001.c index ffdbe6a8..6716a4f0 100644 --- a/test_pool/pcie/test_p001.c +++ b/test_pool/pcie/test_p001.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -21,6 +21,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 1) #define TEST_DESC "Check ECAM Presence " +#define TEST_RULE "PCI_IN_01" static void @@ -49,14 +50,14 @@ p001_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p002.c b/test_pool/pcie/test_p002.c index 9ddafb80..5fca846d 100644 --- a/test_pool/pcie/test_p002.c +++ b/test_pool/pcie/test_p002.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -22,6 +22,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 2) #define TEST_DESC "Check ECAM value in MCFG table " +#define TEST_RULE "" static void @@ -50,14 +51,14 @@ p002_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p003.c b/test_pool/pcie/test_p003.c index d47bfbf0..b311f3ae 100644 --- a/test_pool/pcie/test_p003.c +++ b/test_pool/pcie/test_p003.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2021, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -23,6 +23,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 3) #define TEST_DESC "Check ECAM Memory accessibility " +#define TEST_RULE "PCI_IN_02" static void *branch_to_test; @@ -173,14 +174,14 @@ p003_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p005.c b/test_pool/pcie/test_p005.c index fe03169c..b7c57ef4 100644 --- a/test_pool/pcie/test_p005.c +++ b/test_pool/pcie/test_p005.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2020-2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,6 +24,7 @@ /* SBSA-checklist 63 & 64 */ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 5) #define TEST_DESC "PCIe Unaligned access, Norm mem " +#define TEST_RULE "PCI_MM_01, PCI_MM_02, PCI_MM_03, RE_BAR_2" #define DATA 0xC0DECAFE @@ -246,14 +247,14 @@ p005_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p006.c b/test_pool/pcie/test_p006.c index 2e1e4d0d..a5b2e38b 100644 --- a/test_pool/pcie/test_p006.c +++ b/test_pool/pcie/test_p006.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018,2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -23,6 +23,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 6) #define TEST_DESC "No extra addr translation - SMMU " +#define TEST_RULE "PCI_MM_05, PCI_MM_06, PCI_MM_07" /* For all DMA masters populated in the Info table, which are behind an SMMU, @@ -104,14 +105,14 @@ p006_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p007.c b/test_pool/pcie/test_p007.c index ad7163a8..aade0baf 100644 --- a/test_pool/pcie/test_p007.c +++ b/test_pool/pcie/test_p007.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -21,6 +21,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 7) #define TEST_DESC "Check MSI support for PCIe device " +#define TEST_RULE "PCI_MSI_01" static void @@ -74,14 +75,14 @@ p007_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p008.c b/test_pool/pcie/test_p008.c index 109cb286..11dd74de 100644 --- a/test_pool/pcie/test_p008.c +++ b/test_pool/pcie/test_p008.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2021-2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -22,6 +22,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 8) #define TEST_DESC "Check MSI(X) vectors uniqueness " +#define TEST_RULE "" /** @brief Returns MSI(X) status of the device @@ -193,15 +194,15 @@ p008_entry (uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test (TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) { val_run_test_payload (TEST_NUM, num_pe, payload, 0); } /* get the result from all PE and check for failure */ - status = val_check_for_error (TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status (0, SBSA_AVS_END (g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p009.c b/test_pool/pcie/test_p009.c deleted file mode 100644 index 6aa712d4..00000000 --- a/test_pool/pcie/test_p009.c +++ /dev/null @@ -1,147 +0,0 @@ -/** @file - * Copyright (c) 2016-2018, 2021 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/val_interface.h" - -#include "val/include/sbsa_avs_pcie.h" -#include "val/include/sbsa_avs_memory.h" - -#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 9) -#define TEST_DESC "Check all MSI(X) vectors are LPIs " - -#define LPI_BASE 8192 - -/** - @brief Returns MSI(X) status of the device - - @param dev_index index of PCI device - - @return 0 device does not support MSI(X) - @return 1 device supports MSI(X) -**/ -static -uint32_t -check_msi_status (uint32_t dev_index) { - uint32_t data; - - data = val_peripheral_get_info (ANY_FLAGS, dev_index); - - if ((data & PER_FLAG_MSI_ENABLED) && - val_peripheral_get_info (ANY_GSIV, dev_index)) { - return 1; - } - - return 0; -} - -/** - @brief Free memory allocated for a list of MSI(X) vectors - - @param list pointer to a list of MSI(X) vectors -**/ -static -void -clean_msi_list (PERIPHERAL_VECTOR_LIST *list) -{ - PERIPHERAL_VECTOR_LIST *next_node; - PERIPHERAL_VECTOR_LIST *current_node; - - current_node = list; - while (current_node != NULL) { - next_node = current_node->next; - val_memory_free (current_node); - current_node = next_node; - } -} - -static -void -payload (void) -{ - - uint32_t count = val_peripheral_get_info (NUM_ALL, 0); - uint32_t index = val_pe_get_index_mpid (val_pe_get_mpid()); - uint8_t status; - PERIPHERAL_VECTOR_LIST *dev_mvec, *mvec; - uint64_t dev_bdf; - uint32_t test_skip = 1; - - if(!count) { - val_set_status (index, RESULT_SKIP (g_sbsa_level, TEST_NUM, 2)); - return; - } - - status = 0; - dev_mvec = NULL; - - /* - Pull each discovered PCI device and its list of MSI(X) vectors. - Check whether every vector IRQ number is an LPI or not. - */ - while (count > 0 && !status) { - if (check_msi_status (count - 1)) { - /* Get BDF of a device */ - dev_bdf = val_peripheral_get_info (ANY_BDF, count - 1); - if (dev_bdf) { - val_print (AVS_PRINT_INFO, " Checking PCI device with BDF %4X\n", dev_bdf); - /* Read MSI(X) vectors */ - if (val_get_msi_vectors (dev_bdf, &dev_mvec)) { - test_skip = 0; - mvec = dev_mvec; - while(mvec) { - if(mvec->vector.vector_irq_base < LPI_BASE) { - val_print(AVS_PRINT_INFO, " MSI vector irq %d is not an LPI\n", mvec->vector.vector_irq_base); - val_set_status (index, RESULT_FAIL (g_sbsa_level, TEST_NUM, mvec->vector.vector_irq_base)); - status = 1; - } - mvec = mvec->next; - } - clean_msi_list (dev_mvec); - } - } - } - count--; - } - - if (test_skip) { - val_print(AVS_PRINT_ERR, "\n No MSI vectors found ", 0); - val_set_status (index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 0)); - } else if (!status) { - val_set_status (index, RESULT_PASS(g_sbsa_level, TEST_NUM, 0)); - } -} - -uint32_t -p009_entry (uint32_t num_pe) -{ - uint32_t status = AVS_STATUS_FAIL; - - num_pe = 1; //This test is run on single processor - - status = val_initialize_test (TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - if (status != AVS_STATUS_SKIP) { - val_run_test_payload (TEST_NUM, num_pe, payload, 0); - } - - /* get the result from all PE and check for failure */ - status = val_check_for_error (TEST_NUM, num_pe); - - val_report_status (0, SBSA_AVS_END (g_sbsa_level, TEST_NUM)); - - return status; -} diff --git a/test_pool/pcie/test_p010.c b/test_pool/pcie/test_p010.c index 709a925c..930feb16 100644 --- a/test_pool/pcie/test_p010.c +++ b/test_pool/pcie/test_p010.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2019, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -23,6 +23,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 10) #define TEST_DESC "PASID support atleast 16 bits " +#define TEST_RULE "PCI_PAS_1" #define MIN_PASID_SUPPORT 16 @@ -85,14 +86,14 @@ p010_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p011.c b/test_pool/pcie/test_p011.c index f188932b..446fa457 100644 --- a/test_pool/pcie/test_p011.c +++ b/test_pool/pcie/test_p011.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018,2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -23,6 +23,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 11) #define TEST_DESC "PCIe RC & PE, Same Inner SH Domain" +#define TEST_RULE "PCI_IC_02" #define INNER_SHAREABLE 1 @@ -64,14 +65,14 @@ p011_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p012.c b/test_pool/pcie/test_p012.c index 291f32a9..e991cdcc 100644 --- a/test_pool/pcie/test_p012.c +++ b/test_pool/pcie/test_p012.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018,2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -22,6 +22,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 12) #define TEST_DESC "PCI legacy interrupt SPI ID unique" +#define TEST_RULE "PCI_LI_02" static inline char pin_name(int pin) { @@ -155,15 +156,15 @@ p012_entry (uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test (TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) { val_run_test_payload (TEST_NUM, num_pe, payload, 0); } /* get the result from all PE and check for failure */ - status = val_check_for_error (TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status (0, SBSA_AVS_END (g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p013.c b/test_pool/pcie/test_p013.c index d7fcec32..657ebf70 100644 --- a/test_pool/pcie/test_p013.c +++ b/test_pool/pcie/test_p013.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -21,6 +21,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 13) #define TEST_DESC "Addressability of Non-Sec masters " +#define TEST_RULE "B_MEM_03, B_MEM_04, B_MEM_06" #define BAR_64BIT_SUPPORT 0x2 #define ADDR_TYPE_MASK 0x6 @@ -92,15 +93,15 @@ p013_entry (uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test (TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) { val_run_test_payload (TEST_NUM, num_pe, payload, 0); } /* get the result from all PE and check for failure */ - status = val_check_for_error (TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status (0, SBSA_AVS_END (g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p014.c b/test_pool/pcie/test_p014.c index b0acae0d..8e2a9930 100644 --- a/test_pool/pcie/test_p014.c +++ b/test_pool/pcie/test_p014.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2021-2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2021-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -23,6 +23,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 14) #define TEST_DESC "Memory attributes of DMA traffic " +#define TEST_RULE "B_PER_09, B_PER_10" /* For all DMA masters populated in the Info table, which are behind an SMMU, @@ -102,14 +103,14 @@ p014_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p015.c b/test_pool/pcie/test_p015.c index af14ee8a..355276cb 100644 --- a/test_pool/pcie/test_p015.c +++ b/test_pool/pcie/test_p015.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -21,6 +21,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 15) #define TEST_DESC "PCIe No Snoop transaction attr " +#define TEST_RULE "" static void @@ -84,15 +85,15 @@ p015_entry (uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test (TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) { val_run_test_payload (TEST_NUM, num_pe, payload, 0); } /* get the result from all PE and check for failure */ - status = val_check_for_error (TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status (0, SBSA_AVS_END (g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p016.c b/test_pool/pcie/test_p016.c index 9b3e3bde..7dad0f2a 100644 --- a/test_pool/pcie/test_p016.c +++ b/test_pool/pcie/test_p016.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018,2021-2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2021-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -21,6 +21,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 16) #define TEST_DESC "NP type-1 pcie only support 32-bit" +#define TEST_RULE "PCI_MM_04" #define BAR0 0x10 @@ -99,13 +100,13 @@ uint32_t p016_entry(uint32_t num_pe) /* This test is run on single processor */ num_pe = 1; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p017.c b/test_pool/pcie/test_p017.c index 20662734..94d97022 100644 --- a/test_pool/pcie/test_p017.c +++ b/test_pool/pcie/test_p017.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2018-2021, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2018-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -21,6 +21,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 17) #define TEST_DESC "Root port must implement minimal ACS features if P2P supported" +#define TEST_RULE "PCI_PP_04" static void payload(void) { @@ -110,13 +111,13 @@ uint32_t p017_entry(uint32_t num_pe) /* This test is run on single processor */ num_pe = 1; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p018.c b/test_pool/pcie/test_p018.c index c7c555f3..fb2f1a02 100644 --- a/test_pool/pcie/test_p018.c +++ b/test_pool/pcie/test_p018.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2018-2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2018-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -21,6 +21,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 18) #define TEST_DESC "All switches must implement minimal ACS features if P2P supported" +#define TEST_RULE "" static void payload(void) { @@ -115,13 +116,13 @@ uint32_t p018_entry(uint32_t num_pe) /* This test is run on single processor */ num_pe = 1; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p019.c b/test_pool/pcie/test_p019.c index ac0e4fe2..715e701a 100644 --- a/test_pool/pcie/test_p019.c +++ b/test_pool/pcie/test_p019.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2018-2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2018-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -21,6 +21,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 19) #define TEST_DESC "Multifunction devices must implement minimal ACS features if P2P supported" +#define TEST_RULE "" static void payload(void) { @@ -109,13 +110,13 @@ uint32_t p019_entry(uint32_t num_pe) /* This test is run on single processor */ num_pe = 1; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p020.c b/test_pool/pcie/test_p020.c index 7662bb61..c861d0d9 100644 --- a/test_pool/pcie/test_p020.c +++ b/test_pool/pcie/test_p020.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -22,6 +22,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 20) #define TEST_DESC "Check Type 0/1 common config rules" +#define TEST_RULE "RE_REG_1, RE_REC_1, RE_REC_2" static void @@ -54,14 +55,14 @@ p020_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p021.c b/test_pool/pcie/test_p021.c index 39ff953b..0de30bfc 100644 --- a/test_pool/pcie/test_p021.c +++ b/test_pool/pcie/test_p021.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -22,6 +22,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 21) #define TEST_DESC "Check Type 0 config header rules " +#define TEST_RULE "RE_REG_1, RE_REC_1, RE_REC_2" static void @@ -54,14 +55,14 @@ p021_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p022.c b/test_pool/pcie/test_p022.c index 81af76a6..0540107c 100644 --- a/test_pool/pcie/test_p022.c +++ b/test_pool/pcie/test_p022.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -22,6 +22,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 22) #define TEST_DESC "Check Type 1 config header rules " +#define TEST_RULE "RE_REC_1, RE_REC_2" static void @@ -54,14 +55,14 @@ p022_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p023.c b/test_pool/pcie/test_p023.c index c4d13384..fc8ccc26 100644 --- a/test_pool/pcie/test_p023.c +++ b/test_pool/pcie/test_p023.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -22,6 +22,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 23) #define TEST_DESC "Check PCIe capability rules " +#define TEST_RULE "RE_REG_3, RE_REC_1, RE_REC_2" static void @@ -54,14 +55,14 @@ p023_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p024.c b/test_pool/pcie/test_p024.c index 3a40420c..dba62c90 100644 --- a/test_pool/pcie/test_p024.c +++ b/test_pool/pcie/test_p024.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -22,6 +22,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 24) #define TEST_DESC "Check Device capabilites reg rules" +#define TEST_RULE "RE_REG_3, RE_REC_1, RE_REC_2" static void @@ -54,14 +55,14 @@ p024_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p025.c b/test_pool/pcie/test_p025.c index 663baefd..f7e2876e 100644 --- a/test_pool/pcie/test_p025.c +++ b/test_pool/pcie/test_p025.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -22,6 +22,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 25) #define TEST_DESC "Check Device Control register rule" +#define TEST_RULE "RE_REG_3, RE_REC_1, RE_REC_2" static void @@ -54,14 +55,14 @@ p025_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p026.c b/test_pool/pcie/test_p026.c index 858d2722..3964885a 100644 --- a/test_pool/pcie/test_p026.c +++ b/test_pool/pcie/test_p026.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -22,6 +22,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 26) #define TEST_DESC "Check Device cap 2 register rules " +#define TEST_RULE "RE_REG_3, RE_REC_1, RE_REC_2" static void @@ -54,14 +55,14 @@ p026_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p027.c b/test_pool/pcie/test_p027.c index 0004be71..abcbf5ba 100644 --- a/test_pool/pcie/test_p027.c +++ b/test_pool/pcie/test_p027.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -22,6 +22,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 27) #define TEST_DESC "Check Device control 2 reg rules " +#define TEST_RULE "RE_REG_3, RE_REC_1, RE_REC_2" static void @@ -54,14 +55,14 @@ p027_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p028.c b/test_pool/pcie/test_p028.c index b53b1f4a..81a3c52f 100644 --- a/test_pool/pcie/test_p028.c +++ b/test_pool/pcie/test_p028.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -22,6 +22,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 28) #define TEST_DESC "Check Power management cap rules " +#define TEST_RULE "RE_REG_2, RE_REC_1, RE_REC_2" static void @@ -54,14 +55,14 @@ p028_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p029.c b/test_pool/pcie/test_p029.c index e6b09c9b..90f70603 100644 --- a/test_pool/pcie/test_p029.c +++ b/test_pool/pcie/test_p029.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -22,6 +22,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 29) #define TEST_DESC "Check Power management/status rule" +#define TEST_RULE "RE_REG_2, RE_REC_1, RE_REC_2" static void @@ -54,14 +55,14 @@ p029_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p030.c b/test_pool/pcie/test_p030.c index b8eec745..917e81cc 100644 --- a/test_pool/pcie/test_p030.c +++ b/test_pool/pcie/test_p030.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2019-2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -23,6 +23,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 30) #define TEST_DESC "Check Cmd Reg memory space enable " +#define TEST_RULE "RE_REC_1, RE_REC_2" static void *branch_to_test; @@ -168,14 +169,14 @@ p030_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p031.c b/test_pool/pcie/test_p031.c index eb58a4e4..8b9f174d 100644 --- a/test_pool/pcie/test_p031.c +++ b/test_pool/pcie/test_p031.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -23,6 +23,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 31) #define TEST_DESC "Check Type0/1 BIST Register rule " +#define TEST_RULE "RE_REC_1, RE_REC_2" static void @@ -85,14 +86,14 @@ p031_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p032.c b/test_pool/pcie/test_p032.c index 96007626..5860d10d 100644 --- a/test_pool/pcie/test_p032.c +++ b/test_pool/pcie/test_p032.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -23,6 +23,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 32) #define TEST_DESC "Check HDR CapPtr Register rule " +#define TEST_RULE "RE_REC_1, RE_REC_2" static void @@ -82,14 +83,14 @@ p032_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p033.c b/test_pool/pcie/test_p033.c index 28955f13..76416427 100644 --- a/test_pool/pcie/test_p033.c +++ b/test_pool/pcie/test_p033.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -23,6 +23,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 33) #define TEST_DESC "Check Max payload size supported " +#define TEST_RULE "RE_REC_1, RE_REC_2" static void @@ -86,14 +87,14 @@ p033_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p034.c b/test_pool/pcie/test_p034.c index 43d9ac14..4843701f 100644 --- a/test_pool/pcie/test_p034.c +++ b/test_pool/pcie/test_p034.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2019, 2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019, 2021-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -23,6 +23,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 34) #define TEST_DESC "Check BAR memory space & Type rule" +#define TEST_RULE "RE_BAR_3" static void @@ -122,14 +123,14 @@ p034_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p035.c b/test_pool/pcie/test_p035.c index 49d5cee2..290cd062 100644 --- a/test_pool/pcie/test_p035.c +++ b/test_pool/pcie/test_p035.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2019-2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,6 +24,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 35) #define TEST_DESC "Check Function level reset rule " +#define TEST_RULE "RE_RST_1, PCI_SM_02" static uint32_t is_flr_failed(uint32_t bdf) @@ -186,14 +187,14 @@ p035_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p036.c b/test_pool/pcie/test_p036.c index 8f036f76..6e94464b 100644 --- a/test_pool/pcie/test_p036.c +++ b/test_pool/pcie/test_p036.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2019, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,6 +24,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 36) #define TEST_DESC "Check ARI forwarding support rule " +#define TEST_RULE "PCI_IN_17" static void @@ -95,14 +96,14 @@ p036_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p037.c b/test_pool/pcie/test_p037.c index 27d31c1a..d75d5943 100644 --- a/test_pool/pcie/test_p037.c +++ b/test_pool/pcie/test_p037.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2019, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,6 +24,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 37) #define TEST_DESC "Check OBFF supported rule " +#define TEST_RULE "RE_REG_3, RE_REC_1, RE_REC_2" static void @@ -101,14 +102,14 @@ p037_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p038.c b/test_pool/pcie/test_p038.c index ec070c24..9357124a 100644 --- a/test_pool/pcie/test_p038.c +++ b/test_pool/pcie/test_p038.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2019, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,6 +24,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 38) #define TEST_DESC "Check CTRS and CTDS rule " +#define TEST_RULE "RE_REG_3, RE_REC_1, RE_REC_2" static void @@ -109,14 +110,14 @@ p038_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p039.c b/test_pool/pcie/test_p039.c index 58438ee8..c8023dca 100644 --- a/test_pool/pcie/test_p039.c +++ b/test_pool/pcie/test_p039.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,6 +24,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 39) #define TEST_DESC "Check i-EP atomicop rule " +#define TEST_RULE "RE_REG_3, RE_REC_1, RE_REC_2" static void @@ -116,14 +117,14 @@ p039_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p040.c b/test_pool/pcie/test_p040.c index 6c30d706..b9429c01 100644 --- a/test_pool/pcie/test_p040.c +++ b/test_pool/pcie/test_p040.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,6 +24,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 40) #define TEST_DESC "Check Rootport ATS and PRI rule " +#define TEST_RULE "IE_SMU_1, IE_SMU_2" static void @@ -82,14 +83,14 @@ p040_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p041.c b/test_pool/pcie/test_p041.c index 804d28c7..eb6443b7 100644 --- a/test_pool/pcie/test_p041.c +++ b/test_pool/pcie/test_p041.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,6 +24,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 41) #define TEST_DESC "Check MSI and MSI-X support rule " +#define TEST_RULE "RE_INT_1, IE_INT_1" static void @@ -97,14 +98,14 @@ p041_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p042.c b/test_pool/pcie/test_p042.c index 62f1a369..bf736672 100644 --- a/test_pool/pcie/test_p042.c +++ b/test_pool/pcie/test_p042.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,6 +24,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 42) #define TEST_DESC "Check Power Management rules " +#define TEST_RULE "RE_PWR_1" static void @@ -78,14 +79,14 @@ p042_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p043.c b/test_pool/pcie/test_p043.c index 8b4c0d76..2d2e6dca 100644 --- a/test_pool/pcie/test_p043.c +++ b/test_pool/pcie/test_p043.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020-2021, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -25,6 +25,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 43) #define TEST_DESC "Check ARI forwarding enable rule " +#define TEST_RULE "PCI_IN_17" static void @@ -124,14 +125,14 @@ p043_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p044.c b/test_pool/pcie/test_p044.c index 61198029..45c14bfc 100644 --- a/test_pool/pcie/test_p044.c +++ b/test_pool/pcie/test_p044.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -23,6 +23,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 44) #define TEST_DESC "Check device under RP in same ECAM" +#define TEST_RULE "PCI_IN_04" static uint8_t func_ecam_is_rp_ecam(uint32_t dsf_bdf) @@ -139,14 +140,14 @@ p044_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p045.c b/test_pool/pcie/test_p045.c index 9fcfa9c7..410cc88e 100644 --- a/test_pool/pcie/test_p045.c +++ b/test_pool/pcie/test_p045.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,6 +24,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 45) #define TEST_DESC "Check all RP in HB is in same ECAM" +#define TEST_RULE "PCI_IN_03" static @@ -110,14 +111,14 @@ p045_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p046.c b/test_pool/pcie/test_p046.c index 5c7324d8..ca813683 100644 --- a/test_pool/pcie/test_p046.c +++ b/test_pool/pcie/test_p046.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -23,6 +23,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 46) #define TEST_DESC "Check RP Byte Enable Rules " +#define TEST_RULE "PCI_IN_18" static void @@ -146,14 +147,14 @@ p046_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p047.c b/test_pool/pcie/test_p047.c index 0fde1636..ebb9ec05 100644 --- a/test_pool/pcie/test_p047.c +++ b/test_pool/pcie/test_p047.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -23,6 +23,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 47) #define TEST_DESC "Check Config Txn for RP in HB " +#define TEST_RULE "PCI_IN_12" static void @@ -101,14 +102,14 @@ p047_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p048.c b/test_pool/pcie/test_p048.c index 3f3effe1..73d382bf 100644 --- a/test_pool/pcie/test_p048.c +++ b/test_pool/pcie/test_p048.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020-2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -23,6 +23,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 48) #define TEST_DESC "Check RootPort NP Memory Access " +#define TEST_RULE "PCI_IN_13" #define KNOWN_DATA 0xABABABAB @@ -183,7 +184,7 @@ payload(void) * Write known value to an address which is in range * Base + offset should always be in the range. * Read the same - */ + */ old_value = (*(volatile uint32_t *)(mem_base + mem_offset)); *(volatile uint32_t *)(mem_base + mem_offset) = KNOWN_DATA; @@ -265,14 +266,14 @@ p048_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p049.c b/test_pool/pcie/test_p049.c index 639bfe5c..859df040 100644 --- a/test_pool/pcie/test_p049.c +++ b/test_pool/pcie/test_p049.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -23,6 +23,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 49) #define TEST_DESC "Check RootPort P Memory Access " +#define TEST_RULE "PCI_IN_13" #define KNOWN_DATA 0xABABABAB @@ -296,14 +297,14 @@ p049_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p050.c b/test_pool/pcie/test_p050.c index 1ed9a208..6e284069 100644 --- a/test_pool/pcie/test_p050.c +++ b/test_pool/pcie/test_p050.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,6 +24,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 50) #define TEST_DESC "Check L-Intr SPI Level-Sensitive " +#define TEST_RULE "PCI_LI_01, PCI_LI_03" static void @@ -109,14 +110,14 @@ p050_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p051.c b/test_pool/pcie/test_p051.c index c3da5707..25187c46 100644 --- a/test_pool/pcie/test_p051.c +++ b/test_pool/pcie/test_p051.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020-2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,6 +24,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 51) #define TEST_DESC "Check Sec Bus Reset For iEP_RP " +#define TEST_RULE "IE_RST_2" static uint32_t @@ -235,14 +236,14 @@ p051_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p052.c b/test_pool/pcie/test_p052.c index 7a73fd07..a1e6c851 100644 --- a/test_pool/pcie/test_p052.c +++ b/test_pool/pcie/test_p052.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,6 +24,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 52) #define TEST_DESC "Check ATS Support Rule " +#define TEST_RULE "RE_SMU_2" static void @@ -91,14 +92,14 @@ p052_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p053.c b/test_pool/pcie/test_p053.c index 70e3400d..cd026a1b 100644 --- a/test_pool/pcie/test_p053.c +++ b/test_pool/pcie/test_p053.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020-2021, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,6 +24,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 53) #define TEST_DESC "Check RootPort P2P Support " +#define TEST_RULE "PCI_PP_04" static void @@ -136,14 +137,14 @@ p053_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p054.c b/test_pool/pcie/test_p054.c index d87938e3..41a73d06 100644 --- a/test_pool/pcie/test_p054.c +++ b/test_pool/pcie/test_p054.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020-2021, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,6 +24,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 54) #define TEST_DESC "Check RP Adv Error Report Support " +#define TEST_RULE "PCI_PP_04" static void @@ -100,14 +101,14 @@ p054_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p055.c b/test_pool/pcie/test_p055.c index faea79fe..07f0e601 100644 --- a/test_pool/pcie/test_p055.c +++ b/test_pool/pcie/test_p055.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,6 +24,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 55) #define TEST_DESC "Check Direct Translated P2P Supp " +#define TEST_RULE "PCI_PP_05" static void @@ -102,14 +103,14 @@ p055_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p056.c b/test_pool/pcie/test_p056.c index 566f18fe..f93175b4 100644 --- a/test_pool/pcie/test_p056.c +++ b/test_pool/pcie/test_p056.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020-2021, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,6 +24,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 56) #define TEST_DESC "Check iEP-RootPort P2P Support " +#define TEST_RULE "" static void @@ -157,14 +158,14 @@ p056_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p057.c b/test_pool/pcie/test_p057.c index d5f29b8b..fbfc0fff 100644 --- a/test_pool/pcie/test_p057.c +++ b/test_pool/pcie/test_p057.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -23,6 +23,7 @@ #include "val/include/sbsa_avs_memory.h" #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 57) +#define TEST_RULE "" #define TEST_DESC "Check RCiEP, iEP_EP P2P Supp " static @@ -39,7 +40,7 @@ payload(void) uint32_t test_skip = 1; uint32_t acs_data; uint32_t data; - uint8_t p2p_support_flag=0; + uint8_t p2p_support_flag = 0; pcie_device_bdf_table *bdf_tbl_ptr; pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); @@ -57,7 +58,7 @@ payload(void) if ((dp_type == RCiEP) || (dp_type == iEP_EP)) { /* Check if the EP Supports Multifunction */ - if(val_pcie_multifunction_support(bdf)) + if (val_pcie_multifunction_support(bdf)) continue; /* Check If Endpoint supports P2P with other Functions. */ @@ -118,14 +119,12 @@ p057_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p058.c b/test_pool/pcie/test_p058.c index 9c3475f5..75ac9a2a 100644 --- a/test_pool/pcie/test_p058.c +++ b/test_pool/pcie/test_p058.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -22,7 +22,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 58) #define TEST_RULE "RE_BAR_1" -#define TEST_DESC "Read and write to RCiEP BAR reg " +#define TEST_DESC "Read and write to RCiEP BAR reg " #define TEST_DATA_1 0xDEADDAED #define TEST_DATA_2 0xABABABAB @@ -153,14 +153,14 @@ p058_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from the PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p059.c b/test_pool/pcie/test_p059.c index e27a880a..ffbaf1ff 100644 --- a/test_pool/pcie/test_p059.c +++ b/test_pool/pcie/test_p059.c @@ -92,14 +92,14 @@ p059_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pcie/test_p060.c b/test_pool/pcie/test_p060.c index 798cd5d0..a06be830 100644 --- a/test_pool/pcie/test_p060.c +++ b/test_pool/pcie/test_p060.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2021, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -23,7 +23,7 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 60) #define TEST_RULE "RE_PCI_1" -#define TEST_DESC "Check RCiEP Hdr type & link Cap " +#define TEST_DESC "Check RCiEP Hdr type & link Cap " static void @@ -89,14 +89,14 @@ p060_entry(uint32_t num_pe) num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from the PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pe/test_c004.c b/test_pool/pe/operating_system/test_c001.c similarity index 90% rename from test_pool/pe/test_c004.c rename to test_pool/pe/operating_system/test_c001.c index 0e346001..4cd75470 100644 --- a/test_pool/pe/test_c004.c +++ b/test_pool/pe/operating_system/test_c001.c @@ -18,7 +18,8 @@ #include "val/include/sbsa_avs_val.h" #include "val/include/sbsa_avs_pe.h" -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 04) +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 01) +#define TEST_RULE "S_L3PE_01" #define TEST_DESC "Check PE Granule Support " static @@ -59,19 +60,19 @@ payload(void) } uint32_t -c004_entry(uint32_t num_pe) +c001_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pe/test_c003.c b/test_pool/pe/operating_system/test_c002.c similarity index 85% rename from test_pool/pe/test_c003.c rename to test_pool/pe/operating_system/test_c002.c index da8cf328..3f29f05d 100644 --- a/test_pool/pe/test_c003.c +++ b/test_pool/pe/operating_system/test_c002.c @@ -18,7 +18,8 @@ #include "val/include/sbsa_avs_val.h" #include "val/include/sbsa_avs_pe.h" -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 03) +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 02) +#define TEST_RULE "S_L3PE_02" #define TEST_DESC "Check for 16-bit ASID support " static @@ -43,19 +44,19 @@ payload(void) @brief Read System register to verify 16-bit ASID support **/ uint32_t -c003_entry(uint32_t num_pe) +c002_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pe/test_c010.c b/test_pool/pe/operating_system/test_c003.c similarity index 74% rename from test_pool/pe/test_c010.c rename to test_pool/pe/operating_system/test_c003.c index 81e4dcca..4ab7c56e 100644 --- a/test_pool/pe/test_c010.c +++ b/test_pool/pe/operating_system/test_c003.c @@ -18,7 +18,8 @@ #include "val/include/sbsa_avs_val.h" #include "val/include/sbsa_avs_pe.h" -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 10) +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 3) +#define TEST_RULE "S_L3PE_03" #define TEST_DESC "Check AARCH64 implementation " static @@ -30,29 +31,30 @@ payload(void) data = val_pe_reg_read(ID_AA64PFR0_EL1); - if ((data & 0x3) && (data & 0x30) && (data & 0x300) && (data & 0x3000)) //bits 1:0, 5:4, 9:8 and 13:12 must not be zero - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + /* bits 1:0, 5:4, 9:8 and 13:12 must not be zero */ + if ((data & 0x3) && (data & 0x30) && (data & 0x300) && (data & 0x3000)) + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); else - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); return; } uint32_t -c010_entry(uint32_t num_pe) +c003_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pe/operating_system/test_c004.c b/test_pool/pe/operating_system/test_c004.c new file mode 100644 index 00000000..c1d44cb0 --- /dev/null +++ b/test_pool/pe/operating_system/test_c004.c @@ -0,0 +1,83 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/val_interface.h" +#include "val/include/sbsa_avs_peripherals.h" + +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 4) +#define TEST_RULE "S_L3PE_04" +#define TEST_DESC "Check FEAT_LPA Requirements " + +#define FEAT_LPA_IMPL 0x6 +/* Retuns true if addr is greater than 48 bits */ +#define IS_ADDR_EXCEEDS_48BITS(addr) (addr & (0xfULL << 48)) + +static void payload(void) +{ + uint64_t data = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + uint64_t peri_count; + uint64_t peri_base; + + /* ID_AA64MMFR0_EL1.PARange [3:0] = 0b0110 indicates FEAT_LPA is implemented */ + data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR0_EL1), 0, 3); + peri_count = val_peripheral_get_info(NUM_ALL, 0); + + if (data == FEAT_LPA_IMPL) + { + /* If the PE implements FEAT_LPA Index through Peripheral info table and + get base addresses */ + while (peri_count) + { + peri_base = val_peripheral_get_info(ANY_BASE0, peri_count - 1); + + /* If the base address is greater than 48 bits it is outside 256TB memory map */ + if (IS_ADDR_EXCEEDS_48BITS(peri_base)) + { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + peri_count--; + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + } + else + { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + } +} + +uint32_t c004_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, + TEST_RULE); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/pe/test_c019.c b/test_pool/pe/operating_system/test_c005.c similarity index 86% rename from test_pool/pe/test_c019.c rename to test_pool/pe/operating_system/test_c005.c index 52130102..f0f227d2 100644 --- a/test_pool/pe/test_c019.c +++ b/test_pool/pe/operating_system/test_c005.c @@ -19,7 +19,8 @@ #include "val/include/sbsa_avs_pe.h" #include "val/include/val_interface.h" -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 19) +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 5) +#define TEST_RULE "S_L4PE_01" #define TEST_DESC "Check for RAS extension " static @@ -42,21 +43,21 @@ void payload(void) val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); } -uint32_t c019_entry(uint32_t num_pe) +uint32_t c005_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); /* This check is when user is forcing us to skip this test */ if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pe/operating_system/test_c006.c b/test_pool/pe/operating_system/test_c006.c new file mode 100644 index 00000000..25e9bc8a --- /dev/null +++ b/test_pool/pe/operating_system/test_c006.c @@ -0,0 +1,65 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_memory.h" + +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 6) +#define TEST_RULE "S_L4PE_02" +#define TEST_DESC "Check DC CVAP support " + +static void payload(void) +{ + uint64_t data = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 4) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + if (val_memory_check_for_persistent_mem()) { + /* ID_AA64ISAR1_EL1.DPB[3:0] = 0b0001 or 0b0010 indicate support for + DC CVAP instruction */ + data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR1_EL1), 0, 3); + if (data == 0b0001 || data == 0b0010) + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); +} + +uint32_t c006_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, + TEST_RULE); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/pe/test_c020.c b/test_pool/pe/operating_system/test_c007.c similarity index 86% rename from test_pool/pe/test_c020.c rename to test_pool/pe/operating_system/test_c007.c index e90706c6..0876ddc2 100644 --- a/test_pool/pe/test_c020.c +++ b/test_pool/pe/operating_system/test_c007.c @@ -19,7 +19,8 @@ #include "val/include/sbsa_avs_pe.h" #include "val/include/val_interface.h" -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 20) +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 7) +#define TEST_RULE "S_L4PE_03" #define TEST_DESC "Check for 16-Bit VMID " static void payload(void) @@ -41,21 +42,21 @@ static void payload(void) val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); } -uint32_t c020_entry(uint32_t num_pe) +uint32_t c007_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); /* This check is when user is forcing us to skip this test */ if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pe/test_c021.c b/test_pool/pe/operating_system/test_c008.c similarity index 86% rename from test_pool/pe/test_c021.c rename to test_pool/pe/operating_system/test_c008.c index 663d23e0..41b8b26b 100644 --- a/test_pool/pe/test_c021.c +++ b/test_pool/pe/operating_system/test_c008.c @@ -19,7 +19,8 @@ #include "val/include/sbsa_avs_pe.h" #include "val/include/val_interface.h" -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 21) +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 8) +#define TEST_RULE "S_L4PE_04" #define TEST_DESC "Check for Virtual host extensions " static void payload(void) @@ -41,21 +42,21 @@ static void payload(void) val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); } -uint32_t c021_entry(uint32_t num_pe) +uint32_t c008_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); /* This check is when user is forcing us to skip this test */ if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pe/test_c024.c b/test_pool/pe/operating_system/test_c009.c similarity index 86% rename from test_pool/pe/test_c024.c rename to test_pool/pe/operating_system/test_c009.c index 6b74fc75..7b98df3d 100644 --- a/test_pool/pe/test_c024.c +++ b/test_pool/pe/operating_system/test_c009.c @@ -18,7 +18,8 @@ #include "val/include/sbsa_avs_pe.h" #include "val/include/val_interface.h" -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 24) +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 9) +#define TEST_RULE "S_L5PE_01" #define TEST_DESC "Support Page table map size change" static void payload(void) @@ -41,18 +42,18 @@ static void payload(void) val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); } -uint32_t c024_entry(uint32_t num_pe) +uint32_t c009_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); /* This check is when user is forcing us to skip this test */ if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pe/test_c022.c b/test_pool/pe/operating_system/test_c010.c similarity index 90% rename from test_pool/pe/test_c022.c rename to test_pool/pe/operating_system/test_c010.c index d1f7efbf..613047b4 100644 --- a/test_pool/pe/test_c022.c +++ b/test_pool/pe/operating_system/test_c010.c @@ -18,7 +18,8 @@ #include "val/include/sbsa_avs_pe.h" #include "val/include/val_interface.h" -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 22) +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 10) +#define TEST_RULE "S_L5PE_02" #define TEST_DESC "Check for pointer signing " static void check_pointer_signing_algorithm(uint32_t index, uint64_t data) @@ -59,18 +60,18 @@ static void payload(void) } } -uint32_t c022_entry(uint32_t num_pe) +uint32_t c010_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); /* This check is when user is forcing us to skip this test */ if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pe/test_c026.c b/test_pool/pe/operating_system/test_c011.c similarity index 86% rename from test_pool/pe/test_c026.c rename to test_pool/pe/operating_system/test_c011.c index 862a4088..c62175a2 100644 --- a/test_pool/pe/test_c026.c +++ b/test_pool/pe/operating_system/test_c011.c @@ -19,7 +19,8 @@ #include "val/include/sbsa_avs_pe.h" #include "val/include/val_interface.h" -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 26) +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 11) +#define TEST_RULE "S_L5PE_04" #define TEST_DESC "Check Activity monitors extension " static void payload(void) @@ -40,18 +41,18 @@ static void payload(void) val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); } -uint32_t c026_entry(uint32_t num_pe) +uint32_t c011_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); /* This check is when user is forcing us to skip this test */ if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pe/test_c027.c b/test_pool/pe/operating_system/test_c012.c similarity index 88% rename from test_pool/pe/test_c027.c rename to test_pool/pe/operating_system/test_c012.c index 522fefd7..c6dfb73b 100644 --- a/test_pool/pe/test_c027.c +++ b/test_pool/pe/operating_system/test_c012.c @@ -18,7 +18,8 @@ #include "val/include/sbsa_avs_pe.h" #include "val/include/val_interface.h" -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 27) +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 12) +#define TEST_RULE "S_L5PE_05" #define TEST_DESC "Check for SHA3 and SHA512 support " static void payload(void) @@ -48,18 +49,18 @@ static void payload(void) val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); } -uint32_t c027_entry(uint32_t num_pe) +uint32_t c012_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); /* This check is when user is forcing us to skip this test */ if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pe/test_c025.c b/test_pool/pe/operating_system/test_c013.c similarity index 86% rename from test_pool/pe/test_c025.c rename to test_pool/pe/operating_system/test_c013.c index ced8c7cf..002b71e1 100644 --- a/test_pool/pe/test_c025.c +++ b/test_pool/pe/operating_system/test_c013.c @@ -18,7 +18,8 @@ #include "val/include/sbsa_avs_pe.h" #include "val/include/val_interface.h" -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 25) +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 13) +#define TEST_RULE "S_L5PE_06" #define TEST_DESC "Stage 2 control of mem and cache " static void payload(void) @@ -39,18 +40,18 @@ static void payload(void) val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); } -uint32_t c025_entry(uint32_t num_pe) +uint32_t c013_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); /* This check is when user is forcing us to skip this test */ if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pe/test_c023.c b/test_pool/pe/operating_system/test_c014.c similarity index 86% rename from test_pool/pe/test_c023.c rename to test_pool/pe/operating_system/test_c014.c index b61c85e1..e8b64f8d 100644 --- a/test_pool/pe/test_c023.c +++ b/test_pool/pe/operating_system/test_c014.c @@ -18,7 +18,8 @@ #include "val/include/sbsa_avs_pe.h" #include "val/include/val_interface.h" -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 23) +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 14) +#define TEST_RULE "S_L5PE_07" #define TEST_DESC "Check for nested virtualization " static void payload(void) @@ -39,18 +40,18 @@ static void payload(void) val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); } -uint32_t c023_entry(uint32_t num_pe) +uint32_t c014_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); /* This check is when user is forcing us to skip this test */ if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pe/operating_system/test_c015.c b/test_pool/pe/operating_system/test_c015.c new file mode 100644 index 00000000..56c82fb6 --- /dev/null +++ b/test_pool/pe/operating_system/test_c015.c @@ -0,0 +1,93 @@ +/** @file + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/val_interface.h" +#include "val/include/sbsa_avs_mpam.h" + +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 15) +#define TEST_RULE "S_MPAM_PE" +#define TEST_DESC "Check MPAM PE Requirements " + +static void payload(void) +{ + uint64_t data = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 5) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + /* Check if PEs implements FEAT_MPAM */ + /* ID_AA64PFR0_EL1.MPAM bits[43:40] > 0 or ID_AA64PFR1_EL1.MPAM_frac bits[19:16] > 0 + indicates implementation of MPAM extension */ + + if (!((VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 40, 43) > 0) || + (VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR1_EL1), 16, 19) > 0))) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + /* check support for minimum of 16 physical partition IDs, MPAMIDR_EL1.PARTID_MAX + must be >= 16 */ + data = VAL_EXTRACT_BITS(val_mpam_reg_read(MPAMIDR_EL1), 0, 15); + if (data < 16) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* check support for MPAM virtulization support indicated by MPAMIDR_EL1.HAS_HCR bit */ + data = VAL_EXTRACT_BITS(val_mpam_reg_read(MPAMIDR_EL1), 17, 17); + if (data == 0) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } + + /* check support for minimum of 8 virtual partition IDs, + MPAMIDR_EL1.VPMR_MAX must be > 0 */ + data = VAL_EXTRACT_BITS(val_mpam_reg_read(MPAMIDR_EL1), 18, 20); + if (data < 1) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03)); + return; + } + + /* Check support for minimum of 2 performance monitor groups (PMGs), + MPAMIDR_EL1.PMG_MAX must be >= 2 */ + data = VAL_EXTRACT_BITS(val_mpam_reg_read(MPAMIDR_EL1), 32, 39); + if (data < 2) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 04)); + return; + } + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t c015_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/pe/operating_system/test_c016.c b/test_pool/pe/operating_system/test_c016.c new file mode 100644 index 00000000..f5bc52e3 --- /dev/null +++ b/test_pool/pe/operating_system/test_c016.c @@ -0,0 +1,126 @@ +/** @file + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/val_interface.h" +#include "val/include/sbsa_avs_mpam.h" + +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 16) +#define TEST_RULE "S_MPAM_PE" +#define TEST_DESC "Check MPAM LLC Requirements " + +static void payload(void) +{ + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + uint32_t msc_node_cnt; + uint32_t rsrc_node_cnt; + uint32_t msc_index, rsrc_index; + uint32_t llc_index; + uint64_t cache_identifier; + uint32_t test_run = 0; + + if (g_sbsa_level < 5) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* Find the LLC cache identifier */ + llc_index = val_cache_get_llc_index(); + if (llc_index == CACHE_TABLE_EMPTY) { + val_print(AVS_PRINT_ERR, "\n PPTT table empty", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + cache_identifier = val_cache_get_info(CACHE_ID, llc_index); + + if (cache_identifier == INVALID_CACHE_INFO) { + val_print(AVS_PRINT_ERR, "\n LLC invalid in PPTT", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } + + /* Check in the MPAM table which MSC is attached to the LLC */ + msc_node_cnt = val_mpam_get_msc_count(); + val_print(AVS_PRINT_DEBUG, "\n MSC count = %d", msc_node_cnt); + + /* Check if PE implements FEAT_MPAM */ + if (!((VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 40, 43) > 0) || + (VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR1_EL1), 16, 19) > 0))) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + if (msc_node_cnt == 0) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03)); + return; + } + + /* visit each MSC node and check for cache resources */ + for (msc_index = 0; msc_index < msc_node_cnt; msc_index++) { + rsrc_node_cnt = val_mpam_get_info(MPAM_MSC_RSRC_COUNT, msc_index, 0); + + val_print(AVS_PRINT_DEBUG, "\n msc index = %d", msc_index); + val_print(AVS_PRINT_DEBUG, "\n Resource count %d = ", rsrc_node_cnt); + + for (rsrc_index = 0; rsrc_index < rsrc_node_cnt; rsrc_index++) { + + /* check whether the resource location is cache */ + if (val_mpam_get_info(MPAM_MSC_RSRC_TYPE, msc_index, rsrc_index) == + MPAM_RSRC_TYPE_PE_CACHE) { + if (val_mpam_get_info(MPAM_MSC_RSRC_DESC1, msc_index, rsrc_index) == + cache_identifier) { + /* We have MSC which controls/monitors the LLC cache */ + val_print(AVS_PRINT_DEBUG, "\n rsrc index = %d", rsrc_index); + + test_run = 1; + /* Check CPOR are present */ + if (!val_mpam_supports_cpor(msc_index)) { + val_print(AVS_PRINT_ERR, "\n CPOR unsupported by LLC", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 04)); + return; + } + } + } + } + } + + if (!test_run) { + val_print(AVS_PRINT_ERR, "\n No LLC MSC found", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 05)); + return; + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t c016_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/pe/test_c018.c b/test_pool/pe/operating_system/test_c017.c similarity index 88% rename from test_pool/pe/test_c018.c rename to test_pool/pe/operating_system/test_c017.c index 0eba2373..42e1c566 100644 --- a/test_pool/pe/test_c018.c +++ b/test_pool/pe/operating_system/test_c017.c @@ -19,7 +19,8 @@ #include "val/include/sbsa_avs_pe.h" #include "val/include/val_interface.h" -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 18) +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 17) +#define TEST_RULE "B_PE_17" #define TEST_DESC "Check SPE if implemented " static @@ -52,18 +53,18 @@ void payload(void) } -uint32_t c018_entry(uint32_t num_pe) +uint32_t c017_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); /* This check is when user is forcing us to skip this test */ if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pe/test_c033.c b/test_pool/pe/operating_system/test_c018.c similarity index 86% rename from test_pool/pe/test_c033.c rename to test_pool/pe/operating_system/test_c018.c index 3e5be7c2..c9b352c8 100644 --- a/test_pool/pe/test_c033.c +++ b/test_pool/pe/operating_system/test_c018.c @@ -19,7 +19,8 @@ #include "val/include/sbsa_avs_pe.h" #include "val/include/val_interface.h" -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 33) +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 18) +#define TEST_RULE "S_L6PE_02" #define TEST_DESC "Check Branch Target Support " static void payload(void) @@ -41,18 +42,18 @@ static void payload(void) val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); } -uint32_t c033_entry(uint32_t num_pe) +uint32_t c018_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); /* This check is when user is forcing us to skip this test */ if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pe/test_c034.c b/test_pool/pe/operating_system/test_c019.c similarity index 86% rename from test_pool/pe/test_c034.c rename to test_pool/pe/operating_system/test_c019.c index bdf6b61d..216176d4 100644 --- a/test_pool/pe/test_c034.c +++ b/test_pool/pe/operating_system/test_c019.c @@ -19,7 +19,8 @@ #include "val/include/sbsa_avs_pe.h" #include "val/include/val_interface.h" -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 34) +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 19) +#define TEST_RULE "S_L6PE_03" #define TEST_DESC "Check Protect Against Timing Fault" static void payload(void) @@ -41,18 +42,18 @@ static void payload(void) val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); } -uint32_t c034_entry(uint32_t num_pe) +uint32_t c019_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); /* This check is when user is forcing us to skip this test */ if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pe/test_c036.c b/test_pool/pe/operating_system/test_c020.c similarity index 86% rename from test_pool/pe/test_c036.c rename to test_pool/pe/operating_system/test_c020.c index 79b46c6c..bb73b586 100644 --- a/test_pool/pe/test_c036.c +++ b/test_pool/pe/operating_system/test_c020.c @@ -19,7 +19,8 @@ #include "val/include/sbsa_avs_pe.h" #include "val/include/val_interface.h" -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 36) +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 20) +#define TEST_RULE "S_L6PE_04" #define TEST_DESC "Check PMU Version Support " static void payload(void) @@ -41,18 +42,18 @@ static void payload(void) val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); } -uint32_t c036_entry(uint32_t num_pe) +uint32_t c020_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); /* This check is when user is forcing us to skip this test */ if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pe/test_c028.c b/test_pool/pe/operating_system/test_c021.c similarity index 86% rename from test_pool/pe/test_c028.c rename to test_pool/pe/operating_system/test_c021.c index 1da118fb..ac7c1e77 100644 --- a/test_pool/pe/test_c028.c +++ b/test_pool/pe/operating_system/test_c021.c @@ -19,7 +19,8 @@ #include "val/include/sbsa_avs_pe.h" #include "val/include/val_interface.h" -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 28) +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 21) +#define TEST_RULE "S_L6PE_05" #define TEST_DESC "Check AccessFlag DirtyState Update" static void payload(void) @@ -41,18 +42,18 @@ static void payload(void) val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); } -uint32_t c028_entry(uint32_t num_pe) +uint32_t c021_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); /* This check is when user is forcing us to skip this test */ if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pe/test_c035.c b/test_pool/pe/operating_system/test_c022.c similarity index 86% rename from test_pool/pe/test_c035.c rename to test_pool/pe/operating_system/test_c022.c index 8c2c31ec..4a6c30e4 100644 --- a/test_pool/pe/test_c035.c +++ b/test_pool/pe/operating_system/test_c022.c @@ -19,7 +19,8 @@ #include "val/include/sbsa_avs_pe.h" #include "val/include/val_interface.h" -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 35) +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 22) +#define TEST_RULE "S_L6PE_06" #define TEST_DESC "Check Enhanced Virtualization Trap" static void payload(void) @@ -41,18 +42,18 @@ static void payload(void) val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); } -uint32_t c035_entry(uint32_t num_pe) +uint32_t c022_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); /* This check is when user is forcing us to skip this test */ if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pe/test_c029.c b/test_pool/pe/operating_system/test_c023.c similarity index 88% rename from test_pool/pe/test_c029.c rename to test_pool/pe/operating_system/test_c023.c index 41ad8003..52bc5b6b 100644 --- a/test_pool/pe/test_c029.c +++ b/test_pool/pe/operating_system/test_c023.c @@ -19,7 +19,8 @@ #include "val/include/sbsa_avs_pe.h" #include "val/include/val_interface.h" -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 29) +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 23) +#define TEST_RULE "B_SEC_01" #define TEST_DESC "Check Speculation Restriction " static void payload(void) @@ -46,18 +47,18 @@ static void payload(void) val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); } -uint32_t c029_entry(uint32_t num_pe) +uint32_t c023_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); /* This check is when user is forcing us to skip this test */ if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pe/operating_system/test_c024.c b/test_pool/pe/operating_system/test_c024.c new file mode 100644 index 00000000..ba2204da --- /dev/null +++ b/test_pool/pe/operating_system/test_c024.c @@ -0,0 +1,59 @@ +/** @file + * Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/val_interface.h" + +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 24) +#define TEST_RULE "B_SEC_02" +#define TEST_DESC "Check Speculative Str Bypass Safe " + +static void payload(void) +{ + uint64_t data = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 6) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* Read ID_AA64PFR1_EL1.SSBS[7:4] = 0b0010 */ + data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR1_EL1), 4, 7); + + if (data != 2) + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t c024_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/pe/test_os_c018.c b/test_pool/pe/operating_system/test_c025.c similarity index 82% rename from test_pool/pe/test_os_c018.c rename to test_pool/pe/operating_system/test_c025.c index aacde8ea..1bbfdffb 100644 --- a/test_pool/pe/test_os_c018.c +++ b/test_pool/pe/operating_system/test_c025.c @@ -19,9 +19,9 @@ #include "val/include/sbsa_avs_pe.h" #include "val/include/val_interface.h" -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 40) +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 25) #define TEST_RULE "B_SEC_03" -#define TEST_DESC "Check PEs Impl CSDB,SSBB,PSSBB " +#define TEST_DESC "Check PEs Impl CSDB,SSBB,PSSBB " static void @@ -40,18 +40,18 @@ payload() } uint32_t -os_c018_entry(uint32_t num_pe) +c025_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, 6); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, 6, TEST_RULE); /* This check is when user is forcing us to skip this test */ if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - val_report_status(0, SBSA_AVS_END(6, TEST_NUM)); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(6, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pe/test_c031.c b/test_pool/pe/operating_system/test_c026.c similarity index 86% rename from test_pool/pe/test_c031.c rename to test_pool/pe/operating_system/test_c026.c index 1abf8b1c..ed167c7e 100644 --- a/test_pool/pe/test_c031.c +++ b/test_pool/pe/operating_system/test_c026.c @@ -19,7 +19,8 @@ #include "val/include/sbsa_avs_pe.h" #include "val/include/val_interface.h" -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 31) +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 26) +#define TEST_RULE "B_SEC_04" #define TEST_DESC "Check PEs Implement SB Barrier " static void payload(void) @@ -41,18 +42,18 @@ static void payload(void) val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); } -uint32_t c031_entry(uint32_t num_pe) +uint32_t c026_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); /* This check is when user is forcing us to skip this test */ if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pe/test_c032.c b/test_pool/pe/operating_system/test_c027.c similarity index 86% rename from test_pool/pe/test_c032.c rename to test_pool/pe/operating_system/test_c027.c index a5ef91e4..a3d6f2bc 100644 --- a/test_pool/pe/test_c032.c +++ b/test_pool/pe/operating_system/test_c027.c @@ -19,7 +19,8 @@ #include "val/include/sbsa_avs_pe.h" #include "val/include/val_interface.h" -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 32) +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 27) +#define TEST_RULE "B_SEC_05" #define TEST_DESC "Check PE Impl CFP,DVP,CPP RCTX " static void payload(void) @@ -41,18 +42,18 @@ static void payload(void) val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); } -uint32_t c032_entry(uint32_t num_pe) +uint32_t c027_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); /* This check is when user is forcing us to skip this test */ if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pe/operating_system/test_c028.c b/test_pool/pe/operating_system/test_c028.c new file mode 100644 index 00000000..fae8bdd7 --- /dev/null +++ b/test_pool/pe/operating_system/test_c028.c @@ -0,0 +1,59 @@ +/** @file + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/val_interface.h" + +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 28) +#define TEST_RULE "S_L7PE_01" +#define TEST_DESC "Check Fine Grain Trap Support " + +static void payload(void) +{ + uint64_t data = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 7) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* ID_AA64MMFR0_EL1.FGT[59:56] = 0b0001 indicate fine grained trap feature */ + data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR0_EL1), 56, 59); + + if (data == 1) + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t c028_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/pe/operating_system/test_c029.c b/test_pool/pe/operating_system/test_c029.c new file mode 100644 index 00000000..13fa0c5e --- /dev/null +++ b/test_pool/pe/operating_system/test_c029.c @@ -0,0 +1,59 @@ +/** @file + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/val_interface.h" + +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 29) +#define TEST_RULE "S_L7PE_02" +#define TEST_DESC "Check for ECV support " + +static void payload(void) +{ + uint64_t data = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 7) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* ID_AA64MMFR0_EL1.ECV[63:60] = 0b0010 indicate Enhanced counter vitualization */ + data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR0_EL1), 60, 63); + + if (data == 2) + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t c029_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/pe/test_c030.c b/test_pool/pe/operating_system/test_c030.c similarity index 75% rename from test_pool/pe/test_c030.c rename to test_pool/pe/operating_system/test_c030.c index 63a571b6..5c2939b7 100644 --- a/test_pool/pe/test_c030.c +++ b/test_pool/pe/operating_system/test_c030.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -20,39 +20,40 @@ #include "val/include/val_interface.h" #define TEST_NUM (AVS_PE_TEST_NUM_BASE + 30) -#define TEST_DESC "Check Speculative Str Bypass Safe " +#define TEST_RULE "S_L7PE_03" +#define TEST_DESC "Check for AMU Support " static void payload(void) { uint64_t data = 0; uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - if (g_sbsa_level < 6) { + if (g_sbsa_level < 7) { val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); return; } - /* Read ID_AA64PFR1_EL1.SSBS[7:4] = 0b0010 */ - data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR1_EL1), 4, 7); + /* ID_AA64PFR0_EL1.AMU[47:44] = 0b0010 indicate AMU Support */ + data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 44, 47); - if (data != 2) - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - else + if (data == 2) val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); } uint32_t c030_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); /* This check is when user is forcing us to skip this test */ if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/pe/operating_system/test_c031.c b/test_pool/pe/operating_system/test_c031.c new file mode 100644 index 00000000..e215ee28 --- /dev/null +++ b/test_pool/pe/operating_system/test_c031.c @@ -0,0 +1,59 @@ +/** @file + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/val_interface.h" + +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 31) +#define TEST_RULE "S_L7PE_04" +#define TEST_DESC "Checks ASIMD Int8 matrix multiplc " + +static void payload(void) +{ + uint64_t data = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 7) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* ID_AA64ISAR1_EL1.I8MM[55:52] = 0b0001 Advanced SIMD int8 matrix multiply support */ + data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR1_EL1), 52, 55); + + if (data == 1) + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t c031_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/pe/operating_system/test_c032.c b/test_pool/pe/operating_system/test_c032.c new file mode 100644 index 00000000..d68047de --- /dev/null +++ b/test_pool/pe/operating_system/test_c032.c @@ -0,0 +1,60 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/val_interface.h" + +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 32) +#define TEST_RULE "S_L7PE_05" +#define TEST_DESC "Check for BFLOAT16 extension " + +static void payload(void) +{ + uint64_t data = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 7) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* ID_AA64ISAR1_EL1.BF16[47:44] = 0b0001 indicate FEAT_BF16 support */ + data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR1_EL1), 44, 47); + + if (data == 1) + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t c032_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, + TEST_RULE); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/pe/operating_system/test_c033.c b/test_pool/pe/operating_system/test_c033.c new file mode 100644 index 00000000..1289c151 --- /dev/null +++ b/test_pool/pe/operating_system/test_c033.c @@ -0,0 +1,60 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/val_interface.h" + +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 33) +#define TEST_RULE "S_L7PE_06" +#define TEST_DESC "Check for EnhancedPAC2 and FPAC " + +static void payload(void) +{ + uint64_t data = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 7) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* ID_AA64ISAR1_EL1.APA[7:4] = 0b0101 indicate EnhancedPAC2 and FPAC support */ + data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR1_EL1), 4, 7); + + if (data == 5) + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t c033_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, + TEST_RULE); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/pe/operating_system/test_c034.c b/test_pool/pe/operating_system/test_c034.c new file mode 100644 index 00000000..dfca79ae --- /dev/null +++ b/test_pool/pe/operating_system/test_c034.c @@ -0,0 +1,68 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/val_interface.h" + +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 34) +#define TEST_RULE "S_L7PE_07" +#define TEST_DESC "Check for SVE Int8 matrix multiplc" + +static void payload(void) +{ + uint64_t data = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 7) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* ID_AA64PFR0_EL1.SVE[35:32] non-zero value indicate SVE support */ + data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 32, 35); + + if (data == 0) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + /* ID_AA64ZFR0_EL1.I8MM[47:44] = 0b0001 indicate SVE Int8 matrix multiply support */ + data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ZFR0_EL1), 44, 47); + + if (data == 1) + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t c034_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, + TEST_RULE); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/pe/operating_system/test_c035.c b/test_pool/pe/operating_system/test_c035.c new file mode 100644 index 00000000..0febe50d --- /dev/null +++ b/test_pool/pe/operating_system/test_c035.c @@ -0,0 +1,60 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/val_interface.h" + +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 35) +#define TEST_RULE "S_L7PE_08" +#define TEST_DESC "Check for data gathering hint " + +static void payload(void) +{ + uint64_t data = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 7) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* ID_AA64ISAR1_EL1.DGH[51:48] = 0b0001 indicate data gathering hint feature */ + data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR1_EL1), 48, 51); + + if (data == 1) + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t c035_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, + TEST_RULE); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/pe/operating_system/test_c036.c b/test_pool/pe/operating_system/test_c036.c new file mode 100644 index 00000000..cc6a09f1 --- /dev/null +++ b/test_pool/pe/operating_system/test_c036.c @@ -0,0 +1,61 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/val_interface.h" + +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 36) +#define TEST_RULE "S_L7PE_09" +#define TEST_DESC "Check WFE Fine tune delay feature " + +static void payload(void) +{ + uint64_t data = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 7) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* ID_AA64MMFR1_EL1.TWED [35:32] = 0b0001 indicates support for configurable delayed + trapping for WFE instruction */ + data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR1_EL1), 32, 35); + + if (data == 1) + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t c036_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, + TEST_RULE); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/pe/operating_system/test_c037.c b/test_pool/pe/operating_system/test_c037.c new file mode 100644 index 00000000..a8014bd1 --- /dev/null +++ b/test_pool/pe/operating_system/test_c037.c @@ -0,0 +1,60 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/val_interface.h" + +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 37) +#define TEST_RULE "S_L7PE_10" +#define TEST_DESC "Check for enhanced PAN feature " + +static void payload(void) +{ + uint64_t data = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 7) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* ID_AA64MMFR1_EL1.PAN [23:20] = 0b0011 indicate support for enhanced PAN feature */ + data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR1_EL1), 20, 23); + + if (data == 3) + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t c037_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, + TEST_RULE); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/pe/test_c001.c b/test_pool/pe/test_c001.c deleted file mode 100644 index dfe0b3ca..00000000 --- a/test_pool/pe/test_c001.c +++ /dev/null @@ -1,65 +0,0 @@ -/** @file - * Copyright (c) 2016-2018, 2021-2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/sbsa_avs_pe.h" -#include "val/include/val_interface.h" - -#define TEST_NUM AVS_PE_TEST_NUM_BASE + 1 -#define TEST_DESC "Check for number of PE " - -static -void -payload(void) -{ - uint64_t num_of_pe = 0; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - num_of_pe = val_pe_get_num(); - - if (num_of_pe > MAX_NUM_PE) { - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - val_print(AVS_PRINT_ERR, "Number of PE is %d \n", num_of_pe); - return; - } - - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - - return; - -} - -uint32_t -c001_entry() -{ - - uint32_t status = AVS_STATUS_FAIL; //default value - uint32_t num_pe = 1; - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - - /* This check is when user is forcing us to skip this test */ - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} diff --git a/test_pool/pe/test_c002.c b/test_pool/pe/test_c002.c deleted file mode 100644 index 67ccb5e8..00000000 --- a/test_pool/pe/test_c002.c +++ /dev/null @@ -1,62 +0,0 @@ -/** @file - * Copyright (c) 2016-2018, 2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ -#include "val/include/sbsa_avs_val.h" -#include "val/include/sbsa_avs_pe.h" -#include "val/include/val_interface.h" - -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 02) -#define TEST_DESC "Check for SIMD extensions " - -static -void -payload(void) -{ - uint64_t data = 0; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - data = val_pe_reg_read(ID_AA64PFR0_EL1); - data = (data & 0xF00000) >> 20; - - if ((data == 0x0) || (data == 0x1)) - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - else - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - - return; - -} - -uint32_t -c002_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL; //default value - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - - /* This check is when user is forcing us to skip this test */ - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} - diff --git a/test_pool/pe/test_c005.c b/test_pool/pe/test_c005.c deleted file mode 100644 index 06c79f3c..00000000 --- a/test_pool/pe/test_c005.c +++ /dev/null @@ -1,59 +0,0 @@ -/** @file - * Copyright (c) 2016-2018, 2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/sbsa_avs_pe.h" - -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 05) -#define TEST_DESC "Check Cache Architecture " - -static -void -payload(void) -{ - uint64_t data = 0; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - data = val_pe_reg_read(CTR_EL0); - - if ((data & 0x8000)) //bits 15:14 - bit 15 must be 1 for VIPT or PIPT - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - else - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - - return; - -} - -uint32_t -c005_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL; - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} - diff --git a/test_pool/pe/test_c006.c b/test_pool/pe/test_c006.c deleted file mode 100644 index e41e194a..00000000 --- a/test_pool/pe/test_c006.c +++ /dev/null @@ -1,69 +0,0 @@ -/** @file - * Copyright (c) 2016-2018, 2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/sbsa_avs_pe.h" - -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 06) -#define TEST_DESC "Check HW Coherence support " - -static -void -payload(void) -{ - uint64_t data = 0; - uint64_t pfr0, a32_support; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - pfr0 = val_pe_reg_read(ID_AA64PFR0_EL1); - a32_support = ((pfr0 & 0xf000) == 0x2000)? 1:((pfr0 & 0xf00) == 0x200)?\ - 1:((pfr0 & 0xf0) == 0x20)? 1:((pfr0 & 0xf) == 0x2)? 1:0; - - if(a32_support == 0){ - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); - return; - } - - data = val_pe_reg_read(ID_MMFR0_EL1); - - if ((((data >> 28) & 0xF) == 1) && (((data >> 12) & 0xF) == 1)) //bits 31:28 and 15:12 should be 1 - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - else - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - - return; - -} - -uint32_t -c006_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL; - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} - diff --git a/test_pool/pe/test_c007.c b/test_pool/pe/test_c007.c deleted file mode 100644 index 10dba70e..00000000 --- a/test_pool/pe/test_c007.c +++ /dev/null @@ -1,59 +0,0 @@ -/** @file - * Copyright (c) 2016-2018, 2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/sbsa_avs_pe.h" - -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 07) -#define TEST_DESC "Check Cryptographic extensions " - -static -void -payload(void) -{ - uint64_t data = 0; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - data = val_pe_reg_read(ID_AA64ISAR0_EL1); - - if (((data >> 4) & 0xF) && ((data >> 8) & 0xF) && ((data >> 12) & 0xF)) //bits 7:4, 11:8, 15:12 must be non-zero - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - else - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - - return; - -} - -uint32_t -c007_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL; - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} - diff --git a/test_pool/pe/test_c008.c b/test_pool/pe/test_c008.c deleted file mode 100644 index bf7cd0ae..00000000 --- a/test_pool/pe/test_c008.c +++ /dev/null @@ -1,61 +0,0 @@ -/** @file - * Copyright (c) 2016-2019, 2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/sbsa_avs_pe.h" - -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 8) -#define TEST_DESC "Check Little Endian support " - -static -void -payload(void) -{ - uint64_t data = 0; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - /* Check the current endianness setting of SCTLR.EE */ - if (val_pe_reg_read(CurrentEL) == AARCH64_EL2) { - data = val_pe_reg_read(SCTLR_EL2); - } else if (val_pe_reg_read(CurrentEL) == AARCH64_EL1) { - data = val_pe_reg_read(SCTLR_EL1); - } - - if (((data >> 25) & 1) == 0) //Bit 25 must be 0 - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 02)); - else - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); - - return; -} - -uint32_t -c008_entry(uint32_t num_pe) -{ - uint32_t status = AVS_STATUS_FAIL; - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} diff --git a/test_pool/pe/test_c011.c b/test_pool/pe/test_c011.c deleted file mode 100755 index 1c21d373..00000000 --- a/test_pool/pe/test_c011.c +++ /dev/null @@ -1,110 +0,0 @@ -/** @file - * Copyright (c) 2016-2018, 2021-2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/sbsa_avs_pe.h" - - -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 11) -#define TEST_DESC "Check PMU Overflow signal " - -static uint32_t int_id; - -static -void -set_pmu_overflow(void) -{ - uint64_t pmcr; - - //Initializing the state of overflow status and interrupt request registers - val_pe_reg_write(PMINTENCLR_EL1, 0xFFFFFFFF); - val_pe_reg_write(PMOVSCLR_EL0, 0xFFFFFFFF); - - //Sequence to generate PMUIRQ - pmcr = val_pe_reg_read(PMCR_EL0); - val_pe_reg_write(PMCR_EL0, pmcr|0x1); - - val_pe_reg_write(PMINTENSET_EL1, 0x1); - val_pe_reg_write(PMOVSSET_EL0, 0x1); - -} - - -static -void -isr(void) -{ - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - /* We received our interrupt, so disable PMUIRQ from generating further interrupts */ - val_pe_reg_write(PMOVSCLR_EL0, 0x1); - val_print(AVS_PRINT_INFO, "\n Received PMUIRQ ", 0); - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - val_gic_end_of_interrupt(int_id); - - return; -} - - -static -void -payload(void) -{ - uint32_t timeout = 0x100000; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - int_id = val_pe_get_pmu_gsiv(index); - - if (int_id != 23) { - timeout = 0; - val_print(AVS_PRINT_ERR, "\n Incorrect PPI value %d ", int_id); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); - return; - } - - val_gic_install_isr(int_id, isr); - - set_pmu_overflow(); - - while ((--timeout > 0) && (IS_RESULT_PENDING(val_get_status(index)))); - - if(timeout == 0) - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); -} - -/** - @brief Install ISR and verify PMU Overflow Interrupt by programming System registers -**/ -uint32_t -c011_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL; - num_pe = 1; - - status = val_initialize_test(TEST_NUM, TEST_DESC, val_pe_get_num(), g_sbsa_level); - if (status != AVS_STATUS_SKIP) - /* execute payload on present PE and then execute on other PE */ - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} - diff --git a/test_pool/pe/test_c012.c b/test_pool/pe/test_c012.c deleted file mode 100644 index 75de42b3..00000000 --- a/test_pool/pe/test_c012.c +++ /dev/null @@ -1,62 +0,0 @@ -/** @file - * Copyright (c) 2016-2018, 2021-2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/sbsa_avs_pe.h" - -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 12) -#define TEST_DESC "Check number of PMU counters " - -static -void -payload(void) -{ - uint64_t data = 0; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - data = val_pe_reg_read(PMCR_EL0); - - if (((data & 0x0F800) >> 11) > 5) //bits 15:11 for Number of counters. - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - else - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - - return; - -} - -uint32_t -c012_entry(uint32_t num_pe) -{ - - uint32_t status; - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - - if (status != AVS_STATUS_SKIP) - /* execute payload on present PE and then execute on other PE */ - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} - - diff --git a/test_pool/pe/test_c013.c b/test_pool/pe/test_c013.c deleted file mode 100644 index 12661f3e..00000000 --- a/test_pool/pe/test_c013.c +++ /dev/null @@ -1,60 +0,0 @@ -/** @file - * Copyright (c) 2016-2018, 2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/sbsa_avs_pe.h" - -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 13) -#define TEST_DESC "Check Synchronous Watchpoints " - -static -void -payload(void) -{ - uint64_t data = 0; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - data = val_pe_reg_read(ID_AA64DFR0_EL1); - - if (((data >> 20) & 0xF) > 2) //bits 23:20 for Number of watchpoints - 1 - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - else - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - - return; - -} - -uint32_t -c013_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL; - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - if (status != AVS_STATUS_SKIP) - /* execute payload on present PE and then execute on other PE */ - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} - diff --git a/test_pool/pe/test_c014.c b/test_pool/pe/test_c014.c deleted file mode 100644 index f1288473..00000000 --- a/test_pool/pe/test_c014.c +++ /dev/null @@ -1,74 +0,0 @@ -/** @file - * Copyright (c) 2016-2018, 2021-2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/sbsa_avs_pe.h" - -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 14) -#define TEST_DESC "Check number of Breakpoints " - -static -void payload(void) -{ - uint64_t data = 0; - int32_t breakpointcount; - uint32_t context_aware_breakpoints = 0; - uint32_t pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); - - data = val_pe_reg_read(ID_AA64DFR0_EL1); - - /* bits 15:12 for Number of breakpoints - 1 */ - breakpointcount = VAL_EXTRACT_BITS(data, 12, 15) + 1; - - if (breakpointcount < 6) { - val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 1)); - return; - } - - /*bits [31:28] Number of breakpoints that are context-aware, minus 1*/ - context_aware_breakpoints = VAL_EXTRACT_BITS(data, 28, 31) + 1; - if (context_aware_breakpoints > 1) - val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 1)); - else - val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 2)); - - - return; - -} - -/** - @brief Check for the number of breakpoints available -**/ -uint32_t -c014_entry(uint32_t num_pe) -{ - uint32_t status = AVS_STATUS_FAIL; - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - if (status != AVS_STATUS_SKIP) - /* execute payload on present PE and then execute on other PE */ - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} - diff --git a/test_pool/pe/test_c015.c b/test_pool/pe/test_c015.c deleted file mode 100755 index f487940b..00000000 --- a/test_pool/pe/test_c015.c +++ /dev/null @@ -1,279 +0,0 @@ -/** @file - * Copyright (c) 2016-2018, 2021-2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/sbsa_avs_pe.h" - -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 15) -#define TEST_DESC "Check Arch symmetry across PE " - -#define NUM_OF_REGISTERS 32 - -#define RAS 1 -#define SPE 2 -#define LOR 3 -#define AA32 4 -#define PMUV3 5 - -#define MASK_AA64MMFR0 0xF -#define MASK_MIDR 0x00F0FFFF -#define MASK_MPIDR 0xFF3FFFFFFF -#define MASK_CTR 0xC000 -#define MASK_CCSIDR 0xFFFFFF8 -#define MASK_PMCR 0xFFFF - -#define MAX_CACHE_LEVEL 7 - -uint64_t rd_data_array[NUM_OF_REGISTERS]; -uint64_t cache_list[MAX_CACHE_LEVEL]; - -typedef struct{ - uint32_t reg_name; - uint64_t reg_mask; - char reg_desc[30]; - uint8_t dependency; -}reg_details; - -reg_details reg_list[] = { - {CCSIDR_EL1, MASK_CCSIDR, "CCSIDR_EL1" , 0x0 }, - {ID_AA64PFR0_EL1, 0x0, "ID_AA64PFR0_EL1" , 0x0 }, - {ID_AA64PFR1_EL1, 0x0, "ID_AA64PFR1_EL1" , 0x0 }, - {ID_AA64DFR0_EL1, 0x0, "ID_AA64DFR0_EL1" , 0x0 }, - {ID_AA64DFR1_EL1, 0x0, "ID_AA64DFR1_EL1" , 0x0 }, - {ID_AA64MMFR0_EL1, MASK_AA64MMFR0, "ID_AA64MMFR0_EL1", 0x0 }, - {ID_AA64MMFR1_EL1, 0x0, "ID_AA64MMFR1_EL1", 0x0 }, - //{ID_AA64MMFR2_EL1, 0x0, "ID_AA64MMFR2_EL1", 0x0 }, - {CTR_EL0, MASK_CTR, "CTR_EL0" , 0x0 }, - {ID_AA64ISAR0_EL1, 0x0, "ID_AA64ISAR0_EL1", 0x0 }, - {ID_AA64ISAR1_EL1, 0x0, "ID_AA64ISAR1_EL1", 0x0 }, - {MPIDR_EL1, MASK_MPIDR, "MPIDR_EL1" , 0x0 }, - {MIDR_EL1, MASK_MIDR, "MIDR_EL1" , 0x0 }, - {ID_DFR0_EL1, 0x0, "ID_DFR0_EL1" , AA32}, - {ID_ISAR0_EL1, 0x0, "ID_ISAR0_EL1" , AA32}, - {ID_ISAR1_EL1, 0x0, "ID_ISAR1_EL1" , AA32}, - {ID_ISAR2_EL1, 0x0, "ID_ISAR2_EL1" , AA32}, - {ID_ISAR3_EL1, 0x0, "ID_ISAR3_EL1" , AA32}, - {ID_ISAR4_EL1, 0x0, "ID_ISAR4_EL1" , AA32}, - {ID_ISAR5_EL1, 0x0, "ID_ISAR5_EL1" , AA32}, - {ID_MMFR0_EL1, 0x0, "ID_MMFR0_EL1" , AA32}, - {ID_MMFR1_EL1, 0x0, "ID_MMFR1_EL1" , AA32}, - {ID_MMFR2_EL1, 0x0, "ID_MMFR2_EL1" , AA32}, - {ID_MMFR3_EL1, 0x0, "ID_MMFR3_EL1" , AA32}, - {ID_MMFR4_EL1, 0x0, "ID_MMFR4_EL1" , AA32}, - {ID_PFR0_EL1, 0x0, "ID_PFR0_EL1" , AA32}, - {ID_PFR1_EL1, 0x0, "ID_PFR1_EL1" , AA32}, - {MVFR0_EL1, 0x0, "MVFR0_EL1" , AA32}, - {MVFR1_EL1, 0x0, "MVFR1_EL1" , AA32}, - {MVFR2_EL1, 0x0, "MVFR2_EL1" , AA32}, - {PMCEID0_EL0, 0x0, "PMCEID0_EL0", PMUV3 }, - {PMCEID1_EL0, 0x0, "PMCEID1_EL0", PMUV3 }, - {PMCR_EL0, MASK_PMCR, "PMCR_EL0", PMUV3 }, - {PMBIDR_EL1, 0x0, "PMBIDR_EL1" , SPE }, - {PMSIDR_EL1, 0x0, "PMSIDR_EL1" , SPE }, - {ERRIDR_EL1, 0x0, "ERRIDR_EL1" , RAS }, - {ERR0FR_EL1, 0x0, "ERR0FR_EL1" , RAS }, - {ERR1FR_EL1, 0x0, "ERR1FR_EL1" , RAS }, - {ERR2FR_EL1, 0x0, "ERR2FR_EL1" , RAS }, - {ERR3FR_EL1, 0x0, "ERR3FR_EL1" , RAS }, - {LORID_EL1, 0x0, "LORID_EL1" , LOR } -}; - -static -uint64_t -return_reg_value(uint32_t reg, uint8_t dependency) -{ - uint64_t temp=0; - - if(dependency == 0) - return val_pe_reg_read(reg); - - switch(dependency) - { - case RAS: // If RAS is not supported, then skip register check - temp = val_pe_reg_read(ID_AA64PFR0_EL1); - temp = (temp >> 28) & 0xf; - if(temp == 1) - return val_pe_reg_read(reg); - else - return 0; - break; - - case SPE: // If Statistical Profiling Extension is not supported, then skip register check - temp = val_pe_reg_read(ID_AA64DFR0_EL1); - temp = (temp >> 32) & 0xf; - if(temp == 1) - return val_pe_reg_read(reg); - else - return 0; - break; - - case LOR: // If Limited Ordering Region is not supported, then skip register check - temp = val_pe_reg_read(ID_AA64MMFR1_EL1); - temp = (temp >> 16) & 0xf; - if(temp == 1) - return val_pe_reg_read(reg); - else - return 0; - break; - - case AA32: // If the register is UNK in pure AArch64 implementation, then skip register check - temp = val_pe_reg_read(ID_AA64PFR0_EL1); - temp = (temp & 1); - if(temp == 0) - return val_pe_reg_read(reg); - else - return 0; - break; - - case PMUV3: // If PMUv3 is not supported, then skip register check - temp = val_pe_reg_read(ID_AA64DFR0_EL1); - temp = (temp >> 8) & 0xf; - if (temp != 0 && temp != 0b1111) - return val_pe_reg_read(reg); - else - return 0; - break; - - default: - val_print(AVS_PRINT_ERR, "\n Unknown dependency = %d ", dependency); - return 0x0; - } - -} - -static -void -id_regs_check(void) -{ - uint64_t reg_read_data; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - uint32_t i = 0; - - /* Loop CLIDR to check if a cache level is implemented before comparing */ - while (i < MAX_CACHE_LEVEL) { - reg_read_data = val_pe_reg_read(CLIDR_EL1); - if (reg_read_data & ((0x7) << (i * 3))) { - /* Select the correct cache in csselr register */ - val_pe_reg_write(CSSELR_EL1, i << 1); - reg_read_data = return_reg_value(reg_list[0].reg_name, reg_list[0].dependency); - - if ((reg_read_data & (~reg_list[0].reg_mask)) != (cache_list[i] & (~reg_list[0].reg_mask))) { - val_set_test_data(index, (reg_read_data & (~reg_list[0].reg_mask)), 0); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - return; - } - } - i++; - } - - for (i = 1; i < NUM_OF_REGISTERS; i++) { - reg_read_data = return_reg_value(reg_list[i].reg_name, reg_list[i].dependency); - - if((reg_read_data & (~reg_list[i].reg_mask)) != (rd_data_array[i] & (~reg_list[i].reg_mask))) - { - val_set_test_data(index, (reg_read_data & (~reg_list[i].reg_mask)), i); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - return; - } - reg_read_data = 0; - } - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - - return; -} - -static -void -payload(uint32_t num_pe) -{ - uint32_t my_index = val_pe_get_index_mpid(val_pe_get_mpid()); - uint32_t i; - uint32_t timeout; - uint64_t reg_read_data, debug_data=0, array_index=0; - - if (num_pe == 1) { - val_print(AVS_PRINT_WARN, "\n Skipping as num of PE is 1 ", 0); - val_set_status(my_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); - return; - } - - /* Loop CLIDR to check if a cache level is implemented */ - i = 0; - while (i < MAX_CACHE_LEVEL) { - reg_read_data = val_pe_reg_read(CLIDR_EL1); - if (reg_read_data & ((0x7) << (i * 3))) { - /* Select the correct cache level in csselr register */ - val_pe_reg_write(CSSELR_EL1, i << 1); - cache_list[i] = return_reg_value(reg_list[0].reg_name, reg_list[0].dependency); - val_data_cache_ops_by_va((addr_t)(cache_list + i), CLEAN_AND_INVALIDATE); - val_print(AVS_PRINT_INFO, "\n Cache size read is %x ", cache_list[i]); - } - i++; - } - - for (i = 1; i < NUM_OF_REGISTERS; i++) { - rd_data_array[i] = return_reg_value(reg_list[i].reg_name, reg_list[i].dependency); - val_data_cache_ops_by_va((addr_t)(rd_data_array + i), CLEAN_AND_INVALIDATE); - } - - for (i = 0; i < num_pe; i++) { - if (i != my_index) { - timeout=TIMEOUT_LARGE; - val_execute_on_pe(i, id_regs_check, 0); - while ((--timeout) && (IS_RESULT_PENDING(val_get_status(i)))); - - if(timeout == 0) { - val_print(AVS_PRINT_ERR, "\n **Timed out** for PE index = %d", i); - val_set_status(i, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); - return; - } - - if(IS_TEST_FAIL(val_get_status(i))) { - val_get_test_data(i, &debug_data, &array_index); - val_print(AVS_PRINT_ERR, "\n Reg compare failed for PE index=%d for Register: ", i); - val_print(AVS_PRINT_ERR, reg_list[array_index].reg_desc, 0); - val_print(AVS_PRINT_ERR, "\n Current PE value = 0x%llx", rd_data_array[array_index] & (~reg_list[array_index].reg_mask)); - val_print(AVS_PRINT_ERR, " Other PE value = 0x%llx", debug_data); - return; - } - } - } - - return; - -} - -uint32_t -c015_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL; - - status = val_initialize_test(TEST_NUM, TEST_DESC, val_pe_get_num(), g_sbsa_level); - - if (status != AVS_STATUS_SKIP) - /* execute payload, which will execute relevant functions on current and other PEs */ - payload(num_pe); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} - diff --git a/test_pool/pe/test_c017.c b/test_pool/pe/test_c017.c deleted file mode 100644 index 0bf99980..00000000 --- a/test_pool/pe/test_c017.c +++ /dev/null @@ -1,60 +0,0 @@ -/** @file - * Copyright (c) 2016-2018, 2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/sbsa_avs_pe.h" - -#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 17) -#define TEST_DESC "Check CRC32 instruction support " - -static -void -payload(void) -{ - uint64_t data = 0; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - data = val_pe_reg_read(ID_AA64ISAR0_EL1); - - if ((data >> 16) & 0xF) //bits 19:16 are CRC32 and should not be zero - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - else - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - - return; - -} - -uint32_t -c017_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL; - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} - diff --git a/test_pool/peripherals/test_d001.c b/test_pool/peripherals/test_d001.c deleted file mode 100644 index 3b22d529..00000000 --- a/test_pool/peripherals/test_d001.c +++ /dev/null @@ -1,92 +0,0 @@ -/** @file - * Copyright (c) 2016-2019, 2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/val_interface.h" - -#include "val/include/sbsa_avs_peripherals.h" -#include "val/include/sbsa_avs_pcie.h" - -#define TEST_NUM (AVS_PER_TEST_NUM_BASE + 1) -#define TEST_DESC "Check USB CTRL Interface via PCIe " - -static -void -payload(void) -{ - - uint32_t interface = 0; - uint32_t ret; - uint32_t bdf; - uint64_t count = val_peripheral_get_info(NUM_USB, 0); - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - if (count == 0) { - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); - return; - } - - while (count != 0) { - bdf = val_peripheral_get_info(USB_BDF, count - 1); - ret = val_pcie_read_cfg(bdf, 0x8, &interface); - interface = (interface >> 8) & 0xFF; - if (ret == PCIE_NO_MAPPING || (interface < 0x20) || (interface == 0xFF)) { - val_print(AVS_PRINT_WARN, "\n WARN: USB CTRL ECAM access failed 0x%x ", interface); - val_print(AVS_PRINT_WARN, "\n Re-checking USB CTRL using PciIo protocol ", 0); - ret = val_pcie_io_read_cfg(bdf, 0x8, &interface); - if (ret == PCIE_NO_MAPPING) { - val_print(AVS_PRINT_ERR, "\n Reading device class code using PciIo protocol failed ", 0); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); - return; - } - interface = (interface >> 8) & 0xFF; - if ((interface < 0x20) || (interface == 0xFF)) { - val_print(AVS_PRINT_ERR, "\n Detected USB CTRL not EHCI/XHCI 0x%x ", interface); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - return; - } - } - count--; - } - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - return; -} - -/** - @brief Read PCI CFG space class and sub-class register - to determine the USB interface version -**/ -uint32_t -d001_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL; - - num_pe = 1; //This test is run on single processor - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} diff --git a/test_pool/peripherals/test_d002.c b/test_pool/peripherals/test_d002.c deleted file mode 100644 index 3571d405..00000000 --- a/test_pool/peripherals/test_d002.c +++ /dev/null @@ -1,92 +0,0 @@ -/** @file - * Copyright (c) 2016-2019, 2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/val_interface.h" - -#include "val/include/sbsa_avs_peripherals.h" -#include "val/include/sbsa_avs_pcie.h" - -#define TEST_NUM (AVS_PER_TEST_NUM_BASE + 2) -#define TEST_DESC "Check SATA CTRL Interface via PCIe" - -static -void -payload(void) -{ - - uint32_t interface = 0; - uint32_t bdf; - uint32_t ret; - uint32_t count = val_peripheral_get_info(NUM_SATA, 0); - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - if (count == 0) { - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); - return; - } - - while (count != 0) { - bdf = val_peripheral_get_info(SATA_BDF, count - 1); - ret = val_pcie_read_cfg(bdf, 0x8, &interface); - interface = (interface >> 8) & 0xFF; - if (ret == PCIE_NO_MAPPING || interface != 0x01) { - val_print(AVS_PRINT_WARN, "\n WARN: SATA CTRL ECAM access failed %x ", interface); - val_print(AVS_PRINT_WARN, "\n Re-checking SATA CTRL using PciIo protocol ", 0); - ret = val_pcie_io_read_cfg(bdf, 0x8, &interface); - if (ret == PCIE_NO_MAPPING) { - val_print(AVS_PRINT_ERR, "\n Reading device class code using PciIo protocol failed ", 0); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); - return; - } - interface = (interface >> 8) & 0xFF; - if (interface != 0x01) { - val_print(AVS_PRINT_ERR, "\n Detected SATA CTRL not AHCI ", 0); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - return; - } - } - count--; - } - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - return; -} - -/** - @brief Read PCI CFG space class and sub-class register - to determine the SATA interface version -**/ -uint32_t -d002_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL; - - num_pe = 1; //This test is run on single processor - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} diff --git a/test_pool/peripherals/test_d003.c b/test_pool/peripherals/test_d003.c deleted file mode 100755 index 0658a458..00000000 --- a/test_pool/peripherals/test_d003.c +++ /dev/null @@ -1,270 +0,0 @@ -/** @file - * Copyright (c) 2016-2018, 2021-2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/val_interface.h" -#include "val/include/sbsa_avs_pe.h" - -#include "val/include/sbsa_avs_peripherals.h" -#include "val/include/sbsa_avs_gic.h" - -#define TEST_NUM (AVS_PER_TEST_NUM_BASE + 3) -/*one space character is removed from TEST_DESC, to nullify a space written as part of the test */ -#define TEST_DESC "Check SBSA UART register offsets " -#define TEST_NUM1 (AVS_PER_TEST_NUM_BASE + 4) -#define TEST_DESC1 "Check Generic UART Interrupt " - -static uint64_t l_uart_base; -static uint32_t int_id; -static uint64_t branch_to_test; -static uint32_t test_fail; - -static -void -esr(uint64_t interrupt_type, void *context) -{ - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - /* Update the ELR to point to next instrcution */ - val_pe_update_elr(context, branch_to_test); - - val_print(AVS_PRINT_ERR, "\n Error : Received Sync Exception type %d", interrupt_type); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); -} - -static -uint32_t -uart_reg_read(uint32_t offset, uint32_t width_mask) -{ - if (width_mask & WIDTH_BIT8) - return *((volatile uint8_t *)(l_uart_base + offset)); - - if (width_mask & WIDTH_BIT16) - return *((volatile uint16_t *)(l_uart_base + offset)); - - if (width_mask & WIDTH_BIT32) - return *((volatile uint32_t *)(l_uart_base + offset)); - - return 0; -} - -static -void -uart_reg_write(uint32_t offset, uint32_t width_mask, uint32_t data) -{ - if (width_mask & WIDTH_BIT8) - *((volatile uint8_t *)(l_uart_base + offset)) = (uint8_t)data; - - if (width_mask & WIDTH_BIT16) - *((volatile uint16_t *)(l_uart_base + offset)) = (uint16_t)data; - - if (width_mask & WIDTH_BIT32) - *((volatile uint32_t *)(l_uart_base + offset)) = (uint32_t)data; - -} - -static -void -uart_setup(void) -{ - - - -} - -static -void -uart_enable_txintr(void) -{ - uint32_t data; - - /* Enable TX interrupt by setting mask bit[5] in UARTIMSC */ - data = uart_reg_read(SBSA_UARTIMSC, WIDTH_BIT32); - data = data | (1<<5); - uart_reg_write(SBSA_UARTIMSC, WIDTH_BIT32, data); -} - -static -void -uart_disable_txintr(void) -{ - uint32_t data; - - /* Disable TX interrupt by clearing mask bit[5] in UARTIMSC */ - data = uart_reg_read(SBSA_UARTIMSC, WIDTH_BIT32); - data = data & (~(1<<5)); - uart_reg_write(SBSA_UARTIMSC, WIDTH_BIT32, data); - -} - -static -void -isr(void) -{ - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - uart_disable_txintr(); - val_print(AVS_PRINT_DEBUG, "\n Received interrupt ", 0); - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM1, 01)); - val_gic_end_of_interrupt(int_id); -} - -static -uint32_t -validate_register_access(uint32_t offset, uint32_t width) -{ - if (width & WIDTH_BIT8) { - uart_reg_write(offset, WIDTH_BIT8, 0xF); - } - if (width & WIDTH_BIT16) { - uart_reg_write(offset, WIDTH_BIT16, 0xF); - } - if (width & WIDTH_BIT32) { - uart_reg_write(offset, WIDTH_BIT32, 0xF); - } - return AVS_STATUS_PASS; - -} - -static -void -payload(void) -{ - - uint32_t count = val_peripheral_get_info(NUM_UART, 0); - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - val_pe_install_esr(EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, esr); - val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); - - branch_to_test = (uint64_t)&&exception_taken; - - if (count == 0) { - val_print(AVS_PRINT_WARN, "\n No UART defined by Platform ", 0); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - return; - } - - while (count != 0) { - - l_uart_base = val_peripheral_get_info(UART_BASE0, count - 1); - if (l_uart_base == 0) { - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); - return; - } - - uart_setup(); - - /*Make sure write to a read only register doesn't cause any exceptions*/ - validate_register_access(SBSA_UARTFR, WIDTH_BIT8 | WIDTH_BIT16 | WIDTH_BIT32); - validate_register_access(SBSA_UARTRIS, WIDTH_BIT16 | WIDTH_BIT32); - validate_register_access(SBSA_UARTMIS, WIDTH_BIT16 | WIDTH_BIT32); - /* Writing bits 11:8 as 0xF and writing space character (0x20) to UART data register */ - uart_reg_write(SBSA_UARTDR, WIDTH_BIT32, 0xF20); - - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - - count--; - } -exception_taken: - return; -} - -static -void -payload1(void) -{ - uint32_t count = val_peripheral_get_info(NUM_UART, 0); - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - uint32_t timeout; - - if (count == 0) { - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM1, 01)); - return; - } - - while (count != 0) { - timeout = TIMEOUT_MEDIUM; - int_id = val_peripheral_get_info(UART_GSIV, count - 1); - l_uart_base = val_peripheral_get_info(UART_BASE0, count - 1); - - /* If Interrupt ID is available, check for interrupt generation */ - if (int_id != 0x0) { - /* PASS will be set from ISR */ - val_set_status(index, RESULT_PENDING(g_sbsa_level, TEST_NUM1)); - if (val_gic_install_isr(int_id, isr)) { - val_print(AVS_PRINT_ERR, "\n GIC Install Handler Fail", 0); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM1, 01)); - return; - } - uart_enable_txintr(); - val_print_raw(l_uart_base, g_print_level, - "\n Test Message ", 0); - - while ((--timeout > 0) && (IS_RESULT_PENDING(val_get_status(index)))) { - }; - - if (timeout == 0) { - val_print(AVS_PRINT_ERR, - "\n Did not receive UART interrupt %d ", int_id); - test_fail++; - } - } else { - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM1, 02)); - } - - count--; - } - if (test_fail) - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM1, 02)); - else - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM1, 02)); -} - - -/** - @brief Verify UART registers for Read-only bits and also - enable interrupt generation -**/ -uint32_t -d003_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL; - - num_pe = 1; //This test is run on single processor - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - if (!status) { - status = val_initialize_test(TEST_NUM1, TEST_DESC1, val_pe_get_num(), g_sbsa_level); - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM1, num_pe, payload1, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM1, num_pe); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM1)); - } - - - return status; -} diff --git a/test_pool/peripherals/test_m001.c b/test_pool/peripherals/test_m001.c deleted file mode 100644 index 25a9ff05..00000000 --- a/test_pool/peripherals/test_m001.c +++ /dev/null @@ -1,127 +0,0 @@ -/** @file - * Copyright (c) 2016-2018, 2020-2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/val_interface.h" - -#include "val/include/sbsa_avs_peripherals.h" -#include "val/include/sbsa_avs_pe.h" -#include "val/include/sbsa_avs_memory.h" - -#define TEST_NUM (AVS_PER_TEST_NUM_BASE + 5) -#define TEST_DESC "Memory Access to Un-Populated addr" - -#define LOOP_VAR 3 /* Number of Addresses to check */ - -static void *branch_to_test; - -static -void -esr(uint64_t interrupt_type, void *context) -{ - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - /* Update the ELR to point to next instrcution */ - val_pe_update_elr(context, (uint64_t)branch_to_test); - - val_print(AVS_PRINT_INFO, "\n Received DAbort Exception %d", interrupt_type); - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); -} - -static -void -payload(void) -{ - addr_t addr; - uint64_t attr; - uint32_t instance = 0; - uint64_t status; - uint32_t loop_var = LOOP_VAR; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - status = val_pe_install_esr(EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, esr); - status |= val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); - if (status) - { - val_print(AVS_PRINT_ERR, "\n Failed in installing the exception handler", 0); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - return; - } - - /* If we don't find a single un-populated address, mark this test as skipped */ - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); - - while (loop_var) { - /* Get the base address of unpopulated region */ - status = val_memory_get_unpopulated_addr(&addr, instance); - if (status == MEM_MAP_NO_MEM) { - val_print(AVS_PRINT_INFO, "\n All instances of unpopulated memory were obtained", 0); - return; - } - - if (status) { - val_print(AVS_PRINT_ERR, "\n Error in obtaining unpopulated memory for instance 0x%d", instance); - return; - } - - if (val_memory_get_info(addr, &attr) == MEM_TYPE_NOT_POPULATED) { - /* default value of FAIL, Pass is set in the exception handler */ - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - - branch_to_test = &&exception_taken; - - *((volatile uint64_t*)addr) = 0x100; -exception_taken: - /* if the access did not go to our exception handler, fail and exit */ - if (IS_TEST_FAIL(val_get_status(index))) { - val_print(AVS_PRINT_ERR, "\n Memory access check fails at address = 0x%llx ", addr); - return; - } - - } - - loop_var--; - instance++; - } - -} - -uint32_t -m001_entry(uint32_t num_pe) -{ - - uint32_t error_flag = 0; - uint32_t status = AVS_STATUS_FAIL; - - num_pe = 1; //This test is run on single processor - - status = val_initialize_test(TEST_NUM, TEST_DESC, val_pe_get_num(), g_sbsa_level); - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - error_flag = val_check_for_error(TEST_NUM, num_pe); - - if (!error_flag) - status = AVS_STATUS_PASS; - else - status = AVS_STATUS_FAIL; - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} diff --git a/test_pool/power_wakeup/test_u001.c b/test_pool/power_wakeup/test_u001.c deleted file mode 100755 index c50ebaa9..00000000 --- a/test_pool/power_wakeup/test_u001.c +++ /dev/null @@ -1,355 +0,0 @@ -/** @file - * Copyright (c) 2016-2019, 2021-2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/sbsa_avs_pe.h" -#include "val/include/val_interface.h" - -#include "val/include/sbsa_avs_wakeup.h" - -#define TEST_DESC " TEST Wakeup from Power Semantic B \n" - -#define TEST_NUM (AVS_WAKEUP_TEST_NUM_BASE + 1) -#define TEST_DESC1 "Wake from EL0 PHY Timer Interrupt " -#define TEST_NUM2 (AVS_WAKEUP_TEST_NUM_BASE + 2) -#define TEST_DESC2 "Wake from EL0 VIRT Timer Interrupt" -#define TEST_NUM3 (AVS_WAKEUP_TEST_NUM_BASE + 3) -#define TEST_DESC3 "Wake from EL2 PHY Timer Interrupt " -#define TEST_NUM4 (AVS_WAKEUP_TEST_NUM_BASE + 4) -#define TEST_DESC4 "Wake from Watchdog WS0 Interrupt " -#define TEST_NUM5 (AVS_WAKEUP_TEST_NUM_BASE + 5) -#define TEST_DESC5 "Wake from System Timer Interrupt " - -static uint32_t intid; -uint64_t timer_num; -static uint32_t g_wd_int_received; -static uint32_t g_failsafe_int_received; -extern uint32_t g_wakeup_timeout; - -static -void -isr_failsafe(void) -{ - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - val_timer_set_phy_el1(0); - val_print(AVS_PRINT_ERR, "\n Received Failsafe interrupt ", 0); - g_failsafe_int_received = 1; - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID, 0); - val_gic_end_of_interrupt(intid); -} - -static -void -isr1(void) -{ - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - val_timer_set_phy_el1(0); - val_print(AVS_PRINT_INFO, "\n Received EL1 PHY interrupt ", 0); - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID, 0); - val_gic_end_of_interrupt(intid); -} - - -static -void -isr2(void) -{ - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - /* We received our interrupt, so disable timer from generating further interrupts */ - val_timer_set_vir_el1(0); - val_print(AVS_PRINT_INFO, "\n Received EL1 VIRT interrupt ", 0); - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM2, 01)); - intid = val_timer_get_info(TIMER_INFO_VIR_EL1_INTID, 0); - val_gic_end_of_interrupt(intid); -} - -static -void -isr3(void) -{ - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - /* We received our interrupt, so disable timer from generating further interrupts */ - val_timer_set_phy_el2(0); - val_print(AVS_PRINT_INFO, "\n Received EL2 Physical interrupt ", 0); - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM3, 01)); - intid = val_timer_get_info(TIMER_INFO_PHY_EL2_INTID, 0); - val_gic_end_of_interrupt(intid); -} - -static -void -isr4(void) -{ - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - val_wd_set_ws0(timer_num, 0); - val_print(AVS_PRINT_INFO, "\n Received WS0 interrupt ", 0); - g_wd_int_received = 1; - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM4, 01)); - intid = val_wd_get_info(timer_num, WD_INFO_GSIV); - val_gic_end_of_interrupt(intid); -} - -static -void -isr5(void) -{ - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - uint64_t cnt_base_n = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N, timer_num); - val_timer_disable_system_timer((addr_t)cnt_base_n); - val_print(AVS_PRINT_INFO, "\n Received Sys timer interrupt ", 0); - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM5, 01)); - intid = val_timer_get_info(TIMER_INFO_SYS_INTID, timer_num); - val_gic_end_of_interrupt(intid); -} - -static -void -wakeup_set_failsafe(void) -{ - uint64_t timer_expire_val = val_get_counter_frequency() * (g_wakeup_timeout + 1); - - intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID, 0); - val_gic_install_isr(intid, isr_failsafe); - val_timer_set_phy_el1(timer_expire_val); -} - -static -void -wakeup_clear_failsafe(void) -{ - val_timer_set_phy_el1(0); - -} - -static -void -payload1(void) -{ - uint64_t timer_expire_val = val_get_counter_frequency() * g_wakeup_timeout; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - - intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID, 0); - val_gic_install_isr(intid, isr1); - val_timer_set_phy_el1(timer_expire_val); - val_power_enter_semantic(SBSA_POWER_SEM_B); - return; -} - -static -void -payload2(void) -{ - uint64_t timer_expire_val = val_get_counter_frequency() * g_wakeup_timeout; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM2, 01)); - intid = val_timer_get_info(TIMER_INFO_VIR_EL1_INTID, 0); - val_gic_install_isr(intid, isr2); - wakeup_set_failsafe(); - val_timer_set_vir_el1(timer_expire_val); - val_power_enter_semantic(SBSA_POWER_SEM_B); - wakeup_clear_failsafe(); - return; -} - -static -void -payload3(void) -{ - uint64_t timer_expire_val = val_get_counter_frequency() * g_wakeup_timeout; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM3, 01)); - intid = val_timer_get_info(TIMER_INFO_PHY_EL2_INTID, 0); - val_gic_install_isr(intid, isr3); - wakeup_set_failsafe(); - val_timer_set_phy_el2(timer_expire_val); - val_power_enter_semantic(SBSA_POWER_SEM_B); - wakeup_clear_failsafe(); - return; -} - -static -void -payload4(void) -{ - uint32_t status, ns_wdg = 0; - uint64_t timer_expire_val = 1 * g_wakeup_timeout; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - timer_num = val_wd_get_info(0, WD_INFO_COUNT); - if(!timer_num){ - val_print(AVS_PRINT_WARN, "\n No watchdog implemented ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM4, 01)); - return; - } - - while(timer_num--) { - if(val_wd_get_info(timer_num, WD_INFO_ISSECURE)) - continue; - - ns_wdg++; - intid = val_wd_get_info(timer_num, WD_INFO_GSIV); - status = val_gic_install_isr(intid, isr4); - if (status == 0) { - wakeup_set_failsafe(); - status = val_wd_set_ws0(timer_num, timer_expire_val); - if (status) { - val_print(AVS_PRINT_ERR, "\n Setting watchdog timeout failed", 0); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM4, 02)); - return; - } - g_wd_int_received = 0; - g_failsafe_int_received = 0; - - val_power_enter_semantic(SBSA_POWER_SEM_B); - wakeup_clear_failsafe(); - /* If PE wakeup is due to some interrupt other than WD - or failsafe, test will be consider as PASS(as BSA WAK_10 rule - Semantic B is satisfied) - Test will be consider as failure in case WD interrupt - failed to fire. - */ - if (!(g_wd_int_received || g_failsafe_int_received)) { - val_gic_clear_interrupt(intid); - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM4, 1)); - } - } else { - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM4, 01)); - } - } - - if(!ns_wdg){ - val_print(AVS_PRINT_WARN, "\n No non-secure watchdog implemented ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM4, 02)); - return; - } - -} - -static -void -payload5(void) -{ - uint64_t cnt_base_n; - uint64_t timer_expire_val = val_get_counter_frequency() * g_wakeup_timeout; - uint32_t status, ns_timer = 0; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - timer_num = val_timer_get_info(TIMER_INFO_NUM_PLATFORM_TIMERS, 0); - if(!timer_num){ - val_print(AVS_PRINT_WARN, "\n No system timers implemented ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM5, 01)); - return; - } - - while(timer_num--) { - - if(val_timer_get_info(TIMER_INFO_IS_PLATFORM_TIMER_SECURE, timer_num)) - continue; - - ns_timer++; - status = val_timer_get_info(TIMER_INFO_SYS_TIMER_STATUS, 0); - if(status != AVS_STATUS_PASS){ - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM5, 02)); - return; - } - - //Read CNTACR to determine whether access permission from NS state is permitted - status = val_timer_skip_if_cntbase_access_not_allowed(timer_num); - if(status == AVS_STATUS_SKIP){ - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM5, 03)); - return; - } - - cnt_base_n = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N, timer_num); - if(cnt_base_n == 0){ - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM5, 04)); - return; - } - - intid = val_timer_get_info(TIMER_INFO_SYS_INTID, timer_num); - status = val_gic_install_isr(intid, isr5); - - if(status == 0) { - wakeup_set_failsafe(); - /* enable System timer */ - val_timer_set_system_timer((addr_t)cnt_base_n, timer_expire_val); - val_power_enter_semantic(SBSA_POWER_SEM_B); - wakeup_clear_failsafe(); - } else{ - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM5, 01)); - return; - } - } - - if(!ns_timer){ - val_print(AVS_PRINT_WARN, "\n No non-secure systimer implemented ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM4, 03)); - return; - } -} - -uint32_t -u001_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL, status_test = AVS_STATUS_FAIL; - - num_pe = 1; //This Timer test is run on single processor - - val_print(AVS_PRINT_TEST, TEST_DESC, 0); - - status_test = val_initialize_test(TEST_NUM, TEST_DESC1, num_pe, g_sbsa_level); - if (status_test != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload1, 0); - status = val_check_for_error(TEST_NUM, num_pe); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - status_test = val_initialize_test(TEST_NUM2, TEST_DESC2, num_pe, g_sbsa_level); - if (status_test != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM2, num_pe, payload2, 0); - status |= val_check_for_error(TEST_NUM2, num_pe); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM2)); - - /* Run this test if current exception level is EL2 */ - if (val_pe_reg_read(CurrentEL) == AARCH64_EL2) { - status_test = val_initialize_test(TEST_NUM3, TEST_DESC3, num_pe, g_sbsa_level); - if (status_test != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM3, num_pe, payload3, 0); - status |= val_check_for_error(TEST_NUM3, num_pe); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM3)); - } - - status_test = val_initialize_test(TEST_NUM4, TEST_DESC4, num_pe, g_sbsa_level); - if (status_test != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM4, num_pe, payload4, 0); - status |= val_check_for_error(TEST_NUM4, num_pe); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM4)); - - status_test = val_initialize_test(TEST_NUM5, TEST_DESC5, num_pe, g_sbsa_level); - if (status_test != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM5, num_pe, payload5, 0); - status |= val_check_for_error(TEST_NUM5, num_pe); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM5)); - - return status; -} diff --git a/test_pool/power_wakeup/test_u002.c b/test_pool/power_wakeup/test_u002.c deleted file mode 100755 index a8c1823c..00000000 --- a/test_pool/power_wakeup/test_u002.c +++ /dev/null @@ -1,275 +0,0 @@ -/** @file - * Copyright (c) 2016-2018, 2021-2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/sbsa_avs_pe.h" -#include "val/include/val_interface.h" - -#include "val/include/sbsa_avs_wakeup.h" -#include "val/include/sbsa_std_smc.h" - -#define TEST_NUM (AVS_WAKEUP_TEST_NUM_BASE + 6) -#define TEST_DESC "Test No-Wake from Power Semantic F" - -static uint32_t intid, wakeup_event, cnt_base_n=0; -static uint64_t timer_num, wd_num; - -#define WATCHDOG_SEMF 0x1 -#define SYSTIMER_SEMF 0x2 - -static -void -isr(void) -{ - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - uint32_t status; - - //val_print(AVS_PRINT_INFO, "\n Received interrupt ", 0); - if(wakeup_event == SYSTIMER_SEMF) - val_timer_disable_system_timer((addr_t)cnt_base_n); - else if(wakeup_event == WATCHDOG_SEMF) { - status = val_wd_set_ws0(wd_num, 0); - if (status) - val_print(AVS_PRINT_ERR, "\n Setting watchdog timeout failed", 0); - } - - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - val_gic_end_of_interrupt(intid); -} - -static -uint32_t -wakeup_event_for_semantic_f(void) -{ - uint32_t ns_timer = 0, ns_wdg = 0; - wd_num = val_wd_get_info(0, WD_INFO_COUNT); - - if(wd_num == 0){ - timer_num = val_timer_get_info(TIMER_INFO_NUM_PLATFORM_TIMERS, 0); - if(timer_num == 0) - return 0; - else{ - while(timer_num--) { - if(val_timer_get_info(TIMER_INFO_IS_PLATFORM_TIMER_SECURE, timer_num)) - continue; - else{ - ns_timer++; - break; - } - } - if(ns_timer == 0) - return 0; - intid = val_timer_get_info(TIMER_INFO_SYS_INTID, timer_num); - return SYSTIMER_SEMF; - } - } - else{ - while(wd_num--) { - if(val_wd_get_info(wd_num, WD_INFO_ISSECURE)) - continue; - else{ - ns_wdg++; - break; - } - } - if(ns_wdg == 0) - return 0; - intid = val_wd_get_info(wd_num, WD_INFO_GSIV); - return WATCHDOG_SEMF; - } - -} - -static -void -payload_target_pe(void) -{ - uint64_t data1, data2; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - //val_print(AVS_PRINT_INFO, "\n Print from target PE ", 0); - val_get_test_data(index, &data1, &data2); - val_pe_reg_write(VBAR_EL2, data2); - - val_gic_cpuif_init(); - val_suspend_pe(0,0,0); - // Set the status to indicate that target PE has resumed execution from sleep mode - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); -} - -static -void -payload_dummy(void) -{ - -} - -static -void -payload(void) -{ - uint64_t timeout = TIMEOUT_SMALL; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - uint32_t target_pe, status; - uint64_t timer_expire_ticks = TIMEOUT_SMALL; - - // Step1: Choose the index of the target PE - if ((index + 1) >= val_pe_get_num()) - target_pe = index-1; - else - target_pe = index+1; - - val_set_status(target_pe, RESULT_PENDING(g_sbsa_level, TEST_NUM)); - - // Step2: Get the wakeup event, which is either watchdog signal or system timer - // if none of these are present in a platform, skip the test - wakeup_event = wakeup_event_for_semantic_f(); - if(wakeup_event == 0){ - val_print(AVS_PRINT_WARN, "\n No Watchdogs and system timers present", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); - return; - } - - // Step3: Route the interrupt to target PE and install ISR - val_gic_route_interrupt_to_pe(intid, val_pe_get_mpid_index(target_pe)); - val_gic_install_isr(intid, isr); - - // Step4: val_execute_on_pe will call payload on target PE and target PE will do following: - // 1. program VBAR of target PE with the same vale as main PE - // 2. initialize gic cpu interface for target PE - // 3. place itself in sleep mode and expect the wakeup_event to wake it up - // 4. after wake-up it will update the status, which main PE will rely on - val_execute_on_pe(target_pe, payload_target_pe, val_pe_reg_read(VBAR_EL2)); - - // Step5: Program timer/watchdog, which on expiry will generate an interrupt - // and wake target PE - if(wakeup_event == SYSTIMER_SEMF){ - cnt_base_n = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N, timer_num); - val_timer_set_system_timer((addr_t)cnt_base_n, timer_expire_ticks); - } - else if(wakeup_event == WATCHDOG_SEMF){ - status = val_wd_set_ws0(wd_num, timer_expire_ticks); - if (status) { - val_print(AVS_PRINT_ERR, "\n Setting watchdof timeout failed", 0); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); - return; - } - } - - // Step6: Wait for target PE to update the status, if a timeout occurs that would mean that - // target PE was not able to wakeup - while((IS_TEST_PASS(val_get_status(target_pe))) && (--timeout)); - - if(timeout == 0) - val_print(AVS_PRINT_INFO, "\n Target PE was not able to wakeup succesfully from sleep \n due to watchdog/sytimer interrupt", 0); - - // Step7: Clear the pending/active interrupt if any - if(1 == val_gic_get_interrupt_state(intid)){ - val_print(AVS_PRINT_INFO, "\n Pending interrupt was seen for the 1st interrupt", 0); - if(wakeup_event == SYSTIMER_SEMF) - val_timer_disable_system_timer((addr_t)cnt_base_n); - else if(wakeup_event == WATCHDOG_SEMF) { - status = val_wd_set_ws0(wd_num, 0); - if (status) { - val_print(AVS_PRINT_ERR, "\n Setting watchdof timeout failed", 0); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03)); - return; - } - } - - val_gic_clear_interrupt(intid); - } - val_gic_end_of_interrupt(intid); // trigger END of interrupt for above interrupt - - // Step8: Wait for target PE to switch itself off, if it still doesn't switch off timeout - // value should be increased - timeout = TIMEOUT_SMALL; - while(--timeout); - - // Step9: Generate timer interrupt again, when target PE is off and make sure it doesn't wakeup - val_gic_route_interrupt_to_pe(intid, val_pe_get_mpid_index(target_pe)); - val_gic_install_isr(intid, isr); - timer_expire_ticks = TIMEOUT_SMALL; - - if(wakeup_event == SYSTIMER_SEMF) - val_timer_set_system_timer((addr_t)cnt_base_n, timer_expire_ticks); - else if(wakeup_event == WATCHDOG_SEMF) { - status = val_wd_set_ws0(wd_num, timer_expire_ticks); - if (status) { - val_print(AVS_PRINT_ERR, "\n Setting watchdof timeout failed", 0); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 04)); - return; - } - } - - val_print(AVS_PRINT_INFO, "\n Interrupt generating sequence triggered", 0); - - // Step10: wait for interrupt to become active or pendind for a timeout duration - timeout = TIMEOUT_MEDIUM; - while ((--timeout) && (0 == val_gic_get_interrupt_state(intid))); - - if(timeout == 0) - val_print(AVS_PRINT_INFO, "\n No pending interrupt was seen for the 2nd interrupt", 0); - else{ - val_print(AVS_PRINT_INFO, "\n Pending interrupt was seen for the 2nd interrupt", 0); - if(wakeup_event == SYSTIMER_SEMF) - val_timer_disable_system_timer((addr_t)cnt_base_n); - else if(wakeup_event == WATCHDOG_SEMF) { - status = val_wd_set_ws0(wd_num, 0); - if (status) { - val_print(AVS_PRINT_ERR, "\n Setting watchdof timeout failed", 0); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 05)); - return; - } - } - - val_gic_clear_interrupt(intid); - val_gic_end_of_interrupt(intid); // trigger END of interrupt for above interrupt - } - - // Step11: If event triggered woke up the target PE when it was off, then making PSCI call - // to switch it ON again would throw an error response, based on which the test is - // passed ot failed. - val_execute_on_pe(target_pe, payload_dummy, 0); - - if(IS_TEST_FAIL(val_get_status(target_pe)) || IS_RESULT_PENDING(val_get_status(target_pe))) - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - else - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - - return; -} - - -uint32_t -u002_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL, status_test = AVS_STATUS_FAIL; - - num_pe = 1; //This test is run on single processor, which will start and trigger interrupt to - // target PE. - - status_test = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - if (status_test != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} diff --git a/test_pool/io_virt/test_i007.c b/test_pool/smmu/operating_system/test_i001.c old mode 100755 new mode 100644 similarity index 89% rename from test_pool/io_virt/test_i007.c rename to test_pool/smmu/operating_system/test_i001.c index ea54b109..76e7e575 --- a/test_pool/io_virt/test_i007.c +++ b/test_pool/smmu/operating_system/test_i001.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020-2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -20,7 +20,8 @@ #include "val/include/sbsa_avs_smmu.h" -#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 7) +#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 1) +#define TEST_RULE "S_L3SM_01 " #define TEST_DESC "Check SMMU Version " static @@ -73,21 +74,21 @@ payload(void) } uint32_t -i007_entry(uint32_t num_pe) +i001_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/io_virt/test_i003.c b/test_pool/smmu/operating_system/test_i002.c old mode 100755 new mode 100644 similarity index 89% rename from test_pool/io_virt/test_i003.c rename to test_pool/smmu/operating_system/test_i002.c index df6ac6c3..e0a51d57 --- a/test_pool/io_virt/test_i003.c +++ b/test_pool/smmu/operating_system/test_i002.c @@ -20,8 +20,8 @@ #include "val/include/sbsa_avs_smmu.h" -#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 3) -#define TEST_RULE "S_L4SM_01, S_L4SM_02" +#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 2) +#define TEST_RULE "S_L4SM_01, S_L4SM_02, S_L5SM_01, S_L5SM_02" #define TEST_DESC "SMMU Compatibility Check " static @@ -48,7 +48,7 @@ payload(void) if (g_sbsa_level > 3) { val_print(AVS_PRINT_ERR, - "\n Smmuv3 should be supported Level %x", g_sbsa_level); + "\n SMMUv3 should be supported at level %x", g_sbsa_level); val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); return; } @@ -93,21 +93,21 @@ payload(void) } uint32_t -i003_entry(uint32_t num_pe) +i002_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/smmu/operating_system/test_i003.c b/test_pool/smmu/operating_system/test_i003.c new file mode 100644 index 00000000..f2c24a2e --- /dev/null +++ b/test_pool/smmu/operating_system/test_i003.c @@ -0,0 +1,100 @@ +/** @file + * Copyright (c) 2016-2018, 2021 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_smmu.h" +#include "val/include/sbsa_avs_pcie.h" + +#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 3) +#define TEST_RULE "B_SMMU_09" +#define TEST_DESC "SMMU revision and S-EL2 support " + +static +void +payload() +{ + + uint32_t num_smmu; + uint32_t index; + uint32_t s_el2; + uint32_t smmu_rev; + uint32_t minor; + uint32_t s1ts, s1p; + + index = val_pe_get_index_mpid(val_pe_get_mpid()); + s_el2 = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 36, 39); + + num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); + if (num_smmu == 0) { + val_print(AVS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 3)); + return; + } + + while (num_smmu--) { + smmu_rev = val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu); + + if (s_el2) { + if (smmu_rev == 2) { + s1ts = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv2_IDR0, num_smmu), 30, 30); + // Stage 1 translation functionality cannot be provided by SMMU v2 revision + if (s1ts) { + val_print(AVS_PRINT_ERR, + "\n SMMUv2 detected: revision must be v3.2 or higher ", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 4)); + return; + } + } + else if (smmu_rev == 3) { + minor = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_AIDR, num_smmu), 0, 3); + s1p = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR0, num_smmu), 1, 1); + // Stage 1 translation functionality cannot be provided by SMMU v3.0/3.1 revisions + if ((minor < 2) && s1p) { + val_print(AVS_PRINT_ERR, + "\n SMMUv3.%d detected: revision must be v3.2 or higher ", minor); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 4)); + return; + } + } + } + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 1)); +} + +uint32_t +i003_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/smmu/operating_system/test_i004.c b/test_pool/smmu/operating_system/test_i004.c new file mode 100644 index 00000000..ecb319a4 --- /dev/null +++ b/test_pool/smmu/operating_system/test_i004.c @@ -0,0 +1,100 @@ +/** @file + * Copyright (c) 2016-2018, 2021 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_smmu.h" +#include "val/include/sbsa_avs_pcie.h" + +#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 4) +#define TEST_RULE "B_SMMU_20" +#define TEST_DESC "SMMU Revision,S-EL2 support Hyp " + +static +void +payload() +{ + /* Check SMMU Revision & S-EL2 Support for Hypervisor */ + uint32_t num_smmu; + uint32_t index; + uint32_t s_el2; + uint32_t smmu_rev; + uint32_t minor; + uint32_t s2ts, s2p; + + index = val_pe_get_index_mpid(val_pe_get_mpid()); + s_el2 = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 36, 39); + + num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); + if (num_smmu == 0) { + val_print(AVS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 3)); + return; + } + + while (num_smmu--) { + smmu_rev = val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu); + + if (s_el2) { + if (smmu_rev == 2) { + s2ts = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv2_IDR0, num_smmu), 29, 29); + // Stage 2 translation functionality cannot be provided by SMMU v2 revision + if (s2ts) { + val_print(AVS_PRINT_ERR, + "\n SMMUv2 detected: revision must be v3.2 or higher ", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 4)); + return; + } + } + else if (smmu_rev == 3) { + minor = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_AIDR, num_smmu), 0, 3); + s2p = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR0, num_smmu), 0, 0); + // Stage 2 translation functionality cannot be provided by SMMU v3.0/3.1 revisions + if ((minor < 2) && s2p) { + val_print(AVS_PRINT_ERR, + "\n SMMUv3.%d detected: revision must be v3.2 or higher ", minor); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 4)); + return; + } + } + } + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 1)); +} + +uint32_t +i004_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/io_virt/test_i013.c b/test_pool/smmu/operating_system/test_i005.c similarity index 90% rename from test_pool/io_virt/test_i013.c rename to test_pool/smmu/operating_system/test_i005.c index 98c345e1..a6f60f0f 100644 --- a/test_pool/io_virt/test_i013.c +++ b/test_pool/smmu/operating_system/test_i005.c @@ -21,7 +21,8 @@ #include "val/include/sbsa_avs_smmu.h" #include "val/include/sbsa_avs_pcie.h" -#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 13) +#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 5) +#define TEST_RULE "S_L6SM_01" #define TEST_DESC "Check SMMU Coherent Access Support" static @@ -74,21 +75,21 @@ payload(void) } uint32_t -i013_entry(uint32_t num_pe) +i005_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/io_virt/test_i014.c b/test_pool/smmu/operating_system/test_i006.c similarity index 90% rename from test_pool/io_virt/test_i014.c rename to test_pool/smmu/operating_system/test_i006.c index b3c1981a..e2ceeb4c 100644 --- a/test_pool/io_virt/test_i014.c +++ b/test_pool/smmu/operating_system/test_i006.c @@ -21,7 +21,8 @@ #include "val/include/sbsa_avs_smmu.h" #include "val/include/sbsa_avs_pcie.h" -#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 14) +#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 6) +#define TEST_RULE "S_L6SM_02" #define TEST_DESC "Check SMMU HTTU Support " static @@ -74,21 +75,21 @@ payload(void) } uint32_t -i014_entry(uint32_t num_pe) +i006_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/io_virt/test_i009.c b/test_pool/smmu/operating_system/test_i007.c similarity index 76% rename from test_pool/io_virt/test_i009.c rename to test_pool/smmu/operating_system/test_i007.c index 21a4498d..c57b8fe6 100644 --- a/test_pool/io_virt/test_i009.c +++ b/test_pool/smmu/operating_system/test_i007.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -21,12 +21,13 @@ #include "val/include/sbsa_avs_smmu.h" #include "val/include/sbsa_avs_pcie.h" -#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 9) -#define TEST_DESC "Check SMMU 16 Bit ASID Support " +#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 7) +#define TEST_RULE "S_L6SM_03" +#define TEST_DESC "Check SMMU MSI Support " static void -payload(void) +payload() { uint64_t data; @@ -38,32 +39,25 @@ payload(void) return; } - data = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); - - if (data == 0) { - val_print(AVS_PRINT_WARN, "\n PCIe Subsystem not discovered ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); - return; - } - num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { val_print(AVS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); return; } while (num_smmu--) { if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { val_print(AVS_PRINT_WARN, "\n Not valid for SMMU v2 ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 04)); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); return; } - data = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR0, num_smmu), 12, 12); + data = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR0, num_smmu), 13, 13); - if (data != 1) { + /* Check If SMMU_IDR0.MSI[13:13] == 0b1*/ + if (data != 0b1) { val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); return; } @@ -73,21 +67,21 @@ payload(void) } uint32_t -i009_entry(uint32_t num_pe) +i007_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/io_virt/test_hyp_i005.c b/test_pool/smmu/operating_system/test_i008.c similarity index 87% rename from test_pool/io_virt/test_hyp_i005.c rename to test_pool/smmu/operating_system/test_i008.c index 53ad966b..64c8b2dd 100644 --- a/test_pool/io_virt/test_hyp_i005.c +++ b/test_pool/smmu/operating_system/test_i008.c @@ -22,9 +22,9 @@ #include "val/include/sbsa_avs_smmu.h" #include "val/include/sbsa_avs_pcie.h" -#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 20) +#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 8) #define TEST_RULE "B_SMMU_23" -#define TEST_DESC "Check SMMU 16 Bit VMID Support " +#define TEST_DESC "Check SMMU 16 Bit VMID Support " static void @@ -67,21 +67,21 @@ payload() } uint32_t -hyp_i005_entry(uint32_t num_pe) +i008_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, 6); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, 6, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(6, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(6, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/io_virt/test_os_i005.c b/test_pool/smmu/operating_system/test_i009.c similarity index 90% rename from test_pool/io_virt/test_os_i005.c rename to test_pool/smmu/operating_system/test_i009.c index 09f9604c..d7b47156 100644 --- a/test_pool/io_virt/test_os_i005.c +++ b/test_pool/smmu/operating_system/test_i009.c @@ -21,7 +21,7 @@ #include "val/include/sbsa_avs_smmu.h" #include "val/include/sbsa_avs_pe.h" -#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 21) +#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 9) #define TEST_RULE "B_SMMU_03" #define TEST_DESC "Check Large Virtual Addr Support " @@ -73,22 +73,22 @@ payload() } uint32_t -os_i005_entry(uint32_t num_pe) +i009_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, 6); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, 6, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(6, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(6, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/io_virt/test_os_i006.c b/test_pool/smmu/operating_system/test_i010.c similarity index 89% rename from test_pool/io_virt/test_os_i006.c rename to test_pool/smmu/operating_system/test_i010.c index 8b652c72..eb710c40 100644 --- a/test_pool/io_virt/test_os_i006.c +++ b/test_pool/smmu/operating_system/test_i010.c @@ -21,9 +21,9 @@ #include "val/include/sbsa_avs_smmu.h" #include "val/include/sbsa_avs_pe.h" -#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 22) +#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 10) #define TEST_RULE "B_SMMU_04, B_SMMU_05" -#define TEST_DESC "Check TLB Range Invalidation " +#define TEST_DESC "Check TLB Range Invalidation " static void @@ -77,22 +77,22 @@ payload() } uint32_t -os_i006_entry(uint32_t num_pe) +i010_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, 6); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, 6, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(6, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(6, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/io_virt/test_os_i007.c b/test_pool/smmu/operating_system/test_i011.c similarity index 89% rename from test_pool/io_virt/test_os_i007.c rename to test_pool/smmu/operating_system/test_i011.c index 2e827c4c..cccb3b4b 100644 --- a/test_pool/io_virt/test_os_i007.c +++ b/test_pool/smmu/operating_system/test_i011.c @@ -22,9 +22,9 @@ #include "val/include/sbsa_avs_smmu.h" #include "val/include/sbsa_avs_pcie.h" -#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 23) +#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 11) #define TEST_RULE "B_SMMU_13" -#define TEST_DESC "Check SMMU 16 Bit ASID Support " +#define TEST_DESC "Check SMMU 16 Bit ASID Support " static void @@ -79,21 +79,21 @@ payload() } uint32_t -os_i007_entry(uint32_t num_pe) +i011_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, 6); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, 6, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(6, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(6, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/io_virt/test_os_i008.c b/test_pool/smmu/operating_system/test_i012.c similarity index 90% rename from test_pool/io_virt/test_os_i008.c rename to test_pool/smmu/operating_system/test_i012.c index da8a944f..24d2d9b2 100644 --- a/test_pool/io_virt/test_os_i008.c +++ b/test_pool/smmu/operating_system/test_i012.c @@ -22,9 +22,9 @@ #include "val/include/sbsa_avs_pcie.h" #include "val/include/sbsa_avs_pe.h" -#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 24) +#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 12) #define TEST_RULE "B_SMMU_14" -#define TEST_DESC "Check SMMU Endianess Support " +#define TEST_DESC "Check SMMU Endianess Support " static void @@ -88,21 +88,21 @@ payload() } uint32_t -os_i008_entry(uint32_t num_pe) +i012_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, 6); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, 6, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(6, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(6, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/smmu/operating_system/test_i013.c b/test_pool/smmu/operating_system/test_i013.c new file mode 100644 index 00000000..6a8ca189 --- /dev/null +++ b/test_pool/smmu/operating_system/test_i013.c @@ -0,0 +1,108 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" +#include "val/include/sbsa_avs_iovirt.h" +#include "val/include/sbsa_avs_pe.h" + +#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 13) +#define TEST_RULE "S_L7SM_01" +#define TEST_DESC "Check if all DMA reqs behind SMMU " + +static +void +payload() +{ + + uint32_t num_pcie_rc, num_named_comp; + uint32_t i, test_fails = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 7) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* check whether all DMA capable PCIe root complexes are behind a SMMU */ + num_pcie_rc = val_iovirt_get_pcie_rc_info(NUM_PCIE_RC, 0); + + for (i = 0; i < num_pcie_rc; i++) { + /* print info fields */ + val_print(AVS_PRINT_DEBUG, "\n RC segment no : 0x%llx", + val_iovirt_get_pcie_rc_info(RC_SEGMENT_NUM, i)); + val_print(AVS_PRINT_DEBUG, "\n CCA attribute : 0x%x", + val_iovirt_get_pcie_rc_info(RC_MEM_ATTRIBUTE, i)); + val_print(AVS_PRINT_DEBUG, "\n SMMU base addr : 0x%llx\n", + val_iovirt_get_pcie_rc_info(RC_SMMU_BASE, i)); + + if (val_iovirt_get_pcie_rc_info(RC_MEM_ATTRIBUTE, i) == 0x1 && + val_iovirt_get_pcie_rc_info(RC_SMMU_BASE, i) == 0) { + val_print(AVS_PRINT_ERR, + "\n DMA capable PCIe root port with segment no: %llx not behind a SMMU.", + val_iovirt_get_pcie_rc_info(RC_SEGMENT_NUM, i)); + test_fails++; + } + } + + /* check whether all DMA capable Named component requestors are behind a SMMU */ + num_named_comp = val_iovirt_get_named_comp_info(NUM_NAMED_COMP, 0); + for (i = 0; i < num_named_comp; i++) { + /* print info fields */ + val_print(AVS_PRINT_DEBUG, "\n Named component :", 0); + val_print(AVS_PRINT_DEBUG, + (char8_t *)val_iovirt_get_named_comp_info(NAMED_COMP_DEV_OBJ_NAME, i), 0); + val_print(AVS_PRINT_DEBUG, "\n CCA attribute : 0x%x", + val_iovirt_get_named_comp_info(NAMED_COMP_CCA_ATTR, i)); + val_print(AVS_PRINT_DEBUG, "\n SMMU base addr : 0x%llx\n", + val_iovirt_get_named_comp_info(NAMED_COMP_SMMU_BASE, i)); + if (val_iovirt_get_named_comp_info(NAMED_COMP_CCA_ATTR, i) == 0x1 && + val_iovirt_get_named_comp_info(NAMED_COMP_SMMU_BASE, i) == 0) { + val_print(AVS_PRINT_ERR, + "\n DMA capable named component with namespace path: ", 0); + val_print(AVS_PRINT_ERR, + (char8_t *)val_iovirt_get_named_comp_info(NAMED_COMP_DEV_OBJ_NAME, i), 0); + val_print(AVS_PRINT_ERR, " not behind a SMMU.", 0); + test_fails++; + } + } + + if (test_fails) + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +i013_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; /* This test is run on single processor */ + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/smmu/operating_system/test_i014.c b/test_pool/smmu/operating_system/test_i014.c new file mode 100644 index 00000000..438ae0df --- /dev/null +++ b/test_pool/smmu/operating_system/test_i014.c @@ -0,0 +1,120 @@ +/** @file + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_iovirt.h" +#include "val/include/sbsa_avs_smmu.h" +#include "val/include/sbsa_avs_pcie.h" + +#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 14) +#define TEST_RULE "S_L7SM_03, S_L7SM_04" +#define TEST_DESC "Check SMMUv3 PMU Extension " + +static +void +payload() +{ + + uint32_t num_smmu; + uint32_t num_pmcg = 0; + uint32_t i = 0; + uint32_t smmu_version; + uint64_t smmu_base = 0; + uint64_t pmcg_base = 0; + uint64_t pmcg_node_ref = 0; + uint64_t num_pmcg_count = 0; + uint64_t num_pmcg_found = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 6) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); + num_pmcg = val_iovirt_get_pmcg_info(PMCG_NUM_CTRL, 0); + + if (num_smmu == 0) { + val_print(AVS_PRINT_DEBUG, "\n No SMMU Controllers are discovered ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + while (num_smmu--) { + smmu_version = val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu); + if (smmu_version != 3) { + val_print(AVS_PRINT_DEBUG, + "\n Valid for only SMMU v3, smmu version %d", smmu_version); + continue; + } + + smmu_base = val_smmu_get_info(SMMU_CTRL_BASE, num_smmu); + + num_pmcg_found = 0; + /* Each SMMUv3 should contain atleast 1 PMCG*/ + for (i = 0; i < num_pmcg; i++) { + pmcg_node_ref = val_iovirt_get_pmcg_info(PMCG_NODE_REF, i); + if (smmu_base == pmcg_node_ref) { + pmcg_base = val_iovirt_get_pmcg_info(PMCG_CTRL_BASE, i); + /*Check if SMMU_PMCG_CFGR.NCTR > 4*/ + num_pmcg_count = VAL_EXTRACT_BITS(val_mmio_read(pmcg_base + SMMU_PMCG_CFGR), 0, 5); + /*No of counters in a group is SMMU_PMCG_CFGR.NCTR + 1*/ + num_pmcg_count++; + /* Each PMCG should have atleast 4 counters*/ + if (num_pmcg_count < 4) { + val_print(AVS_PRINT_ERR, "\n PMCG has less then 4 counters", 0); + val_print(AVS_PRINT_ERR, + "\n No of PMCG counters :%d ", num_pmcg_count); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + num_pmcg_found++; + } + } + + if (num_pmcg_found == 0) { + val_print(AVS_PRINT_ERR, "\n PMU Extension not implimented for SMMUv3", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } + + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +i014_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/io_virt/test_os_i009.c b/test_pool/smmu/operating_system/test_i015.c similarity index 82% rename from test_pool/io_virt/test_os_i009.c rename to test_pool/smmu/operating_system/test_i015.c index 38ff8f66..f3a12290 100644 --- a/test_pool/io_virt/test_os_i009.c +++ b/test_pool/smmu/operating_system/test_i015.c @@ -21,9 +21,9 @@ #include "val/include/sbsa_avs_pe.h" #include "val/include/sbsa_avs_smmu.h" -#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 25) +#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 15) #define TEST_RULE "B_SMMU_11, B_SMMU_22" -#define TEST_DESC "Check system for MPAM support " +#define TEST_DESC "Check system for MPAM support " static void @@ -47,13 +47,13 @@ payload() num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); if (num_smmu == 0) { val_print(AVS_PRINT_DEBUG, "\n No SMMU Controllers are discovered ", 0); - val_set_status(index, RESULT_SKIP(6, TEST_NUM, 3)); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 3)); return; } if (!(pe_mpam || frac)) { val_print(AVS_PRINT_DEBUG, "\n No MPAM controlled resources present ", 0); - val_set_status(index, RESULT_SKIP(6, TEST_NUM, 3)); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 3)); return; } @@ -62,7 +62,7 @@ payload() if (smmu_rev < 3) { // MPAM support not required for SMMUv2 and below val_print(AVS_PRINT_DEBUG, "\n SMMU revision v2 or lower detected ", 0); - val_set_status(index, RESULT_SKIP(6, TEST_NUM, 4)); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 4)); return; } else { @@ -78,7 +78,7 @@ payload() if (!(mpam && max_id)) { val_print(AVS_PRINT_ERR, "\n SMMU without MPAM support detected ", 0); - val_set_status(index, RESULT_FAIL(6, TEST_NUM, 4)); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 4)); return; } } @@ -86,31 +86,31 @@ payload() // MPAM support not required for SMMUv3.0/3.1 val_print(AVS_PRINT_WARN, "\n SMMU revision v3.0/3.1 detected ", 0); - val_set_status(index, RESULT_SKIP(6, TEST_NUM, 4)); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 4)); return; } } } - val_set_status(index, RESULT_PASS(6, TEST_NUM, 1)); + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 1)); } uint32_t -os_i009_entry(uint32_t num_pe) +i015_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, 6); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); - val_report_status(0, SBSA_AVS_END(6, TEST_NUM)); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; } diff --git a/test_pool/smmu/operating_system/test_i016.c b/test_pool/smmu/operating_system/test_i016.c new file mode 100644 index 00000000..84b9ced2 --- /dev/null +++ b/test_pool/smmu/operating_system/test_i016.c @@ -0,0 +1,137 @@ +/** @file + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" +#include "val/include/sbsa_avs_iovirt.h" + +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_smmu.h" + +#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 16) +#define TEST_RULE "S_L7SM_02" +#define TEST_DESC "Check for SMMU/CATU in ETR Path " + +#define MAX_NUM_ETR 6 + +static +void +payload(void) +{ + uint32_t index = 0; + uint32_t status = 0; + uint32_t etr_count = 0; + uint32_t smmu_found = 0; + uint32_t num_named_comp = 0; + char etr_path[MAX_NUM_ETR][MAX_NAMED_COMP_LENGTH]; + uint32_t i = 0; + uint32_t j = 0; + + index = val_pe_get_index_mpid(val_pe_get_mpid()); + memset(etr_path, 0, sizeof(etr_path)); + + /*Check for ETR devices using ETR using unique HID (ARMHC501)*/ + status = val_get_device_path("ARMHC501", etr_path); + if (status != 0) { + val_print(AVS_PRINT_ERR, "\n Unable to get ETR device info from ACPI namespace", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 1)); + return; + } + + if ((char)etr_path[0][0] == '\0') { + val_print(AVS_PRINT_ERR, "\n No ETR devices are discovered ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 1)); + return; + } else { + /*Counting num of ETR Devices*/ + for (i = 0; i < MAX_NUM_ETR; i++) { + if ((char)etr_path[i][0] != '\0') + etr_count++; + } + } + val_print(AVS_PRINT_DEBUG, "\n Num of ETR devices found etr_count: %d ", etr_count); + + num_named_comp = val_iovirt_get_named_comp_info(NUM_NAMED_COMP, 0); + val_print(AVS_PRINT_DEBUG, "\n NUM Named component : %d", num_named_comp); + + /*ETR device should be behind SMMU or CATU*/ + for (i = 0; i < etr_count; i++) { + for (j = 0; j < num_named_comp; j++) { + smmu_found = 0; + /* print info fields */ + val_print(AVS_PRINT_DEBUG, "\n Named component :", 0); + val_print(AVS_PRINT_DEBUG, + (char8_t *)val_iovirt_get_named_comp_info(NAMED_COMP_DEV_OBJ_NAME, j), 0); + + /*Check the ETR and Named Componnet paths are matching*/ + if (!val_strncmp((char8_t *)val_iovirt_get_named_comp_info(NAMED_COMP_DEV_OBJ_NAME, j), + (char8_t *)etr_path[i], 9)) { + + /*Check Named Component with ETR path have SMMU*/ + if (val_iovirt_get_named_comp_info(NAMED_COMP_SMMU_BASE, j)) { + smmu_found++; + break; + } + } + } + + /*SMMU not found in ETR path, check for CATU*/ + if (!smmu_found) { + /*Check for CATU in the path of ETR device*/ + val_print(AVS_PRINT_DEBUG, "\n SMMU not found in ETR Path at index %d", i); + + /*Check the CATU in ETR path*/ + status = val_smmu_is_etr_behind_catu((char8_t *)etr_path[i]); + if (status == NOT_IMPLEMENTED) { + val_print(AVS_PRINT_DEBUG, + "\n val_smmu_is_etr_behind_catu API not implemented", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 2)); + return; + } else if (status) { + val_print(AVS_PRINT_DEBUG, "\n No CATU found in ETR path at index %d", i); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 2)); + return; + } + } + + if (!smmu_found) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 3)); + return; + } + } + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 1)); +} + +uint32_t +i016_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/timer_wd/test_t001.c b/test_pool/timer_wd/test_t001.c deleted file mode 100644 index f6b64881..00000000 --- a/test_pool/timer_wd/test_t001.c +++ /dev/null @@ -1,65 +0,0 @@ -/** @file - * Copyright (c) 2016-2018,2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/val_interface.h" - -#include "val/include/sbsa_avs_timer.h" - -#define TEST_NUM (AVS_TIMER_TEST_NUM_BASE + 1) -#define TEST_DESC "Check Counter Frequency " - -static -void -payload(void) -{ - - uint32_t counter_freq; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - counter_freq = val_timer_get_info(TIMER_INFO_CNTFREQ, 0); - val_print(AVS_PRINT_DEBUG, "\n Counter frequency is %x ", counter_freq); - - if (counter_freq > 10*1000*1000) { - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - return; - } - - val_print(AVS_PRINT_ERR, "\n Counter frequency is %x ", counter_freq); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - -} - -uint32_t -t001_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL; - - num_pe = 1; //This Timer test is run on single processor - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} diff --git a/test_pool/timer_wd/test_t002.c b/test_pool/timer_wd/test_t002.c deleted file mode 100644 index 00e81885..00000000 --- a/test_pool/timer_wd/test_t002.c +++ /dev/null @@ -1,88 +0,0 @@ -/** @file - * Copyright (c) 2016-2018,2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/val_interface.h" - -#include "val/include/sbsa_avs_timer.h" - -#define TEST_NUM (AVS_TIMER_TEST_NUM_BASE + 2) -#define TEST_DESC "Check EL0-Phy timer interrupt " - -static uint32_t intid; - -static -void -isr(void) -{ - val_timer_set_phy_el1(0); - val_print(AVS_PRINT_INFO, "\n Received interrupt ", 0); - val_set_status(0, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - val_gic_end_of_interrupt(intid); -} - - -static -void -payload(void) -{ - - uint32_t timeout = TIMEOUT_LARGE; - uint32_t timer_expire_val = 100; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID, 0); - - if (intid != 30) { - timeout = 0; - val_print(AVS_PRINT_ERR, "\n Incorrect PPI value %d ", intid); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); - return; - } - - val_gic_install_isr(intid, isr); - - val_timer_set_phy_el1(timer_expire_val); - - while ((--timeout > 0) && (IS_RESULT_PENDING(val_get_status(index)))); - - if (timeout == 0){ - val_print(AVS_PRINT_ERR, "\n EL0-Phy timer interrupt not received on %d ", intid); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - } - -} - -uint32_t -t002_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL; - - num_pe = 1; // This Timer test is run on single processor - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} diff --git a/test_pool/timer_wd/test_t003.c b/test_pool/timer_wd/test_t003.c deleted file mode 100644 index d74c0cff..00000000 --- a/test_pool/timer_wd/test_t003.c +++ /dev/null @@ -1,88 +0,0 @@ -/** @file - * Copyright (c) 2016-2018,2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/val_interface.h" - -#include "val/include/sbsa_avs_timer.h" - -#define TEST_NUM (AVS_TIMER_TEST_NUM_BASE + 3) -#define TEST_DESC "Check EL0-Virtual timer interrupt " - -static uint32_t intid; - -static -void -isr(void) -{ - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - /* We received our interrupt, so disable timer from generating further interrupts */ - val_timer_set_vir_el1(0); - val_print(AVS_PRINT_INFO, "\n Received interrupt ", 0); - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - val_gic_end_of_interrupt(intid); -} - - -static -void -payload(void) -{ - - uint32_t timeout = TIMEOUT_LARGE; - uint64_t timer_expire_val = 100; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - intid = val_timer_get_info(TIMER_INFO_VIR_EL1_INTID, 0); - - if (intid != 27) { - val_print(AVS_PRINT_ERR, "\n Incorrect PPI value %d ", intid); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); - } - - val_gic_install_isr(intid, isr); - - val_timer_set_vir_el1(timer_expire_val); - - while ((--timeout > 0) && (IS_RESULT_PENDING(val_get_status(index)))); - - if (timeout == 0) { - val_print(AVS_PRINT_ERR, "\n EL0-Virtual timer interrupt not received on %d ", intid); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - } - -} - -uint32_t -t003_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL; - - num_pe = 1; //This Timer test is run on single processor - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} diff --git a/test_pool/timer_wd/test_t004.c b/test_pool/timer_wd/test_t004.c deleted file mode 100644 index 4755746d..00000000 --- a/test_pool/timer_wd/test_t004.c +++ /dev/null @@ -1,94 +0,0 @@ -/** @file - * Copyright (c) 2016-2018,2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/val_interface.h" - -#include "val/include/sbsa_avs_timer.h" - -#define TEST_NUM (AVS_TIMER_TEST_NUM_BASE + 4) -#define TEST_DESC "Check EL2-phy timer interrupt " - -static uint32_t intid; - -static -void -isr(void) -{ - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - /* We received our interrupt, so disable timer from generating further interrupts */ - val_timer_set_phy_el2(0); - val_print(AVS_PRINT_INFO, "\n Received interrupt ", 0); - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - val_gic_end_of_interrupt(intid); -} - - -static -void -payload(void) -{ - - uint32_t timeout = TIMEOUT_LARGE; - uint64_t timer_expire_val = 100; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - intid = val_timer_get_info(TIMER_INFO_PHY_EL2_INTID, 0); - if (intid != 26) { - val_print(AVS_PRINT_ERR, "\n Incorrect PPI value %d ", intid); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); - return; - } - - val_gic_install_isr(intid, isr); - - val_timer_set_phy_el2(timer_expire_val); - - while ((--timeout > 0) && (IS_RESULT_PENDING(val_get_status(index)))); - - if (timeout == 0) { - val_print(AVS_PRINT_ERR, "\n EL2-Phy timer interrupt not received on %d ", intid); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - } - -} - -uint32_t -t004_entry(uint32_t num_pe) -{ - - uint32_t error_flag = 0; - uint32_t status = AVS_STATUS_FAIL; - - num_pe = 1; //This Timer test is run on single processor - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - error_flag = val_check_for_error(TEST_NUM, num_pe); - - if (!error_flag) - status = AVS_STATUS_PASS; - else - status = AVS_STATUS_FAIL; - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - return status; - -} diff --git a/test_pool/timer_wd/test_t005.c b/test_pool/timer_wd/test_t005.c deleted file mode 100644 index 30c67bde..00000000 --- a/test_pool/timer_wd/test_t005.c +++ /dev/null @@ -1,105 +0,0 @@ -/** @file - * Copyright (c) 2016-2018,2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/val_interface.h" - -#include "val/include/sbsa_avs_timer.h" -#include "val/include/sbsa_avs_pe.h" - -#define TEST_NUM (AVS_TIMER_TEST_NUM_BASE + 5) -#define TEST_DESC "Check EL2-Virtual timer interrupt " - -static uint32_t intid; - -static -void -isr(void) -{ - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - /* We received our interrupt, so disable timer from generating further interrupts */ - val_timer_set_vir_el2(0); - val_print(AVS_PRINT_INFO, "\n Received interrupt ", 0); - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - val_gic_end_of_interrupt(intid); -} - - - -static -void -payload(void) -{ - - uint32_t timeout = TIMEOUT_LARGE; - uint64_t timer_expire_val = 100; - uint64_t data = 0; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - /* This test is run only when ARM v8.1 Virtualized Host Extensions are supported */ - data = val_pe_reg_read(ID_AA64MMFR1_EL1); - - if (((data >> 8) & 0xF) == 0) { - val_print(AVS_PRINT_WARN, "\n v8.1 VHE not supported on this PE ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); - return; - } - - intid = val_timer_get_info(TIMER_INFO_VIR_EL2_INTID, 0); - - if (intid != 28) { - val_print(AVS_PRINT_ERR, "\n Incorrect PPI value %d ", intid); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - return; - } - - val_gic_install_isr(intid, isr); - - val_timer_set_vir_el2(timer_expire_val); - - while ((--timeout > 0) && (IS_RESULT_PENDING(val_get_status(index)))); - - if (timeout == 0) { - val_print(AVS_PRINT_ERR, "\n EL2-Virtual timer interrupt not received on %d ", intid); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - } - -} - -/** - @brief Check interrupt generation from EL2-Virtual timer. - Depends on ARM V8.1 VHE Extensions. -**/ -uint32_t -t005_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL; - - num_pe = 1; //This Timer test is run on single processor - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} diff --git a/test_pool/timer_wd/test_t006.c b/test_pool/timer_wd/test_t006.c deleted file mode 100644 index 096ac3a6..00000000 --- a/test_pool/timer_wd/test_t006.c +++ /dev/null @@ -1,71 +0,0 @@ -/** @file - * Copyright (c) 2016-2018,2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/val_interface.h" - -#include "val/include/sbsa_avs_timer.h" -#include "val/include/sbsa_avs_pe.h" - -#define TEST_NUM (AVS_TIMER_TEST_NUM_BASE + 6) -#define TEST_DESC "SYS Timer if PE Timer not ON " - -static -void -payload(void) -{ - - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - if (val_timer_get_info(TIMER_INFO_NUM_PLATFORM_TIMERS, 0) == 0) { - val_print(AVS_PRINT_INFO, "\n Physical EL1 timer flag = %x", val_timer_get_info(TIMER_INFO_PHY_EL1_FLAGS, 0)); - val_print(AVS_PRINT_INFO, "\n Physical EL2 timer flag = %x", val_timer_get_info(TIMER_INFO_PHY_EL2_FLAGS, 0)); - val_print(AVS_PRINT_INFO, "\n Virtual EL1 timer flag = %x", val_timer_get_info(TIMER_INFO_VIR_EL1_FLAGS, 0)); - - if((val_timer_get_info(TIMER_INFO_PHY_EL1_FLAGS, 0) & SBSA_TIMER_FLAG_ALWAYS_ON) && - (val_timer_get_info(TIMER_INFO_PHY_EL2_FLAGS, 0) & SBSA_TIMER_FLAG_ALWAYS_ON) && - (val_timer_get_info(TIMER_INFO_VIR_EL1_FLAGS, 0) & SBSA_TIMER_FLAG_ALWAYS_ON)) { - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - } else { - val_print(AVS_PRINT_ERR, "\n PE Timers are not always-on. ", 0); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - } - } else { - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 02)); - } - -} - -uint32_t -t006_entry(uint32_t num_pe) -{ - - uint32_t status = AVS_STATUS_FAIL; - - num_pe = 1; //This Timer test is run on single processor - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - return status; - -} diff --git a/test_pool/timer_wd/test_t007.c b/test_pool/timer_wd/test_t007.c deleted file mode 100755 index badf3694..00000000 --- a/test_pool/timer_wd/test_t007.c +++ /dev/null @@ -1,162 +0,0 @@ -/** @file - * Copyright (c) 2016-2018,2021-2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ -#include "val/include/sbsa_avs_val.h" -#include "val/include/val_interface.h" - -#include "val/include/sbsa_avs_timer.h" -#include "val/include/sbsa_avs_pe.h" - -#define TEST_NUM (AVS_TIMER_TEST_NUM_BASE + 7) -#define TEST_DESC "CNTCTLBase & CNTBaseN access " - -#define ARBIT_VALUE 0xA000 - -static -void -payload(void) -{ - - uint64_t cnt_ctl_base, cnt_base_n; - uint32_t data; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - uint64_t timer_num = val_timer_get_info(TIMER_INFO_NUM_PLATFORM_TIMERS, 0); - uint64_t data1; - - if (!timer_num) { - val_print(AVS_PRINT_WARN, "\n No System timers are defined ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 0x1)); - return; - } - - while(timer_num){ - --timer_num; //array index starts from 0, so subtract 1 from count - - if (val_timer_get_info(TIMER_INFO_IS_PLATFORM_TIMER_SECURE, timer_num)) - continue; //Skip Secure Timer - - cnt_ctl_base = val_timer_get_info(TIMER_INFO_SYS_CNTL_BASE, timer_num); - cnt_base_n = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N, timer_num); - - if (cnt_ctl_base == 0) { - val_print(AVS_PRINT_WARN, "\n CNTCTL BASE_N is zero ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 0x2)); - return; - } - - data = val_mmio_read(cnt_ctl_base + 0x8); - val_mmio_write(cnt_ctl_base + 0x8, 0xFFFFFFFF); - if(data != val_mmio_read(cnt_ctl_base + 0x8)) { - val_print(AVS_PRINT_ERR, "\n Read-write check failed for CNTCTLBase.CNTTIDR", 0); - val_print(AVS_PRINT_ERR, ", expected value %x ", data); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 1)); - return; - } - - if (cnt_base_n == 0) { - val_print(AVS_PRINT_WARN, "\n CNT_BASE_N is zero ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 0x3)); - return; - } - - // Read CNTPCT register - data1 = val_mmio_read64(cnt_base_n + 0x0); - val_print(AVS_PRINT_DEBUG, "\n CNTPCT Read value = 0x%llx ", data1); - - // Writes to Read-Only registers should be ignore - val_mmio_write64(cnt_base_n + 0x0, (data1 - ARBIT_VALUE)); - - if (val_mmio_read64(cnt_base_n + 0x0) < data1) { - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 2)); - val_print(AVS_PRINT_ERR, "\n CNTBaseN: CNTPCT reg should be read-only ", 0); - return; - } - - // Read CNTVCT register - data1 = val_mmio_read64(cnt_base_n + 0x8); - val_print(AVS_PRINT_DEBUG, "\n CNTVCT Read value = 0x%llx ", data1); - - // Writes to Read-Only registers should be ignore - val_mmio_write64(cnt_base_n + 0x8, (data1 - ARBIT_VALUE)); - - if (val_mmio_read64(cnt_base_n + 0x8) < data1) { - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 3)); - val_print(AVS_PRINT_ERR, "\n CNTBaseN: CNTVCT reg should be read-only ", 0); - return; - } - - // Read CNTFRQ register - data = val_mmio_read(cnt_base_n + 0x10); - val_print(AVS_PRINT_DEBUG, "\n CNTFRQ Read value = 0x%x ", - data); - - // Writes to Read-Only registers should be ignore - val_mmio_write(cnt_base_n + 0x10, (data - ARBIT_VALUE)); - - if (val_mmio_read(cnt_base_n + 0x10) != data) { - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 4)); - val_print(AVS_PRINT_ERR, "\n CNTBaseN: CNTFRQ reg should be read-only ", 0); - return; - } - - data = 0x3; - val_mmio_write(cnt_base_n + 0x2C, data); - if(data != (val_mmio_read(cnt_base_n + 0x2C) & 0x3)) { - val_print(AVS_PRINT_ERR, "\n Read-write check failed for CNTBaseN.CNTP_CTL", 0); - val_print(AVS_PRINT_ERR, ", expected value %x ", data); - val_print(AVS_PRINT_ERR, "\n Read value %x ", val_mmio_read(cnt_base_n + 0x2C)); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 0x5)); - val_mmio_write(cnt_base_n + 0x2C, 0x0); // Disable the timer before return - return; - } - val_mmio_write(cnt_base_n + 0x2C, 0x0); // Disable timer - - data1 = 0xFF00FF00FF00FF00; - /* Write a random value to CNTP_CVAL*/ - val_mmio_write64(cnt_base_n + 0x20, data1); - - if (data1 != val_mmio_read64(cnt_base_n + 0x20)) { - val_print(AVS_PRINT_ERR, "\n Read-write check failed for " - "CNTBaseN.CNTP_CVAL, read value %llx ", - val_mmio_read64(cnt_base_n + 0x20)); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 6)); - return; - } - - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - } - -} - -uint32_t -t007_entry(uint32_t num_pe) -{ - uint32_t status = AVS_STATUS_FAIL; - - num_pe = 1; //This Timer test is run on single processor - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} diff --git a/test_pool/timer_wd/test_t008.c b/test_pool/timer_wd/test_t008.c deleted file mode 100644 index 94060e01..00000000 --- a/test_pool/timer_wd/test_t008.c +++ /dev/null @@ -1,128 +0,0 @@ -/** @file - * Copyright (c) 2016-2018, 2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ -#include "val/include/sbsa_avs_val.h" -#include "val/include/val_interface.h" - -#include "val/include/sbsa_avs_timer.h" -#include "val/include/sbsa_avs_pe.h" -#include "val/include/sbsa_avs_wakeup.h" - - -#define TEST_NUM (AVS_TIMER_TEST_NUM_BASE + 8) -#define TEST_DESC "Generate Mem Mapped SYS Timer Intr" - -static uint32_t intid; -static uint64_t cnt_base_n; - -static -void -isr(void) -{ - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - - val_print(AVS_PRINT_INFO, "\n Received interrupt ", 0); - val_timer_disable_system_timer((addr_t)cnt_base_n); - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - val_gic_end_of_interrupt(intid); -} - - -static -void -payload(void) -{ - - volatile uint32_t timeout; - uint32_t timer_expire_val = TIMEOUT_MEDIUM; - uint32_t status, ns_timer = 0; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - uint64_t timer_num = val_timer_get_info(TIMER_INFO_NUM_PLATFORM_TIMERS, 0); - - if (!timer_num) { - val_print(AVS_PRINT_WARN, "\n No System timers are defined ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); - return; - } - - while(timer_num){ - timer_num--; //array index starts from 0, so subtract 1 from count - - if (val_timer_get_info(TIMER_INFO_IS_PLATFORM_TIMER_SECURE, timer_num)) - continue; //Skip Secure Timer - - ns_timer++; - timeout = TIMEOUT_LARGE; - val_set_status(index, RESULT_PENDING(g_sbsa_level, TEST_NUM)); // Set the initial result to pending - - //Read CNTACR to determine whether access permission from NS state is permitted - status = val_timer_skip_if_cntbase_access_not_allowed(timer_num); - if(status == AVS_STATUS_SKIP){ - val_print(AVS_PRINT_WARN, "\n Security doesn't allow access to timer registers ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); - return; - } - - cnt_base_n = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N, timer_num); - if (cnt_base_n == 0) { - val_print(AVS_PRINT_WARN, "\n CNT_BASE_N is zero ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); - return; - } - - /* Install ISR */ - intid = val_timer_get_info(TIMER_INFO_SYS_INTID, timer_num); - val_gic_install_isr(intid, isr); - - /* enable System timer */ - val_timer_set_system_timer((addr_t)cnt_base_n, timer_expire_val); - - while ((--timeout > 0) && (IS_RESULT_PENDING(val_get_status(index)))); - - if (timeout == 0){ - val_print(AVS_PRINT_ERR, "\n Sys timer interrupt not received on %d ", intid); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - return; - } - } - - if(!ns_timer) { - val_print(AVS_PRINT_WARN, "\n No non-secure systimer implemented", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 04)); - return; - } - -} - -uint32_t -t008_entry(uint32_t num_pe) -{ - uint32_t status = AVS_STATUS_FAIL; - - num_pe = 1; //This Timer test is run on single processor - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - - return status; -} diff --git a/test_pool/timer_wd/test_w001.c b/test_pool/timer_wd/test_w001.c deleted file mode 100755 index 333ece78..00000000 --- a/test_pool/timer_wd/test_w001.c +++ /dev/null @@ -1,105 +0,0 @@ -/** @file - * Copyright (c) 2016-2018, 2021-2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - -#include "val/include/sbsa_avs_val.h" -#include "val/include/val_interface.h" - -#include "val/include/sbsa_avs_wd.h" - -#define TEST_NUM (AVS_WD_TEST_NUM_BASE + 1) -#define TEST_DESC "Check NS Watchdog Accessibility " - -static -void -payload(void) -{ - - uint64_t ctrl_base; - uint64_t refresh_base; - uint64_t wd_num = val_wd_get_info(0, WD_INFO_COUNT); - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - uint32_t data, ns_wdg = 0; - - val_print(AVS_PRINT_DEBUG, "\n Found %d watchdogs in ACPI table ", wd_num); - - if (wd_num == 0) { - val_print(AVS_PRINT_WARN, "\n No Watchdogs reported %d ", wd_num); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - return; - } - - do { - wd_num--; //array index starts from 0, so subtract 1 from count - - if (val_wd_get_info(wd_num, WD_INFO_ISSECURE)) - continue; //Skip Secure watchdog - - ns_wdg++; - refresh_base = val_wd_get_info(wd_num, WD_INFO_REFRESH_BASE); - val_print(AVS_PRINT_INFO, "\n Watchdog Refresh base is %llx ", refresh_base); - ctrl_base = val_wd_get_info(wd_num, WD_INFO_CTRL_BASE); - val_print(AVS_PRINT_INFO, "\n Watchdog CTRL base is %llx ", ctrl_base); - - data = val_mmio_read(ctrl_base); - //Control register bits 31:4 are reserved 0 - if(data >> 4) { - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); - return; - } - - data = val_mmio_read(refresh_base); - //refresh frame offset 0 must return 0 on reads. - if(data) { - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03)); - return; - } - } while(wd_num); - - if(!ns_wdg) { - val_print(AVS_PRINT_WARN, "\n No non-secure Watchdogs reported", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); - return; - } - - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - -} - -uint32_t -w001_entry(uint32_t num_pe) -{ - - uint32_t error_flag = 0; - uint32_t status = AVS_STATUS_FAIL; - - num_pe = 1; //This Timer test is run on single processor - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - /* This check is when user is forcing us to skip this test */ - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - error_flag = val_check_for_error(TEST_NUM, num_pe); - - if (!error_flag) - status = AVS_STATUS_PASS; - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - return status; - -} diff --git a/test_pool/timer_wd/test_w002.c b/test_pool/timer_wd/test_w002.c deleted file mode 100755 index 3eebf8e8..00000000 --- a/test_pool/timer_wd/test_w002.c +++ /dev/null @@ -1,128 +0,0 @@ -/** @file - * Copyright (c) 2016-2018, 2020-2022 Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - **/ - - -#include "val/include/sbsa_avs_val.h" -#include "val/include/val_interface.h" - -#include "val/include/sbsa_avs_wd.h" - -#define TEST_NUM (AVS_WD_TEST_NUM_BASE + 2) -#define TEST_DESC "Check Watchdog WS0 interrupt " - -static uint32_t int_id; -static uint64_t wd_num; - -static -void -isr(void) -{ - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - val_wd_set_ws0(wd_num, 0); - val_print(AVS_PRINT_DEBUG, "\n Received WS0 interrupt ", 0); - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - val_gic_end_of_interrupt(int_id); -} - - -static -void -payload(void) -{ - - uint32_t status, timeout, ns_wdg = 0; - uint64_t timer_expire_ticks = 1; - uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - wd_num = val_wd_get_info(0, WD_INFO_COUNT); - - - if (wd_num == 0) { - val_print(AVS_PRINT_WARN, "\n No Watchdogs reported %d ", wd_num); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - return; - } - - do { - wd_num--; //array index starts from 0, so subtract 1 from count - - if (val_wd_get_info(wd_num, WD_INFO_ISSECURE)) - continue; //Skip Secure watchdog - - ns_wdg++; - timeout = val_get_counter_frequency() * 2; - val_set_status(index, RESULT_PENDING(g_sbsa_level, TEST_NUM)); // Set the initial result to pending - - int_id = val_wd_get_info(wd_num, WD_INFO_GSIV); - val_print(AVS_PRINT_DEBUG, "\n WS0 Interrupt id %d ", int_id); - - val_gic_install_isr(int_id, isr); - - /* Set Interrupt Type Edge/Level Trigger */ - if (val_wd_get_info(wd_num, WD_INFO_IS_EDGE)) - val_gic_set_intr_trigger(int_id, INTR_TRIGGER_INFO_EDGE_RISING); - else - val_gic_set_intr_trigger(int_id, INTR_TRIGGER_INFO_LEVEL_HIGH); - - status = val_wd_set_ws0(wd_num, timer_expire_ticks); - if (status) { - val_print(AVS_PRINT_ERR, "\n Setting watchdog timeout failed", 0); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); - return; - } - - while ((--timeout > 0) && (IS_RESULT_PENDING(val_get_status(index)))); - - if (timeout == 0) { - val_print(AVS_PRINT_ERR, "\n WS0 Interrupt not received on %d ", int_id); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); - return; - } - - } while(wd_num); - - if(!ns_wdg) { - val_print(AVS_PRINT_WARN, "\n No non-secure Watchdogs reported", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); - return; - } - -} - -uint32_t -w002_entry(uint32_t num_pe) -{ - - uint32_t error_flag = 0; - uint32_t status = AVS_STATUS_FAIL; - - num_pe = 1; //This Timer test is run on single processor - - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); - /* This check is when user is forcing us to skip this test */ - if (status != AVS_STATUS_SKIP) - val_run_test_payload(TEST_NUM, num_pe, payload, 0); - - /* get the result from all PE and check for failure */ - error_flag = val_check_for_error(TEST_NUM, num_pe); - - if (!error_flag) - status = AVS_STATUS_PASS; - - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - return status; - -} diff --git a/test_pool/timer_wd/test_w003.c b/test_pool/watchdog/operating_system/test_w001.c similarity index 90% rename from test_pool/timer_wd/test_w003.c rename to test_pool/watchdog/operating_system/test_w001.c index 6acd5fca..08dfaac6 100644 --- a/test_pool/timer_wd/test_w003.c +++ b/test_pool/watchdog/operating_system/test_w001.c @@ -20,8 +20,9 @@ #include "val/include/sbsa_avs_wd.h" -#define TEST_NUM (AVS_WD_TEST_NUM_BASE + 3) -#define TEST_DESC "Check NS Watchdog Architecture Version" +#define TEST_NUM (AVS_WD_TEST_NUM_BASE + 1) +#define TEST_RULE "S_L6WD_01" +#define TEST_DESC "Check NS Watchdog Revision " static void @@ -88,20 +89,20 @@ payload(void) } uint32_t -w003_entry(uint32_t num_pe) +w001_entry(uint32_t num_pe) { uint32_t status = AVS_STATUS_FAIL; num_pe = 1; //This test is run on single processor - status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); /* This check is when user is forcing us to skip this test */ if (status != AVS_STATUS_SKIP) val_run_test_payload(TEST_NUM, num_pe, payload, 0); /* get the result from all PE and check for failure */ - status = val_check_for_error(TEST_NUM, num_pe); - val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); return status; diff --git a/uefi_app/SbsaAvs.inf b/uefi_app/SbsaAvs.inf index 27898aaf..0392208d 100644 --- a/uefi_app/SbsaAvs.inf +++ b/uefi_app/SbsaAvs.inf @@ -1,5 +1,5 @@ ## @file -# Copyright (c) 2016-2021, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2016-2023 Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -31,57 +31,50 @@ [Sources.AARCH64] ../ SbsaAvsMain.c - ../test_pool/pe/test_c001.c - ../test_pool/pe/test_c002.c - ../test_pool/pe/test_c003.c - ../test_pool/pe/test_c004.c - ../test_pool/pe/test_c005.c - ../test_pool/pe/test_c006.c - ../test_pool/pe/test_c007.c - ../test_pool/pe/test_c008.c - ../test_pool/pe/test_c010.c - ../test_pool/pe/test_c011.c - ../test_pool/pe/test_c012.c - ../test_pool/pe/test_c013.c - ../test_pool/pe/test_c014.c - ../test_pool/pe/test_c015.c - ../test_pool/pe/test_c017.c - ../test_pool/pe/test_c018.c - ../test_pool/pe/test_c019.c - ../test_pool/pe/test_c020.c - ../test_pool/pe/test_c021.c - ../test_pool/pe/test_c022.c - ../test_pool/pe/test_c023.c - ../test_pool/pe/test_c024.c - ../test_pool/pe/test_c025.c - ../test_pool/pe/test_c026.c - ../test_pool/pe/test_c027.c - ../test_pool/pe/test_c028.c - ../test_pool/pe/test_c029.c - ../test_pool/pe/test_c030.c - ../test_pool/pe/test_c031.c - ../test_pool/pe/test_c032.c - ../test_pool/pe/test_c033.c - ../test_pool/pe/test_c034.c - ../test_pool/pe/test_c035.c - ../test_pool/pe/test_c036.c - ../test_pool/gic/test_g001.c - ../test_pool/gic/test_g002.c - ../test_pool/gic/test_g003.c - ../test_pool/gic/test_g004.c - ../test_pool/timer_wd/test_t001.c - ../test_pool/timer_wd/test_t002.c - ../test_pool/timer_wd/test_t003.c - ../test_pool/timer_wd/test_t004.c - ../test_pool/timer_wd/test_t005.c - ../test_pool/timer_wd/test_t006.c - ../test_pool/timer_wd/test_t007.c - ../test_pool/timer_wd/test_t008.c - ../test_pool/timer_wd/test_w001.c - ../test_pool/timer_wd/test_w002.c - ../test_pool/timer_wd/test_w003.c + ../test_pool/pe/operating_system/test_c001.c + ../test_pool/pe/operating_system/test_c002.c + ../test_pool/pe/operating_system/test_c003.c + ../test_pool/pe/operating_system/test_c004.c + ../test_pool/pe/operating_system/test_c005.c + ../test_pool/pe/operating_system/test_c006.c + ../test_pool/pe/operating_system/test_c007.c + ../test_pool/pe/operating_system/test_c008.c + ../test_pool/pe/operating_system/test_c009.c + ../test_pool/pe/operating_system/test_c010.c + ../test_pool/pe/operating_system/test_c011.c + ../test_pool/pe/operating_system/test_c012.c + ../test_pool/pe/operating_system/test_c013.c + ../test_pool/pe/operating_system/test_c014.c + ../test_pool/pe/operating_system/test_c015.c + ../test_pool/pe/operating_system/test_c016.c + ../test_pool/pe/operating_system/test_c017.c + ../test_pool/pe/operating_system/test_c018.c + ../test_pool/pe/operating_system/test_c019.c + ../test_pool/pe/operating_system/test_c020.c + ../test_pool/pe/operating_system/test_c021.c + ../test_pool/pe/operating_system/test_c022.c + ../test_pool/pe/operating_system/test_c023.c + ../test_pool/pe/operating_system/test_c024.c + ../test_pool/pe/operating_system/test_c025.c + ../test_pool/pe/operating_system/test_c026.c + ../test_pool/pe/operating_system/test_c027.c + ../test_pool/pe/operating_system/test_c028.c + ../test_pool/pe/operating_system/test_c029.c + ../test_pool/pe/operating_system/test_c030.c + ../test_pool/pe/operating_system/test_c031.c + ../test_pool/pe/operating_system/test_c032.c + ../test_pool/pe/operating_system/test_c033.c + ../test_pool/pe/operating_system/test_c034.c + ../test_pool/pe/operating_system/test_c035.c + ../test_pool/pe/operating_system/test_c036.c + ../test_pool/pe/operating_system/test_c037.c + + ../test_pool/gic/operating_system/test_g001.c + ../test_pool/gic/operating_system/test_g002.c + + ../test_pool/watchdog/operating_system/test_w001.c + ../test_pool/pcie/test_p001.c - ../test_pool/pcie/test_p002.c ../test_pool/pcie/test_p003.c ../test_pool/pcie/test_p020.c ../test_pool/pcie/test_p021.c @@ -103,7 +96,6 @@ ../test_pool/pcie/test_p037.c ../test_pool/pcie/test_p038.c ../test_pool/pcie/test_p039.c - ../test_pool/pcie/test_p040.c ../test_pool/pcie/test_p041.c ../test_pool/pcie/test_p042.c ../test_pool/pcie/test_p043.c @@ -116,35 +108,27 @@ ../test_pool/pcie/test_p050.c ../test_pool/pcie/test_p051.c ../test_pool/pcie/test_p052.c - ../test_pool/pcie/test_p053.c - ../test_pool/pcie/test_p054.c - ../test_pool/pcie/test_p055.c ../test_pool/pcie/test_p056.c ../test_pool/pcie/test_p057.c ../test_pool/pcie/test_p058.c ../test_pool/pcie/test_p059.c ../test_pool/pcie/test_p060.c - ../test_pool/io_virt/test_i001.c - ../test_pool/io_virt/test_i002.c - ../test_pool/io_virt/test_i003.c - ../test_pool/io_virt/test_i004.c - ../test_pool/io_virt/test_i005.c - ../test_pool/io_virt/test_i006.c - ../test_pool/io_virt/test_i007.c - ../test_pool/io_virt/test_i008.c - ../test_pool/io_virt/test_i009.c - ../test_pool/io_virt/test_i010.c - ../test_pool/io_virt/test_i011.c - ../test_pool/io_virt/test_i012.c - ../test_pool/io_virt/test_i013.c - ../test_pool/io_virt/test_i014.c - ../test_pool/io_virt/test_i015.c - ../test_pool/io_virt/test_i016.c - ../test_pool/power_wakeup/test_u001.c - ../test_pool/power_wakeup/test_u002.c - ../test_pool/peripherals/test_d001.c - ../test_pool/peripherals/test_d002.c - ../test_pool/peripherals/test_d003.c + ../test_pool/smmu/operating_system/test_i001.c + ../test_pool/smmu/operating_system/test_i002.c + ../test_pool/smmu/operating_system/test_i003.c + ../test_pool/smmu/operating_system/test_i004.c + ../test_pool/smmu/operating_system/test_i005.c + ../test_pool/smmu/operating_system/test_i006.c + ../test_pool/smmu/operating_system/test_i007.c + ../test_pool/smmu/operating_system/test_i008.c + ../test_pool/smmu/operating_system/test_i009.c + ../test_pool/smmu/operating_system/test_i010.c + ../test_pool/smmu/operating_system/test_i011.c + ../test_pool/smmu/operating_system/test_i012.c + ../test_pool/smmu/operating_system/test_i013.c + ../test_pool/smmu/operating_system/test_i014.c + ../test_pool/smmu/operating_system/test_i015.c + ../test_pool/memory_map/operating_system/test_m001.c ../test_pool/exerciser/test_e001.c ../test_pool/exerciser/test_e002.c ../test_pool/exerciser/test_e003.c @@ -161,14 +145,6 @@ ../test_pool/exerciser/test_e014.c ../test_pool/exerciser/test_e015.c ../test_pool/exerciser/test_e016.c -# BSA test which gets compile with SBSA - ../test_pool/pe/test_os_c018.c - ../test_pool/io_virt/test_os_i005.c - ../test_pool/io_virt/test_os_i006.c - ../test_pool/io_virt/test_os_i007.c - ../test_pool/io_virt/test_os_i008.c -# ../test_pool/io_virt/test_os_i009.c - ../test_pool/io_virt/test_hyp_i005.c [Packages] StdLib/StdLib.dec diff --git a/uefi_app/SbsaAvsNist.inf b/uefi_app/SbsaAvsNist.inf index 68d6e401..57c82db4 100644 --- a/uefi_app/SbsaAvsNist.inf +++ b/uefi_app/SbsaAvsNist.inf @@ -31,57 +31,49 @@ [Sources.AARCH64] ../ SbsaAvsMain.c - ../test_pool/pe/test_c001.c - ../test_pool/pe/test_c002.c - ../test_pool/pe/test_c003.c - ../test_pool/pe/test_c004.c - ../test_pool/pe/test_c005.c - ../test_pool/pe/test_c006.c - ../test_pool/pe/test_c007.c - ../test_pool/pe/test_c008.c - ../test_pool/pe/test_c009.c - ../test_pool/pe/test_c010.c - ../test_pool/pe/test_c011.c - ../test_pool/pe/test_c012.c - ../test_pool/pe/test_c013.c - ../test_pool/pe/test_c014.c - ../test_pool/pe/test_c015.c - ../test_pool/pe/test_c016.c - ../test_pool/pe/test_c017.c - ../test_pool/pe/test_c018.c - ../test_pool/pe/test_c019.c - ../test_pool/pe/test_c020.c - ../test_pool/pe/test_c021.c - ../test_pool/pe/test_c022.c - ../test_pool/pe/test_c023.c - ../test_pool/pe/test_c024.c - ../test_pool/pe/test_c025.c - ../test_pool/pe/test_c026.c - ../test_pool/pe/test_c027.c - ../test_pool/pe/test_c028.c - ../test_pool/pe/test_c029.c - ../test_pool/pe/test_c030.c - ../test_pool/pe/test_c031.c - ../test_pool/pe/test_c032.c - ../test_pool/pe/test_c033.c - ../test_pool/pe/test_c034.c - ../test_pool/pe/test_c035.c - ../test_pool/pe/test_c036.c - ../test_pool/gic/test_g001.c - ../test_pool/gic/test_g002.c - ../test_pool/gic/test_g003.c - ../test_pool/gic/test_g004.c - ../test_pool/timer_wd/test_t001.c - ../test_pool/timer_wd/test_t002.c - ../test_pool/timer_wd/test_t003.c - ../test_pool/timer_wd/test_t004.c - ../test_pool/timer_wd/test_t005.c - ../test_pool/timer_wd/test_t006.c - ../test_pool/timer_wd/test_t007.c - ../test_pool/timer_wd/test_t008.c - ../test_pool/timer_wd/test_w001.c - ../test_pool/timer_wd/test_w002.c - ../test_pool/timer_wd/test_w003.c + ../test_pool/pe/operating_system/test_c001.c + ../test_pool/pe/operating_system/test_c002.c + ../test_pool/pe/operating_system/test_c003.c + ../test_pool/pe/operating_system/test_c004.c + ../test_pool/pe/operating_system/test_c005.c + ../test_pool/pe/operating_system/test_c006.c + ../test_pool/pe/operating_system/test_c007.c + ../test_pool/pe/operating_system/test_c008.c + ../test_pool/pe/operating_system/test_c009.c + ../test_pool/pe/operating_system/test_c010.c + ../test_pool/pe/operating_system/test_c011.c + ../test_pool/pe/operating_system/test_c012.c + ../test_pool/pe/operating_system/test_c013.c + ../test_pool/pe/operating_system/test_c014.c + ../test_pool/pe/operating_system/test_c015.c + ../test_pool/pe/operating_system/test_c016.c + ../test_pool/pe/operating_system/test_c017.c + ../test_pool/pe/operating_system/test_c018.c + ../test_pool/pe/operating_system/test_c019.c + ../test_pool/pe/operating_system/test_c020.c + ../test_pool/pe/operating_system/test_c021.c + ../test_pool/pe/operating_system/test_c022.c + ../test_pool/pe/operating_system/test_c023.c + ../test_pool/pe/operating_system/test_c024.c + ../test_pool/pe/operating_system/test_c025.c + ../test_pool/pe/operating_system/test_c026.c + ../test_pool/pe/operating_system/test_c027.c + ../test_pool/pe/operating_system/test_c028.c + ../test_pool/pe/operating_system/test_c029.c + ../test_pool/pe/operating_system/test_c030.c + ../test_pool/pe/operating_system/test_c031.c + ../test_pool/pe/operating_system/test_c032.c + ../test_pool/pe/operating_system/test_c033.c + ../test_pool/pe/operating_system/test_c034.c + ../test_pool/pe/operating_system/test_c035.c + ../test_pool/pe/operating_system/test_c036.c + ../test_pool/pe/operating_system/test_c037.c + + ../test_pool/gic/operating_system/test_g001.c + ../test_pool/gic/operating_system/test_g002.c + + ../test_pool/watchdog/operating_system/test_w001.c + ../test_pool/pcie/test_p001.c ../test_pool/pcie/test_p002.c ../test_pool/pcie/test_p003.c @@ -123,28 +115,22 @@ ../test_pool/pcie/test_p055.c ../test_pool/pcie/test_p056.c ../test_pool/pcie/test_p057.c - ../test_pool/io_virt/test_i001.c - ../test_pool/io_virt/test_i002.c - ../test_pool/io_virt/test_i003.c - ../test_pool/io_virt/test_i004.c - ../test_pool/io_virt/test_i005.c - ../test_pool/io_virt/test_i006.c - ../test_pool/io_virt/test_i007.c - ../test_pool/io_virt/test_i008.c - ../test_pool/io_virt/test_i009.c - ../test_pool/io_virt/test_i010.c - ../test_pool/io_virt/test_i011.c - ../test_pool/io_virt/test_i012.c - ../test_pool/io_virt/test_i013.c - ../test_pool/io_virt/test_i014.c - ../test_pool/io_virt/test_i015.c - ../test_pool/io_virt/test_i016.c - ../test_pool/power_wakeup/test_u001.c - ../test_pool/power_wakeup/test_u002.c - ../test_pool/peripherals/test_d001.c - ../test_pool/peripherals/test_d002.c - ../test_pool/peripherals/test_d003.c - ../test_pool/peripherals/test_m001.c + ../test_pool/smmu/operating_system/test_i001.c + ../test_pool/smmu/operating_system/test_i002.c + ../test_pool/smmu/operating_system/test_i003.c + ../test_pool/smmu/operating_system/test_i004.c + ../test_pool/smmu/operating_system/test_i005.c + ../test_pool/smmu/operating_system/test_i006.c + ../test_pool/smmu/operating_system/test_i007.c + ../test_pool/smmu/operating_system/test_i008.c + ../test_pool/smmu/operating_system/test_i009.c + ../test_pool/smmu/operating_system/test_i010.c + ../test_pool/smmu/operating_system/test_i011.c + ../test_pool/smmu/operating_system/test_i012.c + ../test_pool/smmu/operating_system/test_i013.c + ../test_pool/smmu/operating_system/test_i014.c + ../test_pool/smmu/operating_system/test_i015.c + ../test_pool/memory_map/operating_system/test_m001.c ../test_pool/exerciser/test_e001.c ../test_pool/exerciser/test_e002.c ../test_pool/exerciser/test_e003.c diff --git a/val/include/pal_interface.h b/val/include/pal_interface.h index 3dbc0568..1adb5e96 100644 --- a/val/include/pal_interface.h +++ b/val/include/pal_interface.h @@ -115,6 +115,7 @@ typedef struct { uint32_t attr; ///< PE attributes uint64_t mpidr; ///< PE MPIDR uint32_t pmu_gsiv; ///< PMU Interrupt ID + uint32_t gmain_gsiv; /* GIC Maintenance Interrupt */ }PE_INFO_ENTRY; typedef struct { @@ -615,6 +616,7 @@ typedef enum { MEMORY_TYPE_NORMAL, MEMORY_TYPE_RESERVED, MEMORY_TYPE_NOT_POPULATED, + MEMORY_TYPE_PERSISTENT, MEMORY_TYPE_LAST_ENTRY }MEM_INFO_TYPE_e; diff --git a/val/include/sbsa_avs_common.h b/val/include/sbsa_avs_common.h index 9245f28e..4bc2186d 100644 --- a/val/include/sbsa_avs_common.h +++ b/val/include/sbsa_avs_common.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2021, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -32,6 +32,7 @@ #define AVS_SMMU_TEST_NUM_BASE 700 #define AVS_EXERCISER_TEST_NUM_BASE 800 #define AVS_NIST_TEST_NUM_BASE 900 +#define AVS_MEM_MAP_TEST_NUM_BASE 1300 #define STATE_BIT 28 #define STATE_MASK 0xF @@ -108,10 +109,11 @@ void val_mmio_write64(addr_t addr, uint64_t data); uint32_t -val_initialize_test(uint32_t test_num, char8_t * desc, uint32_t num_pe, uint32_t level); +val_initialize_test(uint32_t test_num, char8_t *desc, uint32_t num_pe, uint32_t level, + char8_t *ruleid); uint32_t -val_check_for_error(uint32_t test_num, uint32_t num_pe); +val_check_for_error(uint32_t test_num, uint32_t num_pe, char8_t *ruleid); void val_run_test_payload(uint32_t test_num, uint32_t num_pe, void (*payload)(void), uint64_t test_input); @@ -130,7 +132,8 @@ typedef enum { WAKEUP_MODULE, PERIPHERAL_MODULE, SMMU_MODULE, - EXERCISER_MODULE + EXERCISER_MODULE, + MEM_MAP_MODULE } MODULE_ID_e; #endif diff --git a/val/include/sbsa_avs_memory.h b/val/include/sbsa_avs_memory.h index 47505b87..593f841a 100644 --- a/val/include/sbsa_avs_memory.h +++ b/val/include/sbsa_avs_memory.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -21,6 +21,7 @@ #define MEM_MAP_SUCCESS 0x0 #define MEM_MAP_NO_MEM 0x1 #define MEM_MAP_FAILURE 0x2 +#define MEM_SIZE_64KB 65536 addr_t val_memory_ioremap(void *addr, uint32_t size, uint64_t attr); @@ -38,5 +39,8 @@ uint32_t val_memory_page_size(void); void *val_memory_alloc_pages(uint32_t num_pages); void val_memory_free_pages(void *page_base, uint32_t num_pages); void *val_aligned_alloc( uint32_t alignment, uint32_t size ); +uint32_t val_memory_check_for_persistent_mem(void); -#endif // __SBSA_AVS_PERIPHERAL_H__ +uint32_t m001_entry(uint32_t num_pe); + +#endif diff --git a/val/include/sbsa_avs_pe.h b/val/include/sbsa_avs_pe.h index 6edc44cf..0aff60bd 100644 --- a/val/include/sbsa_avs_pe.h +++ b/val/include/sbsa_avs_pe.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -317,7 +317,7 @@ void val_pe_context_restore(uint64_t sp); void val_pe_default_esr(uint64_t interrupt_type, void *context); void val_pe_cache_clean_range(uint64_t start_addr, uint64_t length); -uint32_t c001_entry(void); +uint32_t c001_entry(uint32_t num_pe); uint32_t c002_entry(uint32_t num_pe); uint32_t c003_entry(uint32_t num_pe); uint32_t c004_entry(uint32_t num_pe); @@ -353,7 +353,7 @@ uint32_t c033_entry(uint32_t num_pe); uint32_t c034_entry(uint32_t num_pe); uint32_t c035_entry(uint32_t num_pe); uint32_t c036_entry(uint32_t num_pe); +uint32_t c037_entry(uint32_t num_pe); -uint32_t os_c018_entry(uint32_t num_pe); #endif diff --git a/val/include/sbsa_avs_val.h b/val/include/sbsa_avs_val.h index 3bf0891f..264f5299 100644 --- a/val/include/sbsa_avs_val.h +++ b/val/include/sbsa_avs_val.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -49,7 +49,7 @@ uint8_t val_is_el2_enabled(void); void -val_report_status(uint32_t id, uint32_t status); +val_report_status(uint32_t id, uint32_t status, char8_t *ruleid); void val_set_status(uint32_t index, uint32_t status); diff --git a/val/include/val_interface.h b/val/include/val_interface.h index 82794774..437eaeec 100644 --- a/val/include/val_interface.h +++ b/val/include/val_interface.h @@ -78,6 +78,7 @@ uint32_t val_pe_get_pmu_gsiv(uint32_t index); uint64_t val_pe_get_mpid(void); uint32_t val_pe_get_index_mpid(uint64_t mpid); uint32_t val_pe_install_esr(uint32_t exception_type, void (*esr)(uint64_t, void *)); +uint32_t val_pe_get_gmain_gsiv(uint32_t index); void val_execute_on_pe(uint32_t index, void (*payload)(void), uint64_t args); void val_suspend_pe(uint32_t power_state, uint64_t entry, uint32_t context_id); @@ -314,6 +315,7 @@ typedef enum { UART_BASE0, UART_GSIV, UART_FLAGS, + ANY_BASE0, ANY_FLAGS, ANY_GSIV, ANY_BDF, diff --git a/val/src/avs_gic_support.c b/val/src/avs_gic_support.c index 8f8754c8..e6a09fb1 100644 --- a/val/src/avs_gic_support.c +++ b/val/src/avs_gic_support.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -50,7 +50,8 @@ val_gic_reg_read(uint32_t reg_id) case ICH_MISR_EL2: return GicReadIchMisr(); default: - val_report_status(val_pe_get_index_mpid(val_pe_get_mpid()), RESULT_FAIL(g_sbsa_level, 0, 0x78)); + val_report_status(val_pe_get_index_mpid(val_pe_get_mpid()), + RESULT_FAIL(g_sbsa_level, 0, 0x78), NULL); } return 0x0; @@ -86,7 +87,8 @@ val_gic_reg_write(uint32_t reg_id, uint64_t write_data) GicWriteIccPmr(write_data); break; default: - val_report_status(val_pe_get_index_mpid(val_pe_get_mpid()), RESULT_FAIL(g_sbsa_level, 0, 0x78)); + val_report_status(val_pe_get_index_mpid(val_pe_get_mpid()), + RESULT_FAIL(g_sbsa_level, 0, 0x78), NULL); } } diff --git a/val/src/avs_memory.c b/val/src/avs_memory.c index 96f17248..94521edf 100644 --- a/val/src/avs_memory.c +++ b/val/src/avs_memory.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -35,7 +35,26 @@ uint32_t val_memory_execute_tests(uint32_t level, uint32_t num_pe) { - uint32_t status; + uint32_t status = 0; + uint32_t i; + + for (i = 0 ; i < MAX_TEST_SKIP_NUM ; i++) { + if (g_skip_test_num[i] == AVS_MEM_MAP_TEST_NUM_BASE) { + val_print(AVS_PRINT_TEST, " USER Override - Skipping all memory tests \n", 0); + return AVS_STATUS_SKIP; + } + } + + if (g_single_module != SINGLE_MODULE_SENTINEL && g_single_module != AVS_MEM_MAP_TEST_NUM_BASE && + (g_single_test == SINGLE_MODULE_SENTINEL || + (g_single_test - AVS_MEM_MAP_TEST_NUM_BASE > 100 || + g_single_test - AVS_MEM_MAP_TEST_NUM_BASE < 0))) { + val_print(AVS_PRINT_TEST, " USER Override - Skipping all memory tests \n", 0); + val_print(AVS_PRINT_TEST, " (Running only a single module)\n", 0); + return AVS_STATUS_SKIP; + } + + g_curr_module = 1 << MEM_MAP_MODULE; status = m001_entry(num_pe); @@ -281,4 +300,27 @@ void *val_aligned_alloc( uint32_t alignment, uint32_t size ) { return pal_aligned_alloc(alignment, size); + +} + +/** + @brief Checks for presence of persistent memory. + + @param none + + @return 1 - persistent memory exists. + 0 - persistent memory does not exist. +**/ +uint32_t +val_memory_check_for_persistent_mem(void) +{ + + uint32_t index = 0; + + while (g_memory_info_table->info[index].type != MEMORY_TYPE_LAST_ENTRY) { + if (g_memory_info_table->info[index].type == MEMORY_TYPE_PERSISTENT) + return 1; + index++; + } + return 0; } diff --git a/val/src/avs_pe.c b/val/src/avs_pe.c index cb7fb24f..ba83648a 100644 --- a/val/src/avs_pe.c +++ b/val/src/avs_pe.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2021, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -61,32 +61,35 @@ val_pe_execute_tests(uint32_t level, uint32_t num_pe) g_curr_module = 1 << PE_MODULE; -#ifndef ONLY_SBSA_RULE_TESTS - status |= c001_entry(); + status |= c001_entry(num_pe); status |= c002_entry(num_pe); - status |= c005_entry(num_pe); - status |= c006_entry(num_pe); - status |= c007_entry(num_pe); - status |= c008_entry(num_pe); - status |= c011_entry(num_pe); - status |= c012_entry(num_pe); - status |= c013_entry(num_pe); - status |= c014_entry(num_pe); - status |= c015_entry(num_pe); - status |= c017_entry(num_pe); -#endif - status |= c003_entry(num_pe); status |= c004_entry(num_pe); - status |= c010_entry(num_pe); if (level > 3) { - status |= c019_entry(num_pe); - status |= c020_entry(num_pe); - status |= c021_entry(num_pe); + status |= c005_entry(num_pe); + status |= c006_entry(num_pe); + status |= c007_entry(num_pe); + status |= c008_entry(num_pe); } if (level > 4) { + status |= c009_entry(num_pe); + status |= c010_entry(num_pe); + status |= c011_entry(num_pe); + status |= c012_entry(num_pe); + status |= c013_entry(num_pe); + status |= c014_entry(num_pe); + status |= c015_entry(num_pe); + status |= c016_entry(num_pe); + } + + if (level > 5) { + status |= c017_entry(num_pe); + status |= c018_entry(num_pe); + status |= c019_entry(num_pe); + status |= c020_entry(num_pe); + status |= c021_entry(num_pe); status |= c022_entry(num_pe); status |= c023_entry(num_pe); status |= c024_entry(num_pe); @@ -95,8 +98,7 @@ val_pe_execute_tests(uint32_t level, uint32_t num_pe) status |= c027_entry(num_pe); } - if (level > 5) { - status |= c018_entry(num_pe); + if (level > 6) { status |= c028_entry(num_pe); status |= c029_entry(num_pe); status |= c030_entry(num_pe); @@ -106,10 +108,7 @@ val_pe_execute_tests(uint32_t level, uint32_t num_pe) status |= c034_entry(num_pe); status |= c035_entry(num_pe); status |= c036_entry(num_pe); - -#ifdef ONLY_SBSA_RULE_TESTS - status |= os_c018_entry(num_pe); -#endif + status |= c037_entry(num_pe); } val_print_test_end(status, "PE"); @@ -249,7 +248,8 @@ val_pe_reg_read(uint32_t reg_id) if (AA64ReadCurrentEL() == AARCH64_EL2) return AA64ReadTcr2(); default: - val_report_status(val_pe_get_index_mpid(val_pe_get_mpid()), RESULT_FAIL(g_sbsa_level, 0, 0x78)); + val_report_status(val_pe_get_index_mpid(val_pe_get_mpid()), + RESULT_FAIL(g_sbsa_level, 0, 0x78), NULL); } return 0x0; @@ -308,7 +308,8 @@ val_pe_reg_write(uint32_t reg_id, uint64_t write_data) AA64WritePmblimitr(write_data); break; default: - val_report_status(val_pe_get_index_mpid(val_pe_get_mpid()), RESULT_FAIL(g_sbsa_level, 0, 0x78)); + val_report_status(val_pe_get_index_mpid(val_pe_get_mpid()), + RESULT_FAIL(g_sbsa_level, 0, 0x78), NULL); } } @@ -361,7 +362,7 @@ val_pe_get_pmu_gsiv(uint32_t index) PE_INFO_ENTRY *entry; if (index > g_pe_info_table->header.num_of_pe) { - val_report_status(index, RESULT_FAIL(g_sbsa_level, 0, 0xFF)); + val_report_status(index, RESULT_FAIL(g_sbsa_level, 0, 0xFF), NULL); return 0xFFFFFF; } @@ -461,3 +462,27 @@ uint32_t val_pe_reg_read_ttbr(uint32_t ttbr1, uint64_t *ttbr_ptr) *ttbr_ptr = ReadTtbr[ttbr1][(el >> 2) - 1](); return 0; } + +/** + @brief This API returns the GIC Maintenance Interrupt ID for a given PE index + 1. Caller - Test Suite + 2. Prerequisite - val_create_peinfo_table + @param index - the index of PE whose GIC Maintenace interrupt ID is returned. + @return GIC Maintenance interrupt ID +**/ +uint32_t +val_pe_get_gmain_gsiv(uint32_t index) +{ + + PE_INFO_ENTRY *entry; + + if (index > g_pe_info_table->header.num_of_pe) { + val_report_status(index, RESULT_FAIL(g_sbsa_level, 0, 0xFF), NULL); + return 0xFFFFFF; + } + + entry = g_pe_info_table->pe_info; + + return entry[index].gmain_gsiv; + +} diff --git a/val/src/avs_pe_infra.c b/val/src/avs_pe_infra.c index 88f1ab61..ed3a89c1 100644 --- a/val/src/avs_pe_infra.c +++ b/val/src/avs_pe_infra.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2020-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -144,7 +144,7 @@ val_pe_get_mpid_index(uint32_t index) PE_INFO_ENTRY *entry; if (index > g_pe_info_table->header.num_of_pe) { - val_report_status(index, RESULT_FAIL(g_sbsa_level, 0, 0xFF)); + val_report_status(index, RESULT_FAIL(g_sbsa_level, 0, 0xFF), NULL); return 0xFFFFFF; } @@ -225,7 +225,7 @@ val_execute_on_pe(uint32_t index, void (*payload)(void), uint64_t test_input) int timeout = TIMEOUT_LARGE; if (index > g_pe_info_table->header.num_of_pe) { val_print(AVS_PRINT_ERR, "Input Index exceeds Num of PE %x \n", index); - val_report_status(index, RESULT_FAIL(g_sbsa_level, 0, 0xFF)); + val_report_status(index, RESULT_FAIL(g_sbsa_level, 0, 0xFF), NULL); return; } diff --git a/val/src/avs_peripherals.c b/val/src/avs_peripherals.c index d14a6fd9..7ea417e0 100644 --- a/val/src/avs_peripherals.c +++ b/val/src/avs_peripherals.c @@ -181,6 +181,11 @@ val_peripheral_get_info(PERIPHERAL_INFO_e info_type, uint32_t instance) if (i != 0xFFFF) return g_peripheral_info_table->info[i].flags; break; + case ANY_BASE0: + i = val_peripheral_get_entry_index(PERIPHERAL_TYPE_NONE, instance); + if (i != 0xFFFF) + return g_peripheral_info_table->info[i].base0; + break; case ANY_FLAGS: i = val_peripheral_get_entry_index (PERIPHERAL_TYPE_NONE, instance); if (i != 0xFFFF) diff --git a/val/src/avs_status.c b/val/src/avs_status.c index 29ffa82f..aaebf916 100644 --- a/val/src/avs_status.c +++ b/val/src/avs_status.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2021, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,7 +29,7 @@ @return none **/ void -val_report_status(uint32_t index, uint32_t status) +val_report_status(uint32_t index, uint32_t status, char8_t *ruleid) { if (IS_TEST_FAIL(status)) { @@ -37,14 +37,32 @@ val_report_status(uint32_t index, uint32_t status) val_print(AVS_PRINT_ERR, "for Level= %2d ", (status >> LEVEL_BIT) & LEVEL_MASK); } - if (IS_TEST_PASS(status)) - val_print(AVS_PRINT_TEST, ": Result: PASS \n", status); + if (IS_TEST_PASS(status)) { + val_print(AVS_PRINT_DEBUG, "\n ", 0); + val_print(AVS_PRINT_DEBUG, ruleid, 0); + val_print(AVS_PRINT_DEBUG, "\n ", 0); + val_print(AVS_PRINT_TEST, ": Result: PASS \n", status); + } else - if (IS_TEST_FAIL(status)) - val_print(AVS_PRINT_ERR, ": Result: --FAIL-- %x \n", status & STATUS_MASK); + if (IS_TEST_FAIL(status)) { + if (ruleid) { + val_print(AVS_PRINT_ERR, "\n ", 0); + val_print(AVS_PRINT_ERR, ruleid, 0); + val_print(AVS_PRINT_ERR, "\n Checkpoint -- %2d ", + status & STATUS_MASK); + } + val_print(AVS_PRINT_ERR, " : Result: FAIL \n", 0); + } else - if (IS_TEST_SKIP(status)) - val_print(AVS_PRINT_WARN, ": Result: -SKIPPED- %x \n", status & STATUS_MASK); + if (IS_TEST_SKIP(status)) { + if (ruleid) { + val_print(AVS_PRINT_WARN, "\n ", 0); + val_print(AVS_PRINT_WARN, ruleid, 0); + val_print(AVS_PRINT_WARN, "\n Checkpoint -- %2d ", + status & STATUS_MASK); + } + val_print(AVS_PRINT_WARN, " : Result: SKIPPED \n", 0); + } else if (IS_TEST_START(status)) val_print(AVS_PRINT_INFO, "\n START ", status); diff --git a/val/src/avs_test_infra.c b/val/src/avs_test_infra.c index 8571755d..bee37f39 100644 --- a/val/src/avs_test_infra.c +++ b/val/src/avs_test_infra.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2020, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -236,7 +236,8 @@ val_mmio_write64(addr_t addr, uint64_t data) @return Skip - if the user has overriden to skip the test. **/ uint32_t -val_initialize_test(uint32_t test_num, char8_t *desc, uint32_t num_pe, uint32_t level) +val_initialize_test(uint32_t test_num, char8_t *desc, uint32_t num_pe, uint32_t level, + char8_t *ruleid) { uint32_t i; @@ -244,7 +245,7 @@ val_initialize_test(uint32_t test_num, char8_t *desc, uint32_t num_pe, uint32_t val_print(AVS_PRINT_ERR, "%4d : ", test_num); //Always print this val_print(AVS_PRINT_TEST, desc, 0); - val_report_status(0, SBSA_AVS_START(level, test_num)); + val_report_status(0, SBSA_AVS_START(level, test_num), ruleid); val_pe_initialize_default_exception_handler(val_pe_default_esr); g_sbsa_tests_total++; @@ -454,7 +455,7 @@ val_run_test_payload(uint32_t test_num, uint32_t num_pe, void (*payload)(void), @return Success or on failure - status of the last failed PE **/ uint32_t -val_check_for_error(uint32_t test_num, uint32_t num_pe) +val_check_for_error(uint32_t test_num, uint32_t num_pe, char8_t *ruleid) { uint32_t i; uint32_t status = 0; @@ -465,7 +466,7 @@ val_check_for_error(uint32_t test_num, uint32_t num_pe) of pe_info_table but num_pe is 1 for SOC tests */ if (num_pe == 1) { status = val_get_status(my_index); - val_report_status(my_index, status); + val_report_status(my_index, status, ruleid); if (IS_TEST_PASS(status)) { g_sbsa_tests_pass++; return AVS_STATUS_PASS; @@ -481,14 +482,14 @@ val_check_for_error(uint32_t test_num, uint32_t num_pe) status = val_get_status(i); //val_print(AVS_PRINT_ERR, "Status %4x \n", status); if (IS_TEST_FAIL_SKIP(status)) { - val_report_status(i, status); + val_report_status(i, status, ruleid); error_flag += 1; break; } } if (!error_flag) - val_report_status(my_index, status); + val_report_status(my_index, status, ruleid); if (IS_TEST_PASS(status)) { g_sbsa_tests_pass++; From 4b36750957c13483b1fdd73b278fae178f5d5ca9 Mon Sep 17 00:00:00 2001 From: Rajat Goyal Date: Thu, 12 Jan 2023 17:35:46 +0530 Subject: [PATCH 2/8] SBSA 7.1 Changes - Added MPAM Related tests - Added New PMU Tests - Added RAS tests - Exerciser Test Bug Fixes - Nist Test changes Signed-off-by: Rajat Goyal --- test_pool/exerciser/test_e003.c | 3 + test_pool/exerciser/test_e005.c | 6 + test_pool/exerciser/test_e011.c | 3 + test_pool/exerciser/test_e012.c | 21 +- test_pool/exerciser/test_e013.c | 3 + test_pool/exerciser/test_e015.c | 14 +- .../mpam/operating_system/test_mpam001.c | 77 ++ .../mpam/operating_system/test_mpam002.c | 140 +++ .../mpam/operating_system/test_mpam003.c | 213 ++++ .../mpam/operating_system/test_mpam004.c | 141 +++ .../mpam/operating_system/test_mpam005.c | 131 ++ .../mpam/operating_system/test_mpam006.c | 299 +++++ test_pool/nist_sts/test_n001.c | 14 +- test_pool/pcie/operating_system/test_p009.c | 148 +++ test_pool/pcie/operating_system/test_p061.c | 197 +++ test_pool/pcie/operating_system/test_p062.c | 102 ++ test_pool/pmu/operating_system/test_pmu001.c | 112 ++ test_pool/pmu/operating_system/test_pmu002.c | 63 + test_pool/pmu/operating_system/test_pmu003.c | 66 + test_pool/pmu/operating_system/test_pmu004.c | 228 ++++ test_pool/pmu/operating_system/test_pmu005.c | 186 +++ test_pool/pmu/operating_system/test_pmu006.c | 78 ++ test_pool/pmu/operating_system/test_pmu007.c | 204 ++++ test_pool/pmu/operating_system/test_pmu008.c | 253 ++++ test_pool/pmu/operating_system/test_pmu009.c | 146 +++ test_pool/ras/operating_system/test_ras001.c | 120 ++ test_pool/ras/operating_system/test_ras002.c | 134 ++ test_pool/ras/operating_system/test_ras003.c | 130 ++ test_pool/ras/operating_system/test_ras004.c | 130 ++ test_pool/ras/operating_system/test_ras005.c | 185 +++ test_pool/ras/operating_system/test_ras006.c | 310 +++++ test_pool/ras/operating_system/test_ras007.c | 128 ++ test_pool/ras/operating_system/test_ras008.c | 116 ++ test_pool/ras/operating_system/test_ras009.c | 208 ++++ test_pool/ras/operating_system/test_ras010.c | 86 ++ test_pool/ras/operating_system/test_ras011.c | 259 ++++ test_pool/ras/operating_system/test_ras012.c | 142 +++ uefi_app/SbsaAvs.h | 16 +- uefi_app/SbsaAvs.inf | 39 +- uefi_app/SbsaAvsMain.c | 300 ++++- uefi_app/SbsaAvsNist.inf | 51 +- val/include/pal_interface.h | 362 +++++- val/include/sbsa_avs_common.h | 9 + val/include/sbsa_avs_exerciser.h | 2 +- val/include/sbsa_avs_mmu.h | 34 + val/include/sbsa_avs_mpam.h | 112 ++ val/include/sbsa_avs_mpam_reg.h | 167 +++ val/include/sbsa_avs_pmu.h | 55 + val/include/sbsa_avs_pmu_reg.h | 130 ++ val/include/sbsa_avs_ras.h | 133 ++ val/src/AArch64/MpamSupport.s | 54 + val/src/AArch64/RasSupport.S | 109 ++ val/src/avs_mmu.c | 238 ++++ val/src/avs_mpam.c | 1073 +++++++++++++++++ val/src/avs_pmu.c | 555 +++++++++ val/src/avs_ras.c | 827 +++++++++++++ 56 files changed, 8983 insertions(+), 79 deletions(-) create mode 100644 test_pool/mpam/operating_system/test_mpam001.c create mode 100644 test_pool/mpam/operating_system/test_mpam002.c create mode 100644 test_pool/mpam/operating_system/test_mpam003.c create mode 100644 test_pool/mpam/operating_system/test_mpam004.c create mode 100644 test_pool/mpam/operating_system/test_mpam005.c create mode 100644 test_pool/mpam/operating_system/test_mpam006.c create mode 100644 test_pool/pcie/operating_system/test_p009.c create mode 100644 test_pool/pcie/operating_system/test_p061.c create mode 100644 test_pool/pcie/operating_system/test_p062.c create mode 100644 test_pool/pmu/operating_system/test_pmu001.c create mode 100644 test_pool/pmu/operating_system/test_pmu002.c create mode 100644 test_pool/pmu/operating_system/test_pmu003.c create mode 100644 test_pool/pmu/operating_system/test_pmu004.c create mode 100644 test_pool/pmu/operating_system/test_pmu005.c create mode 100644 test_pool/pmu/operating_system/test_pmu006.c create mode 100644 test_pool/pmu/operating_system/test_pmu007.c create mode 100644 test_pool/pmu/operating_system/test_pmu008.c create mode 100644 test_pool/pmu/operating_system/test_pmu009.c create mode 100644 test_pool/ras/operating_system/test_ras001.c create mode 100644 test_pool/ras/operating_system/test_ras002.c create mode 100644 test_pool/ras/operating_system/test_ras003.c create mode 100644 test_pool/ras/operating_system/test_ras004.c create mode 100644 test_pool/ras/operating_system/test_ras005.c create mode 100644 test_pool/ras/operating_system/test_ras006.c create mode 100644 test_pool/ras/operating_system/test_ras007.c create mode 100644 test_pool/ras/operating_system/test_ras008.c create mode 100644 test_pool/ras/operating_system/test_ras009.c create mode 100644 test_pool/ras/operating_system/test_ras010.c create mode 100644 test_pool/ras/operating_system/test_ras011.c create mode 100644 test_pool/ras/operating_system/test_ras012.c create mode 100644 val/include/sbsa_avs_mmu.h create mode 100644 val/include/sbsa_avs_mpam.h create mode 100644 val/include/sbsa_avs_mpam_reg.h create mode 100644 val/include/sbsa_avs_pmu.h create mode 100644 val/include/sbsa_avs_pmu_reg.h create mode 100644 val/include/sbsa_avs_ras.h create mode 100644 val/src/AArch64/MpamSupport.s create mode 100644 val/src/AArch64/RasSupport.S create mode 100644 val/src/avs_mmu.c create mode 100644 val/src/avs_mpam.c create mode 100644 val/src/avs_pmu.c create mode 100644 val/src/avs_ras.c diff --git a/test_pool/exerciser/test_e003.c b/test_pool/exerciser/test_e003.c index bfe3c184..0fcad4ec 100644 --- a/test_pool/exerciser/test_e003.c +++ b/test_pool/exerciser/test_e003.c @@ -182,6 +182,9 @@ payload(void) if ((pgt_desc.oas = val_smmu_get_info(SMMU_OUT_ADDR_SIZE, master.smmu_index)) == 0) goto test_fail; + /* set pgt_desc.pgt_base to NULL to create new translation table, val_pgt_create + will update pgt_desc.pgt_base to point to created translation table */ + pgt_desc.pgt_base = (uint64_t) NULL; if (val_pgt_create(mem_desc, &pgt_desc)) goto test_fail; diff --git a/test_pool/exerciser/test_e005.c b/test_pool/exerciser/test_e005.c index a1ae015a..b3850676 100644 --- a/test_pool/exerciser/test_e005.c +++ b/test_pool/exerciser/test_e005.c @@ -232,6 +232,9 @@ payload(void) if ((pgt_desc.oas = val_smmu_get_info(SMMU_OUT_ADDR_SIZE, master.smmu_index)) == 0) goto test_fail; + /* set pgt_desc.pgt_base to NULL to create new translation table, val_pgt_create + will update pgt_desc.pgt_base to point to created translation table */ + pgt_desc.pgt_base = (uint64_t) NULL; if (val_pgt_create(mem_desc, &pgt_desc)) goto test_fail; @@ -308,6 +311,9 @@ payload(void) mem_desc->length = test_data_blk_size; mem_desc->attributes |= PGT_STAGE1_AP_RW; + /* set pgt_desc.pgt_base to NULL to create new translation table, val_pgt_create + will update pgt_desc.pgt_base to point to created translation table */ + pgt_desc.pgt_base = (uint64_t) NULL; if (val_pgt_create(mem_desc, &pgt_desc)) goto test_fail; diff --git a/test_pool/exerciser/test_e011.c b/test_pool/exerciser/test_e011.c index adbc02aa..4616848c 100644 --- a/test_pool/exerciser/test_e011.c +++ b/test_pool/exerciser/test_e011.c @@ -199,6 +199,9 @@ payload(void) if ((pgt_desc.oas = val_smmu_get_info(SMMU_OUT_ADDR_SIZE, master.smmu_index)) == 0) goto test_fail; + /* set pgt_desc.pgt_base to NULL to create new translation table, val_pgt_create + will update pgt_desc.pgt_base to point to created translation table */ + pgt_desc.pgt_base = (uint64_t) NULL; if (val_pgt_create(mem_desc, &pgt_desc)) goto test_fail; diff --git a/test_pool/exerciser/test_e012.c b/test_pool/exerciser/test_e012.c index bf5a76a0..a31f646b 100644 --- a/test_pool/exerciser/test_e012.c +++ b/test_pool/exerciser/test_e012.c @@ -245,6 +245,8 @@ payload(void) if (val_pcie_get_rootport(req_e_bdf, &req_rp_bdf)) continue; + val_print(AVS_PRINT_DEBUG, "\n bdf is 0x%x", req_e_bdf); + val_print(AVS_PRINT_DEBUG, "\n RP bdf is 0x%x", req_rp_bdf); /* It ACS Not Supported, Fail.*/ if (val_pcie_find_capability(req_rp_bdf, PCIE_ECAP, ECID_ACS, &cap_base) != PCIE_SUCCESS) { val_print(AVS_PRINT_ERR, "\n ACS Not Supported for BDF : 0x%x", req_rp_bdf); @@ -258,9 +260,15 @@ payload(void) val_pcie_write_cfg(req_rp_bdf, cap_base + ACSCR_OFFSET, reg_value); /* Find another exerciser on other rootport, - Break from the test if no such exerciser if found */ + Break from the test if no such exerciser if found and + Disable Source Validation & Transaction Blocking of req_rp_bdf*/ if (get_target_exer_bdf(req_rp_bdf, &tgt_e_bdf, &tgt_rp_bdf, &bar_base)) - continue; + { + val_pcie_read_cfg(req_rp_bdf, cap_base + ACSCR_OFFSET, ®_value); + reg_value = reg_value & (0 << ACS_CTRL_SVE_SHIFT) & (0 << ACS_CTRL_TBE_SHIFT); + val_pcie_write_cfg(req_rp_bdf, cap_base + ACSCR_OFFSET, reg_value); + continue; + } /* Enable Source Validation & Transaction Blocking */ val_pcie_read_cfg(tgt_rp_bdf, cap_base + ACSCR_OFFSET, ®_value); @@ -279,18 +287,23 @@ payload(void) status = check_transaction_blocking(instance, req_rp_bdf, bar_base); if (status == AVS_STATUS_SKIP) - val_print(AVS_PRINT_DEBUG, "\n ACS Transaction Blocking Skipped for 0x%x", req_rp_bdf); + val_print(AVS_PRINT_DEBUG, "\n ACS Transaction Blocking Skipped for 0x%x", req_rp_bdf); else if (status) curr_bdf_failed++; if(curr_bdf_failed > 0) { - val_print(AVS_PRINT_ERR, "\n ACS Functional Check Failed, RP Bdf : 0x%x", req_rp_bdf); + val_print(AVS_PRINT_ERR, "\n ACS Functional Check Failed, RP Bdf : 0x%x", req_rp_bdf); curr_bdf_failed = 0; fail_cnt++; } /* Clear Error Status Bits */ val_pcie_clear_device_status_error(req_rp_bdf); val_pcie_clear_sig_target_abort(req_rp_bdf); + + /* Disable Source Validation & Transaction Blocking */ + val_pcie_read_cfg(tgt_rp_bdf, cap_base + ACSCR_OFFSET, ®_value); + reg_value = reg_value & (0 << ACS_CTRL_SVE_SHIFT) & (0 << ACS_CTRL_TBE_SHIFT); + val_pcie_write_cfg(tgt_rp_bdf, cap_base + ACSCR_OFFSET, reg_value); } if (test_skip == 1) diff --git a/test_pool/exerciser/test_e013.c b/test_pool/exerciser/test_e013.c index 57fe8645..876a981a 100644 --- a/test_pool/exerciser/test_e013.c +++ b/test_pool/exerciser/test_e013.c @@ -161,6 +161,9 @@ create_va_pa_mapping (uint64_t txn_va, uint64_t txn_pa, if (!pgt_desc->oas) return AVS_STATUS_FAIL; + /* set pgt_desc.pgt_base to NULL to create new translation table, val_pgt_create + will update pgt_desc.pgt_base to point to created translation table */ + pgt_desc->pgt_base = (uint64_t) NULL; if (val_pgt_create(mem_desc, pgt_desc)) return AVS_STATUS_FAIL; diff --git a/test_pool/exerciser/test_e015.c b/test_pool/exerciser/test_e015.c index eb704c43..2cc66080 100644 --- a/test_pool/exerciser/test_e015.c +++ b/test_pool/exerciser/test_e015.c @@ -54,12 +54,7 @@ static uint32_t test_sequence_check(uint32_t instance) uint64_t num_transactions; uint64_t transaction_type; - /* Get number of transactions captured from exerciser */ - val_exerciser_get_param(NUM_TRANSACTIONS, NULL, &num_transactions, instance); - if (num_transactions != sizeof(transaction_order)/sizeof(transaction_order[0])) { - val_print(AVS_PRINT_ERR, "\n Exerciser %d gathering check failed", instance); - return 1; - } + num_transactions = sizeof(transaction_order)/sizeof(transaction_order[0]); /* Check transactions arrival order */ for (idx = 0; idx < sizeof(transaction_order)/sizeof(transaction_order[0]); idx++) { @@ -69,6 +64,13 @@ static uint32_t test_sequence_check(uint32_t instance) return 1; } } + + /* Get number of transactions captured from exerciser */ + if (num_transactions != idx) { + val_print(AVS_PRINT_ERR, "\n Exerciser %d gathering check failed", instance); + return 1; + } + return 0; } diff --git a/test_pool/mpam/operating_system/test_mpam001.c b/test_pool/mpam/operating_system/test_mpam001.c new file mode 100644 index 00000000..c9e76846 --- /dev/null +++ b/test_pool/mpam/operating_system/test_mpam001.c @@ -0,0 +1,77 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_common.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_mpam.h" + + +#define TEST_NUM (AVS_MPAM_TEST_NUM_BASE + 1) +#define TEST_RULE "S_L7MP_01, S_L7MP_02" +#define TEST_DESC "Check for MPAM extension " + +static void payload(void) +{ + uint32_t pe_index; + uint64_t data = 0; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 7) { + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* PEs must implement FEAT_MPAM */ + /* ID_AA64PFR0_EL1.MPAM bits[43:40] > 0 or ID_AA64PFR1_EL1.MPAM_frac bits[19:16] > 0 + indicates implementation of MPAM extension */ + + if (!((VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 40, 43) > 0) || + (VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR1_EL1), 16, 19) > 0))) { + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + + + /* check support for minimum of 16 physical partition IDs, MPAMIDR_EL1.PARTID_MAX + must be >= 16 */ + data = VAL_EXTRACT_BITS(val_mpam_reg_read(MPAMIDR_EL1), 0, 15); + if (data < 16) { + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } + + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t mpam001_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/mpam/operating_system/test_mpam002.c b/test_pool/mpam/operating_system/test_mpam002.c new file mode 100644 index 00000000..ad3ffc50 --- /dev/null +++ b/test_pool/mpam/operating_system/test_mpam002.c @@ -0,0 +1,140 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_common.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_mpam.h" + + +#define TEST_NUM (AVS_MPAM_TEST_NUM_BASE + 2) +#define TEST_RULE "S_L7MP_03, S_L7MP_04" +#define TEST_DESC "Check for MPAM LLC CSU " + +static void payload(void) +{ + uint32_t llc_index; + uint32_t cache_identifier; + uint32_t msc_node_cnt; + uint32_t rsrc_node_cnt; + uint32_t msc_index, rsrc_index; + uint32_t csumon_count; + uint32_t test_fail = 0; + uint32_t test_run = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 7) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* Check if PE implements FEAT_MPAM */ + if (!((VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 40, 43) > 0) || + (VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR1_EL1), 16, 19) > 0))) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + /* Find the LLC cache identifier */ + llc_index = val_cache_get_llc_index(); + if (llc_index == CACHE_TABLE_EMPTY) { + val_print(AVS_PRINT_ERR, "\n Cache info table empty", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + + cache_identifier = val_cache_get_info(CACHE_ID, llc_index); + if (cache_identifier == INVALID_CACHE_INFO) { + val_print(AVS_PRINT_ERR, "\n LLC invalid in PPTT", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } + + + /* Check in the MPAM table which MSC is attached to the LLC */ + + msc_node_cnt = val_mpam_get_msc_count(); + val_print(AVS_PRINT_DEBUG, "\n MSC count = %d", msc_node_cnt); + + if (msc_node_cnt == 0) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03)); + return; + } + + /* visit each MSC node and check for cache resources */ + for (msc_index = 0; msc_index < msc_node_cnt; msc_index++) { + rsrc_node_cnt = val_mpam_get_info(MPAM_MSC_RSRC_COUNT, msc_index, 0); + + val_print(AVS_PRINT_DEBUG, "\n msc index = %d", msc_index); + val_print(AVS_PRINT_DEBUG, "\n Resource count %d = ", rsrc_node_cnt); + + for (rsrc_index = 0; rsrc_index < rsrc_node_cnt; rsrc_index++) { + + /* check whether the resource location is cache */ + if (val_mpam_get_info(MPAM_MSC_RSRC_TYPE, msc_index, rsrc_index) == + MPAM_RSRC_TYPE_PE_CACHE) { + if (val_mpam_get_info(MPAM_MSC_RSRC_DESC1, msc_index, rsrc_index) == + cache_identifier) { + /* We have MSC which controls/monitors the LLC cache */ + val_print(AVS_PRINT_DEBUG, "\n rsrc index = %d", rsrc_index); + + test_run = 1; + /* Check CSU monitor are present */ + if (!val_mpam_supports_csumon(msc_index)) { + val_print(AVS_PRINT_ERR, "\n CSU MON unsupported by LLC", 0); + test_fail = 1; + } + /* Check min 16 CSU monitor are present */ + csumon_count = val_mpam_get_csumon_count(msc_index); + if (csumon_count < 16) { + val_print(AVS_PRINT_ERR, "\n CSU MON %d less than 16", csumon_count); + test_fail = 1; + } + } + } + } + } + + if (!test_run) { + val_print(AVS_PRINT_ERR, "\n No LLC MSC found", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 04)); + return; + } + + if (test_fail) + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 05)); + else + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + +} + +uint32_t mpam002_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/mpam/operating_system/test_mpam003.c b/test_pool/mpam/operating_system/test_mpam003.c new file mode 100644 index 00000000..94a8cc7e --- /dev/null +++ b/test_pool/mpam/operating_system/test_mpam003.c @@ -0,0 +1,213 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_common.h" +#include "val/include/sbsa_avs_memory.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_mpam.h" + + +#define TEST_NUM (AVS_MPAM_TEST_NUM_BASE + 3) +#define TEST_RULE "S_L7MP_05, S_L7MP_06" +#define TEST_DESC "Check for MPAM MBWUs Monitor func " + +#define BUFFER_SIZE 65536 /* 64 Kilobytes*/ + +static void payload(void) +{ + uint32_t pe_index; + uint32_t msc_node_cnt, msc_index; + uint32_t rsrc_node_cnt, rsrc_index; + uint64_t mpam2_el2, mpam2_el2_temp; + uint64_t byte_count; + uint64_t addr_base, addr_len; + uint64_t nrdy_timeout; + uint32_t test_fails = 0; + uint32_t test_skip = 1; + void *src_buf = 0; + void *dest_buf = 0; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 7) { + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* Check if PE implements FEAT_MPAM */ + if (!((VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 40, 43) > 0) || + (VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR1_EL1), 16, 19) > 0))) { + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + + /* get total number of MSCs reported by MPAM ACPI table */ + msc_node_cnt = val_mpam_get_msc_count(); + val_print(AVS_PRINT_DEBUG, "\n MSC count = %d", msc_node_cnt); + + if (!msc_node_cnt) { + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); + return; + } + + /* MSC must implement MPAM v1.1 version */ + for (msc_index = 0; msc_index < msc_node_cnt; msc_index++) { + if (val_mpam_msc_get_version(msc_index) != MPAM_VERSION_1_1) { + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03)); + return; + } + } + + /* read MPAM2_EL2 and store the value for restoring later */ + mpam2_el2 = val_mpam_reg_read(MPAM2_EL2); + mpam2_el2_temp = mpam2_el2; + + /* Write DEFAULT_PARTID & DEFAULT PMG to mpam2_el2 to generate PE traffic */ + mpam2_el2 = (mpam2_el2 & ~(MPAMn_ELx_PARTID_D_MASK << MPAMn_ELx_PARTID_D_SHIFT)) | + DEFAULT_PARTID << MPAMn_ELx_PARTID_D_SHIFT; + mpam2_el2 = (mpam2_el2 & ~(MPAMn_ELx_PMG_D_MASK << MPAMn_ELx_PMG_D_SHIFT)) | + DEFAULT_PMG << MPAMn_ELx_PMG_D_SHIFT; + + val_print(AVS_PRINT_DEBUG, "\n Value written to MPAM2_EL2 = 0x%llx", mpam2_el2); + val_mpam_reg_write(MPAM2_EL2, mpam2_el2); + + /* visit each MSC node and check for memory resources */ + for (msc_index = 0; msc_index < msc_node_cnt; msc_index++) { + rsrc_node_cnt = val_mpam_get_info(MPAM_MSC_RSRC_COUNT, msc_index, 0); + + val_print(AVS_PRINT_DEBUG, "\n msc index = %d", msc_index); + val_print(AVS_PRINT_DEBUG, "\n Resource count %d = ", rsrc_node_cnt); + + for (rsrc_index = 0; rsrc_index < rsrc_node_cnt; rsrc_index++) { + + /* check whether the resource location is memory */ + if (val_mpam_get_info(MPAM_MSC_RSRC_TYPE, msc_index, rsrc_index) == + MPAM_RSRC_TYPE_MEMORY) { + + /* As per S_L7MP_05, MBWU monitoring must be supported for general purpose mem */ + if (!val_mpam_msc_supports_mbwumon(msc_index)) { + val_print(AVS_PRINT_ERR, "\n MBWU MON unsupported by MSC %d", msc_index); + test_fails++; + break; + } + + test_skip = 0; + /* select resource instance if RIS feature implemented */ + if (val_mpam_msc_supports_ris(msc_index)) + val_mpam_memory_configure_ris_sel(msc_index, rsrc_index); + + val_print(AVS_PRINT_DEBUG, "\n rsrc index = %d", rsrc_index); + + /* Allocate source and destination memory buffers*/ + addr_base = val_mpam_memory_get_base(msc_index, rsrc_index); + addr_len = val_mpam_memory_get_size(msc_index, rsrc_index); + + if ((addr_base == SRAT_INVALID_INFO) || (addr_len == SRAT_INVALID_INFO) || + (addr_len <= 2 * BUFFER_SIZE)) { /* src and dst buffer size */ + val_print(AVS_PRINT_ERR, "\n No SRAT mem range info found", 0); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + + /* Restore MPAM2_EL2 settings */ + val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); + return; + } + + + src_buf = (void *)val_mem_alloc_at_address(addr_base, BUFFER_SIZE); + dest_buf = (void *)val_mem_alloc_at_address(addr_base + BUFFER_SIZE, BUFFER_SIZE); + + if ((src_buf == NULL) || (dest_buf == NULL)) { + val_print(AVS_PRINT_ERR, "\n Memory allocation of buffers failed", 0); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + + /* Restore MPAM2_EL2 settings */ + val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); + return; + } + + /* configure MBWU Monitor for this memory resource node */ + val_mpam_memory_configure_mbwumon(msc_index); + + /* enable MBWU monitoring */ + val_mpam_memory_mbwumon_enable(msc_index); + + + /* wait for MAX_NRDY_USEC after msc config change */ + nrdy_timeout = val_mpam_get_info(MPAM_MSC_NRDY, msc_index, 0); + while (nrdy_timeout) { + --nrdy_timeout; + }; + + /* perform memory operation */ + val_memcpy(src_buf, dest_buf, BUFFER_SIZE); + + /* read the memory bandwidth usage monitor */ + byte_count = val_mpam_memory_mbwumon_read_count(msc_index); + + /* disable and reset the MBWU monitor */ + val_mpam_memory_mbwumon_disable(msc_index); + val_mpam_memory_mbwumon_reset(msc_index); + + val_print(AVS_PRINT_DEBUG, "\n byte_count = 0x%llx bytes", byte_count); + + /* the monitor should count both read and write bandwidth, + hence count should be twice of the buffer size */ + if ((byte_count != 2 * BUFFER_SIZE)) { + val_print(AVS_PRINT_ERR, "\n Monitor count incorrect for MSC %d", + msc_index); + val_print(AVS_PRINT_ERR, " rsrc node %d", rsrc_index); + test_fails++; + } + + /* free the buffers */ + val_mem_free_at_address((uint64_t)src_buf, BUFFER_SIZE); + val_mem_free_at_address((uint64_t)dest_buf, BUFFER_SIZE); + } + } + } + /* Restore MPAM2_EL2 settings */ + val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); + + if (test_fails) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 04)); + else if (test_skip) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 04)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + + return; +} + +uint32_t mpam003_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, + TEST_RULE); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/mpam/operating_system/test_mpam004.c b/test_pool/mpam/operating_system/test_mpam004.c new file mode 100644 index 00000000..7db82c2b --- /dev/null +++ b/test_pool/mpam/operating_system/test_mpam004.c @@ -0,0 +1,141 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_common.h" +#include "val/include/sbsa_avs_memory.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_mpam.h" + + +#define TEST_NUM (AVS_MPAM_TEST_NUM_BASE + 4) +#define TEST_RULE "S_L7MP_07" +#define TEST_DESC "Check for MBWU counter size " + +#define MBWU_COUNTER_44BIT 0 +#define MAX_44BIT_COUNTER_BW 1677722 /* this is in MB (1.6 TB) */ + +static void payload(void) +{ + uint32_t pe_index; + uint32_t msc_node_cnt, msc_index; + uint32_t rsrc_node_cnt, rsrc_index; + uint64_t mbwu_bw; + uint32_t test_fails = 0; + uint32_t test_skip = 1; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 7) { + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + /* Check if PE implements FEAT_MPAM */ + if (!((VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 40, 43) > 0) || + (VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR1_EL1), 16, 19) > 0))) { + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + /* get total number of MSCs reported by MPAM ACPI table */ + msc_node_cnt = val_mpam_get_msc_count(); + val_print(AVS_PRINT_DEBUG, "\n MSC count = %d", msc_node_cnt); + + if (!msc_node_cnt) { + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* visit each MSC node and check for memory resources */ + for (msc_index = 0; msc_index < msc_node_cnt; msc_index++) { + rsrc_node_cnt = val_mpam_get_info(MPAM_MSC_RSRC_COUNT, msc_index, 0); + + val_print(AVS_PRINT_DEBUG, "\n msc index = %d", msc_index); + val_print(AVS_PRINT_DEBUG, "\n Resource count %d = ", rsrc_node_cnt); + + for (rsrc_index = 0; rsrc_index < rsrc_node_cnt; rsrc_index++) { + + /* check whether the resource location is memory */ + if (val_mpam_get_info(MPAM_MSC_RSRC_TYPE, msc_index, rsrc_index) == + MPAM_RSRC_TYPE_MEMORY) { + + /* As per S_L7MP_05, MBWU monitoring must be supported for general purpose mem */ + if (!val_mpam_msc_supports_mbwumon(msc_index)) { + val_print(AVS_PRINT_ERR, "\n MBWU MON unsupported by MSC %d", msc_index); + test_fails++; + break; + } + + test_skip = 0; + + /* L7MP_07, MBWU counter size must be 44 bit for interface b/w upto 1.6 TB/s + else 66 bit. Check MBWUMON_IDR HAS_LONG[30] and LWD[29] bits. The reg is + present only if mbwumon is supported */ + if (!val_mpam_msc_supports_mbwumon(msc_index)) { + val_print(AVS_PRINT_ERR, "\n MBWU MON unsupported by MSC %d", msc_index); + test_fails++; + break; + } + if (!val_mpam_mbwu_supports_long(msc_index)) { + val_print(AVS_PRINT_ERR, "\n MBWU long unsupported MSC %d", msc_index); + test_fails++; + break; + } + mbwu_bw = val_mpam_msc_get_mscbw(msc_index, rsrc_index); + if (mbwu_bw == HMAT_INVALID_INFO) + { + val_print(AVS_PRINT_ERR, "\n No HMAT info ", 0); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } + if ((val_mpam_mbwu_supports_lwd(msc_index) == MBWU_COUNTER_44BIT) + && (mbwu_bw >= MAX_44BIT_COUNTER_BW)) { + val_print(AVS_PRINT_ERR, "\n MBWU supported b/w %d", mbwu_bw); + test_fails++; + break; + } + } + } + } + + if (test_fails) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03)); + else if (test_skip) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + + return; +} + +uint32_t mpam004_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, + TEST_RULE); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/mpam/operating_system/test_mpam005.c b/test_pool/mpam/operating_system/test_mpam005.c new file mode 100644 index 00000000..33b32070 --- /dev/null +++ b/test_pool/mpam/operating_system/test_mpam005.c @@ -0,0 +1,131 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_common.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_mpam.h" +#include "val/include/sbsa_avs_peripherals.h" + +#define TEST_NUM (AVS_MPAM_TEST_NUM_BASE + 5) +#define TEST_RULE "S_L7MP_08" +#define TEST_DESC "Check for MPAM MSC address overlap" + +static void payload(void) +{ + uint32_t msc_node_cnt; + uint32_t msc_index; + uint32_t msc_index1; + uint64_t msc_addr; + uint32_t msc_len; + uint64_t msc_addr1; + uint32_t test_fails = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + uint64_t peri_count; + uint64_t peripheral_base; + + if (g_sbsa_level < 7) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + msc_node_cnt = val_mpam_get_msc_count(); + val_print(AVS_PRINT_DEBUG, "\n MSC count = %d", msc_node_cnt); + + if (msc_node_cnt == 0) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* Check MSC memory node size are not overlapping with other MSC */ + for (msc_index = 0; msc_index < msc_node_cnt; msc_index++) { + msc_addr = val_mpam_get_info(MPAM_MSC_BASE_ADDR, msc_index, 0); + msc_len = val_mpam_get_info(MPAM_MSC_ADDR_LEN, msc_index, 0); + + for (msc_index1 = msc_index + 1; msc_index1 < msc_node_cnt; msc_index1++) { + msc_addr1 = val_mpam_get_info(MPAM_MSC_BASE_ADDR, msc_index1, 0); + + if (msc_addr1 >= msc_addr && msc_addr1 <= (msc_addr + msc_len)) { + val_print(AVS_PRINT_ERR, "\n MSC %d and", msc_index); + val_print(AVS_PRINT_ERR, " %d memory layout overlapping", msc_index1); + test_fails++; + } + } + + /* Check with peripherals - USB */ + peri_count = val_peripheral_get_info(NUM_USB, 0); + while (peri_count) { + --peri_count; //array index starts from 0, so subtract 1 from count + val_print(AVS_PRINT_DEBUG, "\n USB index %d", peri_count); + peripheral_base = val_peripheral_get_info(USB_BASE0, peri_count); + if (peripheral_base >= msc_addr && peripheral_base <= (msc_addr + msc_len)) { + val_print(AVS_PRINT_ERR, "\n MSC %d and", msc_index); + val_print(AVS_PRINT_ERR, " USB %d memory layout overlapping", peri_count); + test_fails++; + } + } + + + /* Check with peripherals - UART */ + peri_count = val_peripheral_get_info(NUM_UART, 0); + while (peri_count) { + --peri_count; //array index starts from 0, so subtract 1 from count + val_print(AVS_PRINT_DEBUG, "\n UART index %d", peri_count); + peripheral_base = val_peripheral_get_info(UART_BASE0, peri_count); + if (peripheral_base >= msc_addr && peripheral_base <= (msc_addr + msc_len)) { + val_print(AVS_PRINT_ERR, "\n MSC %d and", msc_index); + val_print(AVS_PRINT_ERR, " UART %d memory layout overlapping", peri_count); + test_fails++; + } + } + + /* Check with peripherals - SATA */ + peri_count = val_peripheral_get_info(NUM_SATA, 0); + while (peri_count) { + --peri_count; //array index starts from 0, so subtract 1 from count + val_print(AVS_PRINT_DEBUG, "\n SATA index %d", peri_count); + peripheral_base = val_peripheral_get_info(SATA_BASE0, peri_count); + if (peripheral_base >= msc_addr && peripheral_base <= (msc_addr + msc_len)) { + val_print(AVS_PRINT_ERR, "\n MSC %d and", msc_index); + val_print(AVS_PRINT_ERR, " SATA %d memory layout overlapping", peri_count); + test_fails++; + } + } + } + + if (test_fails) + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + else + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t mpam005_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/mpam/operating_system/test_mpam006.c b/test_pool/mpam/operating_system/test_mpam006.c new file mode 100644 index 00000000..484712a8 --- /dev/null +++ b/test_pool/mpam/operating_system/test_mpam006.c @@ -0,0 +1,299 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_common.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_mpam.h" +#include "val/include/sbsa_avs_memory.h" + +#define TEST_NUM (AVS_MPAM_TEST_NUM_BASE + 6) +#define TEST_RULE "S_L7MP_03" +#define TEST_DESC "Check PMG storage by CPOR nodes " + +#define PARTITION_PERCENTAGE 75 +#define CACHE_PERCENTAGE 50 + +static uint64_t mpam2_el2_temp; + +static void payload(void) +{ + uint32_t msc_node_cnt; + uint32_t rsrc_node_cnt; + uint32_t msc_index; + uint32_t rsrc_index; + uint32_t llc_index; + uint32_t cache_identifier; + uint32_t cache_size; + uint32_t max_pmg; + uint32_t max_partid; + uint32_t cpor_nodes = 0; + uint32_t csumon_count = 0; + uint8_t pmg1; + uint8_t pmg2; + void *src_buf = 0; + void *dest_buf = 0; + uint64_t buf_size; + uint64_t mpam2_el2 = 0; + uint64_t nrdy_timeout; + uint32_t storage_value1; + uint32_t storage_value2; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 7) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* Check if PE implements FEAT_MPAM */ + if (!((VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 40, 43) > 0) || + (VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR1_EL1), 16, 19) > 0))) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + /* Get the Index for LLC */ + llc_index = val_cache_get_llc_index(); + if (llc_index == CACHE_TABLE_EMPTY) { + val_print(AVS_PRINT_ERR, "\n Cache info table empty", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* Get the cache identifier for LLC */ + cache_identifier = val_cache_get_info(CACHE_ID, llc_index); + if (cache_identifier == INVALID_CACHE_INFO) { + val_print(AVS_PRINT_ERR, "\n LLC invalid in PPTT", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } + + /* Get total number of MSCs reported by MPAM ACPI table */ + msc_node_cnt = val_mpam_get_msc_count(); + val_print(AVS_PRINT_DEBUG, "\n MSC count = %d", msc_node_cnt); + + if (msc_node_cnt == 0) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03)); + return; + } + + /* Get MPAM related information for LLC */ + for (msc_index = 0; msc_index < msc_node_cnt; msc_index++) { + rsrc_node_cnt = val_mpam_get_info(MPAM_MSC_RSRC_COUNT, msc_index, 0); + for (rsrc_index = 0; rsrc_index < rsrc_node_cnt; rsrc_index++) { + if (val_mpam_get_info(MPAM_MSC_RSRC_TYPE, msc_index, rsrc_index) == + MPAM_RSRC_TYPE_PE_CACHE) { + if (val_mpam_get_info(MPAM_MSC_RSRC_DESC1, msc_index, rsrc_index) == + cache_identifier) { + if (val_mpam_supports_cpor(msc_index)) { + cache_size = val_cache_get_info(CACHE_SIZE, llc_index); + + max_pmg = val_mpam_get_max_pmg(msc_index); + + if (val_mpam_supports_csumon(msc_index)) + csumon_count = val_mpam_get_csumon_count(msc_index); + cpor_nodes++; + } + max_partid = val_mpam_get_max_partid(msc_index); + } + } + } + } + + val_print(AVS_PRINT_DEBUG, "\n CPOR Nodes = %d", cpor_nodes); + val_print(AVS_PRINT_DEBUG, "\n Max PMG = %d", max_pmg); + val_print(AVS_PRINT_DEBUG, "\n Max PARTID = %d", max_partid); + val_print(AVS_PRINT_DEBUG, "\n Cache Size = 0x%x", cache_size); + val_print(AVS_PRINT_DEBUG, "\n Number of CSU Monitors = %d", csumon_count); + + if (csumon_count == 0 || cpor_nodes == 0) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); + return; + } + + /* Configure CPOR settings for nodes supporting CPOR */ + for (msc_index = 0; msc_index < msc_node_cnt; msc_index++) { + rsrc_node_cnt = val_mpam_get_info(MPAM_MSC_RSRC_COUNT, msc_index, 0); + for (rsrc_index = 0; rsrc_index < rsrc_node_cnt; rsrc_index++) { + if (val_mpam_get_info(MPAM_MSC_RSRC_TYPE, msc_index, rsrc_index) == + MPAM_RSRC_TYPE_PE_CACHE) { + if (val_mpam_get_info(MPAM_MSC_RSRC_DESC1, msc_index, rsrc_index) == + cache_identifier) { + /* Select resource instance if RIS feature implemented */ + if (val_mpam_msc_supports_ris(msc_index)) + val_mpam_memory_configure_ris_sel(msc_index, rsrc_index); + + if (val_mpam_supports_cpor(msc_index)) + val_mpam_configure_cpor(msc_index, max_partid, PARTITION_PERCENTAGE); + } + } + } + } + + /* Create two PMG groups for PE traffic */ + pmg1 = max_pmg; + pmg2 = max_pmg-1; + + mpam2_el2 = val_mpam_reg_read(MPAM2_EL2); + mpam2_el2_temp = mpam2_el2; + + /* visit each MSC node and check for Cache resources */ + for (msc_index = 0; msc_index < msc_node_cnt; msc_index++) { + rsrc_node_cnt = val_mpam_get_info(MPAM_MSC_RSRC_COUNT, msc_index, 0); + + val_print(AVS_PRINT_DEBUG, "\n msc index = %d", msc_index); + val_print(AVS_PRINT_DEBUG, "\n Resource count %d = ", rsrc_node_cnt); + + for (rsrc_index = 0; rsrc_index < rsrc_node_cnt; rsrc_index++) { + + /* Check whether resource node is a PE Cache */ + if (val_mpam_get_info(MPAM_MSC_RSRC_TYPE, msc_index, rsrc_index) == + MPAM_RSRC_TYPE_PE_CACHE) { + + /*Check if the PE Cache ID matches LLC ID */ + if (val_mpam_get_info(MPAM_MSC_RSRC_DESC1, msc_index, rsrc_index) == + cache_identifier) { + + buf_size = cache_size * CACHE_PERCENTAGE / 100 ; + + /*Allocate memory for source and destination buffers */ + src_buf = (void *)val_memory_alloc(buf_size); + dest_buf = (void *)val_memory_alloc(buf_size); + + val_print(AVS_PRINT_DEBUG, "\n buf_size = 0x%x", buf_size); + + if ((src_buf == NULL) || (dest_buf == NULL)) { + val_print(AVS_PRINT_ERR, "\n Mem allocation failed", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 04)); + } + + /* Clear the PARTID_D & PMG_D bits in mpam2_el2 before writing to them */ + mpam2_el2 = CLEAR_BITS_M_TO_N(mpam2_el2, MPAMn_ELx_PARTID_D_SHIFT+15, + MPAMn_ELx_PARTID_D_SHIFT); + mpam2_el2 = CLEAR_BITS_M_TO_N(mpam2_el2, MPAMn_ELx_PMG_D_SHIFT+7, + MPAMn_ELx_PMG_D_SHIFT); + + /* Write MAX_PARTID & PMG2 to MPAM2_EL2 and generate PE traffic */ + mpam2_el2 |= (((uint64_t)pmg2 << MPAMn_ELx_PMG_D_SHIFT) | + ((uint64_t)max_partid << MPAMn_ELx_PARTID_D_SHIFT)); + + val_mpam_reg_write(MPAM2_EL2, mpam2_el2); + + /* Configure CSU monitors with PMG1 */ + if (val_mpam_supports_cpor(msc_index) && val_mpam_supports_csumon(msc_index)) + val_mpam_configure_csu_mon(msc_index, max_partid, pmg1, 0); + + /* Enable CSU monitoring */ + val_mpam_csumon_enable(msc_index); + + /* wait for MAX_NRDY_USEC after msc config change */ + nrdy_timeout = val_mpam_get_info(MPAM_MSC_NRDY, msc_index, 0); + while (nrdy_timeout) { + --nrdy_timeout; + }; + + /*Perform first memory transaction */ + val_memcpy(src_buf, dest_buf, buf_size); + + /* Read Cache storage value */ + storage_value1 = val_mpam_read_csumon(msc_index); + + val_print(AVS_PRINT_DEBUG, "\n Storage Value 1 = 0x%x", storage_value1); + + /*Restore initial MPAM_EL2 settings */ + mpam2_el2 = mpam2_el2_temp; + + /* Clear the PARTID_D & PMG_D bits in mpam2_el2 before writing to them */ + mpam2_el2 = CLEAR_BITS_M_TO_N(mpam2_el2, MPAMn_ELx_PARTID_D_SHIFT+15, + MPAMn_ELx_PARTID_D_SHIFT); + mpam2_el2 = CLEAR_BITS_M_TO_N(mpam2_el2, MPAMn_ELx_PMG_D_SHIFT+7, + MPAMn_ELx_PMG_D_SHIFT); + + /* Write MAX_PARTID & PMG1 to MPAM2_EL2 and generate PE traffic */ + mpam2_el2 |= (((uint64_t)pmg1 << MPAMn_ELx_PMG_D_SHIFT) | + ((uint64_t)max_partid << MPAMn_ELx_PARTID_D_SHIFT)); + + val_mpam_reg_write(MPAM2_EL2, mpam2_el2); + + /* Disable the monitor */ + val_mpam_csumon_disable(msc_index); + + /* Enable CSU monitoring */ + val_mpam_csumon_enable(msc_index); + + /* wait for MAX_NRDY_USEC after msc config change */ + nrdy_timeout = val_mpam_get_info(MPAM_MSC_NRDY, msc_index, 0); + while (nrdy_timeout) { + --nrdy_timeout; + }; + + /*Perform second memory transaction */ + val_memcpy(src_buf, dest_buf, buf_size); + + /* Read Cache storage value for PMG1 */ + storage_value2 = val_mpam_read_csumon(msc_index); + + val_print(AVS_PRINT_DEBUG, "\n Storage Value 1 = 0x%x", storage_value2); + + /* Disable the monitor */ + val_mpam_csumon_disable(msc_index); + + /* Test fails if storage_value1 is non zero or storage_value2 is zero */ + if (storage_value1 || !storage_value2) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 05)); + + /*Restore MPAM2_EL2 settings */ + val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); + + /*Free the buffers */ + val_memory_free(src_buf); + val_memory_free(dest_buf); + + return; + } + + /*Restore MPAM2_EL2 settings */ + val_mpam_reg_write(MPAM2_EL2, mpam2_el2_temp); + + /*Free the buffers */ + val_memory_free(src_buf); + val_memory_free(dest_buf); + } + } + } + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + return; +} + +uint32_t mpam006_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/nist_sts/test_n001.c b/test_pool/nist_sts/test_n001.c index b0939fe3..8f02994e 100644 --- a/test_pool/nist_sts/test_n001.c +++ b/test_pool/nist_sts/test_n001.c @@ -38,6 +38,16 @@ extern int main(int argc, char *argv[]); +static int acs_strnlen(const char *buffer, size_t max_len) +{ + size_t len; + for (len = 0; len < max_len; len++, buffer++) { + if (!*buffer) + break; + } + return (len); +} + /*Enabling all NIST test suites(test 1 - 15) by default */ uint32_t test_select = ALL_NIST_TEST; @@ -55,7 +65,7 @@ check_prerequisite_nist(void) * executing NIST test suite. */ for (i = 0; i < REQ_OPEN_FILES; i++) { - sprintf(file_name[i], "tmp_%d.txt", i); + snprintf(file_name[i], 20, "tmp_%d.txt", i); fp[i] = fopen(file_name[i], "wb"); if (fp[i] == NULL) { val_print(AVS_PRINT_ERR, "\nMax # of opened files has been reached. " @@ -96,7 +106,7 @@ print_nist_result(void) while (fgets(buffer, BUFFER_SIZE, fptr) != NULL) { /* Total character read count */ - totalRead = strlen(buffer); + totalRead = acs_strnlen(buffer, BUFFER_SIZE); /* Trim new line character from last if exists */ buffer[totalRead - 1] = buffer[totalRead - 1] == '\n' diff --git a/test_pool/pcie/operating_system/test_p009.c b/test_pool/pcie/operating_system/test_p009.c new file mode 100644 index 00000000..96ca8bbd --- /dev/null +++ b/test_pool/pcie/operating_system/test_p009.c @@ -0,0 +1,148 @@ +/** @file + * Copyright (c) 2016-2018, 2021-2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_memory.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 9) +#define TEST_DESC "Check all MSI(X) vectors are LPIs " +#define TEST_RULE "S_L3GI_02" + +#define LPI_BASE 8192 + +/** + @brief Returns MSI(X) status of the device + + @param dev_index index of PCI device + + @return 0 device does not support MSI(X) + @return 1 device supports MSI(X) +**/ +static +uint32_t +check_msi_status (uint32_t dev_index) { + uint32_t data; + + data = val_peripheral_get_info (ANY_FLAGS, dev_index); + + if ((data & PER_FLAG_MSI_ENABLED) && + val_peripheral_get_info (ANY_GSIV, dev_index)) { + return 1; + } + + return 0; +} + +/** + @brief Free memory allocated for a list of MSI(X) vectors + + @param list pointer to a list of MSI(X) vectors +**/ +static +void +clean_msi_list (PERIPHERAL_VECTOR_LIST *list) +{ + PERIPHERAL_VECTOR_LIST *next_node; + PERIPHERAL_VECTOR_LIST *current_node; + + current_node = list; + while (current_node != NULL) { + next_node = current_node->next; + val_memory_free (current_node); + current_node = next_node; + } +} + +static +void +payload (void) +{ + + uint32_t count = val_peripheral_get_info (NUM_ALL, 0); + uint32_t index = val_pe_get_index_mpid (val_pe_get_mpid()); + uint8_t status; + PERIPHERAL_VECTOR_LIST *dev_mvec, *mvec; + uint64_t dev_bdf; + uint32_t test_skip = 1; + + if(!count) { + val_set_status (index, RESULT_SKIP (g_sbsa_level, TEST_NUM, 2)); + return; + } + + status = 0; + dev_mvec = NULL; + + /* + Pull each discovered PCI device and its list of MSI(X) vectors. + Check whether every vector IRQ number is an LPI or not. + */ + while (count > 0 && !status) { + if (check_msi_status (count - 1)) { + /* Get BDF of a device */ + dev_bdf = val_peripheral_get_info (ANY_BDF, count - 1); + if (dev_bdf) { + val_print (AVS_PRINT_INFO, " Checking PCI device with BDF %4X\n", dev_bdf); + /* Read MSI(X) vectors */ + if (val_get_msi_vectors (dev_bdf, &dev_mvec)) { + test_skip = 0; + mvec = dev_mvec; + while(mvec) { + if(mvec->vector.vector_irq_base < LPI_BASE) { + val_print(AVS_PRINT_INFO, " MSI vector irq %d is not an LPI\n", mvec->vector.vector_irq_base); + val_set_status (index, RESULT_FAIL (g_sbsa_level, TEST_NUM, mvec->vector.vector_irq_base)); + status = 1; + } + mvec = mvec->next; + } + clean_msi_list (dev_mvec); + } + } + } + count--; + } + + if (test_skip) { + val_print(AVS_PRINT_ERR, "\n No MSI vectors found ", 0); + val_set_status (index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 0)); + } else if (!status) { + val_set_status (index, RESULT_PASS(g_sbsa_level, TEST_NUM, 0)); + } +} + +uint32_t +p009_entry (uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + if (status != AVS_STATUS_SKIP) { + val_run_test_payload (TEST_NUM, num_pe, payload, 0); + } + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/pcie/operating_system/test_p061.c b/test_pool/pcie/operating_system/test_p061.c new file mode 100644 index 00000000..0baee70c --- /dev/null +++ b/test_pool/pcie/operating_system/test_p061.c @@ -0,0 +1,197 @@ +/** @file + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 61) +#define TEST_DESC "Check RootPort P&NP Memory Access " +#define TEST_RULE "S_PCI_02" + +static void *branch_to_test; + +static +void +esr(uint64_t interrupt_type, void *context) +{ + uint32_t pe_index; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + + /* Update the ELR to return to test specified address */ + val_pe_update_elr(context, (uint64_t)branch_to_test); + + val_print(AVS_PRINT_INFO, "\n Received exception of type: %d", interrupt_type); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); +} + +static uint32_t test_sequence_1B(uint8_t *addr) +{ + uint32_t write_val = 0xAB; + uint32_t read_value, old_value; + uint32_t pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + + for (int idx = 0; idx < 8; idx++) { + old_value = val_mmio_read8((addr_t)addr); + val_mmio_write8((addr_t)addr, write_val); + read_value = val_mmio_read8((addr_t)addr); + + if ((old_value != read_value && read_value == PCIE_UNKNOWN_RESPONSE)) { + val_print(AVS_PRINT_ERR, "\n Error in read and write 1B", 0); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return 1; + } + + val_mmio_write8((addr_t)addr, old_value); + addr++; + } + + return 0; +} + +uint32_t test_sequence_2B(uint16_t *addr) +{ + uint32_t write_val = 0xABCD; + uint32_t read_value, old_value; + uint32_t pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + + for (int idx = 0; idx < 4; idx++) { + old_value = val_mmio_read16((addr_t)addr); + val_mmio_write16((addr_t)addr, write_val); + read_value = val_mmio_read16((addr_t)addr); + + if ((old_value != read_value && read_value == PCIE_UNKNOWN_RESPONSE)) { + val_print(AVS_PRINT_ERR, "\n Error in read and write 2B", 0); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03)); + return 1; + } + + val_mmio_write16((addr_t)addr, old_value); + addr++; + } + + return 0; +} + +static +void +payload(void) +{ + + uint32_t bdf; + uint32_t pe_index; + uint32_t tbl_index; + uint32_t bar_data; + uint32_t test_fails; + uint32_t test_skip = 1; + uint64_t bar_base = 0; + uint32_t status; + pcie_device_bdf_table *bdf_tbl_ptr; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + + /* Install sync and async handlers to handle exceptions.*/ + status = val_pe_install_esr(EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, esr); + status |= val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); + if (status) + { + val_print(AVS_PRINT_ERR, "\n Failed in installing the exception handler", 0); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + + branch_to_test = &&exception_return; + + bar_data = 0; + tbl_index = 0; + test_fails = 0; + + while (tbl_index < bdf_tbl_ptr->num_entries) + { + bdf = bdf_tbl_ptr->device[tbl_index++].bdf; + + /* + * For Function with Type 1 config space header, obtain + * base address of the its own BAR address. + */ + if ((val_pcie_function_header_type(bdf) == TYPE1_HEADER)) + val_pcie_get_mmio_bar(bdf, &bar_base); + + /* Skip this function if it doesn't have mmio BAR */ + if (!bar_base) + continue; + + /* If test runs for atleast an endpoint */ + test_skip = 0; + + bar_data = val_mmio_read(bar_base); + + if (test_sequence_1B((uint8_t *)bar_base)) { + val_print(AVS_PRINT_ERR, "\n Failed check for Bdf 0x%x", bdf); + test_fails++; + } + + if (test_sequence_2B((uint16_t *)bar_base)) { + val_print(AVS_PRINT_ERR, "\n Failed check for Bdf 0x%x", bdf); + test_fails++; + } + + val_mmio_write(bar_base, bar_data); + +exception_return: + + if (IS_TEST_FAIL(val_get_status(pe_index))) { + val_print(AVS_PRINT_ERR, "\n Failed. Exception on Memory Access For Bdf 0x%x", bdf); + val_pcie_clear_urd(bdf); + test_fails++; + } + + /* Reset the loop variables */ + bar_data = 0; + } + + if (test_skip == 1) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + else if (test_fails) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, test_fails)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +p061_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/pcie/operating_system/test_p062.c b/test_pool/pcie/operating_system/test_p062.c new file mode 100644 index 00000000..645bf0c7 --- /dev/null +++ b/test_pool/pcie/operating_system/test_p062.c @@ -0,0 +1,102 @@ +/** @file + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 62) +#define TEST_DESC "Check EA Capability " +#define TEST_RULE "S_L4PCI_2" + +static +void +payload(void) +{ + + uint32_t bdf; + uint32_t pe_index; + uint32_t tbl_index; + uint32_t reg_value; + uint32_t enable_value; + uint32_t test_fails; + uint32_t test_skip = 1; + uint32_t cap_base; + uint32_t status; + pcie_device_bdf_table *bdf_tbl_ptr; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + + tbl_index = 0; + test_fails = 0; + + while (tbl_index < bdf_tbl_ptr->num_entries) + { + bdf = bdf_tbl_ptr->device[tbl_index++].bdf; + + /* If test runs for atleast an endpoint */ + test_skip = 0; + + /* Retrieve the addr of Enhanced Allocation capability (14h) and check if the + * capability structure is not supported. + */ + status = val_pcie_find_capability(bdf, PCIE_CAP, CID_EA, &cap_base); + if (status == PCIE_CAP_NOT_FOUND) + continue; + + /* Read Entry type register(08h) present in Enhanced Allocation capability struct(10h) */ + val_pcie_read_cfg(bdf, cap_base + EA_ENTRY_TYPE_OFFSET, ®_value); + + /* Extract enable value */ + enable_value = (reg_value >> EA_ENTRY_TYPE_ENABLE_SHIFT) & EA_ENTRY_TYPE_ENABLE_MASK; + if (enable_value) + { + val_print(AVS_PRINT_ERR, "\n Failed. BDF 0x%x Supports Enhanced Allocation", bdf); + test_fails++; + } + } + + if (test_skip == 1) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + else if (test_fails) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, test_fails)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +p062_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/pmu/operating_system/test_pmu001.c b/test_pool/pmu/operating_system/test_pmu001.c new file mode 100644 index 00000000..92d7500f --- /dev/null +++ b/test_pool/pmu/operating_system/test_pmu001.c @@ -0,0 +1,112 @@ +/** @file + * Copyright (c) 2016-2018, 2021-2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_pe.h" + + +#define TEST_NUM (AVS_PMU_TEST_NUM_BASE + 1) +#define TEST_RULE "PMU_PE_02" +#define TEST_DESC "Check PMU Overflow signal " + +static uint32_t int_id; + +void +set_pmu_overflow() +{ + uint64_t pmcr; + + //Initializing the state of overflow status and interrupt request registers + val_pe_reg_write(PMINTENCLR_EL1, 0xFFFFFFFF); + val_pe_reg_write(PMOVSCLR_EL0, 0xFFFFFFFF); + + //Sequence to generate PMUIRQ + pmcr = val_pe_reg_read(PMCR_EL0); + val_pe_reg_write(PMCR_EL0, pmcr|0x1); + + val_pe_reg_write(PMINTENSET_EL1, 0x1); + val_pe_reg_write(PMOVSSET_EL0, 0x1); + +} + + +static +void +isr() +{ + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + /* We received our interrupt, so disable PMUIRQ from generating further interrupts */ + val_pe_reg_write(PMOVSCLR_EL0, 0x1); + val_print(AVS_PRINT_INFO, "\n Received PMUIRQ ", 0); + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + val_gic_end_of_interrupt(int_id); + + return; +} + + +static +void +payload() +{ + uint32_t timeout = 0x100000; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + int_id = val_pe_get_pmu_gsiv(index); + + if (int_id != 23) { + timeout = 0; + val_print(AVS_PRINT_ERR, "\n Incorrect PPI value %d ", int_id); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } + + val_gic_install_isr(int_id, isr); + + set_pmu_overflow(); + + while ((--timeout > 0) && (IS_RESULT_PENDING(val_get_status(index)))) { + ; + } + + if (timeout == 0) + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); +} + +/** + @brief Install ISR and verify PMU Overflow Interrupt by programming System registers +**/ +uint32_t +pmu001_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + num_pe = 1; + + status = val_initialize_test(TEST_NUM, TEST_DESC, val_pe_get_num(), g_sbsa_level, TEST_RULE); + if (status != AVS_STATUS_SKIP) + /* execute payload on present PE and then execute on other PE */ + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} + diff --git a/test_pool/pmu/operating_system/test_pmu002.c b/test_pool/pmu/operating_system/test_pmu002.c new file mode 100644 index 00000000..5e79674d --- /dev/null +++ b/test_pool/pmu/operating_system/test_pmu002.c @@ -0,0 +1,63 @@ +/** @file + * Copyright (c) 2016-2018, 2021-2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_pe.h" + +#define TEST_NUM (AVS_PMU_TEST_NUM_BASE + 2) +#define TEST_RULE " PMU_PE_03" +#define TEST_DESC "Check number of PMU counters " + +static +void +payload() +{ + uint64_t data = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + data = val_pe_reg_read(PMCR_EL0); + + if (((data & 0x0F800) >> 11) > 5) //bits 15:11 for Number of counters. + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + + return; + +} + +uint32_t +pmu002_entry(uint32_t num_pe) +{ + + uint32_t status; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + + if (status != AVS_STATUS_SKIP) + /* execute payload on present PE and then execute on other PE */ + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} + + diff --git a/test_pool/pmu/operating_system/test_pmu003.c b/test_pool/pmu/operating_system/test_pmu003.c new file mode 100644 index 00000000..061b6956 --- /dev/null +++ b/test_pool/pmu/operating_system/test_pmu003.c @@ -0,0 +1,66 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_common.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_pmu.h" + + +#define TEST_NUM (AVS_PMU_TEST_NUM_BASE + 3) +#define TEST_RULE "PMU_EV_11" +#define TEST_DESC "Check for multi-threaded PMU ext " + +static void payload(void) +{ + uint64_t data = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 7) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + data = val_pe_reg_read(ID_AA64DFR0_EL1); + /* ID_AA64DFR0_EL1 bits 48 to 51 is MTPMU support. + * MTPMU = 0xF: Not implement any multithreaded PMU extension. + * MTPMU = 0x1: Implement the ARMv8.6-MTPMU extension. + */ + if ((VAL_EXTRACT_BITS(data, 48, 51) == 0xF) || (VAL_EXTRACT_BITS(data, 48, 51) == 0x1)) + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + + return; +} + +uint32_t pmu003_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, + TEST_RULE); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/pmu/operating_system/test_pmu004.c b/test_pool/pmu/operating_system/test_pmu004.c new file mode 100644 index 00000000..43d6e89b --- /dev/null +++ b/test_pool/pmu/operating_system/test_pmu004.c @@ -0,0 +1,228 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_common.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_pmu.h" +#include "val/include/sbsa_avs_memory.h" +#include "val/include/sbsa_avs_mpam.h" + + +#define TEST_NUM (AVS_PMU_TEST_NUM_BASE + 4) +#define TEST_RULE "PMU_BM_1, PMU_SYS_1, PMU_SYS_2" +#define TEST_DESC "Check memory bandwidth monitors " + +#define BUFFER_SIZE 4194304 /* 4 Megabytes*/ +#define NUM_PMU_MON 3 /* Minimum required monitors */ + +static PMU_EVENT_TYPE_e config_events[NUM_PMU_MON] = {PMU_EVENT_IB_TOTAL_BW, + PMU_EVENT_IB_READ_BW, + PMU_EVENT_IB_WRITE_BW}; + +/* Generates Inbound read/write traffic at memory interface */ +static uint32_t generate_inbound_traffic(uint32_t node_index, uint64_t base_addr, uint32_t size, + uint64_t *value) +{ + uint32_t i; + void *src_buf = 0; + void *dest_buf = 0; + /* Generate inbound traffic for given size*/ + + /* Allocate memory for 4 Megabytes */ + src_buf = (void *)val_mem_alloc_at_address(base_addr, BUFFER_SIZE); + dest_buf = (void *)val_mem_alloc_at_address(base_addr + BUFFER_SIZE, BUFFER_SIZE); + + if ((src_buf == NULL) || (dest_buf == NULL)) + return 1; + + /* Perform memory copy for given size */ + val_memcpy(src_buf, dest_buf, size); + + /* Read the configured monitors for bandwidth values */ + for (i = 0; i < NUM_PMU_MON ; i++) + value[i] = val_pmu_read_count(node_index, i); + + /*Free the buffers */ + val_mem_free_at_address((uint64_t)src_buf, BUFFER_SIZE); + val_mem_free_at_address((uint64_t)dest_buf, BUFFER_SIZE); + + return 0; +} + +static void payload(void) +{ + uint64_t data = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + uint32_t fail_cnt = 0, test_skip = 1; + uint32_t node_count; + uint32_t node_index; + uint64_t bandwidth1[NUM_PMU_MON]; + uint64_t bandwidth2[NUM_PMU_MON]; + uint32_t status; + uint64_t mem_range_index; + uint64_t num_mem_range; + uint64_t mc_prox_domain; + uint64_t prox_base_addr, addr_len; + uint32_t i; + + if (g_sbsa_level < 7) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + node_count = val_pmu_get_info(PMU_NODE_COUNT, 0); + val_print(AVS_PRINT_DEBUG, "\n PMU NODES = %d", node_count); + + if (node_count == 0) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + val_print(AVS_PRINT_ERR, "\n No PMU nodes found", 0); + return; + } + + /*Get number of memory ranges from SRAT table */ + num_mem_range = val_srat_get_info(SRAT_MEM_NUM_MEM_RANGE, 0); + if (num_mem_range == 0 || num_mem_range == SRAT_INVALID_INFO) { + val_print(AVS_PRINT_ERR, "\n No Proximity domains in the system", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } + + /* Loop through the memory ranges listed on SRAT table */ + for (mem_range_index = 0 ; mem_range_index < num_mem_range ; mem_range_index++) { + + /* Get proximity domain mapped to the memory range */ + mc_prox_domain = val_srat_get_prox_domain(mem_range_index); + if (mc_prox_domain == SRAT_INVALID_INFO) { + val_print(AVS_PRINT_ERR, "\n Proximity domain not found", 0); + fail_cnt++; + continue; + } + + /* Get PMU node index corresponding to the proximity domain */ + node_index = val_pmu_get_node_index(mc_prox_domain); + if (node_index == PMU_INVALID_INDEX) { + val_print(AVS_PRINT_ERR, + "\n Proximity domain %d has no PMU associated with it", mc_prox_domain); + fail_cnt++; + continue; + } + + /* Check if the PMU supports atleast 3 counters */ + data = val_pmu_get_monitor_count(node_index); + if (data < 3) { + val_print(AVS_PRINT_ERR, "\n PMU should support atleast 3 counter", 0); + fail_cnt++; + continue; + } + + /* Get base address of the proximity domain */ + prox_base_addr = val_srat_get_info(SRAT_MEM_BASE_ADDR, mc_prox_domain); + addr_len = val_srat_get_info(SRAT_MEM_ADDR_LEN, mc_prox_domain); + if ((prox_base_addr == SRAT_INVALID_INFO) || (addr_len == SRAT_INVALID_INFO) || + (addr_len <= 2 * BUFFER_SIZE)) { + val_print(AVS_PRINT_ERR, + "\n Invalid base address for proximity domain : 0x%lx", + mc_prox_domain); + fail_cnt++; + continue; + } + + /* Configure PMEVTYPER to monitor Bandwidth value */ + for (i = 0; i < NUM_PMU_MON; i++) { + status = val_pmu_configure_monitor(node_index, config_events[i], i); + if (status) { + val_print(AVS_PRINT_ERR, + "\n Required PMU Event 0x%x not supported", config_events[i]); + val_print(AVS_PRINT_ERR, " at node %d", node_index); + fail_cnt++; + break; + } + } + + if (status) + continue; + + /* Enable specific monitors */ + for (i = 0; i < NUM_PMU_MON ; i++) + val_pmu_enable_monitor(node_index, i); + + /* Generate first memory traffic for 2 MB */ + status = generate_inbound_traffic(node_index, prox_base_addr, BUFFER_SIZE / 2, bandwidth1); + + if (status) { + val_print(AVS_PRINT_ERR, "\n Memory allocation failed", node_index); + fail_cnt++; + continue; + } + + /* Reset the monitors */ + for (i = 0; i < NUM_PMU_MON ; i++) { + val_pmu_disable_monitor(node_index, i); + val_pmu_enable_monitor(node_index, i); + } + + /* Generate second memory traffic for 4 MB */ + status = generate_inbound_traffic(node_index, prox_base_addr, BUFFER_SIZE, bandwidth2); + + if (status) { + val_print(AVS_PRINT_ERR, "\n Memory allocation failed", node_index); + fail_cnt++; + continue; + } + + /* Consider delta to check if counter is moving in proportion */ + for (i = 0; i < NUM_PMU_MON ; i++) { + if (bandwidth1[i] > bandwidth2[i]) { + fail_cnt++; + break; + } + } + + /* Disable PMU monitors */ + val_pmu_disable_all_monitors(node_index); + } + + if (fail_cnt) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03)); + return; + } else if (test_skip) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); + return; + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t pmu004_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; /* This test is run on a single PE */ + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, + TEST_RULE); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/pmu/operating_system/test_pmu005.c b/test_pool/pmu/operating_system/test_pmu005.c new file mode 100644 index 00000000..674b0830 --- /dev/null +++ b/test_pool/pmu/operating_system/test_pmu005.c @@ -0,0 +1,186 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_common.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_pmu.h" +#include "val/include/sbsa_avs_memory.h" +#include "val/include/sbsa_avs_mpam.h" + + +#define TEST_NUM (AVS_PMU_TEST_NUM_BASE + 5) +#define TEST_RULE "PMU_MEM_1, PMU_SYS_1, PMU_SYS_2" +#define TEST_DESC "Check memory latency monitors " + +#define BUFFER_SIZE 4194304 /* 4 Megabytes*/ + +static void payload(void) +{ + uint64_t data = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + uint32_t fail_cnt = 0, test_skip = 1; + uint32_t node_count; + uint32_t node_index; + uint64_t num_open_txn; + uint64_t num_total_txn; + uint64_t mem_range_index; + uint64_t num_mem_range; + uint64_t mc_prox_domain; + uint64_t prox_base_addr, addr_len; + uint32_t status1, status2; + void *src_buf = 0; + void *dest_buf = 0; + + if (g_sbsa_level < 7) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + node_count = val_pmu_get_info(PMU_NODE_COUNT, 0); + val_print(AVS_PRINT_DEBUG, "\n PMU NODES = %d", node_count); + + if (node_count == 0) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + val_print(AVS_PRINT_ERR, "\n No PMU nodes found", 0); + return; + } + + /*Get number of memory ranges from SRAT table */ + num_mem_range = val_srat_get_info(SRAT_MEM_NUM_MEM_RANGE, 0); + if (num_mem_range == 0 || num_mem_range == SRAT_INVALID_INFO) { + val_print(AVS_PRINT_ERR, "\n No Proximity domains in the system", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } + + + /* Loop through the memory ranges listed on SRAT table */ + for (mem_range_index = 0 ; mem_range_index < num_mem_range ; mem_range_index++) { + + /* Get proximity domain mapped to the memory range */ + mc_prox_domain = val_srat_get_prox_domain(mem_range_index); + if (mc_prox_domain == SRAT_INVALID_INFO) { + val_print(AVS_PRINT_ERR, "\n Proximity domain not found", 0); + fail_cnt++; + continue; + } + + /* Get PMU node index corresponding to the proximity domain */ + node_index = val_pmu_get_node_index(mc_prox_domain); + if (node_index == PMU_INVALID_INDEX) { + val_print(AVS_PRINT_ERR, + "\n Proximity domain %d has no PMU associated with it", mc_prox_domain); + fail_cnt++; + continue; + } + + + /* Check if the PMU supports atleast 2 counters */ + data = val_pmu_get_monitor_count(node_index); + if (data < 2) { + val_print(AVS_PRINT_ERR, "\n Number of monitors supported = %d", data); + fail_cnt++; + continue; + } + + /* Configure PMEVTYPER to monitor memory latency */ + status1 = val_pmu_configure_monitor(node_index, PMU_EVENT_IB_OPEN_TXN, 0); + status2 = val_pmu_configure_monitor(node_index, PMU_EVENT_IB_TOTAL_TXN, 1); + if (status1 || status2) { + val_print(AVS_PRINT_ERR, + "\n Required events are not supported at node %d", node_index); + fail_cnt++; + continue; + } + + /* Get base address of the proximity domain */ + prox_base_addr = val_srat_get_info(SRAT_MEM_BASE_ADDR, mc_prox_domain); + addr_len = val_srat_get_info(SRAT_MEM_ADDR_LEN, mc_prox_domain); + if ((prox_base_addr == SRAT_INVALID_INFO) || (addr_len == SRAT_INVALID_INFO) || + (addr_len <= 2 * BUFFER_SIZE)) { + val_print(AVS_PRINT_ERR, + "\n Invalid base address for proximity domain : 0x%lx", + mc_prox_domain); + fail_cnt++; + continue; + } + + //* Allocate memory for 4 Megabytes */ + src_buf = (void *)val_mem_alloc_at_address(prox_base_addr, BUFFER_SIZE); + dest_buf = (void *)val_mem_alloc_at_address(prox_base_addr + BUFFER_SIZE, BUFFER_SIZE); + + if ((src_buf == NULL) || (dest_buf == NULL)) { + val_print(AVS_PRINT_ERR, "\n Memory allocation of buffers failed", 0); + fail_cnt++; + continue; + } + + + /* Enable the required counters to count programmed events */ + val_pmu_enable_monitor(node_index, 0); + val_pmu_enable_monitor(node_index, 1); + + /* Perform read/write and vary scale */ + val_memcpy(src_buf, dest_buf, BUFFER_SIZE); + + /* Read the monitors */ + num_open_txn = val_pmu_read_count(node_index, 0); + num_total_txn = val_pmu_read_count(node_index, 1); + + /*Free the buffers */ + val_mem_free_at_address((uint64_t)src_buf, BUFFER_SIZE); + val_mem_free_at_address((uint64_t)dest_buf, BUFFER_SIZE); + + /* Check if counters are moving */ + if (!num_open_txn || !num_total_txn) { + fail_cnt++; + } + + /* Disable PMU monitors */ + val_pmu_disable_all_monitors(node_index); + } + + if (fail_cnt) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03)); + return; + } else if (test_skip) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t pmu005_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; /* This test is run on a single PE */ + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, + TEST_RULE); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/pmu/operating_system/test_pmu006.c b/test_pool/pmu/operating_system/test_pmu006.c new file mode 100644 index 00000000..6fbe725a --- /dev/null +++ b/test_pool/pmu/operating_system/test_pmu006.c @@ -0,0 +1,78 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_common.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_pmu.h" + + +#define TEST_NUM (AVS_PMU_TEST_NUM_BASE + 6) +#define TEST_RULE "PMU_SPE" +#define TEST_DESC "Check for PMU SPE Requirements " + +static void payload(void) +{ + uint64_t data = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 7) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* ID_AA64DFR0_EL1.PMSVer bits 32 to 35 indicate the implementation of + Statistical Profiling extension */ + data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64DFR0_EL1), 32, 35); + + if (data > 0) { + /* PMBIDR_EL1.F bit 5 indicates if PE supports Hardware management of + the Access Flag and dirty state for accesses made by the SPE */ + data = VAL_EXTRACT_BITS(val_pe_reg_read(PMBIDR_EL1), 5, 5); + + if (data == 1) { + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + return; + } + else { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + } + /* Implementation of PMU_SPE is optional, skipping the test */ + else + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + + return; +} + +uint32_t pmu006_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, + TEST_RULE); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/pmu/operating_system/test_pmu007.c b/test_pool/pmu/operating_system/test_pmu007.c new file mode 100644 index 00000000..037a30ae --- /dev/null +++ b/test_pool/pmu/operating_system/test_pmu007.c @@ -0,0 +1,204 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_common.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_pmu.h" +#include "val/include/sbsa_avs_pcie.h" + + +#define TEST_NUM (AVS_PMU_TEST_NUM_BASE + 7) +#define TEST_RULE "PMU_BM_2, PMU_SYS_1, PMU_SYS_2" +#define TEST_DESC "Check PCIe bandwidth monitors " + +#define NUM_TOTAL_PMU_MON 6 /* Minimum required bandwidth monitors */ + +PMU_EVENT_TYPE_e bandwidth_events[NUM_TOTAL_PMU_MON] = {PMU_EVENT_IB_TOTAL_BW, + PMU_EVENT_IB_READ_BW, + PMU_EVENT_IB_WRITE_BW, + PMU_EVENT_OB_TOTAL_BW, + PMU_EVENT_OB_READ_BW, + PMU_EVENT_OB_WRITE_BW}; + +static void generate_inbound_traffic(uint32_t num_ecam, uint32_t size) +{ + uint32_t ecam_index; + uint32_t start_bus, seg_num; + uint32_t dev_index, func_index; + uint32_t bdf, reg_value; + + for (ecam_index = 0; ecam_index < num_ecam; ecam_index++) + { + /* Derive ecam specific information */ + seg_num = val_pcie_get_info(PCIE_INFO_SEGMENT, ecam_index); + start_bus = val_pcie_get_info(PCIE_INFO_START_BUS, ecam_index); + + /* Iterate over all buses, devices and functions in this ecam */ + for (dev_index = 0; dev_index < size; dev_index++) { + for (func_index = 0; func_index < PCIE_MAX_FUNC; func_index++) { + /* Form bdf using seg, bus, device, function numbers */ + bdf = PCIE_CREATE_BDF(seg_num, start_bus, dev_index, func_index); + val_pcie_read_cfg(bdf, TYPE01_VIDR, ®_value); + val_pcie_write_cfg(bdf, TYPE01_VIDR, 0xFFFFFFFF); + } + } + } +} + +static void generate_traffic(uint32_t node_index, uint32_t num_ecam, uint32_t size, uint64_t *value) +{ + uint32_t i; + + /* Generate inbound/outbound traffic for given size*/ + generate_inbound_traffic(num_ecam, size); + + /* Read the configured monitors for bandwidth values */ + for (i = 0; i < NUM_TOTAL_PMU_MON ; i++) + value[i] = val_pmu_read_count(node_index, i); +} + +static void payload(void) +{ + uint64_t data = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + uint32_t node_count; + uint32_t node_index; + uint64_t bandwidth1[NUM_TOTAL_PMU_MON], bandwidth2[NUM_TOTAL_PMU_MON]; + uint32_t fail_cnt = 0, test_skip = 0; + uint32_t run_flag = 0; + uint32_t status; + uint32_t num_ecam; + uint32_t i; + + if (g_sbsa_level < 7) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + num_ecam = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); + if (num_ecam == 0) + { + val_print(AVS_PRINT_ERR, "\n No ECAMs present ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + node_count = val_pmu_get_info(PMU_NODE_COUNT, 0); + val_print(AVS_PRINT_DEBUG, "\n PMU NODES = %d", node_count); + + if (node_count == 0) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03)); + val_print(AVS_PRINT_ERR, "\n No PMU nodes found", 0); + return; + } + + /* Loop through all the PMU nodes */ + for (node_index = 0; node_index < node_count; node_index++) { + + /* Check the PMU nodes which are associated with PCIe RC */ + if (val_pmu_get_info(PMU_NODE_TYPE, node_index) == PMU_NODE_PCIE_RC) { + run_flag = 1; + + /* Check if the PMU supports atleast 6 counter */ + data = val_pmu_get_monitor_count(node_index); + if (data < NUM_TOTAL_PMU_MON) { + val_print(AVS_PRINT_ERR, "\n PMU should support atleast 6 counters", 0); + fail_cnt++; + continue; + } + + /* Configure PMEVTYPER to monitor Bandwidth value */ + for (i = 0; i < NUM_TOTAL_PMU_MON; i++) { + status = val_pmu_configure_monitor(node_index, bandwidth_events[i], i); + if (status) { + val_print(AVS_PRINT_ERR, + "\n Required PMU Event 0x%x not supported", bandwidth_events[i]); + val_print(AVS_PRINT_ERR, " at node %d", node_index); + fail_cnt++; + break; + } + } + + if (status) + continue; + + /* Enable specific monitors */ + for (i = 0; i < NUM_TOTAL_PMU_MON ; i++) + val_pmu_enable_monitor(node_index, i); + + /* Generate first pcie traffic */ + generate_traffic(node_index, num_ecam, 10, bandwidth1); + + /* Reset the monitors */ + for (i = 0; i < NUM_TOTAL_PMU_MON ; i++) { + val_pmu_disable_monitor(node_index, i); + val_pmu_enable_monitor(node_index, i); + } + + /* Generate second pcie traffic */ + generate_traffic(node_index, num_ecam, 20, bandwidth2); + + /* Consider delta to check if counter is moving in proportion */ + for (i = 0; i < NUM_TOTAL_PMU_MON ; i++) { + if (bandwidth1[i] > bandwidth2[i]) { + fail_cnt++; + break; + } + } + + /* Disable PMU monitors */ + val_pmu_disable_all_monitors(node_index); + } + } + + if (!run_flag) { + val_print(AVS_PRINT_ERR, "\n No PMU associated with PCIe interface", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 04)); + return; + } + + if (fail_cnt) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 05)); + return; + } else if (test_skip) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 05)); + return; + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 06)); +} + +uint32_t +pmu007_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; /* This test is run on a single PE */ + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, + TEST_RULE); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/pmu/operating_system/test_pmu008.c b/test_pool/pmu/operating_system/test_pmu008.c new file mode 100644 index 00000000..f657a99b --- /dev/null +++ b/test_pool/pmu/operating_system/test_pmu008.c @@ -0,0 +1,253 @@ +/** @file + * Copyright (c) 2022-2023, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_common.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_pmu.h" +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_mpam.h" + + +#define TEST_NUM (AVS_PMU_TEST_NUM_BASE + 8) +#define TEST_RULE "PMU_SYS_5" +#define TEST_DESC "Check System PMU for NUMA systems " + +#define BUFFER_SIZE 4194304 /* 4 Megabytes*/ + +#define NUM_PMU_MON 3 /* Minimum required monitors */ + +static PMU_EVENT_TYPE_e config_events[NUM_PMU_MON] = {PMU_EVENT_LOCAL_BW, + PMU_EVENT_REMOTE_BW, + PMU_EVENT_ALL_BW}; + +static uint32_t remote_pe_index; +static void *src_buf; +static void *dest_buf; + +/* This payload generates remote PE traffic for 2 MB*/ +static void payload1(void) +{ + val_memcpy(src_buf, dest_buf, BUFFER_SIZE / 2); + + val_set_status(remote_pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +/* This payload generates remote PE traffic for 4 MB*/ +static void payload2(void) +{ + val_memcpy(src_buf, dest_buf, BUFFER_SIZE); + + val_set_status(remote_pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 02)); +} + +static uint32_t generate_traffic(uint64_t prox_domain, uint32_t size, void (*remote_traffic)(void)) +{ + uint64_t prox_base_addr, addr_len; + uint32_t timeout = TIMEOUT_LARGE; + + prox_base_addr = val_srat_get_info(SRAT_MEM_BASE_ADDR, prox_domain); + addr_len = val_srat_get_info(SRAT_MEM_ADDR_LEN, prox_domain); + if ((prox_base_addr == SRAT_INVALID_INFO) || (addr_len == SRAT_INVALID_INFO) || + (addr_len <= 2 * BUFFER_SIZE)) { + val_print(AVS_PRINT_ERR, + "\n Invalid base address for proximity domain : 0x%lx", + prox_domain); + return 1; + } + + /* Allocate memory for 4 Megabytes */ + src_buf = (void *)val_mem_alloc_at_address(prox_base_addr, BUFFER_SIZE); + dest_buf = (void *)val_mem_alloc_at_address(prox_base_addr + BUFFER_SIZE, BUFFER_SIZE); + + if ((src_buf == NULL) || (dest_buf == NULL)) + return 1; + + /* Perform memory copy for given size */ + val_memcpy(src_buf, dest_buf, size); + + /* Perform memory copy from remote PE*/ + val_execute_on_pe(remote_pe_index, remote_traffic, 0); + + /* Wait for execution to complete*/ + while (--timeout) + { + if (!(IS_RESULT_PENDING(val_get_status(remote_pe_index)))) { + break; + } + } + + /*Free the buffers */ + val_mem_free_at_address((uint64_t)src_buf, BUFFER_SIZE); + val_mem_free_at_address((uint64_t)dest_buf, BUFFER_SIZE); + + return 0; +} + +static void payload(void) +{ + uint64_t data = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + uint32_t node_count; + uint32_t mc_node_index; + uint32_t status; + uint32_t i; + uint64_t num_mem_range; + uint32_t pe_uid, pe_prox_domain; + uint32_t remote_pe_uid, remote_pe_prox_domain; + uint64_t value1[NUM_PMU_MON]; + uint64_t value2[NUM_PMU_MON]; + + if (g_sbsa_level < 7) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + node_count = val_pmu_get_info(PMU_NODE_COUNT, 0); + val_print(AVS_PRINT_DEBUG, "\n PMU NODES = %d", node_count); + + if (node_count == 0) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 1)); + val_print(AVS_PRINT_ERR, "\n No PMU nodes found", 0); + return; + } + + /*Get number of memory ranges from SRAT table */ + num_mem_range = val_srat_get_info(SRAT_MEM_NUM_MEM_RANGE, 0); + if (num_mem_range == 0 || num_mem_range == SRAT_INVALID_INFO) { + val_print(AVS_PRINT_ERR, "\n No Proximity domains in the system", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 2)); + return; + } + + /*Get local PE details */ + pe_uid = val_pe_get_uid(index); + pe_prox_domain = val_srat_get_info(SRAT_GICC_PROX_DOMAIN, pe_uid); + if (pe_prox_domain == SRAT_INVALID_INFO) { + val_print(AVS_PRINT_ERR, "\n Could not get proximity domain info for given PE", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 3)); + return; + } + /* Get memory controller local to the primary PE */ + mc_node_index = val_pmu_get_node_index(pe_prox_domain); + if (mc_node_index == PMU_INVALID_INDEX) { + val_print(AVS_PRINT_ERR, "\n PMU node not found", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 4)); + return; + } + + /* Check if the PMU supports atleast 3 counters */ + data = val_pmu_get_monitor_count(mc_node_index); + if (data < 3) { + val_print(AVS_PRINT_ERR, "\n PMU should support atleast 3 counter", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 5)); + return; + } + + /* Configure PMEVTYPER to monitor Bandwidth value */ + for (i = 0; i < NUM_PMU_MON; i++) { + status = val_pmu_configure_monitor(mc_node_index, config_events[i], i); + if (status) { + val_print(AVS_PRINT_ERR, + "\n Required PMU Event 0x%x not supported", config_events[i]); + val_print(AVS_PRINT_ERR, " at node %d", mc_node_index); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 6)); + return; + } + } + + /* Enable specific monitors */ + for (i = 0; i < NUM_PMU_MON ; i++) + val_pmu_enable_monitor(mc_node_index, i); + + /* Get remote PE details */ + remote_pe_prox_domain = val_srat_get_info(SRAT_GICC_REMOTE_PROX_DOMAIN, pe_prox_domain); + if (remote_pe_prox_domain == SRAT_INVALID_INFO) { + val_print(AVS_PRINT_ERR, "\n Could not get remote PE proximity domain", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 7)); + return; + } + remote_pe_uid = val_srat_get_info(SRAT_GICC_PROC_UID, remote_pe_prox_domain); + remote_pe_index = val_pe_get_index_uid(remote_pe_uid); + + /* Generate traffic to the memory controller with varied scale. First with + size 2 MB and second with 4 MB. Consider delta for results */ + + /* Generate remote and local traffic for 2 MB */ + status = generate_traffic(pe_prox_domain, BUFFER_SIZE / 2, payload1); + if (status) { + val_print(AVS_PRINT_ERR, "\n Memory allocation failed", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 8)); + return; + } + + /* Read the configured monitors for bandwidth values */ + for (i = 0; i < NUM_PMU_MON ; i++) + value1[i] = val_pmu_read_count(mc_node_index, i); + + /* Reset the monitors */ + for (i = 0; i < NUM_PMU_MON ; i++) { + val_pmu_disable_monitor(mc_node_index, i); + val_pmu_enable_monitor(mc_node_index, i); + } + + /* Generate remote and local traffic for 4 MB */ + status = generate_traffic(pe_prox_domain, BUFFER_SIZE, payload2); + + if (status) { + val_print(AVS_PRINT_ERR, "\n Memory allocation failed", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 9)); + return; + } + + /* Read the configured monitors for bandwidth values */ + for (i = 0; i < NUM_PMU_MON ; i++) + value2[i] = val_pmu_read_count(mc_node_index, i); + + /*Consider delta for results*/ + for (i = 0 ; i < NUM_PMU_MON ; i++) { + if (value2[i] <= value1[i]) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 10)); + return; + } + } + + /* Disable PMU monitors */ + val_pmu_disable_all_monitors(mc_node_index); + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 03)); +} + +uint32_t +pmu008_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; /* This test is run on a single PE */ + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, + TEST_RULE); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/pmu/operating_system/test_pmu009.c b/test_pool/pmu/operating_system/test_pmu009.c new file mode 100644 index 00000000..cc694684 --- /dev/null +++ b/test_pool/pmu/operating_system/test_pmu009.c @@ -0,0 +1,146 @@ +/** @file + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_common.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_pmu.h" +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_mpam.h" + + +#define TEST_NUM (AVS_PMU_TEST_NUM_BASE + 9) +#define TEST_RULE "PMU_SYS_6" +#define TEST_DESC "Check multiple types of traffic measurement" + +#define NUM_TRAFFIC_TYPE 2 /* To atleast check 2 different types of traffic */ + +static PMU_EVENT_TYPE_e config_events[NUM_TRAFFIC_TYPE] = {PMU_EVENT_TRAFFIC_1, + PMU_EVENT_TRAFFIC_2}; + +static void payload(void) +{ + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + uint32_t pmu_node_count, num_mon, i; + uint32_t mon_index, pmu_node_index; + uint32_t mon_count_value; + uint32_t ret_status, status; + uint64_t interface_acpiid; + uint32_t num_traffic_support; + + if (g_sbsa_level < 7) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 1)); + return; + } + + pmu_node_count = val_pmu_get_info(PMU_NODE_COUNT, 0); + val_print(AVS_PRINT_DEBUG, "\n PMU NODES = %d", pmu_node_count); + + if (pmu_node_count == 0) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 2)); + val_print(AVS_PRINT_ERR, "\n No PMU nodes found", 0); + return; + } + + /* PAL API to know the interface id which supports multiple types of traffic + and all the types of traffic supported */ + ret_status = val_pmu_get_multi_traffic_support_interface(&interface_acpiid, + &num_traffic_support); + if (ret_status == NOT_IMPLEMENTED) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 3)); + return; + } + + /* PMU info table index for the interface */ + pmu_node_index = val_pmu_get_index_acpiid(interface_acpiid); + if (pmu_node_index == PMU_INVALID_INDEX) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 4)); + return; + } + + /* Get number of monitor to the interface pmu node */ + num_mon = val_pmu_get_monitor_count(pmu_node_index); + if (num_mon == 0) { + val_print(AVS_PRINT_ERR, "\n PMU should support atleast 1 counter", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 5)); + return; + } + + /* Each monitor must be able to measure each supported traffic type */ + for (mon_index = 0; mon_index < num_mon; mon_index++) + { + /* Configure PMEVTYPER with required event type */ + for (i = 0; i < NUM_TRAFFIC_TYPE; i++) { + + status = val_pmu_configure_monitor(pmu_node_index, config_events[i], mon_index); + if (status) { + val_print(AVS_PRINT_ERR, + "\n Required PMU Event 0x%x not supported", config_events[i]); + val_print(AVS_PRINT_ERR, " at node %d", pmu_node_index); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 6)); + return; + } + val_pmu_enable_monitor(pmu_node_index, mon_index); + + /* generate workload */ + ret_status = val_generate_traffic(interface_acpiid, pmu_node_index, mon_index, + config_events[i]); + if (ret_status) { + val_print(AVS_PRINT_ERR, "\n workload generate function failed", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 7)); + return; + } + mon_count_value = val_pmu_read_count(pmu_node_index, mon_index); + + /* check if the monitor count value is as expected */ + ret_status = val_pmu_check_monitor_count_value(interface_acpiid, mon_count_value, + config_events[i]); + if (ret_status) { + val_print(AVS_PRINT_ERR, "\n count value not as expected", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 8)); + return; + } + + val_pmu_disable_monitor(pmu_node_index, mon_index); + } + } + + /* Disable PMU monitors */ + val_pmu_disable_all_monitors(pmu_node_index); + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 9)); +} + +uint32_t +pmu009_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; /* This test is run on a single PE */ + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, + TEST_RULE); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/ras/operating_system/test_ras001.c b/test_pool/ras/operating_system/test_ras001.c new file mode 100644 index 00000000..4a08197c --- /dev/null +++ b/test_pool/ras/operating_system/test_ras001.c @@ -0,0 +1,120 @@ +/** @file + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" +#include "val/include/sbsa_avs_memory.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_ras.h" + +#define TEST_NUM (AVS_RAS_TEST_NUM_BASE + 1) +#define TEST_RULE "RAS_01" +#define TEST_DESC "Check Error Counter " + +static +void +payload() +{ + + uint32_t status; + uint32_t fail_cnt = 0; + uint64_t num_node; + uint64_t value; + uint32_t node_index; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + /* Get Number of nodes with RAS Functionality */ + status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_node); + if (status || (num_node == 0)) { + val_print(AVS_PRINT_DEBUG, "\n RAS Nodes not found. Skipping...", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + for (node_index = 0; node_index < num_node; node_index++) { + + /* Get Current Node Type */ + status = val_ras_get_info(RAS_INFO_NODE_TYPE, node_index, &value); + if (status) { + val_print(AVS_PRINT_DEBUG, "\n Node Type not found index %d", node_index); + fail_cnt++; + break; + } + + /* Check if Node is Memory Controller/PE (Cache Resource) */ + if (!((value == NODE_TYPE_MC) || (value == NODE_TYPE_PE))) + continue; + + /* Check for Cache Resource Type in case of Processor Node */ + if (value == NODE_TYPE_PE) { + status = val_ras_get_info(RAS_INFO_PE_RES_TYPE, node_index, &value); + if (status) { + val_print(AVS_PRINT_DEBUG, "\n PE Resource type not found index %d", node_index); + fail_cnt++; + break; + } + + if (value != 0) + continue; + } + + /* Read FR register of the first error record */ + value = val_ras_reg_read(node_index, RAS_ERR_FR, 0); + if (value == INVALID_RAS_REG_VAL) { + val_print(AVS_PRINT_ERR, + "\n Couldn't read ERR<0>FR register for RAS node index: 0x%lx", + node_index); + fail_cnt++; + continue; + } + + /* Check ERR_FR.CEC[14:12] != 0 for CEC to be implemented */ + if (!(value & ERR_FR_CEC_MASK)) { + val_print(AVS_PRINT_ERR, "\n CEC not implemented for node_index %d", node_index); + fail_cnt++; + continue; + } + } + + if (fail_cnt) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +ras001_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/ras/operating_system/test_ras002.c b/test_pool/ras/operating_system/test_ras002.c new file mode 100644 index 00000000..2d4da0f9 --- /dev/null +++ b/test_pool/ras/operating_system/test_ras002.c @@ -0,0 +1,134 @@ +/** @file + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" +#include "val/include/sbsa_avs_memory.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_ras.h" + +#define TEST_NUM (AVS_RAS_TEST_NUM_BASE + 2) +#define TEST_RULE "RAS_02" +#define TEST_DESC "Check CFI, DUI, UI Controls " + +static +void +payload() +{ + + uint32_t status; + uint32_t fail_cnt = 0; + uint64_t num_node; + uint64_t value; + uint32_t node_index; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + /* Get Number of nodes with RAS Functionality */ + status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_node); + if (status || (num_node == 0)) { + val_print(AVS_PRINT_DEBUG, "\n RAS Nodes not found. Skipping...", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + for (node_index = 0; node_index < num_node; node_index++) { + + /* Get Current Node Type */ + status = val_ras_get_info(RAS_INFO_NODE_TYPE, node_index, &value); + if (status) { + val_print(AVS_PRINT_DEBUG, "\n Node Type not found index %d", node_index); + fail_cnt++; + break; + } + + /* Check if Node is Memory Controller/PE (Cache Resource) */ + if (!((value == NODE_TYPE_MC) || (value == NODE_TYPE_PE))) + continue; + + /* Check for Cache Resource Type in case of Processor Node */ + if (value == NODE_TYPE_PE) { + status = val_ras_get_info(RAS_INFO_PE_RES_TYPE, node_index, &value); + if (status) { + val_print(AVS_PRINT_DEBUG, "\n PE Resource type not found index %d", node_index); + fail_cnt++; + break; + } + + if (value != 0) + continue; + } + + /* Read FR register of the first error record */ + value = val_ras_reg_read(node_index, RAS_ERR_FR, 0); + if (value == INVALID_RAS_REG_VAL) { + val_print(AVS_PRINT_ERR, + "\n Couldn't read ERR<0>FR register for RAS node index: 0x%lx", + node_index); + fail_cnt++; + continue; + } + + /* Check DUI[17:16] != 0 of FR Register For DUI Control */ + if (!(value & ERR_FR_DUI_MASK)) { + val_print(AVS_PRINT_ERR, "\n DUI not implemented for node_index %d", node_index); + fail_cnt++; + continue; + } + + /* Check CFI[11:10] != 0 of FR Register For CFI Control */ + if (!(value & ERR_FR_CFI_MASK)) { + val_print(AVS_PRINT_ERR, "\n CFI not implemented for node_index %d", node_index); + fail_cnt++; + continue; + } + + /* Check UI[5:4] != 0 of FR Register For UI Control */ + if (!(value & ERR_FR_UI_MASK)) { + val_print(AVS_PRINT_ERR, "\n UI not implemented for node_index %d", node_index); + fail_cnt++; + continue; + } + } + + if (fail_cnt) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +ras002_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/ras/operating_system/test_ras003.c b/test_pool/ras/operating_system/test_ras003.c new file mode 100644 index 00000000..1b3350f1 --- /dev/null +++ b/test_pool/ras/operating_system/test_ras003.c @@ -0,0 +1,130 @@ +/** @file + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" +#include "val/include/sbsa_avs_memory.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_ras.h" + +#define TEST_NUM (AVS_RAS_TEST_NUM_BASE + 3) +#define TEST_RULE "RAS_03" +#define TEST_DESC "Check FHI in Error Record Group " + +static +void +payload() +{ + + uint32_t status; + uint32_t fail_cnt = 0, test_skip = 1; + uint64_t num_node; + uint32_t node_index, sec_node; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + uint64_t base_addr, base_addr_sec; + uint64_t fhi_id, fhi_id_sec; + + /* Get Number of nodes with RAS Functionality */ + status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_node); + if (status || (num_node < 2)) { + val_print(AVS_PRINT_DEBUG, "\n RAS Nodes should be more than 1. Skipping...", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + for (node_index = 0; node_index < (num_node - 1); node_index++) { + + /* Get Current Node Base Address */ + status = val_ras_get_info(RAS_INFO_BASE_ADDR, node_index, &base_addr); + if (status) { + /* Interface is System Register based, Skipping this node */ + val_print(AVS_PRINT_DEBUG, "\n Interface is SR, Skipping node %d", node_index); + continue; + } + + /* Get FHI number for this Node, If Not Skip the Node */ + status = val_ras_get_info(RAS_INFO_FHI_ID, node_index, &fhi_id); + if (status) { + val_print(AVS_PRINT_DEBUG, "\n FHI not supported for index %d", node_index); + continue; + } + + test_skip = 0; + + /* Compare with Rest of the node having same Base Address */ + for (sec_node = node_index + 1; sec_node < num_node; sec_node++) { + + /* Get Second Node Base Address */ + status = val_ras_get_info(RAS_INFO_BASE_ADDR, sec_node, &base_addr_sec); + if (status) { + /* Interface is System Register based, Skipping this node */ + val_print(AVS_PRINT_DEBUG, "\n Interface is SR, Skipping sec_node %d", node_index); + continue; + } + + /* If not same base address then skip this node */ + if (base_addr != base_addr_sec) + continue; + + /* Get FHI number for this Node */ + status = val_ras_get_info(RAS_INFO_FHI_ID, sec_node, &fhi_id_sec); + if (status) { + val_print(AVS_PRINT_DEBUG, "\n FHI not supported for index %d", sec_node); + continue; + } + + /* Check if FHI is same otherwise fail the test */ + if (fhi_id != fhi_id_sec) { + val_print(AVS_PRINT_ERR, "\n FHI different for Same Group index %d", node_index); + val_print(AVS_PRINT_ERR, " : %d", sec_node); + fail_cnt++; + continue; + } + } + } + + if (fail_cnt) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } else if (test_skip) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +ras003_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/ras/operating_system/test_ras004.c b/test_pool/ras/operating_system/test_ras004.c new file mode 100644 index 00000000..60e54047 --- /dev/null +++ b/test_pool/ras/operating_system/test_ras004.c @@ -0,0 +1,130 @@ +/** @file + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" +#include "val/include/sbsa_avs_memory.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_ras.h" + +#define TEST_NUM (AVS_RAS_TEST_NUM_BASE + 4) +#define TEST_RULE "RAS_04" +#define TEST_DESC "Check ERI in Error Record Group " + +static +void +payload() +{ + + uint32_t status; + uint32_t fail_cnt = 0, test_skip = 1; + uint64_t num_node; + uint32_t node_index, sec_node; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + uint64_t base_addr, base_addr_sec; + uint64_t eri_id, eri_id_sec; + + /* Get Number of nodes with RAS Functionality */ + status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_node); + if (status || (num_node < 2)) { + val_print(AVS_PRINT_DEBUG, "\n RAS Nodes should be more than 1. Skipping...", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + for (node_index = 0; node_index < (num_node - 1); node_index++) { + + /* Get Current Node Base Address */ + status = val_ras_get_info(RAS_INFO_BASE_ADDR, node_index, &base_addr); + if (status) { + /* Interface is System Register based, Skipping this node */ + val_print(AVS_PRINT_DEBUG, "\n Interface is SR, Skipping node %d", node_index); + continue; + } + + /* Get ERI number for Node, If Not Skip the Node */ + status = val_ras_get_info(RAS_INFO_ERI_ID, node_index, &eri_id); + if (status) { + val_print(AVS_PRINT_DEBUG, "\n ERI Not supported for index %d", node_index); + continue; + } + + test_skip = 0; + + /* Compare with Rest of the node having same Base Address */ + for (sec_node = node_index + 1; sec_node < num_node; sec_node++) { + + /* Get Second Node Base Address */ + status = val_ras_get_info(RAS_INFO_BASE_ADDR, sec_node, &base_addr_sec); + if (status) { + /* Interface is System Register based, Skipping this node */ + val_print(AVS_PRINT_DEBUG, "\n Interface is SR, Skipping sec_node %d", node_index); + continue; + } + + /* If not same base address then skip this node */ + if (base_addr != base_addr_sec) + continue; + + /* Get ERI number for this Node */ + status = val_ras_get_info(RAS_INFO_ERI_ID, sec_node, &eri_id_sec); + if (status) { + val_print(AVS_PRINT_DEBUG, "\n ERI Not supported for index %d", sec_node); + continue; + } + + /* Check if ERI is same otherwise fail the test */ + if (eri_id != eri_id_sec) { + val_print(AVS_PRINT_ERR, "\n ERI Diff for Same Group Nodes. Index %d", node_index); + val_print(AVS_PRINT_ERR, " : %d", sec_node); + fail_cnt++; + continue; + } + } + } + + if (fail_cnt) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } else if (test_skip) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +ras004_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/ras/operating_system/test_ras005.c b/test_pool/ras/operating_system/test_ras005.c new file mode 100644 index 00000000..7eac4508 --- /dev/null +++ b/test_pool/ras/operating_system/test_ras005.c @@ -0,0 +1,185 @@ +/** @file + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" +#include "val/include/sbsa_avs_memory.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_ras.h" + +#define TEST_NUM (AVS_RAS_TEST_NUM_BASE + 5) +#define TEST_RULE "RAS_06" +#define TEST_DESC "Check ERI/FHI Connected to GIC " + +#define IS_NOT_SPI_PPI(int_id) ((int_id < 16) || (int_id > 1019)) + +static uint64_t int_id; +static uint32_t intr_pending = 1; + +static +void +intr_handler(void) +{ + intr_pending = 0; + + /* Clear the interrupt pending state */ + + val_print(AVS_PRINT_INFO, "\n Received interrupt %x ", 0); + val_gic_end_of_interrupt(int_id); + return; +} + +static +void +payload() +{ + + uint32_t status; + uint32_t fail_cnt = 0, test_skip = 1; + uint64_t num_node; + uint32_t node_index; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + uint64_t eri_id = 0, fhi_id = 0; + uint64_t rec_index; + RAS_ERR_IN_t err_in_params; + RAS_ERR_OUT_t err_out_params; + + /* Get Number of nodes with RAS Functionality */ + status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_node); + if (status) { + val_print(AVS_PRINT_ERR, "\n RAS Nodes not present", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + + for (node_index = 0; node_index < num_node; node_index++) { + + /* Get ERI number for Node, If Not Skip the Node */ + status = val_ras_get_info(RAS_INFO_ERI_ID, node_index, &eri_id); + if (status) { + /* No ERI Support for this node */ + val_print(AVS_PRINT_DEBUG, "\n ERI Not supported for node %d", node_index); + } else { + test_skip = 0; + /* ERI Support, Check for SPI/PPI */ + if (IS_NOT_SPI_PPI(eri_id)) { + val_print(AVS_PRINT_ERR, "\n ERI Not SPI/PPI for node %d", node_index); + fail_cnt++; + continue; + } + } + + /* Get FHI number for Node, If Not Skip the Node */ + status = val_ras_get_info(RAS_INFO_FHI_ID, node_index, &fhi_id); + if (status) { + /* No FHI Support for this node */ + val_print(AVS_PRINT_DEBUG, "\n FHI Not supported for node %d", node_index); + } else { + test_skip = 0; + /* FHI Support, Check for SPI/PPI */ + if (IS_NOT_SPI_PPI(fhi_id)) { + val_print(AVS_PRINT_ERR, "\n FHI Not SPI/PPI for node %d", node_index); + fail_cnt++; + continue; + } + } + + /* Check with Interrupt Generation if platform supports */ + if (test_skip == 0) { + + int_id = (fhi_id) ? fhi_id : eri_id; + + /* Get Error Record number for this Node */ + status = val_ras_get_info(RAS_INFO_START_INDEX, node_index, &rec_index); + if (status) { + val_print(AVS_PRINT_DEBUG, "\n Could not get Start Index for index %d", node_index); + fail_cnt++; + continue; + } + + err_in_params.rec_index = rec_index; + err_in_params.node_index = node_index; + err_in_params.ras_error_type = ERR_CE; + err_in_params.is_pfg_check = 0; + + /* Install handler for interrupt */ + val_gic_install_isr(int_id, intr_handler); + + /* Setup an error in an implementation defined way */ + status = val_ras_setup_error(err_in_params, &err_out_params); + if (status == NOT_IMPLEMENTED) { + val_print(AVS_PRINT_DEBUG, "\n Skipping Functional Check, node %d", node_index); + continue; + } else if (status) { + val_print(AVS_PRINT_ERR, "\n val_ras_setup_error failed, node %d", node_index); + fail_cnt++; + break; + } + + /* Inject error in an implementation defined way */ + status = val_ras_inject_error(err_in_params, &err_out_params); + if (status == NOT_IMPLEMENTED) { + val_print(AVS_PRINT_DEBUG, "\n Skipping Functional Check, node %d", node_index); + continue; + } else if (status) { + val_print(AVS_PRINT_ERR, "\n val_ras_inject_error failed, node %d", node_index); + fail_cnt++; + break; + } + + /* Wait loop */ + val_ras_wait_timeout(1); + + if (intr_pending) { + val_print(AVS_PRINT_ERR, "\n Not Connected to GIC for node %d", node_index); + fail_cnt++; + continue; + } + } + } + + if (fail_cnt) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } else if (test_skip) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +ras005_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/ras/operating_system/test_ras006.c b/test_pool/ras/operating_system/test_ras006.c new file mode 100644 index 00000000..6d368814 --- /dev/null +++ b/test_pool/ras/operating_system/test_ras006.c @@ -0,0 +1,310 @@ +/** @file + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" +#include "val/include/sbsa_avs_memory.h" +#include "val/include/sbsa_avs_mpam.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_ras.h" + +#define TEST_NUM (AVS_RAS_TEST_NUM_BASE + 6) +#define TEST_RULE "RAS_07" +#define TEST_DESC "RAS ERRADDR.AI bit status check" + +#define ONE_BYTE_BUFFER 0x1 + +static +void +payload() +{ + uint64_t num_node; + uint64_t num_mc_node; + uint64_t node_type; + uint64_t err_inj_addr; + uint64_t prox_base_addr; + uint64_t num_err_recs; + uint64_t err_rec_impl_bitmap; + uint64_t err_rec_addrmode_bitmap; + uint64_t data; + + uint32_t status; + uint32_t fail_cnt = 0, test_skip = 0; + uint32_t node_index; + uint64_t mc_prox_domain; + uint32_t err_rec_addrmode; + uint32_t err_rec_addr_ai; + uint32_t err_rec_index; + uint32_t err_inj_addr_data; + uint32_t err_recorded = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + RAS_ERR_IN_t err_in_params; + RAS_ERR_OUT_t err_out_params; + +/* get number of nodes with RAS functionality */ + status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_node); + if (status || (num_node == 0)) { + val_print(AVS_PRINT_ERR, "\n RAS nodes not found. Skipping...", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* get number of MC nodes with RAS functionality */ + status = val_ras_get_info(RAS_INFO_NUM_MC, 0, &num_mc_node); + if (status || (num_mc_node == 0)) { + val_print(AVS_PRINT_ERR, "\n RAS MC nodes not found. Skipping...", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + for (node_index = 0; node_index < num_node; node_index++) { + /* check whether current node is memory controller node */ + status = val_ras_get_info(RAS_INFO_NODE_TYPE, node_index, &node_type); + if (status) { + val_print(AVS_PRINT_ERR, + "\n Couldn't get node type for RAS node index: 0x%lx", + node_index); + fail_cnt++; + continue; + } + + if (node_type == NODE_TYPE_MC) { + /* get number of error records for the current RAS node + (both implemented and unimplemented) */ + status = val_ras_get_info(RAS_INFO_NUM_ERR_REC, node_index, &num_err_recs); + if (status) { + val_print(AVS_PRINT_ERR, + "\n Couldn't get number of error records for RAS node index: 0x%lx", + node_index); + fail_cnt++; + continue; + } + /* skip if num of error records in zero */ + if (num_err_recs == 0) { + val_print(AVS_PRINT_DEBUG, + "\n Number of error records for RAS node index: 0x%lx is zero", + node_index); + test_skip++; + continue; + } + + /* get proximity domain of RAS memory controller node */ + status = val_ras_get_info(RAS_INFO_MC_RES_PROX_DOMAIN, node_index, &mc_prox_domain); + if (status) { + val_print(AVS_PRINT_ERR, + "\n Couldn't get MC proximity domain for RAS node index: 0x%lx", + node_index); + fail_cnt++; + continue; + } + + /* fetch base addr of the proximity domain to inject an error in platform + defined method */ + prox_base_addr = val_srat_get_info(SRAT_MEM_BASE_ADDR, mc_prox_domain); + if (prox_base_addr == SRAT_INVALID_INFO) { + val_print(AVS_PRINT_ERR, + "\n Invalid base address for proximity domain : 0x%lx", + mc_prox_domain); + fail_cnt++; + continue; + } + + /* check if the address accessible to PE by trying to allocate the address */ + err_inj_addr = (uint64_t)val_mem_alloc_at_address(prox_base_addr, ONE_BYTE_BUFFER); + + if (err_inj_addr == 0) { + val_print(AVS_PRINT_ERR, + "\n Unable to allocate address in proximity domain : 0x%lx failed.", + mc_prox_domain); + /* test not applicable if memory isn't accessible by PE */ + test_skip++; + continue; + } + + /* inject error with following parameters */ + err_in_params.rec_index = 0; /* not applicable for scenario*/ + err_in_params.node_index = node_index; + err_in_params.ras_error_type = ERR_CE; /* correctable error */ + err_in_params.error_pa = err_inj_addr; /* address of the location where error + needs to be injected */ + err_in_params.is_pfg_check = 0; /* not a pseudo fault check */ + + /* Setup error in an implementation defined way */ + status = val_ras_setup_error(err_in_params, &err_out_params); + if (status) { + val_print(AVS_PRINT_ERR, "\n val_ras_setup_error failed, node %d", node_index); + fail_cnt++; + break; + } + + /* Inject error in an implementation defined way */ + status = val_ras_inject_error(err_in_params, &err_out_params); + if (status) { + val_print(AVS_PRINT_ERR, "\n val_ras_inject_error failed, node %d", node_index); + fail_cnt++; + break; + } + + /* wait loop to allow system to inject the error */ + val_ras_wait_timeout(1); + + if (status) { + val_print(AVS_PRINT_ERR, + "\n Memory error injection for RAS node index: 0x%lx failed.", + node_index); + fail_cnt++; + continue; + } + + /* perform a read to error-injected address, which will cause system to record the error + with address syndrome in one of the error records present for the current RAS node */ + err_inj_addr_data = val_mmio_read(err_inj_addr); + val_print(AVS_PRINT_DEBUG, "\n Error injected address: 0x%llx", err_inj_addr); + val_print(AVS_PRINT_DEBUG, " Data read: 0x%lx", err_inj_addr_data); + + /* wait loop to allow system to update RAS error records */ + val_ras_wait_timeout(1); + + /* get error record implemented bitmap from RAS info table */ + status = val_ras_get_info(RAS_INFO_ERR_REC_IMP, node_index, &err_rec_impl_bitmap); + if (status) { + val_print(AVS_PRINT_ERR, + "\n Couldn't get implemented rec bitmap for RAS node index: 0x%lx", + node_index); + fail_cnt++; + continue; + } + + /* get addressing mode bitmap by which current RAS node populates + ERRADDR field of error records */ + status = val_ras_get_info(RAS_INFO_ADDR_MODE, node_index, &err_rec_addrmode_bitmap); + if (status) { + val_print(AVS_PRINT_ERR, + "\n Couldn't get implemented addr mode bitmap for RAS node index: 0x%lx", + node_index); + fail_cnt++; + continue; + } + + /* Iterate through each error record implemented and check if ERRADDR.AI bit is 0b0 + if the address is the same as System Physical Address for the location, + and 0b1 otherwise.*/ + for (err_rec_index = 0; err_rec_index < num_err_recs; err_rec_index++) { + /* check if error record is implemented for current node + Bit[n] = 0b: Error record at index n is implemented. + Bit[n] = 1b: Error record at index n is not implemented. + If not implemented skip the error record */ + if ((err_rec_impl_bitmap >> err_rec_index) & 0x1) + continue; + /* since we have injected error in a memory location in current MC proximity domain + space, one of the error record should have recorded address syndrome and + ERRSTATUS AV, bit [31] & V, bit [30] should be valid for that error record */ + + /* if ERRSTATUS AV, bit [31] & V, bit [30] is invalid, continue with next + error record */ + data = val_ras_reg_read(node_index, RAS_ERR_STATUS, err_rec_index); + if (data == INVALID_RAS_REG_VAL) { + val_print(AVS_PRINT_ERR, + "\n Couldn't read ERR<%d>STATUS register for ", + err_rec_index); + val_print(AVS_PRINT_ERR, + "RAS node index: 0x%lx", + node_index); + fail_cnt++; + continue; + } + if (!((data & ERR_STATUS_V_MASK) && (data & ERR_STATUS_AV_MASK))) + continue; + + /* valid error record with address syndrome found */ + err_recorded = 1; + + /* get addressing mode for ERRADDR field in current error record + Bit[n] = 0b: Error record at index n reports System Physical + Addresses (SPA) in the ERR_ADDR register. + Bit[n] = 1b: otherwise */ + err_rec_addrmode = (err_rec_addrmode_bitmap >> err_rec_index) & 0x1; + + /* read ERRADDR.AI bit */ + data = val_ras_reg_read(node_index, RAS_ERR_ADDR, err_rec_index); + if (data == INVALID_RAS_REG_VAL) { + val_print(AVS_PRINT_ERR, + "\n Couldn't read ERR<%d>STATUS register for ", + err_rec_index); + val_print(AVS_PRINT_ERR, + "RAS node index: 0x%lx", + node_index); + fail_cnt++; + continue; + } + err_rec_addr_ai = (data >> ERR_ADDR_AI_SHIFT) & 0x1; + + if (err_rec_addrmode == 0 && err_rec_addr_ai == 0) { + val_print(AVS_PRINT_DEBUG, + "\n RAS node index: 0x%lx PASSED", + node_index); + /* error record comply with RAS_07 requirements */ + break; + } else { + fail_cnt++; + break; + } + } + + /* check if system RAS recorded the error in memory with address syndrome + if no, rule is not applicable for the node */ + if (!err_recorded) { + val_print(AVS_PRINT_ERR, + "\n Memory error not recorded for RAS node index: 0x%lx", + node_index); + test_skip++; + } + } + } + + if (fail_cnt) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } else if (test_skip) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); + return; + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +ras006_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; /* This test is run on single processor */ + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/ras/operating_system/test_ras007.c b/test_pool/ras/operating_system/test_ras007.c new file mode 100644 index 00000000..bf635a17 --- /dev/null +++ b/test_pool/ras/operating_system/test_ras007.c @@ -0,0 +1,128 @@ +/** @file + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" +#include "val/include/sbsa_avs_memory.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_ras.h" + +#define TEST_NUM (AVS_RAS_TEST_NUM_BASE + 7) +#define TEST_RULE "RAS_08" +#define TEST_DESC "Check Error Group Status " + +static +void +payload() +{ + + uint32_t status; + uint32_t fail_cnt = 0, test_skip = 1; + uint64_t num_node; + uint64_t value; + uint32_t node_index; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + uint64_t start_index; + uint64_t err_rec_implement, err_status, record_imp_bits; + + /* Get Number of nodes with RAS Functionality */ + status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_node); + if (status || (num_node == 0)) { + val_print(AVS_PRINT_DEBUG, "\n RAS Nodes not found. Skipping...", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + for (node_index = 0; node_index < num_node; node_index++) { + + /* Get Current Node Interface Type */ + status = val_ras_get_info(RAS_INFO_BASE_ADDR, node_index, &value); + if (status) { + /* Interface is System Register based, Skipping this node */ + val_print(AVS_PRINT_DEBUG, "\n Interface is SR, Skipping node %d", node_index); + continue; + } + + test_skip = 0; + + /* Get Start error index number for this Node */ + status = val_ras_get_info(RAS_INFO_START_INDEX, node_index, &start_index); + if (status) { + val_print(AVS_PRINT_DEBUG, "\n Could not get Start Index for index %d", node_index); + fail_cnt++; + continue; + } + + /* Check which error records are implemented in this node */ + status = val_ras_get_info(RAS_INFO_ERR_REC_IMP, node_index, &err_rec_implement); + if (status) { + val_print(AVS_PRINT_DEBUG, "\n Could not get err rec info for index %d", node_index); + fail_cnt++; + continue; + } + + /* Get error status reporting value for this node */ + status = val_ras_get_info(RAS_INFO_STATUS_REPORT, node_index, &err_status); + if (status) { + val_print(AVS_PRINT_DEBUG, "\n Could not get status for index %d", node_index); + fail_cnt++; + continue; + } + + /* This will have bit value 1 for all the implemented error records */ + record_imp_bits = (err_rec_implement ^ AVS_ALL_1_64BIT); + + if (err_status & record_imp_bits) { + /* Fail the test as one of the implemented ER has error reporting not supported */ + val_print(AVS_PRINT_ERR, "\n ERRGSR not supported for index %d", node_index); + fail_cnt++; + continue; + } + + } + + if (fail_cnt) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } else if (test_skip) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +ras007_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/ras/operating_system/test_ras008.c b/test_pool/ras/operating_system/test_ras008.c new file mode 100644 index 00000000..8e388f3b --- /dev/null +++ b/test_pool/ras/operating_system/test_ras008.c @@ -0,0 +1,116 @@ +/** @file + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" +#include "val/include/sbsa_avs_memory.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_ras.h" +#include "val/include/sbsa_avs_peripherals.h" + +#define TEST_NUM (AVS_RAS_TEST_NUM_BASE + 8) +#define TEST_RULE "RAS_11, RAS_12" +#define TEST_DESC "Software Fault Error Check " + +/* The generic peripherals which ACS can rely on like PCIe spec it ruled out as the + rule mentions to follow PCIe specification mentioned behaviour for handling those + errors. + The most generic address access which can be used will be UART space, In the PL011 + there are some unused address space and the UART specification is mandating the + response for access to those space. + + As part of this rule we can make sure data abort if not generated as part of access + to the unused address space. +*/ + +static uint64_t branch_to_test; +static uint64_t l_uart_base; + +static +void +esr(uint64_t interrupt_type, void *context) +{ + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + /* Update the ELR to point to next instrcution */ + val_pe_update_elr(context, branch_to_test); + + val_print(AVS_PRINT_ERR, "\n Error : Received Sync Exception type %d", interrupt_type); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); +} + +static +void +payload(void) +{ + + uint32_t count = val_peripheral_get_info(NUM_UART, 0); + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + uint64_t value; + + val_pe_install_esr(EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, esr); + val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); + + branch_to_test = (uint64_t)&&exception_taken; + + if (count == 0) { + val_print(AVS_PRINT_WARN, "\n No UART defined by Platform ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + while (count != 0) { + l_uart_base = val_peripheral_get_info(UART_BASE0, count - 1); + if (l_uart_base == 0) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + /*Make sure access to Reserved doesn't cause any exceptions*/ + value = *((volatile uint32_t *)(l_uart_base + SBSA_UART_RES)); + val_print(AVS_PRINT_DEBUG, "\n Value from UART Reserved Space 0x%llx", value); + + *((volatile uint32_t *)(l_uart_base + SBSA_UART_RES)) = (uint32_t)(0xDEAD); + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + + count--; + } +exception_taken: + return; +} + +uint32_t +ras008_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/ras/operating_system/test_ras009.c b/test_pool/ras/operating_system/test_ras009.c new file mode 100644 index 00000000..6ef435fd --- /dev/null +++ b/test_pool/ras/operating_system/test_ras009.c @@ -0,0 +1,208 @@ +/** @file + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" +#include "val/include/sbsa_avs_memory.h" +#include "val/include/sbsa_avs_mpam.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_ras.h" + +#define TEST_NUM (AVS_RAS_TEST_NUM_BASE + 9) +#define TEST_RULE "S_L7RAS_1" +#define TEST_DESC "Data abort on Containable err " + +#define ONE_BYTE_BUFFER 0x1 + +static uint32_t esr_pending = 1; +static void *branch_to_test; + +static +void +esr(uint64_t interrupt_type, void *context) +{ + esr_pending = 0; + + /* Update the ELR to return to test specified address */ + val_pe_update_elr(context, (uint64_t)branch_to_test); + + val_print(AVS_PRINT_ERR, "\n Received exception of type: %d", interrupt_type); +} + +static +void +payload() +{ + uint64_t num_node; + uint64_t num_mc_node; + uint64_t node_type; + uint64_t err_inj_addr; + uint64_t prox_base_addr; + + uint32_t status; + uint32_t fail_cnt = 0, test_skip = 0; + uint32_t node_index; + uint64_t mc_prox_domain; + uint32_t err_inj_addr_data; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + RAS_ERR_IN_t err_in_params; + RAS_ERR_OUT_t err_out_params; + + /* get number of nodes with RAS functionality */ + status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_node); + if (status || (num_node == 0)) { + val_print(AVS_PRINT_ERR, "\n RAS nodes not found. Skipping...", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* get number of MC nodes with RAS functionality */ + status = val_ras_get_info(RAS_INFO_NUM_MC, 0, &num_mc_node); + if (status || (num_mc_node == 0)) { + val_print(AVS_PRINT_ERR, "\n RAS MC nodes not found. Skipping...", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + for (node_index = 0; node_index < num_node; node_index++) { + + /* check whether current node is memory controller node */ + status = val_ras_get_info(RAS_INFO_NODE_TYPE, node_index, &node_type); + if (status) { + val_print(AVS_PRINT_ERR, "\n Couldn't get node type for node : 0x%lx", node_index); + fail_cnt++; + continue; + } + + if (node_type != NODE_TYPE_MC) + continue; + + /* Get proximity domain of RAS memory controller node */ + status = val_ras_get_info(RAS_INFO_MC_RES_PROX_DOMAIN, node_index, &mc_prox_domain); + if (status) { + val_print(AVS_PRINT_ERR, "\n Couldn't get MC prox domain for node : 0x%lx", node_index); + fail_cnt++; + continue; + } + + /* Get base addr for proximity domain to inject error in platform defined method */ + prox_base_addr = val_srat_get_info(SRAT_MEM_BASE_ADDR, mc_prox_domain); + if (prox_base_addr == SRAT_INVALID_INFO) { + val_print(AVS_PRINT_ERR, "\n Invalid base for prox domain : 0x%lx", mc_prox_domain); + fail_cnt++; + continue; + } + + /* check if the address accessible to PE by trying to allocate the address */ + err_inj_addr = (uint64_t)val_mem_alloc_at_address(prox_base_addr, ONE_BYTE_BUFFER); + + if (err_inj_addr == 0) { + val_print(AVS_PRINT_ERR, "\n Unable to allocate address in prox domain : 0x%lx", + mc_prox_domain); + /* test not applicable if memory isn't accessible by PE */ + test_skip++; + continue; + } + + /* Install sync and async handlers to handle exceptions.*/ + status = val_pe_install_esr(EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, esr); + status |= val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); + if (status) + { + val_print(AVS_PRINT_ERR, "\n Failed in installing the exception handler", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03)); + return; + } + branch_to_test = &&exception_return; + + /* Inject error with following parameters */ + err_in_params.rec_index = 0; /* not applicable for scenario*/ + err_in_params.node_index = node_index; + err_in_params.ras_error_type = ERR_CONTAINABLE; /* containable error */ + err_in_params.error_pa = err_inj_addr; /* address of the location where error + needs to be injected */ + err_in_params.is_pfg_check = 0; /* not a pseudo fault check */ + + /* Setup error in an implementation defined way */ + status = val_ras_setup_error(err_in_params, &err_out_params); + if (status) { + val_print(AVS_PRINT_ERR, "\n val_ras_setup_error failed, node %d", node_index); + fail_cnt++; + break; + } + + /* Inject error in an implementation defined way */ + status = val_ras_inject_error(err_in_params, &err_out_params); + if (status) { + val_print(AVS_PRINT_ERR, "\n val_ras_inject_error failed, node %d", node_index); + fail_cnt++; + break; + } + + /* wait loop to allow system to inject the error */ + val_ras_wait_timeout(1); + + /* Perform a read to error-injected address, which will cause system to record the error + with address syndrome in one of the error records present for the current RAS node */ + err_inj_addr_data = val_mmio_read(err_inj_addr); + val_print(AVS_PRINT_DEBUG, "\n Error injected address: 0x%llx", err_inj_addr); + val_print(AVS_PRINT_DEBUG, " Data read: 0x%lx", err_inj_addr_data); + + /* wait loop to allow system to update RAS error records */ + val_ras_wait_timeout(1); + +exception_return: + /* Check for External Abort */ + if (esr_pending) { + val_print(AVS_PRINT_DEBUG, "\n Data abort Check Fail, for node %d", node_index); + fail_cnt++; + continue; + } + } + + if (fail_cnt) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } else if (test_skip) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +ras009_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; /* This test is run on single processor */ + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/ras/operating_system/test_ras010.c b/test_pool/ras/operating_system/test_ras010.c new file mode 100644 index 00000000..348fbfb9 --- /dev/null +++ b/test_pool/ras/operating_system/test_ras010.c @@ -0,0 +1,86 @@ +/** @file + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_ras.h" + +#define TEST_NUM (AVS_RAS_TEST_NUM_BASE + 10) +#define TEST_RULE "SYS_RAS_1" +#define TEST_DESC "Check for patrol scrubbing support" + +static +void +payload() +{ + + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + uint32_t num_of_mem_blocks = 0; + uint32_t i, scrub_support; + uint32_t fail_cnt = 0; + + + /* Note: RAS2 entry for a proximity domain imply that the domain supports error detection */ + /* get total number of RAS2 memory info blocks */ + num_of_mem_blocks = val_ras2_get_mem_info(RAS2_NUM_MEM_BLOCK, 0); + if (num_of_mem_blocks == 0) { + val_print(AVS_PRINT_DEBUG, "\n No RAS2 memory nodes found. Skipping...", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + for (i = 0; i < num_of_mem_blocks; i++) { + /* check whether current NUMA node (proximity domain) support patrol scrubbing */ + scrub_support = val_ras2_get_mem_info(RAS2_SCRUB_SUPPORT, i); + if (scrub_support == 0) { + val_print(AVS_PRINT_DEBUG, + "\n Patrol scrubbing not supported by proximity domain: 0x%x", + val_ras2_get_mem_info(RAS2_PROX_DOMAIN, i)); + fail_cnt++; + } + } + + if (fail_cnt) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + return; +} + +uint32_t +ras010_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; /* This test is run on single processor */ + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/ras/operating_system/test_ras011.c b/test_pool/ras/operating_system/test_ras011.c new file mode 100644 index 00000000..882649fe --- /dev/null +++ b/test_pool/ras/operating_system/test_ras011.c @@ -0,0 +1,259 @@ +/** @file + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" +#include "val/include/sbsa_avs_memory.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_ras.h" + +#define TEST_NUM (AVS_RAS_TEST_NUM_BASE + 11) +#define TEST_RULE "SYS_RAS_2,SYS_RAS_3" +#define TEST_DESC "Check Poison Storage & Forwarding " + +static uint32_t esr_pending = 1; +static uint64_t int_id; + +static +void +intr_handler(void) +{ + /* Clear the interrupt pending state */ + + val_print(AVS_PRINT_INFO, "\n Received interrupt %x ", 0); + val_gic_end_of_interrupt(int_id); + return; +} + +static void *branch_to_test; + +static +void +esr(uint64_t interrupt_type, void *context) +{ + esr_pending = 0; + + /* Update the ELR to return to test specified address */ + val_pe_update_elr(context, (uint64_t)branch_to_test); + + val_print(AVS_PRINT_ERR, "\n Received exception of type: %d", interrupt_type); +} + +static +void +payload() +{ + + uint32_t status; + uint32_t fail_cnt = 0, test_skip = 1; + uint64_t num_node; + uint64_t value; + uint64_t mc_status; + uint64_t pe_status; + uint32_t node_index; + uint32_t poison_check; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + uint32_t mpidr = val_pe_get_mpid(); + uint64_t rec_index; + RAS_ERR_IN_t err_in_params; + RAS_ERR_OUT_t err_out_params; + uint64_t pe_node_index; + + /* Get Number of nodes with RAS Functionality */ + status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_node); + if (status || (num_node == 0)) { + val_print(AVS_PRINT_DEBUG, "\n RAS Nodes not found. Skipping...", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* Run this test only if this pe node has ras Functionality */ + /* Check current PE RAS Support with mpidr */ + status = val_ras_get_info(RAS_INFO_NODE_INDEX_FOR_AFF, mpidr, &pe_node_index); + if (status) { + val_print(AVS_PRINT_DEBUG, "\n RAS Node not found for PE", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } + + /* Check if Platform Supports Poison Storage & Forwarding */ + poison_check = val_ras_check_plat_poison_support(); + + for (node_index = 0; node_index < num_node; node_index++) { + + /* Get Current Node Type */ + status = val_ras_get_info(RAS_INFO_NODE_TYPE, node_index, &value); + if (status) { + val_print(AVS_PRINT_DEBUG, "\n Node Type not found index %d", node_index); + fail_cnt++; + break; + } + + /* Check if Node is Memory Controller */ + if (value != NODE_TYPE_MC) + continue; + + + /* Get Error Record number for this Node */ + status = val_ras_get_info(RAS_INFO_START_INDEX, node_index, &rec_index); + if (status) { + val_print(AVS_PRINT_DEBUG, "\n Could not get Start Index for index %d", node_index); + fail_cnt++; + continue; + } + + err_in_params.rec_index = rec_index; + err_in_params.node_index = node_index; + err_in_params.ras_error_type = ERR_CE; + err_in_params.is_pfg_check = 0; + + /* Get Interrupt details for this node */ + status = val_ras_get_info(RAS_INFO_ERI_ID, node_index, &int_id); + if (status) { + /* Interrupt details not found, Failing for this node */ + val_print(AVS_PRINT_DEBUG, "\n No Intr found, Failed for node %d", node_index); + fail_cnt++; + continue; + } + + test_skip = 0; + + /* Install sync and async handlers to handle exceptions.*/ + status = val_pe_install_esr(EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, esr); + status |= val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); + if (status) + { + val_print(AVS_PRINT_ERR, "\n Failed in installing the exception handler", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03)); + return; + } + branch_to_test = &&exception_return; + + /* Install handler for interrupt */ + val_gic_install_isr(int_id, intr_handler); + + /* Setup an error in an implementation defined way */ + status = val_ras_setup_error(err_in_params, &err_out_params); + if (status) { + val_print(AVS_PRINT_ERR, "\n val_ras_setup_error failed, node %d", node_index); + fail_cnt++; + break; + } + + /* Inject error in an implementation defined way */ + status = val_ras_inject_error(err_in_params, &err_out_params); + if (status) { + val_print(AVS_PRINT_ERR, "\n val_ras_inject_error failed, node %d", node_index); + fail_cnt++; + break; + } + +exception_return: + /* Read Status Register for Memory Controller RAS Node */ + status = val_ras_check_err_record(node_index, err_in_params.ras_error_type); + if (status) { + val_print(AVS_PRINT_ERR, "\n MC Err Status Check Failed, for node %d", node_index); + fail_cnt++; + continue; + } + + /* Read Status Register for PE RAS Node */ + status = val_ras_check_err_record(pe_node_index, err_in_params.ras_error_type); + if (status) { + val_print(AVS_PRINT_ERR, "\n PE Err Status Check Failed, for node %d", node_index); + fail_cnt++; + continue; + } + + if (poison_check) { + /* Poison Check only if Poison Storage & Forwarding Supported */ + /* Read Status Register for RAS Nodes */ + mc_status = val_ras_reg_read(node_index, RAS_ERR_STATUS, rec_index); + if (mc_status == INVALID_RAS_REG_VAL) { + val_print(AVS_PRINT_ERR, + "\n Couldn't read ERR<%d>STATUS register for ", + rec_index); + val_print(AVS_PRINT_ERR, + "RAS node index: 0x%lx", + node_index); + fail_cnt++; + continue; + } + pe_status = val_ras_reg_read(pe_node_index, RAS_ERR_STATUS, rec_index); + if (pe_status == INVALID_RAS_REG_VAL) { + val_print(AVS_PRINT_ERR, + "\n Couldn't read ERR<%d>STATUS register for ", + rec_index); + val_print(AVS_PRINT_ERR, + "RAS node index: 0x%lx", + pe_node_index); + fail_cnt++; + continue; + } + + /* Check Poison Information Storage/Forwarding in MC/PE Ras Node */ + if (!(mc_status & ERR_STATUS_PN_MASK)) { + val_print(AVS_PRINT_DEBUG, "\n Poison Storage Fail, for node %d", node_index); + fail_cnt++; + continue; + } + if (!(pe_status & ERR_STATUS_PN_MASK)) { + val_print(AVS_PRINT_DEBUG, "\n Poison Frwding Fail, for node %d", pe_node_index); + fail_cnt++; + continue; + } + } else { + /* Check for External Abort */ + if (esr_pending) { + val_print(AVS_PRINT_DEBUG, "\n EA Check Fail, for node %d", pe_node_index); + fail_cnt++; + continue; + } + } + } + + if (fail_cnt) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 04)); + return; + } else if (test_skip) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +ras011_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/ras/operating_system/test_ras012.c b/test_pool/ras/operating_system/test_ras012.c new file mode 100644 index 00000000..662031ce --- /dev/null +++ b/test_pool/ras/operating_system/test_ras012.c @@ -0,0 +1,142 @@ +/** @file + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" +#include "val/include/sbsa_avs_memory.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_ras.h" + +#define TEST_NUM (AVS_RAS_TEST_NUM_BASE + 12) +#define TEST_RULE "SYS_RAS_2" +#define TEST_DESC "Check Pseudo Fault Injection " + +static void *branch_to_test; + +static +void +esr(uint64_t interrupt_type, void *context) +{ + /* Update the ELR to return to test specified address */ + val_pe_update_elr(context, (uint64_t)branch_to_test); + + val_print(AVS_PRINT_ERR, "\n Received exception of type: %d", interrupt_type); +} + +static +void +payload() +{ + + uint32_t status; + uint32_t fail_cnt = 0, test_skip = 1; + uint64_t num_node; + uint32_t node_index; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + uint64_t rec_index; + RAS_ERR_IN_t err_in_params; + RAS_ERR_OUT_t err_out_params; + + /* Get Number of nodes with RAS Functionality */ + status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_node); + if (status || (num_node == 0)) { + val_print(AVS_PRINT_DEBUG, "\n RAS Nodes not found. Skipping...", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* Run this test only if this pe node has ras Functionality */ + for (node_index = 0; node_index < num_node; node_index++) { + + /* Get Error Record number for this Node */ + status = val_ras_get_info(RAS_INFO_START_INDEX, node_index, &rec_index); + if (status) { + val_print(AVS_PRINT_DEBUG, "\n Could not get Start Index for index %d", node_index); + fail_cnt++; + continue; + } + + err_in_params.rec_index = rec_index; + err_in_params.node_index = node_index; + err_in_params.ras_error_type = ERR_CE; + err_in_params.is_pfg_check = 0; + + test_skip = 0; + + /* Install sync and async handlers to handle exceptions.*/ + status = val_pe_install_esr(EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, esr); + status |= val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); + if (status) + { + val_print(AVS_PRINT_ERR, "\n Failed in installing the exception handler", 0); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } + branch_to_test = &&exception_return; + + /* Setup an error in an implementation defined way */ + status = val_ras_setup_error(err_in_params, &err_out_params); + if (status == NOT_IMPLEMENTED) { + val_print(AVS_PRINT_ERR, "\n ras_setup_error API unimplemented", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* Inject error in an implementation defined way */ + status = val_ras_inject_error(err_in_params, &err_out_params); + +exception_return: + /* Read Status Register for RAS Nodes */ + status = val_ras_check_err_record(node_index, err_in_params.ras_error_type); + if (status) { + val_print(AVS_PRINT_ERR, "\n Err Status Check Failed, for node %d", node_index); + fail_cnt++; + continue; + } + } + + if (fail_cnt) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03)); + return; + } else if (test_skip) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +ras012_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/uefi_app/SbsaAvs.h b/uefi_app/SbsaAvs.h index a3c5e441..a344b0eb 100644 --- a/uefi_app/SbsaAvs.h +++ b/uefi_app/SbsaAvs.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2021, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -20,13 +20,13 @@ - #define SBSA_ACS_MAJOR_VER 6 - #define SBSA_ACS_MINOR_VER 1 + #define SBSA_ACS_MAJOR_VER 7 + #define SBSA_ACS_MINOR_VER 1 #define SBSA_ACS_SUBMINOR_VER 0 #define G_SBSA_LEVEL 4 #define SBSA_MIN_LEVEL_SUPPORTED 3 - #define SBSA_MAX_LEVEL_SUPPORTED 6 + #define SBSA_MAX_LEVEL_SUPPORTED 7 #define G_PRINT_LEVEL AVS_PRINT_TEST #define PE_INFO_TBL_SZ 8192 /*Supports maximum 400 PEs*/ @@ -39,6 +39,14 @@ #define PERIPHERAL_INFO_TBL_SZ 1024 /*Supports maximum 20 PCIe EPs (USB and SATA controllers only) */ #define PCIE_INFO_TBL_SZ 512 /*Supports maximum 20 RC's*/ + #define PMU_INFO_TBL_SZ 20488 /*Supports maximum 512 PMUs*/ + #define RAS_INFO_TBL_SZ 32768 /*Supports maximum 256 RAS Nodes*/ + #define RAS2_FEAT_INFO_TBL_SZ 32768 /*Supports maximum of 1024 RAS2 memory feature entries*/ + #define CACHE_INFO_TBL_SZ 262144 /*Support maximum of 7280 cache entries*/ + #define SRAT_INFO_TBL_SZ 12000 /*Support maximum of 500 mem proximity domain entries*/ + #define MPAM_INFO_TBL_SZ 98304 /*Supports maximum of 2048 MSC entries*/ + #define HMAT_INFO_TBL_SZ 8192 /*Supports maximum of 400 Proximity domains*/ + #ifdef _AARCH64_BUILD_ unsigned long __stack_chk_guard = 0xBAAAAAAD; unsigned long __stack_chk_fail = 0xBAAFAAAD; diff --git a/uefi_app/SbsaAvs.inf b/uefi_app/SbsaAvs.inf index 0392208d..b07490eb 100644 --- a/uefi_app/SbsaAvs.inf +++ b/uefi_app/SbsaAvs.inf @@ -113,6 +113,9 @@ ../test_pool/pcie/test_p058.c ../test_pool/pcie/test_p059.c ../test_pool/pcie/test_p060.c + ../test_pool/pcie/operating_system/test_p061.c + ../test_pool/pcie/operating_system/test_p062.c + ../test_pool/smmu/operating_system/test_i001.c ../test_pool/smmu/operating_system/test_i002.c ../test_pool/smmu/operating_system/test_i003.c @@ -145,6 +148,40 @@ ../test_pool/exerciser/test_e014.c ../test_pool/exerciser/test_e015.c ../test_pool/exerciser/test_e016.c + ../test_pool/exerciser/operating_system/test_e017.c + ../test_pool/exerciser/operating_system/test_e018.c + ../test_pool/exerciser/operating_system/test_e019.c + ../test_pool/exerciser/operating_system/test_e020.c + + ../test_pool/mpam/operating_system/test_mpam001.c + ../test_pool/mpam/operating_system/test_mpam002.c + ../test_pool/mpam/operating_system/test_mpam003.c + ../test_pool/mpam/operating_system/test_mpam004.c + ../test_pool/mpam/operating_system/test_mpam005.c + ../test_pool/mpam/operating_system/test_mpam006.c + + ../test_pool/pmu/operating_system/test_pmu001.c + ../test_pool/pmu/operating_system/test_pmu002.c + ../test_pool/pmu/operating_system/test_pmu003.c + ../test_pool/pmu/operating_system/test_pmu004.c + ../test_pool/pmu/operating_system/test_pmu005.c + ../test_pool/pmu/operating_system/test_pmu006.c + ../test_pool/pmu/operating_system/test_pmu007.c + ../test_pool/pmu/operating_system/test_pmu008.c + ../test_pool/pmu/operating_system/test_pmu009.c + + ../test_pool/ras/operating_system/test_ras001.c + ../test_pool/ras/operating_system/test_ras002.c + ../test_pool/ras/operating_system/test_ras003.c + ../test_pool/ras/operating_system/test_ras004.c + ../test_pool/ras/operating_system/test_ras005.c + ../test_pool/ras/operating_system/test_ras006.c + ../test_pool/ras/operating_system/test_ras007.c + ../test_pool/ras/operating_system/test_ras008.c + ../test_pool/ras/operating_system/test_ras009.c + ../test_pool/ras/operating_system/test_ras010.c + ../test_pool/ras/operating_system/test_ras011.c + ../test_pool/ras/operating_system/test_ras012.c [Packages] StdLib/StdLib.dec @@ -177,4 +214,4 @@ [BuildOptions] GCC:*_*_*_ASM_FLAGS = -march=armv8.1-a - GCC:*_*_*_CC_FLAGS = -O0 -D ONLY_SBSA_RULE_TESTS + GCC:*_*_*_CC_FLAGS = -O0 diff --git a/uefi_app/SbsaAvsMain.c b/uefi_app/SbsaAvsMain.c index a04b761b..95072e7b 100644 --- a/uefi_app/SbsaAvsMain.c +++ b/uefi_app/SbsaAvsMain.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -36,9 +36,9 @@ UINT32 g_sbsa_level; UINT32 g_enable_pcie_tests; UINT32 g_print_level; UINT32 g_execute_nist; -UINT32 g_print_mmio; -UINT32 g_curr_module; -UINT32 g_enable_module; +UINT32 g_print_mmio = FALSE; +UINT32 g_curr_module = 0; +UINT32 g_enable_module = 0; UINT32 g_skip_test_num[MAX_TEST_SKIP_NUM] = { 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000, 10000 }; UINT32 g_single_test = SINGLE_TEST_SENTINEL; @@ -239,6 +239,175 @@ createPeripheralInfoTable( return Status; } +EFI_STATUS +createPmuInfoTable( +) +{ + UINT64 *PmuInfoTable; + EFI_STATUS Status; + + Status = gBS->AllocatePool (EfiBootServicesData, + PMU_INFO_TBL_SZ, + (VOID **) &PmuInfoTable); + + if (EFI_ERROR(Status)) + { + Print(L"Allocate Pool failed %x \n", Status); + return Status; + } + val_pmu_create_info_table(PmuInfoTable); + + return Status; + +} + +EFI_STATUS +createRasInfoTable( +) +{ + UINT64 *RasInfoTable; + EFI_STATUS Status; + + Status = gBS->AllocatePool(EfiBootServicesData, + RAS_INFO_TBL_SZ, + (VOID **) &RasInfoTable); + + if (EFI_ERROR(Status)) + { + Print(L"Allocate Pool failed %x \n", Status); + return Status; + } + val_ras_create_info_table(RasInfoTable); + + return Status; + +} + +EFI_STATUS +createCacheInfoTable( +) +{ + UINT64 *CacheInfoTable; + EFI_STATUS Status; + + Status = gBS->AllocatePool(EfiBootServicesData, + CACHE_INFO_TBL_SZ, + (VOID **) &CacheInfoTable); + + if (EFI_ERROR(Status)) + { + Print(L"Allocate Pool failed %x \n", Status); + return Status; + } + val_cache_create_info_table(CacheInfoTable); + + return Status; +} + +EFI_STATUS +createMpamInfoTable( +) +{ + UINT64 *MpamInfoTable; + EFI_STATUS Status; + + Status = gBS->AllocatePool(EfiBootServicesData, + MPAM_INFO_TBL_SZ, + (VOID **) &MpamInfoTable); + + if (EFI_ERROR(Status)) + { + Print(L"Allocate Pool failed %x \n", Status); + return Status; + } + val_mpam_create_info_table(MpamInfoTable); + + return Status; +} + +EFI_STATUS +createHmatInfoTable( +) +{ + UINT64 *HmatInfoTable; + EFI_STATUS Status; + + Status = gBS->AllocatePool(EfiBootServicesData, + HMAT_INFO_TBL_SZ, + (VOID **) &HmatInfoTable); + + if (EFI_ERROR(Status)) + { + Print(L"Allocate Pool failed %x \n", Status); + return Status; + } + val_hmat_create_info_table(HmatInfoTable); + + return Status; +} + +EFI_STATUS +createSratInfoTable( +) +{ + UINT64 *SratInfoTable; + EFI_STATUS Status; + + Status = gBS->AllocatePool(EfiBootServicesData, + SRAT_INFO_TBL_SZ, + (VOID **) &SratInfoTable); + + if (EFI_ERROR(Status)) + { + Print(L"Allocate Pool failed %x \n", Status); + return Status; + } + val_srat_create_info_table(SratInfoTable); + + return Status; +} + +/** + @brief This API allocates memory for info table and + calls create info table function passed as parameter. + + @param create_info_tbl_func - function pointer to val_*_create_info_table + @param info_table_size - memory size to be allocated. + + @return None +**/ + +EFI_STATUS +createInfoTable( + VOID(*create_info_tbl_func)(UINT64 *), + UINT64 info_table_size, + CHAR8 *table_name + ) +{ + UINT64 *InfoTable; + EFI_STATUS Status; + + val_print(AVS_PRINT_DEBUG, "\n Allocating memory for ", 0); + val_print(AVS_PRINT_DEBUG, table_name, 0); + val_print(AVS_PRINT_DEBUG, " info table", 0); + + Status = gBS->AllocatePool(EfiBootServicesData, + info_table_size, + (VOID **) &InfoTable); + + if (EFI_ERROR(Status)) + { + val_print(AVS_PRINT_ERR, "\n Allocate memory for ", 0); + val_print(AVS_PRINT_ERR, table_name, 0); + val_print(AVS_PRINT_ERR, " info table failed : %x", Status); + return Status; + } + + (*create_info_tbl_func)(InfoTable); + + return Status; +} + VOID freeSbsaAvsMem() { @@ -250,6 +419,12 @@ freeSbsaAvsMem() val_pcie_free_info_table(); val_iovirt_free_info_table(); val_peripheral_free_info_table(); + val_pmu_free_info_table(); + val_cache_free_info_table(); + val_mpam_free_info_table(); + val_hmat_free_info_table(); + val_srat_free_info_table(); + val_ras2_free_info_table(); val_free_shared_mem(); } @@ -258,16 +433,14 @@ HelpMsg ( VOID ) { - Print (L"\nUsage: Sbsa.efi [-v ] | [-l ] | [-f ] | [-skip ] | [-nist] | [-p ] | [-t ] | [-m ]\n" - "[-skip ] | [-nist] | [-p ]\n" + Print (L"\nUsage: Sbsa.efi [-v ] | [-l ] | [-f ] | " + "[-skip ] | [-nist] | [-p ] | [-t ] | [-m ]\n" "Options:\n" "-v Verbosity of the Prints\n" " 1 shows all prints, 5 shows Errors\n" - " Note: pal_mmio prints can be enabled for specific modules by passing\n" - " module numbers along with global verbosity level 1\n" - " Module numbers are PE 0, GIC 1, ...\n" - " E.g., To enable mmio prints for PE and TIMER pass -v 102 \n" "-mmio Pass this flag to enable pal_mmio_read/write prints, use with -v 1\n" + " Refer to section 4 of SBSA_ACS_User_Guide\n" + " To skip a module, use Model_ID as mentioned in user guide\n" "-l Level of compliance to be tested for\n" " As per SBSA spec, 3 to 6\n" "-f Name of the log file to record the test results in\n" @@ -296,7 +469,7 @@ STATIC CONST SHELL_PARAM_ITEM ParamList[] = { {L"-h" , TypeFlag}, // -h # help : info about commands {L"-nist" , TypeFlag}, // -nist # Binary Flag to enable the execution of NIST STS {L"-p" , TypeValue}, // -p # Enable/disable PCIe SBSA 6.0 (RCiEP) compliance tests. - {L"-mmio" , TypeFlag}, // -mmio # Enable pal_mmio prints + {L"-mmio" , TypeValue}, // -mmio # Enable pal_mmio prints {L"-t" , TypeValue}, // -t # Test to be run {L"-m" , TypeValue}, // -m # Module to be run {L"-p2p", TypeFlag}, // -p2p # Peer-to-Peer is supported @@ -325,7 +498,7 @@ ShellAppMainsbsa ( CONST CHAR16 *CmdLineArg; CHAR16 *ProbParam; UINT32 Status; - UINT32 ReadVerbosity; + UINT32 MmioVerbosity; UINT32 i,j=0; VOID *branch_label; @@ -375,12 +548,7 @@ ShellAppMainsbsa ( if (CmdLineArg == NULL) { g_print_level = G_PRINT_LEVEL; } else { - ReadVerbosity = StrDecimalToUintn(CmdLineArg); - while (ReadVerbosity/10) { - g_enable_module |= (1 << ReadVerbosity%10); - ReadVerbosity /= 10; - } - g_print_level = ReadVerbosity; + g_print_level = StrDecimalToUintn(CmdLineArg); if (g_print_level > 5) { g_print_level = G_PRINT_LEVEL; } @@ -417,17 +585,21 @@ ShellAppMainsbsa ( return 0; } - // Options with Flags - if (ShellCommandLineGetFlag (ParamPackage, L"-nist")) { - g_execute_nist = TRUE; - } else { - g_execute_nist = FALSE; - } if (ShellCommandLineGetFlag (ParamPackage, L"-mmio")) { - g_print_mmio = TRUE; - } else { - g_print_mmio = FALSE; + CmdLineArg = ShellCommandLineGetValue (ParamPackage, L"-mmio"); + if (CmdLineArg == NULL) { + g_print_mmio = TRUE; + } else { + MmioVerbosity = StrDecimalToUintn((CONST CHAR16 *)(CmdLineArg+0)); + g_enable_module |= (1 << MmioVerbosity/100); + for (i=0 ; i < StrLen(CmdLineArg) ; i++) { + if (*(CmdLineArg + i) == L',') { + MmioVerbosity = StrDecimalToUintn((CONST CHAR16 *)(CmdLineArg+i+1)); + g_enable_module |= (1 << MmioVerbosity/100); + } + } + } } if (ShellCommandLineGetFlag (ParamPackage, L"-p2p")) { @@ -457,6 +629,16 @@ ShellAppMainsbsa ( } } + // Options with Flags + if (ShellCommandLineGetFlag (ParamPackage, L"-nist")) { + g_execute_nist = TRUE; + } else { + g_execute_nist = FALSE; + } + + if (g_sbsa_level == 7) + g_execute_nist = TRUE; + // Options with Values CmdLineArg = ShellCommandLineGetValue (ParamPackage, L"-t"); if (CmdLineArg != NULL) { @@ -496,8 +678,31 @@ ShellAppMainsbsa ( createTimerInfoTable(); createWatchdogInfoTable(); + + Status = createCacheInfoTable(); + if (Status) + Print(L" Failed to created Cache info table \n"); + + Status = createMpamInfoTable(); + if (Status) + Print(L" Failed to created Mpam info table \n"); + + Status = createHmatInfoTable(); + if (Status) + Print(L" Failed to created HMAT info table \n"); + + Status = createSratInfoTable(); + if (Status) + Print(L" Failed to created SRAT info table \n"); + + Status = createInfoTable(val_ras2_create_info_table, RAS2_FEAT_INFO_TBL_SZ, "RAS2"); + if (Status) + Print(L" Failed to created RAS2 feature info table \n"); + createPcieVirtInfoTable(); createPeripheralInfoTable(); + createPmuInfoTable(); + createRasInfoTable(); val_allocate_shared_mem(); @@ -513,33 +718,36 @@ ShellAppMainsbsa ( val_print(AVS_PRINT_TEST, "\n *** Starting GIC tests *** \n", 0); Status |= val_gic_execute_tests(g_sbsa_level, val_pe_get_num()); -#ifndef ONLY_SBSA_RULE_TESTS - val_print(AVS_PRINT_TEST, "\n *** Starting Timer tests *** \n", 0); - Status |= val_timer_execute_tests(g_sbsa_level, val_pe_get_num()); -#endif - -#ifdef ONLY_SBSA_RULE_TESTS if (g_sbsa_level > 4) -#endif { val_print(AVS_PRINT_TEST, "\n *** Starting Watchdog tests *** \n", 0); Status |= val_wd_execute_tests(g_sbsa_level, val_pe_get_num()); } -#ifndef ONLY_SBSA_RULE_TESTS - val_print(AVS_PRINT_TEST, "\n *** Starting Power and Wakeup semantic tests *** \n", 0); - Status |= val_wakeup_execute_tests(g_sbsa_level, val_pe_get_num()); + if (g_sbsa_level > 3) { + val_print(AVS_PRINT_TEST, "\n *** Starting SMMU tests *** \n", 0); + Status |= val_smmu_execute_tests(g_sbsa_level, val_pe_get_num()); + } - val_print(AVS_PRINT_TEST, "\n *** Starting Peripheral tests *** \n", 0); - Status |= val_peripheral_execute_tests(g_sbsa_level, val_pe_get_num()); -#endif + val_print(AVS_PRINT_TEST, "\n *** Starting Memory tests *** \n", 0); + Status |= val_memory_execute_tests(g_sbsa_level, val_pe_get_num()); - val_print(AVS_PRINT_TEST, "\n *** Starting SMMU tests *** \n", 0); - Status |= val_smmu_execute_tests(g_sbsa_level, val_pe_get_num()); + if (g_sbsa_level > 6) { + val_print(AVS_PRINT_TEST, "\n *** Starting MPAM tests *** \n", 0); + Status |= val_mpam_execute_tests(g_sbsa_level, val_pe_get_num()); + } + + if (g_sbsa_level > 6) { + val_print(AVS_PRINT_TEST, "\n *** Starting PMU tests *** \n", 0); + Status |= val_pmu_execute_tests(g_sbsa_level, val_pe_get_num()); + } + + if (g_sbsa_level > 6) { + val_print(AVS_PRINT_TEST, "\n *** Starting RAS tests *** \n", 0); + Status |= val_ras_execute_tests(g_sbsa_level, val_pe_get_num()); + } -#ifdef ONLY_SBSA_RULE_TESTS if (g_sbsa_level > 5) -#endif { val_print(AVS_PRINT_TEST, "\n *** Starting PCIe tests *** \n", 0); Status |= val_pcie_execute_tests(g_enable_pcie_tests, g_sbsa_level, val_pe_get_num()); @@ -557,12 +765,12 @@ ShellAppMainsbsa ( } - #ifdef ENABLE_NIST +#ifdef ENABLE_NIST if (g_execute_nist == TRUE) { val_print(AVS_PRINT_TEST, "\n *** Starting NIST statistical tests *** \n", 0); Status |= val_nist_execute_tests(g_sbsa_level, val_pe_get_num()); } - #endif +#endif print_test_status: val_print(AVS_PRINT_TEST, "\n ------------------------------------------------------- \n", 0); diff --git a/uefi_app/SbsaAvsNist.inf b/uefi_app/SbsaAvsNist.inf index 57c82db4..a5a54a95 100644 --- a/uefi_app/SbsaAvsNist.inf +++ b/uefi_app/SbsaAvsNist.inf @@ -1,5 +1,5 @@ ## @file -# Copyright (c) 2020-2021, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2020-2023, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -75,7 +75,6 @@ ../test_pool/watchdog/operating_system/test_w001.c ../test_pool/pcie/test_p001.c - ../test_pool/pcie/test_p002.c ../test_pool/pcie/test_p003.c ../test_pool/pcie/test_p020.c ../test_pool/pcie/test_p021.c @@ -97,7 +96,6 @@ ../test_pool/pcie/test_p037.c ../test_pool/pcie/test_p038.c ../test_pool/pcie/test_p039.c - ../test_pool/pcie/test_p040.c ../test_pool/pcie/test_p041.c ../test_pool/pcie/test_p042.c ../test_pool/pcie/test_p043.c @@ -110,11 +108,14 @@ ../test_pool/pcie/test_p050.c ../test_pool/pcie/test_p051.c ../test_pool/pcie/test_p052.c - ../test_pool/pcie/test_p053.c - ../test_pool/pcie/test_p054.c - ../test_pool/pcie/test_p055.c ../test_pool/pcie/test_p056.c ../test_pool/pcie/test_p057.c + ../test_pool/pcie/test_p058.c + ../test_pool/pcie/test_p059.c + ../test_pool/pcie/test_p060.c + ../test_pool/pcie/operating_system/test_p061.c + ../test_pool/pcie/operating_system/test_p062.c + ../test_pool/smmu/operating_system/test_i001.c ../test_pool/smmu/operating_system/test_i002.c ../test_pool/smmu/operating_system/test_i003.c @@ -146,6 +147,42 @@ ../test_pool/exerciser/test_e013.c ../test_pool/exerciser/test_e014.c ../test_pool/exerciser/test_e015.c + ../test_pool/exerciser/test_e016.c + ../test_pool/exerciser/operating_system/test_e017.c + ../test_pool/exerciser/operating_system/test_e018.c + ../test_pool/exerciser/operating_system/test_e019.c + ../test_pool/exerciser/operating_system/test_e020.c + + ../test_pool/mpam/operating_system/test_mpam001.c + ../test_pool/mpam/operating_system/test_mpam002.c + ../test_pool/mpam/operating_system/test_mpam003.c + ../test_pool/mpam/operating_system/test_mpam004.c + ../test_pool/mpam/operating_system/test_mpam005.c + ../test_pool/mpam/operating_system/test_mpam006.c + + ../test_pool/pmu/operating_system/test_pmu001.c + ../test_pool/pmu/operating_system/test_pmu002.c + ../test_pool/pmu/operating_system/test_pmu003.c + ../test_pool/pmu/operating_system/test_pmu004.c + ../test_pool/pmu/operating_system/test_pmu005.c + ../test_pool/pmu/operating_system/test_pmu006.c + ../test_pool/pmu/operating_system/test_pmu007.c + ../test_pool/pmu/operating_system/test_pmu008.c + ../test_pool/pmu/operating_system/test_pmu009.c + + ../test_pool/ras/operating_system/test_ras001.c + ../test_pool/ras/operating_system/test_ras002.c + ../test_pool/ras/operating_system/test_ras003.c + ../test_pool/ras/operating_system/test_ras004.c + ../test_pool/ras/operating_system/test_ras005.c + ../test_pool/ras/operating_system/test_ras006.c + ../test_pool/ras/operating_system/test_ras007.c + ../test_pool/ras/operating_system/test_ras008.c + ../test_pool/ras/operating_system/test_ras009.c + ../test_pool/ras/operating_system/test_ras010.c + ../test_pool/ras/operating_system/test_ras011.c + ../test_pool/ras/operating_system/test_ras012.c + ../test_pool/nist_sts/test_n001.c [Packages] @@ -180,3 +217,5 @@ [BuildOptions] GCC:*_*_*_ASM_FLAGS = -march=armv8.1-a + GCC:*_*_*_CC_FLAGS = -O0 + diff --git a/val/include/pal_interface.h b/val/include/pal_interface.h index 1adb5e96..584806ca 100644 --- a/val/include/pal_interface.h +++ b/val/include/pal_interface.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -20,6 +20,7 @@ #ifdef TARGET_LINUX #include +#include #endif #ifdef TARGET_LINUX @@ -110,12 +111,17 @@ typedef struct { /** @brief structure instance for PE entry **/ +#define DEFAULT_CACHE_IDX 0xFFFFFFFF +#define MAX_L1_CACHE_RES 2 /* Generally PE Level 1 have a data and a instruction cache */ + typedef struct { - uint32_t pe_num; ///< PE Index - uint32_t attr; ///< PE attributes - uint64_t mpidr; ///< PE MPIDR - uint32_t pmu_gsiv; ///< PMU Interrupt ID + uint32_t pe_num; /* PE Index */ + uint32_t attr; /* PE attributes */ + uint64_t mpidr; /* PE MPIDR */ + uint32_t pmu_gsiv; /* PMU Interrupt */ uint32_t gmain_gsiv; /* GIC Maintenance Interrupt */ + uint32_t acpi_proc_uid; /* ACPI Processor UID */ + uint32_t level_1_res[MAX_L1_CACHE_RES]; /* index of level 1 cache(s) in cache_info_table */ }PE_INFO_ENTRY; typedef struct { @@ -402,8 +408,14 @@ typedef union { #define MAX_NAMED_COMP_LENGTH 256 +typedef struct { + uint64_t smmu_base; /* SMMU base to which component is attached, else NULL */ + uint32_t cca; /* Cache Coherency Attribute */ + char name[MAX_NAMED_COMP_LENGTH]; /* Device object name */ +} IOVIRT_NAMED_COMP_INFO_BLOCK; + typedef union { - char name[MAX_NAMED_COMP_LENGTH]; + IOVIRT_NAMED_COMP_INFO_BLOCK named_comp; IOVIRT_RC_INFO_BLOCK rc; IOVIRT_PMCG_INFO_BLOCK pmcg; uint32_t its_count; @@ -435,6 +447,10 @@ void pal_iovirt_create_info_table(IOVIRT_INFO_TABLE *iovirt); uint32_t pal_iovirt_check_unique_ctx_intid(uint64_t smmu_block); uint32_t pal_iovirt_unique_rid_strid_map(uint64_t rc_block); uint64_t pal_iovirt_get_rc_smmu_base(IOVIRT_INFO_TABLE *iovirt, uint32_t rc_seg_num, uint32_t rid); +#ifdef TARGET_LINUX +uint32_t pal_get_device_path(const char *hid, char hid_path[][MAX_NAMED_COMP_LENGTH]); +uint32_t pal_smmu_is_etr_behind_catu(char *etr_path); +#endif /** @brief SMMU Info Table @@ -722,7 +738,10 @@ typedef enum { CFG_TXN_ATTRIBUTES = 0x7, ATS_RES_ATTRIBUTES = 0x8, TRANSACTION_TYPE = 0x9, - NUM_TRANSACTIONS = 0xA + NUM_TRANSACTIONS = 0xA, + ADDRESS_ATTRIBUTES = 0xB, + DATA_ATTRIBUTES = 0xC, + ERROR_INJECT_TYPE = 0xD } EXERCISER_PARAM_TYPE; typedef enum { @@ -758,7 +777,8 @@ typedef enum { TXN_NO_SNOOP_DISABLE = 0xa, START_TXN_MONITOR = 0xb, STOP_TXN_MONITOR = 0xc, - ATS_TXN_REQ = 0xd + ATS_TXN_REQ = 0xd, + INJECT_ERROR = 0xe } EXERCISER_OPS; typedef enum { @@ -817,7 +837,331 @@ uint32_t pal_exerciser_get_state(EXERCISER_STATE *state, uint32_t bdf); uint32_t pal_exerciser_ops(EXERCISER_OPS ops, uint64_t param, uint32_t instance); uint32_t pal_exerciser_get_data(EXERCISER_DATA_TYPE type, exerciser_data_t *data, uint32_t bdf, uint64_t ecam); - uint32_t pal_nist_generate_rng(uint32_t *rng_buffer); + +/* PMU related APIs and structures*/ + +/** + @brief Instance of system pmu info +**/ +typedef struct { + uint8_t type; /* The component that this PMU block is associated with*/ + uint64_t primary_instance; /* Primary node instance, specific to the PMU type*/ + uint32_t secondary_instance; /* Secondary node instance, specific to the PMU type*/ + uint8_t dual_page_extension; /* Support of the dual-page mode*/ + uint64_t base0; /* Base address of Page 0 of the PMU*/ + uint64_t base1; /* Base address of Page 1 of the PMU, + valid only if dual_page_extension is 1*/ +} PMU_INFO_BLOCK; + +typedef struct { + uint32_t pmu_count; /* Total number of PMU info blocks*/ + PMU_INFO_BLOCK info[]; /* PMU info blocks for each PMU nodes*/ +} PMU_INFO_TABLE; + +/** + @brief SRAT node type +**/ + +typedef enum { + SRAT_NODE_MEM_AFF = 0x01, + SRAT_NODE_GICC_AFF = 0x03 +} SRAT_NODE_TYPE_e; + +/** + @brief SRAT GICC Affinity Structure +**/ + +typedef struct { + uint32_t prox_domain; /* Proximity domain*/ + uint32_t proc_uid; /* ACPI Processor UID */ + uint32_t flags; /* Flags*/ + uint32_t clk_domain; /* Clock Domain*/ +} SRAT_GICC_AFF_ENTRY; + +/** + @brief SRAT Memory Affinity Structure +**/ + +typedef struct { + uint32_t prox_domain; /* Proximity domain */ + uint32_t flags; /* flags */ + uint64_t addr_base; /* mem range address base */ + uint64_t addr_len; /* mem range address len */ +} SRAT_MEM_AFF_ENTRY; + +typedef union { + SRAT_MEM_AFF_ENTRY mem_aff; + SRAT_GICC_AFF_ENTRY gicc_aff; +} SRAT_NODE_INFO; + +typedef struct { + uint32_t node_type; /* Node type*/ + SRAT_NODE_INFO node_data; +} SRAT_INFO_ENTRY; + +typedef struct { + uint32_t num_of_srat_entries; + uint32_t num_of_mem_ranges; + SRAT_INFO_ENTRY srat_info[]; +} SRAT_INFO_TABLE; + +typedef enum { + PMU_EVENT_IB_TOTAL_BW, /* Inbound total bandwidth */ + PMU_EVENT_OB_TOTAL_BW, /* Outbound total bandwidth */ + PMU_EVENT_IB_READ_BW, /* Inbound read bandwidth */ + PMU_EVENT_IB_WRITE_BW, /* Inbound write bandwidth */ + PMU_EVENT_OB_READ_BW, /* Outbound read bandwidth */ + PMU_EVENT_OB_WRITE_BW, /* Outbound write bandwidth */ + PMU_EVENT_IB_OPEN_TXN, /* Inbound open transactions */ + PMU_EVENT_IB_TOTAL_TXN, /* Inbound total transactions */ + PMU_EVENT_OB_OPEN_TXN, /* Outbound open transactions */ + PMU_EVENT_OB_TOTAL_TXN, /* Outbound total transactions */ + PMU_EVENT_LOCAL_BW, /* Local traffic bandwidth */ + PMU_EVENT_REMOTE_BW, /* Remote trafic bandwidth */ + PMU_EVENT_ALL_BW, /* All traffic bandwidth */ + PMU_EVENT_TRAFFIC_1, /* traffic type 1 */ + PMU_EVENT_TRAFFIC_2 /* traffic type 2 */ +} PMU_EVENT_TYPE_e; + +/* PMU node types */ +typedef enum { + PMU_NODE_MEM_CNTR, + PMU_NODE_SMMU, + PMU_NODE_PCIE_RC, + PMU_NODE_ACPI_DEVICE, + PMU_NODE_PE_CACHE +} PMU_NODE_INFO_TYPE; + + +#define PMU_EVENT_INVALID 0xFFFFFFFF + +/** + @brief This API fills in the PMU_INFO_TABLE with information about local and system + timers in the system. This is achieved by parsing the ACPI - APMT table. + + @param PmuTable - Address where the PMU information needs to be filled. + + @return None +**/ +void pal_pmu_create_info_table(PMU_INFO_TABLE *PmuTable); +uint32_t pal_pmu_get_event_info(PMU_EVENT_TYPE_e event_type, PMU_NODE_INFO_TYPE node_type); +uint32_t pal_pmu_get_multi_traffic_support_interface(uint64_t *interface_acpiid, + uint32_t *num_traffic_type_support); +uint32_t pal_generate_traffic(uint64_t interface_acpiid, uint32_t pmu_node_index, + uint32_t mon_index, uint32_t eventid); +uint32_t pal_pmu_check_monitor_count_value(uint64_t interface_acpiid, uint32_t count_value, + uint32_t eventid); + +/* Cache info table structures and APIs */ + +#define CACHE_TYPE_SHARED 0x0 +#define CACHE_TYPE_PRIVATE 0x1 +#define CACHE_INVALID_NEXT_LVL_IDX 0xFFFFFFFF +#define CACHE_INVALID_IDX 0xFFFFFFFF + +/*only the fields and flags required by ACS are parsed from ACPI PPTT table*/ +/*Cache flags indicate validity of cache info provided by PPTT Table*/ +typedef struct { + uint32_t size_property_valid; + uint32_t cache_type_valid; + uint32_t cache_id_valid; +} CACHE_FLAGS; + +/* Since most of platform doesn't support cache id field (ACPI 6.4+), ACS uses PPTT offset as key + to uniquely identify a cache, In future once platforms align with ACPI 6.4+ my_offset member + might be removed from cache entry*/ +typedef struct { + CACHE_FLAGS flags; /* Cache flags */ + uint32_t my_offset; /* Cache PPTT structure offset */ + uint32_t next_level_index; /* Index of next level cache entry in CACHE_INFO_TABLE */ + uint32_t size; /* Size of the cache in bytes */ + uint32_t cache_id; /* Unique, non-zero identifier for this cache */ + uint32_t is_private; /* Field indicate whether cache is private */ + uint8_t cache_type; /* Cache type */ +} CACHE_INFO_ENTRY; + +typedef struct { + uint32_t num_of_cache; /* Total of number of cache info entries */ + CACHE_INFO_ENTRY cache_info[]; /* Array of cache info entries */ +} CACHE_INFO_TABLE; + +void pal_cache_create_info_table(CACHE_INFO_TABLE *CacheTable, PE_INFO_TABLE *PeTable); +void pal_cache_dump_info_table(CACHE_INFO_TABLE *CacheTable, PE_INFO_TABLE *PeTable); + +/* + * @brief MPAM Resource Node + */ + +#define MPAM_NEXT_MSC(msc_entry) \ + (MPAM_MSC_NODE *)((uint8_t *)(&msc_entry->rsrc_node[0]) \ + + msc_entry->rsrc_count * sizeof(MPAM_RESOURCE_NODE)) + +typedef struct { + uint8_t ris_index; + uint8_t locator_type; /* Identifies location of this resource */ + uint64_t descriptor1; /* Primary acpi description of location */ + uint32_t descriptor2; /* Secondary acpi description of location */ +} MPAM_RESOURCE_NODE; + +/* + * @brief MPAM MSC Node + */ +typedef struct { + uint64_t msc_base_addr; /* base addr of mem-map MSC reg */ + uint32_t msc_addr_len; /* MSC mem map size */ + uint32_t max_nrdy; /* max time in microseconds that MSC not ready + after config change */ + uint32_t rsrc_count; /* number of resource nodes */ + MPAM_RESOURCE_NODE rsrc_node[]; /* Details of resource node */ +} MPAM_MSC_NODE; + +/* + * @brief Mpam info table + */ +typedef struct { + uint32_t msc_count; /* Number of MSC node */ + MPAM_MSC_NODE msc_node[]; /* Details of MSC node */ +} MPAM_INFO_TABLE; + +void pal_mpam_create_info_table(MPAM_INFO_TABLE *MpamTable); +void *pal_mem_alloc_at_address(uint64_t mem_base, uint64_t size); +void pal_mem_free_at_address(uint64_t mem_base, uint64_t size); + +/* RAS INFO table */ + +typedef enum { + NODE_TYPE_PE = 0x0, + NODE_TYPE_MC = 0x1, + NODE_TYPE_SMMU = 0x2, + NODE_TYPE_VDR = 0x3, + NODE_TYPE_GIC = 0x4, + NODE_TYPE_LAST_ENTRY +} RAS_NODE_TYPE_e; + +typedef enum { + RAS_INTF_TYPE_SYS_REG, /* System register RAS node interface type */ + RAS_INTF_TYPE_MMIO /* MMIO RAS node interface type */ +} RAS_NODE_INTF_TYPE; + +typedef struct { + uint32_t processor_id; + uint32_t resource_type; + uint32_t flags; + uint64_t affinity; + uint64_t res_specific_data; /* Resource Specific Data */ +} RAS_NODE_PE_DATA; + +typedef struct { + uint32_t proximity_domain; +} RAS_NODE_MC_DATA; + +typedef struct { + RAS_NODE_INTF_TYPE intf_type; /* Interface Type */ + uint32_t flags; + uint64_t base_addr; + uint32_t start_rec_index; /* Start Record Index */ + uint32_t num_err_rec; + uint64_t err_rec_implement; + uint64_t err_status_reporting; + uint64_t addressing_mode; +} RAS_INTERFACE_INFO; + +typedef struct { + uint32_t type; + uint32_t flag; + uint32_t gsiv; + uint32_t its_grp_id; +} RAS_INTERRUPT_INFO; + +typedef union { + RAS_NODE_PE_DATA pe; + RAS_NODE_MC_DATA mc; +} RAS_NODE_DATA; + +typedef struct { + RAS_NODE_TYPE_e type; /* Node Type PE/GIC/SMMU */ + uint16_t length; /* Length of the Node */ + uint64_t num_intr_entries; /* Number of Interrupt Entry */ + RAS_NODE_DATA node_data; /* Node Specific Data */ + RAS_INTERFACE_INFO intf_info; /* Node Interface Info */ + RAS_INTERRUPT_INFO intr_info[2]; /* Node Interrupt Info */ + uint32_t err_grp_id; /* Error Group ID used in the ACS */ +} RAS_NODE_INFO; + +typedef struct { + uint32_t num_nodes; /* Number of total RAS Nodes */ + uint32_t num_pe_node; /* Number of PE RAS Nodes */ + uint32_t num_mc_node; /* Number of Memory Controller Nodes */ + RAS_NODE_INFO node[]; /* Array of RAS nodes */ +} RAS_INFO_TABLE; + +typedef enum { + ERR_UC = 0x1, /* UnContainable Error */ + ERR_DE, /* Deferred Error */ + ERR_CE, /* Correctable Error */ + ERR_CRITICAL, /* Critical Error */ + ERR_CONTAINABLE /* Containable Error */ +} RAS_ERROR_TYPE; + +typedef struct { + RAS_ERROR_TYPE ras_error_type; /* Error Type */ + uint64_t error_pa; /* Error Phy Address */ + uint32_t rec_index; /* Error Record Index */ + uint32_t node_index; /* Error Node Index in Info table */ + uint8_t is_pfg_check; /* Pseudo Fault Check or not */ +} RAS_ERR_IN_t; + +typedef struct { + uint32_t intr_id; /* Interrupt ID */ + uint32_t error_record; /* Error Record Number */ +} RAS_ERR_OUT_t; + +typedef enum { + RAS2_TYPE_MEMORY = 0 /* RAS2 memory feature type*/ +} RAS2_FEAT_TYPE; + +typedef struct { + uint32_t proximity_domain; /* Proximity domain of the memory */ + uint32_t patrol_scrub_support; /* Patrol srub support flag */ +} RAS2_MEM_INFO; + +typedef union { + RAS2_MEM_INFO mem_feat_info; /* Memory feature specific info */ +} RAS2_BLOCK_INFO; + +typedef struct { + RAS2_FEAT_TYPE type; /* RAS2 feature type*/ + RAS2_BLOCK_INFO block_info; /* RAS2 block info */ +} RAS2_BLOCK; + +typedef struct { + uint32_t num_all_block; /* Number of RAS2 feature blocks */ + uint32_t num_of_mem_block; /* Number of memory feature blocks */ + RAS2_BLOCK blocks[]; +} RAS2_INFO_TABLE; + +void pal_ras2_create_info_table(RAS2_INFO_TABLE *ras2_info_table); +void pal_ras_create_info_table(RAS_INFO_TABLE *ras_info_table); + +uint32_t pal_ras_setup_error(RAS_ERR_IN_t in_param, RAS_ERR_OUT_t *out_param); +uint32_t pal_ras_inject_error(RAS_ERR_IN_t in_param, RAS_ERR_OUT_t *out_param); +void pal_ras_wait_timeout(uint32_t count); +uint32_t pal_ras_check_plat_poison_support(void); + +typedef struct { + uint32_t mem_prox_domain; /* Proximity domain of the memory region*/ + uint64_t write_bw; /* Maximum write bandwidth */ + uint64_t read_bw; /* Maximum read bandwidth */ +} HMAT_BW_ENTRY; + +typedef struct { + uint32_t num_of_mem_prox_domain; /* Number of Memory Proximity Domains */ + HMAT_BW_ENTRY bw_info[]; /* Array of bandwidth info based on proximity domain */ +} HMAT_INFO_TABLE; + +void pal_hmat_create_info_table(HMAT_INFO_TABLE *HmatTable); +void pal_srat_create_info_table(SRAT_INFO_TABLE *SratTable); + #endif diff --git a/val/include/sbsa_avs_common.h b/val/include/sbsa_avs_common.h index 4bc2186d..e1c6cf29 100644 --- a/val/include/sbsa_avs_common.h +++ b/val/include/sbsa_avs_common.h @@ -32,6 +32,9 @@ #define AVS_SMMU_TEST_NUM_BASE 700 #define AVS_EXERCISER_TEST_NUM_BASE 800 #define AVS_NIST_TEST_NUM_BASE 900 +#define AVS_MPAM_TEST_NUM_BASE 1000 +#define AVS_PMU_TEST_NUM_BASE 1100 +#define AVS_RAS_TEST_NUM_BASE 1200 #define AVS_MEM_MAP_TEST_NUM_BASE 1300 #define STATE_BIT 28 @@ -63,7 +66,9 @@ #define SBSA_AVS_START(level, test_num) (((TEST_START_VAL) << STATE_BIT) | ((level) << LEVEL_BIT) | ((test_num) << TEST_NUM_BIT)) #define SBSA_AVS_END(level, test_num) (((TEST_END_VAL) << STATE_BIT) | ((level) << LEVEL_BIT) | ((test_num) << TEST_NUM_BIT)) +/* status definations*/ +#define STATUS_SYS_REG_ACCESS_FAIL 0x78 /* TEST Result defines */ @@ -133,6 +138,10 @@ typedef enum { PERIPHERAL_MODULE, SMMU_MODULE, EXERCISER_MODULE, + NIST_MODULE, + MPAM_MODULE, + PMU_MODULE, + RAS_MODULE, MEM_MAP_MODULE } MODULE_ID_e; diff --git a/val/include/sbsa_avs_exerciser.h b/val/include/sbsa_avs_exerciser.h index 8d807351..c44ce3fa 100644 --- a/val/include/sbsa_avs_exerciser.h +++ b/val/include/sbsa_avs_exerciser.h @@ -43,7 +43,7 @@ typedef enum { } EXERCISER_INFO_TYPE; -void val_exerciser_create_info_table(void); +uint32_t val_exerciser_create_info_table(void); uint32_t val_exerciser_init(uint32_t instance); uint32_t val_exerciser_get_info(EXERCISER_INFO_TYPE type, uint32_t instance); uint32_t val_exerciser_set_param(EXERCISER_PARAM_TYPE type, uint64_t value1, uint64_t value2, uint32_t instance); diff --git a/val/include/sbsa_avs_mmu.h b/val/include/sbsa_avs_mmu.h new file mode 100644 index 00000000..fdb557c6 --- /dev/null +++ b/val/include/sbsa_avs_mmu.h @@ -0,0 +1,34 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#ifndef __SBSA_AVS_MMU_H__ +#define __SBSA_AVS_MMU_H__ + +/* upper and lower mem attribute shift definitions */ +#define MEM_ATTR_INDX_SHIFT 2 +#define MEM_ATTR_AP_SHIFT 6 +#define MEM_ATTR_SH_SHIFT 8 +#define MEM_ATTR_AF_SHIFT 10 + +/* memory type MAIR register index definitions*/ +#define ATTR_DEVICE_nGnRnE (0x0ULL << MEM_ATTR_INDX_SHIFT) + +uint32_t val_mmu_check_for_entry(uint64_t base_addr); +uint32_t val_mmu_add_entry(uint64_t base_addr, uint64_t size); +uint32_t val_mmu_update_entry(uint64_t address, uint32_t size); + +#endif /* __SBSA_AVS_MMU_H__ */ diff --git a/val/include/sbsa_avs_mpam.h b/val/include/sbsa_avs_mpam.h new file mode 100644 index 00000000..987f2e7a --- /dev/null +++ b/val/include/sbsa_avs_mpam.h @@ -0,0 +1,112 @@ +/** @file + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#ifndef __SBSA_AVS_MPAM_H__ +#define __SBSA_AVS_MPAM_H__ + +/* The return value is always 64-bit, type casting is needed by the caller and (m > n) */ +#define CLEAR_BITS_M_TO_N(num, m, n) (num & ((~0UL << (m+1)) | ((1UL << n) - 1))) + +#define MPAM_VERSION_1_1 0x11 + +/******************************************************************************* + * MPAM system register bit definitions & constants + ******************************************************************************/ +/* MPAMn_ELx bit definitions */ +#define MPAMn_ELx_PARTID_I_SHIFT 0 +#define MPAMn_ELx_PARTID_D_SHIFT 16 +#define MPAMn_ELx_PMG_I_SHIFT 32 +#define MPAMn_ELx_PMG_D_SHIFT 40 +#define MPAMn_ELx_MPAMEN_SHIFT 63 +#define MPAMn_ELx_PARTID_I_MASK 0xffffULL +#define MPAMn_ELx_PARTID_D_MASK 0xffffULL +#define MPAMn_ELx_PMG_I_MASK 0xffULL +#define MPAMn_ELx_PMG_D_MASK 0xffULL +#define MPAMn_ELx_MPAMEN_MASK 0x1ULL +/* MPAMIDR_EL1 bit definitions */ +#define MPAMIDR_PARTID_MAX_SHIFT 0 +#define MPAMIDR_PMG_MAX_SHIFT 32 +#define MPAMIDR_PARTID_MAX_MASK 0xffff +#define MPAMIDR_PMG_MAX_MASK 0xff + +#define CPOR_BITMAP_DEF_VAL 0xFFFFFFFF + +/* MPAM system registers */ +typedef enum { + MPAMIDR_EL1, + MPAM2_EL2, + MPAM1_EL1 +} MPAM_SYS_REGS; + +#define DEFAULT_PARTID 0ULL +#define DEFAULT_PARTID_MAX 65535 //(2^16 - 1) +#define DEFAULT_PMG 0ULL +#define DEFAULT_PMG_MAX 255 //(2^8 - 1) +#define MPAM_MON_NOT_READY -1 + +void val_mpam_reg_write(MPAM_SYS_REGS reg_id, uint64_t write_data); +uint64_t val_mpam_reg_read(MPAM_SYS_REGS reg_id); +uint64_t AA64ReadMpamidr(void); +uint64_t AA64ReadMpam1(void); +uint64_t AA64ReadMpam2(void); +void AA64IssueDSB(void); +void AA64WriteMpam1(uint64_t write_data); +void AA64WriteMpam2(uint64_t write_data); + +uint64_t val_mpam_get_info(MPAM_INFO_e type, uint32_t msc_index, uint32_t rsrc_index); +uint32_t val_mpam_msc_supports_mon(uint32_t msc_index); +uint32_t val_mpam_msc_supports_mbwumon(uint32_t msc_index); +void val_mpam_memory_configure_mbwumon(uint32_t msc_index); +void val_mpam_memory_mbwumon_enable(uint32_t msc_index); +void val_mpam_memory_mbwumon_disable(uint32_t msc_index); +void val_mpam_memory_configure_ris_sel(uint32_t msc_index, uint32_t rsrc_index); +uint32_t val_mpam_msc_supports_ris(uint32_t msc_index); +uint64_t val_mpam_memory_mbwumon_read_count(uint32_t msc_index); +uint32_t val_mpam_get_msc_count(void); +void val_mpam_memory_mbwumon_reset(uint32_t msc_index); +void *val_mem_alloc_at_address (uint64_t mem_base, uint64_t size); +void val_mem_free_at_address (uint64_t mem_base, uint64_t size); +uint32_t val_mpam_get_csumon_count(uint32_t msc_index); +uint32_t val_mpam_supports_csumon(uint32_t msc_index); +uint64_t val_mpam_memory_get_size(uint32_t msc_index, uint32_t rsrc_index); +uint64_t val_mpam_memory_get_base(uint32_t msc_index, uint32_t rsrc_index); +uint32_t val_mpam_supports_cpor(uint32_t msc_index); +uint64_t val_mpam_msc_get_mscbw(uint32_t msc_index, uint32_t rsrc_index); +uint32_t val_mpam_mbwu_supports_long(uint32_t msc_index); +uint32_t val_mpam_mbwu_supports_lwd(uint32_t msc_index); +uint32_t val_mpam_get_max_partid(uint32_t msc_index); +uint32_t val_mpam_msc_get_version(uint32_t msc_index); +uint32_t val_mpam_get_max_pmg(uint32_t msc_index); +void val_mpam_configure_cpor(uint32_t msc_index, uint16_t partid, uint32_t cpbm_percentage); +uint32_t val_mpam_get_cpbm_width(uint32_t msc_index); +void val_mem_issue_dsb(void); +void val_mpam_configure_csu_mon(uint32_t msc_index, uint16_t partid, uint8_t pmg, uint16_t mon_sel); +void val_mpam_csumon_enable(uint32_t msc_index); +void val_mpam_csumon_disable(uint32_t msc_index); +uint32_t val_mpam_read_csumon(uint32_t msc_index); +uint64_t val_srat_get_prox_domain(uint64_t mem_range_index); + + + +uint32_t mpam001_entry(uint32_t num_pe); +uint32_t mpam002_entry(uint32_t num_pe); +uint32_t mpam003_entry(uint32_t num_pe); +uint32_t mpam004_entry(uint32_t num_pe); +uint32_t mpam005_entry(uint32_t num_pe); +uint32_t mpam006_entry(uint32_t num_pe); + +#endif /*__SBSA_AVS_MPAM_H__ */ diff --git a/val/include/sbsa_avs_mpam_reg.h b/val/include/sbsa_avs_mpam_reg.h new file mode 100644 index 00000000..d91852d3 --- /dev/null +++ b/val/include/sbsa_avs_mpam_reg.h @@ -0,0 +1,167 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#ifndef __MPAM_REG_H__ +#define __MPAM_REG_H__ + +/* Macro can be used to declare MASK and SHIFT for bitfields using MSB and LSB */ +#define BITFIELD_DECL(type, name, msb, lsb) \ + const uint32_t name##_SHIFT = lsb; \ + const type name##_MASK = ((((type)0x1) << (msb - lsb + 1)) - 1); + +/* Macro can be used to read bitfields with name##_MASK and name##_SHIFT + already defined or declared for it*/ +#define BITFIELD_READ(name, val) ((val >> name##_SHIFT) & name##_MASK) + +/* Macro can be used to set bitfields with name##_MASK and name##_SHIFT + already defined or declared for it*/ +#define BITFIELD_SET(name, val) ((val & name##_MASK) << name##_SHIFT) + +/* Macro can be used write a particular bitfield with name##_MASK and name##_SHIFT + already defined or declared for it without affecting other fields*/ +#define BITFIELD_WRITE(reg_val, name, val) \ + ((reg_val & ~(name##_MASK << name##_SHIFT)) | val << name##_SHIFT) + +/******************************************************************************* + * MPAM memory mapped register offsets + ******************************************************************************/ +#define REG_MPAMF_IDR 0x0000 +#define REG_MPAMF_SIDR 0x0008 +#define REG_MPAMF_IIDR 0x0018 +#define REG_MPAMF_AIDR 0x0020 +#define REG_MPAMF_IMPL_IDR 0x0028 +#define REG_MPAMF_CPOR_IDR 0x0030 +#define REG_MPAMF_CCAP_IDR 0x0038 +#define REG_MPAMF_MBW_IDR 0x0040 +#define REG_MPAMF_PRI_IDR 0x0048 +#define REG_PARTID_NRW_IDR 0x0050 +#define REG_MPAMF_MSMON_IDR 0x0080 +#define REG_MPAMF_CSUMON_IDR 0x0088 +#define REG_MPAMF_MBWUMON_IDR 0x0090 + +#define REG_MSMON_CFG_MON_SEL 0x0800 +#define REG_MSMON_CAPT_EVNT 0x0808 +#define REG_MSMON_CFG_CSU_FLT 0x0810 +#define REG_MSMON_CFG_CSU_CTL 0x0818 +#define REG_MSMON_CFG_MBWU_FLT 0x0820 +#define REG_MSMON_CFG_MBWU_CTL 0x0828 +#define REG_MSMON_CSU 0x0840 +#define REG_MSMON_CSU_CAPTURE 0x0848 +#define REG_MSMON_CSU_OFSR 0x0858 +#define REG_MSMON_MBWU 0x0860 +#define REG_MSMON_MBWU_CAPTURE 0x0868 +#define REG_MSMON_MBWU_L 0x0880 +#define REG_MSMON_MBWU_L_CAPTURE 0x0890 + +#define REG_MPAMCFG_PART_SEL 0x0100 +#define REG_MPAMCFG_CPBM 0x1000 + +/* MPAMF_IDR bit definitions */ +BITFIELD_DECL(uint64_t, IDR_PARTID_MAX, 15, 0) +BITFIELD_DECL(uint64_t, IDR_PMG_MAX, 23, 16) +BITFIELD_DECL(uint64_t, IDR_HAS_CCAP_PART, 24, 24) +BITFIELD_DECL(uint64_t, IDR_HAS_CPOR_PART, 25, 25) +BITFIELD_DECL(uint64_t, IDR_HAS_MBW_PART, 26, 26) +BITFIELD_DECL(uint64_t, IDR_HAS_MSMON, 30, 30) +BITFIELD_DECL(uint64_t, IDR_HAS_RIS, 32, 32) + +/* MPAMF_AIDR bit definitions */ +BITFIELD_DECL(uint32_t, AIDR_VERSION, 7, 0) + +/* MPAMF_MSMON_IDR bit definitions */ +BITFIELD_DECL(uint32_t, MSMON_IDR_MSMON_CSU, 16, 16) +BITFIELD_DECL(uint32_t, MSMON_IDR_MSMON_MBWU, 17, 17) +BITFIELD_DECL(uint32_t, MSMON_IDR_HAS_LOCAL_CAPT_EVN, 31, 31) + +/* MPAMF_MBWUMON_IDR bit definitions */ +BITFIELD_DECL(uint32_t, MBWUMON_IDR_NUM_MON, 15, 0) +BITFIELD_DECL(uint32_t, MBWUMON_IDR_SCALE, 20, 16) +BITFIELD_DECL(uint32_t, MBWUMON_IDR_LWD, 29, 29) +BITFIELD_DECL(uint32_t, MBWUMON_IDR_HAS_LONG, 30, 30) +BITFIELD_DECL(uint32_t, MBWUMON_IDR_HAS_CAPTURE, 31, 31) + +/* MSMON_CFG_MBWU_FLT bit definitions */ +BITFIELD_DECL(uint32_t, MBWU_FLT_PARTID, 15, 0) +BITFIELD_DECL(uint32_t, MBWU_FLT_PMG, 23, 16) + +/* MSMON_CFG_MBWU_CTL bit definitions */ +BITFIELD_DECL(uint32_t, MBWU_CTL_TYPE, 7, 0) +BITFIELD_DECL(uint32_t, MBWU_CTL_MATCH_PARTID, 16, 16) +BITFIELD_DECL(uint32_t, MBWU_CTL_MATCH_PMG, 17, 17) +BITFIELD_DECL(uint32_t, MBWU_CTL_SUBTYPE, 23, 20) +BITFIELD_DECL(uint32_t, MBWU_CTL_OFLOW_FRZ, 24, 24) +BITFIELD_DECL(uint32_t, MBWU_CTL_OFLOW_INTR, 25, 25) +BITFIELD_DECL(uint32_t, MBWU_CTL_OFLOW_STATUS, 26, 26) +BITFIELD_DECL(uint32_t, MBWU_CTL_CAPT_RESET, 27, 27) +BITFIELD_DECL(uint32_t, MBWU_CTL_CAPT_EVNT, 30, 28) +BITFIELD_DECL(uint32_t, MBWU_CTL_EN, 31, 31) + +/* MSMON_MBWU bit definitions */ +BITFIELD_DECL(uint32_t, MSMON_MBWU_VALUE, 30, 0) +BITFIELD_DECL(uint32_t, MSMON_MBWU_NRDY, 31, 31) + +/* MSMON_MBWU_CAPTURE bit definitions */ +BITFIELD_DECL(uint32_t, MSMON_MBWU_CAPTURE_VALUE, 30, 0) +BITFIELD_DECL(uint32_t, MSMON_MBWU_CAPTURE_NRDY, 31, 31) + +/* MSMON_MBWU_L bit definitions */ +BITFIELD_DECL(uint64_t, MSMON_MBWU_L_NRDY, 63, 63) +BITFIELD_DECL(uint64_t, MSMON_MBWU_L_44BIT_VALUE, 43, 0) +BITFIELD_DECL(uint64_t, MSMON_MBWU_L_63BIT_VALUE, 62, 0) + +/* MSMON_MBWU_L_CAPTURE bit definitions */ +BITFIELD_DECL(uint64_t, MSMON_MBWU_L_CAPTURE_NRDY, 63, 63) +BITFIELD_DECL(uint64_t, MSMON_MBWU_L_CAPTURE_44BIT_VALUE, 43, 0) +BITFIELD_DECL(uint64_t, MSMON_MBWU_L_CAPTURE_63BIT_VALUE, 62, 0) + +/* MSMON_CFG_MON_SEL bit definitions */ +BITFIELD_DECL(uint32_t, MON_SEL_MON_SEL, 15, 0) +BITFIELD_DECL(uint32_t, MON_SEL_RIS, 27, 24) + +/* MPAMCFG_PART_SEL bit definitions */ +BITFIELD_DECL(uint32_t, PART_SEL_PARTID_SEL, 15, 0) +BITFIELD_DECL(uint32_t, PART_SEL_RIS, 27, 24) + +/* MPAMF_CSUMON_IDR bit definitions */ +BITFIELD_DECL(uint32_t, CSUMON_IDR_NUM_MON, 15, 0) + +/* MPAMF_CPOR_IDR bit definitions */ +BITFIELD_DECL(uint32_t, CPOR_IDR_CPBM_WD, 15, 0) + +/* MSMON_CFG_CSU_CTL bit definitions */ +BITFIELD_DECL(uint32_t, CSU_CTL_TYPE, 7, 0) +BITFIELD_DECL(uint32_t, CSU_CTL_MATCH_PARTID, 16, 16) +BITFIELD_DECL(uint32_t, CSU_CTL_MATCH_PMG, 17, 17) +BITFIELD_DECL(uint32_t, CSU_CTL_SUBTYPE, 22, 20) +BITFIELD_DECL(uint32_t, CSU_CTL_OFLOW_FRZ, 24, 24) +BITFIELD_DECL(uint32_t, CSU_CTL_OFLOW_INTR, 25, 25) +BITFIELD_DECL(uint32_t, CSU_CTL_OFLOW_STATUS, 26, 26) +BITFIELD_DECL(uint32_t, CSU_CTL_CAPT_RESET, 27, 27) +BITFIELD_DECL(uint32_t, CSU_CTL_CAPT_EVNT, 30, 28) +BITFIELD_DECL(uint32_t, CSU_CTL_EN, 31, 31) + +/* MSMON_CFG_CSU_FLT bit definitions */ +BITFIELD_DECL(uint32_t, CSU_FLT_PARTID, 15, 0) +BITFIELD_DECL(uint32_t, CSU_FLT_PMG, 23, 16) + +/* MSMON_CSU bit definitions */ +BITFIELD_DECL(uint32_t, MSMON_CSU_VALUE, 30, 0) +BITFIELD_DECL(uint32_t, MSMON_CSU_NRDY, 31, 31) + + + +#endif /*__MPAM_REG_H__ */ diff --git a/val/include/sbsa_avs_pmu.h b/val/include/sbsa_avs_pmu.h new file mode 100644 index 00000000..7bce4eb6 --- /dev/null +++ b/val/include/sbsa_avs_pmu.h @@ -0,0 +1,55 @@ +/** @file + * Copyright (c) 2022-2023 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#ifndef __SBSA_AVS_PMU_H__ +#define __SBSA_AVS_PMU_H__ + +uint64_t val_pmu_get_info(PMU_INFO_e type, uint32_t node_index); +uint8_t val_pmu_supports_dedicated_cycle_counter(uint32_t node_index); +uint32_t val_pmu_get_monitor_count(uint32_t node_index); +void val_pmu_disable_all_monitors(uint32_t node_index); +void val_pmu_enable_all_monitors(uint32_t node_index); +void val_pmu_reset_all_monitors(uint32_t node_index); +uint32_t val_pmu_get_monitor_group_count(uint32_t node_index); +uint32_t val_pmu_get_max_monitor_size(uint32_t node_index); +uint32_t val_pmu_configure_monitor(uint32_t node_index, PMU_EVENT_TYPE_e event_type, + uint32_t mon_inst); +void val_pmu_enable_monitor(uint32_t node_index, uint32_t mon_inst); +void val_pmu_disable_monitor(uint32_t node_index, uint32_t mon_inst); +uint64_t val_pmu_read_count(uint32_t node_index, uint32_t mon_inst); +uint32_t val_pmu_get_node_index(uint64_t prox_domain); +uint32_t val_pmu_implements_pmscr(uint32_t node_index); +uint32_t val_pmu_is_secure(uint32_t node_index); +uint32_t val_pmu_get_multi_traffic_support_interface(uint64_t *interface_acpiid, + uint32_t *num_traffic_type_support); +uint32_t val_pmu_get_index_acpiid(uint64_t interface_acpiid); +uint32_t val_generate_traffic(uint64_t interface_acpiid, uint32_t pmu_node_index, + uint32_t mon_index, uint32_t eventid); +uint32_t val_pmu_check_monitor_count_value(uint64_t interface_acpiid, uint32_t count_value, + uint32_t eventid); + +uint32_t pmu001_entry(uint32_t num_pe); +uint32_t pmu002_entry(uint32_t num_pe); +uint32_t pmu003_entry(uint32_t num_pe); +uint32_t pmu004_entry(uint32_t num_pe); +uint32_t pmu005_entry(uint32_t num_pe); +uint32_t pmu006_entry(uint32_t num_pe); +uint32_t pmu007_entry(uint32_t num_pe); +uint32_t pmu008_entry(uint32_t num_pe); +uint32_t pmu009_entry(uint32_t num_pe); + +#endif /*__SBSA_AVS_PMU_H__ */ diff --git a/val/include/sbsa_avs_pmu_reg.h b/val/include/sbsa_avs_pmu_reg.h new file mode 100644 index 00000000..ce44c5d8 --- /dev/null +++ b/val/include/sbsa_avs_pmu_reg.h @@ -0,0 +1,130 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#ifndef __PMU_REG_H__ +#define __PMU_REG_H__ + +/* Macro can be used to declare MASK and SHIFT for bitfields using MSB and LSB */ +#define BITFIELD_DECL(type, name, msb, lsb) \ + const uint32_t name##_SHIFT = lsb; \ + const type name##_MASK = ((((type)0x1) << (msb - lsb + 1)) - 1); + +/* Macro can be used to read bitfields with name##_MASK and name##_SHIFT + already defined or declared for it*/ +#define BITFIELD_READ(name, val) ((val >> name##_SHIFT) & name##_MASK) + +/* Macro can be used to set bitfields with name##_MASK and name##_SHIFT + already defined or declared for it*/ +#define BITFIELD_SET(name, val) ((val & name##_MASK) << name##_SHIFT) + +/* Macro can be used write a particular bitfield with name##_MASK and name##_SHIFT + already defined or declared for it without affecting other fields*/ +#define BITFIELD_WRITE(reg_val, name, val) \ + ((reg_val & ~(name##_MASK << name##_SHIFT)) | val << name##_SHIFT) + +/******************************************************************************* + * PMU memory mapped register offsets + ******************************************************************************/ +#define REG_PMEVCNTR 0x0000 +#define REG_PMEVCNTR_L 0x0000 +#define REG_PMEVCNTR_H 0x0004 +#define REG_PMCCNTR 0x003C +#define REG_PMCCNTR_L 0x00F8 +#define REG_PMCCNTR_H 0x00FC +#define REG_PMEVTYPER 0x0400 +#define REG_PMCCFILTR 0x047C +#define REG_PMSVR 0x0600 +#define REG_PMEVFILTR 0x0A00 +#define REG_PMCNTENSET 0x0C00 +#define REG_PMCNTENCLR 0x0C20 +#define REG_PMINTENSET 0x0C40 +#define REG_PMINTENCLR 0x0C60 +#define REG_PMOVSCLR 0x0C80 +#define REG_PMOVSSET 0x0CC0 +#define REG_PMCGR 0x0CE0 +#define REG_PMCFGR 0x0E00 +#define REG_PMCR 0x0E04 +#define REG_PMIIDR 0x0E08 +#define REG_PMCEID 0x0E20 +#define REG_PMSSCR 0x0E30 +#define REG_PMSSRR_L 0x0E38 +#define REG_PMSSRR_H 0x0E3C +#define REG_PMSCR_L 0x0E40 +#define REG_PMSCR_H 0x0E44 +#define REG_PMIRQCR0_L 0x0E80 +#define REG_PMIRQCR0_H 0x0E84 +#define REG_PMIRQCR1 0x0E88 +#define REG_PMIRQCR2 0x0E8C +#define REG_PMIRQSR_L 0x0EF8 +#define REG_PMIRQSR_H 0x0EFC +#define REG_PMDEVAFF_L 0x0FA8 +#define REG_PMDEVAFF_H 0x0FAC +#define REG_PMAUTHSTATUS 0x0FB8 +#define REG_PMDEVARCH 0x0FBC +#define REG_PMDEVID 0x0FC8 +#define REG_PMDEVTYPE 0x0FCC +#define REG_PMPIDR4 0x0FD0 +#define REG_PMPIDR5 0x0FD4 +#define REG_PMPIDR6 0x0FD8 +#define REG_PMPIDR7 0x0FDC +#define REG_PMPIDR0 0x0FE0 +#define REG_PMPIDR1 0x0FE4 +#define REG_PMPIDR2 0x0FE8 +#define REG_PMPIDR3 0x0FEC +#define REG_PMCIDR0 0x0FF0 +#define REG_PMCIDR1 0x0FF4 +#define REG_PMCIDR2 0x0FF8 +#define REG_PMCIDR3 0x0FFC + + + +/* PMCFGR bit definitions */ +BITFIELD_DECL(uint32_t, PMCFGR_N, 7, 0) +BITFIELD_DECL(uint32_t, PMCFGR_SIZE, 13, 8) +BITFIELD_DECL(uint32_t, PMCFGR_CC, 14, 14) +BITFIELD_DECL(uint32_t, PMCFGR_CCD, 15, 15) +BITFIELD_DECL(uint32_t, PMCFGR_EX, 16, 16) +BITFIELD_DECL(uint32_t, PMCFGR_NA, 17, 17) +BITFIELD_DECL(uint32_t, PMCFGR_UEN, 19, 19) +BITFIELD_DECL(uint32_t, PMCFGR_MSI, 20, 20) +BITFIELD_DECL(uint32_t, PMCFGR_FZO, 21, 21) +BITFIELD_DECL(uint32_t, PMCFGR_SS, 22, 22) +BITFIELD_DECL(uint32_t, PMCFGR_TRO, 23, 23) +BITFIELD_DECL(uint32_t, PMCFGR_HDBG, 24, 24) +BITFIELD_DECL(uint32_t, PMCFGR_NCG, 31, 28) + +/* PMCR bit configuration */ +BITFIELD_DECL(uint32_t, PMCR_E, 0, 0) +BITFIELD_DECL(uint32_t, PMCR_P, 1, 1) +BITFIELD_DECL(uint32_t, PMCR_C, 2, 2) +BITFIELD_DECL(uint32_t, PMCR_D, 3, 3) +BITFIELD_DECL(uint32_t, PMCR_X, 4, 4) +BITFIELD_DECL(uint32_t, PMCR_DP, 5, 5) +BITFIELD_DECL(uint32_t, PMCR_NA, 8, 8) +BITFIELD_DECL(uint32_t, PMCR_FZO, 9, 9) +BITFIELD_DECL(uint32_t, PMCR_HDBG, 10, 10) +BITFIELD_DECL(uint32_t, PMCR_TRO, 11, 11) + +/* PMSCR_L bit configuration */ +BITFIELD_DECL(uint32_t, PMSCR_SO, 0, 0) +BITFIELD_DECL(uint32_t, PMSCR_NSRA, 1, 1) +BITFIELD_DECL(uint32_t, PMSCR_NSMSI, 2, 2) +BITFIELD_DECL(uint32_t, PMSCR_MSI_MPAM_NS, 3, 3) +BITFIELD_DECL(uint32_t, PMSCR_NAO, 4, 4) +BITFIELD_DECL(uint32_t, PMSCR_IMPL, 31, 31) + +#endif /*__PMU_REG_H__ */ diff --git a/val/include/sbsa_avs_ras.h b/val/include/sbsa_avs_ras.h new file mode 100644 index 00000000..8fbd662c --- /dev/null +++ b/val/include/sbsa_avs_ras.h @@ -0,0 +1,133 @@ +/** @file + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. +**/ + +#ifndef __SBSA_AVS_RAS_H +#define __SBSA_AVS_RAS_H + + +#define ERR_FR_INJ_MASK (0x3ull << 20) +#define ERR_FR_DUI_MASK (0x3ull << 16) +#define ERR_FR_CEC_MASK (0x7ull << 12) +#define ERR_FR_CFI_MASK (0x3ull << 10) +#define ERR_FR_UI_MASK (0x3ull << 4) + +#define ERR_STATUS_V_MASK (0x1 << 30) +#define ERR_STATUS_AV_MASK (0x1 << 31) +#define ERR_STATUS_UE_MASK (0x1 << 29) +#define ERR_STATUS_CE_MASK (0x3 << 24) +#define ERR_STATUS_DE_MASK (0x1 << 23) +#define ERR_STATUS_PN_MASK (0x1 << 22) +#define ERR_STATUS_CI_MASK (0x1 << 19) +#define ERR_STATUS_CLEAR (0xFFF80000) + +#define ERR_CTLR_CLEAR_MASK 0x3FFD +#define ERR_CTLR_ED_ENABLE 0x1 + +#define ERR_ADDR_AI_SHIFT 61 + +#define ERR_PFGCTL_UC_ENABLE (0x1ull << 1) +#define ERR_PFGCTL_DE_ENABLE (0x1ull << 5) +#define ERR_PFGCTL_CE_NON_ENABLE (0x1ull << 6) +#define ERR_PFGCTL_CI_ENABLE (0x1ull << 8) +#define ERR_PFGCTL_CDNEN_ENABLE (0x1ull << 31) + +#define ERR_FR_OFFSET 0x000 +#define ERR_CTLR_OFFSET 0x008 +#define ERR_STATUS_OFFSET 0x010 +#define ERR_ADDR_OFFSET 0x018 +#define ERR_PFGCTL_OFFSET 0x808 +#define ERR_PFGCDN_OFFSET 0x810 +#define ERR_ERRDEVAFF_OFFSET 0xFA8 + +#define RAS_INTERFACE_SR 0x0 +#define RAS_INTERFACE_MMIO 0x1 + +#define AVS_ALL_1_64BIT 0xFFFFFFFFFFFFFFFF + +typedef enum { + RAS_ERR_FR = 0x1, + RAS_ERR_CTLR, + RAS_ERR_STATUS, + RAS_ERR_ADDR, + RAS_ERR_PFGCDN, + RAS_ERR_PFGCTL, + RAS_ERR_ERRDEVAFF +} RAS_REG_LIST; + +typedef enum { + RAS_INFO_NUM_PE = 0x1, /* Number of PE RAS Node */ + RAS_INFO_NUM_MC, /* Number of MC RAS Node */ + RAS_INFO_NUM_NODES, /* Number of RAS Nodes */ + RAS_INFO_NODE_TYPE, /* RAS Node Type */ + RAS_INFO_PE_RES_TYPE, /* PE Resource Type */ + RAS_INFO_MC_RES_PROX_DOMAIN, /* Memory controller RAS node proximity domain */ + RAS_INFO_INTF_TYPE, /* RAS registers interface type */ + RAS_INFO_ADDR_MODE, /* bitmap based policy for ERRADDR field of error records */ + RAS_INFO_BASE_ADDR, /* Base Address */ + RAS_INFO_NUM_ERR_REC, /* Number of Error Record */ + RAS_INFO_START_INDEX, /* Error Record Start Index */ + RAS_INFO_ERR_REC_IMP, /* Error Record Implemented */ + RAS_INFO_STATUS_REPORT, /* Error Status Reporting */ + RAS_INFO_ERI_ID, /* ERI Interrupt ID */ + RAS_INFO_FHI_ID, /* FHI Interrupt ID */ + RAS_INFO_PFG_SUPPORT, /* Pseudo Fault Inj Support */ + RAS_INFO_NODE_INDEX_FOR_AFF /* RAS Node Index for Affinity */ +} RAS_INFO_TYPE; + +uint32_t val_ras_setup_error(RAS_ERR_IN_t in_param, RAS_ERR_OUT_t *out_param); +uint32_t val_ras_inject_error(RAS_ERR_IN_t in_param, RAS_ERR_OUT_t *out_param); +void val_ras_wait_timeout(uint32_t count); + +uint32_t val_ras_check_err_record(uint32_t node_index, uint32_t error_type); +uint32_t val_ras_check_plat_poison_support(void); + +uint64_t val_ras_reg_read(uint32_t node_index, uint32_t reg, uint32_t err_rec_idx); +void val_ras_reg_write(uint32_t node_index, uint32_t reg, uint64_t write_data); + +uint32_t ras001_entry(uint32_t num_pe); +uint32_t ras002_entry(uint32_t num_pe); +uint32_t ras003_entry(uint32_t num_pe); +uint32_t ras004_entry(uint32_t num_pe); +uint32_t ras005_entry(uint32_t num_pe); +uint32_t ras006_entry(uint32_t num_pe); +uint32_t ras007_entry(uint32_t num_pe); +uint32_t ras008_entry(uint32_t num_pe); +uint32_t ras009_entry(uint32_t num_pe); +uint32_t ras010_entry(uint32_t num_pe); +uint32_t ras011_entry(uint32_t num_pe); +uint32_t ras012_entry(uint32_t num_pe); + +uint64_t AA64ReadErrIdr1(void); +uint64_t AA64ReadErrAddr1(void); +uint64_t AA64ReadErrCtlr1(void); +uint64_t AA64ReadErrFr1(void); +uint64_t AA64ReadErrStatus1(void); +uint64_t AA64ReadErrSelr1(void); +uint64_t AA64ReadErrPfgf1(void); +uint64_t AA64ReadErrPfgctl1(void); +uint64_t AA64ReadErrPfgcdn1(void); + +void AA64WriteErrIdr1(uint64_t write_data); +void AA64WriteErrAddr1(uint64_t write_data); +void AA64WriteErrCtlr1(uint64_t write_data); +void AA64WriteErrStatus1(uint64_t write_data); +void AA64WriteErrSelr1(uint64_t write_data); +void AA64WriteErrPfgf1(uint64_t write_data); +void AA64WriteErrPfgctl1(uint64_t write_data); +void AA64WriteErrPfgcdn1(uint64_t write_data); + +#endif // __SBSA_AVS_RAS_H diff --git a/val/src/AArch64/MpamSupport.s b/val/src/AArch64/MpamSupport.s new file mode 100644 index 00000000..17b93837 --- /dev/null +++ b/val/src/AArch64/MpamSupport.s @@ -0,0 +1,54 @@ +#/** @file +# Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. +# SPDX-License-Identifier : Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#**/ + +.text +.align 2 + +GCC_ASM_EXPORT(AA64ReadMpam1) +GCC_ASM_EXPORT(AA64WriteMpam1) +GCC_ASM_EXPORT(AA64ReadMpam2) +GCC_ASM_EXPORT(AA64WriteMpam2) +GCC_ASM_EXPORT(AA64ReadMpamidr) +GCC_ASM_EXPORT(AA64IssueDSB) + + +ASM_PFX(AA64ReadMpam1): + mrs x0, mpam1_el1 + ret + +ASM_PFX(AA64WriteMpam1): + msr mpam1_el1, x0 + ret + +ASM_PFX(AA64ReadMpam2): + mrs x0, mpam2_el2 + ret + +ASM_PFX(AA64WriteMpam2): + msr mpam2_el2, x0 + ret + +ASM_PFX(AA64ReadMpamidr): + mrs x0, mpamidr_el1 + ret + +ASM_PFX(AA64IssueDSB): + dsb sy + ret + +ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/val/src/AArch64/RasSupport.S b/val/src/AArch64/RasSupport.S new file mode 100644 index 00000000..12501d07 --- /dev/null +++ b/val/src/AArch64/RasSupport.S @@ -0,0 +1,109 @@ +#/** @file +# Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. +# SPDX-License-Identifier : Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#**/ + +.text +.align 2 + +GCC_ASM_EXPORT(AA64ReadErrIdr1) +GCC_ASM_EXPORT(AA64WriteErrIdr1) +GCC_ASM_EXPORT(AA64ReadErrAddr1) +GCC_ASM_EXPORT(AA64WriteErrAddr1) +GCC_ASM_EXPORT(AA64ReadErrCtlr1) +GCC_ASM_EXPORT(AA64WriteErrCtlr1) +GCC_ASM_EXPORT(AA64ReadErrFr1) +GCC_ASM_EXPORT(AA64ReadErrStatus1) +GCC_ASM_EXPORT(AA64WriteErrStatus1) +GCC_ASM_EXPORT(AA64ReadErrSelr1) +GCC_ASM_EXPORT(AA64WriteErrSelr1) +GCC_ASM_EXPORT(AA64ReadErrPfgf1) +GCC_ASM_EXPORT(AA64ReadErrPfgctl1) +GCC_ASM_EXPORT(AA64ReadErrPfgcdn1) +GCC_ASM_EXPORT(AA64WriteErrPfgf1) +GCC_ASM_EXPORT(AA64WriteErrPfgctl1) +GCC_ASM_EXPORT(AA64WriteErrPfgcdn1) + + +ASM_PFX(AA64ReadErrIdr1): + mrs x0, erridr_el1 + ret + +ASM_PFX(AA64WriteErrIdr1): + msr erridr_el1, x0 + ret + +ASM_PFX(AA64ReadErrAddr1): + mrs x0, erxaddr_el1 + ret + +ASM_PFX(AA64WriteErrAddr1): + msr erxaddr_el1, x0 + ret + +ASM_PFX(AA64ReadErrCtlr1): + mrs x0, erxctlr_el1 + ret + +ASM_PFX(AA64WriteErrCtlr1): + msr erxctlr_el1, x0 + ret + +ASM_PFX(AA64ReadErrFr1): + mrs x0, erxfr_el1 + ret + +ASM_PFX(AA64ReadErrStatus1): + mrs x0, erxstatus_el1 + ret + +ASM_PFX(AA64WriteErrStatus1): + msr erxstatus_el1, x0 + ret + +ASM_PFX(AA64ReadErrSelr1): + mrs x0, errselr_el1 + ret + +ASM_PFX(AA64WriteErrSelr1): + msr errselr_el1, x0 + ret + +ASM_PFX(AA64ReadErrPfgf1): + mrs x0, erxpfgf_el1 + ret + +ASM_PFX(AA64WriteErrPfgf1): + msr erxpfgf_el1, x0 + ret + +ASM_PFX(AA64ReadErrPfgctl1): + mrs x0, erxpfgctl_el1 + ret + +ASM_PFX(AA64WriteErrPfgctl1): + msr erxpfgctl_el1, x0 + ret + +ASM_PFX(AA64ReadErrPfgcdn1): + mrs x0, erxpfgcdn_el1 + ret + +ASM_PFX(AA64WriteErrPfgcdn1): + msr erxpfgcdn_el1, x0 + ret + +ASM_FUNCTION_REMOVE_IF_UNREFERENCED diff --git a/val/src/avs_mmu.c b/val/src/avs_mmu.c new file mode 100644 index 00000000..0d094148 --- /dev/null +++ b/val/src/avs_mmu.c @@ -0,0 +1,238 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "include/sbsa_avs_val.h" +#include "include/sbsa_avs_common.h" +#include "include/sbsa_avs_mmu.h" +#include "include/sbsa_avs_pgt.h" +#include "include/sbsa_avs_pe.h" +#include "include/sbsa_avs_memory.h" + +static uint32_t log2_func(uint64_t size); + +/** + @brief This API will check whether inputted base address is already + mapped in the translation table or not. + + @param addr - address to be checked. + + @return 0 - if mmu entry is present, 1 otherwise. +**/ +uint32_t +val_mmu_check_for_entry(uint64_t addr) +{ + PE_TCR_BF tcr; + uint64_t ttbr, ttable_entry; + uint64_t tt_base_phys, *tt_base_virt; + uint32_t ias, index, num_pgt_levels, this_level; + uint32_t page_size_log2, bits_per_level, page_size; + uint32_t bits_at_this_level, bits_remaining; + + /* Get translation attributes from TCR and translation table base from TTBR + TTBR0 is used since we are accessing lower address region */ + if (val_pe_reg_read_tcr(0 /*for TTBR0*/, &tcr)) { + val_print(AVS_PRINT_ERR, "\n Failed to fetch TCR", 0); + return 1; + } + + if (val_pe_reg_read_ttbr(0 /*TTBR0*/, &ttbr)) { + val_print(AVS_PRINT_ERR, "\n Failed to fetch TTBR0", 0); + return 1; + } + + /* obtain page size */ + page_size = val_memory_page_size(); + /* number of bits required to index byte location inside the page */ + page_size_log2 = log2_func(page_size); + /* calculate input addr size */ + ias = 64 - tcr.tsz; + /* calculate bits resolved per level for all granule sizes */ + bits_per_level = page_size_log2 - 3; + /* calculate max num of translation levels possible */ + num_pgt_levels = (ias - page_size_log2 + bits_per_level - 1)/bits_per_level; + /* start translation from lowest level */ + this_level = PGT_LEVEL_MAX - num_pgt_levels; + /* bits to translate after first translation */ + bits_remaining = (num_pgt_levels - 1) * bits_per_level + page_size_log2; + /* bits translated at current level */ + bits_at_this_level = ias - bits_remaining; + /* address to first translation table comes from TTBR0 register */ + tt_base_phys = ttbr & AARCH64_TTBR_ADDR_MASK; + + while (this_level < PGT_LEVEL_MAX) { + /* translation starts from most siginificant bits of VA */ + index = (addr >> bits_remaining) & ((0x1u << bits_at_this_level) - 1); + tt_base_virt = (uint64_t *)val_memory_phys_to_virt(tt_base_phys); + /* index the translation table and read the entry */ + ttable_entry = tt_base_virt[index]; + + val_print(AVS_PRINT_INFO, "\n Translation table level = %d", this_level); + val_print(AVS_PRINT_INFO, "\n Table base address = 0x%llx", + (uint64_t)tt_base_virt); + val_print(AVS_PRINT_INFO, "\n Table entry index = %d", index); + val_print(AVS_PRINT_INFO, "\n Table entry = 0x%llx", + ttable_entry); + val_print(AVS_PRINT_INFO, "\n VA bits remaining to be resolve = %d", bits_remaining); + + /* check whether the table entry is invalid */ + if (IS_PGT_ENTRY_INVALID(ttable_entry)) { + val_print(AVS_PRINT_DEBUG, "\n VA not mapped in translation table", 0); + return 1; + } + + /* As per Arm ARM, entry of type "table descriptor" is only + valid at translation level 0 */ + if (this_level == 0 && !IS_PGT_ENTRY_TABLE(ttable_entry)) { + val_print(AVS_PRINT_DEBUG, + "\n VA not mapped correctly in translation table", 0); + return 1; + } + + if (this_level == 3) { + /* at level 3 table entry should be of type "page descriptor" with + ttable_entry[1:0] bits = b11 */ + if (!IS_PGT_ENTRY_PAGE(ttable_entry)) { + val_print(AVS_PRINT_DEBUG, + "\n VA not mapped correctly in translation table", 0); + return 1; + } + else { + val_print(AVS_PRINT_DEBUG, "\n VA translation successful", 0); + return 0; + } + } + + /* check whether table walk hit a block descriptor entry + Note : level 0 table entry can't describe a page or a block + level 3 can only have entry of type page descriptor + (Refer Arm ARM for more info) */ + if (IS_PGT_ENTRY_BLOCK(ttable_entry) && this_level != 0) { + val_print(AVS_PRINT_DEBUG, "\n VA translation successful", 0); + return 0; + } + + /* point to next translation table if table walk still not hit + a page or a block descriptor entry */ + tt_base_phys = ttable_entry & (((0x1ull << (ias - page_size_log2)) - 1) << page_size_log2); + + /* update level and remaining VA bits to resolve */ + ++this_level; + bits_remaining -= bits_at_this_level; + bits_at_this_level = bits_per_level; + } + /* execution should don't reach here */ + return 1; +} + +/** + @brief This API adds translation table entry for memory region specified. + Note : This API should only be used to map memory of type Device. + + @param base_addr - base address of the memory. + @param size - size of the memory region. + + @return 0 - if SUCCESS, 1 otherwise. +**/ +uint32_t +val_mmu_add_entry(uint64_t base_addr, uint64_t size) +{ + pgt_descriptor_t pgt_desc; + memory_region_descriptor_t mem_desc; + uint64_t ttbr; + const uint32_t oas_bit_arr[7] = {32, 36, 40, 42, 44, 48, 52}; /* Physical address sizes */ + + /* init descriptors */ + val_memory_set(&mem_desc, sizeof(mem_desc), 0); + val_memory_set(&pgt_desc, sizeof(pgt_desc), 0); + + /* Get translation attributes from TCR and translation table base from TTBR */ + if (val_pe_reg_read_tcr(0 /*for TTBR0*/, &pgt_desc.tcr)) { + val_print(AVS_PRINT_ERR, "\n Failed to fetch TCR", 0); + return 1; + } + if (val_pe_reg_read_ttbr(0 /*TTBR0*/, &ttbr)) { + val_print(AVS_PRINT_ERR, "\n Failed to fetch TTBR0", 0); + return 1; + } + + /* update pgt descriptor structure with translation table base from TTBR0 */ + pgt_desc.pgt_base = (ttbr & AARCH64_TTBR_ADDR_MASK); + /* only stage one translation */ + pgt_desc.stage = PGT_STAGE1; + + /* realise OAS and IAS from TCR register */ + pgt_desc.oas = oas_bit_arr[pgt_desc.tcr.ps]; + pgt_desc.ias = 64 - pgt_desc.tcr.tsz; + val_print(AVS_PRINT_DEBUG, "\n Input addr size in bits (ias) = %d", pgt_desc.ias); + val_print(AVS_PRINT_DEBUG, "\n Output addr size in bits (oas) = %d\n", pgt_desc.oas); + + /* populate mem descriptor structure with addr region to be mapped and attributes */ + mem_desc.virtual_address = base_addr; + mem_desc.physical_address = base_addr; + mem_desc.length = size; + mem_desc.attributes = ATTR_DEVICE_nGnRnE | (1ull << MEM_ATTR_AF_SHIFT); + + /* update translation table entry(s) for addr region defined by memory descriptor structure */ + if (val_pgt_create(&mem_desc, &pgt_desc)) { + val_print(AVS_PRINT_ERR, " Failed to create MMU translation entry(s)\n", 0); + return 1; + } + return 0; +} + +/** + @brief This API adds translation table entry for memory region specified + if the region is not yet mapped. + Note : This API should only be used to map memory of type Device. + + @param None + + @return 0 if Success, 1 otherwise. +**/ +uint32_t val_mmu_update_entry(uint64_t address, uint32_t size) +{ + + /* If entry is already present return success */ + if (!val_mmu_check_for_entry(address)) { + val_print(AVS_PRINT_DEBUG, "\n Address is already mapped", 0); + return 0; + } + + /* Add the entry and return status */ + return val_mmu_add_entry(address, size); +} + +/** + @brief This is local function is used to get log base 2 of input value. + + @param value - input value + + @return result +**/ +static uint32_t log2_func(uint64_t value) +{ + int bit = 0; + + while (value != 0) + { + if (value & 1) + return bit; + value >>= 1; + ++bit; + } + return 0; +} diff --git a/val/src/avs_mpam.c b/val/src/avs_mpam.c new file mode 100644 index 00000000..c379697f --- /dev/null +++ b/val/src/avs_mpam.c @@ -0,0 +1,1073 @@ +/** @file + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "include/sbsa_avs_val.h" +#include "include/sbsa_avs_common.h" +#include "include/sbsa_avs_mpam.h" +#include "include/sbsa_avs_mpam_reg.h" + +static MPAM_INFO_TABLE *g_mpam_info_table; +static SRAT_INFO_TABLE *g_srat_info_table; +static HMAT_INFO_TABLE *g_hmat_info_table; + +/** + @brief This API executes all the MPAM tests sequentially + 1. Caller - Application layer. + 2. Prerequisite - val_mpam_create_info_table + @param level - level of compliance being tested for. + @param num_pe - the number of PE to run these tests on. + @return Consolidated status of all the tests run. +**/ +uint32_t +val_mpam_execute_tests(uint32_t level, uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL, i; + uint32_t msc_node_cnt; + + for (i = 0; i < MAX_TEST_SKIP_NUM; i++) { + if (g_skip_test_num[i] == AVS_MPAM_TEST_NUM_BASE) { + val_print(AVS_PRINT_TEST, " USER Override - Skipping all MPAM tests \n", 0); + return AVS_STATUS_SKIP; + } + } + + if (g_single_module != SINGLE_MODULE_SENTINEL && g_single_module != AVS_MPAM_TEST_NUM_BASE && + (g_single_test == SINGLE_MODULE_SENTINEL || + (g_single_test - AVS_MPAM_TEST_NUM_BASE > 100 || + g_single_test - AVS_MPAM_TEST_NUM_BASE < 0))) { + val_print(AVS_PRINT_TEST, " USER Override - Skipping all MPAM tests \n", 0); + val_print(AVS_PRINT_TEST, " (Running only a single module)\n", 0); + return AVS_STATUS_SKIP; + } + + /* check if PE supports MPAM extension, else skip all MPAM tests */ + if (val_pe_feat_check(PE_FEAT_MPAM)) { + val_print(AVS_PRINT_TEST, + "\n PE MPAM extension unimplemented. Skipping all MPAM tests\n", 0); + return AVS_STATUS_SKIP; + } + + g_curr_module = 1 << MPAM_MODULE; + + /* run tests which don't check MPAM MSCs */ + if (g_sbsa_level > 6) + status = mpam001_entry(num_pe); + + msc_node_cnt = val_mpam_get_msc_count(); + if (msc_node_cnt == 0) { + val_print(AVS_PRINT_TEST, + "\n MPAM MSCs not found. Skipping remaining MPAM tests\n", 0); + return AVS_STATUS_SKIP; + } + + if (g_sbsa_level > 6) { + status |= mpam002_entry(num_pe); + status |= mpam003_entry(num_pe); + status |= mpam004_entry(num_pe); + status |= mpam005_entry(num_pe); + status |= mpam006_entry(num_pe); + val_print_test_end(status, "MPAM"); + } + + return status; +} + +/** + @brief This API provides a 'C' interface to call MPAM system register reads + 1. Caller - Test Suite + 2. Prerequisite - None + @param reg_id - the system register index for which data is returned. + @return the value read from the system register. +**/ +uint64_t +val_mpam_reg_read(MPAM_SYS_REGS reg_id) +{ + switch (reg_id) { + case MPAMIDR_EL1: + return AA64ReadMpamidr(); + case MPAM2_EL2: + return AA64ReadMpam2(); + case MPAM1_EL1: + return AA64ReadMpam1(); + default: + val_report_status(val_pe_get_index_mpid(val_pe_get_mpid()), + RESULT_FAIL(g_sbsa_level, 0, STATUS_SYS_REG_ACCESS_FAIL), NULL); + } + + return 0; +} + +/** + @brief This API provides a 'C' interface to call MPAM system register writes + 1. Caller - Test Suite + 2. Prerequisite - None + @param reg_id - the system register index for which data is written + @param write_data - the 64-bit data to write to the system register + @return None +**/ +void +val_mpam_reg_write(MPAM_SYS_REGS reg_id, uint64_t write_data) +{ + switch (reg_id) { + case MPAM2_EL2: + AA64WriteMpam2(write_data); + break; + case MPAM1_EL1: + AA64WriteMpam1(write_data); + break; + default: + val_report_status(val_pe_get_index_mpid(val_pe_get_mpid()), + RESULT_FAIL(g_sbsa_level, 0, STATUS_SYS_REG_ACCESS_FAIL), NULL); + } + + return; +} + +/** + @brief This API returns requested MSC or resource info. + + @param type - the type of information being requested. + @param msc_index - index of the MSC node in the MPAM info table. + @param rsrc_index - index of the resource node in the MPAM MSC node if resource + related info is requested, set this parameter 0 otherwise. + + @return requested data if found, otherwise MPAM_INVALID_INFO. +**/ +uint64_t +val_mpam_get_info(MPAM_INFO_e type, uint32_t msc_index, uint32_t rsrc_index) +{ + uint32_t i = 0; + MPAM_MSC_NODE *msc_entry; + + if (g_mpam_info_table == NULL) { + val_print(AVS_PRINT_WARN, "\n MPAM info table not found", 0); + return MPAM_INVALID_INFO; + } + + if (msc_index > g_mpam_info_table->msc_count) { + val_print(AVS_PRINT_ERR, "Invalid MSC index = 0x%lx ", msc_index); + return 0; + } + + /* Walk the MPAM info table and return requested info */ + msc_entry = &g_mpam_info_table->msc_node[0]; + for (i = 0; i < g_mpam_info_table->msc_count; i++, msc_entry = MPAM_NEXT_MSC(msc_entry)) { + if (msc_index == i) { + if (rsrc_index > msc_entry->rsrc_count - 1) { + val_print(AVS_PRINT_ERR, + "\n Invalid MSC resource index = 0x%lx for", rsrc_index); + val_print(AVS_PRINT_ERR, "MSC index = 0x%lx ", msc_index); + return MPAM_INVALID_INFO; + } + switch (type) { + case MPAM_MSC_RSRC_COUNT: + return msc_entry->rsrc_count; + case MPAM_MSC_RSRC_RIS: + return msc_entry->rsrc_node[rsrc_index].ris_index; + case MPAM_MSC_RSRC_TYPE: + return msc_entry->rsrc_node[rsrc_index].locator_type; + case MPAM_MSC_RSRC_DESC1: + return msc_entry->rsrc_node[rsrc_index].descriptor1; + case MPAM_MSC_BASE_ADDR: + return msc_entry->msc_base_addr; + case MPAM_MSC_ADDR_LEN: + return msc_entry->msc_addr_len; + case MPAM_MSC_NRDY: + return msc_entry->max_nrdy; + default: + val_print(AVS_PRINT_ERR, + "\n This MPAM info option for type %d is not supported", type); + return MPAM_INVALID_INFO; + } + } + } + return MPAM_INVALID_INFO; +} + +/** + @brief This API returns requested Base address or Address length or num of mem ranges info. + 1. Caller - Test Suite + 2. Prerequisite - val_srat_create_info_table + @param type - the type of information being requested. + @param data - proximity domain or uid. + + @return requested data if found, otherwise SRAT_INVALID_INFO. +**/ +uint64_t +val_srat_get_info(SRAT_INFO_e type, uint64_t data) +{ + uint32_t i = 0; + + if (g_srat_info_table == NULL) { + val_print(AVS_PRINT_WARN, "\n SRAT info table not found", 0); + return SRAT_INVALID_INFO; + } + + switch (type) { + case SRAT_MEM_NUM_MEM_RANGE: + return g_srat_info_table->num_of_mem_ranges; + case SRAT_MEM_BASE_ADDR: + for (i = 0; i < g_srat_info_table->num_of_srat_entries; i++) { + if (g_srat_info_table->srat_info[i].node_type == SRAT_NODE_MEM_AFF) { + if (data == g_srat_info_table->srat_info[i].node_data.mem_aff.prox_domain) { + return g_srat_info_table->srat_info[i].node_data.mem_aff.addr_base; + } + } + } + break; + case SRAT_MEM_ADDR_LEN: + for (i = 0; i < g_srat_info_table->num_of_srat_entries; i++) { + if (g_srat_info_table->srat_info[i].node_type == SRAT_NODE_MEM_AFF) { + if (data == g_srat_info_table->srat_info[i].node_data.mem_aff.prox_domain) { + return g_srat_info_table->srat_info[i].node_data.mem_aff.addr_len; + } + } + } + break; + case SRAT_GICC_PROX_DOMAIN: + for (i = 0; i < g_srat_info_table->num_of_srat_entries; i++) { + if (g_srat_info_table->srat_info[i].node_type == SRAT_NODE_GICC_AFF) { + if (data == g_srat_info_table->srat_info[i].node_data.gicc_aff.proc_uid) { + return g_srat_info_table->srat_info[i].node_data.gicc_aff.prox_domain; + } + } + } + break; + case SRAT_GICC_PROC_UID: + for (i = 0; i < g_srat_info_table->num_of_srat_entries; i++) { + if (g_srat_info_table->srat_info[i].node_type == SRAT_NODE_GICC_AFF) { + if (data == g_srat_info_table->srat_info[i].node_data.gicc_aff.prox_domain) { + return g_srat_info_table->srat_info[i].node_data.gicc_aff.proc_uid; + } + } + } + return SRAT_INVALID_INFO; + break; + case SRAT_GICC_REMOTE_PROX_DOMAIN: + for (i = 0; i < g_srat_info_table->num_of_srat_entries; i++) { + if (g_srat_info_table->srat_info[i].node_type == SRAT_NODE_GICC_AFF) { + if (g_srat_info_table->srat_info[i].node_data.gicc_aff.prox_domain != data) { + return g_srat_info_table->srat_info[i].node_data.gicc_aff.prox_domain; + } + } + } + return SRAT_INVALID_INFO; + break; + default: + val_print(AVS_PRINT_ERR, + "\n This SRAT info option for type %d is not supported", type); + break; + } + return SRAT_INVALID_INFO; +} + +/** + @brief This API returns proximity domain mapped to the memory range. + + @param none + @return proximity domain +**/ +uint64_t +val_srat_get_prox_domain(uint64_t mem_range_index) +{ + uint32_t i = 0; + + if (g_srat_info_table == NULL) { + val_print(AVS_PRINT_WARN, "\n SRAT info table not found", 0); + return SRAT_INVALID_INFO; + } + + if (mem_range_index > g_srat_info_table->num_of_mem_ranges) { + val_print(AVS_PRINT_WARN, "\n Invalid index", 0); + return SRAT_INVALID_INFO; + } + + for (i = 0; i < g_srat_info_table->num_of_mem_ranges; i++) { + if (g_srat_info_table->srat_info[i].node_type == SRAT_NODE_MEM_AFF) { + if (mem_range_index == 0) + return g_srat_info_table->srat_info[i].node_data.mem_aff.prox_domain; + else + mem_range_index--; + } + } + return SRAT_INVALID_INFO; +} + +/** + * @brief This API returns numbers of MPAM MSC nodes in the system. + * + * @param None + * @return number of MPAM MSC nodes + */ +uint32_t +val_mpam_get_msc_count(void) +{ + if (g_mpam_info_table == NULL) { + val_print(AVS_PRINT_WARN, "\n MPAM info table not found", 0); + return 0; + } + else + return g_mpam_info_table->msc_count; +} + +/** + @brief This API returns MSC MAPAM version + @param msc_index - index of the MSC node in the MPAM info table. + @return msc mpam version. +**/ +uint32_t +val_mpam_msc_get_version(uint32_t msc_index) +{ + addr_t base; + + base = val_mpam_get_info(MPAM_MSC_BASE_ADDR, msc_index, 0); + return BITFIELD_READ(AIDR_VERSION, val_mmio_read(base + REG_MPAMF_AIDR)); +} + +/** + @brief This API checks whether resource monitoring is supported by the MPAM MSC. + @param msc_index - index of the MSC node in the MPAM info table. + @return 1 if supported 0 otherwise. +**/ +uint32_t +val_mpam_msc_supports_mon(uint32_t msc_index) +{ + addr_t base; + + base = val_mpam_get_info(MPAM_MSC_BASE_ADDR, msc_index, 0); + return BITFIELD_READ(IDR_HAS_MSMON, val_mmio_read(base + REG_MPAMF_IDR)); +} + +/** + @brief This API checks whether MSC has cache portion partitioning. + @param msc_index - index of the MSC node in the MPAM info table. + @return 1 if supported 0 otherwise. +**/ +uint32_t +val_mpam_supports_cpor(uint32_t msc_index) +{ + addr_t base; + + base = val_mpam_get_info(MPAM_MSC_BASE_ADDR, msc_index, 0); + return BITFIELD_READ(IDR_HAS_CPOR_PART, val_mmio_read(base + REG_MPAMF_IDR)); +} + +/** + @brief This API checks whether resource instance selection (RIS) implemented + for the MSC. + @param msc_index - index of the MSC node in the MPAM info table. + @return 1 if supported 0 otherwise. +**/ +uint32_t +val_mpam_msc_supports_ris(uint32_t msc_index) +{ + addr_t base; + + base = val_mpam_get_info(MPAM_MSC_BASE_ADDR, msc_index, 0); + return BITFIELD_READ(IDR_HAS_RIS, val_mmio_read(base + REG_MPAMF_IDR)); +} + +/** + @brief This API checks if the MSC supports Memory Bandwidth Usage Monitor (MBWU) + Prerequisite - If MSC supports RIS, Resource instance should be + selected using val_mpam_memory_configure_ris_sel + prior calling this API. + @param msc_index - index of the MSC node in the MPAM info table. + @return 1 if supported 0 otherwise. +**/ +uint32_t +val_mpam_msc_supports_mbwumon(uint32_t msc_index) +{ + addr_t base; + + base = val_mpam_get_info(MPAM_MSC_BASE_ADDR, msc_index, 0); + if (val_mpam_msc_supports_mon(msc_index)) + return BITFIELD_READ(MSMON_IDR_MSMON_MBWU, val_mmio_read(base + REG_MPAMF_MSMON_IDR)); + else + return 0; +} + +/** + @brief This API returns max bandwidth supported by a memory interface with mbwu attached + @param msc_index - index of the MSC node in the MPAM info table. + @return 1 if supported 0 otherwise. +**/ +uint64_t +val_mpam_msc_get_mscbw(uint32_t msc_index, uint32_t rsrc_index) +{ + uint64_t prox_domain; + uint32_t i = 0; + + prox_domain = val_mpam_get_info(MPAM_MSC_RSRC_DESC1, msc_index, rsrc_index); + + if (g_hmat_info_table == NULL) { + val_print(AVS_PRINT_WARN, "\n HMAT info table not found", 0); + return HMAT_INVALID_INFO; + } + + for (i = 0; i < g_hmat_info_table->num_of_mem_prox_domain ; i++) { + if (g_hmat_info_table->bw_info[i].mem_prox_domain == prox_domain) { + return (g_hmat_info_table->bw_info[i].write_bw + + g_hmat_info_table->bw_info[i].read_bw); + } + } + val_print(AVS_PRINT_WARN, "\n Invalid Proximity domain 0x%lx", prox_domain); + return HMAT_INVALID_INFO; +} + +/** + @brief This API checks if the MBWU supports 44-bit ot 64-bit counter + @param msc_index - index of the MSC node in the MPAM info table. + @return 1 if supported 0 otherwise. +**/ +uint32_t +val_mpam_mbwu_supports_long(uint32_t msc_index) +{ + addr_t base; + + base = val_mpam_get_info(MPAM_MSC_BASE_ADDR, msc_index, 0); + return BITFIELD_READ(MBWUMON_IDR_HAS_LONG, val_mmio_read(base + REG_MPAMF_MBWUMON_IDR)); +} + +/** + @brief This API checks if the MBWU supports 64 bit counter + @param msc_index - index of the MSC node in the MPAM info table. + @return 1 if supported 0 otherwise. +**/ +uint32_t +val_mpam_mbwu_supports_lwd(uint32_t msc_index) +{ + addr_t base; + + base = val_mpam_get_info(MPAM_MSC_BASE_ADDR, msc_index, 0); + return BITFIELD_READ(MBWUMON_IDR_LWD, val_mmio_read(base + REG_MPAMF_MBWUMON_IDR)); +} + +/** + @brief This API checks if the MSC supports Cache Usage Monitor (CSU) + Prerequisite - If MSC supports RIS, Resource instance should be + selected using val_mpam_memory_configure_ris_sel + prior calling this API. + @param msc_index - index of the MSC node in the MPAM info table. + @return 1 if supported 0 otherwise. +**/ +uint32_t +val_mpam_supports_csumon(uint32_t msc_index) +{ + addr_t base; + + base = val_mpam_get_info(MPAM_MSC_BASE_ADDR, msc_index, 0); + if (val_mpam_msc_supports_mon(msc_index)) + return BITFIELD_READ(MSMON_IDR_MSMON_CSU, val_mmio_read(base + REG_MPAMF_MSMON_IDR)); + else + return 0; +} + +/** + @brief This API checks if the MSC supports Cache Usage Monitor (CSU) + Prerequisite - If MSC supports RIS, Resource instance should be + selected using val_mpam_memory_configure_ris_sel + prior calling this API. + @param msc_index - index of the MSC node in the MPAM info table. + @return 1 if supported 0 otherwise. +**/ +uint32_t +val_mpam_get_csumon_count(uint32_t msc_index) +{ + addr_t base; + + base = val_mpam_get_info(MPAM_MSC_BASE_ADDR, msc_index, 0); + return BITFIELD_READ(CSUMON_IDR_NUM_MON, val_mmio_read(base + REG_MPAMF_CSUMON_IDR)); +} + +/** + @brief This API configures MPAM MBWU selection registers. + Prerequisite - val_mpam_msc_supports_ris + This API should only be used for MSC supporting RIS. + + @param msc_index - index of the MSC node in the MPAM info table. + @param rsrc_index - index of the resource node in the MPAM MSC node. + + @return null +**/ +void +val_mpam_memory_configure_ris_sel(uint32_t msc_index, uint32_t rsrc_index) +{ + addr_t base; + uint32_t data; + uint8_t ris_index; + + base = val_mpam_get_info(MPAM_MSC_BASE_ADDR, msc_index, 0); + ris_index = val_mpam_get_info(MPAM_MSC_RSRC_RIS, msc_index, rsrc_index); + + /*configure MSMON_CFG_MON_SEL.RIS field and write MSMON_CFG_MON_SEL.MON_SEL + field to be 0 */ + data = BITFIELD_SET(MON_SEL_RIS, ris_index); + val_mmio_write(base + REG_MSMON_CFG_MON_SEL, data); + + /* configure MPAMCFG_PART_SEL.RIS field and write MPAMCFG_PART_SEL. + PARTID_SEL field to DEFAULT PARTID*/ + data = BITFIELD_SET(PART_SEL_RIS, ris_index) + | BITFIELD_SET(PART_SEL_PARTID_SEL, DEFAULT_PARTID); + val_mmio_write(base + REG_MPAMCFG_PART_SEL, data); +} + +/** + @brief This API configures the bandwidth usage monitor. + Prerequisite - If MSC supports RIS, Resource instance should be + selected using val_mpam_memory_configure_ris_sel + prior calling this API. + - MSC should support MBWU monitoring, can be checked + using val_mpam_msc_supports_mbwumon API. + + @param msc_index - index of the MSC node in the MPAM info table. + @return None +**/ +void +val_mpam_memory_configure_mbwumon(uint32_t msc_index) +{ + uint32_t data = 0; + addr_t base; + + base = val_mpam_get_info(MPAM_MSC_BASE_ADDR, msc_index, 0); + + /* select monitor instance zero by writing zero to MSMON_CFG_MON_SEL.MON_SEL */ + data = val_mmio_read(base + REG_MSMON_CFG_MON_SEL); + /* retaining other configured fields e.g, RIS index if supported */ + data = BITFIELD_WRITE(data, MON_SEL_MON_SEL, 0); + val_mmio_write(base + REG_MSMON_CFG_MON_SEL, data); + + /* disable monitor instance before configuration */ + val_mpam_memory_mbwumon_disable(msc_index); + + /* configure monitor ctrl reg for default partid and default pmg */ + data = BITFIELD_SET(MBWU_CTL_MATCH_PARTID, 1) | BITFIELD_SET(MBWU_CTL_MATCH_PMG, 1); + val_mmio_write(base + REG_MSMON_CFG_MBWU_CTL, data); + + /* configure monitor filter reg for default partid and default pmg */ + data = BITFIELD_SET(MBWU_FLT_PARTID, DEFAULT_PARTID) | BITFIELD_SET(MBWU_FLT_PMG, DEFAULT_PMG); + val_mmio_write(base + REG_MSMON_CFG_MBWU_FLT, data); + + /* reset the MBWU monitor count */ + val_mpam_memory_mbwumon_reset(msc_index); +} + +/** + @brief This API enables the bandwidth usage monitor. + Prerequisite - If MSC supports RIS, Resource instance should be + selected using val_mpam_memory_configure_ris_sel + prior calling this API. + - MSC should support MBWU monitoring, can be checked + using val_mpam_msc_supports_mbwumon API.. + + @param msc_index - index of the MSC node in the MPAM info table. +**/ +void +val_mpam_memory_mbwumon_enable(uint32_t msc_index) +{ + addr_t base; + + base = val_mpam_get_info(MPAM_MSC_BASE_ADDR, msc_index, 0); + /* enable the monitor instance to collect information according to the configuration */ + val_mmio_write(base + REG_MSMON_CFG_MBWU_CTL, BITFIELD_SET(MBWU_CTL_EN, 1)); +} + +/** + @brief This API disables the bandwidth usage monitor. + Prerequisite - If MSC supports RIS, Resource instance should be + selected using val_mpam_memory_configure_ris_sel + prior calling this API. + - MSC should support MBWU monitoring, can be checked + using val_mpam_msc_supports_mbwumon API. + + @param msc_index - index of the MSC node in the MPAM info table. +**/ +void +val_mpam_memory_mbwumon_disable(uint32_t msc_index) +{ + addr_t base; + + base = val_mpam_get_info(MPAM_MSC_BASE_ADDR, msc_index, 0); + /* disable the monitor */ + val_mmio_write(base + REG_MSMON_CFG_MBWU_CTL, BITFIELD_SET(MBWU_CTL_EN, 0)); +} + +/** + @brief This API reads the MBWU montior counter value. + Prerequisite - val_mpam_memory_configure_mbwumon, + This API can be called only after configuring MBWU monitor. + + @param msc_index - MPAM feature page index for this MSC. + @return MPAM_MON_NOT_READY if monitor has Not Ready status, + else counter value. +**/ +uint64_t +val_mpam_memory_mbwumon_read_count(uint32_t msc_index) +{ + addr_t base; + uint64_t count = MPAM_MON_NOT_READY; + + base = val_mpam_get_info(MPAM_MSC_BASE_ADDR, msc_index, 0); + + /*if MSMON_MBWU_L is implemented*/ + if (BITFIELD_READ(MBWUMON_IDR_LWD, val_mmio_read64(base + REG_MPAMF_MBWUMON_IDR))) { + if (BITFIELD_READ(MBWUMON_IDR_HAS_LONG, val_mmio_read64(base + REG_MPAMF_MBWUMON_IDR))) { + // (63 bits) + if (BITFIELD_READ(MSMON_MBWU_L_NRDY, val_mmio_read64(base + REG_MSMON_MBWU_L)) == 0) + count = BITFIELD_READ(MSMON_MBWU_L_63BIT_VALUE, + val_mmio_read64(base + REG_MSMON_MBWU_L)); + } + else { + // (44 bits) + if (BITFIELD_READ(MSMON_MBWU_L_NRDY, val_mmio_read64(base + REG_MSMON_MBWU_L) == 0)) + count = BITFIELD_READ(MSMON_MBWU_L_44BIT_VALUE, + val_mmio_read64(base + REG_MSMON_MBWU_L)); + } + } + else { + // (31 bits) + if (BITFIELD_READ(MSMON_MBWU_NRDY, val_mmio_read(base + REG_MSMON_MBWU)) == 0) { + count = BITFIELD_READ(MSMON_MBWU_VALUE, + val_mmio_read(base + REG_MSMON_MBWU)); + /* shift the count if scaling is enabled */ + count = count << BITFIELD_READ(MBWUMON_IDR_SCALE, + val_mmio_read(base + REG_MPAMF_MBWUMON_IDR)); + } + } + return(count); +} + +/** + @brief This API resets the MBWU montior counter value. + Prerequisite - val_mpam_memory_configure_mbwumon, + This API can be called only after configuring MBWU monitor. + + @param msc_index - MPAM feature page index for this MSC. + @return None +**/ +void +val_mpam_memory_mbwumon_reset(uint32_t msc_index) +{ + addr_t base; + + base = val_mpam_get_info(MPAM_MSC_BASE_ADDR, msc_index, 0); + + /*if MSMON_MBWU_L is implemented*/ + if (BITFIELD_READ(MBWUMON_IDR_LWD, val_mmio_read64(base + REG_MPAMF_MBWUMON_IDR))) + val_mmio_write64(base + REG_MSMON_MBWU_L, 0); + else + val_mmio_write(base + REG_MSMON_MBWU, 0); +} + + +/** + @brief Creates a buffer with length equal to size within the + address range (mem_base, mem_base + mem_size) + + @param mem_base - Base address of the memory range + @param size - Buffer size to be created + + @return Buffer address if SUCCESSFUL, else NULL +**/ +void * +val_mem_alloc_at_address(uint64_t mem_base, uint64_t size) +{ + return pal_mem_alloc_at_address(mem_base, size); +} + +/** + @brief Frees the allocated buffer with length equal to size within the + address range (mem_base, mem_base + mem_size) + + @param mem_base - Base address of the memory range + @param size - Buffer size to be created + + @return Buffer address if SUCCESSFUL, else NULL +**/ +void +val_mem_free_at_address(uint64_t mem_base, uint64_t size) +{ + return pal_mem_free_at_address(mem_base, size); +} +/** + @brief Creates a buffer with length equal to size within the + address range (mem_base, mem_base + mem_size) + + @param mem_base - Base address of the memory range + @param mem_size - Size of the memory range of interest + @param size - Buffer size to be created + + @return Buffer address if SUCCESSFUL, else NULL +**/ +uint64_t val_mpam_memory_get_size(uint32_t msc_index, uint32_t rsrc_index) +{ + uint64_t prox_domain; + + prox_domain = val_mpam_get_info(MPAM_MSC_RSRC_DESC1, msc_index, rsrc_index); + return val_srat_get_info(SRAT_MEM_ADDR_LEN, prox_domain); +} + +/** + @brief Creates a buffer with length equal to size within the + address range (mem_base, mem_base + mem_size) + + @param mem_base - Base address of the memory range + @param mem_size - Size of the memory range of interest + @param size - Buffer size to be created + + @return Buffer address if SUCCESSFUL, else NULL +**/ +uint64_t val_mpam_memory_get_base(uint32_t msc_index, uint32_t rsrc_index) +{ + uint64_t prox_domain; + + prox_domain = val_mpam_get_info(MPAM_MSC_RSRC_DESC1, msc_index, rsrc_index); + return val_srat_get_info(SRAT_MEM_BASE_ADDR, prox_domain); +} + +/** + @brief This API will call PAL layer to fill in the MPAM table information + into the g_mpam_info_table pointer. + 1. Caller - Application layer. + 2. Prerequisite - Memory allocated and passed as argument. + @param mpam_info_table pre-allocated memory pointer for cache info. + @return Error if Input parameter is NULL +**/ +void +val_mpam_create_info_table(uint64_t *mpam_info_table) +{ + if (mpam_info_table == NULL) { + val_print(AVS_PRINT_ERR, "\n Pre-allocated memory pointer is NULL \n", 0); + return; + } + + g_mpam_info_table = (MPAM_INFO_TABLE *)mpam_info_table; +#ifndef TARGET_LINUX + pal_mpam_create_info_table(g_mpam_info_table); + + val_print(AVS_PRINT_TEST, + " MPAM INFO: Number of MSC nodes : %d \n", g_mpam_info_table->msc_count); +#endif +} + +/** + @brief This API frees the memory allocated for MPAM info table. + @param None + @return None +**/ +void +val_mpam_free_info_table(void) +{ + pal_mem_free((void *)g_mpam_info_table); +} + +/** + @brief This API will call PAL layer to fill in the HMAT table information + into the g_hmat_info_table pointer. + 1. Caller - Application layer. + 2. Prerequisite - Memory allocated and passed as argument. + @param hmat_info_table pre-allocated memory pointer for cache info. + @return Error if Input parameter is NULL +**/ +void +val_hmat_create_info_table(uint64_t *hmat_info_table) +{ + if (hmat_info_table == NULL) { + val_print(AVS_PRINT_ERR, "\n Pre-allocated memory pointer is NULL \n", 0); + return; + } +#ifndef TARGET_LINUX + g_hmat_info_table = (HMAT_INFO_TABLE *)hmat_info_table; + + pal_hmat_create_info_table(g_hmat_info_table); + + if (g_hmat_info_table->num_of_mem_prox_domain != 0) + val_print(AVS_PRINT_TEST, + " HMAT INFO: Number of Prox domains : %d \n", + g_hmat_info_table->num_of_mem_prox_domain); +#endif +} + +/** + @brief This API frees the memory allocated for HMAT info table. + @param None + @return None +**/ +void +val_hmat_free_info_table(void) +{ + pal_mem_free((void *)g_hmat_info_table); +} + +/** + @brief This API will call PAL layer to fill in the SRAT table information + into the g_hmat_info_table pointer. + 1. Caller - Application layer. + 2. Prerequisite - Memory allocated and passed as argument. + @param srat_info_table pre-allocated memory pointer for cache info. + @return Error if Input parameter is NULL +**/ +void +val_srat_create_info_table(uint64_t *srat_info_table) +{ + if (srat_info_table == NULL) { + val_print(AVS_PRINT_ERR, "\n Pre-allocated memory pointer is NULL \n", 0); + return; + } +#ifndef TARGET_LINUX + g_srat_info_table = (SRAT_INFO_TABLE *)srat_info_table; + + pal_srat_create_info_table(g_srat_info_table); + + if (g_srat_info_table->num_of_mem_ranges != 0) + val_print(AVS_PRINT_TEST, + " SRAT INFO: Number of Memory Ranges : %d \n", + g_srat_info_table->num_of_mem_ranges); +#endif +} + +/** + @brief This API frees the memory allocated for SRAT info table. + @param None + @return None +**/ +void +val_srat_free_info_table(void) +{ + pal_mem_free((void *)g_srat_info_table); +} + +/** + @brief This API gets maximum supported value of PMG + @param msc_index - index of the MSC node in the MPAM info table. + @return PMG value. +**/ +uint32_t +val_mpam_get_max_pmg(uint32_t msc_index) +{ + addr_t base; + + base = val_mpam_get_info(MPAM_MSC_BASE_ADDR, msc_index, 0); + return BITFIELD_READ(IDR_PMG_MAX, val_mmio_read(base + REG_MPAMF_IDR)); +} + +/** + @brief This API gets Maximum supported value of PARTID + @param msc_index - index of the MSC node in the MPAM info table. + @return Partion ID value. +**/ +uint32_t +val_mpam_get_max_partid(uint32_t msc_index) +{ + addr_t base; + + base = val_mpam_get_info(MPAM_MSC_BASE_ADDR, msc_index, 0); + return BITFIELD_READ(IDR_PARTID_MAX, val_mmio_read(base + REG_MPAMF_IDR)); +} + +/** + @brief This API Configures CPOR settings for given MSC + Prerequisite - If MSC supports RIS, Resource instance should be + selected using val_mpam_memory_configure_ris_sel + prior calling this API. + - MSC should support CSU monitoring, can be checked + using val_mpam_supports_csumon API. + @param msc_index - index of the MSC node in the MPAM info table. + @param partid - PATRTID for CPOR configuration + @param cpbm_percentage - Percentage of cache to be partitioned + @return void. +**/ +void +val_mpam_configure_cpor(uint32_t msc_index, uint16_t partid, uint32_t cpbm_percentage) +{ + addr_t base; + uint16_t index; + uint32_t unset_bitmask; + uint32_t num_unset_bits; + uint16_t num_cpbm_bits; + uint32_t data; + + base = val_mpam_get_info(MPAM_MSC_BASE_ADDR, msc_index, 0); + + /* Get CPBM width */ + num_cpbm_bits = val_mpam_get_cpbm_width(msc_index); + + /* retaining other configured fields e.g, RIS index if supported */ + data = val_mmio_read(base + REG_MPAMCFG_PART_SEL); + + /* Select PARTID */ + data = BITFIELD_WRITE(data, PART_SEL_PARTID_SEL, partid); + val_mmio_write(base + REG_MPAMCFG_PART_SEL, partid); + + /* + * Configure CPBM register to have a 1 in cpbm_percentage + * bits in the overall CPBM_WD bit positions + */ + num_cpbm_bits = (num_cpbm_bits * cpbm_percentage) / 100 ; + for (index = 0; index < num_cpbm_bits - 31; index += 32) + val_mmio_write(base + REG_MPAMCFG_CPBM + index, CPOR_BITMAP_DEF_VAL); + + /* Unset bits from above step are set */ + num_unset_bits = num_cpbm_bits - index; + unset_bitmask = (1 << num_unset_bits) - 1; + if (unset_bitmask) + val_mmio_write(base + REG_MPAMCFG_CPBM + index, unset_bitmask); + + /* Issue a DSB instruction */ + val_mem_issue_dsb(); + + return; +} + +/** + @brief This API gets CPBM width + @param msc_index - index of the MSC node in the MPAM info table. + @return Number of bits in the cache portion partitioning bit map. +**/ +uint32_t +val_mpam_get_cpbm_width(uint32_t msc_index) +{ + addr_t base; + + base = val_mpam_get_info(MPAM_MSC_BASE_ADDR, msc_index, 0); + if (val_mpam_supports_cpor(msc_index)) + return BITFIELD_READ(CPOR_IDR_CPBM_WD, val_mmio_read(base + REG_MPAMF_CPOR_IDR)); + else + return 0; +} + +/** + @brief This API issues a DSB Memory barrier instruction + @param None + @return None +**/ +void +val_mem_issue_dsb(void) +{ + AA64IssueDSB(); +} + +/** + @brief This API configures the cache storage usage monitor. + Prerequisite - If MSC supports RIS, Resource instance should be + selected using val_mpam_memory_configure_ris_sel + prior calling this API. + - MSC should support CSU monitoring, can be checked + using val_mpam_supports_csumon API. + + @param msc_index - index of the MSC node in the MPAM info table. + @return None +**/ +void +val_mpam_configure_csu_mon(uint32_t msc_index, uint16_t partid, uint8_t pmg, uint16_t mon_sel) +{ + addr_t base; + uint32_t data; + + base = val_mpam_get_info(MPAM_MSC_BASE_ADDR, msc_index, 0); + + /* retaining other configured fields e.g, RIS index if supported */ + data = val_mmio_read(base + REG_MSMON_CFG_MON_SEL); + /* Select the monitor instance */ + data = BITFIELD_WRITE(data, MON_SEL_MON_SEL, mon_sel); + val_mmio_write(base + REG_MSMON_CFG_MON_SEL, data); + + /* Configure the CSU monitor filter register for input PARTID & PMG */ + data = BITFIELD_SET(CSU_FLT_PARTID, partid) | BITFIELD_SET(CSU_FLT_PMG, pmg); + val_mmio_write(base + REG_MSMON_CFG_CSU_FLT, data); + + /*Disable the monitor */ + val_mpam_csumon_disable(msc_index); + + /* Configure the CSU monitor control register to match input PARTID & PMG */ + data = BITFIELD_SET(CSU_CTL_MATCH_PARTID, 1) | BITFIELD_SET(CSU_CTL_MATCH_PMG, 1); + val_mmio_write(base + REG_MSMON_CFG_CSU_CTL, data); + + /* Issue a DSB instruction */ + val_mem_issue_dsb(); + + return; +} + +/** + @brief This API enables the Cache storage usage monitor. + Prerequisite - If MSC supports RIS, Resource instance should be + selected using val_mpam_memory_configure_ris_sel + prior calling this API. + - MSC should support CSU monitoring, can be checked + using val_mpam_supports_csumon API.. + + @param msc_index - index of the MSC node in the MPAM info table. +**/ +void +val_mpam_csumon_enable(uint32_t msc_index) +{ + addr_t base; + uint32_t data; + base = val_mpam_get_info(MPAM_MSC_BASE_ADDR, msc_index, 0); + + /* enable the monitor instance to collect information according to the configuration */ + data = BITFIELD_WRITE(val_mmio_read(base + REG_MSMON_CFG_CSU_CTL), CSU_CTL_EN, 1); + val_mmio_write(base + REG_MSMON_CFG_CSU_CTL, data); +} + +/** + @brief This API disables the Cache strorage usage monitor. + Prerequisite - If MSC supports RIS, Resource instance should be + selected using val_mpam_memory_configure_ris_sel + prior calling this API. + - MSC should support CSU monitoring, can be checked + using val_mpam_supports_csumon API. + + @param msc_index - index of the MSC node in the MPAM info table. + @return None +**/ +void +val_mpam_csumon_disable(uint32_t msc_index) +{ + addr_t base; + uint32_t data; + base = val_mpam_get_info(MPAM_MSC_BASE_ADDR, msc_index, 0); + + /* enable the monitor instance to collect information according to the configuration */ + data = BITFIELD_WRITE(val_mmio_read(base + REG_MSMON_CFG_CSU_CTL), CSU_CTL_EN, 0); + val_mmio_write(base + REG_MSMON_CFG_CSU_CTL, data); +} + +/** + @brief This API reads the CSU montior counter value. + Prerequisite - val_mpam_configure_csu_mon, + This API can be called only after configuring CSU monitor. + + @param msc_index - MPAM feature page index for this MSC. + @return 0 if monitor has Not Ready status, + else counter value. +**/ +uint32_t +val_mpam_read_csumon(uint32_t msc_index) +{ + addr_t base; + uint32_t count; + + base = val_mpam_get_info(MPAM_MSC_BASE_ADDR, msc_index, 0); + if (BITFIELD_READ(MSMON_CSU_NRDY, val_mmio_read(base + REG_MSMON_CSU)) == 0) { + count = BITFIELD_READ(MSMON_CSU_VALUE, + val_mmio_read(base + REG_MSMON_CSU)); + return count; + } + return 0; +} diff --git a/val/src/avs_pmu.c b/val/src/avs_pmu.c new file mode 100644 index 00000000..383681a3 --- /dev/null +++ b/val/src/avs_pmu.c @@ -0,0 +1,555 @@ +/** @file + * Copyright (c) 2022-2023, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "include/sbsa_avs_val.h" +#include "include/sbsa_avs_common.h" +#include "include/sbsa_avs_pmu.h" +#include "include/sbsa_avs_pmu_reg.h" + +PMU_INFO_TABLE *g_pmu_info_table; + +/** + @brief This API executes all the PMU tests sequentially + 1. Caller - Application layer. + 2. Prerequisite - val_pmu_create_info_table + @param level - level of compliance being tested for. + @param num_pe - the number of PE to run these tests on. + @return Consolidated status of all the tests run. +**/ +uint32_t +val_pmu_execute_tests(uint32_t level, uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + uint32_t i, pmu_node_count; + + for (i = 0; i < MAX_TEST_SKIP_NUM; i++) { + if (g_skip_test_num[i] == AVS_PMU_TEST_NUM_BASE) { + val_print(AVS_PRINT_TEST, " USER Override - Skipping all PMU tests \n", 0); + return AVS_STATUS_SKIP; + } + } + + if (g_single_module != SINGLE_MODULE_SENTINEL && g_single_module != AVS_PMU_TEST_NUM_BASE && + (g_single_test == SINGLE_MODULE_SENTINEL || + (g_single_test - AVS_PMU_TEST_NUM_BASE > 100 || + g_single_test - AVS_PMU_TEST_NUM_BASE < 0))) { + val_print(AVS_PRINT_TEST, " USER Override - Skipping all PMU tests \n", 0); + val_print(AVS_PRINT_TEST, " (Running only a single module)\n", 0); + return AVS_STATUS_SKIP; + } + + /* check if PE supports PMU extension, else skip all PMU tests */ + if (val_pe_feat_check(PE_FEAT_PMU)) { + val_print(AVS_PRINT_TEST, + "\n PE PMU extension unimplemented. Skipping all PMU tests\n", 0); + return AVS_STATUS_SKIP; + } + + g_curr_module = 1 << PMU_MODULE; + + /* run tests which don't check PMU nodes */ + if (g_sbsa_level > 6) { + status = pmu001_entry(num_pe); + status |= pmu002_entry(num_pe); + status |= pmu003_entry(num_pe); + status |= pmu006_entry(num_pe); + } + + pmu_node_count = val_pmu_get_info(PMU_NODE_COUNT, 0); + if (pmu_node_count == 0) { + val_print(AVS_PRINT_TEST, + "\n PMU nodes not found. Skipping remaining PMU tests\n", 0); + return AVS_STATUS_SKIP; + } + + if (g_sbsa_level > 6) { + status |= pmu004_entry(num_pe); + status |= pmu005_entry(num_pe); + status |= pmu007_entry(num_pe); + status |= pmu008_entry(num_pe); + status |= pmu009_entry(num_pe); + } + + val_print_test_end(status, "PMU"); + + return status; +} + +/** + @brief This API will call PAL layer to fill in the PMU information + into the address pointed by g_pmu_info_table pointer. + 1. Caller - Application layer. + 2. Prerequisite - Memory allocated and passed as argument. + @param pmu_info_table pre-allocated memory pointer for PMU info + @return Error if Input param is NULL +**/ +void +val_pmu_create_info_table(uint64_t *pmu_info_table) +{ + if (pmu_info_table == NULL) { + val_print(AVS_PRINT_ERR, "\nInput for Create PMU Info table cannot be NULL", 0); + return; + } + + g_pmu_info_table = (PMU_INFO_TABLE *)pmu_info_table; + + pal_pmu_create_info_table(g_pmu_info_table); + + val_print(AVS_PRINT_TEST, " PMU_INFO: Number of PMU units : %4d\n", + g_pmu_info_table->pmu_count); + + return; +} + +/** + @brief Free the memory allocated for the PMU information table +**/ +void +val_pmu_free_info_table() +{ + pal_mem_free((void *)g_pmu_info_table); + g_pmu_info_table = NULL; +} + +/** + @brief This API returns requested PMU node info. + + @param type - the type of information being requested. + @param node_index - index of the node in the APMT info table.. + + @return requested data if found, otherwise PMU_INVALID_INFO. +**/ + +uint64_t +val_pmu_get_info(PMU_INFO_e type, uint32_t node_index) +{ + PMU_INFO_BLOCK *entry; + + if (g_pmu_info_table == NULL) { + val_print(AVS_PRINT_WARN, "\n APMT info table not found", 0); + return 0; + } + + if (node_index > g_pmu_info_table->pmu_count) { + val_print(AVS_PRINT_WARN, "\n Invalid Node index ", 0); + return 0; + } + + entry = &g_pmu_info_table->info[node_index]; + + switch (type) { + case PMU_NODE_TYPE: + return entry->type; + case PMU_NODE_BASE0: + return entry->base0; + case PMU_NODE_BASE1: + return entry->base1; + case PMU_NODE_PRI_INST: + return entry->primary_instance; + case PMU_NODE_SEC_INST: + return entry->secondary_instance; + case PMU_NODE_COUNT: + return g_pmu_info_table->pmu_count; + case PMU_NODE_DP_EXTN: + return entry->dual_page_extension; + default: + val_print(AVS_PRINT_ERR, "\n This PMU info option is not supported : %d ", type); + return 0; + } +} + +/** + @brief This API checks if the PMU implements dedicated cycle counter. + @param node_index - index of the PMU node in the APMT info table. + @return 1 if supported 0 otherwise. +**/ +uint8_t +val_pmu_supports_dedicated_cycle_counter(uint32_t node_index) +{ + addr_t base; + + base = val_pmu_get_info(PMU_NODE_BASE0, node_index); + + return BITFIELD_READ(PMCFGR_CC, val_mmio_read(base + REG_PMCFGR)); +} + +/** + @brief This API gets the number of monitors supported by the PMU node. + @param node_index - index of the PMU node in the APMT info table. + @return monitor count. +**/ +uint32_t +val_pmu_get_monitor_count(uint32_t node_index) +{ + addr_t base; + + base = val_pmu_get_info(PMU_NODE_BASE0, node_index); + + /* If PMCFGR.CC == 1 PMEVCNTR31 is implemented and is a dedicated cycle counter + else If PMEVCNTR31 is implemented, it is a normal monitor */ + if (val_pmu_supports_dedicated_cycle_counter(node_index)) + return BITFIELD_READ(PMCFGR_N, val_mmio_read(base + REG_PMCFGR)); + else + return BITFIELD_READ(PMCFGR_N, val_mmio_read(base + REG_PMCFGR)) + 1; +} + +/** + @brief This API disbles all PMU monitors. + @param node_index - index of the PMU node in the APMT info table. + @return none. +**/ +void +val_pmu_disable_all_monitors(uint32_t node_index) +{ + addr_t base; + uint32_t data; + + base = val_pmu_get_info(PMU_NODE_BASE0, node_index); + + data = BITFIELD_WRITE(val_mmio_read(base + REG_PMCR), PMCR_E, 0); + + val_mmio_write(base + REG_PMCR, data); +} + +/** + @brief This API enable all PMU monitors count. Monitors are enabled by PMCNTENSET + @param node_index - index of the PMU node in the APMT info table. + @return none. +**/ +void +val_pmu_enable_all_monitors(uint32_t node_index) +{ + addr_t base; + uint32_t data; + + base = val_pmu_get_info(PMU_NODE_BASE0, node_index); + + data = BITFIELD_WRITE(val_mmio_read(base + REG_PMCR), PMCR_E, 1); + + val_mmio_write(base + REG_PMCR, data); +} + +/** + @brief This API resets all PMU monitors. + @param node_index - index of the PMU node in the APMT info table. + @return none. +**/ +void +val_pmu_reset_all_monitors(uint32_t node_index) +{ + addr_t base; + uint32_t data; + + base = val_pmu_get_info(PMU_NODE_BASE0, node_index); + + data = BITFIELD_WRITE(val_mmio_read(base + REG_PMCR), PMCR_P, 1); + + val_mmio_write(base + REG_PMCR, data); +} + +/** + @brief This API returns the number of monitor groups implemented by the PMU node. + @param node_index - index of the PMU node in the APMT info table. + @return monitor group count. +**/ +uint32_t +val_pmu_get_monitor_group_count(uint32_t node_index) +{ + addr_t base; + + base = val_pmu_get_info(PMU_NODE_BASE0, node_index); + + /* PMCFGR.NCG gives number of monitor groups implemented minus one */ + return BITFIELD_READ(PMCFGR_NCG, val_mmio_read(base + REG_PMCFGR)) + 1; +} + +/** + @brief This API returns the size of the largest implemented monitor. + @param node_index - index of the PMU node in the APMT info table. + @return The size of the largest implemented monitor. +**/ +uint32_t +val_pmu_get_max_monitor_size(uint32_t node_index) +{ + addr_t base; + + base = val_pmu_get_info(PMU_NODE_BASE0, node_index); + + return BITFIELD_READ(PMCFGR_SIZE, val_mmio_read(base + REG_PMCFGR)); +} + +/** + @brief This API Configures the requested monitor instance. + @param node_index - index of the PMU node in the APMT info table. + @param event_type - PMU event type. + @param mon_inst - instance of the monitor to enable. + @return status 1 - Configure FAIL due to unsupported event + 0 - PASS +**/ +uint32_t +val_pmu_configure_monitor(uint32_t node_index, PMU_EVENT_TYPE_e event_type, uint32_t mon_inst) +{ + addr_t base; + uint32_t offset; + uint32_t data; + uint32_t node_type; + + base = val_pmu_get_info(PMU_NODE_BASE0, node_index); + + /* Calculate the register offset based on selected monitor */ + offset = 4 * mon_inst; + + /* Disable all monitors before configuring the monitor */ + val_pmu_disable_all_monitors(node_index); + + node_type = val_pmu_get_info(PMU_NODE_TYPE, node_index); + /* Get event id details based on Implementation */ + data = pal_pmu_get_event_info(event_type, node_type); + + if (data == PMU_EVENT_INVALID) { + return 1; + } + + /* Write the received details into PMEVTYPER */ + val_mmio_write(base + offset + REG_PMEVTYPER, data); + + /* Enable all the monitors using PMCR.E */ + val_pmu_enable_all_monitors(node_index); + + /* Reset the all monitor counts before enabling required monitor */ + val_pmu_reset_all_monitors(node_index); + + return 0; +} + +/** + @brief This API Enables the requested monitor instance. + @param node_index - index of the PMU node in the APMT info table. + @param mon_inst - instance of the monitor to enable. + @return The size of the largest implemented monitor. +**/ +void +val_pmu_enable_monitor(uint32_t node_index, uint32_t mon_inst) +{ + addr_t base; + + base = val_pmu_get_info(PMU_NODE_BASE0, node_index); + + uint32_t reg_offset, bit_offset; + + /* Register offset and bit offset is calculated based on the selected + monitor */ + reg_offset = mon_inst / 32 * 4; + bit_offset = mon_inst % 32; + + val_mmio_write(base + reg_offset + REG_PMCNTENSET, 1 << bit_offset); +} + +/** + @brief This API disables the requested monitor instance. + @param node_index - index of the PMU node in the APMT info table. + @param mon_inst - instance of the monitor to disable. + @return None. +**/ +void +val_pmu_disable_monitor(uint32_t node_index, uint32_t mon_inst) +{ + addr_t base; + + base = val_pmu_get_info(PMU_NODE_BASE0, node_index); + + uint32_t reg_offset, bit_offset; + + /* Register offset and bit offset is calculated based on the selected + monitor */ + reg_offset = mon_inst / 32 * 4; + bit_offset = mon_inst % 32; + + val_mmio_write(base + reg_offset + REG_PMCNTENCLR, 1 << bit_offset); + + /* Reset all the monitors */ + val_pmu_reset_all_monitors(node_index); +} + +/** + @brief This API reads PMU counter value. + @param node_index - index of the PMU node in the APMT info table. + @param mon_inst - instance of the monitor to read. + @return Counter value. +**/ +uint64_t +val_pmu_read_count(uint32_t node_index, uint32_t mon_inst) +{ + addr_t base; + uint64_t count; + uint32_t offset; + + /* PMEVCNTR is a page 1 register when dual page extension is implemented */ + if (val_pmu_get_info(PMU_NODE_DP_EXTN, node_index)) + base = val_pmu_get_info(PMU_NODE_BASE1, node_index); + else + base = val_pmu_get_info(PMU_NODE_BASE0, node_index); + + /* The width of the register PMEVCNTR depends on the size of the largest + implemented counter. if size if PMCFGR.SIZE <= 0b011111, all monitors are + 32 bits or smaller else at least one monitor is larger than 32 bits. The + offset is then calculated accordingly. */ + + if (val_pmu_get_max_monitor_size(node_index) > 0b011111) { + offset = 8 * mon_inst; + count = (uint64_t)val_mmio_read(base + offset + REG_PMEVCNTR_H) << 32 | + val_mmio_read(base + offset + REG_PMEVCNTR_L); + } + else { + offset = 4 * mon_inst; + count = val_mmio_read(base + offset + REG_PMEVCNTR); + } + + return count; +} + +/** + @brief This API returns PMU node index for given proximity domain + @param prox_domain Proximity domain from SRAT ACPI table. + @return PMU node index from APMT ACPI table. +**/ +uint32_t +val_pmu_get_node_index(uint64_t prox_domain) +{ + uint32_t node_index; + PMU_INFO_BLOCK *entry; + + for (node_index = 0 ; node_index < g_pmu_info_table->pmu_count ; node_index++) + { + entry = &g_pmu_info_table->info[node_index]; + if (entry->type == PMU_NODE_MEM_CNTR) { + if (prox_domain == entry->primary_instance) { + return node_index; + } + } + } + val_print(AVS_PRINT_DEBUG, "\n PMU node for given proximity domain not found ", 0); + return PMU_INVALID_INDEX; +} + +/* the below API are needed for test update to Coresight PMU EAC release specification, + The tests are currently based on beta release of spec and below API are not called */ +/** + @brief This API checks if PMU node implements PMSCR register. + @param node_index - index of the PMU node in the APMT info table. + @return 1 - PMSCR is present. + 0 - PMSCR is absent. +**/ +uint32_t +val_pmu_implements_pmscr(uint32_t node_index) +{ + addr_t base; + + base = val_pmu_get_info(PMU_NODE_BASE0, node_index); + + return BITFIELD_READ(PMSCR_IMPL, val_mmio_read(base + REG_PMSCR_L)); +} + +/** + @brief This API checks if PMU node is secure only. + @param node_index - index of the PMU node in the APMT info table. + @return 0 - Non-secure and Realm Register Access is disabled + 1 - Non-secure and Realm Register Access is enabled +**/ +uint32_t +val_pmu_is_secure(uint32_t node_index) +{ + addr_t base; + + base = val_pmu_get_info(PMU_NODE_BASE0, node_index); + + if (val_pmu_implements_pmscr(node_index)) { + return BITFIELD_READ(PMSCR_NSRA, val_mmio_read(base + REG_PMSCR_L)); + } + + return 0; +} + +/** + @brief This API checks if pmu monitor count value is valid + @param interface_acpiid - acpiid of interface + @param count_value - monitor count value + @param eventid - eventid + @return 0 - monitor count value is valid + non-zero - error or invallid count value +**/ +uint32_t +val_pmu_check_monitor_count_value(uint64_t interface_acpiid, uint32_t count_value, + uint32_t eventid) +{ + return pal_pmu_check_monitor_count_value(interface_acpiid, count_value, eventid); +} + +/** + @brief This API generates required workload for given pmu node and event id + @param interface_acpiid - acpiid of interface + @param pmu_node_index - pmu node index + @param mon_index - monitor index + @param eventid - eventid + @return 0 - success status + non-zero - error status +**/ +uint32_t +val_generate_traffic(uint64_t interface_acpiid, uint32_t pmu_node_index, + uint32_t mon_index, uint32_t eventid) +{ + return pal_generate_traffic(interface_acpiid, pmu_node_index, mon_index, eventid); +} +/** + @brief This API generates required workload for given pmu node and event id + @param interface_acpiid - acpiid of interface + @param index_id - index id of interface + @return 0 - success status + non-zero - error status +**/ +uint32_t +val_pmu_get_index_acpiid(uint64_t interface_acpiid) +{ + uint32_t node_index; + PMU_INFO_BLOCK *entry; + + for (node_index = 0 ; node_index < g_pmu_info_table->pmu_count ; node_index++) + { + entry = &g_pmu_info_table->info[node_index]; + if ((entry->type == PMU_NODE_ACPI_DEVICE) && + (entry->primary_instance == interface_acpiid)) { + return node_index; + } + } + val_print(AVS_PRINT_DEBUG, "\n PMU node for given acpi id not found ", 0); + return PMU_INVALID_INDEX; + +} +/** + @brief This API checks if PMU node is secure only. + @param interface_acpiid - acpiid of interface + @param num_traffic_type_support - num of traffic type supported. + @return 0 - success status + non-zero - error status +**/ +uint32_t +val_pmu_get_multi_traffic_support_interface(uint64_t *interface_acpiid, + uint32_t *num_traffic_type_support) +{ + return pal_pmu_get_multi_traffic_support_interface(interface_acpiid, num_traffic_type_support); +} diff --git a/val/src/avs_ras.c b/val/src/avs_ras.c new file mode 100644 index 00000000..8ee36603 --- /dev/null +++ b/val/src/avs_ras.c @@ -0,0 +1,827 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "include/sbsa_avs_val.h" +#include "include/sbsa_avs_common.h" +#include "include/sbsa_avs_ras.h" +#include "include/sbsa_avs_pe.h" + +static RAS_INFO_TABLE *g_ras_info_table; +static RAS2_INFO_TABLE *g_ras2_info_table; + +/** + @brief This API executes all the RAS tests sequentially + 1. Caller - Application layer. + 2. Prerequisite - val_ras_create_info_table + @param level - level of compliance being tested for. + @param num_pe - the number of PE to run these tests on. + @return Consolidated status of all the tests run. +**/ +uint32_t +val_ras_execute_tests(uint32_t level, uint32_t num_pe) +{ + uint32_t status, i; + uint64_t num_ras_nodes = 0; + + for (i = 0; i < MAX_TEST_SKIP_NUM; i++) { + if (g_skip_test_num[i] == AVS_RAS_TEST_NUM_BASE) { + val_print(AVS_PRINT_TEST, "\n USER Override - Skipping all RAS tests \n", 0); + return AVS_STATUS_SKIP; + } + } + + if (g_single_module != SINGLE_MODULE_SENTINEL && g_single_module != AVS_RAS_TEST_NUM_BASE && + (g_single_test == SINGLE_MODULE_SENTINEL || + (g_single_test - AVS_RAS_TEST_NUM_BASE > 100 || + g_single_test - AVS_RAS_TEST_NUM_BASE < 0))) { + val_print(AVS_PRINT_TEST, " USER Override - Skipping all RAS tests \n", 0); + val_print(AVS_PRINT_TEST, " (Running only a single module)\n", 0); + return AVS_STATUS_SKIP; + } + + /* check if PE supports RAS extension, else skip all RAS tests */ + if (val_pe_feat_check(PE_FEAT_RAS)) { + val_print(AVS_PRINT_TEST, + "\n PE RAS extension unimplemented. Skipping all RAS tests\n", 0); + return AVS_STATUS_SKIP; + } + + g_curr_module = 1 << RAS_MODULE; + + status = val_ras_get_info(RAS_INFO_NUM_NODES, 0, &num_ras_nodes); + if (status || (num_ras_nodes == 0)) { + val_print(AVS_PRINT_TEST, "\n RAS nodes not found. Skipping all RAS tests\n", 0); + return AVS_STATUS_SKIP; + } + + /* set default status to AVS_STATUS_FAIL */ + status = AVS_STATUS_FAIL; + + if (g_sbsa_level > 6) { + status = ras001_entry(num_pe); + status |= ras002_entry(num_pe); + status |= ras003_entry(num_pe); + status |= ras004_entry(num_pe); + status |= ras005_entry(num_pe); + status |= ras006_entry(num_pe); + status |= ras007_entry(num_pe); + status |= ras008_entry(num_pe); + status |= ras009_entry(num_pe); + status |= ras010_entry(num_pe); + status |= ras011_entry(num_pe); + status |= ras012_entry(num_pe); + } + val_print_test_end(status, "RAS"); + + return status; +} + +/** + @brief This API will call PAL layer to fill in the RAS information + into the address pointed by g_ras_info_table pointer. + 1. Caller - Application layer. + 2. Prerequisite - Memory allocated and passed as argument. + @param ras_info_table pre-allocated memory pointer for RAS info + @return Error if Input param is NULL +**/ +uint32_t +val_ras_create_info_table(uint64_t *ras_info_table) +{ + + if (ras_info_table == NULL) { + val_print(AVS_PRINT_ERR, "Input for Create Info table cannot be NULL \n", 0); + return AVS_STATUS_ERR; + } + + g_ras_info_table = (RAS_INFO_TABLE *)ras_info_table; + + pal_ras_create_info_table(g_ras_info_table); + + val_print(AVS_PRINT_TEST, " RAS_INFO: Number of RAS nodes : %4d \n", + g_ras_info_table->num_nodes); + + return AVS_STATUS_PASS; +} + +/** + @brief Free the memory allocated for the RAS information table +**/ +void +val_ras_free_info_table() +{ + pal_mem_free((void *)g_ras_info_table); +} + +/** + @brief This API will call PAL layer to fill in the RAS2 feature + information into the address pointed by g_ras2_info_table pointer. + 1. Caller - Application layer. + 2. Prerequisite - Memory allocated and passed as argument. + @param ras_info_table pre-allocated memory pointer for RAS info + @return Error if Input param is NULL +**/ +void +val_ras2_create_info_table(uint64_t *ras2_info_table) +{ + + if (ras2_info_table == NULL) { + val_print(AVS_PRINT_ERR, "\nInput for RAS2 feat create info table cannot be NULL \n", 0); + return; + } + +#ifndef TARGET_LINUX + g_ras2_info_table = (RAS2_INFO_TABLE *)ras2_info_table; + + pal_ras2_create_info_table(g_ras2_info_table); + + val_print(AVS_PRINT_TEST, " RAS2_INFO: Number of RAS2 entries : %4d \n", + g_ras2_info_table->num_all_block); + val_print(AVS_PRINT_TEST, " RAS2_INFO: Num of RAS2 memory entries: %4d \n", + g_ras2_info_table->num_of_mem_block); +#endif +return; +} + +/** + @brief Free the memory allocated for the RAS2 feature information table +**/ +void +val_ras2_free_info_table() +{ + pal_mem_free((void *)g_ras2_info_table); +} + +/** + @brief This API will use the info table to return the RAS information + for info_type and param1 into the address pointed by ret_data. + 1. Caller - Test layer. + 2. Prerequisite - val_ras_create_info_table. + @param info_type Required RAS information type enum + @param param1 Variable passed from test for which info needs to be returned. + @param *ret_data Return Data Pointer + @return Status +**/ +uint32_t +val_ras_get_info(uint32_t info_type, uint32_t param1, uint64_t *ret_data) +{ + uint32_t status = AVS_STATUS_FAIL; + uint32_t j = 0; + uint64_t value = 0; + uint64_t pe_affinity = 0; + uint32_t pe_uid = 0; + + switch (info_type) { + + case RAS_INFO_NUM_NODES: + *ret_data = g_ras_info_table->num_nodes; + return AVS_STATUS_PASS; + case RAS_INFO_NODE_TYPE: + *ret_data = g_ras_info_table->node[param1].type; + return AVS_STATUS_PASS; + case RAS_INFO_INTF_TYPE: + *ret_data = g_ras_info_table->node[param1].intf_info.intf_type; + return AVS_STATUS_PASS; + case RAS_INFO_PE_RES_TYPE: + if (g_ras_info_table->node[param1].type == NODE_TYPE_PE) { + *ret_data = g_ras_info_table->node[param1].node_data.pe.resource_type; + return AVS_STATUS_PASS; + } else + return AVS_STATUS_FAIL; + break; + case RAS_INFO_MC_RES_PROX_DOMAIN: + if (g_ras_info_table->node[param1].type == NODE_TYPE_MC) { + *ret_data = g_ras_info_table->node[param1].node_data.mc.proximity_domain; + return AVS_STATUS_PASS; + } else + return AVS_STATUS_FAIL; + break; + case RAS_INFO_NUM_PE: + /* Returns the number of PE RAS Nodes */ + *ret_data = g_ras_info_table->num_pe_node; + return AVS_STATUS_PASS; + break; + case RAS_INFO_NUM_MC: + /* Returns the number of MC RAS Nodes */ + *ret_data = g_ras_info_table->num_mc_node; + return AVS_STATUS_PASS; + break; + case RAS_INFO_BASE_ADDR: + /* Returns the Base address of Error Group. Valid only in MMIO */ + if (g_ras_info_table->node[param1].intf_info.intf_type == RAS_INTERFACE_MMIO) { + *ret_data = g_ras_info_table->node[param1].intf_info.base_addr; + return AVS_STATUS_PASS; + } else + return AVS_STATUS_FAIL; + break; + case RAS_INFO_START_INDEX: + /* Returns the Start Error Record Index Number */ + *ret_data = g_ras_info_table->node[param1].intf_info.start_rec_index; + return AVS_STATUS_PASS; + break; + case RAS_INFO_NUM_ERR_REC: + /* Returns the Number of Error Records */ + *ret_data = g_ras_info_table->node[param1].intf_info.num_err_rec; + return AVS_STATUS_PASS; + break; + case RAS_INFO_ERR_REC_IMP: + /* Returns the Error Record Implemented */ + *ret_data = g_ras_info_table->node[param1].intf_info.err_rec_implement; + return AVS_STATUS_PASS; + break; + case RAS_INFO_ADDR_MODE: + /* Returns the addressing mode bitmap for RAS address syndrome */ + *ret_data = g_ras_info_table->node[param1].intf_info.addressing_mode; + return AVS_STATUS_PASS; + break; + case RAS_INFO_STATUS_REPORT: + /* Returns the Error Reporting Status Field */ + *ret_data = g_ras_info_table->node[param1].intf_info.err_status_reporting; + return AVS_STATUS_PASS; + break; + case RAS_INFO_PFG_SUPPORT: + /* Returns the PFG Support */ + value = val_ras_reg_read(param1, RAS_ERR_FR, 0); + if (value == INVALID_RAS_REG_VAL) { + val_print(AVS_PRINT_ERR, + "\n Couldn't read ERR<0>FR register for RAS node index: 0x%lx", + param1); + return AVS_STATUS_FAIL; + } + if (value & ERR_FR_INJ_MASK) + *ret_data = 0x1; + else + *ret_data = 0x0; + return AVS_STATUS_PASS; + case RAS_INFO_ERI_ID: + /* Returns the ERI ID For the Node */ + for (j = 0; j < g_ras_info_table->node[param1].num_intr_entries; j++) { + if (g_ras_info_table->node[param1].intr_info[j].type) { + *ret_data = g_ras_info_table->node[param1].intr_info[j].gsiv; + return AVS_STATUS_PASS; + } + } + return AVS_STATUS_FAIL; + break; + case RAS_INFO_FHI_ID: + /* Returns the FHI ID For the Node */ + for (j = 0; j < g_ras_info_table->node[param1].num_intr_entries; j++) { + if (!(g_ras_info_table->node[param1].intr_info[j].type)) { + *ret_data = g_ras_info_table->node[param1].intr_info[j].gsiv; + return AVS_STATUS_PASS; + } + } + return AVS_STATUS_FAIL; + break; + case RAS_INFO_NODE_INDEX_FOR_AFF: + /* Returns the Node Index For the PE node for MPIDR = param1 */ + val_print(AVS_PRINT_DEBUG, + "\n RAS_GET_INFO : Param1 = 0x%x ", + param1); + for (j = 0; j < g_ras_info_table->num_nodes; j++) { + if (g_ras_info_table->node[j].type == NODE_TYPE_PE) { + if (g_ras_info_table->node[j].node_data.pe.flags & 0x1) { + /* This is a global node return the index*/ + *ret_data = j; + return AVS_STATUS_PASS; + } else if (g_ras_info_table->node[j].node_data.pe.flags & 0x2) { + /* This is a shared resource */ + /* Get RAS node interface type and read for processor affinity */ + if (g_ras_info_table->node[j].intf_info.intf_type == RAS_INTF_TYPE_SYS_REG) + /* affinity field read from ACPI */ + pe_affinity = g_ras_info_table->node[j].node_data.pe.affinity; + else { + pe_affinity = val_ras_reg_read(RAS_ERR_ERRDEVAFF, j, 0); + if (pe_affinity == INVALID_RAS_REG_VAL) { + val_print(AVS_PRINT_ERR, + "\n RAS_GET_INFO : Invalid pe_affinity (ERR_ERRDEVAFF) for RAS node = %d ", + j); + return AVS_STATUS_FAIL; + } + } + /* check if PE belongs to any of the higher affinity level i.e, 1, 2, or 3 */ + if (((param1 & PE_AFFINITY_LVL_1) == (pe_affinity & PE_AFFINITY_LVL_1)) + || ((param1 & PE_AFFINITY_LVL_2) == (pe_affinity & PE_AFFINITY_LVL_2)) + || ((param1 & PE_AFFINITY_LVL_3) == (pe_affinity & PE_AFFINITY_LVL_3))) { + *ret_data = j; + return AVS_STATUS_PASS; + } + } else { + /* if global or shared error flag not set for node, + Use g_ras_info_table->node[j].node_data.pe.processor_id */ + /* get processor UID */ + pe_uid = val_pe_get_uid(param1); + if (pe_uid == INVALID_PE_INFO) { + val_print(AVS_PRINT_ERR, + "\n RAS_GET_INFO : Invalid PE UID for MPIDR = %lx", + param1); + return AVS_STATUS_FAIL; + } + if (pe_uid == g_ras_info_table->node[j].node_data.pe.processor_id) { + *ret_data = j; + return AVS_STATUS_PASS; + } + } + } + } + val_print(AVS_PRINT_ERR, + "\n RAS_GET_INFO : No PE RAS node matches with MPIDR = %lx", + param1); + return AVS_STATUS_FAIL; + break; + default: + break; + + } + + return status; +} + +/** + @brief This API is a single point of entry to retrieve + RAS2 memory feature info from RAS2 info table. + 1. Caller - Test suite + 2. Prerequisite - val_ras2_create_info_table + @param type the type of information being requested. + @param index the index of RAS2 memory feat info instance. + @return 64-bit data +**/ +uint64_t +val_ras2_get_mem_info(RAS2_MEM_INFO_e type, uint32_t index) +{ + uint32_t i, j = 0; + RAS2_BLOCK *block; + + if (g_ras2_info_table == NULL) { + val_print(AVS_PRINT_ERR, "\nRAS2_GET_MEM_INFO : ras2 info table is not created \n", 0); + return 0; /* imply no ras2_info entries */ + } + + if (type == RAS2_NUM_MEM_BLOCK) + return g_ras2_info_table->num_of_mem_block; + + /* check if index in range */ + if (index > g_ras2_info_table->num_of_mem_block - 1) { + val_print(AVS_PRINT_ERR, + "\nRAS2_GET_MEM_INFO: Index (%d) is greater than num of RAS2 mem blocks\n", + index); + return INVALID_RAS2_INFO; + } + + /* Go through the table return the relevant field value for RAS2 memory info block */ + /* at the index position */ + block = &g_ras2_info_table->blocks[0]; + for (i = 0; i < g_ras2_info_table->num_all_block; i++, block++) { + if (block->type == RAS2_FEATURE_TYPE_MEMORY) { + if (j == index) { + switch (type) { + case RAS2_PROX_DOMAIN: + return block->block_info.mem_feat_info.proximity_domain; + case RAS2_SCRUB_SUPPORT: + return block->block_info.mem_feat_info.patrol_scrub_support; + default: + val_print(AVS_PRINT_ERR, + "\nThis RAS2 memory info option not supported: %d \n", type); + return INVALID_RAS2_INFO; + } + } + j++; + } + } + return INVALID_RAS2_INFO; +} + +/** + @brief This API will be used to Read RAS Registers based on interface + 1. Caller - Test layer. + 2. Prerequisite - val_ras_create_info_table. + @param node_index RAS Node Index + @param reg Register to read. + @param err_rec_idx Error record index (required for record specific registers). + @return register read value or INVALID_RAS_REG_VAL if failure +**/ +uint64_t +val_ras_reg_read(uint32_t node_index, uint32_t reg, uint32_t err_rec_idx) +{ + uint64_t base, value = INVALID_RAS_REG_VAL; + uint32_t start_rec_index, offset; + uint64_t num_err_recs, err_rec_impl_bitmap; + + start_rec_index = g_ras_info_table->node[node_index].intf_info.start_rec_index; + + /* err_rec_idx = 0 means the first error record of the node */ + if (err_rec_idx == 0) + err_rec_idx = start_rec_index; + + /* Check if err record index is valid */ + val_ras_get_info(RAS_INFO_NUM_ERR_REC, node_index, &num_err_recs); + if ((err_rec_idx - start_rec_index) >= num_err_recs) { + val_print(AVS_PRINT_ERR, + "\n RAS_REG_READ : Invalid Input error record index(%d)\n", err_rec_idx); + return INVALID_RAS_REG_VAL; + } + + /* check if err record is implemented for given node index*/ + val_ras_get_info(RAS_INFO_ERR_REC_IMP, node_index, &err_rec_impl_bitmap); + + if ((err_rec_impl_bitmap >> err_rec_idx) & 0x1) { + val_print(AVS_PRINT_ERR, + "\n RAS_REG_READ : Error record index(%d) is unimplemented ", err_rec_idx); + val_print(AVS_PRINT_ERR, + "for node with index: %d \n", node_index); + return INVALID_RAS_REG_VAL; + } + + if (g_ras_info_table->node[node_index].intf_info.intf_type == RAS_INTF_TYPE_MMIO) { + /* MMIO based RAS register read */ + + /* Get the Base address for this node */ + base = g_ras_info_table->node[node_index].intf_info.base_addr; + + switch (reg) { + case RAS_ERR_FR: + /* ERRFR RAS register of first standard error record is + shared across multiple error records if exists */ + offset = ERR_FR_OFFSET + (64 * start_rec_index); + break; + case RAS_ERR_CTLR: + /* ERRCTLR RAS register of first standard error record is + shared across multiple error records if exists */ + offset = ERR_CTLR_OFFSET + (64 * start_rec_index); + break; + case RAS_ERR_STATUS: + offset = ERR_STATUS_OFFSET + (64 * err_rec_idx); + break; + case RAS_ERR_ADDR: + offset = ERR_ADDR_OFFSET + (64 * err_rec_idx); + break; + case RAS_ERR_PFGCDN: + /* ERRPFGCDN RAS register is valid only for first error record */ + if (err_rec_idx == start_rec_index) + offset = ERR_PFGCDN_OFFSET + (64 * start_rec_index); + else { + val_print(AVS_PRINT_ERR, + "\n RAS_REG_READ : ERR<%d>PFGCDN is RES0 for node index :", err_rec_idx); + val_print(AVS_PRINT_ERR, " %d", node_index); + return INVALID_RAS_REG_VAL; + } + break; + case RAS_ERR_PFGCTL: + /* ERRPFGCTL RAS register is valid only for first error record */ + if (err_rec_idx == start_rec_index) + offset = ERR_PFGCTL_OFFSET + (64 * start_rec_index); + else { + val_print(AVS_PRINT_ERR, + "\n RAS_REG_READ : ERR<%d>PFGCTL is RES0 for node index :", err_rec_idx); + val_print(AVS_PRINT_ERR, " %d", node_index); + return INVALID_RAS_REG_VAL; + } + break; + case RAS_ERR_ERRDEVAFF: + /* only valid for MMIO interface */ + offset = ERR_ERRDEVAFF_OFFSET; + default: + break; + } + value = val_mmio_read(base + offset); + } else { + /* System register based read */ + + /* RAS registers reads with ERRSELR_EL1.SEL set to start error record index */ + AA64WriteErrSelr1(start_rec_index); + + switch (reg) { + case RAS_ERR_FR: + value = AA64ReadErrFr1(); + break; + case RAS_ERR_CTLR: + value = AA64ReadErrCtlr1(); + break; + case RAS_ERR_PFGCDN: + /* ERRPFGCDN RAS register is valid only for first error record */ + if (err_rec_idx == start_rec_index) + value = AA64ReadErrPfgcdn1(); + else { + val_print(AVS_PRINT_ERR, + "\n RAS_REG_READ : ERR<%d>PFGCDN is RES0 for the node index :", err_rec_idx); + val_print(AVS_PRINT_ERR, " %d", node_index); + return INVALID_RAS_REG_VAL; + } + break; + case RAS_ERR_PFGCTL: + /* ERRPFGCTL RAS register is valid only for first error record */ + if (err_rec_idx == start_rec_index) + value = AA64ReadErrPfgctl1(); + else { + val_print(AVS_PRINT_ERR, + "\n RAS_REG_READ : ERR<%d>PFGCTL is RES0 for the node index :", err_rec_idx); + val_print(AVS_PRINT_ERR, " %d", node_index); + return INVALID_RAS_REG_VAL; + } + break; + default: + break; + } + + /* RAS registers reads with ERRSELR_EL1.SEL set to current error record index + These registers are unique to given error record */ + AA64WriteErrSelr1(err_rec_idx); + + switch (reg) { + case RAS_ERR_STATUS: + value = AA64ReadErrStatus1(); + break; + case RAS_ERR_ADDR: + value = AA64ReadErrAddr1(); + break; + default: + break; + } + } + + return value; +} + +/** + @brief This API will be used to Write RAS Registers based on interface + 1. Caller - Test layer. + 2. Prerequisite - val_ras_create_info_table. + @param node_index RAS Node Index + @param reg Register to write. + @param write_data Value to write in reg + @return None +**/ +void +val_ras_reg_write(uint32_t node_index, uint32_t reg, uint64_t write_data) +{ + uint64_t base; + uint32_t rec_index, offset; + + rec_index = g_ras_info_table->node[node_index].intf_info.start_rec_index; + + if (g_ras_info_table->node[node_index].intf_info.intf_type == RAS_INTF_TYPE_MMIO) { + /* MMIO Based Write */ + + /* Get the Base address for this node */ + base = g_ras_info_table->node[node_index].intf_info.base_addr; + + switch (reg) { + case RAS_ERR_FR: + offset = ERR_FR_OFFSET + (64 * rec_index); + break; + case RAS_ERR_CTLR: + offset = ERR_CTLR_OFFSET + (64 * rec_index); + break; + case RAS_ERR_STATUS: + offset = ERR_STATUS_OFFSET + (64 * rec_index); + break; + case RAS_ERR_PFGCDN: + offset = ERR_PFGCDN_OFFSET + (64 * rec_index); + break; + case RAS_ERR_PFGCTL: + offset = ERR_PFGCTL_OFFSET + (64 * rec_index); + break; + default: + break; + } + + val_mmio_write(base + offset, write_data); + } else { + /* System register based Write */ + + /* Update ERRSELR_EL1.SEL to choose which record index to use */ + AA64WriteErrSelr1(rec_index); + + switch (reg) { + case RAS_ERR_CTLR: + AA64WriteErrCtlr1(write_data); + break; + case RAS_ERR_STATUS: + AA64WriteErrStatus1(write_data); + break; + case RAS_ERR_PFGCDN: + AA64WriteErrPfgcdn1(write_data); + break; + case RAS_ERR_PFGCTL: + AA64WriteErrPfgctl1(write_data); + break; + default: + break; + } + } +} + +/** + @brief Function for setting up the Error Environment + + @param in_param - Error Input Parameters. + @param *out_param - Parameters returned from platform to be used in the test. + + @return Status +**/ +uint32_t +val_ras_setup_error(RAS_ERR_IN_t in_param, RAS_ERR_OUT_t *out_param) +{ + uint32_t status = AVS_STATUS_FAIL; + uint32_t pfgctl_value = 0; + + /* Clear the ERR_STATUS for any previous error */ + val_ras_reg_write(in_param.node_index, RAS_ERR_STATUS, ERR_STATUS_CLEAR); + + /* Make Sure ERI/FHI is not enabled */ + val_ras_reg_write(in_param.node_index, RAS_ERR_CTLR, 0); + + /* Enable fault injection: ERRCTLR.ED=1 */ + val_ras_reg_write(in_param.node_index, RAS_ERR_CTLR, ERR_CTLR_ED_ENABLE); + + /* Check if Pseudo Fault needs to test */ + if (in_param.is_pfg_check) + { + /* Write Counter in ERRPFGCDN */ + val_ras_reg_write(in_param.node_index, RAS_ERR_PFGCDN, 0x5); + + /* Write to ERRPFGCTL.* To Enable Error */ + switch (in_param.ras_error_type) { + case ERR_UC: + pfgctl_value = ERR_PFGCTL_UC_ENABLE; + break; + case ERR_DE: + pfgctl_value = ERR_PFGCTL_DE_ENABLE; + break; + case ERR_CE: + pfgctl_value = ERR_PFGCTL_CE_NON_ENABLE; + break; + case ERR_CRITICAL: + pfgctl_value = ERR_PFGCTL_CI_ENABLE; + break; + default: + break; + } + val_ras_reg_write(in_param.node_index, RAS_ERR_PFGCTL, pfgctl_value); + + return AVS_STATUS_PASS; + } + + /* Platform defined way of error setup */ + status = pal_ras_setup_error(in_param, out_param); + return status; +} + +/** + @brief Platform Defined way of Timeout/Wait loop + + @param count - Timeout/Wait Multiplier. + + @return None +**/ +void +val_ras_wait_timeout(uint32_t count) +{ + pal_ras_wait_timeout(count); +} + +void +ras_pfg_access_node(uint32_t node_index) +{ + uint64_t reg_value; + + /* Loop for Wait */ + val_ras_wait_timeout(1); + + /* Access to the Node register, Might need an imp def way here */ + reg_value = val_ras_reg_read(node_index, RAS_ERR_CTLR, 0); + if (reg_value == INVALID_RAS_REG_VAL) { + val_print(AVS_PRINT_ERR, + "\n Couldn't read ERR<0>CTLR register for RAS node index: 0x%lx", + node_index); + } + + val_print(AVS_PRINT_INFO, " Access RAS Node, CTLR : 0x%llx \n", reg_value); +} + +/** + @brief Function for injecting the Error + + @param in_param - Error Input Parameters. + @param *out_param - Parameters returned from platform to be used in the test. + + @return Status +**/ +uint32_t +val_ras_inject_error(RAS_ERR_IN_t in_param, RAS_ERR_OUT_t *out_param) +{ + uint32_t status = AVS_STATUS_FAIL; + uint64_t reg_value; + + /* Check if Pseudo Fault needs to test */ + if (in_param.is_pfg_check) + { + /* Write to ERRPFGCTL.CDNEN */ + reg_value = val_ras_reg_read(in_param.node_index, RAS_ERR_PFGCTL, in_param.rec_index); + + if (reg_value == INVALID_RAS_REG_VAL) { + val_print(AVS_PRINT_ERR, + "\n Couldn't read ERR<%d>PFGCTL register for ", + in_param.rec_index); + val_print(AVS_PRINT_ERR, + "RAS node index: 0x%lx", + in_param.node_index); + return AVS_STATUS_FAIL; + } + + val_ras_reg_write(in_param.node_index, RAS_ERR_PFGCTL, reg_value | ERR_PFGCTL_CDNEN_ENABLE); + + /* Wait and Access to Node */ + ras_pfg_access_node(in_param.node_index); + + return AVS_STATUS_PASS; + } + + /* Platform Defined Way of Error Injection */ + status = pal_ras_inject_error(in_param, out_param); + + return status; +} + +/** + @brief Function to check the Error Record Status + + @param node_index - RAS Node index in the info table. + @param error_type - RAS Error Type. + + @return Status +**/ +uint32_t val_ras_check_err_record(uint32_t node_index, uint32_t error_type) +{ + uint32_t status = AVS_STATUS_PASS; + uint64_t err_status; + uint32_t err_type_mask; + + /* Loop for Wait */ + val_ras_wait_timeout(1); + + err_status = val_ras_reg_read(node_index, RAS_ERR_STATUS, 0); + if (err_status == INVALID_RAS_REG_VAL) { + val_print(AVS_PRINT_ERR, + "\n Couldn't read ERR<0>STATUS register for RAS node index: 0x%lx", + node_index); + return AVS_STATUS_FAIL; + } + + /* Check Status Register Validity in Ras Node */ + if (!(err_status & ERR_STATUS_V_MASK)) { + val_print(AVS_PRINT_DEBUG, "\n Status Reg Not Valid, for node %d", node_index); + status = AVS_STATUS_FAIL; + } + + switch (error_type) { + case ERR_UC: + err_type_mask = ERR_STATUS_UE_MASK; + break; + case ERR_DE: + err_type_mask = ERR_STATUS_DE_MASK; + break; + case ERR_CE: + err_type_mask = ERR_STATUS_CE_MASK; + break; + case ERR_CRITICAL: + err_type_mask = ERR_STATUS_CI_MASK; + break; + default: + break; + } + + /* Check Error Bit in Ras Node */ + if (!(err_status & err_type_mask)) { + val_print(AVS_PRINT_DEBUG, "\n ERR Status Type Fail, for node %d", node_index); + status = AVS_STATUS_FAIL; + } + + return status; +} + +/** + @brief API to check support for Poison + + @param None + + @return 0 - Poison storage & forwarding not supported + 1 - Poison storage & forwarding supported +**/ +uint32_t val_ras_check_plat_poison_support(void) +{ + return pal_ras_check_plat_poison_support(); +} From b049f8a26e87ce788090babd51df06765fb4bc8f Mon Sep 17 00:00:00 2001 From: Rajat Goyal Date: Thu, 12 Jan 2023 19:31:20 +0530 Subject: [PATCH 3/8] val/pal : SBSA 7.1 Changes - Added val layer api's for RAS, MPAM, PMU. - Bug Fix for Peripheral dump info - Added SRAT, HMAT, AEST, RAS2, PPTT ACPI Parsing code. Signed-off-by: Rajat Goyal --- platform/pal_uefi/SbsaPalLib.inf | 6 +- platform/pal_uefi/SbsaPalNistLib.inf | 6 +- platform/pal_uefi/include/pal_mpam.h | 67 ++++ platform/pal_uefi/include/pal_pmu.h | 76 ++++ platform/pal_uefi/include/pal_ras.h | 80 ++++ platform/pal_uefi/include/pal_uefi.h | 314 +++++++++++++++- platform/pal_uefi/src/pal_acpi.c | 241 +++++++++++- platform/pal_uefi/src/pal_gic.c | 5 +- platform/pal_uefi/src/pal_hmat.c | 256 +++++++++++++ platform/pal_uefi/src/pal_iovirt.c | 27 +- platform/pal_uefi/src/pal_misc.c | 51 ++- platform/pal_uefi/src/pal_mpam.c | 263 +++++++++++++ platform/pal_uefi/src/pal_pcie.c | 11 +- platform/pal_uefi/src/pal_pe.c | 273 +++++++++++++- platform/pal_uefi/src/pal_peripherals.c | 8 +- platform/pal_uefi/src/pal_pmu.c | 216 +++++++++++ platform/pal_uefi/src/pal_ras.c | 472 ++++++++++++++++++++++++ platform/pal_uefi/src/pal_timer_wd.c | 5 +- uefi_app/SbsaAvs.inf | 4 - uefi_app/SbsaAvsNist.inf | 4 - val/SbsaValLib.inf | 11 +- val/SbsaValNistLib.inf | 22 +- val/include/sbsa_avs_exerciser.h | 2 +- val/include/sbsa_avs_gic.h | 6 +- val/include/sbsa_avs_iovirt.h | 4 +- val/include/sbsa_avs_pcie.h | 8 +- val/include/sbsa_avs_pcie_spec.h | 65 +++- val/include/sbsa_avs_pe.h | 12 +- val/include/sbsa_avs_peripherals.h | 4 +- val/include/sbsa_avs_pgt.h | 17 +- val/include/sbsa_avs_smmu.h | 20 +- val/include/sbsa_avs_timer.h | 2 +- val/include/sbsa_avs_wd.h | 8 +- val/include/val_interface.h | 158 +++++++- val/src/AArch64/PeRegSysSupport.S | 8 +- val/src/avs_gic.c | 12 +- val/src/avs_iovirt.c | 166 ++++++++- val/src/avs_pcie.c | 88 +++-- val/src/avs_pe.c | 40 ++ val/src/avs_pe_infra.c | 205 ++++++++++ val/src/avs_peripherals.c | 63 ++-- val/src/avs_pgt.c | 41 +- val/src/avs_smmu.c | 65 ++-- val/src/avs_timer.c | 56 +-- val/src/avs_timer_support.c | 12 +- val/src/avs_wakeup.c | 9 +- val/src/avs_wd.c | 8 +- 47 files changed, 3203 insertions(+), 294 deletions(-) create mode 100644 platform/pal_uefi/include/pal_mpam.h create mode 100644 platform/pal_uefi/include/pal_pmu.h create mode 100644 platform/pal_uefi/include/pal_ras.h create mode 100644 platform/pal_uefi/src/pal_hmat.c create mode 100644 platform/pal_uefi/src/pal_mpam.c create mode 100644 platform/pal_uefi/src/pal_pmu.c create mode 100644 platform/pal_uefi/src/pal_ras.c diff --git a/platform/pal_uefi/SbsaPalLib.inf b/platform/pal_uefi/SbsaPalLib.inf index 759f880a..71e7194a 100644 --- a/platform/pal_uefi/SbsaPalLib.inf +++ b/platform/pal_uefi/SbsaPalLib.inf @@ -1,5 +1,5 @@ ## @file -# Copyright (c) 2016-2021, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -39,6 +39,10 @@ src/pal_peripherals.c src/pal_exerciser.c src/pal_smmu.c + src/pal_hmat.c + src/pal_pmu.c + src/pal_mpam.c + src/pal_ras.c [Packages] ArmPkg/ArmPkg.dec diff --git a/platform/pal_uefi/SbsaPalNistLib.inf b/platform/pal_uefi/SbsaPalNistLib.inf index c75909b7..025fc610 100644 --- a/platform/pal_uefi/SbsaPalNistLib.inf +++ b/platform/pal_uefi/SbsaPalNistLib.inf @@ -1,5 +1,5 @@ ## @file -# Copyright (c) 2020-2021, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2020-2023, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -40,6 +40,10 @@ src/pal_exerciser.c src/pal_smmu.c src/pal_nist.c + src/pal_hmat.c + src/pal_pmu.c + src/pal_mpam.c + src/pal_ras.c [Packages] diff --git a/platform/pal_uefi/include/pal_mpam.h b/platform/pal_uefi/include/pal_mpam.h new file mode 100644 index 00000000..a63b23d0 --- /dev/null +++ b/platform/pal_uefi/include/pal_mpam.h @@ -0,0 +1,67 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. +**/ + +#ifndef __PAL_MPAM_H__ +#define __PAL_MPAM_H__ + +/* Not defined in EDK2: Remove once EDK2 supports MPAM*/ +#define MEMORY_RESOURCE_PARTITIONING_AND_MONITORING_TABLE_SIGNATURE SIGNATURE_32('M', 'P', 'A', 'M') + +#pragma pack(1) + +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER header; +} EFI_ACPI_MPAM_TABLE; + +typedef struct { + UINT16 length; + UINT16 reserved; + UINT32 identifier; + UINT64 base_address; + UINT32 mmio_size; + UINT32 overflow_interrupt; + UINT32 overflow_int_flags; + UINT32 reserved1; + UINT32 overflow_int_aff; + UINT32 error_interrupt; + UINT32 error_int_flags; + UINT32 reserved2; + UINT32 error_int_aff; + UINT32 max_nrdy_usec; + UINT64 hardware_id; + UINT32 instance_id; + UINT32 num_resource_nodes; +} EFI_ACPI_MPAM_MSC_NODE_STRUCTURE; + +typedef struct { + UINT32 identifier; + UINT8 ris_index; + UINT16 reserved1; + UINT8 locator_type; + UINT64 descriptor1; + UINT32 descriptor2; + UINT32 num_dependencies; +} EFI_ACPI_MPAM_RESOURCE_NODE_STRUCTURE; + +typedef struct { + UINT32 producer; + UINT32 reserved; +} EFI_ACPI_MPAM_FUNC_DEPEN_DESC_STRUCTURE; + +#pragma pack() + +#endif diff --git a/platform/pal_uefi/include/pal_pmu.h b/platform/pal_uefi/include/pal_pmu.h new file mode 100644 index 00000000..35ff2b59 --- /dev/null +++ b/platform/pal_uefi/include/pal_pmu.h @@ -0,0 +1,76 @@ +/** @file + * Copyright (c) 2022-2023, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. +**/ + +#ifndef __PAL_PMU_H__ +#define __PAL_PMU_H__ + +/* Not defined APMT related structures and defines in EDK2, + * Remove this header once EDK2 supports APMT */ + +#define ARM_PERFORMANCE_MONITORING_TABLE_SIGNATURE SIGNATURE_32('A', 'P', 'M', 'T') + +typedef enum { + PMU_EVENT_IB_TOTAL_BW, /* Inbound total bandwidth */ + PMU_EVENT_OB_TOTAL_BW, /* Outbound total bandwidth */ + PMU_EVENT_IB_READ_BW, /* Inbound read bandwidth */ + PMU_EVENT_IB_WRITE_BW, /* Inbound write bandwidth */ + PMU_EVENT_OB_READ_BW, /* Outbound read bandwidth */ + PMU_EVENT_OB_WRITE_BW, /* Outbound write bandwidth */ + PMU_EVENT_IB_OPEN_TXN, /* Inbound open transactions */ + PMU_EVENT_IB_TOTAL_TXN, /* Inbound total transactions */ + PMU_EVENT_OB_OPEN_TXN, /* Outbound open transactions */ + PMU_EVENT_OB_TOTAL_TXN, /* Outbound total transactions */ + PMU_EVENT_LOCAL_BW, /* Local traffic bandwidth */ + PMU_EVENT_REMOTE_BW, /* Remote traffic bandwidth */ + PMU_EVENT_ALL_BW, /* All traffic bandwidth */ + PMU_EVENT_TRAFFIC_1, /* traffic type 1 */ + PMU_EVENT_TRAFFIC_2 /* traffic type 2 */ +} PMU_EVENT_TYPE_e; + +typedef enum { + PMU_NODE_MEM_CNTR, + PMU_NODE_SMMU, + PMU_NODE_PCIE_RC, + PMU_NODE_ACPI_DEVICE, + PMU_NODE_PE_CACHE +} PMU_NODE_INFO_TYPE; + +#define PMU_EVENT_INVALID 0xFFFFFFFF + +#pragma pack(1) + +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER header; +} APMT_TABLE; + +typedef struct { + UINT16 length; + UINT8 flags; + UINT8 type; + UINT32 identifier; + UINT64 primary_instance; + UINT32 secondary_instance; + UINT64 base_addr0; + UINT64 base_addr1; + UINT32 interrupt; + UINT32 reserved; + UINT32 interrupt_flags; + UINT32 affinity; + UINT32 implementation_id; +} APMT_NODE; + +#endif diff --git a/platform/pal_uefi/include/pal_ras.h b/platform/pal_uefi/include/pal_ras.h new file mode 100644 index 00000000..9205743a --- /dev/null +++ b/platform/pal_uefi/include/pal_ras.h @@ -0,0 +1,80 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. +**/ + +#ifndef __PAL_RAS_H__ +#define __PAL_RAS_H__ + +#pragma pack(1) + +#define MAX_NUM_OF_RAS_SUPPORTED 140 + +typedef union { + EFI_ACPI_AEST_PROCESSOR_STRUCT Proc; + EFI_ACPI_AEST_MEMORY_CONTROLLER_STRUCT Mem; + EFI_ACPI_AEST_SMMU_STRUCT Smmu; + EFI_ACPI_AEST_VENDOR_DEFINED_STRUCT Vendor; + EFI_ACPI_AEST_GIC_STRUCT Gic; +} AEST_NODE_RESOURCE; + +typedef struct { + AEST_NODE_RESOURCE NodeResource; + EFI_ACPI_AEST_INTERFACE_STRUCT NodeInterface; + EFI_ACPI_AEST_INTERRUPT_STRUCT NodeInterrupt[2]; +} AEST_NODE; + +typedef struct { + EFI_ACPI_ARM_ERROR_SOURCE_TABLE Header; + AEST_NODE node[]; +} AEST_TABLE; + + +/* RAS2 Feature ACPI Table Structures and Definitions*/ + +/* EDK2 doesn't define RAS2 table signature and structures, remove and use EDK2 definitions + once EDK2 extends support */ + +#define EFI_ACPI_6_5_RAS2_FEATURE_TABLE_SIGNATURE SIGNATURE_32('R', 'A', 'S', '2') +#define RAS2_FEATURE_TYPE_MEMORY 0x0 +#define RAS2_PLATFORM_FEATURE_PATROL_SCRUB_BITMASK 0x1ULL + +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT16 Reserved; + UINT16 NumOfPccDescriptors; +} RAS_FEATURE_2_TABLE_HEADER; + +typedef struct { + UINT8 PccIdentifier; + UINT16 Reserved; + UINT8 FeatureType; + UINT32 Instance; +} RAS2_PCC_DESCRIPTOR; + +typedef struct { + UINT32 Signature; + UINT16 Command; + UINT16 Status; + UINT16 Version; + UINT64 RasFeatures[2]; + UINT64 SetRasCapabilities[2]; + UINT16 NumOfRas2ParameterBlocks; + UINT32 SetRasCapabilitiesStatus; +} RAS2_PCC_SHARED_MEMORY_REGION; + +#pragma pack() + +#endif diff --git a/platform/pal_uefi/include/pal_uefi.h b/platform/pal_uefi/include/pal_uefi.h index bb37a96e..187c7b35 100644 --- a/platform/pal_uefi/include/pal_uefi.h +++ b/platform/pal_uefi/include/pal_uefi.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -60,6 +60,9 @@ extern UINT32 g_pcie_cache_present; #define BAR_MT_SHIFT 3 #define BAR_BASE_SHIFT 4 +#define PLATFORM_TIMEOUT_MEDIUM 0x1000 +#define PLATFORM_TIMEOUT_SMALL 0x10 + typedef enum { MMIO = 0, IO = 1 @@ -83,6 +86,7 @@ typedef struct { #define sbsa_print(verbose, string, ...) if(verbose >= g_print_level) \ Print(string, ##__VA_ARGS__) +UINT64 pal_get_acpi_table_ptr(UINT32 table_signature); /** Conduits for service calls (SMC vs HVC). @@ -99,12 +103,17 @@ typedef struct { /** @brief structure instance for PE entry **/ +#define DEFAULT_CACHE_IDX 0xFFFFFFFF +#define MAX_L1_CACHE_RES 2 /* Generally PE Level 1 have a data and a instruction cache */ + typedef struct { - UINT32 pe_num; ///< PE Index - UINT32 attr; ///< PE attributes - UINT64 mpidr; ///< PE MPIDR - UINT32 pmu_gsiv; ///< PMU Interrupt ID + UINT32 pe_num; /* PE Index */ + UINT32 attr; /* PE attributes */ + UINT64 mpidr; /* PE MPIDR */ + UINT32 pmu_gsiv; /* PMU Interrupt */ UINT32 gmain_gsiv; /* GIC Maintenace Interrupt */ + UINT32 acpi_proc_uid; /* ACPI Processor UID */ + UINT32 level_1_res[MAX_L1_CACHE_RES]; /* index of level 1 cache(s) in cache_info_table */ }PE_INFO_ENTRY; typedef struct { @@ -266,7 +275,7 @@ typedef struct { UINT64 base; UINT32 overflow_gsiv; UINT32 node_ref; -} IOVIRT_PMCG_INFO_BLOCK; +}IOVIRT_PMCG_INFO_BLOCK; typedef enum { IOVIRT_NODE_ITS_GROUP = 0x00, @@ -287,7 +296,8 @@ typedef struct { UINT32 input_base; UINT32 id_count; UINT32 output_base; - UINT32 output_ref; + UINT32 output_ref; /* output ref captured here is offset to iovirt block in + IOVIRT info table not IORT ACPI table in memory */ }ID_MAP; typedef union { @@ -297,8 +307,14 @@ typedef union { #define MAX_NAMED_COMP_LENGTH 256 +typedef struct { + UINT64 smmu_base; /* SMMU base to which component is attached, else NULL */ + UINT32 cca; /* Cache Coherency Attribute */ + CHAR8 name[MAX_NAMED_COMP_LENGTH]; /* Device object name */ +} IOVIRT_NAMED_COMP_INFO_BLOCK; + typedef union { - CHAR8 name[MAX_NAMED_COMP_LENGTH]; + IOVIRT_NAMED_COMP_INFO_BLOCK named_comp; IOVIRT_RC_INFO_BLOCK rc; IOVIRT_PMCG_INFO_BLOCK pmcg; UINT32 its_count; @@ -454,4 +470,286 @@ UINT64 pal_memory_get_unpopulated_addr(UINT64 *addr, UINT32 instance); UINT32 pal_pe_get_num(); +/** + @brief Instance of system pmu info +**/ +typedef struct { + UINT8 type; /* The component that this PMU block is associated with*/ + UINT64 primary_instance; /* Primary node instance, specific to the PMU type*/ + UINT32 secondary_instance; /* Secondary node instance, specific to the PMU type*/ + UINT8 dual_page_extension; /* Support of the dual-page mode*/ + UINT64 base0; /* Base address of Page 0 of the PMU*/ + UINT64 base1; /* Base address of Page 1 of the PMU, + valid only if dual_page_extension is 1*/ +} PMU_INFO_BLOCK; + +typedef struct { + UINT32 pmu_count; /* Total number of PMU info blocks*/ + PMU_INFO_BLOCK info[]; /* PMU info blocks for each PMU nodes*/ +} PMU_INFO_TABLE; + +/* + * @brief Mpam Resource Node + */ +typedef struct { + UINT8 ris_index; + UINT8 locator_type; /* Identifies location of this resource */ + UINT64 descriptor1; /* Primary acpi description of location */ + UINT32 descriptor2; /* Secondary acpi description of location */ +} MPAM_RESOURCE_NODE; + +/* + * @brief Mpam MSC Node + */ +typedef struct { + UINT64 msc_base_addr; /* base addr of mem-map MSC reg */ + UINT32 msc_addr_len; /* MSC mem map size */ + UINT32 max_nrdy; /* max time in microseconds that MSC not ready + after config change */ + UINT32 rsrc_count; /* number of resource nodes */ + MPAM_RESOURCE_NODE rsrc_node[]; /* Details of resource node */ +} MPAM_MSC_NODE; + +/* + * @brief Mpam info table + */ + +#define MPAM_NEXT_MSC(msc_entry) \ + (MPAM_MSC_NODE *)((UINT8 *)(&msc_entry->rsrc_node[0]) \ + + msc_entry->rsrc_count * sizeof(MPAM_RESOURCE_NODE)) + +typedef struct { + UINT32 msc_count; /* Number of MSC node */ + MPAM_MSC_NODE msc_node[]; /* Details of MSC node */ +} MPAM_INFO_TABLE; + +/** + @brief SRAT node type +**/ + +typedef enum { + SRAT_NODE_MEM_AFF = 0x01, + SRAT_NODE_GICC_AFF = 0x03 +} SRAT_NODE_TYPE_e; + +/** + @brief SRAT GICC Affinity Structure +**/ + +typedef struct { + UINT32 prox_domain; /* Proximity domain*/ + UINT32 proc_uid; /* ACPI Processor UID */ + UINT32 flags; /* Flags*/ + UINT32 clk_domain; /* Clock Domain*/ +} SRAT_GICC_AFF_ENTRY; + +/** + @brief SRAT Memory Affinity Structure +**/ + +typedef struct { + UINT32 prox_domain; /* Proximity domain */ + UINT32 flags; /* flags */ + UINT64 addr_base; /* mem range address base */ + UINT64 addr_len; /* mem range address len */ +} SRAT_MEM_AFF_ENTRY; + +typedef union { + SRAT_MEM_AFF_ENTRY mem_aff; + SRAT_GICC_AFF_ENTRY gicc_aff; +} SRAT_NODE_INFO; + +typedef struct { + UINT32 node_type; /* Node type*/ + SRAT_NODE_INFO node_data; +} SRAT_INFO_ENTRY; + +typedef struct { + UINT32 num_of_srat_entries; + UINT32 num_of_mem_ranges; + SRAT_INFO_ENTRY srat_info[]; +} SRAT_INFO_TABLE; + +/* SRAT node structure header. Can be removed after it is defined in EDKII*/ +typedef struct { + UINT8 Type; + UINT8 Length; +} EFI_ACPI_6_4_SRAT_STRUCTURE_HEADER; + + +/* Cache info table structures and APIs */ + +#define CACHE_TYPE_SHARED 0x0 +#define CACHE_TYPE_PRIVATE 0x1 +#define CACHE_INVALID_NEXT_LVL_IDX 0xFFFFFFFF +#define CACHE_INVALID_IDX 0xFFFFFFFF + +/*only the fields and flags required by ACS are parsed from ACPI PPTT table*/ +/*Cache flags indicate validity of cache info provided by PPTT Table*/ +typedef struct { + UINT32 size_property_valid; + UINT32 cache_type_valid; + UINT32 cache_id_valid; +} CACHE_FLAGS; + +/* Since most of platform doesn't support cache id field (ACPI 6.4+), ACS uses PPTT offset as key + to uniquely identify a cache, In future once platforms align with ACPI 6.4+ my_offset member + might be removed from cache entry*/ +typedef struct { + CACHE_FLAGS flags; /* Cache flags */ + UINT32 my_offset; /* Cache PPTT structure offset */ + UINT32 next_level_index; /* Index of next level cache entry in CACHE_INFO_TABLE */ + UINT32 size; /* Size of the cache in bytes */ + UINT32 cache_id; /* Unique, non-zero identifier for this cache */ + UINT32 is_private; /* Field indicate whether cache is private */ + UINT8 cache_type; /* Cache type */ +} CACHE_INFO_ENTRY; + +typedef struct { + UINT32 num_of_cache; /* Total of number of cache info entries */ + CACHE_INFO_ENTRY cache_info[]; /* Array of cache info entries */ +} CACHE_INFO_TABLE; + +/* RAS Information */ + +typedef enum { + NODE_TYPE_PE = 0x0, + NODE_TYPE_MC = 0x1, + NODE_TYPE_SMMU = 0x2, + NODE_TYPE_VDR = 0x3, + NODE_TYPE_GIC = 0x4, + NODE_TYPE_LAST_ENTRY +} RAS_NODE_TYPE_e; + +typedef enum { + RAS_INTF_TYPE_SYS_REG, /* System register RAS node interface type */ + RAS_INTF_TYPE_MMIO /* MMIO RAS node interface type */ +} RAS_NODE_INTF_TYPE; +typedef struct { + UINT32 processor_id; + UINT32 resource_type; + UINT32 flags; + UINT64 affinity; + UINT64 res_specific_data; /* Resource Specific Data */ +} RAS_NODE_PE_DATA; + +typedef struct { + UINT32 proximity_domain; +} RAS_NODE_MC_DATA; + +typedef struct { + RAS_NODE_INTF_TYPE intf_type; /* Interface Type */ + UINT32 flags; + UINT64 base_addr; /* Base address to MMIO region, valid for MMIO intf type */ + UINT32 start_rec_index; /* Start Record Index */ + UINT32 num_err_rec; /* Number of error records (implemented & unimplemented)*/ + UINT64 err_rec_implement; /* bitmap of error records implemented */ + UINT64 err_status_reporting; /* bitmap indicates which error records within this error + node support error status reporting using ERRGSR */ + UINT64 addressing_mode; /* bitmap based policy for ERRADDR field of error records */ +} RAS_INTERFACE_INFO; + +typedef struct { + UINT32 type; + UINT32 flag; + UINT32 gsiv; + UINT32 its_grp_id; +} RAS_INTERRUPT_INFO; + +typedef union { + RAS_NODE_PE_DATA pe; + RAS_NODE_MC_DATA mc; +} RAS_NODE_DATA; + +typedef struct { + RAS_NODE_TYPE_e type; /* Node Type PE/GIC/SMMU */ + UINT16 length; /* Length of the Node */ + UINT64 num_intr_entries; /* Number of Interrupt Entry */ + RAS_NODE_DATA node_data; /* Node Specific Data */ + RAS_INTERFACE_INFO intf_info; /* Node Interface Info */ + RAS_INTERRUPT_INFO intr_info[2]; /* Node Interrupt Info */ +} RAS_NODE_INFO; + +typedef struct { + UINT32 num_nodes; /* Number of total RAS Nodes */ + UINT32 num_pe_node; /* Number of PE RAS Nodes */ + UINT32 num_mc_node; /* Number of Memory Controller Nodes */ + RAS_NODE_INFO node[]; /* Array of RAS nodes */ +} RAS_INFO_TABLE; + +typedef enum { + ERR_UC = 0x1, /* Uncorrectable Error */ + ERR_DE, /* Deferred Error */ + ERR_CE, /* Correctable Error */ + ERR_CRITICAL, /* Critical Error */ + ERR_CONTAINABLE /* Containable Error */ +} RAS_ERROR_TYPE; + +typedef struct { + RAS_ERROR_TYPE ras_error_type; /* Error Type */ + UINT64 error_pa; /* Error Phy Address */ + UINT32 rec_index; /* Error Record Index */ + UINT32 node_index; /* Error Node Index in Info table */ + UINT8 is_pfg_check; /* Pseudo Fault Check or not */ +} RAS_ERR_IN_t; + +typedef struct { + UINT32 intr_id; /* Interrupt ID */ + UINT32 error_record; /* Error Record Number */ +} RAS_ERR_OUT_t; + +void pal_ras_create_info_table(RAS_INFO_TABLE *ras_info_table); +UINT32 pal_ras_setup_error(RAS_ERR_IN_t in_param, RAS_ERR_OUT_t *out_param); +UINT32 pal_ras_inject_error(RAS_ERR_IN_t in_param, RAS_ERR_OUT_t *out_param); +void pal_ras_wait_timeout(UINT32 count); +UINT32 pal_ras_check_plat_poison_support(void); + + +typedef enum { + RAS2_TYPE_MEMORY = 0 /* RAS2 memory feature type*/ +} RAS2_FEAT_TYPE; + +typedef struct { + UINT32 proximity_domain; /* Proximity domain of the memory */ + UINT32 patrol_scrub_support; /* Patrol srub support flag */ +} RAS2_MEM_INFO; + +typedef union { + RAS2_MEM_INFO mem_feat_info; /* Memory feature specific info */ +} RAS2_BLOCK_INFO; + +typedef struct { + RAS2_FEAT_TYPE type; /* RAS2 feature type*/ + RAS2_BLOCK_INFO block_info; /* RAS2 block info */ +} RAS2_BLOCK; + +typedef struct { + UINT32 num_all_block; /* Number of RAS2 feature blocks */ + UINT32 num_of_mem_block; /* Number of memory feature blocks */ + RAS2_BLOCK blocks[]; +} RAS2_INFO_TABLE; + +void pal_ras2_create_info_table(RAS2_INFO_TABLE *ras2_info_table); + +/* HMAT info table structures and APIs*/ + +#define HMAT_MEM_HIERARCHY_MEMORY 0x00 +#define HMAT_DATA_TYPE_ACCESS_BW 0x03 +#define HMAT_DATA_TYPE_READ_BW 0x04 +#define HMAT_DATA_TYPE_WRITE_BW 0x05 +#define HMAT_BW_ENTRY_UNREACHABLE 0xFFFF +#define HMAT_BASE_UNIT_48BIT 0xFFFFFFFFFFFFULL +typedef struct { + UINT32 mem_prox_domain; /* Proximity domain of the memory region*/ + UINT64 write_bw; /* Maximum write bandwidth */ + UINT64 read_bw; /* Maximum read bandwidth */ +} HMAT_BW_ENTRY; + +typedef struct { + UINT32 num_of_mem_prox_domain; /* Number of Memory Proximity Domains */ + HMAT_BW_ENTRY bw_info[]; /* Array of bandwidth info based on proximity domain */ +} HMAT_INFO_TABLE; + +VOID pal_hmat_create_info_table(HMAT_INFO_TABLE *HmatTable); + #endif diff --git a/platform/pal_uefi/src/pal_acpi.c b/platform/pal_uefi/src/pal_acpi.c index 7327fffb..754d29d8 100644 --- a/platform/pal_uefi/src/pal_acpi.c +++ b/platform/pal_uefi/src/pal_acpi.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2020-2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2020-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -20,12 +20,11 @@ #include #include #include - -#include "Include/Guid/Acpi.h" -#include -#include "Include/IndustryStandard/Acpi61.h" +#include "Include/IndustryStandard/ArmErrorSourceTable.h" #include "include/pal_uefi.h" +#include "include/pal_pmu.h" +#include "include/pal_mpam.h" /** @brief Checks if System information is passed using Baremetal (BM) @@ -72,6 +71,39 @@ pal_get_xsdt_ptr() } +/** + @brief Iterate through the ACPI tables pointed by XSDT and return table address. + + @param table_signature Signature of the requested ACPI table. + + @return 64-bit ACPI table address if found, else zero is returned. +**/ +UINT64 +pal_get_acpi_table_ptr(UINT32 table_signature) +{ + + EFI_ACPI_DESCRIPTION_HEADER *Xsdt; + UINT64 *Entry64; + UINT32 Entry64Num; + UINT32 Idx; + + Xsdt = (EFI_ACPI_DESCRIPTION_HEADER *) pal_get_xsdt_ptr(); + if (Xsdt == NULL) { + sbsa_print(AVS_PRINT_ERR, L" XSDT not found \n"); + return 0; + } + + Entry64 = (UINT64 *)(Xsdt + 1); + Entry64Num = (Xsdt->Length - sizeof(EFI_ACPI_DESCRIPTION_HEADER)) >> 3; + for (Idx = 0; Idx < Entry64Num; Idx++) { + if (*(UINT32 *)(UINTN)(Entry64[Idx]) == table_signature) { + return(UINT64)(Entry64[Idx]); + } + } + + return 0; +} + /** @brief Iterate through the tables pointed by XSDT and return MADT address @@ -243,6 +275,205 @@ pal_get_iort_ptr() } +/** + @brief Iterate through the tables pointed by XSDT and return AEST Table address + + @param None + + @return 64-bit AEST address + **/ +UINT64 +pal_get_aest_ptr() +{ + EFI_ACPI_DESCRIPTION_HEADER *Xsdt; + UINT64 *Entry64; + UINT32 Entry64Num; + UINT32 Idx; + + Xsdt = (EFI_ACPI_DESCRIPTION_HEADER *) pal_get_xsdt_ptr(); + if (Xsdt == NULL) { + sbsa_print(AVS_PRINT_ERR, L" XSDT not found \n"); + return 0; + } + + Entry64 = (UINT64 *)(Xsdt + 1); + Entry64Num = (Xsdt->Length - sizeof(EFI_ACPI_DESCRIPTION_HEADER)) >> 3; + for (Idx = 0; Idx < Entry64Num; Idx++) { + if (*(UINT32 *)(UINTN)(Entry64[Idx]) == EFI_ACPI_6_3_ARM_ERROR_SOURCE_TABLE_SIGNATURE) { + return(UINT64)(Entry64[Idx]); + } + } + + return 0; +} + + /** + @brief Iterate through the tables pointed by XSDT and return APMT Table address + + @param None + + @return 64-bit APMT address + **/ +UINT64 +pal_get_apmt_ptr() +{ + EFI_ACPI_DESCRIPTION_HEADER *Xsdt; + UINT64 *Entry64; + UINT32 Entry64Num; + UINT32 Idx; + + Xsdt = (EFI_ACPI_DESCRIPTION_HEADER *) pal_get_xsdt_ptr(); + if (Xsdt == NULL) { + sbsa_print(AVS_PRINT_ERR, L" XSDT not found \n"); + return 0; + } + + Entry64 = (UINT64 *)(Xsdt + 1); + Entry64Num = (Xsdt->Length - sizeof(EFI_ACPI_DESCRIPTION_HEADER)) >> 3; + for (Idx = 0; Idx < Entry64Num; Idx++) { + if (*(UINT32 *)(UINTN)(Entry64[Idx]) == ARM_PERFORMANCE_MONITORING_TABLE_SIGNATURE) { + return(UINT64)(Entry64[Idx]); + } + } + + return 0; +} + +/** + @brief Iterate through the tables pointed by XSDT and return HMAT address + + @param None + + @return 64-bit HMAT address +**/ +UINT64 +pal_get_hmat_ptr(void) +{ + + EFI_ACPI_DESCRIPTION_HEADER *Xsdt; + UINT64 *Entry64; + UINT32 Entry64Num; + UINT32 Idx; + + Xsdt = (EFI_ACPI_DESCRIPTION_HEADER *) pal_get_xsdt_ptr(); + if (Xsdt == NULL) { + sbsa_print(AVS_PRINT_ERR, L" XSDT not found \n"); + return 0; + } + + Entry64 = (UINT64 *)(Xsdt + 1); + Entry64Num = (Xsdt->Length - sizeof(EFI_ACPI_DESCRIPTION_HEADER)) >> 3; + for (Idx = 0; Idx < Entry64Num; Idx++) { + if (*(UINT32 *)(UINTN)(Entry64[Idx]) == + EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE) { + return(UINT64)(Entry64[Idx]); + } + } + + return 0; +} + + /** + @brief Iterate through the tables pointed by XSDT and return MPAM Table address + + @param None + + @return 64-bit MPAM address + **/ +UINT64 +pal_get_mpam_ptr() +{ + EFI_ACPI_DESCRIPTION_HEADER *Xsdt; + UINT64 *Entry64; + UINT32 Entry64Num; + UINT32 Idx; + + Xsdt = (EFI_ACPI_DESCRIPTION_HEADER *) pal_get_xsdt_ptr(); + if (Xsdt == NULL) { + sbsa_print(AVS_PRINT_ERR, L" XSDT not found \n"); + return 0; + } + + Entry64 = (UINT64 *)(Xsdt + 1); + Entry64Num = (Xsdt->Length - sizeof(EFI_ACPI_DESCRIPTION_HEADER)) >> 3; + for (Idx = 0; Idx < Entry64Num; Idx++) { + if (*(UINT32 *)(UINTN)(Entry64[Idx]) == + MEMORY_RESOURCE_PARTITIONING_AND_MONITORING_TABLE_SIGNATURE) { + return(UINT64)(Entry64[Idx]); + } + } + + return 0; +} + +/** + @brief Iterate through the tables pointed by XSDT and return PPTT address + + @param None + + @return 64-bit PPTT address +**/ +UINT64 +pal_get_pptt_ptr(void) +{ + + EFI_ACPI_DESCRIPTION_HEADER *Xsdt; + UINT64 *Entry64; + UINT32 Entry64Num; + UINT32 Idx; + + Xsdt = (EFI_ACPI_DESCRIPTION_HEADER *) pal_get_xsdt_ptr(); + if (Xsdt == NULL) { + sbsa_print(AVS_PRINT_ERR, L" XSDT not found \n"); + return 0; + } + + Entry64 = (UINT64 *)(Xsdt + 1); + Entry64Num = (Xsdt->Length - sizeof(EFI_ACPI_DESCRIPTION_HEADER)) >> 3; + for (Idx = 0; Idx < Entry64Num; Idx++) { + if (*(UINT32 *)(UINTN)(Entry64[Idx]) == + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE) { + return(UINT64)(Entry64[Idx]); + } + } + + return 0; +} + +/** + @brief Iterate through the tables pointed by XSDT and return SRAT address + + @param None + + @return 64-bit SRAT address +**/ +UINT64 +pal_get_srat_ptr(void) +{ + + EFI_ACPI_DESCRIPTION_HEADER *Xsdt; + UINT64 *Entry64; + UINT32 Entry64Num; + UINT32 Idx; + + Xsdt = (EFI_ACPI_DESCRIPTION_HEADER *) pal_get_xsdt_ptr(); + if (Xsdt == NULL) { + sbsa_print(AVS_PRINT_ERR, L" XSDT not found \n"); + return 0; + } + + Entry64 = (UINT64 *)(Xsdt + 1); + Entry64Num = (Xsdt->Length - sizeof(EFI_ACPI_DESCRIPTION_HEADER)) >> 3; + for (Idx = 0; Idx < Entry64Num; Idx++) { + if (*(UINT32 *)(UINTN)(Entry64[Idx]) == + EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE) { + return(UINT64)(Entry64[Idx]); + } + } + + return 0; +} + /** @brief Iterate through the tables pointed by XSDT and return FADT Table address diff --git a/platform/pal_uefi/src/pal_gic.c b/platform/pal_uefi/src/pal_gic.c index 19a55748..d3d40af9 100644 --- a/platform/pal_uefi/src/pal_gic.c +++ b/platform/pal_uefi/src/pal_gic.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2021, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -19,9 +19,6 @@ #include #include #include - -#include "Include/IndustryStandard/Acpi61.h" -#include #include #include diff --git a/platform/pal_uefi/src/pal_hmat.c b/platform/pal_uefi/src/pal_hmat.c new file mode 100644 index 00000000..96a3aff6 --- /dev/null +++ b/platform/pal_uefi/src/pal_hmat.c @@ -0,0 +1,256 @@ +/** @file + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. +**/ + +#include +#include +#include +#include + +#include "include/pal_uefi.h" + +#define ADD_PTR(t, p, l) ((t*)((UINT8*)p + l)) + +UINT64 pal_get_hmat_ptr(); + +/** + @brief This function checks whether an entry already present for + a input proximity domain else creates new entry and returns the + index. + + @param HmatTable pointer to pre-allocated memory for hmat info table. + @param mem_prox_domain input memory proximity domain. + + @return Returns index to hmat bw_info_entry for input memory proximity domain. +**/ +UINT32 pal_hmat_get_entry_index(HMAT_INFO_TABLE *HmatTable, UINT32 mem_prox_domain) +{ + HMAT_BW_ENTRY *curr_entry; + UINT32 i; + + curr_entry = HmatTable->bw_info; + for (i = 0 ; i < HmatTable->num_of_mem_prox_domain ; i++) { + /* match mem_prox_domain of the entry with input prox_domain */ + if (curr_entry->mem_prox_domain == mem_prox_domain) { + return i; + } + curr_entry++; + } + + /* if no matching entry found, add the proximity domain to info table + and return the index*/ + curr_entry = &HmatTable->bw_info[HmatTable->num_of_mem_prox_domain]; + curr_entry->mem_prox_domain = mem_prox_domain; + curr_entry->write_bw = 0; /* initialize write bandwidth */ + curr_entry->read_bw = 0; /* initialize read bandwidth */ + HmatTable->num_of_mem_prox_domain++; + + return HmatTable->num_of_mem_prox_domain - 1; +} + +/** + @brief This function returns maximum bandwidth matrix entry for input + target proximity domain among all available initiator proximity domains. + + @param target_prox_index index of target proximity domain in SLLBI target domain list. + @param curr_bw_struct pointer to SLLBI HMAT structure. + + @return Returns maximum bandwidth matrix entry for input target_prox_index + and SLLBI HMAT structure. +**/ +UINT16 pal_hmat_get_max_bw_entry(UINT32 target_prox_index, +EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO *curr_bw_struct) +{ + UINT32 i, offset; + UINT16 max_bw_entry = 0; + UINT16 *bw_entry; + + /* calculate offset to first bandwidth matrix entry for passed target + proximity domain index in current HMAT structure and get */ + offset = sizeof(EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO) + + sizeof(UINT32) * curr_bw_struct->NumberOfInitiatorProximityDomains + + sizeof(UINT32) * curr_bw_struct->NumberOfTargetProximityDomains + + sizeof(UINT16) * target_prox_index; + bw_entry = ADD_PTR(UINT16, curr_bw_struct, offset); + + /* check all available Initiator Proximity Domains */ + for (i = 0 ; i < curr_bw_struct->NumberOfInitiatorProximityDomains ; i++) { + /* if entry value is 0xFFFF then the initiator and target domains are + unreachable from each other, hence ignoring the entry */ + if (*bw_entry == HMAT_BW_ENTRY_UNREACHABLE) { + bw_entry = bw_entry + curr_bw_struct->NumberOfTargetProximityDomains; + continue; + } + + if (max_bw_entry < *bw_entry) + max_bw_entry = *bw_entry; + + /* increment pointer to next intitiator target pair */ + bw_entry = bw_entry + curr_bw_struct->NumberOfTargetProximityDomains; + } + + return max_bw_entry; +} + +/** + @brief This function updates hmat info table after parsing input SLLBI HMAT structure + + @param HmatTable pointer to pre-allocated memory for hmat info table. + @param curr_bw_struct pointer to SLLBI HMAT structure. + + @return None +**/ +VOID pal_hmat_update_info(HMAT_INFO_TABLE *HmatTable, +EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO *curr_bw_struct) +{ + HMAT_BW_ENTRY *curr_info_entry; + UINT64 entry_base_unit, curr_max_bw; + UINT32 i, bw_info_index; + UINT32 *curr_tgt_prox_domain; + UINT16 curr_max_bw_entry; + + entry_base_unit = curr_bw_struct->EntryBaseUnit; + + if (entry_base_unit > HMAT_BASE_UNIT_48BIT) { + sbsa_print(AVS_PRINT_ERR, L"\nEntry Base unit exceeds 0x%llx Mbytes/s ", + HMAT_BASE_UNIT_48BIT); + sbsa_print(AVS_PRINT_ERR, L"\n BW info entries might overflow 64 bit boundary"); + } + + /* pointer to list of target proximity domains */ + curr_tgt_prox_domain = ADD_PTR(UINT32, curr_bw_struct, + (sizeof(EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO) + + 4 * curr_bw_struct->NumberOfInitiatorProximityDomains)); + + for (i = 0 ; i < curr_bw_struct->NumberOfTargetProximityDomains ; i++) { + /* get maximum bandwidth for curr_tgt_prox_domain among available initiator + proxmity domains */ + curr_max_bw_entry = pal_hmat_get_max_bw_entry(i, curr_bw_struct); + curr_max_bw = entry_base_unit * curr_max_bw_entry; + + sbsa_print(AVS_PRINT_INFO, L"\nMemory Proximity Domain : 0x%llx", *curr_tgt_prox_domain); + sbsa_print(AVS_PRINT_INFO, L"\nEntry Base Unit : 0x%llx", entry_base_unit); + sbsa_print(AVS_PRINT_INFO, L"\nMax Bandwidth entry : 0x%llx", curr_max_bw_entry); + sbsa_print(AVS_PRINT_INFO, L"\nMax Bandwidth : 0x%llx", curr_max_bw); + /* get index to HMAT info table entry for curr_tgt_prox_domain */ + bw_info_index = pal_hmat_get_entry_index(HmatTable, *curr_tgt_prox_domain); + /* pointer to HMAT info table entry curr_tgt_prox_domain */ + curr_info_entry = &HmatTable->bw_info[bw_info_index]; + + /* update the HMAT info table only if current seen bandwidth is + greater than previously seen bandwidth. HMAT allows table developer + to capture bandwidth for different scenarios */ + if (curr_bw_struct->DataType == HMAT_DATA_TYPE_ACCESS_BW || + curr_bw_struct->DataType == HMAT_DATA_TYPE_WRITE_BW ) { + if (curr_max_bw > curr_info_entry->write_bw) + curr_info_entry->write_bw = curr_max_bw; + } + + if (curr_bw_struct->DataType == HMAT_DATA_TYPE_ACCESS_BW || + curr_bw_struct->DataType == HMAT_DATA_TYPE_READ_BW ) { + if (curr_max_bw > curr_info_entry->read_bw) + curr_info_entry->read_bw = curr_max_bw; + } + /* point to next target proximity domain */ + curr_tgt_prox_domain++; + } +} + +/** + @brief This API prints hmat info table entries. + + @param HmatTable pointer to pre-allocated memory for hmat info table. + + @return None +**/ +VOID pal_hmat_dump_info_table(HMAT_INFO_TABLE *HmatTable) +{ + HMAT_BW_ENTRY *curr_entry; + UINT32 i; + + if (HmatTable == NULL) + return; + + curr_entry = HmatTable->bw_info; + sbsa_print(AVS_PRINT_INFO, L"\n*** HMAT info table entries ***\n"); + for (i = 0 ; i < HmatTable->num_of_mem_prox_domain ; i++) { + sbsa_print(AVS_PRINT_INFO, L"\nMemory Proximity domain : 0x%llx", curr_entry->mem_prox_domain); + sbsa_print(AVS_PRINT_INFO, L"\n Write bandwidth : 0x%llx", curr_entry->write_bw); + sbsa_print(AVS_PRINT_INFO, L"\n Read bandwidth : 0x%llx\n", curr_entry->read_bw); + curr_entry++; + } +} + +/** + @brief Parses ACPI HMAT table and populates the local hmat info table with + maximum read/write bandwidth for memory proximity domains. + + @param HmatTable pointer to pre-allocated memory for hmat info table. + + @return None +**/ +VOID pal_hmat_create_info_table(HMAT_INFO_TABLE *HmatTable) +{ + EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER *HmatHdr; + EFI_ACPI_6_4_HMAT_STRUCTURE_HEADER *hmat_struct, *hmat_end; + EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO *curr_bw_struct; + UINT32 TableLength = 0; + + if (HmatTable == NULL) { + sbsa_print(AVS_PRINT_ERR, L" Unable to create HMAT info table, input pointer is NULL \n"); + return; + } + + /* initialize hmat info table number of entries */ + HmatTable->num_of_mem_prox_domain = 0; + + HmatHdr = (EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER *) pal_get_hmat_ptr(); + if (HmatHdr == NULL) { + sbsa_print(AVS_PRINT_DEBUG, L" HMAT ACPI table not found\n"); + return; + } + else { + TableLength = HmatHdr->Header.Length; + sbsa_print(AVS_PRINT_INFO, L"HMAT ACPI table found at 0x%llx with length 0x%x\n", + HmatHdr, TableLength); + } + + /* pointer to first HMAT structure in ACPI table */ + /* HMAT table has 4 bytes addition to ACPI header to + make the HMAT structures 8 byte aligned */ + hmat_struct = ADD_PTR(EFI_ACPI_6_4_HMAT_STRUCTURE_HEADER, HmatHdr, + sizeof(EFI_ACPI_DESCRIPTION_HEADER) + 4); + + /* HMAT end boundary */ + hmat_end = ADD_PTR(EFI_ACPI_6_4_HMAT_STRUCTURE_HEADER, HmatHdr, TableLength); + /* iterate HMAT structs in HMAT ACPI table */ + while (hmat_struct < hmat_end) { + /* look for system locality latency and bandwidth info HMAT structure */ + if (hmat_struct->Type == EFI_ACPI_6_4_HMAT_TYPE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO) { + curr_bw_struct = ( + EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO *) hmat_struct; + /* update info table, if the data captured by structure is of type bandwidth */ + if (curr_bw_struct->Flags.MemoryHierarchy == HMAT_MEM_HIERARCHY_MEMORY) + if (curr_bw_struct->DataType == HMAT_DATA_TYPE_ACCESS_BW || + curr_bw_struct->DataType == HMAT_DATA_TYPE_WRITE_BW || + curr_bw_struct->DataType == HMAT_DATA_TYPE_READ_BW) + pal_hmat_update_info(HmatTable, curr_bw_struct); + } + /* point to next hmat structure*/ + hmat_struct = ADD_PTR(EFI_ACPI_6_4_HMAT_STRUCTURE_HEADER, hmat_struct, hmat_struct->Length); + } + pal_hmat_dump_info_table(HmatTable); +} diff --git a/platform/pal_uefi/src/pal_iovirt.c b/platform/pal_uefi/src/pal_iovirt.c index 7127bd79..485ff308 100644 --- a/platform/pal_uefi/src/pal_iovirt.c +++ b/platform/pal_uefi/src/pal_iovirt.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2019, 2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2019, 2021-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -19,12 +19,8 @@ #include #include #include - -#include #include -#include "Include/IndustryStandard/Acpi61.h" - #include "include/pal_uefi.h" #include "include/platform_override.h" #include "include/pal_iovirt.h" @@ -59,7 +55,8 @@ dump_block(IOVIRT_BLOCK *block) { return; case IOVIRT_NODE_NAMED_COMPONENT: sbsa_print(AVS_PRINT_INFO, - L" Named Component: Device Name:%a\n", block->data.name); + L" Named Component:\n Device Name:%a", block->data.named_comp.name); + sbsa_print(AVS_PRINT_INFO, L"\n CCA Attribute: 0x%lx\n", block->data.named_comp.cca); break; case IOVIRT_NODE_PCI_ROOT_COMPLEX: sbsa_print(AVS_PRINT_INFO, @@ -252,14 +249,17 @@ iort_add_block(IORT_TABLE *iort, IORT_NODE *iort_node, IOVIRT_INFO_TABLE *IoVirt count = &IoVirtTable->num_its_groups; break; case IOVIRT_NODE_NAMED_COMPONENT: - AsciiStrnCpyS((CHAR8*)(*data).name, MAX_NAMED_COMP_LENGTH, + AsciiStrnCpyS((CHAR8*)(*data).named_comp.name, MAX_NAMED_COMP_LENGTH, (CHAR8*)((IORT_NAMED_COMPONENT*)node_data)->device_name, (MAX_NAMED_COMP_LENGTH -1)); + (*data).named_comp.cca = (UINT32)(((IORT_NAMED_COMPONENT*)node_data)->memory_properties & IOVIRT_CCA_MASK); + (*data).named_comp.smmu_base = 0; /* initialize smmu_base info for named component */ count = &IoVirtTable->num_named_components; break; case IOVIRT_NODE_PCI_ROOT_COMPLEX: (*data).rc.segment = ((IORT_ROOT_COMPLEX*)node_data)->pci_segment_number; (*data).rc.cca = (UINT32)(((IORT_ROOT_COMPLEX*)node_data)->memory_properties & IOVIRT_CCA_MASK); (*data).rc.ats_attr = ((IORT_ROOT_COMPLEX*)node_data)->ats_attribute; + (*data).rc.smmu_base = 0; /* initialize smmu_base info for root complex */ count = &IoVirtTable->num_pci_rcs; break; case IOVIRT_NODE_SMMU: @@ -330,7 +330,6 @@ iort_add_block(IORT_TABLE *iort, IORT_NODE *iort_node, IOVIRT_INFO_TABLE *IoVirt * Else save NULL pointer. */ temp_block = ADD_PTR(IOVIRT_BLOCK, IoVirtTable, offset); - (*data).rc.smmu_base = 0; if (((*block)->type == IOVIRT_NODE_PCI_ROOT_COMPLEX) && ((temp_block->type == IOVIRT_NODE_SMMU) || (temp_block->type == IOVIRT_NODE_SMMU_V3))) { @@ -338,6 +337,18 @@ iort_add_block(IORT_TABLE *iort, IORT_NODE *iort_node, IOVIRT_INFO_TABLE *IoVirt (*data).rc.smmu_base = (*temp_data).smmu.base; } + /* If this node is a named component, Check whether it is behind a SMMU + * store the SMMU base in named component info structure if true, else + * save NULL pointer. + */ + temp_block = ADD_PTR(IOVIRT_BLOCK, IoVirtTable, offset); + if (((*block)->type == IOVIRT_NODE_NAMED_COMPONENT) && + ((temp_block->type == IOVIRT_NODE_SMMU) || + (temp_block->type == IOVIRT_NODE_SMMU_V3))) { + temp_data = &(temp_block->data); + (*data).named_comp.smmu_base = (*temp_data).smmu.base; + } + } } /* So we successfully added a new block. Calculate its offset */ diff --git a/platform/pal_uefi/src/pal_misc.c b/platform/pal_uefi/src/pal_misc.c index 96a0098f..de1d7973 100644 --- a/platform/pal_uefi/src/pal_misc.c +++ b/platform/pal_uefi/src/pal_misc.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -424,6 +424,55 @@ pal_mem_calloc ( return Buffer; } +/** + @brief Creates a buffer with length equal to size within the + address range (mem_base, mem_base + mem_size) + + @param mem_base - Base address of the memory range + @param mem_size - Size of the memory range of interest + @param size - Buffer size to be created + + @return Buffer address if SUCCESSFUL, else NULL +**/ +VOID * +pal_mem_alloc_at_address ( + UINT64 mem_base, + UINT64 Size + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS PageBase; + + PageBase = mem_base; + Status = gBS->AllocatePages (AllocateAddress, + EfiBootServicesData, + EFI_SIZE_TO_PAGES(Size), + &PageBase); + if (EFI_ERROR(Status)) + { + sbsa_print(AVS_PRINT_ERR, L" Allocate Pages failed %x \n", Status); + return NULL; + } + + return (VOID*)(UINTN)PageBase; +} + +/** + @brief Free number of pages in the memory as requested. + + @param PageBase Address from where we need to free + @param NumPages Number of memory pages needed + + @return None +**/ +VOID +pal_mem_free_at_address( + UINT64 mem_base, + UINT64 Size + ) +{ + gBS->FreePages(mem_base, EFI_SIZE_TO_PAGES(Size)); +} /** * @brief Allocates requested buffer size in bytes in a contiguous cacheable * memory and returns the base address of the range. diff --git a/platform/pal_uefi/src/pal_mpam.c b/platform/pal_uefi/src/pal_mpam.c new file mode 100644 index 00000000..edc11419 --- /dev/null +++ b/platform/pal_uefi/src/pal_mpam.c @@ -0,0 +1,263 @@ +/** @file + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. +**/ + +#include +#include +#include +#include + +#include "include/pal_uefi.h" +#include "include/platform_override.h" +#include "include/pal_mpam.h" + +#define ADD_PTR(t, p, l) ((t*)((UINT8*)p + l)) + +UINT64 pal_get_mpam_ptr(); + +UINT64 pal_get_srat_ptr(); + +/** + @brief Display MPAM info table details + + @param MpamTable - Address to the MPAM information table. + + @return None +**/ +VOID +pal_mpam_dump_table(MPAM_INFO_TABLE *MpamTable) +{ + UINT32 i, j; + MPAM_MSC_NODE *curr_entry; + + if (MpamTable == NULL) { + return; + } + + /* point to first entry in MPAM info table*/ + curr_entry = &(MpamTable->msc_node[0]); + + for (i = 0; i < MpamTable->msc_count; i++) { + sbsa_print(AVS_PRINT_INFO, L"\nMSC node Index :%d ", i); + sbsa_print(AVS_PRINT_INFO, L"\nMSC base addr :%llx ", + curr_entry->msc_base_addr); + sbsa_print(AVS_PRINT_INFO, L"\nMSC resource count :%lx ", + curr_entry->rsrc_count); + + for (j = 0; j < curr_entry->rsrc_count; j++) { + sbsa_print(AVS_PRINT_INFO, L"\nRESOURCE index :%d ", j); + sbsa_print(AVS_PRINT_INFO, L"\nRIS index :%d ", + curr_entry->rsrc_node[j].ris_index); + sbsa_print(AVS_PRINT_INFO, L"\nlocator type :%08X ", + curr_entry->rsrc_node[j].locator_type); + sbsa_print(AVS_PRINT_INFO, L"\ndescriptor1 :%llx ", + curr_entry->rsrc_node[j].descriptor1); + } + curr_entry = MPAM_NEXT_MSC(curr_entry); + } +} + +/** + @brief Display SRAT info table details + + @param SratTable - Address to the SRAT information table. + + @return None +**/ +VOID +pal_srat_dump_table(SRAT_INFO_TABLE *SratTable) +{ + UINT32 i; + SRAT_INFO_ENTRY *curr_entry; + + if (SratTable == NULL) { + return; + } + + for (i = 0; i < SratTable->num_of_srat_entries; i++) { + curr_entry = &(SratTable->srat_info[i]); + if ( curr_entry->node_type == SRAT_NODE_MEM_AFF) { + sbsa_print(AVS_PRINT_INFO, L"\n SRAT mem prox domain :%x ", + curr_entry->node_data.mem_aff.prox_domain); + sbsa_print(AVS_PRINT_INFO, L"\n SRAT mem addr_base :%llx ", + curr_entry->node_data.mem_aff.addr_base); + sbsa_print(AVS_PRINT_INFO, L"\n SRAT mem addr_len :%llx ", + curr_entry->node_data.mem_aff.addr_len); + } + else if ( curr_entry->node_type == SRAT_NODE_GICC_AFF) { + sbsa_print(AVS_PRINT_INFO, L"\n SRAT Gicc prox domain :%x ", + curr_entry->node_data.gicc_aff.prox_domain); + sbsa_print(AVS_PRINT_INFO, L"\n SRAT Gicc processor uid :%x ", + curr_entry->node_data.gicc_aff.proc_uid); + } + } +} + +/** + @brief This API fills in the MPAM_INFO_TABLE with the platform information + This is achieved by parsing the ACPI - MPAM table. + + @param MpamTable - Address where the MPAM information needs to be filled. + + @return None +**/ +VOID +pal_mpam_create_info_table(MPAM_INFO_TABLE *MpamTable) +{ + UINT32 i; + EFI_ACPI_MPAM_TABLE *mpam; + EFI_ACPI_MPAM_MSC_NODE_STRUCTURE *msc_node, *msc_end; + EFI_ACPI_MPAM_RESOURCE_NODE_STRUCTURE *rsrc_node; + MPAM_MSC_NODE *curr_entry; + + if (MpamTable == NULL) { + sbsa_print(AVS_PRINT_ERR, L" Input MPAM Table Pointer is NULL \n"); + return; + } + + /* Initialize MpamTable */ + MpamTable->msc_count = 0; + + /* point to first entry in MPAM info table*/ + curr_entry = &(MpamTable->msc_node[0]); + + mpam = (EFI_ACPI_MPAM_TABLE *)pal_get_mpam_ptr(); + if (mpam == NULL) { + sbsa_print(AVS_PRINT_DEBUG, L" MPAM table not found\n"); + return; + } + + /* Pointer to the first MSC node */ + msc_node = ADD_PTR(EFI_ACPI_MPAM_MSC_NODE_STRUCTURE, mpam, + sizeof(EFI_ACPI_DESCRIPTION_HEADER)); + msc_end = ADD_PTR(EFI_ACPI_MPAM_MSC_NODE_STRUCTURE, mpam, + mpam->header.Length); + + /* Populate MPAM table MSC node from acpi table MSC node*/ + while (msc_node < msc_end) { + curr_entry->msc_base_addr = msc_node->base_address; + curr_entry->msc_addr_len = msc_node->mmio_size; + curr_entry->max_nrdy = msc_node->max_nrdy_usec; + curr_entry->rsrc_count = msc_node->num_resource_nodes; + + /* Each MSC can have multiple resource node, Populate info table resource + node from acpi table resource node*/ + rsrc_node = ADD_PTR(EFI_ACPI_MPAM_RESOURCE_NODE_STRUCTURE, msc_node, + sizeof(EFI_ACPI_MPAM_MSC_NODE_STRUCTURE)); + i = 0; + + while (i < curr_entry->rsrc_count) { + curr_entry->rsrc_node[i].ris_index = rsrc_node->ris_index; + curr_entry->rsrc_node[i].locator_type = rsrc_node->locator_type; + curr_entry->rsrc_node[i].descriptor1 = rsrc_node->descriptor1; + rsrc_node = ADD_PTR(EFI_ACPI_MPAM_RESOURCE_NODE_STRUCTURE, rsrc_node, + sizeof(EFI_ACPI_MPAM_RESOURCE_NODE_STRUCTURE) + + (sizeof(EFI_ACPI_MPAM_FUNC_DEPEN_DESC_STRUCTURE) * + rsrc_node->num_dependencies)); + i++; + } + MpamTable->msc_count++; + msc_node = ADD_PTR(EFI_ACPI_MPAM_MSC_NODE_STRUCTURE, msc_node, + msc_node->length); + curr_entry = MPAM_NEXT_MSC(curr_entry); + } + pal_mpam_dump_table(MpamTable); +} + +/** + @brief This API fills in the SRAT_INFO_TABLE with the platform information + This is achieved by parsing the ACPI - SRAT table. + + @param SratTable - Address where the SRAT information needs to be filled. + + @return None +**/ +VOID +pal_srat_create_info_table(SRAT_INFO_TABLE *SratTable) +{ + EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER *SratHdr; + EFI_ACPI_6_4_SRAT_STRUCTURE_HEADER *Entry = NULL; + EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE *Mem_Aff_Entry = NULL; + EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE *Gicc_Aff_Entry = NULL; + SRAT_INFO_ENTRY *Ptr = NULL; + UINT32 TableLength = 0; + UINT32 Length = 0; + + if (SratTable == NULL) { + sbsa_print(AVS_PRINT_ERR, L" Input SRAT Table Pointer is NULL \n"); + return; + } + + /* Initialize SratTable */ + SratTable->num_of_mem_ranges = 0; + SratTable->num_of_srat_entries = 0; + + SratHdr = (EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER *) pal_get_srat_ptr(); + + if (SratHdr != NULL) { + TableLength = SratHdr->Header.Length; + sbsa_print(AVS_PRINT_INFO, L" SRAT is at %x and length is %x \n", SratHdr, TableLength); + } else { + sbsa_print(AVS_PRINT_DEBUG, L" SRAT not found \n"); + return; + } + + Entry = (EFI_ACPI_6_4_SRAT_STRUCTURE_HEADER *) (SratHdr + 1); + Length = sizeof (EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER); + Ptr = SratTable->srat_info; + + do { + + if (Entry->Type == EFI_ACPI_6_4_MEMORY_AFFINITY) { + //Fill in the mem ranges proximity domain, addr, len + Mem_Aff_Entry = (EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE *) Entry; + Ptr->node_type = Mem_Aff_Entry->Type; + Ptr->node_data.mem_aff.prox_domain = Mem_Aff_Entry->ProximityDomain; + Ptr->node_data.mem_aff.addr_base = ((UINT64) Mem_Aff_Entry->AddressBaseHigh << 32) | + Mem_Aff_Entry->AddressBaseLow; + Ptr->node_data.mem_aff.addr_len = ((UINT64) Mem_Aff_Entry->LengthHigh << 32) | + Mem_Aff_Entry->LengthLow; + Ptr->node_data.mem_aff.flags = Mem_Aff_Entry->Flags; + sbsa_print(AVS_PRINT_DEBUG, L" Proximity Domain %x \n", Ptr->node_data.mem_aff.prox_domain); + sbsa_print(AVS_PRINT_DEBUG, L" Address %x \n", Ptr->node_data.mem_aff.addr_base); + sbsa_print(AVS_PRINT_DEBUG, L" Length %x \n", Ptr->node_data.mem_aff.addr_len); + pal_pe_data_cache_ops_by_va((UINT64)Ptr, CLEAN_AND_INVALIDATE); + Ptr++; + SratTable->num_of_mem_ranges++; + SratTable->num_of_srat_entries++; + } + + else if (Entry->Type == EFI_ACPI_6_4_GICC_AFFINITY) { + Gicc_Aff_Entry = (EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE *) Entry; + Ptr->node_type = Gicc_Aff_Entry->Type; + Ptr->node_data.gicc_aff.prox_domain = Gicc_Aff_Entry->ProximityDomain; + Ptr->node_data.gicc_aff.proc_uid = Gicc_Aff_Entry->AcpiProcessorUid; + Ptr->node_data.gicc_aff.flags = Gicc_Aff_Entry->Flags; + Ptr->node_data.gicc_aff.clk_domain = Gicc_Aff_Entry->ClockDomain; + sbsa_print(AVS_PRINT_DEBUG, L" Proximity Domain %x \n", Ptr->node_data.gicc_aff.prox_domain); + sbsa_print(AVS_PRINT_DEBUG, L" Processor UID %x \n", Ptr->node_data.gicc_aff.proc_uid); + sbsa_print(AVS_PRINT_DEBUG, L" Clock Domain %x \n", Ptr->node_data.gicc_aff.clk_domain); + pal_pe_data_cache_ops_by_va((UINT64)Ptr, CLEAN_AND_INVALIDATE); + Ptr++; + SratTable->num_of_srat_entries++; + } + Length += Entry->Length; + Entry = (EFI_ACPI_6_4_SRAT_STRUCTURE_HEADER *) ((UINT8 *)Entry + + (Entry->Length)); + } while(Length < TableLength); + + pal_srat_dump_table(SratTable); +} diff --git a/platform/pal_uefi/src/pal_pcie.c b/platform/pal_uefi/src/pal_pcie.c index 458661dd..9c5eed3c 100644 --- a/platform/pal_uefi/src/pal_pcie.c +++ b/platform/pal_uefi/src/pal_pcie.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -19,10 +19,7 @@ #include #include #include - -#include "Include/IndustryStandard/Acpi61.h" #include "Include/IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h" -#include #include #include "Include/IndustryStandard/Pci.h" @@ -222,7 +219,7 @@ UINT32 pal_pcie_p2p_support() { /* - * TODO + * This is platform specific API which needs to be populated with system p2p capability * PCIe support for peer to peer * transactions is platform implementation specific */ @@ -246,7 +243,7 @@ pal_pcie_dev_p2p_support ( UINT32 Fn) { /* - * TODO + * This is platform specific API which needs to be populated with pcie device p2p capability * Root port or Switch support for peer to peer * transactions is platform implementation specific */ @@ -383,7 +380,7 @@ pal_pcie_check_device_list(void) accessed from the BAR base and is within BAR limit value - @param memory offset + @param type @return memory offset **/ UINT32 diff --git a/platform/pal_uefi/src/pal_pe.c b/platform/pal_uefi/src/pal_pe.c index 5ab15bda..537c3efc 100644 --- a/platform/pal_uefi/src/pal_pe.c +++ b/platform/pal_uefi/src/pal_pe.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2021-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -18,13 +18,12 @@ #include #include #include - -#include "Include/IndustryStandard/Acpi61.h" -#include #include #include "include/pal_uefi.h" +UINT64 pal_get_pptt_ptr(void); + static EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *gMadtHdr; UINT8 *gSecondaryPeStack; UINT64 gMpidrMax; @@ -34,6 +33,11 @@ extern INT32 gPsciConduit; #define SIZE_STACK_SECONDARY_PE 0x100 //256 bytes per core #define UPDATE_AFF_MAX(src,dest,mask) ((dest & mask) > (src & mask) ? (dest & mask) : (src & mask)) +#define PPTT_STRUCT_OFFSET 0x24 +#define PPTT_PE_PRIV_RES_OFFSET 0x14 +#define ADD_PTR(t, p, l) ((t*)((UINT8*)p + l)) +#define GET_ADDR_DIFF(a, b) ((UINT8*)a - (UINT8*)b) + UINT64 pal_get_madt_ptr(); @@ -182,7 +186,7 @@ pal_pe_create_info_table(PE_INFO_TABLE *PeTable) { EFI_ACPI_6_1_GIC_STRUCTURE *Entry = NULL; PE_INFO_ENTRY *Ptr = NULL; - UINT32 TableLength = 0; + UINT32 TableLength = 0, i; UINT32 Length = 0; UINT64 MpidrAff0Max = 0, MpidrAff1Max = 0, MpidrAff2Max = 0, MpidrAff3Max = 0; @@ -216,7 +220,10 @@ pal_pe_create_info_table(PE_INFO_TABLE *PeTable) Ptr->pe_num = PeTable->header.num_of_pe; Ptr->pmu_gsiv = Entry->PerformanceInterruptGsiv; Ptr->gmain_gsiv = Entry->VGICMaintenanceInterrupt; - sbsa_print(AVS_PRINT_DEBUG, L" MPIDR %x PE num %x \n", Ptr->mpidr, Ptr->pe_num); + Ptr->acpi_proc_uid = Entry->AcpiProcessorUid; + for (i = 0; i < MAX_L1_CACHE_RES; i++) + Ptr->level_1_res[i] = DEFAULT_CACHE_IDX; //initialize cache index fields with all 1's + sbsa_print(AVS_PRINT_DEBUG, L" MPIDR %llx PE num %x \n", Ptr->mpidr, Ptr->pe_num); pal_pe_data_cache_ops_by_va((UINT64)Ptr, CLEAN_AND_INVALIDATE); Ptr++; PeTable->header.num_of_pe++; @@ -387,3 +394,257 @@ pal_pe_data_cache_ops_by_va(UINT64 addr, UINT32 type) } } + +/** + @brief This API prints cache info table and cache entry indices for each pe. + @param CacheTable Pointer to cache info table. + @param PeTable Pointer to pe info table. + @return None +**/ +VOID +pal_cache_dump_info_table(CACHE_INFO_TABLE *CacheTable, PE_INFO_TABLE *PeTable) +{ + UINT32 i, j; + CACHE_INFO_ENTRY *curr_entry; + PE_INFO_ENTRY *pe_entry; + curr_entry = CacheTable->cache_info; + pe_entry = PeTable->pe_info; + + /*Iterate cache info table and print cache info entries*/ + for (i = 0 ; i < CacheTable->num_of_cache ; i++) { + sbsa_print(AVS_PRINT_INFO, L"\nCache info * Index %d *", i); + sbsa_print(AVS_PRINT_INFO, L"\n Offset: 0x%llx", curr_entry->my_offset); + sbsa_print(AVS_PRINT_INFO, L"\n Type: 0x%llx", curr_entry->cache_type); + sbsa_print(AVS_PRINT_INFO, L"\n Cache ID: 0x%llx", curr_entry->cache_id); + sbsa_print(AVS_PRINT_INFO, L"\n Size: 0x%llx", curr_entry->size); + sbsa_print(AVS_PRINT_INFO, L"\n Next level index: %d", curr_entry->next_level_index); + sbsa_print(AVS_PRINT_INFO, L"\n Private flag: 0x%llx\n", curr_entry->is_private); + curr_entry++; + } + + sbsa_print(AVS_PRINT_INFO, L"\nPE level one cache index info"); + /*Iterate PE info table and print level one cache index info*/ + for (i = 0 ; i < PeTable->header.num_of_pe; i++) { + sbsa_print(AVS_PRINT_INFO, L"\nPE Index * %d *", i); + sbsa_print(AVS_PRINT_INFO, L"\n Level 1 Cache index(s) :"); + + for (j = 0; pe_entry->level_1_res[j] != DEFAULT_CACHE_IDX && j < MAX_L1_CACHE_RES; j++) { + sbsa_print(AVS_PRINT_INFO, L" %d,", pe_entry->level_1_res[j]); + } + sbsa_print(AVS_PRINT_INFO, L"\n"); + pe_entry++; + } +} + +/** + @brief This function parses and stores cache info in cache info table + Caller - pal_cache_create_info_table + @param CacheTable Pointer to cache info table. + @param cache_type_struct Pointer to PPTT cache structure that needs to be parsed. + @param offset Offset of the cache structure in PPTT ACPI table. + @param is_private Flag indicating whether the cache is private. + @return Index to the cache info entry where parsed info is stored. +**/ + +UINT32 +pal_cache_store_info(CACHE_INFO_TABLE *CacheTable, + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE *cache_type_struct, + UINT32 offset, UINT32 is_private) +{ + CACHE_INFO_ENTRY *curr_entry; + curr_entry = &(CacheTable->cache_info[CacheTable->num_of_cache]); + CacheTable->num_of_cache++; + + curr_entry->my_offset = offset; + curr_entry->flags.size_property_valid = cache_type_struct->Flags.SizePropertyValid; + curr_entry->flags.cache_type_valid = cache_type_struct->Flags.CacheTypeValid; + curr_entry->flags.cache_id_valid = cache_type_struct->Flags.CacheIdValid; + curr_entry->size = cache_type_struct->Size; + curr_entry->cache_type = cache_type_struct->Attributes.CacheType; + curr_entry->cache_id = cache_type_struct->CacheId; + curr_entry->is_private = is_private; + + /* set default next level index to invalid */ + curr_entry->next_level_index = CACHE_INVALID_NEXT_LVL_IDX; + + return CacheTable->num_of_cache - 1; +} + +/** + @brief This function checks whether the cache info for a particular cache already stored. + Caller - pal_cache_create_info_table + @param CacheTable Pointer to cache info table. + @param offset Offset of the cache structure in PPTT ACPI table. + @param found_index pointer to a variable, to return index if cache info already present. + @return 0 if cache info not present, 1 otherwise +**/ +UINT32 +pal_cache_find(CACHE_INFO_TABLE *CacheTable, UINT32 offset, UINT32 *found_index) +{ + CACHE_INFO_ENTRY *curr_entry; + UINT32 i; + + curr_entry = CacheTable->cache_info; + for (i = 0 ; i < CacheTable->num_of_cache ; i++) { + /* match cache offset of the entry with input offset*/ + if(curr_entry->my_offset == offset) { + *found_index = i; + return 1; + } + curr_entry++; + } + return 0; +} + +/** + @brief This function stores level 1 cache info entry index(s) to pe info table. + Caller - pal_cache_create_info_table + @param PeTable Pointer to pe info table. + @param acpi_uid ACPI UID of the pe entry, to which index(s) to be stored. + @param cache_index index of the level 1 cache entry. + @param res_index private resource index of pe private cache. + @return None +**/ +VOID +pal_cache_store_pe_res(PE_INFO_TABLE *PeTable, UINT32 acpi_uid, + UINT32 cache_index, UINT32 res_index) +{ + PE_INFO_ENTRY *entry; + entry = PeTable->pe_info; + UINT32 i; + + if (res_index < MAX_L1_CACHE_RES) { + for (i = 0 ; i < PeTable->header.num_of_pe; i++) { + if (entry->acpi_proc_uid == acpi_uid) { + entry->level_1_res[res_index] = cache_index; + } + entry++; + } + } + else + sbsa_print(AVS_PRINT_ERR, + L"\n The input resource index is greater than supported value %d", MAX_L1_CACHE_RES); +} + + +/** + @brief Parses ACPI PPTT table and populates the local cache info table. + Prerequisite - pal_pe_create_info_table + @param CacheTable Pointer to pre-allocated memory for cache info table. + @return None +**/ + +VOID +pal_cache_create_info_table(CACHE_INFO_TABLE *CacheTable, PE_INFO_TABLE *PeTable) +{ + EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER *PpttHdr; + UINT32 TableLength = 0; + EFI_ACPI_6_4_PPTT_STRUCTURE_HEADER *pptt_struct, *pptt_end ; + EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR *pe_type_struct, *temp_pe_struct; + EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE *cache_type_struct; + UINT32 i, j, status=0; + UINT32 offset; + UINT32 index; + UINT32 next_index; + + if (CacheTable == NULL) { + sbsa_print(AVS_PRINT_ERR, L" Unable to create cache info table, input pointer is NULL \n"); + return; + } + + /* initialize cache info table entries */ + CacheTable->num_of_cache = 0; + + PpttHdr = (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER *) pal_get_pptt_ptr(); + if (PpttHdr == NULL) { + sbsa_print(AVS_PRINT_ERR, L" PPTT Table not found\n"); + return; + } + else { + TableLength = PpttHdr->Header.Length; + sbsa_print(AVS_PRINT_INFO, L"PPTT table found at 0x%llx with length 0x%x\n", + PpttHdr, TableLength); + } + +/* Pointer to first PPTT structure in PPTT ACPI table */ + pptt_struct = ADD_PTR(EFI_ACPI_6_4_PPTT_STRUCTURE_HEADER, PpttHdr, PPTT_STRUCT_OFFSET); + +/* PPTT end boundary */ + pptt_end = ADD_PTR(EFI_ACPI_6_4_PPTT_STRUCTURE_HEADER, PpttHdr, TableLength); + +/* iterate PPTT structs in PPTT ACPI Table */ + while (pptt_struct < pptt_end) { + if (pptt_struct->Type == EFI_ACPI_6_4_PPTT_TYPE_PROCESSOR) { + pe_type_struct = (EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR *) pptt_struct; + /* check whether the PPTT PE structure corresponds to a actual PE and not a group */ + if (pe_type_struct->Flags.NodeIsALeaf == 1) { + /* Parse PE private cache resources*/ + for (i = 0 ; i < pe_type_struct->NumberOfPrivateResources ; i++) { + offset = *(ADD_PTR(UINT32, pe_type_struct, PPTT_PE_PRIV_RES_OFFSET + i*4)); + cache_type_struct = ADD_PTR(EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE, PpttHdr, offset); + index = pal_cache_store_info(CacheTable, cache_type_struct, offset, CACHE_TYPE_PRIVATE); + pal_cache_store_pe_res(PeTable, pe_type_struct->AcpiProcessorId, index, i); + /* parse next level(s) of current private PE cache */ + while(cache_type_struct->NextLevelOfCache != 0) { + offset = cache_type_struct->NextLevelOfCache; + cache_type_struct = ADD_PTR(EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE, PpttHdr, offset); + /* check if cache PPTT struct is already parsed*/ + status = pal_cache_find(CacheTable, offset, &next_index); + /* if cache structure is already parsed update the previous cache info with index + of found cache entry in cache_info_table, else parse the cache structure*/ + if (status) { + CacheTable->cache_info[index].next_level_index = next_index; + break; + } + else { + CacheTable->cache_info[index].next_level_index = CacheTable->num_of_cache; + index = pal_cache_store_info(CacheTable, cache_type_struct, + offset, CACHE_TYPE_PRIVATE); + } + } + + /* if a cache entry is already present in info table, then it means next level cache(s) + for that cache is already parsed in past iteration, else parse parent PE group */ + if (status) continue; + temp_pe_struct = pe_type_struct; + + /* Keep on parsing PPTT PE group structures until root */ + while (temp_pe_struct->Parent != 0 ) { + temp_pe_struct = ADD_PTR(EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR, PpttHdr, + temp_pe_struct->Parent); + /* If a group has cache resources parse it */ + for (j = 0 ; j < temp_pe_struct->NumberOfPrivateResources;j++) { + offset = *(ADD_PTR(UINT32, temp_pe_struct, PPTT_PE_PRIV_RES_OFFSET + j*4)); + cache_type_struct = ADD_PTR(EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE, PpttHdr, offset); + /* Next level cache type should unified type(0x2 or 0x3) or same as previous type*/ + if (cache_type_struct->Attributes.CacheType > 0x1 || + cache_type_struct->Attributes.CacheType == + CacheTable->cache_info[index].cache_type ) { + status = pal_cache_find(CacheTable, offset, &next_index); + /* if cache structure is already parsed update the previous cache info with index + of found cache entry in cache_info_table, else parse the cache structure */ + if (status) { + CacheTable->cache_info[index].next_level_index = next_index; + break; + } + else { + CacheTable->cache_info[index].next_level_index = CacheTable->num_of_cache; + index = pal_cache_store_info(CacheTable, cache_type_struct, offset, + CACHE_TYPE_SHARED); + } + } + } + /* If cache entry already found in info table, then it means next level cache(s) + for that cache is already parsed in past iteration, else parse parent PE group + of current group */ + if(status) break; + } + } + } + } + pptt_struct = ADD_PTR(EFI_ACPI_6_4_PPTT_STRUCTURE_HEADER, pptt_struct, pptt_struct->Length); + } + pal_cache_dump_info_table(CacheTable, PeTable); +} + + diff --git a/platform/pal_uefi/src/pal_peripherals.c b/platform/pal_uefi/src/pal_peripherals.c index 643f6d4d..81a36e6f 100644 --- a/platform/pal_uefi/src/pal_peripherals.c +++ b/platform/pal_uefi/src/pal_peripherals.c @@ -22,9 +22,6 @@ #include #include #include - -#include -#include "Include/IndustryStandard/Acpi61.h" #include "Include/IndustryStandard/SerialPortConsoleRedirectionTable.h" #include "include/pal_uefi.h" @@ -67,6 +64,7 @@ pal_peripheral_create_info_table(PERIPHERAL_INFO_TABLE *peripheralInfoTable) peripheralInfoTable->header.num_usb = 0; peripheralInfoTable->header.num_sata = 0; peripheralInfoTable->header.num_uart = 0; + peripheralInfoTable->header.num_all = 0; /* check for any USB Controllers */ do { @@ -78,6 +76,7 @@ pal_peripheral_create_info_table(PERIPHERAL_INFO_TABLE *peripheralInfoTable) per_info->bdf = DeviceBdf; sbsa_print(AVS_PRINT_INFO, L" Found a USB controller %4x \n", per_info->base0); peripheralInfoTable->header.num_usb++; + peripheralInfoTable->header.num_all++; per_info++; } StartBdf = incrementBusDev(DeviceBdf); @@ -95,6 +94,7 @@ pal_peripheral_create_info_table(PERIPHERAL_INFO_TABLE *peripheralInfoTable) per_info->bdf = DeviceBdf; sbsa_print(AVS_PRINT_INFO, L" Found a SATA controller %4x \n", per_info->base0); peripheralInfoTable->header.num_sata++; + peripheralInfoTable->header.num_all++; per_info++; } //Increment and check if we have more controllers @@ -107,6 +107,7 @@ pal_peripheral_create_info_table(PERIPHERAL_INFO_TABLE *peripheralInfoTable) if (spcr) { peripheralInfoTable->header.num_uart++; + peripheralInfoTable->header.num_all++; per_info->base0 = spcr->BaseAddress.Address; per_info->irq = spcr->GlobalSystemInterrupt; per_info->type = PERIPHERAL_TYPE_UART; @@ -115,6 +116,7 @@ pal_peripheral_create_info_table(PERIPHERAL_INFO_TABLE *peripheralInfoTable) if (PLATFORM_GENERIC_UART_BASE) { peripheralInfoTable->header.num_uart++; + peripheralInfoTable->header.num_all++; per_info->base0 = PLATFORM_GENERIC_UART_BASE; per_info->irq = PLATFORM_GENERIC_UART_INTID; per_info->type = PERIPHERAL_TYPE_UART; diff --git a/platform/pal_uefi/src/pal_pmu.c b/platform/pal_uefi/src/pal_pmu.c new file mode 100644 index 00000000..a6e57406 --- /dev/null +++ b/platform/pal_uefi/src/pal_pmu.c @@ -0,0 +1,216 @@ +/** @file + * Copyright (c) 2022-2023 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. +**/ + +#include +#include +#include +#include + +#include "include/pal_uefi.h" +#include "include/platform_override.h" +#include "include/pal_pmu.h" + +#define ADD_PTR(t, p, l) ((t*)((UINT8*)p + l)) +#define MAX_NUM_OF_PMU_SUPPORTED 512 + +UINT64 pal_get_apmt_ptr(); + +/** + @brief Display PMU info table details + + @param PmuTable - Address to the PMU information table. + + @return None +**/ +VOID +pal_pmu_dump_info_table(PMU_INFO_TABLE *PmuTable) +{ + UINT32 i; + + if (PmuTable == NULL) { + return; + } + + for (i = 0; i < PmuTable->pmu_count; i++) { + sbsa_print(AVS_PRINT_INFO, L"\nPMU info Index :%d ", i); + sbsa_print(AVS_PRINT_INFO, L"\nPMU node type :%02X ", PmuTable->info[i].type); + sbsa_print(AVS_PRINT_INFO, L"\nDual page extension :%d ", + PmuTable->info[i].dual_page_extension); + sbsa_print(AVS_PRINT_INFO, L"\nBase Address 0 :%llX ", PmuTable->info[i].base0); + if(PmuTable->info[i].dual_page_extension) + sbsa_print(AVS_PRINT_INFO, L"\nBase Address 1 :%llX ", PmuTable->info[i].base1); + sbsa_print(AVS_PRINT_INFO, L"\nPrimary Instance :%llX ", + PmuTable->info[i].primary_instance); + sbsa_print(AVS_PRINT_INFO, L"\nSecondary Instance :%08X ", + PmuTable->info[i].secondary_instance); + + } +} + +/** + @brief This API fills in the PMU_INFO_TABLE with information about local and system + timers in the system. This is achieved by parsing the ACPI - APMT table. + + @param PmuTable - Address where the PMU information needs to be filled. + + @return None +**/ +VOID +pal_pmu_create_info_table(PMU_INFO_TABLE *PmuTable) +{ + APMT_TABLE *apmt; + APMT_NODE *apmt_node, *apmt_end; + + if (PmuTable == NULL) { + sbsa_print(AVS_PRINT_ERR, L"\n Input PMU Table Pointer is NULL"); + return; + } + + /* Initialize PmuTable */ + PmuTable->pmu_count = 0; + + apmt = (APMT_TABLE *)pal_get_apmt_ptr(); + if (apmt == NULL) { + sbsa_print(AVS_PRINT_DEBUG, L" APMT table not found\n"); + return; + } + + /* Pointer to the first APMT node */ + apmt_node = ADD_PTR(APMT_NODE, apmt, sizeof(EFI_ACPI_DESCRIPTION_HEADER)); + apmt_end = ADD_PTR(APMT_NODE, apmt, apmt->header.Length); + + /* Create PMU info block for each APMT node*/ + while (apmt_node < apmt_end) { + PmuTable->info[PmuTable->pmu_count].type = apmt_node->type; + PmuTable->info[PmuTable->pmu_count].dual_page_extension = apmt_node->flags & 1; + PmuTable->info[PmuTable->pmu_count].base0 = apmt_node->base_addr0; + PmuTable->info[PmuTable->pmu_count].base1 = apmt_node->base_addr1; + PmuTable->info[PmuTable->pmu_count].primary_instance = apmt_node->primary_instance; + PmuTable->info[PmuTable->pmu_count].secondary_instance = apmt_node->secondary_instance; + PmuTable->pmu_count++; + if (PmuTable->pmu_count >= MAX_NUM_OF_PMU_SUPPORTED) { + sbsa_print(AVS_PRINT_WARN, L"\n Number of PMUs greater than %d", + MAX_NUM_OF_PMU_SUPPORTED); + break; + } + apmt_node = ADD_PTR(APMT_NODE, apmt_node, apmt_node->length); + } + pal_pmu_dump_info_table(PmuTable); +} + +typedef struct{ + PMU_NODE_INFO_TYPE node_type; + PMU_EVENT_TYPE_e event_desc; + UINT32 event_id; +}event_details; + +/* Array containing the details of implementation defined system PMU events */ +event_details event_list[] = { + {PMU_NODE_MEM_CNTR, PMU_EVENT_IB_TOTAL_BW, PMU_EVENT_INVALID}, + {PMU_NODE_MEM_CNTR, PMU_EVENT_OB_TOTAL_BW, PMU_EVENT_INVALID}, + {PMU_NODE_MEM_CNTR, PMU_EVENT_IB_READ_BW, PMU_EVENT_INVALID}, + {PMU_NODE_MEM_CNTR, PMU_EVENT_IB_WRITE_BW, PMU_EVENT_INVALID}, + {PMU_NODE_MEM_CNTR, PMU_EVENT_OB_READ_BW, PMU_EVENT_INVALID}, + {PMU_NODE_MEM_CNTR, PMU_EVENT_OB_WRITE_BW, PMU_EVENT_INVALID}, + {PMU_NODE_MEM_CNTR, PMU_EVENT_IB_OPEN_TXN, PMU_EVENT_INVALID}, + {PMU_NODE_MEM_CNTR, PMU_EVENT_IB_TOTAL_TXN, PMU_EVENT_INVALID}, + {PMU_NODE_MEM_CNTR, PMU_EVENT_OB_OPEN_TXN, PMU_EVENT_INVALID}, + {PMU_NODE_MEM_CNTR, PMU_EVENT_OB_TOTAL_TXN, PMU_EVENT_INVALID}, + {PMU_NODE_MEM_CNTR, PMU_EVENT_LOCAL_BW, PMU_EVENT_INVALID}, + {PMU_NODE_MEM_CNTR, PMU_EVENT_REMOTE_BW, PMU_EVENT_INVALID}, + {PMU_NODE_MEM_CNTR, PMU_EVENT_ALL_BW, PMU_EVENT_INVALID}, + {PMU_NODE_PCIE_RC, PMU_EVENT_IB_TOTAL_BW, PMU_EVENT_INVALID}, + {PMU_NODE_PCIE_RC, PMU_EVENT_OB_TOTAL_BW, PMU_EVENT_INVALID}, + {PMU_NODE_PCIE_RC, PMU_EVENT_IB_READ_BW, PMU_EVENT_INVALID}, + {PMU_NODE_PCIE_RC, PMU_EVENT_IB_WRITE_BW, PMU_EVENT_INVALID}, + {PMU_NODE_PCIE_RC, PMU_EVENT_OB_READ_BW, PMU_EVENT_INVALID}, + {PMU_NODE_PCIE_RC, PMU_EVENT_OB_WRITE_BW, PMU_EVENT_INVALID}, + {PMU_NODE_PCIE_RC, PMU_EVENT_IB_OPEN_TXN, PMU_EVENT_INVALID}, + {PMU_NODE_PCIE_RC, PMU_EVENT_IB_TOTAL_TXN, PMU_EVENT_INVALID}, + {PMU_NODE_PCIE_RC, PMU_EVENT_OB_OPEN_TXN, PMU_EVENT_INVALID}, + {PMU_NODE_PCIE_RC, PMU_EVENT_OB_TOTAL_TXN, PMU_EVENT_INVALID}, + {PMU_NODE_PCIE_RC, PMU_EVENT_LOCAL_BW, PMU_EVENT_INVALID}, + {PMU_NODE_PCIE_RC, PMU_EVENT_REMOTE_BW, PMU_EVENT_INVALID}, + {PMU_NODE_PCIE_RC, PMU_EVENT_ALL_BW, PMU_EVENT_INVALID}, + {PMU_NODE_ACPI_DEVICE, PMU_EVENT_TRAFFIC_1, PMU_EVENT_INVALID}, + {PMU_NODE_ACPI_DEVICE, PMU_EVENT_TRAFFIC_2, PMU_EVENT_INVALID} +}; + +/** + @brief This API returns the event ID to be filled into PMEVTYPER register. + Prerequisite - event_list array. This API should be called after + filling the required event IDs into event_list array. + + @param event_type - Type of the event. + @param node_type - PMU Node type + + @return Event ID + +**/ +UINT32 +pal_pmu_get_event_info(PMU_EVENT_TYPE_e event_type, PMU_NODE_INFO_TYPE node_type) +{ + UINT32 i=0; + while (event_list[i].node_type != node_type || event_list[i].event_desc != event_type) { + i++; + } + return event_list[i].event_id; +} + +/** + @brief This API checks if pmu monitor count value is valid + @param interface_acpiid - acpiid of interface + @param count_value - monitor count value + @param eventid - eventid + @return 0 - monitor count value is valid + non-zero - error or invallid count value +**/ +UINT32 +pal_pmu_check_monitor_count_value(UINT64 interface_acpiid, UINT32 count_value, UINT32 eventid) +{ + return NOT_IMPLEMENTED; +} + +/** + @brief This API generates required workload for given pmu node and event id + @param interface_acpiid - acpiid of interface + @param pmu_node_index - pmu node index + @param mon_index - monitor index + @param eventid - eventid + @return 0 - success status + non-zero - error status +**/ +UINT32 +pal_generate_traffic(UINT64 interface_acpiid, UINT32 pmu_node_index, + UINT32 mon_index, UINT32 eventid) +{ + return NOT_IMPLEMENTED; +} + +/** + @brief This API checks if PMU node is secure only. + @param interface_acpiid - acpiid of interface + @param num_traffic_type_support - num of traffic type supported. + @return 0 - success status + non-zero - error status +**/ +UINT32 +pal_pmu_get_multi_traffic_support_interface(UINT64 *interface_acpiid, + UINT32 *num_traffic_type_support) +{ + return NOT_IMPLEMENTED; +} diff --git a/platform/pal_uefi/src/pal_ras.c b/platform/pal_uefi/src/pal_ras.c new file mode 100644 index 00000000..10717f19 --- /dev/null +++ b/platform/pal_uefi/src/pal_ras.c @@ -0,0 +1,472 @@ +/** @file + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. +**/ + +#include +#include +#include +#include +#include "Include/IndustryStandard/ArmErrorSourceTable.h" + +#include "include/pal_uefi.h" +#include "include/pal_ras.h" +#include "include/platform_override.h" + +#define ADD_PTR(t, p, l) ((t*)((UINT8*)p + l)) + +UINT64 pal_get_aest_ptr(); + +/** + @brief API to check support for Poison + + @param None + + @return 0 - Poison storage & forwarding not supported + 1 - Poison storage & forwarding supported +**/ +UINT32 +pal_ras_check_plat_poison_support() +{ + return 0; +} + +/** + @brief Platform Defined way of setting up the Error Environment + + @param in_param - Error Input Parameters. + @param *out_param - Parameters returned from platform to be used in the test. + + @return 0 - Success, NOT_IMPLEMENTED - API not implemented, Other values - Failure +**/ +UINT32 +pal_ras_setup_error(RAS_ERR_IN_t in_param, RAS_ERR_OUT_t *out_param) +{ + /* Platform Defined way of setting up the Error Environment */ + return NOT_IMPLEMENTED; +} + +/** + @brief Platform Defined way of injecting up the Error Environment + + @param in_param - Error Input Parameters. + @param *out_param - Parameters returned from platform to be used in the test. + + @return 0 - Success, NOT_IMPLEMENTED - API not implemented, Other values - Failure +**/ +UINT32 +pal_ras_inject_error(RAS_ERR_IN_t in_param, RAS_ERR_OUT_t *out_param) +{ + return NOT_IMPLEMENTED; +} + +/** + @brief Platform Defined way of Timeout/Wait loop + + @param count - Timeout/Wait Multiplier. + + @return None +**/ +VOID +pal_ras_wait_timeout(UINT32 count) +{ + UINT32 timeout = count * PLATFORM_TIMEOUT_MEDIUM; + + /* Wait Loop */ + while (timeout > 0) + timeout--; +} + +/** + @brief Display RAS info table details + + @param RasInfoTable - Address to the RAS information table. + + @return None +**/ +VOID +pal_ras_dump_info_table(RAS_INFO_TABLE *RasInfoTable) +{ + UINT32 i, j; + RAS_NODE_INFO *curr; + + if (RasInfoTable == NULL) { + return; + } + + sbsa_print(AVS_PRINT_INFO, L"\nRAS Info :"); + sbsa_print(AVS_PRINT_INFO, L"\nRAS Num Nodes : %d ", RasInfoTable->num_nodes); + + curr = &(RasInfoTable->node[0]); + + for (i = 0; i < RasInfoTable->num_nodes; i++) { + sbsa_print(AVS_PRINT_INFO, L"\n Index : %d ", i); + sbsa_print(AVS_PRINT_INFO, L"\n Type : 0x%x ", curr->type); + sbsa_print(AVS_PRINT_INFO, L"\n Num Intr : 0x%x ", curr->num_intr_entries); + + switch (curr->type) { + case NODE_TYPE_PE: + /* Print Processor Node Details */ + sbsa_print(AVS_PRINT_INFO, L"\n ProcessorID : 0x%x ", curr->node_data.pe.processor_id); + sbsa_print(AVS_PRINT_INFO, L"\n resource_type : 0x%x ", + curr->node_data.pe.resource_type); + sbsa_print(AVS_PRINT_INFO, L"\n flags : 0x%x ", curr->node_data.pe.flags); + sbsa_print(AVS_PRINT_INFO, L"\n affinity : 0x%x ", curr->node_data.pe.affinity); + break; + case NODE_TYPE_MC: + /* Print Memory Controller Node Details */ + sbsa_print(AVS_PRINT_INFO, L"\n proximity_domain : 0x%x ", + curr->node_data.mc.proximity_domain); + break; + default: + break; + } + + sbsa_print(AVS_PRINT_INFO, L"\n Interface Info :"); + sbsa_print(AVS_PRINT_INFO, L"\n type : 0x%x ", curr->intf_info.intf_type); + sbsa_print(AVS_PRINT_INFO, L"\n base : 0x%x ", curr->intf_info.base_addr); + sbsa_print(AVS_PRINT_INFO, L"\n num_err : 0x%x ", curr->intf_info.num_err_rec); + + sbsa_print(AVS_PRINT_INFO, L"\n Interrupt Info :"); + for (j = 0; j < curr->num_intr_entries; j++) { + sbsa_print(AVS_PRINT_INFO, L"\n type : 0x%x ", curr->intr_info[j].type); + sbsa_print(AVS_PRINT_INFO, L"\n gsiv : 0x%x ", curr->intr_info[j].gsiv); + } + + curr++; + } + sbsa_print(AVS_PRINT_INFO, L"\n"); +} + +void fill_node_specific_data ( + RAS_INFO_TABLE *RasInfoTable, + AEST_NODE *aest_node, + RAS_NODE_INFO *curr_node, + EFI_ACPI_AEST_NODE_STRUCT *node_header + ) +{ + EFI_ACPI_AEST_PROCESSOR_STRUCT *pe_node; + EFI_ACPI_AEST_MEMORY_CONTROLLER_STRUCT *mc_node; + + switch (node_header->Type) { + case EFI_ACPI_AEST_NODE_TYPE_PROCESSOR: + /* Fill Processor Node Details */ + pe_node = (EFI_ACPI_AEST_PROCESSOR_STRUCT *)aest_node; + curr_node->type = NODE_TYPE_PE; + curr_node->node_data.pe.processor_id = pe_node->AcpiProcessorId; + curr_node->node_data.pe.resource_type = pe_node->ResourceType; + curr_node->node_data.pe.flags = pe_node->Flags; + curr_node->node_data.pe.affinity = pe_node->ProcessorAffinityLevelIndicator; + RasInfoTable->num_pe_node++; + break; + case EFI_ACPI_AEST_NODE_TYPE_MEMORY: + /* Fill Memory Controller Node Details */ + mc_node = (EFI_ACPI_AEST_MEMORY_CONTROLLER_STRUCT *)aest_node; + curr_node->type = NODE_TYPE_MC; + curr_node->node_data.mc.proximity_domain = mc_node->ProximityDomain; + RasInfoTable->num_mc_node++; + break; + default: + break; + } +} + +void fill_node_interface_data ( + RAS_INFO_TABLE *RasInfoTable, + AEST_NODE *aest_node, + RAS_NODE_INFO *curr_node, + EFI_ACPI_AEST_NODE_STRUCT *node_header + ) +{ + EFI_ACPI_AEST_INTERFACE_STRUCT *node_intf; + + node_intf = ADD_PTR(EFI_ACPI_AEST_INTERFACE_STRUCT, aest_node, node_header->InterfaceOffset); + + curr_node->intf_info.intf_type = node_intf->Type; + curr_node->intf_info.flags = node_intf->Flags; + curr_node->intf_info.base_addr = node_intf->BaseAddress; + curr_node->intf_info.start_rec_index = node_intf->StartErrorRecordIndex; + curr_node->intf_info.num_err_rec = node_intf->NumberErrorRecords; + curr_node->intf_info.err_rec_implement = node_intf->ErrorRecordImplemented; + curr_node->intf_info.err_status_reporting = node_intf->ErrorRecordStatusReportingSupported; + curr_node->intf_info.addressing_mode = node_intf->AddressingMode; +} + +void fill_node_interrupt_data ( + RAS_INFO_TABLE *RasInfoTable, + AEST_NODE *aest_node, + RAS_NODE_INFO *curr_node, + EFI_ACPI_AEST_NODE_STRUCT *node_header + ) +{ + EFI_ACPI_AEST_INTERRUPT_STRUCT *node_intr_data; + UINT32 count = 0; + + node_intr_data = ADD_PTR(EFI_ACPI_AEST_INTERRUPT_STRUCT, aest_node, + node_header->InterruptArrayOffset); + + for (count = 0; count < curr_node->num_intr_entries; count++) + { + curr_node->intr_info[count].type = node_intr_data->InterruptType; + curr_node->intr_info[count].gsiv = node_intr_data->InterruptGsiv; + curr_node->intr_info[count].flag = node_intr_data->InterruptFlags; + curr_node->intr_info[count].its_grp_id = node_intr_data->ItsGroupRefId; + + node_intr_data = ADD_PTR(EFI_ACPI_AEST_INTERRUPT_STRUCT, node_intr_data, + sizeof(EFI_ACPI_AEST_INTERRUPT_STRUCT)); + } + +} +/** + @brief This API fills in the RAS_INFO_TABLE with information about local and system + timers in the system. This is achieved by parsing the ACPI - AEST table. + + @param RasInfoTable - Address where the RAS information needs to be filled. + + @return None +**/ +VOID +pal_ras_create_info_table(RAS_INFO_TABLE *RasInfoTable) +{ + EFI_ACPI_ARM_ERROR_SOURCE_TABLE *aest; + AEST_NODE *aest_node, *aest_end; + EFI_ACPI_AEST_NODE_STRUCT *node_header; + RAS_NODE_INFO *curr_node; + + if (RasInfoTable == NULL) { + sbsa_print(AVS_PRINT_ERR, L"\n Input RAS Table Pointer is NULL"); + return; + } + + /* Initialize RasInfoTable */ + RasInfoTable->num_nodes = 0; + RasInfoTable->num_pe_node = 0; + RasInfoTable->num_mc_node = 0; + + aest = (EFI_ACPI_ARM_ERROR_SOURCE_TABLE *)pal_get_aest_ptr(); + if (aest == NULL) { + sbsa_print(AVS_PRINT_DEBUG, L" AEST table not found\n"); + return; + } + + /* Pointer to the first AEST node */ + aest_node = ADD_PTR(AEST_NODE, aest, sizeof(EFI_ACPI_DESCRIPTION_HEADER)); + aest_end = ADD_PTR(AEST_NODE, aest, aest->Header.Length); + + curr_node = &(RasInfoTable->node[0]); + + /* Create RAS info block for each AEST node*/ + while (aest_node < aest_end) { + /* Add common data for each node */ + node_header = (EFI_ACPI_AEST_NODE_STRUCT *)(aest_node); + + curr_node->type = node_header->Type; + curr_node->length = node_header->Length; + curr_node->num_intr_entries = node_header->InterruptArrayCount; + + /* Fill Node Specific data */ + fill_node_specific_data(RasInfoTable, aest_node, curr_node, node_header); + + /* Fill Node Interface data */ + fill_node_interface_data(RasInfoTable, aest_node, curr_node, node_header); + + /* Fill Node Interrupt data */ + fill_node_interrupt_data(RasInfoTable, aest_node, curr_node, node_header); + + RasInfoTable->num_nodes++; + + if (RasInfoTable->num_nodes >= MAX_NUM_OF_RAS_SUPPORTED) { + sbsa_print(AVS_PRINT_WARN, L"\n Number of RAS nodes greater than %d", + MAX_NUM_OF_RAS_SUPPORTED); + break; + } + + /* Move to the next AEST node */ + aest_node = ADD_PTR(AEST_NODE, aest_node, curr_node->length); + curr_node++; + } + + pal_ras_dump_info_table(RasInfoTable); +} + +/** + @brief Display RAS info table details + + @param RasInfoTable - Address to the RAS information table. + + @return None +**/ +VOID +pal_ras2_dump_info_table(RAS2_INFO_TABLE *RasFeatInfoTable) +{ + RAS2_BLOCK *curr_block; + + if (RasFeatInfoTable == NULL) { + sbsa_print(AVS_PRINT_ERR, L"\n Input RAS Table Pointer is NULL"); + return; + } + + curr_block = RasFeatInfoTable->blocks; + UINT32 i; + + sbsa_print(AVS_PRINT_INFO, L"\nRAS2 Feature Info :"); + sbsa_print(AVS_PRINT_INFO, + L"\n Total number of RAS2 feature info blocks : %d", + RasFeatInfoTable->num_all_block); + sbsa_print(AVS_PRINT_INFO, + L"\n Number of RAS2 memory feature info blocks : %d\n", + RasFeatInfoTable->num_of_mem_block); + + /*Iterate RAS2 feature info table and print info fields */ + for (i = 0 ; i < RasFeatInfoTable->num_all_block ; i++) { + sbsa_print(AVS_PRINT_INFO, L"\n RAS2 feature info * Index %d *", i); + switch(curr_block->type) { + case RAS2_FEATURE_TYPE_MEMORY: + sbsa_print(AVS_PRINT_INFO, L"\n Type : 0x%x", + curr_block->type); + sbsa_print(AVS_PRINT_INFO, L"\n Proximity Domain : 0x%llx", + curr_block->block_info.mem_feat_info.proximity_domain); + sbsa_print(AVS_PRINT_INFO, L"\n Patrol scrub support : 0x%lx\n", + curr_block->block_info.mem_feat_info.patrol_scrub_support); + break; + default: + sbsa_print(AVS_PRINT_INFO, + L"\n Invalid RAS feature type : 0x%x", + curr_block->type); + } + curr_block++; + } +} + + + +/** + @brief This is a helper function to update RAS2_INFO_TABLE block + with required PCCT subspace information for memory instance. + Caller : pal_ras2_create_info_table() + @param pcct - Pointer to PCCT ACPI table + @param curr_block - Pointer to RAS2_BLOCK block. + @param pcct_array_idx - Index of PCCT entry to parse. + + @return None +**/ +VOID pal_ras2_fill_mem_pcct_info( + EFI_ACPI_6_4_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER *pcct, + RAS2_BLOCK *curr_block, + UINT8 pcct_array_idx + ) +{ + + EFI_ACPI_6_4_PCCT_SUBSPACE_GENERIC *pcct_subspace, *pcct_end; + RAS2_PCC_SHARED_MEMORY_REGION *ras2_pcc_shared_mem = NULL; + UINT32 index = 0; + + /* initialise RAS2_MEM_INFO PCCT info fields */ + curr_block->block_info.mem_feat_info.patrol_scrub_support = 0; + + /* pointer to start of PCC subspace structure entries */ + pcct_subspace = ADD_PTR(EFI_ACPI_6_4_PCCT_SUBSPACE_GENERIC, pcct, + sizeof(EFI_ACPI_6_4_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER)); + pcct_end = ADD_PTR(EFI_ACPI_6_4_PCCT_SUBSPACE_GENERIC, pcct, + pcct->Header.Length); + + while (pcct_subspace < pcct_end) { + if (index == pcct_array_idx) { + /* get base address of Generic Communications Channel Shared Memory Region + i.e., RAS2 Platform Communication Channel Shared Memory Region in RAS + context */ + ras2_pcc_shared_mem = (RAS2_PCC_SHARED_MEMORY_REGION * )pcct_subspace->BaseAddress; + /* check if memory instance supports PATROL_SCRUB RAS feature */ + /* RasFeatures[1] is lower 64bits in 128bits member */ + if (ras2_pcc_shared_mem->RasFeatures[1] & RAS2_PLATFORM_FEATURE_PATROL_SCRUB_BITMASK) + curr_block->block_info.mem_feat_info.patrol_scrub_support = 1; + return; + } + /* point to next PCC subspace entry */ + pcct_subspace = ADD_PTR(EFI_ACPI_6_4_PCCT_SUBSPACE_GENERIC, pcct_subspace, + pcct_subspace->Length); + index++; + } + + if (ras2_pcc_shared_mem == NULL) { + sbsa_print(AVS_PRINT_ERR, L"\n No PCC subspace found for PCCT index : 0x%x", pcct_array_idx); + return; + } + + return; +} + +/** + @brief This API fills in the RAS_INFO_TABLE with memory patrol scrub info + from parsing RAS2 ACPI table. + + @return None +**/ +VOID +pal_ras2_create_info_table(RAS2_INFO_TABLE *RasFeatInfoTable) +{ + RAS_FEATURE_2_TABLE_HEADER *ras2; + RAS2_PCC_DESCRIPTOR *ras2_pcc_descp; + RAS2_BLOCK *curr_block; + EFI_ACPI_6_4_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER *pcct; + + + UINT32 i; + UINT8 pcct_array_idx; + + if (RasFeatInfoTable == NULL) { + sbsa_print(AVS_PRINT_ERR, L"\n Input RAS Table Pointer is NULL"); + return; + } + + /* initialise RAS2_INFO_TABLE fields */ + RasFeatInfoTable->num_all_block = 0; + RasFeatInfoTable->num_of_mem_block = 0; + + ras2 = (RAS_FEATURE_2_TABLE_HEADER *)pal_get_acpi_table_ptr(EFI_ACPI_6_5_RAS2_FEATURE_TABLE_SIGNATURE); + if (ras2 == NULL) { + sbsa_print(AVS_PRINT_DEBUG, L" RAS2 ACPI table not found\n"); + return; + } + + pcct = (EFI_ACPI_6_4_PLATFORM_COMMUNICATION_CHANNEL_TABLE_HEADER * ) + pal_get_acpi_table_ptr(EFI_ACPI_6_4_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE); + if (pcct == NULL) { + sbsa_print(AVS_PRINT_DEBUG, L" PCCT ACPI table not found\n"); + return; + } + /* pointer to the start of RAS2 PCC descriptor array */ + ras2_pcc_descp = ADD_PTR(RAS2_PCC_DESCRIPTOR, ras2, sizeof(RAS_FEATURE_2_TABLE_HEADER)); + + /* point to first info block */ + curr_block = RasFeatInfoTable->blocks; + + /* Iterate PCC descriptors and parse corresponding PCC info for each proxomity domain */ + for (i = 0; i < ras2->NumOfPccDescriptors; i++, ras2_pcc_descp++) { + if (ras2_pcc_descp->FeatureType == RAS2_FEATURE_TYPE_MEMORY) { + /* Parse required fields from RAS2 ACPI table*/ + curr_block->type = ras2_pcc_descp->FeatureType; + curr_block->block_info.mem_feat_info.proximity_domain = ras2_pcc_descp->Instance; + pcct_array_idx = ras2_pcc_descp->PccIdentifier; + pal_ras2_fill_mem_pcct_info(pcct, curr_block, pcct_array_idx); + + /* increment block count and move the pointer to next info block*/ + RasFeatInfoTable->num_all_block++; + RasFeatInfoTable->num_of_mem_block++; + curr_block++; + } + } + pal_ras2_dump_info_table(RasFeatInfoTable); +} diff --git a/platform/pal_uefi/src/pal_timer_wd.c b/platform/pal_uefi/src/pal_timer_wd.c index 101120ee..ae301927 100644 --- a/platform/pal_uefi/src/pal_timer_wd.c +++ b/platform/pal_uefi/src/pal_timer_wd.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2018-2019, 2021-2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2018-2019, 2021-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -20,9 +20,6 @@ #include #include -#include -#include "Include/IndustryStandard/Acpi61.h" - #include "include/pal_uefi.h" #include "include/platform_override.h" diff --git a/uefi_app/SbsaAvs.inf b/uefi_app/SbsaAvs.inf index b07490eb..61d05276 100644 --- a/uefi_app/SbsaAvs.inf +++ b/uefi_app/SbsaAvs.inf @@ -148,10 +148,6 @@ ../test_pool/exerciser/test_e014.c ../test_pool/exerciser/test_e015.c ../test_pool/exerciser/test_e016.c - ../test_pool/exerciser/operating_system/test_e017.c - ../test_pool/exerciser/operating_system/test_e018.c - ../test_pool/exerciser/operating_system/test_e019.c - ../test_pool/exerciser/operating_system/test_e020.c ../test_pool/mpam/operating_system/test_mpam001.c ../test_pool/mpam/operating_system/test_mpam002.c diff --git a/uefi_app/SbsaAvsNist.inf b/uefi_app/SbsaAvsNist.inf index a5a54a95..a6769aa8 100644 --- a/uefi_app/SbsaAvsNist.inf +++ b/uefi_app/SbsaAvsNist.inf @@ -148,10 +148,6 @@ ../test_pool/exerciser/test_e014.c ../test_pool/exerciser/test_e015.c ../test_pool/exerciser/test_e016.c - ../test_pool/exerciser/operating_system/test_e017.c - ../test_pool/exerciser/operating_system/test_e018.c - ../test_pool/exerciser/operating_system/test_e019.c - ../test_pool/exerciser/operating_system/test_e020.c ../test_pool/mpam/operating_system/test_mpam001.c ../test_pool/mpam/operating_system/test_mpam002.c diff --git a/val/SbsaValLib.inf b/val/SbsaValLib.inf index dfb2a266..9188bd83 100644 --- a/val/SbsaValLib.inf +++ b/val/SbsaValLib.inf @@ -1,5 +1,5 @@ ## @file -# Copyright (c) 2016-2021, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -28,6 +28,8 @@ src/AArch64/PeTestSupport.S src/AArch64/ArchTimerSupport.S src/AArch64/GicSupport.S + src/AArch64/MpamSupport.s + src/AArch64/RasSupport.S src/avs_status.c src/avs_pe.c src/avs_pe_infra.c @@ -45,6 +47,7 @@ src/avs_memory.c src/avs_exerciser.c src/avs_pgt.c + src/avs_ras.c sys_arch_src/smmu_v3/smmu_v3.c sys_arch_src/gic/gic.c sys_arch_src/gic/sbsa_exception.c @@ -55,10 +58,12 @@ sys_arch_src/gic/v2/gic_v2.c sys_arch_src/gic/its/sbsa_gic_its.c sys_arch_src/gic/its/sbsa_gic_redistributor.c + src/avs_pmu.c + src/avs_mpam.c + src/avs_mmu.c [Packages] MdePkg/MdePkg.dec [BuildOptions] - GCC:*_*_*_ASM_FLAGS = -march=armv8.2-a - GCC:*_*_*_CC_FLAGS = -D ONLY_SBSA_RULE_TESTS + GCC:*_*_*_ASM_FLAGS = -march=armv8.2-a+sve+profile diff --git a/val/SbsaValNistLib.inf b/val/SbsaValNistLib.inf index 0ca2390c..d5329f73 100644 --- a/val/SbsaValNistLib.inf +++ b/val/SbsaValNistLib.inf @@ -1,5 +1,5 @@ ## @file -# Copyright (c) 2020-2021, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2020-2023, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -28,6 +28,8 @@ src/AArch64/PeTestSupport.S src/AArch64/ArchTimerSupport.S src/AArch64/GicSupport.S + src/AArch64/MpamSupport.s + src/AArch64/RasSupport.S src/avs_status.c src/avs_pe.c src/avs_pe_infra.c @@ -46,9 +48,20 @@ src/avs_exerciser.c src/avs_nist.c src/avs_pgt.c + src/avs_ras.c sys_arch_src/smmu_v3/smmu_v3.c - sys_arch_src/gic_its_v3/sbsa_gic_its.c - sys_arch_src/gic_its_v3/sbsa_gic_redistributor.c + sys_arch_src/gic/gic.c + sys_arch_src/gic/sbsa_exception.c + sys_arch_src/gic/AArch64/sbsa_exception_asm.S + sys_arch_src/gic/v3/gic_v3.c + sys_arch_src/gic/v3/gic_v3_extended.c + sys_arch_src/gic/v3/AArch64/v3_asm.S + sys_arch_src/gic/v2/gic_v2.c + sys_arch_src/gic/its/sbsa_gic_its.c + sys_arch_src/gic/its/sbsa_gic_redistributor.c + src/avs_pmu.c + src/avs_mpam.c + src/avs_mmu.c [Packages] StdLib/StdLib.dec @@ -64,5 +77,4 @@ MdePkg/MdePkg.dec [BuildOptions] - GCC:*_*_*_ASM_FLAGS = -march=armv8.2-a - GCC:*_*_*_CC_FLAGS = -D ONLY_SBSA_RULE_TESTS + GCC:*_*_*_ASM_FLAGS = -march=armv8.2-a+sve+profile diff --git a/val/include/sbsa_avs_exerciser.h b/val/include/sbsa_avs_exerciser.h index c44ce3fa..8d807351 100644 --- a/val/include/sbsa_avs_exerciser.h +++ b/val/include/sbsa_avs_exerciser.h @@ -43,7 +43,7 @@ typedef enum { } EXERCISER_INFO_TYPE; -uint32_t val_exerciser_create_info_table(void); +void val_exerciser_create_info_table(void); uint32_t val_exerciser_init(uint32_t instance); uint32_t val_exerciser_get_info(EXERCISER_INFO_TYPE type, uint32_t instance); uint32_t val_exerciser_set_param(EXERCISER_PARAM_TYPE type, uint64_t value1, uint64_t value2, uint32_t instance); diff --git a/val/include/sbsa_avs_gic.h b/val/include/sbsa_avs_gic.h index 467b1b83..adbfbe54 100644 --- a/val/include/sbsa_avs_gic.h +++ b/val/include/sbsa_avs_gic.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Redistribution and use in source and binary forms, with or without @@ -85,10 +85,6 @@ uint32_t g001_entry(uint32_t num_pe); uint32_t g002_entry(uint32_t num_pe); -uint32_t -g003_entry(uint32_t num_pe); -uint32_t -g004_entry(uint32_t num_pe); uint32_t val_get_max_intid(void); diff --git a/val/include/sbsa_avs_iovirt.h b/val/include/sbsa_avs_iovirt.h index 75384673..a13e1490 100644 --- a/val/include/sbsa_avs_iovirt.h +++ b/val/include/sbsa_avs_iovirt.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -23,5 +23,7 @@ uint32_t val_iovirt_check_unique_ctx_intid(uint32_t smmu_index); uint32_t val_iovirt_unique_rid_strid_map(uint32_t rc_index); int val_iovirt_get_device_info(uint32_t rid, uint32_t segment, uint32_t *device_id, uint32_t *stream_id, uint32_t *its_id); uint64_t val_iovirt_get_pcie_rc_info(PCIE_RC_INFO_e type, uint32_t index); +uint64_t val_iovirt_get_named_comp_info(NAMED_COMP_INFO_e type, uint32_t index); +uint64_t val_iovirt_get_pmcg_info(PMCG_INFO_e type, uint32_t index); #endif diff --git a/val/include/sbsa_avs_pcie.h b/val/include/sbsa_avs_pcie.h index 26ea268c..2af8cffd 100644 --- a/val/include/sbsa_avs_pcie.h +++ b/val/include/sbsa_avs_pcie.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -392,4 +392,10 @@ p059_entry(uint32_t num_pe); uint32_t p060_entry(uint32_t num_pe); +uint32_t +p061_entry(uint32_t num_pe); + +uint32_t +p062_entry(uint32_t num_pe); + #endif diff --git a/val/include/sbsa_avs_pcie_spec.h b/val/include/sbsa_avs_pcie_spec.h index 141235fd..f62e82fd 100644 --- a/val/include/sbsa_avs_pcie_spec.h +++ b/val/include/sbsa_avs_pcie_spec.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2019-2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2019-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -188,6 +188,7 @@ #define CID_MSI 0x05 #define CID_MSIX 0x11 #define CID_PMC 0x01 +#define CID_EA 0x14 #define ECID_AER 0x0001 #define ECID_RCECEA 0x0007 #define ECID_ACS 0x000D @@ -195,6 +196,8 @@ #define ECID_ATS 0x000F #define ECID_PRI 0x0013 #define ECID_PASID 0x001B +#define ECID_DPC 0x001D +#define ECID_DVSEC 0x0023 /* PCI Express capability struct offsets */ #define CIDR_OFFSET 0x0 @@ -210,6 +213,66 @@ #define LCAP2R_OFFSET 0x2C #define LCTL2R_OFFSET 0x30 #define DCTL2R_MASK 0xFFFF +#define DSTS_SHIFT 16 +#define DS_UNCORR_MASK 0x6 +#define DS_CORR_MASK 0x1 + +/* DPC Capability struct offsets and shifts */ +#define DPC_CTRL_OFFSET 0x4 +#define DPC_STATUS_OFFSET 0x8 +#define DPC_STATUS_RESET 0xFFFFFFFF +#define DPC_STATUS_MASK 0x1 +#define DPC_TRIGGER_MASK 0x6 +#define DPC_TRIGGER_FATAL 0x2 +#define DPC_TRIGGER_NON_FATAL 0x1 +#define DPC_CTRL_TRG_EN_SHIFT 16 +#define DPC_CTRL_TRG_EN_MASK 0x3 +#define DPC_SOURCE_ID_SHIFT 16 +#define DPC_TRIGGER_SHIFT 0x1 + +/* AER Capability struct offsets and shifts */ +#define ERR_CNT 0x18 +#define AER_UNCORR_STATUS_OFFSET 0x4 +#define AER_UNCORR_MASK_OFFSET 0x8 +#define AER_UNCORR_SEVR_OFFSET 0xC +#define AER_UNCORR_SEVR_FATAL 0xFFFFFFFF +#define AER_UNCORR_SEVR_NONFATAL 0x0 +#define AER_CORR_STATUS_OFFSET 0x10 +#define AER_CORR_MASK_OFFSET 0x14 +#define AER_ROOT_ERR_CMD_OFFSET 0x2C +#define AER_ROOT_ERR_OFFSET 0x30 +#define AER_ROOT_ERR_SOURCE_ID 0x34 +#define AER_SOURCE_ID_SHIFT 16 +#define AER_SOURCE_ID_MASK 0xFFFF +#define AER_ERROR_MASK 0xFFFFFFFF + +/* DPC Capability struct offsets and shifts */ +#define DPC_CTRL_OFFSET 0x4 +#define DPC_STATUS_OFFSET 0x8 +#define DPC_STATUS_RESET 0xFFFFFFFF +#define DPC_STATUS_MASK 0x1 +#define DPC_TRIGGER_MASK 0x6 +#define DPC_TRIGGER_FATAL 0x2 +#define DPC_TRIGGER_NON_FATAL 0x1 +#define DPC_CTRL_TRG_EN_SHIFT 16 +#define DPC_CTRL_TRG_EN_MASK 0x3 +#define DPC_SOURCE_ID_SHIFT 16 +#define DPC_TRIGGER_SHIFT 0x1 +#define DPC_DISABLE_MASK 0xFFFCFFFF +#define DPC_INTR_ENABLE 0x80000 + +/* AER Capability struct offsets and shifts */ +#define AER_UNCORR_STATUS_OFFSET 0x4 +#define AER_UNCORR_MASK_OFFSET 0x8 +#define AER_UNCORR_SEVR_OFFSET 0xC +#define AER_UNCORR_SEVR_FATAL 0xFFFFFFFF +#define AER_UNCORR_SEVR_NONFATAL 0x0 +#define AER_ROOT_ERR_OFFSET 0x30 + +/* EA Capability struct offsets */ +#define EA_ENTRY_TYPE_OFFSET 8 +#define EA_ENTRY_TYPE_ENABLE_SHIFT 31 +#define EA_ENTRY_TYPE_ENABLE_MASK 1 /* ACS Capability Register */ #define ACS_CTRL_SVE_SHIFT 16 diff --git a/val/include/sbsa_avs_pe.h b/val/include/sbsa_avs_pe.h index 0aff60bd..1be123d6 100644 --- a/val/include/sbsa_avs_pe.h +++ b/val/include/sbsa_avs_pe.h @@ -24,6 +24,13 @@ #define MPIDR_AFF_MASK (0xFF00FFFFFF) +/* PE Affinity level masks */ +#define PE_AFFINITY_LVL_1 0xFF00FFFF00ULL +#define PE_AFFINITY_LVL_2 0xFF00FF0000ULL +#define PE_AFFINITY_LVL_3 0xFF00000000ULL + +#define INVALID_PE_INFO 0xDEADDEAD + // // AARCH64 processor exception types. // @@ -134,7 +141,8 @@ typedef enum { RDVL, MAIR_ELx, TCR_ELx, - TTBR_ELx + TTBR_ELx, + ID_AA64ZFR0_EL1 }SBSA_AVS_PE_REGS; uint64_t ArmReadMpidr(void); @@ -297,6 +305,8 @@ void ArmCallWFI(void); void ArmExecuteMemoryBarrier(void); +uint64_t AA64ReadZfr0(void); + void SpeProgramUnderProfiling(uint64_t interval, uint64_t address); void DisableSpe(void); diff --git a/val/include/sbsa_avs_peripherals.h b/val/include/sbsa_avs_peripherals.h index b228c8e5..6b1e6a83 100644 --- a/val/include/sbsa_avs_peripherals.h +++ b/val/include/sbsa_avs_peripherals.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2021, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -37,8 +37,10 @@ uint32_t d003_entry(uint32_t num_pe); #define SBSA_UARTRIS 0x3C #define SBSA_UARTMIS 0x40 #define SBSA_UARTICR 0x44 +#define SBSA_UART_RES 0x50 uint32_t m001_entry(uint32_t num_pe); +uint32_t m002_entry(uint32_t num_pe); #endif // __SBSA_AVS_PERIPHERAL_H__ diff --git a/val/include/sbsa_avs_pgt.h b/val/include/sbsa_avs_pgt.h index a5b3975c..a1b5e0e5 100644 --- a/val/include/sbsa_avs_pgt.h +++ b/val/include/sbsa_avs_pgt.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -22,12 +22,19 @@ #define PGT_STAGE2 2 #define PGT_ENTRY_TABLE_MASK (0x1 << 1) -#define PGT_ENTRY_VALID_MASK 0x1 +#define PGT_ENTRY_VALID_MASK 0x1ULL #define PGT_ENTRY_PAGE_MASK (0x1 << 1) #define PGT_ENTRY_BLOCK_MASK (0x0 << 1) -#define IS_PGT_ENTRY_PAGE(val) (val & 0x2) -#define IS_PGT_ENTRY_BLOCK(val) !(val & 0x2) +#define PGT_ENTRY_TYPE_MASK 0x3ULL +#define PGT_ENTRY_TYPE_TABLE 0x3 +#define PGT_ENTRY_TYPE_BLOCK 0x1 +#define PGT_ENTRY_TYPE_PAGE 0x3 + +#define IS_PGT_ENTRY_PAGE(val) ((val & PGT_ENTRY_TYPE_MASK) == PGT_ENTRY_TYPE_PAGE) +#define IS_PGT_ENTRY_BLOCK(val) ((val & PGT_ENTRY_TYPE_MASK) == PGT_ENTRY_TYPE_BLOCK) +#define IS_PGT_ENTRY_TABLE(val) ((val & PGT_ENTRY_TYPE_MASK) == PGT_ENTRY_TYPE_TABLE) +#define IS_PGT_ENTRY_INVALID(val) !(val & PGT_ENTRY_VALID_MASK) #define PGT_DESC_SIZE 8 #define PGT_DESC_ATTR_UPPER_MASK ((0x1ull << 12) - 1) << 52 @@ -40,6 +47,8 @@ #define PGT_STAGE2_AP_RO (0x1ull << 6) #define PGT_STAGE2_AP_RW (0x3ull << 6) +#define PGT_LEVEL_MAX 4 + uint32_t val_pgt_create(memory_region_descriptor_t *mem_desc, pgt_descriptor_t *pgt_desc); void val_pgt_destroy(pgt_descriptor_t pgt_desc); uint64_t val_pgt_get_attributes(pgt_descriptor_t pgt_desc, uint64_t virtual_address, uint64_t *attributes); diff --git a/val/include/sbsa_avs_smmu.h b/val/include/sbsa_avs_smmu.h index d1fe8d7b..053244da 100644 --- a/val/include/sbsa_avs_smmu.h +++ b/val/include/sbsa_avs_smmu.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -32,6 +32,11 @@ #define SMMUv3_IIDR 0x18 #define SMMUv3_AIDR 0x1C +#define SMMUv3_MPAMIDR 0x130 + +/* PMCG CNTBaseN register offset*/ +#define SMMU_PMCG_CFGR 0xE00 + uint64_t val_smmu_ssid_bits(uint32_t smmu_index); @@ -103,17 +108,4 @@ i015_entry(uint32_t num_pe); uint32_t i016_entry(uint32_t num_pe); -uint32_t -os_i005_entry(uint32_t num_pe); -uint32_t -os_i006_entry(uint32_t num_pe); -uint32_t -os_i007_entry(uint32_t num_pe); -uint32_t -os_i008_entry(uint32_t num_pe); -uint32_t -os_i009_entry(uint32_t num_pe); -uint32_t -hyp_i005_entry(uint32_t num_pe); - #endif diff --git a/val/include/sbsa_avs_timer.h b/val/include/sbsa_avs_timer.h index ff6e1d59..8bfe7624 100644 --- a/val/include/sbsa_avs_timer.h +++ b/val/include/sbsa_avs_timer.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: diff --git a/val/include/sbsa_avs_wd.h b/val/include/sbsa_avs_wd.h index 05ca727c..8cc13748 100644 --- a/val/include/sbsa_avs_wd.h +++ b/val/include/sbsa_avs_wd.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -23,10 +23,4 @@ uint32_t w001_entry(uint32_t num_pe); -uint32_t -w002_entry(uint32_t num_pe); - -uint32_t -w003_entry(uint32_t num_pe); - #endif // __SBSA_AVS_WD_H diff --git a/val/include/val_interface.h b/val/include/val_interface.h index 437eaeec..053fdfa7 100644 --- a/val/include/val_interface.h +++ b/val/include/val_interface.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -69,6 +69,13 @@ void *val_memcpy(void *dest_buffer, void *src_buffer, uint32_t len); uint64_t val_time_delay_ms(uint64_t time_ms); /* VAL PE APIs */ + +typedef enum { + PE_FEAT_MPAM, + PE_FEAT_PMU, + PE_FEAT_RAS +} PE_FEAT_NAME; + uint32_t val_pe_execute_tests(uint32_t level, uint32_t num_pe); uint32_t val_pe_create_info_table(uint64_t *pe_info_table); void val_pe_free_info_table(void); @@ -77,8 +84,11 @@ uint64_t val_pe_get_mpid_index(uint32_t index); uint32_t val_pe_get_pmu_gsiv(uint32_t index); uint64_t val_pe_get_mpid(void); uint32_t val_pe_get_index_mpid(uint64_t mpid); +uint32_t val_pe_get_index_uid(uint32_t uid); +uint32_t val_pe_get_uid(uint64_t mpidr); uint32_t val_pe_install_esr(uint32_t exception_type, void (*esr)(uint64_t, void *)); uint32_t val_pe_get_gmain_gsiv(uint32_t index); +uint32_t val_pe_feat_check(PE_FEAT_NAME pe_feature); void val_execute_on_pe(uint32_t index, void (*payload)(void), uint64_t args); void val_suspend_pe(uint32_t power_state, uint64_t entry, uint32_t context_id); @@ -204,6 +214,7 @@ void val_pcie_enable_msa(uint32_t bdf); uint32_t val_pcie_is_msa_enabled(uint32_t bdf); void val_pcie_clear_urd(uint32_t bdf); uint32_t val_pcie_is_urd(uint32_t bdf); +void val_pcie_enable_eru(uint32_t bdf); void val_pcie_disable_eru(uint32_t bdf); uint32_t val_pcie_bitfield_check(uint32_t bdf, uint64_t *bf_entry); uint32_t val_pcie_register_bitfields_check(uint64_t *bf_info_table, uint32_t table_size); @@ -221,6 +232,8 @@ uint32_t val_pcie_mem_get_offset(uint32_t type); uint32_t val_pcie_link_cap_support(uint32_t bdf); /* IO-VIRT APIs */ +#define INVALID_NAMED_COMP_INFO 0xFFFFFFFFFFFFFFFFULL + typedef enum { SMMU_NUM_CTRL = 1, SMMU_CTRL_BASE, @@ -249,9 +262,24 @@ typedef enum { RC_SEGMENT_NUM, RC_ATS_ATTRIBUTE, RC_MEM_ATTRIBUTE, - RC_IOVIRT_BLOCK + RC_IOVIRT_BLOCK, + RC_SMMU_BASE }PCIE_RC_INFO_e; +typedef enum { + NUM_NAMED_COMP = 1, + NAMED_COMP_CCA_ATTR, + NAMED_COMP_DEV_OBJ_NAME, + NAMED_COMP_SMMU_BASE +} NAMED_COMP_INFO_e; + +typedef enum { + PMCG_NUM_CTRL = 1, + PMCG_CTRL_BASE, + PMCG_IOVIRT_BLOCK, + PMCG_NODE_REF +} PMCG_INFO_e; + void val_iovirt_create_info_table(uint64_t *iovirt_info_table); void val_iovirt_free_info_table(void); uint32_t val_iovirt_get_rc_smmu_index(uint32_t rc_seg_num, uint32_t rid); @@ -259,6 +287,11 @@ uint32_t val_smmu_execute_tests(uint32_t level, uint32_t num_pe); uint64_t val_smmu_get_info(SMMU_INFO_e, uint32_t index); uint64_t val_iovirt_get_smmu_info(SMMU_INFO_e type, uint32_t index); +#ifdef TARGET_LINUX +uint32_t val_get_device_path(const char *hid, char hid_path[][MAX_NAMED_COMP_LENGTH]); +uint32_t val_smmu_is_etr_behind_catu(char *etr_path); +#endif + typedef enum { DMA_NUM_CTRL = 1, DMA_HOST_INFO, @@ -335,12 +368,16 @@ typedef enum { MEM_TYPE_NORMAL, MEM_TYPE_RESERVED, MEM_TYPE_NOT_POPULATED, + MEM_TYPE_PERSISTENT, MEM_TYPE_LAST_ENTRY }MEMORY_INFO_e; #define MEM_ATTR_UNCACHED 0x2000 #define MEM_ATTR_CACHED 0x1000 +/* MMU entries APIs*/ +uint32_t val_mmu_update_entry(uint64_t address, uint32_t size); + /* Identify memory type using MAIR attribute, refer to ARM ARM VMSA for details */ #define MEM_NORMAL_WB_IN_OUT(attr) (((attr & 0xcc) == 0xcc) || (((attr & 0x7) >= 5) && (((attr >> 4) & 0x7) >= 5))) @@ -354,24 +391,113 @@ uint32_t val_memory_execute_tests(uint32_t level, uint32_t num_pe); uint64_t val_memory_get_info(addr_t addr, uint64_t *attr); uint64_t val_memory_get_unpopulated_addr(addr_t *addr, uint32_t instance); -/* Secure mode EL3 Firmware tests */ - -typedef struct { - uint64_t test_index; - uint64_t test_arg01; - uint64_t test_arg02; - uint64_t test_arg03; -} SBSA_SMC_t; - -void val_secure_call_smc(SBSA_SMC_t *smc); -uint32_t val_secure_get_result(SBSA_SMC_t *smc, uint32_t timeout); -uint32_t val_secure_execute_tests(uint32_t level, uint32_t num_pe); -uint32_t val_secure_trusted_firmware_init(void); - /* PCIe Exerciser tests */ uint32_t val_exerciser_execute_tests(uint32_t level); /* NIST Statistical tests */ uint32_t val_nist_execute_tests(uint32_t level, uint32_t num_pe); uint32_t val_nist_generate_rng(uint32_t *rng_buffer); + +/* PMU test related APIS*/ +void val_pmu_create_info_table(uint64_t *pmu_info_table); +void val_pmu_free_info_table(void); +uint32_t val_pmu_execute_tests(uint32_t level, uint32_t num_pe); + +/*Cache related info APIs*/ +#define INVALID_CACHE_INFO 0xFFFFFFFFFFFFFFFF +#define CACHE_TABLE_EMPTY 0xFFFFFFFF + +typedef enum { + CACHE_TYPE, + CACHE_SIZE, + CACHE_ID, + CACHE_NEXT_LEVEL_IDX, + CACHE_PRIVATE_FLAG +} CACHE_INFO_e; + +void val_cache_create_info_table(uint64_t *cache_info_table); +void val_cache_free_info_table(void); +uint64_t val_cache_get_info(CACHE_INFO_e type, uint32_t cache_index); +uint32_t val_cache_get_llc_index(void); +uint32_t val_cache_get_pe_l1_cache_res(uint32_t res_index); + +/* MPAM tests APIs */ +#define MPAM_INVALID_INFO 0xFFFFFFFF +#define SRAT_INVALID_INFO 0xFFFFFFFF +#define HMAT_INVALID_INFO 0xFFFFFFFF + +uint32_t val_mpam_execute_tests(uint32_t level, uint32_t num_pe); +void val_mpam_create_info_table(uint64_t *mpam_info_table); +void val_mpam_free_info_table(void); + +typedef enum { + MPAM_RSRC_TYPE_PE_CACHE, + MPAM_RSRC_TYPE_MEMORY, + MPAM_RSRC_TYPE_SMMU, + MPAM_RSRC_TYPE_MEM_SIDE_CACHE, + MPAM_RSRC_TYPE_ACPI_DEVICE, + MPAM_RSRC_TYPE_UNKNOWN = 0xFF /* 0x05-0xFE Reserved for future use */ +} MPAM_RSRC_LOCATOR_TYPE; + +/* MPAM info request types*/ +typedef enum { + MPAM_MSC_RSRC_COUNT, + MPAM_MSC_RSRC_RIS, + MPAM_MSC_RSRC_TYPE, + MPAM_MSC_BASE_ADDR, + MPAM_MSC_ADDR_LEN, + MPAM_MSC_RSRC_DESC1, + MPAM_MSC_NRDY +} MPAM_INFO_e; + +/* RAS APIs */ +#define INVALID_RAS2_INFO 0xFFFFFFFFFFFFFFFFULL +#define INVALID_RAS_REG_VAL 0xDEADDEADDEADDEADULL +#define RAS2_FEATURE_TYPE_MEMORY 0x0 + +typedef enum { + RAS2_NUM_MEM_BLOCK, + RAS2_PROX_DOMAIN, + RAS2_SCRUB_SUPPORT +} RAS2_MEM_INFO_e; + +uint32_t val_ras_execute_tests(uint32_t level, uint32_t num_pe); +uint32_t val_ras_create_info_table(uint64_t *ras_info_table); +uint32_t val_ras_get_info(uint32_t info_type, uint32_t param1, uint64_t *ret_data); +void val_ras2_create_info_table(uint64_t *ras2_info_table); +void val_ras2_free_info_table(void); +uint64_t val_ras2_get_mem_info(RAS2_MEM_INFO_e type, uint32_t index); + +/* HMAT APIs */ +void val_hmat_create_info_table(uint64_t *hmat_info_table); +void val_hmat_free_info_table(void); + +/* SRAT APIs */ +typedef enum { + SRAT_MEM_NUM_MEM_RANGE, + SRAT_MEM_BASE_ADDR, + SRAT_MEM_ADDR_LEN, + SRAT_GICC_PROX_DOMAIN, + SRAT_GICC_PROC_UID, + SRAT_GICC_REMOTE_PROX_DOMAIN +} SRAT_INFO_e; + +void val_srat_create_info_table(uint64_t *srat_info_table); +void val_srat_free_info_table(void); +uint64_t val_srat_get_info(SRAT_INFO_e type, uint64_t prox_domain); + +#define PMU_INVALID_INFO 0xFFFFFFFFFFFFFFFF +#define PMU_INVALID_INDEX 0xFFFFFFFF + +/* PMU info request types */ +typedef enum { + PMU_NODE_TYPE, /* PMU Node type */ + PMU_NODE_BASE0, /* Page 0 Base address */ + PMU_NODE_BASE1, /* Page 1 Base address */ + PMU_NODE_PRI_INST, /* Primary instance */ + PMU_NODE_SEC_INST, /* Secondary instance */ + PMU_NODE_COUNT, /* PMU Node count */ + PMU_NODE_DP_EXTN, /* Dual page extension support */ +} PMU_INFO_e; + #endif diff --git a/val/src/AArch64/PeRegSysSupport.S b/val/src/AArch64/PeRegSysSupport.S index eb2587a9..8b7aee18 100644 --- a/val/src/AArch64/PeRegSysSupport.S +++ b/val/src/AArch64/PeRegSysSupport.S @@ -1,5 +1,5 @@ #/** @file -# Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -117,6 +117,7 @@ GCC_ASM_EXPORT (AA64ReadTtbr0El1) GCC_ASM_EXPORT (AA64ReadTtbr0El2) GCC_ASM_EXPORT (AA64ReadTtbr1El1) GCC_ASM_EXPORT (AA64ReadTtbr1El2) +GCC_ASM_EXPORT (AA64ReadZfr0) ASM_PFX(ArmReadMpidr): mrs x0, mpidr_el1 // read EL1 MPIDR @@ -336,7 +337,7 @@ ASM_PFX(AA64ReadVpidr): ret ASM_PFX(AA64ReadPmbidr): - //mrs x0, pmbidr_el1 + mrs x0, pmbidr_el1 ret ASM_PFX(AA64ReadPmsidr): @@ -445,3 +446,6 @@ ASM_PFX(ArmRdvl): .inst 0x04BF5100 ret +ASM_PFX(AA64ReadZfr0): + mrs x0, id_aa64zfr0_el1 + ret diff --git a/val/src/avs_gic.c b/val/src/avs_gic.c index 477779e9..b37f1060 100644 --- a/val/src/avs_gic.c +++ b/val/src/avs_gic.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2021-2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2021-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -54,12 +54,12 @@ val_gic_execute_tests(uint32_t level, uint32_t num_pe) } g_curr_module = 1 << GIC_MODULE; + status = g001_entry(num_pe); -#ifndef ONLY_SBSA_RULE_TESTS - status |= g002_entry(num_pe); - status |= g003_entry(num_pe); - status |= g004_entry(num_pe); -#endif + + if (level > 4) { + status = g002_entry(num_pe); + } val_print_test_end(status, "GIC"); diff --git a/val/src/avs_iovirt.c b/val/src/avs_iovirt.c index cff6dd3f..64d28416 100644 --- a/val/src/avs_iovirt.c +++ b/val/src/avs_iovirt.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2021, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -103,7 +103,7 @@ val_iovirt_get_pcie_rc_info(PCIE_RC_INFO_e type, uint32_t index) if(type == NUM_PCIE_RC) return g_iovirt_info_table->num_pci_rcs; - /* Go through the table return the relevant field value for the SMMU block */ + /* Go through the table return the relevant field value for the PCIe root complex block */ /* at the index position */ block = &g_iovirt_info_table->blocks[0]; for(i = 0; i < g_iovirt_info_table->num_blocks; i++, block=IOVIRT_NEXT_BLOCK(block)) @@ -122,6 +122,8 @@ val_iovirt_get_pcie_rc_info(PCIE_RC_INFO_e type, uint32_t index) return block->data.rc.ats_attr; case RC_IOVIRT_BLOCK: return (uint64_t)block; + case RC_SMMU_BASE: + return block->data.rc.smmu_base; default: val_print(AVS_PRINT_ERR, "This PCIe RC info option not supported %d \n", type); return 0; @@ -139,6 +141,129 @@ val_iovirt_get_pcie_rc_info(PCIE_RC_INFO_e type, uint32_t index) } +/** + @brief This API is a single point of entry to retrieve + Named component info stored in the iovirt info table. + 1. Caller - Test suite + 2. Prerequisite - val_iovirt_create_info_table + @param type the type of information being requested. + @param index the index of named component info instance. + @return 64-bit data +**/ +uint64_t +val_iovirt_get_named_comp_info(NAMED_COMP_INFO_e type, uint32_t index) +{ + uint32_t i, j = 0; + IOVIRT_BLOCK *block; + + if (g_iovirt_info_table == NULL) + { + val_print(AVS_PRINT_ERR, "GET_NAMED_COMP_INFO: iovirt info table is not created \n", 0); + return 0; /* imply no named components parsed */ + } + + if (type == NUM_NAMED_COMP) + return g_iovirt_info_table->num_named_components; + + /* check if index in range */ + if (index > g_iovirt_info_table->num_named_components - 1) { + val_print(AVS_PRINT_ERR, + "GET_NAMED_COMP_INFO: Index (%d) is greater than num of Named components \n", + index); + return INVALID_NAMED_COMP_INFO; + } + + /* Go through the table return the relevant field value for the Named component block */ + /* at the index position */ + block = &g_iovirt_info_table->blocks[0]; + for (i = 0; i < g_iovirt_info_table->num_blocks; i++, block = IOVIRT_NEXT_BLOCK(block)) + { + if (block->type == IOVIRT_NODE_NAMED_COMPONENT) + { + if (j == index) + { + switch (type) + { + case NAMED_COMP_CCA_ATTR: + return block->data.named_comp.cca; + case NAMED_COMP_DEV_OBJ_NAME: + /* caller needs to typecast data to (char *) to retrieve full path + to named component in namespace */ + return (uint64_t)block->data.named_comp.name; + case NAMED_COMP_SMMU_BASE: + return block->data.named_comp.smmu_base; + default: + val_print(AVS_PRINT_ERR, + "This Named component info option not supported %d \n", type); + return INVALID_NAMED_COMP_INFO; + } + } + j++; + } + } + + return INVALID_NAMED_COMP_INFO; +} + +/** + @brief This API is a single point of entry to retrieve + PMCG information stored in the IoVirt Info table + 1. Caller - Test suite + 2. Prerequisite - val_iovirt_create_info_table + @param type the type of information being requested + @param index the index of pmcg info instance. + @return 64-bit data +**/ +uint64_t +val_iovirt_get_pmcg_info(PMCG_INFO_e type, uint32_t index) +{ + uint32_t i, j = 0; + IOVIRT_BLOCK *block; + + if (g_iovirt_info_table == NULL) + { + val_print(AVS_PRINT_ERR, "GET_PMCG_INFO: iovirt info table is not created \n", 0); + return 0; + } + + if (type == PMCG_NUM_CTRL) + return g_iovirt_info_table->num_pmcgs; + + /* Go through the table return the relevant field value for the SMMU block */ + /* at the index position */ + block = &g_iovirt_info_table->blocks[0]; + for (i = 0; i < g_iovirt_info_table->num_blocks; i++, block = IOVIRT_NEXT_BLOCK(block)) + { + if (block->type == IOVIRT_NODE_PMCG) + { + if (j == index) + { + switch (type) + { + case PMCG_CTRL_BASE: + return block->data.pmcg.base; + case PMCG_IOVIRT_BLOCK: + return (uint64_t)block; + case PMCG_NODE_REF: + return block->data.pmcg.node_ref; + default: + val_print(AVS_PRINT_ERR, "This PMCG info option not supported %d \n", type); + return 0; + } + } + j++; + } + } + + if (index > j-1) + { + val_print(AVS_PRINT_ERR, "GET_PMCG_INFO: Index (%d) is greater than num of PMCG \n", index); + return 0; + } + return j; +} + + uint32_t val_iovirt_unique_rid_strid_map(uint32_t rc_index) { @@ -312,3 +437,40 @@ val_iovirt_get_rc_smmu_index(uint32_t rc_seg_num, uint32_t rid) val_print(AVS_PRINT_INFO, "RC with segment number %d is not behind any SMMU", rc_seg_num); return AVS_INVALID_INDEX; } + +#ifdef TARGET_LINUX +/** + @brief This API will call PAL layer to fill in the path of the hid passed in the + hid parameter. + 1. Caller - Application layer. + @param hid hardware ID of the device to which the path is filled + @param hid_path 2D array in which the path is stored + @return Error if not able to find the path of given hid +**/ +uint32_t +val_get_device_path(const char *hid, char hid_path[][MAX_NAMED_COMP_LENGTH]) +{ + uint32_t status = 0; + + status = pal_get_device_path(hid, hid_path); + + return status; +} + +/** + @brief This API will call PAL layer to check if etr is behind the catu. + 1. Caller - Application layer. + @param etr_path path of ETR + @return Error if CATU is not behind ETR device +**/ + +uint32_t +val_smmu_is_etr_behind_catu(char *etr_path) +{ + uint32_t status = 0; + + status = pal_smmu_is_etr_behind_catu(etr_path); + + return status; +} +#endif diff --git a/val/src/avs_pcie.c b/val/src/avs_pcie.c index 7649bcc5..2cfedf69 100644 --- a/val/src/avs_pcie.c +++ b/val/src/avs_pcie.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -283,7 +283,6 @@ val_pcie_execute_tests(uint32_t enable_pcie, uint32_t level, uint32_t num_pe) g_curr_module = 1 << PCIE_MODULE; -#ifdef ONLY_SBSA_RULE_TESTS #ifdef TARGET_LINUX status = p009_entry(num_pe); /* This covers GIC rule */ #endif @@ -291,38 +290,17 @@ val_pcie_execute_tests(uint32_t enable_pcie, uint32_t level, uint32_t num_pe) val_print(AVS_PRINT_TEST, " RCiEP and iEP tests are for sbsa level 6+ \n", 0); return AVS_STATUS_SKIP; } -#endif status = p001_entry(num_pe); - if (status == AVS_STATUS_FAIL) { + if (status != AVS_STATUS_PASS) { val_print(AVS_PRINT_WARN, "\n *** Skipping remaining PCIE tests *** \n", 0); return status; } -#ifndef ONLY_SBSA_RULE_TESTS - status |= p002_entry(num_pe); -#endif - #ifdef TARGET_LINUX status |= p005_entry(num_pe); -#ifndef ONLY_SBSA_RULE_TESTS - status |= p006_entry(num_pe); - status |= p007_entry(num_pe); - status |= p008_entry(num_pe); - status |= p009_entry(num_pe); - status |= p010_entry(num_pe); - status |= p011_entry(num_pe); - status |= p012_entry(num_pe); - status |= p013_entry(num_pe); - status |= p014_entry(num_pe); - status |= p015_entry(num_pe); - status |= p016_entry(num_pe); - status |= p017_entry(num_pe); - status |= p018_entry(num_pe); - status |= p019_entry(num_pe); -#endif #else if (g_pcie_bdf_table->num_entries == 0) { @@ -368,17 +346,12 @@ val_pcie_execute_tests(uint32_t enable_pcie, uint32_t level, uint32_t num_pe) status |= p052_entry(num_pe); status |= p056_entry(num_pe); /* iEP/RP only */ status |= p057_entry(num_pe); -#ifndef ONLY_SBSA_RULE_TESTS - status |= p040_entry(num_pe); - status |= p053_entry(num_pe); - status |= p054_entry(num_pe); - status |= p055_entry(num_pe); -#endif -#ifdef ONLY_SBSA_RULE_TESTS status |= p058_entry(num_pe); status |= p059_entry(num_pe); status |= p060_entry(num_pe); -#endif + status |= p061_entry(num_pe); + status |= p062_entry(num_pe); + } #endif @@ -403,7 +376,7 @@ val_pcie_print_device_info(void) if (bdf_tbl_ptr->num_entries == 0) { - val_print(AVS_PRINT_ERR, " PCIE_INFO: BDF Table: No RCiEP or iEP devices found\n", 0); + val_print(AVS_PRINT_DEBUG, " BDF Table: No RCiEP or iEP found\n", 0); return; } @@ -583,11 +556,9 @@ val_pcie_create_device_bdf_table() dp_type = val_pcie_device_port_type(bdf); val_print(AVS_PRINT_INFO, "\n dp_type 0x%x ", dp_type); -#ifdef ONLY_SBSA_RULE_TESTS /* SBSA 6.1 have only rciep and iep/rp rules only */ if ((dp_type != RCiEP) && (dp_type != iEP_EP) && (dp_type != iEP_RP)) continue; -#endif status = pal_pcie_check_device_valid(bdf); if (status) continue; @@ -599,16 +570,19 @@ val_pcie_create_device_bdf_table() } } - val_print(AVS_PRINT_INFO, - " PCIE_INFO: Number of valid BDFs is %x\n", g_pcie_bdf_table->num_entries); - /* Sanity Check : Confirm all EP (normal, integrated) have a rootport */ if (val_pcie_populate_device_rootport()) { /* Discard the bdf table */ g_pcie_bdf_table->num_entries = 0; + val_print(AVS_PRINT_TEST, + " PCIE_INFO: Number of BDFs found : %x\n", g_pcie_bdf_table->num_entries); + return 1; } + val_print(AVS_PRINT_TEST, + " PCIE_INFO: Number of BDFs found : %x\n", g_pcie_bdf_table->num_entries); + return 0; } @@ -1489,6 +1463,43 @@ val_pcie_is_sig_target_abort(uint32_t bdf) return 0; } +/** + @brief Enable error reporting of the PCIe Function to the upstream + @param bdf - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF + @return None +**/ +void +val_pcie_enable_eru(uint32_t bdf) +{ + + uint32_t reg_value; + uint32_t dis_mask; + uint32_t pciecs_base; + + /* Set SERR# Enable bit in the Command Register to enable reporting + * upstream of Non-fatal and Fatal errors detected by the Function. + */ + val_pcie_read_cfg(bdf, TYPE01_CR, ®_value); + dis_mask = (1 << CR_SERRE_SHIFT); + val_pcie_write_cfg(bdf, TYPE01_CR, reg_value | dis_mask); + + /* Get the PCI Express Capability structure offset and + * use that offset to read the Device Control register + */ + val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &pciecs_base); + val_pcie_read_cfg(bdf, pciecs_base + DCTLR_OFFSET, ®_value); + + /* Set Correctable, Non-fatal, Fatal, UR Reporting Enable bits in the + * Device Control Register to enable reporting upstream of these errors + * detected by the Function. + */ + dis_mask = (1 << DCTLR_CERE_SHIFT | + 1 << DCTLR_NFERE_SHIFT | + 1 << DCTLR_FERE_SHIFT | + 1 << DCTLR_URRE_SHIFT); + val_pcie_write_cfg(bdf, pciecs_base + DCTLR_OFFSET, reg_value | dis_mask); +} + /** @brief Disable error reporting of the PCIe Function to the upstream @param bdf - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF @@ -1782,6 +1793,7 @@ val_pcie_get_mmio_bar(uint32_t bdf, void *base) val_print(AVS_PRINT_ERR, "\n pal_exerciser_get_data() not implemented", 0); } + /* data.bar_space.base_addr will be zero if no MMIO bar are present for the function */ *(uint64_t *)base = (uint64_t)data.bar_space.base_addr; return; } diff --git a/val/src/avs_pe.c b/val/src/avs_pe.c index ba83648a..e8b24cd9 100644 --- a/val/src/avs_pe.c +++ b/val/src/avs_pe.c @@ -247,6 +247,8 @@ val_pe_reg_read(uint32_t reg_id) return AA64ReadTcr1(); if (AA64ReadCurrentEL() == AARCH64_EL2) return AA64ReadTcr2(); + case ID_AA64ZFR0_EL1: + return AA64ReadZfr0(); default: val_report_status(val_pe_get_index_mpid(val_pe_get_mpid()), RESULT_FAIL(g_sbsa_level, 0, 0x78), NULL); @@ -486,3 +488,41 @@ val_pe_get_gmain_gsiv(uint32_t index) return entry[index].gmain_gsiv; } + +/** + @brief This API checks whether the requested PE feature is implemented or not. + @param pe_feature - PE feature to be checked. + @return AVS_STATUS_PASS if implemented., else AVS_STATUS_FAIL. +**/ +uint32_t val_pe_feat_check(PE_FEAT_NAME pe_feature) +{ + uint64_t data; + + switch (pe_feature) { + case PE_FEAT_MPAM: + /* ID_AA64PFR0_EL1.MPAM bits[43:40] > 0 or ID_AA64PFR1_EL1.MPAM_frac bits[19:16] > 0 + indicates implementation of MPAM extension */ + if ((VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 40, 43) > 0) || + (VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR1_EL1), 16, 19) > 0)) + return AVS_STATUS_PASS; + else + return AVS_STATUS_FAIL; + case PE_FEAT_PMU: + /* ID_AA64DFR0_EL1.PMUVer, bits [11:8] == 0000 or 1111 + indicate PMU extension not implemented */ + data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64DFR0_EL1), 8, 11); + if (!(data == 0 || data == 0xF)) + return AVS_STATUS_PASS; + else + return AVS_STATUS_FAIL; + case PE_FEAT_RAS: + /* ID_AA64PFR0_EL1 RAS bits [31:28] != 0 indicate RAS extension implemented */ + if ((VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 28, 31)) != 0) + return AVS_STATUS_PASS; + else + return AVS_STATUS_FAIL; + default: + val_print(AVS_PRINT_ERR, "\nPE_FEAT_CHECK: Invalid PE feature", 0); + return AVS_STATUS_FAIL; + } +} diff --git a/val/src/avs_pe_infra.c b/val/src/avs_pe_infra.c index ed3a89c1..77689128 100644 --- a/val/src/avs_pe_infra.c +++ b/val/src/avs_pe_infra.c @@ -27,6 +27,12 @@ int32_t gPsciConduit; @brief Pointer to the memory location of the PE Information table **/ PE_INFO_TABLE *g_pe_info_table; + +/** + @brief Pointer to the memory location of the cache Information table +**/ +CACHE_INFO_TABLE *g_cache_info_table; + /** @brief global structure to pass and retrieve arguments for the SMC call **/ @@ -182,6 +188,60 @@ val_pe_get_index_mpid(uint64_t mpid) return 0x0; //Return index 0 as a safe failsafe value } +/** + @brief This API returns the index of the PE whose ACPI UID matches with the input UID + 1. Caller - Test Suite, VAL + 2. Prerequisite - val_create_peinfo_table + @param mpid - the mpidr value of pE whose index is returned. + @return Index of PE +**/ +uint32_t +val_pe_get_index_uid(uint32_t uid) +{ + + PE_INFO_ENTRY *entry; + uint32_t i = g_pe_info_table->header.num_of_pe; + + entry = g_pe_info_table->pe_info; + + while (i > 0) { + if (entry->acpi_proc_uid == uid) { + return entry->pe_num; + } + entry++; + i--; + } + + return 0x0; //Return index 0 as a safe failsafe value +} + + +/** + @brief This API returns the ACPI UID of the PE whose MPIDR matches with the input MPIDR + 1. Caller - Test Suite, VAL + 2. Prerequisite - val_create_pe_info_table + @param mpidr - the MPIDR value of PE whose UID is returned. + @return ACPI UID of the processor. +**/ +uint32_t +val_pe_get_uid(uint64_t mpidr) +{ + + PE_INFO_ENTRY *entry; + uint32_t i = g_pe_info_table->header.num_of_pe; + + entry = g_pe_info_table->pe_info; + + while (i > 0) { + if (entry->mpidr == mpidr) { + return entry->acpi_proc_uid; + } + entry++; + i--; + } + + return INVALID_PE_INFO; +} /** @brief 'C' Entry point for Secondary PE. @@ -379,3 +439,148 @@ val_pe_cache_clean_range(uint64_t start_addr, uint64_t length) } #endif } + +/** + @brief This API will call PAL layer to fill in the PPTT ACPI table information + into the g_cache_info_table pointer. + 1. Caller - Application layer. + 2. Prerequisite - Memory allocated and passed as argument. + @param cache_info_table pre-allocated memory pointer for cache info. + @return Error if Input parameter is NULL +**/ +void +val_cache_create_info_table(uint64_t *cache_info_table) +{ + if (cache_info_table == NULL) { + val_print(AVS_PRINT_ERR, "\n Pre-allocated memory pointer is NULL \n", 0); + return; + } + + g_cache_info_table = (CACHE_INFO_TABLE *)cache_info_table; +#ifndef TARGET_LINUX + pal_cache_create_info_table(g_cache_info_table, g_pe_info_table); + + if (g_cache_info_table->num_of_cache != 0) { + val_print(AVS_PRINT_TEST, + " CACHE_INFO: Number of cache nodes : %4d\n", + g_cache_info_table->num_of_cache); + } + +#endif +} + +/** + @brief This API frees the memory allocated for cache info table. + @param None + @return None +**/ +void +val_cache_free_info_table(void) +{ + pal_mem_free((void *)g_cache_info_table); +} + +/** + @brief This API returns info of the cache indexed in cache info table. + @param type - requested info type. + @param cache_index - index of the cache in cache info table. + @return info value in 64-bit unsigned int if success, + else returns INVALID_CACHE_INFO indicating failure. +**/ +uint64_t +val_cache_get_info(CACHE_INFO_e type, uint32_t cache_index) +{ + CACHE_INFO_ENTRY *entry; + char *cache_info_type[] = {"cache_type", "cache_size", "cache_identifier"}; + + if (cache_index >= g_cache_info_table->num_of_cache) { + val_print(AVS_PRINT_ERR, "\n invalid cache index: %d", cache_index); + return 0; + } + entry = &(g_cache_info_table->cache_info[cache_index]); + switch (type) { + case CACHE_TYPE: + if (entry->flags.cache_type_valid) + return entry->cache_type; + break; + case CACHE_SIZE: + if (entry->flags.size_property_valid) + return entry->size; + break; + case CACHE_ID: + if (entry->flags.cache_id_valid) + return entry->cache_id; + break; + case CACHE_NEXT_LEVEL_IDX: + return entry->next_level_index; + case CACHE_PRIVATE_FLAG: + return entry->is_private; + default: + val_print(AVS_PRINT_ERR, + "\n cache option not supported %d \n", type); + return INVALID_CACHE_INFO; + } + + val_print(AVS_PRINT_ERR, + "\n cache %d has invalid ", cache_index); + val_print(AVS_PRINT_ERR, cache_info_type[type], 0); + return INVALID_CACHE_INFO; +} + +/** + @brief This API returns index of last-level cache in cache info table + for the current PE. + + @return index of the last-level cache. +**/ +uint32_t +val_cache_get_llc_index(void) +{ + uint32_t curr_cache_idx; + uint32_t next_lvl_idx; + uint32_t llc_idx = CACHE_INVALID_IDX; + if (g_cache_info_table->num_of_cache) { + /* get first level private cache index for current PE */ + /* setting res_index to 0 since PE should have atleast one L1 cache */ + curr_cache_idx = val_cache_get_pe_l1_cache_res(0); + + /* get to last level cache in the cache info chain */ + while (curr_cache_idx != CACHE_INVALID_NEXT_LVL_IDX) { + /* check if next level cache is present */ + next_lvl_idx = val_cache_get_info(CACHE_NEXT_LEVEL_IDX, curr_cache_idx); + if (next_lvl_idx == CACHE_INVALID_NEXT_LVL_IDX) { + llc_idx = curr_cache_idx; + break; + } + else + curr_cache_idx = next_lvl_idx; + } + + return llc_idx; + } + else { + val_print(AVS_PRINT_DEBUG, "\n CACHE INFO table invalid", 0); + return CACHE_TABLE_EMPTY; + } +} + +/** + @brief This API returns level 1 cache index for resource index requested. + @param res_index level 1 private resource index. + @return return index of cache in the cache info table. +**/ +uint32_t +val_cache_get_pe_l1_cache_res(uint32_t res_index) +{ + PE_INFO_ENTRY *entry; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + entry = &(g_pe_info_table->pe_info[index]); + if (res_index < MAX_L1_CACHE_RES) + return entry->level_1_res[res_index]; + else { + val_print(AVS_PRINT_ERR, + "\n Requested resource index exceeds maximum index value %d\n", MAX_L1_CACHE_RES); + return DEFAULT_CACHE_IDX; + } +} diff --git a/val/src/avs_peripherals.c b/val/src/avs_peripherals.c index 7ea417e0..35edb23c 100644 --- a/val/src/avs_peripherals.c +++ b/val/src/avs_peripherals.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2021-2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -36,7 +36,7 @@ uint32_t val_peripheral_execute_tests(uint32_t level, uint32_t num_pe) { - uint32_t status, i; + uint32_t status = AVS_STATUS_SKIP, i; for (i=0 ; i> TYPE01_BCC_SHIFT; - if (base_cc == CNTRL_CC) - ntwk++; - if (base_cc == DP_CNTRL_CC) - dply++; - if (base_cc == MAS_CC) - strg++; - else - continue; + for (func = 0; func < PCIE_MAX_FUNC; func++) + { + dev_bdf = PCIE_CREATE_BDF(seg, bus, dev, func); + val_pcie_read_cfg(dev_bdf, TYPE01_VIDR, ®_value); + if (reg_value == PCIE_UNKNOWN_RESPONSE) + continue; + val_pcie_read_cfg(dev_bdf, TYPE01_RIDR, ®_value); + val_print(AVS_PRINT_DEBUG, "\n BDF is %x", dev_bdf); + val_print(AVS_PRINT_DEBUG, "\n Class code is %x", reg_value); + base_cc = reg_value >> TYPE01_BCC_SHIFT; + if (base_cc == CNTRL_CC) + ntwk++; + if (base_cc == DP_CNTRL_CC) + dply++; + if (base_cc == MAS_CC) + strg++; + else + continue; + } } } } @@ -284,7 +287,7 @@ val_peripheral_create_info_table(uint64_t *peripheral_info_table) pal_peripheral_create_info_table(g_peripheral_info_table); - val_print(AVS_PRINT_TEST, "\n Peripheral: Num of USB controllers : %d \n", + val_print(AVS_PRINT_TEST, " Peripheral: Num of USB controllers : %d \n", val_peripheral_get_info(NUM_USB, 0)); val_print(AVS_PRINT_TEST, " Peripheral: Num of SATA controllers : %d \n", val_peripheral_get_info(NUM_SATA, 0)); diff --git a/val/src/avs_pgt.c b/val/src/avs_pgt.c index 98b9afea..5e6a9db6 100644 --- a/val/src/avs_pgt.c +++ b/val/src/avs_pgt.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2019, 2021-2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -138,6 +138,8 @@ uint32_t log2_page_size(uint64_t size) /** @brief Create stage 1 or stage 2 page table, with given memory addresses and attributes + Note: This API updates existing translation table if pgt_desc->pgt_base is not NULL + else it created new table and updated pgt_desc->pgt_base with the address. @param mem_desc - Array of memory addresses and attributes needed for page table creation. @param pgt_desc - Data structure for output page table base and input translation attributes. @return status @@ -157,21 +159,28 @@ uint32_t val_pgt_create(memory_region_descriptor_t *mem_desc, pgt_descriptor_t * val_print(PGT_DEBUG_LEVEL, "\n val_pgt_create: nbits_per_level = %d ", bits_per_level); val_print(PGT_DEBUG_LEVEL, "\n val_pgt_create: page_size_log2 = %d ", page_size_log2); - tt_base = (uint64_t*) val_memory_alloc_pages(1); - if (tt_base == NULL) - { - val_print(AVS_PRINT_ERR, "\n val_pgt_create: page allocation failed ", 0); - return AVS_STATUS_ERR; + /* check whether input page descriptor has base addr of translation table + to use. If the pgt_base member is NULL allocate a page to create a new + table, else update existing translation table */ + if (pgt_desc->pgt_base == (uint64_t) NULL) { + tt_base = (uint64_t *) val_memory_alloc_pages(1); + if (tt_base == NULL) { + val_print(AVS_PRINT_ERR, "\n val_pgt_create: page allocation failed ", 0); + return AVS_STATUS_ERR; + } + val_memory_set(tt_base, page_size, 0); } - val_memory_set(tt_base, page_size, 0); + else + tt_base = (uint64_t *) pgt_desc->pgt_base; + tt_desc.tt_base = tt_base; - pgt_addr_mask = ((0x1ull << (48 - page_size_log2)) - 1) << page_size_log2; + pgt_addr_mask = ((0x1ull << (pgt_desc->ias - page_size_log2)) - 1) << page_size_log2; for (mem_desc_iter = mem_desc; mem_desc_iter->length != 0; ++mem_desc_iter) { - val_print(PGT_DEBUG_LEVEL, "val_pgt_create: i/p addr 0x%llx", mem_desc->virtual_address); - val_print(PGT_DEBUG_LEVEL, "val_pgt_create: o/p addr 0x%llx", mem_desc->physical_address); - val_print(PGT_DEBUG_LEVEL, "val_pgt_create: length 0x%llx\n ", mem_desc->length); + val_print(PGT_DEBUG_LEVEL, " val_pgt_create: input addr = 0x%x ", mem_desc->virtual_address); + val_print(PGT_DEBUG_LEVEL, " val_pgt_create: output addr = 0x%x ", mem_desc->physical_address); + val_print(PGT_DEBUG_LEVEL, " val_pgt_create: length = 0x%x\n ", mem_desc->length); if ((mem_desc->virtual_address & (uint64_t)(page_size - 1)) != 0 || (mem_desc->physical_address & (uint64_t)(page_size - 1)) != 0) { @@ -250,11 +259,11 @@ uint64_t val_pgt_get_attributes(pgt_descriptor_t pgt_desc, uint64_t virtual_addr tt_base_virt = (uint64_t*)val_memory_phys_to_virt(tt_base_phys); val64 = tt_base_virt[index]; - val_print(PGT_DEBUG_LEVEL, "\nval_pgt_get_attr: this_level = %d ", this_level); - val_print(PGT_DEBUG_LEVEL, "\nval_pgt_get_attr: index = %d ", index); - val_print(PGT_DEBUG_LEVEL, "\nval_pgt_get_attr: bits_remaining = %d ", bits_remaining); - val_print(PGT_DEBUG_LEVEL, "\nval_pgt_get_attr: tt_base_virt %llx", (uint64_t)tt_base_virt); - val_print(PGT_DEBUG_LEVEL, "\nval_pgt_get_attr: val64 = %llx ", val64); + val_print(PGT_DEBUG_LEVEL, "\n val_pgt_get_attributes: this_level = %d ", this_level); + val_print(PGT_DEBUG_LEVEL, "\n val_pgt_get_attributes: index = %d ", index); + val_print(PGT_DEBUG_LEVEL, "\n val_pgt_get_attributes: bits_remaining = %d ", bits_remaining); + val_print(PGT_DEBUG_LEVEL, "\n val_pgt_get_attributes: tt_base_virt = %x ", (uint64_t)tt_base_virt); + val_print(PGT_DEBUG_LEVEL, "\n val_pgt_get_attributes: val64 = %x ", val64); if (this_level == 3) { if (!IS_PGT_ENTRY_PAGE(val64)) diff --git a/val/src/avs_smmu.c b/val/src/avs_smmu.c index d9c94362..b42a5940 100644 --- a/val/src/avs_smmu.c +++ b/val/src/avs_smmu.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -42,7 +42,6 @@ val_smmu_read_cfg(uint32_t offset, uint32_t index) return val_mmio_read(ctrl_base + offset); } -#ifndef TARGET_LINUX /** @brief This API executes all the SMMU tests sequentially @@ -57,7 +56,6 @@ val_smmu_execute_tests(uint32_t level, uint32_t num_pe) { uint32_t status = AVS_STATUS_PASS, i; uint32_t num_smmu; - uint32_t status_version_chk; for (i=0 ; i 3) - status |= i003_entry(num_pe); + status |= i002_entry(num_pe); if (g_sbsa_level > 4) { - status_version_chk = i007_entry(num_pe); - status |= status_version_chk; + status = i003_entry(num_pe); + status = i004_entry(num_pe); } if (g_sbsa_level > 5) { - if (status_version_chk != AVS_STATUS_PASS) { - val_print(AVS_PRINT_ERR, "\n SMMU Version Not Compliant, Skipping Remaining SMMU Tests...\n", 0); - } else { - -#ifndef ONLY_SBSA_RULE_TESTS - status |= i008_entry(num_pe); - status |= i009_entry(num_pe); - status |= i010_entry(num_pe); - status |= i011_entry(num_pe); - status |= i012_entry(num_pe); - status |= i015_entry(num_pe); - status |= i016_entry(num_pe); -#endif - status |= i013_entry(num_pe); - status |= i014_entry(num_pe); - -#ifdef ONLY_SBSA_RULE_TESTS - status |= hyp_i005_entry(num_pe); - status |= os_i005_entry(num_pe); - status |= os_i006_entry(num_pe); - status |= os_i007_entry(num_pe); - status |= os_i008_entry(num_pe); -#endif - } + status |= i005_entry(num_pe); + status |= i006_entry(num_pe); + status |= i007_entry(num_pe); + status |= i008_entry(num_pe); + status |= i009_entry(num_pe); + status |= i010_entry(num_pe); + status |= i011_entry(num_pe); + status |= i012_entry(num_pe); + status |= i015_entry(num_pe); } + if (g_sbsa_level > 6) { + status |= i013_entry(num_pe); + status |= i014_entry(num_pe); + } +#endif +#ifdef TARGET_LINUX + if (level > 6) + status |= i016_entry(num_pe); +#endif val_print_test_end(status, "SMMU"); return status; } -#endif uint32_t val_smmu_start_monitor_dev(uint32_t ctrl_index) diff --git a/val/src/avs_timer.c b/val/src/avs_timer.c index 38efcfea..fa0cf4aa 100644 --- a/val/src/avs_timer.c +++ b/val/src/avs_timer.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2019, 2021-2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -20,7 +20,7 @@ #include "include/sbsa_avs_timer_support.h" #include "include/sbsa_avs_timer.h" #include "include/sbsa_avs_common.h" - +#include "include/sbsa_avs_mmu.h" TIMER_INFO_TABLE *g_timer_info_table; @@ -35,7 +35,7 @@ TIMER_INFO_TABLE *g_timer_info_table; uint32_t val_timer_execute_tests(uint32_t level, uint32_t num_pe) { - uint32_t status, status_sys_timer, i; + uint32_t status = AVS_STATUS_SKIP, i; for (i=0 ; iheader.sys_timer_status = status_sys_timer; - - val_print_test_end(status, "Timer"); return status; } @@ -302,6 +278,10 @@ void val_timer_create_info_table(uint64_t *timer_info_table) { + uint64_t timer_num; + uint64_t gt_entry; + uint64_t timer_entry; + if (timer_info_table == NULL) { val_print(AVS_PRINT_ERR, "Input for Create Info table cannot be NULL \n", 0); return; @@ -316,8 +296,28 @@ val_timer_create_info_table(uint64_t *timer_info_table) val_timer_set_phy_el1(0); - val_print(AVS_PRINT_TEST, " TIMER_INFO: Number of system timers : %4d \n", g_timer_info_table->header.num_platform_timer); + val_print(AVS_PRINT_TEST, " TIMER_INFO: Number of system timers : %4d \n", + g_timer_info_table->header.num_platform_timer); + + timer_num = val_timer_get_info(TIMER_INFO_NUM_PLATFORM_TIMERS, 0); + + while (timer_num) { + --timer_num; + + if (val_timer_get_info(TIMER_INFO_IS_PLATFORM_TIMER_SECURE, timer_num)) + continue; //Skip Secure Timer + gt_entry = val_timer_get_info(TIMER_INFO_SYS_CNTL_BASE, timer_num); + timer_entry = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N, timer_num); + + val_print(AVS_PRINT_DEBUG, " Add entry %lx entry in memmap", gt_entry); + if (val_mmu_update_entry(gt_entry, 0x10000)) + val_print(AVS_PRINT_WARN, "\n Adding %lx entry failed", gt_entry); + + val_print(AVS_PRINT_DEBUG, "\n Add entry %lx entry in memmap", timer_entry); + if (val_mmu_update_entry(timer_entry, 0x10000)) + val_print(AVS_PRINT_WARN, "\n Adding %lx entry failed", timer_entry); + } } /** diff --git a/val/src/avs_timer_support.c b/val/src/avs_timer_support.c index 72c6f6fe..af253ee0 100644 --- a/val/src/avs_timer_support.c +++ b/val/src/avs_timer_support.c @@ -1,6 +1,6 @@ /** @file - * Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -71,7 +71,8 @@ ArmArchTimerReadReg ( case CnthCtl: case CnthpCval: - pal_print ("The register is related to Hypervisor Mode. Can't perform requested operation\n ", 0); + pal_print ("The register is related to Hypervisor Mode." + " Can't perform requested operation\n ", 0); break; default: @@ -88,7 +89,7 @@ ArmArchTimerWriteReg ( ) { - switch(Reg) { + switch (Reg) { case CntPct: pal_print("Can't write to Read Only Register: CNTPCT \n", 0); @@ -144,7 +145,8 @@ ArmArchTimerWriteReg ( break; case CnthCtl: case CnthpCval: - pal_print("The register is related to Hypervisor Mode. Can't perform requested operation\n ", 0); + pal_print("The register is related to Hypervisor Mode." + " Can't perform requested operation\n ", 0); break; default: diff --git a/val/src/avs_wakeup.c b/val/src/avs_wakeup.c index 5e5628e2..f6eeb1c6 100644 --- a/val/src/avs_wakeup.c +++ b/val/src/avs_wakeup.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2021-2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2021-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -35,7 +35,7 @@ extern int32_t gPsciConduit; uint32_t val_wakeup_execute_tests(uint32_t level, uint32_t num_pe) { - uint32_t status, i; + uint32_t status = AVS_STATUS_SKIP, i; for (i=0 ; i 5) - status |= w003_entry(num_pe); + status |= w001_entry(num_pe); val_print_test_end(status, "Watchdog"); From fb0bca8e0724687f99d8c939e199c71f4bb2ddaf Mon Sep 17 00:00:00 2001 From: Rajat Goyal Date: Thu, 12 Jan 2023 19:51:05 +0530 Subject: [PATCH 4/8] Linux Changes ACS 7.1 - Added MTE test for B_PE_16 - Added PMU tests - Added SMMU tests Signed-off-by: Rajat Goyal --- linux_app/mte/build_mte.sh | 39 + linux_app/mte/test_mte.c | 166 + linux_app/pmu_app/build_pmu.sh | 64 + linux_app/pmu_app/pmuval/sbsa_acs_pmu.py | 349 ++ linux_app/pmu_app/pmuval/sbsa_pmu_input.csv | 82 + linux_app/pmu_app/pyperf/Makefile | 12 + linux_app/pmu_app/pyperf/pyperf/README.md | 29 + linux_app/pmu_app/pyperf/pyperf/__init__.py | 0 linux_app/pmu_app/pyperf/pyperf/datamap.py | 216 ++ linux_app/pmu_app/pyperf/pyperf/elf.py | 424 +++ linux_app/pmu_app/pyperf/pyperf/hexdump.py | 96 + linux_app/pmu_app/pyperf/pyperf/imagemap.py | 713 ++++ linux_app/pmu_app/pyperf/pyperf/perf_abi.py | 739 ++++ linux_app/pmu_app/pyperf/pyperf/perf_attr.py | 454 +++ .../pmu_app/pyperf/pyperf/perf_aux_arm_spe.py | 118 + .../pmu_app/pyperf/pyperf/perf_aux_cs_etm.py | 311 ++ .../pmu_app/pyperf/pyperf/perf_buildid.py | 396 ++ linux_app/pmu_app/pyperf/pyperf/perf_data.py | 1576 ++++++++ linux_app/pmu_app/pyperf/pyperf/perf_enum.py | 368 ++ linux_app/pmu_app/pyperf/pyperf/perf_espec.py | 797 ++++ linux_app/pmu_app/pyperf/pyperf/perf_parse.py | 119 + linux_app/pmu_app/pyperf/pyperf/perf_sysfs.py | 251 ++ linux_app/pmu_app/pyperf/pyperf/perf_util.py | 282 ++ linux_app/pmu_app/pyperf/pyperf/perf_zstd.py | 151 + linux_app/pmu_app/pyperf/setup.py | 30 + linux_app/pmu_app/pyperf/src/NOTES.txt | 40 + linux_app/pmu_app/pyperf/src/pyperf_events.c | 3261 +++++++++++++++++ linux_app/pmu_app/pysweep/Makefile | 21 + linux_app/pmu_app/pysweep/setup.py | 38 + linux_app/pmu_app/pysweep/src/arch.h | 42 + .../pmu_app/pysweep/src/branch_prediction.c | 103 + .../pmu_app/pysweep/src/branch_prediction.h | 22 + linux_app/pmu_app/pysweep/src/denormals.c | 194 + linux_app/pmu_app/pysweep/src/denormals.h | 45 + linux_app/pmu_app/pysweep/src/genelf.c | 677 ++++ linux_app/pmu_app/pysweep/src/genelf.h | 71 + linux_app/pmu_app/pysweep/src/loadcode.c | 623 ++++ linux_app/pmu_app/pysweep/src/loaddata.c | 458 +++ linux_app/pmu_app/pysweep/src/loadgen.c | 644 ++++ linux_app/pmu_app/pysweep/src/loadgen.h | 258 ++ linux_app/pmu_app/pysweep/src/loadgenp.h | 56 + linux_app/pmu_app/pysweep/src/loadinst.c | 1117 ++++++ linux_app/pmu_app/pysweep/src/loadinst.h | 202 + linux_app/pmu_app/pysweep/src/prepcode.c | 160 + linux_app/pmu_app/pysweep/src/prepcode.h | 47 + linux_app/pmu_app/pysweep/src/pysweep.c | 1341 +++++++ linux_app/pmu_app/pysweep/src/sleep.c | 131 + linux_app/pmu_app/pysweep/src/sleep.h | 39 + .../pmu_app/pysweep/tests/code_template.c | 115 + linux_app/sbsa-acs-app/include/sbsa_app.h | 9 +- .../sbsa-acs-app/include/sbsa_drv_intf.h | 3 +- linux_app/sbsa-acs-app/sbsa_app_main.c | 17 +- linux_app/sbsa-acs-app/sbsa_app_smmu.c | 47 + platform/pal_uefi/include/pal_exerciser.h | 11 +- test_pool/Makefile | 14 +- val/Makefile | 4 +- 56 files changed, 17569 insertions(+), 23 deletions(-) create mode 100644 linux_app/mte/build_mte.sh create mode 100644 linux_app/mte/test_mte.c create mode 100755 linux_app/pmu_app/build_pmu.sh create mode 100644 linux_app/pmu_app/pmuval/sbsa_acs_pmu.py create mode 100644 linux_app/pmu_app/pmuval/sbsa_pmu_input.csv create mode 100644 linux_app/pmu_app/pyperf/Makefile create mode 100644 linux_app/pmu_app/pyperf/pyperf/README.md create mode 100644 linux_app/pmu_app/pyperf/pyperf/__init__.py create mode 100644 linux_app/pmu_app/pyperf/pyperf/datamap.py create mode 100644 linux_app/pmu_app/pyperf/pyperf/elf.py create mode 100644 linux_app/pmu_app/pyperf/pyperf/hexdump.py create mode 100644 linux_app/pmu_app/pyperf/pyperf/imagemap.py create mode 100644 linux_app/pmu_app/pyperf/pyperf/perf_abi.py create mode 100644 linux_app/pmu_app/pyperf/pyperf/perf_attr.py create mode 100644 linux_app/pmu_app/pyperf/pyperf/perf_aux_arm_spe.py create mode 100644 linux_app/pmu_app/pyperf/pyperf/perf_aux_cs_etm.py create mode 100644 linux_app/pmu_app/pyperf/pyperf/perf_buildid.py create mode 100644 linux_app/pmu_app/pyperf/pyperf/perf_data.py create mode 100644 linux_app/pmu_app/pyperf/pyperf/perf_enum.py create mode 100644 linux_app/pmu_app/pyperf/pyperf/perf_espec.py create mode 100644 linux_app/pmu_app/pyperf/pyperf/perf_parse.py create mode 100644 linux_app/pmu_app/pyperf/pyperf/perf_sysfs.py create mode 100644 linux_app/pmu_app/pyperf/pyperf/perf_util.py create mode 100644 linux_app/pmu_app/pyperf/pyperf/perf_zstd.py create mode 100644 linux_app/pmu_app/pyperf/setup.py create mode 100644 linux_app/pmu_app/pyperf/src/NOTES.txt create mode 100644 linux_app/pmu_app/pyperf/src/pyperf_events.c create mode 100644 linux_app/pmu_app/pysweep/Makefile create mode 100644 linux_app/pmu_app/pysweep/setup.py create mode 100644 linux_app/pmu_app/pysweep/src/arch.h create mode 100644 linux_app/pmu_app/pysweep/src/branch_prediction.c create mode 100644 linux_app/pmu_app/pysweep/src/branch_prediction.h create mode 100644 linux_app/pmu_app/pysweep/src/denormals.c create mode 100644 linux_app/pmu_app/pysweep/src/denormals.h create mode 100644 linux_app/pmu_app/pysweep/src/genelf.c create mode 100644 linux_app/pmu_app/pysweep/src/genelf.h create mode 100644 linux_app/pmu_app/pysweep/src/loadcode.c create mode 100644 linux_app/pmu_app/pysweep/src/loaddata.c create mode 100644 linux_app/pmu_app/pysweep/src/loadgen.c create mode 100644 linux_app/pmu_app/pysweep/src/loadgen.h create mode 100644 linux_app/pmu_app/pysweep/src/loadgenp.h create mode 100644 linux_app/pmu_app/pysweep/src/loadinst.c create mode 100644 linux_app/pmu_app/pysweep/src/loadinst.h create mode 100644 linux_app/pmu_app/pysweep/src/prepcode.c create mode 100644 linux_app/pmu_app/pysweep/src/prepcode.h create mode 100644 linux_app/pmu_app/pysweep/src/pysweep.c create mode 100644 linux_app/pmu_app/pysweep/src/sleep.c create mode 100644 linux_app/pmu_app/pysweep/src/sleep.h create mode 100644 linux_app/pmu_app/pysweep/tests/code_template.c create mode 100644 linux_app/sbsa-acs-app/sbsa_app_smmu.c diff --git a/linux_app/mte/build_mte.sh b/linux_app/mte/build_mte.sh new file mode 100644 index 00000000..dd8ca42c --- /dev/null +++ b/linux_app/mte/build_mte.sh @@ -0,0 +1,39 @@ + # #!/usr/bin/env bash + + # @file + # Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. + # SPDX-License-Identifier : Apache-2.0 + # + # Licensed under the Apache License, Version 2.0 (the "License"); + # you may not use this file except in compliance with the License. + # You may obtain a copy of the License at + # + # http://www.apache.org/licenses/LICENSE-2.0 + # + # Unless required by applicable law or agreed to in writing, software + # distributed under the License is distributed on an "AS IS" BASIS, + # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + # See the License for the specific language governing permissions and + # limitations under the License. + +arch=$(uname -m) +echo $arch +if [[ $arch = "aarch64" ]] +then + echo "aarch64 native build" + export CROSS_COMPILE='' +elif [ -v $CROSS_COMPILE ] +then + echo "CROSS_COMPILE is not set" + echo "set using export CROSS_COMPILE=/bin/aarch64-none-linux-gnu-" + return 0 +fi + +export CC=${CROSS_COMPILE}gcc +echo "Building Linux MTE test..." +echo "CC = $CC" + +$CC -o mte_test -O0 -march=armv8.5-a+memtag test_mte.c + +unset CC +unset CROSS_COMPILE diff --git a/linux_app/mte/test_mte.c b/linux_app/mte/test_mte.c new file mode 100644 index 00000000..1038e30b --- /dev/null +++ b/linux_app/mte/test_mte.c @@ -0,0 +1,166 @@ +/** @file + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TEST_RULE "B_PE_16" +#define TEST_DESC "Check for MTE support " + +#define HWCAP2_MTE (1 << 18) +#define PROT_MTE 0x20 +#define PR_SET_TAGGED_ADDR_CTRL 55 +#define PR_TAGGED_ADDR_ENABLE (1UL << 0) +#define PR_MTE_TCF_SHIFT 1 +#define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT) +#define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT) +#define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT) +#define PR_MTE_TCF_MASK (3UL << PR_MTE_TCF_SHIFT) +#define PR_MTE_TAG_SHIFT 3 +#define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT) +#define SIGSEGV_EXIT_CODE 139 +#define EXIT_SKIPPED 2 + +/* insert a random logical tag into the given pointer */ +#define insert_random_tag(ptr) ({ \ + uint64_t __val; \ + asm("irg %0, %1" : "=r" (__val) : "r" (ptr)); \ + __val; \ +}) + +/* set the allocation tag on the destination address */ +#define set_tag(tagged_addr) do { \ + asm volatile("stg %0, [%0]" : : "r" (tagged_addr) : "memory"); \ +} while (0) + + + +uint32_t payload(void) +{ + unsigned char *var; + unsigned long page_sz = sysconf(_SC_PAGESIZE); + unsigned long hwcap2 = getauxval(AT_HWCAP2); + uint32_t pid; + uint32_t childReturnCode; + uint64_t timeout = 100000; + + /* check if MTE is supported */ + if (!(hwcap2 & HWCAP2_MTE)) { + perror("\n Memory tagging extension(MTE) not supported."); + return EXIT_SKIPPED; + } + + /* enable the tagged address ABI, synchronous or asynchronous MTE tag check faults */ + if (prctl(PR_SET_TAGGED_ADDR_CTRL, + PR_TAGGED_ADDR_ENABLE | PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC | + (0xfffe << PR_MTE_TAG_SHIFT), + 0, 0, 0)) { + perror("\n prctl() failed"); + return EXIT_FAILURE; + } + + var = mmap(0, page_sz, PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + if (var == MAP_FAILED) { + perror("\n mmap() failed"); + return EXIT_FAILURE; + } + + /* Enable MTE on the above mmap.*/ + if (mprotect(var, page_sz, PROT_READ | PROT_WRITE | PROT_MTE)) { + perror("\n mprotect() failed"); + return EXIT_FAILURE; + } + + /* access with the default tag (0) */ + var[0] = 1; + var[1] = 10; + printf("\n Access with the default tag (0)"); + printf("\n var[0] = %hhu var[1] = %hhu", var[0], var[1]); + printf("\n Default tag(0) pointer : %p", var); + + /* set the logical and allocation tags */ + var = (unsigned char *)insert_random_tag(var); + set_tag(var); + + /* access with non-zero tag */ + var[0] = 3; + printf("\n Access with the non-zero tag"); + printf("\n var[0] = %hhu var[1] = %hhu", var[0], var[1]); + printf("\n Non zero tag pointer : %p", var); + + /* If MTE is enabled correctly the access to next 16 byte granule will cause an exception + due to mismatch in logical and allocation tags */ + + /* creating a child process and accessing var[16] or later to cause exception */ + /*delay for above printf*/ + while (timeout--); + pid = fork(); + + if (pid == 0) { + /* true for child process */ + printf("\n Expecting SIGSEGV exception..."); + var[18] = 0xdd; + + while (timeout--); + exit(0); + } + else if (pid < 0) { + /* fork failure */ + printf("\n Fork failed."); + return EXIT_FAILURE; + } + else { + /* parent process wait and check return status */ + waitpid(pid, &childReturnCode, 0); + printf("\n Child process returned with exit code: %d", childReturnCode); + + if (childReturnCode == SIGSEGV_EXIT_CODE) { + return EXIT_SUCCESS; + } + else { + printf("\n Not received SIGSEGV"); + return EXIT_FAILURE; + } + } + return EXIT_FAILURE; +} + +void main(void) +{ + uint32_t status; + /* test start */ + printf("\n%s: %s:", TEST_RULE, TEST_DESC); + /* call test payload */ + status = payload(); + /*check test return status*/ + if (status == EXIT_SUCCESS) + printf("\nResult: PASS\n"); + else if (status == EXIT_SKIPPED) + printf("\nResult: SKIP\n"); + else + printf("\nResult: FAIL\n"); + + return; +} \ No newline at end of file diff --git a/linux_app/pmu_app/build_pmu.sh b/linux_app/pmu_app/build_pmu.sh new file mode 100755 index 00000000..f5860297 --- /dev/null +++ b/linux_app/pmu_app/build_pmu.sh @@ -0,0 +1,64 @@ + # #!/usr/bin/env bash + + # @file + # Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + # SPDX-License-Identifier : Apache-2.0 + # + # Licensed under the Apache License, Version 2.0 (the "License"); + # you may not use this file except in compliance with the License. + # You may obtain a copy of the License at + # + # http://www.apache.org/licenses/LICENSE-2.0 + # + # Unless required by applicable law or agreed to in writing, software + # distributed under the License is distributed on an "AS IS" BASIS, + # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + # See the License for the specific language governing permissions and + # limitations under the License. + +arch=$(uname -m) +echo $arch +if [[ $arch = "aarch64" ]] +then + echo "aarch64 native build" + export CROSS_COMPILE='' +elif [ -v $CROSS_COMPILE ] +then + echo "CROSS_COMPILE is not set" + echo "set using export CROSS_COMPILE=/bin/aarch64-none-linux-gnu-" + return 0 +fi + +if [ -v $PYTHON ] +then + echo "PYTHON is not set" + echo "set using export PYTHON=/python" + return 0 +fi +export CC=${CROSS_COMPILE}gcc +#Info logs +echo $CC +echo $CROSS_COMPILE +echo $PYTHON + +if [ -v $CROSSBASE ] +then + export CROSSBASE=`pwd` +fi +export LDSHARED="${CC} -shared" + +pushd pyperf + make clean + make +popd + +pushd pysweep + make clean + make +popd + +unset CC +unset LDSHARED +unset PYTHON +unset CROSSBASE +unset CROSS_COMPILE diff --git a/linux_app/pmu_app/pmuval/sbsa_acs_pmu.py b/linux_app/pmu_app/pmuval/sbsa_acs_pmu.py new file mode 100644 index 00000000..aef8668e --- /dev/null +++ b/linux_app/pmu_app/pmuval/sbsa_acs_pmu.py @@ -0,0 +1,349 @@ +# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# SPDX-License-Identifier : Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" +Test SBSA PMU events +""" + +from __future__ import print_function + +import os, sys, subprocess, argparse + +import pysweep +from pyperf.perf_enum import * +from pyperf.perf_attr import * +import pyperf.perf_util as perf_util +import pyperf.perf_events as pp + +g_workload = None + + +def ecode(s): + # For an event specifier, return an integer code + return int(s,16) + + +parser = argparse.ArgumentParser(description="test relationships between PMU events") +parser.add_argument("-a", "--all-cpus", action="store_true", help="collect on all CPUs") +parser.add_argument("--sleep", type=float, default=0.1, help="time to wait") +parser.add_argument("--data", type=perf_util.str_memsize, help="use a data working set as the workload") +parser.add_argument("--data-dispersion", type=int, help="expansion factor for data working set") +parser.add_argument("--code", type=perf_util.str_memsize, help="use a code working set as the workload") +parser.add_argument("-e", "--event", type=ecode, action="append", default=[], help="also count this event") +parser.add_argument("-r", "--repeat", type=int, default=1, help="repeat test N times") +parser.add_argument("-v", "--verbose", action="count", default=0, help="increase verbosity level") +parser.add_argument("--scaling", type=int, default=0, help="Enable scaling factor") +parser.add_argument("command", nargs=argparse.REMAINDER, help="command to execute") + +opts = parser.parse_args([]) + +total = [0, 0, 0] + +class BadEvent(Exception): + pass + + +def echeck(s): + """ + Filter event codes affected by cores that don't check bit 15 in the event selector. + (Architecture loophole, not technically a silicon errata.) + """ + n = ecode(s) + + return n + + +class EventProperty: + def __init__(self): + pass + + def contains_any(self, el): + for e in el: + if self.contains(e): + return True + return False + + +class Relation(EventProperty): + def __init__(self): + self.n_tests = 0 + self.n_fails = 0 + self.sup = None # The event code. + self.reason = None # Event description + self.rule = None # SBSA rule ID assosiated with event + + def contains(self, e): + return e == self.sup + + def accepts(self, vsub): + if opts.scaling: + if vsub[0] == 0 or vsub[1] == 0 or vsub[2] == 0: + return 0 # if counter is not moved , test failed + if vsub[0] > vsub[1] or vsub[1] > vsub[2]: + return 0 #Faile if counter not moved as per scaling factor + else: + if vsub[0] <= 0: + return 0 + return 1 + + def __str__(self): + return "%s: %x: %s" % (self.rule, self.sup, self.reason) + +def read_csv(fn): + f = open(fn) + for ln in f: + if ln.startswith("#") or not ln.strip(): + continue + yield ln.strip() + f.close() + +def read_relations(): + """ + Read the relationships from a text file, yielding Relation objects. + """ + for ln in read_csv("sbsa_pmu_input.csv"): + (rule,sup, reason) = ln.split(',', 2) + r = Relation() + r.reason = reason + r.rule = rule + try: + r.sup = echeck(sup) + except BadEvent: + continue + yield r + +def open_event(en, group=None, enabled=True): + """ + Open a hardware PMU event to monitor the workload. + + This may fail with an assertion because: + - we don't have privilege + - we're on an inappropriate target that doesn't support this hardware event code + - we are opening as a group member, and haven't got enough physical counters + """ + if opts.all_cpus: + pid = -1 + cpu = 0 + else: + pid = g_workload.pid + cpu = -1 + # Tool verbosity=1: no event messages; tool verbosity=2 (-vv), minimal event messages + event_verbose = max(0, (opts.verbose - 1)) + rf = PERF_FORMAT_TOTAL_TIME_RUNNING|PERF_FORMAT_TOTAL_TIME_ENABLED + attr = PerfEventAttr(type=PERF_TYPE_RAW, config=en, read_format=rf, exclude_kernel=False, inherit=True) + flags = pp.PERF_FLAG_WEAK_GROUP + e = None + try: + if event_verbose: + print("open_event: %s" % attr) + if group is not None: + print(" in group: %s" % group) + e = pp.Event(attr, pid=pid, cpu=cpu, enabled=enabled, group=group, verbose=event_verbose, flags=flags) + except OSError: + print("** could not open hardware performance event - retrying as userspace only", file=sys.stderr) + attr.update(exclude_kernel=True) + if e is None: + e = pp.Event(attr, pid=pid, cpu=cpu, enabled=enabled, group=group, verbose=event_verbose, flags=flags) + assert e is not None + return e + + +class Monitor: + """ + Set up the events to monitor a relationship. + """ + def __init__(self, r, x): + self.r = r + self.x = x + self.supe = open_event(r.sup, enabled=False) + + def enable(self): + self.supe.enable() # Enable the group + return self + + def read(self): + return Witness(self) + + def disable(self): + self.supe.disable() # Disable the group + return self + + def close(self): + self.supe.close() + return self + +def read_events_values(el): + """ + Read a set of values from a list of events. The first event may be a + group event, and some or all of the remaining events may be members of its group. + These may be followed by non-group events. + """ + e = el[0] + if PerfEventAttr(e.attr_struct()).read_format & PERF_FORMAT_GROUP: + g = e.read() # a GroupReading object + values = [r.value for r in g] + else: + values = [] + ix = len(values) + values += [e.read().value for e in el[ix:]] + return values + +class Witness: + """ + Take a reading from a monitor, to get a set of event values to check against the relationship. + """ + def __init__(self, m): + self.m = m + self.read() + def read(self): + vs = read_events_values([self.m.supe]) + self.sup_value = vs[0] + total[self.m.x] = self.sup_value + self.ok = self.accepts() + return self + + def accepts(self): + if opts.scaling: + if x == 2: + return self.m.r.accepts(total) + else : + return 1 + else: + return self.m.r.accepts(total) + +class Workload: + def __init__(self): + self.pid = None + + def prepare(self): + if opts.data or opts.code: + load_opts = {"data": opts.data, "data_dispersion": opts.data_dispersion, "inst": opts.code, "flags": pysweep.MEM_NO_HUGEPAGE} + self.load = pysweep.Load(load_opts, verbose=max(0, opts.verbose-1)) + self.load.start() + self.pid = self.load.tids()[0] + if opts.verbose: + print("reltest: suspend") + self.load.suspend() + else: + self.pid = os.getpid() + + def run(self): + if opts.verbose: + print("reltest: run") + if command: + # Run a subcommand and wait until it terminates + p = subprocess.Popen(command.split(), stdout=subprocess.PIPE, stderr=subprocess.PIPE) + (out, err) = p.communicate() + if p.returncode != 0: + print(err, file=sys.stderr) + sys.exit(p.returncode) + if opts.verbose: + print(out, end="") + elif opts.data or opts.code: + # Run a synthetic workload, for the --sleep duration + self.load.resume() + pysweep.sleep(opts.sleep) + self.load.suspend() + else: + # Just sleep for the --sleep duration, e.g. to pick up background system activity + pysweep.sleep(opts.sleep) + +def test_relation(r,x): + """ + Test a relationship between events. Because each relationship involves a specific + set of events and these all need to be counted at the same time, we run a separate + test for each relationship, with just those events configured. + """ + + if opts.scaling: + opts.data = (x + 1) * 100 + opts.code = (x + 1) * 100 + + g_workload.prepare() + m = Monitor(r, x) + m.enable() + g_workload.run() # Dynamic code & data gen + if opts.scaling: + pysweep.br_pred(opts.data) + else: + pysweep.br_pred(1); + m.disable() + w = m.read() + m.close() + + if opts.scaling: + if x == 2: # Update test count on third itration + r.n_tests += 1 + if not w.ok: + r.n_fails += 1 + show_witness(w) + else: + r.n_tests += 1 + if not w.ok: + r.n_fails += 1 + show_witness(w) + + return w.ok + +def show_witness(w): + # Print more detail about how these values contradict the relationship. + # (Or perhaps not - when verbose, we also show this for all tests.) + r = w.m.r + if opts.scaling: + print(" Rule : %s, event : %04x, count[%08u,%08u,%08u]" % (r.rule, r.sup, total[0], total[1], total[2]), end="") + else : + print(" Rule : %s, event : %04x, count[%08u]" % (r.rule, r.sup, total[0]), end="") + + string_revised=r.reason.ljust(30) + print(" %s" % (string_revised), end="") + + if not w.ok: + print(" :FAIL") + else: + print(" :PASS") + +if __name__ == "__main__": + opts = parser.parse_args() + if opts.command: + command = ' '.join(opts.command) + else: + command = None + g_workload = Workload() + rels = list(read_relations()) + + total_tests = 0 + total_fails = 0 + + print("") + print("***** Starting PMU event test *****") + print("") + + for i in range(opts.repeat): + for r in rels: + total[0] = 0 + total[1] = 0 + total[2] = 0 + if opts.scaling: + for x in range(0, 3): + test_relation(r, x) + else: + test_relation(r, 0) + + total_tests += r.n_tests + total_fails += r.n_fails + + print("----------------------------------------------------------") + print(" Total tets: %d , Total Passed: %d, Total Failed: %d" % (total_tests, (total_tests - total_fails), total_fails)) + print("----------------------------------------------------------") diff --git a/linux_app/pmu_app/pmuval/sbsa_pmu_input.csv b/linux_app/pmu_app/pmuval/sbsa_pmu_input.csv new file mode 100644 index 00000000..18cae6c0 --- /dev/null +++ b/linux_app/pmu_app/pmuval/sbsa_pmu_input.csv @@ -0,0 +1,82 @@ +# Entries are in format +# RULE_ID,EVENT_ID,EVENT_DESCRIPTION + +# IPC Events +PMU_EV_01,08,INST_RETIRED +PMU_EV_01,11,CPU_CYCLES + +# Cache Events +PMU_EV_02,04,L1D_CACHE +PMU_EV_02,13,MEM_ACCESS +PMU_EV_02,14,L1I_CACHE +PMU_EV_02,16,L2D_CACHE +PMU_EV_02,27,L2I_CACHE +PMU_EV_02,2B,L3D_CACHE +PMU_EV_02,36,LL_CACHE_RD +PMU_EV_02,0037,LL_CACHE_MISS_RD +PMU_EV_02,39,L1D_CACHE_LMISS_RD +PMU_EV_02,40,L1D_CACHE_RD +PMU_EV_02,50,L2D_CACHE_RD +PMU_EV_02,66,MEM_ACCESS_RD +PMU_EV_02,A0,L3D_CACHE_RD +PMU_EV_02,4006,L1I_CACHE_LMISS +PMU_EV_02,4009,L2D_CACHE_LMISS_RD +PMU_EV_02,400A,L2I_CACHE_LMISS +PMU_EV_02,400B,L3D_CACHE_LMISS_RD + +# TLB Events +PMU_EV_03,25,L1D_TLB +PMU_EV_03,26,L1I_TLB +PMU_EV_03,34,DTLB_WALK +PMU_EV_03,35,ITLB_WALK + +# Cycle accounting events +PMU_EV_05,11,CPU_CYCLES +PMU_EV_05,23,STALL_FRONTEND +PMU_EV_05,24,STALL_BACKEND +PMU_EV_05,3C,STALL +PMU_EV_05,4005,STALL_BACKEND_MEM + +# Top-down accounting events +PMU_EV_06,11,CPU_CYCLES +PMU_EV_06,3A,OP_RETIRED +PMU_EV_06,3B,OP_SPEC +PMU_EV_06,3D,STALL_SLOT_BACKEND +PMU_EV_06,3E,STALL_SLOT_FRONTEND +PMU_EV_06,3F,STALL_SLOT + +# Workload Events +PMU_EV_07,80C1,FP_FIXED_OPS_SPEC +PMU_EV_07,80C9,INT_FIXED_OPS_SPEC + +#Branching Events +PMU_EV_08,000C,PC_WRITE_RETIRED +PMU_EV_08,000D,BR_IMMED_RETIRED +PMU_EV_08,000E,BR_RETURN_RETIRED +PMU_EV_08,0021,BR_RETIRED +PMU_EV_08,0022,BR_MIS_PRED_RETIRED +PMU_EV_08,8110,BR_IMMED_PRED_RETIRED +PMU_EV_08,8111,BR_IMMED_MIS_PRED_RETIRED +PMU_EV_08,8112,BR_IND_PRED_RETIRED +PMU_EV_08,8113,BR_IND_MIS_PRED_RETIRED +PMU_EV_08,8114,BR_RETURN_PRED_RETIRED +PMU_EV_08,8115,BR_RETURN_MIS_PRED_RETIRED +PMU_EV_08,8116,BR_INDNR_PRED_RETIRED +PMU_EV_08,8117,BR_INDNR_MIS_PRED_RETIRED +PMU_EV_08,8118,BR_TAKEN_PRED_RETIRED +PMU_EV_08,8119,BR_TAKEN_MIS_PRED_RETIRED +PMU_EV_08,811A,BR_SKIP_PRED_RETIRED +PMU_EV_08,811B,BR_SKIP_MIS_PRED_RETIRED +PMU_EV_08,811C,BR_PRED_RETIRED +PMU_EV_08,811D,BR_IND_RETIRED +PMU_EV_08,811E,BR_INDNR_RETIRED + +#Latency Events +PMU_EV_10,13,MEM_ACCESS +PMU_EV_10,19,BUS_ACCESS +PMU_EV_10,34,DTLB_WALK +PMU_EV_10,35,ITLB_WALK +PMU_EV_10,60,BUS_ACCESS_RD +PMU_EV_10,61,BUS_ACCESS_WR +PMU_EV_10,66,MEM_ACCESS_RD +PMU_EV_10,67,MEM_ACCESS_WR diff --git a/linux_app/pmu_app/pyperf/Makefile b/linux_app/pmu_app/pyperf/Makefile new file mode 100644 index 00000000..940d2685 --- /dev/null +++ b/linux_app/pmu_app/pyperf/Makefile @@ -0,0 +1,12 @@ + +default: install + +install: + $(PYTHON) setup.py install --prefix=$(CROSSBASE) + +sysinstall: + sudo $(PYTHON) setup.py install + +.PHONY: clean +clean: + rm -rf build diff --git a/linux_app/pmu_app/pyperf/pyperf/README.md b/linux_app/pmu_app/pyperf/pyperf/README.md new file mode 100644 index 00000000..0cb1a11a --- /dev/null +++ b/linux_app/pmu_app/pyperf/pyperf/README.md @@ -0,0 +1,29 @@ +How this module is structured +----------------------------- + +These modules wrap the system call and mmap buffer, and provide direct access to PMU events. + + - pyperf_events.c - wraps the perf_event_open syscall and mmap buffers + - perf_enum.py - perf-related enumerations + - perf_attr.py - the perf_event_attr structure + - perf_abi.py - decode records returned in the mmap buffer + +These modules provide access to the list of events exported from the kernel via sysfs, +and parse event specifiers as used by the userspace perf tools: + + - perf_util.py - parse and print various types (memory sizes, CPU lists etc.) + - perf_sysfs.py - read event data from sysfs + - perf_parse.py - helper functions for perf_espec.py + - perf_espec.py - parse an invidual event specifier + +These modules replicate some of the functionality of the userspace perf tools: + + - perf_data.py - read perf.data files as created by the 'perf record' tool + - perf_zstd.py - wrap libzstd (if installed) to decompress perf.data files + - datamap.py - helper functions for perf_data.py (self-checking) + - perf_buildid.py - manage the buildid cache. Also, can be used as a command-line tool similar to 'perf buildid' + - elf.py - minimal ELF reader to get buildid + +-------------- + +*Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.* diff --git a/linux_app/pmu_app/pyperf/pyperf/__init__.py b/linux_app/pmu_app/pyperf/pyperf/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/linux_app/pmu_app/pyperf/pyperf/datamap.py b/linux_app/pmu_app/pyperf/pyperf/datamap.py new file mode 100644 index 00000000..21d1b231 --- /dev/null +++ b/linux_app/pmu_app/pyperf/pyperf/datamap.py @@ -0,0 +1,216 @@ +# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# SPDX-License-Identifier : Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" +Build a hierarchical map of sections of a file or other memory space. +Useful when dealing with complicated file formats like perf.data. +""" + +from __future__ import print_function + +import sys + +class DataRange: + def __init__(self, map, base, size, name, parent=None): + self.name = name + self.map = map + self.base = base + self.size = size + self.parent = parent + self.subranges = [] # Ordered by base address + + def limit(self): + return self.base + self.size + + def contains(self, addr, size=1): + return (self.base is None or self.base <= addr) and (self.size is None or (addr+size) <= self.limit()) + + def contains_range(self, range): + return self.contains(range.base, range.size) + + def descent(self): + if self.parent is None: + return [] + return [self] + self.parent.descent() + + def add_range(self, range): + assert self.contains_range(range), "%s should contain %s" % (self, range) + down = [] + for r in self.subranges: + if r.contains_range(range): + # New range is completely inside one of our subranges + assert not down + r.add_range(range) + return + if range.contains_range(r): + # New range contains one of our subranges... and possibly others + r.parent = range + range.add_range(r) + down.append(r) + for r in down: + self.subranges.remove(r) + range.parent = self + ix = 0 + # Add the new range as one of our subranges, ordered by address + for r in self.subranges: + if range.limit() <= r.base: + break + ix = ix + 1 + self.subranges.insert(ix, range) + + def iter_subranges(self, depth=0): + for r in self.subranges: + yield (depth, r) + for rr in r.iter_subranges(depth+1): + yield rr + + def iter_unmapped(self): + start = self.base + for r in self.subranges: + if start < r.base: + yield DataRange(self.map, start, r.base-start, "**unmapped**", parent=self) + start = r.limit() + if start < self.limit(): + yield DataRange(self.map, start, self.limit()-start, "**unmappped**", parent=self) + + def find_subrange(self, n): + # Find immediate subrange containing n, or None + for r in self.subranges: + if r.contains(n): + return r + return None + + def find(self, n): + assert self.is_top() or self.contains(n), "%s should be top or contain %s" % (self, n) + r = self.find_subrange(n) + if r is not None: + return r.find(n) + return self + + def is_top(self): + return self.base is None + + def check(self): + last_range = None + for r in self.subranges: + assert self.contains_range(r), "%s doesn't contain subrange %s" % (self, r) + if last_range is not None: + assert last_range.base <= r.base, "%s contains out-of-sequence subranges %s and %s" % (self, last_range, r) + assert r.base >= last_range.limit(), "%s contains consecutive overlapping ranges %s and %s" % (self, last_range, r) + r.check() + last_range = r + + def __str__(self): + if self.is_top(): + return "TOP" + return "%-10s %-10s %s" % (self.base, self.limit(), self.name) + + def __repr__(self): + return self.name + + def dump(self): + print() + print("Range: %s:" % self, end="") + if self.subranges: + print() + print(" subranges:") + for r in self.subranges: + print(" ", r) + print("----") + for r in self.subranges: + r.dump() + else: + print(" no subranges") + + +class DataMap: + def __init__(self): + self.toprange = DataRange(self, None, None, "TOP") + self.log = [self.toprange] + + def add(self, base, size, name=""): + dr = DataRange(self, base, size, name) + self.log.append(dr) + if size: + self.toprange.add_range(dr) + self.check() + else: + dr = None + return dr + + def find(self, n): + # Find the most specific subrange + return self.toprange.find(n) + + def contains(self, n): + return self.toprange.find_subrange(n) is not None + + def iter_subranges(self): + for r in self.toprange.iter_subranges(): + yield r + + def check(self): + try: + self.toprange.check() + except AssertionError as e: + print("Data map consistency check failed: %s" % e, file=sys.stderr) + self.toprange.dump() + print() + print("Log:") + for dr in self.log: + print(dr) + raise + + def show(self, fmt="%-10s"): + print_datamap(self, fmt=fmt) + + +def print_datamap(d, fmt="%-10s"): + fmt = "%s" + fmt + " " + fmt + " %s" + last_at_level = {} + for (level, r) in d.iter_subranges(): + if level in last_at_level and last_at_level[level].limit() < r.base: + print(fmt % (" "*level, last_at_level[level].limit(), r.base, "**unmapped**")) + print(fmt % (" "*level, r.base, r.limit(), r.name)) + last_at_level[level] = r + d.check() + + +def test(): + d = DataMap() + d.add(15,8,"A") + d.add(17,2,"B") + d.add(1,8,"C") + d.add(12,20,"D") + d.add(1,3,"E") + d.add(2,1,"F") + d.add(4,2,"G") + print_datamap(d) + for i in range(0,20): + r = d.find(i) + print("%3s %s" % (i, r.descent())) + d = DataMap() + d.add(0,37132,"file") + d.add(0,104,"header") + d.add(120,256,"data") + d.add(104,8,"desc 0") + d.add(112,8,"desc 1") + + +if __name__ == "__main__": + import argparse + parser = argparse.ArgumentParser(description="map an address space") + opts = parser.parse_args() + test() diff --git a/linux_app/pmu_app/pyperf/pyperf/elf.py b/linux_app/pmu_app/pyperf/pyperf/elf.py new file mode 100644 index 00000000..a86223cd --- /dev/null +++ b/linux_app/pmu_app/pyperf/pyperf/elf.py @@ -0,0 +1,424 @@ +# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# SPDX-License-Identifier : Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" +Map an ELF file (including /proc/kcore) +""" + +from __future__ import print_function + +import os, sys, struct, errno + +# Image type +ET_NONE = 0 +ET_REL = 1 +ET_EXEC = 2 +ET_DYN = 3 +ET_CORE = 4 + +# Machine type +EM_386 = 3 +EM_ARM = 40 +EM_X86_64 = 62 +EM_AARCH64 = 183 + +PT_NULL = 0 +PT_LOAD = 1 +PT_DYNAMIC = 2 +PT_INTERP = 3 +PT_NOTE = 4 +PT_SHLIB = 5 +PT_PHDR = 6 +PT_TLS = 7 +PT_GNU_EH_FRAME = 0x6474e550 +PT_GNU_STACK = 0x6474e551 +PT_GNU_RELRO = 0x6474e552 +PT_PAX_FLAGS = 0x65041580 + +PT_ARM_EXIDX = 0x70000001 + +PF_X = 1 +PF_W = 2 +PF_R = 4 + +SHT_NULL = 0 +SHT_PROGBITS = 1 +SHT_SYMTAB = 2 +SHT_STRTAB = 3 +SHT_RELA = 4 +SHT_HASH = 5 +SHT_DYNAMIC = 6 +SHT_NOTE = 7 +SHT_NOBITS = 8 +SHT_REL = 9 +SHT_DYNSYM = 11 +SHT_INIT_ARRAY = 14 +SHT_FINI_ARRAY = 15 +SHT_PREINIT_ARRAY = 16 +SHT_GROUP = 17 +SHT_GNU_ATTRIBUTES = 0x6ffffff5 +SHT_GNU_HASH = 0x6ffffff6 +SHT_GNU_verdef = 0x6ffffffd +SHT_GNU_verneed = 0x6ffffffe +SHT_GNU_versym = 0x6fffffff + +SHT_ARM_EXIDX = 0x70000001 +SHT_ARM_PREEMPTMAP = 0x70000002 +SHT_ARM_ATTRIBUTES = 0x70000003 + +SHF_WRITE = 0x0001 +SHF_ALLOC = 0x0002 +SHF_EXECINSTR = 0x0004 + +SHN_UNDEX = 0 +SHN_ABS = 0xfff1 +SHN_COMMON = 0xfff2 + +# "CORE" note types +NT_PRSTATUS = 1 +NT_PRFPREG = 2 +NT_PRPSINFO = 3 +NT_TASKSTRUCT = 4 +NT_AUXV = 6 + +# "GNU" note types +NT_GNU_ABI_TAG = 1 +NT_GNU_HWCAP = 2 +NT_GNU_BUILD_ID = 3 +NT_GNU_GOLD_VERSION = 4 +NT_GNU_PROPERTY_TYPE_0 = 5 + + +pt_name = {} +sht_name = {} +for x in list(globals()): + if x.startswith("PT_"): + pt_name[globals()[x]] = x[3:] + if x.startswith("SHT_"): + sht_name[globals()[x]] = x[4:] + + +class NotELF(Exception): + pass + + +class Segment: + """ + A program segment (may contain multiple sections). + """ + def __init__(self, file): + self.file = file + self._data = None + + def data(self): + if self._data is None: + self._data = self.file.readat(self.offset, self.filesz) + return self._data + + def size(self): + # Size of segment in memory - including zero padding + return self.memsz + + def vaddr_end(self): + # End address of the segment (not included in the segment). We hope this is representable. + return self.vaddr + self.memsz + + def vaddr_last(self): + # Last valid address in the segment + if self.memsz == 0: + return None + else: + return self.vaddr + (self.memsz - 1) + + def is_padded(self): + assert self.memsz == 0 or self.memsz >= self.filesz + return self.memsz > self.filesz + + def contains_vaddr(self, va, size=1): + return self.vaddr <= va and (va+size) <= self.vaddr_end() + + def is_executable(self): + return (self.flags & PF_X) != 0 + + def __str__(self): + s = "%s[%u]: %s 0x%x-0x%x" % (self.file, self.index, pt_name[self.type], self.vaddr, self.vaddr_end()) + return s + + +class Section: + def __init__(self, file): + self.file = file + self._data = None + + def data(self): + if self._data is None: + self._data = self.file.readat(self.soff, self.ssize) + return self._data + + def __str__(self): + s = "#%u" % (self.index) + + +class Note: + def __init__(self, group, ntype, desc): + self.group = group + self.ntype = ntype + self.desc = bytes(desc) + + def __str__(self): + s = "Note(\"%s\",type=0x%x,data=%u)" % (self.group, self.ntype, len(self.desc)) + return s + + + +def is_mapping_symbol_False(s): + return False + +def symbol_real_address_default(addr): + return addr + + +def is_mapping_symbol_ARM(s): + if s[0] == "$" and len(s) >= 2: + return s[0:2] in ["$a", "$t", "$d", "$x"] and (len(s) == 2 or s[2] == '.') + else: + return False + +def symbol_real_address_ARM(addr): + return addr & ~1 + + +class ELF: + """ + Encapsulate an ELF file for reading. + The constructor attempts to check it's an ELF file and read headers etc. + If that fails, it will throw a NotELF or IOError exception. + """ + def __init__(self, fn): + """ + Construct an ELF object reader, by file name. + """ + self.fn = fn + self.fd = None + self.elf_type = None + self.machine = None + self.is_mapping_symbol = is_mapping_symbol_False + self.symbol_real_address = symbol_real_address_default + self.read_headers() + + def read_headers(self): + try: + self.fd = open(self.fn, "rb") + except IOError as e: + if False and e.errno == errno.EACCES: + print("%s: no permission to read - try as root" % self.fn, file=sys.stderr) + return + raise + s = self.fd.read(80) + if not s.startswith(b"\x7fELF"): + #print("%s: not an ELF file" % self.fn, file=sys.stderr) + #return + raise NotELF() + self.elf_type = self.read16(16) # EXE, OBJ etc. + self.machine = self.read16(18) # EM_ARM etc. + if self.machine == EM_ARM: + self.symbol_real_address = symbol_real_address_ARM + if self.machine in [EM_ARM, EM_AARCH64]: + self.is_mapping_symbol = is_mapping_symbol_ARM + self.sf = (self.read8(4) == 2) # 64-bit ELF + if not self.sf: + self.entry = self.read32(24) + self.phoff = self.read32(28) + self.phsize = self.read16(42) + self.phnum = self.read16(44) + self.shoff = self.read32(32) + self.shsize = self.read16(46) + self.shnum = self.read16(48) + else: + self.entry = self.read64(24) + self.phoff = self.read64(32) + self.phsize = self.read16(54) + self.phnum = self.read16(56) + self.shoff = self.read64(40) + self.shsize = self.read16(58) + self.shnum = self.read16(60) + + def __str__(self): + s = self.fn + return s + + def __del__(self): + if self.fd is not None: + self.fd.close() + + def readat(self, off, n): + self.fd.seek(off) + try: + s = self.fd.read(n) + except IOError: + print("%s: failed to read 0x%x bytes" % (self.fn, n), file=sys.stderr) + s = None + except MemoryError: + print("%s: failed to read 0x%x bytes - out of memory" % (self.fn, n), file=sys.stderr) + s = None + return s + + def readnum(self, fmt, n, off, s=None): + # TBD: handle endianness conversion + if s is None: + s = self.readat(off, n) + else: + s = s[off:off+n] + return struct.unpack(fmt, s)[0] + + def read64(self, off, s=None): + return self.readnum("Q", 8, off, s) + + def read32(self, off, s=None): + return self.readnum("I", 4, off, s) + + def read16(self, off, s=None): + return self.readnum("H", 2, off, s) + + def read8(self, off, s=None): + return self.readnum("B", 1, off, s) + + def segments(self, type=None): + """ + Iterate through segments, possibly of a given type. + """ + for i in range(0, self.phnum): + pho = self.phoff + i*self.phsize + ph = self.readat(pho, self.phsize) + stype = self.read32(0, ph) + if type is not None and stype != type: + continue + s = Segment(self) + s.index = i + s.type = stype + if not self.sf: + s.flags = self.read32(24, ph) + s.filesz = self.read32(16, ph) + s.memsz = self.read32(20, ph) + s.offset = self.read32(4, ph) + s.vaddr = self.read32(8, ph) + else: + s.flags = self.read32(4, ph) + s.filesz = self.read64(32, ph) + s.memsz = self.read64(40, ph) + s.offset = self.read64(8, ph) + s.vaddr = self.read64(16, ph) + yield s + + def notes(self, group=None): + for ns in self.segments(type=PT_NOTE): + d = ns.data() + while d: + if self.read32(0, d) == 0: + d = d[4:] # unclear why we see this + if True or not self.sf: + # ELF spec says 64-bit ELF has 64-bit fields, but in practice, it's 32-bit + namesz = self.read32(0, d) + descsz = self.read32(4, d) + ntype = self.read32(8, d) + d = d[12:] + else: + assert False + assert namesz <= 32, "unexpected namesz in note: 0x%x" % namesz + name = d[0:namesz] + while name[-1:] == b'\00': + name = name[:-1] + d = d[((namesz+3)&~3):] + desc = d[:descsz] + d = d[((descsz+3)&~3):] + if group is None or name == group: + yield Note(name, ntype, desc) + + def build_id(self): + for n in self.notes(group=b"GNU"): + if n.ntype == NT_GNU_BUILD_ID: + return n.desc + return None + + def sections(self): + for i in range(0, self.shnum): + sho = self.shoff + i*self.shsize + sh = self.readat(sho, self.shsize) + s = Section(self) + s.index = i + s.type = self.read32(4, sh) + if not self.sf: + s.flags = self.read32(8, sh) + s.saddr = self.read32(12, sh) + s.soff = self.read32(16, sh) + s.ssize = self.read32(20, sh) + s.salign = self.read32(32, sh) + else: + s.flags = self.read64(8, sh) + s.saddr = self.read64(16, sh) + s.soff = self.read64(24, sh) + s.ssize = self.read64(32, sh) + s.salign = self.read64(48, sh) + yield s + + +if __name__ == "__main__": + import argparse + import hexdump + parser = argparse.ArgumentParser(description="ELF file inspector") + parser.add_argument("--binutils", action="store_true", help="emulate binutils output") + parser.add_argument("--verbose", "-v", action="count", help="increase verbosity") + parser.add_argument("files", type=str, nargs="+", help="ELF files") + opts = parser.parse_args() + for fn in opts.files: + try: + e = ELF(fn) + except NotELF: + print("%s: not ELF" % (fn)) + continue + if e.elf_type is None: + continue + print("%s: elf%s" % (fn, int(e.sf)*32+32)) + if True: + print("Segments:") + for s in e.segments(): + if opts.binutils: + print(" %-12s 0x%016x 0x%016x" % (pt_name[s.type], s.offset, s.vaddr)) + print(" 0x%016x %04x" % (s.filesz, s.flags)) + else: + print(" %3u" % (s.index), end="") + if s.vaddr_last() is not None: + print(" %x-%x" % (s.vaddr, s.vaddr_last()), end="") + else: + print(" vaddr=%x" % (s.vaddr), end="") + print(" %04x %-12s %16x @%x" % (s.flags, pt_name[s.type], s.filesz, s.offset), end="") + if s.is_padded(): + print("*", end="") + print() + print("Sections:") + for s in e.sections(): + print(" %3u %-12s 0x%016x 0x%04x" % (s.index, sht_name[s.type], s.saddr, s.flags)) + print("Notes:") + for n in e.notes(): + print(" %s" % n) + if opts.verbose: + hexdump.print_hex_dump(n.desc, prefix=" ") + bid = e.build_id() + if bid is not None: + print("Build ID: ", end="") + for c in bytearray(bid): + print("%02x" % c, end="") + print() + diff --git a/linux_app/pmu_app/pyperf/pyperf/hexdump.py b/linux_app/pmu_app/pyperf/pyperf/hexdump.py new file mode 100644 index 00000000..cc0cee22 --- /dev/null +++ b/linux_app/pmu_app/pyperf/pyperf/hexdump.py @@ -0,0 +1,96 @@ +# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# SPDX-License-Identifier : Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" +Show raw data in traditional hex dump format. +""" + +from __future__ import print_function + +import sys + + +def is_printable(c, upper7=False): + if 32 <= c and c <= 0x7e: + return True + if upper7 and c >= 0xa0 and c <= 0xff: + return True + return False + + +def as_bytes(s): + # We want to access the characters of the string as bytes, + # consistently between Python2 and Python3. + if isinstance(s, str): + s = bytearray(s) + return s + + +def print_hex_dump(d, base=0, prefix="", width=16, file=None, upper7=False): + """ + Show raw data from a byte array, in traditional hex dump format. + """ + f = file + if f is None: + f = sys.stdout + d = as_bytes(d) + size = len(d) + nl = int((size+width-1) / width) + tp = size + for i in range(0, nl): + ip = i * width + print("%s%04x: " % (prefix, base+ip), end="", file=f) + nb = min(tp, width) + for j in range(0, nb): + print(" %02x" % d[ip+j], end="", file=f) + for j in range(nb, width): + print(" ", end="", file=f) + print(" ", end="", file=f) + for j in range(0, nb): + c = d[ip+j] + cs = "." + if is_printable(c, upper7=upper7): + cs = chr(c) + try: + print(cs, end="", file=f) + except UnicodeEncodeError: + print(".", end="", file=f) + print("", file=f) + tp -= nb + + +def str_hex(x): + x = as_bytes(x) + s = "" + for c in x: + s += ("%02x" % c) + return s + + +def str_hex_escape(x): + x = as_bytes(x) + s = "" + for c in x: + if is_printable(c): + s += chr(c) + else: + s += "\\x%02x" % c + return s + + +if __name__ == "__main__": + f = open(sys.argv[1]) + print_hex_dump(f.read(), width=32) + f.close() diff --git a/linux_app/pmu_app/pyperf/pyperf/imagemap.py b/linux_app/pmu_app/pyperf/pyperf/imagemap.py new file mode 100644 index 00000000..8e5181f2 --- /dev/null +++ b/linux_app/pmu_app/pyperf/pyperf/imagemap.py @@ -0,0 +1,713 @@ +# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# SPDX-License-Identifier : Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" +This module manages a set of program images, providing opcodes +and/or symbols at given addresses. + +An imagemap object owns multiple images. + +TBD: we don't yet support multiple address spaces. + +There are two ways we could support multiple address spaces: + + - we could rely on the caller to construct multiple imagemaps. + When changing context id they would change to the imagemap + for that context id. Images such as the kernel, which are + common to all address spaces, would need to be loaded into + each imagemap. + + - we could add a context parameter to each image. When looking + up an address, the caller would supply the current context id. + Images such as the kernel could have a 'None' context id. + +TBD: we don't yet have time awareness, i.e. a mapping only being +valid from, until or between time durations. +This also could be done two ways: + + - by requiring the caller to keep the imagemap up to date, + e.g. by tracking image load and unload events. + + - by associating validity intervals with each image and requiring + a caller to pass in a timestamp with each address. + +Note that multi-address-space support could be built on top of +time-awareness, in the sense that images for an address space could +have their validity intervals intersected with the set of intervals +when their address space was the active one. +""" + +from __future__ import print_function + +import os, sys +import struct, mmap +import bisect +import subprocess +import platform + +import pyperf.elf as elf + +# sys.path.append("/root/symbolizer") +# import symbolizer + +o_target_arch = platform.machine() + + +def binutil(cmd): + """ + Get a binutil command name, appropriate for trace decode, PC-to-symbol resolution etc. + For native ARM systems (32 or 64 bit) this will use native binutils. + For other platforms it will assume you will be decoding 32-bit trace. + """ + if o_target_arch == platform.machine(): + return "/usr/bin/" + cmd + else: + return "arm-none-eabi-" + cmd + + +def is_ARM_mapping_symbol(s): + return elf.is_mapping_symbol_ARM(s) + + +class Symtab(): + """ + Symbol table - maps addresses to symbols. + """ + def __init__(self): + self.syms = [] # list of (addr, name) pairs + self.sym_addr = None + self.sym_names = {} + + def __len__(self): + return len(self.syms) + + def __getitem__(self, ix): + self.ensure_sorted() + return self.syms[ix] + + def add(self, addr, name): + self.syms.append((addr, name)) + self.sym_addr = None + self.sym_names[name] = addr + + def sorted_by_addr(self): + self.ensure_sorted() + for sym in self.syms: + yield sym + + def show(self): + for (addr, name) in self.sorted_by_addr(): + print("0x%08x %s" % (addr, name)) + + def ensure_sorted(self): + if self.sym_addr is None: + self.syms.sort(key=lambda a_n: a_n[0]) + self.sym_addr = [addr for (addr, name) in self.syms] + # now self.syms is sorted by address and sym.addr is the + # addresses from the same list + + def find_sym_by_name(self, name): + """ + Given a name, find the (first?) symbol with that name. + """ + if name in self.sym_names: + return self.sym_names[name] + return None + + def find_exact_sym_by_addr(self, addr): + """ + Given an address, find a symbol at that address, or None. + """ + st = self.find_sym_by_addr(addr) + if st is None or st[0] != addr: + return None + return st[1] + + def find_sym_by_addr(self, addr): + """ + Given an address, return a tuple + (addr, name) + for the nearest previous symbol in address order. + """ + self.ensure_sorted() + ix = bisect.bisect_right(self.sym_addr, addr) + if ix: + ix -= 1 + assert self.sym_addr[ix] <= addr + s = self.syms[ix] + assert s[0] <= addr + return s + else: + return None + + def desc_sym_by_addr(self, addr, decimal=False): + """ + Given an address, return a descriptive string, e.g. + "name+0x10" + """ + s = self.find_sym_by_addr(addr) + if s is None: + return "0x%x" % addr + else: + (a, name) = s + if a == addr: + return name + else: + offset = addr - a + assert offset > 0 + if decimal: + return "%s+%u" % (name, offset) + else: + return "%s+0x%x" % (name, offset) + + + +def read_nm_symlist(sl, symtab, load=0, reject=None, map=None): + """ + Read a symbol list, as output from 'nm', into a provided symbol table. + Input is a file-like-object that we can read line by line. + Return the number of symbols added. + We can't assume input is sorted (/proc/kallsyms isn't). + + In /proc/kallsyms, symbols from dynamically loaded modules are suffixed by the module name. + + 123456 t sym + 123456 t sym [module] + """ + n = 0 + for s in sl: + try: + s = s.decode() + except AttributeError: + pass + if s[0] == " ": + # e.g. undefined symbol + continue + sp = s.find(' ') + if sp < 4: + continue + try: + # Symbol 'address'. In AArch32, LSB will be interworking bit. + addr = int(s[0:sp], 16) + except ValueError: + if s.startswith("ELF"): + print("possibly ELF file?") + raise + print("odd line: %s" % s) + raise + if map is not None: + addr = map(addr) + pa = addr + load + name = s[sp+3:-1] + if not name: + # sometimes seen for 'r' symbols + continue + if reject is not None and reject(name): + continue + symtab.add(pa, name) + n += 1 + return n + + +def read_elf_symlist(fn, symtab, load=0): + """ + For an ELF file, add its exported symbols to a provided symbol table. + The symbol address can be adjusted by a provided load address - + this is for shared objects. + """ + E = elf.ELF(fn) + method = "nm" + cmd = binutil("nm") + (" %s" % fn) + if False: + print(">>> %s" % cmd) + p = subprocess.Popen(cmd.split(), shell=False, stdout=subprocess.PIPE, stderr=subprocess.PIPE) + pipe = p.stdout + n = read_nm_symlist(pipe, symtab, load=load, reject=E.is_mapping_symbol, map=E.symbol_real_address) + pipe.close() + rc = p.wait() + if rc != 0: + raise OSError("command failed: %s" % cmd) + if n == 0: + # nm didn't find anything. Perhaps a library with only dynamic symbols? + method = "objdump -T" + cmd = binutil("objdump") + (" -T %s" % fn) + p = subprocess.Popen(cmd.split(), shell=False, stdout=subprocess.PIPE) + pipe = p.stdout + for s in pipe: + if len(s) < 30: + continue + if s[17:22] != ".text": + continue + try: + addr = int(s[0:8], 16) + except ValueError: + print("odd line: %s" % s) + continue + # split() isn't very helpful here as some columns are blanks. + ix = 37 + while s[ix] != ' ': + ix += 1 + while s[ix] == ' ': + ix += 1 + name = s[ix:-1] + pa = addr + load + symtab.add(pa, name) + n += 1 + pipe.close() + if n > 0: + print("%s: added %u symbols (%s)" % (fn, n, method)) + return n + + +def proc_map_images(fn): + """ + Read a /proc//map file and yield any images with an executable part. + """ + f = open(fn, "r") + for ln in f: + v = ln.split() + ix = ln.find("-") + base = int(ln[0:ix], 16) + if v[1][2] == 'x': + # executable area + fn = v[5] + if fn[0] != "[": + yield (base, fn) + f.close() + + +def proc_modules(): + """ + Read /proc/modules and yield modules and their load-addresses, as a map + """ + modules = {} + f = open("/proc/modules") + for ln in f: + # don't do tuple assignment as number of fields may vary + d = ln.split() + name = d[0] + saddr = d[5] + status = d[4] + if status == "Live": + modules[name] = int(saddr[2:], 16) + f.close() + return modules + + +class image(): + """ + An object of this class represents a specific instance of a + program text section, loaded into an address space at a given address. + + For shared objects, load_addr should indicate the actual load address. + This is then used to adjust actual addresses down to their relative + address in the image. + """ + def __init__(self, base_addr, data, elf=None, original_name=None, description=None, load_addr=0x0, deferred=False): + # base_addr is the address, in the address space, corresponding + # to byte 0 of the data. That is, data()[0] is the byte at address 'base_addr'. + # It isn't necessarily the load address of the containing module, which + # is used to adjust addresses. + # For example, an executable whose .text section is at 0x8000 + # would have, for the image object for that .text section: + # base_addr = 0x8000 + # load_addr = 0 + self.base_addr = base_addr # Address within the address space + self.deferred = deferred + if not deferred: + self._data = bytearray(data) # Contents of this range of addresses + self.end_addr = base_addr + len(data) # End address within address space + else: + self._data = data + self.end_addr = base_addr + data.size() + self.elf = elf + if original_name is None: + original_name = elf + self.original_name = original_name + if description is None and self.file_name() is not None: + description = "from %s" % self.file_name() + if self.elf != self.original_name: + description += " (%s)" % self.elf + self.description = description + self.load_addr = load_addr + self.a2l_process = None + + def data(self): + if self.deferred: + self._data = self._data.data() + self.deferred = False + return self._data + + def contains(self, addr, size=1): + return self.base_addr <= addr and (addr+size) <= self.end_addr + + def symbolize(self, addr): + addr -= self.load_addr + if self.elf is not None: + return symbolizer.symbolize(self.elf, addr) + + def file_name(self): + return self.original_name + + def __str__(self): + s = "0x%x..0x%x %s" % (self.base_addr, self.end_addr-1, self.description) + return s + + def addr2line(self, addr): + """ + Given an absolute address, map it to a source position. + The result is + (fun, file, line, disc) + fun is the function name string (from DWARF if possible - e.g. inlined function) + file is the source filename, with directory prepended + line is the line number + disc is the DWARF4 discriminator where supplied - normally zero + Return None if the address doesn't resolve to a source line. + TBD: check we do the right thing with column, for those compilers that generate it. + """ + debug = False + addr -= self.load_addr + if False: + pos = symbolizer.symbolize(self.elf, addr)[0] + if pos[0] == "??": + pos = None + return pos + if self.a2l_process is None: + if self.elf is None: + # print "no ELF image for address 0x%x" % addr + return None + if not os.path.isfile(self.elf): + return None + if debug: + print("%s: starting addr2line (load addr = 0x%x)" % (self.elf, self.load_addr), file=sys.stderr) + cmd = binutil("addr2line") + " -f --exe=%s" % self.elf + self.a2l_process = subprocess.Popen(cmd.split(), shell=False, stdin=subprocess.PIPE, stdout=subprocess.PIPE, universal_newlines=True) + # For a position-independent dynamic module, we need to convert the + # address in the current address space, into an address that will be + # meaningful to addr2info. To do that, we subtract the module load address. + # For executables (or any other image that is loaded at the address specified + # in the ELF image), the load address is zero. + if debug: + print("%s: addr2line 0x%x" % (self.elf, addr), file=sys.stderr) + self.a2l_process.stdin.write("0x%x\n" % addr) + self.a2l_process.stdin.flush() + fun = self.a2l_process.stdout.readline()[:-1] + pos = self.a2l_process.stdout.readline()[:-1] + if is_ARM_mapping_symbol(fun): + # addr2line shouldn't do this: GNUTOOLS-5134 + if False: + print("addr2line returned ARM mapping symbol %s as function name" % fun) + print("%s -f -e %s %x" % (binutil("addr2line"), self.elf, addr)) + fun = "?" + if False: + print("addr2line: 0x%08x -> [%s,%s]" % (addr, fun, pos)) + p = pos.index(':') + if pos[p+1] != "?": + file = pos[:p] + sline = pos[p+1:] + p = sline.find(" (discriminator ") + if p == -1: + line = int(sline) + disc = 0 + else: + line = int(sline[:p]) + sline = sline[p+16:] + p = sline.index(")") + disc = int(sline[:p]) + return (fun, file, line, disc) + else: + return None + + +class imagemap(): + """ + Map one or more address spaces. + An address space is assumed to be covered by multiple images. + Images can be added to (TBD: and removed from) the address space. + An address can be looked up in the map, giving an image and + within that, address properties such as symbol and source position. + """ + def __init__(self): + self.images = [] + self.symtab = Symtab() + + def add_segment(self, bin, addr, name=None, elf=None, original_name=None, load_addr=0, deferred=False): + """ + Add a binary blob at a given address. + The load_addr is the load address of a dynamic module - + this is used to adjust the address passed in to binutils + utilities. + The name parameter is for diagnostic purposes only - + it can be used to indicate where we got this blob from. + """ + assert load_addr <= addr, "%s: adding segment, expected load address 0x%x <= 0x%x" % (elf, load_addr, addr) + im = image(addr, bin, description=name, elf=elf, original_name=original_name, load_addr=load_addr, deferred=deferred) + self.images.append(im) + return im + + def add_bin(self, fn, addr, name=None, offset=0, size=None, original_name=None): + """ + Add a binary blob from a file. + [offset,offset+size) indicates the bloblet within the file. + [addr,addr+size) is where it is loaded into the address space. + """ + f = open(fn, "rb") + bin = bytearray(f.read()) + f.close() + if name is None: + rfn = fn + if original_name is not None: + rfn = original_name + name = "(from %s)" % rfn + if size is not None: + bin = bin[offset:offset+size] + else: + bin = bin[offset:] + return self.add_segment(bin, addr, name=name, original_name=original_name) + + def add_proc_map_images(self, fn, dir="."): + """ + Process /proc//xxx and add any described images to the + image map. + """ + for (base, im) in proc_map_images(fn): + if os.path.exists(im): + self.add_elf(im, load=base) + continue + lfn = dir + os.sep + im + if os.path.exists(lfn): + self.add_elf(lfn, load=base) + else: + print("missing code at 0x%08x: %s" % (base, lfn)) + + def show(self): + # show memory mappings + if not self.images: + print("** no images loaded in address map **") + sorted_images = sorted(self.images, key=lambda im: im.base_addr) + for im in sorted_images: + if im.description is None: + name = "" + else: + name = im.description + if False: + for i in range(0, 20): + byte = im.data()[i] # it's now a bytearray + print("%02x" % (byte), end=' ') + print(" ", end=' ') + print("0x%016x-0x%016x: %s" % (im.base_addr, im.end_addr, name)) + # after all the address ranges, show symbols (summary) + if self.symtab: + print("symbol table:") + print(" 0x%08x (%s) to 0x%08x (%s)" % (self.symtab[0][0], self.symtab[0][1], self.symtab[-1][0], self.symtab[-1][0])) + + def add_nm_syms(self, fn): + """ + Read a file containing the output of 'nm' (or Symtab) and add to the symbol list + This can also be used with /proc/kallsyms. + """ + f = open(fn, "r") + read_nm_symlist(f, self.symtab) + f.close() + + def add_file(self, fn, load=0, offset=0, size=None, original_name=None): + """ + Given a file (maybe ELF, maybe not) map it into the address space. + [offset,offset+size) denotes the region within the file. + [load,load+size) denotes the region within the address space. + """ + if offset > 0: + self.add_bin(fn, load, offset=offset, size=size, original_name=original_name) + return + try: + self.add_elf(fn, load=load, original_name=original_name) + except elf.NotELF: + self.add_bin(fn, load, offset=offset, size=size, original_name=original_name) + + def add_elf_syms(self, fn, load=0): + """ + Given an ELF file, add just the symbols. + """ + #print("read ELF symbols: %s" % fn, file=sys.stderr) + read_elf_symlist(fn, self.symtab, load=load) + + def add_elf(self, fn, load=0, is_ko=False, original_name=None, syms=None): + """ + Given an ELF file, add the symbols and all available text. + The 'load' parameter indicates where in the address space the ELF file was loaded. + """ + # Extract the code sections - objcopy -O binary isn't enough + #print("%s: reading code, loaded at 0x%x..." % (fn, load)) + expected_type = None + trace = False + if is_ko: + expected_type = 1 + e = elf.ELF(fn) + if e.elf_type is None: + print("%s: not an ELF file" % fn) + return None + if expected_type is not None: + if e.elf_type != expected_type: + print("%s: expected ELF type %u, got %u" % (fn, expected_type, e.elf_type)) + return None + else: + if e.elf_type != elf.ET_DYN: + # if it's not ET_DYN, don't do the address adjustment + print("%s: not a shared object (type=%u) - load address ignored" % (fn, e.elf_type)) + load = 0 + if syms is not None: + self.add_nm_syms(syms) + elif fn == "/proc/kcore": + self.add_nm_syms("/proc/kallsyms") + else: + self.add_elf_syms(fn, load=load) + if is_ko: + # loadable kernel module (see add_ko below): emulate layout_sections() + alloc = load + # we should run through the sections several times, for each section class + # (executable sections first etc.) but as we're only interested in executable + # sections, we just do that + for s in e.sections(): + if (s.sflags & elf.SHF_ALLOC) == 0: + continue + if s.stype != elf.SHT_PROGBITS: + continue + if (s.sflags & elf.SHF_EXECINSTR) == 0: + continue + if s.salign == 0: + s.salign = 1 + assert saddr == 0, "expected section address zero in kernel module" + alloc = (alloc+s.salign-1) & ~(s.salign-1) + print(" section #%u at addr=0x%x size=0x%x align=%u" % (i, alloc, s.ssize, s.salign)) + self.add_segment(s.data(), alloc, elf=fn, load_addr=load) + # TBD we should fix up relocations to the kernel / other modules, + # so that BLs point to the right places. We should also patch out + # calls to _mcount, and apply alternative code sequences. + alloc += s.ssize + return + n_segments = 0 + if trace: + print("%s load address 0x%x" % (original_name, load)) + for s in e.segments(): + if s.type != elf.PT_LOAD: + continue + if trace: + print("considering at 0x%x..0x%x size 0x%x" % (s.vaddr+load, s.vaddr+load+s.filesz, s.filesz)) + if (s.flags & elf.PF_X) == 0: + continue # Not a code segment + if s.filesz > 0x100000000: + continue # seen in /proc/kcore, overlays with other segments + im = self.add_segment(s, s.vaddr+load, elf=fn, original_name=original_name, load_addr=load, deferred=True) + if trace: + print(" added segment: %s" % im) + n_segments += 1 + if n_segments == 0: + print("** %s: no load segments!" % fn) + + def add_ko(self, name, load): + """ + Add a loadable kernel module (a xxx.ko file). + Unlike a userspace shared object, a KO is a relocatable file (ET_REL) + described by sections rather than segments. The address layout is done + at load time: see layout_sections(). + """ + self.add_elf(name, load, is_ko=True) + + def find_sym_by_name(self, name): + return self.symtab.find_sym_by_name(name) + + def desc_sym_by_addr(self, addr, decimal=False): + return self.symtab.desc_sym_by_addr(addr, decimal=decimal) + + def find_sym_by_addr(self, addr): + # return None or a tuple (addr, name) + return self.symtab.find_sym_by_addr(addr) + + def find_exact_sym_by_addr(self, addr): + return self.symtab.find_exact_sym_by_addr(addr) + + def find_image(self, addr, size=1): + for im in self.images: + if im.contains(addr, size): + return im + return None + + def is_mapped(self, addr, size=1): + return self.find_image(addr, size) is not None + + def addr2line(self, addr): + im = self.find_image(addr, 1) + if im is not None: + return im.addr2line(addr) + else: + return None + + def symbolize(self, addr): + im = self.find_image(addr, 1) + if im is not None: + return im.symbolize(addr) + else: + return None + + def read(self, addr, size): + im = self.find_image(addr, size) + if im is not None: + return im.data()[addr-im.base_addr:addr-im.base_addr+size] + return None + + def write(self, addr, s): + # patch the image contents. This might be necessary in order to track + # hotpatching events, or apply alternative code sequences (as described + # in the __alt_instructions table) to a kernel image. + # We rely on the image being a bytearray(). + size = len(s) + im = self.find_image(addr, size) + assert im is not None + im.data()[addr-im.base_addr:addr-im.base_addr+size] = s + + def read16(self, addr): + s = self.read(addr, 2) + if s is not None: + s = struct.unpack("H", s)[0] + return s + + def read32(self, addr): + s = self.read(addr, 4) + if s is not None: + s = struct.unpack("I", s)[0] + return s + + +if __name__ == "__main__": + args = sys.argv[1:] + m = imagemap() + while len(args) > 0: + arg = args[0] + del args[0] + if arg.startswith("--"): + if arg == "--elf": + fn = args[0] + del args[0] + m.add_elf(fn) + else: + print("** unknown option: %s" % arg) + else: + addr = int(arg, 16) + print("0x%x -> %s" % (addr, m.desc_sym_by_addr(addr))) + val = m.read32(addr) + if val is not None: + print("0x%x: 0x%08x" % (addr, val)) + else: + print("0x%x: not available" % (addr)) diff --git a/linux_app/pmu_app/pyperf/pyperf/perf_abi.py b/linux_app/pmu_app/pyperf/pyperf/perf_abi.py new file mode 100644 index 00000000..c782ab33 --- /dev/null +++ b/linux_app/pmu_app/pyperf/pyperf/perf_abi.py @@ -0,0 +1,739 @@ +# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# SPDX-License-Identifier : Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" +This module encapsulates data structures defined by the perf_event_open syscall ABI, +and (as a result) by the perf.data file format: + + PerfRecord - an event record returned by the kernel in the + memory-mapped buffer. + Also recorded in the data section of perf.data. + +Note the terminology: + + - a RECORD (PerfRecord) is a specific occurrence of some event, + generated for us by the kernel. + + - an EVENT (PerfEventAttr) is a descriptor of a set of event occurrences + that we are interested in. An EVENT will (in the kernel) have a file + descriptor and ring buffer associated with it. + + - an EVENT DESCRIPTOR (PerfDataEventDesc) in perf.data describes a + group of events. + +Structures specific to perf.data (i.e. artefacts of the userspace tools) +are defined in the perf_data module. + +""" + +from __future__ import print_function + +from pyperf.perf_enum import * +from pyperf.perf_attr import PerfEventAttr +from pyperf.hexdump import print_hex_dump, str_hex, str_hex_escape + +import struct, sys + + +_PERF_RECORD_MAX_FROM_KERNEL = 64 + +def bits(x, pos, w): + return (x >> pos) & ((1<> p) & 1 + + +def bitbool(x, p): + return bit(x, p) != 0 + + +def ip_perf_context(ip): + # TBD this is wrong on 32-bit systems. + if (ip & 0xfffffffffffff000) == 0xfffffffffffff000: + return ip - 0x10000000000000000 + else: + return None + + +def trailing_string(d, check=None): + # d is a byte array, length a multiple of 8. Extract a string and remove trailing NULs. + # Check that the NUL is in the expected place. + assert isinstance(d, bytearray) or isinstance(d, bytes), "invalid record: %s" % type(d) + ix = d.find(b'\0') + if ix < 0: + if check: + check.note("string does not have trailing NUL: '%s'" % str_hex_escape(d)) + ix = len(d) + if ix < len(d)-8: + if check: + check.note("string has NUL too early: '%s'" % str_hex_escape(d)) + s = d[:ix].decode() + nuls = bytearray(d[ix:]) # should be all NULs + for c in nuls: + if c != 0x00: + # We see this in synthesized MMAP records + if check: + check.note("unexpected character '0x%02x' found in string padding after \"%s\"" % (c, s)) + break + return s + + +def strip_trailing_nuls(s): + if '\0' in s: + s = s[:s.index('\0')] + return s + + +class PerfBranchEntry: + def __init__(self): + pass + + +class PerfRegSample: + """ + Register snapshot - architecture-specific + """ + def __init__(self, sample_regs): + self.sample_regs = sample_regs + + def sample(self, d): + self.abi = struct.unpack("Q", d[:8])[0] + sru = self.sample_regs + d = d[8:] + self.regs = {} + n = 0 + while sru != 0: + if (sru & 1) != 0: + if self.abi == PERF_SAMPLE_REGS_ABI_32: + r = struct.unpack("I", d[:4])[0] + d = d[4:] + elif self.abi == PERF_SAMPLE_REGS_ABI_64: + r = struct.unpack("Q", d[:8])[0] + d = d[8:] + else: + assert False, "unknown PERF_SAMPLE_REGS_USER ABI=%u" % self.abi + self.regs[n] = r + sru >>= 1 + n += 1 + return d + + +class ReadFormat: + """ + One, or several, event values. + """ + def __init__(self, read_format): + self.read_format = read_format + self.values = [] + + def _unpack_times(self, d): + if self.read_format & PERF_FORMAT_TOTAL_TIME_ENABLED: + self.time_enabled = struct.unpack("Q", d[:8]) + d = d[8:] + else: + self.time_enabled = None + if self.read_format & PERF_FORMAT_TOTAL_TIME_RUNNING: + self.time_running = struct.unpack("Q", d[:8]) + d = d[8:] + else: + self.time_running = None + return d + + def unpack(self, d): + if self.read_format & PERF_FORMAT_GROUP: + self.nr = struct.unpack("Q", d[:8])[0] + d = self._unpack_times(d[8:]) + for i in range(0, self.nr): + value = struct.unpack("Q", d[:8])[0] + d = d[8:] + if self.read_format & PERF_FORMAT_ID: + vid = struct.unpack("Q", d[:8])[0] + d = d[8:] + else: + vid = None + self.values.append((value, vid)) + else: + self.nr = 1 + value = struct.unpack("Q", d[:8])[0] + d = self._unpack_times(d[8:]) + if self.read_format & PERF_FORMAT_ID: + vid = struct.unpack("Q", d[:8])[0] + d = d[8:] + else: + vid = None + self.values.append((value, vid)) + return d + + +def record_trailing_bytes(ea): + # Return the size of the standard trailing fields in a non-SAMPLE record, + # given an event attribute with sample type. + # See also PerfRecord.unpack_sample_id(). + if not ea.sample_id_all: + return 0 + st = ea.sample_type + n = 0 + if st & PERF_SAMPLE_IDENTIFIER: + n += 8 + if st & PERF_SAMPLE_CPU: + n += 8 + if st & PERF_SAMPLE_STREAM_ID: + n += 8 + if st & PERF_SAMPLE_ID: + n += 8 + if st & PERF_SAMPLE_TIME: + n += 8 + if st & PERF_SAMPLE_TID: + n += 8 + return n + + +def record_non_sample_id_offset(ea): + # Get the offset (negative from end-of-record) of the id field, + # for a non-sample record. + if not ea.sample_id_all: + return None + st = ea.sample_type + if st & PERF_SAMPLE_IDENTIFIER: + return -8 + if st & PERF_SAMPLE_ID: + n = 0 + if st & PERF_SAMPLE_CPU: + n -= 8 + if st & PERF_SAMPLE_STREAM_ID: + n -= 8 + n -= 8 + return n + return None + + +def record_non_sample_time_offset(ea): + # Get the offset (negative from end-of-record) of the time field, + # for a non-sample record. + if not ea.sample_id_all: + return None + st = ea.sample_type + if st & PERF_SAMPLE_TIME: + n = 0 + if st & PERF_SAMPLE_IDENTIFIER: + n -= 8 + if st & PERF_SAMPLE_CPU: + n -= 8 + if st & PERF_SAMPLE_STREAM_ID: + n -= 8 + if st & PERF_SAMPLE_ID: + n -= 8 + n -= 8 + return n + return None + + +def record_sample_id_offset(ea): + # Get the offset (from start of payload) of the id field for a sample. + st = ea.sample_type + if st & PERF_SAMPLE_IDENTIFIER: + return 0 + if st & PERF_SAMPLE_ID: + n = 0 + if st & PERF_SAMPLE_IP: + n += 8 + if st & PERF_SAMPLE_TID: + n += 8 + if st & PERF_SAMPLE_TIME: + n += 8 + if st & PERF_SAMPLE_ADDR: + n += 8 + return n + return None + + +def record_sample_time_offset(ea): + # Get the offset (from start of payload) of the time field for a sample. + st = ea.sample_type + if st & PERF_SAMPLE_TIME: + n = 0 + if st & PERF_SAMPLE_IDENTIFIER: + n += 8 + if st & PERF_SAMPLE_IP: + n += 8 + if st & PERF_SAMPLE_TID: + n += 8 + return n + return None + + +_non_sample_trailing_sample_fields = PERF_SAMPLE_IDENTIFIER|PERF_SAMPLE_CPU|PERF_SAMPLE_STREAM_ID|PERF_SAMPLE_ID|PERF_SAMPLE_TIME|PERF_SAMPLE_TID + + +def non_sample_sample_type(ea): + if ea.sample_id_all: + return ea.sample_type & _non_sample_trailing_sample_fields + else: + return 0 + + +def non_sample_has_sample_fields(ea): + return non_sample_sample_type(ea) != 0 + + +class PerfRecord: + """ + Maps on to "struct perf_event" defined by the perf_event_open syscall ABI. + This is, basically, a record of an event. + The kernel puts a series of these in the ring buffer, + and "perf record" writes them into perf.data. + + As a Python object, this contains both + - the raw encoded binary data, in 'struct perf_event' format + - separate fields for each data item, as a result of unpacking the raw binary data + The caller must set the event_attr field so that the encoding + can be determined. + """ + def __init__(self, raw=None, type=None, event_attr=None, perf_version=0): + self._abi_errors = [] + self.raw = raw + self.perf_version = perf_version # If read from perf.data - for working around perf inject bugs + if raw is not None: + # it should be str/bytes (Python2) or bytes (Python3), or bytearray + assert type is None + (self.type, self.misc, self.size) = struct.unpack("IHH", raw[0:8]) + assert self.size == len(raw), "record size mismatch: given %u bytes but header says %u" % (len(raw), self.size) + else: + assert type is not None + self.type = type + self.misc = 0 + self.has_been_unpacked = False + if event_attr is not None: + assert isinstance(event_attr, PerfEventAttr) + self.event_attr = event_attr + self.reset() + + def note(self, s, sev=None): + """ + Note that something odd happened during decode. + """ + #print("%s" % s, file=sys.stderr) + if sev != "warning": + self._abi_errors.append(s) + + def time(self): + """ + Get the record's timestamp. If the record hasn't yet been fully unpacked, + get the timestamp as quickly as we can. + """ + if self.t is not None or self.has_been_unpacked: + return self.t + # Don't unpack the whole thing, just get the time as quickly as we can + if self.is_sample(): + off = record_sample_time_offset(self.event_attr) + if off is not None: + off = off + 8 # we got the offset in the payload, need it from the header + self.t = struct.unpack("Q", self.raw[off:off+8])[0] + elif self.is_kernel_type(): + off = record_non_sample_time_offset(self.event_attr) + if off is not None: + if off != -8: + td = self.raw[off:off+8] + else: + td = self.raw[-8:] + self.t = struct.unpack("Q", td)[0] + return self.t + + def data(self): + return self.raw[8:] + + def set_data(self, d): + self.size = 8 + len(d) + self.raw = struct.pack("IHH", self.type, self.misc, self.size) + d + assert self.size == len(self.raw) + + def is_sample(self): + return self.type == PERF_RECORD_SAMPLE + + def is_kernel_type(self): + """ + Return true if the record was of a type that the kernel creates and puts + in the mmap buffer, with a format defined by the kernel ABI (although + any given record might have been synthesized in userspace, e.g. the + synthetic MMAP records created by "perf record"). + """ + return self.type < _PERF_RECORD_MAX_FROM_KERNEL + + def __str__(self): + """ + Return a basic description of the record. + """ + s = "[0x%x]: %s%s" % (self.size, str_PERF_RECORD(self.type), self.payload_str()) + return s + + def payload_str(self): + """ + Return summary details of the record payload, as a string. + This isn't a substitute for the detailed description of "perf report -D". + """ + s = "" + if self.id is not None: + s += " id=%s" % self.id + if self.cpu is not None: + s += " cpu=%d" % self.cpu + if self.pid is not None: + s += " pid=%d" % self.pid + if self.tid is not None: + s += " tid=%d" % self.tid + if self.ip is not None: + s += " ip=0x%x" % self.ip + if self.has_been_unpacked: + if self.type in [PERF_RECORD_MMAP, PERF_RECORD_MMAP2]: + s += " %s @0x%x" % (self.filename, self.pgoff) + elif self.type == PERF_RECORD_COMM: + s += " '%s'" % (self.thread_name) + elif self.type == PERF_RECORD_AUX: + s += " offset=0x%x size=0x%x flags=0x%x" % (self.aux_offset, self.aux_size, self.flags) + elif self.type == PERF_RECORD_LOST: + s += " lost_id=%d n=%d" % (self.lost_id, self.lost_n) + elif self.type == PERF_RECORD_SWITCH_CPU_WIDE: + if (self.misc & PERF_RECORD_MISC_SWITCH_OUT) != 0: + s += " OUT next_pid=%d next_tid=%d" % (self.next_prev_pid, self.next_prev_tid) + else: + s += " IN prev_pid=%d prev_tid=%d" % (self.next_prev_pid, self.next_prev_tid) + else: + s += " " + return s + + def unpack_sample_id(self, d): + """ + When sample_id_all is set, fields such as TID/TIME/ID/STREAM_ID/CPU + (as selected by sample_type) can be included in non-SAMPLE records + as trailing fields. + Retrieve the fields, and strip it from the record data, + updating the record object fields and returning the remaining + record-type-specific payload. + Note that if PERF_SAMPLE_IDENTIFIER and PERF_SAMPLE_ID are set, + the identifier will appear twice. + """ + if self.event_attr is None: + assert False, "attempt to get trailing fields when attributes not set" + if not self.event_attr.sample_id_all: + # This record is associated with an event that doesn't have + # trailing fields. + return d + st = self.event_attr.sample_type + if st & PERF_SAMPLE_IDENTIFIER: + self.id = struct.unpack("Q", d[-8:])[0] + d = d[:-8] + if st & PERF_SAMPLE_CPU: + (self.cpu, res) = struct.unpack("II", d[-8:]) + d = d[:-8] + if st & PERF_SAMPLE_STREAM_ID: + self.stream_id = struct.unpack("Q", d[-8:])[0] + d = d[:-8] + if st & PERF_SAMPLE_ID: + self.id = struct.unpack("Q", d[-8:])[0] + #print("%s ASSIGNED ID : %s" % (self.type, self.id)) + d = d[:-8] + if st & PERF_SAMPLE_TIME: + self.t = struct.unpack("Q", d[-8:])[0] + d = d[:-8] + if st & PERF_SAMPLE_TID: + (self.pid, self.tid) = struct.unpack("ii", d[-8:]) + # Should we assign to self.pid and self.tid? + d = d[:-8] + return d + + def reset(self): + self.id = None + self.ip = None + self.pid = None + self.tid = None + self.addr = None + self.data_src = None + self.phys_addr = None + self.t = None + self.period = None + self.cpu = None + self.callchain = None + self.branch_stack = None + self.read = None + self.weight = None + self.stack_user = None + self.regs_user = None + self.regs_intr = None + + def string(self, d): + return trailing_string(d, check=self) + + def unpack(self): + """ + Unpack the encoded data in the perf record, setting appropriate + fields in the Python object. + + The event attributes tell us the format of sample records. + We will already have got the event attributes, either because we're + parsing the result of a specific mmap buffer, or because we've peeked into + the record and got the identifier at a known offset. + """ + if self.has_been_unpacked: + return self + assert self.event_attr is not None, "event attributes must be set before unpacking: %s" % self + self._abi_errors = [] + d = self.data() + if self.is_sample(): + """ + Process the fields in the sample. These occur in a defined order + and are present/absent depending on the PERF_SAMPLE flags. + See the section beginning "This record indicates a sample" + in the perf_event_open man page. + """ + st = self.event_attr.sample_type + if st & PERF_SAMPLE_IDENTIFIER: + # "This is a duplication of the PERF_SAMPLE_ID id value, + # but included at the beginning of the sample so parsers + # can easily obtain the value." + self.id = struct.unpack("Q", d[:8])[0] + st &= ~PERF_SAMPLE_IDENTIFIER + d = d[8:] + if st & PERF_SAMPLE_IP: + self.ip = struct.unpack("Q", d[:8])[0] + st &= ~PERF_SAMPLE_IP + d = d[8:] + if st & PERF_SAMPLE_TID: + (self.pid, self.tid) = struct.unpack("ii", d[:8]) + st &= ~PERF_SAMPLE_TID + d = d[8:] + if st & PERF_SAMPLE_TIME: + self.t = struct.unpack("Q", d[:8])[0] + st &= ~PERF_SAMPLE_TIME + d = d[8:] + if st & PERF_SAMPLE_ADDR: + self.addr = struct.unpack("Q", d[:8])[0] + st &= ~PERF_SAMPLE_ADDR + d = d[8:] + if st & PERF_SAMPLE_ID: + # Collective identifier for the event - parent of stream id + self.id = struct.unpack("Q", d[:8])[0] + st &= ~PERF_SAMPLE_ID + d = d[8:] + if st & PERF_SAMPLE_STREAM_ID: + # Unique identifier for the event + self.stream_id = struct.unpack("Q", d[:8])[0] + st &= ~PERF_SAMPLE_STREAM_ID + d = d[8:] + if st & PERF_SAMPLE_CPU: + (self.cpu, res) = struct.unpack("II", d[:8]) + st &= ~PERF_SAMPLE_CPU + d = d[8:] + if st & PERF_SAMPLE_PERIOD: + self.period = struct.unpack("Q", d[:8])[0] + st &= ~PERF_SAMPLE_PERIOD + d = d[8:] + else: + if not self.event_attr.freq: + self.period = self.event_attr.sample_period + if st & PERF_SAMPLE_READ: + # "A structure of type read_format is included which + # has values for all events in the event group. + # The values included depend on the read_format + # value used at perf_event_open time." + self.read = ReadFormat(self.event_attr.read_format) + d = self.read.unpack(d) + st &= ~PERF_SAMPLE_READ + if st & PERF_SAMPLE_CALLCHAIN: + nr = struct.unpack("Q", d[:8])[0] + self.callchain = list(struct.unpack("Q"*nr, d[8:8+(nr*8)])) + st &= ~PERF_SAMPLE_CALLCHAIN + d = d[8+(nr*8):] + if st & PERF_SAMPLE_RAW: + size = struct.unpack("I", d[:4])[0] + self.sample_data = d[4:4+size] + st &= ~PERF_SAMPLE_RAW + d = d[4+size:] + if st & PERF_SAMPLE_BRANCH_STACK: + # This samples either an LBR sequence, or callchain information + bnr = struct.unpack("Q", d[:8])[0] + d = d[8:] + expect_hw_idx = (self.event_attr.branch_sample_type & PERF_SAMPLE_BRANCH_HW_INDEX) != 0 + if expect_hw_idx: + self.hw_idx = struct.unpack("q", d[:8])[0] + d = d[8:] + assert self.hw_idx <= bnr, "bad hw_idx field 0x%x, expected 0..%u" % (self.hw_idx, bnr) + elif bnr > 0 and struct.unpack("q", d[:8])[0] in [-1]: + # Around 2020, "perf inject" had a bug where it used the hw_idx + # field for synthetic samples (from PT or ETM) but didn't set HW_INDEX, + # so there's a spurious extra doubleword in the record. + # Speculatively work around that. The bug is specific to perf userspace. + # so ideally we'd only do it when decoding a perf.data file. + # The check on bnr avoids testing the field when we have an empty + # branch stack, as then we might be at the end of the sample record + # or be followed by unknown data. + # The failure mode is that we guess we have the extra doubleword, + # when it's actually the first branch source address. + # We try and defend against this by assuming that the dummy word will be + # 0xffffffffffffffff and that this is never a valid branch source address. + self.note("working around branch stack format bug", sev="warning") + d = d[8:] + self.hw_idx = None + else: + self.hw_idx = None + # Populate the branch_stack field in the returned record. This is in the + # order as it appears in the branch stack - i.e. most recent branch first, + # and possibly padded out to 32 (or whatever) number with "0->0" records. + self.branch_stack = [] + assert (bnr*24) <= len(d), "invalid branch stack count: %d needs %u bytes, only %u left (HW_INDEX=%u)" % (bnr, bnr*24, len(d), expect_hw_idx) + for i in range(0, bnr): + pbe = PerfBranchEntry() + (pbe.from_addr, pbe.to_addr, pbe.flags) = struct.unpack("QQQ", d[:24]) + pbe.mispred = bitbool(pbe.flags, 0) + pbe.predicted = bitbool(pbe.flags, 1) + pbe.in_tx = bitbool(pbe.flags, 2) + pbe.abort = bitbool(pbe.flags, 3) + pbe.cycles = bits(pbe.flags, 4, 16) + pbe.type = bits(pbe.flags, 20, 4) + self.branch_stack.append(pbe) + d = d[24:] + st &= ~PERF_SAMPLE_BRANCH_STACK + if st & PERF_SAMPLE_REGS_USER: + self.regs_user = PerfRegSample(self.event_attr.sample_regs_user) + d = self.regs_user.sample(d) + st &= ~PERF_SAMPLE_REGS_USER + if st & PERF_SAMPLE_STACK_USER: + size = struct.unpack("Q", d[:8])[0] + self.stack_offset = len(self.data()) - len(d) + 8 # remember offset in raw data + self.stack_user = d[8:8+size] + d = d[8+size:] + if size != 0: + dyn_size = struct.unpack("Q", d[:8])[0] + d = d[8:] + self.stack_dyn_size = dyn_size + else: + self.stack_dyn_size = 0 + st &= ~PERF_SAMPLE_STACK_USER + if st & PERF_SAMPLE_WEIGHT: + self.weight = struct.unpack("Q", d[:8])[0] + st &= ~PERF_SAMPLE_WEIGHT + d = d[8:] + if st & PERF_SAMPLE_DATA_SRC: + self.data_src = struct.unpack("Q", d[:8])[0] + st &= ~PERF_SAMPLE_DATA_SRC + d = d[8:] + if st & PERF_SAMPLE_TRANSACTION: + self.transaction = struct.unpack("Q", d[:8])[0] + st &= ~PERF_SAMPLE_TRANSACTION + d = d[8:] + if st & PERF_SAMPLE_REGS_INTR: + self.regs_intr = PerfRegSample(self.event_attr.sample_regs_intr) + d = self.regs_intr.sample(d) + st &= ~PERF_SAMPLE_REGS_INTR + if st & PERF_SAMPLE_PHYS_ADDR: + self.phys_addr = struct.unpack("Q", d[:8])[0] + st &= ~PERF_SAMPLE_PHYS_ADDR + d = d[8:] + if st & PERF_SAMPLE_CGROUP: + self.cgroup = struct.unpack("Q", d[:8])[0] + st &= ~PERF_SAMPLE_CGROUP + d = d[8:] + if st: + self.note("unconsumed sample_type bits: %s" % str_flags_PERF_SAMPLE(st)) + if d: + self.note("%u bytes unexpected data at end of %s sample" % (len(d), str_flags_PERF_SAMPLE(self.event_attr.sample_type))) + else: + # Record type other than PERF_RECORD_SAMPLE. + # This may be some other event record collected by the kernel perf subsystem and returned via mmap, + # or it may be a kernel-type record synthesized by "perf record", e.g. to provide initial memory mappings, + # or it may be a userspace-specific record used to provide additional metadata in perf.data. + if self.is_kernel_type() and non_sample_has_sample_fields(self.event_attr): + # Kernel-type records (whether synthetic or not) may be followed by trailing fields. + olen = len(d) + d = self.unpack_sample_id(d) + nlen = len(d) + assert nlen + record_trailing_bytes(self.event_attr) == olen + if self.type == PERF_RECORD_MMAP: + stuff = struct.unpack("iiQQQ", d[0:32]) + (self.pid, self.tid, self.addr, self.len, self.pgoff) = stuff + self.prot = 0x04 # PROT_EXEC; other flags unknown + self.flags = None + self.maj = None + self.min = None + self.filename = self.string(d[32:]) + elif self.type == PERF_RECORD_LOST: + (self.lost_id, self.lost_n) = struct.unpack("QQ", d) + elif self.type == PERF_RECORD_COMM: + (self.pid, self.tid) = struct.unpack("ii", d[0:8]) + self.thread_name = self.string(d[8:]) # max 16 chars: see TASK_COMM_LEN + elif self.type == PERF_RECORD_EXIT: + # the sample_id timestamp is preferred to the one in the record + stuff = struct.unpack("IIIIQ", d) + (self.pid, self.ppid, self.tid, self.ptid, ignore_time) = stuff + elif self.type == PERF_RECORD_THROTTLE: + (self.t, self.id, self.stream_id) = struct.unpack("QQQ", d) + elif self.type == PERF_RECORD_UNTHROTTLE: + (self.t, self.id, self.stream_id) = struct.unpack("QQQ", d) + elif self.type == PERF_RECORD_FORK: + # the sample_id timestamp is preferred to the one in the record + stuff = struct.unpack("IIIIQ", d) + (self.pid, self.ppid, self.tid, self.ptid, ignore_time) = stuff + elif self.type == PERF_RECORD_READ: + (self.pid, self.tid) = struct.unpack("ii", d[0:8]) + self.read = ReadFormat(self.event_attr.read_format) + d = self.read.unpack(d) + elif self.type == PERF_RECORD_SAMPLE: + assert False, "shouldn't reach here" + elif self.type == PERF_RECORD_MMAP2: + assert len(d) > 64, "missing filename" + stuff = struct.unpack("iiQQQIIQQII", d[0:64]) + (self.pid, self.tid, self.addr, self.len, self.pgoff, self.maj, self.min, self.ino, self.ino_generation, self.prot, self.flags) = stuff + self.filename = self.string(d[64:]) + elif self.type == PERF_RECORD_AUX: + # PERF_RECORD_AUX is generated by the kernel, to indicate that AUX data was produced. + (self.aux_offset, self.aux_size, self.flags) = struct.unpack("QQQ", d) + elif self.type == PERF_RECORD_ITRACE_START: + (self.pid, self.tid) = struct.unpack("II", d) + elif self.type == PERF_RECORD_LOST_SAMPLES: + self.lost_n = struct.unpack("Q", d)[0] + elif self.type == PERF_RECORD_SWITCH: + # PERF_RECORD_MISC_SWITCH_OUT applies here + pass + elif self.type == PERF_RECORD_SWITCH_CPU_WIDE: + stuff = struct.unpack("II", d) + (self.next_prev_pid, self.next_prev_tid) = stuff + elif self.type == PERF_RECORD_NAMESPACES: + (self.pid, self.tid, self.nr_namespaces) = struct.unpack("IIQ", d[:16]) + self.namespaces = [] + for i in range(0, self.nr_namespaces): + self.namespaces.append(struct.unpack("QQ", d[16+i*16:16+i*16+16])) + elif self.type == PERF_RECORD_KSYMBOL: + (self.addr, self.len, self.ksym_type, self.flags) = struct.unpack("QIHH", d[:16]) + self.name = self.string(d[16:]) + elif self.type == PERF_RECORD_BPF_EVENT: + (self.bpf_type, self.bpf_flags, self.bpf_id) = struct.unpack("HHI", d[:8]) + self.bpf_tag = d[8:16] + elif self.type == PERF_RECORD_CGROUP: + self.cgroup_id = struct.unpack("Q", d[:8])[0] + self.cgroup_name = self.string(d[8:]) + elif self.type == PERF_RECORD_TEXT_POKE: + (self.addr, self.old_len, self.new_len) = struct.unpack("QHH", d[:12]) + self.old_bytes = d[12:12+self.old_len] + self.new_bytes = d[12+self.old_len:12+self.old_len+self.new_len] + elif self.type < _PERF_RECORD_MAX_FROM_KERNEL: + # Unknown kernel (mmap buffer) record type to unpack. + # Maybe one added in a very recent kernel. + self.note("unknown kernel perf record type: %s" % str_PERF_RECORD(self.type)) + pass + else: + # unknown synthetic (perf.data) record type to unpack + pass + self.has_been_unpacked = True + return self diff --git a/linux_app/pmu_app/pyperf/pyperf/perf_attr.py b/linux_app/pmu_app/pyperf/pyperf/perf_attr.py new file mode 100644 index 00000000..a3d1b483 --- /dev/null +++ b/linux_app/pmu_app/pyperf/pyperf/perf_attr.py @@ -0,0 +1,454 @@ +# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# SPDX-License-Identifier : Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" +Encapsulate the perf_event_attr structure used by the +perf_event_open syscall and in perf.data. + +Python descriptors are used to make the structure look like a +plain C struct but with validity checking on the fields. + +There are two ways to create a PerfEventAttr: + + - with raw data, e.g. as read from perf.data: + + attr = PerfEventAttr(raw) + if attr.type == PERF_TYPE_HARDWARE ... + + - with fields, to set up a new event: + + attr = PerfEventAttr(type=PERF_TYPE_HARDWARE, ...) + perf_event_open(attr._raw ...) +""" + +from __future__ import print_function + +from pyperf.perf_enum import * + +import struct, os, sys, types, copy + +from pyperf.hexdump import print_hex_dump + +perf_attr_size_default = 112 + + +class _FieldBase(object): + def __init__(self): + pass + + def __get__(self, obj, type=None): + if not obj._is_valid(self.ix): + return None + return self.get_value(obj) + + def __set__(self, obj, value): + if value is None: + obj._set_valid(self.ix, False) + else: + assert self.epos <= obj.size + self.set_value(obj, value) + obj._set_valid(self.ix, True) + + +class _Field(_FieldBase): + def __init__(self, fmt, pos): + self.pos = pos + self.ix = pos * 8 + self.fmt = fmt + self.epos = pos + struct.calcsize(fmt) + + def get_value(self, obj): + return struct.unpack(self.fmt, obj._raw[self.pos:self.epos])[0] + + def set_value(self, obj, value): + struct.pack_into(self.fmt, obj._raw, self.pos, value) + + +def setbitof(s, b, n, v): + mask = 1 << (n&7) + b = b + (n // 8) + s[b] = (s[b] & ~mask) | ((v&1) << (n&7)) + + +class _Bit(_FieldBase): + def __init__(self, pos, n): + self.pos = pos + self.ix = pos*8 + n + self.n = n + self.byte = (self.pos + (self.n >> 3)) + self.epos = self.byte + 1 + + def get_value(self, obj): + return (obj._raw[self.byte] >> (self.n&7)) & 1 + + def set_value(self, obj, value): + setbitof(obj._raw, self.pos, self.n, value) + + +class _Bits(_FieldBase): + def __init__(self, fmt, pos, n, b): + self.pos = pos + self.ix = pos*8 + n + self.n = n + self.b = b + self.fmt = fmt + self.epos = pos + struct.calcsize(fmt) + + def get_value(self, obj): + x = struct.unpack(self.fmt, obj._raw[self.pos:self.epos])[0] + return (x >> self.n) & ((1< 0: + self.misc |= PERF_RECORD_MISC_KERNEL + self.addr = p.data_address + self.phys_addr = p.phys_address + self.weight = p.total_latency() - p.issue_latency() + self.t = hw_time_to_kernel_time(p.timestamp) + ds = 0 + if p.op.is_access(): + if not p.op.is_store(): + ds |= (PERF_MEM_OP_LOAD << PERF_MEM_OP_SHIFT) + if p.data_source == 0: + ds |= ((PERF_MEM_LVL_HIT|PERF_MEM_LVL_L1) << PERF_MEM_LVL_SHIFT) + elif p.data_source == 8: + ds |= ((PERF_MEM_LVL_HIT|PERF_MEM_LVL_L2) << PERF_MEM_LVL_SHIFT) + elif p.data_source == 11: + ds |= ((PERF_MEM_LVL_HIT|PERF_MEM_LVL_L3) << PERF_MEM_LVL_SHIFT) + elif p.data_source == 13: + ds |= (PERF_MEM_REMOTE_REMOTE << PERF_MEM_REMOTE_SHIFT) + elif p.data_source == 14: + ds |= ((PERF_MEM_LVL_HIT|PERF_MEM_LVL_LOC_RAM) << PERF_MEM_LVL_SHIFT) + else: + print("UNKNOWN LEVEL: %u" % p.data_source) + else: + ds |= (PERF_MEM_OP_STORE << PERF_MEM_OP_SHIFT) + if p.op.subclass_bit(1): # atomic, exclusive etc. + if p.op.subclass_bit(2) or p.op.subclass_bit(3): + ds |= (PERF_MEM_LOCK_LOCKED << PERF_MEM_LOCK_SHIFT) + self.data_src = ds + + +def arm_spe_records(r): + """ + From an AUXTRACE record conaining ARM SPE data, yield a series of SPERecords that behave like samples. + """ + assert r.type == PERF_RECORD_AUXTRACE and r.auxtrace_info_type == PERF_AUXTRACE_ARM_SPE, "expected AUX with ARM SPE data" + for p in arm_spe.Decoder().records(bytearray(r.aux_data)): + if p.op.is_access() and p.is_retired(): + yield SPERecord(p, pid=r.pid, cpu=r.cpu) + + +class AuxTraceHandlerArmSPE(AuxTraceHandler): + def handle_auxtrace_info(self, pd, r): + r.pmu_type = struct.unpack("Q", r.raw[16:24])[0] + assert pd.pmu_names[r.pmu_type].startswith("arm_spe") + + def report_auxtrace_info(self, r, reporter): + fields = [ + ("PMU Type", "%d") + ] + reporter.print_auxinfo_fields(r, fields, 19) + + def report_auxtrace(self, r, reporter): + dec = arm_spe.Decoder() + if False: + # Compact: print one SPE sample per line + for sr in dec.records(r.aux_data): + print(". %s" % str(sr)) + else: + # perf report -D: print one SPE packet per line + pos = 0 + for sp in dec.decode(r.aux_data): + print(". %08x: " % pos, end="") + pktp = sp.raw + for b in pktp: + print(" %02x" % b, end="") + if len(pktp) < 16: + print(" " * (16-len(pktp)), end="") + print(" %s" % str(sp), end="") + print() + pos += len(pktp) + + +register_auxtrace_handler(PERF_AUXTRACE_ARM_SPE, AuxTraceHandlerArmSPE()) + diff --git a/linux_app/pmu_app/pyperf/pyperf/perf_aux_cs_etm.py b/linux_app/pmu_app/pyperf/pyperf/perf_aux_cs_etm.py new file mode 100644 index 00000000..febdabd2 --- /dev/null +++ b/linux_app/pmu_app/pyperf/pyperf/perf_aux_cs_etm.py @@ -0,0 +1,311 @@ +# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# SPDX-License-Identifier : Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" +Decode the PERF_RECORD_AUXTRACE_INFO data for CS_ETM +""" + +from __future__ import print_function + +import struct, os, sys +import pyperf.perf_util as utils +import pyperf.perf_data as perf_data + +cs_etm_enabled = False +if os.path.isdir("./csdecode"): + sys.path.append("./csdecode") # TBD: locate the CoreSight decoder + import cs_decode, cs_decode_etm, cs_viewer_raw, cs_viewer_ds5, cs_viewer_profile, imagemap + cs_etm_enabled = True + +MAGIC_ETM3 = 0x3030303030303030 +MAGIC_ETM4 = 0x4040404040404040 +MAGIC_ETM5 = 0x5050505050505050 + +ETM_MAGICS = [MAGIC_ETM3, MAGIC_ETM4, MAGIC_ETM5] + + +class AuxInfoETMCPU: + """ + Base class for ETM configuration information for a single CPU. + """ + def __init__(self, cpu, magic): + self.cpu = cpu + self.magic = magic + self.regs = {} + + def __getitem__(self, name): + return self.regs[name] + + def __setitem__(self, name, value): + self.regs[name] = value + + def __str__(self): + s = "CPU #%u: %s [%s]" % (self.cpu, self.etm_version_str(), ', '.join([("%s=0x%x" % (rn, self.regs[rn])) for rn in self.regnames])) + return s + + +class AuxInfoETMCPU3(AuxInfoETMCPU): + """ + ETM configuration for a CPU with ETM 3.x. + """ + def __init__(self, cpu): + AuxInfoETMCPU.__init__(self, cpu, MAGIC_ETM3) + self.regnames = ["ETMCR", "ETMTRACEIDR", "ETMCCER", "ETMIDR"] + self.etm_version = 3 + + def atid(self): + return self["ETMTRACEIDR"] & 0x7f + + def etm_version_str(self): + return "ETMv3" + + +class AuxInfoETMCPU4(AuxInfoETMCPU): + """ + ETM configuration for a CPU with ETM 4.x. + """ + def __init__(self, cpu): + AuxInfoETMCPU.__init__(self, cpu, MAGIC_ETM4) + self.regnames = ["TRCCONFIGR", "TRCTRACEIDR", "TRCIDR0", "TRCIDR1", "TRCIDR2", "TRCIDR8", "TRCAUTHSTATUS"] + self.etm_version = 4 + + def atid(self): + return self["TRCTRACEIDR"] & 0x7f + + def use_devarch(self): + return (self["TRCIDR1"] & 0xff0) == 0xff0 + + def is_unformatted(self): + # TBD: this is quite wrong. The metadata should indicate whether the data in the buffer is unformatted. + # However, for the time being, data from ETMv4 is formatted while data from future trace is unformatted, + # and we can use TRCIDR1's major/minor version fields being 0xFF as an indicator of future trace. + if self.use_devarch(): + return True + return False + + def etm_version_str(self): + if not self.use_devarch(): + s = "ETMv4.%u" % ((self["TRCIDR1"] & 0x0f0) >> 4) + else: + s = "ETM-future" + return s + + +class AuxInfoETECPU(AuxInfoETMCPU): + """ + ETM configuration for a CPU with ETE. + """ + def __init__(self, cpu): + AuxInfoETMCPU.__init__(self, cpu, MAGIC_ETM5) + self.regnames = ["TRCCONFIGR", "TRCTRACEIDR", "TRCIDR0", "TRCIDR1", "TRCIDR2", "TRCIDR8", "TRCAUTHSTATUS", "TRCDEVARCH"] + self.etm_version = 5 + + def atid(self): + # TBD: should we fault calling this, since trace is unformatted? + return self["TRCTRACEIDR"] & 0x7f + + def is_unformatted(self): + # TBD: assume ETE is not being collected in a shared trace buffer + return True + + def etm_version_str(self): + return "ETEv%.u" % (self["TRCDEVARCH"] & 0xf) + + +class AuxInfoETM: + """ + Describe a system-wide trace configuration - the ETM configuration for each CPU. + In a heterogeneous (big.LITTLE) system, different CPUs might have different ETM versions. + """ + def __init__(self, raw=None, verbose=0): + self.cpu = {} # Info indexed by CPU + self.id_info = {} # Info indexed by ATB trace id + self.verbose = verbose + if raw is not None: + self.init_from_auxtrace_info(raw) + else: + self.init_from_local() + + def add_info(self, cpu_info): + """ + Add the info for a single CPU. The CPU number is already set in the info object. + """ + assert isinstance(cpu_info, AuxInfoETMCPU) + cpu = cpu_info.cpu + assert cpu not in self.cpu, "duplicate CPU number: %s" % cpu + self.cpu[cpu] = cpu_info + self.id_info[cpu_info.atid()] = cpu_info + + def init_from_auxtrace_info(self, raw): + """ + Construct the ETM trace metadata from the payload of a PERF_RECORD_AUXTRACE_INFO record. + The format is: + 0000: type = 70 (PERF_RECORD_AUXTRACE_INFO) + 0006: record size + 0008: aux type = 3 (PERF_AUXTRACE_CS_ETM) + 0010: version + 0018: n_cpus + 001c: pmu type, as defined by the kernel + 0020: snapshot + 0028: first CPU metadata, starts with 'magic' indicator + """ + (self.version, self.n_cpus, self.pmu_type, self.snapshot) = struct.unpack("QIIQ", raw[16:40]) + if self.verbose: + print("ETM metadata:") + print(" version: %u" % self.version) + print(" cpus: %u" % self.n_cpus) + print(" PMU type: %u" % self.pmu_type) + print(" snapshot: 0x%x" % self.snapshot) + pos = 40 + for c in range(0, self.n_cpus): + magic = struct.unpack("Q", raw[pos:pos+8])[0] + cpu = struct.unpack("Q", raw[pos+8:pos+16])[0] + if self.verbose: + print(" CPU #%u" % cpu) + print(" magic: 0x%016x" % magic) + pos = pos + 16 + if magic == MAGIC_ETM3: + cpu_info = AuxInfoETMCPU3(cpu) + elif magic == MAGIC_ETM4: + cpu_info = AuxInfoETMCPU4(cpu) + elif magic == MAGIC_ETM5: + cpu_info = AuxInfoETECPU(cpu) + else: + # If we get this for other than the first CPU, we probably had the wrong number of registers + assert False, "unknown ETM version for CPU #%u: 0x%x" % (cpu, magic) + break # not safe to continue from here - don't know number of fields + if self.version == 1: + n_regs = struct.unpack("Q", raw[pos:pos+8])[0] + pos = pos + 8 + else: + n_regs = len(cpu_info.regnames) + for fname in cpu_info.regnames[:n_regs]: + cpu_info[fname] = struct.unpack("Q", raw[pos:pos+8])[0] + if self.verbose: + print(" %s = %016x" % (fname, cpu_info[fname])) + pos = pos + 8 + # Check for trailing unknown registers + while pos <= (len(raw)-8) and struct.unpack("Q", raw[pos:pos+8])[0] not in ETM_MAGICS: + print("ETM: CPU #%u: ignoring unknown register: 0x%016x" % (cpu, struct.unpack("Q", raw[pos:pos+8])[0]), file=sys.stderr) + pos = pos + 8 + self.add_info(cpu_info) + assert pos == len(raw), "unexpected length of AUXTRACE_INFO: raw data %u bytes, expected %u bytes" % (len(raw), pos) + + def init_from_local(self): + """ + Construct the ETM trace metadata from the local sysfs. + """ + sysfs = "/sys/bus/event_source/devices/cs_etm" + self.version = 0 + self.pmu_type = utils.file_int(sysfs + "/type") + self.snapshot = None + self.n_cpus = 0 + for d in os.listdir(sysfs): + if d.startswith("cpu"): + try: + cpu = int(d[3:]) + cdir = sysfs + "/" + d + self.n_cpus += 1 + if os.path.exists(cdir + "/trcidr/trcidr0"): + ci = AuxInfoETMCPU4(cpu) + else: + ci = AuxInfoETMCPU3(cpu) + for rn in ci.regnames: + rl = rn.lower() + rv = None + try: + rv = utils.file_hex(cdir + "/trcidr/" + rl) + except IOError: + if rl in ["trcconfigr", "trctraceidr"]: + rl = rl[:-1] + try: + rv = utils.file_hex(cdir + "/mgmt/" + rl) + except IOError: + print("can't get reg for %s" % rl) + ci.regs[rn] = rv + except Exception: + continue + self.add_info(ci) + + def iter_cpu(self): + for c in sorted(self.cpu.keys()): + yield self.cpu[c] + + def print(self): + print("ETM configuration (pmu_type=%d)" % self.pmu_type) + for ci in self.iter_cpu(): + print(" %s" % ci) + + +class AuxTraceHandlerCSETM(perf_data.AuxTraceHandler): + def handle_auxtrace_info(self, pd, r): + e = AuxInfoETM(r.raw) + pd.auxtrace_info_cs_etm = e + + def report_auxtrace_info(self, r, reporter): + def padtabs(s): + ntabs = (31 - len(s)) // 8 + return "\t" + s + ("\t"*ntabs) + " " + print("%s%u" % (padtabs("Header version"), e.version)) + print("%s%x" % (padtabs("PMU type/num cpus"), ((e.pmu_type << 32) | e.n_cpus))) + print("%s%x" % (padtabs("Snapshot"), e.snapshot)) + for cpu_info in e.iter_cpu(): + print("%s%x" % (padtabs("Magic number"), cpu_info.magic)) + print("%s%u" % (padtabs("CPU"), cpu_info.cpu)) + for fname in cpu_info.regnames: + print("%s%x" % (padtabs(fname), cpu_info[fname])) + + def report_auxtrace(self, r, reporter): + if not cs_etm_enabled: + return + decoders = {} + viewer = cs_viewer_raw.viewer() + cs_decode_etm.default_verbose = 0 + images = imagemap.imagemap() + cs_decode_etm.default_map = images + for cpu_info in p.auxtrace_info_cs_etm.iter_cpu(): + config = cs_decode_etm.etm_config(arch=cs_decode_etm.ARCH_ETM4) + for cr in cpu_info.regnames: + config.set_etmv4_reg(cr, cpu_info[cr]) + decoders[cpu_info.atid()] = cs_decode_etm.decode_etm(config, cpu_info.atid(), viewer=viewer) + cs_decode.buffer_decode(r.aux_data, decoders) + + +perf_data.register_auxtrace_handler(perf_data.PERF_AUXTRACE_CS_ETM, AuxTraceHandlerCSETM()) + + +if __name__ == "__main__": + import argparse + parser = argparse.ArgumentParser(description="Manage ETM metadata in perf.data files") + parser.add_argument("-v", "--verbose", action="count", help="increase verbosity level") + parser.add_argument("-i", "--input", type=str, help="input perf.data file") + opts = parser.parse_args() + if opts.input: + import perf_data, hexdump + pd = perf_data.PerfData(opts.input) + for r in pd.records(): + if r.type == perf_data.PERF_RECORD_AUXTRACE_INFO: + if opts.verbose >= 2: + hexdump.print_hex_dump(r.raw, width=32, prefix=" ") + if r.auxtrace_info_type != perf_data.PERF_AUXTRACE_CS_ETM: + print("AUXTRACE_INFO is not ETM") + sys.exit() + auxinfo = AuxInfoETM(raw=r.raw, verbose=opts.verbose) + auxinfo.print() + else: + # Construct and show AuxInfo from the local sysfs + auxinfo = AuxInfoETM(verbose=opts.verbose) + auxinfo.print() + diff --git a/linux_app/pmu_app/pyperf/pyperf/perf_buildid.py b/linux_app/pmu_app/pyperf/pyperf/perf_buildid.py new file mode 100644 index 00000000..66726b2a --- /dev/null +++ b/linux_app/pmu_app/pyperf/pyperf/perf_buildid.py @@ -0,0 +1,396 @@ +# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# SPDX-License-Identifier : Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" +Manage the perf tool buildid cache in ~/.debug. + +This module doesn't deal directly with perf.data files. +""" + +from __future__ import print_function + +import os, sys, struct, subprocess, shutil + +import pyperf.elf as elf + + +def _home_dir(): + hd = os.path.expanduser("~") + assert os.path.isdir(hd), "missing home directory: %s" % hd + return hd + + +class BuildID(object): + """ + A unique 20-byte build id, possibly with a filename. + """ + def __init__(self, num, filename=None): + self.filename = filename + if isinstance(num, str): + # For Python2, this might be bytes(): a binary string or a text string. + if len(num) == 20: + self.id = _bytearray_int(bytearray(num)) + else: + self.id = int(num, 16) + elif isinstance(num, bytearray) or isinstance(num, bytes): + self.id = _bytearray_int(num) + elif isinstance(num, int) or isinstance(num, long): + self.id = num + else: + assert False, "invalid type '%s' for %s" % (type(num), num) + + def is_valid(self): + return self.filename is not None and self == file_buildid(self.filename) + + def __eq__(self, x): + return x is not None and self.id == x.id + + def __str__(self): + # The 40-character string + return "%040x" % self.id + + def index0(self): + return "%02x" % (self.id >> 152) + + def index1(self): + return str(self)[2:] + + def default(self, obj): + # Encode as JSON + return str(obj) + + +NT_GNU_BUILD_ID = 3 + +KALLSYMS = "[kernel.kallsyms]" + +def _bytearray_int(d): + n = 0 + if not isinstance(d, bytearray): + d = bytearray(d) + for x in d: + n = (n << 8) | x + return n + + +def kernel_buildid(): + """ + Get the build id from the current kernel. + """ + with open("/sys/kernel/notes", "rb") as f: + d = f.read() + # 32-bit fields even on 64-bit kernels + while d: + (namesz, descsz, type) = struct.unpack("III", d[0:12]) + if namesz == 4 and descsz == 20 and type == NT_GNU_BUILD_ID and d[12:15] == b"GNU": + id = _bytearray_int(d[16:36]) + return BuildID(id, filename=KALLSYMS) + d = d[12+namesz+descsz:] + return None + + +def file_buildid(fn): + """ + Get the build identifier for an ELF file. + + We can either invoke readelf, or read the file directly. + """ + if fn == KALLSYMS: + return kernel_buildid() + if not os.path.isfile(fn): + return None + try: + e = elf.ELF(fn) + bid = e.build_id() + if bid is not None: + return BuildID(bid, filename=fn) + except elf.NotELF: + # Unexpected... might be a perf.data where /bin/xxx is a binary, but on our system it's a script + #print("%s: not ELF" % fn, file=sys.stderr) + return None + except IOError: + print("%s: reading build id failed, trying readelf" % (fn), file=sys.stderr) + p = subprocess.Popen(["readelf", "-n", fn], stdout=subprocess.PIPE, stderr=subprocess.PIPE, universal_newlines=True) + (out, err) = p.communicate() + if p.returncode == 0: + for ln in out.split('\n'): + if ln.startswith(" Build ID:"): + return BuildID(ln[14:54], filename=fn) + else: + print("%s: readelf failed" % (fn), file=sys.stderr) + return None + + +class BuildIDCacheRO(object): + """ + Read-only methods of the buildid cache. + """ + def __init__(self, dir=None): + if dir is None: + dir = os.path.join(_home_dir(), ".debug") + self.dir = dir + self.idx = os.path.join(self.dir, ".build-id") + + def __str__(self): + return "buildid cache in %s" % self.idx + + def __repr__(self): + return 'BuildIDCache("%s")' % self.dir + + def exists(self): + return os.path.exists(self.idx) + + def id_dir(self, id): + return os.path.join(self.idx, id.index0(), id.index1()) + + def id_files(self, id): + """ + Return the list of unqualified filenames cached for an id. Often ["elf"]. + """ + d = self.id_dir(id) + if os.path.isdir(d): + return list(os.listdir(d)) + else: + return None + + def id_file(self, id): + """ + Return the single unqualified filename for an id, if there is exactly one. + """ + files = self.id_files(id) + if files is not None and len(files) == 1: + return files[0] + return None + + def contains_id(self, id): + # Return true if the cache contains the given build id, i.e. the build id directory exists. + # We assume this directory contains a copy of the ELF file (usually, but not always, called "elf") + return os.path.exists(self.id_dir(id)) + + def contains_file(self, fn): + # Return true if the cache has a valid copy of the current version of a given file + assert os.path.exists(fn), "cache contains check needs file to be valid: %s" % fn + return self.contains_id(file_buildid(fn)) + + def id_cache_contents(self, id, name=None): + # Return the full name of a specific cached file for an id - usually "elf", "vdso" or "kallsyms" + if name is None: + name = self.id_file(id) + if name is None: + return None + d = os.path.join(self.id_dir(id), name) + if not os.path.isfile(d): + d = None + return d + + def id_matching_file(self, id, filename, name=None): + # Return the full name of a file that has the given build id. + # This is either a file in the cache (if cached) or on disk (if it has the correct build id) + d = self.id_cache_contents(id, name=name) + if d is None and filename is not None: + fid = file_buildid(filename) + if id == fid: + d = filename + return d + + def list(self): + # List the buildid cache contents, by id + if not self.exists(): + return + # List the top-level 2-digit buildid prefixes + for d0r in sorted(os.listdir(self.idx)): + d0 = os.path.join(self.idx, d0r) + for d1r in sorted(os.listdir(d0)): + d1 = os.path.join(d0, d1r) + bifn = os.readlink(d1) + # The link target is e.g. "../../bin/ls" meaning "~/.debug/bin/ls" + if bifn.startswith("../../"): + bifn = bifn[5:] + elif bifn.startswith(self.dir + os.sep): + bifn = bifn[len(self.dir):] + else: + assert False, "unexpected link target: %s" % bifn + fn = os.path.dirname(bifn) + if fn.startswith("/[") and fn.endswith("]"): + fn = fn[1:] # e.g. [kernel.kallsyms] or [vdso] + buildid = BuildID(os.path.basename(bifn), filename=fn) + yield buildid + + +class BuildIDCache(BuildIDCacheRO): + """ + A cached mapping of buildids to files, as stored in ~/.debug + """ + def __init__(self, dir=None): + BuildIDCacheRO.__init__(self, dir) + + def create(self): + if not self.exists(): + os.mkdir(self.dir) + os.mkdir(self.idx) + + def add_file(self, fn, force=False, verbose=False): + # To add an entry, we must find the build-id, add a path under .debug, + # copy the file to 'elf' and add a link in .build-id. + # The file might already be in cache, under the same or a different build id. + # Exceptionally, an entry for this build id might exist, but with different contents - + # e.g. stripped vs. non-stripped versions of a binary. + assert os.path.isfile(fn), "missing file: %s" % fn + fn = os.path.abspath(fn) + id = file_buildid(fn) + if self.contains_id(id): + if verbose: + print("cache already contains %s %s" % (fn, id)) + if not force: + return False + cp = self.dir + fn # not join: "~/.debug"+"/bin/ls" -> "~/.debug/bin/ls" + if not os.path.exists(cp): + os.makedirs(cp) + ci = os.path.join(cp, str(id)) + if not os.path.exists(ci): + os.mkdir(ci) # 'contains' check will likely mean this doesn't exist + elf = os.path.join(ci, "elf") + try: + shutil.copyfile(fn, elf) + except shutil.Error as e: + # SameFileError: already in the cache with identical contents + print("Couldn't copy file: %s" % (e), file=sys.stderr) + pass + # Make the symbolic link + d0 = os.path.join(self.idx, id.index0()) + if not os.path.exists(d0): + os.mkdir(d0) + d1 = os.path.join(d0, id.index1()) # The link name + ci = os.path.join("../.." + fn, str(id)) + if os.path.exists(d1): + # Unusual, but might happen if we force update, or replace a stripped binary + # with the non-stripped version of the same binary (same build id). + os.remove(d1) + os.symlink(ci, d1) + return True + + def remove_file(self, fn, force=False, verbose=False): + """ + Remove an entry with the buildid of the specified file. I.e. the real file exists, + we get its build-id, and we remove that build-id entry from the cache. + """ + # To remove an entry, we must remove the path under .debug and remove the link in .build-id. + assert os.path.isfile(fn), "missing file: %s" % fn + fn = os.path.abspath(fn) + id = file_buildid(fn) + if not self.contains_id(id): + if verbose: + print("cache does not contain %s %s" % (fn, id)) + if not force: + return False + cp = self.dir + fn # not join + ci = os.path.join(cp, str(id)) + # remove the link + d1 = os.path.join(self.idx, id.index0(), id.index1()) + if os.path.exists(d1): + assert os.path.islink(d1), "expected symbolic link: %s" % d1 + assert d1.startswith(self.dir) + os.remove(d1) + # remove the id-specific subdirectory under the filename path + if os.path.exists(ci): + assert ci.startswith(self.dir) + shutil.rmtree(ci) + # This may leave the bare name e.g. "~/.debug/bin/ls" with no ids. + return True + + def purge_file(self, fn, verbose=False): + # Remove all cached files of a given name. + n = 0 + fn = os.path.abspath(fn) + cp = self.dir + fn # not join + if not os.path.exists(cp): + if verbose: + print("cache does not contain any %s" % (fn)) + return 0 + for id in os.listdir(cp): + ci = os.path.join(cp, id) + ix0 = id[0:2] + ix1 = id[2:40] + d1 = os.path.join(self.idx, ix0, ix1) + if verbose: + print("removing %s %s" % (fn, id)) + assert os.path.islink(d1), "expected symbolic link: %s" % d1 + assert d1.startswith(self.dir) + os.remove(d1) + n += 1 + assert cp.startswith(self.dir) + shutil.rmtree(cp) + return n + + def clear(self): + # Clear the entire cache. + shutil.rmtree(self.dir) + + +def self_test(): + kb = kernel_buildid() + print("Kernel build id: %s" % kb) + + +if __name__ == "__main__": + import argparse + parser = argparse.ArgumentParser(description="build-id cache") + parser.add_argument("--list", "-l", action="store_true", help="list valid entries in cache") + parser.add_argument("--list-all", action="store_true", help="list all entries in cache") + parser.add_argument("--add", "-a", type=str, help="add file to cache") + parser.add_argument("--remove", "-r", type=str, help="remove current cached copy of file") + parser.add_argument("--update", "-u", type=str, help="update copy of file") + parser.add_argument("--purge", "-p", type=str, help="purge files by name") + parser.add_argument("--purge-all", "-P", action="store_true", help="purge all files") + parser.add_argument("--force", action="store_true", help="force add even if in index") + parser.add_argument("--home", type=str, default=None, help="location of buildid cache") + parser.add_argument("--verbose", "-v", action="store_true", help="print helpful messages") + parser.add_argument("--test", action="store_true", help="run self-tests") + opts = parser.parse_args() + B = BuildIDCache(opts.home) + if opts.test: + self_test() + if opts.list or opts.list_all: + B = BuildIDCacheRO(opts.home) + if not B.exists(): + print("%s: buildid cache does not exist" % B.idx) + n_invalid = 0 + for id in B.list(): + is_valid = id.is_valid() + if not is_valid: + n_invalid += 1 + if is_valid or opts.list_all: + print("%s %s" % (id, id.filename), end="") + if not is_valid: + print(" (invalid)", end="") + #print(" %s" % str(B.id_files(id)), end="") + print() + elif opts.verbose: + print("%s %s != %s" % (id, id.filename, file_buildid(id.filename))) + if n_invalid > 0 and not opts.list_all: + print("%s: %u invalid entries not shown; use --list-all to list" % (B.idx, n_invalid)) + elif opts.add: + B.add_file(opts.add, force=opts.force, verbose=opts.verbose) + elif opts.update: + # Unclear how this differs from --add --force + # See https://lore.kernel.org/lkml/20150211145742.GI24251@kernel.org/ + B.add_file(opts.add, force=True, verbose=opts.verbose) + elif opts.remove: + B.remove_file(opts.remove, force=opts.force, verbose=opts.verbose) + elif opts.purge: + B.purge_file(opts.purge, verbose=opts.verbose) + elif opts.purge_all: + B.clear() + diff --git a/linux_app/pmu_app/pyperf/pyperf/perf_data.py b/linux_app/pmu_app/pyperf/pyperf/perf_data.py new file mode 100644 index 00000000..2162fd3d --- /dev/null +++ b/linux_app/pmu_app/pyperf/pyperf/perf_data.py @@ -0,0 +1,1576 @@ +# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# SPDX-License-Identifier : Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" +Parse perf.data file. + +perf.data is created by "perf record". Much (but not all) of the format is +determined by the records returned from the perf_event_open syscall, +and which we manage in the perf_abi module. + +This module defines a PerfData object that enscapsulates the various structures +within perf.data. +""" + +from __future__ import print_function + +from pyperf.perf_enum import * +from pyperf.perf_attr import * +from pyperf.perf_abi import * +import pyperf.perf_buildid as perf_buildid + +from pyperf.hexdump import print_hex_dump +import pyperf.datamap as datamap + +import os, sys, struct, time, copy, platform + + +PERF_MAGIC = struct.unpack("Q", b"PERFILE2")[0] + + +# perf.data begins with a set of headers. +# We believe there is at most one header for a given type. +# These aren't enumerated in a public header. See tools/perf/util.h. +HEADER_TRACING_DATA = 1 +HEADER_BUILD_ID = 2 +HEADER_HOSTNAME = 3 +HEADER_OSRELEASE = 4 +HEADER_VERSION = 5 +HEADER_ARCH = 6 +HEADER_NRCPUS = 7 +HEADER_CPUDESC = 8 +HEADER_CPUID = 9 +HEADER_TOTAL_MEM = 10 +HEADER_CMDLINE = 11 +HEADER_EVENT_DESC = 12 +HEADER_CPU_TOPOLOGY = 13 +HEADER_NUMA_TOPOLOGY = 14 +HEADER_BRANCH_STACK = 15 +HEADER_PMU_MAPPINGS = 16 +HEADER_GROUP_DESC = 17 +HEADER_AUXTRACE = 18 +HEADER_STAT = 19 +HEADER_CACHE = 20 +HEADER_SAMPLE_TIME = 21 +HEADER_MEM_TOPOLOGY = 22 +HEADER_CLOCKID = 23 +HEADER_DIR_FORMAT = 24 +HEADER_BPF_PROG_INFO = 25 +HEADER_BPF_BTF = 26 +HEADER_COMPRESSED = 27 +HEADER_CPU_PMU_CAPS = 28 +HEADER_CLOCK_DATA = 29 + +HEADER_MAX = 128 + + +# After the headers, perf.data has records, generally collected from perf_event_open. +# Record types are indicated in the record header. +# The following special (synthetic) PERF_RECORD types are used only in perf.data. +FIRST_SYNTHETIC_PERF_RECORD = 64 +PERF_RECORD_HEADER_ATTR = 64 +PERF_RECORD_HEADER_EVENT_TYPE = 65 +PERF_RECORD_HEADER_TRACING_DATA = 66 +PERF_RECORD_HEADER_BUILD_ID = 67 +PERF_RECORD_FINISHED_ROUND = 68 +PERF_RECORD_ID_INDEX = 69 +PERF_RECORD_AUXTRACE_INFO = 70 +PERF_RECORD_AUXTRACE = 71 +PERF_RECORD_AUXTRACE_ERROR = 72 +PERF_RECORD_THREAD_MAP = 73 +PERF_RECORD_CPU_MAP = 74 +PERF_RECORD_STAT_CONFIG = 75 +PERF_RECORD_STAT = 76 +PERF_RECORD_STAT_ROUND = 77 +PERF_RECORD_EVENT_UPDATE = 78 +PERF_RECORD_TIME_CONV = 79 +PERF_RECORD_HEADER_FEATURE = 80 # subheaders when streaming +PERF_RECORD_COMPRESSED = 81 + +PERF_RECORD_MAX = 82 + + +# Compression types +PERF_COMP_NONE = 0 +PERF_COMP_ZSTD = 1 # Zstd - when libstd-dev is present + + +# Type field of synthetic PERF_RECORD_AUXTRACE_INFO +PERF_AUXTRACE_UNKNOWN = 0 # Unknown trace format +PERF_AUXTRACE_INTEL_PT = 1 # Processor Trace +PERF_AUXTRACE_INTEL_BTS = 2 # Branch Trace Store (not generally used) +PERF_AUXTRACE_CS_ETM = 3 # Arm CoreSight ETM trace +PERF_AUXTRACE_ARM_SPE = 4 # Arm Statistical Profiling Extension +PERF_AUXTRACE_S390_CPUMSF = 5 # S/390 Measurement Sampling Facility + + +class AuxTraceHandler: + def __init__(self): + pass + + def handle_auxtrace_info(self, perf_data, rec): + pass + + def report_auxtrace_info(self, rec, reporter): + pass + + def report_auxtrace(self, rec, reporter): + pass + + +auxtrace_handlers = {} # indexed by PERF_AUXTRACE... + +def register_auxtrace_handler(auxtype, handler): + auxtrace_handlers[auxtype] = handler + + +STROF_HEADER = {} +PERF_DATA_RECORD = {} +for s in list(globals()): + if s.startswith("HEADER_") and s != "HEADER_MAX": + STROF_HEADER[globals()[s]] = s + if s.startswith("PERF_RECORD_") and s != "PERF_RECORD_MAX": + PERF_DATA_RECORD[globals()[s]] = s + + +def record_type_str(type, short=False): + if type < FIRST_SYNTHETIC_PERF_RECORD: + rname = str_PERF_RECORD(type, short=False) + elif type in PERF_DATA_RECORD: + rname = PERF_DATA_RECORD[type] + else: + rname = "PERF_RECORD_%u??" % type + if short: + rname = rname[12:] + return rname + + +assert record_type_str(1) == "PERF_RECORD_MMAP" +assert record_type_str(71) == "PERF_RECORD_AUXTRACE" + + +def clean_str(s): + # Strings in perf.data may be padded, with the size including the padding. + # But sometimes the padding appears to include junk (see strings in + # HEADER_BUILD_ID for example). + # Given something like "hello\0junk\0\0\0" return "hello". + ix = s.find(b'\0') + if ix >= 0: + s = s[:ix] + return s.decode() + + +def header_type_name(n, short=False): + if n in STROF_HEADER: + s = STROF_HEADER[n] + else: + s = "HEADER_%u" % n + if short: + s = s[7:] + return s + + +def header_from_string(s): + s = s.encode() + b'\0' + while (len(s) % 4) != 0: + s += b'\0' + n = len(s) + return struct.pack("I", n) + s + + +def perf_header_string(d): + # return a string and the remaining data + len = struct.unpack("I", d[0:4])[0] + s = clean_str(d[4:4+len]) + return (s, d[4+len:]) + + +def perf_header_string_only(d): + (s, d) = perf_header_string(d) + assert not d + return s + + +def perf_header_string_list(d): + argc = struct.unpack("I", d[0:4])[0] + argv = [] + d = d[4:] + for i in range(0, argc): + (s, d) = perf_header_string(d) + argv.append(s) + return (argv, d) + +def header_from_string_list(sl): + b = struct.pack("I", len(sl)) + for arg in sl: + b += header_from_string(arg) + return b + + +class PerfFileSection: + """ + PerfFileSection is a contiguous area within a perf.data file. + It may be one of the headers, or some other kind of section. + A section descriptor is a pair of doublewords, outside the section itself, + that locates the section. + Three sections are described in the header: + - an array of perf_event_attr's + - the section containing all the data records + - event types + """ + def __init__(self, perf_data, descriptor_offset=None, data=None): + assert isinstance(perf_data, PerfData) + self.descriptor_offset = descriptor_offset + self.perf_data = perf_data # owning object + self.cached_data = data + + def read_descriptor(self): + h = self.perf_data.readat(self.descriptor_offset, 16) + (self.offset, self.size) = struct.unpack("QQ", h) + return self + + def write_descriptor(self): + desc = struct.pack("QQ", self.offset, self.size) + self.perf_data.writeat(self.descriptor_offset, desc) + + def data(self): + if self.cached_data is None: + self.read_descriptor() + self.cached_data = self.perf_data.readat(self.offset, self.size) + return self.cached_data + + def write(self, offset): + assert self.cached_data is not None + self.offset = offset + self.size = len(self.cached_data) + self.write_descriptor() + self.perf_data.writeat(offset, self.cached_data) + return offset + self.size + + def end_offset(self): + return self.offset + self.size + + def set_data(self, data): + self.cached_data = data + return self + + def REMOVETHISstring(self): + # return contents as a string - only valid for some header types (not checked here) + s = perf_header_string(self.data())[0] + return s + + def __str__(self): + return "[0x%x..0x%x] (%u bytes)" % (self.offset, self.offset+self.size, self.size) + + +class PerfDataEventDesc: + """ + An event description, as recorded in a perf.data file. + Generally this will correspond to several perf_event_open events, + one per CPU, perhaps one per thread. + """ + def __init__(self, attr=None, name=None, ids=None, index=None): + self.index = index # descriptor index in this perf.data file, e.g. 0, 1, etc. + self.ids = ids # array of event identifiers for the perf_event_open events (e.g. one per CPU) + self.name = name # descriptive name, as recorded in perf.data + self.attr = attr # PerfEventAttr object + + def id_index(self, id): + # Go from an event identifier that's unique in this perf session (across all event types), + # to a zero-based event index within this descriptor. + # E.g. if the event has ids [140,141,142] then id=141 gives us index=1. + if self.ids is not None: + return self.ids.index(id) + else: + return id # TBD: assume it's zero-based + + def __str__(self): + if self.name is not None: + namestr = self.name + else: + namestr = "" + s = "#%u: %s %s" % (self.index, namestr, self.attr) + if self.ids is not None: + s += " (%u ids)" % (len(self.ids)) + else: + s += " (no ids!)" + return s + + +class PerfDataRecord(PerfRecord): + """ + A record read in a perf.data file. This is a superset of the + type of records found in a perf_event_open mmap buffer. + """ + def __init__(self, *x, **k): + self.file = k["file"] + del k["file"] + if "file_offset" in k: + self.file_offset = k["file_offset"] + del k["file_offset"] + else: + # from a PERF_RECORD_COMPRESSED? + self.file_offset = None + PerfRecord.__init__(self, *x, **k) + + def __str__(self): + if self.file_offset is not None: + s = "@0x%x" % (self.file_offset) + else: + s = "@?" + return s + " " + record_type_str(self.type) + " " + self.payload_str() + + def payload_str(self): + if self.type == PERF_RECORD_AUXTRACE: + return "idx=%u offset=0x%x size=0x%x" % (self.idx, self.auxtrace_offset, self.auxtrace_size) + else: + return PerfRecord.payload_str(self) + + def is_aux(self, typ=None): + return self.type == PERF_RECORD_AUXTRACE and (typ is None or self.auxtrace_info_type == typ) + + def aux_data_segment(self): + # A PERF_RECORD_AUX record is generated by the kernel and describes a segment of data in an AUX buffer. + # Retrieve the actual data. + assert self.type == PERF_RECORD_AUX + self.unpack() + if self.aux_size == 0: + # Seen from the kernel; perf will not create an AUXTRACE record in this case + return b"" + for r in self.file.auxtrace_buffers(idx=self.idx): + if self.aux_offset >= r.auxtrace_offset and (self.aux_offset+self.aux_size) <= (r.auxtrace_offset+r.auxtrace_size): + self.aux_data = self.file.readat(r.auxtrace_file_offset+(self.aux_offset-r.auxtrace_offset), self.aux_size) + return self.aux_data + assert False, "can't find AUXTRACE buffer for AUX: %s" % self + + def aux_data_segments(self): + # For an AUXTRACE record, return the buffer segments as described by PERF_RECORD_AUX records. + # There may be multiple segments for a single AUXTRACE buffer. + # We return them as tuples: + # (PERF_RECORD_AUX record, data) + assert False, "don't call this function, it's broken" + assert self.is_aux() and self.aux_data is not None, "AUXTRACE data is not available" + for ar in self.aux_records: + offset_in_buffer = ar.aux_offset - self.auxtrace_offset + assert 0 <= offset_in_buffer and (offset_in_buffer+ar.aux_size) <= self.auxtrace_size, "%s: bad AUX offset: 0x%x+%x in %x..%x" % (ar, ar.aux_offset, ar.aux_size, self.auxtrace_offset, self.auxtrace_offset+self.auxtrace_size) + if False: + print("offset: %x..%x" % (offset_in_buffer, offset_in_buffer+ar.aux_size)) + data = self.aux_data[offset_in_buffer:offset_in_buffer+ar.aux_size] + yield (ar, data) + + +class PerfData: + """ + A PerfData object represents the contents of a perf.data file. + + perf.data consists of + - a header (about 200 bytes) + - a section describing the events in the data + - a data section, which can be huge + - sub-headers describing the data and environment + The format supports reading the data as a stream, e.g. "perf record | perf report". + So the data is not dependent on the headers. + """ + def __init__(self, fn=None, fd=None, debug=False, buildid_cache=""): + self.file_is_valid = False + self.fn = fn + self.perf_data_version = None + self.set_buildid_cache(buildid_cache) + self.f = fd + self.debug = debug # print helpful diagnostics when reading + self.header_section = {} # Header type -> PerfFileSection + self.section_data = None + self.flags = 0 + self.compression_type = PERF_COMP_NONE + self.attr_entry_size = None + self.pmu_names = {} # type -> name + self.pmu_types = {} # name -> type + self.default_event_attr = None + self.event_index = {} # event id (per cpu) to event number + self.event_attrs = [] # PerfEventAttr, by event number + self.event_descs = [] # event descriptors, by event number + self.aux_event = None # PerfDataEventDesc for the event owning AUX records + self.build_id_map = {} # (pid, filename) -> build id + self.kcore_dir = None + self.auxtrace_info_type = None + self.auxtrace_buffer_cache = None + # Map the section descriptors. This doesn't read the actual descriptors. + self.section_attr = PerfFileSection(self, 24) # Section containing some number of perf_event_attr's + self.section_data = PerfFileSection(self, 40) + self.section_event_types = PerfFileSection(self, 56) + if fn is not None: + self.open_and_read_header(fn) + + def open_and_read_header(self, fn): + self.datamap = datamap.DataMap() + if fn == "-": + if self.f is None: + self.f = sys.stdin + self.is_pipe_mode = True + self.file_size = None + self.datatop = None + else: + assert self.f is None + if os.path.isdir(fn): + # It's a directory containing "data" and "kcore_dir/{kcore,kallsyms,modules}" + self.kcore_dir = os.path.join(fn,"kcore_dir") + assert os.path.isdir(self.kcore_dir), "%s: expected kcore_dir subdirectory" % fn + fn = os.path.join(fn,"data") + self.f = open(fn, "rb") + self.is_pipe_mode = False + self.file_size = os.path.getsize(fn) + self.datatop = self.datamap.add(0, self.file_size, fn) + self.fn = fn + self.is_writing = False + if self.debug: + print("perf.data in %s..." % self.fn) + h = self.f.read(16) + assert len(h) >= 16, "%s: file is empty" % fn + (magic, hsize) = struct.unpack("QQ", h) + # TBD: opposite endianness + assert magic == PERF_MAGIC, "%s: header magic is 0x%x, expected 0x%x" % (fn, magic, PERF_MAGIC) + if self.debug: + print(" header size 0x%x" % hsize) # typically 104 bytes for perf.data on disk + # when reading stream data, we get an empty (16-byte) header, + # and other information is communicated via records. + if hsize == 16: + self.file_is_valid = True # valid because it's legitimate in pipe reading mode + return + h = h + self.f.read(hsize-16) + self.datamap.add(0, hsize, "header") + # Size of an entry in the attribute section: 'struct perf_event_attr' plus 16-byte descriptor for the ids. + self.attr_entry_size = struct.unpack("Q", h[16:24])[0] + self.section_attr.read_descriptor() + if (self.section_attr.size % self.attr_entry_size) != 0: + print("%s: attribute section %s is not a multiple of attribute size %u" % (self.fn, self.section_attr, self.attr_entry_size), file=sys.stderr) + self.section_data.read_descriptor() + if self.section_data.size == 0: + print("%s: data section has size zero; capture session may have been improperly terminated" % (self.fn), file=sys.stderr) + if self.section_attr.offset <= self.section_data.offset and self.section_attr.end_offset() > self.section_data.offset: + print("%s: attribute section %s overlaps data section %s" % (self.fn, self.section_attr, self.section_data), file=sys.stderr) + self.section_event_types.read_descriptor() + self.datamap.add(self.section_attr.offset, self.section_attr.size, "attr (%u-byte entries)" % (self.attr_entry_size)) + self.datamap.add(self.section_data.offset, self.section_data.size, "data") + self.datamap.add(self.section_event_types.offset, self.section_event_types.size, "events") + # TBD there might be more than 2 flags doublewords + (flags, flags1a) = struct.unpack("QQ", h[72:88]) + self.flags = flags | (flags1a << 64) + self.n_events = 0 + if self.debug: + print(" attr: %s (attr entry size %u)" % (self.section_attr, self.attr_entry_size)) + print(" data: %s" % self.section_data) + print(" event_types: %s" % self.section_event_types) + print(" flags: 0x%x" % self.flags) + print(" headers:", end="") + for i in range(0, 128): + if self.has_header(i): + print(" %s" % header_type_name(i, short=True), end="") + print() + if (self.header_descriptor_offset() + (self.n_headers()*16)) > self.file_size: + print("%s: header descriptors incompletely written, cannot read file" % (self.fn), file=sys.stderr) + return + # Read all the headers, populating various metadata about this perf capture. + # HEADER_EVENT_DESC is the standard way of describing events. + for (type, hsect) in self.headers(): + self.header_section[type] = hsect + self.process_header(type, hsect.data()) + for (pid, buildid, filename) in self.build_ids(): + self.build_id_map[(pid, filename)] = buildid + if False: + print("Build id map:") + for (pid, filename) in self.build_id_map.keys(): + print(" %-30s %5d %s" % (self.build_id_map[(pid, filename)], pid, filename)) + sys.exit() + for (name, type) in self.pmu_mappings(): + self.pmu_names[type] = name + self.pmu_types[name] = type + if self.section_attr.size > 0: + # older way of specifying events + assert (self.section_attr.size % self.attr_entry_size) == 0, "unexpected attribute section size %u for %u-byte attribute entries" % (self.section_attr.size, self.attr_entry_size) + attr_n_events = self.section_attr.size // self.attr_entry_size + if self.debug: + print("%s: attributes section has %u events" % (self.fn, attr_n_events), file=sys.stderr) + already_got_events = (self.n_events > 0) + if already_got_events: + if self.debug: + print("%s: already got %u events from HEADER_EVENT_DESC" % (self.fn, self.n_events), file=sys.stderr) + if False and already_got_events: + # already had some events from a header + assert self.n_events == attr_n_events, "mismatch in number of events: %u vs. %u" % (self.n_events, attr_n_events) + if False: + print("already got %u events:" % self.n_events, file=sys.stderr) + for ed in self.event_descs: + print(" %s" % ed.attr, file=sys.stderr) + attr_data = self.section_attr.data() + pos = 0 + for i in range(0, attr_n_events): + this_attr_size = struct.unpack("I", attr_data[pos+4:pos+8])[0] + assert this_attr_size >= 32 and this_attr_size < 256, "invalid attribute size: %u" % this_attr_size + ea_raw = attr_data[pos:pos+this_attr_size] + ea = PerfEventAttr(ea_raw) + if (ea.size + 16) != self.attr_entry_size: + print("%s: mismatch in attribute size: attribute entries are %u (%u-byte descriptors) but %u-byte attribute in section" % (self.fn, self.attr_entry_size, self.attr_entry_size-16, ea.size), file=sys.stderr) + # regardless of the size in the structure, the spacing is set by the global size - + # either the one from the perf.data header, or the one from the HEADER_EVENT_DESC header. + pos = pos + (self.attr_entry_size - 16) + if not already_got_events: + self.add_event(ea, ids=None) + else: + if ea != self.event_attrs[i]: + print("%s: event descriptor #%u: mismatch between attributes section and HEADER_EVENT_DESC:\n %s\nvs.\n %s" % (self.fn, i, ea, self.event_attrs[i]), file=sys.stderr) + (idso, idss) = struct.unpack("QQ", attr_data[pos:pos+16]) + self.datamap.add(idso, idss, "ids for event #%u" % i) + pos = pos + 16 # skip the ids + if self.debug: + print(" events:") + for evd in self.events(): + print(" %s" % evd.attr) + self.file_is_valid = True + + def is_valid(self): + return self.file_is_valid + + def is_compressed(self): + return self.compression_type != PERF_COMP_NONE + + def open_and_write_header(self, fn): + assert self.f is None + self.fn = fn + if fn == "-": + self.f = sys.stdout + self.is_pipe_mode = True + else: + self.f = open(fn, "wb") + self.is_pipe_mode = False + self.is_writing = True + self.update_environment_headers() + # TBD: write header and event description, then leave file position for user to write records + # into the data section. Sub-headers are written at the end. + self.write_headers_at_end = not self.is_pipe_mode + #self.write_headers_at_end = False + self.need_to_write_headers = self.write_headers_at_end + if self.is_pipe_mode: + # Write a minimal header followed by FEATURE records + self.f.write(struct.pack("QQ", PERF_MAGIC, 16)) + else: + # Write a full header, followed by the event section + if self.attr_entry_size is None: + self.attr_entry_size = perf_attr_size_default + 16 + flags = 0 + if self.write_headers_at_end: + for i in range(0, 128): + if i in self.header_section: + flags |= (1 << i) + flags1a = flags >> 64 + flags = flags & 0xffffffffffffffff + # descriptors will be updated when sections are written + h = struct.pack("QQQQQQQQQQQ", self.attr_entry_size, 0, 0, 0, 0, 0, 0, flags, flags1a, 0, 0) + self.f.write(struct.pack("QQ", PERF_MAGIC, len(h)+16) + h) + offset = self.f.tell() + attrs = b'' + for evd in self.event_descs: + attrs += evd.attr.encode() + self.section_attr.set_data(attrs) + offset = self.section_attr.write(offset) + self.section_data.offset = offset + self.section_data.size = 0 # will be updated as we write records + self.seek(offset) + if not self.write_headers_at_end: + self.write_headers_as_records() + else: + # let the caller write some records, then on close() we will write the headers + pass + + def write_headers_as_records(self): + assert self.is_writing + for ht in self.header_section: + r = PerfRecord(type=PERF_RECORD_HEADER_FEATURE) + r.set_data(struct.pack("Q", ht) + self.header_section[ht].data()) + self.write_record(r) + self.need_to_write_headers = False + + def close(self): + if self.f is None: + return + if self.is_writing: + offset = self.f.tell() + if not self.is_pipe_mode: + # Update the data size. We only do this in non-pipe mode, when we are + # following the data section with subheaders. + self.section_data.write_descriptor() + self.seek(offset) + if self.need_to_write_headers: + # Write subheaders after data, if not already written as FEATURE records. + # We only do this in non-pipe mode. + # It is assumed the current file position is after the most recent record. + # We write an array of section descriptors, one per header. + # Each section descriptor describes a header. + dummy_descriptor = struct.pack("QQ", 0, 0) + for i in range(0, HEADER_MAX): + if i in self.header_section: + self.header_section[i].descriptor_offset = offset + self.f.write(dummy_descriptor) + offset += 16 + for i in range(0, HEADER_MAX): + if i in self.header_section: + offset = self.header_section[i].write(offset) + self.f.close() + self.f = None + self.fn = None + self.is_writing = None + + def write_record(self, r): + assert isinstance(r, PerfRecord) + assert self.is_writing + self.f.write(r.raw) + self.section_data.size += r.size + + def __enter__(self): + return self + + def __exit__(self, exc_type, exc_val, exc_tb): + self.close() + + def __del__(self): + self.close() + + def update_environment_headers(self): + """ + Populate the headers, e.g. HEADER_HOSTNAME, HEADER_ARCH etc. + """ + self.header_section[HEADER_HOSTNAME] = PerfFileSection(self, data=header_from_string(platform.node())) + self.header_section[HEADER_ARCH] = PerfFileSection(self, data=header_from_string(platform.machine())) + self.header_section[HEADER_OSRELEASE] = PerfFileSection(self, data=header_from_string(platform.release())) + self.header_section[HEADER_CMDLINE] = PerfFileSection(self, data=header_from_string_list(sys.argv)) + + def set_buildid_cache(self, buildid_cache): + """ + Set the buildid cache to be used for looking up build ids that occur in this file. + It can be passed in either as a BuildIDCache object, or as a string ("" means use the default in ~/.debug). + Buildid lookup happens in two stages: + - the pid/filename combination in an MMAP record is looked up in the buildid table from PERF_HEADER_BUILD_ID + - the resulting buildid is looked up in the buildid cache that we set here. + """ + if buildid_cache is None: + pass # Operate without a buildid cache + elif isinstance(buildid_cache, perf_buildid.BuildIDCache): + pass # Caller has already constructed the cache + elif buildid_cache == "": + buildid_cache = perf_buildid.BuildIDCache() # use our home directory on this system + else: + # Assume we've been passed a directory name, so construct the buildid cache + buildid_cache = perf_buildid.BuildIDCache(buildid_cache) + self.buildid_cache = buildid_cache + + def add_events(self, d): + """ + Given an event array (from HEADER_EVENT_DESC or a corresponding PERF_RECORD_HEADER_FEATURE) + remember the event descriptions. + Each event comprises + - a PerfEventAttr structure + - a human-readable string (e.g. "instructions") + - a list of numeric identifiers for the event + """ + self.event_attrs = [] + self.n_events = 0 + (n_events, sect_attr_size) = struct.unpack("II", d[0:8]) + if self.debug: + print("%s: %u events, attr size %u" % (self.fn, n_events, sect_attr_size), file=sys.stderr) + if self.attr_entry_size is not None and self.attr_entry_size != 0 and (self.attr_entry_size-16) != sect_attr_size: + print("%s: file header says attribute size is %u but HEADER_EVENT_DESC says attribute size is %u" % (self.fn, self.attr_entry_size-16, sect_attr_size), file=sys.stderr) + #self.attr_entry_size = sect_attr_size - 16 + d = d[8:] + for i in range(0, n_events): + this_attr_size = struct.unpack("I", d[4:8])[0] + if self.debug: + print(" %u bytes left: this attribute size = %u" % (len(d), this_attr_size)); + assert this_attr_size >= 32 and this_attr_size < 256, "invalid attribute size: %u" % this_attr_size + assert len(d) >= this_attr_size, "attr size %u but only %u bytes left" % (this_attr_size, len(d)) + ea_raw = d[0:this_attr_size] + ea = PerfEventAttr(ea_raw, size=this_attr_size) + # Regardless of the size in the structure, the spacing in the file is set by the global size + d = d[sect_attr_size:] + (nr_ids, nlen) = struct.unpack("II", d[0:8]) + assert nr_ids > 0, "unexpected: no ids for %s" % (ea) + name = d[8:8+nlen].strip(b'\0').decode() + d = d[8+nlen:] + ids = [] + for j in range(0, nr_ids): + ids.append(struct.unpack("Q", d[0:8])[0]) + d = d[8:] + if ea.size != sect_attr_size: + print("%s: attribute size mismatch in HEADER_EVENT_DESC: subheader says %u bytes but event descriptor is %u bytes" % (self.fn, sect_attr_size, ea.size), file=sys.stderr) + self.add_event(ea, ids, name) + + def add_event(self, ea, ids=[], name=None): + """ + Create a PerfDataEventDesc object and add it to this file. + """ + assert isinstance(ea, PerfEventAttr) + # Exceptionally, in pipe mode, we might see events duplicated between different metadata records. + if self.is_pipe_mode and ids is not None: + if set(ids).issubset(self.event_index.keys()): + return + eix = len(self.event_descs) + self.event_attrs.append(ea) + desc = PerfDataEventDesc(attr=ea, ids=ids, name=name, index=eix) + self.event_descs.append(desc) + self.n_events = len(self.event_descs) + # The magic offsets within the records need to be the same across all events - + # we need the offset to get the identifier to identify the event. + sample_id_offset = record_sample_id_offset(ea) + non_sample_id_offset = record_non_sample_id_offset(ea) + if self.n_events == 1: + self.sample_id_offset = sample_id_offset + self.non_sample_id_offset = non_sample_id_offset + else: + assert self.sample_id_offset == sample_id_offset + assert self.non_sample_id_offset == non_sample_id_offset + if self.default_event_attr is None: + assert eix == 0 + # Event #0 becomes the default. Note that "perf inject" may rearrange events. + self.default_event_attr = ea + if ids is not None: + # The event identifiers are meant to uniquely identify the events. + for id in ids: + assert id not in self.event_index, "event id %u is duplicated between descriptors #%u and #%u" % (id, self.event_index[id], eix) + self.event_index[id] = eix + return eix + + def events_all(self): + """ + Return the perf event definitions. + """ + return self.event_descs + + def events(self, type=None): + """ + Iterate over all events, optionally selecting by various criteria. + Yield PerfDataEventDesc's. + """ + for desc in self.events_all(): + if type is not None and desc.attr.type != type: + continue + yield desc + + def event_index_by_id(self, ident): + """ + Given an event identifier (as recorded by PERF_SAMPLE_IDENTIFIER and communicated + in HEADER_EVENT_DESC), get the PerfDataEventDesc. + """ + if ident in self.event_index: + eix = self.event_index[ident] # Some small number e.g. 0 or 1 + elif self.n_events == 1: + # There's only one descriptor so it must be this one + eix = 0 + else: + eix = None + return eix + + def event_desc_by_id(self, ident): + eix = self.event_index_by_id(ident) + if eix is not None: + return self.event_descs[eix] + else: + return None + + def event_attr_by_id(self, ident): + """ + Given an event identifier, get the PerfEventAttr. + """ + desc = self.event_desc_by_id(ident) + if desc is not None: + return desc.attr + else: + return None + + def show_events(self): + # For diagnostics, show all the event descriptors and events known in this file + print("Events:") + print(" Descriptors:") + for eix in range(len(self.event_descs)): + desc = self.event_descs[eix] + print(" %s" % (desc)) + + def has_header(self, i): + return (self.flags & (1<= 8, "%s: invalid perf record at file offset 0x%x (type=0x%x, size=%d)" % (self.fn, eoff, type, size) + # read the rest of the record, as indicated by the size field + try: + e = h + self.read(size-8) + except IOError: + print("** %s: could not read %u-byte payload for record type %u at 0x%x" % (self.fn, size-8, type, eoff)) + r = PerfDataRecord(e, file=self, file_offset=eoff) + if r.type == PERF_RECORD_AUXTRACE: + r.auxtrace_file_offset = eoff + r.size + (r.auxtrace_size, r.auxtrace_offset, r.ref, r.idx, r.tid, r.cpu) = struct.unpack("QQQIii", r.raw[8:44]) + elif r.type == PERF_RECORD_AUX: + self.unpack_record(r) + aux_event = self.event_desc_by_id(r.id) + if aux_event is None: + self.show_events() + assert aux_event is not None, "can't find event descriptor for id=%u" % r.id + assert isinstance(aux_event,PerfDataEventDesc) + if self.aux_event is None: + self.aux_event = aux_event + else: + assert self.aux_event == aux_event + r.idx = aux_event.id_index(r.id) # To correspond with PERF_RECORD_AUXTRACE + return r + + def raw0_records(self, data=True): + """ + Iterate over the records, returning raw PerfRecord objects, in the order they occur in perf.data. + The only processing and conditioning we do here: + - get (or skip over) the raw data buffer following PERF_RECORD_AUXTRACE + - expand PERF_RECORD_COMPRESSED + """ + assert self.file_is_valid, "%s: attempt to read records from invalid file" % (self.fn) + if not self.is_pipe_mode: + eoff = self.section_data.offset + self.data_end = self.section_data.offset + self.section_data.size + self.seek(eoff) + else: + # Reading from stdin - non-seekable. Or possibly reading from a file saved via a pipe. + #if self.f != sys.stdin: + # self.seek(16) + eoff = 0 + self.data_end = None + # Loop through the raw records. Note that a PERF_RECORD_AUXTRACE record will be immediately + # followed by the contents of an AUX buffer, which we need to account for. + itrace_tid = None + while self.data_end is None or eoff < self.data_end: + r = self.read_record(eoff, already_here=True) + if r is None and self.is_pipe_mode: + break + eoff += r.size + # if the record has AUX data immediately following, read it now to avoid getting confused about the offset + if r.type == PERF_RECORD_AUXTRACE: + if data or self.is_pipe_mode: + r.aux_data = self.f.read(r.auxtrace_size) + else: + r.aux_data = None + self.seek(eoff + r.auxtrace_size) # Not reading it this time, so step past it + eoff += r.auxtrace_size + elif r.type == PERF_RECORD_COMPRESSED: + # TBD this section is work-in-progress + # We use our perf_zstd module. zstandard/zstd don't seem to work. + zstd_magic = struct.unpack("I",r.raw[8:12])[0] + assert zstd_magic == 0xFD2FB528, "%s: bad Zstd magic: 0x%X" % (self.fn, zstd_magic) + import pyperf.perf_zstd as perf_zstd + ucd = perf_zstd.decompress(r.raw[8:], ratio=8) + print_hex_dump(ucd) + print("decompressed %u bytes to %u bytes" % (len(r.raw)-8, len(ucd))) + while len(ucd) > 0: + (type, misc, size) = struct.unpack("IHH", ucd[:8]) + e = ucd[:size] + print("uncompressed: %u %u %u" % (type, misc, size)) + r = PerfDataRecord(e, file=self) + #print(r) + yield r + ucd = ucd[size:] + continue + # Old abandoned ways + try: + import zstandard + except: + print("** %s: compressed file needs 'zstandard' module to uncompress" % (self.fn), file=sys.stderr) + if False: + ddd = zstd.ZSTD_compress("ABCD",1,4) + print_hex_dump(ddd) + eee = zstd.ZSTD_uncompress(ddd) + print_hex_dump(eee) + if True: + print("Compressed data:") + print_hex_dump(r.raw[:32]) + fp = zstandard.get_frame_parameters(r.raw[8:]) + print(" content size: 0x%x" % (fp.content_size)) + print(" window size: 0x%x" % (fp.window_size)) + max_size = (self.compression_ratio + 1) * len(r.raw) + print("trying %u bytes -> %u bytes" % (len(r.raw), max_size)) + ucd = zstandard.ZstdDecompressor().decompress(r.raw[8:], max_output_size=max_size) + print_hex_dump(ucd) + yield r + + def raw_records(self, event=False, unpack=False, time=False, data=True): + """ + Iterate over the records, returning raw PerfRecord objects, in the order they occur in perf.data. + + This also updates metadata in response to some record types - this is especially important + in pipe mode when we don't have a proper header. + """ + pending_aux = {} # indexed by event ID: AUX records waiting for AUXTRACE + for r in self.raw0_records(data=data): + if r.type == PERF_RECORD_HEADER_FEATURE: + # pipe mode: this supplies a sub-header + # Process some record types to add global context that we'd normally get from subheaders. + r.header_type = struct.unpack("Q", r.raw[8:16])[0] + r.header_data = r.raw[16:] + # Note that we might see event descriptions duplicated between + # PERF_RECORD_HEADER_FEATURE, subtype HEADER_EVENT_DESC + # PERF_RECORD_HEADER_ATTR + self.process_header(r.header_type, r.header_data) + elif r.type == PERF_RECORD_HEADER_ATTR: + # pipe mode: this supplies a perf_event_attr and some ids + attr_size = struct.unpack("I", r.raw[12:16])[0] # peek from inside the perf_event_attr + assert attr_size > 64 and attr_size <= 1024, "ATTR invalid perf_event_attr size %d" % attr_size + attr = PerfEventAttr(r.raw[8:attr_size+8]) + ids_array = r.raw[attr_size+8:] + assert len(ids_array) > 0 and len(ids_array) % 8 == 0, "bad length of ATTR id array: %d (attr_size=%d)" % (len(ids_array), attr_size) + n_ids = len(ids_array) // 8 + ids = [] + for i in range(n_ids): + id = struct.unpack("Q", ids_array[i*8:i*8+8])[0] + ids.append(id) + self.add_event(attr, ids=ids) + elif r.type == PERF_RECORD_AUXTRACE_INFO: + # The auxtrace info type indicates the type of trace and the format of the info, + # e.g. it might be PERF_AUXTRACE_CS_ETM. + r.auxtrace_info_type = struct.unpack("I", r.raw[8:12])[0] + # Hypothesis: there is at most one type of AUX buffer per perf.data file, + # and one set of info, no matter how many aux buffers are collected. + # So we can set a per-file 'auxtrace_info_type' and info. + # We will need to rethink this. + assert self.auxtrace_info_type is None, "multiple PERF_RECORD_AUXTRACE_INFO, unexpected" + self.auxtrace_info_type = r.auxtrace_info_type + # The private information is at offset 16. + # Some formats have a "PMU type" corresponding perf_event_attr.type and named in HEADER_PMU_MAPPINGS, + # but the location is different for different AUX formats, e.g. + # INTEL_PT: "Q" 16:24 + # CS_ETM: "I" 28:32 + r.pmu_type = None + if r.auxtrace_info_type in auxtrace_handlers: + auxtrace_handlers[r.auxtrace_info_type].handle_auxtrace_info(self,r) + elif r.type == PERF_RECORD_AUX: + # Generated by kernel to indicate that data is available in the AUX buffer. + r.auxtrace_info_type = self.auxtrace_info_type # TBD should check in case we have multiple AUX events + self.unpack_record(r) + # We may see PERF_RECORD_AUX for different events, but they will all be for the same event descriptor. + # r.id gives us the event descriptor and the 0-based index within that descriptor, that corresponds + # to the index in the PERF_RECORD_AUXTRACE record. Using the index and the offset, we can find + # the PERF_RECORD_AUXTRACE buffer for this PERF_RECORD_AUX segment. + # If the PERF_RECORD_AUX doesn't have a valid CPU field, it's probably for a per-thread event. + if r.id not in pending_aux: + pending_aux[r.id] = [] + pending_aux[r.id].append(r) + # We haven't yet seen this AUX record's AUXTRACE buffer, but we will soon... + r.auxtrace_record = None + elif r.type == PERF_RECORD_AUXTRACE: + # Synthesized by perf. Data immediately follows and we will have read it. + assert self.auxtrace_info_type is not None, "seen PERF_RECORD_AUXTRACE without info" + r.auxtrace_info_type = self.auxtrace_info_type + # Fields: + # auxtrace_size: number of bytes in this buffer + # auxtrace_offset: offset into the overall stream, of which this buffer is one chunk + # ref: unique identifier for this buffer, may be random (see e.g. cs_etm_reference()) + # idx: the 0-based index of the event (or event buffer): for events opened per cpu, matches cpu, or 0 if cpu is -1 + # tid: thread id or -1, as for perf_event_open(); actual trace may be from a different thread or even process + # cpu: cpu or -1 + assert r.id is None + if self.aux_event is None: + print("No PERF_RECORD_AUX seen before %s" % (r), file=sys.stderr) + r.aux_records = [] + else: + # The 0-based index gets us the event identifier, which matches this AUXTRACE up with AUX records. + if self.aux_event.ids is not None: + r.id = self.aux_event.ids[r.idx] + else: + # Event wasn't described in HEADER_EVENT_DESC, so has no ids + r.id = r.idx + # Attach the pending PERF_RECORD_AUX record(s) to this trace buffer record. + if r.cpu != -1: + cpu = r.cpu + else: + cpu = None + if r.id in pending_aux: + r.aux_records = pending_aux[r.id] + del pending_aux[r.id] + else: + if False and r.auxtrace_size > 8: + # We sometimes see some anomalous AUXTRACE records at the end of a session. + assert r.id in pending_aux, "PERF_RECORD_AUXTRACE for event %u, no matching PERF_RECORD_AUX seen" % (r.id) + r.aux_records = [] + r.has_been_unpacked = True + r.itrace_tid = itrace_tid + elif r.type == PERF_RECORD_ITRACE_START: + self.unpack_record(r) + itrace_tid = r.tid + if event or time or unpack: + self.get_record_event(r) + if unpack: + self.unpack_record(r) + elif time: + r.t = r.time() + if (not data) and r.file_offset is not None and not self.is_pipe_mode: + # If data is not needed now, and we can re-read from disk, discard it to save memory + r.raw = None + yield r + + def records(self, sorted_time=False, unpack=True, time=True): + """ + Iterate over the perf records, returning PerfRecord objects. + These aren't guaranteed to be in time order, as the perf + subsystem may have combined records from several CPUs. + (Use sorted_time=True to get them yielded in time order.) + Generally the record header indicates the total size of the record. + The exception is PERF_RECORD_AUXTRACE records where the record from + the main mmap is immediately followed by the raw data from the AUX mmap. + We try to avoid doing too much record processing before sorting - + instead, we get the time and not much else, then unpack after sorting. + """ + if sorted_time: + def rectime(r): + t = r.t + if t is None: + return 0 + return t + sorted_recs = sorted(list(self.raw_records(unpack=False, time=True, data=False)), key=rectime) + for r in sorted_recs: + self.get_record_data(r) + if unpack: + self.unpack_record(r) + yield r + else: + for r in self.raw_records(event=True, time=time, unpack=unpack): + yield r + + def reader(self): + return PerfDataReader(self) + + + +""" +In order to resolve program addresses we need to know what context (pid -> memory mapping) +applies at the time of an event. We can do this two ways: + + - we can process events in time order, with the various MMAP, FORK etc. events + being used to update the context: this is what we do below with the + PerfDataReader object. This works for sample events but does not, + in general, work where we have additional streams of events over + multiple pids/tids and a significant time period, as we do with e.g. + PT/ETM trace or SPE. ("perf inject" can turn these into individually + timed and annotated sample events, at the cost of a huge increase in + perf.data size.) + + - we can build, as a property of the perf.data file, a time-aware + database where we can ask questions like "what was the mapping for + address A in thread N at time T?" + +""" + + +class ThreadInfo: + """ + Information about a thread at some current time. + This information may change over time. It is intended to provide context + for other events (e.g. when an IP value needs to be looked up). + """ + def __init__(self, tid, name=None, process=None): + self.tid = tid + self.thread_name = name + self.process = None + if process is not None: + self.set_process(process) + + def set_process(self, process): + if self.process is None: + self.process = process + assert self.tid not in process.threads + process.threads[self.tid] = self + else: + assert process == self.process, "thread %s changed process from %s to %s" % (self, self.process, process) + + def __str__(self): + if self.thread_name is not None: + return "%s:%d" % (self.thread_name, self.tid) + else: + return "[tid=%d]" % (self.tid) + + +def proc_map(m): + """ + Generate a /proc/n/maps style line for a PERF_RECORD_MMAP or PERF_RECORD_MMAP2. + """ + s = "%016x-%016x " % (m.addr, m.addr+m.len) + s += "-r"[(m.prot & 0x01) != 0] + s += "-w"[(m.prot & 0x02) != 0] + s += "-x"[(m.prot & 0x04) != 0] + if m.flags is not None: + # from PERF_RECORD_MMAP2 + s += "-sp?"[((m.flags & 0x01) != 0) + 2*((m.flags & 0x02) != 0)] + else: + s += "?" + s += " %08x" % m.pgoff + if m.maj is not None: + s += " %02x:%02x " % (m.maj, m.min) + s += m.filename + return s + + +class ProcessInfo: + """ + Track information for a process (address space) at a point in time. + """ + def __init__(self, pid): + self.pid = pid # -1 for kernel etc. + self.maps = [] # a list of MMAP/MMAP2 event records + self.threads = {} # threads, indexed by tid + + def proc_maps(self): + # Return something looking like /proc/.../maps + s = "" + for m in self.maps: + s += proc_map(m) + "\n" + return s + + def find_addr(self, addr): + for m in self.maps: + if addr >= m.addr and addr < (m.addr + m.len): + return m + return None + + def __str__(self): + s = "[pid=%d]" % self.pid + return s + + +class PerfDataReader: + """ + Read records from a PerfData object, continually maintaining a context + that can be used to interpret the records. Because we mutate this object's + context in the process of reading, this is a separate object from the + PerfData object, which can be shared between several readers. + """ + def __init__(self, pd): + self.pd = pd + kernel_space = ProcessInfo(-1) + swapper_thread = ThreadInfo(0, name="swapper", process=kernel_space) + self.threads = { 0: swapper_thread } + self.procs = { -1: kernel_space } + + def get_thread(self, tid): + if tid not in self.threads: + t = ThreadInfo(tid) # We don't yet know process + self.threads[tid] = t + else: + t = self.threads[tid] + return t + + def get_proc(self, pid): + if pid not in self.procs: + self.procs[pid] = ProcessInfo(pid) + return self.procs[pid] + + def find_proc(self, tid): + if tid in self.threads: + t = self.threads[tid] + assert t.process is not None, "missing process for thread %u" % tid + return t.process + return None + + def lookup_addr(self, pid, addr): + # Return a PERF_RECORD_MMAP PerfRecord, or None + p = self.find_proc(pid) + if p is not None: + mr = p.find_addr(addr) + if mr is not None: + return mr + # Now look again in all-process maps (e.g. VDSO) + return self.procs[-1].find_addr(addr) + + def lookup_addr_all(self, addr): + """ + Look up the address in all current mappings. + """ + mr = self.lookup_addr(-1, addr) + if mr is not None: + yield (-1, mr) + else: + for p in self.procs.values(): + if p.pid != -1: + m = p.find_addr(addr) + if m is not None: + yield (p.pid, m) + + def proc_maps_all(self): + s = self.procs[-1].proc_maps() + for p in self.procs.values(): + s += "\n[%u]\n" % p.pid + s += p.proc_maps() + return s + + def records(self, sorted_time=False, unpack=True): + """ + Yield all records, sorted or unsorted, with additional tracking of address space mapping events + in the PerfDataReader object. + """ + for r in self.pd.records(sorted_time=sorted_time, unpack=unpack): + if r.type == PERF_RECORD_MMAP or r.type == PERF_RECORD_MMAP2: + if not unpack: + r.unpack() + # Look up the filename in this perf.data file's HEADER_BUILD_ID cache. + r.build_id = self.pd.build_id(r.pid, r.filename) + # If we found a buildid, get the file with this buildid, possibly from the ~/.debug buildid cache. + r.file_cached = None + if r.build_id is not None: + if self.pd.buildid_cache is not None: + r.file_cached = self.pd.buildid_cache.id_matching_file(r.build_id, r.filename) + elif perf_buildid.file_buildid(r.filename) == r.build_id: + r.file_cached = r.filename + yield r + # Update context for the benefit of other events + if r.type == PERF_RECORD_COMM: + if not unpack: + r.unpack() + t = self.get_thread(r.tid) + t.set_process(self.get_proc(r.pid)) + t.thread_name = r.thread_name + elif r.type == PERF_RECORD_FORK: + # We always create a new thread. We might also create a new process. + if not unpack: + r.unpack() + if r.pid != r.ppid: + # Created new process (with its own main thread) + assert r.tid == r.pid, "expected new process to have TID=PID" + p = self.get_proc(r.pid) + if r.ppid in self.procs: + p.maps = copy.copy(self.procs[r.ppid].maps) + else: + # Created new thread in same process + p = self.get_proc(r.pid) + t = self.get_thread(r.tid) + t.set_process(p) + if r.ptid in self.threads: + # Propagate the old thread name to the forked thread name + t.thread_name = self.threads[r.ptid].thread_name + elif r.type == PERF_RECORD_MMAP or r.type == PERF_RECORD_MMAP2: + # Already unpacked + p = self.get_proc(r.pid) + p.maps.append(r) + elif r.type == PERF_RECORD_EXIT: + # Should we delete knowledge of the exiting thread? + pass + + +if __name__ == "__main__": + # As a self-test, print basic details of the current perf.data file. + # For more detailed printing, in the style of "perf report", see perf_report.py. + fn = "perf.data" + for arg in sys.argv[1:]: + if arg == "write": + w = PerfData() + w.add_event(PerfEventAttr(type=PERF_TYPE_HARDWARE, config=PERF_COUNT_HW_CACHE_MISSES)) + w.open_and_write_header("new.perf.data") + w.close() + fn = "new.perf.data" + else: + fn = arg + d = PerfData(fn, debug=True) + for r in d.records(): + print("%8x %s: %s" % (r.file_offset, record_type_str(r.type), r)) + if d.datatop is not None: + datamap.print_datamap(d.datamap, fmt="%-10x") + for r in d.datatop.iter_unmapped(): + print("unmapped area: %s" % r) + data = d.readat(r.base, r.size) + print_hex_dump(data, prefix=" ", base=r.base) + d.close() diff --git a/linux_app/pmu_app/pyperf/pyperf/perf_enum.py b/linux_app/pmu_app/pyperf/pyperf/perf_enum.py new file mode 100644 index 00000000..70589344 --- /dev/null +++ b/linux_app/pmu_app/pyperf/pyperf/perf_enum.py @@ -0,0 +1,368 @@ +# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# SPDX-License-Identifier : Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" +Manage enumerations relating to the perf_event_open API. + +Enumerations specific to perf.data files are not generally here. +""" + +from __future__ import print_function + +# Values in attr.type; other values are for custom PMUs +PERF_TYPE_HARDWARE = 0 +PERF_TYPE_SOFTWARE = 1 +PERF_TYPE_TRACEPOINT = 2 +PERF_TYPE_HW_CACHE = 3 +PERF_TYPE_RAW = 4 +PERF_TYPE_BREAKPOINT = 5 + +PERF_COUNT_HW_CPU_CYCLES = 0 +PERF_COUNT_HW_INSTRUCTIONS = 1 +PERF_COUNT_HW_CACHE_REFERENCES = 2 +PERF_COUNT_HW_CACHE_MISSES = 3 +PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4 +PERF_COUNT_HW_BRANCH_MISSES = 5 +PERF_COUNT_HW_BUS_CYCLES = 6 +PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7 +PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8 +PERF_COUNT_HW_REF_CPU_CYCLES = 9 + +PERF_COUNT_SW_CPU_CLOCK = 0 +PERF_COUNT_SW_TASK_CLOCK = 1 +PERF_COUNT_SW_PAGE_FAULTS = 2 +PERF_COUNT_SW_CONTEXT_SWITCHES = 3 +PERF_COUNT_SW_CPU_MIGRATIONS = 4 +PERF_COUNT_SW_PAGE_FAULTS_MIN = 5 +PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6 +PERF_COUNT_SW_ALIGNMENT_FAULTS = 7 +PERF_COUNT_SW_EMULATION_FAULTS = 8 +PERF_COUNT_SW_DUMMY = 9 +PERF_COUNT_SW_BPF_OUTPUT = 10 + +# Cache level is at bit position 0 +PERF_COUNT_HW_CACHE_L1D = 0 +PERF_COUNT_HW_CACHE_L1I = 1 +PERF_COUNT_HW_CACHE_LL = 2 +PERF_COUNT_HW_CACHE_DTLB = 3 +PERF_COUNT_HW_CACHE_ITLB = 4 +PERF_COUNT_HW_CACHE_BPU = 5 +PERF_COUNT_HW_CACHE_NODE = 6 +# Access type is at bit position 8 +PERF_COUNT_HW_CACHE_OP_READ = 0 +PERF_COUNT_HW_CACHE_OP_WRITE = 1 +PERF_COUNT_HW_CACHE_OP_PREFETCH = 2 +# Result is at bit position 16 +PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0 +PERF_COUNT_HW_CACHE_RESULT_MISS = 1 + +def PERF_HW_CACHE(unit, op, result): + return (result << 16) | (op << 8) | (unit) + +def PERF_HW_CACHE_UNIT(cfg): + return cfg & 0xff + +def PEFF_HW_CACHE_OP(cfg): + return (cfg >> 8) & 0xff + +def PERF_HW_CACHE_RESULT(cfg): + return (cfg >> 16) & 0xff + + +HW_BREAKPOINT_EMPTY = 0 +HW_BREAKPOINT_R = 1 +HW_BREAKPOINT_W = 2 +HW_BREAKPOINT_RW = 3 +HW_BREAKPOINT_X = 4 + +# Flags in attr.read_format +PERF_FORMAT_TOTAL_TIME_ENABLED = 0x00000001 +PERF_FORMAT_TOTAL_TIME_RUNNING = 0x00000002 +PERF_FORMAT_ID = 0x00000004 +PERF_FORMAT_GROUP = 0x00000008 +PERF_FORMAT_MAX = 0x00000010 + +# Flags in attr.sample_type +PERF_SAMPLE_IP = 0x00000001 +PERF_SAMPLE_TID = 0x00000002 +PERF_SAMPLE_TIME = 0x00000004 +PERF_SAMPLE_ADDR = 0x00000008 +PERF_SAMPLE_READ = 0x00000010 +PERF_SAMPLE_CALLCHAIN = 0x00000020 +PERF_SAMPLE_ID = 0x00000040 +PERF_SAMPLE_CPU = 0x00000080 +PERF_SAMPLE_PERIOD = 0x00000100 +PERF_SAMPLE_STREAM_ID = 0x00000200 +PERF_SAMPLE_RAW = 0x00000400 +PERF_SAMPLE_BRANCH_STACK = 0x00000800 +PERF_SAMPLE_REGS_USER = 0x00001000 +PERF_SAMPLE_STACK_USER = 0x00002000 +PERF_SAMPLE_WEIGHT = 0x00004000 +PERF_SAMPLE_DATA_SRC = 0x00008000 +PERF_SAMPLE_IDENTIFIER = 0x00010000 +PERF_SAMPLE_TRANSACTION = 0x00020000 +PERF_SAMPLE_REGS_INTR = 0x00040000 +PERF_SAMPLE_PHYS_ADDR = 0x00080000 +PERF_SAMPLE_AUX = 0x00100000 +PERF_SAMPLE_CGROUP = 0x00200000 + +# Flags in attr.branch_sample_type +PERF_SAMPLE_BRANCH_USER = 0x00000001 +PERF_SAMPLE_BRANCH_KERNEL = 0x00000002 +PERF_SAMPLE_BRANCH_HV = 0x00000004 +PERF_SAMPLE_BRANCH_PLM_ALL = 0x00000007 +PERF_SAMPLE_BRANCH_ANY = 0x00000008 +PERF_SAMPLE_BRANCH_ANY_CALL = 0x00000010 +PERF_SAMPLE_BRANCH_ANY_RETURN = 0x00000020 +PERF_SAMPLE_BRANCH_IND_CALL = 0x00000040 +PERF_SAMPLE_BRANCH_ABORT_TX = 0x00000080 +PERF_SAMPLE_BRANCH_IN_TX = 0x00000100 +PERF_SAMPLE_BRANCH_NO_TX = 0x00000200 +PERF_SAMPLE_BRANCH_COND = 0x00000400 +PERF_SAMPLE_BRANCH_CALL_STACK = 0x00000800 +PERF_SAMPLE_BRANCH_IND_JUMP = 0x00001000 +PERF_SAMPLE_BRANCH_CALL = 0x00002000 +PERF_SAMPLE_BRANCH_NO_FLAGS = 0x00004000 +PERF_SAMPLE_BRANCH_NO_CYCLES = 0x00008000 +PERF_SAMPLE_BRANCH_TYPE_SAVE = 0x00010000 +PERF_SAMPLE_BRANCH_HW_INDEX = 0x00020000 +PERF_SAMPLE_BRANCH_MAX = 0x00040000 + +PERF_SAMPLE_REGS_ABI_NONE = 0 +PERF_SAMPLE_REGS_ABI_32 = 1 +PERF_SAMPLE_REGS_ABI_64 = 2 + +# Values in record.type +PERF_RECORD_MMAP = 1 +PERF_RECORD_LOST = 2 +PERF_RECORD_COMM = 3 +PERF_RECORD_EXIT = 4 +PERF_RECORD_THROTTLE = 5 +PERF_RECORD_UNTHROTTLE = 6 +PERF_RECORD_FORK = 7 +PERF_RECORD_READ = 8 +PERF_RECORD_SAMPLE = 9 +PERF_RECORD_MMAP2 = 10 +PERF_RECORD_AUX = 11 +PERF_RECORD_ITRACE_START = 12 +PERF_RECORD_LOST_SAMPLES = 13 +PERF_RECORD_SWITCH = 14 +PERF_RECORD_SWITCH_CPU_WIDE = 15 +PERF_RECORD_NAMESPACES = 16 +PERF_RECORD_KSYMBOL = 17 +PERF_RECORD_BPF_EVENT = 18 +PERF_RECORD_CGROUP = 19 +PERF_RECORD_TEXT_POKE = 20 + +PERF_RECORD_MISC_CPUMODE_MASK = 0x7 +PERF_RECORD_MISC_CPUMODE_UNKNOWN = 0 +PERF_RECORD_MISC_KERNEL = 1 +PERF_RECORD_MISC_USER = 2 +PERF_RECORD_MISC_HYPERVISOR = 3 +PERF_RECORD_MISC_GUEST_KERNEL = 4 +PERF_RECORD_MISC_GUEST_USER = 5 +PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT = 0x1000 +PERF_RECORD_MISC_MMAP_DATA = 0x2000 +PERF_RECORD_MISC_COMM_EXEC = 0x2000 +PERF_RECORD_MISC_SWITCH_OUT = 0x2000 +PERF_RECORD_MISC_EXACT_IP = 0x4000 +PERF_RECORD_MISC_SWITCH_OUT_PREEMPT = 0x4000 + +PERF_AUX_FLAG_TRUNCATED = 0x01 +PERF_AUX_FLAG_OVERWRITE = 0x02 +PERF_AUX_FLAG_PARTIAL = 0x04 +PERF_AUX_FLAG_COLLISION = 0x08 + +PERF_MEM_OP_NA = 1 +PERF_MEM_OP_LOAD = 2 +PERF_MEM_OP_STORE = 4 +PERF_MEM_OP_PFETCH = 8 +PERF_MEM_OP_EXEC = 16 +PERF_MEM_OP_SHIFT = 0 + +PERF_MEM_LVL_NA = 1 +PERF_MEM_LVL_HIT = 2 +PERF_MEM_LVL_MISS = 4 +PERF_MEM_LVL_L1 = 8 +PERF_MEM_LVL_LFB = 16 +PERF_MEM_LVL_L2 = 32 +PERF_MEM_LVL_L3 = 64 +PERF_MEM_LVL_LOC_RAM = 128 +PERF_MEM_LVL_REM_RAM1 = 256 +PERF_MEM_LVL_REM_RAM2 = 512 +PERF_MEM_LVL_REM_CCE1 = 1024 +PERF_MEM_LVL_REM_CCE2 = 2048 +PERF_MEM_LVL_IO = 4096 +PERF_MEM_LVL_UNC = 8192 +PERF_MEM_LVL_SHIFT = 5 + +PERF_MEM_SNOOP_NA = 1 +PERF_MEM_SNOOP_NONE = 2 +PERF_MEM_SNOOP_HIT = 4 +PERF_MEM_SNOOP_MISS = 8 +PERF_MEM_SNOOP_HITM = 16 +PERF_MEM_SNOOP_SHIFT = 19 + +PERF_MEM_LOCK_NA = 1 +PERF_MEM_LOCK_LOCKED = 2 +PERF_MEM_LOCK_SHIFT = 24 + +PERF_MEM_TLB_NA = 1 +PERF_MEM_TLB_HIT = 2 +PERF_MEM_TLB_MISS = 4 +PERF_MEM_TLB_L1 = 8 +PERF_MEM_TLB_L2 = 16 +PERF_MEM_TLB_WK = 32 +PERF_MEM_TLB_OS = 64 +PERF_MEM_TLB_SHIFT = 26 + +PERF_MEM_LVLNUM_L1 = 1 +PERF_MEM_LVLNUM_L2 = 2 +PERF_MEM_LVLNUM_L3 = 3 +PERF_MEM_LVLNUM_L4 = 4 +PERF_MEM_LVLNUM_ANY_CACHE = 11 +PERF_MEM_LVLNUM_LFB = 12 +PERF_MEM_LVLNUM_RAM = 13 +PERF_MEM_LVLNUM_PMEM = 14 +PERF_MEM_LVLNUM_SHIFT = 33 + +PERF_MEM_REMOTE_REMOTE = 1 +PERF_MEM_REMOTE_SHIFT = 37 + +PERF_MEM_SNOOPX_FWD = 1 +PERF_MEM_SNOOPX_SHIFT = 38 + +# Special values in branch stack +PERF_CONTEXT_HV = -32 # ...ffe0 +PERF_CONTEXT_KERNEL = -128 # ...ff80 +PERF_CONTEXT_USER = -512 # ...fe00 +PERF_CONTEXT_GUEST = -2048 # ...f800 +PERF_CONTEXT_GUEST_KERNEL = -2176 +PERF_CONTEXT_GUEST_USER = -2560 + + +def _str_enum(pfx, n, exclude=[], short=False): + """ + Resolve a number into a constant name, given a prefix, + e.g. _str_enum("TYPE", 4) == "PERF_TYPE_RAW" + 'exclude' is so we can resolve PERF_RECORD constants but + exclude PERF_RECORD_MISC flags. + """ + if n is None: + return None + s = None + def canon(pfx): + if not pfx.startswith("PERF_"): + pfx = "PERF_" + pfx + if not pfx.endswith("_"): + pfx += "_" + return pfx + pfx = canon(pfx) + exclude = map(canon, exclude) + for (name, value) in globals().items(): + if value == n and name.startswith(pfx): + excluded = False + for e in exclude: + if name.startswith(e): + excluded = True + break + if not excluded: + s = name + break + if s is None: + s = pfx + ("%u??" % n) + if short: + s = s[len(pfx):] + return s + + +assert _str_enum("TYPE", 1) == "PERF_TYPE_SOFTWARE" +assert _str_enum("TYPE", 2, short=True) == "TRACEPOINT" + +def str_PERF_TYPE(n, short=False): + return _str_enum("TYPE", n, short=short) + + +def str_PERF_RECORD(n, short=False): + return _str_enum("RECORD", n, short=short, exclude=["RECORD_MISC"]) + +assert str_PERF_RECORD(2) == "PERF_RECORD_LOST" + + +def _enums(pfx, keys=[]): + if keys: + for k in keys: + g = pfx + "_" + k + yield (k, globals()[g]) + else: + for g in globals(): + if g.startswith(pfx + "_"): + yield (g[len(pfx)+1:], globals()[g]) + + +def _flag_ored_string(x, pfx, keys=[]): + flags = [] + for (k, v) in _enums(pfx, keys=keys): + if x & v: + flags.append(k) + x &= ~v + if x: + flags.append("0x%x" % x) + return "|".join(flags) + + +def str_flags_PERF_SAMPLE(x): + return _flag_ored_string(x, "PERF_SAMPLE", ["IP", "TID", "TIME", "ADDR", "READ", "CALLCHAIN", "ID", "CPU", "PERIOD", "STREAM_ID", "RAW", "BRANCH_STACK", "REGS_USER", "STACK_USER", "WEIGHT", "DATA_SRC", "IDENTIFIER"]) + +assert str_flags_PERF_SAMPLE(PERF_SAMPLE_ID|PERF_SAMPLE_RAW) == "ID|RAW" + + +def str_flags_PERF_SAMPLE_BRANCH(x): + return _flag_ored_string(x, "PERF_SAMPLE_BRANCH", ["USER", "KERNEL", "HV", "ANY", "ANY_CALL", "IND_CALL", "CALL", "HW_INDEX"]) + + +def str_flags_PERF_FORMAT(x): + return _flag_ored_string(x, "PERF_FORMAT", ["TOTAL_TIME_ENABLED","TOTAL_TIME_RUNNING","ID","GROUP"]) + + +def str_PERF_RECORD_MISC(x): + cmode = x & PERF_RECORD_MISC_CPUMODE_MASK + flags = x & ~PERF_RECORD_MISC_CPUMODE_MASK + s = _flag_ored_string(flags, "PERF_RECORD_MISC").split('|') + if s == ['']: + s = [] + s += [_str_enum("PERF_RECORD_MISC", cmode, short=True)] + s = '|'.join(s) + return s + + +def test(): + import os + fn = "/tmp/perf_enum_test.c" + fd = open(fn, "w") + print("#include ", file=fd) + print("#include ", file=fd) + for name in globals(): + if name.startswith("PERF_"): + print("int test_%s[1/(%s==%u)];" % (name, name, globals()[name]), file=fd) + print(file=fd) + print("int main(void) { return 0; }", file=fd) + fd.close() + os.system("cc %s" % fn) + + +if __name__ == "__main__": + test() + diff --git a/linux_app/pmu_app/pyperf/pyperf/perf_espec.py b/linux_app/pmu_app/pyperf/pyperf/perf_espec.py new file mode 100644 index 00000000..1491c9b5 --- /dev/null +++ b/linux_app/pmu_app/pyperf/pyperf/perf_espec.py @@ -0,0 +1,797 @@ +# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# SPDX-License-Identifier : Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" +perf event parser + +Given a string as passed to the -e argument to perf, +return an event configuration object (EventConfig) +that can be used with the perf events module. + +An EventConfig object is roughly equivalent to the +perf_event_attr structure passed to perf_event_open, +but with additional information such as + - the event description string, as used to select it + - scale and units +""" + +from __future__ import print_function + +import os, sys +sys.path.append(os.path.dirname(__file__)) + +from perf_enum import * +from perf_sysfs import * +from perf_attr import * +import perf_parse +from perf_util import * + +# Experimental support for reading PMU event names from JSON +sys.path.append(os.path.join(os.path.dirname(__file__), "..")) +try: + import PMUdescx +except ImportError: + pass + +o_verbose = 0 + +PRECISE_MAX = 3 + + +# +# This tries to map between the simple names used by 'perf list' +# and the enumerators exported by pysweep. However, those enumerators +# may depend on kernel configuration, e.g. COUNT_SW_BPF_OUTPUT. +# +perf_event_map = { + + "cpu-cycles": (PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES), + "cycles": (PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES), + "instructions": (PERF_TYPE_HARDWARE, PERF_COUNT_HW_INSTRUCTIONS), + "ref-cycles": (PERF_TYPE_HARDWARE, PERF_COUNT_HW_REF_CPU_CYCLES), + "cache-references": (PERF_TYPE_HARDWARE, PERF_COUNT_HW_CACHE_REFERENCES), + "cache-misses": (PERF_TYPE_HARDWARE, PERF_COUNT_HW_CACHE_MISSES), + "branch-instructions": (PERF_TYPE_HARDWARE, PERF_COUNT_HW_BRANCH_INSTRUCTIONS), + "branches": (PERF_TYPE_HARDWARE, PERF_COUNT_HW_BRANCH_INSTRUCTIONS), + "branch-misses": (PERF_TYPE_HARDWARE, PERF_COUNT_HW_BRANCH_MISSES), + "bus-cycles": (PERF_TYPE_HARDWARE, PERF_COUNT_HW_BUS_CYCLES), + "stalled-cycles-frontend": (PERF_TYPE_HARDWARE, PERF_COUNT_HW_STALLED_CYCLES_FRONTEND), + "stalled-cycles-backend": (PERF_TYPE_HARDWARE, PERF_COUNT_HW_STALLED_CYCLES_BACKEND), + + "cpu-clock": (PERF_TYPE_SOFTWARE, PERF_COUNT_SW_CPU_CLOCK), + "task-clock": (PERF_TYPE_SOFTWARE, PERF_COUNT_SW_TASK_CLOCK), + "page-faults": (PERF_TYPE_SOFTWARE, PERF_COUNT_SW_PAGE_FAULTS), + "faults": (PERF_TYPE_SOFTWARE, PERF_COUNT_SW_PAGE_FAULTS), + "context-switches": (PERF_TYPE_SOFTWARE, PERF_COUNT_SW_CONTEXT_SWITCHES), + "cs": (PERF_TYPE_SOFTWARE, PERF_COUNT_SW_CONTEXT_SWITCHES), + "cpu-migrations": (PERF_TYPE_SOFTWARE, PERF_COUNT_SW_CPU_MIGRATIONS), + "migrations": (PERF_TYPE_SOFTWARE, PERF_COUNT_SW_CPU_MIGRATIONS), + "minor-faults": (PERF_TYPE_SOFTWARE, PERF_COUNT_SW_PAGE_FAULTS_MIN), + "major-faults": (PERF_TYPE_SOFTWARE, PERF_COUNT_SW_PAGE_FAULTS_MAJ), + "alignment-faults": (PERF_TYPE_SOFTWARE, PERF_COUNT_SW_ALIGNMENT_FAULTS), + "bpf-output": (PERF_TYPE_SOFTWARE, PERF_COUNT_SW_BPF_OUTPUT), + "emulation-faults": (PERF_TYPE_SOFTWARE, PERF_COUNT_SW_EMULATION_FAULTS), + "dummy": (PERF_TYPE_SOFTWARE, PERF_COUNT_SW_DUMMY) +} + + +def perf_event_name(etype, ecode): + if etype == PERF_TYPE_HW_CACHE: + return hw_cache_event_name(ecode) + ls = [] + for e in perf_event_map: + (type, code) = perf_event_map[e] + if type == etype and code == ecode: + ls.append(e) + return " OR ".join(ls) + +assert perf_event_name(PERF_TYPE_HARDWARE, PERF_COUNT_HW_CPU_CYCLES) == "cpu-cycles OR cycles" + + +# This list must match perf_hw_cache_id in the kernel +hw_cache_types = [ "L1-dcache", "L1-icache", "LLC", "dTLB", "iTLB", "branch", "node"] + +def hw_cache_event_name(code): + """ + Given a cache event encoding, return the name. + This doesn't indicate that the event is supported on the target. + """ + cix = code & 0xff + aix = (code >> 8) & 0xff + rix = (code >> 16) & 0xff + try: + aname = ["load", "store"][aix] + rname = ["s", "-misses"][rix] + return "%s-%s%s" % (hw_cache_types[cix], aname, rname) + except IndexError: + return None + + +def hwcc(cix, aix, rix): + # form the code from the cache type, access type and result + return cix + (aix<<8) + (rix<<16) + + +def hw_cache_event_code(s): + """ + Given an event name (such as "LLC-load-misses"), + check if it's a cache event, and if so, return the encoding. + This doesn't indicate that the event is supported on the target. + """ + for (cix, ctype) in enumerate(hw_cache_types): + if s.startswith(ctype + "-"): + s = s[len(ctype)+1:] + if s == "loads": + return hwcc(cix,PERF_COUNT_HW_CACHE_OP_READ,PERF_COUNT_HW_CACHE_RESULT_ACCESS) + elif s == "stores": + return hwcc(cix,PERF_COUNT_HW_CACHE_OP_WRITE,PERF_COUNT_HW_CACHE_RESULT_ACCESS) + elif s == "load-misses": + return hwcc(cix,PERF_COUNT_HW_CACHE_OP_READ,PERF_COUNT_HW_CACHE_RESULT_MISS) + elif s == "store-misses": + return hwcc(cix,PERF_COUNT_HW_CACHE_OP_WRITE,PERF_COUNT_HW_CACHE_RESULT_MISS) + else: + return None + return None + + +def hw_cache_event_codes(): + """ + Enumerate the possible HW cache event codes, in the same order as + perf list cache + This does not indicate whether the events are supported on the target. + """ + for cix in range(0, len(hw_cache_types)): + for aix in range(0, 2): + for rix in range(0, 2): + yield hwcc(cix, aix, rix) + + +branch_sample_types = { + "any": PERF_SAMPLE_BRANCH_ANY, + "any_call": PERF_SAMPLE_BRANCH_ANY_CALL, + "any_ret": PERF_SAMPLE_BRANCH_ANY_RETURN, + "ind_jmp": PERF_SAMPLE_BRANCH_IND_JUMP, # not documented + "ind_call": PERF_SAMPLE_BRANCH_IND_CALL, # documented as 'any indirect branch' + "call": PERF_SAMPLE_BRANCH_CALL, + "u": PERF_SAMPLE_BRANCH_USER, + "k": PERF_SAMPLE_BRANCH_KERNEL, + "hv": PERF_SAMPLE_BRANCH_HV, + "in_tx": PERF_SAMPLE_BRANCH_IN_TX, + "no_tx": PERF_SAMPLE_BRANCH_NO_TX, + "abort_tx": PERF_SAMPLE_BRANCH_ABORT_TX, + "cond": PERF_SAMPLE_BRANCH_COND, +} + + +def branch_sample_type(s): + st = 0 + for bf in s.split(','): + if bf in branch_sample_types: + st |= branch_sample_types[bf] + else: + print("** unknown branch sample type: '%s'" % bf) + return st + + +def is_hex(s): + try: + n = int(s, 16) + return True + except ValueError: + return False + + +def parameter_map(flist): + """ + Convert a list of "a=v" strings into a Python map + """ + fmap = {} + for f in flist: + if not f: + # a blank - either "subsys//" or extra comma + continue + # it's either "field=x" or just "field" + if '=' in f: + (field, value) = f.split('=') + else: + field = f + value = "1" # single-bit field, e.g. "inv" on x86_64 + assert field # should look like an identifier + # validate 'value'? should it be a hex number? + fmap[field] = value + return fmap + +assert parameter_map([""]) == {} +assert parameter_map(["a=1"]) == {"a": "1"} +assert parameter_map(["a=1","b=2"]) == {"a": "1", "b": "2"} + +# standard fields in the event config (perf_event_attr). +# Individual event groups may add additional names for subfields. +predefined_fields = [ + "config", + "config1", + "config2", + "name", + "period", + "freq", + "branch-type", + "time", + "call-graph", + "stack-size", + "no-inherit", + "inherit", + "max-stack", + "nr", + "overwrite", + "no-overwrite", + "driver-config", + "percore", + "aux-output", +] + +class EventConfig: + """ + An 'event configuration' object represents, basically, a single event, + but one that might be collected across multiple CPUs and threads. + The -e argument to perf may specify one or more of these events. + The event configuration specifies, directly or by reference to + events in predefined lists and in sysfs, the perf_event_attr structure + passed to perf_event_open, but also other fields used by the userspace tool. + It may also indicate filtering, e.g. to kernel and/or userspace. + At measurement time, there might be multiple perf_events for this event + specification, one per CPU. + + If errors occurred when parsing the event, an EventConfig object will be + constructed with is_valid() false, and error messages logged in error_log. + """ + def __init__(self, e=None): + if e is not None: + self.configure(e) + else: + self.reset() + + def is_simple(self): + """ + Return true if the event has not been modified with suffixes, extra parameters etc. + """ + return self.attr.config1 == 0 and \ + self.attr.config2 == 0 and \ + (not self.modifiers) and \ + (not self.extra_modifiers) and \ + (not self.space) and \ + self.attr.precise_ip == 0 and \ + self.attr.bp_type is None and \ + self.cpumask is None + + def reset(self): + self.error_log = [] + self.attr = PerfEventAttr() + self.attr._set_all_valid() + self.scale = None + self.unit = None + self.cpumask = None + self.modifiers = "" + self.extra_modifiers = "" + self.PMU = None # a SysPMU object + + def configure(self, e, quiet=False): + """ + Configure this descriptor object from an event specifier string. + """ + self.reset() + # Fields for perf_event_attr + self.attr.type = None # e.g. PERF_TYPE_HARDWARE + self.attr.config = None # e.g. PERF_COUNT_HW_CPU_CYCLES + self.attr.config1 = 0 + self.attr.config2 = 0 + self.attr.bp_type = None + self.attr.inherit = None + if True: + # By default, in the perf tool, events get these exclusions. + self.attr.exclude_hv = 1 + self.attr.exclude_guest = 1 + # Fields outside perf_event_attr + self.perf_call_graph = None # a string + self.name = e + # If any inclusion specifiers out of "ukh" are specified, the rest are excluded. + # Similarly for "GH" (guest and host). + self.space = "" # from "u", "k", "h" and also "G", "H" + # Any event may have generic modifiers like 'k' for kernel. + # But tracepoint events are specified as + # abc:xyz + # So we don't know whether a :xyz suffix is a generic modifier or not, + # until after we've processed the event. Split the event spec into + # colon-separated segments - any event can then consume a segment by + # incrementing eix, leaving generic modifiers to be processed at the end. + espec = e.split(':') + e = espec[0] + eix = 0 + if e.find('/') > 0: + ix = e.find('/') + mix = e.rfind('/') + if ix == mix: + self.report("bad event: '%s'" % e) + event_base = e[:ix] + event_parameters = e[ix+1:mix].split(',') + emods = e[mix+1:] + if emods: + espec.insert(1, emods) + else: + event_base = e + event_parameters = [] + if e.startswith("r") and is_hex(e[1:]): + # "-e race" should be valid, equivalent to "-e r0ace" + self.attr.update(type=PERF_TYPE_RAW, config=int(e[1:],16)) + elif event_base in perf_event_map: + # a named event, e.g. "instructions" + self.setup(perf_event_map[event_base]) + # apply generic event parameters e.g. 'config=0x12' + pars = parameter_map(event_parameters) + for p in pars: + self.set_generic_parameter(p, pars[p]) + elif e.startswith("PERF_COUNT_") and e in globals(): + # perf_event.h constants - our extension + if e.startswith("PERF_COUNT_HW_"): + self.setup(PERF_TYPE_HARDWARE, globals()[e]) + elif e.startswith("PERF_COUNT_SW_"): + self.setup(PERF_TYPE_SOFTWARE, globals()[e]) + elif event_parameters: + # custom event in some event subsystem + # e.g. "cpu/branch-instructions/" + subsys = event_base # e.g. "cpu" + spec = event_parameters + pmu_type = system_pmu_type(subsys) + if pmu_type is None: + if not quiet: + self.report("unknown hardware PMU: '%s'" % subsys) + return + self.attr.type = pmu_type + self.PMU = SysPMU(subsys) + self.cpumask = self.PMU.cpumask() + self.attr.config = 0 + self.attr.config1 = 0 + self.attr.config2 = 0 + # look to see if this is a named event + event_name = event_parameters[0] # may be empty string + must_specify_fields = [] + if self.PMU.has_named_events() and event_name.find("=") == -1: + event_specifier = self.PMU.event_specifier(event_name) + if event_specifier is not None: + # this is a named event + self.scale = self.PMU.event_scale(event_name) + self.unit = self.PMU.event_unit(event_name) + event_fields = parameter_map(event_specifier.split(',')) + event_spec = parameter_map(event_parameters[1:]) + # iterate over the predefined or required parameters + for e in event_fields: + if event_fields[e] == "?": + if e in event_spec: + # user supplied a value for this expected parameter + event_fields[e] = event_spec[e] + else: + self.report("missing field '%s' for event '%s'" % (e, event_name)) + else: + if e in event_spec: + self.report("event '%s=%s' already has '%s=%s', not expecting '%s'" % (event_name, e, event_fields[e], e, event_spec[e])) + # add in other supplied parameters + for e in event_spec: + event_fields[e] = event_spec[e] + else: + if not quiet: + self.report("subsystem '%s' does not have event '%s'" % (subsys, event_name)) + self.report("available events: %s" % (", ".join(PMU.event_names()))) + else: + # subsystem has no named events, or event is specified entirely by fields + event_fields = parameter_map(event_parameters) + # for each custom field specified by the user, use the event's + # format specification (if present) to see how it maps on to + # the 'config' fields of the perf_event_open structure. + # some subsystems (e.g. intel-bts//) don't have a format. + for e in event_fields: + vals = event_fields[e] # user-specified or defaulted value + try: + # values are always hex + value = int(vals, 0) + except ValueError: + value = None + if e in predefined_fields: + self.set_generic_parameter(e, vals, value, merge=True) + elif e[0] == '@' and subsys == "cs_etm": + # Sink specifier for CoreSight ETM + sink_dir = "/sys/devices/" + subsys + "/sinks" + assert os.path.isdir(sink_dir), "CoreSight sinks not available" + sp = sink_dir + "/" + e[1:] + if os.path.exists(sp): + value = utils.file_hex(sp) + self.set_custom_parameter("sinkid", value) # somewhere in config2 + else: + print("unknown %s sink: '%s', available sinks are %s" % (subsys, e[1:], list(os.listdir(sink_dir))), file=sys.stderr) + continue + else: + self.set_custom_parameter(e, value) + if False: + print("Raw event: %s" % self) + elif e == "mem" and (len(espec) == 2 or len(espec) == 3): + self.attr.update(type=PERF_TYPE_BREAKPOINT, config=0, bp_addr=int(espec[1],0), bp_len=8) + bp_type = HW_BREAKPOINT_RW + if len(espec) == 3: + bp_type = HW_BREAKPOINT_EMPTY + for c in espec[2]: + if c == 'r': + bp_type |= HW_BREAKPOINT_R + elif c == 'w': + bp_type |= HW_BREAKPOINT_W + elif c == 'x': + bp_type |= HW_BREAKPOINT_X + else: + # actually I think perf just fails here + self.report("breakpoint syntax error: %s" % espec[2]) + self.attr.bp_type = bp_type + return + elif len(espec) == 2: + # could be "sched:sched_switch" or "cache_misses:u" + evid = tracepoint_id(espec[0], espec[1]) + if evid is not None: + self.attr.type = PERF_TYPE_TRACEPOINT + self.attr.config = evid + return # don't do colon-separated modifiers + else: + self.report("unknown or inaccessible tracepoint event: %s (%s)" % (e, espec)) + return + else: + hwcc = hw_cache_event_code(e) + if hwcc is not None: + self.attr.update(type=PERF_TYPE_HW_CACHE, config=hwcc) + else: + # See if this is a cpu event, e.g. "cpu-clock" + # This will only work if /sys/bus/event_source/devices/cpu exists + # It might not exist on ARM systems where CPU PMUs are named e.g. armv8_pmuv3_0 + try: + self.configure("cpu/" + e + "/", quiet=True) + return + except Exception: + self.name = e # restore + pass + # See if this is in the JSON file (our extension) + try: + pmu = PMUdesc.PMUdesc_first() + p = pmu["by_name"][e] + self.attr.type = PERF_TYPE_RAW + self.attr.config = PMUdesc.Intel_config(p) + return + except Exception: + pass + self.report("unknown event: %s" % e) + return + # Process any unused colon-separated segments or g/e/m trailing modifiers. + if len(espec) > eix: + self.modifiers = ''.join(espec[eix+1:]) + # For event modifiers, see perf list --help + for c in self.modifiers: + if c == 'p': + self.attr.precise_ip += 1 + elif c == 'P': + self.attr.precise_ip = PRECISE_MAX + elif c in "ukhGH": + self.space += c + elif c == 'I': + self.attr.exclude_idle = True + elif c == 'D': + self.attr.pinned = True + elif c == 'S': + self.attr.sample_type |= PERF_SAMPLE_READ + else: + self.report("event has invalid modifier suffix '%s': \"%s\"" % (c, e)) + self.extra_modifiers += c + + def setup(self, ptype_config): + # parameter is a tuple: see PEP-3113 + (self.attr.type, self.attr.config) = ptype_config + + def set_custom_parameter(self, e, value=None): + if value is None: + value = 1 + format = self.PMU.field_format(e) + if format is None: + self.report("event %s// unknown field '%s'" % (self.PMU.pmu_name, e)) + self.report("valid fields: %s" % ",".join(self.PMU.field_names() + predefined_fields)) + return False + (struct_field, range) = format + assert struct_field in ["config", "config1", "config2"] + if range.find('-') >= 0: + (rlo, rhi) = range.split('-') + rlo = int(rlo) + rhi = int(rhi) + width = (rhi - rlo) + 1 + else: + # single-bit field + rlo = int(range) + rhi = rlo + width = 1 + maxval = (1 << width) - 1 + if value > maxval: + print("value %u/%x is out of range, max value is %u/%x" % (value, value, maxval, maxval), file=sys.stderr) + value &= maxval + value <<= rlo + self.set_generic_parameter(struct_field, None, value, merge=True) + return True + + def set_generic_parameter(self, p, svalue, value=None, merge=False): + """ + Set a generic parameter, e.g. + perf stat -e cs/config2=123/ + From "perf help record": + "There are also some params which are not defined in + ...//format/* ..." + """ + if value is None: + try: + value = int(svalue, 0) + except ValueError: + value = None + if o_verbose: + print("set generic parameter '%s' adds 0x%x" % (p, value)) + if p == "config": + if merge: + self.attr.config |= value + else: + self.attr.config = value + elif p == "config1": + if merge: + self.attr.config1 |= value + else: + self.attr.config1 = value + elif p == "config2": + if merge: + self.attr.config2 |= value + else: + self.attr.config2 = value + elif p == "name": + self.name = svalue + elif p == "period": + self.attr.sample_period = value + elif p == "freq": + self.attr.sample_freq = value + elif p == "time": + if value: + self.attr.sample_type |= PERF_SAMPLE_TIME + else: + self.attr.sample_type &= ~PERF_SAMPLE_TIME + elif p == "call-graph": + self.attr.sample_type |= PERF_SAMPLE_CALLCHAIN + self.perf_call_graph = svalue + elif p == "stack-size": + self.attr.stack_user = value + elif p == "no-inherit": + self.attr.inherit = False + elif p == "inherit": + self.attr.inherit = True + else: + self.report("unexpected generic parameter: %s=%s" % (p, svalue)) + self.report("valid terms: config,config1,config2,name,period,freq") + + def is_valid(self): + if self.error_log: + return False + if self.attr.config is None: + return False + if self.attr.type is None: + return False + return True + + def report(self, s): + self.error_log.append(s) + print(s, file=sys.stderr) + + def show_raw(self): + print("Event:") + for f in self.__dict__: + print(" %15s: %s" % (f, self.__dict__[f])) + + def has_space(self, spc): + return (self.space == "") or (spc in self.space) + + def __str__(self): + """ + Return a string with a basic definition of the event. + """ + if self.attr.type is None: + return "" + if self.is_simple(): + if self.attr.type == PERF_TYPE_HW_CACHE: + s = hw_cache_event_name(self.attr.config) + if s is not None: + return s + for name in perf_event_map: + if (self.attr.type, self.attr.config) == perf_event_map[name]: + return name + if self.attr.type == PERF_TYPE_RAW: + return "r%x" % self.attr.config + pmu_name = pmu_name_by_type(self.attr.type) + if pmu_name is not None: + s = "%s/" % pmu_name + else: + s = "/type=%u," % self.attr.type + s += "config=0x%x" % (self.attr.config) + if self.attr.config1: + s += ",config1=0x%x" % (self.attr.config1) + if self.attr.config2: + s += ",config2=0x%x" % (self.attr.config2) + s += "/" + if self.cpumask: + s += " (cpumask=0x%x)" % self.cpumask + return s + + +def event(e): + return EventConfig(e) + + +def events(event_spec): + """ + Parse a list of (possibly grouped) events and return + a list of (possibly grouped) EventConfig objects. + """ + espec_groups = perf_parse.perf_parse(event_spec) + egs = [] + for g in espec_groups: + el = [event(es) for es in g] + egs.append(el) + return egs + + +def _test_perf_list_events(): + """ + Check that we recognize all the events listed by "perf list" + """ + print("Checking we recognize all 'perf list' events...") + os.system("perf list >perf_list.out") + n_tested = 0 + f = open("perf_list.out") + in_sqb = False + for ln in f: + if not ln: + continue + if ln[0] != ' ': + continue + ln = ln.strip() + if in_sqb: + if ln.find(']') >= 0: + in_sqb = False + continue + # Deal with the latter half of "perf list", which lists events together + # with detailed descriptions in square brackets, possibly split across lines. + etix = ln.find("[") + if etix >= 0 and ln.find(']') < 0: + in_sqb = True + continue + if etix >= 0: + ln = ln[:etix] + evs = ln.strip() + if not evs: + continue + if evs == "rNNN" or evs == "mem:": + # Hard-coded wildcards in "perf list" output - ignore + continue + #print("EVS: %s" % evs) + evs = evs.split(" OR ") + for (i, e) in enumerate(evs): + try: + c = event(e) + if c.is_valid(): + print(" %s -> %s" % (e, c)) + else: + print("- %s" % (e)) + except Exception: + print("failed to parse: \"%s\"" % e, file=sys.stderr) + raise + n_tested += 1 + # You'd think that if "perf list" lists an event as "x OR y", + # it would end up being the same event for perf_event_open. + # But this isn't the case. E.g. + # branch-instructions OR cpu/branch-instructions/ + # maps to + # PERF_TYPE_HARDWARE / PERF_COUNT_HW_BRANCH_INSTRUCTIONS + # vs. (on x86_64): + # PERF_TYPE_RAW / 0xC4 + continue + if i == 0: + cbase = c + else: + assert str(c) == str(cbase), "%s: %s vs %s" % (ln, cbase, c) + f.close() + print("perf list test: %u tested" % n_tested) + + +def test_event(spec, **kwargs): + """ + Test an event string produces the same result as an event built from keywords. + """ + e = event(spec) # Build from the event specifier string + attr = PerfEventAttr(**kwargs) # Build from the parameters + attr._set_all_valid() + if e.attr != attr: + print("Mismatch for '%s':" % (spec)) + print(" string: %s" % (e.attr)) + print(" direct: %s" % (attr)) + + +def test(): + print("simple tests...") + e = event("instructions") + assert e.attr.type == PERF_TYPE_HARDWARE and e.attr.config == PERF_COUNT_HW_INSTRUCTIONS + e = event("r010") + assert e.attr.type == PERF_TYPE_RAW and e.attr.config == 16 + test_event("r010", type=PERF_TYPE_RAW, config=0x10) + # examples from http://www.brendangregg.com/perf.html + e = event("block:block_rq_issue") + el = events("cycles,instructions,cache-references,cache-misses,bus-cycles") + el = events("L1-dcache-loads,L1-dcache-load-misses,L1-dcache-stores") + el = event("r003c") + if pmu_exists("cpu"): + test_event("cpu/config=0x45/pp", type=PERF_TYPE_RAW, config=0x45, precise_ip=2) + el = event("cpu/event=0x0e,umask=0x01,inv,cmask=0x01/") + test_event("cpu/config2=0x123/", type=PERF_TYPE_RAW, config2=0x123) + else: + print("'cpu/xxx/' events not supported") + e = event("raw_syscalls:sys_inter") + e = event("cpu-clock") + e = event("dummy:u") + assert e.attr.type == PERF_TYPE_SOFTWARE and e.attr.config == PERF_COUNT_SW_DUMMY + e = event("cycles") + assert e.has_space("u") + e = event("cycles:k") + assert e.space == "k" + assert e.has_space("k") + assert not e.has_space("u") + e = event("cycles:u") + assert e.space == "u" + assert e.has_space("u") + assert e.attr.precise_ip == 0 + e = event("cycles:up") + assert e.space == "u" + assert e.attr.precise_ip == 1 + test_event("r01cb:pp", type=PERF_TYPE_RAW, config=0x1cb, precise_ip=2) + e = event("cache-misses:S") + assert (e.attr.sample_type & PERF_SAMPLE_READ) != 0 + el = events("{cycles,cache-misses}:S") + assert len(el[0]) == 2 + e = event("sched:sched_process_exec") + el = events("syscalls:sys_enter_accept*") + e = event("minor-faults") + e = event("probe:tcp_sendmsg") + # these don't work... is max-stack supposed to be a generic perf_event_attr field? + e = event("cpu-clock/max-stack=2/") + e = event("cs/max-stack=5/") + print("simple tests done") + e = event("INST_RETIRED.ANY") + e = event("INST_RETIRED.ANY_P") + _test_perf_list_events() + print("all tests done") + + +if __name__ == "__main__": + import sys + if len(sys.argv) > 1: + for arg in sys.argv[1:]: + if arg == "-v": + o_verbose += 1 + else: + config = event(arg) + print(config) + else: + perf_parse.test() + test() + diff --git a/linux_app/pmu_app/pyperf/pyperf/perf_parse.py b/linux_app/pmu_app/pyperf/pyperf/perf_parse.py new file mode 100644 index 00000000..8e6ce771 --- /dev/null +++ b/linux_app/pmu_app/pyperf/pyperf/perf_parse.py @@ -0,0 +1,119 @@ +# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# SPDX-License-Identifier : Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" +Parse a list of perf events as used in the -e argument to 'perf stat'. + +The output is a list of lists. Each item in the top-level list is a group +of events to be monitored concurrently, corresponding to the +curly braces specification in -e. If there are no groups in the input, +the output is a list of singleton lists. + +This module deals only with syntax. It does not validate or resolve +the event strings against the events exposed in sysfs. + +In particular, this module does not expand wildcarded event names. +Singletons in the list may become multiples after expansion. +""" + +from __future__ import print_function + +def perf_parse(s): + if not s: + return [] + if s[0] == ',': + return perf_parse(s[1:]) + if s[0] == '{': + kix = s.find('}') + assert kix >= 0, "%s: missing closing brace" % s + # we could also check that kix is followed by comma or EOS or a suffix valid for a group + group = perf_parse(s[1:kix]) + suffix = "" + if s[kix+1:].startswith(':'): + # there's a suffix for the whole group: capture it and apply it to each event + cix = s[kix+1].find(",") + if cix >= 0: + suffix = s[kix+1:kix+1+cix] + kix += cix + else: + suffix = s[kix+1:] + kix += len(suffix) + assert suffix.startswith(":") + def flatten(x, suffix): + for sublist in x: + for item in sublist: + yield item + suffix + return [list(flatten(group, suffix))] + perf_parse(s[kix+1:]) + cix = s.find(",") + six = s.find("/") + if six >= 0 and (cix < 0 or six < cix): + # next token has an opening slash - look for the closing slash + csix = s[six+1:].find("/") + assert csix >= 0, "%s: missing trailing slash" % s + csix += six + 1 + cix = s[csix+1:].find(",") + if cix >= 0: + cix += csix + 1 + if cix < 0: + # only one item left + return [[s]] + return [[s[:cix]]] + perf_parse(s[cix+1:]) + + + +""" +Unit tests +""" + +def test_perf_parse(s, ls_expected): + try: + ls_got = perf_parse(s) + except Exception: + if ls_expected is not None: + print("failed: %s -> Exception" % s) + return + assert ls_got == ls_expected, "failed: %s -> %s, expected %s" % (s, ls_got, ls_expected) + + +perf_parse_tests = [ + ( "", [] ), + ( "a", [["a"]] ), + ( "a,", [["a"]] ), + ( "a,b", [["a"], ["b"]] ), + ( "{a,b}", [["a","b"]] ), + ( "{cyc,cyc}", [["cyc","cyc"]] ), + ( "{a,b},c", [["a","b"], ["c"]] ), + ( "{a,b},{c,d}", [["a","b"], ["c","d"]] ), + ( "a,,b", [["a"], ["b"]] ), + ( "a,b/c,d/,e", [["a"], ["b/c,d/"], ["e"]] ), + ( "a,b/cd/,e", [["a"], ["b/cd/"], ["e"]] ), + ( "a,b/c,d/m,e", [["a"], ["b/c,d/m"], ["e"]] ), + ( "a,b/cd/m,e", [["a"], ["b/cd/m"], ["e"]] ), + ( "a:u,b:k", [["a:u"], ["b:k"]] ), + ( "{a,b}:S", [["a:S", "b:S"]] ), # TBD is this the right thing to do? + # broken cases + ( "{a", None ), +# ( "a}", None ), + ( "a,b/c,d", None ), +] + + +def test(): + for (s,ls) in perf_parse_tests: + test_perf_parse(s,ls) + +if __name__ == "__main__": + test() + diff --git a/linux_app/pmu_app/pyperf/pyperf/perf_sysfs.py b/linux_app/pmu_app/pyperf/pyperf/perf_sysfs.py new file mode 100644 index 00000000..4843a9ae --- /dev/null +++ b/linux_app/pmu_app/pyperf/pyperf/perf_sysfs.py @@ -0,0 +1,251 @@ +# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# SPDX-License-Identifier : Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" +This module interfaces to the PMU event descriptions in sysfs. +""" + +from __future__ import print_function + +import perf_util as utils + +import os + +sysfs_pmus_dir = "/sys/bus/event_source/devices" + +def debugfs_dir(): + debugfs = "/sys/kernel/debug" + assert os.path.isdir(debugfs) + return debugfs + + +def _file_scale(fn): + """ + Read a scale factor. This may be a floating-point number, e.g. for converting power readings. + """ + s = utils.file_word(fn) + try: + n = int(s, 0) + except ValueError: + n = float(s) + return n + + +def field_values(s): + """ + Iterate through an event specifier of the form "a=v,b=w" + """ + if s: + for f in s.split(','): + if f.find('=') > 0: + (field, value) = f.split('=') + else: + field = f + value = None + yield (field, value) + + +assert list(field_values("")) == [] +assert list(field_values("a=123,e=?,c,b=0x2")) == [("a","123"),("e","?"),("c",None),("b","0x2")] + + +def pmu_exists(pmu_name): + # Test whether a PMU exists e.g. "cpu", "software", "cs_etm". + return os.path.exists(os.path.join(sysfs_pmus_dir, pmu_name)) + + +class SysPMU(object): + """ + Describes a "PMU" in the kernel sense - corresponding to a value of perf_event_attr.type. + Standard PMUs include: + "software": PERF_TYPE_SOFTWARE + "tracepoint": PERF_TYPE_TRACEPOINT + "cpu": PERF_TYPE_RAW # possibly not on Arm big.LITTLE + """ + def __init__(self, name): + self.pmu_name = name + self.pmu_dir = os.path.join(sysfs_pmus_dir, name) + self.events_dir = os.path.join(self.pmu_dir, "events") + self.format_dir = os.path.join(self.pmu_dir, "format") + + @property + def type(self): + return utils.file_int(os.path.join(self.pmu_dir, "type")) + + def field_names(self): + if os.path.isdir(self.format_dir): + return os.listdir(self.format_dir) + else: + return [] + + def field_format(self, field): + # Get the destination of a field: something like "config:0-7" + format_file = os.path.join(self.format_dir, field) + if os.path.isfile(format_file): + format = utils.file_word(format_file) + (attr, pos) = format.split(':') + assert attr in ["config", "config1", "config2"] + return (attr, pos) + else: + return None + + def cpumask(self): + # Some PMUs must have their events opened on specific CPUs. + cpumask_file = os.path.join(self.pmu_dir, "cpumask") + if os.path.isfile(cpumask_file): + return utils.cpusetstr_mask(utils.file_word(cpumask_file)) + else: + return None + + @property + def nr_addr_filters(self): + try: + return utils.file_int(os.path.join(self.pmu_dir, "nr_addr_filters")) + except IOError: + return 0 + + def has_named_events(self): + return os.path.isdir(self.events_dir) + + def event_names(self): + if os.path.isdir(self.events_dir): + for p in os.listdir(self.events_dir): + if not (p.endswith(".scale") or p.endswith(".unit")): + yield p + else: + pass # do not yield anything + + def event_specifier(self, event_name): + """ + The event specifier is a string assigning values to event fields defined for this PMU. + E.g. "a=1,b=2" where a and b are named fields. + The special syntax "a=?" indicates that the user must specify a value for "a". + """ + event_file = os.path.join(self.events_dir, event_name) + if os.path.isfile(event_file): + return utils.file_word(event_file) + else: + return None + + def event_scale(self, event_name): + event_scale_file = os.path.join(self.events_dir, event_name + ".scale") + if os.path.isfile(event_scale_file): + return _file_scale(event_scale_file) + else: + return None + + def event_unit(self, event_name): + event_unit_file = os.path.join(self.events_dir, event_name + ".unit") + if os.path.isfile(event_unit_file): + return utils.file_word(event_unit_file) + else: + return None + + +def system_pmu_type(pmu_name): + """ + Given a PMU name like "cpu", "cs_etm", "software", return the type number. + Return None if this is not a valid PMU name. + """ + if pmu_exists(pmu_name): + return SysPMU(pmu_name).type + else: + return None + + +def system_pmu_names(sorted_by_type=False): + if sorted_by_type: + m = {} + for pmu_name in system_pmu_names(): + m[system_pmu_type(pmu_name)] = pmu_name + for pmu_type in sorted(m.keys()): + yield m[pmu_type] + else: + for pmu_name in os.listdir(sysfs_pmus_dir): + yield pmu_name + + +def pmu_name_by_type(n): + for pmu_name in system_pmu_names(): + if SysPMU(pmu_name).type == n: + return pmu_name + return None + + +def tracepoint_group_dir(egroup): + events = debugfs_dir() + "/tracing/events" + egdir = "%s/%s" % (events, egroup) + if not os.path.isdir(egdir): + return None + return egdir + + +def tracepoint_id(egroup, event=None): + evid = None + if event is None: + ix = egroup.index(':') + event = egroup[ix+1:] + egroup = egroup[:ix] + edir = "%s/%s" % (tracepoint_group_dir(egroup), event) + if os.path.isdir(edir): + evid = int(utils.file_str(edir + "/id")) + return evid + + +def test(): + if pmu_exists("cpu"): + assert system_pmu_type("cpu") == 4 # PERF_TYPE_RAW + assert pmu_name_by_type(4) == "cpu" + else: + pass # likely Arm big.LITTLE + + +if __name__ == "__main__": + import argparse + parser = argparse.ArgumentParser(description="test finding PMU info from sysfs") + parser.add_argument("--detail", action="store_true", help="show details one per line") + opts = parser.parse_args() + for pmu_name in system_pmu_names(sorted_by_type=True): + P = SysPMU(pmu_name) + print("%2u: %-20s in %s" % (P.type, P.pmu_name, P.pmu_dir)) + cpumask = P.cpumask() + if cpumask is not None: + print(" CPU mask: %s" % utils.mask_cpusetstr(cpumask)) + if P.nr_addr_filters: + print(" Address filters: %u" % P.nr_addr_filters) + if P.field_names(): + if opts.detail: + print(" Fields:") + for field_name in P.field_names(): + print(" %24s: %s" % (field_name, P.field_format(field_name))) + else: + print(" Fields: %s" % (','.join(P.field_names()))) + if P.has_named_events(): + if opts.detail: + print(" Named events:") + for event_name in P.event_names(): + es = P.event_specifier(event_name) + print(" %24s: %s" % (event_name, es), end="") + s = P.event_scale(event_name) + if s is not None: + print(" *%s" % s, end="") + u = P.event_unit(event_name) + if u is not None: + print(" %s" % u, end="") + print() + else: + print(" Named events: %s" % (','.join(P.event_names()))) + test() + diff --git a/linux_app/pmu_app/pyperf/pyperf/perf_util.py b/linux_app/pmu_app/pyperf/pyperf/perf_util.py new file mode 100644 index 00000000..d7908c11 --- /dev/null +++ b/linux_app/pmu_app/pyperf/pyperf/perf_util.py @@ -0,0 +1,282 @@ +# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# SPDX-License-Identifier : Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" +Utility routines for various perf-related tools. + +Mostly related to string conversion, e.g. + - memory sizes, like "64K" + - CPU lists, like "1-3,5" +""" + +from __future__ import print_function + +import os + + +def str_memsize(s): + """ + Turn "2K" into 2048. + Can be used with 'type=' in argparse. + """ + assert s != "" + if s[-1] in "bB": + s = s[:-1] + if s.endswith("K"): + return int(float(s[:-1])*1024) + if s.endswith("M"): + return int(float(s[:-1])*1024*1024) + if s.endswith("G"): + return int(float(s[:-1])*1024*1024*1024) + if s.endswith("T"): + return int(float(s[:-1])*1024*1024*1024*1024) + return int(s) + + +assert str_memsize("2K") == 2048 +assert str_memsize("1.5K") == 1536 + + +def memsize_str(n, B="", unit=None): + """ + Turn 2048 into "2K" + We print fractional values as floating-point, but expect + them to be a small number of decimal places. This is + basically aimed at printing round values like cache sizes. + """ + fmt = "%g" + if unit == "T" or (unit is None and n >= 1024*1024*1024*1024): + s = (fmt + "T") % (n/1024.0/1024/1024/1024) + elif unit == "G" or (unit is None and n >= 1024*1024*1024): + s = (fmt + "G") % (n/1024.0/1024/1024) + elif unit == "M" or (unit is None and n >= 1024*1024): + s = (fmt + "M") % (n/1024.0/1024) + elif unit == "K" or (unit is None and n >= 1024): + s = (fmt + "K") % (n/1024.0) + else: + if not B: + B = "b" + s = "%u" % (n) + s = s + B + return s + + +assert memsize_str(0) == "0b" +assert memsize_str(1) == "1b" +assert memsize_str(2048) == "2K" +assert memsize_str(1536) == "1.5K" +assert memsize_str(2048*1024, "B") == "2MB" +assert memsize_str(2048*1024, unit="K") == "2048K" + +def test_memsize(): + import random + for i in range(10000): + se = random.randrange(10000) + sl = random.randrange(12) + m = se << sl + ms = memsize_str(m) + sm = str_memsize(ms) + if sm != m: + d = (float(sm) / float(m)) + assert d >= 0.999 and d <= 1.001, "mem fail: %u -> \"%s\" -> %u" % (m, ms, sm) + + +def intmask_list(n): + """ + Given an integer mask, return a list of numbers in + ascending order, corresponding to the bits set. + """ + c = [] + for i in range(0, 1000): + if (n & (1<= 1: + stride = 1 + if allow_stride: + strix = s.find(':') + if strix != -1: + stride = int(s[strix+1:]) + s = s[:strix] + [a,b] = s.split('-') + for c in range(int(a),int(b)+1,stride): + yield int(c) + else: + yield int(s) + + +def cpusetstr_list(arg, allow_stride=True): + """ + Given a string specifying a set of CPUs, return the list, + in the original order, and possibly with duplicates. + """ + return list(cpusetstr_iter(arg, allow_stride=allow_stride)) + + +def cpusetstr_mask(arg, allow_stride=True): + """ + Given a string specifying a set of CPUs, return the mask. + """ + cpumask = 0 + for cpu in cpusetstr_iter(arg, allow_stride=allow_stride): + cpumask |= (1 << cpu) + return cpumask + + +assert cpusetstr_mask("3") == 0x08 +assert cpusetstr_mask("1-2,4") == 0x16 +assert cpusetstr_mask("0-31:2") == 0x55555555 + + +def mask_cpusetstr(m): + """ + Turn a CPU mask back into a list. + This should match the rendering of shared_cpu_list in the + sysfs cache topology area. + """ + if m == 0: + return "" + s = "" + i = 0 + while m >= (1 << i): + if (m & (1 << i)) != 0: + if s: + s += "," + s += "%u" % i + if (m & (1 << (i+1))) != 0: + s += "-" + while (m & (1 << i)) != 0: + i += 1 + s += "%u" % (i-1) + else: + i += 1 + else: + i += 1 + return s + + +assert mask_cpusetstr(0x00) == "" +assert mask_cpusetstr(0x01) == "0" +assert mask_cpusetstr(0x16) == "1-2,4" + + +def list_cpusetstr(l): + return mask_cpusetstr(intlist_mask(l)) + +assert list_cpusetstr([]) == "" +assert list_cpusetstr([2,4,8,1,3]) == "1-4,8" + + +def file_str(fn): + """ + For reading sysfs. Return the contents of a file. + """ + with open(fn, "r") as f: + return f.read() + + +def file_word(fn): + """ + For reading sysfs. Return file contents as a stripped token. + """ + return file_str(fn).strip() + + +def file_int(fn): + """ + For reading sysfs. Return integer from a file where it's represented as decimal. + """ + w = file_word(fn) + try: + return int(w) + except ValueError: + assert False, "%s: bad integer value '%s'" % (fn, w) + return None + + +def file_hex(fn): + """ + For reading sysfs. Return integer from a file where it's represented as hex. + """ + w = file_word(fn) + try: + w = ''.join(w.split(',')) + return int(w, 16) + except ValueError: + assert False, "%s: bad hex value '%s'" % (fn, w) + return None + + +def sysctl(p): + """ + Return the value of a system parameter - as a string. + E.g. + sysctl("kernel/osversion") + int(sysctl("kernel/perf_event_paranoid")) + """ + return file_word("/proc/sys/" + p) + + +def pid_tids(pid): + """ + Given a process, get the list of its threads, including itself. + If called with a subthread id, we could either return the list of + the owning process, or we could just return the subthread id as + a singleton. Currently we return the whole list. + """ + def gettgid(tid): + stat = file_str("/proc/%u/status" % tid).split('\n') + assert stat[2].startswith("Tgid:") + tgid = int(stat[2].split()[1].strip()) + return tgid + ls = [] + for d in os.listdir("/proc/%u/task" % pid): + tid = int(d) + ls.append(tid) + return ls + + +if __name__ == "__main__": + import sys + test_memsize() + if len(sys.argv) >= 3 and sys.argv[1] == "tids": + pid = int(sys.argv[2]) + print("process %u tids %s" % (pid, pid_tids(pid))) diff --git a/linux_app/pmu_app/pyperf/pyperf/perf_zstd.py b/linux_app/pmu_app/pyperf/pyperf/perf_zstd.py new file mode 100644 index 00000000..579f66e1 --- /dev/null +++ b/linux_app/pmu_app/pyperf/pyperf/perf_zstd.py @@ -0,0 +1,151 @@ +# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# SPDX-License-Identifier : Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +""" +Wrap libzstd to decode compressed perf.data files. + +We tried the zstd and zstandard modules, and neither handled the compressed +records in perf.data files. +""" + +from __future__ import print_function + +from ctypes import * + + +class ZSTD_inBuffer(Structure): + _fields_ = [("src", c_void_p), ("size", c_size_t), ("pos", c_size_t)] + + +class ZSTD_outBuffer(Structure): + _fields_ = [("dst", c_void_p), ("size", c_size_t), ("pos", c_size_t)] + + +class ZDS: + def __init__(self, Z): + self.Z = Z + self.ds = Z.createDStream() + Z.initDStream(self.ds) + + def processStream(self, output, input): + assert isinstance(input, ZSTD_inBuffer) + assert isinstance(output, ZSTD_outBuffer) + return self.Z.decompressStream(self.ds, addressof(output), addressof(input)) + + def endStream(self, output): + pass + + def __del__(self): + self.Z.freeDStream(self.ds) + + +class ZCS: + def __init__(self, Z): + self.Z = Z + self.cs = Z.createCStream() + Z.initCStream(self.cs) + + def processStream(self, output, input): + assert isinstance(input, ZSTD_inBuffer) + assert isinstance(output, ZSTD_outBuffer) + return self.Z.compressStream(self.cs, addressof(output), addressof(input)) + + def endStream(self, output): + return self.Z.endStream(self.cs, addressof(output)) + + def __del__(self): + self.Z.freeCStream(self.cs) + + +class ZSTD: + """ + Wrap selected functions from the libzstd library + """ + def __init__(self): + self.Z = CDLL("libzstd.so") + self.isError = self.Z.ZSTD_isError + self.isError.argtypes = [c_size_t] + self.isError.restype = c_int + self.createCStream = self.Z.ZSTD_createCStream + self.createCStream.restype = c_void_p + self.createDStream = self.Z.ZSTD_createDStream + self.createDStream.restype = c_void_p + self.initCStream = self.Z.ZSTD_initCStream + self.initCStream.argtypes = [c_void_p] + self.initDStream = self.Z.ZSTD_initDStream + self.initDStream.argtypes = [c_void_p] + self.compressStream = self.Z.ZSTD_compressStream + self.compressStream.argtypes = [c_void_p, c_void_p, c_void_p] + self.compressStream.restype = c_size_t + self.decompressStream = self.Z.ZSTD_decompressStream + self.decompressStream.argtypes = [c_void_p, c_void_p, c_void_p] + self.decompressStream.restype = c_size_t + self.endStream = self.Z.ZSTD_endStream + self.endStream.argtypes = [c_void_p, c_void_p] + self.endStream.restype = c_size_t + self.freeCStream = self.Z.ZSTD_freeCStream + self.freeCStream.argtypes = [c_void_p] + self.freeDStream = self.Z.ZSTD_freeDStream + self.freeDStream.argtypes = [c_void_p] + + def decompress(self, src, ratio=10, compress=False): + src_buf = create_string_buffer(src) + input = ZSTD_inBuffer() + input.src = addressof(src_buf) + input.size = len(src) + input.pos = 0 + dst_size = max(64, len(src) * ratio) + dst = create_string_buffer(dst_size) + output = ZSTD_outBuffer() + output.dst = addressof(dst) + output.size = dst_size + output.pos = 0 + if compress: + s = ZCS(self) + else: + s = ZDS(self) + while input.pos < input.size: + rc = s.processStream(output, input) + if self.isError(rc): + assert False, "error in (de)compressStream" + output.dst = addressof(dst) + output.pos + output.size = dst_size - output.pos + s.endStream(output) + return bytes(dst.raw[:output.pos]) + + def compress(self, src): + return self.decompress(src, ratio=1.1, compress=True) + + +g_ZSTD = ZSTD() + +def decompress(src, ratio=10): + return g_ZSTD.decompress(src, ratio=ratio) + +def compress(src): + return g_ZSTD.compress(src) + + +if __name__ == "__main__": + import argparse + parser = argparse.ArgumentParser(description="test the libzstd wrapper") + parser.add_argument("text", type=str, nargs="+", help="text to decompress") + opts = parser.parse_args() + for s in opts.text: + print("%u -> " % (len(s)), end="") + x = compress(bytes(s)) + print("%u -> " % (len(x)), end="") + d = decompress(x) + print("%u" % (len(d))) diff --git a/linux_app/pmu_app/pyperf/setup.py b/linux_app/pmu_app/pyperf/setup.py new file mode 100644 index 00000000..ff6ef31a --- /dev/null +++ b/linux_app/pmu_app/pyperf/setup.py @@ -0,0 +1,30 @@ +# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# SPDX-License-Identifier : Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +#from setuptools import setup +from distutils.core import setup, Extension + +setup( + name='PyPerf', + author='Al Grant', + author_email='al.grant@arm.com', + packages=['pyperf'], + ext_package='pyperf', + ext_modules=[ + Extension('perf_events', ['src/pyperf_events.c'], extra_compile_args=['-Wall']) + ], + license='Apache 2.0', + description='Python interface to Linux perf events' +) diff --git a/linux_app/pmu_app/pyperf/src/NOTES.txt b/linux_app/pmu_app/pyperf/src/NOTES.txt new file mode 100644 index 00000000..e751b8c3 --- /dev/null +++ b/linux_app/pmu_app/pyperf/src/NOTES.txt @@ -0,0 +1,40 @@ +The code for reading events is complicated. +We have to cope with several cases: + + - reading an event using a read() system call on an event descriptor + - reading a sample out of an mmap() buffer + - reading an event using userspace-readable hardware counters + - reading a group of events in a single action + - returning the difference between the current event values + and values taken at the last reset (see comment at event_reset) + +From the user point of view, the interface is as follows: + + - Event::read() creates and returns a Reading or GroupReading object, + depending on whether the event was opened with PERF_FORMAT_GROUP + + - Record::reading() creates and returns a Reading or GroupReading object + from a sample embedded in a Record of type PERF_RECORD_SAMPLE. + +Internally: + + - event_read(e) + - take_reading(e,NULL) + - allocate reading object r (Reading or GroupReading) + - perf_read_count(r) + - perf_read_count_userspace if possible + - read metadata from mmap page and use rdpmc/mrs + - perf_read_count_using_read otherwise + - read(e->fd) to call the kernel + - for a group, this gets all the readings + - postprocess_reading + + + - data for a single event (a single counter, possibly with + time_enabled/time_running) is captured in event_sample_t + + +-------------- + +*Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.* + diff --git a/linux_app/pmu_app/pyperf/src/pyperf_events.c b/linux_app/pmu_app/pyperf/src/pyperf_events.c new file mode 100644 index 00000000..3fca4569 --- /dev/null +++ b/linux_app/pmu_app/pyperf/src/pyperf_events.c @@ -0,0 +1,3261 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#ifndef _GNU_SOURCE +#define _GNU_SOURCE +#endif + +#ifndef MODULE_NAME +#define MODULE_NAME perf_events +#endif /* !MODULE_NAME */ + +#define MODULE_NAME_STRING3(m) #m +#define MODULE_NAME_STRING2(m) MODULE_NAME_STRING3(m) +#define MODULE_NAME_STRING MODULE_NAME_STRING2(MODULE_NAME) + +#include + +#if PY_MAJOR_VERSION < 3 +/* Provide a function that can create a byte array (whose elements are 'int') + * Some recent Python2 defines PyBytes_FromStringAndSize as an alias of + * PyString_FromStringAndSize but this isn't suitable. */ +#define MyBytes_FromStringAndSize PyByteArray_FromStringAndSize +#define MyBytes_AsString PyByteArray_AsString +#else +/* Python3. Emulate some Python2 API. */ +#define MyBytes_FromStringAndSize PyBytes_FromStringAndSize +#define MyBytes_AsString PyBytes_AsString +#define PyString_FromFormat PyUnicode_FromFormat +#define PyString_AsString PyUnicode_AsUTF8 +#define PyInt_FromLong PyLong_FromLong +#endif +#include + +#include +#include +#include +#include +#include +#include +#include + +/* +Include the system header that defines the layout of the structure passed +to perf_event_open. This must match the kernel version! +*/ +#include +#ifndef PERF_NO_BREAKPOINTS +#include +#endif /* !PERF_NO_BREAKPOINTS */ +#ifndef PERF_AUX_FLAG_COLLISION +#define PERF_AUX_FLAG_COLLISION 0x08 +#endif /* !PERF_AUX_FLAG_COLLISION */ + +#include +#include +#include +#include + + +#define PRINTF_DIAGNOSTICS + + +/* + * Wrap the magic syscall. + */ +static int perf_event_open(struct perf_event_attr *attr, + pid_t pid, int cpu, int group_fd, + unsigned long flags) +{ + return syscall(__NR_perf_event_open, attr, (int)pid, (int)cpu, (int)group_fd, (int)flags); +} + + +#define PERF_FLAG_READ_USERSPACE 0x80000000 /* Read counters from userspace when possible */ +#define PERF_FLAG_NO_READ_USERSPACE 0x40000000 /* Never read counters from userspace */ +#define PERF_FLAG_WEAK_GROUP 0x20000000 /* Fall back to non-membership */ + + +/* + * Format of the data read using the read() call. + * This is determined by the read_format field when the event is opened. + * Now that we handle different values of read_format, this is not + * directly read by the read call. + */ +typedef struct { + unsigned long long value; /* This is reset when we call reset() */ + unsigned long long time_enabled; /* These aren't */ + unsigned long long time_running; + unsigned long long id; +} event_sample_t; + + +/* + * Capability flags, in case not defined individually + */ +const unsigned int _cap_user_rdpmc = 0x04; +const unsigned int _cap_user_time = 0x08; +const unsigned int _cap_user_time_zero = 0x10; + + +/* + * Python object corresponding to a perf event source - i.e. something + * that we've got as a result of a perf_event_open call. + */ +typedef struct event_object_s EventObject; +struct event_object_s { + PyObject_HEAD + struct perf_event_attr attr; /* kernel perf's info about the event */ + int cpu; /* cpu that this event is bound to, or -1 if all-cpu */ + //int pid; /* PID that this event is bound to, or -1 if system-wide */ + int fd; /* file handle from perf_event_open: unique to this event */ + unsigned long long id; /* event unique identifier */ + int verbose; /* -vv or similar was used */ + int try_userspace_read:1; /* try reading from userspace rather than read() */ + EventObject *group_leader; /* group leader, or NULL */ + EventObject *buffer_owner; /* buffer owner (even if we're not in a group) */ + EventObject *next_sub; /* subordinate event, or NULL */ + unsigned short sample_id_bytes; /* in sample records, no. of trailing bytes for the sample_id */ + /* Data to support collecting individual perf events */ + struct perf_event_mmap_page *mmap_page; + unsigned long mmap_size; /* total size of the area, including header page */ + unsigned long mmap_data_size; /* data size, exclusive of header page */ +#define MMAP_DATA_SIZE_DEFAULT ((unsigned long)(-1)) + unsigned char *mmap_data_start; /* start of data in the allocated area */ + unsigned char *mmap_data_end; /* end of the allocated area */ + unsigned char *mmap_cursor; /* current position in the area */ + int need_aux; /* set if event type needs AUX area */ + void *aux_area; /* AUX area e.g. for h/w trace */ + unsigned long aux_size; /* total size of aux area (or 0) */ + /* We want reset() to start a new measurement window, after which we + can read the event's value and also find out what percentage of + time it was running for. But PERF_EVENT_IOC_RESET doesn't reset + the enabled and running measurements. So instead we have to save + the values at the start of the window. */ + PyObject *datasnap; +}; + + +/* + * Base class for either a reading or a group reading. + */ +typedef struct { + PyObject_HEAD + EventObject *event; + event_sample_t sample; + double fraction_running; +} BaseReadingObject; + +static PyTypeObject BaseReadingType; + + +/* + * A single counter reading. This is either from a non-group event, or as a + * member of a group event reading. + */ +typedef struct { + BaseReadingObject base; + PyObject *adjusted_value; +} ReadingObject; + +static PyTypeObject ReadingType; + + +/* + * Reading from a group leader, with data from multiple events. + */ +typedef struct { + BaseReadingObject base; + unsigned int n_values; + event_sample_t *samples; +} GroupReadingObject; + +static PyTypeObject GroupReadingType; + + +/* + * Time conversion parameters + */ +typedef struct { + PyObject_HEAD + unsigned long time_zero; + unsigned long time_mult; + unsigned long time_shift; +} TimeConvObject; + +static PyTypeObject TimeConvType; + + +/* + * Map from fileno to Event object - useful when using select, poll etc. + * We don't use a Python dict as we don't want this to act as a reference. + */ +static PyObject **fileno_events = NULL; +static unsigned int n_fileno_events = 0; + +/* + * Insert a file handle into the array. + * We assume file handles are small integers and we can directly index into an array. + */ +static void fileno_event_insert(int fd, EventObject *e) +{ + assert(e != NULL); + assert(fd >= 0); + if ((unsigned int)fd >= n_fileno_events) { + if (n_fileno_events == 0) { + n_fileno_events = 32; + fileno_events = (PyObject **)calloc(n_fileno_events, sizeof(PyObject *)); + } else { + unsigned int nn = n_fileno_events * 4; + fileno_events = (PyObject **)realloc(fileno_events, nn*sizeof(PyObject *)); + memset(fileno_events + n_fileno_events, 0, (nn-n_fileno_events)*sizeof(PyObject *)); + n_fileno_events = nn; + } + } + assert(fileno_events[fd] == NULL); + fileno_events[fd] = (PyObject *)e; +} + + +static PyObject *event_new(PyTypeObject *t, PyObject *args, PyObject *kwds) +{ + EventObject *e = (EventObject *)t->tp_alloc(t, 0); + assert(e != NULL); + //memset(&e->attr, 0, sizeof(EventObject) - offsetof(EventObject, attr)); + /* All fields that might be referred to in dealloc must be initialized early, + but we are guaranteed that the block returned by tp_alloc is zero-initialized. */ + e->fd = -1; + e->mmap_data_size = MMAP_DATA_SIZE_DEFAULT; + e->mmap_page = NULL; + e->group_leader = NULL; + e->buffer_owner = NULL; + e->next_sub = NULL; + e->aux_size = MMAP_DATA_SIZE_DEFAULT; + e->datasnap = NULL; + return (PyObject *)e; +} + + +/* + * Calculate the size of the sample_id structure that follows the record-specific + * data when sample_id_all is set. + * This is similar in principle to the initial part of a PERF_RECORD_SAMPLE payload, + * but differs in detail as regards the ordering and selection of fields. + * In particular PERF_SAMPLE_IDENTIFIER puts the identifier first in the + * PERF_RECORD_SAMPLE payload, but last in the sample_id structure. + */ +static unsigned int perf_event_attr_sample_id_size(struct perf_event_attr const *a) +{ + unsigned int size = 0; + if (!a->sample_id_all) { + return 0; + } + if (a->sample_type & PERF_SAMPLE_TID) { + size += 4+4; + } + if (a->sample_type & PERF_SAMPLE_TIME) { + size += 8; + } + if (a->sample_type & PERF_SAMPLE_ID) { + size += 8; + } + if (a->sample_type & PERF_SAMPLE_STREAM_ID) { + size += 8; + } + if (a->sample_type & PERF_SAMPLE_CPU) { + size += 8; + } + if (a->sample_type & PERF_SAMPLE_IDENTIFIER) { + size += 8; + } + return size; +} + + +/* + * Find the offset, in a sample record, of the PERF_SAMPLE_READ data. + * We rely on there being no variable-length (data-dependent) + * items before this data - all the preceding items have sizes + * fixed at event configuration time. + */ +static unsigned int sample_offset_to_read(struct perf_event_attr const *e) +{ + unsigned int rdata_calc = 0; + if (e->sample_type & PERF_SAMPLE_IDENTIFIER) { + rdata_calc += 8; + } + if (e->sample_type & PERF_SAMPLE_IP) { + rdata_calc += 8; + } + if (e->sample_type & PERF_SAMPLE_TID) { + rdata_calc += 4+4; + } + if (e->sample_type & PERF_SAMPLE_TIME) { + rdata_calc += 8; + } + if (e->sample_type & PERF_SAMPLE_ADDR) { + rdata_calc += 8; + } + if (e->sample_type & PERF_SAMPLE_ID) { + rdata_calc += 8; + } + if (e->sample_type & PERF_SAMPLE_STREAM_ID) { + rdata_calc += 8; + } + if (e->sample_type & PERF_SAMPLE_CPU) { + rdata_calc += 4+4; + } + if (e->sample_type & PERF_SAMPLE_PERIOD) { + rdata_calc += 8; + } +#if defined(PERF_SAMPLE_DATA_SRC) || !defined(PERF_RECORD_MMAP) + if (e->sample_type & PERF_SAMPLE_DATA_SRC) { + rdata_calc += 8; + } +#endif +#if defined(PERF_SAMPLE_PHYS_ADDR) || !defined(PERF_RECORD_MMAP) + if (e->sample_type & PERF_SAMPLE_PHYS_ADDR) { + rdata_calc += 8; + } +#endif + /* PERF_DATA_READ data follows. Other data types (CALLCHAIN, TRANSACTION etc.) may follow that. */ + return rdata_calc; +} + + +static int perf_reading_size(EventObject const *e) +{ + int size; + if (e->attr.read_format & PERF_FORMAT_GROUP) { + /* Total size is unknown. */ + size = 8; /* Number of values */ + /* Plus 8 or 16 bytes per value, depending on PERF_FORMAT_ID */ + } else { + size = 8; /* value */ + if (e->attr.read_format & PERF_FORMAT_ID) { + size += 8; + } + } + if (e->attr.read_format & PERF_FORMAT_TOTAL_TIME_ENABLED) { + size += 8; + } + if (e->attr.read_format & PERF_FORMAT_TOTAL_TIME_RUNNING) { + size += 8; + } + return size; +} + + +static int perf_reading_size_group(EventObject const *e, unsigned int n) +{ + int size = perf_reading_size(e); + size += (n * 8); + if (e->attr.read_format & PERF_FORMAT_ID) { + size += (n * 8); + } + return size; +} + + +/* + * Return the standard per-CPU buffer allocation, from /proc/sys/kernel/perf_event_mlock_kb + */ +static unsigned int perf_event_mlock_size(void); + + +#ifdef PRINTF_DIAGNOSTICS +typedef struct { + char const *name; + unsigned int value; +} flagnames_t; + +static void fprint_flags(FILE *fd, unsigned long flags, flagnames_t const *flagnames, unsigned int n) +{ + unsigned int i; + for (i = 0; i < n; ++i) { + if (flags & flagnames[i].value) { + fprintf(fd, "%s", flagnames[i].name); + flags &= ~flagnames[i].value; + if (flags) fprintf(fd, "|"); + } + } + if (flags) { + fprintf(fd, "%#lx", flags); + } +} + +/* flag names, see /usr/include/linux/perf_event.h */ +static flagnames_t const sample_flagnames[] = { +#define FLAG(x) { #x, PERF_SAMPLE_##x } + FLAG(IDENTIFIER), + FLAG(IP), + FLAG(TID), + FLAG(TIME), + FLAG(ADDR), + FLAG(READ), + FLAG(CALLCHAIN), + FLAG(ID), + FLAG(CPU), + FLAG(PERIOD), + FLAG(STREAM_ID), + FLAG(RAW), + FLAG(BRANCH_STACK), + FLAG(REGS_USER), + FLAG(STACK_USER), +#if defined(PERF_SAMPLE_DATA_SRC) || !defined(PERF_RECORD_MMAP) + FLAG(DATA_SRC), +#endif +#if defined(PERF_SAMPLE_PHYS_ADDR) || !defined(PERF_RECORD_MMAP) + FLAG(PHYS_ADDR), +#endif +#undef FLAG +}; + +#define FLAG_NAMES(x) x, sizeof(x)/sizeof(x[0]) + +static void fprint_perf_event_attr(FILE *fd, struct perf_event_attr const *a) +{ + fprintf(fd, "perf_event_attr:\n"); + fprintf(fd, " type %d\n", a->type); + fprintf(fd, " size %d\n", a->size); + fprintf(fd, " config %#llx\n", (unsigned long long)a->config); + if (a->sample_period != 0) { + fprintf(fd, " { sample_period, sample_freq } %lu\n", (unsigned long)a->sample_period); + } + if (a->sample_type != 0) { + /* Show combination of PERF_SAMPLE_XXX flags */ + fprintf(fd, " sample_type: "); + fprint_flags(fd, a->sample_type, FLAG_NAMES(sample_flagnames)); + fprintf(fd, "\n"); + } + if (a->read_format != 0) { + /* Show combination of PERF_FORMAT_XXX flags */ + /* flag names, see /usr/include/linux/perf_event.h */ + static flagnames_t const flagnames[] = { +#define FLAG(x) { #x, PERF_FORMAT_##x } + FLAG(TOTAL_TIME_ENABLED), + FLAG(TOTAL_TIME_RUNNING), + FLAG(ID), + FLAG(GROUP) +#undef FLAG + }; + fprintf(fd, " read_format "); + fprint_flags(fd, a->read_format, FLAG_NAMES(flagnames)); + fprintf(fd, "\n"); + } + fprintf(fd, " disabled %d inherit %d\n", a->disabled, a->inherit); + fprintf(fd, " pinned %d exclusive %d\n", a->pinned, a->exclusive); + fprintf(fd, " exclude_user %d exclude_kernel %d\n", a->exclude_user, a->exclude_kernel); + fprintf(fd, " exclude_hv %d exclude_idle %d\n", a->exclude_hv, a->exclude_idle); + fprintf(fd, " enable_on_exec %d task %d\n", a->enable_on_exec, a->task); + fprintf(fd, " exclude_host %d exclude_guest %d\n", a->exclude_host, a->exclude_guest); +#ifdef PERF_RECORD_MISC_COMM_EXEC + if (a->comm || a->comm_exec) { + fprintf(fd, " comm %d comm_exec %d\n", a->comm, a->comm_exec); + } +#else + if (a->comm) { + fprintf(fd, " comm %d\n", a->comm); + } +#endif + if (a->precise_ip) { + fprintf(fd, " precise_ip %d\n", a->precise_ip); + } + if (a->freq) { + fprintf(fd, " freq %d\n", a->freq); + } + if (a->sample_id_all) { + fprintf(fd, " sample_id_all %d\n", a->sample_id_all); + } + if (a->inherit_stat) { + fprintf(fd, " inherit_stat %d\n", a->inherit_stat); + } + fprintf(fd, " bp_type %#x\n", a->bp_type); + if (a->type != PERF_TYPE_BREAKPOINT) { + if (a->config1) { + fprintf(fd, " config1 %#llx\n", a->config1); + } + if (a->config2) { + fprintf(fd, " config2 %#llx\n", a->config2); + } + } else { + fprintf(fd, " bp_addr %#llx\n", a->bp_addr); + fprintf(fd, " bp_len %#llx\n", a->bp_len); + } + fprintf(fd, " mmap %d\n", a->mmap); + fprintf(fd, " mmap2 %d\n", a->mmap2); +#if defined(PERF_RECORD_SWITCH) || !defined(PERF_RECORD_MMAP) + fprintf(fd, " context_switch %d\n", a->context_switch); /* since 4.3 */ +#endif /* PERF_RECORD_SWITCH */ + if (a->sample_type & PERF_SAMPLE_BRANCH_STACK) { + /* Show branch sample properties - field only valid when this flag set */ + static flagnames_t const flagnames[] = { +#define FLAG(x) { #x, PERF_SAMPLE_BRANCH_##x } + FLAG(USER), + FLAG(KERNEL), + FLAG(HV), + FLAG(ANY), + FLAG(ANY_CALL), + FLAG(ANY_RETURN), + FLAG(IND_CALL), + FLAG(ABORT_TX), + FLAG(IN_TX), + FLAG(NO_TX), + FLAG(COND), + FLAG(CALL_STACK), + FLAG(IND_JUMP), + FLAG(CALL) +#undef FLAG + }; + fprintf(fd, " branch_sample_type "); + fprint_flags(fd, a->branch_sample_type, FLAG_NAMES(flagnames)); + fprintf(fd, "\n"); + } +} +#endif /* PRINTF_DIAGNOSTICS */ + +/* Forward declarations */ +static PyTypeObject EventType; +static PyTypeObject RecordType; + +static int event_setup_buffer(EventObject *); +static int event_setup_buffer_aux(EventObject *, int); +static int event_get_id(EventObject *); +static PyObject *event_close(PyObject *x); + +static int event_is_subordinate(EventObject const *e) +{ + return e->group_leader != NULL && e->group_leader != e; +} + + +/* + * Instance initialization function for Event. + * + * Compared to the perf_event_open syscall (perf_event_attr, pid, cpu, group, flags), + * the constructor for Event has some additional arguments: + * - sizes for the mmap buffer and AUX buffer, for when we allocate them + * - verbosity + * + * Return 0 on success. + * Return -1 on failure to create event. + */ +static int event_init(PyObject *x, PyObject *args, PyObject *kwds) +{ + EventObject *e = (EventObject *)x; + PyObject *e_attr = NULL; + unsigned int n_tries = 0; + int fd; + /* perf event description parameters */ + int is_sampling; + int e_pid = 0, e_tid = 0; + int e_cpu = -1; /* all CPUs */ + int e_verbose = 0; + int e_retry = 1; + unsigned long e_mmap_data_size = MMAP_DATA_SIZE_DEFAULT; + unsigned long e_mmap_aux_size = MMAP_DATA_SIZE_DEFAULT; +#ifdef PERF_FLAG_FD_CLOEXEC + unsigned long e_flags = PERF_FLAG_FD_CLOEXEC; +#else + unsigned long e_flags = 0; +#endif + unsigned long e_custom_flags = 0; + int e_group_fd = -1; + PyObject *e_enabled_obj = NULL; + + PyObject *e_group_obj = NULL; + PyObject *e_buffer_obj = NULL; + EventObject *e_buffer_owner = NULL; + + static char *kwlist[] = {"attr", + "verbose", + "retry", + "pid", + "tid", + "cpu", + "mmap_size", + "aux_size", + "flags", + "enabled", + "group", + "buffer", + NULL}; + + assert(e->fd == -1); + memset(&e->attr, 0, sizeof e->attr); + if (!PyArg_ParseTupleAndKeywords(args, kwds, "O|iiiiikkkOOO", kwlist, + &e_attr, + &e_verbose, + &e_retry, + &e_pid, + &e_tid, + &e_cpu, + &e_mmap_data_size, + &e_mmap_aux_size, + &e_flags, + &e_enabled_obj, + &e_group_obj, + &e_buffer_obj)) { + /* On failure this will already have raised the appropriate exception. */ +#ifdef PRINTF_DIAGNOSTICS + if (e_verbose) { + fprintf(stderr, "perf event: Python API argument parsing failed\n"); + } +#endif /* PRINTF_DIAGNOSTICS */ + return -1; + } + if (e_mmap_data_size != MMAP_DATA_SIZE_DEFAULT) { + e->mmap_data_size = e_mmap_data_size; + } + if (e_mmap_aux_size != MMAP_DATA_SIZE_DEFAULT) { + e->aux_size = e_mmap_aux_size; + } + e->try_userspace_read = 1; + + /* Process non-canonical flags encoded in the same parameter as PERF_FLAG_... */ + e_custom_flags = e_flags & 0xff000000; + e_flags &= ~e_custom_flags; + if (e_custom_flags & PERF_FLAG_READ_USERSPACE) { + e->try_userspace_read = 1; + } + if (e_custom_flags & PERF_FLAG_NO_READ_USERSPACE) { + e->try_userspace_read = 0; + } + if (e->attr.read_format & PERF_FORMAT_GROUP) { + /* If we want all the counters read at the same time, then it doesn't + make sense to read 'live' values from userspace - unless those + counters have been simultaneously frozen */ + e->try_userspace_read = 0; + } + + { + /* Get the perf_event_attr buffer. The buffer argument may be any of: + bytes() + bytearray() + an object implementing the __bytes__ method, such as PerfEventAttr + */ + char *data = NULL; + unsigned int attr_size; + if (PyBytes_Check(e_attr)) { + attr_size = PyBytes_Size(e_attr); + data = PyBytes_AsString(e_attr); + } else if (PyByteArray_Check(e_attr)) { + attr_size = PyByteArray_Size(e_attr); + data = PyByteArray_AsString(e_attr); + } else { + PyObject *bytes_callable = PyObject_GetAttrString(e_attr, "__bytes__"); + if (bytes_callable) { + PyObject *b_attr = PyObject_CallObject(bytes_callable, NULL); + if (!b_attr) { + /* Call failed and an error has already been set */ + return -1; + } + attr_size = PyBytes_Size(b_attr); + data = PyBytes_AsString(b_attr); + } + } + if (!data) { +#ifdef PRINTF_DIAGNOSTICS + fprintf(stderr, "perf event: expected bytearray or bytes\n"); +#endif /* PRINTF_DIAGNOSTICS */ + PyErr_SetString(PyExc_TypeError, "invalid event object"); + return -1; + } + if (attr_size > sizeof e->attr) { +#ifdef PRINTF_DIAGNOSTICS + fprintf(stderr, "perf event: attribute size %x, only expecting %u\n", + (unsigned int)attr_size, (unsigned int)(sizeof e->attr)); +#endif /* PRINTF_DIAGNOSTICS */ + PyErr_SetString(PyExc_ValueError, "perf_event_open: attribute data too large"); + return -1; + } + memcpy(&e->attr, data, attr_size); + if (e->attr.size != attr_size) { +#ifdef PRINTF_DIAGNOSTICS + fprintf(stderr, "perf event: attribute length %u doesn't match structure size field %u\n", + (unsigned int)attr_size, (unsigned int)(e->attr.size)); +#endif /* PRINTF_DIAGNOSTICS */ + return -1; + } + } + + if (e_enabled_obj != NULL) { + e->attr.disabled = !PyObject_IsTrue(e_enabled_obj); + } + + /* This is a sampling event, which will need a buffer allocated. + Strictly, we don't need to know that when we create the event. + But it helps to create the buffer early so that + (a) we don't lose any events if the target starts running + before we create the buffer + (b) when grouping events we can direct any subordinate + events to the leader's buffer. */ + is_sampling = e->attr.sample_freq != 0; + if (e_tid != 0 && e_pid != 0) { + /* mutually exclusive */ + return -1; + } + + /* Verbosity setting sticks to the event */ + e->verbose = e_verbose; + + /* "This field specifies the format of the data returned by read(2) on a + perf_event_open() file descriptor." Our event_sample_t must be in sync. */ + if (e->attr.read_format == 0) { + if (!is_sampling) { + /* This is a counting event, e.g. a hardware event count. */ + e->attr.read_format = PERF_FORMAT_TOTAL_TIME_ENABLED|PERF_FORMAT_TOTAL_TIME_RUNNING|PERF_FORMAT_ID; + } else { + /* This is a sampling event, returning records in the mmap buffer. */ + e->attr.read_format = PERF_FORMAT_ID; + } + } + + /* A "sampling" event is one that generates an overflow notification + every N events, where N is given by some sample_period. + A sampling event has sample_period > 0. When an overflow occurs, + requested data is recorded in the mmap buffer... + sample_freq can be used if you wish to use frequency rather than period... + The kernel will adjust the sampling period to try and achieve the + desired rate. The rate of adjustment is a timer tick. */ + if (e->attr.inherit && (e->attr.sample_type & PERF_SAMPLE_READ)) { + /* Currently the kernel doesn't support this combination and will return EINVAL. */ + PyErr_SetString(PyExc_ValueError, "perf_event_open: PERF_SAMPLE_READ not supported with inherited events"); +#ifdef PRINTF_DIAGNOSTICS + if (e_verbose) { + fprintf(stderr, "perf_event_open: PERF_SAMPLE_READ not supported with inherited events\n"); + } +#endif /* PRINTF_DIAGNOSTICS */ + return -1; + } + + if (e->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) { + /* Default to a usable value if the caller has failed to specify. TBD review */ + if (e->attr.branch_sample_type == 0) { + e->attr.branch_sample_type = PERF_SAMPLE_BRANCH_ANY; + } + } + + if (e->attr.sample_type != 0) { + /* TBD - set some flags that perf seems to set for perf record */ + e->attr.comm = 1; +#ifdef PERF_RECORD_MISC_COMM_EXEC + e->attr.comm_exec = 1; +#endif /* PERF_RECORD_MISC_COMM_EXEC */ + e->sample_id_bytes = perf_event_attr_sample_id_size(&e->attr); + } else { + e->sample_id_bytes = 0; + } + + if (e_group_obj == Py_None) { + e_group_obj = NULL; + } + if (e_buffer_obj == Py_None) { + e_buffer_obj = NULL; + } + if (e_buffer_obj != NULL) { + if (!PyObject_TypeCheck(e_buffer_obj, &EventType)) { + PyErr_SetString(PyExc_TypeError, "buffer must be another Event object"); + return -1; + } + e_buffer_owner = (EventObject *)e_buffer_obj; + } + if (e_group_obj != NULL) { + /* We don't use the "O!" typechecking format as we want None to be + equivalent to not using the argument - so typecheck here. */ + if (!PyObject_TypeCheck(e_group_obj, &EventType)) { + PyErr_SetString(PyExc_TypeError, "group must be another Event object"); + return -1; + } else { + EventObject *ge = (EventObject *)e_group_obj; + /* The group object might be a singleton or a group leader, + but it mustn't be a subordinate. (We could be more flexible + and use the leader if a subordinate was passed in, but we + prefer to fault on the grounds that the caller may be confused.) */ + if (event_is_subordinate(ge)) { + PyErr_SetString(PyExc_ValueError, "perf_event_open: group is not a group leader"); + return -1; + } + if (e_buffer_owner == NULL) { + e_buffer_owner = ge; + } + e_group_fd = ge->fd; + } + /* e_flags |= PERF_FLAG_FD_OUTPUT; "broken since Linux 2.6.35 " */ + /* is that equivalent to PERF_SAMPLE_READ? */ + } +retry:; + if (n_tries == 1 && !e_retry) { + PyErr_SetString(PyExc_ValueError, "perf_event_open: invalid descriptor"); + return -1; + } + n_tries++; + /* "pid == -1 and cpu == -1: This setting is invalid and will return an error." */ + /* even though this is the logical setting for offcore PMUs. */ + int const pidtid = (e_pid == 0 && e_tid != 0) ? e_tid : e_pid; + assert(!(pidtid == -1 && e_cpu == -1)); + /* Userspace PMU read generally doesn't make sense if the live PMC counters are + on other cores. So we should enable it only if monitoring the current thread. */ + if (e_tid != 0) { + e->try_userspace_read = 0; + /* TBD: should we also check attr.inherit=0 ? */ + } +#ifdef PRINTF_DIAGNOSTICS + if (e_verbose) { + if (e_verbose >= 2) { + fprint_perf_event_attr(stderr, &e->attr); + } + fprintf(stderr, "perf_event_open: pid %d cpu %d group_fd %d flags %#lx", + e_pid, e_cpu, e_group_fd, e_flags); + } +#endif /* PRINTF_DIAGNOSTICS */ + /* Allocate a file descriptor for this event. Note that even when we're + supplying a fd for the group leader, we still get a new fd. */ + fd = perf_event_open(&e->attr, /*pid=*/pidtid, /*cpu=*/e_cpu, /*group_fd=*/e_group_fd, /*flags=*/e_flags); + int const perf_event_open_errno = errno; +#ifdef PRINTF_DIAGNOSTICS + if (e_verbose) { + fprintf(stderr, " => %d\n", fd); + } +#endif /* PRINTF_DIAGNOSTICS */ + if (fd < 0) { + /* The perf event couldn't be opened. Maybe it's an invalid event + or maybe we tried to open it with attributes that weren't + valid for this event, in which case we can adjust and retry. + What kind of error should we raise? + We take the view that we should + - raise PermissionError if the operation might have succeeded + with more user privilege, or more relaxed perf_event_paranoid + - raise ValueError if the user's input value was invalid + - raise OSError in other cases + Python 2 doesn't have PermissionError so we have to raise + OSError and have the user check errno. + */ + if (e_verbose) { + fprintf(stderr, "sys_perf_event_open failed, errno = -%d\n", perf_event_open_errno); + errno = perf_event_open_errno; + perror("perf_event_open"); + } + if (perf_event_open_errno == ENOENT || + perf_event_open_errno == EOPNOTSUPP) { + /* Input was ok, we just can't do this event on this system. + E.g. stalled-cycles-frontend. perf stat reports "". */ + if (e_verbose) { + fprintf(stderr, "perf event: raising ValueError\n"); + } + PyErr_SetString(PyExc_ValueError, "perf_event_open: event not supported"); + } else if (perf_event_open_errno == EINVAL) { + /* E.g. passed in an undefined event code, or flags not appropriate + for this event. */ + if (e_group_fd != -1) { + /* Check if it was a bad group (or if we'd reached the group limit), + by trying to open the event outside the group. */ + e->attr.read_format &= ~PERF_FORMAT_GROUP; + int temp_fd = perf_event_open(&e->attr, pidtid, e_cpu, /*group=*/-1, e_flags); + if (temp_fd >= 0) { + /* We could create this event, just not in a group */ + if (e_custom_flags & PERF_FLAG_WEAK_GROUP) { + fd = temp_fd; + goto event_created; + } + close(temp_fd); + PyErr_SetString(PyExc_ValueError, "perf_event_open: invalid group"); + return -1; + } + } + /* Exclusion flags might not be supported for uncore events */ + if (e->attr.exclude_guest) { + if (e_verbose) { +#ifdef PRINTF_DIAGNOSTICS + fprintf(stderr, "perf_event_open: switching off exclude_guest flag\n"); +#endif /* PRINTF_DIAGNOSTICS */ + } + e->attr.exclude_guest = 0; + goto retry; + } + if (e->attr.exclude_hv) { + if (e_verbose) { +#ifdef PRINTF_DIAGNOSTICS + fprintf(stderr, "perf_event_open: switching off exclude_hv flag\n"); +#endif /* PRINTF_DIAGNOSTICS */ + } + e->attr.exclude_hv = 0; + goto retry; + } + PyErr_SetString(PyExc_ValueError, "perf_event_open: invalid value"); + } else { + /* could be EPERM e.g. trying to do system-wide monitoring */ + /* or EOPNOTSUPP */ + /* EOPNOTSUPP: branch tracing requested on inappropriate event (s/w, tracepoint etc.) */ + /* Unexpected error */ + /* TBD: we find on AArch64, raw events 0..63 not in PMCEIDR return EOPNOTSUPP, + so we treat that as ENOENT */ + //fprintf(stderr, "perf event attr: type %d config 0x%llx\n", + // (int)e->attr.type, (unsigned long long)e->attr.config); + if (0 && !e_verbose) { + /* Not already printed */ + fprintf(stderr, "perf_event_open: pid %d cpu %d group_fd %d flags %#lx\n", + e_pid, e_cpu, e_group_fd, e_flags); + errno = perf_event_open_errno; + perror("perf_event_open"); + } + errno = perf_event_open_errno; + PyErr_SetFromErrno(PyExc_OSError); + } + return -1; + } + +event_created: + /* + * The event has been successfully created. + */ + e->cpu = e_cpu; + e->fd = fd; + + /* + * Insert the event into our fileno->event map. + * We don't want this map to act as a retainer for otherwise freed events, + * so we ensure it doesn't contribute to the reference count. + */ + fileno_event_insert(fd, e); + + /* Set need_aux to indicate that if we allocate a mmap buffer for events, + we should also allocate an 'aux' buffer for bulk data. */ + if (e->attr.type == PERF_TYPE_HARDWARE || + e->attr.type == PERF_TYPE_HW_CACHE || + e->attr.type == PERF_TYPE_RAW || + e->attr.type == PERF_TYPE_TRACEPOINT || + e->attr.type == PERF_TYPE_BREAKPOINT || + e->attr.type == PERF_TYPE_SOFTWARE) { + e->need_aux = 0; + } else { + e->need_aux = 1; /* TBD should test event type */ + } + if (e_buffer_owner != NULL) { + Py_INCREF(e_buffer_owner); + e->buffer_owner = e_buffer_owner; + /* Add this event to the group leader's list of subordinates. */ + e->next_sub = e->buffer_owner->next_sub; + e->buffer_owner->next_sub = e; + /* TBD: what happens to this list when we delete events + (in some order?) */ + } + if (is_sampling) { + if (e->buffer_owner == NULL) { + event_setup_buffer(e); + } else { + int bfd = e->buffer_owner->fd; + assert(bfd != -1); + /* It doesn't seem to be possible for subordinate events to have + their own buffer even if we wanted to - mmap() returns invalid. */ + int rc; + rc = ioctl(e->fd, PERF_EVENT_IOC_SET_OUTPUT, bfd); + if (rc) { + perror("ioctl"); + fprintf(stderr, "perf event: error redirecting %d's events to %d's buffer\n", e->fd, bfd); + } + } + event_get_id(e); + } else if (e->attr.read_format & PERF_FORMAT_ID) { + /* We need our id in order to match up when we read it */ + event_get_id(e); + } + if (e->try_userspace_read && !e->mmap_page) { + if (!event_setup_buffer_aux(e, /*quiet=*/1)) { + /* Maybe this kernel doesn't support mmap'ing a non-sampling event */ + e->try_userspace_read = 0; + } + } + /* This is the only success return in this function. We must have created an event. */ + assert(e->fd >= 0); + return 0; +} + + +#ifdef PRINTF_DIAGNOSTICS +/* + * Print the current status of an mmap page, from its header. + * This information will change continuously as the kernel adds more records. + */ +static void fprint_mmap_page_status(FILE *fd, struct perf_event_mmap_page const *mp) +{ + fprintf(fd, "time enabled = %lu, time running = %lu", (unsigned long)mp->time_enabled, (unsigned long)mp->time_running); + /* "data_head points to the head of the data section. The value continually increases, it does not wrap." */ + fprintf(fd, ", data_tail = %lx, ", (unsigned long)mp->data_tail); + /* data_tail should be written by user space to reflect the last read data." */ + fprintf(fd, "data_head = %lx", (unsigned long)mp->data_head); + if (mp->aux_size) { + fprintf(fd, ", aux_size = %lx, ", (unsigned long)mp->aux_size); + fprintf(fd, "aux_tail = %lx, ", (unsigned long)mp->aux_tail); + fprintf(fd, "aux_head = %lx", (unsigned long)mp->aux_head); + } + fprintf(fd, "\n"); + if (mp->capabilities & _cap_user_rdpmc) { + /* Show if a userspace-readable hardware counter is currently mapped to this event */ + /* mp->index is not necessarily small: see IA32_FIXED_CTR... */ + fprintf(fd, "counter index = 0x%x, offset = 0x%lx\n", (int)mp->index, (unsigned long)mp->offset); + } +} + + +static void fprint_mmap_page(FILE *fd, struct perf_event_mmap_page const *mp) +{ + fprintf(fd, "mmap page:\n"); + fprintf(fd, " version = %u, ", mp->version); + fprintf(fd, "index = 0x%x, ", mp->index); + fprintf(fd, "data_size = 0x%lx, data_offset = 0x%lx\n", (unsigned long)mp->data_size, (unsigned long)mp->data_offset); /* since 4.1 */ +#ifndef PERF_NO_CAPABILITIES + /* usually 0x1e: cap_user_time_zero, cap_user_time, cap_user_rdpmc, cap_bit0_is_deprecated */ + fprintf(fd, " capabilities = 0x%llx", mp->capabilities); + if (mp->cap_user_rdpmc) { + fprintf(fd, ", pmc_width = %u", mp->pmc_width); + } + if (mp->cap_user_time_zero) { + fprintf(fd, ", time_zero = %#llx", mp->time_zero); + fprintf(fd, ", time_shift = %d", mp->time_shift); + fprintf(fd, ", time_mult = %d", mp->time_mult); + } + fprintf(fd, "\n"); +#endif /* !PERF_NO_CAPABILITIES */ + fprint_mmap_page_status(fd, mp); +} +#endif /* PRINTF_DIAGNOSTICS */ + + +/* + * Map a userspace-accessible ring buffer on to the event's file descriptor so + * that we can retrieve a series of samples produced by the perf subsystem. + * + * Ability to mmap() is subject to the RLIMIT_MEMLOCK resource limit. + * perf_mmap in events/core.c shows that we get a set amount per CPU + * (see /proc/sys/kernel/perf_event_mlock_kb), and any allocation above + * that is counted against RLIMIT_MEMLOCK. Exceeding the limit results + * in EPERM. + * + * So when sampling multiple events, we would generally want to redirect + * all the events to one sampling buffer per CPU even if the events aren't + * being scheduled on to PMU as a group. + */ +static int event_setup_buffer_aux(EventObject *e, int quiet) +{ + void *pmap; + unsigned int const page_size = sysconf(_SC_PAGESIZE); + /* There's a limit on how much memory we can map, and our various mmap + buffers (main, aux etc.) have to come out of that. So we adjust the + sizes of the requests so that we don't get an error. */ + if (e->mmap_data_size == MMAP_DATA_SIZE_DEFAULT) { + unsigned int data_size; + data_size = perf_event_mlock_size() - page_size; + if (e->need_aux) { + data_size /= 2; + } + e->mmap_data_size = data_size; + } + /* Round up to a page size (it should be already) */ + if (e->mmap_data_size < page_size) { + e->mmap_data_size = page_size; + } + /* Size actually mapped should be 1 + 2^n pages, to allow for the header */ + e->mmap_size = page_size + e->mmap_data_size; + /* Provide the buffer to the file handle */ +#ifdef PRINTF_DIAGNOSTICS + if (e->verbose >= 2) { + fprintf(stderr, "mmap(size=%#lx,fd=%d)", e->mmap_size, e->fd); + } +#endif /* PRINTF_DIAGNOSTICS */ + pmap = mmap(NULL, e->mmap_size, PROT_READ|PROT_WRITE, MAP_SHARED, e->fd, 0); + int const mmap_errno = errno; +#ifdef PRINTF_DIAGNOSTICS + if (e->verbose >= 2) { + fprintf(stderr, " => %p\n", pmap); + } +#endif /* PRINTF_DIAGNOSTICS */ + if (pmap == MAP_FAILED) { + if (!quiet) { + errno = mmap_errno; + perror("mmap"); + if (event_is_subordinate(e)) { + fprintf(stderr, " (event is subordinate to fd=%d)\n", e->buffer_owner->fd); + } + if (mmap_errno == EINVAL || 1) { + fprintf(stderr, " size = %lu/0x%lx, page size = %u/0x%x, fd=%d\n", + e->mmap_size, e->mmap_size, + page_size, page_size, + e->fd); + } + if (mmap_errno == EPERM) { + fprintf(stderr, " maybe exceeded process's MEMLOCK limit?\n"); + } + } + return 0; + } + e->mmap_page = (struct perf_event_mmap_page *)pmap; + e->mmap_data_start = (unsigned char *)pmap + page_size; + e->mmap_data_end = (unsigned char *)pmap + e->mmap_size; + e->mmap_cursor = (unsigned char *)pmap + page_size; +#ifdef PRINTF_DIAGNOSTICS + /* The kernel will have filled in some information fields. */ + if (e->verbose >= 2) { + fprintf(stderr, "%p: perf buffer size = 0x%lx, ", pmap, e->mmap_size); + fprint_mmap_page(stderr, e->mmap_page); + } +#endif /* PRINTF_DIAGNOSTICS */ +#if defined(PERF_RECORD_AUX) || !defined(PERF_RECORD_MMAP) + if (e->need_aux) { + void *paux; + assert(e->aux_area == 0); + if (e->aux_size == MMAP_DATA_SIZE_DEFAULT) { + // TBD follow perf in halving the size + e->aux_size = e->mmap_data_size / 2; + } + /* "To set up an AUX area, first aux_offset nedes to be set with + an offset greater than data_offset+data_size and aux_size + needs to be set to the desired buffer size. The desired offset + and size must be page aligned, and the size must be a power of two." */ + unsigned long aux_offset = e->mmap_size; + assert(aux_offset % page_size == 0); + assert(e->aux_size % page_size == 0); + e->mmap_page->aux_offset = aux_offset; + e->mmap_page->aux_size = e->aux_size; +#ifdef PRINTF_DIAGNOSTICS + if (e->verbose >= 2) { + fprintf(stderr, "mmap(%#lx, fd=%d, %#llx) for aux buffer\n", e->aux_size, e->fd, (unsigned long long)aux_offset); + } +#endif /* PRINTF_DIAGNOSTICS */ + paux = mmap(NULL, e->aux_size, PROT_READ|PROT_WRITE, MAP_SHARED, e->fd, aux_offset); + if (paux == MAP_FAILED) { + perror("mmap(aux)"); + fprintf(stderr, " failed to allocate AUX buffer: %lu/0x%lx, fd=%d, type=%d\n", + e->aux_size, e->aux_size, + e->fd, e->attr.type); + return 0; + } + e->aux_area = paux; + if (e->verbose >= 2) { + fprintf(stderr, "%p: aux buffer size = 0x%lx\n", e->aux_area, e->aux_size); + } + } +#endif /* PERF_RECORD_AUX */ + return 1; +} + + +static int event_setup_buffer(EventObject *e) +{ + return event_setup_buffer_aux(e, /*quiet=*/0); +} + + +/* + * Rebind an event object to a new perf_event_attr. + * Not well tested. + */ +static PyObject *event_bind(PyObject *x, PyObject *args, PyObject *kwds) +{ + EventObject *e = (EventObject *)x; + int rc; + (void)event_close(x); + rc = event_init(x, args, kwds); + if (rc != 0) { + PyErr_SetString(PyExc_ValueError, "bad value"); + return NULL; + } + return (PyObject *)e; +} + + +/* + * Given a leader event and an event id, find the event object. + * We might do this every time we read a sample record from the memory buffer, + * so it needs to be reasonably fast. Currently we scan a linked list of + * the leader's subordinates. Typically we only call this when the id + * is known to be a subordinate (or the leader itself) so we won't be doing + * a lot of full-length scans unnecessarily. + * Chaining lots of events together is likely to hit various other performance + * issues so currently we don't focus on making the lookup quicker. + */ +#if 0 +static EventObject *event_find_subordinate(EventObject const *e, unsigned long long id) +{ + assert(id != 0); + assert(e->buffer_owner == NULL); + while (e) { + /* As this is a frequently called routine, we shouldn't be + discovering the events' ids only now, we should have done + this as soon as we knew we might have to do this lookup. */ + assert(e->id != 0); + if (e->id == id) { + break; + } + e = e->next_sub; + } + /* Generally this will not be NULL. */ + return (EventObject *)e; +} +#endif + + +/* + * The __repr__ should be unambiguous. + * So it should contain the full contents of the object. TBD. + */ +static PyObject *event_repr(PyObject *x) +{ + EventObject const *e = (EventObject *)x; + return PyString_FromFormat("Event(type=%u,n=0x%x,cpu=%d)", + (unsigned int)e->attr.type, (unsigned int)e->attr.config, (int)e->cpu); +} + + +/* + * Return the byte string corresponding to the event's perf_event_attr. + * In Python2, this should be a bytearray(). + * In Python3, this should be a bytes() object. + * + * Better would be to return a PerfEventAttr object, but that would involve this + * module knowing about perf_attr. Instead, caller can do: + * PerfEventAttr(e.attr_struct) + */ +static PyObject *event_attr_struct(PyObject *x) +{ + EventObject const *e = (EventObject *)x; + return MyBytes_FromStringAndSize((char const *)&e->attr, sizeof e->attr); +} + + +/* + * Check whether new event(s) are available in the ring buffer, + * by inspecting the head pointer. + */ +static int event_available(EventObject *e) +{ + assert(e->mmap_page != NULL); + return e->mmap_page->data_tail != e->mmap_page->data_head; +} + + +/* + * Check whether an event record is available in the mmap buffer - + * first making sure that events are actually enabled. Non-blocking. + */ +static PyObject *event_poll(PyObject *x) +{ + EventObject *e = (EventObject *)x; + if (!e->mmap_page) { + if (!event_setup_buffer(e)) { + PyErr_SetString(PyExc_ValueError, "no buffer allocated"); + return NULL; + } + assert(e->mmap_page != NULL); + /* Very unlikely the event occurred between allocation and the below test, + but maybe perf has been waiting to put some events in. */ + } + if (e->attr.disabled && !e->attr.enable_on_exec) { + int rc = ioctl(e->fd, PERF_EVENT_IOC_ENABLE, 0); + if (rc < 0) { + perror("ioctl(ENABLE)"); + } + e->attr.disabled = 0; + } + if (e->verbose >= 1) { + fprintf(stderr, "[%d] polling: ", e->fd); + fprint_mmap_page_status(stderr, e->mmap_page); + } + return PyBool_FromLong(event_available(e)); +} + + +/* + * Test if an event still 'exists'. An event bound to a terminated subprocess will + * cease to exist, and our copy of its file descriptor will report ready when polled. + */ +static PyObject *event_is_active(PyObject *x) +{ + EventObject *e = (EventObject *)x; + static struct timespec const fto = { 0, 0 }; + struct pollfd fds = { e->fd, POLLIN, 0 }; + int rc = ppoll(&fds, 1, &fto, NULL); + if (e->verbose) { + if (rc == 1) { + fprintf(stderr, "poll(%d): revents=0x%x\n", e->fd, (unsigned int)fds.revents); + } else { + fprintf(stderr, "poll(%d): rc=%d\n", e->fd, rc); + perror("poll"); + } + } + /* It's active if the event's not ready, or if it's got some data, or if it's just there and hasn't hung up */ + /* Note that POLLIN takes priority over POLLHUP in case there's unconsumed data ready. */ + int is_active = (rc == 0) || (rc == 1 && ((fds.revents & POLLIN) != 0 || (fds.revents & POLLHUP) == 0)); + if (e->verbose) { + fprintf(stderr, "is_active: %d\n", is_active); + } + return PyBool_FromLong(is_active); +} + + +/* + * To read events from userspace, or to get the capabilities that say + * whether we can do that, we need at least the header page of the mmap buffer. + */ +static void ensure_minimal_mmap_page(EventObject *e) +{ + if (!e->mmap_page) { + if (e->verbose) { + fprintf(stderr, "[%d] ensuring mmap page\n", e->fd); + } + event_setup_buffer(e); + } + assert(e->mmap_page != NULL); +} + + +/* + * Get the event capabilities from the mmap page. If we haven't already + * allocated a page, allocate a minimal one now. + */ +static PyObject *event_capabilities(PyObject *x) +{ + EventObject *e = (EventObject *)x; + ensure_minimal_mmap_page(e); + // fprint_mmap_page(stderr, e->mmap_page); // TBD remove + return PyInt_FromLong(e->mmap_page->capabilities); +} + + +/* + * Close the event's file descriptor. We may need to do this to cause events + * to be flushed into the ring buffer. + */ +static PyObject *event_close(PyObject *x) +{ + EventObject *e = (EventObject *)x; + if (e->fd != -1) { +#ifdef PRINTF_DIAGNOSTICS + if (e->verbose) { + fprintf(stderr, "[%d] close event\n", e->fd); + } +#endif /* PRINTF_DIAGNOSTICS */ + int rc = close(e->fd); + if (rc != 0) { + PyErr_SetFromErrno(PyExc_OSError); + perror("close"); + return NULL; + } + /* Now delete the file handle from the map before it goes away. */ + fileno_events[e->fd] = NULL; + e->fd = -1; + if (e->group_leader) { + Py_DECREF(e->group_leader); + e->group_leader = NULL; + } + } + Py_RETURN_NONE; +} + + +static void event_free_buffers(PyObject *x) +{ + EventObject *e = (EventObject *)x; + if (e->mmap_page != NULL) { + int rc = munmap(e->mmap_page, e->mmap_size); + if (rc) { + perror("munmap"); + } + e->mmap_page = NULL; + } + if (e->aux_area != NULL) { + int rc = munmap(e->aux_area, e->aux_size); + if (rc) { + perror("munmap(aux)"); + } + e->aux_area = NULL; + } +} + + +static void event_dealloc(PyObject *x) +{ + EventObject *e = (EventObject *)x; + //fprintf(stderr, "-- event %p dealloc\n", e); +#ifdef PRINTF_DIAGNOSTICS + if (e->verbose && e->fd >= 0) { + fprintf(stderr, "[%d] event object deallocated when event open: closing\n", e->fd); + } +#endif /* PRINTF_DIAGNOSTICS */ + (void)event_close(x); + if (e->buffer_owner) { + Py_DECREF(e->buffer_owner); + e->buffer_owner = NULL; + } + event_free_buffers(x); + if (e->datasnap) { + Py_DECREF(e->datasnap); + } + x->ob_type->tp_free(x); +} + + +static void fprint_event_sample(FILE *fd, event_sample_t const *ed) +{ + fprintf(fd, "value: %llx, enabled: %llx, running: %llx\n", + ed->value, ed->time_enabled, ed->time_running); +} + + +static void subtract_base_event_values(event_sample_t *a, event_sample_t const *b) +{ + a->value -= b->value; + a->time_enabled -= b->time_enabled; + a->time_running -= b->time_running; +} + + +static void subtract_event_values(PyObject *a, PyObject const *b, EventObject *e) +{ + if (b) { + BaseReadingObject *ae = (BaseReadingObject *)a; + BaseReadingObject const *be = (BaseReadingObject const *)b; + subtract_base_event_values(&ae->sample, &be->sample); + if (e->attr.read_format & PERF_FORMAT_GROUP) { + GroupReadingObject *ag = (GroupReadingObject *)a; + GroupReadingObject const *bg = (GroupReadingObject const *)b; + unsigned int i; + for (i = 0; i < bg->n_values; ++i) { + subtract_base_event_values(&ag->samples[i], &bg->samples[i]); + } + } + } +} + + +/* + * Adjust a single value using the time enabled/running counters. + * After this call, the value is either a float, or None. + */ +static void postprocess_value(PyObject **vp, unsigned long long value, BaseReadingObject *br) +{ + if (*vp && *vp != Py_None) { + Py_DECREF(*vp); + } + if (br->fraction_running != 0.0) { + *vp = PyFloat_FromDouble(value / br->fraction_running); + Py_INCREF(*vp); + } else { + *vp = Py_None; + } +} + + +static void postprocess_reading(PyObject *x) +{ + BaseReadingObject *br = (BaseReadingObject *)x; + if (br->sample.time_enabled != 0.0) { + br->fraction_running = (double)br->sample.time_running / br->sample.time_enabled; + } else { + br->fraction_running = 0.0; + } + if (!(br->event->attr.read_format & PERF_FORMAT_GROUP)) { + ReadingObject *r = (ReadingObject *)x; + postprocess_value(&r->adjusted_value, br->sample.value, br); + } + if (br->event->verbose) { + double scale = (br->fraction_running ? (1.0 / br->fraction_running) : 0.0); + fprintf(stderr, "perf event %p: enabled=%llu running=%llu=%.5f", + br->event, + (unsigned long long)br->sample.time_enabled, + (unsigned long long)br->sample.time_running, + br->fraction_running); + if (!(br->event->attr.read_format & PERF_FORMAT_GROUP)) { + ReadingObject *r = (ReadingObject *)x; + fprintf(stderr, " value=%llu (adj=%.2f)\n", + (unsigned long long)r->base.sample.value, + r->base.sample.value * scale); + } else { + GroupReadingObject *r = (GroupReadingObject *)x; + unsigned int i; + fprintf(stderr, " values=%u:", (unsigned int)r->n_values); + for (i = 0; i < r->n_values; ++i) { + fprintf(stderr, " value=%llu (adj=%.2f)", + (unsigned long long)r->samples[i].value, + r->samples[i].value * scale); + } + fprintf(stderr, "\n"); + } + } +} + + +static PyObject *populate_reading_object_from_data(PyObject *x, void const *data, EventObject *e); + +static PyObject *perf_read_count_using_read(PyObject *x) +{ + /* + * Read counter data for an event using read(). + * x is a Reading or GroupReading object. + * If the event was PERF_FORMAT_GROUP, we are collecting multiple + * events in one operation on this file descriptor. + */ + int n; + int size_expected = -1; + unsigned long long buf[20]; /* 8 counters * (1+1) + 4 header */ + BaseReadingObject *base = (BaseReadingObject *)x; + EventObject *e = base->event; + size_t tr = perf_reading_size(e); + if (e->fd == -1) { + PyErr_SetString(PyExc_ValueError, "counter error - attempt to read closed counter"); + return 0; + } + assert(tr <= sizeof buf); + if (e->attr.read_format & PERF_FORMAT_GROUP) { + /* The amount to read is determined by the size of the group. + The kernel will return ENOSPC if we don't supply a big enough buffer. */ + n = read(e->fd, buf, sizeof buf); + if (n > 0) { + unsigned int n_values = (unsigned int)buf[0]; + size_expected = perf_reading_size_group(e, n_values); + } + } else { + n = read(e->fd, buf, tr); + size_expected = tr; + } + if (n > 0 && n != size_expected) { + PyErr_SetString(PyExc_ValueError, "unexpected size from read()"); + return 0; + } else if (n > 0) { + /* Observation was read as expected. */ + return populate_reading_object_from_data(x, buf, e); + } else if (n == 0) { + fprintf(stderr, "perf_events: tried to read while event in error state\n"); + /* Counter is in error state - see perf_event_open man page under "pinned" */ + PyErr_SetString(PyExc_ValueError, "counter error - event is in error state"); + return 0; + } else if (errno == ENOSPC) { + fprintf(stderr, "perf_events: event reading buffer too small\n"); + PyErr_SetString(PyExc_ValueError, "counter error - buffer not big enough"); + return 0; + } else { + fprintf(stderr, "perf_events: unexpected error, errno=%u\n", errno); + PyErr_SetString(PyExc_ValueError, "counter error"); + return 0; + } +} + + +static inline void barrier(void) +{ +#if defined(__arm64__) || defined(__AARCH64EL__) || defined(__ARM_ARCH_ISA_A64) || defined(__ARMEL__) + __asm__ __volatile__("isb":::); +#elif defined(__x86_64__) + __asm__ __volatile__("sfence":::); +#endif +} + + +/* + * Read the hardware timestamp. + * Note that 0 is a valid (if very unlikely) value of a working timestamp. + */ +static inline unsigned long long hardware_timestamp(void) +{ + unsigned long long cyc = 0; +#if defined(__arm64__) || defined(__AARCH64EL__) || defined(__ARM_ARCH_ISA_A64) + __asm__ __volatile__("mrs %0,cntvct_el0":"=r"(cyc)::); +#elif defined(__ARMEL__) + unsigned int hi, lo; + __asm__ __volatile__("mrrc p15,1,%0,%1,c14":"=r"(lo),"=r"(hi)::); + cyc = ((unsigned long long)hi << 32) | lo; +#elif defined(__x86_64__) + unsigned int hi, lo; + __asm__ __volatile__("rdtsc":"=a"(lo),"=d"(hi)); + cyc = ((unsigned long long)hi << 32) | lo; +#else + cyc = 0xBADBAD; +#endif + return cyc; +} + + +/* + * Frequency of the hardware timestamp (not the core clock frequency). + * This could be derived from the time conversion parameters in the + * mmap header, but we may also be able to get it directly. + */ +static inline unsigned long long hardware_timestamp_frequency(void) +{ + unsigned long long freq = 0; +#if defined(__arm64__) || defined(__AARCH64EL__) || defined(__ARM_ARCH_ISA_A64) + __asm__ __volatile__("mrs %0,cntfrq_el0":"=r"(freq)::); +#elif defined(__ARMEL__) + unsigned int lo; /* In AArch32 we only see a 32-bit CNTFRQ */ + __asm__ __volatile__("mrc p15,0,%0,c14,c0,0":"=r"(lo)::); + freq = lo; +#else + // TBD +#endif + return freq; +} + + +/* + * Read a hardware PMU register, given the register selector. + * + * For general events this will be a small integer from 0 upwards. + * In the mmap header, the number is offset by 1 (because 0 indicates the + * event can't be read from a counter). We are called with the actual + * counter number i.e. 0 means counter #0. + * + * For x86, fixed-function register selectors are: + * 40000000: IA32_FIXED_CTR0 INST_RETIRED.ANY + * 40000001: IA32_FIXED_CTR1 CPU_CLK_UNHALTED.THREAD + * 40000002: IA32_FIXED_CTR2 CPU_CLK_UNHALTED.REF_TSC + * 40000003: IA32_FIXED_CTR3 TOPDOWN.SLOTS + */ +static inline unsigned long long rdpmc(unsigned int idx) +{ + unsigned long long count = 0; +#if defined(__arm64__) || defined(__AARCH64EL__) || defined(__ARM_ARCH_ISA_A64) + switch (idx) { + /* ARM PMU architecture defines up to 31 counter registers */ +#define REV(idx) case (idx): __asm__ __volatile__("mrs %0,pmevcntr" #idx "_el0":"=r"(count)); break + REV(0); + REV(1); + REV(2); + REV(3); + REV(4); + REV(5); + REV(6); + REV(7); + REV(8); + REV(9); + REV(10); + REV(11); + REV(12); + REV(13); + REV(14); + REV(15); + REV(16); + REV(17); + REV(18); + REV(19); + REV(20); + REV(21); + REV(22); + REV(23); + REV(24); + REV(25); + REV(26); + REV(27); + REV(28); + REV(29); + REV(30); +#undef REV + case 31: + /* Counter 31 is the dedicated cycle counter */ + __asm__ __volatile__("mrs %0,pmccntr_el0":"=r"(count)); + break; + default: + assert(0); + } +#elif defined(__x86_64__) + unsigned int hi, lo; + __asm__ __volatile__("rdpmc":"=a"(lo),"=d"(hi):"c"(idx)); + count = ((unsigned long long)hi << 32) | lo; +#endif + return count; +} + + +/* + * Try to read the current event value from userspace, into an event_sample_t. + * Return 1 if successful, 0 if unsuccessful. + * + * This only makes sense if we're monitoring either + * - our own thread, and nothing else + * - this core, and nothing else + * It probably doesn't make sense for grouped objects either, since we + * can't guarantee to read all counters in a group without a schedule. + */ +static int perf_read_count_userspace(event_sample_t *ed, EventObject *e) +{ + if (!e->mmap_page) { + fprintf(stderr, "perf event: read_count_userspace called with no buffer\n"); + ensure_minimal_mmap_page(e); + } + struct perf_event_mmap_page volatile *mp = e->mmap_page; + /* First test to see if this event is readable from userspace. + We assume the 'capabilities' don't change during the lifetime of the event. */ + const unsigned int caps_needed = _cap_user_rdpmc|_cap_user_time; + if ((mp->capabilities & caps_needed) != caps_needed) { + /* Can't read PMU from userspace */ + return 0; + } + unsigned int seq; + unsigned long long enabled, running; + unsigned int time_mult, time_shift; + unsigned long long cyc, time_offset; + unsigned int idx, width=0; + unsigned long long count_offset, count_value=0; + do { + seq = mp->lock; + barrier(); + enabled = mp->time_enabled; + running = mp->time_running; + if (1 /* mp->capabilities & _cap_user_time */) { + cyc = hardware_timestamp(); + time_offset = mp->time_offset; + time_mult = mp->time_mult; + time_shift = mp->time_shift; + } + count_offset = mp->offset; + idx = mp->index; + if ((mp->capabilities & _cap_user_rdpmc) && idx != 0) { /* cap_user_rdpmc */ + /* This event is currently scheduled on to a hardware counter. */ + width = mp->pmc_width; + count_value = rdpmc(idx - 1); + } + barrier(); + } while (mp->lock != seq); + if (0) { + fprintf(stderr, "-- [%u] read_count_userspace, caps=0x%x:\n", e->fd, (unsigned int)mp->capabilities); + if (mp->capabilities & _cap_user_time) { + fprintf(stderr, "-- cyc=0x%llx time_offset=0x%llx 0x%llx time_mult=%u/0x%x time_shift=%u\n", + cyc, time_offset, cyc-time_offset, time_mult, time_mult, time_shift); + } + if ((mp->capabilities & _cap_user_rdpmc) && idx != 0) { + fprintf(stderr, "-- idx=%u/0x%x width=%u count_offset=0x%llx count_value=0x%llx adj-count=0x%llx\n", + idx, idx, width, count_offset, count_value, count_offset+count_value); + } + fprintf(stderr, "-- enabled=%llx running=%llx\n", enabled, running); + } + if (idx != 0) { + /* The hardware counter value needs to be sign-extended before use. */ + count_value = (signed long long)(count_value << (64-width)) >> (64-width); + count_value += count_offset; + } else { + count_value = count_offset; + } + { + unsigned long long quot, rem, delta; + quot = (cyc >> time_shift); + rem = cyc & ((1ULL << time_shift) - 1); + delta = time_offset + quot*time_mult + ((rem*time_mult) >> time_shift); + enabled += delta; + if (idx != 0) { + running += delta; + } + } + ed->value = count_value; + ed->time_enabled = enabled; /* should add current time to this? */ + ed->time_running = running; /* ditto */ + ed->id = e->id; + if (0) { + fprintf(stderr, "-- value in mmap: "); + fprint_event_sample(stderr, ed); + } + return 1; +} + + +/* + * Read a counter event's value(s). + * Use userspace if available, else use read(). + */ +static int perf_read_count(PyObject *x) +{ + int ok; + BaseReadingObject *base = (BaseReadingObject *)x; + EventObject *e = base->event; + if (e->try_userspace_read) { + ok = perf_read_count_userspace(&base->sample, e); + if (ok) { + if (0) { + /* Consistency check against read() values */ + event_sample_t *ed = &base->sample; + event_sample_t edr = *ed; + perf_read_count_using_read(x); + if (ed->value < edr.value) { + fprintf(stderr, "[%u] mmap: ", e->fd); + fprint_event_sample(stderr, ed); + fprintf(stderr, "[%u] read: ", e->fd); + fprint_event_sample(stderr, &edr); + } + assert(ed->value >= edr.value); + } + postprocess_reading(x); + return ok; + } + } + ok = !!perf_read_count_using_read(x); + if (e->datasnap != NULL) { + /* Subtract event data from the baseline. */ + subtract_event_values(x, e->datasnap, e); + } + postprocess_reading(x); + return ok; +} + + +/* +Reset an event's value to zero - at least as far as the API is concerned. + +About PERF_EVENT_IOC_RESET: +"This resets only the counts; there is no way to reset the multiplexing +time_enabled or time_running values." + +So instead, we snapshot the counter values, and present future values as +a delta against that. +*/ +static PyObject *event_read(PyObject *x); +static PyObject *event_reset(PyObject *x) +{ + EventObject *e = (EventObject *)x; + if (0) { + int rc = ioctl(e->fd, PERF_EVENT_IOC_RESET, 0); + if (rc != 0) { + PyErr_SetString(PyExc_ValueError, "bad ioctl(RESET)"); + return NULL; + } + return PyInt_FromLong(rc); + } else { + if (e->datasnap) { + Py_DECREF(e->datasnap); + e->datasnap = NULL; + } + e->datasnap = event_read(x); + //fprintf(stderr, "-- [%u] snapshot %llx\n", e->fd, e->datasnap.value); + return PyInt_FromLong(0); /* success */ + } +} + + +static PyObject *event_refresh(PyObject *x, PyObject *arg) +{ + EventObject *e = (EventObject *)x; + int rc; + int n = PyLong_AsLong(arg); + rc = ioctl(e->fd, PERF_EVENT_IOC_REFRESH, n); + if (rc < 0) { + return NULL; + } + return PyInt_FromLong(rc); +} + + +static PyObject *event_pause(PyObject *x) +{ + EventObject *e = (EventObject *)x; + int rc = ioctl(e->fd, PERF_EVENT_IOC_PAUSE_OUTPUT, 1); + return PyInt_FromLong(rc); +} + + +static PyObject *event_resume(PyObject *x) +{ + EventObject *e = (EventObject *)x; + int rc = ioctl(e->fd, PERF_EVENT_IOC_PAUSE_OUTPUT, 0); + return PyInt_FromLong(rc); +} + + +/* + * fileno() method - as for Python file objects. + * This means the Event object can be used directly in e.g. select.poll.register(). + */ +static PyObject *event_fileno(PyObject *x) +{ + EventObject *e = (EventObject *)x; + return PyInt_FromLong(e->fd); +} + + +static PyObject *event_enable(PyObject *x) +{ + EventObject *e = (EventObject *)x; + int rc = ioctl(e->fd, PERF_EVENT_IOC_ENABLE, 0); + if (rc != 0) { + PyErr_SetString(PyExc_ValueError, "bad ioctl(ENABLE)"); + return NULL; + } + e->attr.disabled = 0; + return PyInt_FromLong(rc); +} + + +static PyObject *event_disable(PyObject *x) +{ + EventObject *e = (EventObject *)x; + int rc = ioctl(e->fd, PERF_EVENT_IOC_DISABLE, 0); + if (rc != 0) { + PyErr_SetString(PyExc_ValueError, "bad ioctl(DISABLE)"); + return NULL; + } + e->attr.disabled = 1; + return PyInt_FromLong(rc); +} + + +/* + * Pass a filter to the kernel. See kernel/events/core.c for syntax. + * Address filters for hardware trace have this syntax: + * + * filter - limit tracing to a range + * start - start when execution enters this range + * stop - stop when execution enters this range + * + * is + * + * [/] - kernel address + * [/]@object - address in module + * + * "perf record" accepts a more general syntax that can resolve + * symbol names: see tools/perf/Documentation/perf-record.txt + */ +static PyObject *event_set_filter(PyObject *x, PyObject *s) +{ + EventObject *e = (EventObject *)x; + char const *str = PyString_AsString(s); + if (str) { + if (e->verbose) { + fprintf(stderr, "[%d]: set filter \"%s\"\n", e->fd, str); + } + int rc = ioctl(e->fd, PERF_EVENT_IOC_SET_FILTER, str); + if (rc != 0) { + if (e->verbose) { + perror("ioctl"); + } + PyErr_SetString(PyExc_ValueError, "bad ioctl(SET_FILTER)"); + return NULL; + } else { + /* filter was set successfully: return self */ + Py_INCREF(x); + return x; + } + } else { + PyErr_SetString(PyExc_ValueError, "expected string"); + return NULL; + } +} + + +static int event_get_id(EventObject *e) +{ + if (e->id == 0) { + int rc = ioctl(e->fd, PERF_EVENT_IOC_ID, &e->id); + if (rc != 0) { + return 0; + } + } + return 1; +} + + +static PyObject *event_id(PyObject *x) +{ + EventObject *e = (EventObject *)x; + if (!event_get_id(e)) { + PyErr_SetString(PyExc_ValueError, "bad ioctl"); + return NULL; + } + return PyLong_FromUnsignedLongLong(e->id); +} + + +static PyObject *basereading_new(PyTypeObject *ot, PyObject *args, PyObject *kwds) +{ + assert(0); + return NULL; +} + +static PyObject *reading_new(PyTypeObject *ot, PyObject *args, PyObject *kwds) +{ + ReadingObject *t = (ReadingObject *)ot->tp_alloc(ot, 0); + assert(t->base.event == NULL); + //fprintf(stderr, "-- reading %p alloc\n", t); + return (PyObject *)t; +} + + +static PyObject *groupreading_new(PyTypeObject *ot, PyObject *args, PyObject *kwds) +{ + GroupReadingObject *t = (GroupReadingObject *)ot->tp_alloc(ot, 0); + assert(t->base.event == NULL); + t->samples = NULL; + return (PyObject *)t; +} + + +static void basereading_dealloc(PyObject *x) +{ + assert(0); +} + +static void reading_dealloc(PyObject *x) +{ + ReadingObject *r = (ReadingObject *)x; + //fprintf(stderr, "-- reading %p dealloc\n", r); + Py_DECREF(r->base.event); + r->base.event = NULL; + if (r->adjusted_value != Py_None) { + Py_DECREF(r->adjusted_value); + } + x->ob_type->tp_free(x); +} + +static void groupreading_dealloc(PyObject *x) +{ + GroupReadingObject *r = (GroupReadingObject *)x; + Py_DECREF(r->base.event); + free(r->samples); + x->ob_type->tp_free(x); +} + + +/* + * A reading is missing if the task was never scheduled, or if it was + * scheduled but the event was never assigned to a counter. + */ +static PyObject *reading_is_missing(PyObject *x) +{ + BaseReadingObject *r = (BaseReadingObject *)x; + return PyBool_FromLong(r->sample.time_running == 0); +} + +/* + * A reading is incomplete if the task was scheduled but the event + * was not always assigned to a counter. This includes both the case + * where the event was sometimes assigned to a counter (and 'value' + * will be scaled) and when it was never assigned to a counter + * (and 'value' is None). + */ +static PyObject *reading_is_incomplete(PyObject *x) +{ + BaseReadingObject *r = (BaseReadingObject *)x; + assert(r->sample.time_running <= r->sample.time_enabled); + return PyBool_FromLong(r->sample.time_running != r->sample.time_enabled); +} + + +static PyObject *reading_str(PyObject *x) +{ + ReadingObject *r = (ReadingObject *)x; + if (!r->base.sample.time_enabled) { + return PyString_FromFormat(""); + } else if (r->base.fraction_running == 1.0) { + return PyString_FromFormat("%llu", r->base.sample.value); + } else { + /* PyString_FromFormat doesn't support floats, so we print + the raw enabled/running values */ + char adj_value_string[100]; + if (r->adjusted_value != Py_None) { + sprintf(adj_value_string, "adjusted value %f", PyFloat_AsDouble(r->adjusted_value)); + } else { + strncpy(adj_value_string, "no value", 10); + } + return PyString_FromFormat("%llu (running %llu enabled %llu, %s)", + r->base.sample.value, r->base.sample.time_running, r->base.sample.time_enabled, adj_value_string); + } +} + + +static PyObject *groupreading_str(PyObject *x) +{ + GroupReadingObject *r = (GroupReadingObject *)x; + if (!r->base.sample.time_enabled) { + return PyString_FromFormat(""); + } else { + return PyString_FromFormat("GroupReading(%u values)", r->n_values); + } +} + + +static Py_ssize_t groupreading_seq_length(PyObject *x) +{ + GroupReadingObject *r = (GroupReadingObject *)x; + return r->n_values; +} + + +static ReadingObject *create_reading_object(EventObject *e); + +static PyObject *groupreading_seq_item(PyObject *x, Py_ssize_t i) +{ + GroupReadingObject *r = (GroupReadingObject *)x; + ReadingObject *nr; + if (i < 0 || i >= r->n_values) { + return NULL; + } + nr = create_reading_object(r->base.event); + nr->base.sample = r->samples[i]; + postprocess_value(&nr->adjusted_value, nr->base.sample.value, &r->base); + return (PyObject *)nr; +} + + +/* + * Create a ReadingObject and bind it to an event. + */ +static ReadingObject *create_reading_object(EventObject *e) +{ + ReadingObject *r = (ReadingObject *)PyObject_CallObject((PyObject *)&ReadingType, NULL); + assert(e != NULL); + Py_INCREF(e); + r->base.event = e; + return r; +} + + +/* + * Create a GroupReading object, but don't yet create the array of samples. + */ +static GroupReadingObject *create_group_reading_object(EventObject *e) +{ + GroupReadingObject *r = (GroupReadingObject *)PyObject_CallObject((PyObject *)&GroupReadingType, NULL); + assert(e != NULL); + Py_INCREF(e); + r->base.event = e; + return r; +} + + +static PyObject *create_correct_reading_object(EventObject *e) +{ + return (e->attr.read_format & PERF_FORMAT_GROUP) ? + (PyObject *)create_group_reading_object(e) : + (PyObject *)create_reading_object(e); +} + + +/* + * Create a Reading object from a 'struct read_format', either read from + * the file descriptor (perf stat) or from a PERF_SAMPLE_READ (perf record). + * Fill in the 'adjusted_value' field with a Python object to represent + * the value adjusted for the event's running-fraction - None if the event + * was never running. + */ +#if 0 +static void perf_update_reading(ReadingObject *, event_sample_t const *); +static ReadingObject *reading_from_data(event_sample_t const *ed, EventObject const *e, ReadingObject *r) +{ + assert(!(e->attr.read_format & PERF_FORMAT_GROUP)); + EventObject *re = (EventObject *)e; + if (ed->id != 0 && ed->id != e->id) { + /* A sampling event might have been written to its parent's buffer. + Look up the actual event. */ + re = event_find_subordinate(e, ed->id); + if (!re) { + fprintf(stderr, "perf event: unexpected event id: 0x%llX\n", ed->id); + assert(0); + } + } + if (!r) { + r = create_reading_object(re); + } + assert(r->base.event == e); + perf_update_reading(r, ed); + return r; +} +#endif + + +#if 0 +static void perf_update_reading(ReadingObject *r, event_sample_t const *ed) +{ + EventObject const *e = r->base.event; + //fprintf(stderr, "-- [%u] org value =%llx datasnap = %llx\n", e->fd, ed->value, e->datasnap.value); + /* Because we implement event_reset() by taking a snapshot, we now recalulate + all the event metrics as a delta against that snapshot. */ + assert(ed->value >= e->datasnap.value); + r->base.sample.value = ed->value - e->datasnap.value; + r->base.sample.time_enabled = ed->time_enabled - e->datasnap.time_enabled; + r->base.sample.time_running = ed->time_running - e->datasnap.time_running; + if (r->base.sample.time_enabled != 0.0) { + r->base.fraction_running = (double)r->base.sample.time_running / r->base.sample.time_enabled; + if (r->base.fraction_running != 0.0) { + /* Increase the value to compensate for partial sampling */ + if (r->adjusted_value && r->adjusted_value != Py_None) { + Py_DECREF(r->adjusted_value); + } + r->adjusted_value = PyFloat_FromDouble(r->base.sample.value / r->base.fraction_running); + } else { + r->adjusted_value = Py_None; + } + } else { + r->base.fraction_running = 0.0; + r->adjusted_value = Py_None; + } + if (e->verbose) { + double adjv = (r->base.fraction_running ? (r->base.sample.value / r->base.fraction_running) : 0.0); + fprintf(stderr, "perf event %p: value=%llu enabled=%llu running=%llu=%.5f adjusted=%.2f\n", + e, + (unsigned long long)r->base.sample.value, + (unsigned long long)r->base.sample.time_enabled, + (unsigned long long)r->base.sample.time_running, + r->base.fraction_running, + adjv); + } + Py_INCREF(r->adjusted_value); +} +#endif + + +static unsigned long long const *read_data_to_sample(event_sample_t *ed, unsigned long long const *p, EventObject const *e) +{ + if (e->attr.read_format & PERF_FORMAT_TOTAL_TIME_ENABLED) { + ed->time_enabled = *p++; + } else { + ed->time_enabled = 0xCCCCCCCC; + } + if (e->attr.read_format & PERF_FORMAT_TOTAL_TIME_RUNNING) { + ed->time_running = *p++; + } else { + ed->time_running = 0xCCCCCCCC; + } + return p; +} + + +/* + * Populate a Reading or GroupReading object from a data buffer either read from read() + * or in a record in the mmap buffer. + */ +static PyObject *populate_reading_object_from_data(PyObject *x, void const *data, EventObject *e) +{ + unsigned long long const *p = (unsigned long long const *)data; + if (!(e->attr.read_format & PERF_FORMAT_GROUP)) { + ReadingObject *r = (ReadingObject *)x; + event_sample_t *ed = &r->base.sample; + ed->value = *p++; + p = read_data_to_sample(ed, p, e); + if (e->attr.read_format & PERF_FORMAT_ID) { + ed->id = *p++; + } else { + ed->id = 0xCCCCCCCC; + } + } else { + GroupReadingObject *g = (GroupReadingObject *)x; + event_sample_t *ed = &g->base.sample; + g->n_values = (unsigned int)*p++; + unsigned int i; + p = read_data_to_sample(ed, p, e); + g->samples = (event_sample_t *)malloc(g->n_values * sizeof(event_sample_t)); + for (i = 0; i < g->n_values; ++i) { + event_sample_t *sed = &g->samples[i]; /* array entry to write into */ + *sed = *ed; + sed->value = *p++; + if (e->attr.read_format & PERF_FORMAT_ID) { + sed->id = *p++; + } else { + sed->id = 0xCCCCCCCC; + } + } + } + return x; +} + + +/* + * Create a Reading or GroupReading object from data. + */ +static PyObject *create_reading_object_from_data(void const *data, EventObject *e) +{ + PyObject *x = create_correct_reading_object(e); + x = populate_reading_object_from_data(x, data, e); + return x; +} + + +/* +Read the current value of an event counter, as a Reading object. +We hope it hasn't wrapped. A Reading object may be passed in - its data +will be discarded. + +We only expect to call this on a counting event, not a sampling event. +*/ +static PyObject *take_reading(EventObject *e, PyObject *r) +{ + if (!r) { + r = create_correct_reading_object(e); + } + if (perf_read_count(r)) { + return (PyObject *)r; + } else { + return NULL; + } +} + + +/* + * Return a new Reading or GroupReading object + */ +static PyObject *event_read(PyObject *x) +{ + EventObject *e = (EventObject *)x; + PyObject *r = take_reading(e, NULL); + //Py_INCREF(r); + return r; +} + + +/* + * Update a Reading object + */ +static PyObject *reading_update(PyObject *x) +{ + ReadingObject *r = (ReadingObject *)x; + //fprintf(stderr, "reading %p event %p\n", r, r->event); + assert(r->base.event != NULL); + PyObject *rn = take_reading(r->base.event, x); + /* Returning 'self' creates a new reference, so we must increment the + reference count to avoid being discarded. */ + Py_INCREF(rn); + return rn; +} + + +/* + * The __str__ should be human-readable. + */ +static PyObject *event_str(PyObject *x) +{ + EventObject const *e = (EventObject *)x; + return PyString_FromFormat("event[%d](type=%u,n=0x%x,cpu=%d)[%sabled]", + e->fd, (unsigned int)e->attr.type, (unsigned int)e->attr.config, (int)e->cpu, (e->attr.disabled ? "dis" : "en")); +} + + +/* + * Python object corresponding to a sampled event or other record - as acquired + * from the memory mapped buffer. This object is logically read-only + * once acquired. + */ +typedef struct { + PyObject_HEAD + EventObject *event; /* back-pointer to the sampling event we got this from */ + unsigned long offset; /* original offset of this record in the buffer */ + size_t data_size; /* total size of the collected data */ + struct perf_event_header head; /* includes type, size etc. */ + void *data; /* variable amount of data, specific to record type: includes header */ + PyObject *aux; /* for PERF_RECORD_AUX: AUX buffer segment corresponding to this record */ +} RecordObject; + + +/* + * Return the previously collected record payload as a binary string object. + * This includes: + * the standard record header (perf_event_header) + * the payload + * the 'struct sample_id' possibly present at the end of the payload + * This matches the record that gets written to perf.data. + * + * N.b. this means we copy twice: once out of perf's mmap ring buffer into the + * Record's malloc'ed buffer, and then again when we return the string object. + * We could do better by creating a string to start with. + */ +static PyObject *record_data(PyObject *x) +{ + RecordObject *s = (RecordObject *)x; + return MyBytes_FromStringAndSize(s->data, s->data_size); +} + + +static PyObject *record_new(PyTypeObject *t, PyObject *args, PyObject *kwds) +{ + RecordObject *s = (RecordObject *)t->tp_alloc(t, 0); + assert(s != NULL); + assert(s->event == NULL); + s->data = NULL; + s->aux = Py_None; + Py_INCREF(s->aux); + return (PyObject *)s; +} + + +static char const *record_type_name(unsigned int type) +{ + unsigned int i; + char const *typestr = NULL; + static struct { + char const *name; + unsigned int type; + } const typestrs[] = { +#define TYPE(x) { #x, PERF_RECORD_##x } + TYPE(MMAP), + TYPE(LOST), + TYPE(COMM), + TYPE(EXIT), + TYPE(THROTTLE), + TYPE(UNTHROTTLE), + TYPE(FORK), + TYPE(READ), + TYPE(SAMPLE), + TYPE(MMAP2), +#ifdef PERF_RECORD_MMAP + /* Older kernels have these as macros, so we can test each one. */ +#ifdef PERF_RECORD_AUX + TYPE(AUX), +#endif /* PERF_RECORD_AUX */ +#ifdef PERF_RECORD_ITRACE_START + TYPE(ITRACE_START), +#endif /* PERF_RECORD_ITRACE_START */ +#ifdef PERF_RECORD_LOST_SAMPLES + TYPE(LOST_SAMPLES), +#endif /* PERF_RECORD_LOST_SAMPLES */ +#ifdef PERF_RECORD_SWITCH + TYPE(SWITCH), +#endif /* PERF_RECORD_SWITCH */ +#ifdef PERF_RECORD_SWITCH_CPU_WIDE + TYPE(SWITCH_CPU_WIDE) +#endif /* PERF_RECORD_SWITCH_CPU_WIDE */ +#else + /* PERF_RECORD_MMAP not being #define'd, indicates we're now using enumerators. + So we have to hope that we have the full set. */ + TYPE(AUX), + TYPE(ITRACE_START), + TYPE(LOST_SAMPLES), + TYPE(SWITCH), + TYPE(SWITCH_CPU_WIDE) +#endif +#undef TYPE + }; + for (i = 0; i < sizeof(typestrs)/sizeof(typestrs[0]); ++i) { + if (type == typestrs[i].type) { + typestr = typestrs[i].name; + break; + } + } + return typestr; +} + + + + +/* + * Create a Reading or GroupReading object from data in a record. + */ +static PyObject *record_reading(PyObject *x) +{ + RecordObject const *s = (RecordObject *)x; + if (s->head.type == PERF_RECORD_SAMPLE && + s->event->attr.sample_type & PERF_SAMPLE_READ) { + /* Find the read object in the sample payload */ + unsigned int const offs = sample_offset_to_read(&s->event->attr); + return create_reading_object_from_data((unsigned char const *)s->data + offs, s->event); + } else { + /* Presence/absence of a read object is a property of the sample type and configuration. + It's reasonable to throw an exception if we ask for one invalidly. */ + PyErr_SetString(PyExc_ValueError, "record does not contain a counter reading"); + return NULL; + } +} + + +static PyObject *record_is_sample(PyObject *x) +{ + RecordObject const *s = (RecordObject *)x; + return PyBool_FromLong(s->head.type == PERF_RECORD_SAMPLE); +} + + +static PyObject *record_str(PyObject *x) +{ + RecordObject const *s = (RecordObject *)x; + char const *typestr = record_type_name(s->head.type); + if (!typestr) { + typestr = "?"; + } + return PyString_FromFormat("Record(%s,databytes=%u)", + typestr, (unsigned int)s->data_size); +} + + +static void record_dealloc(PyObject *x) +{ + RecordObject *s = (RecordObject *)x; + free(s->data); + Py_DECREF(s->event); + Py_DECREF(s->aux); + x->ob_type->tp_free(x); +} + + +static struct PyMethodDef Record_methods[] = { + {"data", (PyCFunction)&record_data, METH_NOARGS, "string: raw data"}, + {"reading", (PyCFunction)&record_reading, METH_NOARGS, "Reading: event value reading"}, + {"is_sample", (PyCFunction)&record_is_sample, METH_NOARGS, "bool: record is a sample"}, + {"__bytes__", (PyCFunction)&record_data, METH_NOARGS, "string: raw data"}, + {NULL} +}; + +static struct PyMemberDef Record_members[] = { + {"event", T_OBJECT, offsetof(RecordObject, event), 0, "event that record was read from"}, + {"offset", T_LONG, offsetof(RecordObject, offset), 0, "byte offset in mmap buffer"}, + {"type", T_INT, offsetof(RecordObject, head.type), 0, "record type"}, + {"misc", T_SHORT, offsetof(RecordObject, head.misc), 0, "record mode and flags"}, + {"size", T_SHORT, offsetof(RecordObject, head.size), 0, "record total size (including header)"}, + {"aux", T_OBJECT, offsetof(RecordObject, aux), 0, "AUX buffer contents"}, + {NULL} +}; + + +static PyTypeObject RecordType = { + PyVarObject_HEAD_INIT(NULL, 0) + .tp_basicsize = sizeof(RecordObject), + .tp_name = "perf_events.Record", + .tp_doc = "perf event", + .tp_flags = Py_TPFLAGS_DEFAULT, + .tp_methods = Record_methods, + .tp_members = Record_members, +// tp_repr: sample_repr, + .tp_str = record_str, + .tp_alloc = 0, + .tp_new = record_new, +// tp_init: sample_init, + .tp_dealloc = record_dealloc +}; + + +/* + * Copy 'len' bytes from a buffer which may have wrapped. + * 'offset' is the non-wrapping offset into the buffer - continually increasing + * (as for perf buffers) which must be wrapped into a real offset before use. + */ +void copy_from_wrapped_buffer(void *dst, void const *vbuf, size_t buf_size, size_t virtual_offset, size_t len) +{ + unsigned int real_offset = virtual_offset % buf_size; + unsigned int fs = buf_size - real_offset; + assert(len <= buf_size); + if (fs > len) { + fs = len; + } + /* fs is now the first part of the data to copy (all of it, unless wrapped) */ + memcpy(dst, (unsigned char const *)vbuf + real_offset, fs); + if (fs < len) { + /* data wrapped, copy remainder from the beginning */ + memcpy((unsigned char *)dst + fs, vbuf, len - fs); + } +} + + +#if defined(PERF_RECORD_AUX) || !defined(PERF_RECORD_MMAP) +/* + * There are two ways we could retrieve data from the AUX buffer: + * + * - we can directly poll and update the head/tail pointers like we do for the + * main mmap ring buffer + * + * - we can use the (offset,size) information that we are given in PERF_RECORD_AUX + * records that we get from the main mmap ring buffer. We would expect these + * notifications to occur in order, so that the oldest such outstanding notification + * has the data at the tail pointer. + */ + +/* Manage the AUX buffer tail - factored out in case we use a read-only AUX buffer */ + +static unsigned long event_aux_tail(EventObject *e) +{ + return e->mmap_page->aux_tail; +} + + +static void event_update_aux_tail(EventObject *e, unsigned long na) +{ + if (e->verbose) { + fprintf(stderr, "updating tail from 0x%llx to 0x%lx; head at 0x%llx\n", e->mmap_page->aux_tail, na, e->mmap_page->aux_head); + } + assert(na <= e->mmap_page->aux_head); /* tail must not advance past head */ + e->mmap_page->aux_tail = na; + __sync_synchronize(); +} +#endif /* PERF_RECORD_AUX */ + + +/* + * Get a chunk of AUX data, of a given length. + * This consumes data directly from the mmap'ed AUX buffer. + * Normally it's better to have the data from the AUX buffer consumed by + * reading the corresponding PERF_RECORD_AUX from the main mmap buffer. + */ +static PyObject *get_aux_data(EventObject *e, unsigned int len) +{ + PyObject *s; + if (!e->mmap_page || !e->aux_area) { + Py_RETURN_NONE; + } + if (len == 0) { + Py_RETURN_NONE; + } + /* Get the AUX data. Python lets us construct a buffer object of the required + length and then write directly into it. */ + s = MyBytes_FromStringAndSize(NULL, len); + copy_from_wrapped_buffer(MyBytes_AsString(s), e->aux_area, e->aux_size, event_aux_tail(e), len); + event_update_aux_tail(e, e->mmap_page->aux_tail + len); + return s; +} + + +/* + * Get as big a chunk of AUX data as we can. + */ +static PyObject *event_get_aux(PyObject *x) +{ +#if defined(PERF_RECORD_AUX) || !defined(PERF_RECORD_MMAP) + EventObject *e = (EventObject *)x; + /* Make sure to read aux_head just once, in case it moves on while we're consuming the tail */ + unsigned int len = e->mmap_page->aux_head - e->mmap_page->aux_tail; + return get_aux_data(e, len); +#else /* !PERF_RECORD_AUX */ + Py_RETURN_NONE; +#endif /* PERF_RECORD_AUX */ +} + + +/* + * Collect one record from the mmap buffer - return a Record event if + * an event is available, otherwise return None. + * Event source must already have been set up for sampling, e.g. by calling poll(). + */ +static PyObject *event_get_record(PyObject *x) +{ + EventObject *e = (EventObject *)x; + if (!e->mmap_page) { + /* Never going to return an event until we set up the buffer - + should we raise an exception? */ + Py_RETURN_NONE; + } + if (!event_available(e)) { + Py_RETURN_NONE; + } + /* A sample is available. Construct a new Record object. */ + struct perf_event_header head; + /* Populate the sample object from the mmap'ed sample buffer. + This is slightly tricky as the buffer may wrap around in the + sample - in the header, between header and data or in the data. */ + copy_from_wrapped_buffer(&head, e->mmap_data_start, e->mmap_data_size, e->mmap_page->data_tail, sizeof(struct perf_event_header)); +#ifdef PRINTF_DIAGNOSTICS + if (e->verbose) { + char const *typestr = record_type_name(head.type); + if (!typestr) { + typestr = "?"; + } + fprintf(stderr, "%u: event record available: total record size: %u type: %u (%s); samples expected: ", + e->fd, head.size, head.type, typestr); + fprint_flags(stderr, e->attr.sample_type, FLAG_NAMES(sample_flagnames)); + fprintf(stderr, "\n"); + } +#endif /* PRINTF_DIAGNOSTICS */ + if (head.size < sizeof(struct perf_event_header) || + head.size > e->mmap_data_size) { + /* Corrupt */ + fprintf(stderr, "sample corrupt: length = %ld\n", (long)head.size); + return NULL; + } + /* We could make Record flexibly sized, but for now we have a separate buffer */ + RecordObject *s = (RecordObject *)PyObject_CallObject((PyObject *)&RecordType, NULL); + s->offset = e->mmap_page->data_tail; + s->head = head; /* Copy the (small) head structure */ + s->data_size = head.size; + s->data = malloc(s->data_size); + /* Copy the complete record, including the header (again) */ + copy_from_wrapped_buffer(s->data, e->mmap_data_start, e->mmap_data_size, e->mmap_page->data_tail, s->data_size); + /* data is in s->data in the Record object */ + /* Now update the read pointer in the shared metadata */ + if (1) { + /* Page is writeable - update the tail pointer so kernel can now + overwrite the record we've just collected. */ + e->mmap_page->data_tail += head.size; + __sync_synchronize(); + } + if (e->aux_area) { + //fprintf(stderr, "aux_head = %llx, aux_tail = %llx\n", e->mmap_page->aux_head, e->mmap_page->aux_tail); + } + if (head.type == PERF_RECORD_AUX) { + /* Get the AUX data now */ + typedef struct { + struct perf_event_header header; + unsigned long long aux_offset; + unsigned long long aux_size; + unsigned long long flags; + } aux_header_t; + aux_header_t const *ah = (aux_header_t const *)s->data; + if (1 || e->verbose) { + /* Show this PERF_RECORD_AUX segment in relation to the AUX ring buffer. + The offset, tail and head pointers are "infinite". */ + fprintf(stderr, "[%d] AUX flags=0x%lx offset 0x%lx size 0x%lx, current AUX tail 0x%lx head 0x%lx size 0x%lx", + e->fd, + (unsigned long)ah->flags, + (unsigned long)ah->aux_offset, (unsigned long)ah->aux_size, + (unsigned long)e->mmap_page->aux_tail, + (unsigned long)e->mmap_page->aux_head, + (unsigned long)e->mmap_page->aux_size); + if (ah->flags & PERF_AUX_FLAG_TRUNCATED) { + fprintf(stderr, " TRUNCATED"); + } + if (ah->flags & PERF_AUX_FLAG_OVERWRITE) { + fprintf(stderr, " OVERWRITE"); + } + if (ah->flags & PERF_AUX_FLAG_PARTIAL) { + fprintf(stderr, " PARTIAL"); + } + if (ah->flags & PERF_AUX_FLAG_COLLISION) { + fprintf(stderr, " COLLISION"); + } + fprintf(stderr, "\n"); + } + /* Guard in case AUX chunk was already consumed by get_aux() */ + if (ah->aux_size == 0) { + /* No data - possibly a TRUNCATED indication */ + event_update_aux_tail(e, ah->aux_offset); + } else if (ah->aux_offset == e->mmap_page->aux_tail) { + /* This AUX record describes the next segment available in the AUX buffer. */ +#ifndef NDEBUG + unsigned long available = e->mmap_page->aux_head - e->mmap_page->aux_tail; +#endif + assert(available >= ah->aux_size); + Py_DECREF(s->aux); /* it was None */ + s->aux = get_aux_data(e, ah->aux_size); + Py_INCREF(s->aux); + } else { + /* Mismatch */ + fprintf(stderr, "** AUX record mismatch\n"); + } + } + /* the Record has a back-pointer to the buffer-owning Event */ + Py_INCREF(e); + s->event = e; + return (PyObject *)s; +} + + +static PyMethodDef Event_methods[] = { + {"attr_struct", (PyCFunction)&event_attr_struct, METH_NOARGS, "string: event attributes as raw string"}, + {"fileno", (PyCFunction)&event_fileno, METH_NOARGS, "int: file handle - not for general use"}, /* this makes it a "waitable object" */ + {"id", (PyCFunction)&event_id, METH_NOARGS, "int: unique id"}, + {"close", (PyCFunction)&event_close, METH_NOARGS, "close the event"}, + {"capabilities", (PyCFunction)&event_capabilities, METH_NOARGS, "int: get capability flags"}, + {"bind", (PyCFunction)&event_bind, METH_VARARGS|METH_KEYWORDS, "int, int -> start collecting an event"}, + {"set_filter", (PyCFunction)&event_set_filter, METH_O, "str: set filter on event"}, + {"reset", (PyCFunction)&event_reset, METH_NOARGS, "int: reset the event count"}, + {"enable", (PyCFunction)&event_enable, METH_NOARGS, "int: enable the event"}, + {"disable", (PyCFunction)&event_disable, METH_NOARGS, "int: disable the event"}, + {"refresh", (PyCFunction)&event_refresh, METH_O, "int -> refresh the wakeup counter"}, + {"pause", (PyCFunction)&event_pause, METH_NOARGS, "pause a sampling event"}, + {"resume", (PyCFunction)&event_resume, METH_NOARGS, "resume a sampling event"}, + {"read", (PyCFunction)&event_read, METH_NOARGS, "Reading: read the current value of a counting event"}, + {"poll", (PyCFunction)&event_poll, METH_NOARGS, "bool: test if event record is available"}, + {"is_active", (PyCFunction)&event_is_active, METH_NOARGS, "bool: test if event was closed by kernel"}, + {"get_record", (PyCFunction)&event_get_record, METH_NOARGS, "Record: get next record from a sampling event"}, + {"get_aux", (PyCFunction)&event_get_aux, METH_NOARGS, "string: get AUX data"}, + {NULL} +}; + + +/* + * Need to explicitly include structmember.h for this? + */ +static struct PyMemberDef Event_members[] = { + {"type", T_INT, offsetof(EventObject, attr.type), 0, "perf event type"}, + {"code", T_INT, offsetof(EventObject, attr.config), 0, "perf event code"}, + {"sample_type", T_ULONGLONG, offsetof(EventObject, attr.sample_type), 0, "mask of data in sample records"}, + {"cpu", T_INT, offsetof(EventObject, cpu), 0, "cpu that this event is bound to, or -1"}, + {"verbose", T_INT, offsetof(EventObject, verbose), 0, "verbosity level"}, + {NULL} +}; + + +static PyTypeObject EventType = { + PyVarObject_HEAD_INIT(NULL, 0) + .tp_basicsize = sizeof(EventObject), + .tp_name = "perf_events.Event", + .tp_doc = "perf event", + .tp_flags = Py_TPFLAGS_DEFAULT, + .tp_methods = Event_methods, + .tp_members = Event_members, + .tp_repr = event_repr, + .tp_str = event_str, + .tp_alloc = 0, + .tp_new = event_new, + .tp_init = event_init, + .tp_dealloc = event_dealloc +}; + + +static PyMethodDef BaseReading_methods[] = { + {"is_incomplete", (PyCFunction)&reading_is_incomplete, METH_NOARGS, "bool: only partial data is available"}, + {"is_missing", (PyCFunction)&reading_is_missing, METH_NOARGS, "bool: no data is available"}, + {"update", (PyCFunction)&reading_update, METH_NOARGS, "take another reading"}, + {NULL} +}; + + +static struct PyMemberDef BaseReading_members[] = { + {"time_enabled_ns", T_LONGLONG, offsetof(BaseReadingObject, sample.time_enabled), 0, "time enabled (ns)"}, + {"time_running_ns", T_LONGLONG, offsetof(BaseReadingObject, sample.time_running), 0, "time running (ns)"}, + {"fraction_running", T_DOUBLE, offsetof(BaseReadingObject, fraction_running), 0, "float: fraction of time event was running"}, + {"event", T_OBJECT, offsetof(BaseReadingObject, event), 0, "Event object this reading was taken from"}, + {"id", T_LONGLONG, offsetof(ReadingObject, base.sample.id), 0, "event id"}, + {NULL} +}; + + +static PyMethodDef Reading_methods[] = { + {NULL} +}; + + +static struct PyMemberDef Reading_members[] = { + {"raw_value", T_LONGLONG, offsetof(ReadingObject, base.sample.value), 0, "raw count"}, + {"value", T_OBJECT, offsetof(ReadingObject, adjusted_value), 0, "adjusted count - None if event was never scheduled"}, + {NULL} +}; + + +static PyMethodDef GroupReading_methods[] = { + {NULL} +}; + + +static PySequenceMethods GroupReading_seqmethods = { + .sq_length = &groupreading_seq_length, + .sq_item = &groupreading_seq_item +}; + + +static struct PyMemberDef GroupReading_members[] = { + {NULL} +}; + + +static PyTypeObject BaseReadingType = { + PyVarObject_HEAD_INIT(NULL, 0) + .tp_basicsize = sizeof(BaseReadingObject), + .tp_name = "perf_events.BaseReading", + .tp_doc = "Base reading class", + .tp_flags = Py_TPFLAGS_DEFAULT, + .tp_methods = BaseReading_methods, + .tp_members = BaseReading_members, + //.tp_str = basereading_str, + .tp_new = basereading_new, /* should not be called */ + .tp_dealloc = basereading_dealloc +}; + + +static PyTypeObject ReadingType = { + PyVarObject_HEAD_INIT(NULL, 0) + .tp_base = &BaseReadingType, + .tp_basicsize = sizeof(ReadingObject), + .tp_name = "perf_events.Reading", + .tp_doc = "A reading taken from a counting perf event", + .tp_flags = Py_TPFLAGS_DEFAULT, + .tp_methods = Reading_methods, + .tp_members = Reading_members, + .tp_str = reading_str, + .tp_new = reading_new, + .tp_dealloc = reading_dealloc +}; + + +static PyTypeObject GroupReadingType = { + PyVarObject_HEAD_INIT(NULL, 0) + .tp_base = &BaseReadingType, + .tp_basicsize = sizeof(GroupReadingObject), + .tp_name = "perf_events.GroupReading", + .tp_doc = "A reading taken from a counting perf event group", + .tp_flags = Py_TPFLAGS_DEFAULT, + .tp_methods = GroupReading_methods, + .tp_members = GroupReading_members, + .tp_as_sequence = &GroupReading_seqmethods, + .tp_str = groupreading_str, + .tp_new = groupreading_new, + .tp_dealloc = groupreading_dealloc +}; + + +/* + * Convert a hardware timestamp to a kernel timestamp as found in perf.data. + */ +static PyObject *timeconv_to_time(PyObject *x, PyObject *v) +{ + TimeConvObject *c = (TimeConvObject *)x; + unsigned long cyc = PyLong_AsLong(v); + unsigned long long quot, rem, st; + quot = (cyc >> c->time_shift); + rem = cyc & ((1ULL << c->time_shift) - 1); + st = c->time_zero + quot*c->time_mult + ((rem*c->time_mult) >> c->time_shift); + return PyLong_FromLong(st); +} + + +static int timeconv_from_mmap(TimeConvObject *c, struct perf_event_mmap_page volatile *mp) +{ + if (!(mp->capabilities & _cap_user_time_zero)) { + /* Can't read timebase from userspace */ + return 0; + } + unsigned int seq; + do { + seq = mp->lock; + barrier(); + if (mp->capabilities & _cap_user_time_zero) { + //cyc = hardware_timestamp(); + c->time_zero = mp->time_zero; + c->time_mult = mp->time_mult; + c->time_shift = mp->time_shift; + } + barrier(); + } while (mp->lock != seq); + return 1; +} + + +/* + * Get the time conversion parameters - these are global, but if we don't + * already have an event we need to open a dummy event to get them. + */ +static int timeconv_from_dummy(TimeConvObject *c) +{ + int ok = 0; + struct perf_event_attr pa; + memset(&pa, 0, sizeof pa); + pa.size = sizeof pa; + pa.type = PERF_TYPE_SOFTWARE; + pa.config = PERF_COUNT_SW_DUMMY; + /* Open a temporary dummy event, which we will close before returning. */ + int e_fd = perf_event_open(&pa, /*pid=*/0, -1, -1, 0); + if (e_fd < 0) { + perror("dummy event"); + return 0; + } + unsigned int size = sysconf(_SC_PAGESIZE); + void *pmap = mmap(NULL, size, PROT_READ|PROT_WRITE, MAP_SHARED, e_fd, 0); + if (pmap != MAP_FAILED) { + ok = timeconv_from_mmap(c, (struct perf_event_mmap_page *)pmap); + if (!ok) { + PyErr_SetString(PyExc_ValueError, "mmap buffer doesn't contain system time base"); + } + munmap(pmap, size); + } else { + perror("mmap"); + } + close(e_fd); /* Close the temporary dummy event. */ + return ok; +} + + +static PyObject *timeconv_new(PyTypeObject *t, PyObject *args, PyObject *kwds) +{ + TimeConvObject *c = (TimeConvObject *)t->tp_alloc(t, 0); + int ok = timeconv_from_dummy(c); + if (!ok) { + t->tp_free(c); + return NULL; + } + return (PyObject *)c; +} + + +static void timeconv_dealloc(PyObject *x) +{ + x->ob_type->tp_free(x); +} + + +static PyMethodDef TimeConv_methods[] = { + {"to_time", (PyCFunction)&timeconv_to_time, METH_O, "convert hardware timestamp to user time"}, + {NULL} +}; + +static struct PyMemberDef TimeConv_members[] = { + {"time_zero", T_LONG, offsetof(TimeConvObject, time_zero), 0, "time zero"}, + {"time_mult", T_LONG, offsetof(TimeConvObject, time_mult), 0, "time multiplier"}, + {"time_shift", T_LONG, offsetof(TimeConvObject, time_shift), 0, "time shift"}, + {NULL} +}; + +static PyTypeObject TimeConvType = { + PyVarObject_HEAD_INIT(NULL, 0) + .tp_basicsize = sizeof(TimeConvObject), + .tp_name = "perf_events.TimeConv", + .tp_doc = "time conversion parameters", + .tp_flags = Py_TPFLAGS_DEFAULT, + .tp_methods = TimeConv_methods, + .tp_members = TimeConv_members, + //.tp_str = timeconv_str, + .tp_new = timeconv_new, + .tp_dealloc = timeconv_dealloc +}; + + +static int sysctl_value(char const *s, int dflt) +{ + FILE *fd = fopen(s, "r"); + if (fd) { + int n; + if (fscanf(fd, "%d", &n) == 1) { + return n; + } + fclose(fd); + } + return dflt; +} + + +/* + * Check if the overall perf_events API is available - might have been configured out. + * + * 2: no measurements + * 1: kernel events + * 0: CPU events + * -1: kernel tracepoints + */ +static PyObject *is_available(void) +{ + int ok = (sysctl_value("/proc/sys/kernel/perf_event_paranoid", 3) <= 2); + return PyBool_FromLong(ok); +} + + +static unsigned int perf_event_mlock_size(void) +{ + static unsigned int size_memo = 0; + if (!size_memo) { + size_memo = 1024 * sysctl_value("/proc/sys/kernel/perf_event_mlock_kb", 0); + } + return size_memo; +} + + +/* + * Get the TID of the current thread. + * This is provided as a convenience function for when we need a TID + * to set up a perf event on a thread. + * + * glibc doesn't have a wrapper for this so we must call via syscall(). + * + * Note that the pthread_t value we get when we start a thread, + * isn't necessarily the thread's TID. + */ +static PyObject *perf_gettid(void) +{ + pid_t tid = (pid_t)syscall(SYS_gettid); + return PyInt_FromLong(tid); +} + + +/* + * Increment the "software increment" event(s), where available. + * This may cause a hardware exception (trap to kernel) if not available from userspace. + * + * On ARM we may have multiple counters configured to count software increments. + * Each counter is incremented by writing a 1 bit to the corresponding bit of SWINC. + * However this doesn't work well when events are dynamically mapped to counters + * by the OS. So we play safe and increment all available s/w increment events. + */ +static PyObject *perf_swinc(PyObject *x) +{ + int ok = 0; +#if defined(__arm64__) || defined(__AARCH64EL__) || defined(__ARM_ARCH_ISA_A64) + /* AArch64: this will get Illegal Instruction if not enabled at EL0 */ + __asm__ __volatile__("msr pmswinc_el0,%0"::"r"((unsigned long long)0x7fffffff)); + ok = 1; +#endif + return PyBool_FromLong(ok); +} + + +/* + * Read a value directly from a hardware event counter (may fault) on the current core. + * This is not generally a safe way to read event values. + * It may fault (if userspace access is not permitted), or race with event scheduling. + */ +static PyObject *perf_rdpmc(PyObject *x, PyObject *vo) +{ + unsigned long ix = PyLong_AsLong(vo); + unsigned long long v = rdpmc(ix); + return PyLong_FromLong(v); +} + + +/* + * Write a value to hardware trace, where supported. + */ +static PyObject *perf_swtrace(PyObject *x, PyObject *vo) +{ + int ok = 0; + unsigned long v = PyLong_AsLong(vo); +#if defined(__x86_64__) + /* This may SIGILL on older cores. We could do a feature check beforehand (TBD). */ + __asm__ __volatile__("ptwrite %0"::"r"(v)); + ok = 1; +#else + (void)v; /* trace is a no-op */ +#endif + return PyBool_FromLong(ok); +} + + +static PyObject *addr_no_randomize(PyObject *x) +{ + int ok = 0; + int prev = personality(0xffffffff); + if (prev == -1) { + perror("personality(-1)"); + } else { + prev = personality(prev | ADDR_NO_RANDOMIZE); + if (prev == -1) { + perror("personality update"); + } else { + ok = 1; + } + } + if (!ok) { + PyErr_SetFromErrno(PyExc_OSError); + return NULL; + } + Py_RETURN_NONE; +} + + +/* + * Return the platform-specific hardware timestamp. This can be converted to + * a kernel timestamp using the time conversion factors in the mmap buffer. + * It may appear directly in AUX buffers for various kinds of hardware trace. + */ +static PyObject *perf_hardware_timestamp(PyObject *x) +{ + return PyLong_FromUnsignedLongLong(hardware_timestamp()); +} + + +/* + * Return the platform-specific hardware timestamp frequency, + * if directly available. If not available this way, it might be + * available in the mmap header. + */ +static PyObject *perf_hardware_timestamp_frequency(PyObject *x) +{ + unsigned long long freq = hardware_timestamp_frequency(); + if (freq > 0) { + return PyLong_FromUnsignedLongLong(freq); + } else { + Py_RETURN_NONE; + } +} + + +/* + * Return an integer timestamp with the same timebase as the timestamp in + * perf records (PERF_SAMPLE_TIME). This is typically a count of nanoseconds + * since boot, as returned by sched_clock(). + */ +static PyObject *perf_kernel_timestamp(PyObject *x) +{ + unsigned long long t; + struct timespec ts; + clock_gettime(CLOCK_MONOTONIC, &ts); + t = (unsigned long long)ts.tv_sec * 1000000000 + ts.tv_nsec; + return PyLong_FromUnsignedLongLong(t); +} + + +static PyObject *perf_fileno_event(PyObject *x, PyObject *ixo) +{ + int ix = PyLong_AsLong(ixo); + if (ix < 0 || (unsigned int)ix >= n_fileno_events) { + Py_RETURN_NONE; + } else if (fileno_events[ix] == NULL) { + Py_RETURN_NONE; + } else { + PyObject *e = (PyObject *)fileno_events[ix]; + Py_INCREF(e); + return e; + } +} + + +/* + * General useful global functions. + */ +static PyMethodDef funcs[] = { + {"is_available", (PyCFunction)&is_available, METH_NOARGS, PyDoc_STR("None -> bool: test if perf events is available")}, + {"gettid", (PyCFunction)&perf_gettid, METH_NOARGS, PyDoc_STR("None -> int: get current OS thread id")}, + {"swinc", (PyCFunction)&perf_swinc, METH_NOARGS, PyDoc_STR("None -> bool: increment the Software Increment register")}, + {"swtrace", (PyCFunction)&perf_swtrace, METH_O, PyDoc_STR("int -> write a value to hardware trace")}, + {"rdpmc", (PyCFunction)&perf_rdpmc, METH_O, PyDoc_STR("int -> read a value from a hardware event counter")}, + {"addr_no_randomize", (PyCFunction)&addr_no_randomize, METH_NOARGS, PyDoc_STR("disable ASLR in this and child processes")}, + {"hardware_timestamp", (PyCFunction)&perf_hardware_timestamp, METH_NOARGS, PyDoc_STR("None -> int: read hardware timestamp")}, + {"hardware_timestamp_frequency", (PyCFunction)&perf_hardware_timestamp_frequency, METH_NOARGS, PyDoc_STR("None -> int: read hardware timestamp frequency (Hz)")}, + {"kernel_timestamp", (PyCFunction)&perf_kernel_timestamp, METH_NOARGS, PyDoc_STR("None -> int: read kernel timestamp")}, + {"fileno_event", (PyCFunction)&perf_fileno_event, METH_O, PyDoc_STR("int -> get perf event for an OS file handle")}, + {NULL} +}; + + +#define CON(x) { #x, x } +static struct { + char const *name; + unsigned long value; +} constants[] = { + CON(PERF_FLAG_READ_USERSPACE), + CON(PERF_FLAG_NO_READ_USERSPACE), + CON(PERF_FLAG_WEAK_GROUP), +}; + + +#if PY_MAJOR_VERSION < 3 +#define INIT_NAME2(m) init##m +#else +#define INIT_NAME2(m) PyInit_##m +#endif +#define INIT_NAME(m) INIT_NAME2(m) + +PyMODINIT_FUNC INIT_NAME(MODULE_NAME)(void) +{ + PyObject *pmod; +#if PY_MAJOR_VERSION < 3 + pmod = Py_InitModule3(MODULE_NAME_STRING, funcs, "perf_events API"); +#else + static struct PyModuleDef moduledef = { + PyModuleDef_HEAD_INIT, + .m_name = MODULE_NAME_STRING, + .m_doc = PyDoc_STR("perf_events API"), + .m_size = -1, + .m_methods = funcs + }; + pmod = PyModule_Create(&moduledef); +#endif + PyType_Ready(&EventType); + PyObject_SetAttrString(pmod, "Event", (PyObject *)&EventType); + PyType_Ready(&RecordType); + PyObject_SetAttrString(pmod, "Record", (PyObject *)&RecordType); + PyType_Ready(&ReadingType); + PyObject_SetAttrString(pmod, "Reading", (PyObject *)&ReadingType); + PyType_Ready(&GroupReadingType); + PyObject_SetAttrString(pmod, "GroupReading", (PyObject *)&ReadingType); + PyType_Ready(&TimeConvType); + PyObject_SetAttrString(pmod, "TimeConv", (PyObject *)&TimeConvType); + { + unsigned int i; + for (i = 0; i < (sizeof constants / sizeof constants[0]); ++i) { + PyModule_AddIntConstant(pmod, constants[i].name, constants[i].value); + } + } +#if PY_MAJOR_VERSION >= 3 + return pmod; +#endif +} + +/* end of pyperf_events.c */ diff --git a/linux_app/pmu_app/pysweep/Makefile b/linux_app/pmu_app/pysweep/Makefile new file mode 100644 index 00000000..20166d60 --- /dev/null +++ b/linux_app/pmu_app/pysweep/Makefile @@ -0,0 +1,21 @@ +#PYTHON=python + +default: install +install: + $(PYTHON) setup.py install --prefix=$(CROSSBASE) + +test_denormals: + $(CC) src/denormals.c -pedantic -Wall -Werror -O2 -DCOMPILE_DENORMALS_AS_MAIN + ./a.out + $(CXX) src/denormals.c -pedantic -Wall -Werror -DCOMPILE_DENORMALS_AS_MAIN + ./a.out + rm a.out + +template: + $(CC) -O2 $(COPTS) tests/code_template.c -c -o template.o + objdump -d template.o + +.PHONY: clean +clean: + rm -rf build template.o + diff --git a/linux_app/pmu_app/pysweep/setup.py b/linux_app/pmu_app/pysweep/setup.py new file mode 100644 index 00000000..4c09bf6b --- /dev/null +++ b/linux_app/pmu_app/pysweep/setup.py @@ -0,0 +1,38 @@ +# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# SPDX-License-Identifier : Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +from distutils.core import setup, Extension + +src = [ + 'src/pysweep.c', + 'src/loadcode.c', + 'src/loadinst.c', + 'src/denormals.c', + 'src/loaddata.c', + 'src/loadgen.c', + 'src/prepcode.c', + 'src/genelf.c', + 'src/sleep.c', + 'src/branch_prediction.c', +] + +setup( + name='PySweep', + author='Al Grant', + author_email='al.grant@arm.com', + ext_modules=[Extension('pysweep', src, extra_compile_args=['-Wall'])], + license='Apache 2.0', + description='Dynamically generate and run stressing workloads' +) diff --git a/linux_app/pmu_app/pysweep/src/arch.h b/linux_app/pmu_app/pysweep/src/arch.h new file mode 100644 index 00000000..225fc98b --- /dev/null +++ b/linux_app/pmu_app/pysweep/src/arch.h @@ -0,0 +1,42 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +/* + * Detect if the architecture being compiled for is any ARM-based architecture + * and define a macro to indicate ISA if so. + */ + +#ifndef __included_arch_h +#define __included_arch_h + +#if defined(__arm64__) || defined(__AARCH64EL__) || defined(__ARM_ARCH_ISA_A64) +#define ARCH_A64 /* meaning the instruction set */ +#define ARCH_AARCH64 /* meaning the execution mode */ +#define ARCH_ARM +#elif defined(__thumb__) +#define ARCH_T32 +#define ARCH_AARCH32 +#define ARCH_ARM +#elif defined(__ARMEL__) +#define ARCH_A32 +#define ARCH_AARCH32 +#define ARCH_ARM +#endif + +#endif /* included */ + +/* end of arch.h */ diff --git a/linux_app/pmu_app/pysweep/src/branch_prediction.c b/linux_app/pmu_app/pysweep/src/branch_prediction.c new file mode 100644 index 00000000..9c6695b0 --- /dev/null +++ b/linux_app/pmu_app/pysweep/src/branch_prediction.c @@ -0,0 +1,103 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include +#include +#include +#include + +#define MAX_LENGTH 5 + +void resetOnly(int *len, char *addr) +{ + if (len == NULL|| addr == NULL) + return; + + memset(addr, 0, *len); + *len = 0; + + return; +} + +void printAndReset(int *len, char *addr) +{ + int i; + + if (len == NULL|| addr == NULL) + return; + +// printf("length = %d\n", (*len)); + for (i = 0; i < (*len); i++) { +// printf("%c ", addr[i]); + } + +// printf("\n"); + + memset(addr, 0, *len); + *len = 0; + + return; +} + +int branch_load_gen(int scale) +{ + int j, i, acronymLength = 0, blockCount; + char acronym[MAX_LENGTH] = {0}; + char c; + int length = 100; // string length + char string[] = + "abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789,.-#'?!"; + + srand(time(NULL)); + + // A: loop not entered 1/LOOP_COUNT times + for(j = 0; j < scale; j++) { + //printf("Starting iteration #%d\n", j); + blockCount = 0; + c = 0; + resetOnly(&acronymLength, acronym); + // B: loop not entered 1/length times + for(i = 0; i < length; i++) { + c = string[(rand() % (int)(sizeof(string) - 1))]; + // C: condition true + // (number_of_block_letters)/(total_characters_in_string) times + if (c >= 'A' && c <= 'Z') { + blockCount++; + // D: condition true up to MAX_LENGTH times consecutively + if (acronymLength < MAX_LENGTH) { + acronym[acronymLength] = c; + } + // E: condition true up to MAX_LENGTH+1 times consecutively + if (acronymLength <= MAX_LENGTH) { + acronymLength++; + } + } + else { + // F: condition true if E was true then C was false + if (acronymLength > 1 && acronymLength <= MAX_LENGTH) { + printAndReset(&acronymLength, acronym); + } + // G: condition true if E was false then C was false + else if (acronymLength != 0) { + resetOnly(&acronymLength, acronym); + } + } + } + } + + return 0; +} diff --git a/linux_app/pmu_app/pysweep/src/branch_prediction.h b/linux_app/pmu_app/pysweep/src/branch_prediction.h new file mode 100644 index 00000000..ff4132ed --- /dev/null +++ b/linux_app/pmu_app/pysweep/src/branch_prediction.h @@ -0,0 +1,22 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ +#ifndef __included_br_pred_h +#define __included_br_pred_h + +int branch_load_gen(int scale); + +#endif diff --git a/linux_app/pmu_app/pysweep/src/denormals.c b/linux_app/pmu_app/pysweep/src/denormals.c new file mode 100644 index 00000000..fba07c9b --- /dev/null +++ b/linux_app/pmu_app/pysweep/src/denormals.c @@ -0,0 +1,194 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ +/* + * Enable/disable support for denormal FP operations. + */ + +#include "denormals.h" + +#include "arch.h" + +#include +#include +#if defined(__x86_64__) +#include +#endif + + +#if defined(__x86_64__) + +#define FPCR_FZ 0x8040 +#define get_fpcr _mm_getcsr +#define set_fpcr _mm_setcsr + +#elif defined(ARCH_A64) + +#define FPCR_FZ 0x01000000 + +static uint32_t get_fpcr(void) +{ + uint32_t r; + __asm__ __volatile__("mrs %0,fpcr":"=r"(r)::); + return r; +} + +static void set_fpcr(uint32_t x) +{ + __asm__ __volatile__("msr fpcr,%0"::"r"(x):); +} + +#else +/* On other architectures, we don't know how to get the FPCR */ +#endif + + +/* + * Interrogate the floating-point control word to see if denormals are enabled. + */ +static int __attribute__((unused)) get_denormals_enabled_hw(void) +{ +#ifdef FPCR_FZ + return (get_fpcr() & FPCR_FZ) == 0; +#else + fprintf(stderr, "** Can't get denormal status from hardware on this architecture\n"); + assert(0); + return 0; +#endif +} + + +/* + * Discover if denormals are enabled, empirically + */ +static int denormals_are_enabled_empirical(void) +{ + double volatile x = DOUBLE_DENORMAL; + x += DOUBLE_DENORMAL; + return (x != 0.0); +} + + +/* + * Discover if denormals are enabled, empirically and (if possible) by interrogating + * the floating-point control word. If these tests don't correspond, raise an error. + */ +int denormals_are_enabled(void) +{ + int enabled = denormals_are_enabled_empirical(); +#ifdef FPCR_FZ + assert(enabled == get_denormals_enabled_hw()); +#endif + return enabled; +} + + +int denormals_set_enabled(int enable) +{ + if (enable) { + /* Clear DAZ and FTZ - denormals participate in arithmetic */ +#ifdef FPCR_FZ + set_fpcr(get_fpcr() & ~FPCR_FZ); +#else + /* Can't control - succeed if denormals are already enabled */ +#endif + } else { + /* Set DAZ and FTZ - denormals will be eliminated */ +#ifdef FPCR_FZ + set_fpcr(get_fpcr() | FPCR_FZ); +#else + /* Can't control - succeed if denormals are already disabled */ +#endif + } + /* If we can't control, we succeed iff denormals are already in + the enablement state we wanted. */ + return enable == denormals_are_enabled(); +} + + +/* + * Get the raw representation of floating-point numbers. + * Simplest is + * *(unsigned int *)&x; + * but that will be faulted (at -O2) by -Werror=strict-aliasing + */ +static unsigned int float_as_int(float x) +{ + union { + float f; + unsigned int i; + } u; + u.f = x; + return u.i; +} + + +static unsigned long long double_as_int(double x) +{ + union { + double f; + unsigned long long i; + } u; + u.f = x; + return u.i; +} + + +void test_denormals(void) +{ + float volatile xf; + double volatile xd; + int was_enabled = denormals_are_enabled(); + printf("Denormals test: "); +#ifdef __cplusplus + printf("C++"); +#else + printf("C"); +#endif + printf("\n"); + printf("No-denormals:\n"); + denormals_set_enabled(0); + xd = DOUBLE_DENORMAL; + printf(" %016llx (%.20g)\n", double_as_int(xd), xd); + xf = FLOAT_DENORMAL; + /* The float-to-double conversion will be flushed-to-zero on input */ + printf(" %08x (%.10g) - will print as zero\n", float_as_int(xf), xf); + assert(xd == 0.0); /* It will compare equal to zero, even though it's not */ + xd += DOUBLE_DENORMAL; + printf(" %016llx CSR=0x%04x\n", double_as_int(xd), (unsigned int)get_fpcr()); + assert(xd == 0.0); + printf("Denormals:\n"); + denormals_set_enabled(1); + xd = DOUBLE_DENORMAL; + printf(" %016llx (%g)\n", double_as_int(xd), xd); + assert(xd != 0.0); + xf = FLOAT_DENORMAL; + printf(" %08x (%g)\n", float_as_int(xf), xf); + xd += DOUBLE_DENORMAL; + printf(" %016llx CSR=0x%04x\n", double_as_int(xd), (unsigned int)get_fpcr()); + assert(xd != 0.0); + /* Restore original state */ + denormals_set_enabled(was_enabled); +} + + +#ifdef COMPILE_DENORMALS_AS_MAIN +int main(void) +{ + test_denormals(); + return 0; +} +#endif diff --git a/linux_app/pmu_app/pysweep/src/denormals.h b/linux_app/pmu_app/pysweep/src/denormals.h new file mode 100644 index 00000000..bf63cfdb --- /dev/null +++ b/linux_app/pmu_app/pysweep/src/denormals.h @@ -0,0 +1,45 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ +#ifndef __included_denormals_h +#define __included_denormals_h + +#include + +/* Sample denormal values */ +static double DOUBLE_DENORMAL = 7.9e-323; /* 0x1p-1070 */ +static float FLOAT_DENORMAL = 2.2e-44f; /* 0x1p-145f */ + +/* + * Check if denormals are enabled, without affecting + * current state. + */ +extern int denormals_are_enabled(void); + +/* + * Attempt to set denormals-enabled state. Return the + * resulting state - which can be testing to determine + * success or failure. + */ +extern int denormals_set_enabled(int enable); + +/* + * Run some self-tests. + */ +extern void test_denormals(void); + +#endif /* included */ + diff --git a/linux_app/pmu_app/pysweep/src/genelf.c b/linux_app/pmu_app/pysweep/src/genelf.c new file mode 100644 index 00000000..b5b2ae85 --- /dev/null +++ b/linux_app/pmu_app/pysweep/src/genelf.c @@ -0,0 +1,677 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ +/* + * Generate a minimal ELF image to describe code. + */ + +#include "genelf.h" + +#include "arch.h" + +#include +#include +#include +#include +#include + + +#define SEGMENT_TYPE_CODE 0 +#define SEGMENT_TYPE_DATA 1 +#define BUFFER_SIZE 20 /* based on elf_add_string call */ + +struct string { + struct string *next; + unsigned int offset; /* offset in section-header string section */ + char name[1]; +}; + +struct segment { + struct segment *next; + struct elf *elf; + void const *base; /* Segment data in client's memory */ + unsigned long size; + unsigned int type; + unsigned long file_offset; + unsigned int section_type; + unsigned int link; + unsigned int align; + unsigned int entsize; + struct string *name; + unsigned int section_index; +}; + +struct symbol { + struct symbol *next; + struct string *name; + void const *address; + unsigned long size; + unsigned int type; + struct segment *segment; +}; + +struct elf { + struct segment *segments; + unsigned int n_segments; + struct symbol *symbols; + struct symbol *last_symbol; + unsigned int n_symbols; + void const *entry; /* Entry point in client's memory */ + unsigned char *image; + size_t image_size; + int is_64:1; + int do_segments:1; + int do_sections:1; + unsigned int e_ehsize; + unsigned int e_phentsize; + unsigned int e_shentsize; + struct segment string_table; /* special segment: string table section */ + struct string *strings; + struct string *last_string; + struct segment symbol_table; /* special segment: symbol table section */ + unsigned int offset_to_segment_table; + unsigned int offset_to_section_table; + unsigned int offset_to_string_data; + unsigned int offset_to_symbol_data; +}; + + +static struct string *elf_add_string(elf_t e, char const *str); + +#define STRING_TABLE_INDEX 1 + +static void elf_show(elf_t e); + +elf_t elf_create(void) +{ + /* Freed in elf_destroy */ + elf_t e = (struct elf *)malloc(sizeof(struct elf)); + if (e) { + memset(e, 0, sizeof(struct elf)); + e->is_64 = (sizeof(void *) == 8); + e->e_ehsize = (e->is_64 ? 0x40 : 0x34); + e->e_phentsize = (e->is_64 ? 0x38 : 0x20); + e->e_shentsize = (e->is_64 ? 0x40 : 0x28); + /* Set up string table. In a normal ELF file there would be separate + string tables, .shstrtab for the section headers and .strtab for + symbol strings. But we combine the two. */ + e->string_table.elf = e; + e->string_table.section_type = 3; /* SHT_STRTAB */ + e->string_table.size = 1; /* for the leading NUL */ + e->string_table.align = 1; + e->string_table.name = elf_add_string(e, ".strtab"); + /* String section starts with a zero byte - so that the index of + all the strings are non-zero */ + /* Set up symbol table. We don't create the name yet - if we have + no symbols and don't create a symbol table section, we avoid + adding the symbol table section name to the string table. */ + e->symbol_table.elf = e; + e->symbol_table.section_type = 2; /* SHT_SYMTAB */ + e->symbol_table.link = STRING_TABLE_INDEX; + e->symbol_table.align = sizeof(uintptr_t); + e->symbol_table.entsize = (e->is_64 ? 0x18 : 0x10); + } + return e; +} + + +static int segment_contains(struct segment const *s, void const *addr, unsigned long size) +{ + return ((unsigned char const *)s->base <= (unsigned char const *)addr && + (unsigned char const *)addr + size <= (unsigned char const *)s->base + s->size); +} + + +static struct segment *elf_find_segment(elf_t e, void const *addr, unsigned long size) +{ + struct segment *s; + for (s = e->segments; s != NULL; s = s->next) { + if (segment_contains(s, addr, size)) { + return s; + } + } + return NULL; +} + + +static struct segment *elf_add_segment(elf_t e, void const *base, unsigned long size, unsigned int type) +{ + struct segment *s; + assert(e != NULL); + assert(base != NULL); + assert(size > 0); + /* We should only build an image when we've added all the code segments. */ + assert(!e->image); + + s = (struct segment *)malloc(sizeof(struct segment)); + memset(s, 0, sizeof(struct segment)); + s->elf = e; + s->type = type; + s->base = base; + s->size = size; + s->section_type = 1; /* SHT_PROGBITS */ + s->name = elf_add_string(e, (type == SEGMENT_TYPE_CODE ? ".text" : ".data")); + /* add this section to the list */ + s->next = e->segments; + e->segments = s; + ++e->n_segments; + return s; +} + + +struct segment *elf_add_code(elf_t e, void const *base, unsigned long size) +{ + return elf_add_segment(e, base, size, SEGMENT_TYPE_CODE); +} + + +/* TBD: eliminate duplicates */ +static struct string *elf_add_string(elf_t e, char const *str) +{ + struct string *s; + assert(e != NULL); + assert(str != NULL); + size_t len = strnlen(str, BUFFER_SIZE); + assert(len > 0); + s = (struct string *)malloc(sizeof(struct string) + len); + assert(s); + strncpy(s->name, str, len + 1); + /* extend the string section */ + s->offset = e->string_table.size; + e->string_table.size += len + 1; + /* add this string to the end of the list */ + s->next = NULL; + if (e->last_string == NULL) { + e->strings = s; + } else { + e->last_string->next = s; + } + e->last_string = s; + return s; +} + + +struct symbol *elf_add_symbol(elf_t e, char const *str, void const *address, unsigned long size) +{ + struct symbol *s; + assert(e != NULL); + assert(str != NULL); + s = (struct symbol *)malloc(sizeof(struct symbol)); + assert(s); + memset(s, 0, sizeof(struct symbol)); + if (!e->symbol_table.name) { + e->symbol_table.name = elf_add_string(e, ".symtab"); + } + s->name = elf_add_string(e, str); + s->address = address; + s->size = size; + s->segment = elf_find_segment(e, address, size); + if (s->segment == NULL) { + fprintf(stderr, "Tried to create symbol \"%s\" @%p %lu outside segment\n", + str, address, size); + elf_show(e); + } + assert(s->segment != NULL); + e->symbol_table.size += e->symbol_table.entsize; + e->n_symbols += 1; + if (e->last_symbol == NULL) { + e->symbols = s; + } else { + e->last_symbol->next = s; + } + e->last_symbol = s; + return s; +} + + +struct segment *elf_add_data(elf_t e, void const *base, unsigned long size) +{ + return elf_add_segment(e, base, size, SEGMENT_TYPE_DATA); +} + + +/* + * Set entry point. We'd expect this to be within an executable (code) segment. + */ +void elf_set_entry(elf_t e, void const *entry) +{ + assert(e != NULL); + e->entry = entry; +} + + +static unsigned int elf_segment_table_size(elf_t e) +{ + if (e->do_segments) { + return e->e_phentsize * e->n_segments; + } else { + return 0; + } +} + +static unsigned int elf_n_sections(elf_t e) +{ + if (e->do_sections) { + /* First add 1 for the NULL section table entry (SHN_UNDEF is 0) */ + unsigned int n = 1 + e->n_segments; + if (e->string_table.size > 1) { + n += 1; + } + if (e->symbol_table.size > 0) { + n += 1; + } + return n; + } else { + return 0; + } +} + +static unsigned int elf_section_table_size(elf_t e) +{ + if (e->do_sections) { + return e->e_shentsize * elf_n_sections(e); + } else { + return 0; + } +} + +#define STRING_ALIGNMENT 8 + +static unsigned int elf_string_section_size(elf_t e) +{ + if (e->do_sections) { + unsigned int size = (e->string_table.size + (STRING_ALIGNMENT-1)) & ~(STRING_ALIGNMENT-1); + assert((size & (STRING_ALIGNMENT-1)) == 0); + assert(size >= e->string_table.size); + return size; + } else { + return 0; + } +} + +static unsigned int elf_symbol_section_size(elf_t e) +{ + return e->do_sections ? e->symbol_table.size : 0; +} + + +/* + * Find the total size of ELF headers and other metadata (e.g. string section) + */ +static unsigned int elf_total_headers(elf_t e) +{ + unsigned int n; + n = e->e_ehsize + elf_segment_table_size(e) + elf_section_table_size(e); + n += elf_string_section_size(e); + n += elf_symbol_section_size(e); + return n; +} + + +/* + * Generate ELF header in memory, and also update the offsets + */ +static unsigned int elf_gen_header(elf_t e, unsigned char *h) +{ + unsigned int const len = e->e_ehsize; + unsigned int offset; + + assert(e->do_segments || e->do_sections); + memset(h, 0, len); + e->offset_to_segment_table = len; + /* prepare for writing sections, by updating the section counter */ + offset = len; + offset += elf_segment_table_size(e); + if (elf_n_sections(e) > 0) { + e->offset_to_section_table = offset; + offset += elf_section_table_size(e); + } else { + e->offset_to_section_table = 0; + } + if (e->strings != NULL) { + e->offset_to_string_data = offset; + offset += elf_string_section_size(e); + } else { + e->offset_to_string_data = 0; + } + if (e->symbols != NULL) { + e->offset_to_symbol_data = offset; + offset += e->symbol_table.size; + } else { + e->offset_to_symbol_data = 0; + } + h[0] = 0x7f; + h[1] = 0x45; + h[2] = 0x4c; + h[3] = 0x46; + h[4] = e->is_64 ? 2 : 1; + h[5] = 1; /* little endian */ + h[6] = 1; + h[7] = 0; /* System V */ + *(uint16_t *)(h + 0x10) = 2; /* 1: relocatable, 2: executable, 4: core */ +#if defined(ARCH_AARCH32) +#define ELF_MACHINE_TYPE 0x28 +#elif defined(ARCH_AARCH64) +#define ELF_MACHINE_TYPE 0xB7 +#else +/* TBD: default to x86 */ +#define ELF_MACHINE_TYPE (e->is_64 ? 0x3E : 0x03) +#endif + *(uint16_t *)(h + 0x12) = ELF_MACHINE_TYPE; + *(uint32_t *)(h + 0x14) = 1; + *(uintptr_t *)(h + 0x18) = (uintptr_t)e->entry; + *(uintptr_t *)(h + (e->is_64 ? 0x20 : 0x1C)) = e->offset_to_segment_table; + *(uintptr_t *)(h + (e->is_64 ? 0x28 : 0x20)) = e->offset_to_section_table; /* or zero */ + *(uint16_t *)(h + (e->is_64 ? 0x34 : 0x28)) = e->e_ehsize; + *(uint16_t *)(h + (e->is_64 ? 0x36 : 0x2a)) = e->e_phentsize; + *(uint16_t *)(h + (e->is_64 ? 0x38 : 0x2c)) = e->n_segments; + *(uint16_t *)(h + (e->is_64 ? 0x3a : 0x2e)) = e->e_shentsize; /* maybe zero if no sections? */ + *(uint16_t *)(h + (e->is_64 ? 0x3c : 0x30)) = elf_n_sections(e); + *(uint16_t *)(h + (e->is_64 ? 0x3e : 0x32)) = STRING_TABLE_INDEX; + return e->e_ehsize; +} + + +static unsigned int elf_gen_pheader(struct segment *s, unsigned char *h, unsigned int file_offset) +{ + elf_t const e = s->elf; + assert(e != NULL); + assert(e->e_phentsize > 0); + assert(s->size > 0); + memset(h, 0, e->e_phentsize); + *(uint32_t *)(h + 0x00) = 1; /* PT_LOAD */ + *(uint32_t *)(h + (e->is_64 ? 0x04 : 0x18)) = (s->type == SEGMENT_TYPE_CODE ? 0x05 : 0x04); /* (PF_X+)PF_R */ + *(uintptr_t *)(h + (e->is_64 ? 0x08 : 0x04)) = file_offset; + *(uintptr_t *)(h + (e->is_64 ? 0x20 : 0x10)) = s->size; + *(uintptr_t *)(h + (e->is_64 ? 0x28 : 0x14)) = s->size; + *(uintptr_t *)(h + (e->is_64 ? 0x10 : 0x08)) = (uintptr_t)s->base; + return e->e_phentsize; +} + + +static unsigned int elf_gen_sheader(struct segment *s, unsigned char *h, unsigned int file_offset) +{ + elf_t const e = s->elf; + unsigned int flags = 0; + assert(e != NULL); + assert(e->e_shentsize > 0); + assert(e->e_shentsize <= 0x100); + if (s->section_type == 1) { /* SHT_PROGBITS */ + flags |= 0x002; /* SHF_ALLOC */ + if (s->type == SEGMENT_TYPE_CODE) { + flags |= 0x004; /* SHF_EXECINSTR */ + } + } else if (s->section_type == 3) { + //flags |= 0x020; /* SHF_STRINGS */ + } + /* now clear the section table entry and fill in the fields */ + memset(h, 0, e->e_shentsize); + if (s->name != NULL) { + /* Index in the section header string table of the section's name. */ + *(uint32_t *)(h + 0x00) = s->name->offset; + } + *(uint32_t *)(h + 0x04) = s->section_type; + *(uintptr_t *)(h + 0x08) = flags; + *(uintptr_t *)(h + (e->is_64 ? 0x10 : 0x0c)) = (uintptr_t)s->base; + *(uintptr_t *)(h + (e->is_64 ? 0x18 : 0x10)) = file_offset; + *(uintptr_t *)(h + (e->is_64 ? 0x20 : 0x14)) = (uintptr_t)s->size; + *(uint32_t *)(h + (e->is_64 ? 0x28 : 0x18)) = s->link; + *(uintptr_t *)(h + (e->is_64 ? 0x30 : 0x20)) = (uintptr_t)s->align; + *(uintptr_t *)(h + (e->is_64 ? 0x38 : 0x24)) = (uintptr_t)s->entsize; + return e->e_shentsize; +} + + +static void elf_show(elf_t e) +{ + fprintf(stderr, "ELF:\n"); + fprintf(stderr, " Total header size: %u\n", elf_total_headers(e)); + { + struct segment const *s; + fprintf(stderr, " Segments (%u):\n", e->n_segments); + for (s = e->segments; s != NULL; s = s->next) { + fprintf(stderr, " %016llx %016llx type=%u", + (unsigned long long)s->base, (unsigned long long)s->size, s->type); + if (s->name) { + fprintf(stderr, " name=\"%s\"@%u", s->name->name, s->name->offset); + } + fprintf(stderr, "\n"); + } + } + { + struct string const *s; + fprintf(stderr, " Strings (total %u bytes):\n", (unsigned int)e->string_table.size); + for (s = e->strings; s != NULL; s = s->next) { + fprintf(stderr, " \"%s\"@%u\n", s->name, s->offset); + } + } + { + struct symbol const *s; + fprintf(stderr, " Symbols (%u)\n", e->n_symbols); + for (s = e->symbols; s != NULL; s = s->next) { + fprintf(stderr, " %s @ %p size %lu", + (s->name ? s->name->name : ""), s->address, s->size); + if (s->segment) { + fprintf(stderr, " in #%p", s->segment); + } + fprintf(stderr, "\n"); + } + } +} + + +/* + * Generate a contiguous ELF image in memory. + * The ELF image includes the ELF header and tables, but not the code/data. + * The tables point to the actual code and data in their current locations. + * So the total image is not contiguous, rather we're generating a + * contiguous descriptor for memory areas. + * + * We dynamically allocate a buffer, and the caller must free it. + */ +static void *elf_gen_image(elf_t e, int file_offsets) +{ + void *image; + unsigned char *image_base; + struct segment *s; + size_t image_size; + unsigned int file_offset_for_data; + unsigned char *p; + assert(e != NULL); + assert(e->n_segments > 0); + + e->do_segments = 1; + e->do_sections = 1; + if (0) { + elf_show(e); + } + image_size = elf_total_headers(e); + image = malloc(image_size); + if (!image) { + return NULL; + } + image_base = (unsigned char *)image; + p = image_base; + p += elf_gen_header(e, image); + file_offset_for_data = elf_total_headers(e); + for (s = e->segments; s != NULL; s = s->next) { + s->file_offset = (file_offsets ? file_offset_for_data : 0); + file_offset_for_data += s->size; + } + if (e->do_segments) { + for (s = e->segments; s != NULL; s = s->next) { + unsigned int len = elf_gen_pheader(s, p, s->file_offset); + p += len; + } + } + if (e->do_sections) { + struct string *str; + struct symbol *sym; + unsigned int section_index = 0; + /* Section table */ + assert((p - image_base) == e->offset_to_section_table); + /* Start with section table entries for special (non-segment) sections */ + /* Null entry */ + memset(p, 0, e->e_shentsize); + p += e->e_shentsize; + ++section_index; + /* Entry for the string section. We always expect to generate this, + if only for the section names. */ + if (e->string_table.size > 1) { + //e->string_table.base = image_base + e->offset_to_string_data; + unsigned int len = elf_gen_sheader(&e->string_table, p, e->offset_to_string_data); + p += len; + ++section_index; + } + if (e->symbol_table.size > 0) { + unsigned int len = elf_gen_sheader(&e->symbol_table, p, e->offset_to_symbol_data); + p += len; + ++section_index; + } + /* Iterate the segments again, but this time as sections */ + for (s = e->segments; s != NULL; s = s->next) { + s->section_index = section_index; + unsigned int len = elf_gen_sheader(s, p, s->file_offset); + p += len; + ++section_index; + } + /* We've completed the section table. */ + assert(section_index == elf_n_sections(e)); + /* Now output the special (metadata) section contents. */ + /* string section */ + assert((p - image_base) == e->offset_to_string_data); + unsigned int sp = 0; + /* start with a NUL */ + *p++ = '\0'; + sp += 1; + for (str = e->strings; str != NULL; str = str->next) { + unsigned int templen = strnlen(str->name, BUFFER_SIZE); + strncpy((char *)p, str->name, templen + 1); + unsigned int len = templen + 1; + p += len; + sp += len; + } + while ((sp & (STRING_ALIGNMENT-1)) != 0) { + *p++ = '\0'; + sp += 1; + } + /* symbol section */ + for (sym = e->symbols; sym != NULL; sym = sym->next) { + unsigned char info = 0; /* type in low nybble, binding in high nybble */ + memset(p, 0, e->symbol_table.entsize); + *(uint32_t *)(p + 0) = sym->name ? sym->name->offset : 0; + *(uintptr_t *)(p + (e->is_64 ? 0x08 : 0x04)) = (uintptr_t)sym->address; + *(uintptr_t *)(p + (e->is_64 ? 0x10 : 0x08)) = sym->size; + *(unsigned char *)(p + (e->is_64 ? 0x04 : 0x0c)) = info; + if (sym->segment != NULL) { + *(uint16_t *)(p + (e->is_64 ? 0x06 : 0x0e)) = sym->segment->section_index; + } + p += e->symbol_table.entsize; + } + } + /* check we hit the predicted end of buffer */ + if ((size_t)(p - (unsigned char *)image) != image_size) { + fprintf(stderr, "Image:\n"); + fprintf(stderr, " Start: %p\n", image); + fprintf(stderr, " Segment table: %lx\n", (unsigned long)e->offset_to_segment_table); + fprintf(stderr, " Size: %lx\n", (unsigned long)elf_segment_table_size(e)); + fprintf(stderr, " Section table: %lx\n", (unsigned long)e->offset_to_section_table); + fprintf(stderr, " Size: %lx\n", (unsigned long)elf_section_table_size(e)); + fprintf(stderr, " Strings: %lx\n", (unsigned long)e->offset_to_string_data); + fprintf(stderr, " Size: %lx\n", (unsigned long)elf_string_section_size(e)); + fprintf(stderr, " Symbols: %lx\n", (unsigned long)e->offset_to_symbol_data); + fprintf(stderr, " Size: %lx\n", (unsigned long)e->symbol_table.size); + fprintf(stderr, " Current: %lx\n", (unsigned long)(p - image_base)); + fprintf(stderr, " Predicted: %lx\n", (unsigned long)image_size); + } + assert((p - (unsigned char *)image) == image_size); + e->image_size = image_size; + return image; +} + + +/* +Generate the ELF image in memory. Idempotent. +*/ +void const *elf_image(elf_t e) +{ + assert(e != NULL); + if (!e->image) { + e->image = elf_gen_image(e, 0); + } + return e->image; +} + + +unsigned int elf_image_size(elf_t e) +{ + (void)elf_image(e); + return e->image_size; +} + + + +int elf_dump(elf_t e, char const *fn) +{ + void *image; + struct segment *s; + FILE *fd; + + assert(e != NULL); + + fd = fopen(fn, "wb"); + if (!fd) { + return -1; + } + /* generate and output the contiguous part of the ELF file, same as + we generate in-memory */ + image = elf_gen_image(e, /*file_offsets=*/1); + fwrite(image, e->image_size, 1, fd); + /* last of all, output the data contents from memory to the file */ + for (s = e->segments; s != NULL; s = s->next) { + assert(s->size > 0); + fwrite(s->base, s->size, 1, fd); + } + fclose(fd); + return 0; +} + + +void elf_destroy(elf_t e) +{ + if (e) { + while (e->segments != NULL) { + struct segment *s = e->segments; + e->segments = s->next; + free(s); + } + while (e->strings != NULL) { + struct string *s = e->strings; + e->strings = s->next; + free(s); + } + while (e->symbols != NULL) { + struct symbol *s = e->symbols; + e->symbols = s->next; + free(s); + } + if (e->image) { + free(e->image); + } + free(e); + } +} + diff --git a/linux_app/pmu_app/pysweep/src/genelf.h b/linux_app/pmu_app/pysweep/src/genelf.h new file mode 100644 index 00000000..9c4ad4ab --- /dev/null +++ b/linux_app/pmu_app/pysweep/src/genelf.h @@ -0,0 +1,71 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ +/* + * Generate an ELF image describing code regions. + */ + +#ifndef __included_genelf_h +#define __included_genelf_h + +typedef struct elf *elf_t; +typedef struct segment *elf_segment_t; +typedef struct symbol *elf_symbol_t; + +elf_t elf_create(void); + +/* + * Add a code segment. + */ +elf_segment_t elf_add_code(elf_t, void const *addr, unsigned long size); + +/* + * Add a data segment. + */ +elf_segment_t elf_add_data(elf_t, void const *addr, unsigned long size); + +/* + * Add a symbol. + */ +elf_symbol_t elf_add_symbol(elf_t, char const *name, void const *addr, unsigned long size); + +/* + * Set the entry point. + */ +void elf_set_entry(elf_t, void const *entry); + +/* + * Return a location to the ELF image in memory. + */ +void const *elf_image(elf_t); + +/* + * Return the image size in bytes, exclusive of the actual code/data. + */ +unsigned int elf_image_size(elf_t); + +/* + * Write the ELF image to a file, including the described code. + */ +int elf_dump(elf_t, char const *fn); + +/* + * Destroy an ELF object, freeing its image in memory. + */ +void elf_destroy(elf_t); + +#endif /* included */ + diff --git a/linux_app/pmu_app/pysweep/src/loadcode.c b/linux_app/pmu_app/pysweep/src/loadcode.c new file mode 100644 index 00000000..b2844374 --- /dev/null +++ b/linux_app/pmu_app/pysweep/src/loadcode.c @@ -0,0 +1,623 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +/* + * Generate code for a runnable workload in memory, based on a set of workload characteristics. + * + * Much of this unit is about generating instructions for x86 and ARM. + * A future direction would be for this function to be performed via some + * existing tool such as LLVM or DynamoRIO. + */ + +#include "loadgenp.h" + +#include "loadinst.h" +#include "prepcode.h" +#include "arch.h" +#include "genelf.h" + +#include + +#include +#include +#include +#include + + +/* +Make a data buffer pointer into a function pointer. +This is trivial except in ARM32 where we have to create an interworking pointer +(LSB set to indicate Thumb). We assume - locally to this program - that the +data buffer has been created with code in the same mode as we're currently executing. +*/ +static dummy_fn_t make_fn(void const *p) +{ +#ifdef __thumb__ + return (dummy_fn_t)((unsigned char const *)p + 1); +#else + return (dummy_fn_t)p; +#endif +} + + +void fprint_mem(FILE *fd, void const *pv, size_t size) +{ + unsigned char const *p = (unsigned char const *)pv; + unsigned int i; + for (i = 0; i < size; ++i) { + if ((i % 32) == 0) { + fprintf(fd, " %p ", (p + i)); + } + fprintf(fd, " %02x", p[i]); + if (((i+1) % 32) == 0 || (i+1) == size) { + fprintf(fd, "\n"); + } + } +} + + +void fprint_code(FILE *fd, void const *pv, size_t size) +{ + fprint_mem(fd, pv, size); +} + + +static void character_print(Character const *c) +{ + static char const *const fp_prec_names[] = {"?", "half", "single", "double"}; + static char const *const fp_op_names[] = { + "mov", + "iadd", "ixor", + "fneg", "fadd", "fmul", "fdiv", "fsqrt", + "fma", "fma(acc)", "dot2", "dot3", "dot4", + }; + printf(" page size: %lu\n", (unsigned long)sysconf(_SC_PAGESIZE)); + printf(" inst working set: %lu\n", (unsigned long)c->inst_working_set); + printf(" data working set: %lu\n", (unsigned long)c->data_working_set); + if (c->data_pointer_offset != 0) { + printf(" data pointer offset: %d\n", c->data_pointer_offset); + } + if (c->data_dispersion > 1) { + printf(" data dispersion: %d\n", c->data_dispersion); + } + if (c->data_alignment != 0) { + printf(" data alignment: %d\n", c->data_alignment); + } + printf(" flags: %#x\n", (unsigned int)c->workload_flags); + printf(" FP intensity: %lu\n", (unsigned long)c->fp_intensity); + if (c->fp_intensity > 0) { + printf(" Precision: %s\n", fp_prec_names[c->fp_precision]); + printf(" Operation: %s\n", fp_op_names[c->fp_operation]); + printf(" Concurrency: %u\n", (unsigned int)c->fp_concurrency); + printf(" SIMD: %u-way\n", (unsigned int)c->fp_simd); + printf(" Flags: %#x\n", (unsigned int)c->fp_flags); + } + if (c->debug_flags != 0) { + printf(" debug flags: %#x\n", (unsigned int)c->debug_flags); + } +} + + +static flavor_t character_flavor(Character const *c) +{ + flavor_t flavor = c->fp_precision == FP_PRECISION_DOUBLE ? F64 : + c->fp_precision == FP_PRECISION_SINGLE ? F32 : + c->fp_precision == FP_PRECISION_FP16 ? F16 : 0; + return flavor; +} + + +static unsigned int load_prepcode_flags(Character const *c) +{ + unsigned int pflags = PREPCODE_ALL; + int allow_write_and_exec = !(c->debug_flags & WORKLOAD_DEBUG_NO_WX); + if (c->debug_flags & WORKLOAD_DEBUG_NO_UNIFICATION) { + pflags &= ~PREPCODE_COHERENCE; + } + if (allow_write_and_exec || + (c->debug_flags & WORKLOAD_DEBUG_NO_MPROTECT)) { + pflags &= ~PREPCODE_PROTECT; + } + return pflags; +} + + +static int gen_fp_move(CS *cs, Character const *c, freg_t Rd, freg_t Rn) +{ + int ok; + flavor_t const flavor = character_flavor(c); + if (!(c->fp_flags & FP_FLAG_LOAD_CONST)) { + if (Rd == Rn) { + ok = 1; + } else { + ok = codestream_gen_op(cs, FP_OP_MOV, flavor, Rd, Rn, NR, NR); + } + } else { + /* On some cores, internal result caches have separate slots + for the results of loads, and it can be advantageous + for loop-invariant data to be in these slots. */ + /* FSTR ,[Rscratch,#0] */ + ok = codestream_gen_fp_store(cs, flavor, Rn, 2, 0, 0); + /* FLDR ,[Rscratch,#0] */ + ok = codestream_gen_fp_load(cs, flavor, Rd, 2, 0, 0); + } + return ok; +} + + +/* +Construct some code, representing a workload with given code +characteristics, and traversing the data structure we've constructed. +*/ +void *load_construct_code(Workload *w) +{ + Character const *c = &w->c; + struct workload_mem *m = &w->code_mem; + void *code_entry; + CS *cs; + unsigned int LINE = 64; + size_t const size_rounded_to_lines = round_size(c->inst_working_set, LINE); + size_t const size = size_rounded_to_lines; + dummy_fn_t fp; + void *code_area; + + /* If allow_write_and_exec is set, we allocate code memory with + both PROT_WRITE and PROT_EXEC set. We can then build the code + and execute it immediately (Intel) or after a userspace cache + unification (ARM). */ + int allow_write_and_exec = !(c->debug_flags & WORKLOAD_DEBUG_NO_WX); + + void **dummy_data; + dummy_data = (void **)&dummy_data; /* Dummy circular chain */ + + assert(size_rounded_to_lines > 0); + assert(size_rounded_to_lines % LINE == 0); + + if (workload_verbose) { + printf("loadgen: %p: creating workload code\n", w); + character_print(c); + } + + /* Allocate a page-aligned block of memory to be used for the generated code. */ + m->size_req = size_rounded_to_lines; + if (allow_write_and_exec) { + m->is_exec = 1; + } + code_area = load_alloc_mem(m); + if (!code_area) { + return NULL; + } + if (workload_verbose) { + printf(" constructing branch code at %p, size 0x%lx\n", + code_area, (unsigned long)size); + } + assert(code_area == m->base); + assert(m->size >= size); + elf_add_code(w->elf_image, m->base, m->size); +#if defined(ARCH_A32) || defined(ARCH_T32) || defined(ARCH_A64) + /* Add a mapping symbol for the whole code area */ + { +#ifdef ARCH_A64 + char const *ms = "$x"; +#elif defined(ARCH_A32) + char const *ms = "$a"; +#else + char const *ms = "$t"; +#endif + elf_add_symbol(w->elf_image, ms, code_area, 0); + } +#endif + + /* For the roofline model, we want to be able to generate workloads + with a given "arithmetic intensity". The intensity is a number N + where the ratio of bytes to ops is 1:N. There seems to be an + implicit assumption that data is dense, so when we bring in a + cache line, we count the entire line as used for the purposes of + calculating "arithmetic intensity". */ + unsigned int const fpop_per_mem = c->fp_intensity; + int const any_data = (c->data_working_set > 0); + + cs = codestream_init(&w->expected, code_area, size, LINE); + if (c->fp_flags & FP_FLAG_ALTERNATE) { + codestream_use_alternate(cs); + } + if (workload_verbose) { + codestream_show(cs); + } + + /* Construct code until we fill up the code working set. */ + code_entry = codestream_addr(cs); + + flavor_t flavor = character_flavor(c); + unsigned int const ewidth = FLOAT_BITS(flavor) / 8; + if (c->fp_simd*ewidth == 8) { + flavor |= S64; + } else if (c->fp_simd*ewidth == 16) { + flavor |= S128; + } else if (c->fp_simd*ewidth == 32) { + flavor |= S256; + } else if (c->fp_simd*ewidth == 64) { + flavor |= S512; + } else if (c->fp_simd*ewidth == 128) { + flavor |= S1024; + } else if (c->fp_simd > 1) { + /* Invalid number of lanes */ + load_free_mem(m); + return NULL; + } + + /* Set up the register pool */ + +/* How many floating-point registers are we allowed to clobber? */ +#if defined(ARCH_T32) || defined(ARCH_A32) +#define FP_REGS_AVAIL 16 +#elif defined(ARCH_A64) +#define FP_REGS_AVAIL 32 +#elif defined(__x86_64__) +/* According to the System V ABI for x86_64, a callee can use %xmm0 to %xmm15 */ +#define FP_REGS_AVAIL 16 +#else +#error Unknown architecture +#endif + /* Current state, for generating the instruction mix */ + int op_needs_2_regs = (c->fp_operation >= FP_OP_DOT2); + unsigned int op_regs_used = (op_needs_2_regs ? 2 : 1); + unsigned int fp_regs_cycle = c->fp_concurrency * op_regs_used; + + unsigned int fp_regs_const = 1; + if (fp_regs_cycle > (FP_REGS_AVAIL - fp_regs_const)) { + fp_regs_cycle = FP_REGS_AVAIL - fp_regs_const; + } else if (fp_regs_cycle == 0) { + fp_regs_cycle = 1; + } + unsigned int const reg_first_const = (fp_regs_const > 0) ? fp_regs_cycle : NR; + assert(fp_regs_cycle > 0); + + if (workload_verbose) { + printf(" total regs available: %u\n", FP_REGS_AVAIL); + printf(" regs in recirculation cycle: %u\n", fp_regs_cycle); + printf(" constant regs: %u\n", fp_regs_const); + } + + /* First copy from FP register 0 into the other registers to ensure + none of them contain a NaN, denormal etc. Assume we've got + enough space for this. Assume the workload runner has set up + FP register 0 with a suitable value, e.g. 1.0. + On ARM we could use FCONST instruction to construct suitable + values directly here, but that's harder on x86. + If we request an invalid SIMD size, we'll fail here. + */ + if (fpop_per_mem > 0) { + unsigned int i; + int ok; + unsigned int constval_source = 2; /* i.e. D2, or S2 */ + unsigned int workval_source = 1; /* i.e. D1, or S1 */ + /* Save the const value from R2 before we clobber it. */ + if (reg_first_const != NR && reg_first_const > constval_source) { + for (i = 0; i < fp_regs_const; ++i) { + ok = gen_fp_move(cs, c, reg_first_const+i, constval_source); + if (!ok) { + break; + } + } + } + for (i = 0; i < fp_regs_cycle; ++i) { + if (i != workval_source) { + ok = codestream_gen_op(cs, FP_OP_MOV, flavor, i, workval_source, NR, NR); + if (!ok) { + break; + } + } + if (!codestream_reserve(cs, 8)) { + assert(0); + } + } + if (reg_first_const != NR && reg_first_const <= constval_source) { + gen_fp_move(cs, c, reg_first_const, constval_source); + } + /* We now have all work (recirculation) regs with the initial work + value from R1, and the FIRST_CONST reg with the value from R2. */ + if (codestream_errors(cs) > 0) { + goto generation_failed; + } + } + + /* For small instruction-working-set workloads, we create an inner + loop round the workload to reduce the effect of overhead. + Essentially we aim to execute some reasonably large number + (say 100000 or 50000) 4-byte instructions per outer call + Roughly estimate number of instructions (size/4) and then iterate + that for as many times as we need to hit the target. We don't + need to be super accurate, as the actual instruction counts will + be calculated from the outer iteration count (which is accurate + apart from a possible iteration in progress) and the instruction + counts we record when generating the code. + */ + unsigned int n_iters = (c->inst_target / (size / 4)); + if (n_iters == 0) { + n_iters = 1; + } + void *work_kernel = NULL; +#define IRBASE IR0 /* Memory chain pointer */ +#define IROFFSET IR1 /* Offset for chain pointer */ +#define IRSCRATCH IR2 +#define IRLOOP IR3 /* Top-level loop count */ + assert(n_iters >= 1); + if (n_iters > 1) { + /* Set up a fixed-count loop within the workload. */ + codestream_gen_movi32(cs, IRLOOP, n_iters); + work_kernel = codestream_addr(cs); + /* Instructions generated within the loop add an appropriately scaled + count to the overall workload instruction metrics. */ + codestream_push_multiplier(cs, n_iters); + } + elf_add_symbol(w->elf_image, "kernel", codestream_addr(cs), 0); + + unsigned int fp_reg = 0; /* Cycle through available FP regs */ + + w->n_chain_steps = 0; + + /* Fill the code buffer with instructions implementing the requested code mix. + This is a sequence of operations cycling through the available FP registers. + We might bail out mid-way through an operation. */ + unsigned int load_flags = 0; + if (c->workload_flags & WL_MEM_NONTEMPORAL) { + load_flags |= CS_LOAD_NONTEMPORAL; + } + if (c->workload_flags & WL_MEM_ACQUIRE) { + load_flags |= CS_LOAD_ACQUIRE; + } + if (c->workload_flags & WL_MEM_ATOMIC) { + load_flags |= CS_LOAD_ATOMIC; + } + if (c->workload_flags & WL_MEM_LOAD_PAIR) { + load_flags |= CS_LOAD_PAIR; + } +#ifdef ARCH_A64 + if (c->fp_flags & FP_FLAG_ALTERNATE) { + codestream_gen_direct(cs, 0x2520e020); /* pseudo SVE instruction to ask ArmIE to start trace */ + } +#endif + while (codestream_reserve(cs, 12)) { + unsigned int j; + if (any_data) { + /* Generate a load to follow the chain in the data working set. + This will count as a load instruction in our general code metrics + accumulator, but we also count it specifically as a chain step. */ + w->n_chain_steps += 1; + if (c->workload_flags & WL_MEM_PREFETCH) { + codestream_gen_load(cs, NR, IRBASE, NR, 0, CS_LOAD_PREFETCH); + } + if (c->data_pointer_offset != 0) { + /* Load from the current data-pointer (R0) indexed by the constant offset register (R1) */ + codestream_gen_load(cs, IRBASE, IRBASE, IROFFSET, 0, load_flags); + } else { + if (c->workload_flags & WL_MEM_LOAD_EXTRA) { + codestream_gen_load(cs, IRSCRATCH, IRBASE, NR, 8, load_flags); /* TBD do this better */ + } + codestream_gen_load(cs, IRBASE, IRBASE, NR, 0, load_flags); + } + if (c->workload_flags & WL_MEM_STORE) { + if (!codestream_reserve(cs, 12)) { + break; + } + unsigned int store_flags = CS_STORE_DEFAULT; + if (c->workload_flags & WL_MEM_RELEASE) { + store_flags |= CS_STORE_RELEASE; + } +#ifdef ARCH_A64 + if (c->workload_flags & WL_MEM_RELEASE) { + /* ADD ,,#8 */ + codestream_gen_iopk(cs, CS_IOP_ADD, IRSCRATCH, IRBASE, 8); + /* STLR ,[,#0] - IR1 used as an available value to store */ + codestream_gen_store(cs, IR1, IRSCRATCH, NR, 0, store_flags); + } else + /* ** Careful: next line is the 'else' clause */ +#endif + codestream_gen_store(cs, IR1, IRBASE, NR, 8, store_flags); + } + if (c->workload_flags & WL_MEM_BARRIER) { + unsigned int fence_flags = (c->workload_flags & WL_MEM_STORE) ? CS_FENCE_STORE : CS_FENCE_LOAD; + if (c->workload_flags & WL_MEM_BARRIER_SYSTEM) fence_flags |= CS_FENCE_SYSTEM; + if (c->workload_flags & WL_MEM_BARRIER_SYNC) fence_flags |= CS_FENCE_SYNC; + codestream_gen_fence(cs, fence_flags); + } + if (c->workload_flags & WL_MEM_NOP) { + codestream_gen_nop(cs); + } + } else if (fpop_per_mem == 0) { + /* No data or FP accesses - just generate NOPs to force a code working set */ + codestream_gen_nop(cs); + } + for (j = 0; (j < fpop_per_mem) && codestream_reserve(cs, 8); ++j) { + unsigned int k; + freg_t R1 = fp_reg; + freg_t R2 = (op_regs_used == 2) ? ((fp_reg + 1) % fp_regs_cycle) : NR; + if (c->workload_flags & WL_MEM_NOP) { + codestream_gen_nop(cs); + } + switch (c->fp_operation) { + case FP_OP_MOV: + case FP_OP_NEG: + codestream_gen_op(cs, c->fp_operation, flavor, R1, R1, NR, NR); + break; + case FP_OP_SQRT: + /* x := sqrt(x) converges to 1.0 very rapidly, and might then + take a fast path. So we insert an ADD into the path to + restore the value to something harder. */ + if (!(c->fp_flags & FP_FLAG_CONVERGE)) { + codestream_gen_op(cs, FP_OP_ADD, flavor, R1, R1, reg_first_const, NR); + if (!codestream_reserve(cs, 8)) { + break; + } + } + codestream_gen_op(cs, c->fp_operation, flavor, R1, R1, NR, NR); + break; + case FP_OP_ADD: + case FP_OP_MUL: + case FP_OP_DIV: + case FP_OP_IADD: + case FP_OP_IXOR: + if (c->fp_flags & FP_FLAG_CONVERGE) { + /* x := x/x converges immediately to 1.0, which may then + take a fast path. */ + codestream_gen_op(cs, c->fp_operation, flavor, R1, R1, R1, NR); + } else { + /* With a constant numerator, the result of the divide (and denominator + for the next divide) will oscillate between two values. + We also hope the numerator and denominator will be different. + Data-dependency chain is through the denominator. */ + codestream_gen_op(cs, c->fp_operation, flavor, R1, reg_first_const, R1, NR); + } + break; + case FP_OP_MULADD: + codestream_gen_op(cs, FP_OP_MUL, flavor, R1, R1, R1, NR); + if (!codestream_reserve(cs, 8)) goto end_of_loop; + codestream_gen_op(cs, FP_OP_ADD, flavor, R1, R1, R1, NR); + break; + case FP_OP_FMA: + codestream_gen_op(cs, c->fp_operation, flavor, R1, R1, R1, R1); + break; + case FP_OP_FMAA: + /* Accumulator latency (FMAA). Writes back to its accumulator operand, + but the multiplier operands are not written. */ + codestream_gen_op(cs, FP_OP_FMA, flavor, R1, reg_first_const, reg_first_const, R1); + break; + case FP_OP_DOT2: + /* 2-term dot product (DOT2) */ + codestream_gen_op(cs, FP_OP_MUL, flavor, R1, R1, R1, NR); + if (!codestream_reserve(cs, 8)) goto end_of_loop; + codestream_gen_op(cs, FP_OP_FMA, flavor, R1, R2, R2, R1); + break; + case FP_OP_DOT4: + /* 4-term dot product */ + codestream_gen_op(cs, FP_OP_MUL, flavor, R1, R1, R1, NR); + if (!codestream_reserve(cs, 8)) goto end_of_loop; + codestream_gen_op(cs, FP_OP_FMA, flavor, R1, R2, R2, R1); + if (!codestream_reserve(cs, 8)) goto end_of_loop; + codestream_gen_op(cs, FP_OP_FMA, flavor, R1, R2, R2, R1); + if (!codestream_reserve(cs, 8)) goto end_of_loop; + codestream_gen_op(cs, FP_OP_FMA, flavor, R1, R2, R2, R1); + break; + case FP_OP_DIST2: + /* 2-term distance */ + codestream_gen_op(cs, FP_OP_MUL, flavor, R1, R1, R1, NR); + if (!codestream_reserve(cs, 8)) goto end_of_loop; + codestream_gen_op(cs, FP_OP_FMA, flavor, R1, R2, R2, R1); + if (!codestream_reserve(cs, 8)) goto end_of_loop; + codestream_gen_op(cs, FP_OP_SQRT, flavor, R1, R1, NR, NR); + break; + default: + assert(0); + } + if (c->workload_flags & WL_DEPEND) { + /* The destination register (R1) is also the first input register, + so there is already a loop-carried dependency on R1. If there are + other iput registers, copy R1 to them to make them all + loop-carried dependencies. */ + for (k = 1; k < op_regs_used; ++k) { + if (!codestream_reserve(cs, 4)) { + break; + } + codestream_gen_op(cs, FP_OP_MOV, flavor, ((fp_reg + k) % fp_regs_cycle), R1, NR, NR); + } + } + w->expected.n[COUNT_UNIT] += n_iters; + /* Set up for the next iteration */ + fp_reg = (fp_reg + op_regs_used) % fp_regs_cycle; + } + } +end_of_loop:; + + if (n_iters > 1) { + codestream_gen_decs(cs, IRLOOP); + codestream_gen_branch(cs, work_kernel, CC_NE); + codestream_pop_multiplier(cs, n_iters); + } + +#ifdef ARCH_A64 + if (c->fp_flags & FP_FLAG_ALTERNATE) { + codestream_gen_direct(cs, 0x2520e040); /* pseudo SVE instruction to ask ArmIE to stop trace */ + } +#endif + + /* Add the return in the last instruction block */ + codestream_gen_ret_abi(cs); + + if (codestream_errors(cs) > 0) { +generation_failed: + if (workload_verbose) { + printf(" workload generation failed\n"); + } + codestream_free(cs); + load_free_mem(m); + return NULL; + } + + codestream_free(cs); + + if (workload_verbose) { + fprint_code(stderr, code_area, 200); + } + { + w->entry = make_fn(code_entry); + elf_set_entry(w->elf_image, w->entry); + elf_add_symbol(w->elf_image, "payload", w->entry, 0); + } + /* Prepare the code for execution. This might include: + * - changing the memory protection if not already done + * - cache unification (e.g. on ARM) + * - calling any debugger hooks for JIT + */ + { + int rc; + rc = prepare_code_elf(m->base, m->size, load_prepcode_flags(c), + elf_image(w->elf_image), elf_image_size(w->elf_image)); + if (rc) { + /* Generated code, but failed to mark it executable */ + load_free_mem(m); + return NULL; + } + } + if (c->debug_flags & WORKLOAD_DEBUG_TRIAL_RUN) { + /* test it - probably segfault if not right */ + printf("Testing generated branches at %p... 1 of 2\n", code_area); + fprint_mem(stdout, code_area, 32); + fp = make_fn(code_area); + printf(" function pointer: %p\n", fp); + fp(dummy_data, w->entry_args[1], w->scratch); + printf(" returned ok\n"); + printf("Testing generated branches... 2 of 2\n"); + fp = make_fn(code_area + LINE*2); + printf(" function pointer: %p\n", fp); + fp(dummy_data, w->entry_args[1], w->scratch); + printf(" branches ok\n"); + } + return code_area; +} + + +void load_free_code(Workload *w) +{ + (void)unprepare_code(w->code_mem.base, w->code_mem.size, load_prepcode_flags(&w->c)); + if (w->elf_image) { + elf_destroy(w->elf_image); + w->elf_image = NULL; + } + load_free_mem(&w->code_mem); +} + diff --git a/linux_app/pmu_app/pysweep/src/loaddata.c b/linux_app/pmu_app/pysweep/src/loaddata.c new file mode 100644 index 00000000..ba204274 --- /dev/null +++ b/linux_app/pmu_app/pysweep/src/loaddata.c @@ -0,0 +1,458 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +/* + * Generate a runnable workload in memory, based on a set of workload characteristics. + */ + +#include "loadgenp.h" + +#include "arch.h" + +#include + +#include +#include +#include +#include + + +/* +Test the length of a chain of data. The chain must be completely circular +i.e. we must get back to the beginning. Given bad data, this function will +crash or loop infinitely. +*/ +static unsigned int chain_length(void const *chainp, int offset) +{ + unsigned int n = 0; + void const *p = chainp; + do { + ++n; + void const * const*load_addr = (void const * const*)((unsigned char *)p + offset); + p = *((void const **)load_addr); + } while (p != chainp); + return n; +} + + +/* + * Construct a random maximal cycle, returned as an array of integers, + * caller to free. + * We use Sattolo's algorithm (a variant on Fisher-Yates). + */ +static int *random_maximal_cycle(unsigned int n) +{ + unsigned int i; + int *order = malloc(sizeof(int) * n); /* This could be problematic if w.s. very large */ + assert(order != NULL); + assert(n > 0); + for (i = 0; i < n; ++i) { + order[i] = i; + } + for (i = n-1; i >= 1; --i) { + unsigned int j = rand() % (i); + int temp; + assert(j < n); + temp = order[j]; + order[j] = order[i]; + order[i] = temp; + } + /* order now contains a random maximal cycle. */ + return order; +} + + +/* + * WorkingSet object. + * + * This object captures post-facto characteristics of a working set. + * Can be fed a trace and will update the working set properties. + * + * Currently this is very simplistic. + * + * We don't attempt to characterize how this working set would + * interact with various cache geometries. For example, + * a working set which consisted of accesses at n, n+4K, n+8K + * etc. might have a lot of conflicts due to aliasing. + * + * Nor do we characterize how many distinct + * granules of size N are touched, where interesting values of + * N would relate to various caching mechanisms such as + * - data cache line: 64-bytes or (occasionally) 128-bytes + * - TLB entry for 4K page + * - TLB entry for huge (512K) page + * Nor do we characterize the "page walk working set" or the + * amount of space that would be taken up by caching one or more + * levels of page table. + * + * Other things being equal, for a dense working set we'd expect + * - number of 4K pages to be size / 4K + * - one TLB entry per page assuming no compression + * So for an 8M working set with no huge pages we'd have + * - 2048 pages + * - 2048 last-level page table entries + * - 16K of last-level page tables + */ +typedef struct Footprint { + struct Footprint *next_in_bucket; + void const *granule_address; +#define FOOTPRINT_GRANULE_BITS (8 * sizeof(unsigned long)) + unsigned long bitmap_touch1; /* touch1 and touchm form a saturating-to-2 counter */ + unsigned long bitmap_touchm; + unsigned int n_access; +} Footprint; + +typedef struct WorkingSet { + void const *min_address; /* lowest address accessed */ + void const *max_access_address; /* max (base) address of access */ + void const *hwm; /* high water mark allowing for access size */ + unsigned int n_access; /* number of accesses */ + unsigned int n_unaligned; /* number of unaligned accesses */ + void const *most_recent_access; /* the most recent access - to detect simple streaming */ + unsigned int n_contig_access; /* number of accesses on same line or next line */ +#define FOOTPRINT_N_BUCKETS 16384 + Footprint *cache_lines_touched[FOOTPRINT_N_BUCKETS]; + unsigned int n_cache_lines_touched; +} WorkingSetCharacteristics; + +static void ws_init(WorkingSetCharacteristics *ws) +{ + memset(ws, 0, sizeof *ws); + ws->n_access = 0; + ws->n_unaligned = 0; + ws->min_address = 0; + ws->max_access_address = 0; + ws->hwm = 0; + ws->most_recent_access = 0; + ws->n_contig_access = 0; +} + +/* +Incrementally update working set characteristics, given another access. +Currently we don't distinguish reads and writes. +*/ +static void ws_update(WorkingSetCharacteristics *ws, void const *p, size_t access_size) +{ + ws->n_access++; + void const *pe = (char const *)p + access_size; + unsigned int const LINE = 64; + + assert(p != 0); + assert(access_size > 0); + assert(access_size == (access_size & -access_size)); /* check it's a power of 2 */ + if (ws->n_access == 1) { + /* This is the first access */ + ws->min_address = p; + ws->max_access_address = p; + ws->hwm = pe; + } else { + /* Check if this access is contiguous with the previous access. */ + unsigned long pline = (unsigned long)(ws->most_recent_access) & ~(unsigned long)(LINE-1); + unsigned long line = (unsigned long)p & ~(unsigned long)(LINE-1); + if (line == pline || line == pline+LINE) { + ws->n_contig_access++; + } + if ((char const *)p < (char const *)ws->min_address) { + ws->min_address = p; + } + if ((char const *)p > (char const *)ws->max_access_address) { + ws->max_access_address = p; + } + if ((char const *)pe > (char const *)ws->hwm) { + ws->hwm = pe; + } + } + if (((unsigned long)p & (access_size-1)) != 0) { + ws->n_unaligned += 1; + } + ws->most_recent_access = p; + { + void const *line_address = (void const *)((unsigned long)p & ~(unsigned long)(LINE-1)); + unsigned long line = (unsigned long)line_address / LINE; + unsigned int const bytes_per_granule = (LINE * FOOTPRINT_GRANULE_BITS); + void const *granule_address = (void const *)((unsigned long)p & ~(bytes_per_granule-1)); + unsigned long granule = (unsigned long)granule_address / bytes_per_granule; + unsigned int const bucket = granule % FOOTPRINT_N_BUCKETS; + Footprint *fp; + for (fp = ws->cache_lines_touched[bucket]; fp; fp = fp->next_in_bucket) { + if (fp->granule_address == granule_address) { + break; + } + } + if (!fp) { + fp = (Footprint *)malloc(sizeof *fp); + fp->granule_address = granule_address; + fp->n_access = 0; + fp->bitmap_touch1 = 0; + fp->bitmap_touchm = 0; + fp->next_in_bucket = ws->cache_lines_touched[bucket]; + ws->cache_lines_touched[bucket] = fp; + } + ++fp->n_access; + { + unsigned int offset = line & (FOOTPRINT_GRANULE_BITS-1); + unsigned long mask = 1ULL << offset; + if ((fp->bitmap_touch1 & mask) == 0) { + ++ws->n_cache_lines_touched; + fp->bitmap_touch1 |= mask; + } else if ((fp->bitmap_touchm & mask) == 0) { + fprintf(stderr, "repeat access to %p\n", line_address); + fp->bitmap_touchm |= mask; + } + } + } +} + + +/* + * Queries on the working set characteristics. + */ +static size_t ws_range(WorkingSetCharacteristics const *ws) +{ + return (char const *)ws->hwm - (char const *)ws->min_address; +} + +static void ws_show(WorkingSetCharacteristics const *ws) +{ + printf("Working set (%u accesses):\n", ws->n_access); + printf(" From: %p\n", ws->min_address); + printf(" To: %p\n", ws->hwm); + printf(" Range: %#lx\n", (unsigned long)ws_range(ws)); + printf(" Contig: %u\n", ws->n_contig_access); + printf(" Lines: %u\n", ws->n_cache_lines_touched); + printf(" Unalign:%u\n", ws->n_unaligned); +} + +static void ws_free(WorkingSetCharacteristics *ws) +{ + unsigned int b; + for (b = 0; b < FOOTPRINT_N_BUCKETS; ++b) { + while (ws->cache_lines_touched[b]) { + Footprint *fp = ws->cache_lines_touched[b]; + ws->cache_lines_touched[b] = fp->next_in_bucket; + free(fp); + } + } +} + + +static unsigned int cache_line_length(Character const *c) +{ + static unsigned int line_size = 0; + if (!line_size) { + long line = sysconf(_SC_LEVEL1_DCACHE_LINESIZE); + if (line < 0) { + perror("sysconf(_SC_LEVEL1_DCACHE_LINESIZE)"); + line = 64; /* Fall back to sensible guess at line size */ + } else if (line == 0) { + fprintf(stderr, "sysconf(_SC_LEVEL1_DCACHE_LINESIZE) reports line size zero: assume 64\n"); + line = 64; + } + line_size = (unsigned int)line; + } + return line_size; +} + + +static unsigned int hash_uint(unsigned int n) +{ + return n * (1024+17); +} + + +/* + * Return the placement of the data chain pointer within the cache line or line group. + * This needs to be a deterministic function if i, so if we want to randomize + * the placement we've got to use a pseudo-random function of i. + * We mustn't overspill the end of the line group, as we risk bumping into + * the next line group or unrelated data. + * Exceptionally, the first item is always at offset 0, so that the client + * knows where to start. + */ +static unsigned int line_data_placement(Character const *c, unsigned int i) +{ + unsigned int ix; + unsigned int const LINE = cache_line_length(c); + unsigned int const dispersion = (c->data_dispersion >= 1) ? c->data_dispersion : 1; + unsigned int const chunk = LINE * dispersion; + unsigned int alignment = c->data_alignment ? c->data_alignment : sizeof(void *); + unsigned int range = (chunk - sizeof(void *)) / alignment; + ix = (hash_uint(i) % range) * alignment; + assert((ix + sizeof(void *)) <= chunk); + return (i == 0) ? 0 : ix; +} + + +/* +Construct a data working set, given some characteristics. The output is a contiguous +area of memory consisting of a granules (generally of cache line size) with a pointer +at the start of each granule. The pointers form a linked chain of pointers, which when +followed, will exhibit the desired working set characteristics. + +Return NULL if we fail to allocate the data working set. + +The input characteristics are as follows: + + - the total working set span (c->data_working_set) + + - TBD: add working set density e.g. number of cache lines touched + +The first word of this working set should be the first link in a circular chain of data. + +Layout is randomized in order to avoid hardware prefetching. + +When the workload is run, it starts at the first link in the chain, and progressively +steps through the chain. To fully utilize the working set, we need to process the +whole chain - so the workload must do at least that number of loads before being +reset to the beginning of the chain. If the workload is a relatively small number of +instructions it must either be wrapped by a loop or must remember its state from +one run to the next. +*/ +void *load_construct_data(Character const *c, struct workload_mem *m) +{ + unsigned int i; + int debug = workload_verbose; + unsigned int const LINE = cache_line_length(c); + unsigned int const dispersion = (c->data_dispersion >= 1) ? c->data_dispersion : 1; + unsigned int const chunk = LINE * dispersion; + size_t const size_rounded_to_lines = round_size(c->data_working_set*dispersion, chunk); + unsigned int const n_lines = (size_rounded_to_lines / chunk); + int *order; + void *data; + void *adjusted_data; + unsigned int expected_chain_length = n_lines; + + if (debug >= 1) { + printf("Constructing data working set: size=%lu rounded=%lu lines=%u\n", + (unsigned long)c->data_working_set, + (unsigned long)size_rounded_to_lines, n_lines); + } + assert(size_rounded_to_lines >= c->data_working_set); + if (size_rounded_to_lines == 0) { + /* No data working set required - presumably testing compute only */ + assert(c->data_working_set == 0); + m->size_req = 0; + m->size = 0; + m->base = NULL; + return NULL; + } + /* + * Allocate the actual data area in which we construct the chain of pointers. + * We're possibly asking for a large amount of space here (it's the data + * working set) so we should be prepared for allocation to fail. + */ + memset(m, 0, sizeof(struct workload_mem)); + m->size_req = size_rounded_to_lines; + m->is_no_hugepage = (c->workload_flags & WL_MEM_NO_HUGEPAGE) != 0; + m->is_hugepage = (c->workload_flags & WL_MEM_HUGEPAGE) != 0; + m->is_force_hugepage = (c->workload_flags & WL_MEM_FORCE_HUGEPAGE) != 0; + data = load_alloc_mem(m); + if (!data) { + fprintf(stderr, "loadgen: couldn't allocate %llu bytes for data working set\n", + (unsigned long long)size_rounded_to_lines); + return NULL; + } + /* + * Any placement of links within lines relies on the area being at least line-aligned. + * Check here just to make sure. + */ + assert(((unsigned long)data % LINE) == 0); + adjusted_data = (void *)((unsigned char *)data - c->data_pointer_offset); + if (!(c->workload_flags & WL_MEM_STREAM)) { + /* Construct a random cycle. */ + order = random_maximal_cycle(n_lines); + if (debug >= 3) { + unsigned int i; + for (i = 0; i < n_lines; ++i) { + printf(" %d", order[i]); + } + printf("\n"); + } + /* Use the random cycle to build a chain of pointers in the data area. */ + /* Each link in the chain can, in principle, be allocated anywhere in the line, + or if we're using dispersion, in the group of lines. We can also try to + use unaligned and cross-line data placement. */ + for (i = 0; i < n_lines; ++i) { + assert(order[i] < n_lines); + *(void **)((unsigned char *)data + i*chunk + line_data_placement(c, i)) = + ((unsigned char *)adjusted_data + order[i]*chunk + line_data_placement(c, order[i])); + } + free(order); + } else { + /* Construct a sequential cycle. */ + for (i = 0; i < n_lines; ++i) { + *(void **)((unsigned char *)data + i*chunk) = ((unsigned char *)adjusted_data + ((i+1)%n_lines)*chunk); + } + } + if (debug >= 2) { + printf("Data working set:\n"); + unsigned int lines_to_show = n_lines; + if (lines_to_show > 10) { + lines_to_show = 10; + } + for (i = 0; i < lines_to_show; ++i) { + unsigned int j; + void **p; + unsigned int ix = (c->workload_flags & WL_MEM_STREAM) ? 0 : line_data_placement(c, i); + p = (void **)((unsigned char *)adjusted_data + i*chunk + ix); + printf(" from %2u: ", i); + for (j = 0; j < 10; ++j) { + printf("*(%p+%d) -> ", p, c->data_pointer_offset); + p = (void **)*(void **)((unsigned char *)p + c->data_pointer_offset); + } + printf("...\n"); + } + } + if (debug >= 1) { + /* Do a post-facto check on the data, to check it has the right parameters */ + void *p = adjusted_data; + WorkingSetCharacteristics ws; + printf("Collecting data working set characteristics...\n"); + ws_init(&ws); + do { + void **load_addr = (void **)((unsigned char *)p + c->data_pointer_offset); + ws_update(&ws, load_addr, sizeof(void *)); + p = *load_addr; + if (ws.n_access > expected_chain_length) { + fprintf(stderr, "working set corrupt\n"); + assert(0); + } + } while (p != adjusted_data); + assert(round_size(ws_range(&ws), chunk) == size_rounded_to_lines); + if (debug >= 1) { + ws_show(&ws); + } + ws_free(&ws); + } + if (1) { + unsigned int cl = chain_length(adjusted_data, c->data_pointer_offset); + assert(cl == expected_chain_length); + if (debug >= 1) { + printf("Data chain length verified as %lu (%lu-byte footprint in %u-byte lines)\n", + (unsigned long)cl, ((unsigned long)cl * LINE), LINE); + } + } + if (debug >= 1) { + printf("Constructed data working set.\n"); + } + /* Return the initial offsetted pointer that the client should use when + iterating through the working set. Each load will add the fixed offset to + the current pointer. The actual memory area is remembered in the + memory descriptor structure and will be used on free. */ + return adjusted_data; +} + diff --git a/linux_app/pmu_app/pysweep/src/loadgen.c b/linux_app/pmu_app/pysweep/src/loadgen.c new file mode 100644 index 00000000..5b7ef31f --- /dev/null +++ b/linux_app/pmu_app/pysweep/src/loadgen.c @@ -0,0 +1,644 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +/* + * Generate a runnable workload in memory, based on a set of workload characteristics. + */ + +/* + * Have to define this to get sigaction, MAP_ANONYMOUS etc. + * Define it now in case our headers pull in any system headers. + */ +#ifndef _GNU_SOURCE +#define _GNU_SOURCE +#endif + +#include "loadgenp.h" + +#include "arch.h" +#include "genelf.h" +#include "denormals.h" + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + + +int workload_verbose = 0; + + +static unsigned long round_size_to_pages(unsigned long size) +{ + return round_size(size, sysconf(_SC_PAGESIZE)); +} + + +/* + * Find out the system's huge page size, so that we can safely use MAP_HUGETLB. + * MAP_HUGETLB allocations must be rounded up to this size. + * + * Return 0 if we can't find the size. + */ +static unsigned long huge_page_size(void) +{ + static unsigned long size = 1; /* Never valid; initiates discovery */ + if (size == 1) { + FILE *fd = fopen("/proc/meminfo", "r"); + char buf[100]; + while (fgets(buf, sizeof buf, fd)) { + if (!memcmp(buf, "Hugepagesize:", 13)) { + long sizek = 0; + if (sscanf(buf+13, "%ld", &sizek) == 1) { + size = sizek * 1024; + if (size != 0) { + assert((size & -size) == size); /* power of 2 */ + assert((long)size > sysconf(_SC_PAGESIZE)); /* TBD: always? */ + } + break; + } + } + } + fclose(fd); + if (!size) { + fprintf(stderr, "Couldn't get huge page size\n"); + size = 0; + } + } + return size; +} + + +static unsigned long total_mmap_size = 0; +static unsigned int total_mmap_count = 0; + + +/* + * Allocate some memory, e.g. for data or code working set. + * The memory is page-aligned, so that we can later change its protection. + * On return, the workload_mem structure is filled in. + * TBD: What should we do for size zero? + */ +void *load_alloc_mem(struct workload_mem *m) +{ + void *p; + unsigned long rsize; + /* MAP_POPULATE is documented as pre-populating the page tables. */ + int flags = MAP_PRIVATE|MAP_ANONYMOUS; + assert(m->size_req > 0); + rsize = round_size_to_pages(m->size_req); + /* MAP_HUGETLB is only available if the size is a multiple of the + huge page size. When the user requests HUGETLB for a smaller allocation, + do they want us to round up the size, or ignore HUGETLB? */ + if ((m->is_hugepage && rsize >= huge_page_size()) || + m->is_force_hugepage) { + /* Is it even worth doing this if /proc/sys/vm/nr_hugepages is 0? */ + flags |= MAP_HUGETLB; + rsize = round_size(rsize, huge_page_size()); + } + /* We can't force mmap() to allocate with small pages. + But we can allocate without population, then madvise(MADV_NOHUGEPAGE), + then populate. */ + if (!m->is_no_hugepage) { + flags |= MAP_POPULATE; + } + m->size = rsize; + m->base = NULL; + if (1) { + /* _GNU_SOURCE should have ensured we see MAP_ANONYMOUS */ + unsigned int prot = PROT_READ|PROT_WRITE; + if (m->is_exec) { + prot |= PROT_EXEC; + } + assert(!(flags & MAP_HUGETLB) || (rsize % huge_page_size()) == 0); + if (workload_verbose) { + fprintf(stderr, "loadgen: mmap %lu/%#lx bytes, prot=%04x, flags=%04x\n", + (unsigned long)rsize, (unsigned long)rsize, (unsigned int)prot, (unsigned int)flags); + } + p = mmap(NULL, rsize, prot, flags, -1, 0); + if (p == MAP_FAILED && (flags & MAP_HUGETLB) != 0 && errno == ENOMEM) { + if (workload_verbose) { + fprintf(stderr, "loadgen: mmap(MAP_HUGETLB) failed, will retry and use madvise(MADV_HUGEPAGE)\n"); + } + /* Try again, using madvise() to force huge pages */ + flags = flags & ~MAP_HUGETLB; + /* We don't want the pages to be allocated until we've done madvise() */ + flags = flags & ~MAP_POPULATE; + p = mmap(NULL, rsize, prot, flags, -1, 0); + } + if (p == MAP_FAILED) { + perror("mmap"); + fprintf(stderr, "Failed to allocate %lu/%#lx bytes (flags 0x%x, page size %lu): total out %u, %lu bytes\n", + (unsigned long)rsize, (unsigned long)rsize, + (unsigned int)flags, + (unsigned long)sysconf(_SC_PAGESIZE), + total_mmap_count, + (unsigned long)total_mmap_size); + return NULL; + } + total_mmap_count += 1; + total_mmap_size += rsize; + m->is_mmap = 1; + /* We don't need to use MADV_HUGEPAGE, as we will have mmap'ed with MAP_HUGETLB */ + if ((m->is_hugepage || m->is_force_hugepage) && !(flags & MAP_HUGETLB)) { +#ifdef MADV_HUGEPAGE + int rc = madvise(p, rsize, MADV_HUGEPAGE); + if (rc < 0) { + perror("madvise"); + m->is_hugepage = 0; + } +#else + fprintf(stderr, "MADV_HUGEPAGE not available when this module was built\n"); + m->is_hugepage = 0; +#endif + } + if (m->is_no_hugepage) { +#ifdef MADV_NOHUGEPAGE + int rc = madvise(p, rsize, MADV_NOHUGEPAGE); + if (rc < 0) { + perror("madvise"); + m->is_no_hugepage = 0; + } +#else + fprintf(stderr, "MADV_NOHUGEPAGE not available when this module was built\n"); + m->is_no_hugepage = 0; +#endif + } + } + m->base = p; + if (workload_verbose) { + fprintf(stderr, "loadgen: alloc %p size %lu\n", m->base, m->size); + } + assert(p != NULL); + return p; +} + + +void load_free_mem(struct workload_mem *m) +{ + if (m->base) { + if (workload_verbose) { + fprintf(stderr, "loadgen: free %p size %lu\n", m->base, m->size); + } + if (m->is_mmap) { + unsigned long rsize = round_size_to_pages(m->size); + assert(total_mmap_size >= rsize); + munmap(m->base, rsize); + total_mmap_count -= 1; + total_mmap_size -= rsize; + } else { + free(m->base); + } + m->base = NULL; + } +} + + +/* +This function has the same API as the workload we create, and can be used +as a stub when we're diagnosing crashes with the workload. +*/ +static void *dummy_workload_code(void *p, void *offsetp, void *scratch) +{ + unsigned long offset = (unsigned long)offsetp; + void **actualp = (void **)((unsigned char *)p + offset); + void *next; + if (0) { + fprintf(stderr, "data step: input pointer %p, add %ld, actual address %p:\n", + p, offset, actualp); + } + next = *actualp; + if (0) { + fprintf(stderr, " -> %p\n", next); + } + return next; +} + + +static void *dummy_workload_code_nodata(void *p, void *unused, void *scratch) +{ + return 0; +} + + +static int workload_code_is_trivial(Character const *c) +{ + if (c->debug_flags & WORKLOAD_DEBUG_DUMMY_CODE) { + return 1; + } + return (c->inst_working_set == 0 && c->fp_intensity == 0); +} + + +void workload_init(Character *c) +{ + memset(c, 0, sizeof(Character)); + c->fp_value = 1.0; + c->fp_value2 = 1.0; + c->inst_target = 50000; +} + + +/* + * Construct a new workload. + * All memory needed for this workload is newly allocated. + * Return NULL if we can't create the workload. + */ +Workload *workload_create(Character const *c) +{ + void *data; + Workload *w = (Workload *)malloc(sizeof(Workload)); + + if (workload_verbose) { + fprintf(stderr, "loadgen: creating workload...\n"); + } + memset(w, 0, sizeof(Workload)); + w->elf_image = elf_create(); + /* Take a copy of the supplied workload characteristics. + Later changes made by the caller will not take effect. */ + w->c = *c; + data = load_construct_data(&w->c, &w->data_mem); + if (c->data_working_set > 0 && !data) { + /* Data working set was requested but couldn't be constructed */ + free(w); + if (workload_verbose) { + fprintf(stderr, "loadgen: couldn't create data working set\n"); + } + return NULL; + } + if (w->data_mem.base != NULL) { + elf_add_data(w->elf_image, w->data_mem.base, w->data_mem.size); + } + if (workload_code_is_trivial(c)) { + w->expected.n[COUNT_INST] = 100; /* Just a guess */ + if (c->data_working_set) { + w->entry = &dummy_workload_code; + w->expected.n[COUNT_INST_RD] = 1; + w->expected.n[COUNT_BYTES_RD] = sizeof(void *); + } else { + /* We mustn't try to run a chain pointer step when there's no + data working set. */ + w->entry = &dummy_workload_code_nodata; + } + } else if (load_construct_code(w)) { + /* We've now dynamically constructed a workload code sequence. */ + assert(w->entry != NULL); + } else { + /* Code was requested but couldn't be constructed - + e.g. maybe self-modifying code has been locked out by the OS. + If we didn't need a code workload with specific code footprint, + we might be able to fall back to a predefined function + that would iterate through the data working set. But we don't + currently support that. */ + free(w); + if (workload_verbose) { + fprintf(stderr, "loadgen: couldn't create code working set\n"); + } + return NULL; + } + w->entry_args[0] = data; + w->entry_args[1] = (void *)(unsigned long)w->c.data_pointer_offset; + if (workload_verbose) { + fprintf(stderr, "loadgen: %p: set up workload entry %p with args [%p, %p]\n", + w, w->entry, + w->entry_args[0], w->entry_args[1]); + fprint_code(stderr, w->entry, 32); + } + + /* WORKLOAD_KEEP presets the workload reference counter to a high + number so that the workload isn't deleted even when not in use. + When we later want to delete the workload, we subtract WORKLOAD_KEEP + so that when the reference counter drops to zero the workload can + be deleted. */ +#define WORKLOAD_KEEP 100000 + w->references = WORKLOAD_KEEP; /* Make it stick until deleted */ + if (0) { + if (workload_verbose) { + fprintf(stderr, "loadgen: %p: trial run...\n", w); + } + /* Run the workload once, just to check */ + workload_run_once(w); + if (workload_verbose) { + fprintf(stderr, "loadgen: %p: trial run successful\n", w); + } + } + assert(w->references == WORKLOAD_KEEP); + return w; +} + + +/* + * Create an image file containing the code for the workload. + * The flags option currently isn't used. + * The file is generated in ELF format for direct viewing with e.g. "objdump -d". + * TBD: generate jitdump. + */ +int workload_dump(Workload *w, char const *fn, unsigned int flags) +{ + int rc; + if (workload_verbose) { + fprintf(stderr, "loadgen: %p: dumping image: %s\n", w, fn); + } + rc = elf_dump(w->elf_image, fn); + if (workload_verbose) { + fprintf(stderr, "loadgen: %p: dumped image: %s\n", w, fn); + } + return rc; +} + + +/* + * Clean up and destroy a workload. + * The workload must not be currently running. + * This function must be called once, by only one thread. + */ +static void workload_destroy(Workload *w) +{ + if (workload_verbose) { + fprintf(stderr, "loadgen: %p: destroy\n", w); + } + if (w->references != 0) { + fprintf(stderr, "** loadgen: %p: workload_destroy called when references=%d\n", w, w->references); + /* How did this happen? We shouldn't have been called unless and until + 'running' was finally set to zero, and no more iterations should + have been started after that point. */ + } + assert(!w->references); +#if 0 + if (w->elf_image != NULL) { + elf_destroy(w->elf_image); + w->elf_image = NULL; + } +#endif + if (!(w->c.debug_flags & WORKLOAD_DEBUG_NO_FREE)) { + load_free_mem(&w->data_mem); + load_free_code(w); + } else { + fprintf(stderr, "loadgen: %p: debug request to not free working sets\n", w); + } + /* If somehow we've still got a workload running, it's possibly + crashed by now, as we've released the code and data. */ + assert(!w->references); + free(w); + if (workload_verbose) { + fprintf(stderr, "loadgen: %p (freed): workload destroyed\n", w); + } +} + + +/* + * User request to delete the workload. If the workload is not in use (running), + * it is deleted right now, otherwise it is marked for deletion when the last + * runner completes. + * This function must be called only once per workload. + */ +int workload_free(Workload *w) +{ + int destroyed = 0; + if (w) { + int now_running; + if (workload_verbose) { + fprintf(stderr, "loadgen: %p: free\n", w); + } + now_running = __sync_sub_and_fetch(&w->references, WORKLOAD_KEEP); + if (!now_running) { + workload_destroy(w); + destroyed = 1; + } else { + if (workload_verbose) { + fprintf(stderr, "loadgen: %p: pending delete (%d)\n", w, now_running); + } + assert(destroyed == 0); + } + } + return destroyed; +} + + +void workload_add_reference(Workload *w) +{ + __sync_fetch_and_add(&w->references, 1); +} + + +void workload_remove_reference(Workload *w) +{ + int now_running = __sync_sub_and_fetch(&w->references, 1); + assert(now_running >= 0); + if (__builtin_expect((now_running == 0), 0)) { + if (workload_verbose) { + fprintf(stderr, "loadgen: %p: workload was marked for delete, now deleting\n", w); + } + workload_destroy(w); + } +} + + +/* +This is a dubious way to ensure the FP registers have known values +before we go into the generated workload code. Only the first three +registers need to be set. The workload code will copy them to the +remaining work registers. +*/ +__attribute__((noinline,used)) +static double fp_regs_clearer_double(double a, double b, double c) +{ + __asm__(""); + return a + b + c; +} + +__attribute__((noinline,used)) +static float fp_regs_clearer_float(float a, float b, float c) +{ + __asm__(""); + return a + b + c; +} + + +/* + * As preparation for running a sequence of generated floating-point instructions, + * set up the floating-point work registers. + */ +static void fp_regs_clear_double(double workval, double constval) +{ + fp_regs_clearer_double(0.0, workval, constval); +} + +static void fp_regs_clear_float(double workval, double constval) +{ + fp_regs_clearer_float(0.0, workval, constval); +} + + +/* +If we want to see the effect of denormals on +instruction timings, when we're using the output of one instruction as +a data input of the next, we need to ensure that denormals don't quickly +evaporate. So for example MUL of two denormals would go to zero. +A better result is to MUL a denormal with a value close to 1 (but not +exactly 1 as that might take a fast path): + + x = DENORMAL; + x = NEAR1 * x; + x = NEAR1 * x; + +or + + x = DENORMAL; + x = NEAR1 / x; // x now large finite (not denormal) + x = NEAR1 / x; // x now denormal again + +For division, in order that NEAR1/x doesn't overflow to infinity, +we should pick a value of NEAR1 that's somewhat less than 1, +e.g. 1e-7 for float and 1e-15 for double. +*/ + + +static void signal_handler(int sig, siginfo_t *si, void *unused) +{ + unsigned int i; + if (sig == SIGILL) { + unsigned char const *p = (unsigned char const *)si->si_addr; + fprintf(stderr, "loadgen: SIGILL from illegal instruction at %p\n", p); + fprint_code(stderr, si->si_addr, 32); + } else if (sig == SIGSEGV) { + unsigned char const *p = (unsigned char const *)si->si_addr; + fprintf(stderr, "loadgen: SIGSEGV from illegal address at %p\n", p); + } else { + fprintf(stderr, "loadgen: signal %d at %p\n", sig, si->si_addr); + } + const int MAX_BACKTRACE = 20; + void *array[MAX_BACKTRACE]; + size_t size = backtrace(array, MAX_BACKTRACE); + char **strings = backtrace_symbols(array, size); + for (i = 0; i < size; ++i) { + printf("%s\n", strings[i]); + } + free(strings); + exit(EXIT_FAILURE); +} + + +__attribute__((noinline)) +static void *workload_enter(Workload *w, void *data, unsigned int n_iters) +{ + unsigned int i; + /* Run some iterations of the workload. This may take some time. */ + /* FP operations will use the ambient contents of the FP registers. */ + for (i = 0; i < n_iters; ++i) { + if (0) { + fprintf(stderr, "loadgen: %p: run iteration %u with %p\n", w, i, data); + } + data = (w->entry)(data, w->entry_args[1], w->scratch); + } + return data; +} + + +/* +Run the next 'chunk' of a workload using some prior state, +perhaps the state returned from last time in argument 0. +Other arguments will be picked up from the work descriptor. + +This may be run from multiple threads, so we should avoid updating +any shared state. +*/ +void *workload_run(Workload *w, void *data, unsigned int n_iters) +{ + assert(w != NULL); + if (workload_verbose >= 2) { + fprintf(stderr, "loadgen: %p: run workload entry %p with args [%p (originally %p), %p], %u iterations\n", + w, w->entry, + data, w->entry_args[0], w->entry_args[1], + n_iters); + } + static int sigdone; + if (!sigdone) { + int rc; + struct sigaction sa; + sa.sa_flags = SA_SIGINFO; + sigemptyset(&sa.sa_mask); + sa.sa_sigaction = signal_handler; + sigdone = 1; + rc = sigaction(SIGSEGV, &sa, NULL); + if (rc != -1) { + rc = sigaction(SIGILL, &sa, NULL); + } + if (rc == -1) { + perror("sigaction"); + fprintf(stderr, "loadgen: %p: could not set trap handler\n", w); + } + } + //fp_regs_clear(1.0); + if (!denormals_set_enabled((w->c.fp_flags & FP_FLAG_DENORMAL_FTZ) == 0)) { + /* TBD we should have done this earlier and returned a failure code */ + fprintf(stderr, "** Could not set required denormal handling mode\n"); + assert(0); + } +#if defined(__x86_64__) + /* On x86 with AVX, we can take an ongoing penalty when doing XMM operations, + on 128-bit values, if the upper 128 bits of 256-bit registers are non-zero. + To fix this, we need to do a VZEROALL or VZEROUPPER. + The performance penalty seems to be about 1 cycle per operation. + It doesn't seem to be well indicated by hardware events. It doesn't + correspond to an assist, for example. + */ + __asm__("vzeroupper"); + //_mm256_zeroupper(); +#endif + /* Provide suitable input values. + The sequence of FP operations modifies the values in registers so + (the back-to-back chaining is critical to measuring latency) so the + values we provide here may quickly vanish, diverge etc. TBD do better. + */ + if (w->c.fp_precision == FP_PRECISION_DOUBLE) { + fp_regs_clear_double((w->c.fp_flags & FP_FLAG_DENORMAL_GEN) ? DOUBLE_DENORMAL : w->c.fp_value, + (w->c.fp_operation == FP_OP_DIV ? 1e-15 : w->c.fp_value2)); + } else { + fp_regs_clear_float((w->c.fp_flags & FP_FLAG_DENORMAL_GEN) ? FLOAT_DENORMAL : (float)w->c.fp_value, + (w->c.fp_operation == FP_OP_DIV ? 1e-7 : (float)w->c.fp_value2)); + } + data = workload_enter(w, data, n_iters); + return data; +} + + +void workload_run_once(Workload *w) +{ + void *ndata; + if (workload_verbose) { + fprintf(stderr, "loadgen: %p: run workload entry %p with args %p %p\n", + w, w->entry, + w->entry_args[0], w->entry_args[1]); + } + ndata = workload_run(w, w->entry_args[0], 1); + if (workload_verbose) { + fprintf(stderr, "loadgen: %p: workload returned %p\n", w, ndata); + } +} + + +/* end of loadgen.c */ + diff --git a/linux_app/pmu_app/pysweep/src/loadgen.h b/linux_app/pmu_app/pysweep/src/loadgen.h new file mode 100644 index 00000000..1a357607 --- /dev/null +++ b/linux_app/pmu_app/pysweep/src/loadgen.h @@ -0,0 +1,258 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +/* +Synthetic workload generator / executor. + +This module constructs and executes synthetic workloads based on a set of +generic input parameters (characteristics) describing aspects such as + + - code working set + - data working set + - branch predictability + - use of various instruction groups + +The resulting workload, when run, should consume CPU and system resources +corresponding to its characteristics. +*/ + + +#ifndef __included_loadgen_h +#define __included_loadgen_h + +#include "genelf.h" + +#include + +/* +Workload characteristics structure. + +This is filled in by the client, to specify the workload. +*/ +typedef struct { + /* Data working set in bytes. Currently assumed to be flat + (i.e. randomly distributed, not clumped). */ + unsigned long data_working_set; + /* The data pointer offset can be set non-zero to try and defeat + linked-list prefetchers. The offset will be applied to pointers + stored in the data working set, and adjusted for in the loads. */ + unsigned int data_pointer_offset; + /* How sparse is the data? This multiplier is applied to the + addresses within the data. (A default of 0 has the effect of 1.) */ + unsigned int data_dispersion; + /* Alignment of pointers in the data working set - e.g. 1 for + byte alignment. Set to 0 for natural alignment. */ + unsigned int data_alignment; + /* Instruction working set in bytes. */ + unsigned long inst_working_set; + unsigned int inst_mispredict_rate; +#define WL_MEM_BW 0x01 /* Measure for memory bandwidth not latency */ +#define WL_MEM_NONTEMPORAL 0x02 /* Use non-temporal loads where possible */ +#define WL_MEM_LOAD_EXTRA 0x04 /* Generate an additional (unused) load */ +#define WL_MEM_LOAD_PAIR 0x08 /* Use a non-temporal load */ +#define WL_MEM_PREFETCH 0x10 /* Issue a software prefetch before loading */ +#define WL_MEM_STREAM 0x20 /* Use stream rather than random workload */ +#define WL_MEM_NO_HUGEPAGE 0x40 /* Request no huge-pages */ +#define WL_MEM_HUGEPAGE 0x80 /* Request huge-pages */ +#define WL_MEM_FORCE_HUGEPAGE 0x100 /* Request huge-pages even when small */ +#define WL_MEM_BARRIER 0x200 /* Generate a load barrier after each load */ +#define WL_MEM_ACQUIRE 0x400 /* Use load-acquire instruction */ +#define WL_MEM_NOP 0x800 /* Generate a NOP after each load */ +#define WL_MEM_STORE 0x1000 /* Generate stores as well as loads */ +#define WL_MEM_RELEASE 0x2000 /* Use store-release instruction */ +#define WL_MEM_ATOMIC 0x4000 /* Use atomic instruction */ +#define WL_DEPEND 0x8000 /* Force total dependency chain */ +#define WL_MEM_BARRIER_SYSTEM 0x10000 /* e.g. DMB SY */ +#define WL_MEM_BARRIER_SYNC 0x20000 /* serializing wrt instructions: DSB instead of DMB */ + unsigned int workload_flags; /* WL_xxx flags */ + /* Floating-point intensity - FP ops per memory reference. */ + unsigned int fp_intensity; + /* Arithmetic precision */ +#define FP_PRECISION_FP16 1 +#define FP_PRECISION_SINGLE 2 +#define FP_PRECISION_DOUBLE 3 + unsigned int fp_precision; /* 1: FP16, 2: SP, 3: DP */ + unsigned int fp_simd; /* 0: scalar, N: N-way SIMD */ +#define FP_OP_MOV 0 +#define FP_OP_IADD 1 +#define FP_OP_IXOR 2 +#define FP_OP_NEG 3 +#define FP_OP_ADD 4 +#define FP_OP_MUL 5 +#define FP_OP_DIV 6 +#define FP_OP_SQRT 7 +#define FP_OP_FMA 8 /* up to here, we must match arrays in loadinst.c */ +#define FP_OP_FMAA 9 +#define FP_OP_MULADD 10 +#define FP_OP_DOT2 11 +#define FP_OP_DOT4 12 +#define FP_OP_DIST2 13 + unsigned int fp_operation; + unsigned int fp_concurrency; /* Number of concurrent ops: 1 = back-to-back */ + double fp_value; /* Floating-point data value initializer */ + double fp_value2; /* Floating-point data value corrector */ + + /* Floating-point flags can modify both the target configuration and + our generated code. */ +#define FP_FLAG_DENORMAL_GEN 0x01 /* Code generation: use denormal inputs */ +#define FP_FLAG_DENORMAL_FTZI 0x02 /* Target mode: flush to zero on input */ +#define FP_FLAG_DENORMAL_FTZO 0x04 /* Target mode: flush to zero on output */ +#define FP_FLAG_DENORMAL_FTZ (FP_FLAG_DENORMAL_FTZI|FP_FLAG_DENORMAL_FTZO) +#define FP_FLAG_ALTERNATE 0x08 /* Use alternate instruction form (whatever it is) */ +#define FP_FLAG_SIMPLE_VAL 0x10 /* Use simple (possibly fast) value */ +#define FP_FLAG_CONVERGE 0x20 /* For DIV, converge to result of 1.0 */ +#define FP_FLAG_LOAD_CONST 0x40 /* Load constants from memory */ + unsigned int fp_flags; + + /* Debugging/diagnostic flags for workload generation. */ +#define WORKLOAD_DEBUG_NO_MPROTECT 1 /* don't do mprotect() even if we need to */ +#define WORKLOAD_DEBUG_NO_UNIFICATION 2 /* don't do cache unification even if we need to */ +#define WORKLOAD_DEBUG_DUMMY_CODE 4 /* never generate code */ +#define WORKLOAD_DEBUG_NO_WX 8 /* avoid write+execute */ +#define WORKLOAD_DEBUG_NO_FREE 0x10 /* don't free any memory - in case race */ +#define WORKLOAD_DEBUG_TRIAL_RUN 0x20 /* check workload runs, immediately after construction */ + unsigned int debug_flags; + unsigned long inst_target; /* Target no. of insts for one execution of workload */ +} Character; + + +void workload_init(Character *); + + +/* +What the entry point for a workload looks like. +There may also be implicit floating-point arguments (TBD improve). +*/ +typedef void *(* dummy_fn_t)(void *, void *, void *); + + +/* +When generating the workload code, we keep track of how +many instructions of these different categories we expect +to execute. This can then be calibrated against observed +performance events. +*/ +typedef enum InstCounter { + /* The following correspond to hardware counters. */ + COUNT_INST, /* Total instructions */ + COUNT_BRANCH, /* Any kind of branch or transfer of control */ + COUNT_FLOP_HALF, /* Half-precision floating-point operations */ + COUNT_FLOP_SP, /* SP floating-point operations: FMA counts 2, SIMD counts N */ + COUNT_FLOP_DP, /* DP floating-point operations: FMA counts 2, SIMD counts N */ + COUNT_MOVE, /* Register moves (any kind) */ + COUNT_INST_RD, /* Memory read instructions */ + COUNT_BYTES_RD, /* Memory read bytes */ + COUNT_INST_WR, /* Memory write instructions */ + COUNT_BYTES_WR, /* Memory write bytes */ + COUNT_FENCE, /* Fences/barriers */ +#define COUNT_MEM_PREFETCH COUNT_INST /* Don't count prefetches as reads */ + /* The following are more arbitrary measures, when we are generating + sequences of instructions (e.g. dot-product). */ + COUNT_UNIT, + /* Number of counter types, for sizing counter arrays */ + COUNT_MAX +} inst_counter_t; + + +struct inst_counters { + unsigned int n[COUNT_MAX]; +}; + + +/* Properties of an allocated memory block - useful for when we want to free */ +struct workload_mem { + /* Input parameters */ + unsigned long size_req; /* Size actually wanted */ + int is_exec:1; /* Allocate as executable */ + int is_no_hugepage:1; /* Forbid allocation as huge pages */ + int is_hugepage:1; /* Request opportunistic promotion to huge pages if large enough */ + int is_force_hugepage:1; /* Request promotion to huge pages even for small allocations */ + /* Output */ + void *base; /* Base virtual address */ + unsigned long size; /* Size obtained - maybe rounded up to pages etc. */ + int is_mmap:1; /* Obtained by mmap (not malloc) */ +}; + +/* +Details of a workload created to implement the workload characteristics +requested by a client. +*/ +typedef struct { + /* Data passed in by client */ + Character c; /* Copy of workload characteristics as specified by client */ + + /* Data about the generated workload code */ + struct inst_counters expected; /* Count values per entry call */ + unsigned int n_chain_steps; /* number of data steps per iteration */ + elf_t elf_image; /* Internal descriptor for ELF generation */ + + /* Data required to run the workload */ + dummy_fn_t entry; /* Code entry point */ + void *entry_args[2]; /* Arguments for entry point */ + + /* Following are internal details - shouldn't really be exposed here */ + struct workload_mem code_mem; + struct workload_mem data_mem; + + /* Current status of the workload */ + volatile unsigned int references; /* Number of threads running this workload */ + + /* Anything else needed by the workload */ + uint64_t scratch[16]; /* Scratch space for spills etc. */ +} Workload; + + +/* + * Builds a workload with the given characteristics. + * Returns a workload object. + */ +Workload *workload_create(Character const *); + +/* + * Increment the reference count on a workload. + */ +void workload_add_reference(Workload *); + +/* + * Decrement the reference count and possibly destroy the workload. + */ +void workload_remove_reference(Workload *); + +/* + * Destroy a workload object. + * Return 1 if the workload was actually freed, 0 if deferred. + */ +int workload_free(Workload *); + +/* + * Run the first iteration of a workload in the current thread, and then stop. + * Multiple threads can concurrently run the same workload. + */ +void workload_run_once(Workload *); + +/* + * Run N iterations of a workload in the current thread. + */ +void *workload_run(Workload *, void *, unsigned int); + +/* + * Dump workload to an ELF file. + */ +int workload_dump(Workload *, char const *fn, unsigned int flags); + +#endif /* included */ + diff --git a/linux_app/pmu_app/pysweep/src/loadgenp.h b/linux_app/pmu_app/pysweep/src/loadgenp.h new file mode 100644 index 00000000..2bedc45b --- /dev/null +++ b/linux_app/pmu_app/pysweep/src/loadgenp.h @@ -0,0 +1,56 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +/* Private header for load generation */ + +#ifndef __included_loadgenp_h +#define __included_loadgenp_h + +#include "loadgen.h" + +#include +#include + +extern int workload_verbose; + +extern void *load_alloc_mem(struct workload_mem *); + +extern void load_free_mem(struct workload_mem *); + +extern void *load_construct_code(Workload *); + +extern void load_free_code(Workload *); + +extern void *load_construct_data(Character const *, struct workload_mem *); + +#ifdef __cplusplus +template +inline T round_size(T size, unsigned int granule) +{ + return (size + (granule-1)) & ~(T)(granule-1); +} +#else +/* Round the size by ANDing with a suitable constant. + The constant must be as wide as the size. */ +#define round_size(size, granule) ((size + ((granule)-1)) & ~((size)*0+(granule)-1)) +#endif + +extern void fprint_mem(FILE *, void const *, size_t); + +extern void fprint_code(FILE *, void const *, size_t); + +#endif /* included */ diff --git a/linux_app/pmu_app/pysweep/src/loadinst.c b/linux_app/pmu_app/pysweep/src/loadinst.c new file mode 100644 index 00000000..58e2c2f7 --- /dev/null +++ b/linux_app/pmu_app/pysweep/src/loadinst.c @@ -0,0 +1,1117 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +/* + * Generate code for a runnable workload in memory, based on a set of workload characteristics. + * + * Much of this unit is about generating instructions for x86 and ARM. + * A future direction would be for this function to be performed via some + * existing tool such as LLVM or DynamoRIO. + */ + +#include "loadinst.h" + +#include "loadgenp.h" + +#include +#include +#include +#include +#include +#include + + +/* +Define a type corresponding to a code address. + +Note that for ARM/Thumb we assume that we're generating code according to the +instruction set with which this translation unit is compiled. +*/ +#ifdef ARCH_T32_ +typedef unsigned short code_t; +#elif defined(ARCH_A32) +typedef unsigned int code_t; +#elif defined(ARCH_A64) +typedef unsigned int code_t; +#elif defined(__x86_64__) +typedef unsigned char code_t; +#else +#error "Unexpected architecture" +#endif + + +/* + * This structure maintains a pointer into the instruction stream + * we're building, and allows the code builder to generate branches + * when needed to move to the next cache line. + */ +struct codestream { + struct inst_counters *metrics; /* For counting instructions of different types */ + unsigned int multiplier; + int use_alternate; + unsigned char *base; /* Base of the whole area */ + size_t size; /* Size of the whole area */ + unsigned int line_size; /* Line size e.g. 64 */ + /* The following fields are updated as we generate code */ + unsigned int line_reserve; + unsigned char *line; + unsigned char *line_end; + code_t *p; /* running code pointer */ + int ran_out_of_space; + int error; +}; + + +static void expect_ops(CS *cs, inst_counter_t type, unsigned int n) +{ + cs->metrics->n[type] += n * cs->multiplier; +} + + +static void expect_op(CS *cs, inst_counter_t type) +{ + expect_ops(cs, type, 1); +} + + +static void expect_inst(CS *cs, inst_counter_t type) +{ + expect_op(cs, type); + if (type != COUNT_INST) { + expect_op(cs, COUNT_INST); + } +} + + +void codestream_show(CS const *cs) +{ + fprintf(stderr, "code stream [%p..%p size %#zx] at %p in %p..%p\n", + cs->base, cs->base+cs->size, cs->size, + cs->p, cs->line, cs->line_end); +} + + +static void codestream_start_line(CS *cs, unsigned char *line) +{ + cs->line = line; + cs->line_end = cs->line + cs->line_size; + cs->p = (code_t *)cs->line; +#ifdef __x86_64__ + memset(cs->p, 0xCC, cs->line_size); +#endif +} + + +/* + * Initialize a code writing stream in a code buffer. + * In order to get some diversity in code locations, we arrange the + * buffer as a sequence of code lines. + * The stream actually goes backwards, starting with the last line. + * As we reach the end of a line we hop backwards to the previous line. + */ +CS *codestream_init(struct inst_counters *counters, + void *base, size_t size, unsigned int line_size) +{ + CS *cs = (CS *)malloc(sizeof(CS)); + if (!cs) { + return cs; + } + memset(cs, 0, sizeof *cs); + cs->metrics = counters; + cs->multiplier = 1; + /* line_size must be a suitable cache line size */ + assert(line_size > 0 && (line_size % 32) == 0); + /* base is the code area we dynamically allocated */ + assert((unsigned long)base % line_size == 0); + cs->base = (unsigned char *)base; + /* The user-provided buffer size doesn't have to be a multiple + of the line size. We'll have rounded it up when allocating. */ + cs->size = (size + line_size - 1) & (~(line_size-1)); + assert(cs->size >= size); + assert(cs->size < (size + line_size)); + assert((cs->size % line_size) == 0); + cs->line_size = line_size; + cs->ran_out_of_space = 0; + cs->error = 0; + codestream_start_line(cs, base + (cs->size - cs->line_size)); + cs->line_reserve = 4; /* Enough for a short branch */ + return cs; +} + +void codestream_use_alternate(CS *cs) +{ + cs->use_alternate = 1; +} + +void codestream_set_multiplier(CS *cs, int m) +{ + assert(m >= 0); + cs->multiplier = m; +} + +int codestream_push_multiplier(CS *cs, int m) +{ + assert(m >= 0); + cs->multiplier *= m; + return cs->multiplier; +} + +int codestream_pop_multiplier(CS *cs, int m) +{ + assert(m >= 0); + assert((cs->multiplier % m) == 0); + cs->multiplier /= m; + return cs->multiplier; +} + + +void codestream_free(CS *cs) +{ + free(cs); +} + +void *codestream_addr(CS const *cs) +{ + return cs->p; +} + + +/* + * Set the error flag, which we'll test later + */ +static void codestream_error(CS *cs, char const *reason, ...) +{ + va_list args; + va_start(args, reason); + fprintf(stderr, "codegen error: "); + vfprintf(stderr, reason, args); + fprintf(stderr, "\n"); + va_end(args); + cs->error += 1; +} + +int codestream_errors(CS const *cs) +{ + return cs->error; +} + +static void codestream_gen(CS *cs, code_t data) +{ + *(cs->p++) = data; +} + +void codestream_gen_direct(CS *cs, unsigned int data) +{ + codestream_gen(cs, (code_t)data); +} + +static void __attribute__((unused)) codestream_gen2(CS *cs, code_t a, code_t b) +{ + codestream_gen(cs, a); + codestream_gen(cs, b); +} + +static void __attribute__((unused)) codestream_gen3(CS *cs, code_t a, code_t b, code_t c) +{ + codestream_gen(cs, a); + codestream_gen(cs, b); + codestream_gen(cs, c); +} + +static void __attribute__((unused)) codestream_gen4(CS *cs, code_t a, code_t b, code_t c, code_t d) +{ + codestream_gen(cs, a); + codestream_gen(cs, b); + codestream_gen(cs, c); + codestream_gen(cs, d); +} + +#ifdef __x86_64__ +static void codestream_gen32(CS *cs, int data) +{ + *(signed int *)(cs->p) = data; + cs->p += 4; +} +#endif + + +/* + * See how many contiguous bytes are left in the current code line. + * If the next instruction needs more than this we'll need to first + * branch to a new code line. + */ +static unsigned int codestream_bytes_left(CS const *cs) +{ + int bytes_left_s = (cs->line_end - (unsigned char *)cs->p) - cs->line_reserve; + if (bytes_left_s < 0) { + fprintf(stderr, "overran buffer (reserving %u): p=%p, end=%p\n", + cs->line_reserve, cs->p, cs->line_end); + /* we hope the caller will assert on -ve result */ + bytes_left_s = 0; + } + return (unsigned int)bytes_left_s; +} + + +int codestream_gen_call(CS *cs, void *dest) +{ + int disp; +#ifdef ARCH_T32 +#error TBD +#elif defined(ARCH_A32) +#error TBD +#elif defined(ARCH_A64) + disp = ((code_t *)dest - cs->p); + codestream_gen(cs, 0x97000000 | (disp & 0xffffff)); +#elif defined(__x86_64__) + disp = ((code_t *)dest - (cs->p + 5)); + codestream_gen(cs, 0xE8); /* Relative call */ + codestream_gen32(cs, disp); +#endif + expect_inst(cs, COUNT_BRANCH); + return 1; +} + + +int codestream_gen_ret(CS *cs) +{ +#ifdef ARCH_T32 + codestream_gen(cs, 0x4770); +#elif defined(ARCH_A32) + codestream_gen(cs, 0xe12fff1e); +#elif defined(ARCH_A64) + codestream_gen(cs, 0xd65f03c0); +#elif defined(__x86_64__) + codestream_gen(cs, 0xC3); /* retq */ +#endif + expect_inst(cs, COUNT_BRANCH); + return 1; +} + + +int codestream_gen_ret_abi(CS *cs) +{ +#if defined(__x86_64__) + /* Argument in RDI, return in RAX */ + if (cs->metrics->n[COUNT_FLOP_DP] || cs->metrics->n[COUNT_FLOP_SP]) { + codestream_gen2(cs, 0x0F, 0x77); /* EMMS after using MMX instructions */ + expect_inst(cs, COUNT_INST); + } + codestream_gen3(cs, 0x48, 0x89, 0xF8); /* mov %rdi,%rax */ + expect_inst(cs, COUNT_MOVE); +#endif + return codestream_gen_ret(cs); +} + + + +#if defined(ARCH_T32) || defined(ARCH_A32) || defined(ARCH_A64) +static unsigned char const arm_cc[] = { + 0xe, /* AL */ + 0x0, /* EQ */ + 0x1, /* NE */ + 0x8, /* HI */ + 0x9, /* LS */ + 0x2, /* HS */ + 0x3, /* LO */ + 0xc, /* GT */ + 0xd, /* LE */ + 0xa, /* GE */ + 0xb, /* LT */ + 0x4, /* MI */ + 0x5, /* PL: positive or zero */ + 0x2, /* CS */ + 0x3, /* CC */ + 0x6, /* VS */ + 0x7 /* VC */ +}; +typedef int cc_size_check[1/(sizeof arm_cc == CC_MAX)]; +#elif defined(__x86_64__) +static unsigned char const x86_cc[] = { + 0xEB, /* j */ + 0x74, /* je */ + 0x75, /* jne */ + 0x77, /* ja (above) / jnbe */ + 0x76, /* jbe / jna */ + 0x73, /* jae / jnb */ + 0x72, /* jb (below) / jnae */ + 0x7F, /* jg (greater) */ + 0x7E, /* jle */ + 0x7D, /* jge */ + 0x7C, /* jl */ + 0x78, /* js (sign) */ + 0x79, /* jns (not sign) */ + 0x72, /* jc (carry) */ + 0x73, /* jnc (not carry) */ + 0x70, /* jo */ + 0x71 /* jno */ +}; +typedef int cc_size_check[1/(sizeof x86_cc == CC_MAX)]; +#else +#error Unsupported architecture +#endif + +int codestream_gen_branch(CS *cs, void *dest, cc_t cc) +{ + int disp; + /* Note that the pointer subtractions rely on code_t having the right size. */ +#ifdef ARCH_T32 + disp = ((code_t *)dest - (cs->p + 2)); + if (cc == CC_AL) { + // TBD should use Thumb2 long branch if displacement too large + codestream_gen(cs, 0xe000 + ((disp>>1) & 0x7ff)); + } else { + assert(0); // TBD + } +#elif defined(ARCH_A32) + disp = ((code_t *)dest - (cs->p + 2)); + codestream_gen(cs, 0x0a000000 + (arm_cc[cc] << 28) + (disp & 0x00ffffff)); +#elif defined(ARCH_A64) + disp = ((code_t *)dest - cs->p); + if (cc == CC_AL) { + codestream_gen(cs, 0x17000000 + (disp & 0x00ffffff)); + } else { + codestream_gen(cs, 0x54000000 + ((disp & 0x0007ffff) << 5) + arm_cc[cc]); + } +#elif defined(__x86_64__) + disp = ((code_t *)dest - (cs->p + 2)); + if (disp == (signed char)disp) { + unsigned char op = x86_cc[cc]; + assert(op != 0); + codestream_gen(cs, op); /* Short jump */ + codestream_gen(cs, (signed char)disp); + } else { + if (cc == CC_AL) { + disp -= 3; /* Adjust for instruction size difference */ + codestream_gen(cs, 0xE9); /* Near relative jump */ + } else { + disp -= 4; + codestream_gen(cs, 0x0F); /* Prefix */ + codestream_gen(cs, x86_cc[cc] + 0x10); /* 0x7x --> 0x8x */ + } + codestream_gen32(cs, disp); + } +#endif + expect_inst(cs, COUNT_BRANCH); + return 1; +} + + +/* + * Check there are enough consecutive bytes left in the current line + * for the instruction we're about to generate. If so, do nothing. + * If not, generate a branch to the next line if possible, otherwise + * report failure. + */ +int codestream_reserve(CS *cs, unsigned int bytes) +{ + unsigned int bytes_left = codestream_bytes_left(cs); + if (cs->error > 0) { + /* If we've previously reported an error on a stream, + indicate that we can't generate any more code. + This avoids us repeatedly trying to generate an + unavailable instruction. */ + return 0; + } else if (bytes_left >= bytes) { + return 1; + } else if (cs->line == cs->base) { + /* This was the last line */ + cs->ran_out_of_space = 1; + return 0; + } else { + /* Generate a branch to the previous line */ + unsigned char *dest = (cs->line - cs->line_size); + codestream_gen_branch(cs, dest, CC_AL); + codestream_start_line(cs, dest); + if (cs->line == cs->base) { + /* The last line might need a return epilogue - allow space */ + cs->line_reserve = 20; + } + assert(codestream_bytes_left(cs) >= bytes); + return 1; + } +} + + +/* + * Generate a data-processing operation, with up to four register operands. + * + * Return 0 if the operation cannot be done on this target, e.g. SIMD size unsupported. + * Assert if the request is badly formed on any target, e.g. too many registers for operation. + */ +int codestream_gen_op(CS *cs, unsigned int op, flavor_t flavor, freg_t Rd, freg_t Rx, freg_t Ry, freg_t Ra) +{ + unsigned int const esize_bits = FLOAT_BITS(flavor); + unsigned int const esize_bytes = esize_bits / 8; + int const is_simd = IS_SIMD(flavor); + unsigned int const simd_bytes = is_simd ? SIMD_SIZE(flavor) : 0; + assert(!is_simd || ((simd_bytes*8) >= esize_bits)); + unsigned int const simd_lanes = is_simd ? (simd_bytes / esize_bytes) : 1; + assert(esize_bits == 16 || esize_bits == 32 || esize_bits == 64); + + //fprintf(stderr, "op=%u flav=%u Rd=%d Rx=%d Ry=%d Ra=%d\n", op, flavor, Rd, Rx, Ry, Ra); + + assert(Rd != NR); + assert(Rx != NR); + if (op == FP_OP_MOV || op == FP_OP_NEG || op == FP_OP_SQRT) { + assert(Ry == NR); + } else { + assert(Ry != NR); + if (op == FP_OP_FMA) { + assert(Ra != NR); + } else { + assert(Ra == NR); + } + } + /* n.b. we don't reserve space in the code buffer here. */ +#if defined(ARCH_A64) + int is_bitwise_simd = (is_simd && (op == FP_OP_MOV || op == FP_OP_IXOR)); + unsigned int inst = 0xffffffff; + if (is_simd && cs->use_alternate) { + /* SVE instructions */ + static unsigned int const vinsts[] = { + 0x04603000, /* FMOV */ + 0x04200000, /* ADD */ + 0x04a03000, /* EOR */ + 0x041da000, /* FNEG (predicated) */ + 0x65000000, /* FADD */ + 0x65000800, /* FMUL */ + 0x650d8000, /* FDIV (predicated) */ + 0x650da000, /* FSQRT (predicated) */ + 0x65200000, /* FMLA (predicated) with Rd==Ra */ + }; + assert(op < (sizeof vinsts / sizeof vinsts[0])); + inst = vinsts[op]; + if (!inst) { + codestream_error(cs, "arm64: no SVE instruction for op %u", op); + return 0; + } + if (!is_bitwise_simd) { + if (esize_bits == 64) { + inst |= 0x00c00000; + } else if (esize_bits == 32) { + inst |= 0x00800000; + } + } + goto a64regs; + } + /* For NEON, we support 64-bit and 128-bit operations */ + if (is_simd && !(simd_bytes == 8 || simd_bytes == 16)) { + codestream_error(cs, "arm64: invalid SIMD size %u bytes", simd_bytes); + return 0; + } + /* AArch64 instruction templates */ + static unsigned int const insts[] = { + 0x1e204000, /* FMOV */ + 0, + 0, + 0x1e214000, /* FNEG */ + 0x1e202800, /* FADD */ + 0x1e200800, /* FMUL */ + 0x1e201800, /* FDIV */ + 0x1e21c000, /* FSQRT */ + 0x1f000000, /* FFMA */ + }; + static unsigned int const vinsts[] = { + 0x0ea01c00, /* FMOV (vector): alias of ORR */ + 0x0e208400, /* ADD (vector) */ + 0x2e201c00, /* EOR (vector) */ + 0x2ea0f800, /* FNEG (vector) */ + 0x0e20d400, /* FADD (vector) */ + 0x2e20dc00, /* FMUL (vector) */ + 0, /* no vector FDIV */ + 0, /* no vector FSQRT */ + 0x0e20cc00, /* FMLA (vector) */ + }; + assert(op < (sizeof insts / sizeof insts[0])); + inst = (is_simd ? vinsts[op] : insts[op]); + if (inst == 0) { + /* Something we can't do - e.g. vector DIV on ARM */ + codestream_error(cs, "no encoding for operation %u", op); + return 0; + } + if (is_simd && (esize_bytes == simd_bytes)) { + /* Single-element double-precision isn't really SIMD */ + codestream_error(cs, "can't do single-element SIMD"); + return 0; + } + if (simd_bytes == 16) { + inst |= 0x40000000; /* Set Q [30] */ + } + if (esize_bits == 64 && !is_bitwise_simd) { + inst |= 0x00400000; /* Set sz */ + } else if (esize_bits == 16 && !is_bitwise_simd) { + /* ARMv8.2 half-precision */ + inst ^= 0x0020c000; + } +a64regs: + /* Now add in the registers */ + inst |= (Rd << 0); /* Rd */ + switch (op) { + case FP_OP_ADD: + case FP_OP_MUL: + case FP_OP_DIV: + case FP_OP_IADD: + case FP_OP_IXOR: + /* for add, mul, div but not sqrt, there's a third operand */ + inst |= (Rx << 5) | (Ry << 16); + break; + case FP_OP_MOV: + if (is_simd) { + /* AArch64 MOV (vector) is an alias of ORR */ + inst |= (Rx << 16); + } + /* fall through */ + case FP_OP_NEG: + case FP_OP_SQRT: + inst |= (Rx << 5); /* SQRT has only one source operand */ + break; + case FP_OP_FMA: + /* for FMA scalar, there are four operands */ + if (is_simd && Rd != Ra) { + assert(Rd != Rx); + assert(Rd != Ry); + codestream_gen_op(cs, FP_OP_MOV, flavor, Rd, Ra, NR, NR); + } + inst |= (Rx << 5) | (Ry << 16); /* multiplier */ + if (!is_simd) { + inst |= (Ra << 10); /* accumulator input */ + } + break; + default: + assert(0); + } + codestream_gen(cs, inst); +#elif defined(__x86_64__) + if (esize_bits == 16) { + codestream_error(cs, "x86: can't do FP16"); + return 0; + } + int const is_dp = (esize_bits == 64); + int is_evex = (simd_bytes == 64); /* i.e. AVX512 */ + if (is_simd && !(simd_bytes == 16 || simd_bytes == 32 || simd_bytes == 64)) { + codestream_error(cs, "x86: invalid SIMD size %u bytes", simd_bytes); + return 0; + } + static unsigned char const inst[] = { + 0x28, /* mov */ + 0xfe, /* iadd */ + 0xef, /* ixor */ + 0x57, /* neg - actually xor */ + 0x58, /* add */ + 0x59, /* mul */ + 0x5e, /* div */ + 0x51, /* sqrt */ + 0xb9, /* fma */ + }; + assert(op < (sizeof inst / sizeof inst[0])); + if (is_evex) { + /* e.g. AVX512 */ + int const single_input = (op == FP_OP_SQRT || op == FP_OP_MOV); + unsigned char P1 = 0x01, P2 = 0x04, P3 = 0x00; + unsigned char opcode = inst[op]; + if (op == FP_OP_FMA && Rd != Ra) { + assert(Rd != Rx); + assert(Rd != Ry); + codestream_gen_op(cs, FP_OP_MOV, flavor, Rd, Ra, NR, NR); + } + P1 |= 0x70; + if (single_input) { + assert(Ry == NR); + Ry = Rx; + P2 |= 0x78; + P3 |= 0x08; + } else { + unsigned char nRx = Rx ^ 0x1f; + P2 |= ((nRx & 15) << 3); + P3 |= (((nRx & 0x10) >> 4) << 3); + } + if (op == FP_OP_FMA) { + P1 ^= 0x03; + P2 &= 0xfc; /* .66 */ + P2 |= 0x01; + if (is_dp) { + P2 |= 0x80; /* .W1 */ + } + opcode = 0x98; + } else { + if (!is_simd) { + P2 |= 0x02; + } + if (is_dp) { + P2 |= 0x81; + } + } + if (simd_bytes == 64) { + P3 |= 0x40; + } else if (simd_bytes == 32) { + P3 |= 0x20; + } + if (!single_input && (Ry & 8)) { + P1 &= 0xdf; + } + if (Rd & 8) { + P1 &= 0x7f; + } else { + P1 |= 0x80; + } + codestream_gen4(cs, 0x62, P1, P2, P3); + codestream_gen2(cs, opcode, (0xc0 | ((Rd & 7)<<3) | (Ry & 7))); + } else if (op == FP_OP_MOV || op == FP_OP_IADD || op == FP_OP_IXOR) { + /* copy Rx to Rd */ + if (esize_bits == 64 || op != FP_OP_MOV) { + codestream_gen(cs, 0x66); + } + if ((Rd & 8) || (Rx & 8)) { + unsigned char rex = 0x40; + if (Rd & 8) { + rex |= 0x04; + } + if (Rx & 8) { + rex |= 0x01; + } + codestream_gen(cs, rex); + } + codestream_gen3(cs, 0x0f, inst[op], (0xc0 | ((Rd & 7)<<3) | (Rx & 7))); + } else if (op == FP_OP_FMA) { + /* Intel processors only support FMA3 instruction set with Rd=Ra */ + unsigned char vex1, vex2, opcode; + freg_t Rda = Rd; + if (Rd != Ra) { + assert(Rd != Rx); + assert(Rd != Ry); + codestream_gen_op(cs, FP_OP_MOV, flavor, Rd, Ra, NR, NR); + } + codestream_gen(cs, 0xc4); /* 3-byte VEX prefix */ + vex1 = (Rda & 8) ? 0x62 : 0xe2; + if (Ry & 8) { + /* first operand */ + vex1 ^= 0x20; + } + codestream_gen(cs, vex1); + vex2 = (is_dp ? 0xf8 : 0x78); + vex2 ^= ((Rx & 0xf) << 3); + if (SIMD_SIZE(flavor) == 32) { + vex2 |= 0x04; + } + vex2 |= 0x01; + opcode = inst[op]; + if (is_simd) { + opcode &= 0xFE; + } + codestream_gen3(cs, vex2, opcode, (0xc0 | ((Rda & 7)<<3) | (Ry & 7))); + } else if (cs->use_alternate) { + /* old 2-operand style: addss, addsd, addpd etc. */ + if (Rd != Rx) { + codestream_gen_op(cs, FP_OP_MOV, flavor, Rd, Rx, NR, NR); + } + /* Add REX prefix if necessary */ + unsigned char rex = 0x40; + unsigned char pfx; + if (!is_simd) { + pfx = (is_dp ? 0xf2 : 0xf3); + } else { + pfx = (is_dp ? 0x66 : 0x00); + } + if (pfx != 0x00) { + codestream_gen(cs, pfx); + } + if (Rd & 8) { + rex |= 0x04; /* REX.R */ + } + if (Ry & 8) { + rex |= 0x01; /* REX.B */ + } + if (rex != 0x40) { + codestream_gen(cs, rex); + } + codestream_gen3(cs, 0x0f, inst[op], (0xc0 | ((Rd & 7)<<3) | (Rx & 7))); + } else { + /* new 3-operand style: vaddss, vaddsd etc. */ + /* Floating-point negation is not primitive in x86 */ + /* Compilers do it by XORing with -0.0 */ + /* Another way would be subtracting from 0.0 */ + /* For now, we just generate the VXORPS/D, which won't calculate the + right result, but gets the right performance if we had preloaded + constant -0.0 into a register. In case there's a special optimization + for XOR of a register with itself, we force XOR with another register. */ + unsigned char vex; + int const is_vex3 = ((Ry & 8) != 0); + int const single_input = (op == FP_OP_SQRT); + if (op == FP_OP_NEG) { + Ry = Rx ^ 1; /* see comment about defeating XOR optimization */ + } + if (single_input) { + Ry = Rx; + Rx = 0xCC; /* not to be used */ + } + codestream_gen(cs, (is_vex3 ? 0xc4 : 0xc5)); /* VEX prefix length */ + /* 2nd byte of 2-byte VEX prefix */ + /* 0x80: inverted REX.R */ + vex = 0; + if (!(Rd & 8)) { + vex |= 0x80; /* VEX.R = ~REX.R */ + } + if (is_vex3) { + vex |= 0x01; /* leading 0F, same as 2-byte VEX */ + vex |= 0x40; /* VEX.X = ~REX.X = 0 */ + if ((Ry & 8) == 0) { + vex |= 0x20; /* VEX.B = 1 */ + } + codestream_gen(cs, vex); + vex = 0; + } + /* Last or only byte of VEX prefix */ + /* Set VEX.L */ + if (SIMD_SIZE(flavor) == 32) { + vex |= 0x04; /* 256-bit vectors */ + } + /* Set VEX.pp */ + if (!(is_simd || op == FP_OP_NEG)) { + vex |= (is_dp ? 0x03 : 0x02); /* Implied prefix: DP:F2 vs. SP:F3 */ + } else { + vex |= (is_dp ? 0x01 : 0x00); /* Implied prefix: DP:66 vs. SP:none */ + } + /* register specifier in 1s-complement form */ + if (!single_input) { + vex |= ((Rx & 15) ^ 0xf) << 3; + } else { + /* single-input */ + vex |= (0xf << 3); + } + codestream_gen3(cs, vex, inst[op], (0xc0 | ((Rd & 7)<<3) | (Ry & 7))); + } +#else +#error Unsupported architecture +#endif + if (op == FP_OP_MOV) { + /* A register move doesn't count as a floating-point operation */ + expect_inst(cs, COUNT_MOVE); + } else { + unsigned int n = simd_lanes; + if (op == FP_OP_FMA) { + /* FMA counts as two FP operations */ + n *= 2; + } + expect_inst(cs, COUNT_INST); + expect_ops(cs, (esize_bits == 64) ? COUNT_FLOP_DP : (esize_bits == 16) ? COUNT_FLOP_HALF : COUNT_FLOP_SP, n); + } + return 1; +} + + +int codestream_gen_nop(CS *cs) +{ +#if defined(ARCH_A64) + codestream_gen(cs, 0xd503201f); +#elif defined(__x86_64__) + codestream_gen(cs, 0x90); +#else +#error Unsupported architecture +#endif + expect_inst(cs, COUNT_INST); + return 1; +} + + +#ifdef __x86_64__ +/* Map logical (argument index) reg no. to actual reg no. */ +static unsigned char reg_map(ireg_t r) +{ + /* Argument registers are RDI, RSI, RDX, RCX, R8, R9 */ + /* To use R8, R9 we'd need to use a prefix e.g. 0x41 */ + static unsigned char const reg_map_a[] = { + 0x7, /* RDI */ + 0x6, /* RSI */ + 0x2, /* RDX */ + 0x1, /* RCX */ + /* EAX is 0 */ + /* EBX is 3 */ + /* EBP is 5 */ + }; + assert(r < sizeof reg_map_a); + return reg_map_a[r]; +} +#endif + + +/* + * Decrement a register by 1 and set the Z flag. + */ +int codestream_gen_decs(CS *cs, ireg_t Rd) +{ + unsigned char k = 1; /* The constant */ +#if defined(ARCH_A64) + codestream_gen(cs, (0x71000000 | (k << 10) | (Rd << 5) | (Rd))); +#elif defined(__x86_64__) + if (Rd < 4) { + codestream_gen3(cs, 0x83, (0xe8 | reg_map(Rd)), k); + } else { + codestream_gen4(cs, 0x41, 0x83, (0xe8 | (Rd-4)), k); + } +#else +#error Unsupported architecture +#endif + expect_inst(cs, COUNT_INST); + return 1; +} + + +int codestream_gen_iopk(CS *cs, unsigned int iop, ireg_t Rd, ireg_t Rn, int k) +{ +#if defined(ARCH_A64) + unsigned int opcode = 0xBAD; + if (iop == CS_IOP_ADD) { + opcode = 0x91000000; + } else if (iop == CS_IOP_SUB) { + opcode = 0xd1000000; + } else { + assert(0); + } + codestream_gen(cs, (opcode | (k << 10) | (Rn << 5) | (Rd))); +#elif defined(__x86_64__) + assert(0); +#else +#error Unsupported architecture +#endif + expect_inst(cs, COUNT_INST); + return 1; +} + + +/* + * Load a register with an immediate value. + */ +int codestream_gen_movi32(CS *cs, ireg_t Rd, uint32_t n) +{ +#if defined(ARCH_A64) + /* On AArch64, constants must be done 16 bits at a time */ + codestream_gen(cs, 0xd2800000 | ((n & 0xffff) << 5) | Rd); + if (n >= 0x10000) { + n >>= 16; + /* MOVK into bits 31:16 */ + codestream_gen(cs, 0xf2a00000 | ((n & 0xffff) << 5) | Rd); + } +#elif defined(__x86_64__) + codestream_gen(cs, 0xb8 | reg_map(Rd)); + codestream_gen32(cs, n); +#else +#error Unsupported architecture +#endif + expect_inst(cs, COUNT_INST); + return 1; +} + + +/* + * Check if an immediate fits in a given signed/unsigned bit width. + */ +static int __attribute__((unused)) fits_simm(long x, unsigned int n_bits) +{ + return x >= (-1U << (n_bits-1)) && x < (1U << (n_bits-1)); +} + +static int __attribute__((unused)) fits_uimm(long x, unsigned int n_bits) +{ + return x >= 0 && x < (1U << n_bits); +} + + +/* To share code between load and store, we add an internal-only flag. */ +#define _internal_STORE 0x80000000 + +/* + * Generate a single load instruction. + * Will return zero if the requested combination of index register and offset can't be done. + */ +int codestream_gen_load(CS *cs, ireg_t Rt, ireg_t Rn, ireg_t Radd, int offset, unsigned int flags) +{ + assert((Rt == NR) == ((flags & CS_LOAD_PREFETCH) != 0)); +#if defined(ARCH_A64) + /* flags[0] set to 1 for STRM */ + /* flags[2:1] set to 00 for L1, 01 for L2, 10 for L3 */ + /* flags[4:3] set to 00 for LD, 01 for LI, 10 for ST */ + unsigned int prefetch_flags = 0; /* LOAD KEEP L1 */ + unsigned int flavor_flags = (flags & _internal_STORE) ? 0x00000000 : 0x00400000; + if (flags & CS_LOAD_NONTEMPORAL) { + prefetch_flags |= 0x01; + } + if (flags & _internal_STORE) { + prefetch_flags |= 0x10; + } + if ((flags & CS_LOAD_NONTEMPORAL) && !(flags & CS_LOAD_PREFETCH) && offset != 0) { + codestream_error(cs, "load offset invalid with non-temporal demand-load"); + return 0; + } + if ((flags & CS_LOAD_ATOMIC) && (offset != 0)) { + codestream_error(cs, "load offset invalid with atomic load"); + return 0; + } + if ((flags & CS_LOAD_ATOMIC) && (flags & CS_LOAD_NONTEMPORAL)) { + codestream_error(cs, "unsupported combination of atomic and non-temporal"); + return 0; + } + if ((flags & CS_LOAD_ACQUIRE) && (Radd != NR || offset != 0)) { + codestream_error(cs, "offset or index invalid with load-acquire/store-release"); + return 0; + } + if (Radd == NR) { + unsigned int opcode = 0x00000000; + if ((offset & 7) != 0 || !fits_uimm(offset>>3, 12)) { + codestream_error(cs, "load offset %ld is invalid", (long)offset); + return 0; + } + if (flags & CS_LOAD_PREFETCH) { + /* Store and non-temporality in prefetch_flags */ + opcode = (0xf9800000 | (Rn << 5) | ((offset>>3) << 10) | prefetch_flags); /* PRFM Rt,[Rn,#offset] */ + } else if (flags & CS_LOAD_NONTEMPORAL) { + if (flags & _internal_STORE) { + codestream_error(cs, "can't do non-temporal single-word store"); + return 0; + } + opcode = (0xa8400000 | (31 << 10) | (Rn << 5) | ((offset>>3) << 15) | Rt); /* LDNP Rt,xzr,[Rn,#offset] */ + } else if (flags & CS_LOAD_PAIR) { + if (flags & CS_LOAD_ACQUIRE) { + codestream_error(cs, "can't do pair load-acquire"); + return 0; + } + opcode = (0xa8c00000 | (31 << 10) | (Rn << 5) | ((offset>>3) << 15) | Rt); /* LDP Rt,xzr,[Rn,#offset] */ + } else if (flags & CS_LOAD_ATOMIC) { + opcode = (0xf8202000 | (0x1f << 16) | (Rn << 5) | Rt); /* LDEOR xzr,Rt,[Rn] */ + if (flags & CS_LOAD_ACQUIRE) { + opcode |= 0x00800000; + } + } else if (flags & CS_LOAD_ACQUIRE) { + /* Also CS_STORE_RELEASE: store done in flavor_flags */ + opcode = (0xc89ffc00 | flavor_flags | (Rn << 5) | Rt); /* LDAR Rt,[Rn] */ + } else { + opcode = (0xf9000000 | flavor_flags | (Rn << 5) | ((offset>>3) << 10) | Rt); /* LDR Rt,[Rn,#offset] */ + } + codestream_gen(cs, opcode); + } else { + if (offset != 0) { + codestream_error(cs, "cannot combine register and immediate offset"); + return 0; + } + if (flags & CS_LOAD_PREFETCH) { + /* Store and non-temporality in prefetch_flags */ + codestream_gen(cs, (0xf8a0c800 | (Rn << 5) | (Radd << 16) | prefetch_flags)); /* PRFM Rt,[Rn,Radd,sxtw] */ + } else { + codestream_gen(cs, (0xf860c800 | flavor_flags | (Rn << 5) | (Radd << 16) | Rt)); /* LDR Rt,[Rn,Radd,sxtw] */ + } + } +#elif defined(__x86_64__) + /* Argument registers are RDI, RSI, RDX, RCX, R8, R9 */ + assert(Rt == NR || Rt < sizeof reg_map); + assert(Rn < sizeof reg_map); + if (offset != 0) { + codestream_error(cs, "x86 load immediate offset TBD"); + return 0; /* TBD */ + } + if (Radd == NR) { + if (flags & CS_LOAD_PREFETCH) { + codestream_gen3(cs, 0x0f, 0x18, (0x08 | (reg_map(Rn)))); + } else { + codestream_gen3(cs, 0x48, 0x8b, ((reg_map(Rt) << 3) | (reg_map(Rn) << 0))); /* e.g. (%rdi),%rdi */ + } + } else { + /* e.g. mov %rdi,(%rdi+%rsi*1) */ + if (flags & CS_LOAD_PREFETCH) { + codestream_gen4(cs, 0x0f, 0x18, 0x0c, ((reg_map(Rn) << 3) | (reg_map(Radd) << 0))); + } else { + codestream_gen4(cs, 0x48, 0x8b, ((reg_map(Rt) << 3) | 0x04), ((reg_map(Rn) << 3) | (reg_map(Radd) << 0))); + } + } +#else +#error Unsupported architecture +#endif + expect_inst(cs, ((flags & CS_LOAD_PREFETCH) ? COUNT_MEM_PREFETCH : (flags & _internal_STORE) ? COUNT_INST_WR : COUNT_INST_RD)); + expect_ops(cs, ((flags & _internal_STORE) ? COUNT_BYTES_WR : COUNT_BYTES_RD), sizeof(void *)); + return 1; +} + + +int codestream_gen_store(CS *cs, ireg_t Rt, ireg_t Rn, ireg_t Radd, int offset, unsigned int flags) +{ + return codestream_gen_load(cs, Rt, Rn, Radd, offset, flags|_internal_STORE); +} + + +int codestream_gen_fp_load(CS *cs, flavor_t flavor, freg_t Rt, ireg_t Rn, int offset, unsigned int flags) +{ + assert(!(flags & CS_LOAD_PREFETCH)); +#if defined(ARCH_A64) + unsigned int xflags = (flags & _internal_STORE) ? 0x00000000 : 0x00400000; + uint32_t opcode = 0xbd000000 | xflags | (offset << 10) | (Rn << 5) | (Rt << 0); + unsigned int const esize_bits = FLOAT_BITS(flavor); + if (esize_bits == 64) { + opcode |= 0x40000000; /* 0xbd...... -> 0xfd...... */ + } + assert(offset >= 0 && offset <= 64); + codestream_gen(cs, opcode); +#elif defined(__x86_64__) + fprintf(stderr, "x86: FP load/store not implemented\n"); + return 0; +#else +#error Unsupported architecture +#endif + expect_inst(cs, ((flags & _internal_STORE) ? COUNT_INST_WR : COUNT_INST_RD)); + expect_ops(cs, ((flags & _internal_STORE) ? COUNT_BYTES_WR : COUNT_BYTES_RD), esize_bits / 8); + return 1; +} + + +int codestream_gen_fp_store(CS *cs, flavor_t flavor, freg_t Rt, ireg_t Rn, int offset, unsigned int flags) +{ + return codestream_gen_fp_load(cs, flavor, Rt, Rn, offset, flags|_internal_STORE); +} + + +int codestream_gen_fence(CS *cs, unsigned int flags) +{ + assert((flags & (CS_FENCE_STORE|CS_FENCE_LOAD)) != 0); +#if defined(ARCH_A64) + unsigned int opcode = 0xd50338bf; /* DMB ISH */ + if (flags & CS_FENCE_LOAD) { + opcode |= 0x00000100; + } + if (flags & CS_FENCE_STORE) { + opcode |= 0x00000200; + } + if (flags & CS_FENCE_SYSTEM) { + opcode |= 0x00000400; /* change ISH to SY */ + } + if (flags & CS_FENCE_SYNC) { + opcode &= ~0x00000020; /* change DMB to DSB */ + } + codestream_gen(cs, opcode); +#elif defined(__x86_64__) + unsigned int const lsflags = flags & (CS_FENCE_STORE|CS_FENCE_LOAD); + /* TBD: not sure I understand x86 fences. Useful exposition at + https://hadibrais.wordpress.com/2018/05/14/the-significance-of-the-x86-lfence-instruction/ */ + if (lsflags == CS_FENCE_LOAD) { + codestream_gen3(cs, 0x0F, 0xAE, 0xE8); /* LFENCE */ + } else if (flags == CS_FENCE_STORE) { + codestream_gen3(cs, 0x0F, 0xAE, 0xF8); /* SFENCE */ + } else if (lsflags == (CS_FENCE_STORE|CS_FENCE_LOAD)) { + codestream_gen3(cs, 0x0F, 0xAE, 0xF0); /* MFENCE */ + } +#endif + expect_inst(cs, COUNT_FENCE); + return 1; +} + diff --git a/linux_app/pmu_app/pysweep/src/loadinst.h b/linux_app/pmu_app/pysweep/src/loadinst.h new file mode 100644 index 00000000..e367731d --- /dev/null +++ b/linux_app/pmu_app/pysweep/src/loadinst.h @@ -0,0 +1,202 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +/* + * Generate instructions in memory. + * + * This is a set of general-purpose routines suitable for JITting code. + */ + +#ifndef __included_loadinst_h +#define __included_loadinst_h + +#include "arch.h" + +#include +#include + + +typedef struct codestream CS; + + +/* Code stream management */ + +void codestream_show(CS const *); + +struct inst_counters; + +CS *codestream_init(struct inst_counters *m, void *base, size_t size, unsigned int line_size); + +void *codestream_addr(CS const *); + +void codestream_use_alternate(CS *); + +void codestream_set_multiplier(CS *, int); + +/* Push and pop a multiple, e.g. when looping by a fixed amount */ +int codestream_push_multiplier(CS *, int); +int codestream_pop_multiplier(CS *, int); + +int codestream_errors(CS const *); + +void codestream_free(CS *); + +/* + * Check there are enough consecutive bytes left in the current line + * for the instruction we're about to generate. If so, do nothing. + * If not, generate a branch to the next line if possible, otherwise + * report failure. + */ +int codestream_reserve(CS *, unsigned int bytes); + + +/* Instruction generators */ + +typedef unsigned int ireg_t; +/* Integer argument registers */ +#define IR0 0 +#define IR1 1 +#define IR2 2 +#define IR3 3 +#define IR4 4 +#define IR5 5 + +typedef unsigned int freg_t; +#define NR 0xFF /* no register - placeholder for instructions with less than max no. of regs */ + +/* + * We define various 'flavors' of FP/SIMD operation. + */ +typedef unsigned int flavor_t; +#define F16 0x01 +#define F32 0x02 +#define F64 0x03 +#define S64 0x08 +#define S128 0x10 /* 16 bytes */ +#define S256 0x20 /* 32 bytes */ +#define S512 0x40 /* 64 bytes */ +#define S1024 0x80 /* 128 bytes */ + +#define FLOAT_BITS(t) (8U << ((t) & 0x03)) +#define SIMD_SIZE(t) ((t) & 0xff8) +#define IS_SIMD(t) (((t) & 0xff8) != 0) + + +/* + * Move an immediate value into a register, or return 0 if not possible in one instruction. + */ +int codestream_gen_movi32(CS *, ireg_t Rd, uint32_t n); + +/* + * Decrement an integer register and set the Z flag. + */ +int codestream_gen_decs(CS *, ireg_t Rd); + +/* + * Integer operation + */ +#define CS_IOP_ADD 0 +#define CS_IOP_SUB 1 +int codestream_gen_iopk(CS *, unsigned int iop, ireg_t Rd, ireg_t Rn, int k); + +/* + * Floating-point (or vector) operation on floating-point/vector registers. + */ +int codestream_gen_op(CS *, unsigned int op, flavor_t flavor, freg_t Rd, freg_t Rx, freg_t Ry, freg_t Ra); + +/* + * Generate a load: + * Rt = *(Rn + Radd + offset). + * Radd may be NR. + */ +#define CS_LOAD_DEFAULT 0x00 +#define CS_LOAD_NONTEMPORAL 0x01 /* Use a non-temporal (streaming) load */ +#define CS_LOAD_PAIR 0x02 /* Use a load-pair instruction */ +#define CS_LOAD_PREFETCH 0x04 /* Generate a prefetch instead of a load (Rt==NR) */ +#define CS_LOAD_ACQUIRE 0x08 /* Use load-acquire if available */ +#define CS_LOAD_ATOMIC 0x10 /* Use a load-atomic */ +int codestream_gen_load(CS *, ireg_t Rt, ireg_t Rn, ireg_t Radd, int offset, unsigned int flags); + +int codestream_gen_fp_load(CS *, flavor_t flavor, freg_t Rt, ireg_t Rn, int offset, unsigned int flags); + + +/* + * Generate a store. This has similar constraints as load. + */ +#define CS_STORE_DEFAULT 0x00 +#define CS_STORE_NONTEMPORAL 0x01 +#define CS_STORE_RELEASE 0x08 +int codestream_gen_store(CS *, ireg_t Rt, ireg_t Rn, ireg_t Radd, int offset, unsigned int flags); + +int codestream_gen_fp_store(CS *, flavor_t flavor, freg_t Rt, ireg_t Rn, int offset, unsigned int flags); + +/* Generate an explicit barrier/fence instruction */ +#define CS_FENCE_LOAD 0x01 +#define CS_FENCE_STORE 0x02 +#define CS_FENCE_SYSTEM 0x04 /* Domain: on Arm, use SY instead of ISH */ +#define CS_FENCE_SYNC 0x08 /* Synchronize: on Arm, use DSB instead of DMB */ +int codestream_gen_fence(CS *, unsigned int flags); + +int codestream_gen_nop(CS *); + +int codestream_gen_call(CS *, void *dest); + +int codestream_gen_ret(CS *); + +int codestream_gen_ret_abi(CS *); + +/* + * Generate an instruction or part of an instruction directly. Specialist use only. + */ +void codestream_gen_direct(CS *, unsigned int x); + + +/* + * Condition encodings. Several abstract conditions might have the same encoding, + * but this is different for different ISAs. E.g. "unsigned less than" + * is the same as "carry set" for x86, but "carry clear" for ARM. + * + * N.b. tables in loadinst.c are indexed by this enum. Keep in sync. + */ +typedef enum { + CC_AL, + CC_EQ, + CC_NE, + CC_UGT, + CC_ULE, + CC_UGE, + CC_ULT, + CC_SGT, + CC_SLE, + CC_SGE, + CC_SLT, + CC_NEG, + CC_NNG, + CC_CS, + CC_CC, + CC_VS, + CC_VC, + CC_MAX +} cc_t; + +int codestream_gen_branch(CS *, void *dest, cc_t cc); + + + +#endif /* included */ + +/* end of loadinst.h */ diff --git a/linux_app/pmu_app/pysweep/src/prepcode.c b/linux_app/pmu_app/pysweep/src/prepcode.c new file mode 100644 index 00000000..880d0744 --- /dev/null +++ b/linux_app/pmu_app/pysweep/src/prepcode.c @@ -0,0 +1,160 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ +/* +Given a block of machine code, generated elsewhere, prepare it for execution. + +Platform-specific functions are used for cache unification etc. +*/ + +#include "prepcode.h" + +#include "arch.h" + +#include +#include +#include /* for perror */ +#include + + +#ifdef ARCH_ARM +//#if defined(__ARMEL__) +//#include +extern void __clear_cache(char *beg, char *end); +//#endif + +int cacheflush(char *p, int s, int flag) +{ + __clear_cache(p, p+s); + return 0; +} +#define BCACHE 3 +#endif + +#define GDB_JIT +#ifdef GDB_JIT +typedef enum { + JIT_NOACTION = 0, + JIT_REGISTER_FN, + JIT_UNREGISTER_FN +} jit_actions_t; + +struct jit_code_entry { + struct jit_code_entry *next_entry; + struct jit_code_entry *prev_entry; + char const *symfile_addr; /* sic - not an 'unsigned char *' */ + unsigned long long symfile_size; +}; + +struct jit_descriptor { + unsigned int version; + unsigned int action_flag; + struct jit_code_entry *relevant_entry; + struct jit_code_entry *first_entry; +}; + +struct jit_descriptor __jit_debug_descriptor = {1,0,0,0}; + +void __attribute__((noinline)) __jit_debug_register_code() {} +#endif /* GDB_JIT */ + + +int prepare_code_protection(void const *p, size_t size) +{ + assert(((unsigned long)p & (sysconf(_SC_PAGESIZE)-1)) == 0); + assert((size & (sysconf(_SC_PAGESIZE)-1)) == 0); + if (0 > mprotect((void *)p, size, PROT_READ|PROT_EXEC)) { + perror("mprotect"); + fprintf(stderr, "prepcode: failed to mark %p size %#lx as executable\n", + p, (unsigned long)size); + return -1; + } + return 0; +} + + +int prepare_code_coherence(void const *p, size_t size) +{ +#ifdef ARCH_ARM + if (0 > cacheflush((char *)p, size, BCACHE)) { + perror("cacheflush"); + return -1; + } +#else + /* On other platforms, the D-cache and I-cache are coherent */ +#endif + return 0; +} + + +static struct jit_code_entry the_entry = {NULL, NULL, NULL, 0}; + + +int prepare_code_elf(void const *p, size_t size, unsigned int flags, void const *elf, size_t elf_size) +{ + int rc; + assert(p != NULL); + if (flags & PREPCODE_DEBUGGER) { +#ifdef GDB_JIT + /* TBD - we should support several descriptors active */ + the_entry.symfile_addr = (char *)elf; + the_entry.symfile_size = elf_size; + __jit_debug_descriptor.action_flag = JIT_REGISTER_FN; + __jit_debug_descriptor.relevant_entry = &the_entry; + __jit_debug_descriptor.first_entry = &the_entry; + __jit_debug_register_code(); + /* We need to call this again when we've finished with the code buffer */ +#endif /* GDB_JIT */ + } + if (flags & PREPCODE_PROTECT) { + rc = prepare_code_protection(p, size); + if (rc) { + return rc; + } + } + if ((flags & PREPCODE_COHERENCE) && !(flags & PREPCODE_PROTECT)) { + /* If we've done mprotect() above, we believe we don't have to do + a userspace cache-unification sequence as well. */ + rc = prepare_code_coherence(p, size); + if (rc) { + return rc; + } + } + return 0; +} + + +int prepare_code(void const *p, size_t size, unsigned int flags) +{ + return prepare_code_elf(p, size, flags, NULL, 0); +} + + +int unprepare_code(void const *p, size_t size, unsigned int flags) +{ + if (flags & PREPCODE_DEBUGGER) { +#ifdef GDB_JIT + /* TBD - we might have several descriptors active */ + __jit_debug_descriptor.action_flag = JIT_UNREGISTER_FN; + __jit_debug_register_code(); +#endif /* GDB_JIT */ + } + return 0; +} + + +/* end of prepcode.c */ + diff --git a/linux_app/pmu_app/pysweep/src/prepcode.h b/linux_app/pmu_app/pysweep/src/prepcode.h new file mode 100644 index 00000000..83aecd5f --- /dev/null +++ b/linux_app/pmu_app/pysweep/src/prepcode.h @@ -0,0 +1,47 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ +/* + * Prepare code block for execution + * + * This might involve changing memory protection, synchronizing cache etc. + */ + +#ifndef __included_prepcode_h +#define __included_prepcode_h + +#include + +/* + * Do all necessary prep for executing a block of data as code. + */ +#define PREPCODE_PROTECT 1 +#define PREPCODE_COHERENCE 2 +#define PREPCODE_DEBUGGER 4 /* Notify debugger about new code */ +#define PREPCODE_ALL 0xff +int prepare_code(void const *, size_t size, unsigned int flags); +int prepare_code_elf(void const *, size_t size, unsigned int flags, void const *elf, size_t elf_size); + +int unprepare_code(void const *, size_t size, unsigned int flags); + +/* Just change protection (if needed) */ +int prepare_code_protection(void const *, size_t size); + +/* Just ensure coherence (if needed) */ +int prepare_code_coherence(void const *, size_t size); + +#endif /* included */ + diff --git a/linux_app/pmu_app/pysweep/src/pysweep.c b/linux_app/pmu_app/pysweep/src/pysweep.c new file mode 100644 index 00000000..cc857ff7 --- /dev/null +++ b/linux_app/pmu_app/pysweep/src/pysweep.c @@ -0,0 +1,1341 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +/* + * Python module to generate artificial loads. + */ + +/* + * The main object created by this module is an object of type Load. + * + * load = pyperf.create(spec) + * load.start() + * load.update(new_spec) + * load.stop() + * + * Internally, some worker threads are created, which all run the workload. + * (If you want to have threads running different workloads, then just create + * multiple Load objects.) + * + * As seen above, the characteristics of a workload can be dynamically updated + * while the workload is running. How this is achieved is described in a + * comment below. + */ + + +#ifndef MODULE_NAME +#define MODULE_NAME pysweep +#endif /* !MODULE_NAME */ + +#include +#if PY_MAJOR_VERSION < 3 +#define PyBytes_FromStringAndSize PyString_FromStringAndSize +#else +#define PyString_FromFormat PyUnicode_FromFormat +#define PyInt_FromLong PyLong_FromLong +#define PyInt_AsLong PyLong_AsLong +#define PyInt_Check PyLong_Check +#define PyInt_AsUnsignedLongLongMask PyLong_AsUnsignedLongLongMask +#endif + + +#include "loadgen.h" +#include "loadgenp.h" /* for diagnostics and benchmarking */ +#include "prepcode.h" +#include "sleep.h" +#include "branch_prediction.h" +#include "arch.h" + +#ifndef _GNU_SOURCE +#define _GNU_SOURCE +#endif /* _GNU_SOURCE */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#define MODULE_NAME_STRING3(m) #m +#define MODULE_NAME_STRING2(m) MODULE_NAME_STRING3(m) +#define MODULE_NAME_STRING MODULE_NAME_STRING2(MODULE_NAME) + +extern int workload_verbose; + + +/* +Dynamically updating workloads. + +Internally, workloads use the workload object managed by "loadgen.h". +A workload consists of a code sequence which can be executed repeatedly. +After each repetition we might take some other action. + +We want to be able to dynamically change the characteristics of a workload +while it's running - not just changing scheduling/pinning of the worker threads, +but changing the code they are executing. We want to free up any resources +used by the old workload, but not while it's still running. + +We could do this in different ways: + + - keep the worker threads running, but have them switch to a new load object + if available at the end of an iteration. Ensure that an old load object + is cleaned up when no longer needed. + + - cancel the worker threads (pthread_cancel). Create new threads. + Disadvantage: any external monitoring, such as perf events, that is tied + to the worker threads, would have to be set up for the new threads. +*/ + + +typedef struct load_thread load_thread_t; +typedef struct load_thread_local load_thread_local_t; + + +/* + * pysweep.Load: a Python object representing a workload that we can + * dynamically vary and which has one or more workload execution + * threads associated with it. + */ +typedef struct { + PyObject_HEAD + unsigned int n_threads; /* Number of threads requested */ + /* The workload itself - executable code and its characteristics. + This is a central copy of the pointer. The threads each have + their own pointer to the workload, which they will monitor + for changes. */ + Workload *work; /* Workload as created by loadgen.c */ + load_thread_t *first_thread; /* List of execution threads */ + unsigned int suspend_reasons; /* Supension reason(s) */ +#define SUSPEND_REQUEST 0x01 /* Suspended because requested to be suspended */ +#define SUSPEND_ZEROAFF 0x02 /* Suspended because pinned to the empty set of threads */ +#define SUSPEND_BADWORK 0x04 /* Suspended because couldn't create workload */ + pthread_attr_t thread_attr; /* Default thread attributes (including affinity) */ +} LoadObject; + + +/* + * Description for a workload executor thread. + * Always on the thread list of its owning LoadObject. + * The expectation is that this is mostly unchanging and can live + * as a shared copy in the worker's and master's caches. + */ +struct load_thread { + PyObject_HEAD + struct load_thread *next_thread; + LoadObject *load; /* Point back to the load */ + pthread_t pthread_id; /* The pthread thread id, not the OS thread id */ + pid_t os_tid; /* OS tid, as used for e.g. perf_event_open */ + sem_t sem_started; /* Thread has started and OS tid is available */ + sem_t sem_worktodo; /* Contoller signals thread that there is work to do */ + load_thread_local_t volatile *loc; /* Local, rapidly changing data */ +}; + +typedef load_thread_t ThreadObject; +static PyTypeObject ThreadType; + + +/* + * Local data for a thread. The intention is that this has + * rapidly changing data and will live as an exclusive copy in the + * worker's cache. + */ +struct load_thread_local { + struct load_thread *thread; /* Point back to the thread */ + Workload *volatile vol_work; /* Copy of the workload - NULL if nothing to run */ + unsigned int volatile n_iters;/* Number of times through this workload */ +}; + + +/* + * Some distributions provide a gettid(), others don't. + */ +static pid_t _private_gettid(void) +{ + return (pid_t)syscall(SYS_gettid); +} + +#undef gettid +#define gettid() _private_gettid() + + +static PyObject *load_new(PyTypeObject *t, PyObject *args, PyObject *kwds) +{ + LoadObject *p = (LoadObject *)t->tp_alloc(t, 0); + assert(p != NULL); + p->n_threads = 1; + p->first_thread = NULL; + p->suspend_reasons = 0; + p->work = NULL; + pthread_attr_init(&p->thread_attr); + return (PyObject *)p; +} + + +/* +Given a Python dictionary object of characteristics, update a loadgen +characteristics structure. +Return -1 if unsuccessful. +*/ +static int update_field_long(unsigned long *field, PyObject *spec, char *name) +{ + PyObject *oval = PyDict_GetItemString(spec, name); + if (oval == Py_None) { + /* The value might be 'None'. Should we treat this as + the field not being present? (TBD) */ + /* ignore */ + } else if (oval) { + /* To avoid a DeprecationWarning, check for float and use a different converter */ + if (PyFloat_Check(oval)) { + double d = PyFloat_AsDouble(oval); + if (d < 0) { + PyErr_SetString(PyExc_ValueError, "parameter must be non-negative"); + return -1; + } + *field = (unsigned long)d; + } else { + *field = PyInt_AsLong(oval); + } + if (PyErr_Occurred()) { + return -1; + } + } else { + /* ignore if value not supplied - not an error */ + } + return 0; +} + + +static int update_field_int(unsigned int *field, PyObject *spec, char *name) +{ + unsigned long lfield = *field; + int rc = update_field_long(&lfield, spec, name); + *field = lfield; + return rc; +} + + +static int update_field_float(double *field, PyObject *spec, char *name) +{ + PyObject *oval = PyDict_GetItemString(spec, name); + if (oval) { + *field = PyFloat_AsDouble(oval); + if (PyErr_Occurred()) { + return -1; + } + } + return 0; +} + + +/* +Given a Python map containing workload attributes, +populate fields in a Character object. Fields that aren't +mentioned in the input map are not affected. +*/ +static int setup_char(PyObject *spec, Character *c) +{ + int rc; + /* The working set sizes are 64-bit */ + rc = update_field_long(&c->inst_working_set, spec, "inst"); + if (rc) return rc; + rc = update_field_long(&c->data_working_set, spec, "data"); + if (rc) return rc; + /* Remaining fields control aspects of the workload */ + rc = update_field_int(&c->workload_flags, spec, "flags"); + if (rc) return rc; + rc = update_field_int(&c->debug_flags, spec, "debug_flags"); + if (rc) return rc; + rc = update_field_long(&c->inst_target, spec, "inst_target"); + if (rc) return rc; + rc = update_field_int(&c->data_pointer_offset, spec, "data_pointer_offset"); + if (rc) return rc; + rc = update_field_int(&c->data_dispersion, spec, "data_dispersion"); + if (rc) return rc; + rc = update_field_int(&c->data_alignment, spec, "data_alignment"); + if (rc) return rc; + rc = update_field_int(&c->fp_intensity, spec, "fp_intensity"); + if (rc) return rc; + rc = update_field_int(&c->fp_operation, spec, "fp_operation"); + if (rc) return rc; + rc = update_field_int(&c->fp_precision, spec, "fp_precision"); + if (rc) return rc; + rc = update_field_int(&c->fp_concurrency, spec, "fp_concurrency"); + if (rc) return rc; + rc = update_field_int(&c->fp_simd, spec, "fp_simd"); + if (rc) return rc; + rc = update_field_int(&c->fp_flags, spec, "fp_flags"); + if (rc) return rc; + rc = update_field_float(&c->fp_value, spec, "fp_value1"); + if (rc) return rc; + rc = update_field_float(&c->fp_value2, spec, "fp_value2"); + if (rc) return rc; + /* Force the instruction working set to a suitable minimum? */ +#define MINIMUM_INST_WORKING_SET 64 + if (c->inst_working_set < MINIMUM_INST_WORKING_SET) { + c->inst_working_set = MINIMUM_INST_WORKING_SET; + } + return 0; +} + + +/* +Instance initialization function. Called when a Load object is created: + + w = Load(...) + +Should return 0 on success and -1 on error (see Python issue 17380). +*/ +static int load_init(PyObject *x, PyObject *args, PyObject *kwds) +{ + LoadObject *p = (LoadObject *)x; + PyObject *spec = NULL; + static char *keys[] = { "spec", "threads", "verbose", NULL }; + int verbose = 0; + int n_threads = p->n_threads; /* load_new will have defaulted this to 1 */ + Character c; + /* The default workload characteristics have no data and no FP operations. + setup_char() will default the code working set to at least 1024 bytes. */ + workload_init(&c); + + if (!PyArg_ParseTupleAndKeywords(args, kwds, "O|ii", keys, &spec, &n_threads, &verbose)) { + return -1; + } + assert(spec != NULL); + + if (setup_char(spec, &c) < 0) { + return -1; + } + + if (n_threads <= 0) { + return -1; + } + p->n_threads = n_threads; + + if (verbose) { + workload_verbose = verbose; + fprintf(stderr, "pysweep: setting verbosity level to %d\n", verbose); + } + assert(p->work == NULL); + p->work = workload_create(&c); + if (p->work == NULL) { + PyErr_SetString(PyExc_RuntimeError, "load could not be created"); + return -1; + } + if (workload_verbose) { + fprintf(stderr, "pysweep: %p: workload created\n", p->work); + } + assert(p->work != NULL); + if (0) { + /* Run the workload once on the current thread, as a check */ + /* This might trap with SIGILL if we've generated an invalid instruction */ + if (workload_verbose) { + fprintf(stderr, "pysweep: %p: run once...\n", p->work); + } + workload_run_once(p->work); + if (workload_verbose) { + fprintf(stderr, "pysweep: finished running workload once.\n"); + } + } + return 0; +} + + +#define BENCH_NO_TRIAL 0x8000 +#define BENCH_MMAP 0x4000 +#define BENCH_CODE 0x2000 + + +static PyObject *gfn_bench(PyObject *x, PyObject *args) +{ + int n_iters, flags; + PyObject *spec = NULL; + Character c; + int i; + if (!PyArg_ParseTuple(args, "Oii", &spec, &n_iters, &flags)) { + return NULL; + } + workload_init(&c); + if (setup_char(spec, &c) < 0) { + return NULL; + } + flags |= c.debug_flags; + if (flags & BENCH_MMAP) { + /* Just mmap/munmap */ + unsigned long map_size = sysconf(_SC_PAGESIZE); + unsigned int prot = PROT_READ|PROT_WRITE; + if (flags & BENCH_CODE) { + prot |= PROT_EXEC; + } + if (workload_verbose) { + fprintf(stderr, "pysweep: benchmark mmap size %lu prot %#x\n", map_size, prot); + } + for (i = 0; i < n_iters; ++i) { + void *p = mmap(NULL, map_size, prot, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0); + assert(p != MAP_FAILED); + munmap(p, map_size); + } + } else if (flags & BENCH_CODE) { + /* Just coherency */ + unsigned int code_size = c.inst_working_set; + unsigned long map_size = round_size(code_size, sysconf(_SC_PAGESIZE)); + void *p; + if (workload_verbose) { + fprintf(stderr, "pysweep: benchmark coherence size %u\n", code_size); + } + p = mmap(NULL, map_size, PROT_READ|PROT_WRITE|PROT_EXEC, MAP_PRIVATE|MAP_ANONYMOUS, -1, 0); + for (i = 0; i < n_iters; ++i) { + memset(p, (unsigned char)i, code_size); + prepare_code(p, code_size, (PREPCODE_ALL & ~PREPCODE_PROTECT)); + } + munmap(p, map_size); + } else for (i = 0; i < n_iters; ++i) { + Workload *w = workload_create(&c); + if (w == NULL) { + PyErr_SetString(PyExc_RuntimeError, "load could not be created"); + return NULL; + } + if (!(flags & BENCH_NO_TRIAL)) { + workload_run_once(w); + } + workload_free(w); + } + Py_RETURN_NONE; +} + + +static PyObject *gfn_debug(PyObject *x, PyObject *args) +{ + int flags; + if (!PyArg_ParseTuple(args, "i", &flags)) { + return NULL; + } + workload_verbose = flags; + fprintf(stderr, "pysweep: set diagnostic level to %u\n", workload_verbose); + Py_RETURN_NONE; +} + + +#ifdef ARCH_AARCH64 +static unsigned long long get_ctr(void) +{ + unsigned long ctr; + __asm__ __volatile__("mrs %0,ctr_el0":"=r"(ctr)::); + return ctr; +} + +static PyObject *gfn_ctr(PyObject *x) +{ + return PyInt_FromLong(get_ctr()); +} +#endif /* ARCH_AARCH64 */ + + +/* + * Sleep for a given amount of time, handling EINTR. + */ +static PyObject *gfn_sleep(PyObject *x, PyObject *args) +{ + int n_wait; + double t; + if (!PyArg_ParseTuple(args, "d", &t)) { + return NULL; + } + n_wait = microsleep(t); + return PyInt_FromLong(n_wait); +} + +/* + * Branch prediction code gen + */ +static PyObject *gfn_br_pred(PyObject *x, PyObject *args) +{ + int s; + int ret; + + if (!PyArg_ParseTuple(args, "i", &s)) { + return NULL; + } + ret = branch_load_gen(s); + return PyInt_FromLong(ret); +} + + +/* +Thread 'main' function for the worker threads. +*/ +static void *thread_start(void *ltv) +{ + load_thread_t *const lt = (load_thread_t *)ltv; + load_thread_local_t volatile *const loc = lt->loc; + LoadObject const *const lob = lt->load; + Workload *last_work = NULL; + void *work_data = NULL; + int otype; + /* The tid of this worker thread can be used to control it and also appears + in diagnostic messages. */ + lt->os_tid = gettid(); + /* Allow the thread to be cancelled immediately without waiting until it + encounters a system call. */ + pthread_setcanceltype(PTHREAD_CANCEL_ASYNCHRONOUS, &otype); + /* We are good to go and can signal the parent to return to its caller. */ + sem_post(<->sem_started); + /* Wait for the controller thread to release us */ + sem_wait(<->sem_worktodo); + /* This loop runs continually, even while the workload is being updated. */ + for (;;) { + /* The workload code doesn't take long, so we iterate it several times + in order to get a suitable chunk of work, after which we can check + for new work. To avoid resonance with working set sizes etc., + pick a prime number. */ + const unsigned int N_ITERS = 1; /* or 3, 117 etc. */ + /* Each iteration, we load whatever the workload is, and then run it. + The workload might have changed since last time! */ + Workload *work = loc->vol_work; + if (__builtin_expect(work != last_work, 0) || work == NULL) { + /* Workload has been changed! */ + if (last_work != NULL) { + if (workload_verbose) { + fprintf(stderr, "pysweep: [W %u] workload changed from %p to %p!\n", (unsigned int)lt->os_tid, last_work, work); + } + workload_remove_reference(last_work); + } + /* If we try to update the workload to a new specification + and fail, workload_create() will be null. There's no + point asking the executor threads to keep executing + so we hope the caller will have suspended us. */ + while (work == NULL) { + /* Wait for master to give us some work again */ + if (workload_verbose) { + fprintf(stderr, "pysweep: [W %u] waiting for work...\n", (unsigned int)lt->os_tid); + } + sem_wait(<->sem_worktodo); + if (workload_verbose) { + fprintf(stderr, "pysweep: [W %u] resumed (suspend=%#x)\n", (unsigned int)lt->os_tid, lob->suspend_reasons); + } + work = loc->vol_work; + } + work_data = work->entry_args[0]; /* Reset - including first time round */ + if (workload_verbose) { + /* Report that the workload for the worker threads changed. */ + fprintf(stderr, "pysweep: [W %u] workload updated to code=%p with argument data=%p\n", + (unsigned int)lt->os_tid, work, work_data); + } + last_work = work; + } + if (0 && workload_verbose) { + unsigned int const n_steps = N_ITERS * work->n_chain_steps; + printf(" run %p for %u iters, %u steps, touched %#x\n", + work_data, N_ITERS, n_steps, n_steps*64); + } + assert(work != NULL); + work_data = workload_run(work, work_data, N_ITERS); + /* Update iteration count for this thread */ + loc->n_iters += N_ITERS; + /* TBD: should we put a memory fence here to flush the store? */ + } + /* Don't expect to get here? */ + return NULL; +} + + +static PyObject *thread_new(PyTypeObject *ot, PyObject *args, PyObject *kwds) +{ + ThreadObject *t = (ThreadObject *)ot->tp_alloc(ot, 0); + return (PyObject *)t; +} + + +/* + * Update all threads' local copy of the workload. + * This might be called with NULL, to temporarily stop a thread + * working on anything. + */ +static void load_update_thread_work(LoadObject *p, Workload *w) +{ + load_thread_t *t; + for (t = p->first_thread; t != NULL; t = t->next_thread) { + int was_null = (t->loc->vol_work == NULL); + if (w != NULL) { + workload_add_reference(w); + } + t->loc->vol_work = w; + if (w != NULL && was_null) { + sem_post(&t->sem_worktodo); + } + } +} + + +/* + * Create the worker threads for the load, using pthread_create(). + */ +static PyObject *load_start(PyObject *x) +{ + LoadObject *p = (LoadObject *)x; + unsigned int i; + assert(p->n_threads > 0); + if (p->first_thread != NULL) { + /* Load is already started */ + PyErr_SetString(PyExc_RuntimeError, "load is already started"); + return NULL; + } + if (workload_verbose) { + fprintf(stderr, "pysweep: starting workload %p...\n", p->work); + } + for (i = 0; i < p->n_threads; ++i) { + int rc; + char name[32]; + //load_thread_t *lt = (load_thread_t *)malloc(sizeof(load_thread_t)); + load_thread_local_t *loc = NULL; + load_thread_t *lt = (ThreadObject *)PyObject_CallObject((PyObject *)&ThreadType, NULL); + if (posix_memalign((void **)&loc, 64, sizeof(load_thread_local_t)) != 0) { + PyErr_SetString(PyExc_RuntimeError, "could not allocate aligned memory"); + return NULL; + } + lt->loc = loc; + loc->thread = lt; + lt->load = p; + sem_init(<->sem_started, 0, 0); + sem_init(<->sem_worktodo, 0, 0); + lt->os_tid = 0; /* don't know it yet, will be found in-thread */ + loc->vol_work = NULL; + loc->n_iters = 0; + lt->next_thread = p->first_thread; + p->first_thread = lt; + rc = pthread_create(<->pthread_id, &p->thread_attr, &thread_start, lt); + if (rc < 0) { + perror("pthread_create"); + break; + } + sprintf(name, "sweep-%u", i); + rc = pthread_setname_np(lt->pthread_id, name); + if (rc != 0) { + perror("pthread_setname_np"); + /* Failure to set thread name isn't fatal */ + } + if (workload_verbose) { + fprintf(stderr, "pysweep: [* %u] created thread \"%s\"\n", + (unsigned int)gettid(), name); + } + } + /* At this point we should wait for all the threads to start and + progress to the point where we know their thread identifiers. */ + { + load_thread_t *lt; + for (lt = p->first_thread; lt != NULL; lt = lt->next_thread) { + sem_wait(<->sem_started); + /* The thread should have started and recorded its tid. */ + assert(lt->os_tid > 0); + if (workload_verbose) { + fprintf(stderr, "pysweep: [* %u] has noted start of worker thread [W %u]\n", + (unsigned int)gettid(), (unsigned int)lt->os_tid); + } + } + } + /* All the threads have recorded their identifiers. We can now return + to the caller and they can call the tids() method to get the tids. */ + /* First we release the threads, by setting the workload. */ + (void)sched_yield(); + load_update_thread_work(p, p->work); + assert(p->first_thread != NULL); + if (workload_verbose) { + fprintf(stderr, "pysweep: workload threads started\n"); + } + Py_RETURN_NONE; +} + + +static char const *signame(int sig) +{ + switch (sig) { + case SIGSTOP: + return "SIGSTOP"; + case SIGCONT: + return "SIGCONT"; + case SIGKILL: + return "SIGKILL"; + default: + return "?"; + } +} + + +/* + * Send a signal to all threads in the workload. + */ +static PyObject *load_signal_internal(PyObject *x, int sig) +{ + LoadObject *p = (LoadObject *)x; + load_thread_t *t; + for (t = p->first_thread; t != NULL; t = t->next_thread) { + if (workload_verbose) { + fprintf(stderr, "pysweep: [* %u] sending %s to thread [W %u]\n", + (unsigned int)gettid(), + signame(sig), + (unsigned int)t->os_tid); + } + pthread_kill(t->pthread_id, sig); + } + Py_RETURN_NONE; +} + + +static PyObject *load_signal(PyObject *x, PyObject *arg) +{ + return load_signal_internal(x, PyInt_AsLong(arg)); +} + + +/* + * We've got a reason to suspend the workers. If we hadn't already + * suspended them for any other reason, suspend them now. + */ +static PyObject *load_suspend_internal(LoadObject *p, unsigned int reason) +{ + int was_suspended = (p->suspend_reasons != 0); + p->suspend_reasons |= reason; + if (!was_suspended) { + if (workload_verbose) { + fprintf(stderr, "pysweep: [* %u] suspending workers because %#x\n", + (unsigned int)gettid(), + reason); + } + /* Remove the threads' workload */ + load_update_thread_work(p, NULL); + Py_RETURN_NONE; + } else { + /* Workload was already suspended - but this is another reason + to suspend, which we musn't forget about. */ + if (workload_verbose) { + fprintf(stderr, "pysweep: [* %u] re-suspending workers because %#x: now %#x\n", + (unsigned int)gettid(), + reason, + p->suspend_reasons); + } + Py_RETURN_NONE; + } +} + + +/* + * We've removed a reason to suspend the workers. If there's no + * longer any reason to suspend the workers, resume them. + */ +static PyObject *load_release_internal(LoadObject *p, unsigned int reason) +{ + if ((p->suspend_reasons & reason) != 0) { + /* Was previously suspended because of request for zero affinity - + but should not be suspended (for that reason) any more. */ + p->suspend_reasons &= ~reason; + if (!p->suspend_reasons) { + load_update_thread_work(p, p->work); + } + } + Py_RETURN_NONE; +} + + +/* + * Update the characteristics of an active workload object. + * This will generally involve creating a new workload, + * and deleting the old workload. + * Active threads may be running the old workload, + * so its destruction may be deferred. + */ +static PyObject *load_update(PyObject *x, PyObject *args) +{ + Workload *w, *w_old; + Character c; + LoadObject *p = (LoadObject *)x; + PyObject *spec; + if (!PyArg_ParseTuple(args, "O", &spec)) { + return NULL; + } + if (workload_verbose) { + fprintf(stderr, "pysweep: creating new workload for spec update\n"); + } + workload_init(&c); + if (setup_char(spec, &c)) { + return NULL; + } + /* Try to create a new workload with these characteristics. */ + w = workload_create(&c); + /* Update the workload. At some point the worker threads will pick up this + new workload and start running it. It's possible that we failed + to create the workload and that w is NULL. */ + w_old = p->work; + p->work = w; + if (w_old != NULL && w == NULL) { + /* Now have no workload, so suspend the executors. */ + load_suspend_internal(p, SUSPEND_BADWORK); + /* TBD: perhaps we should wait until the threads have suspended */ + } else if (w_old == NULL && w != NULL) { + load_release_internal(p, SUSPEND_BADWORK); + } else if (!p->suspend_reasons) { + load_update_thread_work(p, w); + } + if (workload_verbose) { + fprintf(stderr, "pysweep: destroying old workload %p\n", w_old); + } + workload_free(w_old); /* Will be deferred until no longer in use */ + if (workload_verbose) { + fprintf(stderr, "pysweep: workload updated\n"); + } + Py_RETURN_NONE; +} + + +/* +Stop (cancel and destroy) the object's threads. +If there are no threads this is a no-op. +This also means that any tids we have got for the load, or any events on +the load, become invalid. +*/ +static PyObject *load_stop(PyObject *x) +{ + LoadObject *p = (LoadObject *)x; + load_thread_t *t, *t_next; + void *retval; + if (workload_verbose) { + fprintf(stderr, "pysweep: stop workload\n"); + } + /* Send cancellation requests to all threads */ + for (t = p->first_thread; t != NULL; t = t->next_thread) { + int rc = pthread_cancel(t->pthread_id); + if (rc) { + perror("pthread_cancel"); + } + } + /* We should arrange to clean up thread resources once the thread has + been cancelled. We can do that two ways: + - use pthread_join waiting to see PTHREAD_CANCELED as exit status + - use pthread_cleanup_push to push a cleanup handler + */ + for (t = p->first_thread; t != NULL; t = t_next) { + int rc; + t_next = t->next_thread; + rc = pthread_join(t->pthread_id, &retval); + if (rc) { + perror("pthread_join"); + } + if (t->loc->vol_work) { + workload_remove_reference(t->loc->vol_work); + } + assert(retval == PTHREAD_CANCELED); + sem_destroy(&t->sem_started); + free((void *)t->loc); + Py_DECREF(t); + //free(t); + } + p->first_thread = NULL; + Py_RETURN_NONE; +} + + +/* + * Return the list of OS thread identifiers for the workload. + * This list is non-empty if the workload has been started. + */ +static PyObject *load_tids(PyObject *x) +{ + LoadObject *p = (LoadObject *)x; + load_thread_t *t; + PyObject *list; + /* If load is not started, it will return an empty list */ + list = PyList_New(0); + for (t = p->first_thread; t != NULL; t = t->next_thread) { + PyList_Append(list, PyInt_FromLong(t->os_tid)); + } + return list; +} + + +static PyObject *thread_tid(PyObject *x) +{ + ThreadObject *t = (ThreadObject *)x; + if (!t->os_tid) { + Py_RETURN_NONE; + } + return PyInt_FromLong(t->os_tid); +} + + +/* + * Provide our own definition so we can build with Python 2.6 + */ +static int MyPyLong_AsLongAndOverflow(PyObject *x, int *overflow) +{ + int n = PyLong_AsLong(x); + if (PyErr_Occurred() && PyErr_ExceptionMatches(PyExc_OverflowError)) { + *overflow = 1; + PyErr_Clear(); + } else { + *overflow = 0; + } + return n; +} + + +static int affinity_object_to_set(PyObject *x, cpu_set_t *cpus) +{ + CPU_ZERO(cpus); + if (PyInt_Check(x)) { + unsigned long long cpumask = PyInt_AsUnsignedLongLongMask(x); + unsigned int i; + //printf("cpuset: int 0x%lx\n", cpumask); + for (i = 0; i < 64; ++i) { + if ((cpumask & (1ULL<= CPU_SETSIZE) { + PyErr_SetString(PyExc_ValueError, "CPU number out of range"); + return 0; + } + CPU_SET(i+pos, cpus); + } + } + x = PyNumber_Rshift(x, PyInt_FromLong(64)); + pos += 64; + done = (MyPyLong_AsLongAndOverflow(x, &overflow) == 0) && !overflow; + } while (!done); + } else if (PyList_Check(x)) { + unsigned int const size = PyList_Size(x); + unsigned int i; + CPU_ZERO(cpus); + for (i = 0; i < size; ++i) { + unsigned int n = PyInt_AsLong(PyList_GET_ITEM(x, i)); + if (n >= CPU_SETSIZE) { + PyErr_SetString(PyExc_ValueError, "CPU number out of range"); + return 0; + } + CPU_SET(n, cpus); + } + } else { + PyErr_SetString(PyExc_TypeError, "Expected list or mask"); + return 0; + } + //printf("cpuset done: %u cpus\n", CPU_COUNT(cpus)); + return 1; +} + +static PyObject *cpu_set_to_list(cpu_set_t const *cpus) +{ + unsigned int i; + PyObject *r = PyList_New(0); + for (i = 0; i < CPU_SETSIZE; ++i) { + if (CPU_ISSET(i, cpus)) { + PyList_Append(r, PyInt_FromLong(i)); + } + } + return r; +} + + +/* + * Report total iterations across all threads + */ +static PyObject *load_iterations(PyObject *x) +{ + LoadObject *p = (LoadObject *)x; + unsigned long long n_iters = 0; + load_thread_t *t; + for (t = p->first_thread; t != NULL; t = t->next_thread) { + n_iters += t->loc->n_iters; + } + return PyInt_FromLong(n_iters); +} + + +static PyObject *load_thread_iterations(PyObject *x, PyObject *args) +{ + LoadObject *p = (LoadObject *)x; + unsigned int tid; + load_thread_t *t; + if (!PyArg_ParseTuple(args, "I", &tid)) { + return NULL; + } + for (t = p->first_thread; t != NULL; t = t->next_thread) { + if (t->os_tid == (pid_t)tid) { + return PyInt_FromLong(t->loc->n_iters); + } + } + /* Either None or an exception will hopefully fault the caller. */ + return NULL; +} + + +static PyObject *thread_iterations(PyObject *x) +{ + ThreadObject *t = (ThreadObject *)x; + return PyInt_FromLong(t->loc->n_iters); +} + + +/* + * Set CPU affinity for the current workload. Affinity is supplied as a bitmask. + * The threads of the workload are each free to use any of the given CPUs. + * The set may be zero in which case the workload is suspended. + * TBD: allow fine-grained pinning of individual threads. + */ +static PyObject *load_setaffinity(PyObject *x, PyObject *mask) +{ + load_thread_t *t; + LoadObject *p = (LoadObject *)x; + cpu_set_t affinity; + if (!affinity_object_to_set(mask, &affinity)) { + return NULL; + } + + /* Set the affinity in the thread attributes. If we haven't created + the threads yet, they will pick it up from here. */ + pthread_attr_setaffinity_np(&p->thread_attr, sizeof affinity, &affinity); + + /* Update running threads. We might not have started any threads yet. */ + + /* If the mask is zero, sched_setaffinity will fail. So instead, + suspend the thread. */ + if (CPU_COUNT(&affinity) == 0) { + return load_suspend_internal(p, SUSPEND_ZEROAFF); + } + + for (t = p->first_thread; t != NULL; t = t->next_thread) { + int rc = sched_setaffinity(t->os_tid, sizeof affinity, &affinity); + if (rc != 0) { + PyErr_SetString(PyExc_RuntimeError, "sched_setaffinity failed"); + return NULL; + } + } + + return load_release_internal(p, SUSPEND_ZEROAFF); +} + +static PyObject *load_getaffinity(PyObject *x) +{ + LoadObject *p = (LoadObject *)x; + cpu_set_t affinity; + pthread_attr_getaffinity_np(&p->thread_attr, sizeof affinity, &affinity); + return cpu_set_to_list(&affinity); +} + + +/* + * Set affinity for a single thread. + */ +static PyObject *thread_setaffinity(PyObject *x, PyObject *mask) +{ + int rc; + ThreadObject *t = (ThreadObject *)x; + cpu_set_t affinity; + if (!affinity_object_to_set(mask, &affinity)) { + return NULL; + } + rc = sched_setaffinity(t->os_tid, sizeof affinity, &affinity); + if (rc != 0) { + PyErr_SetString(PyExc_RuntimeError, "sched_setaffinity failed"); + return NULL; + } + Py_RETURN_NONE; +} + +static PyObject *thread_getaffinity(PyObject *x) +{ + ThreadObject *t = (ThreadObject *)x; + cpu_set_t affinity; + int rc = sched_getaffinity(t->os_tid, sizeof affinity, &affinity); + if (rc) { + PyErr_SetString(PyExc_RuntimeError, "sched_getaffinity failed"); + return NULL; + } + return cpu_set_to_list(&affinity); +} + + +/* +Set affinity for the current (monitoring) thread. +Input is an integer (up to 64 bits) representing a CPU mask. +TBD: handle larger integers. +*/ +static PyObject *gfn_setaffinity(PyObject *x, PyObject *mask) +{ + cpu_set_t cpus; + int rc; + if (!affinity_object_to_set(mask, &cpus)) { + return NULL; + } + rc = sched_setaffinity(0, sizeof cpus, &cpus); + if (rc != 0) { + PyErr_SetString(PyExc_RuntimeError, "sched_setaffinity failed"); + return NULL; + } + Py_RETURN_NONE; +} + + +static PyObject *gfn_sched_yield(PyObject *x) +{ + (void)sched_yield(); + Py_RETURN_NONE; +} + + +static PyObject *load_suspend(PyObject *x) +{ + if (workload_verbose) { + fprintf(stderr, "pysweep: suspending workload\n"); + } + load_suspend_internal((LoadObject *)x, SUSPEND_REQUEST); + Py_RETURN_NONE; +} + + +static PyObject *load_resume(PyObject *x) +{ + return load_release_internal((LoadObject *)x, SUSPEND_REQUEST); +} + + +static PyObject *load_suspense(PyObject *x) +{ + LoadObject *p = (LoadObject *)x; + return PyInt_FromLong(p->suspend_reasons); +} + + +static PyObject *load_expected(PyObject *x) +{ + LoadObject *p = (LoadObject *)x; + Workload *w = p->work; + struct inst_counters const *e = &w->expected; + + if (e->n[COUNT_INST] == 0) { + /* Either we haven't built the workload yet or something went wrong + when we generated the metrics? */ + Py_RETURN_NONE; + } + /* Build a data structure with the expected workload metrics */ + PyObject *data = PyDict_New(); + PyDict_SetItemString(data, "n_inst", PyInt_FromLong(e->n[COUNT_INST])); +#define SETITEM(x, K) \ + PyDict_SetItemString(data, #x, PyFloat_FromDouble((float)e->n[COUNT_##K] / e->n[COUNT_INST])) + SETITEM(branch, BRANCH); + SETITEM(mem_read, INST_RD); + SETITEM(bytes_read, BYTES_RD); + SETITEM(mem_write, INST_WR); + SETITEM(bytes_write, BYTES_WR); + SETITEM(flop_sp, FLOP_SP); + SETITEM(flop_dp, FLOP_DP); + SETITEM(fence, FENCE); + SETITEM(unit, UNIT); +#undef SETITEM + return data; +} + + +static PyObject *load_threads(PyObject *x) +{ + LoadObject *p = (LoadObject *)x; + ThreadObject *t; + PyObject *tmap = PyDict_New(); + for (t = p->first_thread; t != NULL; t = t->next_thread) { + PyDict_SetItem(tmap, PyInt_FromLong(t->os_tid), (PyObject *)t); + } + return tmap; +} + + +static PyObject *load_dump(PyObject *x, PyObject *args) +{ + LoadObject *p = (LoadObject *)x; + int rc; + char *fn; + Workload *w = p->work; + if (!PyArg_ParseTuple(args, "s", &fn)) { + PyErr_SetString(PyExc_TypeError, "expected file name"); + return 0; + } + if (!w) { + PyErr_SetString(PyExc_RuntimeError, "no workload to dump"); + return 0; + } + rc = workload_dump(w, fn, /*flags=*/0); + /* TBD: bad file name etc. ought to be a Python exception */ + return PyInt_FromLong(rc); +} + + +static void load_dealloc(PyObject *x) +{ + LoadObject *p = (LoadObject *)x; + if (workload_verbose) { + fprintf(stderr, "pysweep: dealloc\n"); + } + (void)load_stop(x); + /* Any worker threads have now been cancelled and joined, + so it's safe to free the workload. */ + workload_free(p->work); + pthread_attr_destroy(&p->thread_attr); + /* "finally (as its last action) call the type's tp_free function." */ + x->ob_type->tp_free(x); +} + + +static PyObject *thread_str(PyObject *x) +{ + ThreadObject *t = (ThreadObject *)x; + return PyString_FromFormat("[%u]", (unsigned int)t->os_tid); +} + + +static PyMethodDef Load_methods[] = { + {"start", (PyCFunction)&load_start, METH_VARARGS|METH_KEYWORDS, "None: start running a load"}, + {"update", (PyCFunction)&load_update, METH_VARARGS, "spec -> None: update load specification"}, + {"setaffinity", (PyCFunction)&load_setaffinity, METH_O, "list or mask -> None: set CPU affinity mask for workload"}, + {"getaffinity", (PyCFunction)&load_getaffinity, METH_NOARGS, "list: get CPU affinity"}, + {"stop", (PyCFunction)&load_stop, METH_NOARGS, "None: stop (cancel) load threads"}, + {"suspend", (PyCFunction)&load_suspend, METH_NOARGS, "None: suspend load threads"}, + {"resume", (PyCFunction)&load_resume, METH_NOARGS, "None: resume load threads"}, + {"signal", (PyCFunction)&load_signal, METH_O, "int: send signal to load threads"}, + {"suspense", (PyCFunction)&load_suspense, METH_NOARGS, "int: suspension status"}, + {"iterations", (PyCFunction)&load_iterations, METH_NOARGS, "int: total iterations so far"}, + {"thread_iterations", (PyCFunction)&load_thread_iterations, METH_VARARGS, "int -> int: iterations of a thread"}, + {"threads", (PyCFunction)&load_threads, METH_NOARGS, "{}: get set of threads"}, + {"tids", (PyCFunction)&load_tids, METH_NOARGS, "[tids]: get OS thread ids"}, + {"expected", (PyCFunction)&load_expected, METH_NOARGS, "{}: get expected instruction counts"}, + {"dump", (PyCFunction)&load_dump, METH_VARARGS, "str -> int: generate program image file"}, + {NULL} +}; + + +static PyTypeObject LoadType = { + PyVarObject_HEAD_INIT(NULL, 0) + tp_basicsize: sizeof(LoadObject), + tp_name: "pysweep.Load", + tp_doc: "system load", + tp_flags: Py_TPFLAGS_DEFAULT, + tp_methods: Load_methods, + //tp_members: Load_members, + tp_new: load_new, + tp_init: load_init, + tp_dealloc: load_dealloc +}; + + +static PyMethodDef Thread_methods[] = { + {"tid", (PyCFunction)&thread_tid, METH_NOARGS, "int: OS thread id"}, + {"setaffinity", (PyCFunction)&thread_setaffinity, METH_O, "list or mask -> None: set CPU affinity mask for thread"}, + {"getaffinity", (PyCFunction)&thread_getaffinity, METH_NOARGS, "list: get CPU affinity"}, + {"iterations", (PyCFunction)&thread_iterations, METH_NOARGS, "int: iterations so far"}, + {NULL} +}; + + +static PyTypeObject ThreadType = { + PyVarObject_HEAD_INIT(NULL, 0) + tp_basicsize: sizeof(ThreadObject), + tp_name: "pysweep.Thread", + tp_doc: "system load thread", + tp_flags: Py_TPFLAGS_DEFAULT, + tp_methods: Thread_methods, + tp_new: thread_new, + tp_str: thread_str +}; + + +/* Static functions of this module */ +static PyMethodDef funcs[] = { + {"setaffinity", (PyCFunction)&gfn_setaffinity, METH_O, "list or mask -> None: set CPU affinity mask for future workloads"}, + {"sleep", (PyCFunction)&gfn_sleep, METH_VARARGS, "float -> int: sleep; like time.sleep() but correctly handling interrupts"}, + {"sched_yield", (PyCFunction)&gfn_sched_yield, METH_NOARGS, "None: yield to scheduler"}, + {"bench", (PyCFunction)&gfn_bench, METH_VARARGS, "(spec, int, int) -> None: measure workload creation time"}, + {"debug", (PyCFunction)&gfn_debug, METH_VARARGS, "int -> None: set diagnostic options"}, + {"br_pred", (PyCFunction)&gfn_br_pred, METH_VARARGS, "int -> scaling factor: Run Branch Prediction workload"}, +#ifdef ARCH_AARCH64 + {"ctr", (PyCFunction)&gfn_ctr, METH_NOARGS, "-> int: get value of Cache Type Register"}, +#endif /* ARCH_AARCH64 */ + {NULL} +}; + +static struct { + char const *name; + unsigned int value; +} const constants[] = { + { "MEM_PREFETCH", WL_MEM_PREFETCH }, + { "MEM_NONTEMPORAL", WL_MEM_NONTEMPORAL }, + { "MEM_STREAM", WL_MEM_STREAM }, + { "MEM_HUGEPAGE", WL_MEM_HUGEPAGE }, + { "MEM_NO_HUGEPAGE", WL_MEM_NO_HUGEPAGE }, + { "MEM_FORCE_HUGEPAGE", WL_MEM_FORCE_HUGEPAGE }, + { "MEM_ACQUIRE", WL_MEM_ACQUIRE }, + { "MEM_BARRIER", WL_MEM_BARRIER }, + { "DEBUG_NO_CODE", WORKLOAD_DEBUG_DUMMY_CODE }, + { "DEBUG_NO_COHERENCE", WORKLOAD_DEBUG_NO_UNIFICATION }, + { "DEBUG_NO_MPROTECT", WORKLOAD_DEBUG_NO_MPROTECT }, + { "DEBUG_NO_WX", WORKLOAD_DEBUG_NO_WX }, + { "DEBUG_MMAP", BENCH_MMAP }, + { "DEBUG_CODE", BENCH_CODE }, + { "DEBUG_NO_TRIAL", BENCH_NO_TRIAL } +}; + +#if PY_MAJOR_VERSION < 3 +#define INIT_NAME2(m) init##m +#else +#define INIT_NAME2(m) PyInit_##m +#endif +#define INIT_NAME(m) INIT_NAME2(m) +PyMODINIT_FUNC INIT_NAME(MODULE_NAME)(void) +{ + unsigned int i; + PyObject *pmod; +#if PY_MAJOR_VERSION < 3 + pmod = Py_InitModule3(MODULE_NAME_STRING, funcs, "load generator"); +#else + static struct PyModuleDef moduledef = { + PyModuleDef_HEAD_INIT, + .m_name = MODULE_NAME_STRING, + .m_doc = "load generator", + .m_size = -1, + .m_methods = funcs + }; + pmod = PyModule_Create(&moduledef); +#endif + PyType_Ready(&LoadType); + PyObject_SetAttrString(pmod, "Load", (PyObject *)&LoadType); + PyType_Ready(&ThreadType); + for (i = 0; i < (sizeof constants / sizeof constants[0]); ++i) { + PyModule_AddIntConstant(pmod, constants[i].name, constants[i].value); + } +#if PY_MAJOR_VERSION >= 3 + return pmod; +#endif +} + +/* end of pysweep.c */ diff --git a/linux_app/pmu_app/pysweep/src/sleep.c b/linux_app/pmu_app/pysweep/src/sleep.c new file mode 100644 index 00000000..53e09b71 --- /dev/null +++ b/linux_app/pmu_app/pysweep/src/sleep.c @@ -0,0 +1,131 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +/* + * High-resolution sleep. The aim is to wait for the given duration, + * even if some kind of userspace-interrupt-driven profiling is active. + * + * We use a timed select() call. This may return early with EINTR, + * e.g. after a SIGPROF interrupt. We can calculate the remaining time + * and re-execute a select() for the remaining time. + * + * However, we do want to be able to break out of a long wait with a SIGINT. + * + * TBD: this is not thread-safe! + */ + +#ifndef _GNU_SOURCE +#define _GNU_SOURCE +#endif /* _GNU_SOURCE */ + +#include "sleep.h" + +#include +#include +#include +#include +#include +#include +#include +#include + +#define SECONDS 1000000000 +#define MAX_BLOCKING (1ULL*SECONDS) + + +static unsigned long long nowns(void) +{ + struct timespec ts; + clock_gettime(CLOCK_MONOTONIC, &ts); + return (ts.tv_sec * 1000000000ULL) + ts.tv_nsec; +} + + +static int volatile sigint_received = 0; + + +static void sigint_handler(int sig) +{ + sigint_received = 1; +} + + +int microsleep_ns(long long sleep_nano) +{ + int n_iters = 0; + int rc; + unsigned long long const then = nowns() + sleep_nano; + int const handle_sigint = 1 && (sleep_nano >= MAX_BLOCKING); + struct sigaction oldact; + if (handle_sigint) { + int rc; + struct sigaction act; + memset(&act, 0, sizeof act); + act.sa_handler = sigint_handler; + sigemptyset(&act.sa_mask); + act.sa_flags = 0; + act.sa_restorer = NULL; + sigint_received = 0; + rc = sigaction(SIGINT, &act, &oldact); + if (rc) { + perror("sigaction"); + } + } + while (sleep_nano > 0) { + struct timespec ts_wait; + ts_wait.tv_sec = (sleep_nano / 1000000000); + ts_wait.tv_nsec = (sleep_nano % 1000000000); + rc = pselect(0, NULL, NULL, NULL, &ts_wait, NULL); + if (rc == -1 && errno == EINTR) { + /* woken up by interrupt - perhaps SIGPROF or SIGINT? */ + /* Ideally, we should be able to find out what kind of interrupt + caused the EINTR, but I don't know how to do that. + sigpending() doesn't help. */ + unsigned long long now = nowns(); + if (now >= then) { + /* but rolled off the end anyway */ + rc = n_iters; + break; + } + if (sigint_received) { + break; + } + /* resume the wait, but with a shorter time */ + sleep_nano = then - now; + } else if (rc < 0) { + break; + } else { + rc = n_iters; + break; + } + ++n_iters; + } + if (handle_sigint) { + sigaction(SIGINT, &oldact, NULL); + if (sigint_received) { + raise(SIGINT); + return -1; + } + } + return rc; +} + + +int microsleep(double t) +{ + return microsleep_ns(t * 1e9); +} diff --git a/linux_app/pmu_app/pysweep/src/sleep.h b/linux_app/pmu_app/pysweep/src/sleep.h new file mode 100644 index 00000000..9ab03b7a --- /dev/null +++ b/linux_app/pmu_app/pysweep/src/sleep.h @@ -0,0 +1,39 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ +#ifndef __included_sleep_h +#define __included_sleep_h + +/* + * Wait for a high-resolution amount of time, handling EINTR. + * The standard way is to use select() or pselect(). The underlying + * system call adjusts the time argument to show how much time remains, + * but this is hidden by the library. So to know how long we actually + * slept we have to read the current time, and iterate. + */ + +/* For glibc versions before 2.17, link with -lrt */ + +/* + * Result is a negative return code (with errno set) + * or a non-negative count of the number of times we had to iterate. + */ + +int microsleep_ns(long long); + +int microsleep(double); + +#endif diff --git a/linux_app/pmu_app/pysweep/tests/code_template.c b/linux_app/pmu_app/pysweep/tests/code_template.c new file mode 100644 index 00000000..2a8200ac --- /dev/null +++ b/linux_app/pmu_app/pysweep/tests/code_template.c @@ -0,0 +1,115 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ +/* + * Templates for the kind of code we're going to be dynamically generating. + * We don't auto-generate the generator from this, it's just for convenience. + */ + +#include + +int *arg_to_return(int *p) { return p; } + +int *arg_load_to_return(int **p) { return *p; } + +int *arg_load_load_to_return(int ***p) { return **p; } + +extern int *giver(void); +extern void takerp(int *p); +extern void takerpp(int *p, int *q); + +void arg_load_to_arg(int **p) { takerp(*p); } +void arg_load_to_arg2(int **p) { takerpp(0,*p); } +void arg2_load_to_arg(int **p, int **q) { takerp(*q); } + +int *arg_load_indexed(int a, int **b, int c) { return *(int **)((unsigned char *)b + c); } +int *arg_load_indexed2(int a, int b, int **c) { return *(int **)((unsigned char *)c + b); } +void arg_load_indexed_to_arg(int a, int **b, int c) { takerpp(0,*(int **)((unsigned char *)b + c)); } + +void arg_store(int *p) { *p = 1; } + +void return_to_arg(void) { takerp(giver()); } + +extern void taker2(float, float); +extern void taker3(float, float, float); +void float_to_arg2(float x) { taker2(0.0, x); } + +int mul32(int x, int y) { return x * y; } +long long mul64(long long x, long long y) { return x * y; } +int div32(int x, int y) { return x / y; } +long long div64(long long x, long long y) { return x / y; } + +float add_float00(float x, float y) { return x + x; } +float add_float01(float x, float y) { return x + y; } +float add_float11(float x, float y) { return add_float00(x, y+y); } + +void sub_float01to2(float x, float y) { taker3(0.0, 0.0, x - y); } + +double neg_double(double x) { return -x; } +double add_double(double x, double y) { return x + y; } +double mul_double(double x, double y) { return x * y; } +double div_double(double x, double y) { return x / y; } +double sqrt_double(double x) { return __builtin_sqrt(x); } +double fma_double(double x, double y, double z) { return x + (y*z); } +#ifdef FP_FAST_FMA +float fma2_float(float x, float y, float z) { return fmaf(y,z,x); } +float fma2_float11(float x, float y, float z) { return fmaf(y,y,x); } +float fma2_float22(float x, float y, float z) { return fmaf(z,z,x); } +double fma2_double(double x, double y, double z) { return fma(y,z,x); } +#endif + +double load_double_r0(double *p) { return *p; } +double load_double_r1(double *p, double *q) { return *q; } +float load_float_r0(float *p) { return *p; } +void store_float_r0(float *p, float x) { *p = x; } +void store_float1_r0(float *p, float x, float y) { *p = y; } + +#if 1 +/* + * Try to generate a vector instruction by auto-vectorization. + */ +#define GENVEC(name, T, op) \ +void vec_##name(T *__restrict a, T const *__restrict b, T const *__restrict c) { \ + int i; for (i = 0; i < 4; ++i) { \ + T cb = b[i] op c[i]; T r = cb + cb; a[i] += r; } } + +GENVEC(fadd, float, +) +GENVEC(fmul, float, *) +GENVEC(dadd, double, +) +GENVEC(iadd, int, +) +GENVEC(ieor, int, ^) +GENVEC(imul, int, *) +GENVEC(ladd, long long, +) +#endif + +void countdown(int n) { + do { + taker2(0.0, 0.0); + n--; + } while (n >= 0); +} + +int small_integer(void) { return 12; } +int small_neg_integer(void) { return -12; } +int large_integer(void) { return 12983489; } + + +void pfetch(void *p) { __builtin_prefetch(p); } +void pfetch2(void *x, void *p) { __builtin_prefetch(p); } +void pfetcha(void *p, int n) { __builtin_prefetch((char *)p + n); } +void pfetcha2(void *p, int a, int n) { __builtin_prefetch((char *)p + n); } +void pfetcha3(void *x, void *p, int n) { __builtin_prefetch((char *)p + n); } + diff --git a/linux_app/sbsa-acs-app/include/sbsa_app.h b/linux_app/sbsa-acs-app/include/sbsa_app.h index e24132e5..bc59f0f5 100644 --- a/linux_app/sbsa-acs-app/include/sbsa_app.h +++ b/linux_app/sbsa-acs-app/include/sbsa_app.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2020, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -20,8 +20,8 @@ #define __SBSA_APP_LINUX_H__ -#define SBSA_APP_VERSION_MAJOR 6 -#define SBSA_APP_VERSION_MINOR 1 +#define SBSA_APP_VERSION_MAJOR 7 +#define SBSA_APP_VERSION_MINOR 1 #define SBSA_APP_VERSION_SUBMINOR 0 #include "sbsa_drv_intf.h" @@ -35,4 +35,7 @@ execute_tests_pcie(int num_pe, int level, unsigned int print_level); int execute_tests_exerciser(int num_pe, int level, unsigned int print_level); + +int +execute_tests_smmu(int num_pe, int level, unsigned int print_level); #endif diff --git a/linux_app/sbsa-acs-app/include/sbsa_drv_intf.h b/linux_app/sbsa-acs-app/include/sbsa_drv_intf.h index 1ad7171d..4eebb814 100644 --- a/linux_app/sbsa-acs-app/include/sbsa_drv_intf.h +++ b/linux_app/sbsa-acs-app/include/sbsa_drv_intf.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -26,6 +26,7 @@ #define SBSA_PCIE_EXECUTE_TEST 0x2000 #define SBSA_UPDATE_SKIP_LIST 0x3000 #define SBSA_EXERCISER_EXECUTE_TEST 0x4000 +#define SBSA_SMMU_EXECUTE_TEST 0x5000 #define SBSA_FREE_INFO_TABLES 0x9000 diff --git a/linux_app/sbsa-acs-app/sbsa_app_main.c b/linux_app/sbsa-acs-app/sbsa_app_main.c index a7519a0a..94f1676b 100644 --- a/linux_app/sbsa-acs-app/sbsa_app_main.c +++ b/linux_app/sbsa-acs-app/sbsa_app_main.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -117,7 +117,8 @@ main (int argc, char **argv) printf ("\n ************ SBSA Architecture Compliance Suite ********* \n"); - printf (" Version %d.%d.%d \n", SBSA_APP_VERSION_MAJOR, SBSA_APP_VERSION_MINOR, SBSA_APP_VERSION_SUBMINOR); + printf (" Version %d.%d.%d\n", SBSA_APP_VERSION_MAJOR, + SBSA_APP_VERSION_MINOR, SBSA_APP_VERSION_SUBMINOR); printf ("\n Starting tests for level %2d (Print level is %2d)\n\n", g_sbsa_level, g_print_level); @@ -129,14 +130,18 @@ main (int argc, char **argv) return 0; } + if (g_sbsa_level > 6) + { + printf("\n *** Starting SMMU tests *** \n"); + execute_tests_smmu(1, g_sbsa_level, g_print_level); + } + printf("\n *** Starting PCIe tests *** \n"); + execute_tests_pcie(1, g_sbsa_level, g_print_level); + if (run_exerciser) { printf("\n *** PCIe Exerciser tests only runs on UEFI *** \n"); //execute_tests_exerciser(1, g_sbsa_level, g_print_level); - } else { - printf("\n *** Starting PCIe tests *** \n"); - execute_tests_pcie(1, g_sbsa_level, g_print_level); } - printf("\n *** SBSA tests complete *** \n\n"); cleanup_test_environment(); diff --git a/linux_app/sbsa-acs-app/sbsa_app_smmu.c b/linux_app/sbsa-acs-app/sbsa_app_smmu.c new file mode 100644 index 00000000..4c97382b --- /dev/null +++ b/linux_app/sbsa-acs-app/sbsa_app_smmu.c @@ -0,0 +1,47 @@ +/** @file + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + + +#include +#include +#include +#include +#include +#include + +#include "include/sbsa_app.h" +#include "include/sbsa_drv_intf.h" + + +extern int g_skip_test_num[3]; + +/** + This function calls the SBSA Kernel Module in a loop to execute all the SMMU tests +**/ +int +execute_tests_smmu(int num_pe, int level, unsigned int print_level) +{ + + int status; + + call_update_skip_list(SBSA_UPDATE_SKIP_LIST, g_skip_test_num); + call_drv_execute_test(SBSA_SMMU_EXECUTE_TEST, num_pe, level, print_level, 0); + status = call_drv_wait_for_completion(); + + return status; +} + diff --git a/platform/pal_uefi/include/pal_exerciser.h b/platform/pal_uefi/include/pal_exerciser.h index 3c53dc3b..cc94c20d 100644 --- a/platform/pal_uefi/include/pal_exerciser.h +++ b/platform/pal_uefi/include/pal_exerciser.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -28,6 +28,15 @@ #define BUS_MEM_EN_MASK 0x06 +#define PCIE_EXTRACT_BDF_SEG(bdf) ((bdf >> 24) & 0xFF) +#define PCIE_EXTRACT_BDF_BUS(bdf) ((bdf >> 16) & 0xFF) +#define PCIE_EXTRACT_BDF_DEV(bdf) ((bdf >> 8) & 0xFF) +#define PCIE_EXTRACT_BDF_FUNC(bdf) (bdf & 0xFF) + +#define PCIE_CREATE_BDF_PACKED(bdf) PCIE_EXTRACT_BDF_FUNC(bdf) | \ + (PCIE_EXTRACT_BDF_DEV(bdf) << 3) | \ + (PCIE_EXTRACT_BDF_BUS(bdf) << 8) + /* PCIe Config space Offset */ #define BAR0_OFFSET 0x10 #define COMMAND_REG_OFFSET 0x04 diff --git a/test_pool/Makefile b/test_pool/Makefile index a85eb76f..26d951c9 100644 --- a/test_pool/Makefile +++ b/test_pool/Makefile @@ -1,5 +1,5 @@ ## @file - # Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. + # Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -25,15 +25,9 @@ TEST_POOL = $(ACS_DIR)/ obj-m += sbsa_acs_test.o sbsa_acs_test-objs += $(TEST_POOL)/pcie/test_p001.o \ - $(TEST_POOL)/pcie/test_p002.o \ - $(TEST_POOL)/pcie/test_p005.o $(TEST_POOL)/pcie/test_p006.o \ - $(TEST_POOL)/pcie/test_p007.o $(TEST_POOL)/pcie/test_p008.o \ - $(TEST_POOL)/pcie/test_p009.o $(TEST_POOL)/pcie/test_p010.o \ - $(TEST_POOL)/pcie/test_p011.o $(TEST_POOL)/pcie/test_p012.o \ - $(TEST_POOL)/pcie/test_p013.o $(TEST_POOL)/pcie/test_p014.o \ - $(TEST_POOL)/pcie/test_p015.o $(TEST_POOL)/pcie/test_p016.o \ - $(TEST_POOL)/pcie/test_p017.o $(TEST_POOL)/pcie/test_p018.o \ - $(TEST_POOL)/pcie/test_p019.o \ + $(TEST_POOL)/pcie/test_p002.o $(TEST_POOL)/pcie/test_p005.o \ + $(TEST_POOL)/pcie/operating_system/test_p009.o \ + $(TEST_POOL)/smmu/operating_system/test_i016.o ccflags-y=-I$(PWD)/$(ACS_DIR)/.. -I$(PWD)/$(ACS_DIR)/val/ -I$(PWD)/$(ACS_DIR)/ -DTARGET_LINUX -Wall -Werror diff --git a/val/Makefile b/val/Makefile index c87a66a2..3dad6fa0 100644 --- a/val/Makefile +++ b/val/Makefile @@ -1,5 +1,5 @@ ## @file - # Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. + # Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,7 +30,7 @@ sbsa_acs_val-objs += $(VAL_SRC)/avs_status.o $(VAL_SRC)/avs_memory.o \ $(VAL_SRC)/avs_iovirt.o \ $(ACS_DIR)/sys_arch_src/smmu_v3/smmu_v3.o -ccflags-y=-I$(PWD)/$(ACS_DIR)/include -I$(PWD)/$(ACS_DIR)/ -DTARGET_LINUX -DONLY_SBSA_RULE_TESTS -Wall -Werror +ccflags-y=-I$(PWD)/$(ACS_DIR)/include -I$(PWD)/$(ACS_DIR)/ -DTARGET_LINUX -Wall -Werror all: ifeq ($(KERNEL_SRC),) From 6b135359687dc7a8c019ea15a7adfe6518e25594 Mon Sep 17 00:00:00 2001 From: Sujana M Date: Fri, 13 Jan 2023 10:19:08 +0530 Subject: [PATCH 5/8] SBSA ACS 7.1: Exerciser tests - Added exerciser tests to check AER functionality - Updated Exerciser porting guide Signed-off-by: Sujana M --- docs/Exerciser_porting_guide.md | 47 +- platform/pal_uefi/include/pal_exerciser.h | 66 ++- platform/pal_uefi/src/pal_exerciser.c | 83 +++- .../exerciser/operating_system/test_e017.c | 206 ++++++++ .../exerciser/operating_system/test_e018.c | 438 ++++++++++++++++++ .../exerciser/operating_system/test_e019.c | 362 +++++++++++++++ .../exerciser/operating_system/test_e020.c | 254 ++++++++++ uefi_app/SbsaAvs.inf | 4 + uefi_app/SbsaAvsNist.inf | 4 + val/include/sbsa_avs_exerciser.h | 63 ++- val/src/avs_exerciser.c | 174 +++++-- 11 files changed, 1647 insertions(+), 54 deletions(-) create mode 100644 test_pool/exerciser/operating_system/test_e017.c create mode 100644 test_pool/exerciser/operating_system/test_e018.c create mode 100644 test_pool/exerciser/operating_system/test_e019.c create mode 100644 test_pool/exerciser/operating_system/test_e020.c diff --git a/docs/Exerciser_porting_guide.md b/docs/Exerciser_porting_guide.md index 27eb372a..25f54798 100644 --- a/docs/Exerciser_porting_guide.md +++ b/docs/Exerciser_porting_guide.md @@ -145,6 +145,51 @@ Value1 - Requested transaction data
Value2 - Null
Bdf - BDF of the exerciser

+ +### Error Injection +Error injection capability enables user to inject error in a PCIe endpoint.
+- The user can inject an error at that endpoint with the error configured using the error_code field. The error_codes are defined in Error Codes section. This bit is cleared once the error has been injected. +**pal_exerciser_get_param(Type, Value1, Value2, Bdf)**
+Type - ERRR_INJECT_TYPE
+Value1 - Type of error to inject(Refer error code section)
+Value2 - Null
+Bdf - BDF of the exerciser
+**pal_exerciser_ops(Ops, Param, Bdf)**
+Ops - INJECT_ERROR
+Param - Type of error to inject(Refer error code section)
+Bdf - BDF of the exerciser
+
+ +## Error Codes + |Error Name |Error Code| + |------------------------------------------|----------| + |Correctable Receiver Error |0x00 | + |Correctable Bad TLP |0x01 | + |Correctable Bad DLLP |0x02 | + |Correctable Replay Num Rollover |0x03 | + |Correctable Replay Timer Timeout |0x04 | + |Correctable Advisory Non-Fatal Error |0x05 | + |Correctable Internal Error |0x06 | + |Correctable Header Log OverFlow |0x07 | + |Uncorrectable Data Link Error |0x08 | + |Uncorrectable Surprise Down Error |0x09 | + |Uncorrectable Poisoned TLP Received |0x0A | + |Uncorrectable Flow Control Error |0x0B | + |Uncorrectable Completion Timeout |0x0C | + |Uncorrectable Completer Abort |0x0D | + |Uncorrectable Unexpected Completion |0x0E | + |Uncorrectable Receiver Overflow |0x0F | + |Uncorrectable Malformed TLP |0x10 | + |Uncorrectable ECRC Error |0x11 | + |Uncorrectable Unsupported Request |0x12 | + |Uncorrectable ACS Violation |0x13 | + |Uncorrectable Internal Error |0x14 | + |Uncorrectable MultiCast Blocked TLP |0x15 | + |Uncorrectable Atomic Op Egress Blocked |0x16 | + |Uncorrectable TLP Prefix Blocked Egress |0x17 | + |Uncorrectable Poisoned TLP Egress Blocked |0x18 | + |Invalid configuration |0x19 | +

## License @@ -152,5 +197,5 @@ Arm SBSA ACS is distributed under Apache v2.0 License. -------------- -*Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2022-2023, Arm Limited and Contributors. All rights reserved.* diff --git a/platform/pal_uefi/include/pal_exerciser.h b/platform/pal_uefi/include/pal_exerciser.h index cc94c20d..9f480ed2 100644 --- a/platform/pal_uefi/include/pal_exerciser.h +++ b/platform/pal_uefi/include/pal_exerciser.h @@ -46,22 +46,27 @@ #define PCIE_CAP_CTRL_OFFSET 0x4// offset from the extended capability header /* Exerciser MMIO Offsets */ -#define INTXCTL 0x004 -#define MSICTL 0x000 -#define DMACTL1 0x08 -#define DMA_BUS_ADDR 0x010 -#define DMA_LEN 0x018 -#define DMASTATUS 0x01C -#define PASID_VAL 0x020 -#define ATSCTL 0x024 -#define ATS_ADDR 0x028 +#define INTXCTL 0x004 +#define MSICTL 0x000 +#define DMACTL1 0x08 +#define DMA_BUS_ADDR 0x010 +#define DMA_LEN 0x018 +#define DMASTATUS 0x01C +#define PASID_VAL 0x020 +#define ATSCTL 0x024 +#define ATS_ADDR 0x028 +#define TXN_TRACE 0x40 +#define TXN_CTRL_BASE 0x44 #define PCI_MAX_BUS 255 #define PCI_MAX_DEVICE 31 +#define DVSEC_CTRL 0x8 #define PCI_EXT_CAP_ID 0x10 #define PASID 0x1B #define PCIE 0x1 #define PCI 0x0 +#define DVSEC 0x0023 +#define AER 0x0001 /* PCI/PCIe express extended capability structure's next capability pointer mask and cap ID mask */ @@ -87,6 +92,9 @@ #define SHITT_8BIT 8 #define MASK_BIT 1 #define PREFETCHABLE_BIT_SHIFT 3 +#define ERR_CODE_SHIFT 20 +#define FATAL_SHIFT 31 +#define ERROR_INJECT_BIT 17 #define PCI_CAP_PTR_OFFSET 8 #define PCIE_CAP_PTR_OFFSET 20 @@ -105,6 +113,9 @@ #define RID_NOT_VALID 0 #define ATS_TRIGGER 1 #define ATS_STATUS (1ul << 7) +#define TXN_INVALID 0xFFFFFFFF +#define TXN_START 1 +#define TXN_STOP 0 typedef enum { TYPE0 = 0x0, @@ -134,7 +145,10 @@ typedef enum { CFG_TXN_ATTRIBUTES = 0x7, ATS_RES_ATTRIBUTES = 0x8, TRANSACTION_TYPE = 0x9, - NUM_TRANSACTIONS = 0xA + NUM_TRANSACTIONS = 0xA, + ADDRESS_ATTRIBUTES = 0xB, + DATA_ATTRIBUTES = 0xC, + ERROR_INJECT_TYPE = 0xD } EXERCISER_PARAM_TYPE; typedef enum { @@ -170,7 +184,8 @@ typedef enum { TXN_NO_SNOOP_DISABLE = 0xa, START_TXN_MONITOR = 0xb, STOP_TXN_MONITOR = 0xc, - ATS_TXN_REQ = 0xd + ATS_TXN_REQ = 0xd, + INJECT_ERROR = 0xe } EXERCISER_OPS; typedef enum { @@ -221,6 +236,35 @@ typedef enum { EXERCISER_DATA_MMIO_SPACE = 0x3, } EXERCISER_DATA_TYPE; +typedef enum { + CORR_RCVR_ERR = 0x0, + CORR_BAD_TLP = 0x1, + CORR_BAD_DLLP = 0x2, + CORR_RPL_NUM_ROLL = 0x3, + CORR_RPL_TMR_TIMEOUT = 0x4, + CORR_ADV_NF_ERR = 0x5, + CORR_INT_ERR = 0x6, + CORR_HDR_LOG_OVRFL = 0x7, + UNCORR_DL_ERROR = 0x8, + UNCORR_SD_ERROR = 0x9, + UNCORR_PTLP_REC = 0xA, + UNCORR_FL_CTRL_ERR = 0xB, + UNCORR_CMPT_TO = 0xC, + UNCORR_AMPT_ABORT = 0xD, + UNCORR_UNEXP_CMPT = 0xE, + UNCORR_RCVR_ERR = 0xF, + UNCORR_MAL_TLP = 0x10, + UNCORR_ECRC_ERR = 0x11, + UNCORR_UR = 0x12, + UNCORR_ACS_VIOL = 0x13, + UNCORR_INT_ERR = 0x14, + UNCORR_MC_BLK_TLP = 0x15, + UNCORR_ATOP_EGR_BLK = 0x16, + UNCORR_TLP_PFX_EGR_BLK = 0x17, + UNCORR_PTLP_EGR_BLK = 0x18, + INVALID_CFG = 0x19 +} EXERCISER_ERROR_CODE; + UINT32 pal_exerciser_set_param(EXERCISER_PARAM_TYPE Type, UINT64 Value1, UINT64 Value2, UINT32 Bdf); UINT32 pal_exerciser_get_param(EXERCISER_PARAM_TYPE Type, UINT64 *Value1, UINT64 *Value2, UINT32 Bdf); UINT32 pal_exerciser_set_state(EXERCISER_STATE State, UINT64 *Value, UINT32 Bdf); diff --git a/platform/pal_uefi/src/pal_exerciser.c b/platform/pal_uefi/src/pal_exerciser.c index b479cc1b..2f9752d7 100644 --- a/platform/pal_uefi/src/pal_exerciser.c +++ b/platform/pal_uefi/src/pal_exerciser.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2018-2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2018-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -134,7 +134,7 @@ pal_exerciser_find_pcie_capability ( UINT32 *Offset ) { - UINT64 NxtPtr; + UINT64 NxtPtr = 0; UINT32 Data; UINT32 TempId; UINT64 Ecam; @@ -186,9 +186,13 @@ UINT32 pal_exerciser_set_param ( ) { UINT32 Data; + UINT32 CapabilityOffset = 0; UINT64 Base; + UINT64 Ecam; Base = pal_exerciser_get_ecsr_base(Bdf,0); + Ecam = pal_pcie_get_mcfg_ecam(); // Getting the ECAM address + switch (Type) { case SNOOP_ATTRIBUTES: @@ -257,6 +261,18 @@ UINT32 pal_exerciser_set_param ( return 1; } + case ERROR_INJECT_TYPE: + pal_exerciser_find_pcie_capability(DVSEC, Bdf, PCIE, &CapabilityOffset); + Data = pal_mmio_read(Ecam + CapabilityOffset + + pal_exerciser_get_pcie_config_offset(Bdf) + DVSEC_CTRL); + Data = ((Value1 << ERR_CODE_SHIFT) | (Value2 << FATAL_SHIFT)); + pal_mmio_write(Ecam + CapabilityOffset + DVSEC_CTRL + + pal_exerciser_get_pcie_config_offset(Bdf), Data); + if (Value1 <= 0x7) + return 2; + else + return 3; + default: return 1; } @@ -281,6 +297,11 @@ pal_exerciser_get_param ( UINT32 Status; UINT32 Temp; UINT64 Base; + UINT32 tx_attr; + UINT32 addr_low = 0; + UINT32 addr_high = 0; + UINT32 data_low = 0; + UINT32 data_high = 0; Base = pal_exerciser_get_ecsr_base(Bdf,0); switch (Type) { @@ -307,6 +328,46 @@ pal_exerciser_get_param ( case ATS_RES_ATTRIBUTES: *Value1 = pal_mmio_read(Base + ATS_ADDR); return 0; + case CFG_TXN_ATTRIBUTES: + case TRANSACTION_TYPE: + case ADDRESS_ATTRIBUTES: + case DATA_ATTRIBUTES: + /* Get the first entry and check for validity */ + tx_attr = pal_mmio_read(Base + TXN_TRACE); + if (tx_attr == TXN_INVALID) + return 1; + + /* Obtain all the recorded information of the packet in the format. + ________________________________ + | TX ATTRIBUTES | + | CFG/MEM ADDRESS_LO | + | CFG/MEM ADDRESS_HI | + | DATA_LO | + | DATA_HI | + |________________________________| + */ + addr_low = pal_mmio_read(Base + TXN_TRACE); + addr_high = pal_mmio_read(Base + TXN_TRACE); + data_low = pal_mmio_read(Base + TXN_TRACE); + data_high = pal_mmio_read(Base + TXN_TRACE); + + if (Type == CFG_TXN_ATTRIBUTES) + *Value1 = tx_attr & MASK_BIT; + + /* 0 - Read, 1 - Write */ + else if (Type == TRANSACTION_TYPE) + if (tx_attr & 0x2) + *Value2 = CFG_READ; + else + *Value2 = CFG_WRITE; + + else if (Type == ADDRESS_ATTRIBUTES) + *Value1 = addr_low | ((UINT64)addr_high << 32); + + else if (Type == DATA_ATTRIBUTES) + *Value1 = data_low | ((UINT64)data_high << 32); + + return 0; default: return 1; } @@ -361,7 +422,7 @@ pal_exerciser_ops ( { UINT64 Base; UINT64 Ecam; - UINT32 CapabilityOffset; + UINT32 CapabilityOffset = 0; UINT32 data; Base = pal_exerciser_get_ecsr_base(Bdf,0); Ecam = pal_pcie_get_mcfg_ecam(); // Getting the ECAM address @@ -440,6 +501,22 @@ pal_exerciser_ops ( pal_mmio_write(Base + ATSCTL, ATS_TRIGGER); return !(pal_mmio_read(Base + ATSCTL) & ATS_STATUS); + case START_TXN_MONITOR: + pal_mmio_write(Base + TXN_CTRL_BASE, TXN_START); + return 0; + case STOP_TXN_MONITOR: + pal_mmio_write(Base + TXN_CTRL_BASE, TXN_STOP); + return 0; + + case INJECT_ERROR: + pal_exerciser_find_pcie_capability(DVSEC, Bdf, PCIE, &CapabilityOffset); + data = pal_mmio_read(Ecam + pal_exerciser_get_pcie_config_offset(Bdf) + + CapabilityOffset + DVSEC_CTRL); + data = data | (1 << ERROR_INJECT_BIT); + pal_mmio_write(Ecam + pal_exerciser_get_pcie_config_offset(Bdf) + CapabilityOffset + + DVSEC_CTRL, data); + return Param; + default: return PCIE_CAP_NOT_FOUND; } diff --git a/test_pool/exerciser/operating_system/test_e017.c b/test_pool/exerciser/operating_system/test_e017.c new file mode 100644 index 00000000..02fe26c0 --- /dev/null +++ b/test_pool/exerciser/operating_system/test_e017.c @@ -0,0 +1,206 @@ +/** @file + * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie_enumeration.h" +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_smmu.h" +#include "val/include/sbsa_avs_memory.h" +#include "val/include/sbsa_avs_exerciser.h" + +#define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 17) +#define TEST_DESC "PE 2/4/8B writes tp PCIe as 2/4/8B" +#define TEST_RULE "S_PCIe_03" + +static uint32_t transaction_size = 4; +static uint32_t run_flag; +static uint32_t fail_cnt; + +static uint32_t test_sequence_check(uint32_t instance, uint64_t write_value) +{ + uint64_t idx; + uint64_t transaction_data; + + for (idx = 0; idx < transaction_size; idx++) { + val_exerciser_get_param(DATA_ATTRIBUTES, &transaction_data, &idx, instance); + if (transaction_data != write_value) { + val_print(AVS_PRINT_ERR, "\n Exerciser %d arrival order check failed", instance); + return 1; + } + } + + return 0; +} + +/* Performs write on 2B data */ +static uint32_t test_sequence_2B(uint16_t *addr, uint32_t instance) +{ + uint64_t idx; + uint64_t write_val = 0xABCD; + + /* Start monitoring exerciser transactions */ + if (val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance)) + return AVS_STATUS_SKIP; + + run_flag = 1; + + /* Send the transaction on incremental addresses */ + for (idx = 0; idx < transaction_size; idx++) { + /* Write transaction */ + val_mmio_write16((addr_t)addr, write_val); + addr++; + } + + /* Stop monitoring exerciser transactions */ + val_exerciser_ops(STOP_TXN_MONITOR, CFG_READ, instance); + + return test_sequence_check(instance, write_val); +} + +/* Performs write on 4B data */ +static uint32_t test_sequence_4B(uint32_t *addr, uint32_t instance) +{ + uint64_t idx; + uint64_t write_val = 0xC0DEC0DE; + + /* Start monitoring exerciser transactions */ + if (val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance)) + return AVS_STATUS_SKIP; + + run_flag = 1; + + /* Send the transaction on incremental addresses */ + for (idx = 0; idx < transaction_size; idx++) { + val_mmio_write((addr_t)addr, write_val); + addr++; + } + + /* Stop monitoring exerciser transactions */ + val_exerciser_ops(STOP_TXN_MONITOR, CFG_READ, instance); + + return test_sequence_check(instance, write_val); +} + +/* Performs write on 8B data */ +static uint32_t test_sequence_8B(uint64_t *addr, uint32_t instance) +{ + uint64_t idx; + uint64_t write_val = 0xCAFECAFECAFECAFE; + + /* Start monitoring exerciser transactions */ + if (val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance)) + return AVS_STATUS_SKIP; + + run_flag = 1; + + /* Send the transaction on incremental addresses */ + for (idx = 0; idx < transaction_size; idx++) { + /* Write transaction */ + val_mmio_write64((addr_t)addr, write_val); + addr++; + } + + /* Stop monitoring exerciser transactions */ + val_exerciser_ops(STOP_TXN_MONITOR, CFG_READ, instance); + + return test_sequence_check(instance, write_val); +} + +/* Read and Write on BAR space mapped to Device memory */ +static +void +barspace_transactions_order_check(void) +{ + uint32_t instance; + exerciser_data_t e_data; + char *baseptr; + uint32_t status; + + /* Read the number of excerciser cards */ + instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); + + while (instance-- != 0) { + + /* if init fail moves to next exerciser */ + if (val_exerciser_init(instance)) + continue; + + /* Get BAR 0 details for this instance */ + status = val_exerciser_get_data(EXERCISER_DATA_MMIO_SPACE, &e_data, instance); + if (status == NOT_IMPLEMENTED) { + val_print(AVS_PRINT_ERR, "\n pal_exerciser_get_data() for MMIO not implemented", 0); + continue; + } else if (status) { + val_print(AVS_PRINT_ERR, "\n Exerciser %d data read error ", instance); + continue; + } + + /* Map mmio space to ARM device memory in MMU page tables */ + baseptr = (char *)e_data.bar_space.base_addr; + if (!baseptr) { + val_print(AVS_PRINT_ERR, "\n Failed in BAR ioremap for instance %x", instance); + continue; + } + + /* Test Scenario 1 : Transactions on incremental aligned address */ + fail_cnt += test_sequence_2B((uint16_t *)baseptr, instance); + fail_cnt += test_sequence_4B((uint32_t *)baseptr, instance); + fail_cnt += test_sequence_8B((uint64_t *)baseptr, instance); + } +} + +static +void +payload(void) +{ + uint32_t pe_index; + + pe_index = val_pe_get_index_mpid (val_pe_get_mpid()); + + barspace_transactions_order_check(); + + if (!run_flag) { + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + if (fail_cnt) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, fail_cnt)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +e017_entry(void) +{ + uint32_t num_pe = 1; + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* Get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/exerciser/operating_system/test_e018.c b/test_pool/exerciser/operating_system/test_e018.c new file mode 100644 index 00000000..f8514267 --- /dev/null +++ b/test_pool/exerciser/operating_system/test_e018.c @@ -0,0 +1,438 @@ +/** @file + * Copyright (c) 2019-2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie_enumeration.h" +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_gic.h" +#include "val/include/sbsa_avs_iovirt.h" +#include "val/include/sbsa_avs_smmu.h" +#include "val/include/sbsa_avs_memory.h" +#include "val/include/sbsa_avs_exerciser.h" + +#define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 18) +#define TEST_DESC "RP's must support AER feature " +#define TEST_RULE "PCI_ER_01, PCI_ER_02, PCI_ER_03" + +#define ERR_CORR 0x2 +#define ERR_UNCORR 0x3 +#define CLEAR_STATUS 0xFFFFFFFF + +static uint32_t irq_pending; +static uint32_t lpi_int_id = 0x204C; +static uint32_t mask_value; + +static +void +intr_handler(void) +{ + /* Clear the interrupt pending state */ + irq_pending = 0; + + val_print(AVS_PRINT_INFO, "\n Received MSI interrupt %x ", lpi_int_id); + val_gic_end_of_interrupt(lpi_int_id); + return; +} + +/* Clear all the status bits and set the mask and severity + * @param e_bdf - Exerciser bdf + * aer_offset - AER capability offset of bdf + * mask - Whether error to be masked or not + * 0 - no mask 0xFFFFFFFF - mask all errors + * severity - Whether error is fatal or non-fatal + * 0 - non-fatal 0xFFFFFFFF - fatal + **/ +static void +clear_status_bits(uint32_t e_bdf, uint32_t aer_offset, uint32_t mask, uint32_t severity) +{ + + /* Clear all status bits of Correctable and Unconrrectable errors */ + val_pcie_write_cfg(e_bdf, aer_offset + AER_UNCORR_STATUS_OFFSET, CLEAR_STATUS); + val_pcie_write_cfg(e_bdf, aer_offset + AER_CORR_STATUS_OFFSET, CLEAR_STATUS); + + /* Mask or UnMask all errors */ + val_pcie_write_cfg(e_bdf, aer_offset + AER_UNCORR_MASK_OFFSET, mask); + val_pcie_write_cfg(e_bdf, aer_offset + AER_CORR_MASK_OFFSET, mask); + val_pcie_write_cfg(e_bdf, aer_offset + AER_UNCORR_SEVR_OFFSET, severity); +} + +static uint32_t +correctable_err_status_chk(uint32_t e_bdf, uint32_t aer_offset, uint32_t err_code) +{ + uint32_t erp_bdf, reg_bdf, rp_aer_offset; + uint32_t value, err_bit; + uint32_t pciecs_base, reg_value; + uint32_t fail_cnt = 0; + + val_pcie_get_rootport(e_bdf, &erp_bdf); + val_pcie_find_capability(erp_bdf, PCIE_ECAP, ECID_AER, &rp_aer_offset); + err_bit = val_get_exerciser_err_info(err_code); + + /* Check if corresponding error bit is set */ + val_pcie_read_cfg(e_bdf, aer_offset + AER_CORR_STATUS_OFFSET, &value); + if (!((value >> err_bit) & 0x1)) + { + val_print(AVS_PRINT_ERR, "\n Err bit for error not set", 0); + fail_cnt++; + } + + /* Check if the RP has received the corresponding error type if error is not masked */ + val_pcie_read_cfg(erp_bdf, rp_aer_offset + AER_ROOT_ERR_OFFSET, &value); + if ((mask_value == 0) && ((value & 0x1) == 0)) + { + val_print(AVS_PRINT_ERR, "\n Root error status not set", 0); + fail_cnt++; + } + + if ((mask_value == 1) && ((value & 0x1) == 1)) + { + val_print(AVS_PRINT_ERR, "\n Root error status set when error is masked", 0); + fail_cnt++; + } + + /* Check if the Reg ID matches with the error source ID */ + val_pcie_read_cfg(erp_bdf, rp_aer_offset + AER_ROOT_ERR_SOURCE_ID, &value); + reg_bdf = PCIE_CREATE_BDF_PACKED(e_bdf); + if ((mask_value == 0) && ((value & AER_SOURCE_ID_MASK) != reg_bdf)) + { + val_print(AVS_PRINT_ERR, "\n Error source Identification failed", 0); + fail_cnt++; + } + + /* Check if the appropriate status bit is set in Device status register */ + val_pcie_find_capability(e_bdf, PCIE_CAP, CID_PCIECS, &pciecs_base); + val_pcie_read_cfg(e_bdf, pciecs_base + DCTLR_OFFSET, ®_value); + if (!((reg_value >> DSTS_SHIFT) & 0x1)) + { + val_print(AVS_PRINT_ERR, "\n Device reg of EP not set %x ", reg_value); + fail_cnt++; + } + + /* Clear the Error status bit in the RP */ + val_pcie_write_cfg(erp_bdf, rp_aer_offset + AER_ROOT_ERR_OFFSET, 0x1); + val_pcie_read_cfg(erp_bdf, rp_aer_offset + AER_ROOT_ERR_OFFSET, &value); + if ((value & 0x1)) + { + val_print(AVS_PRINT_ERR, "\n Err bit is not cleared %x ", value); + fail_cnt++; + } + + if (fail_cnt) + return 1; + + return 0; +} + +static uint32_t +uncorrectable_error_chk(uint32_t e_bdf, uint32_t aer_offset, uint32_t err_code) +{ + uint32_t erp_bdf, reg_bdf, rp_aer_offset; + uint32_t value, err_bit; + uint32_t pciecs_base, reg_value; + uint32_t fail_cnt = 0; + + val_pcie_get_rootport(e_bdf, &erp_bdf); + val_pcie_find_capability(erp_bdf, PCIE_ECAP, ECID_AER, &rp_aer_offset); + err_bit = val_get_exerciser_err_info(err_code); + + /* Check if corresponding error bit is set */ + val_pcie_read_cfg(e_bdf, aer_offset + AER_UNCORR_STATUS_OFFSET, &value); + if (!((value >> err_bit) & 0x1)) + { + val_print(AVS_PRINT_ERR, "\n Err bit not set %x", value); + fail_cnt++; + } + + /* Check if the RP has received the corresponding error type if error is not masked */ + val_pcie_read_cfg(erp_bdf, rp_aer_offset + AER_ROOT_ERR_OFFSET, &value); + if ((mask_value == 0) && ((value & 0x4) == 0)) + { + val_print(AVS_PRINT_ERR, "\n Root Error status not set", 0); + fail_cnt++; + } + + if ((mask_value == 1) && ((value & 0x4) == 0x4)) + { + val_print(AVS_PRINT_ERR, "\n Root error status set when error is masked", 0); + fail_cnt++; + } + + /* Check if the Reg ID matches with the error source ID */ + val_pcie_read_cfg(erp_bdf, rp_aer_offset + AER_ROOT_ERR_SOURCE_ID, &value); + reg_bdf = PCIE_CREATE_BDF_PACKED(e_bdf); + if ((mask_value == 0) && (((value >> AER_SOURCE_ID_SHIFT) & AER_SOURCE_ID_MASK) != reg_bdf)) + { + val_print(AVS_PRINT_ERR, "\n Error source Identification failed", 0); + fail_cnt++; + } + + /* Check if the appropriate status bit is set in Device status register */ + val_pcie_find_capability(e_bdf, PCIE_CAP, CID_PCIECS, &pciecs_base); + val_pcie_read_cfg(e_bdf, pciecs_base + DCTLR_OFFSET, ®_value); + if (!((reg_value >> DSTS_SHIFT) & DS_UNCORR_MASK)) + { + val_print(AVS_PRINT_ERR, "\n Device reg of EP not set", 0); + fail_cnt++; + } + + /* Clear the Error status bit in the RP */ + val_pcie_write_cfg(erp_bdf, rp_aer_offset + AER_ROOT_ERR_OFFSET, 0x7F); + val_pcie_read_cfg(erp_bdf, rp_aer_offset + AER_ROOT_ERR_OFFSET, &value); + if ((value & 0x7F)) + { + val_print(AVS_PRINT_ERR, "\n Err bit is not cleared %x", value); + fail_cnt++; + } + + if (fail_cnt) + return 1; + + return 0; + +} + +static +uint32_t +inject_error(uint32_t e_bdf, uint32_t instance, uint32_t aer_offset) +{ + uint32_t err_code; + uint32_t status, value; + uint32_t res, timeout; + + for (err_code = 0; err_code <= ERR_CNT; err_code++) + { + irq_pending = 1; + + status = val_exerciser_set_param(ERROR_INJECT_TYPE, err_code, 0, instance); + value = val_exerciser_ops(INJECT_ERROR, err_code, instance); + + /*Interrupt should be generated on error detection if errors are not masked*/ + if (mask_value == 0) { + timeout = TIMEOUT_LARGE; + while ((--timeout > 0) && irq_pending) + {}; + + if (timeout == 0) + { + val_gic_free_irq(irq_pending, 0); + val_print(AVS_PRINT_ERR, "\n Intr not trigerred on err injection bdf 0x%x", e_bdf); + return 1; + } + } + + /* Check if error injected is correctable or uncorrectable*/ + if (status == ERR_CORR) { + val_print(AVS_PRINT_INFO, "\n Correctable error recieved", 0); + res = correctable_err_status_chk(e_bdf, aer_offset, value); + if (res) { + val_print(AVS_PRINT_ERR, "\n Correctable error check failed for bdf %x", e_bdf); + return 1; + } + } + + else if (status == ERR_UNCORR) { + val_print(AVS_PRINT_INFO, "\n UnCorrectable error recieved", 0); + res = uncorrectable_error_chk(e_bdf, aer_offset, value); + if (res) { + val_print(AVS_PRINT_ERR, "\n Uncorrectable error check failed for bdf %x", e_bdf); + return 1; + } + } + } + + return 0; +} + + +static +void +payload(void) +{ + + uint32_t instance; + uint32_t pe_index; + uint32_t e_bdf; + uint32_t erp_bdf; + uint32_t aer_offset; + uint32_t rp_aer_offset; + uint32_t value = 0; + uint32_t reg_value = 0; + uint32_t test_skip = 1; + + uint32_t status; + uint32_t device_id = 0; + uint32_t stream_id = 0; + uint32_t its_id = 0; + uint32_t msi_index = 0; + uint32_t msi_cap_offset = 0; + uint32_t dpc_cap_base = 0; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); + + while (instance-- != 0) { + + /* if init fail moves to next exerciser */ + if (val_exerciser_init(instance)) + continue; + + e_bdf = val_exerciser_get_bdf(instance); + val_pcie_enable_eru(e_bdf); + if (val_pcie_get_rootport(e_bdf, &erp_bdf)) + continue; + + val_pcie_enable_eru(erp_bdf); + + /*Check AER capability for exerciser and its RP */ + if (val_pcie_find_capability(e_bdf, PCIE_ECAP, ECID_AER, &aer_offset) != PCIE_SUCCESS) { + val_print(AVS_PRINT_ERR, "\n No AER Capability, Skipping for Bdf : 0x%x", e_bdf); + continue; + } + + if (val_pcie_find_capability(erp_bdf, PCIE_ECAP, ECID_AER, &rp_aer_offset) != PCIE_SUCCESS) { + val_print(AVS_PRINT_ERR, "\n AER Capability not supported for RP : 0x%x", erp_bdf); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* Check DPC capability */ + status = val_pcie_find_capability(erp_bdf, PCIE_ECAP, ECID_DPC, &dpc_cap_base); + if (status == PCIE_CAP_NOT_FOUND) + { + val_print(AVS_PRINT_ERR, "\n ECID_DPC not found", 0); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* Warn if DPC enabled */ + val_pcie_read_cfg(erp_bdf, dpc_cap_base + DPC_CTRL_OFFSET, ®_value); + if ((reg_value & 0x3) != 0) + val_print(AVS_PRINT_WARN, "\n DPC enabled for bdf : 0x%x", erp_bdf); + + + /* Search for MSI-X Capability */ + if (val_pcie_find_capability(e_bdf, PCIE_CAP, CID_MSIX, &msi_cap_offset)) { + val_print(AVS_PRINT_ERR, "\n No MSI-X Capability, Skipping for Bdf 0x%x", e_bdf); + continue; + } + + if (val_pcie_find_capability(erp_bdf, PCIE_CAP, CID_MSIX, &msi_cap_offset)) { + val_print(AVS_PRINT_ERR, "\n No MSI-X Capability for RP Bdf 0x%x", erp_bdf); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* Get DeviceID & ITS_ID for this device */ + status = val_iovirt_get_device_info(PCIE_CREATE_BDF_PACKED(erp_bdf), + PCIE_EXTRACT_BDF_SEG(erp_bdf), &device_id, + &stream_id, &its_id); + + if (status) { + val_print(AVS_PRINT_ERR, "\n iovirt_get_device failed for bdf 0x%x", e_bdf); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* MSI assignment */ + status = val_gic_request_msi(erp_bdf, device_id, its_id, lpi_int_id + instance, msi_index); + if (status) { + val_print(AVS_PRINT_ERR, "\n MSI Assignment failed for bdf : 0x%x", erp_bdf); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } + + status = val_gic_install_isr(lpi_int_id + instance, intr_handler); + + if (status) { + val_print(AVS_PRINT_ERR, "\n Intr handler registration failed: 0x%x", lpi_int_id); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } + + test_skip = 0; + val_pcie_find_capability(erp_bdf, PCIE_ECAP, ECID_AER, &rp_aer_offset); + val_pcie_read_cfg(erp_bdf, rp_aer_offset + AER_ROOT_ERR_CMD_OFFSET, &value); + val_pcie_write_cfg(erp_bdf, rp_aer_offset + AER_ROOT_ERR_CMD_OFFSET, (value | 0x7)); + + /* Errors not masked and severity is non-fatal */ + mask_value = 0; + clear_status_bits(e_bdf, aer_offset, 0, 0); + if (inject_error(e_bdf, instance, aer_offset)) + { + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03)); + return; + } + + /* Errors masked and severity is non-fatal */ + mask_value = 1; + clear_status_bits(e_bdf, aer_offset, AER_ERROR_MASK, 0); + if (inject_error(e_bdf, instance, aer_offset)) + { + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 04)); + return; + } + mask_value = 0; + + /* Errors not masked and severity is fatal */ + clear_status_bits(e_bdf, aer_offset, 0, AER_UNCORR_SEVR_FATAL); + if (inject_error(e_bdf, instance, aer_offset)) + { + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 05)); + return; + } + + /* Disable error reporting of Exerciser and upstream Root Port */ + val_pcie_disable_eru(e_bdf); + val_pcie_disable_eru(erp_bdf); + + /* + * Clear unsupported request detected bit in Exerciser upstream + * Rootport's Device Status Register to clear any pending urd status. + */ + val_pcie_clear_urd(erp_bdf); + val_gic_free_msi(erp_bdf, device_id, its_id, lpi_int_id + instance, msi_index); + } + + if (test_skip == 1) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + + return; + +} + +uint32_t +e018_entry(void) +{ + uint32_t num_pe = 1; + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* Get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/exerciser/operating_system/test_e019.c b/test_pool/exerciser/operating_system/test_e019.c new file mode 100644 index 00000000..1d9ea2df --- /dev/null +++ b/test_pool/exerciser/operating_system/test_e019.c @@ -0,0 +1,362 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie_enumeration.h" +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pcie_spec.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_smmu.h" +#include "val/include/sbsa_avs_iovirt.h" +#include "val/include/sbsa_avs_memory.h" +#include "val/include/sbsa_avs_exerciser.h" + +#define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 19) +#define TEST_DESC "RP's must support DPC " +#define TEST_RULE "PCI_ER_05, PCI_ER_06" + +#define ERR_FATAL 1 +#define ERR_FATAL_NONFATAL 2 +#define ERR_UNCORR 0x3 + +static uint32_t msg_type[] = {ERR_FATAL_NONFATAL, ERR_FATAL}; +static uint32_t irq_pending; +static uint32_t lpi_int_id = 0x204C; + +static +void +intr_handler(void) +{ + /* Clear the interrupt pending state */ + irq_pending = 0; + + val_print(AVS_PRINT_INFO, "\n Received MSI interrupt %x ", lpi_int_id); + val_gic_end_of_interrupt(lpi_int_id); + return; +} + +static +void +payload(void) +{ + + uint32_t pe_index; + uint32_t e_bdf; + uint32_t erp_bdf; + uint32_t reg_value; + uint32_t instance; + uint32_t fail_cnt; + uint32_t test_skip = 1; + uint32_t status; + uint32_t dpc_cap_base; + uint32_t rp_dpc_cap_base; + uint32_t aer_offset; + uint32_t rp_aer_offset; + uint32_t error_source_id; + uint32_t source_id; + uint32_t dpc_trigger_reason; + uint32_t timeout; + + uint32_t device_id = 0; + uint32_t stream_id = 0; + uint32_t its_id = 0; + uint32_t msi_index = 0; + uint32_t msi_cap_offset = 0; + + void *cfg_space_buf; + addr_t cfg_space_addr; + uint32_t idx; + cfg_space_buf = NULL; + + fail_cnt = 0; + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); + + while (instance-- != 0) + { + if (val_exerciser_init(instance)) + continue; + + e_bdf = val_exerciser_get_bdf(instance); + + val_pcie_enable_eru(e_bdf); + + if (val_pcie_get_rootport(e_bdf, &erp_bdf)) + continue; + + val_pcie_enable_eru(erp_bdf); + + /* Check DPC capability */ + status = val_pcie_find_capability(erp_bdf, PCIE_ECAP, ECID_DPC, &rp_dpc_cap_base); + if (status == PCIE_CAP_NOT_FOUND) + { + val_print(AVS_PRINT_ERR, "\n ECID_DPC not found", 0); + continue; + } + + status = val_pcie_find_capability(e_bdf, PCIE_ECAP, ECID_DPC, &dpc_cap_base); + test_skip = 0; + + /* Check AER capability for both exerciser and RP */ + if (val_pcie_find_capability(e_bdf, PCIE_ECAP, ECID_AER, &aer_offset) != PCIE_SUCCESS) { + val_print(AVS_PRINT_ERR, "\n AER Capability not supported, Bdf : 0x%x", e_bdf); + continue; + } + + if (val_pcie_find_capability(erp_bdf, PCIE_ECAP, ECID_AER, &rp_aer_offset) != PCIE_SUCCESS) { + val_print(AVS_PRINT_ERR, "\n AER Capability not supported for RP : 0x%x", erp_bdf); + fail_cnt++; + } + + /* Search for MSI-X Capability */ + if (val_pcie_find_capability(e_bdf, PCIE_CAP, CID_MSIX, &msi_cap_offset)) { + val_print(AVS_PRINT_ERR, "\n No MSI-X Capability, Skipping for Bdf 0x%x", e_bdf); + continue; + } + + /* Get DeviceID & ITS_ID for this device */ + status = val_iovirt_get_device_info(PCIE_CREATE_BDF_PACKED(erp_bdf), + PCIE_EXTRACT_BDF_SEG(erp_bdf), &device_id, + &stream_id, &its_id); + + if (status) { + val_print(AVS_PRINT_ERR, "\n iovirt_get_device failed for bdf 0x%x", e_bdf); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* Get DeviceID & ITS_ID for this device */ + status = val_gic_request_msi(erp_bdf, device_id, its_id, lpi_int_id + instance, msi_index); + if (status) { + val_print(AVS_PRINT_ERR, "\n MSI Assignment failed for bdf : 0x%x", erp_bdf); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 2)); + return; + } + + status = val_gic_install_isr(lpi_int_id + instance, intr_handler); + + if (status) { + val_print(AVS_PRINT_ERR, "\n Intr handler registration failed: 0x%x", lpi_int_id); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } + + status = val_exerciser_set_param(ERROR_INJECT_TYPE, UNCORR_CMPT_TO, 1, instance); + if (status != ERR_UNCORR) { + val_print(AVS_PRINT_ERR, "\n Error Injection failed, Bdf : 0x%x", e_bdf); + continue; + } + + /* check for both fatal and non-fatal error */ + for (int i = 0; i < 2; i++) + { + val_pcie_data_link_layer_status(erp_bdf); + cfg_space_buf = val_memory_alloc(PCIE_CFG_SIZE); + if (cfg_space_buf == NULL) + { + val_print(AVS_PRINT_ERR, "\n Memory allocation failed.", 0); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } + + /* Get configuration space address for EP */ + cfg_space_addr = val_pcie_get_bdf_config_addr(e_bdf); + val_print(AVS_PRINT_INFO, "\n EP BDF 0x%x : ", e_bdf); + val_print(AVS_PRINT_INFO, "Config space addr 0x%x", cfg_space_addr); + + /* Save the EP config space to restore after Secondary Bus Reset */ + for (idx = 0; idx < PCIE_CFG_SIZE/4; idx++) { + *((uint32_t *)cfg_space_buf + idx) = *((uint32_t *)cfg_space_addr + idx); + } + + irq_pending = 1; + val_pcie_read_cfg(erp_bdf, rp_dpc_cap_base + DPC_CTRL_OFFSET, ®_value); + reg_value &= DPC_DISABLE_MASK; + reg_value |= DPC_INTR_ENABLE; + reg_value = reg_value | (msg_type[i] << DPC_CTRL_TRG_EN_SHIFT); + val_pcie_write_cfg(erp_bdf, rp_dpc_cap_base + DPC_CTRL_OFFSET, reg_value); + + val_pcie_read_cfg(erp_bdf, rp_dpc_cap_base + DPC_CTRL_OFFSET, ®_value); + + if (msg_type[i] == ERR_FATAL) + { + val_pcie_write_cfg(e_bdf, aer_offset + AER_UNCORR_SEVR_OFFSET, AER_UNCORR_SEVR_FATAL); + val_pcie_write_cfg(e_bdf, aer_offset + AER_UNCORR_MASK_OFFSET, 0x0); + } + else + { + val_pcie_write_cfg(e_bdf, aer_offset + AER_UNCORR_SEVR_OFFSET, 0x0); + } + + /*Inject error immediately*/ + val_exerciser_ops(INJECT_ERROR, CFG_READ, instance); + + val_pcie_read_cfg(e_bdf, CFG_READ, ®_value); + if (reg_value != PCIE_UNKNOWN_RESPONSE) + { + val_print(AVS_PRINT_ERR, "\n EP not contained due to DPC", 0); + fail_cnt++; + } + + val_pcie_read_cfg(erp_bdf, rp_dpc_cap_base + DPC_STATUS_OFFSET, ®_value); + + /* Check DPC Trigger status */ + if ((reg_value & 1) == 0) + { + val_print(AVS_PRINT_ERR, "\n DPC Trigger status bit not set %x", reg_value); + fail_cnt++; + } + + dpc_trigger_reason = (reg_value & DPC_TRIGGER_MASK) >> 1; + if (msg_type[i] == ERR_FATAL) + { + if (dpc_trigger_reason != 2) + { + val_print(AVS_PRINT_ERR, "\n DPC Trigger reason incorrect", 0); + fail_cnt++; + } + } else { + if (dpc_trigger_reason != 1) + { + val_print(AVS_PRINT_ERR, "\n DPC Trigger reason incorrect", 0); + fail_cnt++; + } + } + + source_id = PCIE_CREATE_BDF_PACKED(e_bdf); + error_source_id = (reg_value >> DPC_SOURCE_ID_SHIFT); + if (source_id != error_source_id) + { + val_print(AVS_PRINT_ERR, "\n DPC Error source Identification failed", 0); + fail_cnt++; + } + + timeout = TIMEOUT_LARGE; + while ((--timeout > 0) && irq_pending) + {}; + + if (timeout == 0) { + val_gic_free_irq(irq_pending, 0); + val_print(AVS_PRINT_ERR, "\n Interrupt trigger failed for bdf 0x%lx", e_bdf); + fail_cnt++; + continue; + } + + val_pcie_read_cfg(erp_bdf, rp_dpc_cap_base + DPC_STATUS_OFFSET, ®_value); + while (reg_value & 0x10) + {}; + val_pcie_write_cfg(erp_bdf, rp_dpc_cap_base + DPC_STATUS_OFFSET, 1); + + val_pcie_read_cfg(erp_bdf, TYPE01_ILR, ®_value); + reg_value = reg_value | BRIDGE_CTRL_SBR_SET; + val_pcie_write_cfg(erp_bdf, TYPE01_ILR, reg_value); + + /* Wait for Timeout */ + val_time_delay_ms(2 * ONE_MILLISECOND); + + val_pcie_read_cfg(erp_bdf, TYPE01_ILR, ®_value); + reg_value = reg_value & ~BRIDGE_CTRL_SBR_SET; + val_pcie_write_cfg(erp_bdf, TYPE01_ILR, reg_value); + + timeout = TIMEOUT_LARGE; + while (--timeout) + {}; + + status = val_pcie_data_link_layer_status(erp_bdf); + if (status != PCIE_DLL_LINK_ACTIVE_NOT_SUPPORTED) + { + if (!status) + { + /* Wait for for additional Timeout and check the status*/ + uint32_t delay_status = val_time_delay_ms(100 * ONE_MILLISECOND); + if (!delay_status) + { + val_print(AVS_PRINT_ERR, "\n Failed to time delay for BDF 0x%x ", erp_bdf); + val_memory_free(cfg_space_buf); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } + + status = val_pcie_data_link_layer_status(erp_bdf); + } + } + + if (status == PCIE_DLL_LINK_STATUS_NOT_ACTIVE) + { + val_print(AVS_PRINT_ERR, "\nThe link not active after reset for BDF 0x%x: ", erp_bdf); + return ; + } + + /*Disable the DPC*/ + + val_pcie_read_cfg(erp_bdf, rp_dpc_cap_base + DPC_STATUS_OFFSET, ®_value); + val_pcie_write_cfg(erp_bdf, rp_dpc_cap_base + DPC_STATUS_OFFSET, reg_value | 0x1); + + val_pcie_read_cfg(e_bdf, dpc_cap_base + DPC_STATUS_OFFSET, ®_value); + val_pcie_write_cfg(e_bdf, dpc_cap_base + DPC_STATUS_OFFSET, reg_value | 0x1); + + val_pcie_read_cfg(erp_bdf, rp_dpc_cap_base + DPC_CTRL_OFFSET, ®_value); + val_pcie_write_cfg(erp_bdf, rp_dpc_cap_base + DPC_CTRL_OFFSET, reg_value & 0xFFFCFFFF); + + val_pcie_read_cfg(e_bdf, aer_offset + AER_UNCORR_STATUS_OFFSET, ®_value); + val_pcie_write_cfg(e_bdf, aer_offset + AER_UNCORR_STATUS_OFFSET, reg_value & 0xFFFFFFFF); + + val_pcie_read_cfg(e_bdf, CFG_READ, ®_value); + if (reg_value == PCIE_UNKNOWN_RESPONSE) + { + val_print(AVS_PRINT_ERR, "\n EP not recovered from DPC", 0); + fail_cnt++; + } + + /* Restore EP Config Space */ + for (idx = 0; idx < PCIE_CFG_SIZE/4; idx++) { + *((uint32_t *)cfg_space_addr + idx) = *((uint32_t *)cfg_space_buf + idx); + } + + } + + } + if (test_skip) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + else if (fail_cnt) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, fail_cnt)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + + return; + +} + +uint32_t +e019_entry(void) +{ + uint32_t num_pe = 1; + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* Get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/test_pool/exerciser/operating_system/test_e020.c b/test_pool/exerciser/operating_system/test_e020.c new file mode 100644 index 00000000..6baf5e3e --- /dev/null +++ b/test_pool/exerciser/operating_system/test_e020.c @@ -0,0 +1,254 @@ +/** @file + * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie_enumeration.h" +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_smmu.h" +#include "val/include/sbsa_avs_memory.h" +#include "val/include/sbsa_avs_exerciser.h" +#include "val/include/sbsa_avs_pcie.h" + +#define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 20) +#define TEST_DESC "Check 2/4/8 Bytes targeted writes" +#define TEST_RULE "S_PCIe_04" + + +static +uint32_t +get_target_exer_bdf(uint32_t req_rp_bdf, uint32_t *tgt_e_bdf, + uint32_t *tgt_rp_bdf, uint64_t *bar_base, uint32_t *tgt_instance) +{ + + uint32_t erp_bdf; + uint32_t e_bdf; + uint32_t instance; + uint32_t req_rp_ecam_index; + uint32_t erp_ecam_index; + uint32_t status; + + instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); + + while (instance-- != 0) + { + /* if init fail moves to next exerciser */ + if (val_exerciser_init(instance)) + continue; + + e_bdf = val_exerciser_get_bdf(instance); + + /* Read e_bdf BAR Register to get the Address to perform P2P */ + /* If No BAR Space, continue */ + val_pcie_get_mmio_bar(e_bdf, bar_base); + if (*bar_base == 0) + continue; + + /* Get RP of the exerciser */ + if (val_pcie_get_rootport(e_bdf, &erp_bdf)) + continue; + + if (req_rp_bdf != erp_bdf) + { + status = val_pcie_get_ecam_index(req_rp_bdf, &req_rp_ecam_index); + if (status) + { + val_print(AVS_PRINT_ERR, "\n Error Ecam index for req RP BDF: 0x%x", req_rp_bdf); + goto clean_fail; + } + + status = val_pcie_get_ecam_index(erp_bdf, &erp_ecam_index); + if (status) + { + val_print(AVS_PRINT_ERR, "\n Error Ecam index for tgt RP BDF: 0x%x", erp_bdf); + goto clean_fail; + } + + if (req_rp_ecam_index != erp_ecam_index) + continue; + + *tgt_e_bdf = e_bdf; + *tgt_rp_bdf = erp_bdf; + + /* Enable Bus Master Enable */ + val_pcie_enable_bme(e_bdf); + /* Enable Memory Space Access */ + val_pcie_enable_msa(e_bdf); + + *tgt_instance = instance; + + return AVS_STATUS_PASS; + } + } + +clean_fail: + /* Return failure if No Such Exerciser Found */ + *tgt_e_bdf = 0; + *tgt_rp_bdf = 0; + *bar_base = 0; + return AVS_STATUS_FAIL; +} + +static +uint32_t +check_sequence(uint64_t dma_buffer, uint32_t tgt_instance, uint32_t req_instance, + uint64_t bar_base, uint32_t size) +{ + uint32_t status; + uint64_t transaction_data; + uint64_t idx; + + /* Copy the contents of the memory to requestor exercise's memory */ + val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)dma_buffer, size, req_instance); + val_exerciser_ops(START_DMA, EDMA_TO_DEVICE, req_instance); + + /* Set the destination buffer as BAR base address of target exerciser */ + val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)bar_base, size, req_instance); + + /* Start the transaction monitoring in the target exerciser */ + status = val_exerciser_ops(START_TXN_MONITOR, CFG_READ, tgt_instance); + if (status == PCIE_CAP_NOT_FOUND) + { + val_print(AVS_PRINT_ERR, "\n Transaction Monitoring capability not found", 0); + return 1; + } + + /* Copy the contents from requestor exerciser to target exerciser's BAR address */ + val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, req_instance); + + /* Stop the transaction monitoring in the target exerciser */ + status = val_exerciser_ops(STOP_TXN_MONITOR, CFG_READ, tgt_instance); + if (status == PCIE_CAP_NOT_FOUND) + { + val_print(AVS_PRINT_ERR, "\n Transaction Monitoring capability not found", 0); + return 1; + } + + /* Compare the transaction data */ + val_exerciser_get_param(DATA_ATTRIBUTES, &transaction_data, &idx, tgt_instance); + if (val_memory_compare(&transaction_data, &dma_buffer, size)) + { + val_print(AVS_PRINT_ERR, "\nData mismatch for target exerciser instance: %x", tgt_instance); + val_print(AVS_PRINT_ERR, " with value: %x", transaction_data); + return 1; + } + + return 0; +} + +static +void +payload(void) +{ + + uint32_t status; + uint32_t pe_index; + uint32_t req_instance; + uint32_t fail_cnt; + uint32_t test_skip; + uint32_t req_e_bdf, req_rp_bdf, tgt_e_bdf, tgt_rp_bdf, tgt_instance; + uint64_t bar_base; + uint64_t dma_buffer = 0xABCDC0DEABCDC0DE; + + + fail_cnt = 0; + test_skip = 1; + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + req_instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); + + status = val_pcie_p2p_support(); + /* Check If PCIe Hierarchy supports P2P. */ + if (status) { + val_print(AVS_PRINT_DEBUG, "\nPCIe hierarchy does not support P2P: %x", status); + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + + while (req_instance-- != 0) + { + + /* if init fail moves to next exerciser */ + if (val_exerciser_init(req_instance)) + continue; + + req_e_bdf = val_exerciser_get_bdf(req_instance); + + /* Get RP of the exerciser */ + if (val_pcie_get_rootport(req_e_bdf, &req_rp_bdf)) + continue; + + /* Find another exerciser on other rootport, + Break from the test if no such exerciser if found */ + if (get_target_exer_bdf(req_rp_bdf, &tgt_e_bdf, &tgt_rp_bdf, &bar_base, &tgt_instance)) + continue; + + test_skip = 0; + + status = check_sequence(dma_buffer, tgt_instance, req_instance, bar_base, 2); + if (status) + { + val_print(AVS_PRINT_ERR, "\nFailed for 2B transaction from exerciser: %x", req_instance); + fail_cnt++; + } + + status = check_sequence(dma_buffer, tgt_instance, req_instance, bar_base, 4); + if (status) + { + val_print(AVS_PRINT_ERR, "\nFailed for 4B transaction from exerciser: %x", req_instance); + fail_cnt++; + } + + status = check_sequence(dma_buffer, tgt_instance, req_instance, bar_base, 8); + if (status) + { + val_print(AVS_PRINT_ERR, "\nFailed for 8B transaction from exerciser: %x", req_instance); + fail_cnt++; + } + + } + + if (test_skip == 1) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + else if (fail_cnt) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, fail_cnt)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + + return; + +} + +uint32_t +e020_entry(void) +{ + uint32_t num_pe = 1; + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level, TEST_RULE); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* Get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM), TEST_RULE); + + return status; +} diff --git a/uefi_app/SbsaAvs.inf b/uefi_app/SbsaAvs.inf index 61d05276..b07490eb 100644 --- a/uefi_app/SbsaAvs.inf +++ b/uefi_app/SbsaAvs.inf @@ -148,6 +148,10 @@ ../test_pool/exerciser/test_e014.c ../test_pool/exerciser/test_e015.c ../test_pool/exerciser/test_e016.c + ../test_pool/exerciser/operating_system/test_e017.c + ../test_pool/exerciser/operating_system/test_e018.c + ../test_pool/exerciser/operating_system/test_e019.c + ../test_pool/exerciser/operating_system/test_e020.c ../test_pool/mpam/operating_system/test_mpam001.c ../test_pool/mpam/operating_system/test_mpam002.c diff --git a/uefi_app/SbsaAvsNist.inf b/uefi_app/SbsaAvsNist.inf index a6769aa8..a5a54a95 100644 --- a/uefi_app/SbsaAvsNist.inf +++ b/uefi_app/SbsaAvsNist.inf @@ -148,6 +148,10 @@ ../test_pool/exerciser/test_e014.c ../test_pool/exerciser/test_e015.c ../test_pool/exerciser/test_e016.c + ../test_pool/exerciser/operating_system/test_e017.c + ../test_pool/exerciser/operating_system/test_e018.c + ../test_pool/exerciser/operating_system/test_e019.c + ../test_pool/exerciser/operating_system/test_e020.c ../test_pool/mpam/operating_system/test_mpam001.c ../test_pool/mpam/operating_system/test_mpam002.c diff --git a/val/include/sbsa_avs_exerciser.h b/val/include/sbsa_avs_exerciser.h index 8d807351..1c94c9be 100644 --- a/val/include/sbsa_avs_exerciser.h +++ b/val/include/sbsa_avs_exerciser.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -28,6 +28,32 @@ #define MASTER_ABORT_MASK 0x20000000 #define MASTER_ABORT_SHIFT 29 +#define CORR_RCVR_ERR_OFFSET 0 +#define CORR_BAD_TLP_OFFSET 6 +#define CORR_BAD_DLLP_OFFSET 7 +#define CORR_RPL_NUM_ROLL_OFFSET 8 +#define CORR_RPL_TMR_TIMEOUT_OFFSET 12 +#define CORR_ADV_NF_ERR_OFFSET 13 +#define CORR_INT_ERR_OFFSET 14 +#define CORR_HDR_LOG_OVRFL_OFFSET 15 +#define UNCORR_DL_ERROR_OFFSET 4 +#define UNCORR_SD_ERROR_OFFSET 5 +#define UNCORR_PTLP_REC_OFFSET 12 +#define UNCORR_FL_CTRL_ERR_OFFSET 13 +#define UNCORR_CMPT_TO_OFFSET 14 +#define UNCORR_AMPT_ABORT_OFFSET 15 +#define UNCORR_UNEXP_CMPT_OFFSET 16 +#define UNCORR_RCVR_ERR_OFFSET 17 +#define UNCORR_MAL_TLP_OFFSET 18 +#define UNCORR_ECRC_ERR_OFFSET 19 +#define UNCORR_UR_OFFSET 20 +#define UNCORR_ACS_VIOL_OFFSET 21 +#define UNCORR_INT_ERR_OFFSET 22 +#define UNCORR_MC_BLK_TLP_OFFSET 23 +#define UNCORR_ATOP_EGR_BLK_OFFSET 24 +#define UNCORR_TLP_PFX_EGR_BLK_OFFSET 25 +#define UNCORR_PTLP_EGR_BLK_OFFSET 26 + typedef struct { uint32_t bdf; uint32_t initialized; @@ -42,8 +68,36 @@ typedef enum { EXERCISER_NUM_CARDS = 0x1 } EXERCISER_INFO_TYPE; +typedef enum { + CORR_RCVR_ERR = 0x0, + CORR_BAD_TLP = 0x1, + CORR_BAD_DLLP = 0x2, + CORR_RPL_NUM_ROLL = 0x3, + CORR_RPL_TMR_TIMEOUT = 0x4, + CORR_ADV_NF_ERR = 0x5, + CORR_INT_ERR = 0x6, + CORR_HDR_LOG_OVRFL = 0x7, + UNCORR_DL_ERROR = 0x8, + UNCORR_SD_ERROR = 0x9, + UNCORR_PTLP_REC = 0xA, + UNCORR_FL_CTRL_ERR = 0xB, + UNCORR_CMPT_TO = 0xC, + UNCORR_AMPT_ABORT = 0xD, + UNCORR_UNEXP_CMPT = 0xE, + UNCORR_RCVR_ERR = 0xF, + UNCORR_MAL_TLP = 0x10, + UNCORR_ECRC_ERR = 0x11, + UNCORR_UR = 0x12, + UNCORR_ACS_VIOL = 0x13, + UNCORR_INT_ERR = 0x14, + UNCORR_MC_BLK_TLP = 0x15, + UNCORR_ATOP_EGR_BLK = 0x16, + UNCORR_TLP_PFX_EGR_BLK = 0x17, + UNCORR_PTLP_EGR_BLK = 0x18, + INVALID_CFG = 0x19 +} EXERCISER_ERROR_CODE; -void val_exerciser_create_info_table(void); +uint32_t val_exerciser_create_info_table(void); uint32_t val_exerciser_init(uint32_t instance); uint32_t val_exerciser_get_info(EXERCISER_INFO_TYPE type, uint32_t instance); uint32_t val_exerciser_set_param(EXERCISER_PARAM_TYPE type, uint64_t value1, uint64_t value2, uint32_t instance); @@ -54,6 +108,7 @@ uint32_t val_exerciser_ops(EXERCISER_OPS ops, uint64_t param, uint32_t instance) uint32_t val_exerciser_get_data(EXERCISER_DATA_TYPE type, exerciser_data_t *data, uint32_t instance); uint32_t val_exerciser_execute_tests(uint32_t level); uint32_t val_exerciser_get_bdf(uint32_t instance); +uint32_t val_get_exerciser_err_info(uint32_t type); uint32_t e001_entry(void); uint32_t e002_entry(void); @@ -71,5 +126,9 @@ uint32_t e013_entry(void); uint32_t e014_entry(void); uint32_t e015_entry(void); uint32_t e016_entry(void); +uint32_t e017_entry(void); +uint32_t e018_entry(void); +uint32_t e019_entry(void); +uint32_t e020_entry(void); #endif diff --git a/val/src/avs_exerciser.c b/val/src/avs_exerciser.c index 20d4e129..376fe2fe 100644 --- a/val/src/avs_exerciser.c +++ b/val/src/avs_exerciser.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,44 +29,146 @@ extern uint32_t pcie_bdf_table_list_flag; @param exerciser_info_table - Table pointer to be filled by this API @return exerciser_info_table - Contains info to communicate with stimulus generation hardware **/ -void val_exerciser_create_info_table(void) +uint32_t val_exerciser_create_info_table(void) { - uint32_t Bdf; + uint32_t num_ecam; + uint32_t seg_num; + uint32_t start_bus; + uint32_t end_bus; + uint32_t bus_index; + uint32_t dev_index; + uint32_t func_index; + uint32_t ecam_index; + uint32_t bdf; uint32_t reg_value; - uint32_t num_bdf; - pcie_device_bdf_table *bdf_table; + uint32_t cid_offset; + uint32_t dp_type; - bdf_table = val_pcie_bdf_table_ptr(); - /* if no bdf table ptr return error */ - if (bdf_table->num_entries == 0) + num_ecam = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); + if (num_ecam == 0) { - val_print(AVS_PRINT_DEBUG, "\n No BDFs discovered ", 0); - return; + val_print(AVS_PRINT_ERR, "\n No ECAMs discovered ", 0); + return 1; } - num_bdf = bdf_table->num_entries; - while (num_bdf-- != 0) + for (ecam_index = 0; ecam_index < num_ecam; ecam_index++) { + /* Derive ecam specific information */ + seg_num = val_pcie_get_info(PCIE_INFO_SEGMENT, ecam_index); + start_bus = val_pcie_get_info(PCIE_INFO_START_BUS, ecam_index); + end_bus = val_pcie_get_info(PCIE_INFO_END_BUS, ecam_index); - Bdf = bdf_table->device[num_bdf].bdf; - /* Probe pcie device Function with this bdf */ - if (val_pcie_read_cfg(Bdf, TYPE01_VIDR, ®_value) == PCIE_NO_MAPPING) + /* Iterate over all buses, devices and functions in this ecam */ + for (bus_index = start_bus; bus_index <= end_bus; bus_index++) { - /* Return if there is a bdf mapping issue */ - val_print(AVS_PRINT_ERR, "\n BDF 0x%x mapping issue", Bdf); - return; - } - - /* Store the Function's BDF if there was a valid response */ - if (pal_is_bdf_exerciser(Bdf)) - { - g_exercier_info_table.e_info[g_exercier_info_table.num_exerciser].bdf = Bdf; - g_exercier_info_table.e_info[g_exercier_info_table.num_exerciser++].initialized = 0; - val_print(AVS_PRINT_DEBUG, " exerciser Bdf %x\n", Bdf); + for (dev_index = 0; dev_index < PCIE_MAX_DEV; dev_index++) + { + for (func_index = 0; func_index < PCIE_MAX_FUNC; func_index++) + { + /* Form bdf using seg, bus, device, function numbers */ + bdf = PCIE_CREATE_BDF(seg_num, bus_index, dev_index, func_index); + + /* Probe pcie device Function with this bdf */ + if (val_pcie_read_cfg(bdf, TYPE01_VIDR, ®_value) == PCIE_NO_MAPPING) + { + /* Return if there is a bdf mapping issue */ + val_print(AVS_PRINT_ERR, "\n BDF 0x%x mapping issue", bdf); + return 1; + } + + /* Store the Function's BDF if there was a valid response */ + if (reg_value != PCIE_UNKNOWN_RESPONSE) + { + /* Skip if the device is a host bridge */ + if (val_pcie_is_host_bridge(bdf)) + continue; + + /* Skip if the device is a PCI legacy device */ + if (val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &cid_offset) + != PCIE_SUCCESS) + continue; + + dp_type = val_pcie_device_port_type(bdf); + val_print(AVS_PRINT_INFO, "\n dp_type 0x%x ", dp_type); + + /* Store the Function's BDF if there was a valid response */ + if (pal_is_bdf_exerciser(bdf)) + { + g_exercier_info_table.e_info[g_exercier_info_table.num_exerciser].bdf + = bdf; + g_exercier_info_table.e_info[g_exercier_info_table.num_exerciser++] + .initialized = 0; + val_print(AVS_PRINT_DEBUG, " exerciser Bdf %x\n", bdf); + } + + } + } + } } } - val_print(AVS_PRINT_DEBUG, " exerciser cards in the system %x \n", - g_exercier_info_table.num_exerciser); + + val_print(AVS_PRINT_ERR, " PCIE_INFO: Number of exerciser cards : %4d \n", + g_exercier_info_table.num_exerciser); + return 0; +} + +uint32_t val_get_exerciser_err_info(EXERCISER_ERROR_CODE type) +{ + switch (type) { + case CORR_RCVR_ERR: + return CORR_RCVR_ERR_OFFSET; + case CORR_BAD_TLP: + return CORR_BAD_TLP_OFFSET; + case CORR_BAD_DLLP: + return CORR_BAD_DLLP_OFFSET; + case CORR_RPL_NUM_ROLL: + return CORR_RPL_NUM_ROLL_OFFSET; + case CORR_RPL_TMR_TIMEOUT: + return CORR_RPL_TMR_TIMEOUT_OFFSET; + case CORR_ADV_NF_ERR: + return CORR_ADV_NF_ERR_OFFSET; + case CORR_INT_ERR: + return CORR_INT_ERR_OFFSET; + case CORR_HDR_LOG_OVRFL: + return CORR_HDR_LOG_OVRFL_OFFSET; + case UNCORR_DL_ERROR: + return UNCORR_DL_ERROR_OFFSET; + case UNCORR_SD_ERROR: + return UNCORR_SD_ERROR_OFFSET; + case UNCORR_PTLP_REC: + return UNCORR_PTLP_REC_OFFSET; + case UNCORR_FL_CTRL_ERR: + return UNCORR_FL_CTRL_ERR_OFFSET; + case UNCORR_CMPT_TO: + return UNCORR_CMPT_TO_OFFSET; + case UNCORR_AMPT_ABORT: + return UNCORR_AMPT_ABORT_OFFSET; + case UNCORR_UNEXP_CMPT: + return UNCORR_UNEXP_CMPT_OFFSET; + case UNCORR_RCVR_ERR: + return UNCORR_RCVR_ERR_OFFSET; + case UNCORR_MAL_TLP: + return UNCORR_MAL_TLP_OFFSET; + case UNCORR_ECRC_ERR: + return UNCORR_ECRC_ERR_OFFSET; + case UNCORR_UR: + return UNCORR_UR_OFFSET; + case UNCORR_ACS_VIOL: + return UNCORR_ACS_VIOL_OFFSET; + case UNCORR_INT_ERR: + return UNCORR_INT_ERR_OFFSET; + case UNCORR_MC_BLK_TLP: + return UNCORR_MC_BLK_TLP_OFFSET; + case UNCORR_ATOP_EGR_BLK: + return UNCORR_ATOP_EGR_BLK_OFFSET; + case UNCORR_TLP_PFX_EGR_BLK: + return UNCORR_TLP_PFX_EGR_BLK_OFFSET; + case UNCORR_PTLP_EGR_BLK: + return UNCORR_PTLP_EGR_BLK_OFFSET; + default: + val_print(AVS_PRINT_ERR, "\n Invalid error offset ", 0); + return 0; + } } @@ -243,19 +345,11 @@ val_exerciser_execute_tests(uint32_t level) return AVS_STATUS_SKIP; } - /* Create the list of valid Pcie Device Functions */ - if (val_pcie_create_device_bdf_table()) { + if (val_exerciser_create_info_table()) { val_print(AVS_PRINT_WARN, "\n Create BDF Table Failed, Skipping Exerciser tests...\n", 0); return AVS_STATUS_SKIP; } - if (pcie_bdf_table_list_flag == 1) { - val_print(AVS_PRINT_WARN, "\n *** Created device list with valid bdf doesn't match \ - with the platform pcie device hierarchy, Skipping exerciser tests *** \n", 0); - return AVS_STATUS_SKIP; - } - - val_exerciser_create_info_table(); num_instances = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); if (num_instances == 0) { @@ -290,6 +384,12 @@ val_exerciser_execute_tests(uint32_t level) status |= e015_entry(); status |= e016_entry(); + if (level > 6) { + status = e017_entry(); + status |= e018_entry(); + status |= e019_entry(); + status |= e020_entry(); + } val_print_test_end(status, "Exerciser"); val_smmu_stop(); From 73ea2d53a25cf02037940723d01c3b3d73b2d44b Mon Sep 17 00:00:00 2001 From: Rajat Goyal Date: Fri, 13 Jan 2023 13:08:37 +0530 Subject: [PATCH 6/8] SBSA Document Changes - Updated README & Documents. - Updated Copyright Headers. Signed-off-by: Rajat Goyal --- README.md | 82 ++-- ..._Architecture_Compliance_Test_Scenario.pdf | Bin 646689 -> 569606 bytes ...BSA_Architecture_Compliance_User_Guide.pdf | Bin 236986 -> 263314 bytes ...ture_Compliance_Validation_Methodology.pdf | Bin 502745 -> 596973 bytes docs/Arm_SBSA_NIST_User_Guide.md | 24 +- docs/testcase-checklist.md | 396 +++++++++--------- .../exerciser/operating_system/test_e017.c | 2 +- .../exerciser/operating_system/test_e018.c | 2 +- .../exerciser/operating_system/test_e019.c | 2 +- .../exerciser/operating_system/test_e020.c | 2 +- 10 files changed, 245 insertions(+), 265 deletions(-) diff --git a/README.md b/README.md index 0d5a140f..9de58423 100644 --- a/README.md +++ b/README.md @@ -3,27 +3,27 @@ ## Server Base System Architecture -**Server Base System Architecture** (SBSA) specification specifies a hardware system architecture based on the Arm 64-bit architecture. Server system software such as operating systems, hypervisors, and firmware rely on this. It addresses processing element features and key aspects of system architecture. +**Server Base System Architecture** (SBSA) specification specifies a hardware system architecture based on the Arm 64-bit architecture. +Server system software such as operating systems, hypervisors, and firmware rely on this. It addresses processing element features and key aspects of system architecture. -For more information, download the [SBSA specification](https://developer.arm.com/documentation/den0029/e/?lang=en) +For more information, download the [SBSA specification](https://developer.arm.com/documentation/den0029/h/?lang=en) ## SBSA - Architecture Compliance Suite -SBSA **Architecture Compliance Suite** (ACS) is a collection of self-checking, portable C-based tests. -This suite includes a set of examples of the invariant behaviors that are provided by the [SBSA specification](https://developer.arm.com/documentation/den0029/e/?lang=en), so that implementers can verify if these behaviours have been interpreted correctly. -Most of the tests are executed from UEFI Shell by executing the SBSA UEFI shell application. -A few tests are executed by running the SBSA ACS Linux application which in turn depends on the SBSA ACS Linux kernel module. +SBSA **Architecture Compliance Suite** (ACS) is a collection of self-checking, portable C-based tests. +This suite includes a set of examples of the invariant behaviors that are provided by the [SBSA specification](https://developer.arm.com/documentation/den0029/h/?lang=en), so that implementers can verify if these behaviours have been interpreted correctly. +Most of the tests are executed from UEFI Shell by executing the SBSA UEFI shell application. +A few tests are executed by running the SBSA ACS Linux application which in turn depends on the SBSA ACS Linux kernel module. ## Release details - - Code Quality: REL v6.1.0 - - The tests are written for version 6.1 of the SBSA specification. - - BSA rules referenced in SBSA checklist and common in BSA and SBSA checklist are covered as part of BSA ACS - - For complete SBSA 6.1 coverage, run BSA binary and SBSA binary. + - Code Quality: REL v7.1 BETA-0 + - The tests are written for version 7.1 of the SBSA specification. + - The release includes test which are not verified due to platform dependency. Please refer to [testcase-checklist](docs/testcase-checklist.md) for these tests. - The compliance suite is not a substitute for design verification. - To review the SBSA ACS logs, Arm licensees can contact Arm directly through their partner managers. - - To know about the gaps in the test coverage, see [Testcase checklist](docs/testcase-checklist.md). + - To know about the gaps in the test coverage, see [Test Scenario Document](docs/Arm_SBSA_Architecture_Compliance_Test_Scenario.pdf). ## GitHub branch @@ -31,9 +31,9 @@ A few tests are executed by running the SBSA ACS Linux application which in turn - To get the latest version of the code with bug fixes and new features, use the master branch. ## Additional reading - - For details on the SBSA ACS UEFI Shell Application, see the [Arm SBSA ACS User Guide](docs/Arm_SBSA_Architecture_Compliance_User_Guide.pdf). + - For details on the SBSA ACS UEFI Shell Application, Linux Application and PMU Linux Application see the [Arm SBSA ACS User Guide](docs/Arm_SBSA_Architecture_Compliance_User_Guide.pdf). - For details on the design of the SBSA ACS, see the [Arm SBSA Validation Methodology Document](docs/Arm_SBSA_Architecture_Compliance_Validation_Methodology.pdf). - - For information about the test coverage scenarios that are implemented in the current release of ACS and the scenarios that are planned for the future releases, see the [Testcase checklist](docs/testcase-checklist.md). + - For information about the test coverage scenarios that are implemented in the current release of ACS and the scenarios that are planned for the future releases, see the [Test Scenario Document](docs/Arm_SBSA_Architecture_Compliance_Test_Scenario.pdf). ## SBSA ACS Baremetal Reference Code Bare-metal reference code is added as part of this release. For more information, see @@ -50,19 +50,18 @@ To enable the export of a few kernel APIs that are necessary for PCIe and IOMMU ## ACS build steps - UEFI Shell application ### Prebuilt images -Prebuilt images for v22_10_REL6.1.0 release is available in the prebuilt_images folder of the master branch. The prebuilt images of previous release are present in [release branch](https://github.com/chetan-rathore/sbsa-acs/tree/release/prebuilt_images). You can choose to use this images or build your own image by following the steps below. If you choose to use the prebuilt image, jump to the test suite execution section below for details on how to run the application. +Prebuilt images for v23_01_REL7.1.0_BETA-0 release is available in the prebuilt_images folder of the master branch. The prebuilt images of previous release are present in [release branch](https://github.com/chetan-rathore/sbsa-acs/tree/release/prebuilt_images). You can choose to use this images or build your own image by following the steps below. If you choose to use the prebuilt image, jump to the test suite execution section below for details on how to run the application. ### Prerequisites - Before starting the ACS build, ensure that the following requirements are met. +Before starting the build, ensure that the following requirements are met. - Any mainstream Linux based OS distribution running on a x86 or AArch64 machine. +- Install GCC-ARM 10.3 or later toolchain for Linux from [here](https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads). - git clone the edk2-stable202208 tag of [EDK2 tree](https://github.com/tianocore/edk2). - git clone the [EDK2 port of libc](https://github.com/tianocore/edk2-libc) SHA: 61687168fe02ac4d933a36c9145fdd242ac424d1. -- Install GCC 7.5 or later toolchain for Linux from [here](https://releases.linaro.org/components/toolchain/binaries/). - Install the build prerequisite packages to build EDK2.
Note:
- The details of the packages are beyond the scope of this document. -- GCC 7.5 is recommended toolchain, build issues are observed with toolchain version 10.xx and above. To start the ACS build, perform the following steps: @@ -77,22 +76,12 @@ To start the ACS build, perform the following steps: ### Linux build environment If the build environment is Linux, perform the following steps: -1. export GCC49_AARCH64_PREFIX= GCC7.5 toolchain path pointing to /bin/aarch64-linux-gnu- in case of x86 machine.
For AArch64 build it should point to /usr/bin/ +1. export GCC49_AARCH64_PREFIX= GCC 10.3 toolchain path pointing to /bin/aarch64-none-linux-gnu- in case of x86 machine.
For AArch64 build it should point to /usr/bin/ 2. export PACKAGES_PATH= path pointing to edk2-libc 3. source edksetup.sh 4. make -C BaseTools/Source/C 5. source ShellPkg/Application/sbsa-acs/tools/scripts/avsbuild.sh -### Windows build environment -If the build environment is Windows, perform the following steps: -1. Set the toolchain path to GCC53 or above. -2. Setup the environment for AArch64 EDK2 build. -3. Setup the environment for PACKAGES_PATH. -4. Build the SBSA shell application. - For example, - build -a AARCH64 -t GCC49 -p ShellPkg/ShellPkg.dsc -m - ShellPkg/Application/sbsa-acs/uefi_app/SbsaAvs.inf - **Note:** To build the ACS with NIST Statistical Test Suite, see the [SBSA_NIST_User_Guide](docs/Arm_SBSA_NIST_User_Guide.md) ### Build output @@ -135,14 +124,16 @@ On an emulation environment with secondary storage, perform the following steps: 1. Create an image file which contains the 'Sbsa.efi' file. For Example: - mkfs.vfat -C -n HD0 hda.img 2097152 - - sudo mount -o rw,loop=/dev/loop0,uid=`whoami`,gid=`whoami` hda.img /mnt/sbsa. If loop0 is busy, specify the loop that is free + - sudo mount -o rw,loop=/dev/loop0,uid=`whoami`,gid=`whoami` hda.img /mnt/sbsa. + If loop0 is busy, specify the loop that is free - cp "/Sbsa.efi" /mnt/sbsa/ - sudo umount /mnt/sbsa -2. Load the image file to the secondary storage using a backdoor. The steps followed to load the image file are emulation environment-specific and beyond the scope of this document. +2. Load the image file to the secondary storage using a backdoor. + The steps followed to load the image file are emulation environment-specific and beyond the scope of this document. 3. Boot the system to UEFI shell. 4. To determine the file system number of the secondary storage, execute 'map -r' command. 5. Type 'fsx' where 'x' is replaced by the number determined in step 4. -6. To start the compliance tests, run the executable Sbsa.efi with the appropriate parameters. +6. To start the compliance tests, run the executable Sbsa.efi with the appropriate parameters. For details on the parameters, see the [SBSA ACS User Guide](docs/Arm_SBSA_Architecture_Compliance_User_Guide.pdf) 7. Copy the UART console output to a log file for analysis and certification. @@ -154,8 +145,9 @@ On an emulation platform where secondary storage is not available, perform the f 1. Add the path to 'Sbsa.efi' file in the UEFI FD file. 2. Build UEFI image including the UEFI Shell. 3. Boot the system to UEFI shell. -4. Run the executable 'Sbsa.efi' to start the compliance tests. For details about the parameters, - see the [SBSA ACS User Guide](docs/Arm_SBSA_Architecture_Compliance_User_Guide.pdf). +4. Run the executable 'Sbsa.efi' to start the compliance tests. + For details about the parameters, see the [SBSA ACS User Guide](docs/Arm_SBSA_Architecture_Compliance_User_Guide.pdf). +> shell> Sbsa.efi 5. Copy the UART console output to a log file for analysis and certification. @@ -170,17 +162,17 @@ The patch for the kernel tree and the Linux PAL are hosted separately on [linux- ### 1.1 Building the kernel module #### Prerequisites - Linux kernel source version 5.11, 5.13, 5.15, 6.0. -- Linaro GCC tool chain 7.5 or above. +- Linaro GCC tool chain 10.3 or above. - Build environment for AArch64 Linux kernel.
NOTE:
- Linux version 6.0 is recommened version. -- GCC 7.5 is recommended toolchain, build issues are observed with toolchain version 10.xx and above. +- GCC 10.3 is recommended toolchain. #### Porting steps for Linux kernel 1. git clone https://gitlab.arm.com/linux-arm/linux-acs sbsa-acs-drv 2. git clone https://github.com/ARM-software/sbsa-acs.git sbsa-acs 3. git clone https://github.com/torvalds/linux.git -b v6.0 -4. export CROSS_COMPILE= pointing to /bin/aarch64-linux-gnu- +4. export CROSS_COMPILE= pointing to /bin/aarch64-linux-gnu- 5. git apply /sbsa-acs-drv/kernel/src/0001-BSA-ACS-Linux-6.0.patch to your kernel source tree. 6. make ARCH=arm64 defconfig && make -j $(nproc) ARCH=arm64 @@ -222,8 +214,18 @@ Arm Enterprise ACS test suite may run at higher privilege level. An attacker may Validating the compliance of certain PCIe rules defined in the SBSA specification requires the PCIe end-point to generate specific stimulus during the runtime of the test. Examples of such stimulus are P2P, PASID, ATC, etc. The tests that requires these stimuli are grouped together in the exerciser module. The exerciser layer is an abstraction layer that enables the integration of hardware capable of generating such stimuli to the test framework. The details of the hardware or Verification IP which enable these exerciser tests are platform specific and are beyond the scope of this document. - - Some PCIe and Exerciser test are dependent on PCIe features supported by the test system. - Please fill the required API's with test system information. +### SBSA Level 7 tests dependencies + - MPAM test will require EL3 firmware to enable access to MPAM registers from lower EL's. + If arm trusted firmware is used as EL3 fimrware, enable ENABLE_MPAM_FOR_LOWER_ELS=1 in tf build + - RAS test will require EL3 firmware to enable access to RAS registers from lower EL's and forward RAS related exceptions to lower EL's. + If arm trusted firmware is used as EL3 fimrware, enable EL3_EXCEPTION_HANDLING=1 RAS_EXTENSION=1 HANDLE_EA_EL3_FIRST=1 RAS_TRAP_LOWER_EL_ERR_ACCESS=0 in tf build + - If the above flags are not enabled, MPAM and RAS test can lead to exception at EL3. + - MPAM test will require system to implement MPAM, SRAT, HMAT, PPTT tables. + - RAS test will require system to implement AEST, RAS2, SRAT, HMAT, PPTT tables. + - PMU test will require system to implement APMT table. + - Entrophy rule will require ACS to build with STS package + +**Note:** To build the ACS with NIST Statistical Test Suite, see the [SBSA_NIST_User_Guide](docs/Arm_SBSA_NIST_User_Guide.md) |APIs |Description |Affected tests | |-----------------------------|------------------------------------------------------------------------------|------------------------| @@ -246,10 +248,10 @@ SBSA ACS is distributed under Apache v2.0 License. ## Feedback, contributions, and support - For feedback, use the GitHub Issue Tracker that is associated with this repository. - - For support, send an email to "support-enterprise-acs@arm.com" with details. + - For support, send an email to "support-systemready-acs@arm.com" with details. - Arm licensees may contact Arm directly through their partner managers. - Arm welcomes code contributions through GitHub pull requests. See GitHub documentation on how to raise pull requests. -------------- -*Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2018-2023 Arm Limited and Contributors. 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zL;XZh79@{J%I4Hm;n1LnEmblflV9` zTtj+D+=C#&FfeEs4ax!+6TE^ zC2`3?SsXNL1~BxF%^~vtU-p9pJBjWG7&LDK_E%8Q=op9=utbm!0*u5B!=iTWf9}jb zaMFQ_gBAwdC&hrhgVKSigR&nBrVh$2EE+iZyUU_rC=mZZDg@xp5rMy#BEZo9gANVV zgeb7#2%RQS7VIxV8wQ!Qov8!k|A+mcFdiBpfS!<8J7Q?}w+l_|C=rADga9MiW&#*` zSCWg!e-ICWY#*eDz-@wVjsZH5-h|TONc=xQN0Pus0rA-F`G9so%nSA(AQb}ng$g0i zjUYlGp#xhcBp3qfl7q>FLDe@A`!k*Y`F{W;F|%N4<`fq&%)7+w-?0gPmd!6qO0foup10SI+QL7YRf z$qFzMqXXm|{f}SwUuQsM0?`YA?%!RMfBiocNUlNcI}sxhLXcI3CZR#l1t(czIFL1i z3N<)@0?`Wu;H!b94HYgBZbPFLK!+w-c6g8thK>$kB&^26L3j+|G{DdZi2sKIK@!yH z0E{HlO*}XQP0axe1NC@;gSu-!`-+>DgR`w0y_6L3%#yaNE8z+_a0J-&`z)WDi=8V! zkcdCuPVt*a0r>}t7_JE1G_1S=7JKRxI7XtZfL6dNg2QHt7#aTmpTvyVn2v+DE%9&@ c@x+t+6)U$ZJLjDki7qr6OD`;}q^V5*e@+wHNArgV); +ExitVal = (INTN)ShellAppMainsbsa( (int)Argc, gMD->NArgV); ``` -6. Comment the map[] variable in StdLib/LibC/Main/Arm/flt_rounds.c to avoid -werror=unused-variable +6. Comment the map[] variable in edk2-libc/StdLib/LibC/Main/Arm/flt_rounds.c to avoid -werror=unused-variable ``` +#if 0 static const int map[] = { @@ -104,11 +104,8 @@ The following figure shows the source code directory for SBSA ACS     │
    ├── platform
    │   ├── pal_baremetal
-    │   ├── pal_linux
    │   ├── pal_uefi
-    │   └── secure_sw
-    │       └── arm-tf
-    │
+ |     ├── test_pool
    │   ├── exerciser
    │   ├── gic
@@ -116,8 +113,11 @@ The following figure shows the source code directory for SBSA ACS     │   ├── pcie
    │   ├── pe
    │   ├── peripherals
-    │   ├── power_wakeup
-    │   ├── secure
+    │   ├── power_wakeup
+    │   ├── mpam
+    │   ├── ras
+    │   ├── pmu
+    │   ├── smmu
    │   ├── timer_wd
    │   └── nist_sts
    │       ├── test_n001.c     ────────>  NIST entry point to STS
@@ -170,8 +170,8 @@ Final analysis report is generated when statistical testing is complete. The rep For more details on NIST STS, see: -**Note**: For SBSA level 6 compliance, passing the NIST statistical test suite is not mandatory. +**Note**: For SBSA level 7 compliance, passing the NIST statistical test suite is required for S_L7ENT_1 rule. -------------- -*Copyright (c) 2020, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2020, 2023, Arm Limited and Contributors. All rights reserved.* diff --git a/docs/testcase-checklist.md b/docs/testcase-checklist.md index ba863a0c..370b0b57 100644 --- a/docs/testcase-checklist.md +++ b/docs/testcase-checklist.md @@ -1,219 +1,197 @@ # SBSA ACS Testcase checklist -## Test Number mapped to SBSA specification section +## Test Number mapped to SBSA specification checklist - - Also, indicates the test coverage. + - Also, indicates the test coverage . + - SBSA L3 rules which are common in BSA and SBSA checklist covered by BSA-ACS. + - For details on test algorithm,unimplemented rule coverage refer Test Scenario document. + +| Test Number | Component | Level | Rule ID | Test Description | Verified by ACS | Test Environment | +|----------------|--------------|-------|-------------------------------------------------------|--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|-----------------|--------------------| +| 1 | PE | L3 | S_L3PE_01 | Check PE Granule Support | yes | UEFI App | +| 2 | PE | L3 | S_L3PE_02 | Check for 16-bit ASID support | yes | UEFI App | +| 3 | PE | L3 | S_L3PE_03 | Check AARCH64 implementation | yes | UEFI App | +| 4 | PE | L3 | S_L3PE_04 | Check FEAT_LPA Requirements | yes | UEFI App | +| 5 | PE | L4 | S_L4PE_01 | Check for RAS extension | yes | UEFI App | +| 6 | PE | L4 | S_L4PE_02 | Check DC CVAP support | yes | UEFI App | +| 7 | PE | L4 | S_L4PE_03 | Check for 16-Bit VMID | yes | UEFI App | +| 8 | PE | L4 | S_L4PE_04 | Check for Virtual host extensions | yes | UEFI App | +| 9 | PE | L5 | S_L5PE_01 | Support Page table map size change | yes | UEFI App | +| 10 | PE | L5 | S_L5PE_02 | Check for pointer signing | yes | UEFI App | +| 11 | PE | L5 | S_L5PE_04 | Check Activity monitors extension | yes | UEFI App | +| 12 | PE | L5 | S_L5PE_05 | Check for SHA3 and SHA512 support | yes | UEFI App | +| 13 | PE | L5 | S_L5PE_06 | Stage 2 control of mem and cache | yes | UEFI App | +| 14 | PE | L5 | S_L5PE_07 | Check for nested virtualization | yes | UEFI App | +| 15 | PE | L5 | S_MPAM_PE | Check MPAM PE Requirements | yes | UEFI App | +| 16 | PE | L5 | S_MPAM_PE | Check MPAM LLC Requirements | yes | UEFI App | +| 17 | PE | L6 | B_PE_17 | Check SPE if implemented | no | UEFI App | +| 18 | PE | L6 | S_L6PE_02 | Check Branch Target Support | yes | UEFI App | +| 19 | PE | L6 | S_L6PE_03 | Check Protect Against Timing Fault | yes | UEFI App | +| 20 | PE | L6 | S_L6PE_04 | Check PMU Version Support | yes | UEFI App | +| 21 | PE | L6 | S_L6PE_05 | Check AccessFlag DirtyState Update | yes | UEFI App | +| 22 | PE | L6 | S_L6PE_06 | Check Enhanced Virtualization Tra | yes | UEFI App | +| 23 | PE | L6 | B_SEC_01 | Check Speculation Restriction | yes | UEFI App | +| 24 | PE | L6 | B_SEC_02 | Check Speculative Str Bypass Safe | yes | UEFI App | +| 25 | PE | L6 | B_SEC_03 | Check PEs Impl CSDB,SSBB,PSSBB | yes | UEFI App | +| 26 | PE | L6 | B_SEC_04 | Check PEs Implement SB Barrier | yes | UEFI App | +| 27 | PE | L6 | B_SEC_05 | Check PE Impl CFP,DVP,CPP RCTX | yes | UEFI App | +| 28 | PE | L7 | S_L7PE_01 | Check Fine Grain Trap Support | yes | UEFI App | +| 29 | PE | L7 | S_L7PE_02 | Check for ECV support | yes | UEFI App | +| 30 | PE | L7 | S_L7PE_03 | Check for AMU Support | yes | UEFI App | +| 31 | PE | L7 | S_L7PE_04 | Checks ASIMD Int8 matrix multiplc | yes | UEFI App | +| 32 | PE | L7 | S_L7PE_05 | Check for BFLOAT16 extension | yes | UEFI App | +| 33 | PE | L7 | S_L7PE_06 | Check for EnhancedPAC2 and FPAC | yes | UEFI App | +| 34 | PE | L7 | S_L7PE_07 | Check for SVE Int8 matrix multiplc | yes | UEFI App | +| 35 | PE | L7 | S_L7PE_08 | Check for data gathering hint | yes | UEFI App | +| 36 | PE | L7 | S_L7PE_09 | Check WFE Fine tune delay feature | yes | UEFI App | +| 37 | PE | L7 | S_L7PE_10 | Check for enhanced PAN feature | yes | UEFI App | +| 101 | GICv3 | L3 | S_L3GI_01 | Check GIC version | yes | UEFI App | +| 102 | GICv3 | L5 | S_L5PP_01 | Check Reserved PPI Assignments | yes | UEFI App | +| 301 | Watchdog | L6 | S_L6WD_01 | Check NS Watchdog Revision | yes | UEFI App | +| 401 | PCIe | L6 | PCI_IN_01 | Check ECAM Presence | yes | Linux App | +| 403 | PCIe | L6 | PCI_IN_02 | Check ECAM Memory accessibility | yes | UEFI App | +| 405 | PCIe | L6 | PCI_MM_01, PCI_MM_02, PCI_MM_03, RE_BAR_2 | PCIe Unaligned access, Norm mem | yes | Linux App | +| 409 | GICv3 | L6 | S_L3GI_02 | Check all MSI(X) vectors are LPIs | yes | Linux App | +| 420 | PCIe | L6 | RE_REG_1, RE_REC_1, RE_REC_2 | heck Type 0/1 common config rules | yes | UEFI App | +| 421 | PCIe | L6 | RE_REG_1, RE_REC_1, RE_REC_2 | Check Type 0 config header rules | yes | UEFI App | +| 422 | PCIe | L6 | RE_REC_1, RE_REC_2 | heck Type 1 config header rules | yes | UEFI App | +| 423 | PCIe | L6 | RE_REG_3, RE_REC_1, RE_REC_2 | Check PCIe capability rules | yes | UEFI App | +| 424 | PCIe | L6 | RE_REG_3, RE_REC_1, RE_REC_2 | Check Device capabilites reg rules | yes | UEFI App | +| 425 | PCIe | L6 | RE_REG_3, RE_REC_1, RE_REC_2 | Check Device Control register rule | yes | UEFI App | +| 426 | PCIe | L6 | RE_REG_3, RE_REC_1, RE_REC_2 | Check Device cap 2 register rules | yes | UEFI App | +| 427 | PCIe | L6 | RE_REG_3, RE_REC_1, RE_REC_2 | Check Device control 2 reg rules | yes | UEFI App | +| 428 | PCIe | L6 | RE_REG_2, RE_REC_1, RE_REC_2 | Check Power management cap rules | yes | UEFI App | +| 429 | PCIe | L6 | RE_REG_2, RE_REC_1, RE_REC_2 | Check Power management/status rule | yes | UEFI App | +| 430 | PCIe | L6 | RE_REC_1, RE_REC_2 | Check Cmd Reg memory space enable | yes | UEFI App | +| 431 | PCIe | L6 | RE_REC_1, RE_REC_2 | Check Type0/1 BIST Register rule | yes | UEFI App | +| 432 | PCIe | L6 | RE_REC_1, RE_REC_2 | Check HDR CapPtr Register rule | yes | UEFI App | +| 433 | PCIe | L6 | RE_REC_1, RE_REC_2 | Check Max payload size supported | yes | UEFI App | +| 434 | PCIe | L6 | RE_BAR_3 | Check BAR memory space & Type rule | yes | UEFI App | +| 435 | PCIe | L6 | RE_RST_1, PCI_SM_02 | Check Function level reset rule | yes | UEFI App | +| 436 | PCIe | L6 | PCI_IN_17 | Check ARI forwarding support rule | yes | UEFI App | +| 437 | PCIe | L6 | RE_REG_3, RE_REC_1, RE_REC_2 | Check OBFF supported rule | yes | UEFI App | +| 438 | PCIe | L6 | RE_REG_3, RE_REC_1, RE_REC_2 | Check CTRS and CTDS rule | yes | UEFI App | +| 439 | PCIe | L6 | RE_REG_3, RE_REC_1, RE_REC_2 | Check i-EP atomicop rule | yes | UEFI App | +| 441 | PCIe | L6 | RE_INT_1, IE_INT_1 | Check MSI and MSI-X support rule | yes | UEFI App | +| 442 | PCIe | L6 | RE_PWR_1 | Check Power Management rules | yes | UEFI App | +| 443 | PCIe | L6 | PCI_IN_17 | Check ARI forwarding enable rule | yes | UEFI App | +| 444 | PCIe | L6 | PCI_IN_04 | Check device under RP in same ECAM | yes | UEFI App | +| 445 | PCIe | L6 | PCI_IN_03 | Check all RP in HB is in same ECAM | yes | UEFI App | +| 446 | PCIe | L6 | PCI_IN_18 | Check RP Byte Enable Rules | yes | UEFI App | +| 447 | PCIe | L6 | PCI_IN_12 | Check Config Txn for RP in HB | yes | UEFI App | +| 448 | PCIe | L6 | PCI_IN_13 | Check RootPort NP Memory Access | yes | UEFI App | +| 449 | PCIe | L6 | PCI_IN_13 | Check RootPort P Memory Access | yes | UEFI App | +| 450 | PCIe | L6 | PCI_LI_01, PCI_LI_03 | Check L-Intr SPI Level-Sensitive | yes | UEFI App | +| 451 | PCIe | L6 | IE_RST_2 | Check Sec Bus Reset For iEP_RP | yes | UEFI App | +| 452 | PCIe | L6 | RE_SMU_2 | Check ATS Support Rule | yes | UEFI App | +| 456 | PCIe | L6 | IE_ACS_2 | Check iEP-RootPort P2P Support | yes | UEFI App | +| 457 | PCIe | L6 | IE_ACS_1 | Check RCiEP, iEP_EP P2P Supp | yes | UEFI App | +| 458 | PCIe | L6 | RE_BAR_1 | Read and write to RCiEP BAR reg | yes | UEFI App | +| 459 | PCIe | L6 | RE_PCI_2 | Check RCEC Class code and Ext Cap | yes | UEFI App | +| 460 | PCIe | L6 | RE_PCI_1 | Check RCiEP Hdr type & link Cap | yes | UEFI App | +| 461 | PCIe | L7 | S_PCIe_02 | Check RootPort P & NP Memory Access | no | UEFI App | +| 462 | PCIe | L4 | S_L4PCI_2 | Check EA Capability | yes | UEFI App | +| 701 | SMMU | L3 | Section 1.2.1 | SMMU Version Check | yes | UEFI App | +| 702 | SMMU | L4 | S_L4SM_01, S_L4SM_02 | SMMU Compatibility Check | yes | UEFI App | +| 702 | SMMU | L5 | S_L5SM_01, S_L5SM_02 | SMMU Compatibility Check | yes | UEFI App | +| 703 | SMMU | L5 | B_SMMU_09 | SMMU revision and S-EL2 support | yes | UEFI App | +| 704 | SMMU | L5 | B_SMMU_20 | SMMU Revision,S-EL2 support Hyp | yes | UEFI App | +| 705 | SMMU | L6 | S_L6SM_01 | Check SMMU Coherent Access Support | yes | UEFI App | +| 706 | SMMU | L6 | S_L6SM_02 | Check SMMU HTTU Support | yes | UEFI App | +| 707 | SMMU | L6 | S_L6SM_03 | Check SMMU MSI Support | yes | UEFI App | +| 708 | SMMU | L6 | B_SMMU_23 | Check SMMU 16 Bit VMID Support | yes | UEFI App | +| 709 | SMMU | L6 | B_SMMU_03 | Check Large Virtual Addr Support | yes | UEFI App | +| 710 | SMMU | L6 | B_SMMU_04, B_SMMU_05 | Check TLB Range Invalidation | yes | UEFI App | +| 711 | SMMU | L6 | B_SMMU_13 | Check SMMU 16 Bit ASID Support | yes | UEFI App | +| 712 | SMMU | L6 | B_SMMU_14 | Check SMMU Endianess Support | yes | UEFI App | +| 713 | SMMU | L7 | S_L7SM_01 | Check if all DMA reqs behind SMMU | yes | UEFI App | +| 714 | SMMU | L7 | S_L7SM_03, S_L7SM_04 | Check SMMUv3 PMU Extension | yes | UEFI App | +| 715 | SMMU | L7 | S_L7SM_11, S_L7SM_22 | Check system for MPAM support | yes | UEFI App | +| 716 | SMMU | L7 | S_L7SM_02 | Check for SMMU/CATU in ETR Path | yes | Linux App | +| 804 | PCIe | L4 | PCI_MSI_2,ITS_DEV_6 | Generate MSI(X) interrupts | yes | UEFI App | +| 805 | PCIe | L4 | PCI_PAS_1, RE_SMU_4 | Generate PASID PCIe transactions | yes | UEFI App | +| 806 | PCIe | L4 | PCI_LI_02 | Generate PCIe legacy interrupts | yes | UEFI App | +| 807 | PCIe | L4 | PCI_IC_01, PCI_IC_03, PCI_IC_06, PCI_IC_07, PCI_IC_08 | Check PCI Express I/O Coherency | yes | UEFI App | +| 809 | PCIe | L4 | PCI_IN_11 | Check RP Sec Bus transactions are TYPE0 | yes | UEFI App | +| 810 | PCIe | L4 | PCI_IN_10 | Check RP Sub Bus transactions are TYPE1 | yes | UEFI App | +| 812 | PCIe | L4 | PCI_PP_04 | Check P2P ACS Functionality | yes | UEFI App | +| 813 | PCIe | L4 | PCI_PP_04 | Check ACS Redirected Req Valid | yes | UEFI App | +| 814 | PCIe | L4 | PCI_IC_04, RE_ORD_4 | Check PCIe Software Coherency | yes | UEFI App | +| 815 | PCIe | L4 | PCI_IC_05, RE_ORD_1, RE_ORD_2 | Arrival order & Gathering Check | yes | UEFI App | +| 816 | PCIe | L4 | PCI_IN_17 | ARI forwarding Rule | yes | UEFI App | +| 817 | PCIe | L7 | S_PCIe_03 | PE 2/4/8B writes tp PCIe as 2/4/8B | yes | UEFI App | +| 818 | PCIe | L7 | PCI_ER_01, PCI_ER_02, PCI_ER_03 | RP's must support AER feature | yes | UEFI App | +| 819 | PCIe | L7 | PCI_ER_05, PCI_ER_06 | RP's must support DPC | yes | UEFI App | +| 820 | PCIe | L7 | S_PCIe_04 | Check 2/4/8 Bytes targeted writes | yes | UEFI App | +| 1301 | MEMORY | L3 | S_L3MM_01, S_L3MM_02 | Check peripherals addr 64Kb apart | yes | UEFI App | +| 1001 | MPAM | L7 | S_L7MP_01, S_L7MP_02 | Check for MPAM extension | yes | UEFI App | +| 1002 | MPAM | L7 | S_L7MP_03, S_L7MP_04 | Check for MPAM LLC CSU | yes | UEFI App | +| 1003 | MPAM | L7 | S_L7MP_05, S_L7MP_06 | Check for MPAM MBWUs Monitor func | yes | UEFI App | +| 1004 | MPAM | L7 | S_L7MP_07 | Check for MBWU counter size | yes | UEFI App | +| 1005 | MPAM | L7 | S_L7MP_08 | Check for MPAM MSC address overlap | yes | UEFI App | +| 1006 | MPAM | L7 | S_L7MP_03 | Check PMG storage by CPOR nodes | yes | UEFI App | +| 1101 | PMU | L7 | PMU_PE_02 | Check PMU Overflow signal | yes | UEFI App | +| 1102 | PMU | L7 | PMU_PE_03 | Check number of PMU counters | yes | UEFI App | +| 1103 | PMU | L7 | PMU_EV_11 | Check for multi-threaded PMU ext | yes | UEFI App | +| 1104 | PMU | L7 | PMU_BM_1, PMU_SYS_1, PMU_SYS_2 | Check memory bandwidth monitors | yes | UEFI App | +| 1105 | PMU | L7 | PMU_MEM_1, PMU_SYS_1, PMU_SYS_2 | Check memory latency monitors | yes | UEFI App | +| 1106 | PMU | L7 | PMU_SPE | Check for PMU SPE Requirements | yes | UEFI App | +| 1107 | PMU | L7 | PMU_BM_2, PMU_SYS_1, PMU_SYS_2 | Check PCIe bandwidth monitors | yes | UEFI App | +| 1108 | PMU | L7 | PMU_SYS_5 | Check System PMU for NUMA systems | yes | | +| 1109 | PMU | L7 | PMU_SYS_6 | Check multiple types of traffic measurement | yes | | +| 1201 | RAS | L7 | RAS_01 | Check Error Counter | yes | UEFI App | +| 1202 | RAS | L7 | RAS_02 | Check CFI, DUI, UI Controls | yes | UEFI App | +| 1203 | RAS | L7 | RAS_03 | Check FHI in Error Record Group | yes | UEFI App | +| 1204 | RAS | L7 | RAS_04 | Check ERI in Error Record Group | yes | UEFI App | +| 1205 | RAS | L7 | RAS_06 | Check ERI/FHI Connected to GIC | yes | UEFI App | +| 1206 | RAS | L7 | RAS_07 | RAS ERRADDR.AI bit status check | yes | UEFI App | +| 1207 | RAS | L7 | RAS_08 | Check Error Group Status | yes | UEFI App | +| 1208 | RAS | L7 | RAS_11, RAS_12 | Software Fault Error Check | yes | UEFI App | +| 1209 | RAS | L7 | S_L7RAS_1 | Data abort on Containable err | yes | UEFI App | +| 1210 | RAS | L7 | SYS_RAS_1 | Check for patrol scrubbing support | yes | UEFI App | +| 1211 | RAS | L7 | SYS_RAS_2,SYS_RAS_3 | Check Poison Storage & Forwarding | yes | UEFI App | +| 1212 | RAS | L7 | SYS_RAS_2 | Check Pseudo Fault Injection | yes | UEFI App | +| 901 | Entropy | L7 | S_L7ENT_1 | To support key and nonce generation, a system must have a hardware entropy source. This source must be a true random number generator that is visible to PE software and meets the requirements that are specified in the NIST SP 800-90 series of specifications | yes | UEFI App | +| | PE | L6 | B_PE_16 | Check for MTE support | yes | Linux App | +| PMU app | PMU | L7 | PMU_EV_01 | PMU PE IPC events | yes | Linux App | +| PMU app | PMU | L7 | PMU_EV_02 | PMU PE cache effectiveness events | yes | Linux App | +| PMU app | PMU | L7 | PMU_EV_03 | PMU PE TLB effectiveness events | yes | Linux App | +| | PMU | L7 | PMU_EV_04 | PMU PE demand accesses events | no | | +| PMU app | PMU | L7 | PMU_EV_05 | PMU PE cycle counting events | yes | Linux App | +| PMU app | PMU | L7 | PMU_EV_06 | PMU PE top-down accounting events | yes | Linux App | +| | PMU | L7 | PMU_EV_07 | PMU PE workload events | no | | +| PMU app | PMU | L7 | PMU_EV_08 | PMU PE branch predictor effectiveness events | yes | Linux App | +| PMU app | PMU | L7 | PMU_EV_09 | PMU PE BR_RETRIED event | yes | Linux App | +| PMU app | PMU | L7 | PMU_EV_09 | PMU PE BR_RETRIED event | yes | Linux App | +| PMU app | PMU | L7 | PMU_EV_09 | PMU PE Latency event | yes | Linux App | +| BSA acs | GIC | L3 | S_L3PP_01 | The Interrupt IDs must be the same as the recommended values mentioned in Arm BSA | yes | | +| | SMMU | L3 | S_L3SM_01 | If PEs that are used by the base system support TLB range instructions, then all OS visible requesters that contain a TLB must support range invalidates | no | | +| | SMMU | L4 | S_L4SM_03 | The integration of the System MMUs is compliant with the rules in SMMUv3 integration appendix in Arm BSA | no | | +| | PCIe | L4 | S_L4PCI_1 | All peripherals that are intended for assignment to a virtual machine or a user space device driver must be based on PCI Express | no | Manual | +| | PE | L5 | S_L5PE_03 | PEs that are based on Armv8.4 must implement the requirements of the CS-BSA combination C | no | | +| | GIC | L5 | S_L5GI_01 | Only a GIC v3, or higher, interrupt controller will be visible to operating system software. Other forms of interrupt controller, for example interrupt combining or forwarding engines, are not permissible, if they require a platform specific kernel driver | no | | +| | TIMER | L5 | S_L5TI_01 | A system that is compatible with level 5 will implement a generic counter which counts in nanosecond units. This means that, to the operating system, the reported frequency will be 1GHz | | | +| | RAS | L6 | S_RAS_01 | PEs and other system components that implement the Armv8 RAS extension Use Private Peripheral Interrupts for ERI or FHI if the only interface available for a RAS node is System register based | no | | +| | PCI | L6 | B_REP_1 | BSA Section F describes the rules required for an RCiEP device | no | | +| | PCI | L6 | B_IEP_1 | BSA Section G describes the rules to implement for an i-EP device | no | | +| | PE RAS | L7 | S_L7RAS_2 | PE speculative access not result in abort | no | | +| | PE TME | L7 | S_L7TME_1 | PEs must implement the MPAM extension. See FEAT_MPAM | no | | +| | PE TME | L7 | S_L7TME_2 | PEs must implement a minimum of 16 physical partition IDs | no | | +| | PE TME | L7 | S_L7TME_3 | The implementation must provide MPAM Cache Storage Usage monitors for the last-level cache | no | | +| | PE TME | L7 | S_L7TME_4 | Last-level cache must provide a minimum of 16 Cache Storage Usage monitors | no | | +| | PE TME | L7 | S_L7TME_5 | The implementation must provide MPAM Memory Bandwidth Usage monitors (MBWUs) for the interfaces that provide general purpose memory | no | | +| | PCIe | L7 | S_PCIe_01 | The system must support the translation of PE writes with all byte enable patterns to PCIe write requests. The translation must be done in compliance with PCIe byte enable rules | no | | +| | PMU | L7 | PMU_BM_3 | base server system must implement bandwidth monitors for External accelerator interface | no | | +| | PMU | L7 | PMU_BM_4 | base server system must implement bandwidth monitors for Chip-to-chip interface | no | | +| PMU app | PMU | L7 | PMU_SYS_7 | Each significant cache in the base server system must be capable of measuring cache effectiveness | yes | | +| | PMU | L7 | PMU_SEC_1 | When deployed in production systems, performance monitors must not expose Secure data to untrusted software | no | | +| | RAS | L7 | RAS_05 | If any error record in an error record group is capable of generating a critical error interrupt, the group implements a single critical error interrupt for all the records contained in the group | no | | +| Covered by PCIe tests | RAS | L7 | RAS_10 | Where the PCIe standard [1], Arm architecture[2], or other standard defines a rule or sets a convention for a software fault at a device, that rule or convention must be followed | yes | | -| Test Number | Component | Level | Test assertion | Section | Checked by ACS Now | Test Environment | -|----------------|----------------------------------|-------|----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|-----------------|--------------------|----------------------------| -| 1 | PE | L0 | Number must be < 8 | 4.1.1 | yes | UEFI App | -| 2 | PE | L0+ | PE(s) must implement SIMD extensions | 4.1.1 | yes | UEFI App | -| 3 | PE | L0+ | PE(s) shall implement 16 bit ASID support | 4.1.1 | yes | UEFI App | -| 4 | PE | L0+ | PE(s) shall support 4KB and 64KB at stage 1 and 2 | 4.1.1 | yes | UEFI App | -| 5 | PE | L0+ | cache architecture type VIPT or PIPT | 4.1.1 | yes | UEFI App | -| 6 | PE | L0+ | All PE(s) are coherent in the same same inner sharable domain | 4.1.1 | yes | UEFI App | -| 7 | PE | L0+ | PE(s) where export restrictions allow should implement cryptography extensions | 4.1.1 | yes | UEFI App | -| 8 | PE | L0+ | PE(s) shall implement LE support | 4.1.1 | yes | UEFI App | -| 10 | PE | L0+ | PE(s) shall implement AArch64 at all levels | 4.1.1 | yes | UEFI App | -| 11 | PE | L1- | The PMU overflow signal for each PE must be wired as a unique SPI or PPI with no intervening logic | 4.1.1 | yes | UEFI App | -| 11 | PE | L2+ | The PMU overflow signal from each PE must be wired to a unique PPI interrupt with no intervening logic. PPI must be 23 | 4.3.1 | yes | UEFI App | -| 12 | PE | L0 | Each PE will implement a minimal of four programable PMU counters | 4.1.1 | yes | UEFI App | -| 12 | PE | L1+ | Each PE must implement a minimum of six programmable PMU counters | 4.2.1 | yes | UEFI App | -| 13 | PE | L0+ | Each PE will implement a minimal of four synchronous watchpoints | 4.1.1 | yes | UEFI App | -| 14 | PE | L0 | Each PE implements a minimum of four breakpoints, two of which must be able to match virtual address, contextID or VMID | 4.1.1 | yes | UEFI App | -| 14 | PE | L1+ | Each PE must implement a minimum of six breakpoints, two of which must be able to match virtual address, contextID or VMID | 4.2.1 | yes | UEFI App | -| 15 | PE | L0+ | All PE(s) are architecturally symetric (allowed exceptions in Appendix C) | 4.1.1 | yes | UEFI App | -| 17 | PE | L3+ | Each PE implements CRC32 instructions | 4.4.1 | yes | UEFI App | -| 18 | PE | L6+ | If PEs implement the Scalable Vector Extension (SVE) and the Statistical Profiling Extension (SPE), the PEs will implement Armv8.5-SPE | 4.5.1 | yes | UEFI App | -| 19 | PE | L4+ | All PEs must implement the RAS extension introduced in ARMv8.2 | 4.3.1 | yes | UEFI App | -| 20 | PE | L4+ | All PEs must implement support for 16-bit VMD | 4.3.1 | yes | UEFI App | -| 21 | PE | L4+ | All PEs must implement virtual host extensions | 4.3.1 | yes | UEFI App | -| 22 | PE | L4+ | If PEs implement ARMv8.3 pointer signing, the PEs must provide the standard algorithm defined by the ARM architecture | 4.4.1 | yes | UEFI App | -| 23 | PE | L5+ | All PEs must implement enhanced nested virtualization | 4.4.1 | yes | UEFI App | -| 24 | PE | L5+ | All PEs must support changing of page table mapping size using level1 and level2 solution proposed in the ARMv8.4 extension. Level2 is recommended | 4.4.1 | yes | UEFI App | -| 25 | PE | L5+ | All PEs must provide support for stage-2 control of memory types and cacheability, as introduced by ARMv8.4 extensions | 4.4.1 | yes | UEFI App | -| 26 | PE | L5+ | All PEs must implement the Activity Monitors Extension | 4.4.1 | yes | UEFI App | -| 27 | PE | L5+ | Where export control allows, all PEs must implement cryptography support for SHA3 and SHA512 | 4.4.1 | yes | UEFI App | -| 28 | PE | L6+ | Hardware updates to Access flag and Dirty state in translation tables, must be supported | 4.5.1 | yes | UEFI App | -| 29 | PE | L6+ | PEs must implement restrictions on speculation introduced in the Arm v8.5 extensions | 4.5.1 | yes | UEFI App | -| 30 | PE | L6+ | PEs must implement Speculative Store Bypass Safe | 4.5.1 | yes | UEFI App | -| 31 | PE | L6+ | PEs must implement the SB speculation barrier | 4.5.1 | yes | UEFI App | -| 32 | PE | L6+ | PEs must implement the CFP RCTX, DVP RCTX, CPP RCTX instructions | 4.5.1 | yes | UEFI App | -| 33 | PE | L6+ | PEs must provide support for Branch Target Identification | 4.5.1 | yes | UEFI App | -| 34 | PE | L6+ | PEs must protect against timing faults being used to guess page table mappings | 4.5.1 | yes | UEFI App | -| 35 | PE | L6+ | PEs will provide support for enhanced virtualization traps | 4.5.1 | yes | UEFI App | -| 36 | PE | L6+ | All PEs will implement Armv8.5-PMU | 4.5.1 | yes | UEFI App | -| 101 | GICv3 | L2+ | Interrupt controller shall conform to GICv3 specification | 4.3.2 | yes | UEFI App | -| 102 | GICv3 | L2+ | If the base server system includes PCI Express then the GICv3 interrupt controller shall implement ITS and LPI | 4.3.2 | yes | UEFI App | -| 103 | GIC | L3+ | The GICv3 interrupt controller shall support two Security states | 4.4.4 | yes | UEFI App | -| 104 | GICv2/3 | L2+ | GIC maintenance interrupt shall be wired as PPI 25 | 4.3.2.4 | yes | UEFI App | -| 201 | System counter and generic timer | L0+ | Must run between 10Mhz and 400Mhz | 4.1.5 | yes | UEFI App | -| 202 | System counter and generic timer | L1- | The local PE timer when expiring must generate a PPI when EL1 physical timer expires | 4.1.5 | yes | UEFI App | -| 202 | System counter and generic timer | L2+ | The local PE timer when expiring must generate a PPI when EL1 physical timer expires, and PPI must be 30 | 4.3.2.1 | yes | UEFI App | -| 203 | System counter and generic timer | L1- | The local PE timer when expiring must generate a PPI when the virtual timer expires | 4.1.5 | yes | UEFI App | -| 203 | System counter and generic timer | L2+ | The local PE timer when expiring must generate a PPI when the virtual timer expires, and PPI must be 27 | 4.3.2.1 | yes | UEFI App | -| 204 | System counter and generic timer | L1- | The local PE timer when expiring must generate a PPI when EL2 physical timer expires | 4.1.5 | yes | UEFI App | -| 204 | System counter and generic timer | L2+ | The local PE timer when expiring must generate a PPI when EL2 physical timer expires, and PPI must be 26 | 4.3.2.1 | yes | UEFI App | -| 205 | System counter and generic timer | L1- | For systems where PE are 8.1 or greater local PE timer when expiring must generate a PPI when EL2 virtual timer expires | 4.1.5 | yes | UEFI App | -| 205 | System counter and generic timer | L2+ | For systems where PE are 8.1 or greater local PE timer when expiring must generate a PPI when EL2 virtual timer expires, and PPI must be 28 | 4.3.2.1 | yes | UEFI App | -| 206 | System counter and generic timer | L1+ | In systems that implement EL3, the memory mapped timer (the CNTBaseN frame and associated CNTCTLBase frame) must be mapped into the Non-secure address space | 4.2.3. | yes | UEFI App | -| 206 | System counter and generic timer | L3+ | If the system includes a system wakeup timer, this memory-mapped timer must be mapped on to Non-secure address space | 4.4.6 | yes | UEFI App | -| 207 | System counter and generic timer | L1+ | Unless all local PE timers are Always ON, a system timer based on architecture memory mapped generic itmer view shall generate an SPI | 4.2.3 | yes | UEFI App | -| 208 | System counter and generic timer | L0 | A system specific system timer shall generate an SPI | 4.1.7 | yes | UEFI App | -| 301 | Watchdog | L1+ | system implements a Generic Watchdog as specified in APPENDIX A: Generic Watchdog. | | yes | UEFI App | -| 301 | Watchdog | L3+ | The watchdog required by level 2 must have both its register frames mapped on to Non-secure address space; this is referred to as the Non-secure watchdog | 4.4.7 | yes | UEFI App | -| 302 | Watchdog | L1- | Watchdog Signal 0 is routed as an SPI to the GIC and usable as a EL2 interrupt | 4.2.4 | yes | UEFI App | -| 302 | Watchdog | L2+ | Watchdog Signal 0 is routed as an SPIor LPI to the GIC and usable as a EL2 interrupt | 4.3.8 | yes | UEFI App | -| 303 | Watchdog | L5+ | A system compatible with level 5 will implement a generic counter which counts in nanosecond units. ARM strongly recommends that such systems use revision 1 of the generic watchdog | 4.4.4 | yes | UEFI App | -| 401 | PCIe | L1+ | Systems must map memory space to PCI Express configuration space, using the PCI Express Enhanced Configuration Access Mechanism (ECAM). Tests should be robust to ARI being implemented | 8.1 | yes | Linux driver | -| 402 | PCIe | L1+ | The base address of each ECAM region is discoverable from system firmware data | 8.1 | yes | Linux driver | -| 403 | PCIe | L1+ | PEs are able to access the ECAM region | 8.1 | yes | UEFI App | -| 801 | PCIe | L3+ | PEs are able to access the ECAM region | 8.1 | yes | Linux driver | -| 405 | PCIe | L1+ | All systems must support mapping PCI Express memory space as either device memory or non-cacheable memory | 8.2 | yes | Linux driver | -| 802 | PCIe | L3+ | All systems must support mapping PCI Express memory space as either device memory or non-cacheable memory | 8.2 | yes | UEFI App | -| 405 | PCIe | L1+ | When PCI Express memory space is mapped as normal memory, the system must support unaligned accesses to that region. | 8.2 | yes | Linux driver | -| 802 | PCIe | L3+ | When PCI Express memory space is mapped as normal memory, the system must support unaligned accesses to that region. | 8.2 | yes | UEFI App | -| 803 | PCIe | L3+ | PCIe I/O Coherency Scenarios with System MMU are covered | 8.3 | yes | UEFI App | -| 406 | PCIe | L0+ | In a system with a SMMU for PCI express there are no transformations to addresses being sent by PCI express devices before they are presented as an input address to the SMMU. | 8.3 | yes | Linux driver | -| 406 | PCIe | L3+ | the addresses sent by PCI express devices must be presented to the memory system or SMMU unmodified | 4.4.8 | yes | Linux driver | -| 407 | PCIe | L1+ | Support for Message Signaled Interrupts (MSI/MSI-X) is required for PCI Express devices. MSI and MSI-X are edge-triggered interrupts that are delivered as a memory write transaction | 8.4 | yes | Linux driver | -| 408 | PCIe | L1+ | each unique MSI(-X) shall trigger an interrupt with a unique ID and the MSI(-X) shall target GIC registers requiring no hardware specific software to service the interrupt | 8.4 | Yes | Linux driver | -| 804 | PCIe | L3+ | each unique MSI(-X) shall trigger an interrupt with a unique ID and the MSI(-X) shall target GIC registers requiring no hardware specific software to service the interrupt | 8.4 | Yes | UEFI App | -| | PCIe | L3+ | Add GICv2/v3 support details | 8.4.1/2 | No | Linux driver | -| 409 | GICv3 | L2+ | All MSIs and MSI-x are mapped to LPI | 4.3.2 | yes | Linux driver | -| 410 | PCIe | L3+ | If the system supports PCIe PASID, then at least 16 bits of PASID must be supported | 8.11 | yes | Linux driver | -| 805 | PCIe | L3+ | If the system supports PCIe PASID, then at least 16 bits of PASID must be supported | 8.11 | yes | UEFI App | -| 411 | PCIe | L0+ | The PCI Express root complex is in the same Inner Shareable domain as the PEs | 8.7 | yes | Linux driver | -| 412 | PCIe | L1+ | Each of the 4 legacy interrupt lines must be allocated a unique SPI ID and is programmed as level sensitive | 8.5 | yes | Linux driver | -| 806 | PCIe | L3+ | Each of the 4 legacy interrupt lines must be allocated a unique SPI ID and is programmed as level sensitive | 8.5 | yes | UEFI App | -| 413 | MemoryMap | L3+ | All Non-secure on-chip masters in a base server system that are expected to be under the control of the OS or hypervisor must be capable of addressing all of the NS address space. If the master goes through a SMMU then it must be capable of addressing all of the NS address space when the SMMU is off. | 4.4.3 | yes | Linux driver | -| 413 | MemoryMap / PCIe | L3+ | Non-secure off-chip devices that cannot directly address all of the Non-secure address space must be placed behind a stage 1 System MMU compatible with the ARM SMMUv2 or SMMUv3 specification. that has an output address size large enough to address all of the Non-secure address space. | 4.4.3 | yes | Linux driver | -| 414 | Peripheral Subsystems | L3+ | Memory Attributes of DMA traffic are one of (1) Inner WB, Outer WB, Inner Shareable (2) Inner/Outer Non-Cacheable (3) Device TypeIO Coherent DMA is as per (1) Inner/Outer WB, Inner Shareable | 4.4.8 | yes | Linux driver | -| 415 | PCIe | L0+ | PCI Express transactions not marked as No_snoop accessing memory that the PE translation tables attribute as cacheable and shared are I/O Coherent with the PEs. | 8.7 | yes | Linux driver | -| 807 | PCIe | L3+ | PCI Express transactions not marked as No_snoop accessing memory that the PE translation tables attribute as cacheable and shared are I/O Coherent with the PEs. | 8.7 | yes | UEFI App | -| 416 | PCIe | L4+ | For Non-prefetchable (NP) memory, type-1 headers only support 32bit address, systems complaint with SBSA level 4 or above must support 32bit programming of NP BARs on such endpoints | D.2 | yes | Linux driver | -| 417 | PCIe | L3+ | In a system where the PCIe hierarchy allows peer to peer transactions, the root ports in an ARM based SoC must implement PCIe access control service (ACS) features | D.13 | yes | Linux driver | -| 418 | PCIe | L3+ | All PCIe switches should support the minimal features, refer D.13 section for features list | D.13 | yes | Linux driver | -| 419 | PCIe | L3+ | All multi-function devices, SR-IOV and non-SR-IOV, that are capable of peer to peer traffic between different functions should support the minimal features, refer D.13 section for features list | D.13 | no | Linux driver | -| 420, 431, 432 | PCIe | L3+ | All PCIe devices, must implement the common registers of Type 0/1 header, as per requirements in E.3 and E.4 section | E.3/4 | yes | UEFI App -| 421, 434 | PCIe | L3+ | All PCIe devices, must implement the registers of Type 0/1 header, as per requirements in E.3/E.4/D.1 section | E.3 | yes | UEFI App -| 422 | PCIe | L3+ | All PCIe devices, must implement the registers of Type 1 header, as per requirements in E.4 section | E.3 | yes | UEFI App -| 423 | PCIe | L3+ | i-EP Root Port, must implement the registers of PCIe capability(10h), as per requirements in E.15 section | E.15 | yes | UEFI App -| 424, 433, 435 | PCIe | L3+ | All PCIe devices, must implement the Device capability register of PCIe capability(10h), as per requirements in E.14/15 section | E.14/15 | yes | UEFI App -| 425 | PCIe | L3+ | All PCIe devices, must implement the Device Control register of PCIe capability(10h), as per requirements in E.14/15 section | E.14/15 | yes | UEFI App -| 426, 436, 437 | PCIe | L3+ | All PCIe devices, must implement the Device capabilities 2 register of PCIe capability(10h), as per requirements in E.14/15 section | E.14/15 | yes | UEFI App -| 427 | PCIe | L3+ | All PCIe devices, must implement the Device control 2 register of PCIe capability(10h), as per requirements in E.14/15 section | E.14/15 | yes | UEFI App -| 428 | PCIe | L3+ | All PCIe devices, must implement the power management capability register of power management capability(01h), as per requirements in E.14/15 section | E.14/15 | yes | UEFI App -| 429 | PCIe | L3+ | All PCIe devices, must implement the power management control/status register of power management capability(01h), as per requirements in E.14/15 section | E.14/15 | yes | UEFI App -| 430 | PCIe | L3+ | Memory space access should raise Unsupported Request, when device Memory Space enable bit is clear | E.3/4 | yes | UEFI App -| 808 | PCIe | L3+ | If the Bus Master Enable (BME) bit in Command register is cleared, the i-EP Endpoint must not generate any memory read or write requests. | E.15.1 | yes | UEFI App -| 438, 439 | PCIe | L3+ | iEP root port must follow Completion timeout ranges supported, Completion timeout disable supported and AtomicOp routing supported bit as per Section E.15.11 | E.15.11 | yes | UEFI App -| 440 | PCIe | L3+ | root port must not support ATS and PRS extened capability | | yes | UEFI App -| 441 | PCIe | L3+ | RCiEP and iEP end point must support MSI or MSI-X interrupts | E.7 | yes | UEFI App -| 442 | PCIe | L3+ | RCiEP, iEP root port and iEP end point must support have Power Management Capability | E.11 | yes | UEFI App -| 443 | PCIe | L3+ | Root Port must implement ARI forwarding enable as per in E.15.12 section | E.15.12 | yes | UEFI App -| 444 | PCIe | L3+ | Root Port Configuration Space must be under same ECAM as the Configuration Space of Endpoints and switches in hierachy that originates from that port | D.1 | yes | UEFI App -| 445 | PCIe | L3+ | All Root Port Configuration Space under same Host Bridge must be in same ECAM | D.1 | yes | UEFI App -| 446 | PCIe | L3+ | The Root Port must comply with the byte enable rules and must support 1 byte, 2 byte and 4 byte Configuration read and write requests | D.1 | yes | UEFI App -| 447 | PCIe | L3+ | Must recognize and consume Configuration transactions intended for the Root Port Configurationspace and read/write the appropriate Root Port Configuration register | D.1 | yes | UEFI App -| 448 | PCIe | L3+ | Must recognize transactions received on the primary side of the RP PCI-PCI bridge, targeting non-prefetchable memory spaces of devices and switches that are on the secondary side of the bridge : Where the address falls within the non-prefetchable memory window in the type 1 header registers, the transactions must be forwarded to the secondary side | D.1 | yes | UEFI App -| 449 | PCIe | L3+ | Must recognize transactions received on the primary side of the RP PCI-PCI bridge, targeting prefetchable memory spaces of devices and switches that are on the secondary side of the bridge : Where the address falls within the prefetchable memory window in the type 1 header registers, the transactions must be forwarded to the secondary side | D.1 | yes | UEFI App -| 450 | PCIe | L3+ | Each legacy interrupt SPI must be programmed as level-sensitive in the appropriate GIC_ICFGR | D.6 | yes | UEFI App -| 451 | PCIe | L3+ | For i-EP, the Root Port must provide the ability to do a hot reset of the Endpoint using the Secondary Bus Reset bit in bridge Control Register | E.10 | yes | UEFI App -| 452 | PCIe | L3+ | PCIe ATS capability must be supported if the RCiEP or i-EP has a software visible cache for address translations | E.9 | yes | UEFI App -| 453 | PCIe | L3+ | If the PCIe hierarchy allows peer-to-peer transactions, Root Port must support ACS capability. | D.11 | yes | UEFI App -| 454 | PCIe | L3+ | If the PCIe hierarchy allows peer-to-peer transactions, The root port must support ACS violation error detection, Logging and reporting must be through the usage of AER mechanism | D.11 | yes | UEFI App -| 455 | PCIe | L3+ | If the Root port supports peer-to-peer traffic with other root ports then - If the root port supports Address Translation services and peer-to-peer traffic with other root ports, then it must support ACS direct translated P2P | D.11 | yes | UEFI App -| 456 | PCIe | L3+ | If the i-EP endpoint is capable of sending transactions to a peer endpoint (RCiEP or i-EP endpoint or discrete), then the i-EP root port must have ACS capability | E.12 | yes | UEFI App -| 457 | PCIe | L3+ | ACS capability must be present in the RCiEP or i-EP endpoint functions if the RCiEP or i-EP Endpoint isa multi-function device and supports peer to peer traffic between its functions. | E.12 | yes | UEFI App -| 809 | PCIe | L3+ | Configuration transactions indented for secondary bus of root port must be of Type0 | D.1 | yes | Baremetal -| 810 | PCIe | L3+ | Configuration transactions indented for subordinate bus range of root port must be of Type1 | D.1 | yes | Baremetal -| 811 | PCIe | L3+ | Check Address Translation Service Functional Check | E.9 | yes | UEFI App -| 812 | PCIe | L3+ | Check Peer-to-Peer ACS Source Validation & Transaction Blocking Functionality | D.11 | yes | UEFI App -| 813 | PCIe | L3+ | Check Peer-to-Peer ACS Redirected Request Validation Functionality | D.11 | yes | UEFI App -| 814 | PCIe | L3+ | PCI Express transactions marked as No_snoop accessing memory must have coherency managed by software . | D.8 | yes | UEFI App | -| 815 | PCIe | L3+ | Transactions that are targeted at devices must be treated as device type access. They must be ordered, must not merge and must not allocate in caches . | D.8.1 | yes | UEFI App | -| 816 | PCIe | L3+ | Root Port must implement ARI forwarding enable. | E.15 | yes | UEFI App | -| 504 | Watchdog | L1+ | Watchdog Signal 0 should be able to wakeup at least one PE from various low power states. Based off power states supported - this should be covered for 1 of N condition with some PEs in low power and from the lowest power stated where the Watchdog is ON. | 4.2.6 | yes | UEFI App | -| 504 | System counter and generic timer | L1+ | Unless all local PE timers are Always ON, a system timer based on architecture memory mapped generic timer view shall generate an SPI that wake the platform from states with semantics B,C,D,E,F,H,I | 4.2.3 | yes | UEFI App | -| 505 | System counter and generic timer | L0 | A system specific system timer shall generate an SPI that wake the platform from states with semantics B,C,D,E,F,H,I | 4.1.7 | no | UEFI App | -| 505 | Wakeup semantics | L0+ | Whilst in state F a PE must not wake upon receipt of an SGI, PPI or SPI that directly targets the PE | 4.3.4/7 | yes | UEFI App | -| 601 | Peripheral Subsystems | L0+ | If the system has a USB2.0 host controller peripheral it must conform to EHCI v1.1 or later - Peripheral subsystems which do not conform to the above are permitted, provided that they are not required to boot and install an OS | 4.1.8 | yes | UEFI App | -| 601 | Peripheral Subsystems | L0+ | If the system has a USB3.0 host controller peripheral it must conform to XHCI v1.0 or later - Peripheral subsystems which do not conform to the above are permitted, provided that they are not required to boot and install an OS | 4.1.8 | yes | UEFI App | -| 602 | Peripheral Subsystems | L0+ | If the system has a SATA host controller peripheral it must conform to AHCI v1.3 or later - Peripheral subsystems which do not conform to the above are permitted, provided that they are not required to boot and install an OS | 4.1.8 | yes | UEFI App | -| 603 | Peripheral Subsystems | L1+ | For the purpose of system development and bring up, the base server system shall include a Generic UART. The Generic UART is specified in Appendix B. The UARTINTR interrupt output is connected to the GIC as an SPI. | 4.2.7 | yes | UEFI App | -| 603 | Peripheral Subsystems | L3+ | Check that that Generic UART is mapped to Non-Secure address space | 4.4.8 | yes | UEFI App | -| 604 | Peripheral Subsystems | L2+ | UARTINTR of the generic UART shall be connected as SPI or LPI | 4.3.9 | yes | UEFI App | -| 605 | MemoryMap | L0+ | Accesses to part of the memory map that is unpopulated should not deadlock and cause a precise data abort, SEI or SPU interrupt delivered to the GIC | 4.1.3 | yes | UEFI App | -| 605 | MemoryMap | L2+ | Where a memory access is to an unpopulated part of the addressable memory space, accesses must be terminated in a manner that is presented to the PE as either a precise Data Abort or that causes a system error interrupt or an SPI or LPI interrupt to be delivered to the GIC. | 4.3.3 | yes | UEFI App | -| 701 | IO Virtualisation | L0+ | SMMU if present must spport a 64KB granule, For L1- this would be an SMMUv1 for L2 SMMUv2, and | 4.1.4 | yes | UEFI App | -| 702 | SMMU | L3+ | All the System MMUs in the system must the compliant with the same architecture version | 4.4.5 | yes | UEFI App | -| 703 | SMMU | L3+ | If SMMUv3 is in use, The integration of the System MMUs is compliant with the specification in APPENDIX H: SMMUv3 Integration | 4.4.5Appendix H | yes | UEFI App | -| 703 | IO Virtualisation | L2+ | Stage 2 System MMU functionality must be provided by a System MMU compatible with the ARM SMMUv2 spec | 4.3.5 | yes | UEFI App | -| 703 | SMMU | L3+ | Stage 2 System MMU functionality must be provided by a System MMU compatible with the ARM SMMUv2 or SMMUv3 specification | 4.4.5 | yes | UEFI App | -| 703 | PCIe | L1+ | Hardware support for I/O Virtualization is optional, but if required shall use a System MMU compliant with the ARM System MMU specification | 8.6 | yes | UEFI App | -| 703 | IO Virtualisation | L0+ | Policing is required at stage 2 | 4.1.4 | yes | UEFI App | -| 703 | SMMU | L4+ | Stage 1 and 2 SMMU functionality must be provided by a SMMU compatible with ARM SMMUv3 or higher | 4.3.2 | yes | UEFI App | -| 703 | SMMU | L5+ | SMMU implementations must be complaint with the ARM SMMUv3.2 architecture revision or higher | 4.3.2 | yes | UEFI App | -| 704 | SMMU | L3+ | The SMMUv3 spec requires that PCIe root complex must not use the stall model due to potential deadlock. | Appendix H | yes | UEFI App | -| 705 | SMMU | L3+ | If SMMUv2 is in use, Each context bank must present a unique physical interrupt to the GIC | 4.4.5 | yes | UEFI App | -| 706 | PCIe | L1+ | Each function, or virtual function, that requires hardware I/O virtualization is associated with a SMMU context. The programming of this association is IMPLEMENTATION DEFINED and is expected to be described by system firmware data. | 8.6 | yes | UEFI App | -| 707 | SMMU | L1+ | SMMU Version Check | 8.5.2 | yes | UEFI App | -| 708 | SMMU | L6+ | SMMU must implement support for 16 bit VMID. | 8.5.2 | yes | UEFI App | -| 709 | SMMU | L6+ | SMMU must implement support for 16 bit ASID. | 8.5.2 | yes | UEFI App | -| 710 | SMMU | L6+ | SMMU must support the translation granule sizes supported by the PEs. | 8.5.2 | yes | UEFI App | -| 711 | SMMU | L6+ | if PEs implement ARMv8.2-LVA, the SMMU must support extended virtual addresses | 8.5.2 | yes | UEFI App | -| 712 | SMMU | L3+ | if PEs implement Armv8.2-LPA, it follows that the SMMU must support a 52 bit output size | 8.5.2 | yes | UEFI App | -| 713 | SMMU | L6+ | The SMMU must implement coherent access to in memory structures, queues, and page tables | 8.5.2 | yes | UEFI App | -| 714 | SMMU | L6+ | The SMMU must support hardware translation table update (HTTU) of the Access flag and the Dirty state of the page for AArch64 translation tables. | 8.5.2 | yes | UEFI App | -| 715 | SMMU | L6+ | SMMU will support little endian for translation table walks, and at a minimum must match the endianness support of the PE's. | 8.5.2 | yes | UEFI App | -| 716 | SMMU | L6+ | The DVM capabilities of all DVM receivers (SMMUs and PEs) need to be the same or a superset of the DVM capabilities of all DVM initiators (PEs). Check For TLB Range Invalidation. | 8.5.2 | yes | UEFI App | -| 501, 502 | System counter and generic timer | L0+ | Any local timers that are marked by PE as always ON must be able to wake up the system. This applies to expiry of all non-secure views of the local timer (CNTV/P/HP/HV) | 4.1.7 | yes | UEFI App | -| 501,502,503,504| Wakeup semantics | L0+ | Whilst in state B a PE must be able to wake upon receipt of an SGI, PPI or SPI that directly targets the PE | 4.3.4/7 | yes | UEFI App | -| | PCIe | L1+ | only registers defined in the PCI Express specification and the ARM GIC specification are used to deliver legacy interrupts | 8.5 | yes | ARM Enterprise ACS package | -| | PCIe | L1+ | All end points claiming PCIe support must follow PCIe rules. | 8.9 | yes | ARM Enterprise ACS package | -| | Watchdog | L1+ | Watchdog Signal 1 is available. This may be confirmed in the data base. This may not be possible to exersice as its handling is platform specific | 4.2.4 | no | Secure FW | -| | Watchdog | L3 FW | The Watchdog Signal 1 is routed as a SPI to GIC and usable as an EL3 interrupt, directly targetting a single PE | 4.5.3 | no | Secure FW | -| | System counter and generic timer | L0+ | Must implement at least 56 bits | 4.1.5 | no | Secure FW | -| | System counter and generic timer | L0+ | The counter shall be sized and programmed to ensure that rollover never occurs in pract | 4.1.5 | no | Secure FW | -| | System counter and generic timer | L1+ | In systems that implement EL3, CNTControlBase should be mapped to Secure address space only | 4.2.3 | no | Secure FW | -| | System counter and generic timer | L1+ | Generic Timer required registers are implemented as specified in section 4.2.3.1 "Summary of required registers of the CNTControlBase frame" | 4.2.3.1 | no | Secure FW | -| | System counter and generic timer | L1- | The local PE timer when expiring must generate a PPI when EL3 physical timer expires | 4.1.5 | no | Secure FW | -| | System counter and generic timer | L2+ | The local PE timer when expiring must generate a PPI when EL3 physical timer expires, and PPI must be 29 | 4.3.2.1 | no | Secure FW | -| | System counter and generic timer | L0+ | Any local timers that are marked by PE as always ON must be able to wake up the system. This applies to expiry of all secure views of the local timer (CNTPS) | 4.1.7 | no | Secure FW | -| | Watchdog | L3 FW | Secure Watchdog is implemented. Secure watchdog is not-aliased in non-secure address space. Signal 0 if secure watchdog is routed as an SPI and usable as an interrupt to EL3, directly targetting a single PE | 4.5.3 | no | Secure FW | -| | Peripheral Subsystems | L3 FW | Secure Generic UART is present. It is not aliased in Non-secure address space. The UARTINTR output of the secure generic UART is connected to the GIC as an SPI | 4.5.4 | no | Secure FW | -| | System counter and generic timer | L3 FW | A secure system wakeup timer is present and the interrupt is presented to GIC as a SPI | 4.5.2 | no | Secure FW | -| | Wakeup semantics | L0+ | Whilst in state C a PE must be able to wake upon receipt of an SGI, PPI or SPI that directly targets the PE | 4.3.4/7 | no | | -| | Wakeup semantics | L0+ | Whilst in state D a PE must be able to wake upon receipt of an SGI, PPI or SPI that directly targets the PE | 4.3.4/7 | no | | -| | Wakeup semantics | L0+ | Whilst in state E a PE must be able to wake upon receipt of an SGI, PPI or SPI that directly targets the PE | 4.3.4/7 | no | | -| | Wakeup semantics | L0+ | Whilst in state G a PE must be able to wake upon receipt of an SGI, PPI or SPI that directly targets the PE | 4.3.4/7 | no | | -| | Wakeup semantics | L0+ | Whilst in state H a PE must be able to wake upon receipt of an SGI, PPI or SPI that directly targets the PE | 4.3.4/7 | no | | -| | Power State Semantics | L2+ | System MMUs and, in the future, GICv3, make use of tables in memory in the power states where GIC is ‘On’, system memory shall be available and will respond to requests without requiring intervention from software. | 4.1.7 | no | | -| | Wakeup semantics | L1+ | Power States A-I as described in "Requirements on power state semantics" shall be covered | 4.2.5 | no | | -| | PCIe | L0+ | PCI Express transactions marked as No_snoop accessing memory that the PE translation tables attribute as cacheable and shared behave correctly when appropriate SW coherence is deployed | 8.7 | no | | -| | PCIe | L3+ | Systems compatible with level 3 or above of the SBSA must not deadlock if PCI express devices attempt peer-to-peer transactions – even if the system does not support peer-to-peer traffic | 8.10 | no | | -| | Debug | L2+ | COMMIRQ interrupt for Debug Communications Channel will be wired as PPI 22 | 4.3.2.1 | no | | -| | Debug | L2+ | Cross trigger interface interrupt shall be wired as PPI 24 | 4.3.2.3 | no | | -| | System counter and generic timer | L2+ | Where a system wake up timer is present it shall generate an SPI or LPI that wake the platform from states with semantics B,C,D,E,F,H,I | 4.3.6 | no | | -| | Watchdog | L3 FW | Routing of Signal 1 of Secure Watchdog to Platform | 4.5.3 | no | | -| | Peripheral Subsystems | L3 FW | Some memory is mapped in secure address space. The memory shall not be aliased in Non-secure address space | 4.5.1 | no | | -| | SMMU | L4+ | All addresses output from a device to an SMMU must lie in a continuous space with no holes. All address in said space will be treated equally by the SMMU. There should be no areas within the address space that receive exceptional treatment, such as bypassing the SMMU | 4.3.2 | no | | -| | PE | L5+ | PEs based on ARMv8.4 must implement the requirements of the CS-BSA combination C [6] | 4.4.1 | no | | -| | PE | L5+ | All PEs must implement the Memory Partitioning and Monitoring Extension with a minimal configuration | 4.4.1 | no | | -| | PE | L2+ | PMBIRQ will be wired as PPI 21 | 4.3.2.2 | no | | -| | PE | L3+ | Where PEs implement the scalar vector extension, the vector length maximum must be at least 256 bits | 4.1.1 | no | | -| | System counter | L5+ | A system compatible with level 5 will implement counter scaling as described in the ARMv8.4 architecture | 4.4.4 | no | | -| | PE | L4+ | if the system contains persistent memory that is exposed to the OS, all PEs must support the clean to point of persistence instruction (DC CVAP). The instruction must be able to perform a clean to the point of persistence for all memory that is exposed as persistent memory to the OS | 4.3.1 | no | | -| | PCIe | L5+ | Any system that implements PCIe Precision Time Measurement (PTM) [8] must use the ARM architecture defined System Counter [2] as PTM master time source at the PTM root(s) | D.15 | no | | -| | IO Virtualisation | L3+ | ARMv8.4 introduces TLB Invalidation instructions which apply to a range of input addresses rather than just to a single address. If PEs used by the server base system support TLB range instructions, then all OS visible masters that contain a TLB must support range invalidates | 4.1.6 | no | | -| | System counter and generic timer | L3+ | Previous versions of the SBSA imposed an upper limit of 400Mhz. This is instead replaced by an upper limit on the roll over period | 4.1.7 | no | | -| | IO Virtualisation | L5+ | MPAM architecture requires that all masters that can access an MPAM controlled resource, must support passing MPAM ID information. Therefore, an SMMUv3.2 implementation must support the MPAM extension if the requests it serves access MPAM controlled resources | 4.4.3 | no | | -| | PCIe | L3+ | If the Root port supports peer to peer traffic with other root ports, then it must support minimal features. Refer D.13 section for features list | D.13 | no | | ## License Arm SBSA ACS is distributed under Apache v2.0 License. -------------- -*Copyright (c) 2018-2021, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.* diff --git a/test_pool/exerciser/operating_system/test_e017.c b/test_pool/exerciser/operating_system/test_e017.c index 02fe26c0..6de02d0c 100644 --- a/test_pool/exerciser/operating_system/test_e017.c +++ b/test_pool/exerciser/operating_system/test_e017.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/exerciser/operating_system/test_e018.c b/test_pool/exerciser/operating_system/test_e018.c index f8514267..94527283 100644 --- a/test_pool/exerciser/operating_system/test_e018.c +++ b/test_pool/exerciser/operating_system/test_e018.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2019-2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/exerciser/operating_system/test_e019.c b/test_pool/exerciser/operating_system/test_e019.c index 1d9ea2df..38735282 100644 --- a/test_pool/exerciser/operating_system/test_e019.c +++ b/test_pool/exerciser/operating_system/test_e019.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/exerciser/operating_system/test_e020.c b/test_pool/exerciser/operating_system/test_e020.c index 6baf5e3e..127a4938 100644 --- a/test_pool/exerciser/operating_system/test_e020.c +++ b/test_pool/exerciser/operating_system/test_e020.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); From b9d08f67c0628f5aa9b17143b2a0163a7a310c00 Mon Sep 17 00:00:00 2001 From: Rajat Goyal Date: Mon, 16 Jan 2023 14:58:34 +0530 Subject: [PATCH 7/8] SBSA Updated Copyright Year Signed-off-by: Rajat Goyal --- linux_app/pmu_app/build_pmu.sh | 2 +- linux_app/pmu_app/pmuval/sbsa_acs_pmu.py | 2 +- linux_app/pmu_app/pyperf/pyperf/README.md | 2 +- linux_app/pmu_app/pyperf/pyperf/datamap.py | 2 +- linux_app/pmu_app/pyperf/pyperf/elf.py | 2 +- linux_app/pmu_app/pyperf/pyperf/hexdump.py | 2 +- linux_app/pmu_app/pyperf/pyperf/imagemap.py | 2 +- linux_app/pmu_app/pyperf/pyperf/perf_abi.py | 2 +- linux_app/pmu_app/pyperf/pyperf/perf_attr.py | 2 +- linux_app/pmu_app/pyperf/pyperf/perf_aux_arm_spe.py | 2 +- linux_app/pmu_app/pyperf/pyperf/perf_aux_cs_etm.py | 2 +- linux_app/pmu_app/pyperf/pyperf/perf_buildid.py | 2 +- linux_app/pmu_app/pyperf/pyperf/perf_data.py | 2 +- linux_app/pmu_app/pyperf/pyperf/perf_enum.py | 2 +- linux_app/pmu_app/pyperf/pyperf/perf_espec.py | 2 +- linux_app/pmu_app/pyperf/pyperf/perf_parse.py | 2 +- linux_app/pmu_app/pyperf/pyperf/perf_sysfs.py | 2 +- linux_app/pmu_app/pyperf/pyperf/perf_util.py | 2 +- linux_app/pmu_app/pyperf/pyperf/perf_zstd.py | 2 +- linux_app/pmu_app/pyperf/setup.py | 2 +- linux_app/pmu_app/pyperf/src/NOTES.txt | 2 +- linux_app/pmu_app/pyperf/src/pyperf_events.c | 2 +- linux_app/pmu_app/pysweep/setup.py | 2 +- linux_app/pmu_app/pysweep/src/arch.h | 2 +- linux_app/pmu_app/pysweep/src/branch_prediction.c | 2 +- linux_app/pmu_app/pysweep/src/branch_prediction.h | 2 +- linux_app/pmu_app/pysweep/src/denormals.c | 2 +- linux_app/pmu_app/pysweep/src/denormals.h | 2 +- linux_app/pmu_app/pysweep/src/genelf.c | 2 +- linux_app/pmu_app/pysweep/src/genelf.h | 2 +- linux_app/pmu_app/pysweep/src/loadcode.c | 2 +- linux_app/pmu_app/pysweep/src/loaddata.c | 2 +- linux_app/pmu_app/pysweep/src/loadgen.c | 2 +- linux_app/pmu_app/pysweep/src/loadgen.h | 2 +- linux_app/pmu_app/pysweep/src/loadgenp.h | 2 +- linux_app/pmu_app/pysweep/src/loadinst.c | 2 +- linux_app/pmu_app/pysweep/src/loadinst.h | 2 +- linux_app/pmu_app/pysweep/src/prepcode.c | 2 +- linux_app/pmu_app/pysweep/src/prepcode.h | 2 +- linux_app/pmu_app/pysweep/src/pysweep.c | 2 +- linux_app/pmu_app/pysweep/src/sleep.c | 2 +- linux_app/pmu_app/pysweep/src/sleep.h | 2 +- linux_app/pmu_app/pysweep/tests/code_template.c | 2 +- linux_app/sbsa-acs-app/sbsa_app_smmu.c | 2 +- platform/pal_uefi/include/pal_mpam.h | 2 +- platform/pal_uefi/include/pal_pmu.h | 2 +- platform/pal_uefi/include/pal_ras.h | 2 +- platform/pal_uefi/src/pal_hmat.c | 2 +- platform/pal_uefi/src/pal_mpam.c | 2 +- platform/pal_uefi/src/pal_pmu.c | 2 +- platform/pal_uefi/src/pal_ras.c | 2 +- test_pool/gic/operating_system/test_g001.c | 2 +- test_pool/gic/operating_system/test_g002.c | 2 +- test_pool/memory_map/operating_system/test_m001.c | 2 +- test_pool/mpam/operating_system/test_mpam001.c | 2 +- test_pool/mpam/operating_system/test_mpam002.c | 2 +- test_pool/mpam/operating_system/test_mpam003.c | 2 +- test_pool/mpam/operating_system/test_mpam004.c | 2 +- test_pool/mpam/operating_system/test_mpam005.c | 2 +- test_pool/mpam/operating_system/test_mpam006.c | 2 +- test_pool/pcie/operating_system/test_p009.c | 2 +- test_pool/pcie/operating_system/test_p061.c | 2 +- test_pool/pcie/operating_system/test_p062.c | 2 +- test_pool/pe/operating_system/test_c004.c | 2 +- test_pool/pe/operating_system/test_c006.c | 2 +- test_pool/pe/operating_system/test_c015.c | 2 +- test_pool/pe/operating_system/test_c016.c | 2 +- test_pool/pe/operating_system/test_c028.c | 2 +- test_pool/pe/operating_system/test_c029.c | 2 +- test_pool/pe/operating_system/test_c030.c | 2 +- test_pool/pe/operating_system/test_c031.c | 2 +- test_pool/pe/operating_system/test_c032.c | 2 +- test_pool/pe/operating_system/test_c033.c | 2 +- test_pool/pe/operating_system/test_c034.c | 2 +- test_pool/pe/operating_system/test_c035.c | 2 +- test_pool/pe/operating_system/test_c036.c | 2 +- test_pool/pe/operating_system/test_c037.c | 2 +- test_pool/pmu/operating_system/test_pmu003.c | 2 +- test_pool/pmu/operating_system/test_pmu004.c | 2 +- test_pool/pmu/operating_system/test_pmu005.c | 2 +- test_pool/pmu/operating_system/test_pmu006.c | 2 +- test_pool/pmu/operating_system/test_pmu007.c | 2 +- test_pool/pmu/operating_system/test_pmu008.c | 2 +- test_pool/ras/operating_system/test_ras001.c | 2 +- test_pool/ras/operating_system/test_ras002.c | 2 +- test_pool/ras/operating_system/test_ras003.c | 2 +- test_pool/ras/operating_system/test_ras004.c | 2 +- test_pool/ras/operating_system/test_ras005.c | 2 +- test_pool/ras/operating_system/test_ras006.c | 2 +- test_pool/ras/operating_system/test_ras007.c | 2 +- test_pool/ras/operating_system/test_ras008.c | 2 +- test_pool/ras/operating_system/test_ras009.c | 2 +- test_pool/ras/operating_system/test_ras010.c | 2 +- test_pool/ras/operating_system/test_ras011.c | 2 +- test_pool/ras/operating_system/test_ras012.c | 2 +- test_pool/smmu/operating_system/test_i003.c | 2 +- test_pool/smmu/operating_system/test_i004.c | 2 +- test_pool/smmu/operating_system/test_i007.c | 2 +- test_pool/smmu/operating_system/test_i013.c | 2 +- test_pool/smmu/operating_system/test_i014.c | 2 +- test_pool/smmu/operating_system/test_i016.c | 2 +- test_pool/test_pool.mk | 2 +- val/include/sbsa_avs_mmu.h | 2 +- val/include/sbsa_avs_mpam.h | 2 +- val/include/sbsa_avs_mpam_reg.h | 2 +- val/include/sbsa_avs_pmu_reg.h | 2 +- val/include/sbsa_avs_ras.h | 2 +- val/src/AArch64/MpamSupport.s | 2 +- val/src/AArch64/RasSupport.S | 2 +- val/src/avs_mmu.c | 2 +- val/src/avs_mpam.c | 2 +- val/src/avs_ras.c | 2 +- 112 files changed, 112 insertions(+), 112 deletions(-) diff --git a/linux_app/pmu_app/build_pmu.sh b/linux_app/pmu_app/build_pmu.sh index f5860297..9c16cdbc 100755 --- a/linux_app/pmu_app/build_pmu.sh +++ b/linux_app/pmu_app/build_pmu.sh @@ -1,7 +1,7 @@ # #!/usr/bin/env bash # @file - # Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + # Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pmuval/sbsa_acs_pmu.py b/linux_app/pmu_app/pmuval/sbsa_acs_pmu.py index aef8668e..c474ccca 100644 --- a/linux_app/pmu_app/pmuval/sbsa_acs_pmu.py +++ b/linux_app/pmu_app/pmuval/sbsa_acs_pmu.py @@ -1,4 +1,4 @@ -# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pyperf/pyperf/README.md b/linux_app/pmu_app/pyperf/pyperf/README.md index 0cb1a11a..e97e86d7 100644 --- a/linux_app/pmu_app/pyperf/pyperf/README.md +++ b/linux_app/pmu_app/pyperf/pyperf/README.md @@ -26,4 +26,4 @@ These modules replicate some of the functionality of the userspace perf tools: -------------- -*Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.* diff --git a/linux_app/pmu_app/pyperf/pyperf/datamap.py b/linux_app/pmu_app/pyperf/pyperf/datamap.py index 21d1b231..8947c5ed 100644 --- a/linux_app/pmu_app/pyperf/pyperf/datamap.py +++ b/linux_app/pmu_app/pyperf/pyperf/datamap.py @@ -1,4 +1,4 @@ -# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pyperf/pyperf/elf.py b/linux_app/pmu_app/pyperf/pyperf/elf.py index a86223cd..842f26c8 100644 --- a/linux_app/pmu_app/pyperf/pyperf/elf.py +++ b/linux_app/pmu_app/pyperf/pyperf/elf.py @@ -1,4 +1,4 @@ -# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pyperf/pyperf/hexdump.py b/linux_app/pmu_app/pyperf/pyperf/hexdump.py index cc0cee22..a689ff4d 100644 --- a/linux_app/pmu_app/pyperf/pyperf/hexdump.py +++ b/linux_app/pmu_app/pyperf/pyperf/hexdump.py @@ -1,4 +1,4 @@ -# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pyperf/pyperf/imagemap.py b/linux_app/pmu_app/pyperf/pyperf/imagemap.py index 8e5181f2..f0a90b3a 100644 --- a/linux_app/pmu_app/pyperf/pyperf/imagemap.py +++ b/linux_app/pmu_app/pyperf/pyperf/imagemap.py @@ -1,4 +1,4 @@ -# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pyperf/pyperf/perf_abi.py b/linux_app/pmu_app/pyperf/pyperf/perf_abi.py index c782ab33..ae0b280e 100644 --- a/linux_app/pmu_app/pyperf/pyperf/perf_abi.py +++ b/linux_app/pmu_app/pyperf/pyperf/perf_abi.py @@ -1,4 +1,4 @@ -# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pyperf/pyperf/perf_attr.py b/linux_app/pmu_app/pyperf/pyperf/perf_attr.py index a3d1b483..0b1c7e15 100644 --- a/linux_app/pmu_app/pyperf/pyperf/perf_attr.py +++ b/linux_app/pmu_app/pyperf/pyperf/perf_attr.py @@ -1,4 +1,4 @@ -# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pyperf/pyperf/perf_aux_arm_spe.py b/linux_app/pmu_app/pyperf/pyperf/perf_aux_arm_spe.py index 89bef3c5..f1836389 100644 --- a/linux_app/pmu_app/pyperf/pyperf/perf_aux_arm_spe.py +++ b/linux_app/pmu_app/pyperf/pyperf/perf_aux_arm_spe.py @@ -1,4 +1,4 @@ -# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pyperf/pyperf/perf_aux_cs_etm.py b/linux_app/pmu_app/pyperf/pyperf/perf_aux_cs_etm.py index febdabd2..6116bf07 100644 --- a/linux_app/pmu_app/pyperf/pyperf/perf_aux_cs_etm.py +++ b/linux_app/pmu_app/pyperf/pyperf/perf_aux_cs_etm.py @@ -1,4 +1,4 @@ -# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pyperf/pyperf/perf_buildid.py b/linux_app/pmu_app/pyperf/pyperf/perf_buildid.py index 66726b2a..62a2afe7 100644 --- a/linux_app/pmu_app/pyperf/pyperf/perf_buildid.py +++ b/linux_app/pmu_app/pyperf/pyperf/perf_buildid.py @@ -1,4 +1,4 @@ -# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pyperf/pyperf/perf_data.py b/linux_app/pmu_app/pyperf/pyperf/perf_data.py index 2162fd3d..076b1789 100644 --- a/linux_app/pmu_app/pyperf/pyperf/perf_data.py +++ b/linux_app/pmu_app/pyperf/pyperf/perf_data.py @@ -1,4 +1,4 @@ -# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pyperf/pyperf/perf_enum.py b/linux_app/pmu_app/pyperf/pyperf/perf_enum.py index 70589344..bdb55be4 100644 --- a/linux_app/pmu_app/pyperf/pyperf/perf_enum.py +++ b/linux_app/pmu_app/pyperf/pyperf/perf_enum.py @@ -1,4 +1,4 @@ -# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pyperf/pyperf/perf_espec.py b/linux_app/pmu_app/pyperf/pyperf/perf_espec.py index 1491c9b5..a2e145b6 100644 --- a/linux_app/pmu_app/pyperf/pyperf/perf_espec.py +++ b/linux_app/pmu_app/pyperf/pyperf/perf_espec.py @@ -1,4 +1,4 @@ -# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pyperf/pyperf/perf_parse.py b/linux_app/pmu_app/pyperf/pyperf/perf_parse.py index 8e6ce771..5d5df9e4 100644 --- a/linux_app/pmu_app/pyperf/pyperf/perf_parse.py +++ b/linux_app/pmu_app/pyperf/pyperf/perf_parse.py @@ -1,4 +1,4 @@ -# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pyperf/pyperf/perf_sysfs.py b/linux_app/pmu_app/pyperf/pyperf/perf_sysfs.py index 4843a9ae..b13847be 100644 --- a/linux_app/pmu_app/pyperf/pyperf/perf_sysfs.py +++ b/linux_app/pmu_app/pyperf/pyperf/perf_sysfs.py @@ -1,4 +1,4 @@ -# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pyperf/pyperf/perf_util.py b/linux_app/pmu_app/pyperf/pyperf/perf_util.py index d7908c11..16c9e8d2 100644 --- a/linux_app/pmu_app/pyperf/pyperf/perf_util.py +++ b/linux_app/pmu_app/pyperf/pyperf/perf_util.py @@ -1,4 +1,4 @@ -# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pyperf/pyperf/perf_zstd.py b/linux_app/pmu_app/pyperf/pyperf/perf_zstd.py index 579f66e1..58fb396e 100644 --- a/linux_app/pmu_app/pyperf/pyperf/perf_zstd.py +++ b/linux_app/pmu_app/pyperf/pyperf/perf_zstd.py @@ -1,4 +1,4 @@ -# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pyperf/setup.py b/linux_app/pmu_app/pyperf/setup.py index ff6ef31a..c94b2dbb 100644 --- a/linux_app/pmu_app/pyperf/setup.py +++ b/linux_app/pmu_app/pyperf/setup.py @@ -1,4 +1,4 @@ -# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pyperf/src/NOTES.txt b/linux_app/pmu_app/pyperf/src/NOTES.txt index e751b8c3..2f83dd20 100644 --- a/linux_app/pmu_app/pyperf/src/NOTES.txt +++ b/linux_app/pmu_app/pyperf/src/NOTES.txt @@ -36,5 +36,5 @@ Internally: -------------- -*Copyright (c) 2022, Arm Limited and Contributors. All rights reserved.* +*Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.* diff --git a/linux_app/pmu_app/pyperf/src/pyperf_events.c b/linux_app/pmu_app/pyperf/src/pyperf_events.c index 3fca4569..dda188b5 100644 --- a/linux_app/pmu_app/pyperf/src/pyperf_events.c +++ b/linux_app/pmu_app/pyperf/src/pyperf_events.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pysweep/setup.py b/linux_app/pmu_app/pysweep/setup.py index 4c09bf6b..75e61525 100644 --- a/linux_app/pmu_app/pysweep/setup.py +++ b/linux_app/pmu_app/pysweep/setup.py @@ -1,4 +1,4 @@ -# Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pysweep/src/arch.h b/linux_app/pmu_app/pysweep/src/arch.h index 225fc98b..cd44281c 100644 --- a/linux_app/pmu_app/pysweep/src/arch.h +++ b/linux_app/pmu_app/pysweep/src/arch.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pysweep/src/branch_prediction.c b/linux_app/pmu_app/pysweep/src/branch_prediction.c index 9c6695b0..c04f1c40 100644 --- a/linux_app/pmu_app/pysweep/src/branch_prediction.c +++ b/linux_app/pmu_app/pysweep/src/branch_prediction.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pysweep/src/branch_prediction.h b/linux_app/pmu_app/pysweep/src/branch_prediction.h index ff4132ed..1196e13d 100644 --- a/linux_app/pmu_app/pysweep/src/branch_prediction.h +++ b/linux_app/pmu_app/pysweep/src/branch_prediction.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pysweep/src/denormals.c b/linux_app/pmu_app/pysweep/src/denormals.c index fba07c9b..f41337f2 100644 --- a/linux_app/pmu_app/pysweep/src/denormals.c +++ b/linux_app/pmu_app/pysweep/src/denormals.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pysweep/src/denormals.h b/linux_app/pmu_app/pysweep/src/denormals.h index bf63cfdb..4f1eb485 100644 --- a/linux_app/pmu_app/pysweep/src/denormals.h +++ b/linux_app/pmu_app/pysweep/src/denormals.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pysweep/src/genelf.c b/linux_app/pmu_app/pysweep/src/genelf.c index b5b2ae85..fb1ec047 100644 --- a/linux_app/pmu_app/pysweep/src/genelf.c +++ b/linux_app/pmu_app/pysweep/src/genelf.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pysweep/src/genelf.h b/linux_app/pmu_app/pysweep/src/genelf.h index 9c4ad4ab..0f7edee8 100644 --- a/linux_app/pmu_app/pysweep/src/genelf.h +++ b/linux_app/pmu_app/pysweep/src/genelf.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pysweep/src/loadcode.c b/linux_app/pmu_app/pysweep/src/loadcode.c index b2844374..32638cbf 100644 --- a/linux_app/pmu_app/pysweep/src/loadcode.c +++ b/linux_app/pmu_app/pysweep/src/loadcode.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pysweep/src/loaddata.c b/linux_app/pmu_app/pysweep/src/loaddata.c index ba204274..aefb22ce 100644 --- a/linux_app/pmu_app/pysweep/src/loaddata.c +++ b/linux_app/pmu_app/pysweep/src/loaddata.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pysweep/src/loadgen.c b/linux_app/pmu_app/pysweep/src/loadgen.c index 5b7ef31f..9f8e4c82 100644 --- a/linux_app/pmu_app/pysweep/src/loadgen.c +++ b/linux_app/pmu_app/pysweep/src/loadgen.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pysweep/src/loadgen.h b/linux_app/pmu_app/pysweep/src/loadgen.h index 1a357607..31ccb08b 100644 --- a/linux_app/pmu_app/pysweep/src/loadgen.h +++ b/linux_app/pmu_app/pysweep/src/loadgen.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pysweep/src/loadgenp.h b/linux_app/pmu_app/pysweep/src/loadgenp.h index 2bedc45b..d13efb9c 100644 --- a/linux_app/pmu_app/pysweep/src/loadgenp.h +++ b/linux_app/pmu_app/pysweep/src/loadgenp.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pysweep/src/loadinst.c b/linux_app/pmu_app/pysweep/src/loadinst.c index 58e2c2f7..0039a3d2 100644 --- a/linux_app/pmu_app/pysweep/src/loadinst.c +++ b/linux_app/pmu_app/pysweep/src/loadinst.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pysweep/src/loadinst.h b/linux_app/pmu_app/pysweep/src/loadinst.h index e367731d..2256c7fb 100644 --- a/linux_app/pmu_app/pysweep/src/loadinst.h +++ b/linux_app/pmu_app/pysweep/src/loadinst.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pysweep/src/prepcode.c b/linux_app/pmu_app/pysweep/src/prepcode.c index 880d0744..5c1c01e6 100644 --- a/linux_app/pmu_app/pysweep/src/prepcode.c +++ b/linux_app/pmu_app/pysweep/src/prepcode.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pysweep/src/prepcode.h b/linux_app/pmu_app/pysweep/src/prepcode.h index 83aecd5f..2291d06f 100644 --- a/linux_app/pmu_app/pysweep/src/prepcode.h +++ b/linux_app/pmu_app/pysweep/src/prepcode.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pysweep/src/pysweep.c b/linux_app/pmu_app/pysweep/src/pysweep.c index cc857ff7..cfc32254 100644 --- a/linux_app/pmu_app/pysweep/src/pysweep.c +++ b/linux_app/pmu_app/pysweep/src/pysweep.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pysweep/src/sleep.c b/linux_app/pmu_app/pysweep/src/sleep.c index 53e09b71..3f356a95 100644 --- a/linux_app/pmu_app/pysweep/src/sleep.c +++ b/linux_app/pmu_app/pysweep/src/sleep.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pysweep/src/sleep.h b/linux_app/pmu_app/pysweep/src/sleep.h index 9ab03b7a..9c0bd892 100644 --- a/linux_app/pmu_app/pysweep/src/sleep.h +++ b/linux_app/pmu_app/pysweep/src/sleep.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/pmu_app/pysweep/tests/code_template.c b/linux_app/pmu_app/pysweep/tests/code_template.c index 2a8200ac..22e24bab 100644 --- a/linux_app/pmu_app/pysweep/tests/code_template.c +++ b/linux_app/pmu_app/pysweep/tests/code_template.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/linux_app/sbsa-acs-app/sbsa_app_smmu.c b/linux_app/sbsa-acs-app/sbsa_app_smmu.c index 4c97382b..f73ff85b 100644 --- a/linux_app/sbsa-acs-app/sbsa_app_smmu.c +++ b/linux_app/sbsa-acs-app/sbsa_app_smmu.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/platform/pal_uefi/include/pal_mpam.h b/platform/pal_uefi/include/pal_mpam.h index a63b23d0..ff0baf8c 100644 --- a/platform/pal_uefi/include/pal_mpam.h +++ b/platform/pal_uefi/include/pal_mpam.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/platform/pal_uefi/include/pal_pmu.h b/platform/pal_uefi/include/pal_pmu.h index 35ff2b59..57eadd6e 100644 --- a/platform/pal_uefi/include/pal_pmu.h +++ b/platform/pal_uefi/include/pal_pmu.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022-2023, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/platform/pal_uefi/include/pal_ras.h b/platform/pal_uefi/include/pal_ras.h index 9205743a..e38a4710 100644 --- a/platform/pal_uefi/include/pal_ras.h +++ b/platform/pal_uefi/include/pal_ras.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/platform/pal_uefi/src/pal_hmat.c b/platform/pal_uefi/src/pal_hmat.c index 96a3aff6..3052d1c3 100644 --- a/platform/pal_uefi/src/pal_hmat.c +++ b/platform/pal_uefi/src/pal_hmat.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/platform/pal_uefi/src/pal_mpam.c b/platform/pal_uefi/src/pal_mpam.c index edc11419..e7d39f04 100644 --- a/platform/pal_uefi/src/pal_mpam.c +++ b/platform/pal_uefi/src/pal_mpam.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/platform/pal_uefi/src/pal_pmu.c b/platform/pal_uefi/src/pal_pmu.c index a6e57406..5232cd35 100644 --- a/platform/pal_uefi/src/pal_pmu.c +++ b/platform/pal_uefi/src/pal_pmu.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022-2023 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/platform/pal_uefi/src/pal_ras.c b/platform/pal_uefi/src/pal_ras.c index 10717f19..0a0128bb 100644 --- a/platform/pal_uefi/src/pal_ras.c +++ b/platform/pal_uefi/src/pal_ras.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/gic/operating_system/test_g001.c b/test_pool/gic/operating_system/test_g001.c index f346f19a..e441fef1 100644 --- a/test_pool/gic/operating_system/test_g001.c +++ b/test_pool/gic/operating_system/test_g001.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2021-2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2021-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/gic/operating_system/test_g002.c b/test_pool/gic/operating_system/test_g002.c index a749ffc0..10ea0872 100644 --- a/test_pool/gic/operating_system/test_g002.c +++ b/test_pool/gic/operating_system/test_g002.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/memory_map/operating_system/test_m001.c b/test_pool/memory_map/operating_system/test_m001.c index 670fa181..3fb6e5e2 100644 --- a/test_pool/memory_map/operating_system/test_m001.c +++ b/test_pool/memory_map/operating_system/test_m001.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/mpam/operating_system/test_mpam001.c b/test_pool/mpam/operating_system/test_mpam001.c index c9e76846..af50068c 100644 --- a/test_pool/mpam/operating_system/test_mpam001.c +++ b/test_pool/mpam/operating_system/test_mpam001.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/mpam/operating_system/test_mpam002.c b/test_pool/mpam/operating_system/test_mpam002.c index ad3ffc50..159959e7 100644 --- a/test_pool/mpam/operating_system/test_mpam002.c +++ b/test_pool/mpam/operating_system/test_mpam002.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/mpam/operating_system/test_mpam003.c b/test_pool/mpam/operating_system/test_mpam003.c index 94a8cc7e..b53085e7 100644 --- a/test_pool/mpam/operating_system/test_mpam003.c +++ b/test_pool/mpam/operating_system/test_mpam003.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/mpam/operating_system/test_mpam004.c b/test_pool/mpam/operating_system/test_mpam004.c index 7db82c2b..45f9b1ba 100644 --- a/test_pool/mpam/operating_system/test_mpam004.c +++ b/test_pool/mpam/operating_system/test_mpam004.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/mpam/operating_system/test_mpam005.c b/test_pool/mpam/operating_system/test_mpam005.c index 33b32070..b9231ee5 100644 --- a/test_pool/mpam/operating_system/test_mpam005.c +++ b/test_pool/mpam/operating_system/test_mpam005.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/mpam/operating_system/test_mpam006.c b/test_pool/mpam/operating_system/test_mpam006.c index 484712a8..4e972c7a 100644 --- a/test_pool/mpam/operating_system/test_mpam006.c +++ b/test_pool/mpam/operating_system/test_mpam006.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pcie/operating_system/test_p009.c b/test_pool/pcie/operating_system/test_p009.c index 96ca8bbd..d8082820 100644 --- a/test_pool/pcie/operating_system/test_p009.c +++ b/test_pool/pcie/operating_system/test_p009.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2021-2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2021-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pcie/operating_system/test_p061.c b/test_pool/pcie/operating_system/test_p061.c index 0baee70c..42151df9 100644 --- a/test_pool/pcie/operating_system/test_p061.c +++ b/test_pool/pcie/operating_system/test_p061.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pcie/operating_system/test_p062.c b/test_pool/pcie/operating_system/test_p062.c index 645bf0c7..753b1ff6 100644 --- a/test_pool/pcie/operating_system/test_p062.c +++ b/test_pool/pcie/operating_system/test_p062.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c004.c b/test_pool/pe/operating_system/test_c004.c index c1d44cb0..280ddd8b 100644 --- a/test_pool/pe/operating_system/test_c004.c +++ b/test_pool/pe/operating_system/test_c004.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c006.c b/test_pool/pe/operating_system/test_c006.c index 25e9bc8a..67d11da6 100644 --- a/test_pool/pe/operating_system/test_c006.c +++ b/test_pool/pe/operating_system/test_c006.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c015.c b/test_pool/pe/operating_system/test_c015.c index 56c82fb6..e88fbaa6 100644 --- a/test_pool/pe/operating_system/test_c015.c +++ b/test_pool/pe/operating_system/test_c015.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c016.c b/test_pool/pe/operating_system/test_c016.c index f5bc52e3..9c0869a2 100644 --- a/test_pool/pe/operating_system/test_c016.c +++ b/test_pool/pe/operating_system/test_c016.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c028.c b/test_pool/pe/operating_system/test_c028.c index fae8bdd7..7b794d90 100644 --- a/test_pool/pe/operating_system/test_c028.c +++ b/test_pool/pe/operating_system/test_c028.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c029.c b/test_pool/pe/operating_system/test_c029.c index 13fa0c5e..4b8723f3 100644 --- a/test_pool/pe/operating_system/test_c029.c +++ b/test_pool/pe/operating_system/test_c029.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c030.c b/test_pool/pe/operating_system/test_c030.c index 5c2939b7..76a8b30d 100644 --- a/test_pool/pe/operating_system/test_c030.c +++ b/test_pool/pe/operating_system/test_c030.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c031.c b/test_pool/pe/operating_system/test_c031.c index e215ee28..74211370 100644 --- a/test_pool/pe/operating_system/test_c031.c +++ b/test_pool/pe/operating_system/test_c031.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c032.c b/test_pool/pe/operating_system/test_c032.c index d68047de..73acf74e 100644 --- a/test_pool/pe/operating_system/test_c032.c +++ b/test_pool/pe/operating_system/test_c032.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c033.c b/test_pool/pe/operating_system/test_c033.c index 1289c151..2f0974e0 100644 --- a/test_pool/pe/operating_system/test_c033.c +++ b/test_pool/pe/operating_system/test_c033.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c034.c b/test_pool/pe/operating_system/test_c034.c index dfca79ae..7124fa76 100644 --- a/test_pool/pe/operating_system/test_c034.c +++ b/test_pool/pe/operating_system/test_c034.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c035.c b/test_pool/pe/operating_system/test_c035.c index 0febe50d..39961e67 100644 --- a/test_pool/pe/operating_system/test_c035.c +++ b/test_pool/pe/operating_system/test_c035.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c036.c b/test_pool/pe/operating_system/test_c036.c index cc6a09f1..48fff31c 100644 --- a/test_pool/pe/operating_system/test_c036.c +++ b/test_pool/pe/operating_system/test_c036.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c037.c b/test_pool/pe/operating_system/test_c037.c index a8014bd1..4f7a02e2 100644 --- a/test_pool/pe/operating_system/test_c037.c +++ b/test_pool/pe/operating_system/test_c037.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pmu/operating_system/test_pmu003.c b/test_pool/pmu/operating_system/test_pmu003.c index 061b6956..52f12e07 100644 --- a/test_pool/pmu/operating_system/test_pmu003.c +++ b/test_pool/pmu/operating_system/test_pmu003.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pmu/operating_system/test_pmu004.c b/test_pool/pmu/operating_system/test_pmu004.c index 43d6e89b..967364af 100644 --- a/test_pool/pmu/operating_system/test_pmu004.c +++ b/test_pool/pmu/operating_system/test_pmu004.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pmu/operating_system/test_pmu005.c b/test_pool/pmu/operating_system/test_pmu005.c index 674b0830..3e01ca42 100644 --- a/test_pool/pmu/operating_system/test_pmu005.c +++ b/test_pool/pmu/operating_system/test_pmu005.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pmu/operating_system/test_pmu006.c b/test_pool/pmu/operating_system/test_pmu006.c index 6fbe725a..e072464a 100644 --- a/test_pool/pmu/operating_system/test_pmu006.c +++ b/test_pool/pmu/operating_system/test_pmu006.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pmu/operating_system/test_pmu007.c b/test_pool/pmu/operating_system/test_pmu007.c index 037a30ae..6d1c288f 100644 --- a/test_pool/pmu/operating_system/test_pmu007.c +++ b/test_pool/pmu/operating_system/test_pmu007.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pmu/operating_system/test_pmu008.c b/test_pool/pmu/operating_system/test_pmu008.c index f657a99b..87679a90 100644 --- a/test_pool/pmu/operating_system/test_pmu008.c +++ b/test_pool/pmu/operating_system/test_pmu008.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022-2023, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/ras/operating_system/test_ras001.c b/test_pool/ras/operating_system/test_ras001.c index 4a08197c..05d2713c 100644 --- a/test_pool/ras/operating_system/test_ras001.c +++ b/test_pool/ras/operating_system/test_ras001.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/ras/operating_system/test_ras002.c b/test_pool/ras/operating_system/test_ras002.c index 2d4da0f9..2e0d3439 100644 --- a/test_pool/ras/operating_system/test_ras002.c +++ b/test_pool/ras/operating_system/test_ras002.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/ras/operating_system/test_ras003.c b/test_pool/ras/operating_system/test_ras003.c index 1b3350f1..2809e5be 100644 --- a/test_pool/ras/operating_system/test_ras003.c +++ b/test_pool/ras/operating_system/test_ras003.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/ras/operating_system/test_ras004.c b/test_pool/ras/operating_system/test_ras004.c index 60e54047..dc56d916 100644 --- a/test_pool/ras/operating_system/test_ras004.c +++ b/test_pool/ras/operating_system/test_ras004.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/ras/operating_system/test_ras005.c b/test_pool/ras/operating_system/test_ras005.c index 7eac4508..7b40c278 100644 --- a/test_pool/ras/operating_system/test_ras005.c +++ b/test_pool/ras/operating_system/test_ras005.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/ras/operating_system/test_ras006.c b/test_pool/ras/operating_system/test_ras006.c index 6d368814..8a1bebb8 100644 --- a/test_pool/ras/operating_system/test_ras006.c +++ b/test_pool/ras/operating_system/test_ras006.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/ras/operating_system/test_ras007.c b/test_pool/ras/operating_system/test_ras007.c index bf635a17..803ca4c3 100644 --- a/test_pool/ras/operating_system/test_ras007.c +++ b/test_pool/ras/operating_system/test_ras007.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/ras/operating_system/test_ras008.c b/test_pool/ras/operating_system/test_ras008.c index 8e388f3b..cd8d90a6 100644 --- a/test_pool/ras/operating_system/test_ras008.c +++ b/test_pool/ras/operating_system/test_ras008.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/ras/operating_system/test_ras009.c b/test_pool/ras/operating_system/test_ras009.c index 6ef435fd..d91df312 100644 --- a/test_pool/ras/operating_system/test_ras009.c +++ b/test_pool/ras/operating_system/test_ras009.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/ras/operating_system/test_ras010.c b/test_pool/ras/operating_system/test_ras010.c index 348fbfb9..a2f2378a 100644 --- a/test_pool/ras/operating_system/test_ras010.c +++ b/test_pool/ras/operating_system/test_ras010.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/ras/operating_system/test_ras011.c b/test_pool/ras/operating_system/test_ras011.c index 882649fe..56f1360b 100644 --- a/test_pool/ras/operating_system/test_ras011.c +++ b/test_pool/ras/operating_system/test_ras011.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/ras/operating_system/test_ras012.c b/test_pool/ras/operating_system/test_ras012.c index 662031ce..f3afeb44 100644 --- a/test_pool/ras/operating_system/test_ras012.c +++ b/test_pool/ras/operating_system/test_ras012.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/smmu/operating_system/test_i003.c b/test_pool/smmu/operating_system/test_i003.c index f2c24a2e..e095740c 100644 --- a/test_pool/smmu/operating_system/test_i003.c +++ b/test_pool/smmu/operating_system/test_i003.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2021-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/smmu/operating_system/test_i004.c b/test_pool/smmu/operating_system/test_i004.c index ecb319a4..fb3d76f7 100644 --- a/test_pool/smmu/operating_system/test_i004.c +++ b/test_pool/smmu/operating_system/test_i004.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2021-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/smmu/operating_system/test_i007.c b/test_pool/smmu/operating_system/test_i007.c index c57b8fe6..d8ea7a5f 100644 --- a/test_pool/smmu/operating_system/test_i007.c +++ b/test_pool/smmu/operating_system/test_i007.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/smmu/operating_system/test_i013.c b/test_pool/smmu/operating_system/test_i013.c index 6a8ca189..47ef1118 100644 --- a/test_pool/smmu/operating_system/test_i013.c +++ b/test_pool/smmu/operating_system/test_i013.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/smmu/operating_system/test_i014.c b/test_pool/smmu/operating_system/test_i014.c index 438ae0df..69242e08 100644 --- a/test_pool/smmu/operating_system/test_i014.c +++ b/test_pool/smmu/operating_system/test_i014.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/smmu/operating_system/test_i016.c b/test_pool/smmu/operating_system/test_i016.c index 84b9ced2..ee7de255 100644 --- a/test_pool/smmu/operating_system/test_i016.c +++ b/test_pool/smmu/operating_system/test_i016.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/test_pool.mk b/test_pool/test_pool.mk index c24882db..df912782 100644 --- a/test_pool/test_pool.mk +++ b/test_pool/test_pool.mk @@ -1,5 +1,5 @@ ## @file - # Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + # Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/val/include/sbsa_avs_mmu.h b/val/include/sbsa_avs_mmu.h index fdb557c6..ae66d45c 100644 --- a/val/include/sbsa_avs_mmu.h +++ b/val/include/sbsa_avs_mmu.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/val/include/sbsa_avs_mpam.h b/val/include/sbsa_avs_mpam.h index 987f2e7a..6cc1ba4b 100644 --- a/val/include/sbsa_avs_mpam.h +++ b/val/include/sbsa_avs_mpam.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/val/include/sbsa_avs_mpam_reg.h b/val/include/sbsa_avs_mpam_reg.h index d91852d3..0a77ae94 100644 --- a/val/include/sbsa_avs_mpam_reg.h +++ b/val/include/sbsa_avs_mpam_reg.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/val/include/sbsa_avs_pmu_reg.h b/val/include/sbsa_avs_pmu_reg.h index ce44c5d8..e74a423b 100644 --- a/val/include/sbsa_avs_pmu_reg.h +++ b/val/include/sbsa_avs_pmu_reg.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/val/include/sbsa_avs_ras.h b/val/include/sbsa_avs_ras.h index 8fbd662c..90e4f87c 100644 --- a/val/include/sbsa_avs_ras.h +++ b/val/include/sbsa_avs_ras.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/val/src/AArch64/MpamSupport.s b/val/src/AArch64/MpamSupport.s index 17b93837..cef982aa 100644 --- a/val/src/AArch64/MpamSupport.s +++ b/val/src/AArch64/MpamSupport.s @@ -1,5 +1,5 @@ #/** @file -# Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/val/src/AArch64/RasSupport.S b/val/src/AArch64/RasSupport.S index 12501d07..d144fa15 100644 --- a/val/src/AArch64/RasSupport.S +++ b/val/src/AArch64/RasSupport.S @@ -1,5 +1,5 @@ #/** @file -# Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/val/src/avs_mmu.c b/val/src/avs_mmu.c index 0d094148..7f4dc87c 100644 --- a/val/src/avs_mmu.c +++ b/val/src/avs_mmu.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/val/src/avs_mpam.c b/val/src/avs_mpam.c index c379697f..67fde07a 100644 --- a/val/src/avs_mpam.c +++ b/val/src/avs_mpam.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/val/src/avs_ras.c b/val/src/avs_ras.c index 8ee36603..78f9f800 100644 --- a/val/src/avs_ras.c +++ b/val/src/avs_ras.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); From 6e0bd1292a45a2cc1598ef9930f57da2a8841f49 Mon Sep 17 00:00:00 2001 From: Rajat Goyal Date: Mon, 16 Jan 2023 15:50:41 +0530 Subject: [PATCH 8/8] SBSA test_pool Copyright changes Signed-off-by: Rajat Goyal --- test_pool/pcie/test_p059.c | 2 +- test_pool/pe/operating_system/test_c001.c | 2 +- test_pool/pe/operating_system/test_c002.c | 2 +- test_pool/pe/operating_system/test_c003.c | 2 +- test_pool/pe/operating_system/test_c005.c | 2 +- test_pool/pe/operating_system/test_c007.c | 2 +- test_pool/pe/operating_system/test_c008.c | 2 +- test_pool/pe/operating_system/test_c009.c | 2 +- test_pool/pe/operating_system/test_c010.c | 2 +- test_pool/pe/operating_system/test_c011.c | 2 +- test_pool/pe/operating_system/test_c012.c | 2 +- test_pool/pe/operating_system/test_c013.c | 2 +- test_pool/pe/operating_system/test_c014.c | 2 +- test_pool/pe/operating_system/test_c017.c | 2 +- test_pool/pe/operating_system/test_c018.c | 2 +- test_pool/pe/operating_system/test_c019.c | 2 +- test_pool/pe/operating_system/test_c020.c | 2 +- test_pool/pe/operating_system/test_c021.c | 2 +- test_pool/pe/operating_system/test_c022.c | 2 +- test_pool/pe/operating_system/test_c023.c | 2 +- test_pool/pe/operating_system/test_c024.c | 2 +- test_pool/pe/operating_system/test_c025.c | 2 +- test_pool/pe/operating_system/test_c026.c | 2 +- test_pool/pe/operating_system/test_c027.c | 2 +- test_pool/pmu/operating_system/test_pmu001.c | 2 +- test_pool/pmu/operating_system/test_pmu002.c | 2 +- test_pool/pmu/operating_system/test_pmu008.c | 2 +- test_pool/smmu/operating_system/test_i001.c | 2 +- test_pool/smmu/operating_system/test_i002.c | 2 +- test_pool/smmu/operating_system/test_i003.c | 2 +- test_pool/smmu/operating_system/test_i004.c | 2 +- test_pool/smmu/operating_system/test_i005.c | 2 +- test_pool/smmu/operating_system/test_i006.c | 2 +- test_pool/smmu/operating_system/test_i008.c | 2 +- test_pool/smmu/operating_system/test_i009.c | 2 +- test_pool/smmu/operating_system/test_i010.c | 2 +- test_pool/smmu/operating_system/test_i011.c | 2 +- test_pool/smmu/operating_system/test_i012.c | 2 +- test_pool/smmu/operating_system/test_i015.c | 2 +- test_pool/watchdog/operating_system/test_w001.c | 2 +- 40 files changed, 40 insertions(+), 40 deletions(-) diff --git a/test_pool/pcie/test_p059.c b/test_pool/pcie/test_p059.c index ffbaf1ff..0957eb05 100644 --- a/test_pool/pcie/test_p059.c +++ b/test_pool/pcie/test_p059.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2021, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2021-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c001.c b/test_pool/pe/operating_system/test_c001.c index 4cd75470..905d48f1 100644 --- a/test_pool/pe/operating_system/test_c001.c +++ b/test_pool/pe/operating_system/test_c001.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2020, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2020-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c002.c b/test_pool/pe/operating_system/test_c002.c index 3f29f05d..dc5b9744 100644 --- a/test_pool/pe/operating_system/test_c002.c +++ b/test_pool/pe/operating_system/test_c002.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2022-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c003.c b/test_pool/pe/operating_system/test_c003.c index 4ab7c56e..68fb753e 100644 --- a/test_pool/pe/operating_system/test_c003.c +++ b/test_pool/pe/operating_system/test_c003.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2022-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c005.c b/test_pool/pe/operating_system/test_c005.c index f0f227d2..a589c2f7 100644 --- a/test_pool/pe/operating_system/test_c005.c +++ b/test_pool/pe/operating_system/test_c005.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2022-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c007.c b/test_pool/pe/operating_system/test_c007.c index 0876ddc2..e18e2ca4 100644 --- a/test_pool/pe/operating_system/test_c007.c +++ b/test_pool/pe/operating_system/test_c007.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2022-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c008.c b/test_pool/pe/operating_system/test_c008.c index 41b8b26b..280420fe 100644 --- a/test_pool/pe/operating_system/test_c008.c +++ b/test_pool/pe/operating_system/test_c008.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2022-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c009.c b/test_pool/pe/operating_system/test_c009.c index 7b98df3d..fdf97bfc 100644 --- a/test_pool/pe/operating_system/test_c009.c +++ b/test_pool/pe/operating_system/test_c009.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2022-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c010.c b/test_pool/pe/operating_system/test_c010.c index 613047b4..c311dea6 100644 --- a/test_pool/pe/operating_system/test_c010.c +++ b/test_pool/pe/operating_system/test_c010.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2020-2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2020-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c011.c b/test_pool/pe/operating_system/test_c011.c index c62175a2..08e009ef 100644 --- a/test_pool/pe/operating_system/test_c011.c +++ b/test_pool/pe/operating_system/test_c011.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2022-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c012.c b/test_pool/pe/operating_system/test_c012.c index c6dfb73b..904d3e9f 100644 --- a/test_pool/pe/operating_system/test_c012.c +++ b/test_pool/pe/operating_system/test_c012.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2022-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c013.c b/test_pool/pe/operating_system/test_c013.c index 002b71e1..c46b4e98 100644 --- a/test_pool/pe/operating_system/test_c013.c +++ b/test_pool/pe/operating_system/test_c013.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2020, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2020-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c014.c b/test_pool/pe/operating_system/test_c014.c index e8b64f8d..327ec78d 100644 --- a/test_pool/pe/operating_system/test_c014.c +++ b/test_pool/pe/operating_system/test_c014.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2022-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c017.c b/test_pool/pe/operating_system/test_c017.c index 42e1c566..7ba16b2a 100644 --- a/test_pool/pe/operating_system/test_c017.c +++ b/test_pool/pe/operating_system/test_c017.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c018.c b/test_pool/pe/operating_system/test_c018.c index c9b352c8..eb0224d6 100644 --- a/test_pool/pe/operating_system/test_c018.c +++ b/test_pool/pe/operating_system/test_c018.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020, 2022-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c019.c b/test_pool/pe/operating_system/test_c019.c index 216176d4..48cebe54 100644 --- a/test_pool/pe/operating_system/test_c019.c +++ b/test_pool/pe/operating_system/test_c019.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020, 2022-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c020.c b/test_pool/pe/operating_system/test_c020.c index bb73b586..617a992f 100644 --- a/test_pool/pe/operating_system/test_c020.c +++ b/test_pool/pe/operating_system/test_c020.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020, 2022-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c021.c b/test_pool/pe/operating_system/test_c021.c index ac7c1e77..3bba49e1 100644 --- a/test_pool/pe/operating_system/test_c021.c +++ b/test_pool/pe/operating_system/test_c021.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2022, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c022.c b/test_pool/pe/operating_system/test_c022.c index 4a6c30e4..2045cf5e 100644 --- a/test_pool/pe/operating_system/test_c022.c +++ b/test_pool/pe/operating_system/test_c022.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020, 2022-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c023.c b/test_pool/pe/operating_system/test_c023.c index 52bc5b6b..c36b34c5 100644 --- a/test_pool/pe/operating_system/test_c023.c +++ b/test_pool/pe/operating_system/test_c023.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020, 2022-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c024.c b/test_pool/pe/operating_system/test_c024.c index ba2204da..122c511d 100644 --- a/test_pool/pe/operating_system/test_c024.c +++ b/test_pool/pe/operating_system/test_c024.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020, 2022-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c025.c b/test_pool/pe/operating_system/test_c025.c index 1bbfdffb..111e8eab 100644 --- a/test_pool/pe/operating_system/test_c025.c +++ b/test_pool/pe/operating_system/test_c025.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020,2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c026.c b/test_pool/pe/operating_system/test_c026.c index ed167c7e..0ee9ddaf 100644 --- a/test_pool/pe/operating_system/test_c026.c +++ b/test_pool/pe/operating_system/test_c026.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020, 2022-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pe/operating_system/test_c027.c b/test_pool/pe/operating_system/test_c027.c index a3d6f2bc..5179c102 100644 --- a/test_pool/pe/operating_system/test_c027.c +++ b/test_pool/pe/operating_system/test_c027.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020, 2022-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pmu/operating_system/test_pmu001.c b/test_pool/pmu/operating_system/test_pmu001.c index 92d7500f..cf475f6e 100644 --- a/test_pool/pmu/operating_system/test_pmu001.c +++ b/test_pool/pmu/operating_system/test_pmu001.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2021-2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2021-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pmu/operating_system/test_pmu002.c b/test_pool/pmu/operating_system/test_pmu002.c index 5e79674d..61dfc9d4 100644 --- a/test_pool/pmu/operating_system/test_pmu002.c +++ b/test_pool/pmu/operating_system/test_pmu002.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2021-2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2021-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/pmu/operating_system/test_pmu008.c b/test_pool/pmu/operating_system/test_pmu008.c index 87679a90..74981198 100644 --- a/test_pool/pmu/operating_system/test_pmu008.c +++ b/test_pool/pmu/operating_system/test_pmu008.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2023-2023, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/smmu/operating_system/test_i001.c b/test_pool/smmu/operating_system/test_i001.c index 76e7e575..107b4576 100644 --- a/test_pool/smmu/operating_system/test_i001.c +++ b/test_pool/smmu/operating_system/test_i001.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/smmu/operating_system/test_i002.c b/test_pool/smmu/operating_system/test_i002.c index e0a51d57..70e5851e 100644 --- a/test_pool/smmu/operating_system/test_i002.c +++ b/test_pool/smmu/operating_system/test_i002.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2020-2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2020-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/smmu/operating_system/test_i003.c b/test_pool/smmu/operating_system/test_i003.c index e095740c..0b752775 100644 --- a/test_pool/smmu/operating_system/test_i003.c +++ b/test_pool/smmu/operating_system/test_i003.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2021-2023 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/smmu/operating_system/test_i004.c b/test_pool/smmu/operating_system/test_i004.c index fb3d76f7..1356c87e 100644 --- a/test_pool/smmu/operating_system/test_i004.c +++ b/test_pool/smmu/operating_system/test_i004.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2021-2023 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/smmu/operating_system/test_i005.c b/test_pool/smmu/operating_system/test_i005.c index a6f60f0f..578df05e 100644 --- a/test_pool/smmu/operating_system/test_i005.c +++ b/test_pool/smmu/operating_system/test_i005.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/smmu/operating_system/test_i006.c b/test_pool/smmu/operating_system/test_i006.c index e2ceeb4c..6acca0a1 100644 --- a/test_pool/smmu/operating_system/test_i006.c +++ b/test_pool/smmu/operating_system/test_i006.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/smmu/operating_system/test_i008.c b/test_pool/smmu/operating_system/test_i008.c index 64c8b2dd..8a04cfd7 100644 --- a/test_pool/smmu/operating_system/test_i008.c +++ b/test_pool/smmu/operating_system/test_i008.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2021-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/smmu/operating_system/test_i009.c b/test_pool/smmu/operating_system/test_i009.c index d7b47156..a0a6f71a 100644 --- a/test_pool/smmu/operating_system/test_i009.c +++ b/test_pool/smmu/operating_system/test_i009.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2021-2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2021-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/smmu/operating_system/test_i010.c b/test_pool/smmu/operating_system/test_i010.c index eb710c40..09d7646a 100644 --- a/test_pool/smmu/operating_system/test_i010.c +++ b/test_pool/smmu/operating_system/test_i010.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2021-2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2021-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/smmu/operating_system/test_i011.c b/test_pool/smmu/operating_system/test_i011.c index cccb3b4b..29b799b6 100644 --- a/test_pool/smmu/operating_system/test_i011.c +++ b/test_pool/smmu/operating_system/test_i011.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2021-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/smmu/operating_system/test_i012.c b/test_pool/smmu/operating_system/test_i012.c index 24d2d9b2..e834d168 100644 --- a/test_pool/smmu/operating_system/test_i012.c +++ b/test_pool/smmu/operating_system/test_i012.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2021-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/smmu/operating_system/test_i015.c b/test_pool/smmu/operating_system/test_i015.c index f3a12290..5de4a18b 100644 --- a/test_pool/smmu/operating_system/test_i015.c +++ b/test_pool/smmu/operating_system/test_i015.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2021 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2021-2023 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/watchdog/operating_system/test_w001.c b/test_pool/watchdog/operating_system/test_w001.c index 08dfaac6..15d9afa6 100644 --- a/test_pool/watchdog/operating_system/test_w001.c +++ b/test_pool/watchdog/operating_system/test_w001.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License");

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