diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/CMakeLists.txt b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/CMakeLists.txt index 759187bf962..84317d67ce5 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/CMakeLists.txt +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/CMakeLists.txt @@ -26,7 +26,6 @@ target_sources(mbed-mimxrt1170-evk device/system_MIMXRT1176_cm7.c drivers/fsl_anatop_ai.c - drivers/fsl_anatop.c drivers/fsl_cache.c drivers/fsl_clock.c drivers/fsl_common.c diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/TARGET_EVK/clock_config.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/TARGET_EVK/clock_config.c index 876a061f868..d8840ed896b 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/TARGET_EVK/clock_config.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/TARGET_EVK/clock_config.c @@ -1,15 +1,36 @@ /* - * Copyright 2018-2019 NXP + * Copyright 2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +/* + * How to setup clock using clock driver functions: + * + * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock. + * + * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock. + * + * 3. Call CLOCK_SetRootClock() to configure corresponding module clock source and divider. + * + */ + +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Clocks v7.0 +processor: MIMXRT1176xxxxx +package_id: MIMXRT1176DVMAA +mcu_data: ksdk2_0 +processor_version: 0.8.1 +board: MIMXRT1170-EVK + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + #include "clock_config.h" #include "fsl_iomuxc.h" #include "fsl_dcdc.h" #include "fsl_pmu.h" - +#include "fsl_clock.h" /******************************************************************************* * Definitions @@ -21,6 +42,29 @@ /* System clock frequency. */ extern uint32_t SystemCoreClock; +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +/* This function should not run from SDRAM since it will change SEMC configuration. */ +AT_QUICKACCESS_SECTION_CODE(void UpdateSemcClock(void)); +void UpdateSemcClock(void) +{ + /* Enable self-refresh mode and update semc clock root to 200MHz. */ + SEMC->IPCMD = 0xA55A000D; + while ((SEMC->INTR & 0x3) == 0) + ; + SEMC->INTR = 0x3; + SEMC->DCCR = 0x0B; + /* + * Currently we are using SEMC parameter which fit both 166MHz and 200MHz, only + * need to change the SEMC clock root here. If customer is using their own DCD and + * want to switch from 166MHz to 200MHz, extra SEMC configuration might need to be + * adjusted here to fine tune the SDRAM performance + */ + CCM->CLOCK_ROOT[kCLOCK_Root_Semc].CONTROL = 0x602; +} +#endif +#endif + /******************************************************************************* ************************ BOARD_InitBootClocks function ************************ ******************************************************************************/ @@ -32,6 +76,172 @@ void BOARD_InitBootClocks(void) /******************************************************************************* ********************** Configuration BOARD_BootClockRUN *********************** ******************************************************************************/ +/* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!Configuration +name: BOARD_BootClockRUN +called_from_default_init: true +outputs: +- {id: ACMP_CLK_ROOT.outFreq, value: 24 MHz} +- {id: ADC1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: ADC2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: ARM_PLL_CLK.outFreq, value: 996 MHz} +- {id: ASRC_CLK_ROOT.outFreq, value: 24 MHz} +- {id: AXI_CLK_ROOT.outFreq, value: 996 MHz} +- {id: BUS_CLK_ROOT.outFreq, value: 240 MHz} +- {id: BUS_LPSR_CLK_ROOT.outFreq, value: 160 MHz} +- {id: CAN1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: CAN2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: CAN3_CLK_ROOT.outFreq, value: 24 MHz} +- {id: CCM_CLKO1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: CCM_CLKO2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: CLK_1M.outFreq, value: 1 MHz} +- {id: CSI2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: CSI2_ESC_CLK_ROOT.outFreq, value: 24 MHz} +- {id: CSI2_UI_CLK_ROOT.outFreq, value: 24 MHz} +- {id: CSI_CLK_ROOT.outFreq, value: 24 MHz} +- {id: CSSYS_CLK_ROOT.outFreq, value: 24 MHz} +- {id: CSTRACE_CLK_ROOT.outFreq, value: 24 MHz} +- {id: ELCDIF_CLK_ROOT.outFreq, value: 24 MHz} +- {id: EMV1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: EMV2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: ENET1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: ENET2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: ENET_1G_TX_CLK.outFreq, value: 24 MHz} +- {id: ENET_25M_CLK_ROOT.outFreq, value: 24 MHz} +- {id: ENET_QOS_CLK_ROOT.outFreq, value: 24 MHz} +- {id: ENET_TIMER1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: ENET_TIMER2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: ENET_TIMER3_CLK_ROOT.outFreq, value: 24 MHz} +- {id: ENET_TX_CLK.outFreq, value: 24 MHz} +- {id: FLEXIO1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: FLEXIO2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: FLEXSPI1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: GC355_CLK_ROOT.outFreq, value: 492.0000125 MHz} +- {id: GPT1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: GPT1_ipg_clk_highfreq.outFreq, value: 24 MHz} +- {id: GPT2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: GPT2_ipg_clk_highfreq.outFreq, value: 24 MHz} +- {id: GPT3_CLK_ROOT.outFreq, value: 24 MHz} +- {id: GPT3_ipg_clk_highfreq.outFreq, value: 24 MHz} +- {id: GPT4_CLK_ROOT.outFreq, value: 24 MHz} +- {id: GPT4_ipg_clk_highfreq.outFreq, value: 24 MHz} +- {id: GPT5_CLK_ROOT.outFreq, value: 24 MHz} +- {id: GPT5_ipg_clk_highfreq.outFreq, value: 24 MHz} +- {id: GPT6_CLK_ROOT.outFreq, value: 24 MHz} +- {id: GPT6_ipg_clk_highfreq.outFreq, value: 24 MHz} +- {id: LCDIFV2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPI2C1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPI2C2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPI2C3_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPI2C4_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPI2C5_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPI2C6_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPSPI1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPSPI2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPSPI3_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPSPI4_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPSPI5_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPSPI6_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART10_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART11_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART12_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART3_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART4_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART5_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART6_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART7_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART8_CLK_ROOT.outFreq, value: 24 MHz} +- {id: LPUART9_CLK_ROOT.outFreq, value: 24 MHz} +- {id: M4_CLK_ROOT.outFreq, value: 4320/11 MHz} +- {id: M4_SYSTICK_CLK_ROOT.outFreq, value: 24 MHz} +- {id: M7_CLK_ROOT.outFreq, value: 996 MHz} +- {id: M7_SYSTICK_CLK_ROOT.outFreq, value: 100 kHz} +- {id: MIC_CLK_ROOT.outFreq, value: 24 MHz} +- {id: MIPI_DSI_TX_CLK_ESC_ROOT.outFreq, value: 24 MHz} +- {id: MIPI_ESC_CLK_ROOT.outFreq, value: 24 MHz} +- {id: MIPI_REF_CLK_ROOT.outFreq, value: 24 MHz} +- {id: MQS_CLK_ROOT.outFreq, value: 24 MHz} +- {id: MQS_MCLK.outFreq, value: 24 MHz} +- {id: OSC_24M.outFreq, value: 24 MHz} +- {id: OSC_32K.outFreq, value: 32.768 kHz} +- {id: OSC_RC_16M.outFreq, value: 16 MHz} +- {id: OSC_RC_400M.outFreq, value: 400 MHz} +- {id: OSC_RC_48M.outFreq, value: 48 MHz} +- {id: OSC_RC_48M_DIV2.outFreq, value: 24 MHz} +- {id: PLL_VIDEO_CLK.outFreq, value: 984.000025 MHz} +- {id: SAI1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: SAI1_MCLK1.outFreq, value: 24 MHz} +- {id: SAI1_MCLK3.outFreq, value: 24 MHz} +- {id: SAI2_CLK_ROOT.outFreq, value: 24 MHz} +- {id: SAI2_MCLK1.outFreq, value: 24 MHz} +- {id: SAI2_MCLK3.outFreq, value: 24 MHz} +- {id: SAI3_CLK_ROOT.outFreq, value: 24 MHz} +- {id: SAI3_MCLK1.outFreq, value: 24 MHz} +- {id: SAI3_MCLK3.outFreq, value: 24 MHz} +- {id: SAI4_CLK_ROOT.outFreq, value: 24 MHz} +- {id: SAI4_MCLK1.outFreq, value: 24 MHz} +- {id: SEMC_CLK_ROOT.outFreq, value: 198 MHz} +- {id: SPDIF_CLK_ROOT.outFreq, value: 24 MHz} +- {id: SYS_PLL2_CLK.outFreq, value: 528 MHz} +- {id: SYS_PLL2_PFD0_CLK.outFreq, value: 352 MHz} +- {id: SYS_PLL2_PFD1_CLK.outFreq, value: 594 MHz} +- {id: SYS_PLL2_PFD2_CLK.outFreq, value: 396 MHz} +- {id: SYS_PLL2_PFD3_CLK.outFreq, value: 297 MHz} +- {id: SYS_PLL3_CLK.outFreq, value: 480 MHz} +- {id: SYS_PLL3_DIV2_CLK.outFreq, value: 240 MHz} +- {id: SYS_PLL3_PFD0_CLK.outFreq, value: 8640/13 MHz} +- {id: SYS_PLL3_PFD1_CLK.outFreq, value: 8640/17 MHz} +- {id: SYS_PLL3_PFD2_CLK.outFreq, value: 270 MHz} +- {id: SYS_PLL3_PFD3_CLK.outFreq, value: 4320/11 MHz} +- {id: USDHC1_CLK_ROOT.outFreq, value: 24 MHz} +- {id: USDHC2_CLK_ROOT.outFreq, value: 24 MHz} +settings: +- {id: CoreBusClockRootsInitializationConfig, value: selectedCore} +- {id: SOCDomainVoltage, value: OD} +- {id: ANADIG_OSC_OSC_24M_CTRL_LP_EN_CFG, value: Low} +- {id: ANADIG_OSC_OSC_24M_CTRL_OSC_EN_CFG, value: Enabled} +- {id: ANADIG_PLL.PLL_AUDIO_BYPASS.sel, value: ANADIG_OSC.OSC_24M} +- {id: ANADIG_PLL.PLL_VIDEO.denom, value: '960000'} +- {id: ANADIG_PLL.PLL_VIDEO.div, value: '41'} +- {id: ANADIG_PLL.PLL_VIDEO.num, value: '1'} +- {id: ANADIG_PLL.SYS_PLL1_BYPASS.sel, value: ANADIG_OSC.OSC_24M} +- {id: ANADIG_PLL.SYS_PLL2.denom, value: '268435455'} +- {id: ANADIG_PLL.SYS_PLL2.div, value: '22'} +- {id: ANADIG_PLL.SYS_PLL2.num, value: '0'} +- {id: ANADIG_PLL.SYS_PLL2_SS_DIV.scale, value: '268435455'} +- {id: ANADIG_PLL.SYS_PLL3_PFD3_DIV.scale, value: '22', locked: true} +- {id: ANADIG_PLL.SYS_PLL3_PFD3_MUL.scale, value: '18', locked: true} +- {id: ANADIG_PLL_ARM_PLL_CTRL_POWERUP_CFG, value: Enabled} +- {id: ANADIG_PLL_PLL_AUDIO_CTRL_GATE_CFG, value: Disabled} +- {id: ANADIG_PLL_PLL_VIDEO_CTRL0_POWERUP_CFG, value: Enabled} +- {id: ANADIG_PLL_SYS_PLL1_CTRL0_POWERUP_CFG, value: Disabled} +- {id: ANADIG_PLL_SYS_PLL1_CTRL_GATE_CFG, value: Disabled} +- {id: ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_CFG, value: Enabled} +- {id: ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG, value: Enabled} +- {id: ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CFG, value: Enabled} +- {id: CCM.CLOCK_ROOT0.MUX.sel, value: ANADIG_PLL.ARM_PLL_CLK} +- {id: CCM.CLOCK_ROOT1.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD3_CLK} +- {id: CCM.CLOCK_ROOT2.DIV.scale, value: '2'} +- {id: CCM.CLOCK_ROOT2.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT25.DIV.scale, value: '22'} +- {id: CCM.CLOCK_ROOT25.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK} +- {id: CCM.CLOCK_ROOT26.DIV.scale, value: '22'} +- {id: CCM.CLOCK_ROOT26.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK} +- {id: CCM.CLOCK_ROOT3.DIV.scale, value: '3'} +- {id: CCM.CLOCK_ROOT3.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK} +- {id: CCM.CLOCK_ROOT4.DIV.scale, value: '3'} +- {id: CCM.CLOCK_ROOT4.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD1_CLK} +- {id: CCM.CLOCK_ROOT68.DIV.scale, value: '2'} +- {id: CCM.CLOCK_ROOT68.MUX.sel, value: ANADIG_PLL.PLL_VIDEO_CLK} +- {id: CCM.CLOCK_ROOT8.DIV.scale, value: '240'} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ + +/******************************************************************************* + * Variables for BOARD_BootClockRUN configuration + ******************************************************************************/ #ifndef SKIP_POWER_ADJUSTMENT #if __CORTEX_M == 7 @@ -43,6 +253,29 @@ void BOARD_InitBootClocks(void) #endif #endif +const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = + { + .postDivider = kCLOCK_PllPostDiv2, /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */ + .loopDivider = 166, /* PLL Loop divider, Fout = Fin * 41.5 */ + }; + +const clock_sys_pll2_config_t sysPll2Config_BOARD_BootClockRUN = + { + .mfd = 268435455, /* Denominator of spread spectrum */ + .ss = NULL, /* Spread spectrum parameter */ + .ssEnable = false, /* Enable spread spectrum or not */ + }; + +const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN = + { + .loopDivider = 41, /* PLL Loop divider, valid range for DIV_SELECT divider value: 27 ~ 54. */ + .postDivider = 0, /* Divider after PLL, should only be 1, 2, 4, 8, 16, 32 */ + .numerator = 1, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .denominator = 960000, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */ + .ss = NULL, /* Spread spectrum parameter */ + .ssEnable = false, /* Enable spread spectrum or not */ + }; + /******************************************************************************* * Code for BOARD_BootClockRUN configuration ******************************************************************************/ @@ -55,14 +288,19 @@ void BOARD_BootClockRUN(void) #endif #if !defined(SKIP_FBB_ENABLE) || (!SKIP_FBB_ENABLE) - pmu_static_body_bias_config_t config; - - PMU_StaticGetCm7FBBDefaultConfig(&config); - PMU_StaticCm7FBBInit(ANADIG_PMU, &config); + /* Check if FBB need to be enabled in OverDrive(OD) mode */ + if(((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1) + { + PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, true); + } + else + { + PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, false); + } #endif #if defined(BYPASS_LDO_LPSR) && BYPASS_LDO_LPSR - PMU_StaticSetLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS, kPMU_LpsrAnaLdoBypassMode1); + PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS, true); PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS, true); #endif @@ -84,123 +322,541 @@ void BOARD_BootClockRUN(void) } #endif - /* SYS PLL2 528MHz. */ - const clock_sys_pll_config_t sysPllConfig = { - .loopDivider = 1, - /* Using 24Mhz OSC */ - .mfn = 0, - .mfi = 22, - }; + /* PLL LDO shall be enabled first before enable PLLs */ - const clock_sys_pll3_config_t sysPll3Config = { - .divSelect = 3, - }; + /* Config CLK_1M */ + CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz); - /* PLL LDO shall be enabled first before enable PLLs */ - CLOCK_EnableOsc24M(); + /* Init OSC RC 16M */ + ANADIG_OSC->OSC_16M_CTRL |= ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK; -#if __CORTEX_M == 7 + /* Init OSC RC 400M */ + CLOCK_OSC_EnableOscRc400M(); + CLOCK_OSC_GateOscRc400M(true); + + /* Init OSC RC 48M */ + CLOCK_OSC_EnableOsc48M(true); + CLOCK_OSC_EnableOsc48MDiv2(true); + + /* Config OSC 24M */ + ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(0) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0); + /* Wait for 24M OSC to be stable. */ + while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK != + (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)) + { + } + + /* Swicth both core, M7 Systick and Bus_Lpsr to OscRC48MDiv2 first */ rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2; rootCfg.div = 1; +#if __CORTEX_M == 7 CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg); - -#if defined(CONSUMER_SERIES) - CLOCK_InitArmPllWithFreq(1000); -#elif defined(AUTOMOTIVE_SERIES) || defined(INDUSTRIAL_SERIES) - CLOCK_InitArmPllWithFreq(800); #endif - /* Configure M7 */ +#if __CORTEX_M == 4 + CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg); + CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg); +#endif + + /* + * if DCD is used, please make sure the clock source of SEMC is not changed in the following PLL/PFD configuration code. + */ + /* Init Arm Pll. */ + CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN); + + /* Bypass Sys Pll1. */ + CLOCK_SetPllBypass(kCLOCK_PllSys1, true); + + /* DeInit Sys Pll1. */ + CLOCK_DeinitSysPll1(); + + /* Init Sys Pll2. */ + CLOCK_InitSysPll2(&sysPll2Config_BOARD_BootClockRUN); + + /* Init System Pll2 pfd0. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27); + + /* Init System Pll2 pfd1. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16); + + /* Init System Pll2 pfd2. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24); + + /* Init System Pll2 pfd3. */ + CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32); + + /* Init Sys Pll3. */ + CLOCK_InitSysPll3(); + + /* Init System Pll3 pfd0. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 13); + + /* Init System Pll3 pfd1. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 17); + + /* Init System Pll3 pfd2. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 32); + + /* Init System Pll3 pfd3. */ + CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 22); + + /* Bypass Audio Pll. */ + CLOCK_SetPllBypass(kCLOCK_PllAudio, true); + + /* DeInit Audio Pll. */ + CLOCK_DeinitAudioPll(); + + /* Init Video Pll. */ + CLOCK_InitVideoPll(&videoPllConfig_BOARD_BootClockRUN); + + /* Moduel clock root configurations. */ + /* Configure M7 using ARM_PLL_CLK */ +#if __CORTEX_M == 7 rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); - - /* Configure M7 Systick running at 10K */ - rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 240; - CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg); #endif - CLOCK_InitSysPll2(&sysPllConfig); - CLOCK_InitSysPll3(&sysPll3Config); + /* Configure M4 using SYS_PLL3_PFD3_CLK */ #if __CORTEX_M == 4 - rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2; - rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg); - CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg); - - CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 22); - /* Configure M4 using SysPll3Pfd3 divided by 1 */ rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg); +#endif + + /* Configure BUS using SYS_PLL3_CLK */ +#if __CORTEX_M == 7 + rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg); +#endif - /* SysPll3 divide by 3 */ + /* Configure BUS_LPSR using SYS_PLL3_CLK */ +#if __CORTEX_M == 4 rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out; rootCfg.div = 3; CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg); #endif -#if DEBUG_CONSOLE_UART_INDEX == 1 - /* Configure Lpuart1 using SysPll2*/ - rootCfg.mux = kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out; - rootCfg.div = 22; - CLOCK_SetRootClock(kCLOCK_Root_Lpuart1, &rootCfg); -#else - /* Configure Lpuart2 using SysPll2*/ - rootCfg.mux = kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out; - rootCfg.div = 22; - CLOCK_SetRootClock(kCLOCK_Root_Lpuart2, &rootCfg); -#endif - + /* Configure SEMC using SYS_PLL2_PFD1_CLK */ #ifndef SKIP_SEMC_INIT - CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16); - /* Configure Semc using SysPll2Pfd1 divided by 3 */ rootCfg.mux = kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd1; rootCfg.div = 3; CLOCK_SetRootClock(kCLOCK_Root_Semc, &rootCfg); #endif - /* Configure Bus using SysPll3 divided by 2 */ - rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll3Out; - rootCfg.div = 2; - CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg); +#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) + UpdateSemcClock(); +#endif +#endif - /* Configure Lpi2c1 using Osc48MDiv2 */ - rootCfg.mux = kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2; + /* Configure CSSYS using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2; rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lpi2c1, &rootCfg); + CLOCK_SetRootClock(kCLOCK_Root_Cssys, &rootCfg); - /* Configure Lpi2c5 using Osc48MDiv2 */ - rootCfg.mux = kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2; + /* Configure CSTRACE using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CSTRACE_ClockRoot_MuxOscRc48MDiv2; rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Lpi2c5, &rootCfg); + CLOCK_SetRootClock(kCLOCK_Root_Cstrace, &rootCfg); + + /* Configure M4_SYSTICK using OSC_RC_48M_DIV2 */ +#if __CORTEX_M == 4 + rootCfg.mux = kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_M4_Systick, &rootCfg); +#endif + + /* Configure M7_SYSTICK using OSC_RC_48M_DIV2 */ +#if __CORTEX_M == 7 + rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 240; + CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg); +#endif + + /* Configure ADC1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg); - /* Configure gpt timer using Osc48MDiv2 */ + /* Configure ADC2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ADC2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Adc2, &rootCfg); + + /* Configure ACMP using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg); + + /* Configure FLEXIO1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_FLEXIO1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Flexio1, &rootCfg); + + /* Configure FLEXIO2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_FLEXIO2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Flexio2, &rootCfg); + + /* Configure GPT1 using OSC_RC_48M_DIV2 */ rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg); - /* Configure gpt timer using Osc48MDiv2 */ + /* Configure GPT2 using OSC_RC_48M_DIV2 */ rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxOscRc48MDiv2; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg); - /* Configure lpspi using Osc48MDiv2 */ + /* Configure GPT3 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_GPT3_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Gpt3, &rootCfg); + + /* Configure GPT4 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_GPT4_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Gpt4, &rootCfg); + + /* Configure GPT5 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_GPT5_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Gpt5, &rootCfg); + + /* Configure GPT6 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_GPT6_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Gpt6, &rootCfg); + + /* Configure FLEXSPI1 using OSC_RC_48M_DIV2 */ +#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)) + rootCfg.mux = kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Flexspi1, &rootCfg); +#endif + + /* Configure FLEXSPI2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Flexspi2, &rootCfg); + + /* Configure CAN1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg); + + /* Configure CAN2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CAN2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Can2, &rootCfg); + + /* Configure CAN3 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg); + + /* Configure LPUART1 using SYS_PLL2_CLK */ + rootCfg.mux = kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out; + rootCfg.div = 22; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart1, &rootCfg); + + /* Configure LPUART2 using SYS_PLL2_CLK */ + rootCfg.mux = kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out; + rootCfg.div = 22; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart2, &rootCfg); + + /* Configure LPUART3 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPUART3_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart3, &rootCfg); + + /* Configure LPUART4 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPUART4_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart4, &rootCfg); + + /* Configure LPUART5 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPUART5_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart5, &rootCfg); + + /* Configure LPUART6 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPUART6_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart6, &rootCfg); + + /* Configure LPUART7 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPUART7_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart7, &rootCfg); + + /* Configure LPUART8 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPUART8_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart8, &rootCfg); + + /* Configure LPUART9 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPUART9_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart9, &rootCfg); + + /* Configure LPUART10 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPUART10_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart10, &rootCfg); + + /* Configure LPUART11 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPUART11_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart11, &rootCfg); + + /* Configure LPUART12 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPUART12_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpuart12, &rootCfg); + + /* Configure LPI2C1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c1, &rootCfg); + + /* Configure LPI2C2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPI2C2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c2, &rootCfg); + + /* Configure LPI2C3 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPI2C3_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c3, &rootCfg); + + /* Configure LPI2C4 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPI2C4_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c4, &rootCfg); + + /* Configure LPI2C5 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c5, &rootCfg); + + /* Configure LPI2C6 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPI2C6_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpi2c6, &rootCfg); + + /* Configure LPSPI1 using OSC_RC_48M_DIV2 */ rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Lpspi1, &rootCfg); - /* Configure flexio using Osc48MDiv2 */ - rootCfg.mux = kCLOCK_FLEXIO2_ClockRoot_MuxOscRc48MDiv2; + /* Configure LPSPI2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPSPI2_ClockRoot_MuxOscRc48MDiv2; rootCfg.div = 1; - CLOCK_SetRootClock(kCLOCK_Root_Flexio2, &rootCfg); + CLOCK_SetRootClock(kCLOCK_Root_Lpspi2, &rootCfg); + + /* Configure LPSPI3 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPSPI3_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi3, &rootCfg); + + /* Configure LPSPI4 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPSPI4_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi4, &rootCfg); + + /* Configure LPSPI5 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPSPI5_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi5, &rootCfg); + + /* Configure LPSPI6 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LPSPI6_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lpspi6, &rootCfg); - /* Configure emvsim using Osc48MDiv2 */ + /* Configure EMV1 using OSC_RC_48M_DIV2 */ rootCfg.mux = kCLOCK_EMV1_ClockRoot_MuxOscRc48MDiv2; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Emv1, &rootCfg); + /* Configure EMV2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_EMV2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Emv2, &rootCfg); + + /* Configure ENET1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg); + + /* Configure ENET2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ENET2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Enet2, &rootCfg); + + /* Configure ENET_QOS using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ENET_QOS_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Enet_Qos, &rootCfg); + + /* Configure ENET_25M using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ENET_25M_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Enet_25m, &rootCfg); + + /* Configure ENET_TIMER1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer1, &rootCfg); + + /* Configure ENET_TIMER2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer2, &rootCfg); + + /* Configure ENET_TIMER3 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer3, &rootCfg); + + /* Configure USDHC1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg); + + /* Configure USDHC2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg); + + /* Configure ASRC using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_ASRC_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Asrc, &rootCfg); + + /* Configure MQS using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_MQS_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Mqs, &rootCfg); + + /* Configure MIC using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_MIC_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Mic, &rootCfg); + + /* Configure SPDIF using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_SPDIF_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Spdif, &rootCfg); + + /* Configure SAI1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_SAI1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Sai1, &rootCfg); + + /* Configure SAI2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_SAI2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Sai2, &rootCfg); + + /* Configure SAI3 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_SAI3_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Sai3, &rootCfg); + + /* Configure SAI4 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_SAI4_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Sai4, &rootCfg); + + /* Configure GC355 using PLL_VIDEO_CLK */ + rootCfg.mux = kCLOCK_GC355_ClockRoot_MuxVideoPllOut; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_Gc355, &rootCfg); + + /* Configure LCDIF using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LCDIF_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lcdif, &rootCfg); + + /* Configure LCDIFV2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_LCDIFV2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Lcdifv2, &rootCfg); + + /* Configure MIPI_REF using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_MIPI_REF_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Mipi_Ref, &rootCfg); + + /* Configure MIPI_ESC using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Mipi_Esc, &rootCfg); + + /* Configure CSI2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CSI2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Csi2, &rootCfg); + + /* Configure CSI2_ESC using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Csi2_Esc, &rootCfg); + + /* Configure CSI2_UI using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CSI2_UI_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Csi2_Ui, &rootCfg); + + /* Configure CSI using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CSI_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Csi, &rootCfg); + + /* Configure CKO1 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CKO1_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Cko1, &rootCfg); + + /* Configure CKO2 using OSC_RC_48M_DIV2 */ + rootCfg.mux = kCLOCK_CKO2_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; + CLOCK_SetRootClock(kCLOCK_Root_Cko2, &rootCfg); + + /* Set SAI1 MCLK1 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0); + /* Set SAI1 MCLK2 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 3); + /* Set SAI1 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0); + /* Set SAI2 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0); + /* Set SAI3 MCLK3 clock source. */ + IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0); + + /* Set MQS configuration. */ + IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0); + /* Set ENET Tx clock source. */ + IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_MASK; + /* Set ENET_1G Tx clock source. */ + IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK; + /* Set GPT1 High frequency reference clock source. */ + IOMUXC_GPR->GPR22 &= ~IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK; + /* Set GPT2 High frequency reference clock source. */ + IOMUXC_GPR->GPR23 &= ~IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK; + /* Set GPT3 High frequency reference clock source. */ + IOMUXC_GPR->GPR24 &= ~IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK; + /* Set GPT4 High frequency reference clock source. */ + IOMUXC_GPR->GPR25 &= ~IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK; + /* Set GPT5 High frequency reference clock source. */ + IOMUXC_GPR->GPR26 &= ~IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK; + /* Set GPT6 High frequency reference clock source. */ + IOMUXC_GPR->GPR27 &= ~IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK; + #if __CORTEX_M == 7 SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M7); #else diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/TARGET_EVK/clock_config.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/TARGET_EVK/clock_config.h index d6093b8ba65..f4bc24daa1d 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/TARGET_EVK/clock_config.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/TARGET_EVK/clock_config.h @@ -1,5 +1,5 @@ /* - * Copyright 2018-2019 NXP + * Copyright 2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -13,29 +13,11 @@ /******************************************************************************* * Definitions ******************************************************************************/ -#if (defined(CPU_MIMXRT1171AVM8A) || \ - defined(CPU_MIMXRT1172AVM8A) || \ - defined(CPU_MIMXRT1175AVM8A_cm7) || defined(CPU_MIMXRT1175AVM8A_cm4) || \ - defined(CPU_MIMXRT1176AVM8A_cm7) || defined(CPU_MIMXRT1176AVM8A_cm4)) -#define AUTOMOTIVE_SERIES -#elif (defined(CPU_MIMXRT1171CVM8A) || \ - defined(CPU_MIMXRT1172CVM8A) || \ - defined(CPU_MIMXRT1173CVM8A_cm7) || defined(CPU_MIMXRT1173CVM8A_cm4) || \ - defined(CPU_MIMXRT1175CVM8A_cm7) || defined(CPU_MIMXRT1175CVM8A_cm4) || \ - defined(CPU_MIMXRT1176CVM8A_cm7) || defined(CPU_MIMXRT1176CVM8A_cm4)) -#define INDUSTRIAL_SERIES -#elif (defined(CPU_MIMXRT1171DVMAA) || \ - defined(CPU_MIMXRT1172DVMAA) || \ - defined(CPU_MIMXRT1175DVMAA_cm7) || defined(CPU_MIMXRT1175DVMAA_cm4) || \ - defined(CPU_MIMXRT1176DVMAA_cm7) || defined(CPU_MIMXRT1176DVMAA_cm4)) -#define CONSUMER_SERIES -#else -#error "No valid CPU defined!" -#endif #define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */ -#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ +#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */ + /******************************************************************************* ************************ BOARD_InitBootClocks function ************************ ******************************************************************************/ @@ -60,57 +42,148 @@ void BOARD_InitBootClocks(void); /******************************************************************************* * Definitions for BOARD_BootClockRUN configuration ******************************************************************************/ -#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ +#if __CORTEX_M == 7 + #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 996000000UL /*!< CM7 Core clock frequency: 996000000Hz */ +#else + #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 392727272UL /*!< CM4 Core clock frequency: 392727272Hz */ +#endif /* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL -#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL -#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL -#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL -#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL -#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL -#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL -#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL -#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL -#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL -#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 9642857UL -#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL -#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL -#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL -#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL -#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL -#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL -#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL +#define BOARD_BOOTCLOCKRUN_ACMP_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ADC1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ADC2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 996000000UL +#define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_AXI_CLK_ROOT 996000000UL +#define BOARD_BOOTCLOCKRUN_BUS_CLK_ROOT 240000000UL +#define BOARD_BOOTCLOCKRUN_BUS_LPSR_CLK_ROOT 160000000UL +#define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_CAN3_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_CCM_CLKO1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_CCM_CLKO2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL +#define BOARD_BOOTCLOCKRUN_CSI2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_CSI2_ESC_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_CSI2_UI_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_CSSYS_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_CSTRACE_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ELCDIF_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_EMV1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_EMV2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET_1G_TX_CLK 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET_25M_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET_QOS_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET_TIMER1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET_TIMER2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET_TIMER3_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 24000000UL +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_GC355_CLK_ROOT 492000012UL +#define BOARD_BOOTCLOCKRUN_GPT1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT3_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT3_IPG_CLK_HIGHFREQ 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT4_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT4_IPG_CLK_HIGHFREQ 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT5_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT5_IPG_CLK_HIGHFREQ 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT6_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_GPT6_IPG_CLK_HIGHFREQ 24000000UL +#define BOARD_BOOTCLOCKRUN_LCDIFV2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPI2C1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPI2C2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPI2C3_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPI2C4_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPI2C5_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPI2C6_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPSPI1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPSPI2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPSPI3_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPSPI4_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPSPI5_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPSPI6_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPUART10_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPUART11_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPUART12_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPUART1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPUART2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPUART3_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPUART4_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPUART5_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPUART6_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPUART7_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPUART8_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_LPUART9_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_M4_CLK_ROOT 392727272UL +#define BOARD_BOOTCLOCKRUN_M4_SYSTICK_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT 996000000UL +#define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT 100000UL +#define BOARD_BOOTCLOCKRUN_MIC_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_MIPI_DSI_TX_CLK_ESC_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_MIPI_ESC_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_MIPI_REF_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_MQS_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 24000000UL +#define BOARD_BOOTCLOCKRUN_OSC_24M 24000000UL +#define BOARD_BOOTCLOCKRUN_OSC_32K 32768UL +#define BOARD_BOOTCLOCKRUN_OSC_RC_16M 16000000UL +#define BOARD_BOOTCLOCKRUN_OSC_RC_400M 400000000UL +#define BOARD_BOOTCLOCKRUN_OSC_RC_48M 48000000UL +#define BOARD_BOOTCLOCKRUN_OSC_RC_48M_DIV2 24000000UL +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_CLK 0UL +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_MODULATION 0UL +#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_RANGE 0UL +#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_CLK 984000025UL +#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_MODULATION 0UL +#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_RANGE 0UL +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI4_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK1 24000000UL +#define BOARD_BOOTCLOCKRUN_SAI4_MCLK2 0UL +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 198000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_SPDIF_EXTCLK_OUT 0UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_CLK 0UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV2_CLK 0UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV5_CLK 0UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_MODULATION 0UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_RANGE 0UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_CLK 528000000UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD0_CLK 352000000UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD1_CLK 594000000UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD2_CLK 396000000UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD3_CLK 297000000UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_MODULATION 0UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_RANGE 0UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_CLK 480000000UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_DIV2_CLK 240000000UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD0_CLK 664615384UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD1_CLK 508235294UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD2_CLK 270000000UL +#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD3_CLK 392727272UL +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 24000000UL +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 24000000UL + /******************************************************************************* * API for BOARD_BootClockRUN configuration @@ -129,4 +202,5 @@ void BOARD_BootClockRUN(void); } #endif /* __cplusplus*/ -#endif /* _FSL_CLOCK_CONFIG_H_ */ +#endif /* _CLOCK_CONFIG_H_ */ + diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/MIMXRT1176_cm7.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/MIMXRT1176_cm7.h index 51500aebbb5..36b24fe9898 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/MIMXRT1176_cm7.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/MIMXRT1176_cm7.h @@ -10,15 +10,15 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: IMXRT1170RM, Rev E, 12/2019 -** Version: rev. 0.1, 2018-03-05 -** Build: b200828 +** Reference manual: IMXRT1170RM, Rev 0, 12/2020 +** Version: rev. 1.0, 2020-12-29 +** Build: b210118 ** ** Abstract: ** CMSIS Peripheral Access Layer for MIMXRT1176_cm7 ** ** Copyright 1997-2016 Freescale Semiconductor, Inc. -** Copyright 2016-2020 NXP +** Copyright 2016-2021 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -29,14 +29,16 @@ ** Revisions: ** - rev. 0.1 (2018-03-05) ** Initial version. +** - rev. 1.0 (2020-12-29) +** Update header files to align with IMXRT1170RM Rev.0. ** ** ################################################################### */ /*! * @file MIMXRT1176_cm7.h - * @version 0.1 - * @date 2018-03-05 + * @version 1.0 + * @date 2020-12-29 * @brief CMSIS Peripheral Access Layer for MIMXRT1176_cm7 * * CMSIS Peripheral Access Layer for MIMXRT1176_cm7 @@ -47,9 +49,9 @@ /** Memory map major version (memory maps with equal major version number are * compatible) */ -#define MCU_MEM_MAP_VERSION 0x0000U +#define MCU_MEM_MAP_VERSION 0x0100U /** Memory map minor version */ -#define MCU_MEM_MAP_VERSION_MINOR 0x0001U +#define MCU_MEM_MAP_VERSION_MINOR 0x0000U /* ---------------------------------------------------------------------------- -- @@ -214,8 +216,8 @@ typedef enum IRQn { DMA14_DMA30_IRQn = 14, /**< DMA channel 14/30 transfer complete */ DMA15_DMA31_IRQn = 15, /**< DMA channel 15/31 transfer complete */ DMA_ERROR_IRQn = 16, /**< DMA error interrupt channels 0-15 / 16-31 */ - CTI0_ERROR_IRQn = 17, /**< CTI0_Error */ - CTI1_ERROR_IRQn = 18, /**< CTI1_Error */ + CTI_TRIGGER_OUT0_IRQn = 17, /**< CTI_TRIGGER_OUT0 */ + CTI_TRIGGER_OUT1_IRQn = 18, /**< CTI_TRIGGER_OUT1 */ CORE_IRQn = 19, /**< CorePlatform exception IRQ */ LPUART1_IRQn = 20, /**< LPUART1 TX interrupt and RX interrupt */ LPUART2_IRQn = 21, /**< LPUART2 TX interrupt and RX interrupt */ @@ -251,8 +253,8 @@ typedef enum IRQn { KPP_IRQn = 51, /**< Keypad nterrupt */ Reserved68_IRQn = 52, /**< Reserved interrupt */ GPR_IRQ_IRQn = 53, /**< GPR interrupt */ - LCDIF1_IRQn = 54, /**< LCDIF1 interrupt */ - LCDIF2_IRQn = 55, /**< LCDIF2 interrupt */ + eLCDIF_IRQn = 54, /**< eLCDIF interrupt */ + LCDIFv2_IRQn = 55, /**< LCDIFv2 interrupt */ CSI_IRQn = 56, /**< CSI interrupt */ PXP_IRQn = 57, /**< PXP interrupt */ MIPI_CSI_IRQn = 58, /**< MIPI_CSI interrupt */ @@ -263,16 +265,16 @@ typedef enum IRQn { DAC_IRQn = 63, /**< DAC interrupt */ KEY_MANAGER_IRQn = 64, /**< PUF interrupt */ WDOG2_IRQn = 65, /**< WDOG2 interrupt */ - SNVS_HP_WRAPPER_IRQn = 66, /**< SRTC Consolidated Interrupt. Non TZ */ - SNVS_HP_WRAPPER_TZ_IRQn = 67, /**< SRTC Security Interrupt. TZ */ - SNVS_LP_WRAPPER_IRQn = 68, /**< ON-OFF button press shorter than 5 secs (pulse event) */ + SNVS_HP_NON_TZ_IRQn = 66, /**< SRTC Consolidated Interrupt. Non TZ */ + SNVS_HP_TZ_IRQn = 67, /**< SRTC Security Interrupt. TZ */ + SNVS_PULSE_EVENT_IRQn = 68, /**< ON-OFF button press shorter than 5 secs (pulse event) */ CAAM_IRQ0_IRQn = 69, /**< CAAM interrupt queue for JQ0 */ CAAM_IRQ1_IRQn = 70, /**< CAAM interrupt queue for JQ1 */ CAAM_IRQ2_IRQn = 71, /**< CAAM interrupt queue for JQ2 */ CAAM_IRQ3_IRQn = 72, /**< CAAM interrupt queue for JQ3 */ CAAM_RECORVE_ERRPR_IRQn = 73, /**< CAAM interrupt for recoverable error */ - CAAM_RTC_IRQn = 74, /**< CAAM interrupt for RTC */ - Reserved91_IRQn = 75, /**< Reserved interrupt */ + CAAM_RTIC_IRQn = 74, /**< CAAM interrupt for RTIC */ + CDOG_IRQn = 75, /**< CDOG interrupt */ SAI1_IRQn = 76, /**< SAI1 interrupt */ SAI2_IRQn = 77, /**< SAI1 interrupt */ SAI3_RX_IRQn = 78, /**< SAI3 interrupt */ @@ -291,7 +293,7 @@ typedef enum IRQn { USBPHY2_IRQn = 91, /**< USBPHY2 interrupt */ RDC_IRQn = 92, /**< RDC interrupt */ GPIO13_Combined_0_31_IRQn = 93, /**< Combined interrupt indication for GPIO13 signal 0 throughout 31 */ - SFA_IRQn = 94, /**< SFA interrupt */ + Reserved110_IRQn = 94, /**< Reserved interrupt */ DCIC1_IRQn = 95, /**< DCIC1 interrupt */ DCIC2_IRQn = 96, /**< DCIC2 interrupt */ ASRC_IRQn = 97, /**< ASRC interrupt */ @@ -397,22 +399,22 @@ typedef enum IRQn { Reserved213_IRQn = 197, /**< Reserved interrupt */ Reserved214_IRQn = 198, /**< Reserved interrupt */ Reserved215_IRQn = 199, /**< Reserved interrupt */ - Reserved216_IRQn = 200, /**< Reserved interrupt */ - Reserved217_IRQn = 201, /**< Reserved interrupt */ + HWVAD_EVENT_IRQn = 200, /**< HWVAD event interrupt */ + HWVAD_ERROR_IRQn = 201, /**< HWVAD error interrupt */ PDM_EVENT_IRQn = 202, /**< PDM event interrupt */ PDM_ERROR_IRQn = 203, /**< PDM error interrupt */ EMVSIM1_IRQn = 204, /**< EMVSIM1 interrupt */ EMVSIM2_IRQn = 205, /**< EMVSIM2 interrupt */ - MECC1_INIT_IRQn = 206, /**< MECC1 init */ - MECC1_FATAL_INIT_IRQn = 207, /**< MECC1 fatal init */ - MECC2_INIT_IRQn = 208, /**< MECC2 init */ - MECC2_FATAL_INIT_IRQn = 209, /**< MECC2 fatal init */ - XECC_FLEXSPI1_INIT_IRQn = 210, /**< XECC init */ - XECC_FLEXSPI1_FATAL_INIT_IRQn = 211, /**< XECC fatal init */ - XECC_FLEXSPI2_INIT_IRQn = 212, /**< XECC init */ - XECC_FLEXSPI2_FATAL_INIT_IRQn = 213, /**< XECC fatal init */ - XECC_SEMC_INIT_IRQn = 214, /**< XECC init */ - XECC_SEMC_FATAL_INIT_IRQn = 215, /**< XECC fatal init */ + MECC1_INT_IRQn = 206, /**< MECC1 int */ + MECC1_FATAL_INT_IRQn = 207, /**< MECC1 fatal int */ + MECC2_INT_IRQn = 208, /**< MECC2 int */ + MECC2_FATAL_INT_IRQn = 209, /**< MECC2 fatal int */ + XECC_FLEXSPI1_INT_IRQn = 210, /**< XECC int */ + XECC_FLEXSPI1_FATAL_INT_IRQn = 211, /**< XECC fatal int */ + XECC_FLEXSPI2_INT_IRQn = 212, /**< XECC int */ + XECC_FLEXSPI2_FATAL_INT_IRQn = 213, /**< XECC fatal int */ + XECC_SEMC_INT_IRQn = 214, /**< XECC int */ + XECC_SEMC_FATAL_INT_IRQn = 215, /**< XECC fatal int */ ENET_QOS_IRQn = 216, /**< ENET_QOS interrupt */ ENET_QOS_PMT_IRQn = 217 /**< ENET_QOS_PMT interrupt */ } IRQn_Type; @@ -698,7 +700,7 @@ typedef enum _rdc_periph typedef enum _xbar_input_signal { - kXBARA1_InputRESERVED0 = 0|0x100U, /**< XBARA1_IN0 input is reserved. */ + kXBARA1_InputLogicLow = 0|0x100U, /**< LOGIC_LOW output assigned to XBARA1_IN0 input. */ kXBARA1_InputLogicHigh = 1|0x100U, /**< LOGIC_HIGH output assigned to XBARA1_IN1 input. */ kXBARA1_InputRESERVED2 = 2|0x100U, /**< XBARA1_IN2 input is reserved. */ kXBARA1_InputRESERVED3 = 3|0x100U, /**< XBARA1_IN3 input is reserved. */ @@ -748,22 +750,22 @@ typedef enum _xbar_input_signal kXBARA1_InputRESERVED47 = 47|0x100U, /**< XBARA1_IN47 input is reserved. */ kXBARA1_InputRESERVED48 = 48|0x100U, /**< XBARA1_IN48 input is reserved. */ kXBARA1_InputRESERVED49 = 49|0x100U, /**< XBARA1_IN49 input is reserved. */ - kXBARA1_InputQtimer1Tmr0Output = 50|0x100U, /**< QTIMER1_TMR0_OUTPUT output assigned to XBARA1_IN50 input. */ - kXBARA1_InputQtimer1Tmr1Output = 51|0x100U, /**< QTIMER1_TMR1_OUTPUT output assigned to XBARA1_IN51 input. */ - kXBARA1_InputQtimer1Tmr2Output = 52|0x100U, /**< QTIMER1_TMR2_OUTPUT output assigned to XBARA1_IN52 input. */ - kXBARA1_InputQtimer1Tmr3Output = 53|0x100U, /**< QTIMER1_TMR3_OUTPUT output assigned to XBARA1_IN53 input. */ - kXBARA1_InputQtimer2Tmr0Output = 54|0x100U, /**< QTIMER2_TMR0_OUTPUT output assigned to XBARA1_IN54 input. */ - kXBARA1_InputQtimer2Tmr1Output = 55|0x100U, /**< QTIMER2_TMR1_OUTPUT output assigned to XBARA1_IN55 input. */ - kXBARA1_InputQtimer2Tmr2Output = 56|0x100U, /**< QTIMER2_TMR2_OUTPUT output assigned to XBARA1_IN56 input. */ - kXBARA1_InputQtimer2Tmr3Output = 57|0x100U, /**< QTIMER2_TMR3_OUTPUT output assigned to XBARA1_IN57 input. */ - kXBARA1_InputQtimer3Tmr0Output = 58|0x100U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN58 input. */ - kXBARA1_InputQtimer3Tmr1Output = 59|0x100U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN59 input. */ - kXBARA1_InputQtimer3Tmr2Output = 60|0x100U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN60 input. */ - kXBARA1_InputQtimer3Tmr3Output = 61|0x100U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN61 input. */ - kXBARA1_InputQtimer4Tmr0Output = 62|0x100U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN62 input. */ - kXBARA1_InputQtimer4Tmr1Output = 63|0x100U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN63 input. */ - kXBARA1_InputQtimer4Tmr2Output = 64|0x100U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN64 input. */ - kXBARA1_InputQtimer4Tmr3Output = 65|0x100U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN65 input. */ + kXBARA1_InputQtimer1Timer0 = 50|0x100U, /**< QTIMER1_TIMER0 output assigned to XBARA1_IN50 input. */ + kXBARA1_InputQtimer1Timer1 = 51|0x100U, /**< QTIMER1_TIMER1 output assigned to XBARA1_IN51 input. */ + kXBARA1_InputQtimer1Timer2 = 52|0x100U, /**< QTIMER1_TIMER2 output assigned to XBARA1_IN52 input. */ + kXBARA1_InputQtimer1Timer3 = 53|0x100U, /**< QTIMER1_TIMER3 output assigned to XBARA1_IN53 input. */ + kXBARA1_InputQtimer2Timer0 = 54|0x100U, /**< QTIMER2_TIMER0 output assigned to XBARA1_IN54 input. */ + kXBARA1_InputQtimer2Timer1 = 55|0x100U, /**< QTIMER2_TIMER1 output assigned to XBARA1_IN55 input. */ + kXBARA1_InputQtimer2Timer2 = 56|0x100U, /**< QTIMER2_TIMER2 output assigned to XBARA1_IN56 input. */ + kXBARA1_InputQtimer2Timer3 = 57|0x100U, /**< QTIMER2_TIMER3 output assigned to XBARA1_IN57 input. */ + kXBARA1_InputQtimer3Timer0 = 58|0x100U, /**< QTIMER3_TIMER0 output assigned to XBARA1_IN58 input. */ + kXBARA1_InputQtimer3Timer1 = 59|0x100U, /**< QTIMER3_TIMER1 output assigned to XBARA1_IN59 input. */ + kXBARA1_InputQtimer3Timer2 = 60|0x100U, /**< QTIMER3_TIMER2 output assigned to XBARA1_IN60 input. */ + kXBARA1_InputQtimer3Timer3 = 61|0x100U, /**< QTIMER3_TIMER3 output assigned to XBARA1_IN61 input. */ + kXBARA1_InputQtimer4Timer0 = 62|0x100U, /**< QTIMER4_TIMER0 output assigned to XBARA1_IN62 input. */ + kXBARA1_InputQtimer4Timer1 = 63|0x100U, /**< QTIMER4_TIMER1 output assigned to XBARA1_IN63 input. */ + kXBARA1_InputQtimer4Timer2 = 64|0x100U, /**< QTIMER4_TIMER2 output assigned to XBARA1_IN64 input. */ + kXBARA1_InputQtimer4Timer3 = 65|0x100U, /**< QTIMER4_TIMER3 output assigned to XBARA1_IN65 input. */ kXBARA1_InputRESERVED66 = 66|0x100U, /**< XBARA1_IN66 input is reserved. */ kXBARA1_InputRESERVED67 = 67|0x100U, /**< XBARA1_IN67 input is reserved. */ kXBARA1_InputRESERVED68 = 68|0x100U, /**< XBARA1_IN68 input is reserved. */ @@ -800,14 +802,14 @@ typedef enum _xbar_input_signal kXBARA1_InputRESERVED99 = 99|0x100U, /**< XBARA1_IN99 input is reserved. */ kXBARA1_InputRESERVED100 = 100|0x100U, /**< XBARA1_IN100 input is reserved. */ kXBARA1_InputRESERVED101 = 101|0x100U, /**< XBARA1_IN101 input is reserved. */ - kXBARA1_InputPitTrigger0 = 102|0x100U, /**< PIT_TRIGGER0 output assigned to XBARA1_IN102 input. */ - kXBARA1_InputPitTrigger1 = 103|0x100U, /**< PIT_TRIGGER1 output assigned to XBARA1_IN103 input. */ - kXBARA1_InputPitTrigger2 = 104|0x100U, /**< PIT_TRIGGER2 output assigned to XBARA1_IN104 input. */ - kXBARA1_InputPitTrigger3 = 105|0x100U, /**< PIT_TRIGGER3 output assigned to XBARA1_IN105 input. */ - kXBARA1_InputEnc1PosMatch = 106|0x100U, /**< ENC1_POS_MATCH output assigned to XBARA1_IN106 input. */ - kXBARA1_InputEnc2PosMatch = 107|0x100U, /**< ENC2_POS_MATCH output assigned to XBARA1_IN107 input. */ - kXBARA1_InputEnc3PosMatch = 108|0x100U, /**< ENC3_POS_MATCH output assigned to XBARA1_IN108 input. */ - kXBARA1_InputEnc4PosMatch = 109|0x100U, /**< ENC4_POS_MATCH output assigned to XBARA1_IN109 input. */ + kXBARA1_InputPit1Trigger0 = 102|0x100U, /**< PIT1_TRIGGER0 output assigned to XBARA1_IN102 input. */ + kXBARA1_InputPit1Trigger1 = 103|0x100U, /**< PIT1_TRIGGER1 output assigned to XBARA1_IN103 input. */ + kXBARA1_InputPit1Trigger2 = 104|0x100U, /**< PIT1_TRIGGER2 output assigned to XBARA1_IN104 input. */ + kXBARA1_InputPit1Trigger3 = 105|0x100U, /**< PIT1_TRIGGER3 output assigned to XBARA1_IN105 input. */ + kXBARA1_InputDec1PosMatch = 106|0x100U, /**< DEC1_POS_MATCH output assigned to XBARA1_IN106 input. */ + kXBARA1_InputDec2PosMatch = 107|0x100U, /**< DEC2_POS_MATCH output assigned to XBARA1_IN107 input. */ + kXBARA1_InputDec3PosMatch = 108|0x100U, /**< DEC3_POS_MATCH output assigned to XBARA1_IN108 input. */ + kXBARA1_InputDec4PosMatch = 109|0x100U, /**< DEC4_POS_MATCH output assigned to XBARA1_IN109 input. */ kXBARA1_InputRESERVED110 = 110|0x100U, /**< XBARA1_IN110 input is reserved. */ kXBARA1_InputRESERVED111 = 111|0x100U, /**< XBARA1_IN111 input is reserved. */ kXBARA1_InputDmaDone0 = 112|0x100U, /**< DMA_DONE0 output assigned to XBARA1_IN112 input. */ @@ -834,15 +836,15 @@ typedef enum _xbar_input_signal kXBARA1_InputAoi2Out1 = 133|0x100U, /**< AOI2_OUT1 output assigned to XBARA1_IN133 input. */ kXBARA1_InputAoi2Out2 = 134|0x100U, /**< AOI2_OUT2 output assigned to XBARA1_IN134 input. */ kXBARA1_InputAoi2Out3 = 135|0x100U, /**< AOI2_OUT3 output assigned to XBARA1_IN135 input. */ - kXBARA1_InputAdcEtcXbar0Coco0 = 136|0x100U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN136 input. */ - kXBARA1_InputAdcEtcXbar0Coco1 = 137|0x100U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN137 input. */ - kXBARA1_InputAdcEtcXbar0Coco2 = 138|0x100U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN138 input. */ - kXBARA1_InputAdcEtcXbar0Coco3 = 139|0x100U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN139 input. */ - kXBARA1_InputAdcEtcXbar1Coco0 = 140|0x100U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN140 input. */ - kXBARA1_InputAdcEtcXbar1Coco1 = 141|0x100U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN141 input. */ - kXBARA1_InputAdcEtcXbar1Coco2 = 142|0x100U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN142 input. */ - kXBARA1_InputAdcEtcXbar1Coco3 = 143|0x100U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN143 input. */ - kXBARB2_InputRESERVED0 = 0|0x200U, /**< XBARB2_IN0 input is reserved. */ + kXBARA1_InputAdcEtc0Coco0 = 136|0x100U, /**< ADC_ETC0_COCO0 output assigned to XBARA1_IN136 input. */ + kXBARA1_InputAdcEtc0Coco1 = 137|0x100U, /**< ADC_ETC0_COCO1 output assigned to XBARA1_IN137 input. */ + kXBARA1_InputAdcEtc0Coco2 = 138|0x100U, /**< ADC_ETC0_COCO2 output assigned to XBARA1_IN138 input. */ + kXBARA1_InputAdcEtc0Coco3 = 139|0x100U, /**< ADC_ETC0_COCO3 output assigned to XBARA1_IN139 input. */ + kXBARA1_InputAdcEtc1Coco0 = 140|0x100U, /**< ADC_ETC1_COCO0 output assigned to XBARA1_IN140 input. */ + kXBARA1_InputAdcEtc1Coco1 = 141|0x100U, /**< ADC_ETC1_COCO1 output assigned to XBARA1_IN141 input. */ + kXBARA1_InputAdcEtc1Coco2 = 142|0x100U, /**< ADC_ETC1_COCO2 output assigned to XBARA1_IN142 input. */ + kXBARA1_InputAdcEtc1Coco3 = 143|0x100U, /**< ADC_ETC1_COCO3 output assigned to XBARA1_IN143 input. */ + kXBARB2_InputLogicLow = 0|0x200U, /**< LOGIC_LOW output assigned to XBARB2_IN0 input. */ kXBARB2_InputLogicHigh = 1|0x200U, /**< LOGIC_HIGH output assigned to XBARB2_IN1 input. */ kXBARB2_InputAcmp1Out = 2|0x200U, /**< ACMP1_OUT output assigned to XBARB2_IN2 input. */ kXBARB2_InputAcmp2Out = 3|0x200U, /**< ACMP2_OUT output assigned to XBARB2_IN3 input. */ @@ -852,22 +854,22 @@ typedef enum _xbar_input_signal kXBARB2_InputRESERVED7 = 7|0x200U, /**< XBARB2_IN7 input is reserved. */ kXBARB2_InputRESERVED8 = 8|0x200U, /**< XBARB2_IN8 input is reserved. */ kXBARB2_InputRESERVED9 = 9|0x200U, /**< XBARB2_IN9 input is reserved. */ - kXBARB2_InputQtimer1Tmr0Output = 10|0x200U, /**< QTIMER1_TMR0_OUTPUT output assigned to XBARB2_IN10 input. */ - kXBARB2_InputQtimer1Tmr1Output = 11|0x200U, /**< QTIMER1_TMR1_OUTPUT output assigned to XBARB2_IN11 input. */ - kXBARB2_InputQtimer1Tmr2Output = 12|0x200U, /**< QTIMER1_TMR2_OUTPUT output assigned to XBARB2_IN12 input. */ - kXBARB2_InputQtimer1Tmr3Output = 13|0x200U, /**< QTIMER1_TMR3_OUTPUT output assigned to XBARB2_IN13 input. */ - kXBARB2_InputQtimer2Tmr0Output = 14|0x200U, /**< QTIMER2_TMR0_OUTPUT output assigned to XBARB2_IN14 input. */ - kXBARB2_InputQtimer2Tmr1Output = 15|0x200U, /**< QTIMER2_TMR1_OUTPUT output assigned to XBARB2_IN15 input. */ - kXBARB2_InputQtimer2Tmr2Output = 16|0x200U, /**< QTIMER2_TMR2_OUTPUT output assigned to XBARB2_IN16 input. */ - kXBARB2_InputQtimer2Tmr3Output = 17|0x200U, /**< QTIMER2_TMR3_OUTPUT output assigned to XBARB2_IN17 input. */ - kXBARB2_InputQtimer3Tmr0Output = 18|0x200U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN18 input. */ - kXBARB2_InputQtimer3Tmr1Output = 19|0x200U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN19 input. */ - kXBARB2_InputQtimer3Tmr2Output = 20|0x200U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN20 input. */ - kXBARB2_InputQtimer3Tmr3Output = 21|0x200U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN21 input. */ - kXBARB2_InputQtimer4Tmr0Output = 22|0x200U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN22 input. */ - kXBARB2_InputQtimer4Tmr1Output = 23|0x200U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN23 input. */ - kXBARB2_InputQtimer4Tmr2Output = 24|0x200U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN24 input. */ - kXBARB2_InputQtimer4Tmr3Output = 25|0x200U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN25 input. */ + kXBARB2_InputQtimer1Timer0 = 10|0x200U, /**< QTIMER1_TIMER0 output assigned to XBARB2_IN10 input. */ + kXBARB2_InputQtimer1Timer1 = 11|0x200U, /**< QTIMER1_TIMER1 output assigned to XBARB2_IN11 input. */ + kXBARB2_InputQtimer1Timer2 = 12|0x200U, /**< QTIMER1_TIMER2 output assigned to XBARB2_IN12 input. */ + kXBARB2_InputQtimer1Timer3 = 13|0x200U, /**< QTIMER1_TIMER3 output assigned to XBARB2_IN13 input. */ + kXBARB2_InputQtimer2Timer0 = 14|0x200U, /**< QTIMER2_TIMER0 output assigned to XBARB2_IN14 input. */ + kXBARB2_InputQtimer2Timer1 = 15|0x200U, /**< QTIMER2_TIMER1 output assigned to XBARB2_IN15 input. */ + kXBARB2_InputQtimer2Timer2 = 16|0x200U, /**< QTIMER2_TIMER2 output assigned to XBARB2_IN16 input. */ + kXBARB2_InputQtimer2Timer3 = 17|0x200U, /**< QTIMER2_TIMER3 output assigned to XBARB2_IN17 input. */ + kXBARB2_InputQtimer3Timer0 = 18|0x200U, /**< QTIMER3_TIMER0 output assigned to XBARB2_IN18 input. */ + kXBARB2_InputQtimer3Timer1 = 19|0x200U, /**< QTIMER3_TIMER1 output assigned to XBARB2_IN19 input. */ + kXBARB2_InputQtimer3Timer2 = 20|0x200U, /**< QTIMER3_TIMER2 output assigned to XBARB2_IN20 input. */ + kXBARB2_InputQtimer3Timer3 = 21|0x200U, /**< QTIMER3_TIMER3 output assigned to XBARB2_IN21 input. */ + kXBARB2_InputQtimer4Timer0 = 22|0x200U, /**< QTIMER4_TIMER0 output assigned to XBARB2_IN22 input. */ + kXBARB2_InputQtimer4Timer1 = 23|0x200U, /**< QTIMER4_TIMER1 output assigned to XBARB2_IN23 input. */ + kXBARB2_InputQtimer4Timer2 = 24|0x200U, /**< QTIMER4_TIMER2 output assigned to XBARB2_IN24 input. */ + kXBARB2_InputQtimer4Timer3 = 25|0x200U, /**< QTIMER4_TIMER3 output assigned to XBARB2_IN25 input. */ kXBARB2_InputRESERVED26 = 26|0x200U, /**< XBARB2_IN26 input is reserved. */ kXBARB2_InputRESERVED27 = 27|0x200U, /**< XBARB2_IN27 input is reserved. */ kXBARB2_InputRESERVED28 = 28|0x200U, /**< XBARB2_IN28 input is reserved. */ @@ -876,22 +878,22 @@ typedef enum _xbar_input_signal kXBARB2_InputRESERVED31 = 31|0x200U, /**< XBARB2_IN31 input is reserved. */ kXBARB2_InputRESERVED32 = 32|0x200U, /**< XBARB2_IN32 input is reserved. */ kXBARB2_InputRESERVED33 = 33|0x200U, /**< XBARB2_IN33 input is reserved. */ - kXBARB2_InputFlexpwm1Pwm01OutTrig0 = 34|0x200U, /**< FLEXPWM1_PWM0_1_OUT_TRIG0 output assigned to XBARB2_IN34 input. */ - kXBARB2_InputFlexpwm1Pwm01OutTrig1 = 35|0x200U, /**< FLEXPWM1_PWM0_1_OUT_TRIG1 output assigned to XBARB2_IN35 input. */ - kXBARB2_InputFlexpwm1Pwm01OutTrig2 = 36|0x200U, /**< FLEXPWM1_PWM0_1_OUT_TRIG2 output assigned to XBARB2_IN36 input. */ - kXBARB2_InputFlexpwm1Pwm01OutTrig3 = 37|0x200U, /**< FLEXPWM1_PWM0_1_OUT_TRIG3 output assigned to XBARB2_IN37 input. */ - kXBARB2_InputFlexpwm2Pwm01OutTrig0 = 38|0x200U, /**< FLEXPWM2_PWM0_1_OUT_TRIG0 output assigned to XBARB2_IN38 input. */ - kXBARB2_InputFlexpwm2Pwm01OutTrig1 = 39|0x200U, /**< FLEXPWM2_PWM0_1_OUT_TRIG1 output assigned to XBARB2_IN39 input. */ - kXBARB2_InputFlexpwm2Pwm01OutTrig2 = 40|0x200U, /**< FLEXPWM2_PWM0_1_OUT_TRIG2 output assigned to XBARB2_IN40 input. */ - kXBARB2_InputFlexpwm2Pwm01OutTrig3 = 41|0x200U, /**< FLEXPWM2_PWM0_1_OUT_TRIG3 output assigned to XBARB2_IN41 input. */ - kXBARB2_InputFlexpwm3Pwm01OutTrig0 = 42|0x200U, /**< FLEXPWM3_PWM0_1_OUT_TRIG0 output assigned to XBARB2_IN42 input. */ - kXBARB2_InputFlexpwm3Pwm01OutTrig1 = 43|0x200U, /**< FLEXPWM3_PWM0_1_OUT_TRIG1 output assigned to XBARB2_IN43 input. */ - kXBARB2_InputFlexpwm3Pwm01OutTrig2 = 44|0x200U, /**< FLEXPWM3_PWM0_1_OUT_TRIG2 output assigned to XBARB2_IN44 input. */ - kXBARB2_InputFlexpwm3Pwm01OutTrig3 = 45|0x200U, /**< FLEXPWM3_PWM0_1_OUT_TRIG3 output assigned to XBARB2_IN45 input. */ - kXBARB2_InputFlexpwm4Pwm01OutTrig0 = 46|0x200U, /**< FLEXPWM4_PWM0_1_OUT_TRIG0 output assigned to XBARB2_IN46 input. */ - kXBARB2_InputFlexpwm4Pwm01OutTrig1 = 47|0x200U, /**< FLEXPWM4_PWM0_1_OUT_TRIG1 output assigned to XBARB2_IN47 input. */ - kXBARB2_InputFlexpwm4Pwm01OutTrig2 = 48|0x200U, /**< FLEXPWM4_PWM0_1_OUT_TRIG2 output assigned to XBARB2_IN48 input. */ - kXBARB2_InputFlexpwm4Pwm01OutTrig3 = 49|0x200U, /**< FLEXPWM4_PWM0_1_OUT_TRIG3 output assigned to XBARB2_IN49 input. */ + kXBARB2_InputFlexpwm1Pwm0OutTrig01 = 34|0x200U, /**< FLEXPWM1_PWM0_OUT_TRIG0_1 output assigned to XBARB2_IN34 input. */ + kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 35|0x200U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN35 input. */ + kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 36|0x200U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN36 input. */ + kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 37|0x200U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN37 input. */ + kXBARB2_InputFlexpwm2Pwm0OutTrig01 = 38|0x200U, /**< FLEXPWM2_PWM0_OUT_TRIG0_1 output assigned to XBARB2_IN38 input. */ + kXBARB2_InputFlexpwm2Pwm1OutTrig01 = 39|0x200U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN39 input. */ + kXBARB2_InputFlexpwm2Pwm2OutTrig01 = 40|0x200U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN40 input. */ + kXBARB2_InputFlexpwm2Pwm3OutTrig01 = 41|0x200U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN41 input. */ + kXBARB2_InputFlexpwm3Pwm0OutTrig01 = 42|0x200U, /**< FLEXPWM3_PWM0_OUT_TRIG0_1 output assigned to XBARB2_IN42 input. */ + kXBARB2_InputFlexpwm3Pwm1OutTrig01 = 43|0x200U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN43 input. */ + kXBARB2_InputFlexpwm3Pwm2OutTrig01 = 44|0x200U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN44 input. */ + kXBARB2_InputFlexpwm3Pwm3OutTrig01 = 45|0x200U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN45 input. */ + kXBARB2_InputFlexpwm4Pwm0OutTrig01 = 46|0x200U, /**< FLEXPWM4_PWM0_OUT_TRIG0_1 output assigned to XBARB2_IN46 input. */ + kXBARB2_InputFlexpwm4Pwm1OutTrig01 = 47|0x200U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN47 input. */ + kXBARB2_InputFlexpwm4Pwm2OutTrig01 = 48|0x200U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN48 input. */ + kXBARB2_InputFlexpwm4Pwm3OutTrig01 = 49|0x200U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN49 input. */ kXBARB2_InputRESERVED50 = 50|0x200U, /**< XBARB2_IN50 input is reserved. */ kXBARB2_InputRESERVED51 = 51|0x200U, /**< XBARB2_IN51 input is reserved. */ kXBARB2_InputRESERVED52 = 52|0x200U, /**< XBARB2_IN52 input is reserved. */ @@ -900,16 +902,16 @@ typedef enum _xbar_input_signal kXBARB2_InputRESERVED55 = 55|0x200U, /**< XBARB2_IN55 input is reserved. */ kXBARB2_InputRESERVED56 = 56|0x200U, /**< XBARB2_IN56 input is reserved. */ kXBARB2_InputRESERVED57 = 57|0x200U, /**< XBARB2_IN57 input is reserved. */ - kXBARB2_InputPitTrigger0 = 58|0x200U, /**< PIT_TRIGGER0 output assigned to XBARB2_IN58 input. */ - kXBARB2_InputPitTrigger1 = 59|0x200U, /**< PIT_TRIGGER1 output assigned to XBARB2_IN59 input. */ - kXBARB2_InputAdcEtcXbar0Coco0 = 60|0x200U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN60 input. */ - kXBARB2_InputAdcEtcXbar0Coco1 = 61|0x200U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN61 input. */ - kXBARB2_InputAdcEtcXbar0Coco2 = 62|0x200U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN62 input. */ - kXBARB2_InputAdcEtcXbar0Coco3 = 63|0x200U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN63 input. */ - kXBARB2_InputAdcEtcXbar1Coco0 = 64|0x200U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN64 input. */ - kXBARB2_InputAdcEtcXbar1Coco1 = 65|0x200U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN65 input. */ - kXBARB2_InputAdcEtcXbar1Coco2 = 66|0x200U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN66 input. */ - kXBARB2_InputAdcEtcXbar1Coco3 = 67|0x200U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN67 input. */ + kXBARB2_InputPit1Trigger0 = 58|0x200U, /**< PIT1_TRIGGER0 output assigned to XBARB2_IN58 input. */ + kXBARB2_InputPit1Trigger1 = 59|0x200U, /**< PIT1_TRIGGER1 output assigned to XBARB2_IN59 input. */ + kXBARB2_InputAdcEtc0Coco0 = 60|0x200U, /**< ADC_ETC0_COCO0 output assigned to XBARB2_IN60 input. */ + kXBARB2_InputAdcEtc0Coco1 = 61|0x200U, /**< ADC_ETC0_COCO1 output assigned to XBARB2_IN61 input. */ + kXBARB2_InputAdcEtc0Coco2 = 62|0x200U, /**< ADC_ETC0_COCO2 output assigned to XBARB2_IN62 input. */ + kXBARB2_InputAdcEtc0Coco3 = 63|0x200U, /**< ADC_ETC0_COCO3 output assigned to XBARB2_IN63 input. */ + kXBARB2_InputAdcEtc1Coco0 = 64|0x200U, /**< ADC_ETC1_COCO0 output assigned to XBARB2_IN64 input. */ + kXBARB2_InputAdcEtc1Coco1 = 65|0x200U, /**< ADC_ETC1_COCO1 output assigned to XBARB2_IN65 input. */ + kXBARB2_InputAdcEtc1Coco2 = 66|0x200U, /**< ADC_ETC1_COCO2 output assigned to XBARB2_IN66 input. */ + kXBARB2_InputAdcEtc1Coco3 = 67|0x200U, /**< ADC_ETC1_COCO3 output assigned to XBARB2_IN67 input. */ kXBARB2_InputRESERVED68 = 68|0x200U, /**< XBARB2_IN68 input is reserved. */ kXBARB2_InputRESERVED69 = 69|0x200U, /**< XBARB2_IN69 input is reserved. */ kXBARB2_InputRESERVED70 = 70|0x200U, /**< XBARB2_IN70 input is reserved. */ @@ -918,10 +920,10 @@ typedef enum _xbar_input_signal kXBARB2_InputRESERVED73 = 73|0x200U, /**< XBARB2_IN73 input is reserved. */ kXBARB2_InputRESERVED74 = 74|0x200U, /**< XBARB2_IN74 input is reserved. */ kXBARB2_InputRESERVED75 = 75|0x200U, /**< XBARB2_IN75 input is reserved. */ - kXBARB2_InputEnc1PosMatch = 76|0x200U, /**< ENC1_POS_MATCH output assigned to XBARB2_IN76 input. */ - kXBARB2_InputEnc2PosMatch = 77|0x200U, /**< ENC2_POS_MATCH output assigned to XBARB2_IN77 input. */ - kXBARB2_InputEnc3PosMatch = 78|0x200U, /**< ENC3_POS_MATCH output assigned to XBARB2_IN78 input. */ - kXBARB2_InputEnc4PosMatch = 79|0x200U, /**< ENC4_POS_MATCH output assigned to XBARB2_IN79 input. */ + kXBARB2_InputDec1PosMatch = 76|0x200U, /**< DEC1_POS_MATCH output assigned to XBARB2_IN76 input. */ + kXBARB2_InputDec2PosMatch = 77|0x200U, /**< DEC2_POS_MATCH output assigned to XBARB2_IN77 input. */ + kXBARB2_InputDec3PosMatch = 78|0x200U, /**< DEC3_POS_MATCH output assigned to XBARB2_IN78 input. */ + kXBARB2_InputDec4PosMatch = 79|0x200U, /**< DEC4_POS_MATCH output assigned to XBARB2_IN79 input. */ kXBARB2_InputRESERVED80 = 80|0x200U, /**< XBARB2_IN80 input is reserved. */ kXBARB2_InputRESERVED81 = 81|0x200U, /**< XBARB2_IN81 input is reserved. */ kXBARB2_InputDmaDone0 = 82|0x200U, /**< DMA_DONE0 output assigned to XBARB2_IN82 input. */ @@ -940,7 +942,7 @@ typedef enum _xbar_input_signal kXBARB2_InputDmaLpsrDone5 = 95|0x200U, /**< DMA_LPSR_DONE5 output assigned to XBARB2_IN95 input. */ kXBARB2_InputDmaLpsrDone6 = 96|0x200U, /**< DMA_LPSR_DONE6 output assigned to XBARB2_IN96 input. */ kXBARB2_InputDmaLpsrDone7 = 97|0x200U, /**< DMA_LPSR_DONE7 output assigned to XBARB2_IN97 input. */ - kXBARB3_InputRESERVED0 = 0|0x300U, /**< XBARB3_IN0 input is reserved. */ + kXBARB3_InputLogicLow = 0|0x300U, /**< LOGIC_LOW output assigned to XBARB3_IN0 input. */ kXBARB3_InputLogicHigh = 1|0x300U, /**< LOGIC_HIGH output assigned to XBARB3_IN1 input. */ kXBARB3_InputAcmp1Out = 2|0x300U, /**< ACMP1_OUT output assigned to XBARB3_IN2 input. */ kXBARB3_InputAcmp2Out = 3|0x300U, /**< ACMP2_OUT output assigned to XBARB3_IN3 input. */ @@ -950,22 +952,22 @@ typedef enum _xbar_input_signal kXBARB3_InputRESERVED7 = 7|0x300U, /**< XBARB3_IN7 input is reserved. */ kXBARB3_InputRESERVED8 = 8|0x300U, /**< XBARB3_IN8 input is reserved. */ kXBARB3_InputRESERVED9 = 9|0x300U, /**< XBARB3_IN9 input is reserved. */ - kXBARB3_InputQtimer1Tmr0Output = 10|0x300U, /**< QTIMER1_TMR0_OUTPUT output assigned to XBARB3_IN10 input. */ - kXBARB3_InputQtimer1Tmr1Output = 11|0x300U, /**< QTIMER1_TMR1_OUTPUT output assigned to XBARB3_IN11 input. */ - kXBARB3_InputQtimer1Tmr2Output = 12|0x300U, /**< QTIMER1_TMR2_OUTPUT output assigned to XBARB3_IN12 input. */ - kXBARB3_InputQtimer1Tmr3Output = 13|0x300U, /**< QTIMER1_TMR3_OUTPUT output assigned to XBARB3_IN13 input. */ - kXBARB3_InputQtimer2Tmr0Output = 14|0x300U, /**< QTIMER2_TMR0_OUTPUT output assigned to XBARB3_IN14 input. */ - kXBARB3_InputQtimer2Tmr1Output = 15|0x300U, /**< QTIMER2_TMR1_OUTPUT output assigned to XBARB3_IN15 input. */ - kXBARB3_InputQtimer2Tmr2Output = 16|0x300U, /**< QTIMER2_TMR2_OUTPUT output assigned to XBARB3_IN16 input. */ - kXBARB3_InputQtimer2Tmr3Output = 17|0x300U, /**< QTIMER2_TMR3_OUTPUT output assigned to XBARB3_IN17 input. */ - kXBARB3_InputQtimer3Tmr0Output = 18|0x300U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARB3_IN18 input. */ - kXBARB3_InputQtimer3Tmr1Output = 19|0x300U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARB3_IN19 input. */ - kXBARB3_InputQtimer3Tmr2Output = 20|0x300U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARB3_IN20 input. */ - kXBARB3_InputQtimer3Tmr3Output = 21|0x300U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARB3_IN21 input. */ - kXBARB3_InputQtimer4Tmr0Output = 22|0x300U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARB3_IN22 input. */ - kXBARB3_InputQtimer4Tmr1Output = 23|0x300U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARB3_IN23 input. */ - kXBARB3_InputQtimer4Tmr2Output = 24|0x300U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARB3_IN24 input. */ - kXBARB3_InputQtimer4Tmr3Output = 25|0x300U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARB3_IN25 input. */ + kXBARB3_InputQtimer1Timer0 = 10|0x300U, /**< QTIMER1_TIMER0 output assigned to XBARB3_IN10 input. */ + kXBARB3_InputQtimer1Timer1 = 11|0x300U, /**< QTIMER1_TIMER1 output assigned to XBARB3_IN11 input. */ + kXBARB3_InputQtimer1Timer2 = 12|0x300U, /**< QTIMER1_TIMER2 output assigned to XBARB3_IN12 input. */ + kXBARB3_InputQtimer1Timer3 = 13|0x300U, /**< QTIMER1_TIMER3 output assigned to XBARB3_IN13 input. */ + kXBARB3_InputQtimer2Timer0 = 14|0x300U, /**< QTIMER2_TIMER0 output assigned to XBARB3_IN14 input. */ + kXBARB3_InputQtimer2Timer1 = 15|0x300U, /**< QTIMER2_TIMER1 output assigned to XBARB3_IN15 input. */ + kXBARB3_InputQtimer2Timer2 = 16|0x300U, /**< QTIMER2_TIMER2 output assigned to XBARB3_IN16 input. */ + kXBARB3_InputQtimer2Timer3 = 17|0x300U, /**< QTIMER2_TIMER3 output assigned to XBARB3_IN17 input. */ + kXBARB3_InputQtimer3Timer0 = 18|0x300U, /**< QTIMER3_TIMER0 output assigned to XBARB3_IN18 input. */ + kXBARB3_InputQtimer3Timer1 = 19|0x300U, /**< QTIMER3_TIMER1 output assigned to XBARB3_IN19 input. */ + kXBARB3_InputQtimer3Timer2 = 20|0x300U, /**< QTIMER3_TIMER2 output assigned to XBARB3_IN20 input. */ + kXBARB3_InputQtimer3Timer3 = 21|0x300U, /**< QTIMER3_TIMER3 output assigned to XBARB3_IN21 input. */ + kXBARB3_InputQtimer4Timer0 = 22|0x300U, /**< QTIMER4_TIMER0 output assigned to XBARB3_IN22 input. */ + kXBARB3_InputQtimer4Timer1 = 23|0x300U, /**< QTIMER4_TIMER1 output assigned to XBARB3_IN23 input. */ + kXBARB3_InputQtimer4Timer2 = 24|0x300U, /**< QTIMER4_TIMER2 output assigned to XBARB3_IN24 input. */ + kXBARB3_InputQtimer4Timer3 = 25|0x300U, /**< QTIMER4_TIMER3 output assigned to XBARB3_IN25 input. */ kXBARB3_InputRESERVED26 = 26|0x300U, /**< XBARB3_IN26 input is reserved. */ kXBARB3_InputRESERVED27 = 27|0x300U, /**< XBARB3_IN27 input is reserved. */ kXBARB3_InputRESERVED28 = 28|0x300U, /**< XBARB3_IN28 input is reserved. */ @@ -974,22 +976,22 @@ typedef enum _xbar_input_signal kXBARB3_InputRESERVED31 = 31|0x300U, /**< XBARB3_IN31 input is reserved. */ kXBARB3_InputRESERVED32 = 32|0x300U, /**< XBARB3_IN32 input is reserved. */ kXBARB3_InputRESERVED33 = 33|0x300U, /**< XBARB3_IN33 input is reserved. */ - kXBARB3_InputFlexpwm1Pwm01OutTrig0 = 34|0x300U, /**< FLEXPWM1_PWM0_1_OUT_TRIG0 output assigned to XBARB3_IN34 input. */ - kXBARB3_InputFlexpwm1Pwm01OutTrig1 = 35|0x300U, /**< FLEXPWM1_PWM0_1_OUT_TRIG1 output assigned to XBARB3_IN35 input. */ - kXBARB3_InputFlexpwm1Pwm01OutTrig2 = 36|0x300U, /**< FLEXPWM1_PWM0_1_OUT_TRIG2 output assigned to XBARB3_IN36 input. */ - kXBARB3_InputFlexpwm1Pwm01OutTrig3 = 37|0x300U, /**< FLEXPWM1_PWM0_1_OUT_TRIG3 output assigned to XBARB3_IN37 input. */ - kXBARB3_InputFlexpwm2Pwm01OutTrig0 = 38|0x300U, /**< FLEXPWM2_PWM0_1_OUT_TRIG0 output assigned to XBARB3_IN38 input. */ - kXBARB3_InputFlexpwm2Pwm01OutTrig1 = 39|0x300U, /**< FLEXPWM2_PWM0_1_OUT_TRIG1 output assigned to XBARB3_IN39 input. */ - kXBARB3_InputFlexpwm2Pwm01OutTrig2 = 40|0x300U, /**< FLEXPWM2_PWM0_1_OUT_TRIG2 output assigned to XBARB3_IN40 input. */ - kXBARB3_InputFlexpwm2Pwm01OutTrig3 = 41|0x300U, /**< FLEXPWM2_PWM0_1_OUT_TRIG3 output assigned to XBARB3_IN41 input. */ - kXBARB3_InputFlexpwm3Pwm01OutTrig0 = 42|0x300U, /**< FLEXPWM3_PWM0_1_OUT_TRIG0 output assigned to XBARB3_IN42 input. */ - kXBARB3_InputFlexpwm3Pwm01OutTrig1 = 43|0x300U, /**< FLEXPWM3_PWM0_1_OUT_TRIG1 output assigned to XBARB3_IN43 input. */ - kXBARB3_InputFlexpwm3Pwm01OutTrig2 = 44|0x300U, /**< FLEXPWM3_PWM0_1_OUT_TRIG2 output assigned to XBARB3_IN44 input. */ - kXBARB3_InputFlexpwm3Pwm01OutTrig3 = 45|0x300U, /**< FLEXPWM3_PWM0_1_OUT_TRIG3 output assigned to XBARB3_IN45 input. */ - kXBARB3_InputFlexpwm4Pwm01OutTrig0 = 46|0x300U, /**< FLEXPWM4_PWM0_1_OUT_TRIG0 output assigned to XBARB3_IN46 input. */ - kXBARB3_InputFlexpwm4Pwm01OutTrig1 = 47|0x300U, /**< FLEXPWM4_PWM0_1_OUT_TRIG1 output assigned to XBARB3_IN47 input. */ - kXBARB3_InputFlexpwm4Pwm01OutTrig2 = 48|0x300U, /**< FLEXPWM4_PWM0_1_OUT_TRIG2 output assigned to XBARB3_IN48 input. */ - kXBARB3_InputFlexpwm4Pwm01OutTrig3 = 49|0x300U, /**< FLEXPWM4_PWM0_1_OUT_TRIG3 output assigned to XBARB3_IN49 input. */ + kXBARB3_InputFlexpwm1Pwm0OutTrig01 = 34|0x300U, /**< FLEXPWM1_PWM0_OUT_TRIG0_1 output assigned to XBARB3_IN34 input. */ + kXBARB3_InputFlexpwm1Pwm1OutTrig01 = 35|0x300U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN35 input. */ + kXBARB3_InputFlexpwm1Pwm2OutTrig01 = 36|0x300U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN36 input. */ + kXBARB3_InputFlexpwm1Pwm3OutTrig01 = 37|0x300U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN37 input. */ + kXBARB3_InputFlexpwm2Pwm0OutTrig01 = 38|0x300U, /**< FLEXPWM2_PWM0_OUT_TRIG0_1 output assigned to XBARB3_IN38 input. */ + kXBARB3_InputFlexpwm2Pwm1OutTrig01 = 39|0x300U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN39 input. */ + kXBARB3_InputFlexpwm2Pwm2OutTrig01 = 40|0x300U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN40 input. */ + kXBARB3_InputFlexpwm2Pwm3OutTrig01 = 41|0x300U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN41 input. */ + kXBARB3_InputFlexpwm3Pwm0OutTrig01 = 42|0x300U, /**< FLEXPWM3_PWM0_OUT_TRIG0_1 output assigned to XBARB3_IN42 input. */ + kXBARB3_InputFlexpwm3Pwm1OutTrig01 = 43|0x300U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN43 input. */ + kXBARB3_InputFlexpwm3Pwm2OutTrig01 = 44|0x300U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN44 input. */ + kXBARB3_InputFlexpwm3Pwm3OutTrig01 = 45|0x300U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN45 input. */ + kXBARB3_InputFlexpwm4Pwm0OutTrig01 = 46|0x300U, /**< FLEXPWM4_PWM0_OUT_TRIG0_1 output assigned to XBARB3_IN46 input. */ + kXBARB3_InputFlexpwm4Pwm1OutTrig01 = 47|0x300U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN47 input. */ + kXBARB3_InputFlexpwm4Pwm2OutTrig01 = 48|0x300U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN48 input. */ + kXBARB3_InputFlexpwm4Pwm3OutTrig01 = 49|0x300U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN49 input. */ kXBARB3_InputRESERVED50 = 50|0x300U, /**< XBARB3_IN50 input is reserved. */ kXBARB3_InputRESERVED51 = 51|0x300U, /**< XBARB3_IN51 input is reserved. */ kXBARB3_InputRESERVED52 = 52|0x300U, /**< XBARB3_IN52 input is reserved. */ @@ -998,16 +1000,16 @@ typedef enum _xbar_input_signal kXBARB3_InputRESERVED55 = 55|0x300U, /**< XBARB3_IN55 input is reserved. */ kXBARB3_InputRESERVED56 = 56|0x300U, /**< XBARB3_IN56 input is reserved. */ kXBARB3_InputRESERVED57 = 57|0x300U, /**< XBARB3_IN57 input is reserved. */ - kXBARB3_InputPitTrigger0 = 58|0x300U, /**< PIT_TRIGGER0 output assigned to XBARB3_IN58 input. */ - kXBARB3_InputPitTrigger1 = 59|0x300U, /**< PIT_TRIGGER1 output assigned to XBARB3_IN59 input. */ - kXBARB3_InputAdcEtcXbar0Coco0 = 60|0x300U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARB3_IN60 input. */ - kXBARB3_InputAdcEtcXbar0Coco1 = 61|0x300U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARB3_IN61 input. */ - kXBARB3_InputAdcEtcXbar0Coco2 = 62|0x300U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARB3_IN62 input. */ - kXBARB3_InputAdcEtcXbar0Coco3 = 63|0x300U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARB3_IN63 input. */ - kXBARB3_InputAdcEtcXbar1Coco0 = 64|0x300U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARB3_IN64 input. */ - kXBARB3_InputAdcEtcXbar1Coco1 = 65|0x300U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARB3_IN65 input. */ - kXBARB3_InputAdcEtcXbar1Coco2 = 66|0x300U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARB3_IN66 input. */ - kXBARB3_InputAdcEtcXbar1Coco3 = 67|0x300U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARB3_IN67 input. */ + kXBARB3_InputPit1Trigger0 = 58|0x300U, /**< PIT1_TRIGGER0 output assigned to XBARB3_IN58 input. */ + kXBARB3_InputPit1Trigger1 = 59|0x300U, /**< PIT1_TRIGGER1 output assigned to XBARB3_IN59 input. */ + kXBARB3_InputAdcEtc0Coco0 = 60|0x300U, /**< ADC_ETC0_COCO0 output assigned to XBARB3_IN60 input. */ + kXBARB3_InputAdcEtc0Coco1 = 61|0x300U, /**< ADC_ETC0_COCO1 output assigned to XBARB3_IN61 input. */ + kXBARB3_InputAdcEtc0Coco2 = 62|0x300U, /**< ADC_ETC0_COCO2 output assigned to XBARB3_IN62 input. */ + kXBARB3_InputAdcEtc0Coco3 = 63|0x300U, /**< ADC_ETC0_COCO3 output assigned to XBARB3_IN63 input. */ + kXBARB3_InputAdcEtc1Coco0 = 64|0x300U, /**< ADC_ETC1_COCO0 output assigned to XBARB3_IN64 input. */ + kXBARB3_InputAdcEtc1Coco1 = 65|0x300U, /**< ADC_ETC1_COCO1 output assigned to XBARB3_IN65 input. */ + kXBARB3_InputAdcEtc1Coco2 = 66|0x300U, /**< ADC_ETC1_COCO2 output assigned to XBARB3_IN66 input. */ + kXBARB3_InputAdcEtc1Coco3 = 67|0x300U, /**< ADC_ETC1_COCO3 output assigned to XBARB3_IN67 input. */ kXBARB3_InputRESERVED68 = 68|0x300U, /**< XBARB3_IN68 input is reserved. */ kXBARB3_InputRESERVED69 = 69|0x300U, /**< XBARB3_IN69 input is reserved. */ kXBARB3_InputRESERVED70 = 70|0x300U, /**< XBARB3_IN70 input is reserved. */ @@ -1016,10 +1018,10 @@ typedef enum _xbar_input_signal kXBARB3_InputRESERVED73 = 73|0x300U, /**< XBARB3_IN73 input is reserved. */ kXBARB3_InputRESERVED74 = 74|0x300U, /**< XBARB3_IN74 input is reserved. */ kXBARB3_InputRESERVED75 = 75|0x300U, /**< XBARB3_IN75 input is reserved. */ - kXBARB3_InputEnc1PosMatch = 76|0x300U, /**< ENC1_POS_MATCH output assigned to XBARB3_IN76 input. */ - kXBARB3_InputEnc2PosMatch = 77|0x300U, /**< ENC2_POS_MATCH output assigned to XBARB3_IN77 input. */ - kXBARB3_InputEnc3PosMatch = 78|0x300U, /**< ENC3_POS_MATCH output assigned to XBARB3_IN78 input. */ - kXBARB3_InputEnc4PosMatch = 79|0x300U, /**< ENC4_POS_MATCH output assigned to XBARB3_IN79 input. */ + kXBARB3_InputDec1PosMatch = 76|0x300U, /**< DEC1_POS_MATCH output assigned to XBARB3_IN76 input. */ + kXBARB3_InputDec2PosMatch = 77|0x300U, /**< DEC2_POS_MATCH output assigned to XBARB3_IN77 input. */ + kXBARB3_InputDec3PosMatch = 78|0x300U, /**< DEC3_POS_MATCH output assigned to XBARB3_IN78 input. */ + kXBARB3_InputDec4PosMatch = 79|0x300U, /**< DEC4_POS_MATCH output assigned to XBARB3_IN79 input. */ kXBARB3_InputRESERVED80 = 80|0x300U, /**< XBARB3_IN80 input is reserved. */ kXBARB3_InputRESERVED81 = 81|0x300U, /**< XBARB3_IN81 input is reserved. */ kXBARB3_InputDmaDone0 = 82|0x300U, /**< DMA_DONE0 output assigned to XBARB3_IN82 input. */ @@ -1042,10 +1044,10 @@ typedef enum _xbar_input_signal typedef enum _xbar_output_signal { - kXBARA1_OutputDmaChMuxReq30 = 0|0x100U, /**< XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */ - kXBARA1_OutputDmaChMuxReq31 = 1|0x100U, /**< XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */ - kXBARA1_OutputDmaChMuxReq94 = 2|0x100U, /**< XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */ - kXBARA1_OutputDmaChMuxReq95 = 3|0x100U, /**< XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */ + kXBARA1_OutputDmaChMuxReq81 = 0|0x100U, /**< XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ81 */ + kXBARA1_OutputDmaChMuxReq82 = 1|0x100U, /**< XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ82 */ + kXBARA1_OutputDmaChMuxReq83 = 2|0x100U, /**< XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ83 */ + kXBARA1_OutputDmaChMuxReq84 = 3|0x100U, /**< XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ84 */ kXBARA1_OutputIomuxXbarInout04 = 4|0x100U, /**< XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */ kXBARA1_OutputIomuxXbarInout05 = 5|0x100U, /**< XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */ kXBARA1_OutputIomuxXbarInout06 = 6|0x100U, /**< XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */ @@ -1095,10 +1097,10 @@ typedef enum _xbar_output_signal kXBARA1_OutputFlexpwm1Pwm1Exta = 50|0x100U, /**< XBARA1_OUT50 output assigned to FLEXPWM1_PWM1_EXTA */ kXBARA1_OutputFlexpwm1Pwm2Exta = 51|0x100U, /**< XBARA1_OUT51 output assigned to FLEXPWM1_PWM2_EXTA */ kXBARA1_OutputFlexpwm1Pwm3Exta = 52|0x100U, /**< XBARA1_OUT52 output assigned to FLEXPWM1_PWM3_EXTA */ - kXBARA1_OutputFlexpwm1ExtSync0 = 53|0x100U, /**< XBARA1_OUT53 output assigned to FLEXPWM1_EXT_SYNC0 */ - kXBARA1_OutputFlexpwm1ExtSync1 = 54|0x100U, /**< XBARA1_OUT54 output assigned to FLEXPWM1_EXT_SYNC1 */ - kXBARA1_OutputFlexpwm1ExtSync2 = 55|0x100U, /**< XBARA1_OUT55 output assigned to FLEXPWM1_EXT_SYNC2 */ - kXBARA1_OutputFlexpwm1ExtSync3 = 56|0x100U, /**< XBARA1_OUT56 output assigned to FLEXPWM1_EXT_SYNC3 */ + kXBARA1_OutputFlexpwm1Pwm0ExtSync = 53|0x100U, /**< XBARA1_OUT53 output assigned to FLEXPWM1_PWM0_EXT_SYNC */ + kXBARA1_OutputFlexpwm1Pwm1ExtSync = 54|0x100U, /**< XBARA1_OUT54 output assigned to FLEXPWM1_PWM1_EXT_SYNC */ + kXBARA1_OutputFlexpwm1Pwm2ExtSync = 55|0x100U, /**< XBARA1_OUT55 output assigned to FLEXPWM1_PWM2_EXT_SYNC */ + kXBARA1_OutputFlexpwm1Pwm3ExtSync = 56|0x100U, /**< XBARA1_OUT56 output assigned to FLEXPWM1_PWM3_EXT_SYNC */ kXBARA1_OutputFlexpwm1ExtClk = 57|0x100U, /**< XBARA1_OUT57 output assigned to FLEXPWM1_EXT_CLK */ kXBARA1_OutputFlexpwm1Fault0 = 58|0x100U, /**< XBARA1_OUT58 output assigned to FLEXPWM1_FAULT0 */ kXBARA1_OutputFlexpwm1Fault1 = 59|0x100U, /**< XBARA1_OUT59 output assigned to FLEXPWM1_FAULT1 */ @@ -1109,10 +1111,10 @@ typedef enum _xbar_output_signal kXBARA1_OutputFlexpwm2Pwm1Exta = 64|0x100U, /**< XBARA1_OUT64 output assigned to FLEXPWM2_PWM1_EXTA */ kXBARA1_OutputFlexpwm2Pwm2Exta = 65|0x100U, /**< XBARA1_OUT65 output assigned to FLEXPWM2_PWM2_EXTA */ kXBARA1_OutputFlexpwm2Pwm3Exta = 66|0x100U, /**< XBARA1_OUT66 output assigned to FLEXPWM2_PWM3_EXTA */ - kXBARA1_OutputFlexpwm2ExtSync0 = 67|0x100U, /**< XBARA1_OUT67 output assigned to FLEXPWM2_EXT_SYNC0 */ - kXBARA1_OutputFlexpwm2ExtSync1 = 68|0x100U, /**< XBARA1_OUT68 output assigned to FLEXPWM2_EXT_SYNC1 */ - kXBARA1_OutputFlexpwm2ExtSync2 = 69|0x100U, /**< XBARA1_OUT69 output assigned to FLEXPWM2_EXT_SYNC2 */ - kXBARA1_OutputFlexpwm2ExtSync3 = 70|0x100U, /**< XBARA1_OUT70 output assigned to FLEXPWM2_EXT_SYNC3 */ + kXBARA1_OutputFlexpwm2Pwm0ExtSync = 67|0x100U, /**< XBARA1_OUT67 output assigned to FLEXPWM2_PWM0_EXT_SYNC */ + kXBARA1_OutputFlexpwm2Pwm1ExtSync = 68|0x100U, /**< XBARA1_OUT68 output assigned to FLEXPWM2_PWM1_EXT_SYNC */ + kXBARA1_OutputFlexpwm2Pwm2ExtSync = 69|0x100U, /**< XBARA1_OUT69 output assigned to FLEXPWM2_PWM2_EXT_SYNC */ + kXBARA1_OutputFlexpwm2Pwm3ExtSync = 70|0x100U, /**< XBARA1_OUT70 output assigned to FLEXPWM2_PWM3_EXT_SYNC */ kXBARA1_OutputFlexpwm2ExtClk = 71|0x100U, /**< XBARA1_OUT71 output assigned to FLEXPWM2_EXT_CLK */ kXBARA1_OutputFlexpwm2Fault0 = 72|0x100U, /**< XBARA1_OUT72 output assigned to FLEXPWM2_FAULT0 */ kXBARA1_OutputFlexpwm2Fault1 = 73|0x100U, /**< XBARA1_OUT73 output assigned to FLEXPWM2_FAULT1 */ @@ -1122,17 +1124,17 @@ typedef enum _xbar_output_signal kXBARA1_OutputFlexpwm34Pwm2Exta = 77|0x100U, /**< XBARA1_OUT77 output assigned to FLEXPWM3_4_PWM2_EXTA */ kXBARA1_OutputFlexpwm34Pwm3Exta = 78|0x100U, /**< XBARA1_OUT78 output assigned to FLEXPWM3_4_PWM3_EXTA */ kXBARA1_OutputFlexpwm34ExtClk = 79|0x100U, /**< XBARA1_OUT79 output assigned to FLEXPWM3_4_EXT_CLK */ - kXBARA1_OutputFlexpwm3ExtSync0 = 80|0x100U, /**< XBARA1_OUT80 output assigned to FLEXPWM3_EXT_SYNC0 */ - kXBARA1_OutputFlexpwm3ExtSync1 = 81|0x100U, /**< XBARA1_OUT81 output assigned to FLEXPWM3_EXT_SYNC1 */ - kXBARA1_OutputFlexpwm3ExtSync2 = 82|0x100U, /**< XBARA1_OUT82 output assigned to FLEXPWM3_EXT_SYNC2 */ - kXBARA1_OutputFlexpwm3ExtSync3 = 83|0x100U, /**< XBARA1_OUT83 output assigned to FLEXPWM3_EXT_SYNC3 */ + kXBARA1_OutputFlexpwm3Pwm0ExtSync = 80|0x100U, /**< XBARA1_OUT80 output assigned to FLEXPWM3_PWM0_EXT_SYNC */ + kXBARA1_OutputFlexpwm3Pwm1ExtSync = 81|0x100U, /**< XBARA1_OUT81 output assigned to FLEXPWM3_PWM1_EXT_SYNC */ + kXBARA1_OutputFlexpwm3Pwm2ExtSync = 82|0x100U, /**< XBARA1_OUT82 output assigned to FLEXPWM3_PWM2_EXT_SYNC */ + kXBARA1_OutputFlexpwm3Pwm3ExtSync = 83|0x100U, /**< XBARA1_OUT83 output assigned to FLEXPWM3_PWM3_EXT_SYNC */ kXBARA1_OutputFlexpwm3Fault0 = 84|0x100U, /**< XBARA1_OUT84 output assigned to FLEXPWM3_FAULT0 */ kXBARA1_OutputFlexpwm3Fault1 = 85|0x100U, /**< XBARA1_OUT85 output assigned to FLEXPWM3_FAULT1 */ kXBARA1_OutputFlexpwm3ExtForce = 86|0x100U, /**< XBARA1_OUT86 output assigned to FLEXPWM3_EXT_FORCE */ - kXBARA1_OutputFlexpwm4ExtSync0 = 87|0x100U, /**< XBARA1_OUT87 output assigned to FLEXPWM4_EXT_SYNC0 */ - kXBARA1_OutputFlexpwm4ExtSync1 = 88|0x100U, /**< XBARA1_OUT88 output assigned to FLEXPWM4_EXT_SYNC1 */ - kXBARA1_OutputFlexpwm4ExtSync2 = 89|0x100U, /**< XBARA1_OUT89 output assigned to FLEXPWM4_EXT_SYNC2 */ - kXBARA1_OutputFlexpwm4ExtSync3 = 90|0x100U, /**< XBARA1_OUT90 output assigned to FLEXPWM4_EXT_SYNC3 */ + kXBARA1_OutputFlexpwm4Pwm0ExtSync = 87|0x100U, /**< XBARA1_OUT87 output assigned to FLEXPWM4_PWM0_EXT_SYNC */ + kXBARA1_OutputFlexpwm4Pwm1ExtSync = 88|0x100U, /**< XBARA1_OUT88 output assigned to FLEXPWM4_PWM1_EXT_SYNC */ + kXBARA1_OutputFlexpwm4Pwm2ExtSync = 89|0x100U, /**< XBARA1_OUT89 output assigned to FLEXPWM4_PWM2_EXT_SYNC */ + kXBARA1_OutputFlexpwm4Pwm3ExtSync = 90|0x100U, /**< XBARA1_OUT90 output assigned to FLEXPWM4_PWM3_EXT_SYNC */ kXBARA1_OutputFlexpwm4Fault0 = 91|0x100U, /**< XBARA1_OUT91 output assigned to FLEXPWM4_FAULT0 */ kXBARA1_OutputFlexpwm4Fault1 = 92|0x100U, /**< XBARA1_OUT92 output assigned to FLEXPWM4_FAULT1 */ kXBARA1_OutputFlexpwm4ExtForce = 93|0x100U, /**< XBARA1_OUT93 output assigned to FLEXPWM4_EXT_FORCE */ @@ -1150,61 +1152,61 @@ typedef enum _xbar_output_signal kXBARA1_OutputRESERVED105 = 105|0x100U, /**< XBARA1_OUT105 output is reserved. */ kXBARA1_OutputRESERVED106 = 106|0x100U, /**< XBARA1_OUT106 output is reserved. */ kXBARA1_OutputRESERVED107 = 107|0x100U, /**< XBARA1_OUT107 output is reserved. */ - kXBARA1_OutputEnc1PhaseAInput = 108|0x100U, /**< XBARA1_OUT108 output assigned to ENC1_PHASE_A_INPUT */ - kXBARA1_OutputEnc1PhaseBInput = 109|0x100U, /**< XBARA1_OUT109 output assigned to ENC1_PHASE_B_INPUT */ - kXBARA1_OutputEnc1Index = 110|0x100U, /**< XBARA1_OUT110 output assigned to ENC1_INDEX */ - kXBARA1_OutputEnc1Home = 111|0x100U, /**< XBARA1_OUT111 output assigned to ENC1_HOME */ - kXBARA1_OutputEnc1Trigger = 112|0x100U, /**< XBARA1_OUT112 output assigned to ENC1_TRIGGER */ - kXBARA1_OutputEnc2PhaseAInput = 113|0x100U, /**< XBARA1_OUT113 output assigned to ENC2_PHASE_A_INPUT */ - kXBARA1_OutputEnc2PhaseBInput = 114|0x100U, /**< XBARA1_OUT114 output assigned to ENC2_PHASE_B_INPUT */ - kXBARA1_OutputEnc2Index = 115|0x100U, /**< XBARA1_OUT115 output assigned to ENC2_INDEX */ - kXBARA1_OutputEnc2Home = 116|0x100U, /**< XBARA1_OUT116 output assigned to ENC2_HOME */ - kXBARA1_OutputEnc2Trigger = 117|0x100U, /**< XBARA1_OUT117 output assigned to ENC2_TRIGGER */ - kXBARA1_OutputEnc3PhaseAInput = 118|0x100U, /**< XBARA1_OUT118 output assigned to ENC3_PHASE_A_INPUT */ - kXBARA1_OutputEnc3PhaseBInput = 119|0x100U, /**< XBARA1_OUT119 output assigned to ENC3_PHASE_B_INPUT */ - kXBARA1_OutputEnc3Index = 120|0x100U, /**< XBARA1_OUT120 output assigned to ENC3_INDEX */ - kXBARA1_OutputEnc3Home = 121|0x100U, /**< XBARA1_OUT121 output assigned to ENC3_HOME */ - kXBARA1_OutputEnc3Trigger = 122|0x100U, /**< XBARA1_OUT122 output assigned to ENC3_TRIGGER */ - kXBARA1_OutputEnc4PhaseAInput = 123|0x100U, /**< XBARA1_OUT123 output assigned to ENC4_PHASE_A_INPUT */ - kXBARA1_OutputEnc4PhaseBInput = 124|0x100U, /**< XBARA1_OUT124 output assigned to ENC4_PHASE_B_INPUT */ - kXBARA1_OutputEnc4Index = 125|0x100U, /**< XBARA1_OUT125 output assigned to ENC4_INDEX */ - kXBARA1_OutputEnc4Home = 126|0x100U, /**< XBARA1_OUT126 output assigned to ENC4_HOME */ - kXBARA1_OutputEnc4Trigger = 127|0x100U, /**< XBARA1_OUT127 output assigned to ENC4_TRIGGER */ + kXBARA1_OutputDec1Phasea = 108|0x100U, /**< XBARA1_OUT108 output assigned to DEC1_PHASEA */ + kXBARA1_OutputDec1Phaseb = 109|0x100U, /**< XBARA1_OUT109 output assigned to DEC1_PHASEB */ + kXBARA1_OutputDec1Index = 110|0x100U, /**< XBARA1_OUT110 output assigned to DEC1_INDEX */ + kXBARA1_OutputDec1Home = 111|0x100U, /**< XBARA1_OUT111 output assigned to DEC1_HOME */ + kXBARA1_OutputDec1Trigger = 112|0x100U, /**< XBARA1_OUT112 output assigned to DEC1_TRIGGER */ + kXBARA1_OutputDec2Phasea = 113|0x100U, /**< XBARA1_OUT113 output assigned to DEC2_PHASEA */ + kXBARA1_OutputDec2Phaseb = 114|0x100U, /**< XBARA1_OUT114 output assigned to DEC2_PHASEB */ + kXBARA1_OutputDec2Index = 115|0x100U, /**< XBARA1_OUT115 output assigned to DEC2_INDEX */ + kXBARA1_OutputDec2Home = 116|0x100U, /**< XBARA1_OUT116 output assigned to DEC2_HOME */ + kXBARA1_OutputDec2Trigger = 117|0x100U, /**< XBARA1_OUT117 output assigned to DEC2_TRIGGER */ + kXBARA1_OutputDec3Phasea = 118|0x100U, /**< XBARA1_OUT118 output assigned to DEC3_PHASEA */ + kXBARA1_OutputDec3Phaseb = 119|0x100U, /**< XBARA1_OUT119 output assigned to DEC3_PHASEB */ + kXBARA1_OutputDec3Index = 120|0x100U, /**< XBARA1_OUT120 output assigned to DEC3_INDEX */ + kXBARA1_OutputDec3Home = 121|0x100U, /**< XBARA1_OUT121 output assigned to DEC3_HOME */ + kXBARA1_OutputDec3Trigger = 122|0x100U, /**< XBARA1_OUT122 output assigned to DEC3_TRIGGER */ + kXBARA1_OutputDec4Phasea = 123|0x100U, /**< XBARA1_OUT123 output assigned to DEC4_PHASEA */ + kXBARA1_OutputDec4Phaseb = 124|0x100U, /**< XBARA1_OUT124 output assigned to DEC4_PHASEB */ + kXBARA1_OutputDec4Index = 125|0x100U, /**< XBARA1_OUT125 output assigned to DEC4_INDEX */ + kXBARA1_OutputDec4Home = 126|0x100U, /**< XBARA1_OUT126 output assigned to DEC4_HOME */ + kXBARA1_OutputDec4Trigger = 127|0x100U, /**< XBARA1_OUT127 output assigned to DEC4_TRIGGER */ kXBARA1_OutputRESERVED128 = 128|0x100U, /**< XBARA1_OUT128 output is reserved. */ kXBARA1_OutputRESERVED129 = 129|0x100U, /**< XBARA1_OUT129 output is reserved. */ kXBARA1_OutputRESERVED130 = 130|0x100U, /**< XBARA1_OUT130 output is reserved. */ kXBARA1_OutputRESERVED131 = 131|0x100U, /**< XBARA1_OUT131 output is reserved. */ - kXBARA1_OutputRESERVED132 = 132|0x100U, /**< XBARA1_OUT132 output is reserved. */ - kXBARA1_OutputRESERVED133 = 133|0x100U, /**< XBARA1_OUT133 output is reserved. */ + kXBARA1_OutputCan1 = 132|0x100U, /**< XBARA1_OUT132 output assigned to CAN1 */ + kXBARA1_OutputCan2 = 133|0x100U, /**< XBARA1_OUT133 output assigned to CAN2 */ kXBARA1_OutputRESERVED134 = 134|0x100U, /**< XBARA1_OUT134 output is reserved. */ kXBARA1_OutputRESERVED135 = 135|0x100U, /**< XBARA1_OUT135 output is reserved. */ kXBARA1_OutputRESERVED136 = 136|0x100U, /**< XBARA1_OUT136 output is reserved. */ kXBARA1_OutputRESERVED137 = 137|0x100U, /**< XBARA1_OUT137 output is reserved. */ - kXBARA1_OutputRESERVED138 = 138|0x100U, /**< XBARA1_OUT138 output is reserved. */ - kXBARA1_OutputRESERVED139 = 139|0x100U, /**< XBARA1_OUT139 output is reserved. */ - kXBARA1_OutputRESERVED140 = 140|0x100U, /**< XBARA1_OUT140 output is reserved. */ - kXBARA1_OutputRESERVED141 = 141|0x100U, /**< XBARA1_OUT141 output is reserved. */ - kXBARA1_OutputRESERVED142 = 142|0x100U, /**< XBARA1_OUT142 output is reserved. */ - kXBARA1_OutputRESERVED143 = 143|0x100U, /**< XBARA1_OUT143 output is reserved. */ - kXBARA1_OutputRESERVED144 = 144|0x100U, /**< XBARA1_OUT144 output is reserved. */ - kXBARA1_OutputRESERVED145 = 145|0x100U, /**< XBARA1_OUT145 output is reserved. */ - kXBARA1_OutputRESERVED146 = 146|0x100U, /**< XBARA1_OUT146 output is reserved. */ - kXBARA1_OutputRESERVED147 = 147|0x100U, /**< XBARA1_OUT147 output is reserved. */ - kXBARA1_OutputRESERVED148 = 148|0x100U, /**< XBARA1_OUT148 output is reserved. */ - kXBARA1_OutputRESERVED149 = 149|0x100U, /**< XBARA1_OUT149 output is reserved. */ - kXBARA1_OutputRESERVED150 = 150|0x100U, /**< XBARA1_OUT150 output is reserved. */ - kXBARA1_OutputRESERVED151 = 151|0x100U, /**< XBARA1_OUT151 output is reserved. */ - kXBARA1_OutputRESERVED152 = 152|0x100U, /**< XBARA1_OUT152 output is reserved. */ - kXBARA1_OutputRESERVED153 = 153|0x100U, /**< XBARA1_OUT153 output is reserved. */ + kXBARA1_OutputQtimer1Timer0 = 138|0x100U, /**< XBARA1_OUT138 output assigned to QTIMER1_TIMER0 */ + kXBARA1_OutputQtimer1Timer1 = 139|0x100U, /**< XBARA1_OUT139 output assigned to QTIMER1_TIMER1 */ + kXBARA1_OutputQtimer1Timer2 = 140|0x100U, /**< XBARA1_OUT140 output assigned to QTIMER1_TIMER2 */ + kXBARA1_OutputQtimer1Timer3 = 141|0x100U, /**< XBARA1_OUT141 output assigned to QTIMER1_TIMER3 */ + kXBARA1_OutputQtimer2Timer0 = 142|0x100U, /**< XBARA1_OUT142 output assigned to QTIMER2_TIMER0 */ + kXBARA1_OutputQtimer2Timer1 = 143|0x100U, /**< XBARA1_OUT143 output assigned to QTIMER2_TIMER1 */ + kXBARA1_OutputQtimer2Timer2 = 144|0x100U, /**< XBARA1_OUT144 output assigned to QTIMER2_TIMER2 */ + kXBARA1_OutputQtimer2Timer3 = 145|0x100U, /**< XBARA1_OUT145 output assigned to QTIMER2_TIMER3 */ + kXBARA1_OutputQtimer3Timer0 = 146|0x100U, /**< XBARA1_OUT146 output assigned to QTIMER3_TIMER0 */ + kXBARA1_OutputQtimer3Timer1 = 147|0x100U, /**< XBARA1_OUT147 output assigned to QTIMER3_TIMER1 */ + kXBARA1_OutputQtimer3Timer2 = 148|0x100U, /**< XBARA1_OUT148 output assigned to QTIMER3_TIMER2 */ + kXBARA1_OutputQtimer3Timer3 = 149|0x100U, /**< XBARA1_OUT149 output assigned to QTIMER3_TIMER3 */ + kXBARA1_OutputQtimer4Timer0 = 150|0x100U, /**< XBARA1_OUT150 output assigned to QTIMER4_TIMER0 */ + kXBARA1_OutputQtimer4Timer1 = 151|0x100U, /**< XBARA1_OUT151 output assigned to QTIMER4_TIMER1 */ + kXBARA1_OutputQtimer4Timer2 = 152|0x100U, /**< XBARA1_OUT152 output assigned to QTIMER4_TIMER2 */ + kXBARA1_OutputQtimer4Timer3 = 153|0x100U, /**< XBARA1_OUT153 output assigned to QTIMER4_TIMER3 */ kXBARA1_OutputEwmEwmIn = 154|0x100U, /**< XBARA1_OUT154 output assigned to EWM_EWM_IN */ - kXBARA1_OutputAdcEtcXbar0Trig0 = 155|0x100U, /**< XBARA1_OUT155 output assigned to ADC_ETC_XBAR0_TRIG0 */ - kXBARA1_OutputAdcEtcXbar0Trig1 = 156|0x100U, /**< XBARA1_OUT156 output assigned to ADC_ETC_XBAR0_TRIG1 */ - kXBARA1_OutputAdcEtcXbar0Trig2 = 157|0x100U, /**< XBARA1_OUT157 output assigned to ADC_ETC_XBAR0_TRIG2 */ - kXBARA1_OutputAdcEtcXbar0Trig3 = 158|0x100U, /**< XBARA1_OUT158 output assigned to ADC_ETC_XBAR0_TRIG3 */ - kXBARA1_OutputAdcEtcXbar1Trig0 = 159|0x100U, /**< XBARA1_OUT159 output assigned to ADC_ETC_XBAR1_TRIG0 */ - kXBARA1_OutputAdcEtcXbar1Trig1 = 160|0x100U, /**< XBARA1_OUT160 output assigned to ADC_ETC_XBAR1_TRIG1 */ - kXBARA1_OutputAdcEtcXbar1Trig2 = 161|0x100U, /**< XBARA1_OUT161 output assigned to ADC_ETC_XBAR1_TRIG2 */ - kXBARA1_OutputAdcEtcXbar1Trig3 = 162|0x100U, /**< XBARA1_OUT162 output assigned to ADC_ETC_XBAR1_TRIG3 */ + kXBARA1_OutputAdcEtc0Coco0 = 155|0x100U, /**< XBARA1_OUT155 output assigned to ADC_ETC0_COCO0 */ + kXBARA1_OutputAdcEtc0Coco1 = 156|0x100U, /**< XBARA1_OUT156 output assigned to ADC_ETC0_COCO1 */ + kXBARA1_OutputAdcEtc0Coco2 = 157|0x100U, /**< XBARA1_OUT157 output assigned to ADC_ETC0_COCO2 */ + kXBARA1_OutputAdcEtc0Coco3 = 158|0x100U, /**< XBARA1_OUT158 output assigned to ADC_ETC0_COCO3 */ + kXBARA1_OutputAdcEtc1Coco0 = 159|0x100U, /**< XBARA1_OUT159 output assigned to ADC_ETC1_COCO0 */ + kXBARA1_OutputAdcEtc1Coco1 = 160|0x100U, /**< XBARA1_OUT160 output assigned to ADC_ETC1_COCO1 */ + kXBARA1_OutputAdcEtc1Coco2 = 161|0x100U, /**< XBARA1_OUT161 output assigned to ADC_ETC1_COCO2 */ + kXBARA1_OutputAdcEtc1Coco3 = 162|0x100U, /**< XBARA1_OUT162 output assigned to ADC_ETC1_COCO3 */ kXBARA1_OutputRESERVED163 = 163|0x100U, /**< XBARA1_OUT163 output is reserved. */ kXBARA1_OutputRESERVED164 = 164|0x100U, /**< XBARA1_OUT164 output is reserved. */ kXBARA1_OutputRESERVED165 = 165|0x100U, /**< XBARA1_OUT165 output is reserved. */ @@ -1213,10 +1215,10 @@ typedef enum _xbar_output_signal kXBARA1_OutputRESERVED168 = 168|0x100U, /**< XBARA1_OUT168 output is reserved. */ kXBARA1_OutputRESERVED169 = 169|0x100U, /**< XBARA1_OUT169 output is reserved. */ kXBARA1_OutputRESERVED170 = 170|0x100U, /**< XBARA1_OUT170 output is reserved. */ - kXBARA1_OutputFlexio1TriggerIn0 = 171|0x100U, /**< XBARA1_OUT171 output assigned to FLEXIO1_TRIGGER_IN0 */ - kXBARA1_OutputFlexio1TriggerIn1 = 172|0x100U, /**< XBARA1_OUT172 output assigned to FLEXIO1_TRIGGER_IN1 */ - kXBARA1_OutputFlexio2TriggerIn0 = 173|0x100U, /**< XBARA1_OUT173 output assigned to FLEXIO2_TRIGGER_IN0 */ - kXBARA1_OutputFlexio2TriggerIn1 = 174|0x100U, /**< XBARA1_OUT174 output assigned to FLEXIO2_TRIGGER_IN1 */ + kXBARA1_OutputFlexio1TrigIn0 = 171|0x100U, /**< XBARA1_OUT171 output assigned to FLEXIO1_TRIG_IN0 */ + kXBARA1_OutputFlexio1TrigIn1 = 172|0x100U, /**< XBARA1_OUT172 output assigned to FLEXIO1_TRIG_IN1 */ + kXBARA1_OutputFlexio2TrigIn0 = 173|0x100U, /**< XBARA1_OUT173 output assigned to FLEXIO2_TRIG_IN0 */ + kXBARA1_OutputFlexio2TrigIn1 = 174|0x100U, /**< XBARA1_OUT174 output assigned to FLEXIO2_TRIG_IN1 */ kXBARB2_OutputAoi1In00 = 0|0x200U, /**< XBARB2_OUT0 output assigned to AOI1_IN00 */ kXBARB2_OutputAoi1In01 = 1|0x200U, /**< XBARB2_OUT1 output assigned to AOI1_IN01 */ kXBARB2_OutputAoi1In02 = 2|0x200U, /**< XBARB2_OUT2 output assigned to AOI1_IN02 */ @@ -1382,13 +1384,13 @@ typedef enum _ssarc_power_domain_name } ssarc_power_domain_name_t; /* - * @brief The name of restore resource domain. + * @brief The name of cpu domain. */ -typedef enum _ssarc_restore_resource_domain_name +typedef enum _ssarc_cpu_domain_name { kSSARC_CM7Core = 0U, /**< CM7 Core domain. */ kSSARC_CM4Core = 1U, /**< CM4 Core domain. */ -} ssarc_restore_resource_domain_name_t; +} ssarc_cpu_domain_name_t; /* @} */ @@ -1816,8 +1818,8 @@ typedef enum _dma_request_source kDmaRequestMuxLPUART12Rx = 31|0x100U, /**< LPUART12 Receive */ kDmaRequestMuxCSI = 32|0x100U, /**< CSI */ kDmaRequestMuxPxp = 33|0x100U, /**< PXP */ - kDmaRequestMuxLCDIF1 = 34|0x100U, /**< LCDIF1 */ - kDmaRequestMuxLCDIF2 = 35|0x100U, /**< LCDIF2 */ + kDmaRequestMuxeLCDIF = 34|0x100U, /**< eLCDIF */ + kDmaRequestMuxLCDIFv2 = 35|0x100U, /**< LCDIFv2 */ kDmaRequestMuxLPSPI1Rx = 36|0x100U, /**< LPSPI1 Receive */ kDmaRequestMuxLPSPI1Tx = 37|0x100U, /**< LPSPI1 Transmit */ kDmaRequestMuxLPSPI2Rx = 38|0x100U, /**< LPSPI2 Receive */ @@ -2494,26 +2496,26 @@ typedef struct { __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ uint8_t RESERVED_0[8]; - __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */ - __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */ + __IO uint32_t CTRL; /**< LPADC Control Register, offset: 0x10 */ + __IO uint32_t STAT; /**< LPADC Status Register, offset: 0x14 */ __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */ __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */ - __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */ - __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */ + __IO uint32_t CFG; /**< LPADC Configuration Register, offset: 0x20 */ + __IO uint32_t PAUSE; /**< LPADC Pause Register, offset: 0x24 */ uint8_t RESERVED_1[8]; - __IO uint32_t FCTRL; /**< ADC FIFO Control Register, offset: 0x30 */ + __IO uint32_t FCTRL; /**< LPADC FIFO Control Register, offset: 0x30 */ __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */ uint8_t RESERVED_2[136]; __IO uint32_t TCTRL[8]; /**< Trigger Control Register, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_3[32]; struct { /* offset: 0x100, array step: 0x8 */ - __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ - __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */ + __IO uint32_t CMDL; /**< LPADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */ + __IO uint32_t CMDH; /**< LPADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */ } CMD[15]; uint8_t RESERVED_4[136]; __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */ uint8_t RESERVED_5[240]; - __I uint32_t RESFIFO; /**< ADC Data Result FIFO Register, offset: 0x300 */ + __I uint32_t RESFIFO; /**< LPADC Data Result FIFO Register, offset: 0x300 */ } ADC_Type; /* ---------------------------------------------------------------------------- @@ -2527,6 +2529,7 @@ typedef struct { /*! @name VERID - Version ID Register */ /*! @{ */ + #define ADC_VERID_RES_MASK (0x1U) #define ADC_VERID_RES_SHIFT (0U) /*! RES - Resolution @@ -2534,6 +2537,7 @@ typedef struct { * 0b1..Up to 16-bit differential/15-bit single ended resolution supported. */ #define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK) + #define ADC_VERID_DIFFEN_MASK (0x2U) #define ADC_VERID_DIFFEN_SHIFT (1U) /*! DIFFEN - Differential Supported @@ -2541,13 +2545,15 @@ typedef struct { * 0b1..Differential operation supported. CMDLa[DIFF] and CMDLa[ABSEL] control fields implemented. */ #define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK) + #define ADC_VERID_MVI_MASK (0x8U) #define ADC_VERID_MVI_SHIFT (3U) /*! MVI - Multi Vref Implemented - * 0b0..Single voltage reference high (VREFH) input supported. - * 0b1..Multiple voltage reference high (VREFH) inputs supported. + * 0b0..Single voltage reference input supported. + * 0b1..Multiple voltage reference inputs supported. */ #define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK) + #define ADC_VERID_CSW_MASK (0x70U) #define ADC_VERID_CSW_SHIFT (4U) /*! CSW - Channel Scale Width @@ -2556,6 +2562,7 @@ typedef struct { * 0b110..Channel scaling supported. 6-bit CSCALE control field. */ #define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK) + #define ADC_VERID_VR1RNGI_MASK (0x100U) #define ADC_VERID_VR1RNGI_SHIFT (8U) /*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented @@ -2563,13 +2570,15 @@ typedef struct { * 0b1..Range control required. CFG[VREF1RNG] is implemented. */ #define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK) + #define ADC_VERID_IADCKI_MASK (0x200U) #define ADC_VERID_IADCKI_SHIFT (9U) -/*! IADCKI - Internal ADC Clock implemented +/*! IADCKI - Internal LPADC Clock implemented * 0b0..Internal clock source not implemented. * 0b1..Internal clock source (and CFG[ADCKEN]) implemented. */ #define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK) + #define ADC_VERID_CALOFSI_MASK (0x400U) #define ADC_VERID_CALOFSI_SHIFT (10U) /*! CALOFSI - Calibration Offset Function Implemented @@ -2577,11 +2586,13 @@ typedef struct { * 0b1..Offset calibration and offset trimming implemented. */ #define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK) + #define ADC_VERID_MINOR_MASK (0xFF0000U) #define ADC_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK) + #define ADC_VERID_MAJOR_MASK (0xFF000000U) #define ADC_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number @@ -2591,60 +2602,73 @@ typedef struct { /*! @name PARAM - Parameter Register */ /*! @{ */ + #define ADC_PARAM_TRIG_NUM_MASK (0xFFU) #define ADC_PARAM_TRIG_NUM_SHIFT (0U) /*! TRIG_NUM - Trigger Number + * 0b00001000..8 hardware triggers implemented */ #define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK) + #define ADC_PARAM_FIFOSIZE_MASK (0xFF00U) #define ADC_PARAM_FIFOSIZE_SHIFT (8U) /*! FIFOSIZE - Result FIFO Depth - * 0b00000001..Result FIFO depth = 1 dataword. - * 0b00000100..Result FIFO depth = 4 datawords. - * 0b00001000..Result FIFO depth = 8 datawords. * 0b00010000..Result FIFO depth = 16 datawords. - * 0b00100000..Result FIFO depth = 32 datawords. - * 0b01000000..Result FIFO depth = 64 datawords. */ #define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK) + #define ADC_PARAM_CV_NUM_MASK (0xFF0000U) #define ADC_PARAM_CV_NUM_SHIFT (16U) /*! CV_NUM - Compare Value Number + * 0b00000100..4 compare value registers implemented */ #define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK) + #define ADC_PARAM_CMD_NUM_MASK (0xFF000000U) #define ADC_PARAM_CMD_NUM_SHIFT (24U) /*! CMD_NUM - Command Buffer Number + * 0b00001111..15 command buffers implemented */ #define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK) /*! @} */ -/*! @name CTRL - ADC Control Register */ +/*! @name CTRL - LPADC Control Register */ /*! @{ */ + #define ADC_CTRL_ADCEN_MASK (0x1U) #define ADC_CTRL_ADCEN_SHIFT (0U) -/*! ADCEN - ADC Enable - * 0b0..ADC is disabled. - * 0b1..ADC is enabled. +/*! ADCEN - LPADC Enable + * 0b0..LPADC is disabled. + * 0b1..LPADC is enabled. */ #define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK) + #define ADC_CTRL_RST_MASK (0x2U) #define ADC_CTRL_RST_SHIFT (1U) /*! RST - Software Reset - * 0b0..ADC logic is not reset. - * 0b1..ADC logic is reset. + * 0b0..LPADC logic is not reset. + * 0b1..LPADC logic is reset. */ #define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK) + #define ADC_CTRL_DOZEN_MASK (0x4U) #define ADC_CTRL_DOZEN_SHIFT (2U) /*! DOZEN - Doze Enable - * 0b0..ADC is enabled in Doze mode. - * 0b1..ADC is disabled in Doze mode. + * 0b0..LPADC is enabled in Doze mode. + * 0b1..LPADC is disabled in Doze mode. */ #define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK) + #define ADC_CTRL_TRIG_SRC_MASK (0x18U) #define ADC_CTRL_TRIG_SRC_SHIFT (3U) +/*! TRIG_SRC - Hardware trigger source selection + * 0b00..ADC_ETC hw trigger , and HW trigger are enabled + * 0b01..ADC_ETC hw trigger is enabled + * 0b10..HW trigger is enabled + * 0b11..Reserved + */ #define ADC_CTRL_TRIG_SRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TRIG_SRC_SHIFT)) & ADC_CTRL_TRIG_SRC_MASK) + #define ADC_CTRL_RSTFIFO_MASK (0x100U) #define ADC_CTRL_RSTFIFO_SHIFT (8U) /*! RSTFIFO - Reset FIFO @@ -2654,8 +2678,9 @@ typedef struct { #define ADC_CTRL_RSTFIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO_SHIFT)) & ADC_CTRL_RSTFIFO_MASK) /*! @} */ -/*! @name STAT - ADC Status Register */ +/*! @name STAT - LPADC Status Register */ /*! @{ */ + #define ADC_STAT_RDY_MASK (0x1U) #define ADC_STAT_RDY_SHIFT (0U) /*! RDY - Result FIFO Ready Flag @@ -2663,6 +2688,7 @@ typedef struct { * 0b1..Result FIFO holding data above watermark level. */ #define ADC_STAT_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY_SHIFT)) & ADC_STAT_RDY_MASK) + #define ADC_STAT_FOF_MASK (0x2U) #define ADC_STAT_FOF_SHIFT (1U) /*! FOF - Result FIFO Overflow Flag @@ -2670,13 +2696,15 @@ typedef struct { * 0b1..At least one result FIFO overflow has occurred since the last time the flag was cleared. */ #define ADC_STAT_FOF(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF_SHIFT)) & ADC_STAT_FOF_MASK) + #define ADC_STAT_ADC_ACTIVE_MASK (0x100U) #define ADC_STAT_ADC_ACTIVE_SHIFT (8U) /*! ADC_ACTIVE - ADC Active - * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed. - * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger. + * 0b0..The LPADC is IDLE. There are no pending triggers to service and no active commands are being processed. + * 0b1..The LPADC is processing a conversion, running through the power up delay, or servicing a trigger. */ #define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK) + #define ADC_STAT_TRGACT_MASK (0x70000U) #define ADC_STAT_TRGACT_SHIFT (16U) /*! TRGACT - Trigger Active @@ -2686,6 +2714,7 @@ typedef struct { * 0b011-0b111..Command (sequence) from the associated Trigger number is currently being executed. */ #define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK) + #define ADC_STAT_CMDACT_MASK (0xF000000U) #define ADC_STAT_CMDACT_SHIFT (24U) /*! CMDACT - Command Active @@ -2699,6 +2728,7 @@ typedef struct { /*! @name IE - Interrupt Enable Register */ /*! @{ */ + #define ADC_IE_FWMIE_MASK (0x1U) #define ADC_IE_FWMIE_SHIFT (0U) /*! FWMIE - FIFO Watermark Interrupt Enable @@ -2706,6 +2736,7 @@ typedef struct { * 0b1..FIFO watermark interrupts are enabled. */ #define ADC_IE_FWMIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE_SHIFT)) & ADC_IE_FWMIE_MASK) + #define ADC_IE_FOFIE_MASK (0x2U) #define ADC_IE_FOFIE_SHIFT (1U) /*! FOFIE - Result FIFO Overflow Interrupt Enable @@ -2717,6 +2748,7 @@ typedef struct { /*! @name DE - DMA Enable Register */ /*! @{ */ + #define ADC_DE_FWMDE_MASK (0x1U) #define ADC_DE_FWMDE_SHIFT (0U) /*! FWMDE - FIFO Watermark DMA Enable @@ -2726,11 +2758,12 @@ typedef struct { #define ADC_DE_FWMDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE_SHIFT)) & ADC_DE_FWMDE_MASK) /*! @} */ -/*! @name CFG - ADC Configuration Register */ +/*! @name CFG - LPADC Configuration Register */ /*! @{ */ + #define ADC_CFG_TPRICTRL_MASK (0x1U) #define ADC_CFG_TPRICTRL_SHIFT (0U) -/*! TPRICTRL - ADC trigger priority control +/*! TPRICTRL - LPADC trigger priority control * 0b0..If a higher priority trigger is detected during command processing, the current conversion is aborted and * the new command specified by the trigger is started. * 0b1..If a higher priority trigger is received during command processing, the current conversion is completed @@ -2739,6 +2772,7 @@ typedef struct { * conversion. */ #define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK) + #define ADC_CFG_PWRSEL_MASK (0x30U) #define ADC_CFG_PWRSEL_SHIFT (4U) /*! PWRSEL - Power Configuration Select @@ -2748,6 +2782,7 @@ typedef struct { * 0b11..Level 4 (Highest power setting) */ #define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK) + #define ADC_CFG_REFSEL_MASK (0xC0U) #define ADC_CFG_REFSEL_SHIFT (6U) /*! REFSEL - Voltage Reference Selection @@ -2757,29 +2792,33 @@ typedef struct { * 0b11..Reserved */ #define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK) + #define ADC_CFG_PUDLY_MASK (0xFF0000U) #define ADC_CFG_PUDLY_SHIFT (16U) /*! PUDLY - Power Up Delay */ #define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK) + #define ADC_CFG_PWREN_MASK (0x10000000U) #define ADC_CFG_PWREN_SHIFT (28U) -/*! PWREN - ADC Analog Pre-Enable - * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. - * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost - * of higher DC current consumption). When PWREN is set, the power up delay is enforced such that any +/*! PWREN - LPADC Analog Pre-Enable + * 0b0..LPADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays. + * 0b1..LPADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the + * cost of higher DC current consumption). When PWREN is set, the power up delay is enforced such that any * detected trigger does not begin ADC operation until the power up delay time has passed. */ #define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK) /*! @} */ -/*! @name PAUSE - ADC Pause Register */ +/*! @name PAUSE - LPADC Pause Register */ /*! @{ */ + #define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU) #define ADC_PAUSE_PAUSEDLY_SHIFT (0U) /*! PAUSEDLY - Pause Delay */ #define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK) + #define ADC_PAUSE_PAUSEEN_MASK (0x80000000U) #define ADC_PAUSE_PAUSEEN_SHIFT (31U) /*! PAUSEEN - PAUSE Option Enable @@ -2789,22 +2828,47 @@ typedef struct { #define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK) /*! @} */ -/*! @name FCTRL - ADC FIFO Control Register */ +/*! @name FCTRL - LPADC FIFO Control Register */ /*! @{ */ + #define ADC_FCTRL_FCOUNT_MASK (0x1FU) #define ADC_FCTRL_FCOUNT_SHIFT (0U) /*! FCOUNT - Result FIFO counter + * 0b00000..No data stored in FIFO + * 0b00001..1 dataword stored in FIFO + * 0b00010..2 datawords stored in FIFO + * 0b00100..4 datawords stored in FIFO + * 0b01000..8 datawords stored in FIFO + * 0b10000..16 datawords stored in FIFO */ #define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK) + #define ADC_FCTRL_FWMARK_MASK (0xF0000U) #define ADC_FCTRL_FWMARK_SHIFT (16U) /*! FWMARK - Watermark level selection + * 0b0000..Generates STAT[RDY] flag after 1st successful conversion - single conversion + * 0b0001..Generates STAT[RDY] flag after 2nd successful conversion + * 0b0010..Generates STAT[RDY] flag after 3rd successful conversion + * 0b0011..Generates STAT[RDY] flag after 4th successful conversion + * 0b0100..Generates STAT[RDY] flag after 5th successful conversion + * 0b0101..Generates STAT[RDY] flag after 6th successful conversion + * 0b0110..Generates STAT[RDY] flag after 7th successful conversion + * 0b0111..Generates STAT[RDY] flag after 8th successful conversion + * 0b1000..Generates STAT[RDY] flag after 9th successful conversion + * 0b1001..Generates STAT[RDY] flag after 10th successful conversion + * 0b1010..Generates STAT[RDY] flag after 11th successful conversion + * 0b1011..Generates STAT[RDY] flag after 12th successful conversion + * 0b1100..Generates STAT[RDY] flag after 13th successful conversion + * 0b1101..Generates STAT[RDY] flag after 14th successful conversion + * 0b1110..Generates STAT[RDY] flag after 15th successful conversion + * 0b1111..Generates STAT[RDY] flag after 16th successful conversion */ #define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK) /*! @} */ /*! @name SWTRIG - Software Trigger Register */ /*! @{ */ + #define ADC_SWTRIG_SWT0_MASK (0x1U) #define ADC_SWTRIG_SWT0_SHIFT (0U) /*! SWT0 - Software trigger 0 event @@ -2812,6 +2876,7 @@ typedef struct { * 0b1..Trigger 0 event generated. */ #define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK) + #define ADC_SWTRIG_SWT1_MASK (0x2U) #define ADC_SWTRIG_SWT1_SHIFT (1U) /*! SWT1 - Software trigger 1 event @@ -2819,6 +2884,7 @@ typedef struct { * 0b1..Trigger 1 event generated. */ #define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK) + #define ADC_SWTRIG_SWT2_MASK (0x4U) #define ADC_SWTRIG_SWT2_SHIFT (2U) /*! SWT2 - Software trigger 2 event @@ -2826,6 +2892,7 @@ typedef struct { * 0b1..Trigger 2 event generated. */ #define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK) + #define ADC_SWTRIG_SWT3_MASK (0x8U) #define ADC_SWTRIG_SWT3_SHIFT (3U) /*! SWT3 - Software trigger 3 event @@ -2833,6 +2900,7 @@ typedef struct { * 0b1..Trigger 3 event generated. */ #define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK) + #define ADC_SWTRIG_SWT4_MASK (0x10U) #define ADC_SWTRIG_SWT4_SHIFT (4U) /*! SWT4 - Software trigger 4 event @@ -2840,6 +2908,7 @@ typedef struct { * 0b1..Trigger 4 event generated. */ #define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK) + #define ADC_SWTRIG_SWT5_MASK (0x20U) #define ADC_SWTRIG_SWT5_SHIFT (5U) /*! SWT5 - Software trigger 5 event @@ -2847,6 +2916,7 @@ typedef struct { * 0b1..Trigger 5 event generated. */ #define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK) + #define ADC_SWTRIG_SWT6_MASK (0x40U) #define ADC_SWTRIG_SWT6_SHIFT (6U) /*! SWT6 - Software trigger 6 event @@ -2854,6 +2924,7 @@ typedef struct { * 0b1..Trigger 6 event generated. */ #define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK) + #define ADC_SWTRIG_SWT7_MASK (0x80U) #define ADC_SWTRIG_SWT7_SHIFT (7U) /*! SWT7 - Software trigger 7 event @@ -2865,6 +2936,7 @@ typedef struct { /*! @name TCTRL - Trigger Control Register */ /*! @{ */ + #define ADC_TCTRL_HTEN_MASK (0x1U) #define ADC_TCTRL_HTEN_SHIFT (0U) /*! HTEN - Trigger enable @@ -2872,13 +2944,16 @@ typedef struct { * 0b1..Hardware trigger source enabled */ #define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK) + #define ADC_TCTRL_CMD_SEL_MASK (0x2U) #define ADC_TCTRL_CMD_SEL_SHIFT (1U) /*! CMD_SEL - * 0b0..the command is from software TCMD registers - * 0b1..command is from hardware tcmd signal + * 0b0..TCTRLa[TCMD] will determine the command + * 0b1..Software TCDM is bypassed , and hardware TCMD from ADC_ETC module will be used. The trigger command is + * then defined by ADC hardware trigger command selection field in ADC_ETC->TRIGx_CHAINy_z_n[CSEL]. */ #define ADC_TCTRL_CMD_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_CMD_SEL_SHIFT)) & ADC_TCTRL_CMD_SEL_MASK) + #define ADC_TCTRL_TPRI_MASK (0x700U) #define ADC_TCTRL_TPRI_SHIFT (8U) /*! TPRI - Trigger priority setting @@ -2887,11 +2962,13 @@ typedef struct { * 0b111..Set to lowest priority, Level 8 */ #define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK) + #define ADC_TCTRL_TDLY_MASK (0xF0000U) #define ADC_TCTRL_TDLY_SHIFT (16U) /*! TDLY - Trigger delay select */ #define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK) + #define ADC_TCTRL_TCMD_MASK (0xF000000U) #define ADC_TCTRL_TCMD_SHIFT (24U) /*! TCMD - Trigger command select @@ -2906,8 +2983,9 @@ typedef struct { /* The count of ADC_TCTRL */ #define ADC_TCTRL_COUNT (8U) -/*! @name CMDL - ADC Command Low Buffer Register */ +/*! @name CMDL - LPADC Command Low Buffer Register */ /*! @{ */ + #define ADC_CMDL_ADCH_MASK (0x1FU) #define ADC_CMDL_ADCH_SHIFT (0U) /*! ADCH - Input channel select @@ -2920,6 +2998,7 @@ typedef struct { * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair. */ #define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK) + #define ADC_CMDL_ABSEL_MASK (0x20U) #define ADC_CMDL_ABSEL_SHIFT (5U) /*! ABSEL - A-side vs. B-side Select @@ -2927,6 +3006,7 @@ typedef struct { * 0b1..When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA). */ #define ADC_CMDL_ABSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK) + #define ADC_CMDL_DIFF_MASK (0x40U) #define ADC_CMDL_DIFF_SHIFT (6U) /*! DIFF - Differential Mode Enable @@ -2934,6 +3014,7 @@ typedef struct { * 0b1..Differential mode. */ #define ADC_CMDL_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_DIFF_SHIFT)) & ADC_CMDL_DIFF_MASK) + #define ADC_CMDL_CSCALE_MASK (0x2000U) #define ADC_CMDL_CSCALE_SHIFT (13U) /*! CSCALE - Channel Scale @@ -2946,8 +3027,9 @@ typedef struct { /* The count of ADC_CMDL */ #define ADC_CMDL_COUNT (15U) -/*! @name CMDH - ADC Command High Buffer Register */ +/*! @name CMDH - LPADC Command High Buffer Register */ /*! @{ */ + #define ADC_CMDH_CMPEN_MASK (0x3U) #define ADC_CMDH_CMPEN_SHIFT (0U) /*! CMPEN - Compare Function Enable @@ -2957,6 +3039,7 @@ typedef struct { * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true. */ #define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK) + #define ADC_CMDH_LWI_MASK (0x80U) #define ADC_CMDH_LWI_SHIFT (7U) /*! LWI - Loop with Increment @@ -2964,6 +3047,7 @@ typedef struct { * 0b1..Auto channel increment enabled */ #define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK) + #define ADC_CMDH_STS_MASK (0x700U) #define ADC_CMDH_STS_SHIFT (8U) /*! STS - Sample Time Select @@ -2977,6 +3061,7 @@ typedef struct { * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time. */ #define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK) + #define ADC_CMDH_AVGS_MASK (0x7000U) #define ADC_CMDH_AVGS_SHIFT (12U) /*! AVGS - Hardware Average Select @@ -2990,6 +3075,7 @@ typedef struct { * 0b111..128 conversions averaged. */ #define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK) + #define ADC_CMDH_LOOP_MASK (0xF0000U) #define ADC_CMDH_LOOP_SHIFT (16U) /*! LOOP - Loop Count Select @@ -3000,6 +3086,7 @@ typedef struct { * 0b1111..Loop 15 times. Command executes 16 times. */ #define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK) + #define ADC_CMDH_NEXT_MASK (0xF000000U) #define ADC_CMDH_NEXT_SHIFT (24U) /*! NEXT - Next Command Select @@ -3017,11 +3104,13 @@ typedef struct { /*! @name CV - Compare Value Register */ /*! @{ */ + #define ADC_CV_CVL_MASK (0xFFFFU) #define ADC_CV_CVL_SHIFT (0U) -/*! CVL - Compare Value Low. +/*! CVL - Compare Value Low */ #define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK) + #define ADC_CV_CVH_MASK (0xFFFF0000U) #define ADC_CV_CVH_SHIFT (16U) /*! CVH - Compare Value High. @@ -3032,13 +3121,15 @@ typedef struct { /* The count of ADC_CV */ #define ADC_CV_COUNT (4U) -/*! @name RESFIFO - ADC Data Result FIFO Register */ +/*! @name RESFIFO - LPADC Data Result FIFO Register */ /*! @{ */ + #define ADC_RESFIFO_D_MASK (0xFFFFU) #define ADC_RESFIFO_D_SHIFT (0U) /*! D - Data result */ #define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK) + #define ADC_RESFIFO_TSRC_MASK (0x70000U) #define ADC_RESFIFO_TSRC_SHIFT (16U) /*! TSRC - Trigger Source @@ -3048,6 +3139,7 @@ typedef struct { * 0b111..Trigger source 7 initiated this conversion. */ #define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK) + #define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U) #define ADC_RESFIFO_LOOPCNT_SHIFT (20U) /*! LOOPCNT - Loop count value @@ -3057,6 +3149,7 @@ typedef struct { * 0b1111..Result is from 16th conversion in command. */ #define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK) + #define ADC_RESFIFO_CMDSRC_MASK (0xF000000U) #define ADC_RESFIFO_CMDSRC_SHIFT (24U) /*! CMDSRC - Command Buffer Source @@ -3067,6 +3160,7 @@ typedef struct { * 0b1111..CMD15 buffer used as control settings for this conversion. */ #define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK) + #define ADC_RESFIFO_VALID_MASK (0x80000000U) #define ADC_RESFIFO_VALID_SHIFT (31U) /*! VALID - FIFO entry is valid @@ -3095,6 +3189,8 @@ typedef struct { #define ADC_BASE_ADDRS { 0u, LPADC1_BASE, LPADC2_BASE } /** Array initializer of ADC peripheral base pointers */ #define ADC_BASE_PTRS { (ADC_Type *)0u, LPADC1, LPADC2 } +/** Interrupt vectors for the ADC peripheral type */ +#define ADC_IRQS { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn } /*! * @} @@ -3114,7 +3210,7 @@ typedef struct { typedef struct { __IO uint32_t CTRL; /**< ADC_ETC Global Control Register, offset: 0x0 */ __IO uint32_t DONE0_1_IRQ; /**< ETC DONE0 and DONE1 IRQ State Register, offset: 0x4 */ - __IO uint32_t DONE2_ERR_IRQ; /**< ETC DONE_2 and DONE_ERR IRQ State Register, offset: 0x8 */ + __IO uint32_t DONE2_3_ERR_IRQ; /**< ETC DONE_2, DONE_3 and DONE_ERR IRQ State Register, offset: 0x8 */ __IO uint32_t DMA_CTRL; /**< ETC DMA control Register, offset: 0xC */ struct { /* offset: 0x10, array step: 0x28 */ __IO uint32_t TRIGn_CTRL; /**< ETC_TRIG Control Register, array offset: 0x10, array step: 0x28 */ @@ -3141,234 +3237,550 @@ typedef struct { /*! @name CTRL - ADC_ETC Global Control Register */ /*! @{ */ + #define ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU) #define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U) +/*! TRIG_ENABLE + * 0b00000000..disable all 8 external XBAR triggers. + * 0b00000001..enable external XBAR trigger0. + * 0b00000010..enable external XBAR trigger1. + * 0b00000011..enable external XBAR trigger0 and trigger1. + * 0b11111111..enable all 8 external XBAR triggers. + */ #define ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK) -#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U) -#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U) -#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK) -#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U) -#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U) -#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK) -#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U) -#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U) -#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK) -#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U) -#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U) -#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK) + #define ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U) #define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U) #define ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK) + #define ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U) #define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U) +/*! DMA_MODE_SEL + * 0b0..Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared. + * 0b1..Trig DMA_REQ with pulsed signal, REQ will be cleared by ACK only. + */ #define ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK) -#define ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U) -#define ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U) -#define ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK) + #define ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U) #define ADC_ETC_CTRL_SOFTRST_SHIFT (31U) +/*! SOFTRST + * 0b0..ADC_ETC works normally. + * 0b1..All registers inside ADC_ETC will be reset to the default value. + */ #define ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK) /*! @} */ /*! @name DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register */ /*! @{ */ + #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U) #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U) +/*! TRIG0_DONE0 + * 0b0..No TRIG0_DONE0 interrupt detected + * 0b1..TRIG0_DONE0 interrupt detected + */ #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK) + #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U) #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U) +/*! TRIG1_DONE0 + * 0b0..No TRIG1_DONE0 interrupt detected + * 0b1..TRIG1_DONE0 interrupt detected + */ #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK) + #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U) #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U) +/*! TRIG2_DONE0 + * 0b0..No TRIG2_DONE0 interrupt detected + * 0b1..TRIG2_DONE0 interrupt detected + */ #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK) + #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U) #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U) +/*! TRIG3_DONE0 + * 0b0..No TRIG3_DONE0 interrupt detected + * 0b1..TRIG3_DONE0 interrupt detected + */ #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK) + #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U) #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U) +/*! TRIG4_DONE0 + * 0b0..No TRIG4_DONE0 interrupt detected + * 0b1..TRIG4_DONE0 interrupt detected + */ #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK) + #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U) #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U) +/*! TRIG5_DONE0 + * 0b0..No TRIG5_DONE0 interrupt detected + * 0b1..TRIG5_DONE0 interrupt detected + */ #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK) + #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U) #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U) +/*! TRIG6_DONE0 + * 0b0..No TRIG6_DONE0 interrupt detected + * 0b1..TRIG6_DONE0 interrupt detected + */ #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK) + #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U) #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U) +/*! TRIG7_DONE0 + * 0b0..No TRIG7_DONE0 interrupt detected + * 0b1..TRIG7_DONE0 interrupt detected + */ #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK) + #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U) #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U) +/*! TRIG0_DONE1 + * 0b0..No TRIG0_DONE1 interrupt detected + * 0b1..TRIG0_DONE1 interrupt detected + */ #define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK) + #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U) #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U) +/*! TRIG1_DONE1 + * 0b0..No TRIG1_DONE1 interrupt detected + * 0b1..TRIG1_DONE1 interrupt detected + */ #define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK) + #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U) #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U) +/*! TRIG2_DONE1 + * 0b0..No TRIG2_DONE1 interrupt detected + * 0b1..TRIG2_DONE1 interrupt detected + */ #define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK) + #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U) #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U) +/*! TRIG3_DONE1 + * 0b0..No TRIG3_DONE1 interrupt detected + * 0b1..TRIG3_DONE1 interrupt detected + */ #define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK) + #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U) #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U) +/*! TRIG4_DONE1 + * 0b0..No TRIG4_DONE1 interrupt detected + * 0b1..TRIG4_DONE1 interrupt detected + */ #define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK) + #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U) #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U) +/*! TRIG5_DONE1 + * 0b0..No TRIG5_DONE1 interrupt detected + * 0b1..TRIG5_DONE1 interrupt detected + */ #define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK) + #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U) #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U) +/*! TRIG6_DONE1 + * 0b0..No TRIG6_DONE1 interrupt detected + * 0b1..TRIG6_DONE1 interrupt detected + */ #define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK) + #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U) #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U) +/*! TRIG7_DONE1 + * 0b0..No TRIG7_DONE1 interrupt detected + * 0b1..TRIG7_DONE1 interrupt detected + */ #define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK) /*! @} */ -/*! @name DONE2_ERR_IRQ - ETC DONE_2 and DONE_ERR IRQ State Register */ -/*! @{ */ -#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK (0x2U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT (1U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK (0x4U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT (2U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK (0x8U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT (3U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK (0x10U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT (4U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK (0x20U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT (5U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK (0x40U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT (6U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK (0x80U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT (7U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE3_MASK (0x100U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE3_SHIFT (8U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE3_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE3_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE3_MASK (0x200U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE3_SHIFT (9U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE3_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE3_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE3_MASK (0x400U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE3_SHIFT (10U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE3_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE3_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE3_MASK (0x800U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE3_SHIFT (11U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE3_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE3_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE3_MASK (0x1000U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE3_SHIFT (12U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE3_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE3_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE3_MASK (0x2000U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE3_SHIFT (13U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE3_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE3_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE3_MASK (0x4000U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE3_SHIFT (14U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE3_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE3_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE3_MASK (0x8000U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE3_SHIFT (15U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE3_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE3_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK (0x10000U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT (16U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK (0x20000U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT (17U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK (0x40000U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT (18U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK (0x80000U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT (19U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK (0x100000U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT (20U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK (0x200000U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT (21U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK (0x400000U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT (22U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U) -#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK) +/*! @name DONE2_3_ERR_IRQ - ETC DONE_2, DONE_3 and DONE_ERR IRQ State Register */ +/*! @{ */ + +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK (0x1U) +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_SHIFT (0U) +/*! TRIG0_DONE2 + * 0b0..No TRIG0_DONE2 interrupt detected + * 0b1..TRIG0_DONE2 interrupt detected + */ +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK) + +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_MASK (0x2U) +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_SHIFT (1U) +/*! TRIG1_DONE2 + * 0b0..No TRIG1_DONE2 interrupt detected + * 0b1..TRIG1_DONE2 interrupt detected + */ +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_MASK) + +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_MASK (0x4U) +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_SHIFT (2U) +/*! TRIG2_DONE2 + * 0b0..No TRIG2_DONE2 interrupt detected + * 0b1..TRIG2_DONE2 interrupt detected + */ +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_MASK) + +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_MASK (0x8U) +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_SHIFT (3U) +/*! TRIG3_DONE2 + * 0b0..No TRIG3_DONE2 interrupt detected + * 0b1..TRIG3_DONE2 interrupt detected + */ +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_MASK) + +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_MASK (0x10U) +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_SHIFT (4U) +/*! TRIG4_DONE2 + * 0b0..No TRIG4_DONE2 interrupt detected + * 0b1..TRIG4_DONE2 interrupt detected + */ +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_MASK) + +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_MASK (0x20U) +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_SHIFT (5U) +/*! TRIG5_DONE2 + * 0b0..No TRIG5_DONE2 interrupt detected + * 0b1..TRIG5_DONE2 interrupt detected + */ +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_MASK) + +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_MASK (0x40U) +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_SHIFT (6U) +/*! TRIG6_DONE2 + * 0b0..No TRIG6_DONE2 interrupt detected + * 0b1..TRIG6_DONE2 interrupt detected + */ +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_MASK) + +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_MASK (0x80U) +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_SHIFT (7U) +/*! TRIG7_DONE2 + * 0b0..No TRIG7_DONE2 interrupt detected + * 0b1..TRIG7_DONE2 interrupt detected + */ +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_MASK) + +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_MASK (0x100U) +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_SHIFT (8U) +/*! TRIG0_DONE3 + * 0b0..No TRIG0_DONE3 interrupt detected + * 0b1..TRIG0_DONE3 interrupt detected + */ +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_MASK) + +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3_MASK (0x200U) +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3_SHIFT (9U) +/*! TRIG1_DONE3 + * 0b0..No TRIG1_DONE3 interrupt detected + * 0b1..TRIG1_DONE3 interrupt detected + */ +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3_MASK) + +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3_MASK (0x400U) +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3_SHIFT (10U) +/*! TRIG2_DONE3 + * 0b0..No TRIG2_DONE3 interrupt detected + * 0b1..TRIG2_DONE3 interrupt detected + */ +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3_MASK) + +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3_MASK (0x800U) +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3_SHIFT (11U) +/*! TRIG3_DONE3 + * 0b0..No TRIG3_DONE3 interrupt detected + * 0b1..TRIG3_DONE3 interrupt detected + */ +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3_MASK) + +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3_MASK (0x1000U) +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3_SHIFT (12U) +/*! TRIG4_DONE3 + * 0b0..No TRIG4_DONE3 interrupt detected + * 0b1..TRIG4_DONE3 interrupt detected + */ +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3_MASK) + +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3_MASK (0x2000U) +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3_SHIFT (13U) +/*! TRIG5_DONE3 + * 0b0..No TRIG5_DONE3 interrupt detected + * 0b1..TRIG5_DONE3 interrupt detected + */ +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3_MASK) + +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3_MASK (0x4000U) +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3_SHIFT (14U) +/*! TRIG6_DONE3 + * 0b0..No TRIG6_DONE3 interrupt detected + * 0b1..TRIG6_DONE3 interrupt detected + */ +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3_MASK) + +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3_MASK (0x8000U) +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3_SHIFT (15U) +/*! TRIG7_DONE3 + * 0b0..No TRIG7_DONE3 interrupt detected + * 0b1..TRIG7_DONE3 interrupt detected + */ +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3_MASK) + +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_MASK (0x10000U) +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_SHIFT (16U) +/*! TRIG0_ERR + * 0b0..No TRIG0_ERR interrupt detected + * 0b1..TRIG0_ERR interrupt detected + */ +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_MASK) + +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_MASK (0x20000U) +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_SHIFT (17U) +/*! TRIG1_ERR + * 0b0..No TRIG1_ERR interrupt detected + * 0b1..TRIG1_ERR interrupt detected + */ +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_MASK) + +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_MASK (0x40000U) +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_SHIFT (18U) +/*! TRIG2_ERR + * 0b0..No TRIG2_ERR interrupt detected + * 0b1..TRIG2_ERR interrupt detected + */ +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_MASK) + +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_MASK (0x80000U) +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_SHIFT (19U) +/*! TRIG3_ERR + * 0b0..No TRIG3_ERR interrupt detected + * 0b1..TRIG3_ERR interrupt detected + */ +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_MASK) + +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_MASK (0x100000U) +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_SHIFT (20U) +/*! TRIG4_ERR + * 0b0..No TRIG4_ERR interrupt detected + * 0b1..TRIG4_ERR interrupt detected + */ +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_MASK) + +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_MASK (0x200000U) +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_SHIFT (21U) +/*! TRIG5_ERR + * 0b0..No TRIG5_ERR interrupt detected + * 0b1..TRIG5_ERR interrupt detected + */ +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_MASK) + +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_MASK (0x400000U) +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_SHIFT (22U) +/*! TRIG6_ERR + * 0b0..No TRIG6_ERR interrupt detected + * 0b1..TRIG6_ERR interrupt detected + */ +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_MASK) + +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_MASK (0x800000U) +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_SHIFT (23U) +/*! TRIG7_ERR + * 0b0..No TRIG7_ERR interrupt detected + * 0b1..TRIG7_ERR interrupt detected + */ +#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_MASK) /*! @} */ /*! @name DMA_CTRL - ETC DMA control Register */ /*! @{ */ + #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U) #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U) +/*! TRIG0_ENABLE + * 0b0..TRIG0 DMA request disabled. + * 0b1..TRIG0 DMA request enabled. + */ #define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK) + #define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U) #define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U) +/*! TRIG1_ENABLE + * 0b0..TRIG1 DMA request disabled. + * 0b1..TRIG1 DMA request enabled. + */ #define ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK) + #define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U) #define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U) +/*! TRIG2_ENABLE + * 0b0..TRIG2 DMA request disabled. + * 0b1..TRIG2 DMA request enabled. + */ #define ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK) + #define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U) #define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U) +/*! TRIG3_ENABLE + * 0b0..TRIG3 DMA request disabled. + * 0b1..TRIG3 DMA request enabled. + */ #define ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK) + #define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U) #define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U) +/*! TRIG4_ENABLE + * 0b0..TRIG4 DMA request disabled. + * 0b1..TRIG4 DMA request enabled. + */ #define ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK) + #define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U) #define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U) +/*! TRIG5_ENABLE + * 0b0..TRIG5 DMA request disabled. + * 0b1..TRIG5 DMA request enabled. + */ #define ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK) + #define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U) #define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U) +/*! TRIG6_ENABLE + * 0b0..TRIG6 DMA request disabled. + * 0b1..TRIG6 DMA request enabled. + */ #define ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK) + #define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U) #define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U) +/*! TRIG7_ENABLE + * 0b0..TRIG7 DMA request disabled. + * 0b1..TRIG7 DMA request enabled. + */ #define ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK) + #define ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U) #define ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U) +/*! TRIG0_REQ + * 0b0..TRIG0_REQ not detected. + * 0b1..TRIG0_REQ detected. + */ #define ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK) + #define ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U) #define ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U) +/*! TRIG1_REQ + * 0b0..TRIG1_REQ not detected. + * 0b1..TRIG1_REQ detected. + */ #define ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK) + #define ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U) #define ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U) +/*! TRIG2_REQ + * 0b0..TRIG2_REQ not detected. + * 0b1..TRIG2_REQ detected. + */ #define ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK) + #define ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U) #define ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U) +/*! TRIG3_REQ + * 0b0..TRIG3_REQ not detected. + * 0b1..TRIG3_REQ detected. + */ #define ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK) + #define ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U) #define ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U) +/*! TRIG4_REQ + * 0b0..TRIG4_REQ not detected. + * 0b1..TRIG4_REQ detected. + */ #define ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK) + #define ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U) #define ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U) +/*! TRIG5_REQ + * 0b0..TRIG5_REQ not detected. + * 0b1..TRIG5_REQ detected. + */ #define ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK) + #define ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U) #define ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U) +/*! TRIG6_REQ + * 0b0..TRIG6_REQ not detected. + * 0b1..TRIG6_REQ detected. + */ #define ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK) + #define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U) #define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U) +/*! TRIG7_REQ + * 0b0..TRIG7_REQ not detected. + * 0b1..TRIG7_REQ detected. + */ #define ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK) /*! @} */ /*! @name TRIGn_CTRL - ETC_TRIG Control Register */ /*! @{ */ + #define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U) #define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U) +/*! SW_TRIG + * 0b0..No software trigger event generated. + * 0b1..Software trigger event generated. + */ #define ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK) + #define ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U) #define ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U) +/*! TRIG_MODE + * 0b0..Hardware trigger. The softerware trigger will be ignored. + * 0b1..Software trigger. The hardware trigger will be ignored. + */ #define ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK) + #define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U) #define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U) +/*! TRIG_CHAIN + * 0b000..Trigger chain length is 1 + * 0b001..Trigger chain length is 2 + * 0b010..Trigger chain length is 3 + * 0b011..Trigger chain length is 4 + * 0b100..Trigger chain length is 5 + * 0b101..Trigger chain length is 6 + * 0b110..Trigger chain length is 7 + * 0b111..Trigger chain length is 8 + */ #define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK) + #define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U) #define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U) #define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK) + #define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U) #define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U) +/*! SYNC_MODE + * 0b0..Synchronization mode disabled, TRIGa and TRIG(a+4) are triggered independently. + * 0b1..Synchronization mode enabled, TRIGa and TRIG(a+4) are triggered by TRIGa source synchronously. + */ #define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK) + #define ADC_ETC_TRIGn_CTRL_CHAINx_DONE_MASK (0xFF000000U) #define ADC_ETC_TRIGn_CTRL_CHAINx_DONE_SHIFT (24U) +/*! CHAINx_DONE + * 0b00000000..segment x done not detected. + * 0b00000001..segment x done detected. + */ #define ADC_ETC_TRIGn_CTRL_CHAINx_DONE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_CHAINx_DONE_SHIFT)) & ADC_ETC_TRIGn_CTRL_CHAINx_DONE_MASK) /*! @} */ @@ -3377,9 +3789,11 @@ typedef struct { /*! @name TRIGn_COUNTER - ETC_TRIG Counter Register */ /*! @{ */ + #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU) #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U) #define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK) + #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U) #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U) #define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK) @@ -3390,35 +3804,131 @@ typedef struct { /*! @name TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register */ /*! @{ */ + #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU) #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U) +/*! CSEL0 + * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. + * 0b0001..ADC CMD1 selected. + * 0b0010..ADC CMD2 selected. + * 0b0011..ADC CMD3 selected. + * 0b0100..ADC CMD4 selected. + * 0b0101..ADC CMD5 selected. + * 0b0110..ADC CMD6 selected. + * 0b0111..ADC CMD7 selected. + * 0b1000..ADC CMD8 selected. + * 0b1001..ADC CMD9 selected. + * 0b1010..ADC CMD10 selected. + * 0b1011..ADC CMD11 selected. + * 0b1100..ADC CMD12 selected. + * 0b1101..ADC CMD13 selected. + * 0b1110..ADC CMD14 selected. + * 0b1111..ADC CMD15 selected. + */ #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK) + #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U) #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U) +/*! HWTS0 + * 0b00000000..no trigger selected + * 0b00000001..ADC TRIG0 selected + * 0b00000010..ADC TRIG1 selected + * 0b00000100..ADC TRIG2 selected + * 0b00001000..ADC TRIG3 selected + * 0b00010000..ADC TRIG4 selected + * 0b00100000..ADC TRIG5 selected + * 0b01000000..ADC TRIG6 selected + * 0b10000000..ADC TRIG7 selected + */ #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK) + #define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U) #define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U) +/*! B2B0 + * 0b0..Disable B2B. Wait until delay value defined by TRIG0_COUNTER[SAMPLE_INTERVAL] is reached + * 0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + */ #define ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK) + #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U) #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U) +/*! IE0 + * 0b00..Generate interrupt on Done0 when segment 0 finish. + * 0b01..Generate interrupt on Done1 when segment 0 finish. + * 0b10..Generate interrupt on Done2 when segment 0 finish. + * 0b11..Generate interrupt on Done3 when segment 0 finish. + */ #define ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK) + #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_MASK (0x8000U) #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_SHIFT (15U) +/*! IE0_EN + * 0b0..Interrupt DONE disabled. + * 0b1..Interrupt DONE enabled. When segment 0 finish, an interrupt will be generated on the specific port configured by the IE0. + */ #define ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_MASK) + #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U) #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U) +/*! CSEL1 + * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. + * 0b0001..ADC CMD1 selected. + * 0b0010..ADC CMD2 selected. + * 0b0011..ADC CMD3 selected. + * 0b0100..ADC CMD4 selected. + * 0b0101..ADC CMD5 selected. + * 0b0110..ADC CMD6 selected. + * 0b0111..ADC CMD7 selected. + * 0b1000..ADC CMD8 selected. + * 0b1001..ADC CMD9 selected. + * 0b1010..ADC CMD10 selected. + * 0b1011..ADC CMD11 selected. + * 0b1100..ADC CMD12 selected. + * 0b1101..ADC CMD13 selected. + * 0b1110..ADC CMD14 selected. + * 0b1111..ADC CMD15 selected. + */ #define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK) + #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U) #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U) +/*! HWTS1 + * 0b00000000..no trigger selected + * 0b00000001..ADC TRIG0 selected + * 0b00000010..ADC TRIG1 selected + * 0b00000100..ADC TRIG2 selected + * 0b00001000..ADC TRIG3 selected + * 0b00010000..ADC TRIG4 selected + * 0b00100000..ADC TRIG5 selected + * 0b01000000..ADC TRIG6 selected + * 0b10000000..ADC TRIG7 selected + */ #define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK) + #define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U) #define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U) +/*! B2B1 + * 0b0..Disable B2B. Wait until delay value defined by TRIG1_COUNTER[SAMPLE_INTERVAL] is reached + * 0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + */ #define ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK) + #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U) #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U) +/*! IE1 + * 0b00..Generate interrupt on Done0 when Segment 1 finish. + * 0b01..Generate interrupt on Done1 when Segment 1 finish. + * 0b10..Generate interrupt on Done2 when Segment 1 finish. + * 0b11..Generate interrupt on Done3 when Segment 1 finish. + */ #define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK) + #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_MASK (0x80000000U) #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_SHIFT (31U) +/*! IE1_EN + * 0b0..Interrupt DONE disabled. + * 0b1..Interrupt DONE enabled. When segment 1 finish, an interrupt will be generated on the specific port configured by the IE1. + */ #define ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_MASK) /*! @} */ @@ -3427,35 +3937,131 @@ typedef struct { /*! @name TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register */ /*! @{ */ + #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU) #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U) +/*! CSEL2 + * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. + * 0b0001..ADC CMD1 selected. + * 0b0010..ADC CMD2 selected. + * 0b0011..ADC CMD3 selected. + * 0b0100..ADC CMD4 selected. + * 0b0101..ADC CMD5 selected. + * 0b0110..ADC CMD6 selected. + * 0b0111..ADC CMD7 selected. + * 0b1000..ADC CMD8 selected. + * 0b1001..ADC CMD9 selected. + * 0b1010..ADC CMD10 selected. + * 0b1011..ADC CMD11 selected. + * 0b1100..ADC CMD12 selected. + * 0b1101..ADC CMD13 selected. + * 0b1110..ADC CMD14 selected. + * 0b1111..ADC CMD15 selected. + */ #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK) + #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U) #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U) +/*! HWTS2 + * 0b00000000..no trigger selected + * 0b00000001..ADC TRIG0 selected + * 0b00000010..ADC TRIG1 selected + * 0b00000100..ADC TRIG2 selected + * 0b00001000..ADC TRIG3 selected + * 0b00010000..ADC TRIG4 selected + * 0b00100000..ADC TRIG5 selected + * 0b01000000..ADC TRIG6 selected + * 0b10000000..ADC TRIG7 selected + */ #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK) + #define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U) #define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U) +/*! B2B2 + * 0b0..Disable B2B. Wait until delay value defined by TRIG2_COUNTER[SAMPLE_INTERVAL] is reached + * 0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + */ #define ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK) + #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U) #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U) +/*! IE2 + * 0b00..Generate interrupt on Done0 when segment 2 finish. + * 0b01..Generate interrupt on Done1 when segment 2 finish. + * 0b10..Generate interrupt on Done2 when segment 2 finish. + * 0b11..Generate interrupt on Done3 when segment 2 finish. + */ #define ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK) + #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_MASK (0x8000U) #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_SHIFT (15U) +/*! IE2_EN + * 0b0..Interrupt DONE disabled. + * 0b1..Interrupt DONE enabled. When segment 2 finish, an interrupt will be generated on the specific port configured by the IE2. + */ #define ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_MASK) + #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U) #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U) +/*! CSEL3 + * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. + * 0b0001..ADC CMD1 selected. + * 0b0010..ADC CMD2 selected. + * 0b0011..ADC CMD3 selected. + * 0b0100..ADC CMD4 selected. + * 0b0101..ADC CMD5 selected. + * 0b0110..ADC CMD6 selected. + * 0b0111..ADC CMD7 selected. + * 0b1000..ADC CMD8 selected. + * 0b1001..ADC CMD9 selected. + * 0b1010..ADC CMD10 selected. + * 0b1011..ADC CMD11 selected. + * 0b1100..ADC CMD12 selected. + * 0b1101..ADC CMD13 selected. + * 0b1110..ADC CMD14 selected. + * 0b1111..ADC CMD15 selected. + */ #define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK) + #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U) #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U) +/*! HWTS3 + * 0b00000000..no trigger selected + * 0b00000001..ADC TRIG0 selected + * 0b00000010..ADC TRIG1 selected + * 0b00000100..ADC TRIG2 selected + * 0b00001000..ADC TRIG3 selected + * 0b00010000..ADC TRIG4 selected + * 0b00100000..ADC TRIG5 selected + * 0b01000000..ADC TRIG6 selected + * 0b10000000..ADC TRIG7 selected + */ #define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK) + #define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U) #define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U) +/*! B2B3 + * 0b0..Disable B2B. Wait until delay value defined by TRIG3_COUNTER[SAMPLE_INTERVAL] is reached + * 0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + */ #define ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK) + #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U) #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U) +/*! IE3 + * 0b00..Generate interrupt on Done0 when segment 3 finish. + * 0b01..Generate interrupt on Done1 when segment 3 finish. + * 0b10..Generate interrupt on Done2 when segment 3 finish. + * 0b11..Generate interrupt on Done3 when segment 3 finish. + */ #define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK) + #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_MASK (0x80000000U) #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_SHIFT (31U) +/*! IE3_EN + * 0b0..Interrupt DONE disabled. + * 0b1..Interrupt DONE enabled. When segment 3 finish, an interrupt will be generated on the specific port configured by the IE3. + */ #define ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_MASK) /*! @} */ @@ -3464,35 +4070,131 @@ typedef struct { /*! @name TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register */ /*! @{ */ + #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU) #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U) +/*! CSEL4 + * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. + * 0b0001..ADC CMD1 selected. + * 0b0010..ADC CMD2 selected. + * 0b0011..ADC CMD3 selected. + * 0b0100..ADC CMD4 selected. + * 0b0101..ADC CMD5 selected. + * 0b0110..ADC CMD6 selected. + * 0b0111..ADC CMD7 selected. + * 0b1000..ADC CMD8 selected. + * 0b1001..ADC CMD9 selected. + * 0b1010..ADC CMD10 selected. + * 0b1011..ADC CMD11 selected. + * 0b1100..ADC CMD12 selected. + * 0b1101..ADC CMD13 selected. + * 0b1110..ADC CMD14 selected. + * 0b1111..ADC CMD15 selected. + */ #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK) + #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U) #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U) +/*! HWTS4 + * 0b00000000..no trigger selected + * 0b00000001..ADC TRIG0 selected + * 0b00000010..ADC TRIG1 selected + * 0b00000100..ADC TRIG2 selected + * 0b00001000..ADC TRIG3 selected + * 0b00010000..ADC TRIG4 selected + * 0b00100000..ADC TRIG5 selected + * 0b01000000..ADC TRIG6 selected + * 0b10000000..ADC TRIG7 selected + */ #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK) + #define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U) #define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U) +/*! B2B4 + * 0b0..Disable B2B. Wait until delay value defined by TRIG4_COUNTER[SAMPLE_INTERVAL] is reached + * 0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + */ #define ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK) + #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U) #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U) +/*! IE4 + * 0b00..Generate interrupt on Done0 when segment 4 finish. + * 0b01..Generate interrupt on Done1 when segment 4 finish. + * 0b10..Generate interrupt on Done2 when segment 4 finish. + * 0b11..Generate interrupt on Done3 when segment 4 finish. + */ #define ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK) + #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_MASK (0x8000U) #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_SHIFT (15U) +/*! IE4_EN + * 0b0..Interrupt DONE disabled. + * 0b1..Interrupt DONE enabled. When segment 4 finish, an interrupt will be generated on the specific port configured by the IE4. + */ #define ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_MASK) + #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U) #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U) +/*! CSEL5 + * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. + * 0b0001..ADC CMD1 selected. + * 0b0010..ADC CMD2 selected. + * 0b0011..ADC CMD3 selected. + * 0b0100..ADC CMD4 selected. + * 0b0101..ADC CMD5 selected. + * 0b0110..ADC CMD6 selected. + * 0b0111..ADC CMD7 selected. + * 0b1000..ADC CMD8 selected. + * 0b1001..ADC CMD9 selected. + * 0b1010..ADC CMD10 selected. + * 0b1011..ADC CMD11 selected. + * 0b1100..ADC CMD12 selected. + * 0b1101..ADC CMD13 selected. + * 0b1110..ADC CMD14 selected. + * 0b1111..ADC CMD15 selected. + */ #define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK) + #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U) #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U) +/*! HWTS5 + * 0b00000000..no trigger selected + * 0b00000001..ADC TRIG0 selected + * 0b00000010..ADC TRIG1 selected + * 0b00000100..ADC TRIG2 selected + * 0b00001000..ADC TRIG3 selected + * 0b00010000..ADC TRIG4 selected + * 0b00100000..ADC TRIG5 selected + * 0b01000000..ADC TRIG6 selected + * 0b10000000..ADC TRIG7 selected + */ #define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK) + #define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U) #define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U) +/*! B2B5 + * 0b0..Disable B2B. Wait until delay value defined by TRIG5_COUNTER[SAMPLE_INTERVAL] is reached + * 0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + */ #define ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK) + #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U) #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U) +/*! IE5 + * 0b00..Generate interrupt on Done0 when segment 5 finish. + * 0b01..Generate interrupt on Done1 when segment 5 finish. + * 0b10..Generate interrupt on Done2 when segment 5 finish. + * 0b11..Generate interrupt on Done3 when segment 5 finish. + */ #define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK) + #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_MASK (0x80000000U) #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_SHIFT (31U) +/*! IE5_EN + * 0b0..Interrupt DONE disabled. + * 0b1..Interrupt DONE enabled. When segment 5 finish, an interrupt will be generated on the specific port configured by the IE5. + */ #define ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_MASK) /*! @} */ @@ -3501,35 +4203,131 @@ typedef struct { /*! @name TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register */ /*! @{ */ + #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU) #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U) +/*! CSEL6 + * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. + * 0b0001..ADC CMD1 selected. + * 0b0010..ADC CMD2 selected. + * 0b0011..ADC CMD3 selected. + * 0b0100..ADC CMD4 selected. + * 0b0101..ADC CMD5 selected. + * 0b0110..ADC CMD6 selected. + * 0b0111..ADC CMD7 selected. + * 0b1000..ADC CMD8 selected. + * 0b1001..ADC CMD9 selected. + * 0b1010..ADC CMD10 selected. + * 0b1011..ADC CMD11 selected. + * 0b1100..ADC CMD12 selected. + * 0b1101..ADC CMD13 selected. + * 0b1110..ADC CMD14 selected. + * 0b1111..ADC CMD15 selected. + */ #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK) + #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U) #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U) +/*! HWTS6 + * 0b00000000..no trigger selected + * 0b00000001..ADC TRIG0 selected + * 0b00000010..ADC TRIG1 selected + * 0b00000100..ADC TRIG2 selected + * 0b00001000..ADC TRIG3 selected + * 0b00010000..ADC TRIG4 selected + * 0b00100000..ADC TRIG5 selected + * 0b01000000..ADC TRIG6 selected + * 0b10000000..ADC TRIG7 selected + */ #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK) + #define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U) #define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U) +/*! B2B6 + * 0b0..Disable B2B. Wait until delay value defined by TRIG6_COUNTER[SAMPLE_INTERVAL] is reached + * 0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + */ #define ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK) + #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U) #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U) +/*! IE6 + * 0b00..Generate interrupt on Done0 when segment 6 finish. + * 0b01..Generate interrupt on Done1 when segment 6 finish. + * 0b10..Generate interrupt on Done2 when segment 6 finish. + * 0b11..Generate interrupt on Done3 when segment 6 finish. + */ #define ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK) + #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_MASK (0x8000U) #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_SHIFT (15U) +/*! IE6_EN + * 0b0..Interrupt DONE disabled. + * 0b1..Interrupt DONE enabled. When segment 6 finish, an interrupt will be generated on the specific port configured by the IE6. + */ #define ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_MASK) + #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U) #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U) +/*! CSEL7 + * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored. + * 0b0001..ADC CMD1 selected. + * 0b0010..ADC CMD2 selected. + * 0b0011..ADC CMD3 selected. + * 0b0100..ADC CMD4 selected. + * 0b0101..ADC CMD5 selected. + * 0b0110..ADC CMD6 selected. + * 0b0111..ADC CMD7 selected. + * 0b1000..ADC CMD8 selected. + * 0b1001..ADC CMD9 selected. + * 0b1010..ADC CMD10 selected. + * 0b1011..ADC CMD11 selected. + * 0b1100..ADC CMD12 selected. + * 0b1101..ADC CMD13 selected. + * 0b1110..ADC CMD14 selected. + * 0b1111..ADC CMD15 selected. + */ #define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK) + #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U) #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U) +/*! HWTS7 + * 0b00000000..no trigger selected + * 0b00000001..ADC TRIG0 selected + * 0b00000010..ADC TRIG1 selected + * 0b00000100..ADC TRIG2 selected + * 0b00001000..ADC TRIG3 selected + * 0b00010000..ADC TRIG4 selected + * 0b00100000..ADC TRIG5 selected + * 0b01000000..ADC TRIG6 selected + * 0b10000000..ADC TRIG7 selected + */ #define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK) + #define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U) #define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U) +/*! B2B7 + * 0b0..Disable B2B. Wait until delay value defined by TRIG7_COUNTER[SAMPLE_INTERVAL] is reached + * 0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached. + */ #define ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK) + #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U) #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U) +/*! IE7 + * 0b00..Generate interrupt on Done0 when segment 7 finish. + * 0b01..Generate interrupt on Done1 when segment 7 finish. + * 0b10..Generate interrupt on Done2 when segment 7 finish. + * 0b11..Generate interrupt on Done3 when segment 7 finish. + */ #define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK) + #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_MASK (0x80000000U) #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_SHIFT (31U) +/*! IE7_EN + * 0b0..Interrupt DONE disabled. + * 0b1..Interrupt DONE enabled. When segment 7 finish, an interrupt will be generated on the specific port configured by the IE7. + */ #define ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_MASK) /*! @} */ @@ -3538,9 +4336,11 @@ typedef struct { /*! @name TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register */ /*! @{ */ + #define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU) #define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U) #define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK) + #define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U) #define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U) #define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK) @@ -3551,9 +4351,11 @@ typedef struct { /*! @name TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register */ /*! @{ */ + #define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU) #define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U) #define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK) + #define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U) #define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U) #define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK) @@ -3564,9 +4366,11 @@ typedef struct { /*! @name TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register */ /*! @{ */ + #define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU) #define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U) #define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK) + #define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U) #define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U) #define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK) @@ -3577,9 +4381,11 @@ typedef struct { /*! @name TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register */ /*! @{ */ + #define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU) #define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U) #define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK) + #define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U) #define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U) #define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK) @@ -3612,730 +4418,6 @@ typedef struct { */ /* end of group ADC_ETC_Peripheral_Access_Layer */ -/* ---------------------------------------------------------------------------- - -- AIPSTZ Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer - * @{ - */ - -/** AIPSTZ - Register Layout Typedef */ -typedef struct { - __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */ - uint8_t RESERVED_0[60]; - __IO uint32_t OPACR; /**< Off-Platform Peripheral Access Control Registers, offset: 0x40 */ - __IO uint32_t OPACR1; /**< Off-Platform Peripheral Access Control Registers, offset: 0x44 */ - __IO uint32_t OPACR2; /**< Off-Platform Peripheral Access Control Registers, offset: 0x48 */ - __IO uint32_t OPACR3; /**< Off-Platform Peripheral Access Control Registers, offset: 0x4C */ - __IO uint32_t OPACR4; /**< Off-Platform Peripheral Access Control Registers, offset: 0x50 */ -} AIPSTZ_Type; - -/* ---------------------------------------------------------------------------- - -- AIPSTZ Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks - * @{ - */ - -/*! @name MPR - Master Priviledge Registers */ -/*! @{ */ -#define AIPSTZ_MPR_MPROT5_MASK (0xF00U) -#define AIPSTZ_MPR_MPROT5_SHIFT (8U) -/*! MPROT5 - * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. - * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. - * 0bxx0x..This master is not trusted for write accesses. - * 0bxx1x..This master is trusted for write accesses. - * 0bx0xx..This master is not trusted for read accesses. - * 0bx1xx..This master is trusted for read accesses. - * 0b1xxx..Write accesses from this master are allowed to be buffered - */ -#define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK) -#define AIPSTZ_MPR_MPROT3_MASK (0xF0000U) -#define AIPSTZ_MPR_MPROT3_SHIFT (16U) -/*! MPROT3 - * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. - * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. - * 0bxx0x..This master is not trusted for write accesses. - * 0bxx1x..This master is trusted for write accesses. - * 0bx0xx..This master is not trusted for read accesses. - * 0bx1xx..This master is trusted for read accesses. - * 0b1xxx..Write accesses from this master are allowed to be buffered - */ -#define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK) -#define AIPSTZ_MPR_MPROT2_MASK (0xF00000U) -#define AIPSTZ_MPR_MPROT2_SHIFT (20U) -/*! MPROT2 - * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. - * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. - * 0bxx0x..This master is not trusted for write accesses. - * 0bxx1x..This master is trusted for write accesses. - * 0bx0xx..This master is not trusted for read accesses. - * 0bx1xx..This master is trusted for read accesses. - * 0b1xxx..Write accesses from this master are allowed to be buffered - */ -#define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK) -#define AIPSTZ_MPR_MPROT1_MASK (0xF000000U) -#define AIPSTZ_MPR_MPROT1_SHIFT (24U) -/*! MPROT1 - * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. - * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. - * 0bxx0x..This master is not trusted for write accesses. - * 0bxx1x..This master is trusted for write accesses. - * 0bx0xx..This master is not trusted for read accesses. - * 0bx1xx..This master is trusted for read accesses. - * 0b1xxx..Write accesses from this master are allowed to be buffered - */ -#define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK) -#define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U) -#define AIPSTZ_MPR_MPROT0_SHIFT (28U) -/*! MPROT0 - * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute. - * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access. - * 0bxx0x..This master is not trusted for write accesses. - * 0bxx1x..This master is trusted for write accesses. - * 0bx0xx..This master is not trusted for read accesses. - * 0bx1xx..This master is trusted for read accesses. - * 0b1xxx..Write accesses from this master are allowed to be buffered - */ -#define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK) -/*! @} */ - -/*! @name OPACR - Off-Platform Peripheral Access Control Registers */ -/*! @{ */ -#define AIPSTZ_OPACR_OPAC7_MASK (0xFU) -#define AIPSTZ_OPACR_OPAC7_SHIFT (0U) -/*! OPAC7 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK) -#define AIPSTZ_OPACR_OPAC6_MASK (0xF0U) -#define AIPSTZ_OPACR_OPAC6_SHIFT (4U) -/*! OPAC6 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK) -#define AIPSTZ_OPACR_OPAC5_MASK (0xF00U) -#define AIPSTZ_OPACR_OPAC5_SHIFT (8U) -/*! OPAC5 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK) -#define AIPSTZ_OPACR_OPAC4_MASK (0xF000U) -#define AIPSTZ_OPACR_OPAC4_SHIFT (12U) -/*! OPAC4 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK) -#define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U) -#define AIPSTZ_OPACR_OPAC3_SHIFT (16U) -/*! OPAC3 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK) -#define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U) -#define AIPSTZ_OPACR_OPAC2_SHIFT (20U) -/*! OPAC2 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK) -#define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U) -#define AIPSTZ_OPACR_OPAC1_SHIFT (24U) -/*! OPAC1 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK) -#define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U) -#define AIPSTZ_OPACR_OPAC0_SHIFT (28U) -/*! OPAC0 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK) -/*! @} */ - -/*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */ -/*! @{ */ -#define AIPSTZ_OPACR1_OPAC15_MASK (0xFU) -#define AIPSTZ_OPACR1_OPAC15_SHIFT (0U) -/*! OPAC15 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK) -#define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U) -#define AIPSTZ_OPACR1_OPAC14_SHIFT (4U) -/*! OPAC14 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK) -#define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U) -#define AIPSTZ_OPACR1_OPAC13_SHIFT (8U) -/*! OPAC13 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK) -#define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U) -#define AIPSTZ_OPACR1_OPAC12_SHIFT (12U) -/*! OPAC12 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK) -#define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U) -#define AIPSTZ_OPACR1_OPAC11_SHIFT (16U) -/*! OPAC11 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK) -#define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U) -#define AIPSTZ_OPACR1_OPAC10_SHIFT (20U) -/*! OPAC10 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK) -#define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U) -#define AIPSTZ_OPACR1_OPAC9_SHIFT (24U) -/*! OPAC9 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK) -#define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U) -#define AIPSTZ_OPACR1_OPAC8_SHIFT (28U) -/*! OPAC8 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK) -/*! @} */ - -/*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */ -/*! @{ */ -#define AIPSTZ_OPACR2_OPAC23_MASK (0xFU) -#define AIPSTZ_OPACR2_OPAC23_SHIFT (0U) -/*! OPAC23 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK) -#define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U) -#define AIPSTZ_OPACR2_OPAC22_SHIFT (4U) -/*! OPAC22 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK) -#define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U) -#define AIPSTZ_OPACR2_OPAC21_SHIFT (8U) -/*! OPAC21 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK) -#define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U) -#define AIPSTZ_OPACR2_OPAC20_SHIFT (12U) -/*! OPAC20 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK) -#define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U) -#define AIPSTZ_OPACR2_OPAC19_SHIFT (16U) -/*! OPAC19 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK) -#define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U) -#define AIPSTZ_OPACR2_OPAC18_SHIFT (20U) -/*! OPAC18 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK) -#define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U) -#define AIPSTZ_OPACR2_OPAC17_SHIFT (24U) -/*! OPAC17 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK) -#define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U) -#define AIPSTZ_OPACR2_OPAC16_SHIFT (28U) -/*! OPAC16 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK) -/*! @} */ - -/*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */ -/*! @{ */ -#define AIPSTZ_OPACR3_OPAC31_MASK (0xFU) -#define AIPSTZ_OPACR3_OPAC31_SHIFT (0U) -/*! OPAC31 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK) -#define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U) -#define AIPSTZ_OPACR3_OPAC30_SHIFT (4U) -/*! OPAC30 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK) -#define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U) -#define AIPSTZ_OPACR3_OPAC29_SHIFT (8U) -/*! OPAC29 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK) -#define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U) -#define AIPSTZ_OPACR3_OPAC28_SHIFT (12U) -/*! OPAC28 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK) -#define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U) -#define AIPSTZ_OPACR3_OPAC27_SHIFT (16U) -/*! OPAC27 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK) -#define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U) -#define AIPSTZ_OPACR3_OPAC26_SHIFT (20U) -/*! OPAC26 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK) -#define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U) -#define AIPSTZ_OPACR3_OPAC25_SHIFT (24U) -/*! OPAC25 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK) -#define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U) -#define AIPSTZ_OPACR3_OPAC24_SHIFT (28U) -/*! OPAC24 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK) -/*! @} */ - -/*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */ -/*! @{ */ -#define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U) -#define AIPSTZ_OPACR4_OPAC33_SHIFT (24U) -/*! OPAC33 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK) -#define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U) -#define AIPSTZ_OPACR4_OPAC32_SHIFT (28U) -/*! OPAC32 - * 0bxxx0..Accesses from an untrusted master are allowed. - * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, - * the access is terminated with an error response and no peripheral access is initiated on the IPS bus. - * 0bxx0x..This peripheral allows write accesses. - * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an - * error response and no peripheral access is initiated on the IPS bus. - * 0bx0xx..This peripheral does not require supervisor privilege level for accesses. - * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must - * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must - * be set. If not, the access is terminated with an error response and no peripheral access is initiated - * on the IPS bus. - * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ. - */ -#define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group AIPSTZ_Register_Masks */ - - -/* AIPSTZ - Peripheral instance base addresses */ -/** Peripheral AIPSTZ1 base address */ -#define AIPSTZ1_BASE (0x40000000u) -/** Peripheral AIPSTZ1 base pointer */ -#define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE) -/** Peripheral AIPSTZ2 base address */ -#define AIPSTZ2_BASE (0x40400000u) -/** Peripheral AIPSTZ2 base pointer */ -#define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE) -/** Peripheral AIPSTZ3 base address */ -#define AIPSTZ3_BASE (0x40800000u) -/** Peripheral AIPSTZ3 base pointer */ -#define AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE) -/** Peripheral AIPSTZ4 base address */ -#define AIPSTZ4_BASE (0x40C00000u) -/** Peripheral AIPSTZ4 base pointer */ -#define AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE) -/** Array initializer of AIPSTZ peripheral base addresses */ -#define AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE } -/** Array initializer of AIPSTZ peripheral base pointers */ -#define AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 } - -/*! - * @} - */ /* end of group AIPSTZ_Peripheral_Access_Layer */ - - /* ---------------------------------------------------------------------------- -- ANADIG_LDO_SNVS Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -4366,100 +4448,69 @@ typedef struct { /*! @name PMU_LDO_LPSR_ANA - PMU_LDO_LPSR_ANA_REGISTER */ /*! @{ */ + #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK (0x1U) #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_SHIFT (0U) /*! REG_LP_EN - reg_lp_en */ #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TEST_OVERRIDE_MASK (0x2U) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TEST_OVERRIDE_SHIFT (1U) -/*! TEST_OVERRIDE - test_override - */ -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TEST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TEST_OVERRIDE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TEST_OVERRIDE_MASK) + #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK (0x4U) #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_SHIFT (2U) /*! REG_DISABLE - reg_disable */ #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK) + #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_MASK (0x8U) #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_SHIFT (3U) /*! PULL_DOWN_2MA_EN - pull_down_2ma_en */ #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_MASK) + #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_MASK (0x10U) #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_SHIFT (4U) -/*! LPSR_ANA_CONTROL_MODE - lpsr_ana_control_mode +/*! LPSR_ANA_CONTROL_MODE - LPSR_ANA_CONTROL_MODE + * 0b0..SW Control + * 0b1..HW Control */ #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_MASK) + #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK (0x20U) #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_SHIFT (5U) /*! BYPASS_MODE_EN - bypass_mode_en */ #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK) + #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_MASK (0x40U) #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_SHIFT (6U) /*! STANDBY_EN - standby_en */ #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_MASK) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TEST_EN_MASK (0x80U) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TEST_EN_SHIFT (7U) -/*! TEST_EN - test_en - */ -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TEST_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TEST_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TEST_EN_MASK) + #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_MASK (0x100U) #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_SHIFT (8U) /*! ALWAYS_4MA_PULLDOWN_EN - always_4ma_pulldown_en */ #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_MASK) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_PRECHRG_CURRENT_CFG_MASK (0x600U) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_PRECHRG_CURRENT_CFG_SHIFT (9U) -/*! BYPASS_PRECHRG_CURRENT_CFG - bypass_prechrg_current_cfg - */ -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_PRECHRG_CURRENT_CFG(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_PRECHRG_CURRENT_CFG_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_PRECHRG_CURRENT_CFG_MASK) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_CFG_MASK (0x1800U) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_CFG_SHIFT (11U) -/*! BYPASS_MODE_CFG - bypass_mode_cfg - */ -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_CFG(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_CFG_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_CFG_MASK) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ICP_TRIM_SNVS_MASK (0x6000U) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ICP_TRIM_SNVS_SHIFT (13U) -/*! ICP_TRIM_SNVS - Configure the current of the charge pump: 00: 300nA; 01:400nA; 10:500nA; 11:600nA - */ -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ICP_TRIM_SNVS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ICP_TRIM_SNVS_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ICP_TRIM_SNVS_MASK) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BO_EN_MASK (0x10000U) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BO_EN_SHIFT (16U) -/*! BO_EN - BO_EN - */ -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BO_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BO_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BO_EN_MASK) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BO_OFFSET_MASK (0x60000U) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BO_OFFSET_SHIFT (17U) -/*! BO_OFFSET - bo_offset - */ -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BO_OFFSET_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BO_OFFSET_MASK) + #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_MASK (0x80000U) #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_SHIFT (19U) -/*! TRACK_MODE_EN - track_mode_en +/*! TRACK_MODE_EN - Track Mode Enable + * 0b0..Normal use + * 0b1..Switch preparation */ #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_MASK) + #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_MASK (0x100000U) #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_SHIFT (20U) /*! PULL_DOWN_20UA_EN - pull_down_20ua_en */ #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_MASK) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRIM_MASK (0x1E00000U) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRIM_SHIFT (21U) -/*! TRIM - trim - */ -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRIM_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRIM_MASK) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TEST_SEL_MASK (0xC0000000U) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TEST_SEL_SHIFT (30U) -/*! TEST_SEL - test_sel - */ -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TEST_SEL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TEST_SEL_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TEST_SEL_MASK) /*! @} */ /*! @name PMU_LDO_LPSR_DIG_2 - PMU_LDO_LPSR_DIG_2_REGISTER */ /*! @{ */ + #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_MASK (0x3U) #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_SHIFT (0U) /*! VOLTAGE_STEP_INC - voltage_step_inc @@ -4469,116 +4520,76 @@ typedef struct { /*! @name PMU_LDO_LPSR_DIG - PMU_LDO_LPSR_DIG_REGISTER */ /*! @{ */ -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_HP_EN_MASK (0x1U) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_HP_EN_SHIFT (0U) -/*! REG_HP_EN - ENABLE_LINREG - */ -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_HP_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_HP_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_HP_EN_MASK) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TEST_OVERRIDE_MASK (0x2U) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TEST_OVERRIDE_SHIFT (1U) -/*! TEST_OVERRIDE - ENABLE_BO - */ -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TEST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TEST_OVERRIDE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TEST_OVERRIDE_MASK) + #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK (0x4U) #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_SHIFT (2U) /*! REG_EN - ENABLE_ILIMIT */ #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_RBB_STABLE_DETECT_MASK (0x8U) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_RBB_STABLE_DETECT_SHIFT (3U) -/*! RBB_STABLE_DETECT - ENABLE_PULLDOWN - */ -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_RBB_STABLE_DETECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_RBB_STABLE_DETECT_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_RBB_STABLE_DETECT_MASK) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_BO_MASK (0x10U) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_BO_SHIFT (4U) -/*! EN_BO - BO_OFFSET - */ -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_BO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_BO_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_BO_MASK) + #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_MASK (0x20U) #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_SHIFT (5U) -/*! LPSR_DIG_CONTROL_MODE - lpsr_dig_control_mode +/*! LPSR_DIG_CONTROL_MODE - LPSR_DIG_CONTROL_MODE + * 0b0..SW Control + * 0b1..HW Control */ #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_MASK) + #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN_MASK (0x40U) #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN_SHIFT (6U) /*! STANDBY_EN - standby_en */ #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN_MASK) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_TEST_MASK (0x80U) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_TEST_SHIFT (7U) -/*! EN_TEST - ENABLE_PWRUPLOAD - */ -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_TEST(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_TEST_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_TEST_MASK) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BO_OFFSET_MASK (0x300U) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BO_OFFSET_SHIFT (8U) -/*! BO_OFFSET - OUTPUT_TRG - */ -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BO_OFFSET_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BO_OFFSET_MASK) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_LOAD_2MA_MASK (0x400U) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_LOAD_2MA_SHIFT (10U) -/*! EN_LOAD_2MA - en_load_2ma - */ -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_LOAD_2MA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_LOAD_2MA_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_LOAD_2MA_MASK) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_LOAD_1MA_MASK (0x800U) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_LOAD_1MA_SHIFT (11U) -/*! EN_LOAD_1MA - EN_LOAD_1MA - */ -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_LOAD_1MA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_LOAD_1MA_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_LOAD_1MA_MASK) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_LOAD_200UA_MASK (0x1000U) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_LOAD_200UA_SHIFT (12U) -/*! EN_LOAD_200UA - en_load_200ua - */ -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_LOAD_200UA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_LOAD_200UA_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_LOAD_200UA_MASK) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_CUR_SENSE_MASK (0x2000U) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_CUR_SENSE_SHIFT (13U) -/*! EN_CUR_SENSE - en_cur_sense - */ -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_CUR_SENSE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_CUR_SENSE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_CUR_SENSE_MASK) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_RES_CONFIG_LP_MASK (0xC000U) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_RES_CONFIG_LP_SHIFT (14U) -/*! RES_CONFIG_LP - res_config_lp - */ -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_RES_CONFIG_LP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_RES_CONFIG_LP_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_RES_CONFIG_LP_MASK) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_LOAD_MASK (0x10000U) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_LOAD_SHIFT (16U) -/*! EN_LOAD - BO - */ -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_LOAD(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_LOAD_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_LOAD_MASK) + #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_MASK (0x20000U) #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_SHIFT (17U) /*! TRACKING_MODE - tracking_mode */ #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_MASK) + #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK (0x40000U) #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_SHIFT (18U) /*! BYPASS_MODE - bypass_mode */ #define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_LOW_SETPOINT_MASK (0x80000U) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_LOW_SETPOINT_SHIFT (19U) -/*! EN_LOW_SETPOINT - en_low_setpoint - */ -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_LOW_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_LOW_SETPOINT_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_EN_LOW_SETPOINT_MASK) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRIM_MASK (0x1F00000U) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRIM_SHIFT (20U) -/*! TRIM - REG_TEST - */ -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRIM_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRIM_MASK) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_RES_CONFIG_HP_MASK (0x6000000U) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_RES_CONFIG_HP_SHIFT (25U) -/*! RES_CONFIG_HP - res_config_hp - */ -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_RES_CONFIG_HP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_RES_CONFIG_HP_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_RES_CONFIG_HP_MASK) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_CP_CONFIG_LP_MASK (0x18000000U) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_CP_CONFIG_LP_SHIFT (27U) -/*! CP_CONFIG_LP - cp_config_lp - */ -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_CP_CONFIG_LP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_CP_CONFIG_LP_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_CP_CONFIG_LP_MASK) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_CP_CONFIG_HP_MASK (0x60000000U) -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_CP_CONFIG_HP_SHIFT (29U) -/*! CP_CONFIG_HP - cp_config_hp - */ -#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_CP_CONFIG_HP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_CP_CONFIG_HP_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_CP_CONFIG_HP_MASK) + +#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_MASK (0x1F00000U) +#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_SHIFT (20U) +/*! VOLTAGE_SELECT - VOLTAGE_SELECT + * 0b00000..Stable Voltage (range) + * 0b00001..Stable Voltage (range) + * 0b00010..Stable Voltage (range) + * 0b00011..Stable Voltage (range) + * 0b00100..Stable Voltage (range) + * 0b00101..Stable Voltage (range) + * 0b00110..Stable Voltage (range) + * 0b00111..Stable Voltage (range) + * 0b01000..Stable Voltage (range) + * 0b01001..Stable Voltage (range) + * 0b01010..Stable Voltage (range) + * 0b01011..Stable Voltage (range) + * 0b01100..Stable Voltage (range) + * 0b01101..Stable Voltage (range) + * 0b01110..Stable Voltage (range) + * 0b01111..Stable Voltage (range) + * 0b10000..Stable Voltage (range) + * 0b10001..Stable Voltage (range) + * 0b10010..Stable Voltage (range) + * 0b10011..Stable Voltage (range) + * 0b10100..Stable Voltage (range) + * 0b10101..Stable Voltage (range) + * 0b10110..Stable Voltage (range) + * 0b10111..Stable Voltage (range) + * 0b11000..Stable Voltage (range) + * 0b11001..Stable Voltage (range) + * 0b11010..Stable Voltage (range) + * 0b11011..Stable Voltage (range) + * 0b11100..Stable Voltage (range) + * 0b11101..Stable Voltage (range) + * 0b11110..Stable Voltage (range) + * 0b11111..Stable Voltage (range) + */ +#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_MASK) /*! @} */ @@ -4628,51 +4639,24 @@ typedef struct { /*! @name PMU_LDO_SNVS_DIG - PMU_LDO_SNVS_DIG_REGISTER */ /*! @{ */ + #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_MASK (0x1U) #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_SHIFT (0U) /*! REG_LP_EN - REG_LP_EN */ #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_SHIFT)) & ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_MASK) + #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE_MASK (0x2U) #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE_SHIFT (1U) /*! TEST_OVERRIDE - test_override */ #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE_SHIFT)) & ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE_MASK) + #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_MASK (0x4U) #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_SHIFT (2U) /*! REG_EN - REG_EN */ #define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_SHIFT)) & ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_MASK) -#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_EN_TEST_MASK (0x8U) -#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_EN_TEST_SHIFT (3U) -/*! EN_TEST - EN_TEST - */ -#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_EN_TEST(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_EN_TEST_SHIFT)) & ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_EN_TEST_MASK) -#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_CP_CONFIG_MASK (0x30U) -#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_CP_CONFIG_SHIFT (4U) -/*! CP_CONFIG - CP_CONFIG - */ -#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_CP_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_CP_CONFIG_SHIFT)) & ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_CP_CONFIG_MASK) -#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_RES_CONFIG_MASK (0xC0U) -#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_RES_CONFIG_SHIFT (6U) -/*! RES_CONFIG - RES_CONFIG - */ -#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_RES_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_RES_CONFIG_SHIFT)) & ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_RES_CONFIG_MASK) -#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TRIM_MASK (0x1F00U) -#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TRIM_SHIFT (8U) -/*! TRIM - trim - */ -#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TRIM_SHIFT)) & ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TRIM_MASK) -#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_ENB_PULLDOWN_MASK (0x2000U) -#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_ENB_PULLDOWN_SHIFT (13U) -/*! ENB_PULLDOWN - ENB_PULLDOWN - */ -#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_ENB_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_ENB_PULLDOWN_SHIFT)) & ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_ENB_PULLDOWN_MASK) -#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_STABLE_MASK (0x4000U) -#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_STABLE_SHIFT (14U) -/*! REG_STABLE - REG_STABLE - */ -#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_STABLE_SHIFT)) & ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_STABLE_MASK) /*! @} */ @@ -4708,46 +4692,44 @@ typedef struct { /** ANADIG_MISC - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[2048]; - __I uint32_t MISC_DIFPROG; /**< MISC_DIFPROG_REGISTER, offset: 0x800 */ - uint8_t RESERVED_1[12]; - __IO uint32_t LVDS_CTRL; /**< LVDS_CTRL_REGISTER, offset: 0x810 */ - uint8_t RESERVED_2[12]; + __I uint32_t MISC_DIFPROG; /**< Chip Silicon Version Register, offset: 0x800 */ + uint8_t RESERVED_1[28]; __IO uint32_t VDDSOC_AI_CTRL; /**< VDDSOC_AI_CTRL_REGISTER, offset: 0x820 */ - uint8_t RESERVED_3[12]; + uint8_t RESERVED_2[12]; __IO uint32_t VDDSOC_AI_WDATA; /**< VDDSOC_AI_WDATA_REGISTER, offset: 0x830 */ - uint8_t RESERVED_4[12]; + uint8_t RESERVED_3[12]; __I uint32_t VDDSOC_AI_RDATA; /**< VDDSOC_AI_RDATA_REGISTER, offset: 0x840 */ - uint8_t RESERVED_5[12]; + uint8_t RESERVED_4[12]; __IO uint32_t VDDSOC2PLL_AI_CTRL_1G; /**< VDDSOC2PLL_AI_CTRL_1G_REGISTER, offset: 0x850 */ - uint8_t RESERVED_6[12]; + uint8_t RESERVED_5[12]; __IO uint32_t VDDSOC2PLL_AI_WDATA_1G; /**< VDDSOC2PLL_AI_WDATA_1G_REGISTER, offset: 0x860 */ - uint8_t RESERVED_7[12]; + uint8_t RESERVED_6[12]; __I uint32_t VDDSOC2PLL_AI_RDATA_1G; /**< VDDSOC2PLL_AI_RDATA_1G_REGISTER, offset: 0x870 */ - uint8_t RESERVED_8[12]; + uint8_t RESERVED_7[12]; __IO uint32_t VDDSOC2PLL_AI_CTRL_AUDIO; /**< VDDSOC_AI_CTRL_AUDIO_REGISTER, offset: 0x880 */ - uint8_t RESERVED_9[12]; + uint8_t RESERVED_8[12]; __IO uint32_t VDDSOC2PLL_AI_WDATA_AUDIO; /**< VDDSOC_AI_WDATA_AUDIO_REGISTER, offset: 0x890 */ - uint8_t RESERVED_10[12]; + uint8_t RESERVED_9[12]; __I uint32_t VDDSOC2PLL_AI_RDATA_AUDIO; /**< VDDSOC2PLL_AI_RDATA_REGISTER, offset: 0x8A0 */ - uint8_t RESERVED_11[12]; + uint8_t RESERVED_10[12]; __IO uint32_t VDDSOC2PLL_AI_CTRL_VIDEO; /**< VDDSOC2PLL_AI_CTRL_VIDEO_REGISTER, offset: 0x8B0 */ - uint8_t RESERVED_12[12]; + uint8_t RESERVED_11[12]; __IO uint32_t VDDSOC2PLL_AI_WDATA_VIDEO; /**< VDDSOC2PLL_AI_WDATA_VIDEO_REGISTER, offset: 0x8C0 */ - uint8_t RESERVED_13[12]; + uint8_t RESERVED_12[12]; __I uint32_t VDDSOC2PLL_AI_RDATA_VIDEO; /**< VDDSOC2PLL_AI_RDATA_VIDEO_REGISTER, offset: 0x8D0 */ - uint8_t RESERVED_14[12]; + uint8_t RESERVED_13[12]; __IO uint32_t VDDLPSR_AI_CTRL; /**< VDDSOC_AI_CTRL_REGISTER, offset: 0x8E0 */ - uint8_t RESERVED_15[12]; + uint8_t RESERVED_14[12]; __IO uint32_t VDDLPSR_AI_WDATA; /**< VDDLPSR_AI_WDATA_REGISTER, offset: 0x8F0 */ - uint8_t RESERVED_16[12]; + uint8_t RESERVED_15[12]; __I uint32_t VDDLPSR_AI_RDATA_REFTOP; /**< VDDLPSR_AI_RDATA_REFTOP_REGISTER, offset: 0x900 */ - uint8_t RESERVED_17[12]; + uint8_t RESERVED_16[12]; __I uint32_t VDDLPSR_AI_RDATA_TMPSNS; /**< VDDLPSR_AI_RDATA_TMPSNS_REGISTER, offset: 0x910 */ - uint8_t RESERVED_18[12]; + uint8_t RESERVED_17[12]; __IO uint32_t VDDLPSR_AI400M_CTRL; /**< VDDLPSR_AI400M_CTRL_REGISTER, offset: 0x920 */ - uint8_t RESERVED_19[12]; + uint8_t RESERVED_18[12]; __IO uint32_t VDDLPSR_AI400M_WDATA; /**< VDDLPSR_AI400M_WDATA_REGISTER, offset: 0x930 */ - uint8_t RESERVED_20[12]; + uint8_t RESERVED_19[12]; __I uint32_t VDDLPSR_AI400M_RDATA; /**< VDDLPSR_AI400M_RDATA_REGISTER, offset: 0x940 */ } ANADIG_MISC_Type; @@ -4760,76 +4742,25 @@ typedef struct { * @{ */ -/*! @name MISC_DIFPROG - MISC_DIFPROG_REGISTER */ +/*! @name MISC_DIFPROG - Chip Silicon Version Register */ /*! @{ */ + #define ANADIG_MISC_MISC_DIFPROG_CHIPID_MASK (0xFFFFFFFFU) #define ANADIG_MISC_MISC_DIFPROG_CHIPID_SHIFT (0U) -/*! CHIPID - CHIPID +/*! CHIPID - Chip ID */ #define ANADIG_MISC_MISC_DIFPROG_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_MISC_DIFPROG_CHIPID_SHIFT)) & ANADIG_MISC_MISC_DIFPROG_CHIPID_MASK) /*! @} */ -/*! @name LVDS_CTRL - LVDS_CTRL_REGISTER */ -/*! @{ */ -#define ANADIG_MISC_LVDS_CTRL_LVDS_IPP_IBE_MASK (0x1U) -#define ANADIG_MISC_LVDS_CTRL_LVDS_IPP_IBE_SHIFT (0U) -/*! LVDS_IPP_IBE - lvds_ipp_ibe - */ -#define ANADIG_MISC_LVDS_CTRL_LVDS_IPP_IBE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_LVDS_CTRL_LVDS_IPP_IBE_SHIFT)) & ANADIG_MISC_LVDS_CTRL_LVDS_IPP_IBE_MASK) -#define ANADIG_MISC_LVDS_CTRL_LVDS_IPP_OBE_MASK (0x2U) -#define ANADIG_MISC_LVDS_CTRL_LVDS_IPP_OBE_SHIFT (1U) -/*! LVDS_IPP_OBE - lvds_ipp_obe - */ -#define ANADIG_MISC_LVDS_CTRL_LVDS_IPP_OBE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_LVDS_CTRL_LVDS_IPP_OBE_SHIFT)) & ANADIG_MISC_LVDS_CTRL_LVDS_IPP_OBE_MASK) -#define ANADIG_MISC_LVDS_CTRL_LVDS_DIV4_EN_MASK (0x4U) -#define ANADIG_MISC_LVDS_CTRL_LVDS_DIV4_EN_SHIFT (2U) -/*! LVDS_DIV4_EN - lvds_div4_en - */ -#define ANADIG_MISC_LVDS_CTRL_LVDS_DIV4_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_LVDS_CTRL_LVDS_DIV4_EN_SHIFT)) & ANADIG_MISC_LVDS_CTRL_LVDS_DIV4_EN_MASK) -#define ANADIG_MISC_LVDS_CTRL_LVDS_ANA_TEST_EN_MASK (0x8U) -#define ANADIG_MISC_LVDS_CTRL_LVDS_ANA_TEST_EN_SHIFT (3U) -/*! LVDS_ANA_TEST_EN - lvds_ana_test_en - */ -#define ANADIG_MISC_LVDS_CTRL_LVDS_ANA_TEST_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_LVDS_CTRL_LVDS_ANA_TEST_EN_SHIFT)) & ANADIG_MISC_LVDS_CTRL_LVDS_ANA_TEST_EN_MASK) -#define ANADIG_MISC_LVDS_CTRL_LVDS_SOURCE_MASK (0x30U) -#define ANADIG_MISC_LVDS_CTRL_LVDS_SOURCE_SHIFT (4U) -/*! LVDS_SOURCE - lvds_source - */ -#define ANADIG_MISC_LVDS_CTRL_LVDS_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_LVDS_CTRL_LVDS_SOURCE_SHIFT)) & ANADIG_MISC_LVDS_CTRL_LVDS_SOURCE_MASK) -#define ANADIG_MISC_LVDS_CTRL_LVDS_I_TRIM_MASK (0xC0U) -#define ANADIG_MISC_LVDS_CTRL_LVDS_I_TRIM_SHIFT (6U) -/*! LVDS_I_TRIM - lvds_i_trim - */ -#define ANADIG_MISC_LVDS_CTRL_LVDS_I_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_LVDS_CTRL_LVDS_I_TRIM_SHIFT)) & ANADIG_MISC_LVDS_CTRL_LVDS_I_TRIM_MASK) -#define ANADIG_MISC_LVDS_CTRL_LOWPWR_SETTLE_DETECT_EN_LPSR1P8_MASK (0x100U) -#define ANADIG_MISC_LVDS_CTRL_LOWPWR_SETTLE_DETECT_EN_LPSR1P8_SHIFT (8U) -/*! LOWPWR_SETTLE_DETECT_EN_LPSR1P8 - lowpwr_settle_detect_en_lpsr1p8 - */ -#define ANADIG_MISC_LVDS_CTRL_LOWPWR_SETTLE_DETECT_EN_LPSR1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_LVDS_CTRL_LOWPWR_SETTLE_DETECT_EN_LPSR1P8_SHIFT)) & ANADIG_MISC_LVDS_CTRL_LOWPWR_SETTLE_DETECT_EN_LPSR1P8_MASK) -#define ANADIG_MISC_LVDS_CTRL_BYPASS_CLK_SR_EN_MASK (0x1FFFE00U) -#define ANADIG_MISC_LVDS_CTRL_BYPASS_CLK_SR_EN_SHIFT (9U) -/*! BYPASS_CLK_SR_EN - bypass_clk_sr_en - */ -#define ANADIG_MISC_LVDS_CTRL_BYPASS_CLK_SR_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_LVDS_CTRL_BYPASS_CLK_SR_EN_SHIFT)) & ANADIG_MISC_LVDS_CTRL_BYPASS_CLK_SR_EN_MASK) -#define ANADIG_MISC_LVDS_CTRL_SEL_RC_48M_MASK (0x2000000U) -#define ANADIG_MISC_LVDS_CTRL_SEL_RC_48M_SHIFT (25U) -/*! SEL_RC_48M - sel_rc_48M - */ -#define ANADIG_MISC_LVDS_CTRL_SEL_RC_48M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_LVDS_CTRL_SEL_RC_48M_SHIFT)) & ANADIG_MISC_LVDS_CTRL_SEL_RC_48M_MASK) -#define ANADIG_MISC_LVDS_CTRL_LVDS_CLK_SEL_MASK (0x3C000000U) -#define ANADIG_MISC_LVDS_CTRL_LVDS_CLK_SEL_SHIFT (26U) -/*! LVDS_CLK_SEL - lvds_clk_sel - */ -#define ANADIG_MISC_LVDS_CTRL_LVDS_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_LVDS_CTRL_LVDS_CLK_SEL_SHIFT)) & ANADIG_MISC_LVDS_CTRL_LVDS_CLK_SEL_MASK) -/*! @} */ - /*! @name VDDSOC_AI_CTRL - VDDSOC_AI_CTRL_REGISTER */ /*! @{ */ + #define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK (0xFFU) #define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT (0U) /*! VDDSOC_AI_ADDR - VDDSOC_AI_ADDR */ #define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT)) & ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK) + #define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK (0x10000U) #define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_SHIFT (16U) /*! VDDSOC_AIRWB - VDDSOC_AIRWB @@ -4839,6 +4770,7 @@ typedef struct { /*! @name VDDSOC_AI_WDATA - VDDSOC_AI_WDATA_REGISTER */ /*! @{ */ + #define ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_MASK (0xFFFFFFFFU) #define ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_SHIFT (0U) /*! VDDSOC_AI_WDATA - VDDSOC_AI_WDATA @@ -4848,6 +4780,7 @@ typedef struct { /*! @name VDDSOC_AI_RDATA - VDDSOC_AI_RDATA_REGISTER */ /*! @{ */ + #define ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_MASK (0xFFFFFFFFU) #define ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_SHIFT (0U) /*! VDDSOC_AI_RDATA - VDDSOC_AI_RDATA @@ -4857,21 +4790,25 @@ typedef struct { /*! @name VDDSOC2PLL_AI_CTRL_1G - VDDSOC2PLL_AI_CTRL_1G_REGISTER */ /*! @{ */ + #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK (0xFFU) #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT (0U) /*! VDDSOC2PLL_AIADDR_1G - VDDSOC2PLL_AIADDR_1G */ #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK) + #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK (0x100U) #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_SHIFT (8U) /*! VDDSOC2PLL_AITOGGLE_1G - VDDSOC2PLL_AITOGGLE_1G */ #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK) + #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK (0x200U) #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_SHIFT (9U) /*! VDDSOC2PLL_AITOGGLE_DONE_1G - VDDSOC2PLL_AITOGGLE_DONE_1G */ #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK) + #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK (0x10000U) #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_SHIFT (16U) /*! VDDSOC2PLL_AIRWB_1G - VDDSOC2PLL_AIRWB_1G @@ -4881,6 +4818,7 @@ typedef struct { /*! @name VDDSOC2PLL_AI_WDATA_1G - VDDSOC2PLL_AI_WDATA_1G_REGISTER */ /*! @{ */ + #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_MASK (0xFFFFFFFFU) #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_SHIFT (0U) /*! VDDSOC2PLL_AI_WDATA_1G - VDDSOC2PLL_AI_WDATA_1G @@ -4890,6 +4828,7 @@ typedef struct { /*! @name VDDSOC2PLL_AI_RDATA_1G - VDDSOC2PLL_AI_RDATA_1G_REGISTER */ /*! @{ */ + #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_MASK (0xFFFFFFFFU) #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_SHIFT (0U) /*! VDDSOC2PLL_AI_RDATA_1G - VDDSOC2PLL_AI_RDATA_1G @@ -4899,21 +4838,25 @@ typedef struct { /*! @name VDDSOC2PLL_AI_CTRL_AUDIO - VDDSOC_AI_CTRL_AUDIO_REGISTER */ /*! @{ */ + #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK (0xFFU) #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT (0U) /*! VDDSOC2PLL_AI_ADDR_AUDIO - VDDSOC2PLL_AI_ADDR_AUDIO */ #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK) + #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK (0x100U) #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_SHIFT (8U) /*! VDDSOC2PLL_AITOGGLE_AUDIO - VDDSOC2PLL_AITOGGLE_AUDIO */ #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK) + #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK (0x200U) #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_SHIFT (9U) /*! VDDSOC2PLL_AITOGGLE_DONE_AUDIO - VDDSOC2PLL_AITOGGLE_DONE_AUDIO */ #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK) + #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK (0x10000U) #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_SHIFT (16U) /*! VDDSOC2PLL_AIRWB_AUDIO - VDDSOC_AIRWB @@ -4923,6 +4866,7 @@ typedef struct { /*! @name VDDSOC2PLL_AI_WDATA_AUDIO - VDDSOC_AI_WDATA_AUDIO_REGISTER */ /*! @{ */ + #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_MASK (0xFFFFFFFFU) #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_SHIFT (0U) /*! VDDSOC2PLL_AI_WDATA_AUDIO - VDDSOC2PLL_AI_WDATA_AUDIO @@ -4932,6 +4876,7 @@ typedef struct { /*! @name VDDSOC2PLL_AI_RDATA_AUDIO - VDDSOC2PLL_AI_RDATA_REGISTER */ /*! @{ */ + #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_MASK (0xFFFFFFFFU) #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_SHIFT (0U) /*! VDDSOC2PLL_AI_RDATA_AUDIO - VDDSOC2PLL_AI_RDATA_AUDIO @@ -4941,21 +4886,25 @@ typedef struct { /*! @name VDDSOC2PLL_AI_CTRL_VIDEO - VDDSOC2PLL_AI_CTRL_VIDEO_REGISTER */ /*! @{ */ + #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK (0xFFU) #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT (0U) /*! VDDSOC2PLL_AIADDR_VIDEO - VDDSOC2PLL_AIADDR_VIDEO */ #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK) + #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK (0x100U) #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_SHIFT (8U) /*! VDDSOC2PLL_AITOGGLE_VIDEO - VDDSOC2PLL_AITOGGLE_VIDEO */ #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK) + #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK (0x200U) #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_SHIFT (9U) /*! VDDSOC2PLL_AITOGGLE_DONE_VIDEO - VDDSOC2PLL_AITOGGLE_DONE_VIDEO */ #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK) + #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK (0x10000U) #define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_SHIFT (16U) /*! VDDSOC2PLL_AIRWB_VIDEO - VDDSOC2PLL_AIRWB_VIDEO @@ -4965,6 +4914,7 @@ typedef struct { /*! @name VDDSOC2PLL_AI_WDATA_VIDEO - VDDSOC2PLL_AI_WDATA_VIDEO_REGISTER */ /*! @{ */ + #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_MASK (0xFFFFFFFFU) #define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_SHIFT (0U) /*! VDDSOC2PLL_AI_WDATA_VIDEO - VDDSOC2PLL_AI_WDATA_VIDEO @@ -4974,6 +4924,7 @@ typedef struct { /*! @name VDDSOC2PLL_AI_RDATA_VIDEO - VDDSOC2PLL_AI_RDATA_VIDEO_REGISTER */ /*! @{ */ + #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_MASK (0xFFFFFFFFU) #define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_SHIFT (0U) /*! VDDSOC2PLL_AI_RDATA_VIDEO - VDDSOC2PLL_AI_RDATA_VIDEO @@ -4983,11 +4934,13 @@ typedef struct { /*! @name VDDLPSR_AI_CTRL - VDDSOC_AI_CTRL_REGISTER */ /*! @{ */ + #define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK (0xFFU) #define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT (0U) /*! VDDLPSR_AI_ADDR - VDDLPSR_AI_ADDR */ #define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK) + #define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK (0x10000U) #define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT (16U) /*! VDDLPSR_AIRWB - VDDLPSR_AIRWB @@ -4997,6 +4950,7 @@ typedef struct { /*! @name VDDLPSR_AI_WDATA - VDDLPSR_AI_WDATA_REGISTER */ /*! @{ */ + #define ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_MASK (0xFFFFFFFFU) #define ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_SHIFT (0U) /*! VDDLPSR_AI_WDATA - VDD_LPSR_AI_WDATA @@ -5006,6 +4960,7 @@ typedef struct { /*! @name VDDLPSR_AI_RDATA_REFTOP - VDDLPSR_AI_RDATA_REFTOP_REGISTER */ /*! @{ */ + #define ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_MASK (0xFFFFFFFFU) #define ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_SHIFT (0U) /*! VDDLPSR_AI_RDATA_REFTOP - VDDLPSR_AI_RDATA_REFTOP @@ -5015,6 +4970,7 @@ typedef struct { /*! @name VDDLPSR_AI_RDATA_TMPSNS - VDDLPSR_AI_RDATA_TMPSNS_REGISTER */ /*! @{ */ + #define ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_MASK (0xFFFFFFFFU) #define ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_SHIFT (0U) /*! VDDLPSR_AI_RDATA_TMPSNS - VDDLPSR_AI_RDATA_TMPSNS @@ -5024,21 +4980,25 @@ typedef struct { /*! @name VDDLPSR_AI400M_CTRL - VDDLPSR_AI400M_CTRL_REGISTER */ /*! @{ */ + #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK (0xFFU) #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT (0U) /*! VDDLPSR_AI400M_ADDR - VDDLPSR_AI400M_ADDR */ #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK) + #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK (0x100U) #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_SHIFT (8U) /*! VDDLPSR_AITOGGLE_400M - VDDLPSR_AITOGGLE_400M */ #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK) + #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK (0x200U) #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_SHIFT (9U) /*! VDDLPSR_AITOGGLE_DONE_400M - VDDLPSR_AITOGGLE_DONE_400M */ #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK) + #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK (0x10000U) #define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_SHIFT (16U) /*! VDDLPSR_AI400M_RWB - VDDLPSR_AI400M_RWB @@ -5048,6 +5008,7 @@ typedef struct { /*! @name VDDLPSR_AI400M_WDATA - VDDLPSR_AI400M_WDATA_REGISTER */ /*! @{ */ + #define ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_MASK (0xFFFFFFFFU) #define ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_SHIFT (0U) /*! VDDLPSR_AI400M_WDATA - VDDLPSR_AI400M_WDATA @@ -5057,6 +5018,7 @@ typedef struct { /*! @name VDDLPSR_AI400M_RDATA - VDDLPSR_AI400M_RDATA_REGISTER */ /*! @{ */ + #define ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_MASK (0xFFFFFFFFU) #define ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_SHIFT (0U) /*! VDDLPSR_AI400M_RDATA - VDDLPSR_AI400M_RDATA @@ -5096,31 +5058,18 @@ typedef struct { /** ANADIG_OSC - Register Layout Typedef */ typedef struct { - __IO uint32_t ANATOP_CTRL; /**< ANATOP_CTRL_REGISTER, offset: 0x0 */ - uint8_t RESERVED_0[12]; - __IO uint32_t OSC_48M_CTRL; /**< OSC_48M_CTRL_REGISTER, offset: 0x10 */ + uint8_t RESERVED_0[16]; + __IO uint32_t OSC_48M_CTRL; /**< 48MHz RCOSC Control Register, offset: 0x10 */ uint8_t RESERVED_1[12]; - __IO uint32_t OSC_24M_CTRL; /**< OSC_24M_CTRL_REGISTER, offset: 0x20 */ - uint8_t RESERVED_2[12]; - __IO uint32_t OSC_32K_CTRL; /**< OSC_32K_CTRL_REGISTER, offset: 0x30 */ + __IO uint32_t OSC_24M_CTRL; /**< 24MHz OSC Control Register, offset: 0x20 */ + uint8_t RESERVED_2[28]; + __I uint32_t OSC_400M_CTRL0; /**< 400MHz RCOSC Control0 Register, offset: 0x40 */ uint8_t RESERVED_3[12]; - __I uint32_t OSC_200M_CTRL0; /**< OSC_200M_CTRL0_REGISTER, offset: 0x40 */ + __IO uint32_t OSC_400M_CTRL1; /**< 400MHz RCOSC Control1 Register, offset: 0x50 */ uint8_t RESERVED_4[12]; - __IO uint32_t OSC_200M_CTRL1; /**< OSC_200M_CTRL1_REGISTER, offset: 0x50 */ - uint8_t RESERVED_5[12]; - __IO uint32_t OSC_200M_CTRL2; /**< OSC_200M_CTRL2_REGISTER, offset: 0x60 */ - uint8_t RESERVED_6[92]; - __IO uint32_t OSC_4M16M_CTRL; /**< OSC_4M16M_CTRL_REGISTER, offset: 0xC0 */ - uint8_t RESERVED_7[12]; - __IO uint32_t OSC_4M16M_TRIM; /**< OSC_4M16M_TRIM_REGISTER, offset: 0xD0 */ - uint8_t RESERVED_8[12]; - __I uint32_t OSC_OTP_TRIM_VALUE_48M; /**< OSC_OTP_TIM_VALUE_48M_REGISTER, offset: 0xE0 */ - uint8_t RESERVED_9[12]; - __I uint32_t OSC_OTP_TRIM_VALUE_16M; /**< OSC_OTP_TRIM_VALUE_16M_REGISTER, offset: 0xF0 */ - uint8_t RESERVED_10[12]; - __I uint32_t OSC_OTP_TRIM_VALUE_XTAL_FREQ; /**< OSC_OTP_TRIM_VALUE_XTAL_FREQ_REGISTER, offset: 0x100 */ - uint8_t RESERVED_11[12]; - __I uint32_t OSC_OTP_TRIM_VALUE_200M; /**< OSC_OTP_TRIM_VALUE_200M_REGISTER, offset: 0x110 */ + __IO uint32_t OSC_400M_CTRL2; /**< 400MHz RCOSC Control2 Register, offset: 0x60 */ + uint8_t RESERVED_5[92]; + __IO uint32_t OSC_16M_CTRL; /**< 16MHz RCOSC Control Register, offset: 0xC0 */ } ANADIG_OSC_Type; /* ---------------------------------------------------------------------------- @@ -5132,376 +5081,206 @@ typedef struct { * @{ */ -/*! @name ANATOP_CTRL - ANATOP_CTRL_REGISTER */ +/*! @name OSC_48M_CTRL - 48MHz RCOSC Control Register */ /*! @{ */ -#define ANADIG_OSC_ANATOP_CTRL_ANATOP_MODE_MASK (0x1U) -#define ANADIG_OSC_ANATOP_CTRL_ANATOP_MODE_SHIFT (0U) -/*! ANATOP_MODE - ANATOP_MODE - */ -#define ANADIG_OSC_ANATOP_CTRL_ANATOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_ANATOP_CTRL_ANATOP_MODE_SHIFT)) & ANADIG_OSC_ANATOP_CTRL_ANATOP_MODE_MASK) -#define ANADIG_OSC_ANATOP_CTRL_TRIM_SW_FORCE_MASK (0x2U) -#define ANADIG_OSC_ANATOP_CTRL_TRIM_SW_FORCE_SHIFT (1U) -/*! TRIM_SW_FORCE - TRIM_SW_FORCE - */ -#define ANADIG_OSC_ANATOP_CTRL_TRIM_SW_FORCE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_ANATOP_CTRL_TRIM_SW_FORCE_SHIFT)) & ANADIG_OSC_ANATOP_CTRL_TRIM_SW_FORCE_MASK) -#define ANADIG_OSC_ANATOP_CTRL_TRIM_SW_FORCE_16M_MASK (0x4U) -#define ANADIG_OSC_ANATOP_CTRL_TRIM_SW_FORCE_16M_SHIFT (2U) -/*! TRIM_SW_FORCE_16M - TRIM_SW_FORCE_16M - */ -#define ANADIG_OSC_ANATOP_CTRL_TRIM_SW_FORCE_16M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_ANATOP_CTRL_TRIM_SW_FORCE_16M_SHIFT)) & ANADIG_OSC_ANATOP_CTRL_TRIM_SW_FORCE_16M_MASK) -/*! @} */ -/*! @name OSC_48M_CTRL - OSC_48M_CTRL_REGISTER */ -/*! @{ */ -#define ANADIG_OSC_OSC_48M_CTRL_TTEST_CURRENT_MASK (0x1U) -#define ANADIG_OSC_OSC_48M_CTRL_TTEST_CURRENT_SHIFT (0U) -/*! TTEST_CURRENT - rc48m_ttest_current_lv - */ -#define ANADIG_OSC_OSC_48M_CTRL_TTEST_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_TTEST_CURRENT_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_TTEST_CURRENT_MASK) #define ANADIG_OSC_OSC_48M_CTRL_TEN_MASK (0x2U) #define ANADIG_OSC_OSC_48M_CTRL_TEN_SHIFT (1U) -/*! TEN - rc48m_ten_lv +/*! TEN - 48MHz RCOSC Enable + * 0b0..Power down + * 0b1..Power up */ #define ANADIG_OSC_OSC_48M_CTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_TEN_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_TEN_MASK) -#define ANADIG_OSC_OSC_48M_CTRL_TTEST_BG_MASK (0x4U) -#define ANADIG_OSC_OSC_48M_CTRL_TTEST_BG_SHIFT (2U) -/*! TTEST_BG - rc48m_ttest_bg_lv - */ -#define ANADIG_OSC_OSC_48M_CTRL_TTEST_BG(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_TTEST_BG_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_TTEST_BG_MASK) -#define ANADIG_OSC_OSC_48M_CTRL_TUPDATE_MASK (0x8U) -#define ANADIG_OSC_OSC_48M_CTRL_TUPDATE_SHIFT (3U) -/*! TUPDATE - rc48m_tupdate_lv - */ -#define ANADIG_OSC_OSC_48M_CTRL_TUPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_TUPDATE_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_TUPDATE_MASK) -#define ANADIG_OSC_OSC_48M_CTRL_TTRIM_COARSE_MASK (0x3F0U) -#define ANADIG_OSC_OSC_48M_CTRL_TTRIM_COARSE_SHIFT (4U) -/*! TTRIM_COARSE - rc48m_ttrim_coarse_lv - */ -#define ANADIG_OSC_OSC_48M_CTRL_TTRIM_COARSE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_TTRIM_COARSE_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_TTRIM_COARSE_MASK) -#define ANADIG_OSC_OSC_48M_CTRL_TTRIM_FINE_MASK (0x1FC00U) -#define ANADIG_OSC_OSC_48M_CTRL_TTRIM_FINE_SHIFT (10U) -/*! TTRIM_FINE - rc48m_ttrim_fine_lv - */ -#define ANADIG_OSC_OSC_48M_CTRL_TTRIM_FINE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_TTRIM_FINE_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_TTRIM_FINE_MASK) -#define ANADIG_OSC_OSC_48M_CTRL_TTRIM_RANGE_MASK (0x60000U) -#define ANADIG_OSC_OSC_48M_CTRL_TTRIM_RANGE_SHIFT (17U) -/*! TTRIM_RANGE - rc48m_ttrim_range_lv - */ -#define ANADIG_OSC_OSC_48M_CTRL_TTRIM_RANGE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_TTRIM_RANGE_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_TTRIM_RANGE_MASK) -#define ANADIG_OSC_OSC_48M_CTRL_TRIM_TEMPCO_MASK (0xF80000U) -#define ANADIG_OSC_OSC_48M_CTRL_TRIM_TEMPCO_SHIFT (19U) -/*! TRIM_TEMPCO - TRIM_TEMPCO - */ -#define ANADIG_OSC_OSC_48M_CTRL_TRIM_TEMPCO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_TRIM_TEMPCO_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_TRIM_TEMPCO_MASK) + #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK (0x1000000U) #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_SHIFT (24U) -/*! RC_48M_DIV2_EN - rc_48m_div2_en +/*! RC_48M_DIV2_EN - RCOSC_48M_DIV2 Enable + * 0b0..Disable + * 0b1..Enable */ #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK) + #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_MASK (0x40000000U) #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_SHIFT (30U) -/*! RC_48M_DIV2_CONTROL_MODE - rc_48m_div2_control_mode +/*! RC_48M_DIV2_CONTROL_MODE - RCOSC_48M_DIV2 Control Mode + * 0b0..Software mode (default) + * 0b1..GPC mode (Setpoint) */ #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_MASK) + #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_MASK (0x80000000U) #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_SHIFT (31U) -/*! RC_48M_CONTROL_MODE - rc_48m_control_mode +/*! RC_48M_CONTROL_MODE - 48MHz RCOSC Control Mode + * 0b0..Software mode (default) + * 0b1..GPC mode (Setpoint) */ #define ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_MASK) /*! @} */ -/*! @name OSC_24M_CTRL - OSC_24M_CTRL_REGISTER */ +/*! @name OSC_24M_CTRL - 24MHz OSC Control Register */ /*! @{ */ + #define ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_MASK (0x1U) #define ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_SHIFT (0U) -/*! BYPASS_CLK - osc24m_bypass_clk_1p8v +/*! BYPASS_CLK - 24MHz OSC Bypass Clock */ #define ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_MASK) + #define ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_MASK (0x2U) #define ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_SHIFT (1U) -/*! BYPASS_EN - osc24m_bypass_en_lv +/*! BYPASS_EN - 24MHz OSC Bypass Enable + * 0b0..Disable + * 0b1..Enable */ #define ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_MASK) + #define ANADIG_OSC_OSC_24M_CTRL_LP_EN_MASK (0x4U) #define ANADIG_OSC_OSC_24M_CTRL_LP_EN_SHIFT (2U) -/*! LP_EN - osc24m_lp_en_lv +/*! LP_EN - 24MHz OSC Low-Power Mode Enable + * 0b0..High Gain mode (HP) + * 0b1..Low-power mode (LP) */ #define ANADIG_OSC_OSC_24M_CTRL_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_LP_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_LP_EN_MASK) + #define ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_MASK (0x8U) #define ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_SHIFT (3U) -/*! OSC_COMP_MODE - osc24m_osc_comp_mode_lv +/*! OSC_COMP_MODE - 24MHz OSC Comparator Mode + * 0b0..Single-ended mode (default) + * 0b1..Differential mode (test mode) */ #define ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_MASK) + #define ANADIG_OSC_OSC_24M_CTRL_OSC_EN_MASK (0x10U) #define ANADIG_OSC_OSC_24M_CTRL_OSC_EN_SHIFT (4U) -/*! OSC_EN - osc24m_osc_en_lv +/*! OSC_EN - 24MHz OSC Enable + * 0b0..Disable + * 0b1..Enable */ #define ANADIG_OSC_OSC_24M_CTRL_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_EN_MASK) -#define ANADIG_OSC_OSC_24M_CTRL_OSC_TEST_EN_MASK (0x20U) -#define ANADIG_OSC_OSC_24M_CTRL_OSC_TEST_EN_SHIFT (5U) -/*! OSC_TEST_EN - osc24m_osc_test_en_lv - */ -#define ANADIG_OSC_OSC_24M_CTRL_OSC_TEST_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_TEST_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_TEST_EN_MASK) -#define ANADIG_OSC_OSC_24M_CTRL_OSC_TESTALC_EN_MASK (0x40U) -#define ANADIG_OSC_OSC_24M_CTRL_OSC_TESTALC_EN_SHIFT (6U) -/*! OSC_TESTALC_EN - osc24m_osc_testalc_en_lv - */ -#define ANADIG_OSC_OSC_24M_CTRL_OSC_TESTALC_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_TESTALC_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_TESTALC_EN_MASK) + #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK (0x80U) #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_SHIFT (7U) -/*! OSC_24M_GATE - osc_24m_gate +/*! OSC_24M_GATE - 24MHz OSC Gate Control + * 0b0..Not Gated + * 0b1..Gated */ #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK) + #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK (0x40000000U) #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_SHIFT (30U) -/*! OSC_24M_STABLE - osc_24m_stable +/*! OSC_24M_STABLE - 24MHz OSC Stable + * 0b0..Not Stable + * 0b1..Stable */ #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK) + #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_MASK (0x80000000U) #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_SHIFT (31U) -/*! OSC_24M_CONTROL_MODE - osc_24m_control_mode +/*! OSC_24M_CONTROL_MODE - 24MHz OSC Control Mode + * 0b0..Software mode (default) + * 0b1..GPC mode (Setpoint) */ #define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_MASK) /*! @} */ -/*! @name OSC_32K_CTRL - OSC_32K_CTRL_REGISTER */ +/*! @name OSC_400M_CTRL0 - 400MHz RCOSC Control0 Register */ /*! @{ */ -#define ANADIG_OSC_OSC_32K_CTRL_RTC_XTAL_SOURCE_MASK (0x1U) -#define ANADIG_OSC_OSC_32K_CTRL_RTC_XTAL_SOURCE_SHIFT (0U) -/*! RTC_XTAL_SOURCE - This bit is reserved - */ -#define ANADIG_OSC_OSC_32K_CTRL_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_32K_CTRL_RTC_XTAL_SOURCE_SHIFT)) & ANADIG_OSC_OSC_32K_CTRL_RTC_XTAL_SOURCE_MASK) -/*! @} */ -/*! @name OSC_200M_CTRL0 - OSC_200M_CTRL0_REGISTER */ -/*! @{ */ -#define ANADIG_OSC_OSC_200M_CTRL0_OSC200M_AI_BUSY_MASK (0x80000000U) -#define ANADIG_OSC_OSC_200M_CTRL0_OSC200M_AI_BUSY_SHIFT (31U) -/*! OSC200M_AI_BUSY - osc200m_ai_busy +#define ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_MASK (0x80000000U) +#define ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_SHIFT (31U) +/*! OSC400M_AI_BUSY - 400MHz OSC AI BUSY */ -#define ANADIG_OSC_OSC_200M_CTRL0_OSC200M_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_200M_CTRL0_OSC200M_AI_BUSY_SHIFT)) & ANADIG_OSC_OSC_200M_CTRL0_OSC200M_AI_BUSY_MASK) +#define ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_MASK) /*! @} */ -/*! @name OSC_200M_CTRL1 - OSC_200M_CTRL1_REGISTER */ +/*! @name OSC_400M_CTRL1 - 400MHz RCOSC Control1 Register */ /*! @{ */ -#define ANADIG_OSC_OSC_200M_CTRL1_PWD_MASK (0x1U) -#define ANADIG_OSC_OSC_200M_CTRL1_PWD_SHIFT (0U) -/*! PWD - power down control - */ -#define ANADIG_OSC_OSC_200M_CTRL1_PWD(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_200M_CTRL1_PWD_SHIFT)) & ANADIG_OSC_OSC_200M_CTRL1_PWD_MASK) -#define ANADIG_OSC_OSC_200M_CTRL1_CLKGATE_200MEG_MASK (0x2U) -#define ANADIG_OSC_OSC_200M_CTRL1_CLKGATE_200MEG_SHIFT (1U) -/*! CLKGATE_200MEG - clock gate control for 200m - */ -#define ANADIG_OSC_OSC_200M_CTRL1_CLKGATE_200MEG(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_200M_CTRL1_CLKGATE_200MEG_SHIFT)) & ANADIG_OSC_OSC_200M_CTRL1_CLKGATE_200MEG_MASK) -#define ANADIG_OSC_OSC_200M_CTRL1_CLKGATE_25MEG_MASK (0x4U) -#define ANADIG_OSC_OSC_200M_CTRL1_CLKGATE_25MEG_SHIFT (2U) -/*! CLKGATE_25MEG - clock gate control for 25m - */ -#define ANADIG_OSC_OSC_200M_CTRL1_CLKGATE_25MEG(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_200M_CTRL1_CLKGATE_25MEG_SHIFT)) & ANADIG_OSC_OSC_200M_CTRL1_CLKGATE_25MEG_MASK) -#define ANADIG_OSC_OSC_200M_CTRL1_RC_400M_CONTROL_MODE_MASK (0x80000000U) -#define ANADIG_OSC_OSC_200M_CTRL1_RC_400M_CONTROL_MODE_SHIFT (31U) -/*! RC_400M_CONTROL_MODE - rc_400m_control_mode - */ -#define ANADIG_OSC_OSC_200M_CTRL1_RC_400M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_200M_CTRL1_RC_400M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_200M_CTRL1_RC_400M_CONTROL_MODE_MASK) -/*! @} */ -/*! @name OSC_200M_CTRL2 - OSC_200M_CTRL2_REGISTER */ -/*! @{ */ -#define ANADIG_OSC_OSC_200M_CTRL2_ENABLE_CLK_MASK (0x1U) -#define ANADIG_OSC_OSC_200M_CTRL2_ENABLE_CLK_SHIFT (0U) -/*! ENABLE_CLK - ENABLE_CLK - */ -#define ANADIG_OSC_OSC_200M_CTRL2_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_200M_CTRL2_ENABLE_CLK_SHIFT)) & ANADIG_OSC_OSC_200M_CTRL2_ENABLE_CLK_MASK) -#define ANADIG_OSC_OSC_200M_CTRL2_TUNE_BYP_MASK (0x400U) -#define ANADIG_OSC_OSC_200M_CTRL2_TUNE_BYP_SHIFT (10U) -/*! TUNE_BYP - TUNE_BYP - */ -#define ANADIG_OSC_OSC_200M_CTRL2_TUNE_BYP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_200M_CTRL2_TUNE_BYP_SHIFT)) & ANADIG_OSC_OSC_200M_CTRL2_TUNE_BYP_MASK) -#define ANADIG_OSC_OSC_200M_CTRL2_OSC_TUNE_VAL_MASK (0xFF000000U) -#define ANADIG_OSC_OSC_200M_CTRL2_OSC_TUNE_VAL_SHIFT (24U) -/*! OSC_TUNE_VAL - OSC_TUNE_VAL +#define ANADIG_OSC_OSC_400M_CTRL1_PWD_MASK (0x1U) +#define ANADIG_OSC_OSC_400M_CTRL1_PWD_SHIFT (0U) +/*! PWD - Power down control for 400MHz RCOSC + * 0b0..No Power down + * 0b1..Power down */ -#define ANADIG_OSC_OSC_200M_CTRL2_OSC_TUNE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_200M_CTRL2_OSC_TUNE_VAL_SHIFT)) & ANADIG_OSC_OSC_200M_CTRL2_OSC_TUNE_VAL_MASK) -/*! @} */ +#define ANADIG_OSC_OSC_400M_CTRL1_PWD(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_PWD_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_PWD_MASK) -/*! @name OSC_4M16M_CTRL - OSC_4M16M_CTRL_REGISTER */ -/*! @{ */ -#define ANADIG_OSC_OSC_4M16M_CTRL_EN_LPO1K_MASK (0x1U) -#define ANADIG_OSC_OSC_4M16M_CTRL_EN_LPO1K_SHIFT (0U) -/*! EN_LPO1K - rc4m_en_LPO1K_1p8v - */ -#define ANADIG_OSC_OSC_4M16M_CTRL_EN_LPO1K(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_4M16M_CTRL_EN_LPO1K_SHIFT)) & ANADIG_OSC_OSC_4M16M_CTRL_EN_LPO1K_MASK) -#define ANADIG_OSC_OSC_4M16M_CTRL_EN_IRC4M16M_MASK (0x2U) -#define ANADIG_OSC_OSC_4M16M_CTRL_EN_IRC4M16M_SHIFT (1U) -/*! EN_IRC4M16M - rc4m_en_irc4M16M_1p8v - */ -#define ANADIG_OSC_OSC_4M16M_CTRL_EN_IRC4M16M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_4M16M_CTRL_EN_IRC4M16M_SHIFT)) & ANADIG_OSC_OSC_4M16M_CTRL_EN_IRC4M16M_MASK) -#define ANADIG_OSC_OSC_4M16M_CTRL_SEL_16M_MASK (0x4U) -#define ANADIG_OSC_OSC_4M16M_CTRL_SEL_16M_SHIFT (2U) -/*! SEL_16M - sel_16M - */ -#define ANADIG_OSC_OSC_4M16M_CTRL_SEL_16M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_4M16M_CTRL_SEL_16M_SHIFT)) & ANADIG_OSC_OSC_4M16M_CTRL_SEL_16M_MASK) -#define ANADIG_OSC_OSC_4M16M_CTRL_EN_POWER_SAVE_MASK (0x8U) -#define ANADIG_OSC_OSC_4M16M_CTRL_EN_POWER_SAVE_SHIFT (3U) -/*! EN_POWER_SAVE - en_power_save - */ -#define ANADIG_OSC_OSC_4M16M_CTRL_EN_POWER_SAVE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_4M16M_CTRL_EN_POWER_SAVE_SHIFT)) & ANADIG_OSC_OSC_4M16M_CTRL_EN_POWER_SAVE_MASK) -#define ANADIG_OSC_OSC_4M16M_CTRL_ANALOG_TEST_MASK (0xF0U) -#define ANADIG_OSC_OSC_4M16M_CTRL_ANALOG_TEST_SHIFT (4U) -/*! ANALOG_TEST - analog_test - */ -#define ANADIG_OSC_OSC_4M16M_CTRL_ANALOG_TEST(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_4M16M_CTRL_ANALOG_TEST_SHIFT)) & ANADIG_OSC_OSC_4M16M_CTRL_ANALOG_TEST_MASK) -#define ANADIG_OSC_OSC_4M16M_CTRL_SOURCE_SEL_16M_MASK (0x100U) -#define ANADIG_OSC_OSC_4M16M_CTRL_SOURCE_SEL_16M_SHIFT (8U) -/*! SOURCE_SEL_16M - source_sel_16M +#define ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK (0x2U) +#define ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_SHIFT (1U) +/*! CLKGATE_400MEG - Clock gate control for 400MHz RCOSC + * 0b0..Not Gated + * 0b1..Gated */ -#define ANADIG_OSC_OSC_4M16M_CTRL_SOURCE_SEL_16M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_4M16M_CTRL_SOURCE_SEL_16M_SHIFT)) & ANADIG_OSC_OSC_4M16M_CTRL_SOURCE_SEL_16M_MASK) -#define ANADIG_OSC_OSC_4M16M_CTRL_off_mode_MASK (0x40000000U) -#define ANADIG_OSC_OSC_4M16M_CTRL_off_mode_SHIFT (30U) -/*! off_mode - off_mode - */ -#define ANADIG_OSC_OSC_4M16M_CTRL_off_mode(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_4M16M_CTRL_off_mode_SHIFT)) & ANADIG_OSC_OSC_4M16M_CTRL_off_mode_MASK) -#define ANADIG_OSC_OSC_4M16M_CTRL_RC_16M_CONTROL_MODE_MASK (0x80000000U) -#define ANADIG_OSC_OSC_4M16M_CTRL_RC_16M_CONTROL_MODE_SHIFT (31U) -/*! RC_16M_CONTROL_MODE - rc_16m_control_mode - */ -#define ANADIG_OSC_OSC_4M16M_CTRL_RC_16M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_4M16M_CTRL_RC_16M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_4M16M_CTRL_RC_16M_CONTROL_MODE_MASK) -/*! @} */ +#define ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK) -/*! @name OSC_4M16M_TRIM - OSC_4M16M_TRIM_REGISTER */ -/*! @{ */ -#define ANADIG_OSC_OSC_4M16M_TRIM_TRIM_DLY_MASK (0xFU) -#define ANADIG_OSC_OSC_4M16M_TRIM_TRIM_DLY_SHIFT (0U) -/*! TRIM_DLY - rc4m_trim_dly_1p8v - */ -#define ANADIG_OSC_OSC_4M16M_TRIM_TRIM_DLY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_4M16M_TRIM_TRIM_DLY_SHIFT)) & ANADIG_OSC_OSC_4M16M_TRIM_TRIM_DLY_MASK) -#define ANADIG_OSC_OSC_4M16M_TRIM_TRIM_TEMPCO_MASK (0xF0U) -#define ANADIG_OSC_OSC_4M16M_TRIM_TRIM_TEMPCO_SHIFT (4U) -/*! TRIM_TEMPCO - trim_tempco - */ -#define ANADIG_OSC_OSC_4M16M_TRIM_TRIM_TEMPCO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_4M16M_TRIM_TRIM_TEMPCO_SHIFT)) & ANADIG_OSC_OSC_4M16M_TRIM_TRIM_TEMPCO_MASK) -#define ANADIG_OSC_OSC_4M16M_TRIM_TRIM_LPO1K_MASK (0x3F00U) -#define ANADIG_OSC_OSC_4M16M_TRIM_TRIM_LPO1K_SHIFT (8U) -/*! TRIM_LPO1K - rc4m_trim_LPO1K_1p8v +#define ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_MASK (0x80000000U) +#define ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_SHIFT (31U) +/*! RC_400M_CONTROL_MODE - 400MHz RCOSC Control mode + * 0b0..Software mode (default) + * 0b1..GPC mode (Setpoint) */ -#define ANADIG_OSC_OSC_4M16M_TRIM_TRIM_LPO1K(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_4M16M_TRIM_TRIM_LPO1K_SHIFT)) & ANADIG_OSC_OSC_4M16M_TRIM_TRIM_LPO1K_MASK) -#define ANADIG_OSC_OSC_4M16M_TRIM_TRIM_IREF_MASK (0x7C000U) -#define ANADIG_OSC_OSC_4M16M_TRIM_TRIM_IREF_SHIFT (14U) -/*! TRIM_IREF - trim_iref - */ -#define ANADIG_OSC_OSC_4M16M_TRIM_TRIM_IREF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_4M16M_TRIM_TRIM_IREF_SHIFT)) & ANADIG_OSC_OSC_4M16M_TRIM_TRIM_IREF_MASK) -#define ANADIG_OSC_OSC_4M16M_TRIM_TRIM_FINE_MASK (0xF80000U) -#define ANADIG_OSC_OSC_4M16M_TRIM_TRIM_FINE_SHIFT (19U) -/*! TRIM_FINE - rc4m_trim_fine_1p8v - */ -#define ANADIG_OSC_OSC_4M16M_TRIM_TRIM_FINE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_4M16M_TRIM_TRIM_FINE_SHIFT)) & ANADIG_OSC_OSC_4M16M_TRIM_TRIM_FINE_MASK) -#define ANADIG_OSC_OSC_4M16M_TRIM_RC4M_trim_COARSE_1P8V_MASK (0x1F000000U) -#define ANADIG_OSC_OSC_4M16M_TRIM_RC4M_trim_COARSE_1P8V_SHIFT (24U) -/*! RC4M_trim_COARSE_1P8V - trim_coarse - */ -#define ANADIG_OSC_OSC_4M16M_TRIM_RC4M_trim_COARSE_1P8V(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_4M16M_TRIM_RC4M_trim_COARSE_1P8V_SHIFT)) & ANADIG_OSC_OSC_4M16M_TRIM_RC4M_trim_COARSE_1P8V_MASK) +#define ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_MASK) /*! @} */ -/*! @name OSC_OTP_TRIM_VALUE_48M - OSC_OTP_TIM_VALUE_48M_REGISTER */ +/*! @name OSC_400M_CTRL2 - 400MHz RCOSC Control2 Register */ /*! @{ */ -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_48M_OSC_48M_TRIM_TEMPCO_MASK (0x1FU) -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_48M_OSC_48M_TRIM_TEMPCO_SHIFT (0U) -/*! OSC_48M_TRIM_TEMPCO - osc_48m_trim_tempco - */ -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_48M_OSC_48M_TRIM_TEMPCO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_OTP_TRIM_VALUE_48M_OSC_48M_TRIM_TEMPCO_SHIFT)) & ANADIG_OSC_OSC_OTP_TRIM_VALUE_48M_OSC_48M_TRIM_TEMPCO_MASK) -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_48M_OSC_48M_TRIM_RANGE_MASK (0x60U) -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_48M_OSC_48M_TRIM_RANGE_SHIFT (5U) -/*! OSC_48M_TRIM_RANGE - osc_48m_trim_range - */ -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_48M_OSC_48M_TRIM_RANGE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_OTP_TRIM_VALUE_48M_OSC_48M_TRIM_RANGE_SHIFT)) & ANADIG_OSC_OSC_OTP_TRIM_VALUE_48M_OSC_48M_TRIM_RANGE_MASK) -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_48M_OSC_48M_TRIM_FINE_MASK (0x3F80U) -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_48M_OSC_48M_TRIM_FINE_SHIFT (7U) -/*! OSC_48M_TRIM_FINE - osc_48m_trim_fine - */ -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_48M_OSC_48M_TRIM_FINE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_OTP_TRIM_VALUE_48M_OSC_48M_TRIM_FINE_SHIFT)) & ANADIG_OSC_OSC_OTP_TRIM_VALUE_48M_OSC_48M_TRIM_FINE_MASK) -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_48M_OSC_48M_TRIM_COARSE_MASK (0xFC000U) -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_48M_OSC_48M_TRIM_COARSE_SHIFT (14U) -/*! OSC_48M_TRIM_COARSE - osc_48m_trim_coarse - */ -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_48M_OSC_48M_TRIM_COARSE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_OTP_TRIM_VALUE_48M_OSC_48M_TRIM_COARSE_SHIFT)) & ANADIG_OSC_OSC_OTP_TRIM_VALUE_48M_OSC_48M_TRIM_COARSE_MASK) -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_48M_OSC_48M_TRIM_EN_MASK (0x100000U) -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_48M_OSC_48M_TRIM_EN_SHIFT (20U) -/*! OSC_48M_TRIM_EN - osc_48m_trim_en - */ -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_48M_OSC_48M_TRIM_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_OTP_TRIM_VALUE_48M_OSC_48M_TRIM_EN_SHIFT)) & ANADIG_OSC_OSC_OTP_TRIM_VALUE_48M_OSC_48M_TRIM_EN_MASK) -/*! @} */ -/*! @name OSC_OTP_TRIM_VALUE_16M - OSC_OTP_TRIM_VALUE_16M_REGISTER */ -/*! @{ */ -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_DLY_MASK (0xFU) -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_DLY_SHIFT (0U) -/*! OSC_16M_TRIM_DLY - osc_16m_trim_dly - */ -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_DLY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_DLY_SHIFT)) & ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_DLY_MASK) -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_COARSE_MASK (0x1F0U) -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_COARSE_SHIFT (4U) -/*! OSC_16M_TRIM_COARSE - osc_16m_trim_coarse - */ -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_COARSE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_COARSE_SHIFT)) & ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_COARSE_MASK) -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_FINE_MASK (0x3E00U) -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_FINE_SHIFT (9U) -/*! OSC_16M_TRIM_FINE - osc_16m_trim_fine +#define ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_MASK (0x1U) +#define ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_SHIFT (0U) +/*! ENABLE_CLK - Clock enable + * 0b0..Clock is disabled before entering GPC mode + * 0b1..Clock is enabled before entering GPC mode */ -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_FINE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_FINE_SHIFT)) & ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_FINE_MASK) -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_IREF_MASK (0x7C000U) -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_IREF_SHIFT (14U) -/*! OSC_16M_TRIM_IREF - osc_16m_trim_iref - */ -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_IREF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_IREF_SHIFT)) & ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_IREF_MASK) -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_LP01K_MASK (0x1F80000U) -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_LP01K_SHIFT (19U) -/*! OSC_16M_TRIM_LP01K - osc_16m_trim_LP01K - */ -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_LP01K(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_LP01K_SHIFT)) & ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_LP01K_MASK) -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_TEMPCO_MASK (0x1E000000U) -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_TEMPCO_SHIFT (25U) -/*! OSC_16M_TRIM_TEMPCO - osc_16m_trim_tempco +#define ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_MASK) + +#define ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_MASK (0x400U) +#define ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_SHIFT (10U) +/*! TUNE_BYP - Bypass tuning logic + * 0b0..Use the output of tuning logic to run the oscillator + * 0b1..Bypass the tuning logic and use the programmed OSC_TUNE_VAL to run the oscillator */ -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_TEMPCO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_TEMPCO_SHIFT)) & ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_TEMPCO_MASK) -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_EN_MASK (0x20000000U) -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_EN_SHIFT (29U) -/*! OSC_16M_TRIM_EN - osc_16m_trim_en +#define ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_MASK) + +#define ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_MASK (0xFF000000U) +#define ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_SHIFT (24U) +/*! OSC_TUNE_VAL - Oscillator Tune Value */ -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_EN_SHIFT)) & ANADIG_OSC_OSC_OTP_TRIM_VALUE_16M_OSC_16M_TRIM_EN_MASK) +#define ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_MASK) /*! @} */ -/*! @name OSC_OTP_TRIM_VALUE_XTAL_FREQ - OSC_OTP_TRIM_VALUE_XTAL_FREQ_REGISTER */ +/*! @name OSC_16M_CTRL - 16MHz RCOSC Control Register */ /*! @{ */ -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_XTAL_FREQ_XTAL_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x3U) -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_XTAL_FREQ_XTAL_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (0U) -/*! XTAL_TRIM_PLL_CTRL0_DIV_SEL - xtal_trim_pll_ctrl0_div_sel - */ -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_XTAL_FREQ_XTAL_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_OTP_TRIM_VALUE_XTAL_FREQ_XTAL_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & ANADIG_OSC_OSC_OTP_TRIM_VALUE_XTAL_FREQ_XTAL_TRIM_PLL_CTRL0_DIV_SEL_MASK) -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_XTAL_FREQ_XTAL_TRIM_EN_MASK (0x4U) -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_XTAL_FREQ_XTAL_TRIM_EN_SHIFT (2U) -/*! XTAL_TRIM_EN - xtal_trim_en + +#define ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK (0x2U) +#define ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_SHIFT (1U) +/*! EN_IRC4M16M - Enable Clock Output + * 0b0..Disable + * 0b1..Enable */ -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_XTAL_FREQ_XTAL_TRIM_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_OTP_TRIM_VALUE_XTAL_FREQ_XTAL_TRIM_EN_SHIFT)) & ANADIG_OSC_OSC_OTP_TRIM_VALUE_XTAL_FREQ_XTAL_TRIM_EN_MASK) -/*! @} */ +#define ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK) -/*! @name OSC_OTP_TRIM_VALUE_200M - OSC_OTP_TRIM_VALUE_200M_REGISTER */ -/*! @{ */ -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_200M_RC200M_TUNE_VAL_MASK (0xFFU) -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_200M_RC200M_TUNE_VAL_SHIFT (0U) -/*! RC200M_TUNE_VAL - rc200m_tune_val +#define ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_MASK (0x8U) +#define ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_SHIFT (3U) +/*! EN_POWER_SAVE - Power Save Enable + * 0b0..Disable + * 0b1..Enable */ -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_200M_RC200M_TUNE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_OTP_TRIM_VALUE_200M_RC200M_TUNE_VAL_SHIFT)) & ANADIG_OSC_OSC_OTP_TRIM_VALUE_200M_RC200M_TUNE_VAL_MASK) -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_200M_RC200M_TUNE_BYP_MASK (0x100U) -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_200M_RC200M_TUNE_BYP_SHIFT (8U) -/*! RC200M_TUNE_BYP - rc200m_tune_byp +#define ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_MASK) + +#define ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_MASK (0x100U) +#define ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_SHIFT (8U) +/*! SOURCE_SEL_16M - Source select + * 0b0..16MHz Oscillator + * 0b1..24MHz Oscillator */ -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_200M_RC200M_TUNE_BYP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_OTP_TRIM_VALUE_200M_RC200M_TUNE_BYP_SHIFT)) & ANADIG_OSC_OSC_OTP_TRIM_VALUE_200M_RC200M_TUNE_BYP_MASK) -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_200M_RC200M_TRIM_EN_MASK (0x200U) -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_200M_RC200M_TRIM_EN_SHIFT (9U) -/*! RC200M_TRIM_EN - rc200m_trim_en +#define ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_MASK) + +#define ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_MASK (0x80000000U) +#define ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_SHIFT (31U) +/*! RC_16M_CONTROL_MODE - Control Mode for 16MHz Oscillator + * 0b0..Software mode (default) + * 0b1..GPC mode (Setpoint) */ -#define ANADIG_OSC_OSC_OTP_TRIM_VALUE_200M_RC200M_TRIM_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_OTP_TRIM_VALUE_200M_RC200M_TRIM_EN_SHIFT)) & ANADIG_OSC_OSC_OTP_TRIM_VALUE_200M_RC200M_TRIM_EN_MASK) +#define ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_MASK) /*! @} */ @@ -5537,56 +5316,52 @@ typedef struct { /** ANADIG_PLL - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[512]; - __IO uint32_t PLL_ARM_CTRL; /**< PLL_ARM_CTRL_REGISTER, offset: 0x200 */ + __IO uint32_t ARM_PLL_CTRL; /**< ARM_PLL_CTRL_REGISTER, offset: 0x200 */ uint8_t RESERVED_1[12]; - __IO uint32_t PLL_480_CTRL; /**< PLL_480_CTRL_REGISTER, offset: 0x210 */ + __IO uint32_t SYS_PLL3_CTRL; /**< SYS_PLL3_CTRL_REGISTER, offset: 0x210 */ uint8_t RESERVED_2[12]; - __IO uint32_t PLL_480_UPDATE; /**< PLL_480_UPDATE_REGISTER, offset: 0x220 */ + __IO uint32_t SYS_PLL3_UPDATE; /**< SYS_PLL3_UPDATE_REGISTER, offset: 0x220 */ uint8_t RESERVED_3[12]; - __IO uint32_t PLL_480_PFD; /**< PLL_480_PFD_REGISTER, offset: 0x230 */ + __IO uint32_t SYS_PLL3_PFD; /**< SYS_PLL3_PFD_REGISTER, offset: 0x230 */ uint8_t RESERVED_4[12]; - __IO uint32_t PLL_528_CTRL; /**< PLL_528_CTRL_REGISTER, offset: 0x240 */ + __IO uint32_t SYS_PLL2_CTRL; /**< SYS_PLL2_CTRL_REGISTER, offset: 0x240 */ uint8_t RESERVED_5[12]; - __IO uint32_t PLL_528_UPDATE; /**< PLL_528_UPDATE_REGISTER, offset: 0x250 */ + __IO uint32_t SYS_PLL2_UPDATE; /**< SYS_PLL2_UPDATE_REGISTER, offset: 0x250 */ uint8_t RESERVED_6[12]; - __IO uint32_t PLL_528_SS; /**< PLL_528_SS_REGISTER, offset: 0x260 */ + __IO uint32_t SYS_PLL2_SS; /**< SYS_PLL2_SS_REGISTER, offset: 0x260 */ uint8_t RESERVED_7[12]; - __IO uint32_t PLL_528_PFD; /**< PLL_528_PFD_REGISTER, offset: 0x270 */ - uint8_t RESERVED_8[12]; - __IO uint32_t PLL_528_MFN; /**< PLL_528_MFN_REGISTER, offset: 0x280 */ + __IO uint32_t SYS_PLL2_PFD; /**< SYS_PLL2_PFD_REGISTER, offset: 0x270 */ + uint8_t RESERVED_8[44]; + __IO uint32_t SYS_PLL2_MFD; /**< SYS_PLL2_MFD_REGISTER, offset: 0x2A0 */ uint8_t RESERVED_9[12]; - __IO uint32_t PLL_528_MFI; /**< PLL_528_MFI_REGISTER, offset: 0x290 */ + __IO uint32_t SYS_PLL1_SS; /**< SYS_PLL1_SS_REGISTER, offset: 0x2B0 */ uint8_t RESERVED_10[12]; - __IO uint32_t PLL_528_MFD; /**< PLL_528_MFD_REGISTER, offset: 0x2A0 */ + __IO uint32_t SYS_PLL1_CTRL; /**< SYS_PLL1_CTRL_REGISTER, offset: 0x2C0 */ uint8_t RESERVED_11[12]; - __IO uint32_t PLL_1G_SS; /**< PLL_1G_SS_REGISTER, offset: 0x2B0 */ + __IO uint32_t SYS_PLL1_DENOMINATOR; /**< SYS_PLL1_DENOMINATOR_REGISTER, offset: 0x2D0 */ uint8_t RESERVED_12[12]; - __IO uint32_t PLL_1G_CTRL; /**< PLL_1G_CTRL_REGISTER, offset: 0x2C0 */ + __IO uint32_t SYS_PLL1_NUMERATOR; /**< SYS_PLL1_NUMERATOR_REGISTER, offset: 0x2E0 */ uint8_t RESERVED_13[12]; - __IO uint32_t PLL_1G_DENOMINATOR; /**< PLL_1G_DENOMINATOR_REGISTER, offset: 0x2D0 */ + __IO uint32_t SYS_PLL1_DIV_SELECT; /**< SYS_PLL1_DIV_SELECT_REGISTER, offset: 0x2F0 */ uint8_t RESERVED_14[12]; - __IO uint32_t PLL_1G_NUMERATOR; /**< PLL_1G_NUMERATOR_REGISTER, offset: 0x2E0 */ - uint8_t RESERVED_15[12]; - __IO uint32_t PLL_1G_DIV_SELECT; /**< PLL_1G_DIV_SELECT_REGISTER, offset: 0x2F0 */ - uint8_t RESERVED_16[12]; __IO uint32_t PLL_AUDIO_CTRL; /**< PLL_AUDIO_CTRL_REGISTER, offset: 0x300 */ - uint8_t RESERVED_17[12]; + uint8_t RESERVED_15[12]; __IO uint32_t PLL_AUDIO_SS; /**< PLL_AUDIO_SS_REGISTER, offset: 0x310 */ - uint8_t RESERVED_18[12]; + uint8_t RESERVED_16[12]; __IO uint32_t PLL_AUDIO_DENOMINATOR; /**< PLL_AUDIO_DENOMINATOR_REGISTER, offset: 0x320 */ - uint8_t RESERVED_19[12]; + uint8_t RESERVED_17[12]; __IO uint32_t PLL_AUDIO_NUMERATOR; /**< PLL_AUDIO_NUMERATOR_REGISTER, offset: 0x330 */ - uint8_t RESERVED_20[12]; + uint8_t RESERVED_18[12]; __IO uint32_t PLL_AUDIO_DIV_SELECT; /**< PLL_AUDIO_DIV_SELECT_REGISTER, offset: 0x340 */ - uint8_t RESERVED_21[12]; + uint8_t RESERVED_19[12]; __IO uint32_t PLL_VIDEO_CTRL; /**< PLL_VIDEO_CTRL_REGISTER, offset: 0x350 */ - uint8_t RESERVED_22[12]; + uint8_t RESERVED_20[12]; __IO uint32_t PLL_VIDEO_SS; /**< PLL_VIDEO_SS_REGISTER, offset: 0x360 */ - uint8_t RESERVED_23[12]; + uint8_t RESERVED_21[12]; __IO uint32_t PLL_VIDEO_DENOMINATOR; /**< PLL_VIDEO_DENOMINATOR_REGISTER, offset: 0x370 */ - uint8_t RESERVED_24[12]; + uint8_t RESERVED_22[12]; __IO uint32_t PLL_VIDEO_NUMERATOR; /**< PLL_VIDEO_NUMERATOR_REGISTER, offset: 0x380 */ - uint8_t RESERVED_25[12]; + uint8_t RESERVED_23[12]; __IO uint32_t PLL_VIDEO_DIV_SELECT; /**< PLL_VIDEO_DIV_SELECT_REGISTER, offset: 0x390 */ } ANADIG_PLL_Type; @@ -5599,686 +5374,733 @@ typedef struct { * @{ */ -/*! @name PLL_ARM_CTRL - PLL_ARM_CTRL_REGISTER */ +/*! @name ARM_PLL_CTRL - ARM_PLL_CTRL_REGISTER */ /*! @{ */ -#define ANADIG_PLL_PLL_ARM_CTRL_DIV_SELECT_MASK (0xFFU) -#define ANADIG_PLL_PLL_ARM_CTRL_DIV_SELECT_SHIFT (0U) + +#define ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK (0xFFU) +#define ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_SHIFT (0U) /*! DIV_SELECT - DIV_SELECT */ -#define ANADIG_PLL_PLL_ARM_CTRL_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_ARM_CTRL_DIV_SELECT_SHIFT)) & ANADIG_PLL_PLL_ARM_CTRL_DIV_SELECT_MASK) -#define ANADIG_PLL_PLL_ARM_CTRL_HALF_LF_MASK (0x100U) -#define ANADIG_PLL_PLL_ARM_CTRL_HALF_LF_SHIFT (8U) -/*! HALF_LF - HALF_LF - */ -#define ANADIG_PLL_PLL_ARM_CTRL_HALF_LF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_ARM_CTRL_HALF_LF_SHIFT)) & ANADIG_PLL_PLL_ARM_CTRL_HALF_LF_MASK) -#define ANADIG_PLL_PLL_ARM_CTRL_DOUBLE_LF_MASK (0x200U) -#define ANADIG_PLL_PLL_ARM_CTRL_DOUBLE_LF_SHIFT (9U) -/*! DOUBLE_LF - DOUBLE_LF - */ -#define ANADIG_PLL_PLL_ARM_CTRL_DOUBLE_LF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_ARM_CTRL_DOUBLE_LF_SHIFT)) & ANADIG_PLL_PLL_ARM_CTRL_DOUBLE_LF_MASK) -#define ANADIG_PLL_PLL_ARM_CTRL_HALF_CP_MASK (0x400U) -#define ANADIG_PLL_PLL_ARM_CTRL_HALF_CP_SHIFT (10U) -/*! HALF_CP - HALF_CP - */ -#define ANADIG_PLL_PLL_ARM_CTRL_HALF_CP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_ARM_CTRL_HALF_CP_SHIFT)) & ANADIG_PLL_PLL_ARM_CTRL_HALF_CP_MASK) -#define ANADIG_PLL_PLL_ARM_CTRL_DOUBLE_CP_MASK (0x800U) -#define ANADIG_PLL_PLL_ARM_CTRL_DOUBLE_CP_SHIFT (11U) -/*! DOUBLE_CP - DOUBLE_CP - */ -#define ANADIG_PLL_PLL_ARM_CTRL_DOUBLE_CP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_ARM_CTRL_DOUBLE_CP_SHIFT)) & ANADIG_PLL_PLL_ARM_CTRL_DOUBLE_CP_MASK) -#define ANADIG_PLL_PLL_ARM_CTRL_HOLD_RING_OFF_MASK (0x1000U) -#define ANADIG_PLL_PLL_ARM_CTRL_HOLD_RING_OFF_SHIFT (12U) -/*! HOLD_RING_OFF - Analog debug bit. - */ -#define ANADIG_PLL_PLL_ARM_CTRL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_ARM_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_PLL_ARM_CTRL_HOLD_RING_OFF_MASK) -#define ANADIG_PLL_PLL_ARM_CTRL_POWERUP_MASK (0x2000U) -#define ANADIG_PLL_PLL_ARM_CTRL_POWERUP_SHIFT (13U) -/*! POWERUP - Powers down the PLL. - */ -#define ANADIG_PLL_PLL_ARM_CTRL_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_ARM_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_PLL_ARM_CTRL_POWERUP_MASK) -#define ANADIG_PLL_PLL_ARM_CTRL_ENABLE_CLK_MASK (0x4000U) -#define ANADIG_PLL_PLL_ARM_CTRL_ENABLE_CLK_SHIFT (14U) +#define ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK) + +#define ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_MASK (0x1000U) +#define ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_SHIFT (12U) +/*! HOLD_RING_OFF - PLL Start up initialization + * 0b0..Normal operation + * 0b1..Initialize PLL start up + */ +#define ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_MASK) + +#define ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK (0x2000U) +#define ANADIG_PLL_ARM_PLL_CTRL_POWERUP_SHIFT (13U) +/*! POWERUP - Powers up the PLL. + * 0b1..Power Up the PLL + * 0b0..Power down the PLL + */ +#define ANADIG_PLL_ARM_PLL_CTRL_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK) + +#define ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK (0x4000U) +#define ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_SHIFT (14U) /*! ENABLE_CLK - Enable the clock output. + * 0b0..Disable the clock + * 0b1..Enable the clock */ -#define ANADIG_PLL_PLL_ARM_CTRL_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_ARM_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_PLL_ARM_CTRL_ENABLE_CLK_MASK) -#define ANADIG_PLL_PLL_ARM_CTRL_POST_DIV_SEL_MASK (0x18000U) -#define ANADIG_PLL_PLL_ARM_CTRL_POST_DIV_SEL_SHIFT (15U) +#define ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK) + +#define ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK (0x18000U) +#define ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_SHIFT (15U) /*! POST_DIV_SEL - POST_DIV_SEL + * 0b00..Divide by 2 + * 0b01..Divide by 4 + * 0b10..Divide by 8 + * 0b11..Divide by 1 */ -#define ANADIG_PLL_PLL_ARM_CTRL_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_ARM_CTRL_POST_DIV_SEL_SHIFT)) & ANADIG_PLL_PLL_ARM_CTRL_POST_DIV_SEL_MASK) -#define ANADIG_PLL_PLL_ARM_CTRL_BYPASS_MASK (0x20000U) -#define ANADIG_PLL_PLL_ARM_CTRL_BYPASS_SHIFT (17U) +#define ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK) + +#define ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK (0x20000U) +#define ANADIG_PLL_ARM_PLL_CTRL_BYPASS_SHIFT (17U) /*! BYPASS - Bypass the pll. + * 0b1..Bypass Mode + * 0b0..Function mode */ -#define ANADIG_PLL_PLL_ARM_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_ARM_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_PLL_ARM_CTRL_BYPASS_MASK) -#define ANADIG_PLL_PLL_ARM_CTRL_LVDS_SEL_MASK (0x40000U) -#define ANADIG_PLL_PLL_ARM_CTRL_LVDS_SEL_SHIFT (18U) -/*! LVDS_SEL - LVDS_SEL - */ -#define ANADIG_PLL_PLL_ARM_CTRL_LVDS_SEL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_ARM_CTRL_LVDS_SEL_SHIFT)) & ANADIG_PLL_PLL_ARM_CTRL_LVDS_SEL_MASK) -#define ANADIG_PLL_PLL_ARM_CTRL_TESTMODE_MASK (0x100000U) -#define ANADIG_PLL_PLL_ARM_CTRL_TESTMODE_SHIFT (20U) -/*! TESTMODE - TEST_MODE - */ -#define ANADIG_PLL_PLL_ARM_CTRL_TESTMODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_ARM_CTRL_TESTMODE_SHIFT)) & ANADIG_PLL_PLL_ARM_CTRL_TESTMODE_MASK) -#define ANADIG_PLL_PLL_ARM_CTRL_PLL_ARM_STABLE_MASK (0x20000000U) -#define ANADIG_PLL_PLL_ARM_CTRL_PLL_ARM_STABLE_SHIFT (29U) -/*! PLL_ARM_STABLE - PLL_ARM_STABLE +#define ANADIG_PLL_ARM_PLL_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK) + +#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK (0x20000000U) +#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_SHIFT (29U) +/*! ARM_PLL_STABLE - ARM_PLL_STABLE + * 0b1..ARM PLL is stable + * 0b0..ARM PLL is not stable */ -#define ANADIG_PLL_PLL_ARM_CTRL_PLL_ARM_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_ARM_CTRL_PLL_ARM_STABLE_SHIFT)) & ANADIG_PLL_PLL_ARM_CTRL_PLL_ARM_STABLE_MASK) -#define ANADIG_PLL_PLL_ARM_CTRL_PLL_ARM_GATE_MASK (0x40000000U) -#define ANADIG_PLL_PLL_ARM_CTRL_PLL_ARM_GATE_SHIFT (30U) -/*! PLL_ARM_GATE - PLL_ARM_GATE +#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK) + +#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK (0x40000000U) +#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_SHIFT (30U) +/*! ARM_PLL_GATE - ARM_PLL_GATE + * 0b1..Clock is gated + * 0b0..Clock is not gated */ -#define ANADIG_PLL_PLL_ARM_CTRL_PLL_ARM_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_ARM_CTRL_PLL_ARM_GATE_SHIFT)) & ANADIG_PLL_PLL_ARM_CTRL_PLL_ARM_GATE_MASK) -#define ANADIG_PLL_PLL_ARM_CTRL_PLL_ARM_CONTROL_MODE_MASK (0x80000000U) -#define ANADIG_PLL_PLL_ARM_CTRL_PLL_ARM_CONTROL_MODE_SHIFT (31U) -/*! PLL_ARM_CONTROL_MODE - pll_arm_control_mode +#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK) + +#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK (0x80000000U) +#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_SHIFT (31U) +/*! ARM_PLL_CONTROL_MODE - pll_arm_control_mode + * 0b0..Software Mode (Default) + * 0b1..GPC Mode */ -#define ANADIG_PLL_PLL_ARM_CTRL_PLL_ARM_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_ARM_CTRL_PLL_ARM_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_ARM_CTRL_PLL_ARM_CONTROL_MODE_MASK) +#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK) /*! @} */ -/*! @name PLL_480_CTRL - PLL_480_CTRL_REGISTER */ +/*! @name SYS_PLL3_CTRL - SYS_PLL3_CTRL_REGISTER */ /*! @{ */ -#define ANADIG_PLL_PLL_480_CTRL_DIV_SELECT_MASK (0x7U) -#define ANADIG_PLL_PLL_480_CTRL_DIV_SELECT_SHIFT (0U) -/*! DIV_SELECT - DIV_SELECT + +#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_MASK (0x8U) +#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_SHIFT (3U) +/*! SYS_PLL3_DIV2 - SYS PLL3 DIV2 gate */ -#define ANADIG_PLL_PLL_480_CTRL_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_CTRL_DIV_SELECT_SHIFT)) & ANADIG_PLL_PLL_480_CTRL_DIV_SELECT_MASK) -#define ANADIG_PLL_PLL_480_CTRL_PLL_480_DIV2_MASK (0x8U) -#define ANADIG_PLL_PLL_480_CTRL_PLL_480_DIV2_SHIFT (3U) -/*! PLL_480_DIV2 - PLL 480 DIV2 gate +#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_MASK) + +#define ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_MASK (0x10U) +#define ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_SHIFT (4U) +/*! PLL_REG_EN - Enable Internal PLL Regulator */ -#define ANADIG_PLL_PLL_480_CTRL_PLL_480_DIV2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_CTRL_PLL_480_DIV2_SHIFT)) & ANADIG_PLL_PLL_480_CTRL_PLL_480_DIV2_MASK) -#define ANADIG_PLL_PLL_480_CTRL_PLL_REG_EN_MASK (0x10U) -#define ANADIG_PLL_PLL_480_CTRL_PLL_REG_EN_SHIFT (4U) -/*! PLL_REG_EN - PLL_REG_EN +#define ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_MASK) + +#define ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_MASK (0x800U) +#define ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_SHIFT (11U) +/*! HOLD_RING_OFF - PLL Start up initialization + * 0b0..Normal operation + * 0b1..Initialize PLL start up */ -#define ANADIG_PLL_PLL_480_CTRL_PLL_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_CTRL_PLL_REG_EN_SHIFT)) & ANADIG_PLL_PLL_480_CTRL_PLL_REG_EN_MASK) -#define ANADIG_PLL_PLL_480_CTRL_HALF_LF_MASK (0x80U) -#define ANADIG_PLL_PLL_480_CTRL_HALF_LF_SHIFT (7U) -/*! HALF_LF - HALF_LF - */ -#define ANADIG_PLL_PLL_480_CTRL_HALF_LF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_CTRL_HALF_LF_SHIFT)) & ANADIG_PLL_PLL_480_CTRL_HALF_LF_MASK) -#define ANADIG_PLL_PLL_480_CTRL_DOUBLE_LF_MASK (0x100U) -#define ANADIG_PLL_PLL_480_CTRL_DOUBLE_LF_SHIFT (8U) -/*! DOUBLE_LF - DOUBLE_LF - */ -#define ANADIG_PLL_PLL_480_CTRL_DOUBLE_LF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_CTRL_DOUBLE_LF_SHIFT)) & ANADIG_PLL_PLL_480_CTRL_DOUBLE_LF_MASK) -#define ANADIG_PLL_PLL_480_CTRL_HALF_CP_MASK (0x200U) -#define ANADIG_PLL_PLL_480_CTRL_HALF_CP_SHIFT (9U) -/*! HALF_CP - HALF_CP - */ -#define ANADIG_PLL_PLL_480_CTRL_HALF_CP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_CTRL_HALF_CP_SHIFT)) & ANADIG_PLL_PLL_480_CTRL_HALF_CP_MASK) -#define ANADIG_PLL_PLL_480_CTRL_DOUBLE_CP_MASK (0x400U) -#define ANADIG_PLL_PLL_480_CTRL_DOUBLE_CP_SHIFT (10U) -/*! DOUBLE_CP - DOUBLE_CP - */ -#define ANADIG_PLL_PLL_480_CTRL_DOUBLE_CP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_CTRL_DOUBLE_CP_SHIFT)) & ANADIG_PLL_PLL_480_CTRL_DOUBLE_CP_MASK) -#define ANADIG_PLL_PLL_480_CTRL_HOLD_RING_OFF_MASK (0x800U) -#define ANADIG_PLL_PLL_480_CTRL_HOLD_RING_OFF_SHIFT (11U) -/*! HOLD_RING_OFF - HOLD_RING_OFF - */ -#define ANADIG_PLL_PLL_480_CTRL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_PLL_480_CTRL_HOLD_RING_OFF_MASK) -#define ANADIG_PLL_PLL_480_CTRL_TEST_MODE_MASK (0x1000U) -#define ANADIG_PLL_PLL_480_CTRL_TEST_MODE_SHIFT (12U) -/*! TEST_MODE - TEST_MODE - */ -#define ANADIG_PLL_PLL_480_CTRL_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_CTRL_TEST_MODE_SHIFT)) & ANADIG_PLL_PLL_480_CTRL_TEST_MODE_MASK) -#define ANADIG_PLL_PLL_480_CTRL_ENABLE_CLK_MASK (0x2000U) -#define ANADIG_PLL_PLL_480_CTRL_ENABLE_CLK_SHIFT (13U) -/*! ENABLE_CLK - ENABLE_CLK +#define ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_MASK) + +#define ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK (0x2000U) +#define ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_SHIFT (13U) +/*! ENABLE_CLK - Enable the clock output. + * 0b0..Disable the clock + * 0b1..Enable the clock */ -#define ANADIG_PLL_PLL_480_CTRL_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_PLL_480_CTRL_ENABLE_CLK_MASK) -#define ANADIG_PLL_PLL_480_CTRL_BYPASS_MASK (0x10000U) -#define ANADIG_PLL_PLL_480_CTRL_BYPASS_SHIFT (16U) +#define ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK) + +#define ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK (0x10000U) +#define ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_SHIFT (16U) /*! BYPASS - BYPASS + * 0b1..Bypass Mode + * 0b0..Function mode */ -#define ANADIG_PLL_PLL_480_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_PLL_480_CTRL_BYPASS_MASK) -#define ANADIG_PLL_PLL_480_CTRL_POST_DIV_MASK (0x1C0000U) -#define ANADIG_PLL_PLL_480_CTRL_POST_DIV_SHIFT (18U) -/*! POST_DIV - POST_DIV - */ -#define ANADIG_PLL_PLL_480_CTRL_POST_DIV(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_CTRL_POST_DIV_SHIFT)) & ANADIG_PLL_PLL_480_CTRL_POST_DIV_MASK) -#define ANADIG_PLL_PLL_480_CTRL_POWERUP_MASK (0x200000U) -#define ANADIG_PLL_PLL_480_CTRL_POWERUP_SHIFT (21U) -/*! POWERUP - POWERUP +#define ANADIG_PLL_SYS_PLL3_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK) + +#define ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_MASK (0x200000U) +#define ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_SHIFT (21U) +/*! POWERUP - Powers up the PLL. + * 0b1..Power Up the PLL + * 0b0..Power down the PLL */ -#define ANADIG_PLL_PLL_480_CTRL_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_PLL_480_CTRL_POWERUP_MASK) -#define ANADIG_PLL_PLL_480_CTRL_PLL_480_DIV2_CONTROL_MODE_MASK (0x10000000U) -#define ANADIG_PLL_PLL_480_CTRL_PLL_480_DIV2_CONTROL_MODE_SHIFT (28U) -/*! PLL_480_DIV2_CONTROL_MODE - PLL_480_DIV2_CONTROL_MODE +#define ANADIG_PLL_SYS_PLL3_CTRL_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_MASK) + +#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_MASK (0x10000000U) +#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_SHIFT (28U) +/*! SYS_PLL3_DIV2_CONTROL_MODE - SYS_PLL3_DIV2_CONTROL_MODE + * 0b0..Software Mode (Default) + * 0b1..GPC Mode */ -#define ANADIG_PLL_PLL_480_CTRL_PLL_480_DIV2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_CTRL_PLL_480_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_480_CTRL_PLL_480_DIV2_CONTROL_MODE_MASK) -#define ANADIG_PLL_PLL_480_CTRL_PLL_480_STABLE_MASK (0x20000000U) -#define ANADIG_PLL_PLL_480_CTRL_PLL_480_STABLE_SHIFT (29U) -/*! PLL_480_STABLE - PLL_480_STABLE +#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_MASK) + +#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_MASK (0x20000000U) +#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_SHIFT (29U) +/*! SYS_PLL3_STABLE - SYS_PLL3_STABLE */ -#define ANADIG_PLL_PLL_480_CTRL_PLL_480_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_CTRL_PLL_480_STABLE_SHIFT)) & ANADIG_PLL_PLL_480_CTRL_PLL_480_STABLE_MASK) -#define ANADIG_PLL_PLL_480_CTRL_PLL_480_GATE_MASK (0x40000000U) -#define ANADIG_PLL_PLL_480_CTRL_PLL_480_GATE_SHIFT (30U) -/*! PLL_480_GATE - PLL_480_GATE +#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_MASK) + +#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_MASK (0x40000000U) +#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_SHIFT (30U) +/*! SYS_PLL3_GATE - SYS_PLL3_GATE + * 0b1..Clock is gated + * 0b0..Clock is not gated */ -#define ANADIG_PLL_PLL_480_CTRL_PLL_480_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_CTRL_PLL_480_GATE_SHIFT)) & ANADIG_PLL_PLL_480_CTRL_PLL_480_GATE_MASK) -#define ANADIG_PLL_PLL_480_CTRL_PLL_480_CONTROL_MODE_MASK (0x80000000U) -#define ANADIG_PLL_PLL_480_CTRL_PLL_480_CONTROL_MODE_SHIFT (31U) -/*! PLL_480_CONTROL_MODE - pll_480_control_mode +#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_MASK) + +#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_MASK (0x80000000U) +#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_SHIFT (31U) +/*! SYS_PLL3_CONTROL_MODE - SYS_PLL3_control_mode + * 0b0..Software Mode (Default) + * 0b1..GPC Mode */ -#define ANADIG_PLL_PLL_480_CTRL_PLL_480_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_CTRL_PLL_480_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_480_CTRL_PLL_480_CONTROL_MODE_MASK) +#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_MASK) /*! @} */ -/*! @name PLL_480_UPDATE - PLL_480_UPDATE_REGISTER */ +/*! @name SYS_PLL3_UPDATE - SYS_PLL3_UPDATE_REGISTER */ /*! @{ */ -#define ANADIG_PLL_PLL_480_UPDATE_PLL_480_OVERRIDE_MASK (0x1U) -#define ANADIG_PLL_PLL_480_UPDATE_PLL_480_OVERRIDE_SHIFT (0U) -/*! PLL_480_OVERRIDE - PLL_480_OVERRIDE - */ -#define ANADIG_PLL_PLL_480_UPDATE_PLL_480_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_UPDATE_PLL_480_OVERRIDE_SHIFT)) & ANADIG_PLL_PLL_480_UPDATE_PLL_480_OVERRIDE_MASK) -#define ANADIG_PLL_PLL_480_UPDATE_PFD0_UPDATE_MASK (0x2U) -#define ANADIG_PLL_PLL_480_UPDATE_PFD0_UPDATE_SHIFT (1U) + +#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_MASK (0x2U) +#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_SHIFT (1U) /*! PFD0_UPDATE - PFD0_OVERRIDE */ -#define ANADIG_PLL_PLL_480_UPDATE_PFD0_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_UPDATE_PFD0_UPDATE_SHIFT)) & ANADIG_PLL_PLL_480_UPDATE_PFD0_UPDATE_MASK) -#define ANADIG_PLL_PLL_480_UPDATE_PFD1_UPDATE_MASK (0x4U) -#define ANADIG_PLL_PLL_480_UPDATE_PFD1_UPDATE_SHIFT (2U) +#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_MASK) + +#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_MASK (0x4U) +#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_SHIFT (2U) /*! PFD1_UPDATE - PFD1_OVERRIDE */ -#define ANADIG_PLL_PLL_480_UPDATE_PFD1_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_UPDATE_PFD1_UPDATE_SHIFT)) & ANADIG_PLL_PLL_480_UPDATE_PFD1_UPDATE_MASK) -#define ANADIG_PLL_PLL_480_UPDATE_PFD2_UPDATE_MASK (0x8U) -#define ANADIG_PLL_PLL_480_UPDATE_PFD2_UPDATE_SHIFT (3U) +#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_MASK) + +#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_MASK (0x8U) +#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_SHIFT (3U) /*! PFD2_UPDATE - PFD2_OVERRIDE */ -#define ANADIG_PLL_PLL_480_UPDATE_PFD2_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_UPDATE_PFD2_UPDATE_SHIFT)) & ANADIG_PLL_PLL_480_UPDATE_PFD2_UPDATE_MASK) -#define ANADIG_PLL_PLL_480_UPDATE_PFD3_UPDATE_MASK (0x10U) -#define ANADIG_PLL_PLL_480_UPDATE_PFD3_UPDATE_SHIFT (4U) +#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_MASK) + +#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_MASK (0x10U) +#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_SHIFT (4U) /*! PFD3_UPDATE - PFD3_UPDATE */ -#define ANADIG_PLL_PLL_480_UPDATE_PFD3_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_UPDATE_PFD3_UPDATE_SHIFT)) & ANADIG_PLL_PLL_480_UPDATE_PFD3_UPDATE_MASK) -#define ANADIG_PLL_PLL_480_UPDATE_PFD0_CONTROL_MODE_MASK (0x20U) -#define ANADIG_PLL_PLL_480_UPDATE_PFD0_CONTROL_MODE_SHIFT (5U) +#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_MASK) + +#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_MASK (0x20U) +#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_SHIFT (5U) /*! PFD0_CONTROL_MODE - pfd0_control_mode + * 0b0..Software Mode (Default) + * 0b1..GPC Mode */ -#define ANADIG_PLL_PLL_480_UPDATE_PFD0_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_UPDATE_PFD0_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_480_UPDATE_PFD0_CONTROL_MODE_MASK) -#define ANADIG_PLL_PLL_480_UPDATE_PFD1_CONTROL_MODE_MASK (0x40U) -#define ANADIG_PLL_PLL_480_UPDATE_PFD1_CONTROL_MODE_SHIFT (6U) +#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_MASK) + +#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_MASK (0x40U) +#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_SHIFT (6U) /*! PFD1_CONTROL_MODE - pfd1_control_mode + * 0b0..Software Mode (Default) + * 0b1..GPC Mode */ -#define ANADIG_PLL_PLL_480_UPDATE_PFD1_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_UPDATE_PFD1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_480_UPDATE_PFD1_CONTROL_MODE_MASK) -#define ANADIG_PLL_PLL_480_UPDATE_PDF2_CONTROL_MODE_MASK (0x80U) -#define ANADIG_PLL_PLL_480_UPDATE_PDF2_CONTROL_MODE_SHIFT (7U) +#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_MASK) + +#define ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_MASK (0x80U) +#define ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_SHIFT (7U) /*! PDF2_CONTROL_MODE - pdf2_control_mode + * 0b0..Software Mode (Default) + * 0b1..GPC Mode */ -#define ANADIG_PLL_PLL_480_UPDATE_PDF2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_UPDATE_PDF2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_480_UPDATE_PDF2_CONTROL_MODE_MASK) -#define ANADIG_PLL_PLL_480_UPDATE_PFD3_CONTROL_MODE_MASK (0x100U) -#define ANADIG_PLL_PLL_480_UPDATE_PFD3_CONTROL_MODE_SHIFT (8U) +#define ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_MASK) + +#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_MASK (0x100U) +#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_SHIFT (8U) /*! PFD3_CONTROL_MODE - pfd3_control_mode + * 0b0..Software Mode (Default) + * 0b1..GPC Mode */ -#define ANADIG_PLL_PLL_480_UPDATE_PFD3_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_UPDATE_PFD3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_480_UPDATE_PFD3_CONTROL_MODE_MASK) -#define ANADIG_PLL_PLL_480_UPDATE_PLL480_VTEST_EN_MASK (0x200U) -#define ANADIG_PLL_PLL_480_UPDATE_PLL480_VTEST_EN_SHIFT (9U) -/*! PLL480_VTEST_EN - pll480_vtest_en - */ -#define ANADIG_PLL_PLL_480_UPDATE_PLL480_VTEST_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_UPDATE_PLL480_VTEST_EN_SHIFT)) & ANADIG_PLL_PLL_480_UPDATE_PLL480_VTEST_EN_MASK) +#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_MASK) /*! @} */ -/*! @name PLL_480_PFD - PLL_480_PFD_REGISTER */ +/*! @name SYS_PLL3_PFD - SYS_PLL3_PFD_REGISTER */ /*! @{ */ -#define ANADIG_PLL_PLL_480_PFD_PFD0_FRAC_MASK (0x3FU) -#define ANADIG_PLL_PLL_480_PFD_PFD0_FRAC_SHIFT (0U) + +#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_MASK (0x3FU) +#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_SHIFT (0U) /*! PFD0_FRAC - PFD0_FRAC */ -#define ANADIG_PLL_PLL_480_PFD_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_PFD_PFD0_FRAC_SHIFT)) & ANADIG_PLL_PLL_480_PFD_PFD0_FRAC_MASK) -#define ANADIG_PLL_PLL_480_PFD_PFD0_STABLE_MASK (0x40U) -#define ANADIG_PLL_PLL_480_PFD_PFD0_STABLE_SHIFT (6U) +#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_MASK) + +#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_MASK (0x40U) +#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_SHIFT (6U) /*! PFD0_STABLE - PFD0_STABLE */ -#define ANADIG_PLL_PLL_480_PFD_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_PFD_PFD0_STABLE_SHIFT)) & ANADIG_PLL_PLL_480_PFD_PFD0_STABLE_MASK) -#define ANADIG_PLL_PLL_480_PFD_PFD0_DIV1_CLKGATE_MASK (0x80U) -#define ANADIG_PLL_PLL_480_PFD_PFD0_DIV1_CLKGATE_SHIFT (7U) +#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_MASK) + +#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_MASK (0x80U) +#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_SHIFT (7U) /*! PFD0_DIV1_CLKGATE - PFD0_DIV1_CLKGATE + * 0b1..Fractional divider clock (reference ref_pfd0) is off (power savings + * 0b0..ref_pfd0 fractional divider clock is enabled */ -#define ANADIG_PLL_PLL_480_PFD_PFD0_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_PFD_PFD0_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_PLL_480_PFD_PFD0_DIV1_CLKGATE_MASK) -#define ANADIG_PLL_PLL_480_PFD_PFD1_FRAC_MASK (0x3F00U) -#define ANADIG_PLL_PLL_480_PFD_PFD1_FRAC_SHIFT (8U) +#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_MASK) + +#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_MASK (0x3F00U) +#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_SHIFT (8U) /*! PFD1_FRAC - PFD1_FRAC */ -#define ANADIG_PLL_PLL_480_PFD_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_PFD_PFD1_FRAC_SHIFT)) & ANADIG_PLL_PLL_480_PFD_PFD1_FRAC_MASK) -#define ANADIG_PLL_PLL_480_PFD_PFD1_STABLE_MASK (0x4000U) -#define ANADIG_PLL_PLL_480_PFD_PFD1_STABLE_SHIFT (14U) +#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_MASK) + +#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_MASK (0x4000U) +#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_SHIFT (14U) /*! PFD1_STABLE - PFD1_STABLE */ -#define ANADIG_PLL_PLL_480_PFD_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_PFD_PFD1_STABLE_SHIFT)) & ANADIG_PLL_PLL_480_PFD_PFD1_STABLE_MASK) -#define ANADIG_PLL_PLL_480_PFD_PFD1_DIV1_CLKGATE_MASK (0x8000U) -#define ANADIG_PLL_PLL_480_PFD_PFD1_DIV1_CLKGATE_SHIFT (15U) +#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_MASK) + +#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_MASK (0x8000U) +#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_SHIFT (15U) /*! PFD1_DIV1_CLKGATE - PFD1_DIV1_CLKGATE + * 0b1..Fractional divider clock (reference ref_pfd1) is off (power savings) + * 0b0..ref_pfd1 fractional divider clock is enabled */ -#define ANADIG_PLL_PLL_480_PFD_PFD1_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_PFD_PFD1_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_PLL_480_PFD_PFD1_DIV1_CLKGATE_MASK) -#define ANADIG_PLL_PLL_480_PFD_PFD2_FRAC_MASK (0x3F0000U) -#define ANADIG_PLL_PLL_480_PFD_PFD2_FRAC_SHIFT (16U) +#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_MASK) + +#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_MASK (0x3F0000U) +#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_SHIFT (16U) /*! PFD2_FRAC - PFD2_FRAC */ -#define ANADIG_PLL_PLL_480_PFD_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_PFD_PFD2_FRAC_SHIFT)) & ANADIG_PLL_PLL_480_PFD_PFD2_FRAC_MASK) -#define ANADIG_PLL_PLL_480_PFD_PFD2_STABLE_MASK (0x400000U) -#define ANADIG_PLL_PLL_480_PFD_PFD2_STABLE_SHIFT (22U) +#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_MASK) + +#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_MASK (0x400000U) +#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_SHIFT (22U) /*! PFD2_STABLE - PFD2_STABLE */ -#define ANADIG_PLL_PLL_480_PFD_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_PFD_PFD2_STABLE_SHIFT)) & ANADIG_PLL_PLL_480_PFD_PFD2_STABLE_MASK) -#define ANADIG_PLL_PLL_480_PFD_PFD2_DIV1_CLKGATE_MASK (0x800000U) -#define ANADIG_PLL_PLL_480_PFD_PFD2_DIV1_CLKGATE_SHIFT (23U) +#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_MASK) + +#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_MASK (0x800000U) +#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_SHIFT (23U) /*! PFD2_DIV1_CLKGATE - PFD2_DIV1_CLKGATE + * 0b1..Fractional divider clock (reference ref_pfd2) is off (power savings) + * 0b0..ref_pfd2 fractional divider clock is enabled */ -#define ANADIG_PLL_PLL_480_PFD_PFD2_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_PFD_PFD2_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_PLL_480_PFD_PFD2_DIV1_CLKGATE_MASK) -#define ANADIG_PLL_PLL_480_PFD_PFD3_FRAC_MASK (0x3F000000U) -#define ANADIG_PLL_PLL_480_PFD_PFD3_FRAC_SHIFT (24U) +#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_MASK) + +#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_MASK (0x3F000000U) +#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_SHIFT (24U) /*! PFD3_FRAC - PFD3_FRAC */ -#define ANADIG_PLL_PLL_480_PFD_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_PFD_PFD3_FRAC_SHIFT)) & ANADIG_PLL_PLL_480_PFD_PFD3_FRAC_MASK) -#define ANADIG_PLL_PLL_480_PFD_PFD3_STABLE_MASK (0x40000000U) -#define ANADIG_PLL_PLL_480_PFD_PFD3_STABLE_SHIFT (30U) +#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_MASK) + +#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_MASK (0x40000000U) +#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_SHIFT (30U) /*! PFD3_STABLE - PFD3_STABLE */ -#define ANADIG_PLL_PLL_480_PFD_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_PFD_PFD3_STABLE_SHIFT)) & ANADIG_PLL_PLL_480_PFD_PFD3_STABLE_MASK) -#define ANADIG_PLL_PLL_480_PFD_PFD3_DIV1_CLKGATE_MASK (0x80000000U) -#define ANADIG_PLL_PLL_480_PFD_PFD3_DIV1_CLKGATE_SHIFT (31U) +#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_MASK) + +#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_MASK (0x80000000U) +#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_SHIFT (31U) /*! PFD3_DIV1_CLKGATE - PFD3_DIV1_CLKGATE + * 0b1..Fractional divider clock (reference ref_pfd3) is off (power savings) + * 0b0..ref_pfd3 fractional divider clock is enabled */ -#define ANADIG_PLL_PLL_480_PFD_PFD3_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_480_PFD_PFD3_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_PLL_480_PFD_PFD3_DIV1_CLKGATE_MASK) +#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_MASK) /*! @} */ -/*! @name PLL_528_CTRL - PLL_528_CTRL_REGISTER */ +/*! @name SYS_PLL2_CTRL - SYS_PLL2_CTRL_REGISTER */ /*! @{ */ -#define ANADIG_PLL_PLL_528_CTRL_DIV_SELECT_MASK (0x7U) -#define ANADIG_PLL_PLL_528_CTRL_DIV_SELECT_SHIFT (0U) -/*! DIV_SELECT - DIV_SELECT + +#define ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_MASK (0x8U) +#define ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_SHIFT (3U) +/*! PLL_REG_EN - Enable Internal PLL Regulator */ -#define ANADIG_PLL_PLL_528_CTRL_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_CTRL_DIV_SELECT_SHIFT)) & ANADIG_PLL_PLL_528_CTRL_DIV_SELECT_MASK) -#define ANADIG_PLL_PLL_528_CTRL_PLL_REG_EN_MASK (0x8U) -#define ANADIG_PLL_PLL_528_CTRL_PLL_REG_EN_SHIFT (3U) -/*! PLL_REG_EN - PLL_REG_EN +#define ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_MASK) + +#define ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_MASK (0x800U) +#define ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_SHIFT (11U) +/*! HOLD_RING_OFF - PLL Start up initialization + * 0b0..Normal operation + * 0b1..Initialize PLL start up */ -#define ANADIG_PLL_PLL_528_CTRL_PLL_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_CTRL_PLL_REG_EN_SHIFT)) & ANADIG_PLL_PLL_528_CTRL_PLL_REG_EN_MASK) -#define ANADIG_PLL_PLL_528_CTRL_HALF_LF_MASK (0x80U) -#define ANADIG_PLL_PLL_528_CTRL_HALF_LF_SHIFT (7U) -/*! HALF_LF - HALF_LF - */ -#define ANADIG_PLL_PLL_528_CTRL_HALF_LF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_CTRL_HALF_LF_SHIFT)) & ANADIG_PLL_PLL_528_CTRL_HALF_LF_MASK) -#define ANADIG_PLL_PLL_528_CTRL_DOUBLE_LF_MASK (0x100U) -#define ANADIG_PLL_PLL_528_CTRL_DOUBLE_LF_SHIFT (8U) -/*! DOUBLE_LF - DOUBLE_LF - */ -#define ANADIG_PLL_PLL_528_CTRL_DOUBLE_LF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_CTRL_DOUBLE_LF_SHIFT)) & ANADIG_PLL_PLL_528_CTRL_DOUBLE_LF_MASK) -#define ANADIG_PLL_PLL_528_CTRL_HALF_CP_MASK (0x200U) -#define ANADIG_PLL_PLL_528_CTRL_HALF_CP_SHIFT (9U) -/*! HALF_CP - HALF_CP - */ -#define ANADIG_PLL_PLL_528_CTRL_HALF_CP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_CTRL_HALF_CP_SHIFT)) & ANADIG_PLL_PLL_528_CTRL_HALF_CP_MASK) -#define ANADIG_PLL_PLL_528_CTRL_DOUBLE_CP_MASK (0x400U) -#define ANADIG_PLL_PLL_528_CTRL_DOUBLE_CP_SHIFT (10U) -/*! DOUBLE_CP - DOUBLE_CP - */ -#define ANADIG_PLL_PLL_528_CTRL_DOUBLE_CP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_CTRL_DOUBLE_CP_SHIFT)) & ANADIG_PLL_PLL_528_CTRL_DOUBLE_CP_MASK) -#define ANADIG_PLL_PLL_528_CTRL_HOLD_RING_OFF_MASK (0x800U) -#define ANADIG_PLL_PLL_528_CTRL_HOLD_RING_OFF_SHIFT (11U) -/*! HOLD_RING_OFF - Analog debug bit. - */ -#define ANADIG_PLL_PLL_528_CTRL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_PLL_528_CTRL_HOLD_RING_OFF_MASK) -#define ANADIG_PLL_PLL_528_CTRL_TESTMODE_MASK (0x1000U) -#define ANADIG_PLL_PLL_528_CTRL_TESTMODE_SHIFT (12U) -/*! TESTMODE - TESTMODE - */ -#define ANADIG_PLL_PLL_528_CTRL_TESTMODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_CTRL_TESTMODE_SHIFT)) & ANADIG_PLL_PLL_528_CTRL_TESTMODE_MASK) -#define ANADIG_PLL_PLL_528_CTRL_ENABLE_CLK_MASK (0x2000U) -#define ANADIG_PLL_PLL_528_CTRL_ENABLE_CLK_SHIFT (13U) +#define ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_MASK) + +#define ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK (0x2000U) +#define ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_SHIFT (13U) /*! ENABLE_CLK - Enable the clock output. + * 0b0..Disable the clock + * 0b1..Enable the clock */ -#define ANADIG_PLL_PLL_528_CTRL_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_PLL_528_CTRL_ENABLE_CLK_MASK) -#define ANADIG_PLL_PLL_528_CTRL_BYPASS_MASK (0x10000U) -#define ANADIG_PLL_PLL_528_CTRL_BYPASS_SHIFT (16U) +#define ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) + +#define ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK (0x10000U) +#define ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_SHIFT (16U) /*! BYPASS - Bypass the pll. + * 0b1..Bypass Mode + * 0b0..Function mode */ -#define ANADIG_PLL_PLL_528_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_PLL_528_CTRL_BYPASS_MASK) -#define ANADIG_PLL_PLL_528_CTRL_DITHER_ENABLE_MASK (0x20000U) -#define ANADIG_PLL_PLL_528_CTRL_DITHER_ENABLE_SHIFT (17U) +#define ANADIG_PLL_SYS_PLL2_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) + +#define ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_MASK (0x20000U) +#define ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_SHIFT (17U) /*! DITHER_ENABLE - DITHER_ENABLE + * 0b0..Disable Dither + * 0b1..Enable Dither */ -#define ANADIG_PLL_PLL_528_CTRL_DITHER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_CTRL_DITHER_ENABLE_SHIFT)) & ANADIG_PLL_PLL_528_CTRL_DITHER_ENABLE_MASK) -#define ANADIG_PLL_PLL_528_CTRL_PFD_OFFSET_EN_MASK (0x40000U) -#define ANADIG_PLL_PLL_528_CTRL_PFD_OFFSET_EN_SHIFT (18U) +#define ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_MASK) + +#define ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_MASK (0x40000U) +#define ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_SHIFT (18U) /*! PFD_OFFSET_EN - PFD_OFFSET_EN */ -#define ANADIG_PLL_PLL_528_CTRL_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_CTRL_PFD_OFFSET_EN_SHIFT)) & ANADIG_PLL_PLL_528_CTRL_PFD_OFFSET_EN_MASK) -#define ANADIG_PLL_PLL_528_CTRL_PLL_DDR_OVERRIDE_MASK (0x80000U) -#define ANADIG_PLL_PLL_528_CTRL_PLL_DDR_OVERRIDE_SHIFT (19U) +#define ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_MASK) + +#define ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_MASK (0x80000U) +#define ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_SHIFT (19U) /*! PLL_DDR_OVERRIDE - PLL_DDR_OVERRIDE */ -#define ANADIG_PLL_PLL_528_CTRL_PLL_DDR_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_CTRL_PLL_DDR_OVERRIDE_SHIFT)) & ANADIG_PLL_PLL_528_CTRL_PLL_DDR_OVERRIDE_MASK) -#define ANADIG_PLL_PLL_528_CTRL_POWERUP_MASK (0x800000U) -#define ANADIG_PLL_PLL_528_CTRL_POWERUP_SHIFT (23U) -/*! POWERUP - POWERUP +#define ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_MASK) + +#define ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK (0x800000U) +#define ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_SHIFT (23U) +/*! POWERUP - Powers up the PLL. + * 0b1..Power Up the PLL + * 0b0..Power down the PLL */ -#define ANADIG_PLL_PLL_528_CTRL_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_PLL_528_CTRL_POWERUP_MASK) -#define ANADIG_PLL_PLL_528_CTRL_PLL_528_STABLE_MASK (0x20000000U) -#define ANADIG_PLL_PLL_528_CTRL_PLL_528_STABLE_SHIFT (29U) -/*! PLL_528_STABLE - PLL_528_STABLE +#define ANADIG_PLL_SYS_PLL2_CTRL_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK) + +#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_MASK (0x20000000U) +#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_SHIFT (29U) +/*! SYS_PLL2_STABLE - SYS_PLL2_STABLE */ -#define ANADIG_PLL_PLL_528_CTRL_PLL_528_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_CTRL_PLL_528_STABLE_SHIFT)) & ANADIG_PLL_PLL_528_CTRL_PLL_528_STABLE_MASK) -#define ANADIG_PLL_PLL_528_CTRL_PLL_528_GATE_MASK (0x40000000U) -#define ANADIG_PLL_PLL_528_CTRL_PLL_528_GATE_SHIFT (30U) -/*! PLL_528_GATE - PLL_528_GATE +#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_MASK) + +#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK (0x40000000U) +#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_SHIFT (30U) +/*! SYS_PLL2_GATE - SYS_PLL2_GATE + * 0b1..Clock is gated + * 0b0..Clock is not gated */ -#define ANADIG_PLL_PLL_528_CTRL_PLL_528_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_CTRL_PLL_528_GATE_SHIFT)) & ANADIG_PLL_PLL_528_CTRL_PLL_528_GATE_MASK) -#define ANADIG_PLL_PLL_528_CTRL_PLL_528_CONTROL_MODE_MASK (0x80000000U) -#define ANADIG_PLL_PLL_528_CTRL_PLL_528_CONTROL_MODE_SHIFT (31U) -/*! PLL_528_CONTROL_MODE - pll_528_control_mode +#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK) + +#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK (0x80000000U) +#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_SHIFT (31U) +/*! SYS_PLL2_CONTROL_MODE - SYS_PLL2_control_mode + * 0b0..Software Mode (Default) + * 0b1..GPC Mode */ -#define ANADIG_PLL_PLL_528_CTRL_PLL_528_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_CTRL_PLL_528_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_528_CTRL_PLL_528_CONTROL_MODE_MASK) +#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK) /*! @} */ -/*! @name PLL_528_UPDATE - PLL_528_UPDATE_REGISTER */ +/*! @name SYS_PLL2_UPDATE - SYS_PLL2_UPDATE_REGISTER */ /*! @{ */ -#define ANADIG_PLL_PLL_528_UPDATE_PFD0_UPDATE_MASK (0x2U) -#define ANADIG_PLL_PLL_528_UPDATE_PFD0_UPDATE_SHIFT (1U) + +#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_MASK (0x2U) +#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_SHIFT (1U) /*! PFD0_UPDATE - PFD0_UPDATE */ -#define ANADIG_PLL_PLL_528_UPDATE_PFD0_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_UPDATE_PFD0_UPDATE_SHIFT)) & ANADIG_PLL_PLL_528_UPDATE_PFD0_UPDATE_MASK) -#define ANADIG_PLL_PLL_528_UPDATE_PFD1_UPDATE_MASK (0x4U) -#define ANADIG_PLL_PLL_528_UPDATE_PFD1_UPDATE_SHIFT (2U) +#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_MASK) + +#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_MASK (0x4U) +#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_SHIFT (2U) /*! PFD1_UPDATE - PFD1_UPDATE */ -#define ANADIG_PLL_PLL_528_UPDATE_PFD1_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_UPDATE_PFD1_UPDATE_SHIFT)) & ANADIG_PLL_PLL_528_UPDATE_PFD1_UPDATE_MASK) -#define ANADIG_PLL_PLL_528_UPDATE_PFD2_UPDATE_MASK (0x8U) -#define ANADIG_PLL_PLL_528_UPDATE_PFD2_UPDATE_SHIFT (3U) +#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_MASK) + +#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_MASK (0x8U) +#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_SHIFT (3U) /*! PFD2_UPDATE - PFD2_UPDATE */ -#define ANADIG_PLL_PLL_528_UPDATE_PFD2_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_UPDATE_PFD2_UPDATE_SHIFT)) & ANADIG_PLL_PLL_528_UPDATE_PFD2_UPDATE_MASK) -#define ANADIG_PLL_PLL_528_UPDATE_PFD3_UPDATE_MASK (0x10U) -#define ANADIG_PLL_PLL_528_UPDATE_PFD3_UPDATE_SHIFT (4U) +#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_MASK) + +#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_MASK (0x10U) +#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_SHIFT (4U) /*! PFD3_UPDATE - PFD3_UPDATE */ -#define ANADIG_PLL_PLL_528_UPDATE_PFD3_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_UPDATE_PFD3_UPDATE_SHIFT)) & ANADIG_PLL_PLL_528_UPDATE_PFD3_UPDATE_MASK) -#define ANADIG_PLL_PLL_528_UPDATE_PFD0_CONTROL_MODE_MASK (0x20U) -#define ANADIG_PLL_PLL_528_UPDATE_PFD0_CONTROL_MODE_SHIFT (5U) +#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_MASK) + +#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_MASK (0x20U) +#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_SHIFT (5U) /*! PFD0_CONTROL_MODE - pfd0_control_mode + * 0b0..Software Mode (Default) + * 0b1..GPC Mode */ -#define ANADIG_PLL_PLL_528_UPDATE_PFD0_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_UPDATE_PFD0_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_528_UPDATE_PFD0_CONTROL_MODE_MASK) -#define ANADIG_PLL_PLL_528_UPDATE_PFD1_CONTROL_MODE_MASK (0x40U) -#define ANADIG_PLL_PLL_528_UPDATE_PFD1_CONTROL_MODE_SHIFT (6U) +#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_MASK) + +#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_MASK (0x40U) +#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_SHIFT (6U) /*! PFD1_CONTROL_MODE - pfd1_control_mode + * 0b0..Software Mode (Default) + * 0b1..GPC Mode */ -#define ANADIG_PLL_PLL_528_UPDATE_PFD1_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_UPDATE_PFD1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_528_UPDATE_PFD1_CONTROL_MODE_MASK) -#define ANADIG_PLL_PLL_528_UPDATE_PFD2_CONTROL_MODE_MASK (0x80U) -#define ANADIG_PLL_PLL_528_UPDATE_PFD2_CONTROL_MODE_SHIFT (7U) +#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_MASK) + +#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_MASK (0x80U) +#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_SHIFT (7U) /*! PFD2_CONTROL_MODE - pfd2_control_mode + * 0b0..Software Mode (Default) + * 0b1..GPC Mode */ -#define ANADIG_PLL_PLL_528_UPDATE_PFD2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_UPDATE_PFD2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_528_UPDATE_PFD2_CONTROL_MODE_MASK) -#define ANADIG_PLL_PLL_528_UPDATE_PFD3_CONTROL_MODE_MASK (0x100U) -#define ANADIG_PLL_PLL_528_UPDATE_PFD3_CONTROL_MODE_SHIFT (8U) +#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_MASK) + +#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_MASK (0x100U) +#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_SHIFT (8U) /*! PFD3_CONTROL_MODE - pfd3_control_mode + * 0b0..Software Mode (Default) + * 0b1..GPC Mode */ -#define ANADIG_PLL_PLL_528_UPDATE_PFD3_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_UPDATE_PFD3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_528_UPDATE_PFD3_CONTROL_MODE_MASK) -#define ANADIG_PLL_PLL_528_UPDATE_PLL528_VTEST_EN_MASK (0x200U) -#define ANADIG_PLL_PLL_528_UPDATE_PLL528_VTEST_EN_SHIFT (9U) -/*! PLL528_VTEST_EN - pll528_vtest_en - */ -#define ANADIG_PLL_PLL_528_UPDATE_PLL528_VTEST_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_UPDATE_PLL528_VTEST_EN_SHIFT)) & ANADIG_PLL_PLL_528_UPDATE_PLL528_VTEST_EN_MASK) +#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_MASK) /*! @} */ -/*! @name PLL_528_SS - PLL_528_SS_REGISTER */ +/*! @name SYS_PLL2_SS - SYS_PLL2_SS_REGISTER */ /*! @{ */ -#define ANADIG_PLL_PLL_528_SS_STEP_MASK (0x7FFFU) -#define ANADIG_PLL_PLL_528_SS_STEP_SHIFT (0U) + +#define ANADIG_PLL_SYS_PLL2_SS_STEP_MASK (0x7FFFU) +#define ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT (0U) /*! STEP - STEP */ -#define ANADIG_PLL_PLL_528_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_SS_STEP_SHIFT)) & ANADIG_PLL_PLL_528_SS_STEP_MASK) -#define ANADIG_PLL_PLL_528_SS_ENABLE_MASK (0x8000U) -#define ANADIG_PLL_PLL_528_SS_ENABLE_SHIFT (15U) +#define ANADIG_PLL_SYS_PLL2_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STEP_MASK) + +#define ANADIG_PLL_SYS_PLL2_SS_ENABLE_MASK (0x8000U) +#define ANADIG_PLL_SYS_PLL2_SS_ENABLE_SHIFT (15U) /*! ENABLE - ENABLE + * 0b1..Enable Spread Spectrum + * 0b0..Disable Spread Spectrum */ -#define ANADIG_PLL_PLL_528_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_SS_ENABLE_SHIFT)) & ANADIG_PLL_PLL_528_SS_ENABLE_MASK) -#define ANADIG_PLL_PLL_528_SS_STOP_MASK (0xFFFF0000U) -#define ANADIG_PLL_PLL_528_SS_STOP_SHIFT (16U) +#define ANADIG_PLL_SYS_PLL2_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_ENABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_ENABLE_MASK) + +#define ANADIG_PLL_SYS_PLL2_SS_STOP_MASK (0xFFFF0000U) +#define ANADIG_PLL_SYS_PLL2_SS_STOP_SHIFT (16U) /*! STOP - STOP */ -#define ANADIG_PLL_PLL_528_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_SS_STOP_SHIFT)) & ANADIG_PLL_PLL_528_SS_STOP_MASK) +#define ANADIG_PLL_SYS_PLL2_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STOP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STOP_MASK) /*! @} */ -/*! @name PLL_528_PFD - PLL_528_PFD_REGISTER */ +/*! @name SYS_PLL2_PFD - SYS_PLL2_PFD_REGISTER */ /*! @{ */ -#define ANADIG_PLL_PLL_528_PFD_PFD0_FRAC_MASK (0x3FU) -#define ANADIG_PLL_PLL_528_PFD_PFD0_FRAC_SHIFT (0U) + +#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_MASK (0x3FU) +#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_SHIFT (0U) /*! PFD0_FRAC - PFD0_FRAC */ -#define ANADIG_PLL_PLL_528_PFD_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_PFD_PFD0_FRAC_SHIFT)) & ANADIG_PLL_PLL_528_PFD_PFD0_FRAC_MASK) -#define ANADIG_PLL_PLL_528_PFD_PFD0_STABLE_MASK (0x40U) -#define ANADIG_PLL_PLL_528_PFD_PFD0_STABLE_SHIFT (6U) +#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_MASK) + +#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_MASK (0x40U) +#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_SHIFT (6U) /*! PFD0_STABLE - PFD0_STABLE */ -#define ANADIG_PLL_PLL_528_PFD_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_PFD_PFD0_STABLE_SHIFT)) & ANADIG_PLL_PLL_528_PFD_PFD0_STABLE_MASK) -#define ANADIG_PLL_PLL_528_PFD_PFD0_DIV1_CLKGATE_MASK (0x80U) -#define ANADIG_PLL_PLL_528_PFD_PFD0_DIV1_CLKGATE_SHIFT (7U) +#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_MASK) + +#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_MASK (0x80U) +#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_SHIFT (7U) /*! PFD0_DIV1_CLKGATE - PFD0_DIV1_CLKGATE */ -#define ANADIG_PLL_PLL_528_PFD_PFD0_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_PFD_PFD0_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_PLL_528_PFD_PFD0_DIV1_CLKGATE_MASK) -#define ANADIG_PLL_PLL_528_PFD_PFD1_FRAC_MASK (0x3F00U) -#define ANADIG_PLL_PLL_528_PFD_PFD1_FRAC_SHIFT (8U) +#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_MASK) + +#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_MASK (0x3F00U) +#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_SHIFT (8U) /*! PFD1_FRAC - PFD1_FRAC */ -#define ANADIG_PLL_PLL_528_PFD_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_PFD_PFD1_FRAC_SHIFT)) & ANADIG_PLL_PLL_528_PFD_PFD1_FRAC_MASK) -#define ANADIG_PLL_PLL_528_PFD_PFD1_STABLE_MASK (0x4000U) -#define ANADIG_PLL_PLL_528_PFD_PFD1_STABLE_SHIFT (14U) +#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_MASK) + +#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_MASK (0x4000U) +#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_SHIFT (14U) /*! PFD1_STABLE - PFD1_STABLE */ -#define ANADIG_PLL_PLL_528_PFD_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_PFD_PFD1_STABLE_SHIFT)) & ANADIG_PLL_PLL_528_PFD_PFD1_STABLE_MASK) -#define ANADIG_PLL_PLL_528_PFD_PFD1_DIV1_CLKGATE_MASK (0x8000U) -#define ANADIG_PLL_PLL_528_PFD_PFD1_DIV1_CLKGATE_SHIFT (15U) +#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_MASK) + +#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_MASK (0x8000U) +#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_SHIFT (15U) /*! PFD1_DIV1_CLKGATE - PFD1_DIV1_CLKGATE */ -#define ANADIG_PLL_PLL_528_PFD_PFD1_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_PFD_PFD1_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_PLL_528_PFD_PFD1_DIV1_CLKGATE_MASK) -#define ANADIG_PLL_PLL_528_PFD_PFD2_FRAC_MASK (0x3F0000U) -#define ANADIG_PLL_PLL_528_PFD_PFD2_FRAC_SHIFT (16U) +#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_MASK) + +#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_MASK (0x3F0000U) +#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_SHIFT (16U) /*! PFD2_FRAC - PFD2_FRAC */ -#define ANADIG_PLL_PLL_528_PFD_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_PFD_PFD2_FRAC_SHIFT)) & ANADIG_PLL_PLL_528_PFD_PFD2_FRAC_MASK) -#define ANADIG_PLL_PLL_528_PFD_PFD2_STABLE_MASK (0x400000U) -#define ANADIG_PLL_PLL_528_PFD_PFD2_STABLE_SHIFT (22U) +#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_MASK) + +#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_MASK (0x400000U) +#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_SHIFT (22U) /*! PFD2_STABLE - PFD2_STABLE */ -#define ANADIG_PLL_PLL_528_PFD_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_PFD_PFD2_STABLE_SHIFT)) & ANADIG_PLL_PLL_528_PFD_PFD2_STABLE_MASK) -#define ANADIG_PLL_PLL_528_PFD_PFD2_DIV1_CLKGATE_MASK (0x800000U) -#define ANADIG_PLL_PLL_528_PFD_PFD2_DIV1_CLKGATE_SHIFT (23U) +#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_MASK) + +#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_MASK (0x800000U) +#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_SHIFT (23U) /*! PFD2_DIV1_CLKGATE - PFD2_DIV1_CLKGATE */ -#define ANADIG_PLL_PLL_528_PFD_PFD2_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_PFD_PFD2_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_PLL_528_PFD_PFD2_DIV1_CLKGATE_MASK) -#define ANADIG_PLL_PLL_528_PFD_PFD3_FRAC_MASK (0x3F000000U) -#define ANADIG_PLL_PLL_528_PFD_PFD3_FRAC_SHIFT (24U) +#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_MASK) + +#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_MASK (0x3F000000U) +#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_SHIFT (24U) /*! PFD3_FRAC - PFD3_FRAC */ -#define ANADIG_PLL_PLL_528_PFD_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_PFD_PFD3_FRAC_SHIFT)) & ANADIG_PLL_PLL_528_PFD_PFD3_FRAC_MASK) -#define ANADIG_PLL_PLL_528_PFD_PFD3_STABLE_MASK (0x40000000U) -#define ANADIG_PLL_PLL_528_PFD_PFD3_STABLE_SHIFT (30U) +#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_MASK) + +#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_MASK (0x40000000U) +#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_SHIFT (30U) /*! PFD3_STABLE - PFD3_STABLE */ -#define ANADIG_PLL_PLL_528_PFD_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_PFD_PFD3_STABLE_SHIFT)) & ANADIG_PLL_PLL_528_PFD_PFD3_STABLE_MASK) -#define ANADIG_PLL_PLL_528_PFD_PFD3_DIV1_CLKGATE_MASK (0x80000000U) -#define ANADIG_PLL_PLL_528_PFD_PFD3_DIV1_CLKGATE_SHIFT (31U) +#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_MASK) + +#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_MASK (0x80000000U) +#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_SHIFT (31U) /*! PFD3_DIV1_CLKGATE - PFD3_DIV1_CLKGATE */ -#define ANADIG_PLL_PLL_528_PFD_PFD3_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_PFD_PFD3_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_PLL_528_PFD_PFD3_DIV1_CLKGATE_MASK) +#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_MASK) /*! @} */ -/*! @name PLL_528_MFN - PLL_528_MFN_REGISTER */ +/*! @name SYS_PLL2_MFD - SYS_PLL2_MFD_REGISTER */ /*! @{ */ -#define ANADIG_PLL_PLL_528_MFN_MFN_MASK (0x3FFFFFFFU) -#define ANADIG_PLL_PLL_528_MFN_MFN_SHIFT (0U) -/*! MFN - MFN - */ -#define ANADIG_PLL_PLL_528_MFN_MFN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_MFN_MFN_SHIFT)) & ANADIG_PLL_PLL_528_MFN_MFN_MASK) -/*! @} */ -/*! @name PLL_528_MFI - PLL_528_MFI_REGISTER */ -/*! @{ */ -#define ANADIG_PLL_PLL_528_MFI_MFI_MASK (0x7FU) -#define ANADIG_PLL_PLL_528_MFI_MFI_SHIFT (0U) -/*! MFI - MFI +#define ANADIG_PLL_SYS_PLL2_MFD_MFD_MASK (0x3FFFFFFFU) +#define ANADIG_PLL_SYS_PLL2_MFD_MFD_SHIFT (0U) +/*! MFD - Denominator */ -#define ANADIG_PLL_PLL_528_MFI_MFI(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_MFI_MFI_SHIFT)) & ANADIG_PLL_PLL_528_MFI_MFI_MASK) +#define ANADIG_PLL_SYS_PLL2_MFD_MFD(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_MFD_MFD_SHIFT)) & ANADIG_PLL_SYS_PLL2_MFD_MFD_MASK) /*! @} */ -/*! @name PLL_528_MFD - PLL_528_MFD_REGISTER */ +/*! @name SYS_PLL1_SS - SYS_PLL1_SS_REGISTER */ /*! @{ */ -#define ANADIG_PLL_PLL_528_MFD_MFD_MASK (0x3FFFFFFFU) -#define ANADIG_PLL_PLL_528_MFD_MFD_SHIFT (0U) -/*! MFD - MFD - */ -#define ANADIG_PLL_PLL_528_MFD_MFD(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_528_MFD_MFD_SHIFT)) & ANADIG_PLL_PLL_528_MFD_MFD_MASK) -/*! @} */ -/*! @name PLL_1G_SS - PLL_1G_SS_REGISTER */ -/*! @{ */ -#define ANADIG_PLL_PLL_1G_SS_STEP_MASK (0x7FFFU) -#define ANADIG_PLL_PLL_1G_SS_STEP_SHIFT (0U) +#define ANADIG_PLL_SYS_PLL1_SS_STEP_MASK (0x7FFFU) +#define ANADIG_PLL_SYS_PLL1_SS_STEP_SHIFT (0U) /*! STEP - STEP */ -#define ANADIG_PLL_PLL_1G_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_1G_SS_STEP_SHIFT)) & ANADIG_PLL_PLL_1G_SS_STEP_MASK) -#define ANADIG_PLL_PLL_1G_SS_ENABLE_MASK (0x8000U) -#define ANADIG_PLL_PLL_1G_SS_ENABLE_SHIFT (15U) +#define ANADIG_PLL_SYS_PLL1_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL1_SS_STEP_MASK) + +#define ANADIG_PLL_SYS_PLL1_SS_ENABLE_MASK (0x8000U) +#define ANADIG_PLL_SYS_PLL1_SS_ENABLE_SHIFT (15U) /*! ENABLE - ENABLE + * 0b1..Enable Spread Spectrum + * 0b0..Disable Spread Spectrum */ -#define ANADIG_PLL_PLL_1G_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_1G_SS_ENABLE_SHIFT)) & ANADIG_PLL_PLL_1G_SS_ENABLE_MASK) -#define ANADIG_PLL_PLL_1G_SS_STOP_MASK (0xFFFF0000U) -#define ANADIG_PLL_PLL_1G_SS_STOP_SHIFT (16U) +#define ANADIG_PLL_SYS_PLL1_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_SS_ENABLE_SHIFT)) & ANADIG_PLL_SYS_PLL1_SS_ENABLE_MASK) + +#define ANADIG_PLL_SYS_PLL1_SS_STOP_MASK (0xFFFF0000U) +#define ANADIG_PLL_SYS_PLL1_SS_STOP_SHIFT (16U) /*! STOP - STOP */ -#define ANADIG_PLL_PLL_1G_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_1G_SS_STOP_SHIFT)) & ANADIG_PLL_PLL_1G_SS_STOP_MASK) +#define ANADIG_PLL_SYS_PLL1_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_SS_STOP_SHIFT)) & ANADIG_PLL_SYS_PLL1_SS_STOP_MASK) /*! @} */ -/*! @name PLL_1G_CTRL - PLL_1G_CTRL_REGISTER */ +/*! @name SYS_PLL1_CTRL - SYS_PLL1_CTRL_REGISTER */ /*! @{ */ -#define ANADIG_PLL_PLL_1G_CTRL_ENABLE_CLK_MASK (0x2000U) -#define ANADIG_PLL_PLL_1G_CTRL_ENABLE_CLK_SHIFT (13U) + +#define ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK (0x2000U) +#define ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_SHIFT (13U) /*! ENABLE_CLK - ENABLE_CLK */ -#define ANADIG_PLL_PLL_1G_CTRL_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_1G_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_PLL_1G_CTRL_ENABLE_CLK_MASK) -#define ANADIG_PLL_PLL_1G_CTRL_PLL_1G_GATE_MASK (0x4000U) -#define ANADIG_PLL_PLL_1G_CTRL_PLL_1G_GATE_SHIFT (14U) -/*! PLL_1G_GATE - PLL_1G_GATE - */ -#define ANADIG_PLL_PLL_1G_CTRL_PLL_1G_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_1G_CTRL_PLL_1G_GATE_SHIFT)) & ANADIG_PLL_PLL_1G_CTRL_PLL_1G_GATE_MASK) -#define ANADIG_PLL_PLL_1G_CTRL_PLL_1G_COUNTER_CLR_MASK (0x1000000U) -#define ANADIG_PLL_PLL_1G_CTRL_PLL_1G_COUNTER_CLR_SHIFT (24U) -/*! PLL_1G_COUNTER_CLR - pll_1g_counter_clr +#define ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK) + +#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK (0x4000U) +#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_SHIFT (14U) +/*! SYS_PLL1_GATE - SYS_PLL1_GATE + * 0b1..Gate the output + * 0b0..No gate */ -#define ANADIG_PLL_PLL_1G_CTRL_PLL_1G_COUNTER_CLR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_1G_CTRL_PLL_1G_COUNTER_CLR_SHIFT)) & ANADIG_PLL_PLL_1G_CTRL_PLL_1G_COUNTER_CLR_MASK) -#define ANADIG_PLL_PLL_1G_CTRL_PLL_1G_DIV2_MASK (0x2000000U) -#define ANADIG_PLL_PLL_1G_CTRL_PLL_1G_DIV2_SHIFT (25U) -/*! PLL_1G_DIV2 - pll_1g_div2 +#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK) + +#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK (0x2000000U) +#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_SHIFT (25U) +/*! SYS_PLL1_DIV2 - SYS_PLL1_DIV2 */ -#define ANADIG_PLL_PLL_1G_CTRL_PLL_1G_DIV2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_1G_CTRL_PLL_1G_DIV2_SHIFT)) & ANADIG_PLL_PLL_1G_CTRL_PLL_1G_DIV2_MASK) -#define ANADIG_PLL_PLL_1G_CTRL_PLL_1G_DIV5_MASK (0x4000000U) -#define ANADIG_PLL_PLL_1G_CTRL_PLL_1G_DIV5_SHIFT (26U) -/*! PLL_1G_DIV5 - pll_1g_div5 +#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK) + +#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK (0x4000000U) +#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_SHIFT (26U) +/*! SYS_PLL1_DIV5 - SYS_PLL1_DIV5 */ -#define ANADIG_PLL_PLL_1G_CTRL_PLL_1G_DIV5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_1G_CTRL_PLL_1G_DIV5_SHIFT)) & ANADIG_PLL_PLL_1G_CTRL_PLL_1G_DIV5_MASK) -#define ANADIG_PLL_PLL_1G_CTRL_PLL_1G_DIV5_CONTROL_MODE_MASK (0x8000000U) -#define ANADIG_PLL_PLL_1G_CTRL_PLL_1G_DIV5_CONTROL_MODE_SHIFT (27U) -/*! PLL_1G_DIV5_CONTROL_MODE - pll_1g_div5_control_mode +#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK) + +#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_MASK (0x8000000U) +#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_SHIFT (27U) +/*! SYS_PLL1_DIV5_CONTROL_MODE - SYS_PLL1_DIV5_CONTROL_MODE + * 0b0..Software Mode (Default) + * 0b1..GPC Mode */ -#define ANADIG_PLL_PLL_1G_CTRL_PLL_1G_DIV5_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_1G_CTRL_PLL_1G_DIV5_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_1G_CTRL_PLL_1G_DIV5_CONTROL_MODE_MASK) -#define ANADIG_PLL_PLL_1G_CTRL_PLL_1G_DIV2_CONTROL_MODE_MASK (0x10000000U) -#define ANADIG_PLL_PLL_1G_CTRL_PLL_1G_DIV2_CONTROL_MODE_SHIFT (28U) -/*! PLL_1G_DIV2_CONTROL_MODE - pll_1g_div2_control_mode +#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_MASK) + +#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_MASK (0x10000000U) +#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_SHIFT (28U) +/*! SYS_PLL1_DIV2_CONTROL_MODE - SYS_PLL1_DIV2_CONTROL_MODE + * 0b0..Software Mode (Default) + * 0b1..GPC Mode */ -#define ANADIG_PLL_PLL_1G_CTRL_PLL_1G_DIV2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_1G_CTRL_PLL_1G_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_1G_CTRL_PLL_1G_DIV2_CONTROL_MODE_MASK) -#define ANADIG_PLL_PLL_1G_CTRL_PLL_1G_STABLE_MASK (0x20000000U) -#define ANADIG_PLL_PLL_1G_CTRL_PLL_1G_STABLE_SHIFT (29U) -/*! PLL_1G_STABLE - PLL_1G_STABLE +#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_MASK) + +#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_MASK (0x20000000U) +#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_SHIFT (29U) +/*! SYS_PLL1_STABLE - SYS_PLL1_STABLE */ -#define ANADIG_PLL_PLL_1G_CTRL_PLL_1G_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_1G_CTRL_PLL_1G_STABLE_SHIFT)) & ANADIG_PLL_PLL_1G_CTRL_PLL_1G_STABLE_MASK) -#define ANADIG_PLL_PLL_1G_CTRL_PLL_1G_AI_BUSY_MASK (0x40000000U) -#define ANADIG_PLL_PLL_1G_CTRL_PLL_1G_AI_BUSY_SHIFT (30U) -/*! PLL_1G_AI_BUSY - pll_1g_ai_busy +#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_MASK) + +#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_MASK (0x40000000U) +#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_SHIFT (30U) +/*! SYS_PLL1_AI_BUSY - SYS_PLL1_AI_BUSY */ -#define ANADIG_PLL_PLL_1G_CTRL_PLL_1G_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_1G_CTRL_PLL_1G_AI_BUSY_SHIFT)) & ANADIG_PLL_PLL_1G_CTRL_PLL_1G_AI_BUSY_MASK) -#define ANADIG_PLL_PLL_1G_CTRL_PLL_1G_CONTROL_MODE_MASK (0x80000000U) -#define ANADIG_PLL_PLL_1G_CTRL_PLL_1G_CONTROL_MODE_SHIFT (31U) -/*! PLL_1G_CONTROL_MODE - pll_1g_control_mode +#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_MASK) + +#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK (0x80000000U) +#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_SHIFT (31U) +/*! SYS_PLL1_CONTROL_MODE - SYS_PLL1_CONTROL_MODE + * 0b0..Software Mode (Default) + * 0b1..GPC Mode */ -#define ANADIG_PLL_PLL_1G_CTRL_PLL_1G_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_1G_CTRL_PLL_1G_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_1G_CTRL_PLL_1G_CONTROL_MODE_MASK) +#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK) /*! @} */ -/*! @name PLL_1G_DENOMINATOR - PLL_1G_DENOMINATOR_REGISTER */ +/*! @name SYS_PLL1_DENOMINATOR - SYS_PLL1_DENOMINATOR_REGISTER */ /*! @{ */ -#define ANADIG_PLL_PLL_1G_DENOMINATOR_DEMON_MASK (0x3FFFFFFFU) -#define ANADIG_PLL_PLL_1G_DENOMINATOR_DEMON_SHIFT (0U) -/*! DEMON - DEMON + +#define ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU) +#define ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_SHIFT (0U) +/*! DENOM - DENOM */ -#define ANADIG_PLL_PLL_1G_DENOMINATOR_DEMON(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_1G_DENOMINATOR_DEMON_SHIFT)) & ANADIG_PLL_PLL_1G_DENOMINATOR_DEMON_MASK) +#define ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_SHIFT)) & ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_MASK) /*! @} */ -/*! @name PLL_1G_NUMERATOR - PLL_1G_NUMERATOR_REGISTER */ +/*! @name SYS_PLL1_NUMERATOR - SYS_PLL1_NUMERATOR_REGISTER */ /*! @{ */ -#define ANADIG_PLL_PLL_1G_NUMERATOR_NUM_MASK (0x3FFFFFFFU) -#define ANADIG_PLL_PLL_1G_NUMERATOR_NUM_SHIFT (0U) + +#define ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_MASK (0x3FFFFFFFU) +#define ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_SHIFT (0U) /*! NUM - NUM */ -#define ANADIG_PLL_PLL_1G_NUMERATOR_NUM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_1G_NUMERATOR_NUM_SHIFT)) & ANADIG_PLL_PLL_1G_NUMERATOR_NUM_MASK) +#define ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_SHIFT)) & ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_MASK) /*! @} */ -/*! @name PLL_1G_DIV_SELECT - PLL_1G_DIV_SELECT_REGISTER */ +/*! @name SYS_PLL1_DIV_SELECT - SYS_PLL1_DIV_SELECT_REGISTER */ /*! @{ */ -#define ANADIG_PLL_PLL_1G_DIV_SELECT_DIV_SELECT_MASK (0x7FU) -#define ANADIG_PLL_PLL_1G_DIV_SELECT_DIV_SELECT_SHIFT (0U) + +#define ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_MASK (0x7FU) +#define ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_SHIFT (0U) /*! DIV_SELECT - DIV_SELECT */ -#define ANADIG_PLL_PLL_1G_DIV_SELECT_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_1G_DIV_SELECT_DIV_SELECT_SHIFT)) & ANADIG_PLL_PLL_1G_DIV_SELECT_DIV_SELECT_MASK) +#define ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_SHIFT)) & ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_MASK) /*! @} */ /*! @name PLL_AUDIO_CTRL - PLL_AUDIO_CTRL_REGISTER */ /*! @{ */ + #define ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK (0x2000U) #define ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_SHIFT (13U) /*! ENABLE_CLK - ENABLE_CLK */ #define ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK) + #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_MASK (0x4000U) #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_SHIFT (14U) /*! PLL_AUDIO_GATE - PLL_AUDIO_GATE + * 0b1..Gate the output + * 0b0..No gate */ #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_MASK) -#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_COUNTER_CLR_MASK (0x1000000U) -#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_COUNTER_CLR_SHIFT (24U) -/*! PLL_AUDIO_COUNTER_CLR - pll_audio_counter_clr - */ -#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_COUNTER_CLR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_COUNTER_CLR_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_COUNTER_CLR_MASK) + #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_MASK (0x20000000U) #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_SHIFT (29U) /*! PLL_AUDIO_STABLE - PLL_AUDIO_STABLE */ #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_MASK) + #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_MASK (0x40000000U) #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_SHIFT (30U) /*! PLL_AUDIO_AI_BUSY - pll_audio_ai_busy */ #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_MASK) + #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK (0x80000000U) #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_SHIFT (31U) /*! PLL_AUDIO_CONTROL_MODE - pll_audio_control_mode + * 0b0..Software Mode (Default) + * 0b1..GPC Mode */ #define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK) /*! @} */ /*! @name PLL_AUDIO_SS - PLL_AUDIO_SS_REGISTER */ /*! @{ */ + #define ANADIG_PLL_PLL_AUDIO_SS_STEP_MASK (0x7FFFU) #define ANADIG_PLL_PLL_AUDIO_SS_STEP_SHIFT (0U) /*! STEP - STEP */ #define ANADIG_PLL_PLL_AUDIO_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_SS_STEP_SHIFT)) & ANADIG_PLL_PLL_AUDIO_SS_STEP_MASK) + #define ANADIG_PLL_PLL_AUDIO_SS_ENABLE_MASK (0x8000U) #define ANADIG_PLL_PLL_AUDIO_SS_ENABLE_SHIFT (15U) /*! ENABLE - ENABLE + * 0b1..Enable Spread Spectrum + * 0b0..Disable Spread Spectrum */ #define ANADIG_PLL_PLL_AUDIO_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_SS_ENABLE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_SS_ENABLE_MASK) + #define ANADIG_PLL_PLL_AUDIO_SS_STOP_MASK (0xFFFF0000U) #define ANADIG_PLL_PLL_AUDIO_SS_STOP_SHIFT (16U) /*! STOP - STOP @@ -6288,6 +6110,7 @@ typedef struct { /*! @name PLL_AUDIO_DENOMINATOR - PLL_AUDIO_DENOMINATOR_REGISTER */ /*! @{ */ + #define ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU) #define ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_SHIFT (0U) /*! DENOM - DENOM @@ -6297,6 +6120,7 @@ typedef struct { /*! @name PLL_AUDIO_NUMERATOR - PLL_AUDIO_NUMERATOR_REGISTER */ /*! @{ */ + #define ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_MASK (0x3FFFFFFFU) #define ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_SHIFT (0U) /*! NUM - NUM @@ -6306,6 +6130,7 @@ typedef struct { /*! @name PLL_AUDIO_DIV_SELECT - PLL_AUDIO_DIV_SELECT_REGISTER */ /*! @{ */ + #define ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_MASK (0x7FU) #define ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_SHIFT (0U) /*! PLL_AUDIO_DIV_SELECT - PLL_AUDIO_DIV_SELECT @@ -6315,50 +6140,65 @@ typedef struct { /*! @name PLL_VIDEO_CTRL - PLL_VIDEO_CTRL_REGISTER */ /*! @{ */ + #define ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK (0x2000U) #define ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_SHIFT (13U) /*! ENABLE_CLK - ENABLE_CLK */ #define ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK) + #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_MASK (0x4000U) #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_SHIFT (14U) /*! PLL_VIDEO_GATE - PLL_VIDEO_GATE + * 0b1..Gate the output + * 0b0..No gate */ #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_MASK) + #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_MASK (0x1000000U) #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_SHIFT (24U) /*! PLL_VIDEO_COUNTER_CLR - pll_video_counter_clr */ #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_MASK) + #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_MASK (0x20000000U) #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_SHIFT (29U) /*! PLL_VIDEO_STABLE - PLL_VIDEO_STABLE */ #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_MASK) + #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_MASK (0x40000000U) #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_SHIFT (30U) /*! PLL_VIDEO_AI_BUSY - pll_video_ai_busy */ #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_MASK) + #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK (0x80000000U) #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_SHIFT (31U) /*! PLL_VIDEO_CONTROL_MODE - pll_video_control_mode + * 0b0..Software Mode (Default) + * 0b1..GPC Mode */ #define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK) /*! @} */ /*! @name PLL_VIDEO_SS - PLL_VIDEO_SS_REGISTER */ /*! @{ */ + #define ANADIG_PLL_PLL_VIDEO_SS_STEP_MASK (0x7FFFU) #define ANADIG_PLL_PLL_VIDEO_SS_STEP_SHIFT (0U) /*! STEP - STEP */ #define ANADIG_PLL_PLL_VIDEO_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_SS_STEP_SHIFT)) & ANADIG_PLL_PLL_VIDEO_SS_STEP_MASK) + #define ANADIG_PLL_PLL_VIDEO_SS_ENABLE_MASK (0x8000U) #define ANADIG_PLL_PLL_VIDEO_SS_ENABLE_SHIFT (15U) /*! ENABLE - ENABLE + * 0b1..Enable Spread Spectrum + * 0b0..Disable Spread Spectrum */ #define ANADIG_PLL_PLL_VIDEO_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_SS_ENABLE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_SS_ENABLE_MASK) + #define ANADIG_PLL_PLL_VIDEO_SS_STOP_MASK (0xFFFF0000U) #define ANADIG_PLL_PLL_VIDEO_SS_STOP_SHIFT (16U) /*! STOP - STOP @@ -6368,6 +6208,7 @@ typedef struct { /*! @name PLL_VIDEO_DENOMINATOR - PLL_VIDEO_DENOMINATOR_REGISTER */ /*! @{ */ + #define ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU) #define ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_SHIFT (0U) /*! DENOM - DENOM @@ -6377,6 +6218,7 @@ typedef struct { /*! @name PLL_VIDEO_NUMERATOR - PLL_VIDEO_NUMERATOR_REGISTER */ /*! @{ */ + #define ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_MASK (0x3FFFFFFFU) #define ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_SHIFT (0U) /*! NUM - NUM @@ -6386,6 +6228,7 @@ typedef struct { /*! @name PLL_VIDEO_DIV_SELECT - PLL_VIDEO_DIV_SELECT_REGISTER */ /*! @{ */ + #define ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_MASK (0x7FU) #define ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_SHIFT (0U) /*! DIV_SELECT - DIV_SELECT @@ -6491,9 +6334,7 @@ typedef struct { __IO uint32_t RBB_SOC_CONFIGURE; /**< RBB_SOC_CONFIGURE_REGISTER, offset: 0x7A0 */ uint8_t RESERVED_32[12]; __I uint32_t REFTOP_OTP_TRIM_VALUE; /**< REFTOP_OTP_TRIM_VALUE_REGISTER, offset: 0x7B0 */ - uint8_t RESERVED_33[12]; - __I uint32_t WB_OTP_TRIM_VALUE; /**< WB_OTP_TRIM_VALUE_REGISTER, offset: 0x7C0 */ - uint8_t RESERVED_34[12]; + uint8_t RESERVED_33[28]; __I uint32_t LPSR_1P8_LDO_OTP_TRIM_VALUE; /**< LPSR_1P8_LDO_OTP_TRIM_VALUE_REGISTER, offset: 0x7D0 */ } ANADIG_PMU_Type; @@ -6508,21 +6349,27 @@ typedef struct { /*! @name PMU_LDO_PLL - PMU_LDO_PLL_REGISTER */ /*! @{ */ + #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK (0x1U) #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_SHIFT (0U) /*! LDO_PLL_ENABLE - LDO_PLL_ENABLE */ #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_SHIFT)) & ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK) + #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK (0x2U) #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_SHIFT (1U) /*! LDO_PLL_CONTROL_MODE - LDO_PLL_CONTROL_MODE + * 0b0..SW Control + * 0b1..HW Control */ #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK) + #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK (0x10000U) #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_SHIFT (16U) /*! LDO_PLL_AI_TOGGLE - ldo_pll_ai_toggle */ #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_SHIFT)) & ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK) + #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_MASK (0x40000000U) #define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_SHIFT (30U) /*! LDO_PLL_AI_BUSY - ldo_pll_busy @@ -6532,109 +6379,134 @@ typedef struct { /*! @name PMU_BIAS_CTRL - PMU_BIAS_CTRL_REGISTER */ /*! @{ */ + #define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK (0x1FFFU) #define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_SHIFT (0U) -/*! WB_CFG_1P8 - wb_cfg_1p8_1 +/*! WB_CFG_1P8 - wb_cfg_1p8 */ #define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK) + #define ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_MASK (0x4000U) #define ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_SHIFT (14U) /*! WB_VDD_SEL_1P8 - wb_vdd_sel_1p8 + * 0b0..VDD_LV1 + * 0b1..VDD_LV2 */ #define ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_MASK) -#define ANADIG_PMU_PMU_BIAS_CTRL_WB_IN_SP_1P8_MASK (0xFF0000U) -#define ANADIG_PMU_PMU_BIAS_CTRL_WB_IN_SP_1P8_SHIFT (16U) -/*! WB_IN_SP_1P8 - wb_in_sp_1p8 - */ -#define ANADIG_PMU_PMU_BIAS_CTRL_WB_IN_SP_1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL_WB_IN_SP_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL_WB_IN_SP_1P8_MASK) -#define ANADIG_PMU_PMU_BIAS_CTRL_WB_PW_LVL_1P8_MASK (0xF000000U) -#define ANADIG_PMU_PMU_BIAS_CTRL_WB_PW_LVL_1P8_SHIFT (24U) -/*! WB_PW_LVL_1P8 - wb_pw_lvl_1p8 - */ -#define ANADIG_PMU_PMU_BIAS_CTRL_WB_PW_LVL_1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL_WB_PW_LVL_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL_WB_PW_LVL_1P8_MASK) -#define ANADIG_PMU_PMU_BIAS_CTRL_WB_NW_LVL_1P8_MASK (0xF0000000U) -#define ANADIG_PMU_PMU_BIAS_CTRL_WB_NW_LVL_1P8_SHIFT (28U) -/*! WB_NW_LVL_1P8 - wb_nw_lvl_1p8 - */ -#define ANADIG_PMU_PMU_BIAS_CTRL_WB_NW_LVL_1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL_WB_NW_LVL_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL_WB_NW_LVL_1P8_MASK) /*! @} */ /*! @name PMU_BIAS_CTRL2 - PMU_BIAS_CTRL2_REGISTER */ /*! @{ */ -#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_EN_1P8_MASK (0x1U) -#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_EN_1P8_SHIFT (0U) -/*! WB_TST_EN_1P8 - TST_EN - */ -#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_EN_1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_EN_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_EN_1P8_MASK) + #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_MASK (0x3FEU) #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_SHIFT (1U) /*! WB_TST_MD - TMOD_wb_tst_md_1p8 */ #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_MASK) + #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK (0x1C00U) #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_SHIFT (10U) /*! WB_PWR_SW_EN_1P8 - MODSEL_wb_tst_md_1p8 + * 0b001..No BB + * 0b010..BB + * 0b100..BB */ #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK) + #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_MASK (0x1FE000U) #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_SHIFT (13U) /*! WB_ADJ_1P8 - wb_adj_1p8 + * 0b00000000..Cref= 0fF Cspl= 0fF DeltaC= 0fF + * 0b00000001..Cref= 0fF Cspl= 30fF DeltaC= -30fF + * 0b00000010..Cref= 0fF Cspl= 43fF DeltaC= -43fF + * 0b00000011..Cref= 0fF Cspl= 62fF DeltaC=-62fF + * 0b00000100..Cref= 0fF Cspl=105fF DeltaC=-105fF + * 0b00000101..Cref= 30fF Cspl= 0fF DeltaC= 30fF + * 0b00000110..Cref= 30fF Cspl= 43fF DeltaC= -12fF + * 0b00000111..Cref= 30fF Cspl=105fF DeltaC= -75fF + * 0b00001000..Cref= 43fF Cspl= 0fF DeltaC= 43fF + * 0b00001001..Cref= 43fF Cspl= 30fF DeltaC= 13fF + * 0b00001010..Cref= 43fF Cspl= 62fF DeltaC= -19fF + * 0b00001011..Cref= 62fF Cspl= 0fF DeltaC= 62fF + * 0b00001100..Cref= 62fF Cspl= 43fF DeltaC= 19fF + * 0b00001101..Cref=105fF Cspl= 0fF DeltaC= 105fF + * 0b00001110..Cref=105fF Cspl=30fF DeltaC= 75fF + * 0b00001111..Cref=0fF Cspl=0fF DeltaC= 0fF */ #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_MASK) + #define ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_MASK (0x200000U) #define ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_SHIFT (21U) -/*! FBB_M7_CONTROL_MODE - fbb_m7_control_mode +/*! FBB_M7_CONTROL_MODE - FBB_M7_CONTROL_MODE + * 0b0..SW Control + * 0b1..HW Control */ #define ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_MASK) + #define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_MASK (0x400000U) #define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_SHIFT (22U) -/*! RBB_SOC_CONTROL_MODE - rbb_soc_control_mode +/*! RBB_SOC_CONTROL_MODE - RBB_SOC_CONTROL_MODE + * 0b0..SW Control + * 0b1..HW Control */ #define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_MASK) + #define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_MASK (0x800000U) #define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_SHIFT (23U) -/*! RBB_LPSR_CONTROL_MODE - rbb_lpsr_control_mode +/*! RBB_LPSR_CONTROL_MODE - RBB_LPSR_CONTROL_MODE + * 0b0..SW Control + * 0b1..HW Control */ #define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_MASK) + #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK (0x1000000U) #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_SHIFT (24U) /*! WB_EN - wb_en */ #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK) + #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_MASK (0x2000000U) #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_SHIFT (25U) -/*! WB_TST_DIG_OUT - Digital output for test purpose +/*! WB_TST_DIG_OUT - Digital output */ #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_MASK) + #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK (0x4000000U) #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_SHIFT (26U) -/*! WB_OK - Digital Output pin. Turn on/off acknowledge bit from regulator +/*! WB_OK - Digital Output pin. */ #define ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK) /*! @} */ /*! @name PMU_REF_CTRL - PMU_REF_CTRL_REGISTER */ /*! @{ */ + #define ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_MASK (0x1U) #define ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_SHIFT (0U) /*! REF_AI_TOGGLE - ref_ai_toggle */ #define ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_MASK) + #define ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_MASK (0x2U) #define ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_SHIFT (1U) /*! REF_AI_BUSY - ref_ai_busy */ #define ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_MASK) + #define ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_MASK (0x4U) #define ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_SHIFT (2U) -/*! REF_ENABLE - ref_enable +/*! REF_ENABLE - REF_ENABLE */ #define ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_MASK) + #define ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_MASK (0x8U) #define ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_SHIFT (3U) -/*! REF_CONTROL_MODE - ref_control_mode +/*! REF_CONTROL_MODE - REF_CONTROL_MODE + * 0b0..SW Control + * 0b1..HW Control */ #define ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_MASK) + #define ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_MASK (0x10U) #define ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_SHIFT (4U) /*! EN_PLL_VOL_REF_BUFFER - en_pll_vol_ref_buffer @@ -6644,6 +6516,7 @@ typedef struct { /*! @name PMU_POWER_DETECT_CTRL - PMU_POWER_DETECT_CTRL_REGISTER */ /*! @{ */ + #define ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_MASK (0x100U) #define ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_SHIFT (8U) /*! CKGB_LPSR1P0 - ckgb_lpsr1p0 @@ -6653,609 +6526,949 @@ typedef struct { /*! @name LDO_PLL_ENABLE_SP - LDO_PLL_ENABLE_SP_REGISTER */ /*! @{ */ + #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U) #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U) /*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_MASK) + #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U) #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U) /*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_MASK) + #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U) #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U) /*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_MASK) + #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U) #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U) /*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_MASK) + #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U) #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U) /*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_MASK) + #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U) #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U) /*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_MASK) + #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U) #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U) /*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_MASK) + #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U) #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U) /*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_MASK) + #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U) #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U) /*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_MASK) + #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U) #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U) /*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_MASK) + #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U) #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U) /*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_MASK) + #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U) #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U) /*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_MASK) + #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U) #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U) /*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_MASK) + #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U) #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U) /*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_MASK) + #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U) #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U) /*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_MASK) + #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U) #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U) /*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_MASK) /*! @} */ /*! @name LDO_LPSR_ANA_ENABLE_SP - LDO_LPSR_ANA_ENABLE_SP_REGISTER */ /*! @{ */ + #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U) #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U) /*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U) #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U) /*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U) #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U) /*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U) #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U) /*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U) #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U) /*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U) #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U) /*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U) #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U) /*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U) #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U) /*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U) #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U) /*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U) #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U) /*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U) #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U) /*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U) #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U) /*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U) #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U) /*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U) #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U) /*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U) #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U) /*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U) #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U) /*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_MASK) /*! @} */ /*! @name LDO_LPSR_ANA_LP_MODE_SP - LDO_LPSR_ANA_LP_MODE_SP_REGISTER */ /*! @{ */ + #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_MASK (0x1U) #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT (0U) /*! LP_MODE_SETPOINT0 - LP_MODE_SETPOINT0 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_MASK (0x2U) #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT (1U) /*! LP_MODE_SETPOINT1 - LP_MODE_SETPOINT1 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_MASK (0x4U) #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_SHIFT (2U) /*! LP_MODE_SETPONIT2 - LP_MODE_SETPOINT2 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_MASK (0x8U) #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_SHIFT (3U) /*! LP_MODE_SETPONIT3 - LP_MODE_SETPOINT3 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_MASK (0x10U) #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_SHIFT (4U) /*! LP_MODE_SETPONIT4 - LP_MODE_SETPOINT4 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_MASK (0x20U) #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_SHIFT (5U) /*! LP_MODE_SETPONIT5 - LP_MODE_SETPOINT5 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_MASK (0x40U) #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_SHIFT (6U) /*! LP_MODE_SETPONIT6 - LP_MODE_SETPOINT6 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_MASK (0x80U) #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_SHIFT (7U) /*! LP_MODE_SETPONIT7 - LP_MODE_SETPOINT7 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_MASK (0x100U) #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_SHIFT (8U) /*! LP_MODE_SETPONIT8 - LP_MODE_SETPOINT8 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_MASK (0x200U) #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_SHIFT (9U) /*! LP_MODE_SETPONIT9 - LP_MODE_SETPOINT9 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_MASK (0x400U) #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_SHIFT (10U) /*! LP_MODE_SETPONIT10 - LP_MODE_SETPOINT10 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_MASK (0x800U) #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_SHIFT (11U) /*! LP_MODE_SETPONIT11 - LP_MODE_SETPOINT11 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_MASK (0x1000U) #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_SHIFT (12U) /*! LP_MODE_SETPONIT12 - LP_MODE_SETPOINT12 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_MASK (0x2000U) #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_SHIFT (13U) /*! LP_MODE_SETPONIT13 - LP_MODE_SETPOINT13 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_MASK (0x4000U) #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_SHIFT (14U) /*! LP_MODE_SETPONIT14 - LP_MODE_SETPOINT14 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_MASK (0x8000U) #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_SHIFT (15U) /*! LP_MODE_SETPONIT15 - LP_MODE_SETPOINT15 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_MASK) /*! @} */ /*! @name LDO_LPSR_ANA_TRACKING_EN_SP - LDO_LPSR_ANA_TRACKING_EN_SP_REGISTER */ /*! @{ */ + #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK (0x1U) #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT (0U) /*! TRACKING_EN_SETPOINT0 - TRACKING_EN_SETPOINT0 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK (0x2U) #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT (1U) /*! TRACKING_EN_SETPOINT1 - TRACKING_EN_SETPOINT1 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK (0x4U) #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT (2U) /*! TRACKING_EN_SETPOINT2 - TRACKING_EN_SETPOINT2 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK (0x8U) #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT (3U) /*! TRACKING_EN_SETPOINT3 - TRACKING_EN_SETPOINT3 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK (0x10U) #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT (4U) /*! TRACKING_EN_SETPOINT4 - TRACKING_EN_SETPOINT4 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK (0x20U) #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT (5U) /*! TRACKING_EN_SETPOINT5 - TRACKING_EN_SETPOINT5 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK (0x40U) #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT (6U) /*! TRACKING_EN_SETPOINT6 - TRACKING_EN_SETPOINT6 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK (0x80U) #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT (7U) /*! TRACKING_EN_SETPOINT7 - TRACKING_EN_SETPOINT7 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK (0x100U) #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT (8U) /*! TRACKING_EN_SETPOINT8 - TRACKING_EN_SETPOINT8 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK (0x200U) #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT (9U) /*! TRACKING_EN_SETPOINT9 - TRACKING_EN_SETPOINT9 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK (0x400U) #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT (10U) /*! TRACKING_EN_SETPOINT10 - TRACKING_EN_SETPOINT10 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK (0x800U) #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT (11U) /*! TRACKING_EN_SETPOINT11 - TRACKING_EN_SETPOINT11 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK (0x1000U) #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT (12U) /*! TRACKING_EN_SETPOINT12 - TRACKING_EN_SETPOINT12 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK (0x2000U) #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT (13U) /*! TRACKING_EN_SETPOINT13 - TRACKING_EN_SETPOINT13 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK (0x4000U) #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT (14U) /*! TRACKING_EN_SETPOINT14 - TRACKING_EN_SETPOINT14 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK (0x8000U) #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT (15U) /*! TRACKING_EN_SETPOINT15 - TRACKING_EN_SETPOINT15 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK) /*! @} */ /*! @name LDO_LPSR_ANA_BYPASS_EN_SP - LDO_LPSR_ANA_BYPASS_EN_SP_REGISTER */ /*! @{ */ + #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK (0x1U) #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT (0U) /*! BYPASS_EN_SETPOINT0 - BYPASS_EN_SETPOINT0 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK (0x2U) #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT (1U) /*! BYPASS_EN_SETPOINT1 - BYPASS_EN_SETPOINT1 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK (0x4U) #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT (2U) /*! BYPASS_EN_SETPOINT2 - BYPASS_EN_SETPOINT2 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK (0x8U) #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT (3U) /*! BYPASS_EN_SETPOINT3 - BYPASS_EN_SETPOINT3 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK (0x10U) #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT (4U) /*! BYPASS_EN_SETPOINT4 - BYPASS_EN_SETPOINT4 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK (0x20U) #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT (5U) /*! BYPASS_EN_SETPOINT5 - BYPASS_EN_SETPOINT5 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK (0x40U) #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT (6U) /*! BYPASS_EN_SETPOINT6 - BYPASS_EN_SETPOINT6 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK (0x80U) #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT (7U) /*! BYPASS_EN_SETPOINT7 - BYPASS_EN_SETPOINT7 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK (0x100U) #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT (8U) /*! BYPASS_EN_SETPOINT8 - BYPASS_EN_SETPOINT + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK (0x200U) #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT (9U) /*! BYPASS_EN_SETPOINT9 - BYPASS_EN_SETPOINT9 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK (0x400U) #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT (10U) /*! BYPASS_EN_SETPOINT10 - BYPASS_EN_SETPOINT10 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK (0x800U) #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT (11U) /*! BYPASS_EN_SETPOINT11 - BYPASS_EN_SETPOINT11 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK (0x1000U) #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT (12U) /*! BYPASS_EN_SETPOINT12 - BYPASS_EN_SETPOINT12 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK (0x2000U) #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT (13U) /*! BYPASS_EN_SETPOINT13 - BYPASS_EN_SETPOINT13 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK (0x4000U) #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT (14U) /*! BYPASS_EN_SETPOINT14 - BYPASS_EN_SETPOINT14 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK (0x8000U) #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT (15U) /*! BYPASS_EN_SETPOINT15 - BYPASS_EN_SETPOINT15 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK) /*! @} */ /*! @name LDO_LPSR_ANA_STBY_EN_SP - LDO_LPSR_ANA_STBY_EN_SP_REGISTER */ /*! @{ */ + #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U) #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U) /*! STBY_EN_SETPOINT0 - STBY_EN_SETPOINT0 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U) #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U) /*! STBY_EN_SETPOINT1 - STBY_EN_SETPOINT1 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U) #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U) /*! STBY_EN_SETPOINT2 - STBY_EN_SETPOINT2 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U) #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U) /*! STBY_EN_SETPOINT3 - STBY_EN_SETPOINT3 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U) #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U) /*! STBY_EN_SETPOINT4 - STBY_EN_SETPOINT4 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U) #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U) /*! STBY_EN_SETPOINT5 - STBY_EN_SETPOINT5 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U) #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U) /*! STBY_EN_SETPOINT6 - STBY_EN_SETPOINT6 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U) #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U) /*! STBY_EN_SETPOINT7 - STBY_EN_SETPOINT7 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U) #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U) /*! STBY_EN_SETPOINT8 - STBY_EN_SETPOINT8 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U) #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U) /*! STBY_EN_SETPOINT9 - STBY_EN_SETPOINT9 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U) #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U) /*! STBY_EN_SETPOINT10 - STBY_EN_SETPOINT10 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U) #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U) /*! STBY_EN_SETPOINT11 - STBY_EN_SETPOINT11 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U) #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U) /*! STBY_EN_SETPOINT12 - STBY_EN_SETPOINT12 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U) #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U) /*! STBY_EN_SETPOINT13 - STBY_EN_SETPOINT13 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U) #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U) /*! STBY_EN_SETPOINT14 - STBY_EN_SETPOINT14 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_MASK) + #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U) #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U) /*! STBY_EN_SETPOINT15 - STBY_EN_SETPOINT15 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_MASK) /*! @} */ /*! @name LDO_LPSR_DIG_ENABLE_SP - LDO_LPSR_DIG_ENABLE_SP_REGISTER */ /*! @{ */ + #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U) #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U) /*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U) #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U) /*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U) #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U) /*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U) #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U) /*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U) #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U) /*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U) #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U) /*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U) #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U) /*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U) #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U) /*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U) #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U) /*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U) #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U) /*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U) #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U) /*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U) #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U) /*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U) #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U) /*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U) #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U) /*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U) #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U) /*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U) #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U) /*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_MASK) /*! @} */ /*! @name LDO_LPSR_DIG_TRG_SP0 - LDO_LPSR_DIG_TRG_SP0_REGISTER */ /*! @{ */ + #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_MASK (0xFFU) #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_SHIFT (0U) /*! VOLTAGE_SETPOINT0 - VOLTAGE_SETPOINT0 */ #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_MASK (0xFF00U) #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_SHIFT (8U) /*! VOLTAGE_SETPOINT1 - VOLTAGE_SETPOINT1 */ #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_MASK (0xFF0000U) #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_SHIFT (16U) /*! VOLTAGE_SETPOINT2 - VOLTAGE_SETPOINT2 */ #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_MASK (0xFF000000U) #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_SHIFT (24U) /*! VOLTAGE_SETPOINT3 - VOLTAGE_SETPOINT3 @@ -7265,21 +7478,25 @@ typedef struct { /*! @name LDO_LPSR_DIG_TRG_SP1 - LDO_LPSR_DIG_TRG_SP1_REGISTER */ /*! @{ */ + #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_MASK (0xFFU) #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_SHIFT (0U) /*! VOLTAGE_SETPOINT4 - VOLTAGE_SETPOINT4 */ #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_MASK (0xFF00U) #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_SHIFT (8U) /*! VOLTAGE_SETPOINT5 - VOLTAGE_SETPOINT5 */ #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_MASK (0xFF0000U) #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_SHIFT (16U) /*! VOLTAGE_SETPOINT6 - VOLTAGE_SETPOINT6 */ #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_MASK (0xFF000000U) #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_SHIFT (24U) /*! VOLTAGE_SETPOINT7 - VOLTAGE_SETPOINT7 @@ -7289,21 +7506,25 @@ typedef struct { /*! @name LDO_LPSR_DIG_TRG_SP2 - LDO_LPSR_DIG_TRG_SP2_REGISTER */ /*! @{ */ + #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_MASK (0xFFU) #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_SHIFT (0U) /*! VOLTAGE_SETPOINT8 - VOLTAGE_SETPOINT8 */ #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_MASK (0xFF00U) #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_SHIFT (8U) /*! VOLTAGE_SETPOINT9 - VOLTAGE_SETPOINT9 */ #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_MASK (0xFF0000U) #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_SHIFT (16U) /*! VOLTAGE_SETPOINT10 - VOLTAGE_SETPOINT10 */ #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_MASK (0xFF000000U) #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_SHIFT (24U) /*! VOLTAGE_SETPOINT11 - VOLTAGE_SETPOINT11 @@ -7313,21 +7534,25 @@ typedef struct { /*! @name LDO_LPSR_DIG_TRG_SP3 - LDO_LPSR_DIG_TRG_SP3_REGISTER */ /*! @{ */ + #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_MASK (0xFFU) #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_SHIFT (0U) /*! VOLTAGE_SETPOINT12 - VOLTAGE_SETPOINT12 */ #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_MASK (0xFF00U) #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_SHIFT (8U) /*! VOLTAGE_SETPOINT13 - VOLTAGE_SETPOINT13 */ #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_MASK (0xFF0000U) #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_SHIFT (16U) /*! VOLTAGE_SETPOINT14 - VOLTAGE_SETPOINT14 */ #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_MASK (0xFF000000U) #define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_SHIFT (24U) /*! VOLTAGE_SETPOINT15 - VOLTAGE_SETPOINT15 @@ -7337,1113 +7562,1741 @@ typedef struct { /*! @name LDO_LPSR_DIG_LP_MODE_SP - LDO_LPSR_DIG_LP_MODE_SP_REGISTER */ /*! @{ */ + #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_MASK (0x1U) #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT (0U) /*! LP_MODE_SETPOINT0 - LP_MODE_SETPOINT0 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_MASK (0x2U) #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT (1U) /*! LP_MODE_SETPOINT1 - LP_MODE_SETPOINT1 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_MASK (0x4U) #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_SHIFT (2U) /*! LP_MODE_SETPOINT2 - LP_MODE_SETPOINT2 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_MASK (0x8U) #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_SHIFT (3U) /*! LP_MODE_SETPOINT3 - LP_MODE_SETPOINT3 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_MASK (0x10U) #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_SHIFT (4U) /*! LP_MODE_SETPOINT4 - LP_MODE_SETPOINT4 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_MASK (0x20U) #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_SHIFT (5U) /*! LP_MODE_SETPOINT5 - LP_MODE_SETPOINT5 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_MASK (0x40U) #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_SHIFT (6U) /*! LP_MODE_SETPOINT6 - LP_MODE_SETPOINT6 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_MASK (0x80U) #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_SHIFT (7U) /*! LP_MODE_SETPOINT7 - LP_MODE_SETPOINT7 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_MASK (0x100U) #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_SHIFT (8U) /*! LP_MODE_SETPOINT8 - LP_MODE_SETPOINT8 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_MASK (0x200U) #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_SHIFT (9U) /*! LP_MODE_SETPOINT9 - LP_MODE_SETPOINT9 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_MASK (0x400U) #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_SHIFT (10U) /*! LP_MODE_SETPOINT10 - LP_MODE_SETPOINT10 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_MASK (0x800U) #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_SHIFT (11U) /*! LP_MODE_SETPOINT11 - LP_MODE_SETPOINT11 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_MASK (0x1000U) #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_SHIFT (12U) /*! LP_MODE_SETPOINT12 - LP_MODE_SETPOINT12 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_MASK (0x2000U) #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_SHIFT (13U) /*! LP_MODE_SETPOINT13 - LP_MODE_SETPOINT13 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_MASK (0x4000U) #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_SHIFT (14U) /*! LP_MODE_SETPOINT14 - LP_MODE_SETPOINT14 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_MASK (0x8000U) #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_SHIFT (15U) /*! LP_MODE_SETPOINT15 - LP_MODE_SETPOINT15 + * 0b0..LP + * 0b1..HP */ #define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_MASK) /*! @} */ /*! @name LDO_LPSR_DIG_TRACKING_EN_SP - LDO_LPSR_DIG_TRACKING_EN_SP_REGISTER */ /*! @{ */ + #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK (0x1U) #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT (0U) /*! TRACKING_EN_SETPOINT0 - TRACKING_EN_SETPOINT0 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK (0x2U) #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT (1U) /*! TRACKING_EN_SETPOINT1 - TRACKING_EN_SETPOINT1 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK (0x4U) #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT (2U) /*! TRACKING_EN_SETPOINT2 - TRACKING_EN_SETPOINT2 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK (0x8U) #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT (3U) /*! TRACKING_EN_SETPOINT3 - TRACKING_EN_SETPOINT3 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK (0x10U) #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT (4U) /*! TRACKING_EN_SETPOINT4 - TRACKING_EN_SETPOINT4 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK (0x20U) #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT (5U) /*! TRACKING_EN_SETPOINT5 - TRACKING_EN_SETPOINT5 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK (0x40U) #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT (6U) /*! TRACKING_EN_SETPOINT6 - TRACKING_EN_SETPOINT6 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK (0x80U) #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT (7U) /*! TRACKING_EN_SETPOINT7 - TRACKING_EN_SETPOINT7 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK (0x100U) #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT (8U) /*! TRACKING_EN_SETPOINT8 - TRACKING_EN_SETPOINT8 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK (0x200U) #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT (9U) /*! TRACKING_EN_SETPOINT9 - TRACKING_EN_SETPOINT9 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK (0x400U) #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT (10U) /*! TRACKING_EN_SETPOINT10 - TRACKING_EN_SETPOINT10 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK (0x800U) #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT (11U) /*! TRACKING_EN_SETPOINT11 - TRACKING_EN_SETPOINT11 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK (0x1000U) #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT (12U) /*! TRACKING_EN_SETPOINT12 - TRACKING_EN_SETPOINT12 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK (0x2000U) #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT (13U) /*! TRACKING_EN_SETPOINT13 - TRACKING_EN_SETPOINT13 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK (0x4000U) #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT (14U) /*! TRACKING_EN_SETPOINT14 - TRACKING_EN_SETPOINT14 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK (0x8000U) #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT (15U) /*! TRACKING_EN_SETPOINT15 - TRACKING_EN_SETPOINT15 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK) /*! @} */ /*! @name LDO_LPSR_DIG_BYPASS_EN_SP - LDO_LPSR_DIG_BYPASS_EN_SP_REGISTER */ /*! @{ */ + #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK (0x1U) #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT (0U) /*! BYPASS_EN_SETPOINT0 - BYPASS_EN_SETPOINT0 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK (0x2U) #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT (1U) /*! BYPASS_EN_SETPOINT1 - BYPASS_EN_SETPOINT1 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK (0x4U) #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT (2U) /*! BYPASS_EN_SETPOINT2 - BYPASS_EN_SETPOINT2 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK (0x8U) #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT (3U) /*! BYPASS_EN_SETPOINT3 - BYPASS_EN_SETPOINT3 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK (0x10U) #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT (4U) /*! BYPASS_EN_SETPOINT4 - BYPASS_EN_SETPOINT4 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK (0x20U) #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT (5U) /*! BYPASS_EN_SETPOINT5 - BYPASS_EN_SETPOINT5 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK (0x40U) #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT (6U) /*! BYPASS_EN_SETPOINT6 - BYPASS_EN_SETPOINT6 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK (0x80U) #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT (7U) /*! BYPASS_EN_SETPOINT7 - BYPASS_EN_SETPOINT7 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK (0x100U) #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT (8U) /*! BYPASS_EN_SETPOINT8 - BYPASS_EN_SETPOINT8 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK (0x200U) #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT (9U) /*! BYPASS_EN_SETPOINT9 - BYPASS_EN_SETPOINT9 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK (0x400U) #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT (10U) /*! BYPASS_EN_SETPOINT10 - BYPASS_EN_SETPOINT10 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK (0x800U) #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT (11U) /*! BYPASS_EN_SETPOINT11 - BYPASS_EN_SETPOINT11 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK (0x1000U) #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT (12U) /*! BYPASS_EN_SETPOINT12 - BYPASS_EN_SETPOINT12 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK (0x2000U) #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT (13U) /*! BYPASS_EN_SETPOINT13 - BYPASS_EN_SETPOINT13 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK (0x4000U) #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT (14U) /*! BYPASS_EN_SETPOINT14 - BYPASS_EN_SETPOINT14 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK (0x8000U) #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT (15U) /*! BYPASS_EN_SETPOINT15 - BYPASS_EN_SETPOINT15 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK) /*! @} */ /*! @name LDO_LPSR_DIG_STBY_EN_SP - LDO_LPSR_DIG_STBY_EN_SP_REGISTER */ /*! @{ */ + #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U) #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U) /*! STBY_EN_SETPOINT0 - STBY_EN_SETPOINT0 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U) #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U) /*! STBY_EN_SETPOINT1 - STBY_EN_SETPOINT1 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U) #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U) /*! STBY_EN_SETPOINT2 - STBY_EN_SETPOINT2 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U) #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U) /*! STBY_EN_SETPOINT3 - STBY_EN_SETPOINT3 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U) #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U) /*! STBY_EN_SETPOINT4 - STBY_EN_SETPOINT4 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U) #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U) /*! STBY_EN_SETPOINT5 - STBY_EN_SETPOINT5 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U) #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U) /*! STBY_EN_SETPOINT6 - STBY_EN_SETPOINT6 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U) #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U) /*! STBY_EN_SETPOINT7 - STBY_EN_SETPOINT7 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U) #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U) /*! STBY_EN_SETPOINT8 - STBY_EN_SETPOINT8 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U) #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U) /*! STBY_EN_SETPOINT9 - STBY_EN_SETPOINT9 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U) #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U) /*! STBY_EN_SETPOINT10 - STBY_EN_SETPOINT10 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U) #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U) /*! STBY_EN_SETPOINT11 - STBY_EN_SETPOINT11 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U) #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U) /*! STBY_EN_SETPOINT12 - STBY_EN_SETPOINT12 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U) #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U) /*! STBY_EN_SETPOINT13 - STBY_EN_SETPOINT13 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U) #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U) /*! STBY_EN_SETPOINT14 - STBY_EN_SETPOINT14 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_MASK) + #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U) #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U) /*! STBY_EN_SETPOINT15 - STBY_EN_SETPOINT15 + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_MASK) /*! @} */ /*! @name BANDGAP_ENABLE_SP - BANDGAP_ENABLE_SP_REGISTER */ /*! @{ */ + #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U) #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U) /*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_MASK) + #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U) #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U) /*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_MASK) + #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U) #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U) /*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_MASK) + #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U) #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U) /*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_MASK) + #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U) #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U) /*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_MASK) + #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U) #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U) /*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_MASK) + #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U) #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U) /*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT5 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_MASK) + #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U) #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U) /*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_MASK) + #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U) #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U) /*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_MASK) + #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U) #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U) /*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_MASK) + #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U) #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U) /*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_MASK) + #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U) #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U) /*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_MASK) + #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U) #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U) /*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_MASK) + #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U) #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U) /*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_MASK) + #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U) #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U) /*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_MASK) + #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U) #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U) /*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_MASK) /*! @} */ /*! @name FBB_M7_ENABLE_SP - FBB_M7_ENABLE_SP_REGISTER */ /*! @{ */ + #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U) #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U) /*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT0_MASK) + #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U) #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U) /*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT1_MASK) + #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U) #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U) /*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT2_MASK) + #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U) #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U) /*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT3_MASK) + #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U) #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U) /*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT4_MASK) + #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U) #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U) /*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT5_MASK) + #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U) #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U) /*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT6_MASK) + #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U) #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U) /*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT7_MASK) + #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U) #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U) /*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT8_MASK) + #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U) #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U) /*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT9_MASK) + #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U) #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U) /*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT10_MASK) + #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U) #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U) /*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT11_MASK) + #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U) #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U) /*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT12_MASK) + #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U) #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U) /*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT13_MASK) + #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U) #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U) /*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT14_MASK) + #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U) #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U) /*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT15_MASK) /*! @} */ /*! @name RBB_SOC_ENABLE_SP - RBB_SOC_ENABLE_SP_REGISTER */ /*! @{ */ + #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U) #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U) /*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_MASK) + #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U) #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U) /*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_MASK) + #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U) #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U) /*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_MASK) + #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U) #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U) /*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_MASK) + #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U) #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U) /*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_MASK) + #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U) #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U) /*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_MASK) + #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U) #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U) /*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_MASK) + #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U) #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U) /*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_MASK) + #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U) #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U) /*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_MASK) + #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U) #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U) /*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_MASK) + #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U) #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U) /*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_MASK) + #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U) #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U) /*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_MASK) + #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U) #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U) /*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_MASK) + #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U) #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U) /*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_MASK) + #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U) #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U) /*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_MASK) + #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U) #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U) /*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_MASK) /*! @} */ /*! @name RBB_LPSR_ENABLE_SP - RBB_LPSR_ENABLE_SP_REGISTER */ /*! @{ */ + #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U) #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U) /*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_MASK) + #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U) #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U) /*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_MASK) + #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U) #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U) /*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_MASK) + #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U) #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U) /*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_MASK) + #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U) #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U) /*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_MASK) + #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U) #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U) /*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_MASK) + #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U) #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U) /*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_MASK) + #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U) #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U) /*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_MASK) + #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U) #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U) /*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_MASK) + #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U) #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U) /*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_MASK) + #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U) #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U) /*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_MASK) + #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U) #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U) /*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_MASK) + #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U) #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U) /*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_MASK) + #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U) #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U) /*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_MASK) + #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U) #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U) /*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_MASK) + #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U) #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U) /*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15 + * 0b0..ON + * 0b1..OFF */ #define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_MASK) /*! @} */ /*! @name BANDGAP_STBY_EN_SP - BANDGAP_STBY_EN_SP_REGISTER */ /*! @{ */ + #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U) #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U) /*! STBY_EN_SETPOINT0 - STBY_EN_SETPOINT + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_MASK) + #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U) #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U) /*! STBY_EN_SETPOINT1 - STBY_EN_SETPOINT + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_MASK) + #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U) #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U) /*! STBY_EN_SETPOINT2 - STBY_EN_SETPOINT + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_MASK) + #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U) #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U) /*! STBY_EN_SETPOINT3 - STBY_EN_SETPOINT + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_MASK) + #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U) #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U) /*! STBY_EN_SETPOINT4 - STBY_EN_SETPOINT + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_MASK) + #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U) #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U) /*! STBY_EN_SETPOINT5 - STBY_EN_SETPOINT + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_MASK) + #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U) #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U) /*! STBY_EN_SETPOINT6 - STBY_EN_SETPOINT + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_MASK) + #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U) #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U) /*! STBY_EN_SETPOINT7 - STBY_EN_SETPOINT + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_MASK) + #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U) #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U) /*! STBY_EN_SETPOINT8 - STBY_EN_SETPOINT + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_MASK) + #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U) #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U) /*! STBY_EN_SETPOINT9 - STBY_EN_SETPOINT + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_MASK) + #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U) #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U) /*! STBY_EN_SETPOINT10 - STBY_EN_SETPOINT + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_MASK) + #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U) #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U) /*! STBY_EN_SETPOINT11 - STBY_EN_SETPOINT + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_MASK) + #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U) #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U) /*! STBY_EN_SETPOINT12 - STBY_EN_SETPOINT + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_MASK) + #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U) #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U) /*! STBY_EN_SETPOINT13 - STBY_EN_SETPOINT + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_MASK) + #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U) #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U) /*! STBY_EN_SETPOINT14 - STBY_EN_SETPOINT + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_MASK) + #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U) #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U) /*! STBY_EN_SETPOINT15 - STBY_EN_SETPOINT + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_MASK) /*! @} */ /*! @name PLL_LDO_STBY_EN_SP - PLL_LDO_STBY_EN_SP_REGISTER */ /*! @{ */ + #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U) #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U) -/*! STBY_EN_SETPOINT0 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT0 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_MASK) + #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U) #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U) -/*! STBY_EN_SETPOINT1 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT1 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_MASK) + #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U) #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U) -/*! STBY_EN_SETPOINT2 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT2 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_MASK) + #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U) #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U) -/*! STBY_EN_SETPOINT3 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT3 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_MASK) + #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U) #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U) -/*! STBY_EN_SETPOINT4 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT4 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_MASK) + #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U) #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U) -/*! STBY_EN_SETPOINT5 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT5 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_MASK) + #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U) #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U) -/*! STBY_EN_SETPOINT6 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT6 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_MASK) + #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U) #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U) -/*! STBY_EN_SETPOINT7 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT7 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_MASK) + #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U) #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U) -/*! STBY_EN_SETPOINT8 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT8 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_MASK) + #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U) #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U) -/*! STBY_EN_SETPOINT9 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT9 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_MASK) + #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U) #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U) -/*! STBY_EN_SETPOINT10 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT10 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_MASK) + #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U) #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U) -/*! STBY_EN_SETPOINT11 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT11 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_MASK) + #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U) #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U) -/*! STBY_EN_SETPOINT12 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT12 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_MASK) + #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U) #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U) -/*! STBY_EN_SETPOINT13 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT13 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_MASK) + #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U) #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U) -/*! STBY_EN_SETPOINT14 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT14 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_MASK) + #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U) #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U) -/*! STBY_EN_SETPOINT15 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT15 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_MASK) /*! @} */ /*! @name FBB_M7_STBY_EN_SP - FBB_M7_STBY_EN_SP_REGISTER */ /*! @{ */ + #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U) #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U) -/*! STBY_EN_SETPOINT0 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT0 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT0_MASK) + #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U) #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U) -/*! STBY_EN_SETPOINT1 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT1 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT1_MASK) + #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U) #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U) -/*! STBY_EN_SETPOINT2 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT2 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT2_MASK) + #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U) #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U) -/*! STBY_EN_SETPOINT3 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT3 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT3_MASK) + #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U) #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U) -/*! STBY_EN_SETPOINT4 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT4 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT4_MASK) + #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U) #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U) -/*! STBY_EN_SETPOINT5 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT5 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT5_MASK) + #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U) #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U) -/*! STBY_EN_SETPOINT6 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT6 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT6_MASK) + #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U) #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U) -/*! STBY_EN_SETPOINT7 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT7 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT7_MASK) + #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U) #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U) -/*! STBY_EN_SETPOINT8 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT8 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT8_MASK) + #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U) #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U) -/*! STBY_EN_SETPOINT9 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT9 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT9_MASK) + #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U) #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U) -/*! STBY_EN_SETPOINT10 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT10 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT10_MASK) + #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U) #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U) -/*! STBY_EN_SETPOINT11 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT11 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT11_MASK) + #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U) #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U) -/*! STBY_EN_SETPOINT12 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT12 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT12_MASK) + #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U) #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U) -/*! STBY_EN_SETPOINT13 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT13 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT13_MASK) + #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U) #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U) -/*! STBY_EN_SETPOINT14 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT14 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT14_MASK) + #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U) #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U) -/*! STBY_EN_SETPOINT15 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT15 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT15_MASK) /*! @} */ /*! @name RBB_SOC_STBY_EN_SP - RBB_SOC_STBY_EN_SP_REGISTER */ /*! @{ */ + #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U) #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U) -/*! STBY_EN_SETPOINT0 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT0 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_MASK) + #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U) #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U) -/*! STBY_EN_SETPOINT1 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT1 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_MASK) + #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U) #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U) -/*! STBY_EN_SETPOINT2 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT2 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_MASK) + #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U) #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U) -/*! STBY_EN_SETPOINT3 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT3 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_MASK) + #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U) #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U) -/*! STBY_EN_SETPOINT4 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT4 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_MASK) + #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U) #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U) -/*! STBY_EN_SETPOINT5 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT5 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_MASK) + #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U) #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U) -/*! STBY_EN_SETPOINT6 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT6 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_MASK) + #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U) #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U) -/*! STBY_EN_SETPOINT7 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT7 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_MASK) + #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U) #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U) -/*! STBY_EN_SETPOINT8 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT8 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_MASK) + #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U) #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U) -/*! STBY_EN_SETPOINT9 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT9 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_MASK) + #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U) #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U) -/*! STBY_EN_SETPOINT10 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT10 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_MASK) + #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U) #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U) -/*! STBY_EN_SETPOINT11 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT11 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_MASK) + #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U) #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U) -/*! STBY_EN_SETPOINT12 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT12 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_MASK) + #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U) #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U) -/*! STBY_EN_SETPOINT13 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT13 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_MASK) + #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U) #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U) -/*! STBY_EN_SETPOINT14 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT14 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_MASK) + #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U) #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U) -/*! STBY_EN_SETPOINT15 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT15 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_MASK) /*! @} */ /*! @name RBB_LPSR_STBY_EN_SP - RBB_LPSR_STBY_EN_SP_REGISTER */ /*! @{ */ + #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U) #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U) -/*! STBY_EN_SETPOINT0 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT0 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_MASK) + #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U) #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U) -/*! STBY_EN_SETPOINT1 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT1 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_MASK) + #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U) #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U) -/*! STBY_EN_SETPOINT2 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT2 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_MASK) + #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U) #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U) -/*! STBY_EN_SETPOINT3 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT3 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_MASK) + #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U) #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U) -/*! STBY_EN_SETPOINT4 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT4 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_MASK) + #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U) #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U) -/*! STBY_EN_SETPOINT5 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT5 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_MASK) + #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U) #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U) -/*! STBY_EN_SETPOINT6 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT6 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_MASK) + #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U) #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U) -/*! STBY_EN_SETPOINT7 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT7 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_MASK) + #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U) #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U) -/*! STBY_EN_SETPOINT8 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT8 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_MASK) + #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U) #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U) -/*! STBY_EN_SETPOINT9 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT9 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_MASK) + #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U) #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U) -/*! STBY_EN_SETPOINT10 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT10 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_MASK) + #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U) #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U) -/*! STBY_EN_SETPOINT11 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT11 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_MASK) + #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U) #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U) -/*! STBY_EN_SETPOINT12 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT12 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_MASK) + #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U) #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U) -/*! STBY_EN_SETPOINT13 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT13 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_MASK) + #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U) #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U) -/*! STBY_EN_SETPOINT14 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT14 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_MASK) + #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U) #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U) -/*! STBY_EN_SETPOINT15 - 1-STBY mode is enable 0-STBY mode is diable +/*! STBY_EN_SETPOINT15 - Standby mode + * 0b0..Disabled + * 0b1..Enabled */ #define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_MASK) /*! @} */ /*! @name FBB_M7_CONFIGURE - FBB_M7_CONFIGURE_REGISTER */ /*! @{ */ + #define ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_PW_MASK (0xFU) #define ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_PW_SHIFT (0U) /*! WB_CFG_PW - wb_cfg_pw */ #define ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_PW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_PW_SHIFT)) & ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_PW_MASK) + #define ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_NW_MASK (0xF0U) #define ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_NW_SHIFT (4U) /*! WB_CFG_NW - wb_cfg_nw */ #define ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_NW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_NW_SHIFT)) & ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_NW_MASK) + #define ANADIG_PMU_FBB_M7_CONFIGURE_OSCILLATOR_BITS_MASK (0x700U) #define ANADIG_PMU_FBB_M7_CONFIGURE_OSCILLATOR_BITS_SHIFT (8U) /*! OSCILLATOR_BITS - oscillator_bits */ #define ANADIG_PMU_FBB_M7_CONFIGURE_OSCILLATOR_BITS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_CONFIGURE_OSCILLATOR_BITS_SHIFT)) & ANADIG_PMU_FBB_M7_CONFIGURE_OSCILLATOR_BITS_MASK) + #define ANADIG_PMU_FBB_M7_CONFIGURE_REGULATOR_STRENGTH_MASK (0x3800U) #define ANADIG_PMU_FBB_M7_CONFIGURE_REGULATOR_STRENGTH_SHIFT (11U) /*! REGULATOR_STRENGTH - regulator_strength @@ -8453,21 +9306,25 @@ typedef struct { /*! @name RBB_LPSR_CONFIGURE - RBB_LPSR_CONFIGURE_REGISTER */ /*! @{ */ + #define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_MASK (0xFU) #define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_SHIFT (0U) /*! WB_CFG_PW - wb_cfg_pw */ #define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_SHIFT)) & ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_MASK) + #define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_MASK (0xF0U) #define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_SHIFT (4U) /*! WB_CFG_NW - wb_cfg_nw */ #define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_SHIFT)) & ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_MASK) + #define ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_MASK (0x700U) #define ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_SHIFT (8U) /*! OSCILLATOR_BITS - oscillator_bits */ #define ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_SHIFT)) & ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_MASK) + #define ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_MASK (0x3800U) #define ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_SHIFT (11U) /*! REGULATOR_STRENGTH - regulator_strength @@ -8477,21 +9334,25 @@ typedef struct { /*! @name RBB_SOC_CONFIGURE - RBB_SOC_CONFIGURE_REGISTER */ /*! @{ */ + #define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_MASK (0xFU) #define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_SHIFT (0U) /*! WB_CFG_PW - wb_cfg_pw */ #define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_SHIFT)) & ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_MASK) + #define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_MASK (0xF0U) #define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_SHIFT (4U) /*! WB_CFG_NW - wb_cfg_nw */ #define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_SHIFT)) & ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_MASK) + #define ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_MASK (0x700U) #define ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_SHIFT (8U) /*! OSCILLATOR_BITS - oscillator_bits */ #define ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_SHIFT)) & ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_MASK) + #define ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_MASK (0x3800U) #define ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_SHIFT (11U) /*! REGULATOR_STRENGTH - regulator_strength @@ -8501,16 +9362,19 @@ typedef struct { /*! @name REFTOP_OTP_TRIM_VALUE - REFTOP_OTP_TRIM_VALUE_REGISTER */ /*! @{ */ + #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_MASK (0x7U) #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_SHIFT (0U) /*! REFTOP_IBZTCADJ - REFTOP_IBZTCADJ */ #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_SHIFT)) & ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_MASK) + #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_MASK (0x38U) #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_SHIFT (3U) /*! REFTOP_VBGADJ - REFTOP_VBGADJ */ #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_SHIFT)) & ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_MASK) + #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_MASK (0x40U) #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_SHIFT (6U) /*! REFTOP_TRIM_EN - REFTOP_TRIM_EN @@ -8518,52 +9382,15 @@ typedef struct { #define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_SHIFT)) & ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_MASK) /*! @} */ -/*! @name WB_OTP_TRIM_VALUE - WB_OTP_TRIM_VALUE_REGISTER */ -/*! @{ */ -#define ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_CFG_9_MASK (0x1U) -#define ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_CFG_9_SHIFT (0U) -/*! WB_CFG_9 - WB_CFG_9 - */ -#define ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_CFG_9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_CFG_9_SHIFT)) & ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_CFG_9_MASK) -#define ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_CFG_11_10_MASK (0x6U) -#define ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_CFG_11_10_SHIFT (1U) -/*! WB_CFG_11_10 - WB_CFG_11_10 - */ -#define ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_CFG_11_10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_CFG_11_10_SHIFT)) & ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_CFG_11_10_MASK) -#define ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_NW_LVL_MASK (0x78U) -#define ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_NW_LVL_SHIFT (3U) -/*! WB_NW_LVL - WB_NW_LVL - */ -#define ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_NW_LVL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_NW_LVL_SHIFT)) & ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_NW_LVL_MASK) -#define ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_PW_LVL_MASK (0x780U) -#define ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_PW_LVL_SHIFT (7U) -/*! WB_PW_LVL - WB_PW_LVL - */ -#define ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_PW_LVL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_PW_LVL_SHIFT)) & ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_PW_LVL_MASK) -#define ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_ADJ_MASK (0x7F800U) -#define ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_ADJ_SHIFT (11U) -/*! WB_ADJ - WB_ADJ - */ -#define ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_ADJ(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_ADJ_SHIFT)) & ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_ADJ_MASK) -#define ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_IN_SP_MASK (0x7F80000U) -#define ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_IN_SP_SHIFT (19U) -/*! WB_IN_SP - WB_IN_SP - */ -#define ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_IN_SP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_IN_SP_SHIFT)) & ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_IN_SP_MASK) -#define ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_TRIM_EN_MASK (0x8000000U) -#define ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_TRIM_EN_SHIFT (27U) -/*! WB_TRIM_EN - WB_TRIM_EN - */ -#define ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_TRIM_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_TRIM_EN_SHIFT)) & ANADIG_PMU_WB_OTP_TRIM_VALUE_WB_TRIM_EN_MASK) -/*! @} */ - /*! @name LPSR_1P8_LDO_OTP_TRIM_VALUE - LPSR_1P8_LDO_OTP_TRIM_VALUE_REGISTER */ /*! @{ */ + #define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_MASK (0x3U) #define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_SHIFT (0U) /*! LPSR_LDO_1P8_TRIM - LPSR_LDO_1P8_TRIM */ #define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_SHIFT)) & ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_MASK) + #define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_MASK (0x4U) #define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_SHIFT (2U) /*! LPSR_LDO_1P8_TRIM_EN - LPSR_LDO_1P8_TRIM_EN @@ -8592,233 +9419,6 @@ typedef struct { */ /* end of group ANADIG_PMU_Peripheral_Access_Layer */ -/* ---------------------------------------------------------------------------- - -- ANADIG_PWRDET Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ANADIG_PWRDET_Peripheral_Access_Layer ANADIG_PWRDET Peripheral Access Layer - * @{ - */ - -/** ANADIG_PWRDET - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[1056]; - __IO uint32_t PWRDET; /**< PWRDET_REGISTER, offset: 0x420 */ -} ANADIG_PWRDET_Type; - -/* ---------------------------------------------------------------------------- - -- ANADIG_PWRDET Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ANADIG_PWRDET_Register_Masks ANADIG_PWRDET Register Masks - * @{ - */ - -/*! @name PWRDET - PWRDET_REGISTER */ -/*! @{ */ -#define ANADIG_PWRDET_PWRDET_EN_CURMIR_MASK (0x1U) -#define ANADIG_PWRDET_PWRDET_EN_CURMIR_SHIFT (0U) -/*! EN_CURMIR - en_curmir - */ -#define ANADIG_PWRDET_PWRDET_EN_CURMIR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PWRDET_PWRDET_EN_CURMIR_SHIFT)) & ANADIG_PWRDET_PWRDET_EN_CURMIR_MASK) -#define ANADIG_PWRDET_PWRDET_EN_UA_CURMIR_MASK (0x2U) -#define ANADIG_PWRDET_PWRDET_EN_UA_CURMIR_SHIFT (1U) -/*! EN_UA_CURMIR - en_ua_curmir - */ -#define ANADIG_PWRDET_PWRDET_EN_UA_CURMIR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PWRDET_PWRDET_EN_UA_CURMIR_SHIFT)) & ANADIG_PWRDET_PWRDET_EN_UA_CURMIR_MASK) -#define ANADIG_PWRDET_PWRDET_EN_NA_CURMIR_MASK (0x4U) -#define ANADIG_PWRDET_PWRDET_EN_NA_CURMIR_SHIFT (2U) -/*! EN_NA_CURMIR - en_na_curmir - */ -#define ANADIG_PWRDET_PWRDET_EN_NA_CURMIR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PWRDET_PWRDET_EN_NA_CURMIR_SHIFT)) & ANADIG_PWRDET_PWRDET_EN_NA_CURMIR_MASK) -#define ANADIG_PWRDET_PWRDET_EN_V2V_MASK (0x8U) -#define ANADIG_PWRDET_PWRDET_EN_V2V_SHIFT (3U) -/*! EN_V2V - en_v2v - */ -#define ANADIG_PWRDET_PWRDET_EN_V2V(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PWRDET_PWRDET_EN_V2V_SHIFT)) & ANADIG_PWRDET_PWRDET_EN_V2V_MASK) -#define ANADIG_PWRDET_PWRDET_EN_V2V_BUF_MASK (0x10U) -#define ANADIG_PWRDET_PWRDET_EN_V2V_BUF_SHIFT (4U) -/*! EN_V2V_BUF - en_v2v_buf - */ -#define ANADIG_PWRDET_PWRDET_EN_V2V_BUF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PWRDET_PWRDET_EN_V2V_BUF_SHIFT)) & ANADIG_PWRDET_PWRDET_EN_V2V_BUF_MASK) -#define ANADIG_PWRDET_PWRDET_V2V_TEST_EN_MASK (0x20U) -#define ANADIG_PWRDET_PWRDET_V2V_TEST_EN_SHIFT (5U) -/*! V2V_TEST_EN - v2v_test_en - */ -#define ANADIG_PWRDET_PWRDET_V2V_TEST_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PWRDET_PWRDET_V2V_TEST_EN_SHIFT)) & ANADIG_PWRDET_PWRDET_V2V_TEST_EN_MASK) -#define ANADIG_PWRDET_PWRDET_V2V_1VTRIM_MASK (0x1C0U) -#define ANADIG_PWRDET_PWRDET_V2V_1VTRIM_SHIFT (6U) -/*! V2V_1VTRIM - v2v_1vtrim - */ -#define ANADIG_PWRDET_PWRDET_V2V_1VTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PWRDET_PWRDET_V2V_1VTRIM_SHIFT)) & ANADIG_PWRDET_PWRDET_V2V_1VTRIM_MASK) -#define ANADIG_PWRDET_PWRDET_V2V_TEST_SEL_MASK (0x600U) -#define ANADIG_PWRDET_PWRDET_V2V_TEST_SEL_SHIFT (9U) -/*! V2V_TEST_SEL - v2v_test_sel - */ -#define ANADIG_PWRDET_PWRDET_V2V_TEST_SEL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PWRDET_PWRDET_V2V_TEST_SEL_SHIFT)) & ANADIG_PWRDET_PWRDET_V2V_TEST_SEL_MASK) -#define ANADIG_PWRDET_PWRDET_LOWPWR_SETTLE_DETECT_EN_MASK (0x800U) -#define ANADIG_PWRDET_PWRDET_LOWPWR_SETTLE_DETECT_EN_SHIFT (11U) -/*! LOWPWR_SETTLE_DETECT_EN - lowpwr_settle_detect_en - */ -#define ANADIG_PWRDET_PWRDET_LOWPWR_SETTLE_DETECT_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PWRDET_PWRDET_LOWPWR_SETTLE_DETECT_EN_SHIFT)) & ANADIG_PWRDET_PWRDET_LOWPWR_SETTLE_DETECT_EN_MASK) -#define ANADIG_PWRDET_PWRDET_LOWPWR_SETTLE_DETECT_SEL_MASK (0x1000U) -#define ANADIG_PWRDET_PWRDET_LOWPWR_SETTLE_DETECT_SEL_SHIFT (12U) -/*! LOWPWR_SETTLE_DETECT_SEL - lowpwr_settle_detect_sel - */ -#define ANADIG_PWRDET_PWRDET_LOWPWR_SETTLE_DETECT_SEL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PWRDET_PWRDET_LOWPWR_SETTLE_DETECT_SEL_SHIFT)) & ANADIG_PWRDET_PWRDET_LOWPWR_SETTLE_DETECT_SEL_MASK) -#define ANADIG_PWRDET_PWRDET_LOWPWR_SETTLE_DELAY_EN_MASK (0x2000U) -#define ANADIG_PWRDET_PWRDET_LOWPWR_SETTLE_DELAY_EN_SHIFT (13U) -/*! LOWPWR_SETTLE_DELAY_EN - lowpwr_settle_delay_en - */ -#define ANADIG_PWRDET_PWRDET_LOWPWR_SETTLE_DELAY_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PWRDET_PWRDET_LOWPWR_SETTLE_DELAY_EN_SHIFT)) & ANADIG_PWRDET_PWRDET_LOWPWR_SETTLE_DELAY_EN_MASK) -#define ANADIG_PWRDET_PWRDET_PS_TEST_EN_MASK (0x4000U) -#define ANADIG_PWRDET_PWRDET_PS_TEST_EN_SHIFT (14U) -/*! PS_TEST_EN - ps_test_en - */ -#define ANADIG_PWRDET_PWRDET_PS_TEST_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PWRDET_PWRDET_PS_TEST_EN_SHIFT)) & ANADIG_PWRDET_PWRDET_PS_TEST_EN_MASK) -#define ANADIG_PWRDET_PWRDET_PS_TEST_SEL_MASK (0x8000U) -#define ANADIG_PWRDET_PWRDET_PS_TEST_SEL_SHIFT (15U) -/*! PS_TEST_SEL - ps_test_sel - */ -#define ANADIG_PWRDET_PWRDET_PS_TEST_SEL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PWRDET_PWRDET_PS_TEST_SEL_SHIFT)) & ANADIG_PWRDET_PWRDET_PS_TEST_SEL_MASK) -#define ANADIG_PWRDET_PWRDET_VDD_SOC_OK_MASK (0x10000U) -#define ANADIG_PWRDET_PWRDET_VDD_SOC_OK_SHIFT (16U) -/*! VDD_SOC_OK - vdd_soc_ok - */ -#define ANADIG_PWRDET_PWRDET_VDD_SOC_OK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PWRDET_PWRDET_VDD_SOC_OK_SHIFT)) & ANADIG_PWRDET_PWRDET_VDD_SOC_OK_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ANADIG_PWRDET_Register_Masks */ - - -/* ANADIG_PWRDET - Peripheral instance base addresses */ -/** Peripheral ANADIG_PWRDET base address */ -#define ANADIG_PWRDET_BASE (0x40C84000u) -/** Peripheral ANADIG_PWRDET base pointer */ -#define ANADIG_PWRDET ((ANADIG_PWRDET_Type *)ANADIG_PWRDET_BASE) -/** Array initializer of ANADIG_PWRDET peripheral base addresses */ -#define ANADIG_PWRDET_BASE_ADDRS { ANADIG_PWRDET_BASE } -/** Array initializer of ANADIG_PWRDET peripheral base pointers */ -#define ANADIG_PWRDET_BASE_PTRS { ANADIG_PWRDET } - -/*! - * @} - */ /* end of group ANADIG_PWRDET_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- ANADIG_SPARE_REGS_LPSR Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ANADIG_SPARE_REGS_LPSR_Peripheral_Access_Layer ANADIG_SPARE_REGS_LPSR Peripheral Access Layer - * @{ - */ - -/** ANADIG_SPARE_REGS_LPSR - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[2384]; - __IO uint32_t SPARE_REGS_LPSR; /**< SPARE_REGS_LPSR_REGISTER, offset: 0x950 */ -} ANADIG_SPARE_REGS_LPSR_Type; - -/* ---------------------------------------------------------------------------- - -- ANADIG_SPARE_REGS_LPSR Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ANADIG_SPARE_REGS_LPSR_Register_Masks ANADIG_SPARE_REGS_LPSR Register Masks - * @{ - */ - -/*! @name SPARE_REGS_LPSR - SPARE_REGS_LPSR_REGISTER */ -/*! @{ */ -#define ANADIG_SPARE_REGS_LPSR_SPARE_REGS_LPSR_SPARE_REG_LPSR_MASK (0xFFFFFFFFU) -#define ANADIG_SPARE_REGS_LPSR_SPARE_REGS_LPSR_SPARE_REG_LPSR_SHIFT (0U) -/*! SPARE_REG_LPSR - spare_reg_lpsr - */ -#define ANADIG_SPARE_REGS_LPSR_SPARE_REGS_LPSR_SPARE_REG_LPSR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_SPARE_REGS_LPSR_SPARE_REGS_LPSR_SPARE_REG_LPSR_SHIFT)) & ANADIG_SPARE_REGS_LPSR_SPARE_REGS_LPSR_SPARE_REG_LPSR_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ANADIG_SPARE_REGS_LPSR_Register_Masks */ - - -/* ANADIG_SPARE_REGS_LPSR - Peripheral instance base addresses */ -/** Peripheral ANADIG_SPARE_REGS_LPSR base address */ -#define ANADIG_SPARE_REGS_LPSR_BASE (0x40C84000u) -/** Peripheral ANADIG_SPARE_REGS_LPSR base pointer */ -#define ANADIG_SPARE_REGS_LPSR ((ANADIG_SPARE_REGS_LPSR_Type *)ANADIG_SPARE_REGS_LPSR_BASE) -/** Array initializer of ANADIG_SPARE_REGS_LPSR peripheral base addresses */ -#define ANADIG_SPARE_REGS_LPSR_BASE_ADDRS { ANADIG_SPARE_REGS_LPSR_BASE } -/** Array initializer of ANADIG_SPARE_REGS_LPSR peripheral base pointers */ -#define ANADIG_SPARE_REGS_LPSR_BASE_PTRS { ANADIG_SPARE_REGS_LPSR } - -/*! - * @} - */ /* end of group ANADIG_SPARE_REGS_LPSR_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- ANADIG_SPARE_REGS_SNVS Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ANADIG_SPARE_REGS_SNVS_Peripheral_Access_Layer ANADIG_SPARE_REGS_SNVS Peripheral Access Layer - * @{ - */ - -/** ANADIG_SPARE_REGS_SNVS - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[2400]; - __IO uint32_t SPARE_REGS_SNVS; /**< SPARE_REGS_SNVS_REGISTER, offset: 0x960 */ -} ANADIG_SPARE_REGS_SNVS_Type; - -/* ---------------------------------------------------------------------------- - -- ANADIG_SPARE_REGS_SNVS Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ANADIG_SPARE_REGS_SNVS_Register_Masks ANADIG_SPARE_REGS_SNVS Register Masks - * @{ - */ - -/*! @name SPARE_REGS_SNVS - SPARE_REGS_SNVS_REGISTER */ -/*! @{ */ -#define ANADIG_SPARE_REGS_SNVS_SPARE_REGS_SNVS_SPARE_REG_SNVS_MASK (0xFFFFFFFFU) -#define ANADIG_SPARE_REGS_SNVS_SPARE_REGS_SNVS_SPARE_REG_SNVS_SHIFT (0U) -/*! SPARE_REG_SNVS - spare_reg_snvs - */ -#define ANADIG_SPARE_REGS_SNVS_SPARE_REGS_SNVS_SPARE_REG_SNVS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_SPARE_REGS_SNVS_SPARE_REGS_SNVS_SPARE_REG_SNVS_SHIFT)) & ANADIG_SPARE_REGS_SNVS_SPARE_REGS_SNVS_SPARE_REG_SNVS_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ANADIG_SPARE_REGS_SNVS_Register_Masks */ - - -/* ANADIG_SPARE_REGS_SNVS - Peripheral instance base addresses */ -/** Peripheral ANADIG_SPARE_REGS_SNVS base address */ -#define ANADIG_SPARE_REGS_SNVS_BASE (0x40C84000u) -/** Peripheral ANADIG_SPARE_REGS_SNVS base pointer */ -#define ANADIG_SPARE_REGS_SNVS ((ANADIG_SPARE_REGS_SNVS_Type *)ANADIG_SPARE_REGS_SNVS_BASE) -/** Array initializer of ANADIG_SPARE_REGS_SNVS peripheral base addresses */ -#define ANADIG_SPARE_REGS_SNVS_BASE_ADDRS { ANADIG_SPARE_REGS_SNVS_BASE } -/** Array initializer of ANADIG_SPARE_REGS_SNVS peripheral base pointers */ -#define ANADIG_SPARE_REGS_SNVS_BASE_PTRS { ANADIG_SPARE_REGS_SNVS } - -/*! - * @} - */ /* end of group ANADIG_SPARE_REGS_SNVS_Peripheral_Access_Layer */ - - /* ---------------------------------------------------------------------------- -- ANADIG_TEMPSENSOR Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -8831,13 +9431,9 @@ typedef struct { /** ANADIG_TEMPSENSOR - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[1024]; - __IO uint32_t TEMPSENSOR; /**< TEMPSENSOR_REGISTER, offset: 0x400 */ - uint8_t RESERVED_1[12]; - __IO uint32_t ANAMUX; /**< ANAMUX_REGISTER, offset: 0x410 */ - uint8_t RESERVED_2[28]; + __IO uint32_t TEMPSENSOR; /**< Tempsensor Register, offset: 0x400 */ + uint8_t RESERVED_1[44]; __I uint32_t TEMPSNS_OTP_TRIM_VALUE; /**< TEMPSNS_OTP_TRIM_VALUE_REGISTER, offset: 0x430 */ - uint8_t RESERVED_3[12]; - __I uint32_t PWR_OTP_TRIM_VALUE; /**< PWR_OTP_TRIM_VALUE_REGISTER, offset: 0x440 */ } ANADIG_TEMPSENSOR_Type; /* ---------------------------------------------------------------------------- @@ -8849,75 +9445,30 @@ typedef struct { * @{ */ -/*! @name TEMPSENSOR - TEMPSENSOR_REGISTER */ +/*! @name TEMPSENSOR - Tempsensor Register */ /*! @{ */ + #define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_MASK (0x8000U) #define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_SHIFT (15U) -/*! TEMPSNS_AI_TOGGLE - tempsns_ai_toggle +/*! TEMPSNS_AI_TOGGLE - AI toggle */ #define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_SHIFT)) & ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_MASK) + #define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY_MASK (0x10000U) #define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY_SHIFT (16U) -/*! TEMPSNS_AI_BUSY - tempsns_ai_busy +/*! TEMPSNS_AI_BUSY - AI Busy monitor */ #define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY_SHIFT)) & ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY_MASK) /*! @} */ -/*! @name ANAMUX - ANAMUX_REGISTER */ -/*! @{ */ -#define ANADIG_TEMPSENSOR_ANAMUX_ANAMUX_EN_MASK (0x1U) -#define ANADIG_TEMPSENSOR_ANAMUX_ANAMUX_EN_SHIFT (0U) -/*! ANAMUX_EN - anamux_en - */ -#define ANADIG_TEMPSENSOR_ANAMUX_ANAMUX_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_TEMPSENSOR_ANAMUX_ANAMUX_EN_SHIFT)) & ANADIG_TEMPSENSOR_ANAMUX_ANAMUX_EN_MASK) -#define ANADIG_TEMPSENSOR_ANAMUX_ANAMUX_SEL_MASK (0x3F0000U) -#define ANADIG_TEMPSENSOR_ANAMUX_ANAMUX_SEL_SHIFT (16U) -/*! ANAMUX_SEL - ANAMUX_SEL - */ -#define ANADIG_TEMPSENSOR_ANAMUX_ANAMUX_SEL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_TEMPSENSOR_ANAMUX_ANAMUX_SEL_SHIFT)) & ANADIG_TEMPSENSOR_ANAMUX_ANAMUX_SEL_MASK) -#define ANADIG_TEMPSENSOR_ANAMUX_ANAMUX_TEST_EN_MASK (0x400000U) -#define ANADIG_TEMPSENSOR_ANAMUX_ANAMUX_TEST_EN_SHIFT (22U) -/*! ANAMUX_TEST_EN - anamux_test_en - */ -#define ANADIG_TEMPSENSOR_ANAMUX_ANAMUX_TEST_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_TEMPSENSOR_ANAMUX_ANAMUX_TEST_EN_SHIFT)) & ANADIG_TEMPSENSOR_ANAMUX_ANAMUX_TEST_EN_MASK) -/*! @} */ - /*! @name TEMPSNS_OTP_TRIM_VALUE - TEMPSNS_OTP_TRIM_VALUE_REGISTER */ /*! @{ */ -#define ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_IBIAS_TRIM_MASK (0xFU) -#define ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_IBIAS_TRIM_SHIFT (0U) -/*! TEMPSNS_IBIAS_TRIM - tempsns_ibias_trim - */ -#define ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_IBIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_IBIAS_TRIM_SHIFT)) & ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_IBIAS_TRIM_MASK) -#define ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_SLOPE_CAL_MASK (0x3F0U) -#define ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_SLOPE_CAL_SHIFT (4U) -/*! TEMPSNS_SLOPE_CAL - tempsns_slope_cal - */ -#define ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_SLOPE_CAL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_SLOPE_CAL_SHIFT)) & ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_SLOPE_CAL_MASK) + #define ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_MASK (0x3FFC00U) #define ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_SHIFT (10U) -/*! TEMPSNS_TEMP_VAL - tempsns_temp_val +/*! TEMPSNS_TEMP_VAL - Temperature Value at 25C */ #define ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_SHIFT)) & ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_MASK) -#define ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TRIM_EN_MASK (0x400000U) -#define ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TRIM_EN_SHIFT (22U) -/*! TEMPSNS_TRIM_EN - tempsns_trim_en - */ -#define ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TRIM_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TRIM_EN_SHIFT)) & ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TRIM_EN_MASK) -/*! @} */ - -/*! @name PWR_OTP_TRIM_VALUE - PWR_OTP_TRIM_VALUE_REGISTER */ -/*! @{ */ -#define ANADIG_TEMPSENSOR_PWR_OTP_TRIM_VALUE_PWR_V2V_1VTRIM_MASK (0x7U) -#define ANADIG_TEMPSENSOR_PWR_OTP_TRIM_VALUE_PWR_V2V_1VTRIM_SHIFT (0U) -/*! PWR_V2V_1VTRIM - pwr_v2v_1vtrim - */ -#define ANADIG_TEMPSENSOR_PWR_OTP_TRIM_VALUE_PWR_V2V_1VTRIM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_TEMPSENSOR_PWR_OTP_TRIM_VALUE_PWR_V2V_1VTRIM_SHIFT)) & ANADIG_TEMPSENSOR_PWR_OTP_TRIM_VALUE_PWR_V2V_1VTRIM_MASK) -#define ANADIG_TEMPSENSOR_PWR_OTP_TRIM_VALUE_PWR_TRIM_EN_MASK (0x8U) -#define ANADIG_TEMPSENSOR_PWR_OTP_TRIM_VALUE_PWR_TRIM_EN_SHIFT (3U) -/*! PWR_TRIM_EN - pwr_trim_en - */ -#define ANADIG_TEMPSENSOR_PWR_OTP_TRIM_VALUE_PWR_TRIM_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_TEMPSENSOR_PWR_OTP_TRIM_VALUE_PWR_TRIM_EN_SHIFT)) & ANADIG_TEMPSENSOR_PWR_OTP_TRIM_VALUE_PWR_TRIM_EN_MASK) /*! @} */ @@ -8969,6 +9520,7 @@ typedef struct { /*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn */ /*! @{ */ + #define AOI_BFCRT01_PT1_DC_MASK (0x3U) #define AOI_BFCRT01_PT1_DC_SHIFT (0U) /*! PT1_DC - Product term 1, D input configuration @@ -8978,6 +9530,7 @@ typedef struct { * 0b11..Force the D input in this product term to a logical one */ #define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK) + #define AOI_BFCRT01_PT1_CC_MASK (0xCU) #define AOI_BFCRT01_PT1_CC_SHIFT (2U) /*! PT1_CC - Product term 1, C input configuration @@ -8987,6 +9540,7 @@ typedef struct { * 0b11..Force the C input in this product term to a logical one */ #define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK) + #define AOI_BFCRT01_PT1_BC_MASK (0x30U) #define AOI_BFCRT01_PT1_BC_SHIFT (4U) /*! PT1_BC - Product term 1, B input configuration @@ -8996,6 +9550,7 @@ typedef struct { * 0b11..Force the B input in this product term to a logical one */ #define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK) + #define AOI_BFCRT01_PT1_AC_MASK (0xC0U) #define AOI_BFCRT01_PT1_AC_SHIFT (6U) /*! PT1_AC - Product term 1, A input configuration @@ -9005,6 +9560,7 @@ typedef struct { * 0b11..Force the A input in this product term to a logical one */ #define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK) + #define AOI_BFCRT01_PT0_DC_MASK (0x300U) #define AOI_BFCRT01_PT0_DC_SHIFT (8U) /*! PT0_DC - Product term 0, D input configuration @@ -9014,6 +9570,7 @@ typedef struct { * 0b11..Force the D input in this product term to a logical one */ #define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK) + #define AOI_BFCRT01_PT0_CC_MASK (0xC00U) #define AOI_BFCRT01_PT0_CC_SHIFT (10U) /*! PT0_CC - Product term 0, C input configuration @@ -9023,6 +9580,7 @@ typedef struct { * 0b11..Force the C input in this product term to a logical one */ #define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK) + #define AOI_BFCRT01_PT0_BC_MASK (0x3000U) #define AOI_BFCRT01_PT0_BC_SHIFT (12U) /*! PT0_BC - Product term 0, B input configuration @@ -9032,6 +9590,7 @@ typedef struct { * 0b11..Force the B input in this product term to a logical one */ #define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK) + #define AOI_BFCRT01_PT0_AC_MASK (0xC000U) #define AOI_BFCRT01_PT0_AC_SHIFT (14U) /*! PT0_AC - Product term 0, A input configuration @@ -9048,6 +9607,7 @@ typedef struct { /*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn */ /*! @{ */ + #define AOI_BFCRT23_PT3_DC_MASK (0x3U) #define AOI_BFCRT23_PT3_DC_SHIFT (0U) /*! PT3_DC - Product term 3, D input configuration @@ -9057,6 +9617,7 @@ typedef struct { * 0b11..Force the D input in this product term to a logical one */ #define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK) + #define AOI_BFCRT23_PT3_CC_MASK (0xCU) #define AOI_BFCRT23_PT3_CC_SHIFT (2U) /*! PT3_CC - Product term 3, C input configuration @@ -9066,6 +9627,7 @@ typedef struct { * 0b11..Force the C input in this product term to a logical one */ #define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK) + #define AOI_BFCRT23_PT3_BC_MASK (0x30U) #define AOI_BFCRT23_PT3_BC_SHIFT (4U) /*! PT3_BC - Product term 3, B input configuration @@ -9075,6 +9637,7 @@ typedef struct { * 0b11..Force the B input in this product term to a logical one */ #define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK) + #define AOI_BFCRT23_PT3_AC_MASK (0xC0U) #define AOI_BFCRT23_PT3_AC_SHIFT (6U) /*! PT3_AC - Product term 3, A input configuration @@ -9084,6 +9647,7 @@ typedef struct { * 0b11..Force the A input in this product term to a logical one */ #define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK) + #define AOI_BFCRT23_PT2_DC_MASK (0x300U) #define AOI_BFCRT23_PT2_DC_SHIFT (8U) /*! PT2_DC - Product term 2, D input configuration @@ -9093,6 +9657,7 @@ typedef struct { * 0b11..Force the D input in this product term to a logical one */ #define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK) + #define AOI_BFCRT23_PT2_CC_MASK (0xC00U) #define AOI_BFCRT23_PT2_CC_SHIFT (10U) /*! PT2_CC - Product term 2, C input configuration @@ -9102,6 +9667,7 @@ typedef struct { * 0b11..Force the C input in this product term to a logical one */ #define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK) + #define AOI_BFCRT23_PT2_BC_MASK (0x3000U) #define AOI_BFCRT23_PT2_BC_SHIFT (12U) /*! PT2_BC - Product term 2, B input configuration @@ -9111,6 +9677,7 @@ typedef struct { * 0b11..Force the B input in this product term to a logical one */ #define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK) + #define AOI_BFCRT23_PT2_AC_MASK (0xC000U) #define AOI_BFCRT23_PT2_AC_SHIFT (14U) /*! PT2_AC - Product term 2, A input configuration @@ -9171,8 +9738,8 @@ typedef struct { __IO uint32_t ASRCDR2; /**< ASRC Clock Divider Register 2, offset: 0x1C */ __I uint32_t ASRSTR; /**< ASRC Status Register, offset: 0x20 */ uint8_t RESERVED_1[28]; - __IO uint32_t ASRPMn[5]; /**< ASRC Parameter Register n, array offset: 0x40, array step: 0x4 */ - __IO uint32_t ASRTFR1; /**< ASRC ASRC Task Queue FIFO Register 1, offset: 0x54 */ + __IO uint32_t ASRPM[5]; /**< ASRC Parameter Register n, array offset: 0x40, array step: 0x4 */ + __IO uint32_t ASRTFR1; /**< ASRC Task Queue FIFO Register 1, offset: 0x54 */ uint8_t RESERVED_2[4]; __IO uint32_t ASRCCR; /**< ASRC Channel Counter Register, offset: 0x5C */ __O uint32_t ASRDIA; /**< ASRC Data Input Register for Pair x, offset: 0x60 */ @@ -9211,104 +9778,182 @@ typedef struct { /*! @name ASRCTR - ASRC Control Register */ /*! @{ */ + #define ASRC_ASRCTR_ASRCEN_MASK (0x1U) #define ASRC_ASRCTR_ASRCEN_SHIFT (0U) +/*! ASRCEN - ASRCEN + * 0b0..operation of ASRC disabled + * 0b1..operation ASRC is enabled + */ #define ASRC_ASRCTR_ASRCEN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASRCEN_SHIFT)) & ASRC_ASRCTR_ASRCEN_MASK) + #define ASRC_ASRCTR_ASREA_MASK (0x2U) #define ASRC_ASRCTR_ASREA_SHIFT (1U) +/*! ASREA - ASREA + * 0b0..operation of conversion A is disabled + * 0b1..operation of conversion A is enabled + */ #define ASRC_ASRCTR_ASREA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREA_SHIFT)) & ASRC_ASRCTR_ASREA_MASK) + #define ASRC_ASRCTR_ASREB_MASK (0x4U) #define ASRC_ASRCTR_ASREB_SHIFT (2U) +/*! ASREB - ASREB + * 0b0..operation of conversion B is disabled + * 0b1..operation of conversion B is enabled + */ #define ASRC_ASRCTR_ASREB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREB_SHIFT)) & ASRC_ASRCTR_ASREB_MASK) + #define ASRC_ASRCTR_ASREC_MASK (0x8U) #define ASRC_ASRCTR_ASREC_SHIFT (3U) +/*! ASREC - ASREC + * 0b0..operation of conversion C is disabled + * 0b1..operation of conversion C is enabled + */ #define ASRC_ASRCTR_ASREC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREC_SHIFT)) & ASRC_ASRCTR_ASREC_MASK) + #define ASRC_ASRCTR_SRST_MASK (0x10U) #define ASRC_ASRCTR_SRST_SHIFT (4U) +/*! SRST - SRST + * 0b0..ASRC Software reset cleared + * 0b1..ASRC Software reset generated. NOTE: This is a self-clear bit + */ #define ASRC_ASRCTR_SRST(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_SRST_SHIFT)) & ASRC_ASRCTR_SRST_MASK) + #define ASRC_ASRCTR_IDRA_MASK (0x2000U) #define ASRC_ASRCTR_IDRA_SHIFT (13U) +/*! IDRA - IDRA + * 0b0..ASRC internal measured ratio is used + * 0b1..Ideal ratio from the interface register ASRIDRHA, ASRIDRLA is used + */ #define ASRC_ASRCTR_IDRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRA_SHIFT)) & ASRC_ASRCTR_IDRA_MASK) + #define ASRC_ASRCTR_USRA_MASK (0x4000U) #define ASRC_ASRCTR_USRA_SHIFT (14U) +/*! USRA - USRA + * 0b1..Use ratio as the input to ASRC for pair A + * 0b0..Do not use ratio as the input to ASRC for pair A + */ #define ASRC_ASRCTR_USRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRA_SHIFT)) & ASRC_ASRCTR_USRA_MASK) + #define ASRC_ASRCTR_IDRB_MASK (0x8000U) #define ASRC_ASRCTR_IDRB_SHIFT (15U) +/*! IDRB - IDRB + * 0b0..ASRC internal measured ratio is used + * 0b1..Ideal ratio from the interface register ASRIDRHB, ASRIDRLB is used + */ #define ASRC_ASRCTR_IDRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRB_SHIFT)) & ASRC_ASRCTR_IDRB_MASK) + #define ASRC_ASRCTR_USRB_MASK (0x10000U) #define ASRC_ASRCTR_USRB_SHIFT (16U) +/*! USRB - USRB + * 0b1..Use ratio as the input to ASRC for pair B + * 0b0..Do not use ratio as the input to ASRC for pair B + */ #define ASRC_ASRCTR_USRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRB_SHIFT)) & ASRC_ASRCTR_USRB_MASK) + #define ASRC_ASRCTR_IDRC_MASK (0x20000U) #define ASRC_ASRCTR_IDRC_SHIFT (17U) +/*! IDRC - IDRC + * 0b0..ASRC internal measured ratio is used + * 0b1..Ideal ratio from the interface register ASRIDRHC, ASRIDRLC is used + */ #define ASRC_ASRCTR_IDRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRC_SHIFT)) & ASRC_ASRCTR_IDRC_MASK) + #define ASRC_ASRCTR_USRC_MASK (0x40000U) #define ASRC_ASRCTR_USRC_SHIFT (18U) +/*! USRC - USRC + * 0b1..Use ratio as the input to ASRC for pair C + * 0b0..Do not use ratio as the input to ASRC for pair C + */ #define ASRC_ASRCTR_USRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRC_SHIFT)) & ASRC_ASRCTR_USRC_MASK) + #define ASRC_ASRCTR_ATSA_MASK (0x100000U) #define ASRC_ASRCTR_ATSA_SHIFT (20U) +/*! ATSA - ATSA + * 0b1..Pair A automatically updates its pre-processing and post-processing options + * 0b0..Pair A does not automatically update its pre-processing and post-processing options + */ #define ASRC_ASRCTR_ATSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSA_SHIFT)) & ASRC_ASRCTR_ATSA_MASK) + #define ASRC_ASRCTR_ATSB_MASK (0x200000U) #define ASRC_ASRCTR_ATSB_SHIFT (21U) +/*! ATSB - ATSB + * 0b1..Pair B automatically updates its pre-processing and post-processing options + * 0b0..Pair B does not automatically update its pre-processing and post-processing options + */ #define ASRC_ASRCTR_ATSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSB_SHIFT)) & ASRC_ASRCTR_ATSB_MASK) + #define ASRC_ASRCTR_ATSC_MASK (0x400000U) #define ASRC_ASRCTR_ATSC_SHIFT (22U) +/*! ATSC - ATSC + * 0b1..Pair C automatically updates its pre-processing and post-processing options + * 0b0..Pair C does not automatically update its pre-processing and post-processing options + */ #define ASRC_ASRCTR_ATSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSC_SHIFT)) & ASRC_ASRCTR_ATSC_MASK) /*! @} */ /*! @name ASRIER - ASRC Interrupt Enable Register */ /*! @{ */ + #define ASRC_ASRIER_ADIEA_MASK (0x1U) #define ASRC_ASRIER_ADIEA_SHIFT (0U) -/*! ADIEA +/*! ADIEA - ADIEA * 0b1..interrupt enabled * 0b0..interrupt disabled */ #define ASRC_ASRIER_ADIEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEA_SHIFT)) & ASRC_ASRIER_ADIEA_MASK) + #define ASRC_ASRIER_ADIEB_MASK (0x2U) #define ASRC_ASRIER_ADIEB_SHIFT (1U) -/*! ADIEB +/*! ADIEB - ADIEB * 0b1..interrupt enabled * 0b0..interrupt disabled */ #define ASRC_ASRIER_ADIEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEB_SHIFT)) & ASRC_ASRIER_ADIEB_MASK) + #define ASRC_ASRIER_ADIEC_MASK (0x4U) #define ASRC_ASRIER_ADIEC_SHIFT (2U) -/*! ADIEC +/*! ADIEC - ADIEC * 0b1..interrupt enabled * 0b0..interrupt disabled */ #define ASRC_ASRIER_ADIEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEC_SHIFT)) & ASRC_ASRIER_ADIEC_MASK) + #define ASRC_ASRIER_ADOEA_MASK (0x8U) #define ASRC_ASRIER_ADOEA_SHIFT (3U) -/*! ADOEA +/*! ADOEA - ADOEA * 0b1..interrupt enabled * 0b0..interrupt disabled */ #define ASRC_ASRIER_ADOEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEA_SHIFT)) & ASRC_ASRIER_ADOEA_MASK) + #define ASRC_ASRIER_ADOEB_MASK (0x10U) #define ASRC_ASRIER_ADOEB_SHIFT (4U) -/*! ADOEB +/*! ADOEB - ADOEB * 0b1..interrupt enabled * 0b0..interrupt disabled */ #define ASRC_ASRIER_ADOEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEB_SHIFT)) & ASRC_ASRIER_ADOEB_MASK) + #define ASRC_ASRIER_ADOEC_MASK (0x20U) #define ASRC_ASRIER_ADOEC_SHIFT (5U) -/*! ADOEC +/*! ADOEC - ADOEC * 0b1..interrupt enabled * 0b0..interrupt disabled */ #define ASRC_ASRIER_ADOEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEC_SHIFT)) & ASRC_ASRIER_ADOEC_MASK) + #define ASRC_ASRIER_AOLIE_MASK (0x40U) #define ASRC_ASRIER_AOLIE_SHIFT (6U) -/*! AOLIE +/*! AOLIE - AOLIE * 0b1..interrupt enabled * 0b0..interrupt disabled */ #define ASRC_ASRIER_AOLIE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AOLIE_SHIFT)) & ASRC_ASRIER_AOLIE_MASK) + #define ASRC_ASRIER_AFPWE_MASK (0x80U) #define ASRC_ASRIER_AFPWE_SHIFT (7U) -/*! AFPWE +/*! AFPWE - AFPWE * 0b1..interrupt enabled * 0b0..interrupt disabled */ @@ -9317,9 +9962,10 @@ typedef struct { /*! @name ASRCNCR - ASRC Channel Number Configuration Register */ /*! @{ */ + #define ASRC_ASRCNCR_ANCA_MASK (0xFU) #define ASRC_ASRCNCR_ANCA_SHIFT (0U) -/*! ANCA +/*! ANCA - ANCA * 0b0000..0 channels in A (Pair A is disabled) * 0b0001..1 channel in A * 0b0010..2 channels in A @@ -9331,11 +9977,13 @@ typedef struct { * 0b1000..8 channels in A * 0b1001..9 channels in A * 0b1010..10 channels in A + * 0b1011-0b1111..Should not be used. */ #define ASRC_ASRCNCR_ANCA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCA_SHIFT)) & ASRC_ASRCNCR_ANCA_MASK) + #define ASRC_ASRCNCR_ANCB_MASK (0xF0U) #define ASRC_ASRCNCR_ANCB_SHIFT (4U) -/*! ANCB +/*! ANCB - ANCB * 0b0000..0 channels in B (Pair B is disabled) * 0b0001..1 channel in B * 0b0010..2 channels in B @@ -9347,11 +9995,13 @@ typedef struct { * 0b1000..8 channels in B * 0b1001..9 channels in B * 0b1010..10 channels in B + * 0b1011-0b1111..Should not be used. */ #define ASRC_ASRCNCR_ANCB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCB_SHIFT)) & ASRC_ASRCNCR_ANCB_MASK) + #define ASRC_ASRCNCR_ANCC_MASK (0xF00U) #define ASRC_ASRCNCR_ANCC_SHIFT (8U) -/*! ANCC +/*! ANCC - ANCC * 0b0000..0 channels in C (Pair C is disabled) * 0b0001..1 channel in C * 0b0010..2 channels in C @@ -9363,130 +10013,129 @@ typedef struct { * 0b1000..8 channels in C * 0b1001..9 channels in C * 0b1010..10 channels in C + * 0b1011-0b1111..Should not be used. */ #define ASRC_ASRCNCR_ANCC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCC_SHIFT)) & ASRC_ASRCNCR_ANCC_MASK) /*! @} */ /*! @name ASRCFG - ASRC Filter Configuration Status Register */ /*! @{ */ + #define ASRC_ASRCFG_PREMODA_MASK (0xC0U) #define ASRC_ASRCFG_PREMODA_SHIFT (6U) -/*! PREMODA - * 0b00..Select Upsampling-by-2 as defined in Signal processing flowBy flowing through different processing - * branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate - * conversion requirements. - * 0b01..Select Direct-Connection as defined in Signal processing flowBy flowing through different processing - * branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate - * conversion requirements. - * 0b10..Select Downsampling-by-2 as defined in Signal processing flowBy flowing through different processing - * branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate - * conversion requirements. - * 0b11..Select passthrough mode. In this case, POSTMODA[1-0] have no use. +/*! PREMODA - PREMODA + * 0b00..Select Upsampling-by-2 + * 0b01..Select Direct-Connection + * 0b10..Select Downsampling-by-2 + * 0b11..Select passthrough mode. In this case, POSTMODA[1:0] have no use. */ #define ASRC_ASRCFG_PREMODA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODA_SHIFT)) & ASRC_ASRCFG_PREMODA_MASK) + #define ASRC_ASRCFG_POSTMODA_MASK (0x300U) #define ASRC_ASRCFG_POSTMODA_SHIFT (8U) -/*! POSTMODA - * 0b00..Select Upsampling-by-2 as defined in Signal processing flowBy flowing through different processing - * branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate - * conversion requirements. - * 0b01..Select Direct-Connection as defined in Signal processing flowBy flowing through different processing - * branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate - * conversion requirements. - * 0b10..Select Downsampling-by-2 as defined in Signal processing flowBy flowing through different processing - * branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate - * conversion requirements. +/*! POSTMODA - POSTMODA + * 0b00..Select Upsampling-by-2 + * 0b01..Select Direct-Connection + * 0b10..Select Downsampling-by-2 + * 0b11..Reserved. */ #define ASRC_ASRCFG_POSTMODA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODA_SHIFT)) & ASRC_ASRCFG_POSTMODA_MASK) + #define ASRC_ASRCFG_PREMODB_MASK (0xC00U) #define ASRC_ASRCFG_PREMODB_SHIFT (10U) -/*! PREMODB - * 0b00..Select Upsampling-by-2 as defined in Signal processing flowBy flowing through different processing - * branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate - * conversion requirements. - * 0b01..Select Direct-Connection as defined in Signal processing flowBy flowing through different processing - * branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate - * conversion requirements. - * 0b10..Select Downsampling-by-2 as defined in Signal processing flowBy flowing through different processing - * branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate - * conversion requirements. - * 0b11..Select passthrough mode. In this case, POSTMODB[1-0] have no use. +/*! PREMODB - PREMODB + * 0b00..Select Upsampling-by-2 + * 0b01..Select Direct-Connection + * 0b10..Select Downsampling-by-2 + * 0b11..Select passthrough mode. In this case, POSTMODB[1:0] have no use. */ #define ASRC_ASRCFG_PREMODB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODB_SHIFT)) & ASRC_ASRCFG_PREMODB_MASK) + #define ASRC_ASRCFG_POSTMODB_MASK (0x3000U) #define ASRC_ASRCFG_POSTMODB_SHIFT (12U) -/*! POSTMODB - * 0b00..Select Upsampling-by-2 as defined in Signal processing flowBy flowing through different processing - * branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate - * conversion requirements. - * 0b01..Select Direct-Connection as defined in Signal processing flowBy flowing through different processing - * branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate - * conversion requirements. - * 0b10..Select Downsampling-by-2 as defined in Signal processing flowBy flowing through different processing - * branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate - * conversion requirements. +/*! POSTMODB - POSTMODB + * 0b00..Select Upsampling-by-2 + * 0b01..Select Direct-Connection + * 0b10..Select Downsampling-by-2 + * 0b11..Reserved. */ #define ASRC_ASRCFG_POSTMODB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODB_SHIFT)) & ASRC_ASRCFG_POSTMODB_MASK) + #define ASRC_ASRCFG_PREMODC_MASK (0xC000U) #define ASRC_ASRCFG_PREMODC_SHIFT (14U) -/*! PREMODC - * 0b00..Select Upsampling-by-2 as defined in Signal processing flowBy flowing through different processing - * branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate - * conversion requirements. - * 0b01..Select Direct-Connection as defined in Signal processing flowBy flowing through different processing - * branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate - * conversion requirements. - * 0b10..Select Downsampling-by-2 as defined in Signal processing flowBy flowing through different processing - * branches and different setups of the pre-filter, this ASRC scheme can be used to handle different rate - * conversion requirements. - * 0b11..Select passthrough mode. In this case, POSTMODC[1-0] have no use. +/*! PREMODC - PREMODC + * 0b00..Select Upsampling-by-2 + * 0b01..Select Direct-Connection + * 0b10..Select Downsampling-by-2 + * 0b11..Select passthrough mode. In this case, POSTMODC[1:0] have no use. */ #define ASRC_ASRCFG_PREMODC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODC_SHIFT)) & ASRC_ASRCFG_PREMODC_MASK) + #define ASRC_ASRCFG_POSTMODC_MASK (0x30000U) #define ASRC_ASRCFG_POSTMODC_SHIFT (16U) -/*! POSTMODC +/*! POSTMODC - POSTMODC * 0b00..Select Upsampling-by-2 as defined in Signal Processing Flow. * 0b01..Select Direct-Connection as defined in Signal Processing Flow. * 0b10..Select Downsampling-by-2 as defined in Signal Processing Flow. + * 0b11..Reserved. */ #define ASRC_ASRCFG_POSTMODC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODC_SHIFT)) & ASRC_ASRCFG_POSTMODC_MASK) + #define ASRC_ASRCFG_NDPRA_MASK (0x40000U) #define ASRC_ASRCFG_NDPRA_SHIFT (18U) -/*! NDPRA +/*! NDPRA - NDPRA * 0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM. * 0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM. */ #define ASRC_ASRCFG_NDPRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRA_SHIFT)) & ASRC_ASRCFG_NDPRA_MASK) + #define ASRC_ASRCFG_NDPRB_MASK (0x80000U) #define ASRC_ASRCFG_NDPRB_SHIFT (19U) -/*! NDPRB +/*! NDPRB - NDPRB * 0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM. * 0b1..Don't use default parameters for RAM-stored parameter. Use the parameters already stored in RAM. */ #define ASRC_ASRCFG_NDPRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRB_SHIFT)) & ASRC_ASRCFG_NDPRB_MASK) + #define ASRC_ASRCFG_NDPRC_MASK (0x100000U) #define ASRC_ASRCFG_NDPRC_SHIFT (20U) -/*! NDPRC +/*! NDPRC - NDPRC * 0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM. * 0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM. */ #define ASRC_ASRCFG_NDPRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRC_SHIFT)) & ASRC_ASRCFG_NDPRC_MASK) + #define ASRC_ASRCFG_INIRQA_MASK (0x200000U) #define ASRC_ASRCFG_INIRQA_SHIFT (21U) +/*! INIRQA - INIRQA + * 0b0..Initialization for Conversion Pair A not served + * 0b1..Initialization for Conversion Pair A served + */ #define ASRC_ASRCFG_INIRQA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQA_SHIFT)) & ASRC_ASRCFG_INIRQA_MASK) + #define ASRC_ASRCFG_INIRQB_MASK (0x400000U) #define ASRC_ASRCFG_INIRQB_SHIFT (22U) +/*! INIRQB - INIRQB + * 0b0..Initialization for Conversion Pair B not served + * 0b1..Initialization for Conversion Pair B served + */ #define ASRC_ASRCFG_INIRQB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQB_SHIFT)) & ASRC_ASRCFG_INIRQB_MASK) + #define ASRC_ASRCFG_INIRQC_MASK (0x800000U) #define ASRC_ASRCFG_INIRQC_SHIFT (23U) +/*! INIRQC - INIRQC + * 0b0..Initialization for Conversion Pair C not served + * 0b1..Initialization for Conversion Pair C served + */ #define ASRC_ASRCFG_INIRQC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQC_SHIFT)) & ASRC_ASRCFG_INIRQC_MASK) /*! @} */ /*! @name ASRCSR - ASRC Clock Source Register */ /*! @{ */ + #define ASRC_ASRCSR_AICSA_MASK (0xFU) #define ASRC_ASRCSR_AICSA_SHIFT (0U) -/*! AICSA +/*! AICSA - AICSA * 0b0000..bit clock 0 * 0b0001..bit clock 1 * 0b0010..bit clock 2 @@ -9505,9 +10154,10 @@ typedef struct { * 0b1111..clock disabled, connected to zero */ #define ASRC_ASRCSR_AICSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSA_SHIFT)) & ASRC_ASRCSR_AICSA_MASK) + #define ASRC_ASRCSR_AICSB_MASK (0xF0U) #define ASRC_ASRCSR_AICSB_SHIFT (4U) -/*! AICSB +/*! AICSB - AICSB * 0b0000..bit clock 0 * 0b0001..bit clock 1 * 0b0010..bit clock 2 @@ -9526,9 +10176,10 @@ typedef struct { * 0b1111..clock disabled, connected to zero */ #define ASRC_ASRCSR_AICSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSB_SHIFT)) & ASRC_ASRCSR_AICSB_MASK) + #define ASRC_ASRCSR_AICSC_MASK (0xF00U) #define ASRC_ASRCSR_AICSC_SHIFT (8U) -/*! AICSC +/*! AICSC - AICSC * 0b0000..bit clock 0 * 0b0001..bit clock 1 * 0b0010..bit clock 2 @@ -9547,9 +10198,10 @@ typedef struct { * 0b1111..clock disabled, connected to zero */ #define ASRC_ASRCSR_AICSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSC_SHIFT)) & ASRC_ASRCSR_AICSC_MASK) + #define ASRC_ASRCSR_AOCSA_MASK (0xF000U) #define ASRC_ASRCSR_AOCSA_SHIFT (12U) -/*! AOCSA +/*! AOCSA - AOCSA * 0b0000..bit clock 0 * 0b0001..bit clock 1 * 0b0010..bit clock 2 @@ -9568,9 +10220,10 @@ typedef struct { * 0b1111..clock disabled, connected to zero */ #define ASRC_ASRCSR_AOCSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSA_SHIFT)) & ASRC_ASRCSR_AOCSA_MASK) + #define ASRC_ASRCSR_AOCSB_MASK (0xF0000U) #define ASRC_ASRCSR_AOCSB_SHIFT (16U) -/*! AOCSB +/*! AOCSB - AOCSB * 0b0000..bit clock 0 * 0b0001..bit clock 1 * 0b0010..bit clock 2 @@ -9589,9 +10242,10 @@ typedef struct { * 0b1111..clock disabled, connected to zero */ #define ASRC_ASRCSR_AOCSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSB_SHIFT)) & ASRC_ASRCSR_AOCSB_MASK) + #define ASRC_ASRCSR_AOCSC_MASK (0xF00000U) #define ASRC_ASRCSR_AOCSC_SHIFT (20U) -/*! AOCSC +/*! AOCSC - AOCSC * 0b0000..bit clock 0 * 0b0001..bit clock 1 * 0b0010..bit clock 2 @@ -9614,296 +10268,531 @@ typedef struct { /*! @name ASRCDR1 - ASRC Clock Divider Register 1 */ /*! @{ */ + #define ASRC_ASRCDR1_AICPA_MASK (0x7U) #define ASRC_ASRCDR1_AICPA_SHIFT (0U) +/*! AICPA - AICPA + */ #define ASRC_ASRCDR1_AICPA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPA_SHIFT)) & ASRC_ASRCDR1_AICPA_MASK) + #define ASRC_ASRCDR1_AICDA_MASK (0x38U) #define ASRC_ASRCDR1_AICDA_SHIFT (3U) +/*! AICDA - AICDA + */ #define ASRC_ASRCDR1_AICDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDA_SHIFT)) & ASRC_ASRCDR1_AICDA_MASK) + #define ASRC_ASRCDR1_AICPB_MASK (0x1C0U) #define ASRC_ASRCDR1_AICPB_SHIFT (6U) +/*! AICPB - AICPB + */ #define ASRC_ASRCDR1_AICPB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPB_SHIFT)) & ASRC_ASRCDR1_AICPB_MASK) + #define ASRC_ASRCDR1_AICDB_MASK (0xE00U) #define ASRC_ASRCDR1_AICDB_SHIFT (9U) +/*! AICDB - AICDB + */ #define ASRC_ASRCDR1_AICDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDB_SHIFT)) & ASRC_ASRCDR1_AICDB_MASK) + #define ASRC_ASRCDR1_AOCPA_MASK (0x7000U) #define ASRC_ASRCDR1_AOCPA_SHIFT (12U) +/*! AOCPA - AOCPA + */ #define ASRC_ASRCDR1_AOCPA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPA_SHIFT)) & ASRC_ASRCDR1_AOCPA_MASK) + #define ASRC_ASRCDR1_AOCDA_MASK (0x38000U) #define ASRC_ASRCDR1_AOCDA_SHIFT (15U) +/*! AOCDA - AOCDA + */ #define ASRC_ASRCDR1_AOCDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDA_SHIFT)) & ASRC_ASRCDR1_AOCDA_MASK) + #define ASRC_ASRCDR1_AOCPB_MASK (0x1C0000U) #define ASRC_ASRCDR1_AOCPB_SHIFT (18U) +/*! AOCPB - AOCPB + */ #define ASRC_ASRCDR1_AOCPB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPB_SHIFT)) & ASRC_ASRCDR1_AOCPB_MASK) + #define ASRC_ASRCDR1_AOCDB_MASK (0xE00000U) #define ASRC_ASRCDR1_AOCDB_SHIFT (21U) +/*! AOCDB - AOCDB + */ #define ASRC_ASRCDR1_AOCDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDB_SHIFT)) & ASRC_ASRCDR1_AOCDB_MASK) /*! @} */ /*! @name ASRCDR2 - ASRC Clock Divider Register 2 */ /*! @{ */ + #define ASRC_ASRCDR2_AICPC_MASK (0x7U) #define ASRC_ASRCDR2_AICPC_SHIFT (0U) +/*! AICPC - AICPC + */ #define ASRC_ASRCDR2_AICPC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICPC_SHIFT)) & ASRC_ASRCDR2_AICPC_MASK) + #define ASRC_ASRCDR2_AICDC_MASK (0x38U) #define ASRC_ASRCDR2_AICDC_SHIFT (3U) +/*! AICDC - AICDC + */ #define ASRC_ASRCDR2_AICDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICDC_SHIFT)) & ASRC_ASRCDR2_AICDC_MASK) + #define ASRC_ASRCDR2_AOCPC_MASK (0x1C0U) #define ASRC_ASRCDR2_AOCPC_SHIFT (6U) +/*! AOCPC - AOCPC + */ #define ASRC_ASRCDR2_AOCPC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCPC_SHIFT)) & ASRC_ASRCDR2_AOCPC_MASK) + #define ASRC_ASRCDR2_AOCDC_MASK (0xE00U) #define ASRC_ASRCDR2_AOCDC_SHIFT (9U) +/*! AOCDC - AOCDC + */ #define ASRC_ASRCDR2_AOCDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCDC_SHIFT)) & ASRC_ASRCDR2_AOCDC_MASK) /*! @} */ /*! @name ASRSTR - ASRC Status Register */ /*! @{ */ + #define ASRC_ASRSTR_AIDEA_MASK (0x1U) #define ASRC_ASRSTR_AIDEA_SHIFT (0U) +/*! AIDEA - AIDEA + * 0b1..When AIDEA is set, the ASRC generates data input A interrupt request to the processor if ASRIER[AIDEA] = 1 + * 0b0..The threshold has been met and no data input A interrupt is generated + */ #define ASRC_ASRSTR_AIDEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEA_SHIFT)) & ASRC_ASRSTR_AIDEA_MASK) + #define ASRC_ASRSTR_AIDEB_MASK (0x2U) #define ASRC_ASRSTR_AIDEB_SHIFT (1U) +/*! AIDEB - AIDEB + * 0b1..When AIDEB is set, the ASRC generates data input B interrupt request to the processor if ASRIER[AIDEB] = 1 + * 0b0..The threshold has been met and no data input B interrupt is generated + */ #define ASRC_ASRSTR_AIDEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEB_SHIFT)) & ASRC_ASRSTR_AIDEB_MASK) + #define ASRC_ASRSTR_AIDEC_MASK (0x4U) #define ASRC_ASRSTR_AIDEC_SHIFT (2U) +/*! AIDEC - AIDEC + * 0b1..When AIDEC is set, the ASRC generates data input C interrupt request to the processor if ASRIER[AIDEC] = 1 + * 0b0..The threshold has been met and no data input C interrupt is generated + */ #define ASRC_ASRSTR_AIDEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEC_SHIFT)) & ASRC_ASRSTR_AIDEC_MASK) + #define ASRC_ASRSTR_AODFA_MASK (0x8U) #define ASRC_ASRSTR_AODFA_SHIFT (3U) +/*! AODFA - AODFA + * 0b1..When AODFA is set, the ASRC generates data output A interrupt request to the processor if ASRIER[ADOEA] = 1 + * 0b0..The threshold has not yet been met and no data output A interrupt is generated + */ #define ASRC_ASRSTR_AODFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFA_SHIFT)) & ASRC_ASRSTR_AODFA_MASK) + #define ASRC_ASRSTR_AODFB_MASK (0x10U) #define ASRC_ASRSTR_AODFB_SHIFT (4U) +/*! AODFB - AODFB + * 0b1..When AODFB is set, the ASRC generates data output B interrupt request to the processor if ASRIER[ADOEB] = 1 + * 0b0..The threshold has not yet been met and no data output B interrupt is generated + */ #define ASRC_ASRSTR_AODFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFB_SHIFT)) & ASRC_ASRSTR_AODFB_MASK) + #define ASRC_ASRSTR_AODFC_MASK (0x20U) #define ASRC_ASRSTR_AODFC_SHIFT (5U) +/*! AODFC - AODFC + * 0b1..When AODFC is set, the ASRC generates data output C interrupt request to the processor if ASRIER[ADOEC] = 1 + * 0b0..The threshold has not yet been met and no data output C interrupt is generated + */ #define ASRC_ASRSTR_AODFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFC_SHIFT)) & ASRC_ASRSTR_AODFC_MASK) + #define ASRC_ASRSTR_AOLE_MASK (0x40U) #define ASRC_ASRSTR_AOLE_SHIFT (6U) +/*! AOLE - AOLE + * 0b1..Task rate is too high + * 0b0..No overload + */ #define ASRC_ASRSTR_AOLE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOLE_SHIFT)) & ASRC_ASRSTR_AOLE_MASK) + #define ASRC_ASRSTR_FPWT_MASK (0x80U) #define ASRC_ASRSTR_FPWT_SHIFT (7U) +/*! FPWT - FPWT + * 0b0..ASRC is not in wait state + * 0b0..ASRC is in wait state + */ #define ASRC_ASRSTR_FPWT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_FPWT_SHIFT)) & ASRC_ASRSTR_FPWT_MASK) + #define ASRC_ASRSTR_AIDUA_MASK (0x100U) #define ASRC_ASRSTR_AIDUA_SHIFT (8U) +/*! AIDUA - AIDUA + * 0b0..No Underflow in Input data buffer A + * 0b1..Underflow in Input data buffer A + */ #define ASRC_ASRSTR_AIDUA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUA_SHIFT)) & ASRC_ASRSTR_AIDUA_MASK) + #define ASRC_ASRSTR_AIDUB_MASK (0x200U) #define ASRC_ASRSTR_AIDUB_SHIFT (9U) +/*! AIDUB - AIDUB + * 0b0..No Underflow in Input data buffer B + * 0b1..Underflow in Input data buffer B + */ #define ASRC_ASRSTR_AIDUB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUB_SHIFT)) & ASRC_ASRSTR_AIDUB_MASK) + #define ASRC_ASRSTR_AIDUC_MASK (0x400U) #define ASRC_ASRSTR_AIDUC_SHIFT (10U) +/*! AIDUC - AIDUC + * 0b0..No Underflow in Input data buffer C + * 0b1..Underflow in Input data buffer C + */ #define ASRC_ASRSTR_AIDUC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUC_SHIFT)) & ASRC_ASRSTR_AIDUC_MASK) + #define ASRC_ASRSTR_AODOA_MASK (0x800U) #define ASRC_ASRSTR_AODOA_SHIFT (11U) +/*! AODOA - AODOA + * 0b0..No Overflow in Output data buffer A + * 0b1..Overflow in Output data buffer A + */ #define ASRC_ASRSTR_AODOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOA_SHIFT)) & ASRC_ASRSTR_AODOA_MASK) + #define ASRC_ASRSTR_AODOB_MASK (0x1000U) #define ASRC_ASRSTR_AODOB_SHIFT (12U) +/*! AODOB - AODOB + * 0b0..No Overflow in Output data buffer B + * 0b1..Overflow in Output data buffer B + */ #define ASRC_ASRSTR_AODOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOB_SHIFT)) & ASRC_ASRSTR_AODOB_MASK) + #define ASRC_ASRSTR_AODOC_MASK (0x2000U) #define ASRC_ASRSTR_AODOC_SHIFT (13U) +/*! AODOC - AODOC + * 0b0..No Overflow in Output data buffer C + * 0b1..Overflow in Output data buffer C + */ #define ASRC_ASRSTR_AODOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOC_SHIFT)) & ASRC_ASRSTR_AODOC_MASK) + #define ASRC_ASRSTR_AIOLA_MASK (0x4000U) #define ASRC_ASRSTR_AIOLA_SHIFT (14U) +/*! AIOLA - AIOLA + * 0b0..Pair A input task is not oveloaded + * 0b1..Pair A input task is oveloaded + */ #define ASRC_ASRSTR_AIOLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLA_SHIFT)) & ASRC_ASRSTR_AIOLA_MASK) + #define ASRC_ASRSTR_AIOLB_MASK (0x8000U) #define ASRC_ASRSTR_AIOLB_SHIFT (15U) +/*! AIOLB - AIOLB + * 0b0..Pair B input task is not oveloaded + * 0b1..Pair B input task is oveloaded + */ #define ASRC_ASRSTR_AIOLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLB_SHIFT)) & ASRC_ASRSTR_AIOLB_MASK) + #define ASRC_ASRSTR_AIOLC_MASK (0x10000U) #define ASRC_ASRSTR_AIOLC_SHIFT (16U) +/*! AIOLC - AIOLC + * 0b0..Pair C input task is not oveloaded + * 0b1..Pair C input task is oveloaded + */ #define ASRC_ASRSTR_AIOLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLC_SHIFT)) & ASRC_ASRSTR_AIOLC_MASK) + #define ASRC_ASRSTR_AOOLA_MASK (0x20000U) #define ASRC_ASRSTR_AOOLA_SHIFT (17U) +/*! AOOLA - AOOLA + * 0b0..Pair A output task is not oveloaded + * 0b1..Pair A output task is oveloaded + */ #define ASRC_ASRSTR_AOOLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLA_SHIFT)) & ASRC_ASRSTR_AOOLA_MASK) + #define ASRC_ASRSTR_AOOLB_MASK (0x40000U) #define ASRC_ASRSTR_AOOLB_SHIFT (18U) +/*! AOOLB - AOOLB + * 0b0..Pair B output task is not oveloaded + * 0b1..Pair B output task is oveloaded + */ #define ASRC_ASRSTR_AOOLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLB_SHIFT)) & ASRC_ASRSTR_AOOLB_MASK) + #define ASRC_ASRSTR_AOOLC_MASK (0x80000U) #define ASRC_ASRSTR_AOOLC_SHIFT (19U) +/*! AOOLC - AOOLC + * 0b0..Pair C output task is not oveloaded + * 0b1..Pair C output task is oveloaded + */ #define ASRC_ASRSTR_AOOLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLC_SHIFT)) & ASRC_ASRSTR_AOOLC_MASK) + #define ASRC_ASRSTR_ATQOL_MASK (0x100000U) #define ASRC_ASRSTR_ATQOL_SHIFT (20U) +/*! ATQOL - ATQOL + * 0b0..Task queue FIFO logic is not oveloaded + * 0b1..Task queue FIFO logic is oveloaded + */ #define ASRC_ASRSTR_ATQOL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_ATQOL_SHIFT)) & ASRC_ASRSTR_ATQOL_MASK) + #define ASRC_ASRSTR_DSLCNT_MASK (0x200000U) #define ASRC_ASRSTR_DSLCNT_SHIFT (21U) +/*! DSLCNT - DSLCNT + * 0b0..New DSL counter information is in the process of storage into the internal ASRC FIFO + * 0b1..New DSL counter information is stored in the internal ASRC FIFO + */ #define ASRC_ASRSTR_DSLCNT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_DSLCNT_SHIFT)) & ASRC_ASRSTR_DSLCNT_MASK) /*! @} */ -/*! @name ASRPMn - ASRC Parameter Register n */ +/*! @name ASRPM - ASRC Parameter Register n */ /*! @{ */ -#define ASRC_ASRPMn_PARAMETER_VALUE_MASK (0xFFFFFFU) -#define ASRC_ASRPMn_PARAMETER_VALUE_SHIFT (0U) -#define ASRC_ASRPMn_PARAMETER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRPMn_PARAMETER_VALUE_SHIFT)) & ASRC_ASRPMn_PARAMETER_VALUE_MASK) + +#define ASRC_ASRPM_PARAMETER_VALUE_MASK (0xFFFFFFU) +#define ASRC_ASRPM_PARAMETER_VALUE_SHIFT (0U) +/*! PARAMETER_VALUE - PARAMETER_VALUE + */ +#define ASRC_ASRPM_PARAMETER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRPM_PARAMETER_VALUE_SHIFT)) & ASRC_ASRPM_PARAMETER_VALUE_MASK) /*! @} */ -/* The count of ASRC_ASRPMn */ -#define ASRC_ASRPMn_COUNT (5U) +/* The count of ASRC_ASRPM */ +#define ASRC_ASRPM_COUNT (5U) -/*! @name ASRTFR1 - ASRC ASRC Task Queue FIFO Register 1 */ +/*! @name ASRTFR1 - ASRC Task Queue FIFO Register 1 */ /*! @{ */ + #define ASRC_ASRTFR1_TF_BASE_MASK (0x1FC0U) #define ASRC_ASRTFR1_TF_BASE_SHIFT (6U) +/*! TF_BASE - TF_BASE + */ #define ASRC_ASRTFR1_TF_BASE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_BASE_SHIFT)) & ASRC_ASRTFR1_TF_BASE_MASK) + #define ASRC_ASRTFR1_TF_FILL_MASK (0xFE000U) #define ASRC_ASRTFR1_TF_FILL_SHIFT (13U) +/*! TF_FILL - TF_FILL + */ #define ASRC_ASRTFR1_TF_FILL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_FILL_SHIFT)) & ASRC_ASRTFR1_TF_FILL_MASK) /*! @} */ /*! @name ASRCCR - ASRC Channel Counter Register */ /*! @{ */ + #define ASRC_ASRCCR_ACIA_MASK (0xFU) #define ASRC_ASRCCR_ACIA_SHIFT (0U) +/*! ACIA - ACIA + */ #define ASRC_ASRCCR_ACIA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIA_SHIFT)) & ASRC_ASRCCR_ACIA_MASK) + #define ASRC_ASRCCR_ACIB_MASK (0xF0U) #define ASRC_ASRCCR_ACIB_SHIFT (4U) +/*! ACIB - ACIB + */ #define ASRC_ASRCCR_ACIB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIB_SHIFT)) & ASRC_ASRCCR_ACIB_MASK) + #define ASRC_ASRCCR_ACIC_MASK (0xF00U) #define ASRC_ASRCCR_ACIC_SHIFT (8U) +/*! ACIC - ACIC + */ #define ASRC_ASRCCR_ACIC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIC_SHIFT)) & ASRC_ASRCCR_ACIC_MASK) + #define ASRC_ASRCCR_ACOA_MASK (0xF000U) #define ASRC_ASRCCR_ACOA_SHIFT (12U) +/*! ACOA - ACOA + */ #define ASRC_ASRCCR_ACOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOA_SHIFT)) & ASRC_ASRCCR_ACOA_MASK) + #define ASRC_ASRCCR_ACOB_MASK (0xF0000U) #define ASRC_ASRCCR_ACOB_SHIFT (16U) +/*! ACOB - ACOB + */ #define ASRC_ASRCCR_ACOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOB_SHIFT)) & ASRC_ASRCCR_ACOB_MASK) + #define ASRC_ASRCCR_ACOC_MASK (0xF00000U) #define ASRC_ASRCCR_ACOC_SHIFT (20U) +/*! ACOC - ACOC + */ #define ASRC_ASRCCR_ACOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOC_SHIFT)) & ASRC_ASRCCR_ACOC_MASK) /*! @} */ /*! @name ASRDIA - ASRC Data Input Register for Pair x */ /*! @{ */ + #define ASRC_ASRDIA_DATA_MASK (0xFFFFFFU) #define ASRC_ASRDIA_DATA_SHIFT (0U) +/*! DATA - DATA + */ #define ASRC_ASRDIA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIA_DATA_SHIFT)) & ASRC_ASRDIA_DATA_MASK) /*! @} */ /*! @name ASRDOA - ASRC Data Output Register for Pair x */ /*! @{ */ + #define ASRC_ASRDOA_DATA_MASK (0xFFFFFFU) #define ASRC_ASRDOA_DATA_SHIFT (0U) +/*! DATA - DATA + */ #define ASRC_ASRDOA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOA_DATA_SHIFT)) & ASRC_ASRDOA_DATA_MASK) /*! @} */ /*! @name ASRDIB - ASRC Data Input Register for Pair x */ /*! @{ */ + #define ASRC_ASRDIB_DATA_MASK (0xFFFFFFU) #define ASRC_ASRDIB_DATA_SHIFT (0U) +/*! DATA - DATA + */ #define ASRC_ASRDIB_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIB_DATA_SHIFT)) & ASRC_ASRDIB_DATA_MASK) /*! @} */ /*! @name ASRDOB - ASRC Data Output Register for Pair x */ /*! @{ */ + #define ASRC_ASRDOB_DATA_MASK (0xFFFFFFU) #define ASRC_ASRDOB_DATA_SHIFT (0U) +/*! DATA - DATA + */ #define ASRC_ASRDOB_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOB_DATA_SHIFT)) & ASRC_ASRDOB_DATA_MASK) /*! @} */ /*! @name ASRDIC - ASRC Data Input Register for Pair x */ /*! @{ */ + #define ASRC_ASRDIC_DATA_MASK (0xFFFFFFU) #define ASRC_ASRDIC_DATA_SHIFT (0U) +/*! DATA - DATA + */ #define ASRC_ASRDIC_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIC_DATA_SHIFT)) & ASRC_ASRDIC_DATA_MASK) /*! @} */ /*! @name ASRDOC - ASRC Data Output Register for Pair x */ /*! @{ */ + #define ASRC_ASRDOC_DATA_MASK (0xFFFFFFU) #define ASRC_ASRDOC_DATA_SHIFT (0U) +/*! DATA - DATA + */ #define ASRC_ASRDOC_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOC_DATA_SHIFT)) & ASRC_ASRDOC_DATA_MASK) /*! @} */ /*! @name ASRIDRHA - ASRC Ideal Ratio for Pair A-High Part */ /*! @{ */ + #define ASRC_ASRIDRHA_IDRATIOA_H_MASK (0xFFU) #define ASRC_ASRIDRHA_IDRATIOA_H_SHIFT (0U) +/*! IDRATIOA_H - IDRATIOA_H + */ #define ASRC_ASRIDRHA_IDRATIOA_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHA_IDRATIOA_H_SHIFT)) & ASRC_ASRIDRHA_IDRATIOA_H_MASK) /*! @} */ /*! @name ASRIDRLA - ASRC Ideal Ratio for Pair A -Low Part */ /*! @{ */ + #define ASRC_ASRIDRLA_IDRATIOA_L_MASK (0xFFFFFFU) #define ASRC_ASRIDRLA_IDRATIOA_L_SHIFT (0U) +/*! IDRATIOA_L - IDRATIOA_L + */ #define ASRC_ASRIDRLA_IDRATIOA_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLA_IDRATIOA_L_SHIFT)) & ASRC_ASRIDRLA_IDRATIOA_L_MASK) /*! @} */ /*! @name ASRIDRHB - ASRC Ideal Ratio for Pair B-High Part */ /*! @{ */ + #define ASRC_ASRIDRHB_IDRATIOB_H_MASK (0xFFU) #define ASRC_ASRIDRHB_IDRATIOB_H_SHIFT (0U) +/*! IDRATIOB_H - IDRATIOB_H + */ #define ASRC_ASRIDRHB_IDRATIOB_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHB_IDRATIOB_H_SHIFT)) & ASRC_ASRIDRHB_IDRATIOB_H_MASK) /*! @} */ /*! @name ASRIDRLB - ASRC Ideal Ratio for Pair B-Low Part */ /*! @{ */ + #define ASRC_ASRIDRLB_IDRATIOB_L_MASK (0xFFFFFFU) #define ASRC_ASRIDRLB_IDRATIOB_L_SHIFT (0U) +/*! IDRATIOB_L - IDRATIOB_L + */ #define ASRC_ASRIDRLB_IDRATIOB_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLB_IDRATIOB_L_SHIFT)) & ASRC_ASRIDRLB_IDRATIOB_L_MASK) /*! @} */ /*! @name ASRIDRHC - ASRC Ideal Ratio for Pair C-High Part */ /*! @{ */ + #define ASRC_ASRIDRHC_IDRATIOC_H_MASK (0xFFU) #define ASRC_ASRIDRHC_IDRATIOC_H_SHIFT (0U) +/*! IDRATIOC_H - IDRATIOC_H + */ #define ASRC_ASRIDRHC_IDRATIOC_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHC_IDRATIOC_H_SHIFT)) & ASRC_ASRIDRHC_IDRATIOC_H_MASK) /*! @} */ /*! @name ASRIDRLC - ASRC Ideal Ratio for Pair C-Low Part */ /*! @{ */ + #define ASRC_ASRIDRLC_IDRATIOC_L_MASK (0xFFFFFFU) #define ASRC_ASRIDRLC_IDRATIOC_L_SHIFT (0U) +/*! IDRATIOC_L - IDRATIOC_L + */ #define ASRC_ASRIDRLC_IDRATIOC_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLC_IDRATIOC_L_SHIFT)) & ASRC_ASRIDRLC_IDRATIOC_L_MASK) /*! @} */ /*! @name ASR76K - ASRC 76 kHz Period in terms of ASRC processing clock */ /*! @{ */ + #define ASRC_ASR76K_ASR76K_MASK (0x1FFFFU) #define ASRC_ASR76K_ASR76K_SHIFT (0U) +/*! ASR76K - ASR76K + */ #define ASRC_ASR76K_ASR76K(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASR76K_ASR76K_SHIFT)) & ASRC_ASR76K_ASR76K_MASK) /*! @} */ /*! @name ASR56K - ASRC 56 kHz Period in terms of ASRC processing clock */ /*! @{ */ + #define ASRC_ASR56K_ASR56K_MASK (0x1FFFFU) #define ASRC_ASR56K_ASR56K_SHIFT (0U) +/*! ASR56K - ASR56K + */ #define ASRC_ASR56K_ASR56K(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASR56K_ASR56K_SHIFT)) & ASRC_ASR56K_ASR56K_MASK) /*! @} */ /*! @name ASRMCRA - ASRC Misc Control Register for Pair A */ /*! @{ */ + #define ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK (0x3FU) #define ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT (0U) +/*! INFIFO_THRESHOLDA - INFIFO_THRESHOLDA + */ #define ASRC_ASRMCRA_INFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK) + #define ASRC_ASRMCRA_RSYNOFA_MASK (0x400U) #define ASRC_ASRMCRA_RSYNOFA_SHIFT (10U) +/*! RSYNOFA - RSYNOFA + * 0b1..Force ASRCCR[ACOA]=0 + * 0b0..Do not touch ASRCCR[ACOA] + */ #define ASRC_ASRMCRA_RSYNOFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNOFA_SHIFT)) & ASRC_ASRMCRA_RSYNOFA_MASK) + #define ASRC_ASRMCRA_RSYNIFA_MASK (0x800U) #define ASRC_ASRMCRA_RSYNIFA_SHIFT (11U) +/*! RSYNIFA - RSYNIFA + * 0b1..Force ASRCCR[ACIA]=0 + * 0b0..Do not touch ASRCCR[ACIA] + */ #define ASRC_ASRMCRA_RSYNIFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNIFA_SHIFT)) & ASRC_ASRMCRA_RSYNIFA_MASK) + #define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK (0x3F000U) #define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT (12U) +/*! OUTFIFO_THRESHOLDA - OUTFIFO_THRESHOLDA + */ #define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK) + #define ASRC_ASRMCRA_BYPASSPOLYA_MASK (0x100000U) #define ASRC_ASRMCRA_BYPASSPOLYA_SHIFT (20U) -/*! BYPASSPOLYA +/*! BYPASSPOLYA - BYPASSPOLYA * 0b1..Bypass polyphase filtering. * 0b0..Don't bypass polyphase filtering. */ #define ASRC_ASRMCRA_BYPASSPOLYA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BYPASSPOLYA_SHIFT)) & ASRC_ASRMCRA_BYPASSPOLYA_MASK) + #define ASRC_ASRMCRA_BUFSTALLA_MASK (0x200000U) #define ASRC_ASRMCRA_BUFSTALLA_SHIFT (21U) -/*! BUFSTALLA +/*! BUFSTALLA - BUFSTALLA * 0b1..Stall Pair A conversion in case of near empty/full FIFO conditions. * 0b0..Don't stall Pair A conversion even in case of near empty/full FIFO conditions. */ #define ASRC_ASRMCRA_BUFSTALLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BUFSTALLA_SHIFT)) & ASRC_ASRMCRA_BUFSTALLA_MASK) + #define ASRC_ASRMCRA_EXTTHRSHA_MASK (0x400000U) #define ASRC_ASRMCRA_EXTTHRSHA_SHIFT (22U) -/*! EXTTHRSHA +/*! EXTTHRSHA - EXTTHRSHA * 0b1..Use external defined thresholds. * 0b0..Use default thresholds. */ #define ASRC_ASRMCRA_EXTTHRSHA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_EXTTHRSHA_SHIFT)) & ASRC_ASRMCRA_EXTTHRSHA_MASK) + #define ASRC_ASRMCRA_ZEROBUFA_MASK (0x800000U) #define ASRC_ASRMCRA_ZEROBUFA_SHIFT (23U) -/*! ZEROBUFA +/*! ZEROBUFA - ZEROBUFA * 0b1..Don't zeroize the buffer * 0b0..Zeroize the buffer */ @@ -9912,58 +10801,94 @@ typedef struct { /*! @name ASRFSTA - ASRC FIFO Status Register for Pair A */ /*! @{ */ + #define ASRC_ASRFSTA_INFIFO_FILLA_MASK (0x7FU) #define ASRC_ASRFSTA_INFIFO_FILLA_SHIFT (0U) +/*! INFIFO_FILLA - INFIFO_FILLA + */ #define ASRC_ASRFSTA_INFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_INFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_INFIFO_FILLA_MASK) + #define ASRC_ASRFSTA_IAEA_MASK (0x800U) #define ASRC_ASRFSTA_IAEA_SHIFT (11U) +/*! IAEA - IAEA + * 0b1..Input FIFO is near empty for Pair A + * 0b0..Input FIFO is not near empty for Pair A + */ #define ASRC_ASRFSTA_IAEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_IAEA_SHIFT)) & ASRC_ASRFSTA_IAEA_MASK) + #define ASRC_ASRFSTA_OUTFIFO_FILLA_MASK (0x7F000U) #define ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT (12U) +/*! OUTFIFO_FILLA - OUTFIFO_FILLA + */ #define ASRC_ASRFSTA_OUTFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_OUTFIFO_FILLA_MASK) + #define ASRC_ASRFSTA_OAFA_MASK (0x800000U) #define ASRC_ASRFSTA_OAFA_SHIFT (23U) +/*! OAFA - OAFA + * 0b1..Output FIFO is near full for Pair A + * 0b0..Output FIFO is not near full for Pair A + */ #define ASRC_ASRFSTA_OAFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OAFA_SHIFT)) & ASRC_ASRFSTA_OAFA_MASK) /*! @} */ /*! @name ASRMCRB - ASRC Misc Control Register for Pair B */ /*! @{ */ + #define ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK (0x3FU) #define ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT (0U) +/*! INFIFO_THRESHOLDB - INFIFO_THRESHOLDB + */ #define ASRC_ASRMCRB_INFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK) + #define ASRC_ASRMCRB_RSYNOFB_MASK (0x400U) #define ASRC_ASRMCRB_RSYNOFB_SHIFT (10U) +/*! RSYNOFB - RSYNOFB + * 0b1..Force ASRCCR[ACOB]=0 + * 0b0..Do not touch ASRCCR[ACOB] + */ #define ASRC_ASRMCRB_RSYNOFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNOFB_SHIFT)) & ASRC_ASRMCRB_RSYNOFB_MASK) + #define ASRC_ASRMCRB_RSYNIFB_MASK (0x800U) #define ASRC_ASRMCRB_RSYNIFB_SHIFT (11U) +/*! RSYNIFB - RSYNIFB + * 0b1..Force ASRCCR[ACIB]=0 + * 0b0..Do not touch ASRCCR[ACIB] + */ #define ASRC_ASRMCRB_RSYNIFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNIFB_SHIFT)) & ASRC_ASRMCRB_RSYNIFB_MASK) + #define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK (0x3F000U) #define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT (12U) +/*! OUTFIFO_THRESHOLDB - OUTFIFO_THRESHOLDB + */ #define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK) + #define ASRC_ASRMCRB_BYPASSPOLYB_MASK (0x100000U) #define ASRC_ASRMCRB_BYPASSPOLYB_SHIFT (20U) -/*! BYPASSPOLYB +/*! BYPASSPOLYB - BYPASSPOLYB * 0b1..Bypass polyphase filtering. * 0b0..Don't bypass polyphase filtering. */ #define ASRC_ASRMCRB_BYPASSPOLYB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BYPASSPOLYB_SHIFT)) & ASRC_ASRMCRB_BYPASSPOLYB_MASK) + #define ASRC_ASRMCRB_BUFSTALLB_MASK (0x200000U) #define ASRC_ASRMCRB_BUFSTALLB_SHIFT (21U) -/*! BUFSTALLB +/*! BUFSTALLB - BUFSTALLB * 0b1..Stall Pair B conversion in case of near empty/full FIFO conditions. * 0b0..Don't stall Pair B conversion even in case of near empty/full FIFO conditions. */ #define ASRC_ASRMCRB_BUFSTALLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BUFSTALLB_SHIFT)) & ASRC_ASRMCRB_BUFSTALLB_MASK) + #define ASRC_ASRMCRB_EXTTHRSHB_MASK (0x400000U) #define ASRC_ASRMCRB_EXTTHRSHB_SHIFT (22U) -/*! EXTTHRSHB +/*! EXTTHRSHB - EXTTHRSHB * 0b1..Use external defined thresholds. * 0b0..Use default thresholds. */ #define ASRC_ASRMCRB_EXTTHRSHB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_EXTTHRSHB_SHIFT)) & ASRC_ASRMCRB_EXTTHRSHB_MASK) + #define ASRC_ASRMCRB_ZEROBUFB_MASK (0x800000U) #define ASRC_ASRMCRB_ZEROBUFB_SHIFT (23U) -/*! ZEROBUFB +/*! ZEROBUFB - ZEROBUFB * 0b1..Don't zeroize the buffer * 0b0..Zeroize the buffer */ @@ -9972,58 +10897,94 @@ typedef struct { /*! @name ASRFSTB - ASRC FIFO Status Register for Pair B */ /*! @{ */ + #define ASRC_ASRFSTB_INFIFO_FILLB_MASK (0x7FU) #define ASRC_ASRFSTB_INFIFO_FILLB_SHIFT (0U) +/*! INFIFO_FILLB - INFIFO_FILLB + */ #define ASRC_ASRFSTB_INFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_INFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_INFIFO_FILLB_MASK) + #define ASRC_ASRFSTB_IAEB_MASK (0x800U) #define ASRC_ASRFSTB_IAEB_SHIFT (11U) +/*! IAEB - IAEB + * 0b1..Input FIFO is near empty for Pair B + * 0b0..Input FIFO is not near empty for Pair B + */ #define ASRC_ASRFSTB_IAEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_IAEB_SHIFT)) & ASRC_ASRFSTB_IAEB_MASK) + #define ASRC_ASRFSTB_OUTFIFO_FILLB_MASK (0x7F000U) #define ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT (12U) +/*! OUTFIFO_FILLB - OUTFIFO_FILLB + */ #define ASRC_ASRFSTB_OUTFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_OUTFIFO_FILLB_MASK) + #define ASRC_ASRFSTB_OAFB_MASK (0x800000U) #define ASRC_ASRFSTB_OAFB_SHIFT (23U) +/*! OAFB - OAFB + * 0b1..Output FIFO is near full for Pair B + * 0b0..Output FIFO is not near full for Pair B + */ #define ASRC_ASRFSTB_OAFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OAFB_SHIFT)) & ASRC_ASRFSTB_OAFB_MASK) /*! @} */ /*! @name ASRMCRC - ASRC Misc Control Register for Pair C */ /*! @{ */ + #define ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK (0x3FU) #define ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT (0U) +/*! INFIFO_THRESHOLDC - INFIFO_THRESHOLDC + */ #define ASRC_ASRMCRC_INFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK) + #define ASRC_ASRMCRC_RSYNOFC_MASK (0x400U) #define ASRC_ASRMCRC_RSYNOFC_SHIFT (10U) +/*! RSYNOFC - RSYNOFC + * 0b1..Force ASRCCR[ACOC]=0 + * 0b0..Do not touch ASRCCR[ACOC] + */ #define ASRC_ASRMCRC_RSYNOFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNOFC_SHIFT)) & ASRC_ASRMCRC_RSYNOFC_MASK) + #define ASRC_ASRMCRC_RSYNIFC_MASK (0x800U) #define ASRC_ASRMCRC_RSYNIFC_SHIFT (11U) +/*! RSYNIFC - RSYNIFC + * 0b1..Force ASRCCR[ACIC]=0 + * 0b0..Do not touch ASRCCR[ACIC] + */ #define ASRC_ASRMCRC_RSYNIFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNIFC_SHIFT)) & ASRC_ASRMCRC_RSYNIFC_MASK) + #define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK (0x3F000U) #define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT (12U) +/*! OUTFIFO_THRESHOLDC - OUTFIFO_THRESHOLDC + */ #define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK) + #define ASRC_ASRMCRC_BYPASSPOLYC_MASK (0x100000U) #define ASRC_ASRMCRC_BYPASSPOLYC_SHIFT (20U) -/*! BYPASSPOLYC +/*! BYPASSPOLYC - BYPASSPOLYC * 0b1..Bypass polyphase filtering. * 0b0..Don't bypass polyphase filtering. */ #define ASRC_ASRMCRC_BYPASSPOLYC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BYPASSPOLYC_SHIFT)) & ASRC_ASRMCRC_BYPASSPOLYC_MASK) + #define ASRC_ASRMCRC_BUFSTALLC_MASK (0x200000U) #define ASRC_ASRMCRC_BUFSTALLC_SHIFT (21U) -/*! BUFSTALLC +/*! BUFSTALLC - BUFSTALLC * 0b1..Stall Pair C conversion in case of near empty/full FIFO conditions. * 0b0..Don't stall Pair C conversion even in case of near empty/full FIFO conditions. */ #define ASRC_ASRMCRC_BUFSTALLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BUFSTALLC_SHIFT)) & ASRC_ASRMCRC_BUFSTALLC_MASK) + #define ASRC_ASRMCRC_EXTTHRSHC_MASK (0x400000U) #define ASRC_ASRMCRC_EXTTHRSHC_SHIFT (22U) -/*! EXTTHRSHC +/*! EXTTHRSHC - EXTTHRSHC * 0b1..Use external defined thresholds. * 0b0..Use default thresholds. */ #define ASRC_ASRMCRC_EXTTHRSHC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_EXTTHRSHC_SHIFT)) & ASRC_ASRMCRC_EXTTHRSHC_MASK) + #define ASRC_ASRMCRC_ZEROBUFC_MASK (0x800000U) #define ASRC_ASRMCRC_ZEROBUFC_SHIFT (23U) -/*! ZEROBUFC +/*! ZEROBUFC - ZEROBUFC * 0b1..Don't zeroize the buffer * 0b0..Zeroize the buffer */ @@ -10032,52 +10993,79 @@ typedef struct { /*! @name ASRFSTC - ASRC FIFO Status Register for Pair C */ /*! @{ */ + #define ASRC_ASRFSTC_INFIFO_FILLC_MASK (0x7FU) #define ASRC_ASRFSTC_INFIFO_FILLC_SHIFT (0U) +/*! INFIFO_FILLC - INFIFO_FILLC + */ #define ASRC_ASRFSTC_INFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_INFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_INFIFO_FILLC_MASK) + #define ASRC_ASRFSTC_IAEC_MASK (0x800U) #define ASRC_ASRFSTC_IAEC_SHIFT (11U) +/*! IAEC - IAEC + * 0b1..Input FIFO is near empty for Pair C + * 0b0..Input FIFO is not near empty for Pair C + */ #define ASRC_ASRFSTC_IAEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_IAEC_SHIFT)) & ASRC_ASRFSTC_IAEC_MASK) + #define ASRC_ASRFSTC_OUTFIFO_FILLC_MASK (0x7F000U) #define ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT (12U) +/*! OUTFIFO_FILLC - OUTFIFO_FILLC + */ #define ASRC_ASRFSTC_OUTFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_OUTFIFO_FILLC_MASK) + #define ASRC_ASRFSTC_OAFC_MASK (0x800000U) #define ASRC_ASRFSTC_OAFC_SHIFT (23U) +/*! OAFC - OAFC + * 0b1..Output FIFO is near full for Pair C + * 0b0..Output FIFO is not near full for Pair C + */ #define ASRC_ASRFSTC_OAFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OAFC_SHIFT)) & ASRC_ASRFSTC_OAFC_MASK) /*! @} */ /*! @name ASRMCR1 - ASRC Misc Control Register 1 for Pair X */ /*! @{ */ + #define ASRC_ASRMCR1_OW16_MASK (0x1U) #define ASRC_ASRMCR1_OW16_SHIFT (0U) -/*! OW16 +/*! OW16 - OW16 * 0b1..16-bit output data * 0b0..24-bit output data. */ #define ASRC_ASRMCR1_OW16(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OW16_SHIFT)) & ASRC_ASRMCR1_OW16_MASK) + #define ASRC_ASRMCR1_OSGN_MASK (0x2U) #define ASRC_ASRMCR1_OSGN_SHIFT (1U) -/*! OSGN +/*! OSGN - OSGN * 0b1..Sign extension. * 0b0..No sign extension. */ #define ASRC_ASRMCR1_OSGN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OSGN_SHIFT)) & ASRC_ASRMCR1_OSGN_MASK) + #define ASRC_ASRMCR1_OMSB_MASK (0x4U) #define ASRC_ASRMCR1_OMSB_SHIFT (2U) -/*! OMSB +/*! OMSB - OMSB * 0b1..MSB aligned. * 0b0..LSB aligned. */ #define ASRC_ASRMCR1_OMSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OMSB_SHIFT)) & ASRC_ASRMCR1_OMSB_MASK) + #define ASRC_ASRMCR1_IMSB_MASK (0x100U) #define ASRC_ASRMCR1_IMSB_SHIFT (8U) -/*! IMSB +/*! IMSB - IMSB * 0b1..MSB aligned. * 0b0..LSB aligned. */ #define ASRC_ASRMCR1_IMSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IMSB_SHIFT)) & ASRC_ASRMCR1_IMSB_MASK) -#define ASRC_ASRMCR1_IWD_MASK (0xE00U) + +#define ASRC_ASRMCR1_IWD_MASK (0x600U) #define ASRC_ASRMCR1_IWD_SHIFT (9U) +/*! IWD - IWD + * 0b00..24-bit audio data. + * 0b01..16-bit audio data. + * 0b10..8-bit audio data. + * 0b11..Reserved. + */ #define ASRC_ASRMCR1_IWD(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IWD_SHIFT)) & ASRC_ASRMCR1_IWD_MASK) /*! @} */ @@ -10142,30 +11130,6 @@ typedef struct { __IO uint32_t CLR; /**< Fractional PLL Denominator Control Register, offset: 0x38 */ __IO uint32_t TOG; /**< Fractional PLL Denominator Control Register, offset: 0x3C */ } DENOMINATOR; - struct { /* offset: 0x40 */ - uint32_t RW; /**< Fractional PLL Reserved Control Register, offset: 0x40 */ - uint32_t SET; /**< Fractional PLL Reserved Control Register, offset: 0x44 */ - uint32_t CLR; /**< Fractional PLL Reserved Control Register, offset: 0x48 */ - uint32_t TOG; /**< Fractional PLL Reserved Control Register, offset: 0x4C */ - } CTRL4; - struct { /* offset: 0x50 */ - __I uint32_t RW; /**< Analog Status Register STAT0, offset: 0x50 */ - __I uint32_t SET; /**< Analog Status Register STAT0, offset: 0x54 */ - __I uint32_t CLR; /**< Analog Status Register STAT0, offset: 0x58 */ - __I uint32_t TOG; /**< Analog Status Register STAT0, offset: 0x5C */ - } STAT0; - struct { /* offset: 0x60 */ - __I uint32_t RW; /**< Analog Status Register STAT1, offset: 0x60 */ - __I uint32_t SET; /**< Analog Status Register STAT1, offset: 0x64 */ - __I uint32_t CLR; /**< Analog Status Register STAT1, offset: 0x68 */ - __I uint32_t TOG; /**< Analog Status Register STAT1, offset: 0x6C */ - } STAT1; - struct { /* offset: 0x70 */ - __I uint32_t RW; /**< Analog Status Register STAT2, offset: 0x70 */ - __I uint32_t SET; /**< Analog Status Register STAT2, offset: 0x74 */ - __I uint32_t CLR; /**< Analog Status Register STAT2, offset: 0x78 */ - __I uint32_t TOG; /**< Analog Status Register STAT2, offset: 0x7C */ - } STAT2; } AUDIO_PLL_Type; /* ---------------------------------------------------------------------------- @@ -10179,105 +11143,109 @@ typedef struct { /*! @name CTRL0 - Fractional PLL Control Register */ /*! @{ */ + #define AUDIO_PLL_CTRL0_DIV_SELECT_MASK (0x7FU) #define AUDIO_PLL_CTRL0_DIV_SELECT_SHIFT (0U) /*! DIV_SELECT - DIV_SELECT */ #define AUDIO_PLL_CTRL0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_DIV_SELECT_SHIFT)) & AUDIO_PLL_CTRL0_DIV_SELECT_MASK) -#define AUDIO_PLL_CTRL0_HALF_LF_MASK (0x200U) -#define AUDIO_PLL_CTRL0_HALF_LF_SHIFT (9U) -/*! HALF_LF - HALF_LF - */ -#define AUDIO_PLL_CTRL0_HALF_LF(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_HALF_LF_SHIFT)) & AUDIO_PLL_CTRL0_HALF_LF_MASK) -#define AUDIO_PLL_CTRL0_DOUBLE_LF_MASK (0x400U) -#define AUDIO_PLL_CTRL0_DOUBLE_LF_SHIFT (10U) -/*! DOUBLE_LF - DOUBLE_LF - */ -#define AUDIO_PLL_CTRL0_DOUBLE_LF(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_DOUBLE_LF_SHIFT)) & AUDIO_PLL_CTRL0_DOUBLE_LF_MASK) -#define AUDIO_PLL_CTRL0_HALF_CP_MASK (0x800U) -#define AUDIO_PLL_CTRL0_HALF_CP_SHIFT (11U) -/*! HALF_CP - HALF_CP - */ -#define AUDIO_PLL_CTRL0_HALF_CP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_HALF_CP_SHIFT)) & AUDIO_PLL_CTRL0_HALF_CP_MASK) -#define AUDIO_PLL_CTRL0_DOUBLE_CP_MASK (0x1000U) -#define AUDIO_PLL_CTRL0_DOUBLE_CP_SHIFT (12U) -/*! DOUBLE_CP - DOUBLE_CP - */ -#define AUDIO_PLL_CTRL0_DOUBLE_CP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_DOUBLE_CP_SHIFT)) & AUDIO_PLL_CTRL0_DOUBLE_CP_MASK) + +#define AUDIO_PLL_CTRL0_ENABLE_ALT_MASK (0x100U) +#define AUDIO_PLL_CTRL0_ENABLE_ALT_SHIFT (8U) +/*! ENABLE_ALT - ENABLE_ALT + * 0b0..Disable the alternate clock output + * 0b1..Enable the alternate clock output which is the output of the post_divider, and cannot be bypassed + */ +#define AUDIO_PLL_CTRL0_ENABLE_ALT(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_ENABLE_ALT_SHIFT)) & AUDIO_PLL_CTRL0_ENABLE_ALT_MASK) + #define AUDIO_PLL_CTRL0_HOLD_RING_OFF_MASK (0x2000U) #define AUDIO_PLL_CTRL0_HOLD_RING_OFF_SHIFT (13U) -/*! HOLD_RING_OFF - HOLD_RING_OFF +/*! HOLD_RING_OFF - PLL Start up initialization + * 0b0..Normal operation + * 0b1..Initialize PLL start up */ #define AUDIO_PLL_CTRL0_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_HOLD_RING_OFF_SHIFT)) & AUDIO_PLL_CTRL0_HOLD_RING_OFF_MASK) + #define AUDIO_PLL_CTRL0_POWERUP_MASK (0x4000U) #define AUDIO_PLL_CTRL0_POWERUP_SHIFT (14U) /*! POWERUP - POWERUP + * 0b1..Power Up the PLL + * 0b0..Power down the PLL */ #define AUDIO_PLL_CTRL0_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_POWERUP_SHIFT)) & AUDIO_PLL_CTRL0_POWERUP_MASK) + #define AUDIO_PLL_CTRL0_ENABLE_MASK (0x8000U) #define AUDIO_PLL_CTRL0_ENABLE_SHIFT (15U) /*! ENABLE - ENABLE + * 0b1..Enable the clock output + * 0b0..Disable the clock output */ #define AUDIO_PLL_CTRL0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_ENABLE_SHIFT)) & AUDIO_PLL_CTRL0_ENABLE_MASK) + #define AUDIO_PLL_CTRL0_BYPASS_MASK (0x10000U) #define AUDIO_PLL_CTRL0_BYPASS_SHIFT (16U) /*! BYPASS - BYPASS + * 0b1..Bypass the PLL + * 0b0..No Bypass */ #define AUDIO_PLL_CTRL0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_BYPASS_SHIFT)) & AUDIO_PLL_CTRL0_BYPASS_MASK) + #define AUDIO_PLL_CTRL0_DITHER_EN_MASK (0x20000U) #define AUDIO_PLL_CTRL0_DITHER_EN_SHIFT (17U) /*! DITHER_EN - DITHER_EN + * 0b0..Disable Dither + * 0b1..Enable Dither */ #define AUDIO_PLL_CTRL0_DITHER_EN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_DITHER_EN_SHIFT)) & AUDIO_PLL_CTRL0_DITHER_EN_MASK) -#define AUDIO_PLL_CTRL0_PFD_OFFSET_EN_MASK (0x40000U) -#define AUDIO_PLL_CTRL0_PFD_OFFSET_EN_SHIFT (18U) -/*! PFD_OFFSET_EN - PFD_OFFSET_EN - */ -#define AUDIO_PLL_CTRL0_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_PFD_OFFSET_EN_SHIFT)) & AUDIO_PLL_CTRL0_PFD_OFFSET_EN_MASK) + #define AUDIO_PLL_CTRL0_BIAS_TRIM_MASK (0x380000U) #define AUDIO_PLL_CTRL0_BIAS_TRIM_SHIFT (19U) /*! BIAS_TRIM - BIAS_TRIM */ #define AUDIO_PLL_CTRL0_BIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_BIAS_TRIM_SHIFT)) & AUDIO_PLL_CTRL0_BIAS_TRIM_MASK) + #define AUDIO_PLL_CTRL0_PLL_REG_EN_MASK (0x400000U) #define AUDIO_PLL_CTRL0_PLL_REG_EN_SHIFT (22U) /*! PLL_REG_EN - PLL_REG_EN */ #define AUDIO_PLL_CTRL0_PLL_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_PLL_REG_EN_SHIFT)) & AUDIO_PLL_CTRL0_PLL_REG_EN_MASK) -#define AUDIO_PLL_CTRL0_REGULATOR_VOLT_TRIM_MASK (0x1800000U) -#define AUDIO_PLL_CTRL0_REGULATOR_VOLT_TRIM_SHIFT (23U) -/*! REGULATOR_VOLT_TRIM - Regulator trim - */ -#define AUDIO_PLL_CTRL0_REGULATOR_VOLT_TRIM(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_REGULATOR_VOLT_TRIM_SHIFT)) & AUDIO_PLL_CTRL0_REGULATOR_VOLT_TRIM_MASK) + #define AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK (0xE000000U) #define AUDIO_PLL_CTRL0_POST_DIV_SEL_SHIFT (25U) /*! POST_DIV_SEL - Post Divide Select + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 */ #define AUDIO_PLL_CTRL0_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK) -#define AUDIO_PLL_CTRL0_TEST_MODE_MASK (0x40000000U) -#define AUDIO_PLL_CTRL0_TEST_MODE_SHIFT (30U) -/*! TEST_MODE - TEST_MODE - */ -#define AUDIO_PLL_CTRL0_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_TEST_MODE_SHIFT)) & AUDIO_PLL_CTRL0_TEST_MODE_MASK) -#define AUDIO_PLL_CTRL0_TEST_MUX_ENABLE_MASK (0x80000000U) -#define AUDIO_PLL_CTRL0_TEST_MUX_ENABLE_SHIFT (31U) -/*! TEST_MUX_ENABLE - TEST_MUX_ENABLE + +#define AUDIO_PLL_CTRL0_BIAS_SELECT_MASK (0x20000000U) +#define AUDIO_PLL_CTRL0_BIAS_SELECT_SHIFT (29U) +/*! BIAS_SELECT - BIAS_SELECT + * 0b0..Used in SoCs with a bias current of 10uA + * 0b1..Used in SoCs with a bias current of 2uA */ -#define AUDIO_PLL_CTRL0_TEST_MUX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_TEST_MUX_ENABLE_SHIFT)) & AUDIO_PLL_CTRL0_TEST_MUX_ENABLE_MASK) +#define AUDIO_PLL_CTRL0_BIAS_SELECT(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_BIAS_SELECT_SHIFT)) & AUDIO_PLL_CTRL0_BIAS_SELECT_MASK) /*! @} */ /*! @name SPREAD_SPECTRUM - Fractional PLL Spread Spectrum Control Register */ /*! @{ */ + #define AUDIO_PLL_SPREAD_SPECTRUM_STEP_MASK (0x7FFFU) #define AUDIO_PLL_SPREAD_SPECTRUM_STEP_SHIFT (0U) /*! STEP - Step */ #define AUDIO_PLL_SPREAD_SPECTRUM_STEP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_SPREAD_SPECTRUM_STEP_SHIFT)) & AUDIO_PLL_SPREAD_SPECTRUM_STEP_MASK) + #define AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_MASK (0x8000U) #define AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT (15U) /*! ENABLE - Enable */ #define AUDIO_PLL_SPREAD_SPECTRUM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT)) & AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_MASK) + #define AUDIO_PLL_SPREAD_SPECTRUM_STOP_MASK (0xFFFF0000U) #define AUDIO_PLL_SPREAD_SPECTRUM_STOP_SHIFT (16U) /*! STOP - Stop @@ -10287,6 +11255,7 @@ typedef struct { /*! @name NUMERATOR - Fractional PLL Numerator Control Register */ /*! @{ */ + #define AUDIO_PLL_NUMERATOR_NUM_MASK (0x3FFFFFFFU) #define AUDIO_PLL_NUMERATOR_NUM_SHIFT (0U) /*! NUM - Numerator @@ -10296,6 +11265,7 @@ typedef struct { /*! @name DENOMINATOR - Fractional PLL Denominator Control Register */ /*! @{ */ + #define AUDIO_PLL_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU) #define AUDIO_PLL_DENOMINATOR_DENOM_SHIFT (0U) /*! DENOM - Denominator @@ -10303,33 +11273,6 @@ typedef struct { #define AUDIO_PLL_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_DENOMINATOR_DENOM_SHIFT)) & AUDIO_PLL_DENOMINATOR_DENOM_MASK) /*! @} */ -/*! @name STAT0 - Analog Status Register STAT0 */ -/*! @{ */ -#define AUDIO_PLL_STAT0_REG_MASK (0xFFFFFFFFU) -#define AUDIO_PLL_STAT0_REG_SHIFT (0U) -/*! REG - STAT0 Register - */ -#define AUDIO_PLL_STAT0_REG(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_STAT0_REG_SHIFT)) & AUDIO_PLL_STAT0_REG_MASK) -/*! @} */ - -/*! @name STAT1 - Analog Status Register STAT1 */ -/*! @{ */ -#define AUDIO_PLL_STAT1_REG_MASK (0xFFFFFFFFU) -#define AUDIO_PLL_STAT1_REG_SHIFT (0U) -/*! REG - STAT1 Register - */ -#define AUDIO_PLL_STAT1_REG(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_STAT1_REG_SHIFT)) & AUDIO_PLL_STAT1_REG_MASK) -/*! @} */ - -/*! @name STAT2 - Analog Status Register STAT2 */ -/*! @{ */ -#define AUDIO_PLL_STAT2_REG_MASK (0xFFFFFFFFU) -#define AUDIO_PLL_STAT2_REG_SHIFT (0U) -/*! REG - STAT2 Register - */ -#define AUDIO_PLL_STAT2_REG(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_STAT2_REG_SHIFT)) & AUDIO_PLL_STAT2_REG_MASK) -/*! @} */ - /*! * @} @@ -10499,9 +11442,10 @@ typedef struct { __O uint32_t RDHBUF; /**< RNG DRNG Hash Buffer Register, offset: 0x6E8 */ uint8_t RESERVED_24[788]; struct { /* offset: 0xA00, array step: 0x10 */ - __I uint32_t PX_SDIDR_PG0; /**< Partition 0 SDID register..Partition 15 SDID register, array offset: 0xA00, array step: 0x10 */ + __I uint32_t PX_SDID_PG0; /**< Partition 0 SDID register..Partition 15 SDID register, array offset: 0xA00, array step: 0x10 */ __IO uint32_t PX_SMAPR_PG0; /**< Secure Memory Access Permissions register, array offset: 0xA04, array step: 0x10 */ - __IO uint32_t PX_SMAG_PG0[2]; /**< Secure Memory Access Group Registers, array offset: 0xA08, array step: index*0x10, index2*0x4 */ + __IO uint32_t PX_SMAG2_PG0; /**< Secure Memory Access Group Registers, array offset: 0xA08, array step: 0x10 */ + __IO uint32_t PX_SMAG1_PG0; /**< Secure Memory Access Group Registers, array offset: 0xA0C, array step: 0x10 */ } PX_PG0[16]; __IO uint32_t REIS; /**< Recoverable Error Interrupt Status, offset: 0xB00 */ __IO uint32_t REIE; /**< Recoverable Error Interrupt Enable, offset: 0xB04 */ @@ -10592,9 +11536,10 @@ typedef struct { __I uint64_t JRAAA[4]; /**< Job Ring 0 Address-Array Address 0 Register..Job Ring 3 Address-Array Address 3 Register, array offset: 0x10800, array step: index*0x10000, index2*0x8 */ uint8_t RESERVED_13[480]; struct { /* offset: 0x10A00, array step: index*0x10000, index2*0x10 */ - __I uint32_t PX_SDIDR_JR; /**< Partition 0 SDID register..Partition 15 SDID register, array offset: 0x10A00, array step: index*0x10000, index2*0x10 */ + __I uint32_t PX_SDID_JR; /**< Partition 0 SDID register..Partition 15 SDID register, array offset: 0x10A00, array step: index*0x10000, index2*0x10 */ __IO uint32_t PX_SMAPR_JR; /**< Secure Memory Access Permissions register, array offset: 0x10A04, array step: index*0x10000, index2*0x10 */ - __IO uint32_t PX_SMAG_JR[2]; /**< Secure Memory Access Group Registers, array offset: 0x10A08, array step: index*0x10000, index2*0x10, index3*0x4 */ + __IO uint32_t PX_SMAG2_JR; /**< Secure Memory Access Group Registers, array offset: 0x10A08, array step: index*0x10000, index2*0x10 */ + __IO uint32_t PX_SMAG1_JR; /**< Secure Memory Access Group Registers, array offset: 0x10A0C, array step: index*0x10000, index2*0x10 */ } PX_JR[16]; uint8_t RESERVED_14[228]; __O uint32_t SMCR_JR; /**< Secure Memory Command Register, array offset: 0x10BE4, array step: 0x10000 */ @@ -10820,6 +11765,7 @@ typedef struct { /*! @name MCFGR - Master Configuration Register */ /*! @{ */ + #define CAAM_MCFGR_NORMAL_BURST_MASK (0x1U) #define CAAM_MCFGR_NORMAL_BURST_SHIFT (0U) /*! NORMAL_BURST @@ -10827,18 +11773,23 @@ typedef struct { * 0b1..Aligned 64 byte burst size target */ #define CAAM_MCFGR_NORMAL_BURST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_NORMAL_BURST_SHIFT)) & CAAM_MCFGR_NORMAL_BURST_MASK) + #define CAAM_MCFGR_LARGE_BURST_MASK (0x4U) #define CAAM_MCFGR_LARGE_BURST_SHIFT (2U) #define CAAM_MCFGR_LARGE_BURST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_LARGE_BURST_SHIFT)) & CAAM_MCFGR_LARGE_BURST_MASK) + #define CAAM_MCFGR_AXIPIPE_MASK (0xF0U) #define CAAM_MCFGR_AXIPIPE_SHIFT (4U) #define CAAM_MCFGR_AXIPIPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_AXIPIPE_SHIFT)) & CAAM_MCFGR_AXIPIPE_MASK) + #define CAAM_MCFGR_AWCACHE_MASK (0xF00U) #define CAAM_MCFGR_AWCACHE_SHIFT (8U) #define CAAM_MCFGR_AWCACHE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_AWCACHE_SHIFT)) & CAAM_MCFGR_AWCACHE_MASK) + #define CAAM_MCFGR_ARCACHE_MASK (0xF000U) #define CAAM_MCFGR_ARCACHE_SHIFT (12U) #define CAAM_MCFGR_ARCACHE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_ARCACHE_SHIFT)) & CAAM_MCFGR_ARCACHE_MASK) + #define CAAM_MCFGR_PS_MASK (0x10000U) #define CAAM_MCFGR_PS_SHIFT (16U) /*! PS @@ -10846,21 +11797,27 @@ typedef struct { * 0b1..Pointers require two 32-bit words (pointers are 36-bit addresses). */ #define CAAM_MCFGR_PS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_PS_SHIFT)) & CAAM_MCFGR_PS_MASK) + #define CAAM_MCFGR_DWT_MASK (0x80000U) #define CAAM_MCFGR_DWT_SHIFT (19U) #define CAAM_MCFGR_DWT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_DWT_SHIFT)) & CAAM_MCFGR_DWT_MASK) + #define CAAM_MCFGR_WRHD_MASK (0x8000000U) #define CAAM_MCFGR_WRHD_SHIFT (27U) #define CAAM_MCFGR_WRHD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_WRHD_SHIFT)) & CAAM_MCFGR_WRHD_MASK) + #define CAAM_MCFGR_DMA_RST_MASK (0x10000000U) #define CAAM_MCFGR_DMA_RST_SHIFT (28U) #define CAAM_MCFGR_DMA_RST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_DMA_RST_SHIFT)) & CAAM_MCFGR_DMA_RST_MASK) + #define CAAM_MCFGR_WDF_MASK (0x20000000U) #define CAAM_MCFGR_WDF_SHIFT (29U) #define CAAM_MCFGR_WDF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_WDF_SHIFT)) & CAAM_MCFGR_WDF_MASK) + #define CAAM_MCFGR_WDE_MASK (0x40000000U) #define CAAM_MCFGR_WDE_SHIFT (30U) #define CAAM_MCFGR_WDE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_WDE_SHIFT)) & CAAM_MCFGR_WDE_MASK) + #define CAAM_MCFGR_SWRST_MASK (0x80000000U) #define CAAM_MCFGR_SWRST_SHIFT (31U) #define CAAM_MCFGR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_SWRST_SHIFT)) & CAAM_MCFGR_SWRST_MASK) @@ -10868,6 +11825,7 @@ typedef struct { /*! @name PAGE0_SDID - Page 0 SDID Register */ /*! @{ */ + #define CAAM_PAGE0_SDID_SDID_MASK (0x7FFFU) #define CAAM_PAGE0_SDID_SDID_SHIFT (0U) #define CAAM_PAGE0_SDID_SDID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PAGE0_SDID_SDID_SHIFT)) & CAAM_PAGE0_SDID_SDID_MASK) @@ -10875,6 +11833,7 @@ typedef struct { /*! @name SCFGR - Security Configuration Register */ /*! @{ */ + #define CAAM_SCFGR_PRIBLOB_MASK (0x3U) #define CAAM_SCFGR_PRIBLOB_SHIFT (0U) /*! PRIBLOB @@ -10884,6 +11843,7 @@ typedef struct { * 0b11..Normal operation blobs */ #define CAAM_SCFGR_PRIBLOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_PRIBLOB_SHIFT)) & CAAM_SCFGR_PRIBLOB_MASK) + #define CAAM_SCFGR_RNGSH0_MASK (0x200U) #define CAAM_SCFGR_RNGSH0_SHIFT (9U) /*! RNGSH0 @@ -10894,9 +11854,11 @@ typedef struct { * next power on reset. */ #define CAAM_SCFGR_RNGSH0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_RNGSH0_SHIFT)) & CAAM_SCFGR_RNGSH0_MASK) + #define CAAM_SCFGR_LCK_TRNG_MASK (0x800U) #define CAAM_SCFGR_LCK_TRNG_SHIFT (11U) #define CAAM_SCFGR_LCK_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_LCK_TRNG_SHIFT)) & CAAM_SCFGR_LCK_TRNG_MASK) + #define CAAM_SCFGR_VIRT_EN_MASK (0x8000U) #define CAAM_SCFGR_VIRT_EN_SHIFT (15U) /*! VIRT_EN @@ -10904,12 +11866,15 @@ typedef struct { * 0b1..Enable job ring virtualization */ #define CAAM_SCFGR_VIRT_EN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_VIRT_EN_SHIFT)) & CAAM_SCFGR_VIRT_EN_MASK) + #define CAAM_SCFGR_MPMRL_MASK (0x4000000U) #define CAAM_SCFGR_MPMRL_SHIFT (26U) #define CAAM_SCFGR_MPMRL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_MPMRL_SHIFT)) & CAAM_SCFGR_MPMRL_MASK) + #define CAAM_SCFGR_MPPKRC_MASK (0x8000000U) #define CAAM_SCFGR_MPPKRC_SHIFT (27U) #define CAAM_SCFGR_MPPKRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_MPPKRC_SHIFT)) & CAAM_SCFGR_MPPKRC_MASK) + #define CAAM_SCFGR_MPCURVE_MASK (0xF0000000U) #define CAAM_SCFGR_MPCURVE_SHIFT (28U) #define CAAM_SCFGR_MPCURVE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_MPCURVE_SHIFT)) & CAAM_SCFGR_MPCURVE_MASK) @@ -10917,30 +11882,39 @@ typedef struct { /*! @name JRDID_MS - Job Ring 0 DID Register - most significant half..Job Ring 3 DID Register - most significant half */ /*! @{ */ + #define CAAM_JRDID_MS_PRIM_DID_MASK (0xFU) #define CAAM_JRDID_MS_PRIM_DID_SHIFT (0U) #define CAAM_JRDID_MS_PRIM_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_PRIM_DID_SHIFT)) & CAAM_JRDID_MS_PRIM_DID_MASK) + #define CAAM_JRDID_MS_PRIM_TZ_MASK (0x10U) #define CAAM_JRDID_MS_PRIM_TZ_SHIFT (4U) #define CAAM_JRDID_MS_PRIM_TZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_PRIM_TZ_SHIFT)) & CAAM_JRDID_MS_PRIM_TZ_MASK) + #define CAAM_JRDID_MS_SDID_MS_MASK (0x7FE0U) #define CAAM_JRDID_MS_SDID_MS_SHIFT (5U) #define CAAM_JRDID_MS_SDID_MS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_SDID_MS_SHIFT)) & CAAM_JRDID_MS_SDID_MS_MASK) + #define CAAM_JRDID_MS_TZ_OWN_MASK (0x8000U) #define CAAM_JRDID_MS_TZ_OWN_SHIFT (15U) #define CAAM_JRDID_MS_TZ_OWN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_TZ_OWN_SHIFT)) & CAAM_JRDID_MS_TZ_OWN_MASK) + #define CAAM_JRDID_MS_AMTD_MASK (0x10000U) #define CAAM_JRDID_MS_AMTD_SHIFT (16U) #define CAAM_JRDID_MS_AMTD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_AMTD_SHIFT)) & CAAM_JRDID_MS_AMTD_MASK) + #define CAAM_JRDID_MS_LAMTD_MASK (0x20000U) #define CAAM_JRDID_MS_LAMTD_SHIFT (17U) #define CAAM_JRDID_MS_LAMTD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_LAMTD_SHIFT)) & CAAM_JRDID_MS_LAMTD_MASK) + #define CAAM_JRDID_MS_PRIM_ICID_MASK (0x3FF80000U) #define CAAM_JRDID_MS_PRIM_ICID_SHIFT (19U) #define CAAM_JRDID_MS_PRIM_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_PRIM_ICID_SHIFT)) & CAAM_JRDID_MS_PRIM_ICID_MASK) + #define CAAM_JRDID_MS_USE_OUT_MASK (0x40000000U) #define CAAM_JRDID_MS_USE_OUT_SHIFT (30U) #define CAAM_JRDID_MS_USE_OUT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_USE_OUT_SHIFT)) & CAAM_JRDID_MS_USE_OUT_MASK) + #define CAAM_JRDID_MS_LDID_MASK (0x80000000U) #define CAAM_JRDID_MS_LDID_SHIFT (31U) #define CAAM_JRDID_MS_LDID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_LDID_SHIFT)) & CAAM_JRDID_MS_LDID_MASK) @@ -10951,9 +11925,11 @@ typedef struct { /*! @name JRDID_LS - Job Ring 0 DID Register - least significant half..Job Ring 3 DID Register - least significant half */ /*! @{ */ + #define CAAM_JRDID_LS_OUT_DID_MASK (0xFU) #define CAAM_JRDID_LS_OUT_DID_SHIFT (0U) #define CAAM_JRDID_LS_OUT_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_LS_OUT_DID_SHIFT)) & CAAM_JRDID_LS_OUT_DID_MASK) + #define CAAM_JRDID_LS_OUT_ICID_MASK (0x3FF80000U) #define CAAM_JRDID_LS_OUT_ICID_SHIFT (19U) #define CAAM_JRDID_LS_OUT_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_LS_OUT_ICID_SHIFT)) & CAAM_JRDID_LS_OUT_ICID_MASK) @@ -10964,9 +11940,11 @@ typedef struct { /*! @name DEBUGCTL - Debug Control Register */ /*! @{ */ + #define CAAM_DEBUGCTL_STOP_MASK (0x10000U) #define CAAM_DEBUGCTL_STOP_SHIFT (16U) #define CAAM_DEBUGCTL_STOP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DEBUGCTL_STOP_SHIFT)) & CAAM_DEBUGCTL_STOP_MASK) + #define CAAM_DEBUGCTL_STOP_ACK_MASK (0x20000U) #define CAAM_DEBUGCTL_STOP_ACK_SHIFT (17U) #define CAAM_DEBUGCTL_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DEBUGCTL_STOP_ACK_SHIFT)) & CAAM_DEBUGCTL_STOP_ACK_MASK) @@ -10974,6 +11952,7 @@ typedef struct { /*! @name JRSTARTR - Job Ring Start Register */ /*! @{ */ + #define CAAM_JRSTARTR_Start_JR0_MASK (0x1U) #define CAAM_JRSTARTR_Start_JR0_SHIFT (0U) /*! Start_JR0 @@ -10987,6 +11966,7 @@ typedef struct { * ORJRR, ORSFR and JRSTAR registers for Job Ring 0 can be written only via a bus transaction that has ns=0. */ #define CAAM_JRSTARTR_Start_JR0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTARTR_Start_JR0_SHIFT)) & CAAM_JRSTARTR_Start_JR0_MASK) + #define CAAM_JRSTARTR_Start_JR1_MASK (0x2U) #define CAAM_JRSTARTR_Start_JR1_SHIFT (1U) /*! Start_JR1 @@ -11000,6 +11980,7 @@ typedef struct { * ORJRR, ORSFR and JRSTAR registers for Job Ring 1 can be written only via a bus transaction that has ns=0. */ #define CAAM_JRSTARTR_Start_JR1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTARTR_Start_JR1_SHIFT)) & CAAM_JRSTARTR_Start_JR1_MASK) + #define CAAM_JRSTARTR_Start_JR2_MASK (0x4U) #define CAAM_JRSTARTR_Start_JR2_SHIFT (2U) /*! Start_JR2 @@ -11013,6 +11994,7 @@ typedef struct { * ORJRR, ORSFR and JRSTAR registers for Job Ring 2 can be written only via a bus transaction that has ns=0. */ #define CAAM_JRSTARTR_Start_JR2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTARTR_Start_JR2_SHIFT)) & CAAM_JRSTARTR_Start_JR2_MASK) + #define CAAM_JRSTARTR_Start_JR3_MASK (0x8U) #define CAAM_JRSTARTR_Start_JR3_SHIFT (3U) /*! Start_JR3 @@ -11030,14 +12012,17 @@ typedef struct { /*! @name RTIC_OWN - RTIC OWN Register */ /*! @{ */ + #define CAAM_RTIC_OWN_ROWN_DID_MASK (0xFU) #define CAAM_RTIC_OWN_ROWN_DID_SHIFT (0U) /*! ROWN_DID - RTIC Owner's DID */ #define CAAM_RTIC_OWN_ROWN_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_OWN_ROWN_DID_SHIFT)) & CAAM_RTIC_OWN_ROWN_DID_MASK) + #define CAAM_RTIC_OWN_ROWN_TZ_MASK (0x10U) #define CAAM_RTIC_OWN_ROWN_TZ_SHIFT (4U) #define CAAM_RTIC_OWN_ROWN_TZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_OWN_ROWN_TZ_SHIFT)) & CAAM_RTIC_OWN_ROWN_TZ_MASK) + #define CAAM_RTIC_OWN_LCK_MASK (0x80000000U) #define CAAM_RTIC_OWN_LCK_SHIFT (31U) #define CAAM_RTIC_OWN_LCK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_OWN_LCK_SHIFT)) & CAAM_RTIC_OWN_LCK_MASK) @@ -11045,12 +12030,15 @@ typedef struct { /*! @name RTIC_DID - RTIC DID Register for Block A..RTIC DID Register for Block D */ /*! @{ */ + #define CAAM_RTIC_DID_RTIC_DID_MASK (0xFU) #define CAAM_RTIC_DID_RTIC_DID_SHIFT (0U) #define CAAM_RTIC_DID_RTIC_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_DID_RTIC_DID_SHIFT)) & CAAM_RTIC_DID_RTIC_DID_MASK) + #define CAAM_RTIC_DID_RTIC_TZ_MASK (0x10U) #define CAAM_RTIC_DID_RTIC_TZ_SHIFT (4U) #define CAAM_RTIC_DID_RTIC_TZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_DID_RTIC_TZ_SHIFT)) & CAAM_RTIC_DID_RTIC_TZ_MASK) + #define CAAM_RTIC_DID_RTIC_ICID_MASK (0x3FF80000U) #define CAAM_RTIC_DID_RTIC_ICID_SHIFT (19U) #define CAAM_RTIC_DID_RTIC_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_DID_RTIC_ICID_SHIFT)) & CAAM_RTIC_DID_RTIC_ICID_MASK) @@ -11061,9 +12049,11 @@ typedef struct { /*! @name DECORSR - DECO Request Source Register */ /*! @{ */ + #define CAAM_DECORSR_JR_MASK (0x3U) #define CAAM_DECORSR_JR_SHIFT (0U) #define CAAM_DECORSR_JR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECORSR_JR_SHIFT)) & CAAM_DECORSR_JR_MASK) + #define CAAM_DECORSR_VALID_MASK (0x80000000U) #define CAAM_DECORSR_VALID_SHIFT (31U) #define CAAM_DECORSR_VALID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECORSR_VALID_SHIFT)) & CAAM_DECORSR_VALID_MASK) @@ -11071,9 +12061,11 @@ typedef struct { /*! @name DECORR - DECO Request Register */ /*! @{ */ + #define CAAM_DECORR_RQD0_MASK (0x1U) #define CAAM_DECORR_RQD0_SHIFT (0U) #define CAAM_DECORR_RQD0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECORR_RQD0_SHIFT)) & CAAM_DECORR_RQD0_MASK) + #define CAAM_DECORR_DEN0_MASK (0x10000U) #define CAAM_DECORR_DEN0_SHIFT (16U) #define CAAM_DECORR_DEN0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECORR_DEN0_SHIFT)) & CAAM_DECORR_DEN0_MASK) @@ -11081,14 +12073,17 @@ typedef struct { /*! @name DECODID_MS - DECO0 DID Register - most significant half */ /*! @{ */ + #define CAAM_DECODID_MS_DPRIM_DID_MASK (0xFU) #define CAAM_DECODID_MS_DPRIM_DID_SHIFT (0U) /*! DPRIM_DID - DECO Owner */ #define CAAM_DECODID_MS_DPRIM_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_MS_DPRIM_DID_SHIFT)) & CAAM_DECODID_MS_DPRIM_DID_MASK) + #define CAAM_DECODID_MS_D_NS_MASK (0x10U) #define CAAM_DECODID_MS_D_NS_SHIFT (4U) #define CAAM_DECODID_MS_D_NS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_MS_D_NS_SHIFT)) & CAAM_DECODID_MS_D_NS_MASK) + #define CAAM_DECODID_MS_LCK_MASK (0x80000000U) #define CAAM_DECODID_MS_LCK_SHIFT (31U) #define CAAM_DECODID_MS_LCK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_MS_LCK_SHIFT)) & CAAM_DECODID_MS_LCK_MASK) @@ -11099,15 +12094,19 @@ typedef struct { /*! @name DECODID_LS - DECO0 DID Register - least significant half */ /*! @{ */ + #define CAAM_DECODID_LS_DSEQ_DID_MASK (0xFU) #define CAAM_DECODID_LS_DSEQ_DID_SHIFT (0U) #define CAAM_DECODID_LS_DSEQ_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_LS_DSEQ_DID_SHIFT)) & CAAM_DECODID_LS_DSEQ_DID_MASK) + #define CAAM_DECODID_LS_DSEQ_NS_MASK (0x10U) #define CAAM_DECODID_LS_DSEQ_NS_SHIFT (4U) #define CAAM_DECODID_LS_DSEQ_NS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_LS_DSEQ_NS_SHIFT)) & CAAM_DECODID_LS_DSEQ_NS_MASK) + #define CAAM_DECODID_LS_DNSEQ_DID_MASK (0xF0000U) #define CAAM_DECODID_LS_DNSEQ_DID_SHIFT (16U) #define CAAM_DECODID_LS_DNSEQ_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_LS_DNSEQ_DID_SHIFT)) & CAAM_DECODID_LS_DNSEQ_DID_MASK) + #define CAAM_DECODID_LS_DNONSEQ_NS_MASK (0x100000U) #define CAAM_DECODID_LS_DNONSEQ_NS_SHIFT (20U) #define CAAM_DECODID_LS_DNONSEQ_NS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_LS_DNONSEQ_NS_SHIFT)) & CAAM_DECODID_LS_DNONSEQ_NS_MASK) @@ -11118,6 +12117,7 @@ typedef struct { /*! @name DAR - DECO Availability Register */ /*! @{ */ + #define CAAM_DAR_NYA0_MASK (0x1U) #define CAAM_DAR_NYA0_SHIFT (0U) #define CAAM_DAR_NYA0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DAR_NYA0_SHIFT)) & CAAM_DAR_NYA0_MASK) @@ -11125,6 +12125,7 @@ typedef struct { /*! @name DRR - DECO Reset Register */ /*! @{ */ + #define CAAM_DRR_RST0_MASK (0x1U) #define CAAM_DRR_RST0_SHIFT (0U) #define CAAM_DRR_RST0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DRR_RST0_SHIFT)) & CAAM_DRR_RST0_MASK) @@ -11132,6 +12133,7 @@ typedef struct { /*! @name JRSMVBAR - Job Ring 0 Secure Memory Virtual Base Address Register..Job Ring 3 Secure Memory Virtual Base Address Register */ /*! @{ */ + #define CAAM_JRSMVBAR_SMVBA_MASK (0xFFFFFFFFU) #define CAAM_JRSMVBAR_SMVBA_SHIFT (0U) #define CAAM_JRSMVBAR_SMVBA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRSMVBAR_SMVBA_SHIFT)) & CAAM_JRSMVBAR_SMVBA_MASK) @@ -11142,6 +12144,7 @@ typedef struct { /*! @name PBSL - Peak Bandwidth Smoothing Limit Register */ /*! @{ */ + #define CAAM_PBSL_PBSL_MASK (0x7FU) #define CAAM_PBSL_PBSL_SHIFT (0U) #define CAAM_PBSL_PBSL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PBSL_PBSL_SHIFT)) & CAAM_PBSL_PBSL_MASK) @@ -11149,15 +12152,19 @@ typedef struct { /*! @name DMA_AIDL_MAP_MS - DMA0_AIDL_MAP_MS */ /*! @{ */ + #define CAAM_DMA_AIDL_MAP_MS_AID4_BID_MASK (0xFFU) #define CAAM_DMA_AIDL_MAP_MS_AID4_BID_SHIFT (0U) #define CAAM_DMA_AIDL_MAP_MS_AID4_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_MS_AID4_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_MS_AID4_BID_MASK) + #define CAAM_DMA_AIDL_MAP_MS_AID5_BID_MASK (0xFF00U) #define CAAM_DMA_AIDL_MAP_MS_AID5_BID_SHIFT (8U) #define CAAM_DMA_AIDL_MAP_MS_AID5_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_MS_AID5_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_MS_AID5_BID_MASK) + #define CAAM_DMA_AIDL_MAP_MS_AID6_BID_MASK (0xFF0000U) #define CAAM_DMA_AIDL_MAP_MS_AID6_BID_SHIFT (16U) #define CAAM_DMA_AIDL_MAP_MS_AID6_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_MS_AID6_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_MS_AID6_BID_MASK) + #define CAAM_DMA_AIDL_MAP_MS_AID7_BID_MASK (0xFF000000U) #define CAAM_DMA_AIDL_MAP_MS_AID7_BID_SHIFT (24U) #define CAAM_DMA_AIDL_MAP_MS_AID7_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_MS_AID7_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_MS_AID7_BID_MASK) @@ -11168,15 +12175,19 @@ typedef struct { /*! @name DMA_AIDL_MAP_LS - DMA0_AIDL_MAP_LS */ /*! @{ */ + #define CAAM_DMA_AIDL_MAP_LS_AID0_BID_MASK (0xFFU) #define CAAM_DMA_AIDL_MAP_LS_AID0_BID_SHIFT (0U) #define CAAM_DMA_AIDL_MAP_LS_AID0_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_LS_AID0_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_LS_AID0_BID_MASK) + #define CAAM_DMA_AIDL_MAP_LS_AID1_BID_MASK (0xFF00U) #define CAAM_DMA_AIDL_MAP_LS_AID1_BID_SHIFT (8U) #define CAAM_DMA_AIDL_MAP_LS_AID1_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_LS_AID1_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_LS_AID1_BID_MASK) + #define CAAM_DMA_AIDL_MAP_LS_AID2_BID_MASK (0xFF0000U) #define CAAM_DMA_AIDL_MAP_LS_AID2_BID_SHIFT (16U) #define CAAM_DMA_AIDL_MAP_LS_AID2_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_LS_AID2_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_LS_AID2_BID_MASK) + #define CAAM_DMA_AIDL_MAP_LS_AID3_BID_MASK (0xFF000000U) #define CAAM_DMA_AIDL_MAP_LS_AID3_BID_SHIFT (24U) #define CAAM_DMA_AIDL_MAP_LS_AID3_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_LS_AID3_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_LS_AID3_BID_MASK) @@ -11187,15 +12198,19 @@ typedef struct { /*! @name DMA_AIDM_MAP_MS - DMA0_AIDM_MAP_MS */ /*! @{ */ + #define CAAM_DMA_AIDM_MAP_MS_AID12_BID_MASK (0xFFU) #define CAAM_DMA_AIDM_MAP_MS_AID12_BID_SHIFT (0U) #define CAAM_DMA_AIDM_MAP_MS_AID12_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_MS_AID12_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_MS_AID12_BID_MASK) + #define CAAM_DMA_AIDM_MAP_MS_AID13_BID_MASK (0xFF00U) #define CAAM_DMA_AIDM_MAP_MS_AID13_BID_SHIFT (8U) #define CAAM_DMA_AIDM_MAP_MS_AID13_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_MS_AID13_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_MS_AID13_BID_MASK) + #define CAAM_DMA_AIDM_MAP_MS_AID14_BID_MASK (0xFF0000U) #define CAAM_DMA_AIDM_MAP_MS_AID14_BID_SHIFT (16U) #define CAAM_DMA_AIDM_MAP_MS_AID14_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_MS_AID14_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_MS_AID14_BID_MASK) + #define CAAM_DMA_AIDM_MAP_MS_AID15_BID_MASK (0xFF000000U) #define CAAM_DMA_AIDM_MAP_MS_AID15_BID_SHIFT (24U) #define CAAM_DMA_AIDM_MAP_MS_AID15_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_MS_AID15_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_MS_AID15_BID_MASK) @@ -11206,15 +12221,19 @@ typedef struct { /*! @name DMA_AIDM_MAP_LS - DMA0_AIDM_MAP_LS */ /*! @{ */ + #define CAAM_DMA_AIDM_MAP_LS_AID8_BID_MASK (0xFFU) #define CAAM_DMA_AIDM_MAP_LS_AID8_BID_SHIFT (0U) #define CAAM_DMA_AIDM_MAP_LS_AID8_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_LS_AID8_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_LS_AID8_BID_MASK) + #define CAAM_DMA_AIDM_MAP_LS_AID9_BID_MASK (0xFF00U) #define CAAM_DMA_AIDM_MAP_LS_AID9_BID_SHIFT (8U) #define CAAM_DMA_AIDM_MAP_LS_AID9_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_LS_AID9_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_LS_AID9_BID_MASK) + #define CAAM_DMA_AIDM_MAP_LS_AID10_BID_MASK (0xFF0000U) #define CAAM_DMA_AIDM_MAP_LS_AID10_BID_SHIFT (16U) #define CAAM_DMA_AIDM_MAP_LS_AID10_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_LS_AID10_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_LS_AID10_BID_MASK) + #define CAAM_DMA_AIDM_MAP_LS_AID11_BID_MASK (0xFF000000U) #define CAAM_DMA_AIDM_MAP_LS_AID11_BID_SHIFT (24U) #define CAAM_DMA_AIDM_MAP_LS_AID11_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_LS_AID11_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_LS_AID11_BID_MASK) @@ -11225,51 +12244,67 @@ typedef struct { /*! @name DMA0_AID_ENB - DMA0 AXI ID Enable Register */ /*! @{ */ + #define CAAM_DMA0_AID_ENB_AID0E_MASK (0x1U) #define CAAM_DMA0_AID_ENB_AID0E_SHIFT (0U) #define CAAM_DMA0_AID_ENB_AID0E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID0E_SHIFT)) & CAAM_DMA0_AID_ENB_AID0E_MASK) + #define CAAM_DMA0_AID_ENB_AID1E_MASK (0x2U) #define CAAM_DMA0_AID_ENB_AID1E_SHIFT (1U) #define CAAM_DMA0_AID_ENB_AID1E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID1E_SHIFT)) & CAAM_DMA0_AID_ENB_AID1E_MASK) + #define CAAM_DMA0_AID_ENB_AID2E_MASK (0x4U) #define CAAM_DMA0_AID_ENB_AID2E_SHIFT (2U) #define CAAM_DMA0_AID_ENB_AID2E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID2E_SHIFT)) & CAAM_DMA0_AID_ENB_AID2E_MASK) + #define CAAM_DMA0_AID_ENB_AID3E_MASK (0x8U) #define CAAM_DMA0_AID_ENB_AID3E_SHIFT (3U) #define CAAM_DMA0_AID_ENB_AID3E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID3E_SHIFT)) & CAAM_DMA0_AID_ENB_AID3E_MASK) + #define CAAM_DMA0_AID_ENB_AID4E_MASK (0x10U) #define CAAM_DMA0_AID_ENB_AID4E_SHIFT (4U) #define CAAM_DMA0_AID_ENB_AID4E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID4E_SHIFT)) & CAAM_DMA0_AID_ENB_AID4E_MASK) + #define CAAM_DMA0_AID_ENB_AID5E_MASK (0x20U) #define CAAM_DMA0_AID_ENB_AID5E_SHIFT (5U) #define CAAM_DMA0_AID_ENB_AID5E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID5E_SHIFT)) & CAAM_DMA0_AID_ENB_AID5E_MASK) + #define CAAM_DMA0_AID_ENB_AID6E_MASK (0x40U) #define CAAM_DMA0_AID_ENB_AID6E_SHIFT (6U) #define CAAM_DMA0_AID_ENB_AID6E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID6E_SHIFT)) & CAAM_DMA0_AID_ENB_AID6E_MASK) + #define CAAM_DMA0_AID_ENB_AID7E_MASK (0x80U) #define CAAM_DMA0_AID_ENB_AID7E_SHIFT (7U) #define CAAM_DMA0_AID_ENB_AID7E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID7E_SHIFT)) & CAAM_DMA0_AID_ENB_AID7E_MASK) + #define CAAM_DMA0_AID_ENB_AID8E_MASK (0x100U) #define CAAM_DMA0_AID_ENB_AID8E_SHIFT (8U) #define CAAM_DMA0_AID_ENB_AID8E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID8E_SHIFT)) & CAAM_DMA0_AID_ENB_AID8E_MASK) + #define CAAM_DMA0_AID_ENB_AID9E_MASK (0x200U) #define CAAM_DMA0_AID_ENB_AID9E_SHIFT (9U) #define CAAM_DMA0_AID_ENB_AID9E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID9E_SHIFT)) & CAAM_DMA0_AID_ENB_AID9E_MASK) + #define CAAM_DMA0_AID_ENB_AID10E_MASK (0x400U) #define CAAM_DMA0_AID_ENB_AID10E_SHIFT (10U) #define CAAM_DMA0_AID_ENB_AID10E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID10E_SHIFT)) & CAAM_DMA0_AID_ENB_AID10E_MASK) + #define CAAM_DMA0_AID_ENB_AID11E_MASK (0x800U) #define CAAM_DMA0_AID_ENB_AID11E_SHIFT (11U) #define CAAM_DMA0_AID_ENB_AID11E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID11E_SHIFT)) & CAAM_DMA0_AID_ENB_AID11E_MASK) + #define CAAM_DMA0_AID_ENB_AID12E_MASK (0x1000U) #define CAAM_DMA0_AID_ENB_AID12E_SHIFT (12U) #define CAAM_DMA0_AID_ENB_AID12E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID12E_SHIFT)) & CAAM_DMA0_AID_ENB_AID12E_MASK) + #define CAAM_DMA0_AID_ENB_AID13E_MASK (0x2000U) #define CAAM_DMA0_AID_ENB_AID13E_SHIFT (13U) #define CAAM_DMA0_AID_ENB_AID13E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID13E_SHIFT)) & CAAM_DMA0_AID_ENB_AID13E_MASK) + #define CAAM_DMA0_AID_ENB_AID14E_MASK (0x4000U) #define CAAM_DMA0_AID_ENB_AID14E_SHIFT (14U) #define CAAM_DMA0_AID_ENB_AID14E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID14E_SHIFT)) & CAAM_DMA0_AID_ENB_AID14E_MASK) + #define CAAM_DMA0_AID_ENB_AID15E_MASK (0x8000U) #define CAAM_DMA0_AID_ENB_AID15E_SHIFT (15U) #define CAAM_DMA0_AID_ENB_AID15E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID15E_SHIFT)) & CAAM_DMA0_AID_ENB_AID15E_MASK) @@ -11277,24 +12312,31 @@ typedef struct { /*! @name DMA0_ARD_TC - DMA0 AXI Read Timing Check Register */ /*! @{ */ + #define CAAM_DMA0_ARD_TC_ARSC_MASK (0xFFFFFU) #define CAAM_DMA0_ARD_TC_ARSC_SHIFT (0U) #define CAAM_DMA0_ARD_TC_ARSC(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARSC_SHIFT)) & CAAM_DMA0_ARD_TC_ARSC_MASK) + #define CAAM_DMA0_ARD_TC_ARLC_MASK (0xFFFFF000000U) #define CAAM_DMA0_ARD_TC_ARLC_SHIFT (24U) #define CAAM_DMA0_ARD_TC_ARLC(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARLC_SHIFT)) & CAAM_DMA0_ARD_TC_ARLC_MASK) + #define CAAM_DMA0_ARD_TC_ARL_MASK (0xFFF000000000000U) #define CAAM_DMA0_ARD_TC_ARL_SHIFT (48U) #define CAAM_DMA0_ARD_TC_ARL(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARL_SHIFT)) & CAAM_DMA0_ARD_TC_ARL_MASK) + #define CAAM_DMA0_ARD_TC_ARTL_MASK (0x1000000000000000U) #define CAAM_DMA0_ARD_TC_ARTL_SHIFT (60U) #define CAAM_DMA0_ARD_TC_ARTL(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARTL_SHIFT)) & CAAM_DMA0_ARD_TC_ARTL_MASK) + #define CAAM_DMA0_ARD_TC_ARTT_MASK (0x2000000000000000U) #define CAAM_DMA0_ARD_TC_ARTT_SHIFT (61U) #define CAAM_DMA0_ARD_TC_ARTT(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARTT_SHIFT)) & CAAM_DMA0_ARD_TC_ARTT_MASK) + #define CAAM_DMA0_ARD_TC_ARCT_MASK (0x4000000000000000U) #define CAAM_DMA0_ARD_TC_ARCT_SHIFT (62U) #define CAAM_DMA0_ARD_TC_ARCT(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARCT_SHIFT)) & CAAM_DMA0_ARD_TC_ARCT_MASK) + #define CAAM_DMA0_ARD_TC_ARTCE_MASK (0x8000000000000000U) #define CAAM_DMA0_ARD_TC_ARTCE_SHIFT (63U) #define CAAM_DMA0_ARD_TC_ARTCE(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARTCE_SHIFT)) & CAAM_DMA0_ARD_TC_ARTCE_MASK) @@ -11302,6 +12344,7 @@ typedef struct { /*! @name DMA0_ARD_LAT - DMA0 Read Timing Check Latency Register */ /*! @{ */ + #define CAAM_DMA0_ARD_LAT_SARL_MASK (0xFFFFFFFFU) #define CAAM_DMA0_ARD_LAT_SARL_SHIFT (0U) #define CAAM_DMA0_ARD_LAT_SARL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_ARD_LAT_SARL_SHIFT)) & CAAM_DMA0_ARD_LAT_SARL_MASK) @@ -11309,21 +12352,27 @@ typedef struct { /*! @name DMA0_AWR_TC - DMA0 AXI Write Timing Check Register */ /*! @{ */ + #define CAAM_DMA0_AWR_TC_AWSC_MASK (0xFFFFFU) #define CAAM_DMA0_AWR_TC_AWSC_SHIFT (0U) #define CAAM_DMA0_AWR_TC_AWSC(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWSC_SHIFT)) & CAAM_DMA0_AWR_TC_AWSC_MASK) + #define CAAM_DMA0_AWR_TC_AWLC_MASK (0xFFFFF000000U) #define CAAM_DMA0_AWR_TC_AWLC_SHIFT (24U) #define CAAM_DMA0_AWR_TC_AWLC(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWLC_SHIFT)) & CAAM_DMA0_AWR_TC_AWLC_MASK) + #define CAAM_DMA0_AWR_TC_AWL_MASK (0xFFF000000000000U) #define CAAM_DMA0_AWR_TC_AWL_SHIFT (48U) #define CAAM_DMA0_AWR_TC_AWL(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWL_SHIFT)) & CAAM_DMA0_AWR_TC_AWL_MASK) + #define CAAM_DMA0_AWR_TC_AWTT_MASK (0x2000000000000000U) #define CAAM_DMA0_AWR_TC_AWTT_SHIFT (61U) #define CAAM_DMA0_AWR_TC_AWTT(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWTT_SHIFT)) & CAAM_DMA0_AWR_TC_AWTT_MASK) + #define CAAM_DMA0_AWR_TC_AWCT_MASK (0x4000000000000000U) #define CAAM_DMA0_AWR_TC_AWCT_SHIFT (62U) #define CAAM_DMA0_AWR_TC_AWCT(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWCT_SHIFT)) & CAAM_DMA0_AWR_TC_AWCT_MASK) + #define CAAM_DMA0_AWR_TC_AWTCE_MASK (0x8000000000000000U) #define CAAM_DMA0_AWR_TC_AWTCE_SHIFT (63U) #define CAAM_DMA0_AWR_TC_AWTCE(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWTCE_SHIFT)) & CAAM_DMA0_AWR_TC_AWTCE_MASK) @@ -11331,6 +12380,7 @@ typedef struct { /*! @name DMA0_AWR_LAT - DMA0 Write Timing Check Latency Register */ /*! @{ */ + #define CAAM_DMA0_AWR_LAT_SAWL_MASK (0xFFFFFFFFU) #define CAAM_DMA0_AWR_LAT_SAWL_SHIFT (0U) #define CAAM_DMA0_AWR_LAT_SAWL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AWR_LAT_SAWL_SHIFT)) & CAAM_DMA0_AWR_LAT_SAWL_MASK) @@ -11338,6 +12388,7 @@ typedef struct { /*! @name MPPKR - Manufacturing Protection Private Key Register */ /*! @{ */ + #define CAAM_MPPKR_MPPrivK_MASK (0xFFU) #define CAAM_MPPKR_MPPrivK_SHIFT (0U) #define CAAM_MPPKR_MPPrivK(x) (((uint8_t)(((uint8_t)(x)) << CAAM_MPPKR_MPPrivK_SHIFT)) & CAAM_MPPKR_MPPrivK_MASK) @@ -11348,6 +12399,7 @@ typedef struct { /*! @name MPMR - Manufacturing Protection Message Register */ /*! @{ */ + #define CAAM_MPMR_MPMSG_MASK (0xFFU) #define CAAM_MPMR_MPMSG_SHIFT (0U) #define CAAM_MPMR_MPMSG(x) (((uint8_t)(((uint8_t)(x)) << CAAM_MPMR_MPMSG_SHIFT)) & CAAM_MPMR_MPMSG_MASK) @@ -11358,6 +12410,7 @@ typedef struct { /*! @name MPTESTR - Manufacturing Protection Test Register */ /*! @{ */ + #define CAAM_MPTESTR_TEST_VALUE_MASK (0xFFU) #define CAAM_MPTESTR_TEST_VALUE_SHIFT (0U) #define CAAM_MPTESTR_TEST_VALUE(x) (((uint8_t)(((uint8_t)(x)) << CAAM_MPTESTR_TEST_VALUE_SHIFT)) & CAAM_MPTESTR_TEST_VALUE_MASK) @@ -11368,6 +12421,7 @@ typedef struct { /*! @name MPECC - Manufacturing Protection ECC Register */ /*! @{ */ + #define CAAM_MPECC_MP_SYNDROME_MASK (0x1FF0000U) #define CAAM_MPECC_MP_SYNDROME_SHIFT (16U) /*! MP_SYNDROME @@ -11375,6 +12429,7 @@ typedef struct { * 0b000000001-0b111111111..The MP Key in the SFP fails the ECC check, and this is the ECC failure syndrome. */ #define CAAM_MPECC_MP_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MPECC_MP_SYNDROME_SHIFT)) & CAAM_MPECC_MP_SYNDROME_MASK) + #define CAAM_MPECC_MP_ZERO_MASK (0x8000000U) #define CAAM_MPECC_MP_ZERO_SHIFT (27U) /*! MP_ZERO @@ -11386,6 +12441,7 @@ typedef struct { /*! @name JDKEKR - Job Descriptor Key Encryption Key Register */ /*! @{ */ + #define CAAM_JDKEKR_JDKEK_MASK (0xFFFFFFFFU) #define CAAM_JDKEKR_JDKEK_SHIFT (0U) #define CAAM_JDKEKR_JDKEK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JDKEKR_JDKEK_SHIFT)) & CAAM_JDKEKR_JDKEK_MASK) @@ -11396,6 +12452,7 @@ typedef struct { /*! @name TDKEKR - Trusted Descriptor Key Encryption Key Register */ /*! @{ */ + #define CAAM_TDKEKR_TDKEK_MASK (0xFFFFFFFFU) #define CAAM_TDKEKR_TDKEK_SHIFT (0U) #define CAAM_TDKEKR_TDKEK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_TDKEKR_TDKEK_SHIFT)) & CAAM_TDKEKR_TDKEK_MASK) @@ -11406,6 +12463,7 @@ typedef struct { /*! @name TDSKR - Trusted Descriptor Signing Key Register */ /*! @{ */ + #define CAAM_TDSKR_TDSK_MASK (0xFFFFFFFFU) #define CAAM_TDSKR_TDSK_SHIFT (0U) #define CAAM_TDSKR_TDSK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_TDSKR_TDSK_SHIFT)) & CAAM_TDSKR_TDSK_MASK) @@ -11416,9 +12474,11 @@ typedef struct { /*! @name SKNR - Secure Key Nonce Register */ /*! @{ */ + #define CAAM_SKNR_SK_NONCE_LS_MASK (0xFFFFFFFFU) #define CAAM_SKNR_SK_NONCE_LS_SHIFT (0U) #define CAAM_SKNR_SK_NONCE_LS(x) (((uint64_t)(((uint64_t)(x)) << CAAM_SKNR_SK_NONCE_LS_SHIFT)) & CAAM_SKNR_SK_NONCE_LS_MASK) + #define CAAM_SKNR_SK_NONCE_MS_MASK (0x7FFF00000000U) #define CAAM_SKNR_SK_NONCE_MS_SHIFT (32U) #define CAAM_SKNR_SK_NONCE_MS(x) (((uint64_t)(((uint64_t)(x)) << CAAM_SKNR_SK_NONCE_MS_SHIFT)) & CAAM_SKNR_SK_NONCE_MS_MASK) @@ -11426,12 +12486,15 @@ typedef struct { /*! @name DMA_STA - DMA Status Register */ /*! @{ */ + #define CAAM_DMA_STA_DMA0_ETIF_MASK (0x1FU) #define CAAM_DMA_STA_DMA0_ETIF_SHIFT (0U) #define CAAM_DMA_STA_DMA0_ETIF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_STA_DMA0_ETIF_SHIFT)) & CAAM_DMA_STA_DMA0_ETIF_MASK) + #define CAAM_DMA_STA_DMA0_ITIF_MASK (0x20U) #define CAAM_DMA_STA_DMA0_ITIF_SHIFT (5U) #define CAAM_DMA_STA_DMA0_ITIF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_STA_DMA0_ITIF_SHIFT)) & CAAM_DMA_STA_DMA0_ITIF_MASK) + #define CAAM_DMA_STA_DMA0_IDLE_MASK (0x80U) #define CAAM_DMA_STA_DMA0_IDLE_SHIFT (7U) #define CAAM_DMA_STA_DMA0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_STA_DMA0_IDLE_SHIFT)) & CAAM_DMA_STA_DMA0_IDLE_MASK) @@ -11439,15 +12502,19 @@ typedef struct { /*! @name DMA_X_AID_7_4_MAP - DMA_X_AID_7_4_MAP */ /*! @{ */ + #define CAAM_DMA_X_AID_7_4_MAP_AID4_BID_MASK (0xFFU) #define CAAM_DMA_X_AID_7_4_MAP_AID4_BID_SHIFT (0U) #define CAAM_DMA_X_AID_7_4_MAP_AID4_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_7_4_MAP_AID4_BID_SHIFT)) & CAAM_DMA_X_AID_7_4_MAP_AID4_BID_MASK) + #define CAAM_DMA_X_AID_7_4_MAP_AID5_BID_MASK (0xFF00U) #define CAAM_DMA_X_AID_7_4_MAP_AID5_BID_SHIFT (8U) #define CAAM_DMA_X_AID_7_4_MAP_AID5_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_7_4_MAP_AID5_BID_SHIFT)) & CAAM_DMA_X_AID_7_4_MAP_AID5_BID_MASK) + #define CAAM_DMA_X_AID_7_4_MAP_AID6_BID_MASK (0xFF0000U) #define CAAM_DMA_X_AID_7_4_MAP_AID6_BID_SHIFT (16U) #define CAAM_DMA_X_AID_7_4_MAP_AID6_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_7_4_MAP_AID6_BID_SHIFT)) & CAAM_DMA_X_AID_7_4_MAP_AID6_BID_MASK) + #define CAAM_DMA_X_AID_7_4_MAP_AID7_BID_MASK (0xFF000000U) #define CAAM_DMA_X_AID_7_4_MAP_AID7_BID_SHIFT (24U) #define CAAM_DMA_X_AID_7_4_MAP_AID7_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_7_4_MAP_AID7_BID_SHIFT)) & CAAM_DMA_X_AID_7_4_MAP_AID7_BID_MASK) @@ -11455,15 +12522,19 @@ typedef struct { /*! @name DMA_X_AID_3_0_MAP - DMA_X_AID_3_0_MAP */ /*! @{ */ + #define CAAM_DMA_X_AID_3_0_MAP_AID0_BID_MASK (0xFFU) #define CAAM_DMA_X_AID_3_0_MAP_AID0_BID_SHIFT (0U) #define CAAM_DMA_X_AID_3_0_MAP_AID0_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_3_0_MAP_AID0_BID_SHIFT)) & CAAM_DMA_X_AID_3_0_MAP_AID0_BID_MASK) + #define CAAM_DMA_X_AID_3_0_MAP_AID1_BID_MASK (0xFF00U) #define CAAM_DMA_X_AID_3_0_MAP_AID1_BID_SHIFT (8U) #define CAAM_DMA_X_AID_3_0_MAP_AID1_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_3_0_MAP_AID1_BID_SHIFT)) & CAAM_DMA_X_AID_3_0_MAP_AID1_BID_MASK) + #define CAAM_DMA_X_AID_3_0_MAP_AID2_BID_MASK (0xFF0000U) #define CAAM_DMA_X_AID_3_0_MAP_AID2_BID_SHIFT (16U) #define CAAM_DMA_X_AID_3_0_MAP_AID2_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_3_0_MAP_AID2_BID_SHIFT)) & CAAM_DMA_X_AID_3_0_MAP_AID2_BID_MASK) + #define CAAM_DMA_X_AID_3_0_MAP_AID3_BID_MASK (0xFF000000U) #define CAAM_DMA_X_AID_3_0_MAP_AID3_BID_SHIFT (24U) #define CAAM_DMA_X_AID_3_0_MAP_AID3_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_3_0_MAP_AID3_BID_SHIFT)) & CAAM_DMA_X_AID_3_0_MAP_AID3_BID_MASK) @@ -11471,15 +12542,19 @@ typedef struct { /*! @name DMA_X_AID_15_12_MAP - DMA_X_AID_15_12_MAP */ /*! @{ */ + #define CAAM_DMA_X_AID_15_12_MAP_AID12_BID_MASK (0xFFU) #define CAAM_DMA_X_AID_15_12_MAP_AID12_BID_SHIFT (0U) #define CAAM_DMA_X_AID_15_12_MAP_AID12_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_12_MAP_AID12_BID_SHIFT)) & CAAM_DMA_X_AID_15_12_MAP_AID12_BID_MASK) + #define CAAM_DMA_X_AID_15_12_MAP_AID13_BID_MASK (0xFF00U) #define CAAM_DMA_X_AID_15_12_MAP_AID13_BID_SHIFT (8U) #define CAAM_DMA_X_AID_15_12_MAP_AID13_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_12_MAP_AID13_BID_SHIFT)) & CAAM_DMA_X_AID_15_12_MAP_AID13_BID_MASK) + #define CAAM_DMA_X_AID_15_12_MAP_AID14_BID_MASK (0xFF0000U) #define CAAM_DMA_X_AID_15_12_MAP_AID14_BID_SHIFT (16U) #define CAAM_DMA_X_AID_15_12_MAP_AID14_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_12_MAP_AID14_BID_SHIFT)) & CAAM_DMA_X_AID_15_12_MAP_AID14_BID_MASK) + #define CAAM_DMA_X_AID_15_12_MAP_AID15_BID_MASK (0xFF000000U) #define CAAM_DMA_X_AID_15_12_MAP_AID15_BID_SHIFT (24U) #define CAAM_DMA_X_AID_15_12_MAP_AID15_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_12_MAP_AID15_BID_SHIFT)) & CAAM_DMA_X_AID_15_12_MAP_AID15_BID_MASK) @@ -11487,15 +12562,19 @@ typedef struct { /*! @name DMA_X_AID_11_8_MAP - DMA_X_AID_11_8_MAP */ /*! @{ */ + #define CAAM_DMA_X_AID_11_8_MAP_AID8_BID_MASK (0xFFU) #define CAAM_DMA_X_AID_11_8_MAP_AID8_BID_SHIFT (0U) #define CAAM_DMA_X_AID_11_8_MAP_AID8_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_11_8_MAP_AID8_BID_SHIFT)) & CAAM_DMA_X_AID_11_8_MAP_AID8_BID_MASK) + #define CAAM_DMA_X_AID_11_8_MAP_AID9_BID_MASK (0xFF00U) #define CAAM_DMA_X_AID_11_8_MAP_AID9_BID_SHIFT (8U) #define CAAM_DMA_X_AID_11_8_MAP_AID9_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_11_8_MAP_AID9_BID_SHIFT)) & CAAM_DMA_X_AID_11_8_MAP_AID9_BID_MASK) + #define CAAM_DMA_X_AID_11_8_MAP_AID10_BID_MASK (0xFF0000U) #define CAAM_DMA_X_AID_11_8_MAP_AID10_BID_SHIFT (16U) #define CAAM_DMA_X_AID_11_8_MAP_AID10_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_11_8_MAP_AID10_BID_SHIFT)) & CAAM_DMA_X_AID_11_8_MAP_AID10_BID_MASK) + #define CAAM_DMA_X_AID_11_8_MAP_AID11_BID_MASK (0xFF000000U) #define CAAM_DMA_X_AID_11_8_MAP_AID11_BID_SHIFT (24U) #define CAAM_DMA_X_AID_11_8_MAP_AID11_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_11_8_MAP_AID11_BID_SHIFT)) & CAAM_DMA_X_AID_11_8_MAP_AID11_BID_MASK) @@ -11503,51 +12582,67 @@ typedef struct { /*! @name DMA_X_AID_15_0_EN - DMA_X AXI ID Map Enable Register */ /*! @{ */ + #define CAAM_DMA_X_AID_15_0_EN_AID0E_MASK (0x1U) #define CAAM_DMA_X_AID_15_0_EN_AID0E_SHIFT (0U) #define CAAM_DMA_X_AID_15_0_EN_AID0E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID0E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID0E_MASK) + #define CAAM_DMA_X_AID_15_0_EN_AID1E_MASK (0x2U) #define CAAM_DMA_X_AID_15_0_EN_AID1E_SHIFT (1U) #define CAAM_DMA_X_AID_15_0_EN_AID1E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID1E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID1E_MASK) + #define CAAM_DMA_X_AID_15_0_EN_AID2E_MASK (0x4U) #define CAAM_DMA_X_AID_15_0_EN_AID2E_SHIFT (2U) #define CAAM_DMA_X_AID_15_0_EN_AID2E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID2E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID2E_MASK) + #define CAAM_DMA_X_AID_15_0_EN_AID3E_MASK (0x8U) #define CAAM_DMA_X_AID_15_0_EN_AID3E_SHIFT (3U) #define CAAM_DMA_X_AID_15_0_EN_AID3E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID3E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID3E_MASK) + #define CAAM_DMA_X_AID_15_0_EN_AID4E_MASK (0x10U) #define CAAM_DMA_X_AID_15_0_EN_AID4E_SHIFT (4U) #define CAAM_DMA_X_AID_15_0_EN_AID4E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID4E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID4E_MASK) + #define CAAM_DMA_X_AID_15_0_EN_AID5E_MASK (0x20U) #define CAAM_DMA_X_AID_15_0_EN_AID5E_SHIFT (5U) #define CAAM_DMA_X_AID_15_0_EN_AID5E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID5E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID5E_MASK) + #define CAAM_DMA_X_AID_15_0_EN_AID6E_MASK (0x40U) #define CAAM_DMA_X_AID_15_0_EN_AID6E_SHIFT (6U) #define CAAM_DMA_X_AID_15_0_EN_AID6E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID6E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID6E_MASK) + #define CAAM_DMA_X_AID_15_0_EN_AID7E_MASK (0x80U) #define CAAM_DMA_X_AID_15_0_EN_AID7E_SHIFT (7U) #define CAAM_DMA_X_AID_15_0_EN_AID7E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID7E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID7E_MASK) + #define CAAM_DMA_X_AID_15_0_EN_AID8E_MASK (0x100U) #define CAAM_DMA_X_AID_15_0_EN_AID8E_SHIFT (8U) #define CAAM_DMA_X_AID_15_0_EN_AID8E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID8E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID8E_MASK) + #define CAAM_DMA_X_AID_15_0_EN_AID9E_MASK (0x200U) #define CAAM_DMA_X_AID_15_0_EN_AID9E_SHIFT (9U) #define CAAM_DMA_X_AID_15_0_EN_AID9E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID9E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID9E_MASK) + #define CAAM_DMA_X_AID_15_0_EN_AID10E_MASK (0x400U) #define CAAM_DMA_X_AID_15_0_EN_AID10E_SHIFT (10U) #define CAAM_DMA_X_AID_15_0_EN_AID10E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID10E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID10E_MASK) + #define CAAM_DMA_X_AID_15_0_EN_AID11E_MASK (0x800U) #define CAAM_DMA_X_AID_15_0_EN_AID11E_SHIFT (11U) #define CAAM_DMA_X_AID_15_0_EN_AID11E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID11E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID11E_MASK) + #define CAAM_DMA_X_AID_15_0_EN_AID12E_MASK (0x1000U) #define CAAM_DMA_X_AID_15_0_EN_AID12E_SHIFT (12U) #define CAAM_DMA_X_AID_15_0_EN_AID12E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID12E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID12E_MASK) + #define CAAM_DMA_X_AID_15_0_EN_AID13E_MASK (0x2000U) #define CAAM_DMA_X_AID_15_0_EN_AID13E_SHIFT (13U) #define CAAM_DMA_X_AID_15_0_EN_AID13E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID13E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID13E_MASK) + #define CAAM_DMA_X_AID_15_0_EN_AID14E_MASK (0x4000U) #define CAAM_DMA_X_AID_15_0_EN_AID14E_SHIFT (14U) #define CAAM_DMA_X_AID_15_0_EN_AID14E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID14E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID14E_MASK) + #define CAAM_DMA_X_AID_15_0_EN_AID15E_MASK (0x8000U) #define CAAM_DMA_X_AID_15_0_EN_AID15E_SHIFT (15U) #define CAAM_DMA_X_AID_15_0_EN_AID15E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID15E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID15E_MASK) @@ -11555,21 +12650,27 @@ typedef struct { /*! @name DMA_X_ARTC_CTL - DMA_X AXI Read Timing Check Control Register */ /*! @{ */ + #define CAAM_DMA_X_ARTC_CTL_ART_MASK (0xFFFU) #define CAAM_DMA_X_ARTC_CTL_ART_SHIFT (0U) #define CAAM_DMA_X_ARTC_CTL_ART(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ART_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ART_MASK) + #define CAAM_DMA_X_ARTC_CTL_ARL_MASK (0xFFF0000U) #define CAAM_DMA_X_ARTC_CTL_ARL_SHIFT (16U) #define CAAM_DMA_X_ARTC_CTL_ARL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARL_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARL_MASK) + #define CAAM_DMA_X_ARTC_CTL_ARTL_MASK (0x10000000U) #define CAAM_DMA_X_ARTC_CTL_ARTL_SHIFT (28U) #define CAAM_DMA_X_ARTC_CTL_ARTL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARTL_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARTL_MASK) + #define CAAM_DMA_X_ARTC_CTL_ARTT_MASK (0x20000000U) #define CAAM_DMA_X_ARTC_CTL_ARTT_SHIFT (29U) #define CAAM_DMA_X_ARTC_CTL_ARTT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARTT_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARTT_MASK) + #define CAAM_DMA_X_ARTC_CTL_ARCT_MASK (0x40000000U) #define CAAM_DMA_X_ARTC_CTL_ARCT_SHIFT (30U) #define CAAM_DMA_X_ARTC_CTL_ARCT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARCT_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARCT_MASK) + #define CAAM_DMA_X_ARTC_CTL_ARTCE_MASK (0x80000000U) #define CAAM_DMA_X_ARTC_CTL_ARTCE_SHIFT (31U) #define CAAM_DMA_X_ARTC_CTL_ARTCE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARTCE_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARTCE_MASK) @@ -11577,6 +12678,7 @@ typedef struct { /*! @name DMA_X_ARTC_LC - DMA_X AXI Read Timing Check Late Count Register */ /*! @{ */ + #define CAAM_DMA_X_ARTC_LC_ARLC_MASK (0xFFFFFU) #define CAAM_DMA_X_ARTC_LC_ARLC_SHIFT (0U) #define CAAM_DMA_X_ARTC_LC_ARLC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_LC_ARLC_SHIFT)) & CAAM_DMA_X_ARTC_LC_ARLC_MASK) @@ -11584,6 +12686,7 @@ typedef struct { /*! @name DMA_X_ARTC_SC - DMA_X AXI Read Timing Check Sample Count Register */ /*! @{ */ + #define CAAM_DMA_X_ARTC_SC_ARSC_MASK (0xFFFFFU) #define CAAM_DMA_X_ARTC_SC_ARSC_SHIFT (0U) #define CAAM_DMA_X_ARTC_SC_ARSC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_SC_ARSC_SHIFT)) & CAAM_DMA_X_ARTC_SC_ARSC_MASK) @@ -11591,6 +12694,7 @@ typedef struct { /*! @name DMA_X_ARTC_LAT - DMA_X Read Timing Check Latency Register */ /*! @{ */ + #define CAAM_DMA_X_ARTC_LAT_SARL_MASK (0xFFFFFFFFU) #define CAAM_DMA_X_ARTC_LAT_SARL_SHIFT (0U) #define CAAM_DMA_X_ARTC_LAT_SARL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_LAT_SARL_SHIFT)) & CAAM_DMA_X_ARTC_LAT_SARL_MASK) @@ -11598,18 +12702,23 @@ typedef struct { /*! @name DMA_X_AWTC_CTL - DMA_X AXI Write Timing Check Control Register */ /*! @{ */ + #define CAAM_DMA_X_AWTC_CTL_AWT_MASK (0xFFFU) #define CAAM_DMA_X_AWTC_CTL_AWT_SHIFT (0U) #define CAAM_DMA_X_AWTC_CTL_AWT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWT_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWT_MASK) + #define CAAM_DMA_X_AWTC_CTL_AWL_MASK (0xFFF0000U) #define CAAM_DMA_X_AWTC_CTL_AWL_SHIFT (16U) #define CAAM_DMA_X_AWTC_CTL_AWL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWL_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWL_MASK) + #define CAAM_DMA_X_AWTC_CTL_AWTT_MASK (0x20000000U) #define CAAM_DMA_X_AWTC_CTL_AWTT_SHIFT (29U) #define CAAM_DMA_X_AWTC_CTL_AWTT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWTT_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWTT_MASK) + #define CAAM_DMA_X_AWTC_CTL_AWCT_MASK (0x40000000U) #define CAAM_DMA_X_AWTC_CTL_AWCT_SHIFT (30U) #define CAAM_DMA_X_AWTC_CTL_AWCT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWCT_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWCT_MASK) + #define CAAM_DMA_X_AWTC_CTL_AWTCE_MASK (0x80000000U) #define CAAM_DMA_X_AWTC_CTL_AWTCE_SHIFT (31U) #define CAAM_DMA_X_AWTC_CTL_AWTCE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWTCE_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWTCE_MASK) @@ -11617,6 +12726,7 @@ typedef struct { /*! @name DMA_X_AWTC_LC - DMA_X AXI Write Timing Check Late Count Register */ /*! @{ */ + #define CAAM_DMA_X_AWTC_LC_AWLC_MASK (0xFFFFFU) #define CAAM_DMA_X_AWTC_LC_AWLC_SHIFT (0U) #define CAAM_DMA_X_AWTC_LC_AWLC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_LC_AWLC_SHIFT)) & CAAM_DMA_X_AWTC_LC_AWLC_MASK) @@ -11624,6 +12734,7 @@ typedef struct { /*! @name DMA_X_AWTC_SC - DMA_X AXI Write Timing Check Sample Count Register */ /*! @{ */ + #define CAAM_DMA_X_AWTC_SC_AWSC_MASK (0xFFFFFU) #define CAAM_DMA_X_AWTC_SC_AWSC_SHIFT (0U) #define CAAM_DMA_X_AWTC_SC_AWSC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_SC_AWSC_SHIFT)) & CAAM_DMA_X_AWTC_SC_AWSC_MASK) @@ -11631,6 +12742,7 @@ typedef struct { /*! @name DMA_X_AWTC_LAT - DMA_X Write Timing Check Latency Register */ /*! @{ */ + #define CAAM_DMA_X_AWTC_LAT_SAWL_MASK (0xFFFFFFFFU) #define CAAM_DMA_X_AWTC_LAT_SAWL_SHIFT (0U) #define CAAM_DMA_X_AWTC_LAT_SAWL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_LAT_SAWL_SHIFT)) & CAAM_DMA_X_AWTC_LAT_SAWL_MASK) @@ -11638,6 +12750,7 @@ typedef struct { /*! @name RTMCTL - RNG TRNG Miscellaneous Control Register */ /*! @{ */ + #define CAAM_RTMCTL_SAMP_MODE_MASK (0x3U) #define CAAM_RTMCTL_SAMP_MODE_SHIFT (0U) /*! SAMP_MODE @@ -11647,6 +12760,7 @@ typedef struct { * 0b11..undefined/reserved. */ #define CAAM_RTMCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_SAMP_MODE_SHIFT)) & CAAM_RTMCTL_SAMP_MODE_MASK) + #define CAAM_RTMCTL_OSC_DIV_MASK (0xCU) #define CAAM_RTMCTL_OSC_DIV_SHIFT (2U) /*! OSC_DIV @@ -11656,36 +12770,47 @@ typedef struct { * 0b11..use ring oscillator divided-by-8 */ #define CAAM_RTMCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_OSC_DIV_SHIFT)) & CAAM_RTMCTL_OSC_DIV_MASK) + #define CAAM_RTMCTL_CLK_OUT_EN_MASK (0x10U) #define CAAM_RTMCTL_CLK_OUT_EN_SHIFT (4U) #define CAAM_RTMCTL_CLK_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_CLK_OUT_EN_SHIFT)) & CAAM_RTMCTL_CLK_OUT_EN_MASK) + #define CAAM_RTMCTL_TRNG_ACC_MASK (0x20U) #define CAAM_RTMCTL_TRNG_ACC_SHIFT (5U) #define CAAM_RTMCTL_TRNG_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_TRNG_ACC_SHIFT)) & CAAM_RTMCTL_TRNG_ACC_MASK) + #define CAAM_RTMCTL_RST_DEF_MASK (0x40U) #define CAAM_RTMCTL_RST_DEF_SHIFT (6U) #define CAAM_RTMCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_RST_DEF_SHIFT)) & CAAM_RTMCTL_RST_DEF_MASK) + #define CAAM_RTMCTL_FORCE_SYSCLK_MASK (0x80U) #define CAAM_RTMCTL_FORCE_SYSCLK_SHIFT (7U) #define CAAM_RTMCTL_FORCE_SYSCLK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_FORCE_SYSCLK_SHIFT)) & CAAM_RTMCTL_FORCE_SYSCLK_MASK) + #define CAAM_RTMCTL_FCT_FAIL_MASK (0x100U) #define CAAM_RTMCTL_FCT_FAIL_SHIFT (8U) #define CAAM_RTMCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_FCT_FAIL_SHIFT)) & CAAM_RTMCTL_FCT_FAIL_MASK) + #define CAAM_RTMCTL_FCT_VAL_MASK (0x200U) #define CAAM_RTMCTL_FCT_VAL_SHIFT (9U) #define CAAM_RTMCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_FCT_VAL_SHIFT)) & CAAM_RTMCTL_FCT_VAL_MASK) + #define CAAM_RTMCTL_ENT_VAL_MASK (0x400U) #define CAAM_RTMCTL_ENT_VAL_SHIFT (10U) #define CAAM_RTMCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_ENT_VAL_SHIFT)) & CAAM_RTMCTL_ENT_VAL_MASK) + #define CAAM_RTMCTL_TST_OUT_MASK (0x800U) #define CAAM_RTMCTL_TST_OUT_SHIFT (11U) #define CAAM_RTMCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_TST_OUT_SHIFT)) & CAAM_RTMCTL_TST_OUT_MASK) + #define CAAM_RTMCTL_ERR_MASK (0x1000U) #define CAAM_RTMCTL_ERR_SHIFT (12U) #define CAAM_RTMCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_ERR_SHIFT)) & CAAM_RTMCTL_ERR_MASK) + #define CAAM_RTMCTL_TSTOP_OK_MASK (0x2000U) #define CAAM_RTMCTL_TSTOP_OK_SHIFT (13U) #define CAAM_RTMCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_TSTOP_OK_SHIFT)) & CAAM_RTMCTL_TSTOP_OK_MASK) + #define CAAM_RTMCTL_PRGM_MASK (0x10000U) #define CAAM_RTMCTL_PRGM_SHIFT (16U) #define CAAM_RTMCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_PRGM_SHIFT)) & CAAM_RTMCTL_PRGM_MASK) @@ -11693,9 +12818,11 @@ typedef struct { /*! @name RTSCMISC - RNG TRNG Statistical Check Miscellaneous Register */ /*! @{ */ + #define CAAM_RTSCMISC_LRUN_MAX_MASK (0xFFU) #define CAAM_RTSCMISC_LRUN_MAX_SHIFT (0U) #define CAAM_RTSCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCMISC_LRUN_MAX_SHIFT)) & CAAM_RTSCMISC_LRUN_MAX_MASK) + #define CAAM_RTSCMISC_RTY_CNT_MASK (0xF0000U) #define CAAM_RTSCMISC_RTY_CNT_SHIFT (16U) #define CAAM_RTSCMISC_RTY_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCMISC_RTY_CNT_SHIFT)) & CAAM_RTSCMISC_RTY_CNT_MASK) @@ -11703,6 +12830,7 @@ typedef struct { /*! @name RTPKRRNG - RNG TRNG Poker Range Register */ /*! @{ */ + #define CAAM_RTPKRRNG_PKR_RNG_MASK (0xFFFFU) #define CAAM_RTPKRRNG_PKR_RNG_SHIFT (0U) #define CAAM_RTPKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRRNG_PKR_RNG_SHIFT)) & CAAM_RTPKRRNG_PKR_RNG_MASK) @@ -11710,6 +12838,7 @@ typedef struct { /*! @name RTPKRMAX - RNG TRNG Poker Maximum Limit Register */ /*! @{ */ + #define CAAM_RTPKRMAX_PKR_MAX_MASK (0xFFFFFFU) #define CAAM_RTPKRMAX_PKR_MAX_SHIFT (0U) #define CAAM_RTPKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRMAX_PKR_MAX_SHIFT)) & CAAM_RTPKRMAX_PKR_MAX_MASK) @@ -11717,6 +12846,7 @@ typedef struct { /*! @name RTPKRSQ - RNG TRNG Poker Square Calculation Result Register */ /*! @{ */ + #define CAAM_RTPKRSQ_PKR_SQ_MASK (0xFFFFFFU) #define CAAM_RTPKRSQ_PKR_SQ_SHIFT (0U) #define CAAM_RTPKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRSQ_PKR_SQ_SHIFT)) & CAAM_RTPKRSQ_PKR_SQ_MASK) @@ -11724,9 +12854,11 @@ typedef struct { /*! @name RTSDCTL - RNG TRNG Seed Control Register */ /*! @{ */ + #define CAAM_RTSDCTL_SAMP_SIZE_MASK (0xFFFFU) #define CAAM_RTSDCTL_SAMP_SIZE_SHIFT (0U) #define CAAM_RTSDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSDCTL_SAMP_SIZE_SHIFT)) & CAAM_RTSDCTL_SAMP_SIZE_MASK) + #define CAAM_RTSDCTL_ENT_DLY_MASK (0xFFFF0000U) #define CAAM_RTSDCTL_ENT_DLY_SHIFT (16U) #define CAAM_RTSDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSDCTL_ENT_DLY_SHIFT)) & CAAM_RTSDCTL_ENT_DLY_MASK) @@ -11734,6 +12866,7 @@ typedef struct { /*! @name RTSBLIM - RNG TRNG Sparse Bit Limit Register */ /*! @{ */ + #define CAAM_RTSBLIM_SB_LIM_MASK (0x3FFU) #define CAAM_RTSBLIM_SB_LIM_SHIFT (0U) #define CAAM_RTSBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSBLIM_SB_LIM_SHIFT)) & CAAM_RTSBLIM_SB_LIM_MASK) @@ -11741,6 +12874,7 @@ typedef struct { /*! @name RTTOTSAM - RNG TRNG Total Samples Register */ /*! @{ */ + #define CAAM_RTTOTSAM_TOT_SAM_MASK (0xFFFFFU) #define CAAM_RTTOTSAM_TOT_SAM_SHIFT (0U) #define CAAM_RTTOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTTOTSAM_TOT_SAM_SHIFT)) & CAAM_RTTOTSAM_TOT_SAM_MASK) @@ -11748,6 +12882,7 @@ typedef struct { /*! @name RTFRQMIN - RNG TRNG Frequency Count Minimum Limit Register */ /*! @{ */ + #define CAAM_RTFRQMIN_FRQ_MIN_MASK (0x3FFFFFU) #define CAAM_RTFRQMIN_FRQ_MIN_SHIFT (0U) #define CAAM_RTFRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTFRQMIN_FRQ_MIN_SHIFT)) & CAAM_RTFRQMIN_FRQ_MIN_MASK) @@ -11755,6 +12890,7 @@ typedef struct { /*! @name RTFRQCNT - RNG TRNG Frequency Count Register */ /*! @{ */ + #define CAAM_RTFRQCNT_FRQ_CNT_MASK (0x3FFFFFU) #define CAAM_RTFRQCNT_FRQ_CNT_SHIFT (0U) #define CAAM_RTFRQCNT_FRQ_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTFRQCNT_FRQ_CNT_SHIFT)) & CAAM_RTFRQCNT_FRQ_CNT_MASK) @@ -11762,6 +12898,7 @@ typedef struct { /*! @name RTSCMC - RNG TRNG Statistical Check Monobit Count Register */ /*! @{ */ + #define CAAM_RTSCMC_MONO_CNT_MASK (0xFFFFU) #define CAAM_RTSCMC_MONO_CNT_SHIFT (0U) #define CAAM_RTSCMC_MONO_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCMC_MONO_CNT_SHIFT)) & CAAM_RTSCMC_MONO_CNT_MASK) @@ -11769,9 +12906,11 @@ typedef struct { /*! @name RTSCR1C - RNG TRNG Statistical Check Run Length 1 Count Register */ /*! @{ */ + #define CAAM_RTSCR1C_R1_0_COUNT_MASK (0x7FFFU) #define CAAM_RTSCR1C_R1_0_COUNT_SHIFT (0U) #define CAAM_RTSCR1C_R1_0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR1C_R1_0_COUNT_SHIFT)) & CAAM_RTSCR1C_R1_0_COUNT_MASK) + #define CAAM_RTSCR1C_R1_1_COUNT_MASK (0x7FFF0000U) #define CAAM_RTSCR1C_R1_1_COUNT_SHIFT (16U) #define CAAM_RTSCR1C_R1_1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR1C_R1_1_COUNT_SHIFT)) & CAAM_RTSCR1C_R1_1_COUNT_MASK) @@ -11779,9 +12918,11 @@ typedef struct { /*! @name RTSCR2C - RNG TRNG Statistical Check Run Length 2 Count Register */ /*! @{ */ + #define CAAM_RTSCR2C_R2_0_COUNT_MASK (0x3FFFU) #define CAAM_RTSCR2C_R2_0_COUNT_SHIFT (0U) #define CAAM_RTSCR2C_R2_0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR2C_R2_0_COUNT_SHIFT)) & CAAM_RTSCR2C_R2_0_COUNT_MASK) + #define CAAM_RTSCR2C_R2_1_COUNT_MASK (0x3FFF0000U) #define CAAM_RTSCR2C_R2_1_COUNT_SHIFT (16U) #define CAAM_RTSCR2C_R2_1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR2C_R2_1_COUNT_SHIFT)) & CAAM_RTSCR2C_R2_1_COUNT_MASK) @@ -11789,9 +12930,11 @@ typedef struct { /*! @name RTSCR3C - RNG TRNG Statistical Check Run Length 3 Count Register */ /*! @{ */ + #define CAAM_RTSCR3C_R3_0_COUNT_MASK (0x1FFFU) #define CAAM_RTSCR3C_R3_0_COUNT_SHIFT (0U) #define CAAM_RTSCR3C_R3_0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR3C_R3_0_COUNT_SHIFT)) & CAAM_RTSCR3C_R3_0_COUNT_MASK) + #define CAAM_RTSCR3C_R3_1_COUNT_MASK (0x1FFF0000U) #define CAAM_RTSCR3C_R3_1_COUNT_SHIFT (16U) #define CAAM_RTSCR3C_R3_1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR3C_R3_1_COUNT_SHIFT)) & CAAM_RTSCR3C_R3_1_COUNT_MASK) @@ -11799,9 +12942,11 @@ typedef struct { /*! @name RTSCR4C - RNG TRNG Statistical Check Run Length 4 Count Register */ /*! @{ */ + #define CAAM_RTSCR4C_R4_0_COUNT_MASK (0xFFFU) #define CAAM_RTSCR4C_R4_0_COUNT_SHIFT (0U) #define CAAM_RTSCR4C_R4_0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR4C_R4_0_COUNT_SHIFT)) & CAAM_RTSCR4C_R4_0_COUNT_MASK) + #define CAAM_RTSCR4C_R4_1_COUNT_MASK (0xFFF0000U) #define CAAM_RTSCR4C_R4_1_COUNT_SHIFT (16U) #define CAAM_RTSCR4C_R4_1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR4C_R4_1_COUNT_SHIFT)) & CAAM_RTSCR4C_R4_1_COUNT_MASK) @@ -11809,9 +12954,11 @@ typedef struct { /*! @name RTSCR5C - RNG TRNG Statistical Check Run Length 5 Count Register */ /*! @{ */ + #define CAAM_RTSCR5C_R5_0_COUNT_MASK (0x7FFU) #define CAAM_RTSCR5C_R5_0_COUNT_SHIFT (0U) #define CAAM_RTSCR5C_R5_0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR5C_R5_0_COUNT_SHIFT)) & CAAM_RTSCR5C_R5_0_COUNT_MASK) + #define CAAM_RTSCR5C_R5_1_COUNT_MASK (0x7FF0000U) #define CAAM_RTSCR5C_R5_1_COUNT_SHIFT (16U) #define CAAM_RTSCR5C_R5_1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR5C_R5_1_COUNT_SHIFT)) & CAAM_RTSCR5C_R5_1_COUNT_MASK) @@ -11819,9 +12966,11 @@ typedef struct { /*! @name RTSCR6PC - RNG TRNG Statistical Check Run Length 6+ Count Register */ /*! @{ */ + #define CAAM_RTSCR6PC_R6P_0_COUNT_MASK (0x7FFU) #define CAAM_RTSCR6PC_R6P_0_COUNT_SHIFT (0U) #define CAAM_RTSCR6PC_R6P_0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR6PC_R6P_0_COUNT_SHIFT)) & CAAM_RTSCR6PC_R6P_0_COUNT_MASK) + #define CAAM_RTSCR6PC_R6P_1_COUNT_MASK (0x7FF0000U) #define CAAM_RTSCR6PC_R6P_1_COUNT_SHIFT (16U) #define CAAM_RTSCR6PC_R6P_1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR6PC_R6P_1_COUNT_SHIFT)) & CAAM_RTSCR6PC_R6P_1_COUNT_MASK) @@ -11829,6 +12978,7 @@ typedef struct { /*! @name RTFRQMAX - RNG TRNG Frequency Count Maximum Limit Register */ /*! @{ */ + #define CAAM_RTFRQMAX_FRQ_MAX_MASK (0x3FFFFFU) #define CAAM_RTFRQMAX_FRQ_MAX_SHIFT (0U) #define CAAM_RTFRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTFRQMAX_FRQ_MAX_SHIFT)) & CAAM_RTFRQMAX_FRQ_MAX_MASK) @@ -11836,9 +12986,11 @@ typedef struct { /*! @name RTSCML - RNG TRNG Statistical Check Monobit Limit Register */ /*! @{ */ + #define CAAM_RTSCML_MONO_MAX_MASK (0xFFFFU) #define CAAM_RTSCML_MONO_MAX_SHIFT (0U) #define CAAM_RTSCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCML_MONO_MAX_SHIFT)) & CAAM_RTSCML_MONO_MAX_MASK) + #define CAAM_RTSCML_MONO_RNG_MASK (0xFFFF0000U) #define CAAM_RTSCML_MONO_RNG_SHIFT (16U) #define CAAM_RTSCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCML_MONO_RNG_SHIFT)) & CAAM_RTSCML_MONO_RNG_MASK) @@ -11846,9 +12998,11 @@ typedef struct { /*! @name RTSCR1L - RNG TRNG Statistical Check Run Length 1 Limit Register */ /*! @{ */ + #define CAAM_RTSCR1L_RUN1_MAX_MASK (0x7FFFU) #define CAAM_RTSCR1L_RUN1_MAX_SHIFT (0U) #define CAAM_RTSCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR1L_RUN1_MAX_SHIFT)) & CAAM_RTSCR1L_RUN1_MAX_MASK) + #define CAAM_RTSCR1L_RUN1_RNG_MASK (0x7FFF0000U) #define CAAM_RTSCR1L_RUN1_RNG_SHIFT (16U) #define CAAM_RTSCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR1L_RUN1_RNG_SHIFT)) & CAAM_RTSCR1L_RUN1_RNG_MASK) @@ -11856,9 +13010,11 @@ typedef struct { /*! @name RTSCR2L - RNG TRNG Statistical Check Run Length 2 Limit Register */ /*! @{ */ + #define CAAM_RTSCR2L_RUN2_MAX_MASK (0x3FFFU) #define CAAM_RTSCR2L_RUN2_MAX_SHIFT (0U) #define CAAM_RTSCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR2L_RUN2_MAX_SHIFT)) & CAAM_RTSCR2L_RUN2_MAX_MASK) + #define CAAM_RTSCR2L_RUN2_RNG_MASK (0x3FFF0000U) #define CAAM_RTSCR2L_RUN2_RNG_SHIFT (16U) #define CAAM_RTSCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR2L_RUN2_RNG_SHIFT)) & CAAM_RTSCR2L_RUN2_RNG_MASK) @@ -11866,9 +13022,11 @@ typedef struct { /*! @name RTSCR3L - RNG TRNG Statistical Check Run Length 3 Limit Register */ /*! @{ */ + #define CAAM_RTSCR3L_RUN3_MAX_MASK (0x1FFFU) #define CAAM_RTSCR3L_RUN3_MAX_SHIFT (0U) #define CAAM_RTSCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR3L_RUN3_MAX_SHIFT)) & CAAM_RTSCR3L_RUN3_MAX_MASK) + #define CAAM_RTSCR3L_RUN3_RNG_MASK (0x1FFF0000U) #define CAAM_RTSCR3L_RUN3_RNG_SHIFT (16U) #define CAAM_RTSCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR3L_RUN3_RNG_SHIFT)) & CAAM_RTSCR3L_RUN3_RNG_MASK) @@ -11876,9 +13034,11 @@ typedef struct { /*! @name RTSCR4L - RNG TRNG Statistical Check Run Length 4 Limit Register */ /*! @{ */ + #define CAAM_RTSCR4L_RUN4_MAX_MASK (0xFFFU) #define CAAM_RTSCR4L_RUN4_MAX_SHIFT (0U) #define CAAM_RTSCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR4L_RUN4_MAX_SHIFT)) & CAAM_RTSCR4L_RUN4_MAX_MASK) + #define CAAM_RTSCR4L_RUN4_RNG_MASK (0xFFF0000U) #define CAAM_RTSCR4L_RUN4_RNG_SHIFT (16U) #define CAAM_RTSCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR4L_RUN4_RNG_SHIFT)) & CAAM_RTSCR4L_RUN4_RNG_MASK) @@ -11886,9 +13046,11 @@ typedef struct { /*! @name RTSCR5L - RNG TRNG Statistical Check Run Length 5 Limit Register */ /*! @{ */ + #define CAAM_RTSCR5L_RUN5_MAX_MASK (0x7FFU) #define CAAM_RTSCR5L_RUN5_MAX_SHIFT (0U) #define CAAM_RTSCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR5L_RUN5_MAX_SHIFT)) & CAAM_RTSCR5L_RUN5_MAX_MASK) + #define CAAM_RTSCR5L_RUN5_RNG_MASK (0x7FF0000U) #define CAAM_RTSCR5L_RUN5_RNG_SHIFT (16U) #define CAAM_RTSCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR5L_RUN5_RNG_SHIFT)) & CAAM_RTSCR5L_RUN5_RNG_MASK) @@ -11896,9 +13058,11 @@ typedef struct { /*! @name RTSCR6PL - RNG TRNG Statistical Check Run Length 6+ Limit Register */ /*! @{ */ + #define CAAM_RTSCR6PL_RUN6P_MAX_MASK (0x7FFU) #define CAAM_RTSCR6PL_RUN6P_MAX_SHIFT (0U) #define CAAM_RTSCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR6PL_RUN6P_MAX_SHIFT)) & CAAM_RTSCR6PL_RUN6P_MAX_MASK) + #define CAAM_RTSCR6PL_RUN6P_RNG_MASK (0x7FF0000U) #define CAAM_RTSCR6PL_RUN6P_RNG_SHIFT (16U) #define CAAM_RTSCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR6PL_RUN6P_RNG_SHIFT)) & CAAM_RTSCR6PL_RUN6P_RNG_MASK) @@ -11906,54 +13070,71 @@ typedef struct { /*! @name RTSTATUS - RNG TRNG Status Register */ /*! @{ */ + #define CAAM_RTSTATUS_F1BR0TF_MASK (0x1U) #define CAAM_RTSTATUS_F1BR0TF_SHIFT (0U) #define CAAM_RTSTATUS_F1BR0TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F1BR0TF_SHIFT)) & CAAM_RTSTATUS_F1BR0TF_MASK) + #define CAAM_RTSTATUS_F1BR1TF_MASK (0x2U) #define CAAM_RTSTATUS_F1BR1TF_SHIFT (1U) #define CAAM_RTSTATUS_F1BR1TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F1BR1TF_SHIFT)) & CAAM_RTSTATUS_F1BR1TF_MASK) + #define CAAM_RTSTATUS_F2BR0TF_MASK (0x4U) #define CAAM_RTSTATUS_F2BR0TF_SHIFT (2U) #define CAAM_RTSTATUS_F2BR0TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F2BR0TF_SHIFT)) & CAAM_RTSTATUS_F2BR0TF_MASK) + #define CAAM_RTSTATUS_F2BR1TF_MASK (0x8U) #define CAAM_RTSTATUS_F2BR1TF_SHIFT (3U) #define CAAM_RTSTATUS_F2BR1TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F2BR1TF_SHIFT)) & CAAM_RTSTATUS_F2BR1TF_MASK) + #define CAAM_RTSTATUS_F3BR01TF_MASK (0x10U) #define CAAM_RTSTATUS_F3BR01TF_SHIFT (4U) #define CAAM_RTSTATUS_F3BR01TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F3BR01TF_SHIFT)) & CAAM_RTSTATUS_F3BR01TF_MASK) + #define CAAM_RTSTATUS_F3BR1TF_MASK (0x20U) #define CAAM_RTSTATUS_F3BR1TF_SHIFT (5U) #define CAAM_RTSTATUS_F3BR1TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F3BR1TF_SHIFT)) & CAAM_RTSTATUS_F3BR1TF_MASK) + #define CAAM_RTSTATUS_F4BR0TF_MASK (0x40U) #define CAAM_RTSTATUS_F4BR0TF_SHIFT (6U) #define CAAM_RTSTATUS_F4BR0TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F4BR0TF_SHIFT)) & CAAM_RTSTATUS_F4BR0TF_MASK) + #define CAAM_RTSTATUS_F4BR1TF_MASK (0x80U) #define CAAM_RTSTATUS_F4BR1TF_SHIFT (7U) #define CAAM_RTSTATUS_F4BR1TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F4BR1TF_SHIFT)) & CAAM_RTSTATUS_F4BR1TF_MASK) + #define CAAM_RTSTATUS_F5BR0TF_MASK (0x100U) #define CAAM_RTSTATUS_F5BR0TF_SHIFT (8U) #define CAAM_RTSTATUS_F5BR0TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F5BR0TF_SHIFT)) & CAAM_RTSTATUS_F5BR0TF_MASK) + #define CAAM_RTSTATUS_F5BR1TF_MASK (0x200U) #define CAAM_RTSTATUS_F5BR1TF_SHIFT (9U) #define CAAM_RTSTATUS_F5BR1TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F5BR1TF_SHIFT)) & CAAM_RTSTATUS_F5BR1TF_MASK) + #define CAAM_RTSTATUS_F6PBR0TF_MASK (0x400U) #define CAAM_RTSTATUS_F6PBR0TF_SHIFT (10U) #define CAAM_RTSTATUS_F6PBR0TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F6PBR0TF_SHIFT)) & CAAM_RTSTATUS_F6PBR0TF_MASK) + #define CAAM_RTSTATUS_F6PBR1TF_MASK (0x800U) #define CAAM_RTSTATUS_F6PBR1TF_SHIFT (11U) #define CAAM_RTSTATUS_F6PBR1TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F6PBR1TF_SHIFT)) & CAAM_RTSTATUS_F6PBR1TF_MASK) + #define CAAM_RTSTATUS_FSBTF_MASK (0x1000U) #define CAAM_RTSTATUS_FSBTF_SHIFT (12U) #define CAAM_RTSTATUS_FSBTF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_FSBTF_SHIFT)) & CAAM_RTSTATUS_FSBTF_MASK) + #define CAAM_RTSTATUS_FLRTF_MASK (0x2000U) #define CAAM_RTSTATUS_FLRTF_SHIFT (13U) #define CAAM_RTSTATUS_FLRTF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_FLRTF_SHIFT)) & CAAM_RTSTATUS_FLRTF_MASK) + #define CAAM_RTSTATUS_FPTF_MASK (0x4000U) #define CAAM_RTSTATUS_FPTF_SHIFT (14U) #define CAAM_RTSTATUS_FPTF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_FPTF_SHIFT)) & CAAM_RTSTATUS_FPTF_MASK) + #define CAAM_RTSTATUS_FMBTF_MASK (0x8000U) #define CAAM_RTSTATUS_FMBTF_SHIFT (15U) #define CAAM_RTSTATUS_FMBTF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_FMBTF_SHIFT)) & CAAM_RTSTATUS_FMBTF_MASK) + #define CAAM_RTSTATUS_RETRY_COUNT_MASK (0xF0000U) #define CAAM_RTSTATUS_RETRY_COUNT_SHIFT (16U) #define CAAM_RTSTATUS_RETRY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_RETRY_COUNT_SHIFT)) & CAAM_RTSTATUS_RETRY_COUNT_MASK) @@ -11961,6 +13142,7 @@ typedef struct { /*! @name RTENT - RNG TRNG Entropy Read Register */ /*! @{ */ + #define CAAM_RTENT_ENT_MASK (0xFFFFFFFFU) #define CAAM_RTENT_ENT_SHIFT (0U) #define CAAM_RTENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTENT_ENT_SHIFT)) & CAAM_RTENT_ENT_MASK) @@ -11971,9 +13153,11 @@ typedef struct { /*! @name RTPKRCNT10 - RNG TRNG Statistical Check Poker Count 1 and 0 Register */ /*! @{ */ + #define CAAM_RTPKRCNT10_PKR_0_CNT_MASK (0xFFFFU) #define CAAM_RTPKRCNT10_PKR_0_CNT_SHIFT (0U) #define CAAM_RTPKRCNT10_PKR_0_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT10_PKR_0_CNT_SHIFT)) & CAAM_RTPKRCNT10_PKR_0_CNT_MASK) + #define CAAM_RTPKRCNT10_PKR_1_CNT_MASK (0xFFFF0000U) #define CAAM_RTPKRCNT10_PKR_1_CNT_SHIFT (16U) #define CAAM_RTPKRCNT10_PKR_1_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT10_PKR_1_CNT_SHIFT)) & CAAM_RTPKRCNT10_PKR_1_CNT_MASK) @@ -11981,9 +13165,11 @@ typedef struct { /*! @name RTPKRCNT32 - RNG TRNG Statistical Check Poker Count 3 and 2 Register */ /*! @{ */ + #define CAAM_RTPKRCNT32_PKR_2_CNT_MASK (0xFFFFU) #define CAAM_RTPKRCNT32_PKR_2_CNT_SHIFT (0U) #define CAAM_RTPKRCNT32_PKR_2_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT32_PKR_2_CNT_SHIFT)) & CAAM_RTPKRCNT32_PKR_2_CNT_MASK) + #define CAAM_RTPKRCNT32_PKR_3_CNT_MASK (0xFFFF0000U) #define CAAM_RTPKRCNT32_PKR_3_CNT_SHIFT (16U) #define CAAM_RTPKRCNT32_PKR_3_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT32_PKR_3_CNT_SHIFT)) & CAAM_RTPKRCNT32_PKR_3_CNT_MASK) @@ -11991,9 +13177,11 @@ typedef struct { /*! @name RTPKRCNT54 - RNG TRNG Statistical Check Poker Count 5 and 4 Register */ /*! @{ */ + #define CAAM_RTPKRCNT54_PKR_4_CNT_MASK (0xFFFFU) #define CAAM_RTPKRCNT54_PKR_4_CNT_SHIFT (0U) #define CAAM_RTPKRCNT54_PKR_4_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT54_PKR_4_CNT_SHIFT)) & CAAM_RTPKRCNT54_PKR_4_CNT_MASK) + #define CAAM_RTPKRCNT54_PKR_5_CNT_MASK (0xFFFF0000U) #define CAAM_RTPKRCNT54_PKR_5_CNT_SHIFT (16U) #define CAAM_RTPKRCNT54_PKR_5_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT54_PKR_5_CNT_SHIFT)) & CAAM_RTPKRCNT54_PKR_5_CNT_MASK) @@ -12001,9 +13189,11 @@ typedef struct { /*! @name RTPKRCNT76 - RNG TRNG Statistical Check Poker Count 7 and 6 Register */ /*! @{ */ + #define CAAM_RTPKRCNT76_PKR_6_CNT_MASK (0xFFFFU) #define CAAM_RTPKRCNT76_PKR_6_CNT_SHIFT (0U) #define CAAM_RTPKRCNT76_PKR_6_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT76_PKR_6_CNT_SHIFT)) & CAAM_RTPKRCNT76_PKR_6_CNT_MASK) + #define CAAM_RTPKRCNT76_PKR_7_CNT_MASK (0xFFFF0000U) #define CAAM_RTPKRCNT76_PKR_7_CNT_SHIFT (16U) #define CAAM_RTPKRCNT76_PKR_7_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT76_PKR_7_CNT_SHIFT)) & CAAM_RTPKRCNT76_PKR_7_CNT_MASK) @@ -12011,9 +13201,11 @@ typedef struct { /*! @name RTPKRCNT98 - RNG TRNG Statistical Check Poker Count 9 and 8 Register */ /*! @{ */ + #define CAAM_RTPKRCNT98_PKR_8_CNT_MASK (0xFFFFU) #define CAAM_RTPKRCNT98_PKR_8_CNT_SHIFT (0U) #define CAAM_RTPKRCNT98_PKR_8_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT98_PKR_8_CNT_SHIFT)) & CAAM_RTPKRCNT98_PKR_8_CNT_MASK) + #define CAAM_RTPKRCNT98_PKR_9_CNT_MASK (0xFFFF0000U) #define CAAM_RTPKRCNT98_PKR_9_CNT_SHIFT (16U) #define CAAM_RTPKRCNT98_PKR_9_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT98_PKR_9_CNT_SHIFT)) & CAAM_RTPKRCNT98_PKR_9_CNT_MASK) @@ -12021,9 +13213,11 @@ typedef struct { /*! @name RTPKRCNTBA - RNG TRNG Statistical Check Poker Count B and A Register */ /*! @{ */ + #define CAAM_RTPKRCNTBA_PKR_A_CNT_MASK (0xFFFFU) #define CAAM_RTPKRCNTBA_PKR_A_CNT_SHIFT (0U) #define CAAM_RTPKRCNTBA_PKR_A_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTBA_PKR_A_CNT_SHIFT)) & CAAM_RTPKRCNTBA_PKR_A_CNT_MASK) + #define CAAM_RTPKRCNTBA_PKR_B_CNT_MASK (0xFFFF0000U) #define CAAM_RTPKRCNTBA_PKR_B_CNT_SHIFT (16U) #define CAAM_RTPKRCNTBA_PKR_B_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTBA_PKR_B_CNT_SHIFT)) & CAAM_RTPKRCNTBA_PKR_B_CNT_MASK) @@ -12031,9 +13225,11 @@ typedef struct { /*! @name RTPKRCNTDC - RNG TRNG Statistical Check Poker Count D and C Register */ /*! @{ */ + #define CAAM_RTPKRCNTDC_PKR_C_CNT_MASK (0xFFFFU) #define CAAM_RTPKRCNTDC_PKR_C_CNT_SHIFT (0U) #define CAAM_RTPKRCNTDC_PKR_C_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTDC_PKR_C_CNT_SHIFT)) & CAAM_RTPKRCNTDC_PKR_C_CNT_MASK) + #define CAAM_RTPKRCNTDC_PKR_D_CNT_MASK (0xFFFF0000U) #define CAAM_RTPKRCNTDC_PKR_D_CNT_SHIFT (16U) #define CAAM_RTPKRCNTDC_PKR_D_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTDC_PKR_D_CNT_SHIFT)) & CAAM_RTPKRCNTDC_PKR_D_CNT_MASK) @@ -12041,9 +13237,11 @@ typedef struct { /*! @name RTPKRCNTFE - RNG TRNG Statistical Check Poker Count F and E Register */ /*! @{ */ + #define CAAM_RTPKRCNTFE_PKR_E_CNT_MASK (0xFFFFU) #define CAAM_RTPKRCNTFE_PKR_E_CNT_SHIFT (0U) #define CAAM_RTPKRCNTFE_PKR_E_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTFE_PKR_E_CNT_SHIFT)) & CAAM_RTPKRCNTFE_PKR_E_CNT_MASK) + #define CAAM_RTPKRCNTFE_PKR_F_CNT_MASK (0xFFFF0000U) #define CAAM_RTPKRCNTFE_PKR_F_CNT_SHIFT (16U) #define CAAM_RTPKRCNTFE_PKR_F_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTFE_PKR_F_CNT_SHIFT)) & CAAM_RTPKRCNTFE_PKR_F_CNT_MASK) @@ -12051,33 +13249,43 @@ typedef struct { /*! @name RDSTA - RNG DRNG Status Register */ /*! @{ */ + #define CAAM_RDSTA_IF0_MASK (0x1U) #define CAAM_RDSTA_IF0_SHIFT (0U) #define CAAM_RDSTA_IF0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_IF0_SHIFT)) & CAAM_RDSTA_IF0_MASK) + #define CAAM_RDSTA_IF1_MASK (0x2U) #define CAAM_RDSTA_IF1_SHIFT (1U) #define CAAM_RDSTA_IF1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_IF1_SHIFT)) & CAAM_RDSTA_IF1_MASK) + #define CAAM_RDSTA_PR0_MASK (0x10U) #define CAAM_RDSTA_PR0_SHIFT (4U) #define CAAM_RDSTA_PR0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_PR0_SHIFT)) & CAAM_RDSTA_PR0_MASK) + #define CAAM_RDSTA_PR1_MASK (0x20U) #define CAAM_RDSTA_PR1_SHIFT (5U) #define CAAM_RDSTA_PR1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_PR1_SHIFT)) & CAAM_RDSTA_PR1_MASK) + #define CAAM_RDSTA_TF0_MASK (0x100U) #define CAAM_RDSTA_TF0_SHIFT (8U) #define CAAM_RDSTA_TF0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_TF0_SHIFT)) & CAAM_RDSTA_TF0_MASK) + #define CAAM_RDSTA_TF1_MASK (0x200U) #define CAAM_RDSTA_TF1_SHIFT (9U) #define CAAM_RDSTA_TF1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_TF1_SHIFT)) & CAAM_RDSTA_TF1_MASK) + #define CAAM_RDSTA_ERRCODE_MASK (0xF0000U) #define CAAM_RDSTA_ERRCODE_SHIFT (16U) #define CAAM_RDSTA_ERRCODE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_ERRCODE_SHIFT)) & CAAM_RDSTA_ERRCODE_MASK) + #define CAAM_RDSTA_CE_MASK (0x100000U) #define CAAM_RDSTA_CE_SHIFT (20U) #define CAAM_RDSTA_CE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_CE_SHIFT)) & CAAM_RDSTA_CE_MASK) + #define CAAM_RDSTA_SKVN_MASK (0x40000000U) #define CAAM_RDSTA_SKVN_SHIFT (30U) #define CAAM_RDSTA_SKVN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_SKVN_SHIFT)) & CAAM_RDSTA_SKVN_MASK) + #define CAAM_RDSTA_SKVT_MASK (0x80000000U) #define CAAM_RDSTA_SKVT_SHIFT (31U) #define CAAM_RDSTA_SKVT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_SKVT_SHIFT)) & CAAM_RDSTA_SKVT_MASK) @@ -12085,6 +13293,7 @@ typedef struct { /*! @name RDINT0 - RNG DRNG State Handle 0 Reseed Interval Register */ /*! @{ */ + #define CAAM_RDINT0_RESINT0_MASK (0xFFFFFFFFU) #define CAAM_RDINT0_RESINT0_SHIFT (0U) #define CAAM_RDINT0_RESINT0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDINT0_RESINT0_SHIFT)) & CAAM_RDINT0_RESINT0_MASK) @@ -12092,6 +13301,7 @@ typedef struct { /*! @name RDINT1 - RNG DRNG State Handle 1 Reseed Interval Register */ /*! @{ */ + #define CAAM_RDINT1_RESINT1_MASK (0xFFFFFFFFU) #define CAAM_RDINT1_RESINT1_SHIFT (0U) #define CAAM_RDINT1_RESINT1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDINT1_RESINT1_SHIFT)) & CAAM_RDINT1_RESINT1_MASK) @@ -12099,18 +13309,23 @@ typedef struct { /*! @name RDHCNTL - RNG DRNG Hash Control Register */ /*! @{ */ + #define CAAM_RDHCNTL_HD_MASK (0x1U) #define CAAM_RDHCNTL_HD_SHIFT (0U) #define CAAM_RDHCNTL_HD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HD_SHIFT)) & CAAM_RDHCNTL_HD_MASK) + #define CAAM_RDHCNTL_HB_MASK (0x2U) #define CAAM_RDHCNTL_HB_SHIFT (1U) #define CAAM_RDHCNTL_HB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HB_SHIFT)) & CAAM_RDHCNTL_HB_MASK) + #define CAAM_RDHCNTL_HI_MASK (0x4U) #define CAAM_RDHCNTL_HI_SHIFT (2U) #define CAAM_RDHCNTL_HI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HI_SHIFT)) & CAAM_RDHCNTL_HI_MASK) + #define CAAM_RDHCNTL_HTM_MASK (0x8U) #define CAAM_RDHCNTL_HTM_SHIFT (3U) #define CAAM_RDHCNTL_HTM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HTM_SHIFT)) & CAAM_RDHCNTL_HTM_MASK) + #define CAAM_RDHCNTL_HTC_MASK (0x10U) #define CAAM_RDHCNTL_HTC_SHIFT (4U) #define CAAM_RDHCNTL_HTC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HTC_SHIFT)) & CAAM_RDHCNTL_HTC_MASK) @@ -12118,6 +13333,7 @@ typedef struct { /*! @name RDHDIG - RNG DRNG Hash Digest Register */ /*! @{ */ + #define CAAM_RDHDIG_HASHMD_MASK (0xFFFFFFFFU) #define CAAM_RDHDIG_HASHMD_SHIFT (0U) #define CAAM_RDHDIG_HASHMD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDHDIG_HASHMD_SHIFT)) & CAAM_RDHDIG_HASHMD_MASK) @@ -12125,23 +13341,26 @@ typedef struct { /*! @name RDHBUF - RNG DRNG Hash Buffer Register */ /*! @{ */ + #define CAAM_RDHBUF_HASHBUF_MASK (0xFFFFFFFFU) #define CAAM_RDHBUF_HASHBUF_SHIFT (0U) #define CAAM_RDHBUF_HASHBUF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDHBUF_HASHBUF_SHIFT)) & CAAM_RDHBUF_HASHBUF_MASK) /*! @} */ -/*! @name PX_SDIDR_PG0 - Partition 0 SDID register..Partition 15 SDID register */ +/*! @name PX_SDID_PG0 - Partition 0 SDID register..Partition 15 SDID register */ /*! @{ */ -#define CAAM_PX_SDIDR_PG0_SDID_MASK (0xFFFFU) -#define CAAM_PX_SDIDR_PG0_SDID_SHIFT (0U) -#define CAAM_PX_SDIDR_PG0_SDID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SDIDR_PG0_SDID_SHIFT)) & CAAM_PX_SDIDR_PG0_SDID_MASK) + +#define CAAM_PX_SDID_PG0_SDID_MASK (0xFFFFU) +#define CAAM_PX_SDID_PG0_SDID_SHIFT (0U) +#define CAAM_PX_SDID_PG0_SDID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SDID_PG0_SDID_SHIFT)) & CAAM_PX_SDID_PG0_SDID_MASK) /*! @} */ -/* The count of CAAM_PX_SDIDR_PG0 */ -#define CAAM_PX_SDIDR_PG0_COUNT (16U) +/* The count of CAAM_PX_SDID_PG0 */ +#define CAAM_PX_SDID_PG0_COUNT (16U) /*! @name PX_SMAPR_PG0 - Secure Memory Access Permissions register */ /*! @{ */ + #define CAAM_PX_SMAPR_PG0_G1_READ_MASK (0x1U) #define CAAM_PX_SMAPR_PG0_G1_READ_SHIFT (0U) /*! G1_READ @@ -12152,6 +13371,7 @@ typedef struct { * G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). */ #define CAAM_PX_SMAPR_PG0_G1_READ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G1_READ_SHIFT)) & CAAM_PX_SMAPR_PG0_G1_READ_MASK) + #define CAAM_PX_SMAPR_PG0_G1_WRITE_MASK (0x2U) #define CAAM_PX_SMAPR_PG0_G1_WRITE_SHIFT (1U) /*! G1_WRITE @@ -12161,6 +13381,7 @@ typedef struct { * not a Trusted Descriptor or if G1_TDO=0). */ #define CAAM_PX_SMAPR_PG0_G1_WRITE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G1_WRITE_SHIFT)) & CAAM_PX_SMAPR_PG0_G1_WRITE_MASK) + #define CAAM_PX_SMAPR_PG0_G1_TDO_MASK (0x4U) #define CAAM_PX_SMAPR_PG0_G1_TDO_SHIFT (2U) /*! G1_TDO @@ -12170,6 +13391,7 @@ typedef struct { * G1_WRITE and G1_READ settings. */ #define CAAM_PX_SMAPR_PG0_G1_TDO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G1_TDO_SHIFT)) & CAAM_PX_SMAPR_PG0_G1_TDO_MASK) + #define CAAM_PX_SMAPR_PG0_G1_SMBLOB_MASK (0x8U) #define CAAM_PX_SMAPR_PG0_G1_SMBLOB_SHIFT (3U) /*! G1_SMBLOB @@ -12177,6 +13399,7 @@ typedef struct { * 0b1..Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. */ #define CAAM_PX_SMAPR_PG0_G1_SMBLOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G1_SMBLOB_SHIFT)) & CAAM_PX_SMAPR_PG0_G1_SMBLOB_MASK) + #define CAAM_PX_SMAPR_PG0_G2_READ_MASK (0x10U) #define CAAM_PX_SMAPR_PG0_G2_READ_SHIFT (4U) /*! G2_READ @@ -12187,6 +13410,7 @@ typedef struct { * G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). */ #define CAAM_PX_SMAPR_PG0_G2_READ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G2_READ_SHIFT)) & CAAM_PX_SMAPR_PG0_G2_READ_MASK) + #define CAAM_PX_SMAPR_PG0_G2_WRITE_MASK (0x20U) #define CAAM_PX_SMAPR_PG0_G2_WRITE_SHIFT (5U) /*! G2_WRITE @@ -12196,6 +13420,7 @@ typedef struct { * not a Trusted Descriptor or if G2_TDO=0). */ #define CAAM_PX_SMAPR_PG0_G2_WRITE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G2_WRITE_SHIFT)) & CAAM_PX_SMAPR_PG0_G2_WRITE_MASK) + #define CAAM_PX_SMAPR_PG0_G2_TDO_MASK (0x40U) #define CAAM_PX_SMAPR_PG0_G2_TDO_SHIFT (6U) /*! G2_TDO @@ -12205,6 +13430,7 @@ typedef struct { * G2_WRITE and G2_READ settings. */ #define CAAM_PX_SMAPR_PG0_G2_TDO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G2_TDO_SHIFT)) & CAAM_PX_SMAPR_PG0_G2_TDO_MASK) + #define CAAM_PX_SMAPR_PG0_G2_SMBLOB_MASK (0x80U) #define CAAM_PX_SMAPR_PG0_G2_SMBLOB_SHIFT (7U) /*! G2_SMBLOB @@ -12212,6 +13438,7 @@ typedef struct { * 0b1..Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. */ #define CAAM_PX_SMAPR_PG0_G2_SMBLOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G2_SMBLOB_SHIFT)) & CAAM_PX_SMAPR_PG0_G2_SMBLOB_MASK) + #define CAAM_PX_SMAPR_PG0_SMAG_LCK_MASK (0x1000U) #define CAAM_PX_SMAPR_PG0_SMAG_LCK_SHIFT (12U) /*! SMAG_LCK @@ -12220,6 +13447,7 @@ typedef struct { * until the partition is de-allocated or a POR occurs. */ #define CAAM_PX_SMAPR_PG0_SMAG_LCK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_SMAG_LCK_SHIFT)) & CAAM_PX_SMAPR_PG0_SMAG_LCK_MASK) + #define CAAM_PX_SMAPR_PG0_SMAP_LCK_MASK (0x2000U) #define CAAM_PX_SMAPR_PG0_SMAP_LCK_SHIFT (13U) /*! SMAP_LCK @@ -12229,6 +13457,7 @@ typedef struct { * still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. */ #define CAAM_PX_SMAPR_PG0_SMAP_LCK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_SMAP_LCK_SHIFT)) & CAAM_PX_SMAPR_PG0_SMAP_LCK_MASK) + #define CAAM_PX_SMAPR_PG0_PSP_MASK (0x4000U) #define CAAM_PX_SMAPR_PG0_PSP_SHIFT (14U) /*! PSP @@ -12236,6 +13465,7 @@ typedef struct { * 0b1..The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. */ #define CAAM_PX_SMAPR_PG0_PSP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_PSP_SHIFT)) & CAAM_PX_SMAPR_PG0_PSP_MASK) + #define CAAM_PX_SMAPR_PG0_CSP_MASK (0x8000U) #define CAAM_PX_SMAPR_PG0_CSP_SHIFT (15U) /*! CSP @@ -12245,6 +13475,7 @@ typedef struct { * partition is released or a security alarm occurs. */ #define CAAM_PX_SMAPR_PG0_CSP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_CSP_SHIFT)) & CAAM_PX_SMAPR_PG0_CSP_MASK) + #define CAAM_PX_SMAPR_PG0_PARTITION_KMOD_MASK (0xFFFF0000U) #define CAAM_PX_SMAPR_PG0_PARTITION_KMOD_SHIFT (16U) #define CAAM_PX_SMAPR_PG0_PARTITION_KMOD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_PARTITION_KMOD_SHIFT)) & CAAM_PX_SMAPR_PG0_PARTITION_KMOD_MASK) @@ -12253,129 +13484,299 @@ typedef struct { /* The count of CAAM_PX_SMAPR_PG0 */ #define CAAM_PX_SMAPR_PG0_COUNT (16U) -/*! @name PX_SMAG_PG0 - Secure Memory Access Group Registers */ -/*! @{ */ -#define CAAM_PX_SMAG_PG0_Gx_ID00_MASK (0x1U) -#define CAAM_PX_SMAG_PG0_Gx_ID00_SHIFT (0U) -#define CAAM_PX_SMAG_PG0_Gx_ID00(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID00_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID00_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID01_MASK (0x2U) -#define CAAM_PX_SMAG_PG0_Gx_ID01_SHIFT (1U) -#define CAAM_PX_SMAG_PG0_Gx_ID01(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID01_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID01_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID02_MASK (0x4U) -#define CAAM_PX_SMAG_PG0_Gx_ID02_SHIFT (2U) -#define CAAM_PX_SMAG_PG0_Gx_ID02(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID02_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID02_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID03_MASK (0x8U) -#define CAAM_PX_SMAG_PG0_Gx_ID03_SHIFT (3U) -#define CAAM_PX_SMAG_PG0_Gx_ID03(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID03_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID03_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID04_MASK (0x10U) -#define CAAM_PX_SMAG_PG0_Gx_ID04_SHIFT (4U) -#define CAAM_PX_SMAG_PG0_Gx_ID04(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID04_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID04_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID05_MASK (0x20U) -#define CAAM_PX_SMAG_PG0_Gx_ID05_SHIFT (5U) -#define CAAM_PX_SMAG_PG0_Gx_ID05(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID05_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID05_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID06_MASK (0x40U) -#define CAAM_PX_SMAG_PG0_Gx_ID06_SHIFT (6U) -#define CAAM_PX_SMAG_PG0_Gx_ID06(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID06_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID06_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID07_MASK (0x80U) -#define CAAM_PX_SMAG_PG0_Gx_ID07_SHIFT (7U) -#define CAAM_PX_SMAG_PG0_Gx_ID07(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID07_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID07_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID08_MASK (0x100U) -#define CAAM_PX_SMAG_PG0_Gx_ID08_SHIFT (8U) -#define CAAM_PX_SMAG_PG0_Gx_ID08(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID08_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID08_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID09_MASK (0x200U) -#define CAAM_PX_SMAG_PG0_Gx_ID09_SHIFT (9U) -#define CAAM_PX_SMAG_PG0_Gx_ID09(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID09_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID09_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID10_MASK (0x400U) -#define CAAM_PX_SMAG_PG0_Gx_ID10_SHIFT (10U) -#define CAAM_PX_SMAG_PG0_Gx_ID10(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID10_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID10_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID11_MASK (0x800U) -#define CAAM_PX_SMAG_PG0_Gx_ID11_SHIFT (11U) -#define CAAM_PX_SMAG_PG0_Gx_ID11(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID11_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID11_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID12_MASK (0x1000U) -#define CAAM_PX_SMAG_PG0_Gx_ID12_SHIFT (12U) -#define CAAM_PX_SMAG_PG0_Gx_ID12(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID12_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID12_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID13_MASK (0x2000U) -#define CAAM_PX_SMAG_PG0_Gx_ID13_SHIFT (13U) -#define CAAM_PX_SMAG_PG0_Gx_ID13(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID13_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID13_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID14_MASK (0x4000U) -#define CAAM_PX_SMAG_PG0_Gx_ID14_SHIFT (14U) -#define CAAM_PX_SMAG_PG0_Gx_ID14(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID14_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID14_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID15_MASK (0x8000U) -#define CAAM_PX_SMAG_PG0_Gx_ID15_SHIFT (15U) -#define CAAM_PX_SMAG_PG0_Gx_ID15(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID15_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID15_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID16_MASK (0x10000U) -#define CAAM_PX_SMAG_PG0_Gx_ID16_SHIFT (16U) -#define CAAM_PX_SMAG_PG0_Gx_ID16(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID16_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID16_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID17_MASK (0x20000U) -#define CAAM_PX_SMAG_PG0_Gx_ID17_SHIFT (17U) -#define CAAM_PX_SMAG_PG0_Gx_ID17(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID17_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID17_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID18_MASK (0x40000U) -#define CAAM_PX_SMAG_PG0_Gx_ID18_SHIFT (18U) -#define CAAM_PX_SMAG_PG0_Gx_ID18(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID18_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID18_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID19_MASK (0x80000U) -#define CAAM_PX_SMAG_PG0_Gx_ID19_SHIFT (19U) -#define CAAM_PX_SMAG_PG0_Gx_ID19(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID19_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID19_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID20_MASK (0x100000U) -#define CAAM_PX_SMAG_PG0_Gx_ID20_SHIFT (20U) -#define CAAM_PX_SMAG_PG0_Gx_ID20(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID20_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID20_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID21_MASK (0x200000U) -#define CAAM_PX_SMAG_PG0_Gx_ID21_SHIFT (21U) -#define CAAM_PX_SMAG_PG0_Gx_ID21(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID21_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID21_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID22_MASK (0x400000U) -#define CAAM_PX_SMAG_PG0_Gx_ID22_SHIFT (22U) -#define CAAM_PX_SMAG_PG0_Gx_ID22(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID22_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID22_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID23_MASK (0x800000U) -#define CAAM_PX_SMAG_PG0_Gx_ID23_SHIFT (23U) -#define CAAM_PX_SMAG_PG0_Gx_ID23(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID23_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID23_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID24_MASK (0x1000000U) -#define CAAM_PX_SMAG_PG0_Gx_ID24_SHIFT (24U) -#define CAAM_PX_SMAG_PG0_Gx_ID24(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID24_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID24_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID25_MASK (0x2000000U) -#define CAAM_PX_SMAG_PG0_Gx_ID25_SHIFT (25U) -#define CAAM_PX_SMAG_PG0_Gx_ID25(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID25_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID25_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID26_MASK (0x4000000U) -#define CAAM_PX_SMAG_PG0_Gx_ID26_SHIFT (26U) -#define CAAM_PX_SMAG_PG0_Gx_ID26(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID26_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID26_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID27_MASK (0x8000000U) -#define CAAM_PX_SMAG_PG0_Gx_ID27_SHIFT (27U) -#define CAAM_PX_SMAG_PG0_Gx_ID27(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID27_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID27_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID28_MASK (0x10000000U) -#define CAAM_PX_SMAG_PG0_Gx_ID28_SHIFT (28U) -#define CAAM_PX_SMAG_PG0_Gx_ID28(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID28_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID28_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID29_MASK (0x20000000U) -#define CAAM_PX_SMAG_PG0_Gx_ID29_SHIFT (29U) -#define CAAM_PX_SMAG_PG0_Gx_ID29(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID29_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID29_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID30_MASK (0x40000000U) -#define CAAM_PX_SMAG_PG0_Gx_ID30_SHIFT (30U) -#define CAAM_PX_SMAG_PG0_Gx_ID30(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID30_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID30_MASK) -#define CAAM_PX_SMAG_PG0_Gx_ID31_MASK (0x80000000U) -#define CAAM_PX_SMAG_PG0_Gx_ID31_SHIFT (31U) -#define CAAM_PX_SMAG_PG0_Gx_ID31(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_PG0_Gx_ID31_SHIFT)) & CAAM_PX_SMAG_PG0_Gx_ID31_MASK) -/*! @} */ - -/* The count of CAAM_PX_SMAG_PG0 */ -#define CAAM_PX_SMAG_PG0_COUNT (16U) - -/* The count of CAAM_PX_SMAG_PG0 */ -#define CAAM_PX_SMAG_PG0_COUNT2 (2U) +/*! @name PX_SMAG2_PG0 - Secure Memory Access Group Registers */ +/*! @{ */ + +#define CAAM_PX_SMAG2_PG0_Gx_ID00_MASK (0x1U) +#define CAAM_PX_SMAG2_PG0_Gx_ID00_SHIFT (0U) +#define CAAM_PX_SMAG2_PG0_Gx_ID00(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID00_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID00_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID01_MASK (0x2U) +#define CAAM_PX_SMAG2_PG0_Gx_ID01_SHIFT (1U) +#define CAAM_PX_SMAG2_PG0_Gx_ID01(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID01_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID01_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID02_MASK (0x4U) +#define CAAM_PX_SMAG2_PG0_Gx_ID02_SHIFT (2U) +#define CAAM_PX_SMAG2_PG0_Gx_ID02(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID02_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID02_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID03_MASK (0x8U) +#define CAAM_PX_SMAG2_PG0_Gx_ID03_SHIFT (3U) +#define CAAM_PX_SMAG2_PG0_Gx_ID03(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID03_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID03_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID04_MASK (0x10U) +#define CAAM_PX_SMAG2_PG0_Gx_ID04_SHIFT (4U) +#define CAAM_PX_SMAG2_PG0_Gx_ID04(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID04_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID04_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID05_MASK (0x20U) +#define CAAM_PX_SMAG2_PG0_Gx_ID05_SHIFT (5U) +#define CAAM_PX_SMAG2_PG0_Gx_ID05(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID05_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID05_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID06_MASK (0x40U) +#define CAAM_PX_SMAG2_PG0_Gx_ID06_SHIFT (6U) +#define CAAM_PX_SMAG2_PG0_Gx_ID06(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID06_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID06_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID07_MASK (0x80U) +#define CAAM_PX_SMAG2_PG0_Gx_ID07_SHIFT (7U) +#define CAAM_PX_SMAG2_PG0_Gx_ID07(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID07_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID07_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID08_MASK (0x100U) +#define CAAM_PX_SMAG2_PG0_Gx_ID08_SHIFT (8U) +#define CAAM_PX_SMAG2_PG0_Gx_ID08(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID08_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID08_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID09_MASK (0x200U) +#define CAAM_PX_SMAG2_PG0_Gx_ID09_SHIFT (9U) +#define CAAM_PX_SMAG2_PG0_Gx_ID09(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID09_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID09_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID10_MASK (0x400U) +#define CAAM_PX_SMAG2_PG0_Gx_ID10_SHIFT (10U) +#define CAAM_PX_SMAG2_PG0_Gx_ID10(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID10_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID10_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID11_MASK (0x800U) +#define CAAM_PX_SMAG2_PG0_Gx_ID11_SHIFT (11U) +#define CAAM_PX_SMAG2_PG0_Gx_ID11(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID11_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID11_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID12_MASK (0x1000U) +#define CAAM_PX_SMAG2_PG0_Gx_ID12_SHIFT (12U) +#define CAAM_PX_SMAG2_PG0_Gx_ID12(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID12_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID12_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID13_MASK (0x2000U) +#define CAAM_PX_SMAG2_PG0_Gx_ID13_SHIFT (13U) +#define CAAM_PX_SMAG2_PG0_Gx_ID13(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID13_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID13_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID14_MASK (0x4000U) +#define CAAM_PX_SMAG2_PG0_Gx_ID14_SHIFT (14U) +#define CAAM_PX_SMAG2_PG0_Gx_ID14(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID14_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID14_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID15_MASK (0x8000U) +#define CAAM_PX_SMAG2_PG0_Gx_ID15_SHIFT (15U) +#define CAAM_PX_SMAG2_PG0_Gx_ID15(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID15_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID15_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID16_MASK (0x10000U) +#define CAAM_PX_SMAG2_PG0_Gx_ID16_SHIFT (16U) +#define CAAM_PX_SMAG2_PG0_Gx_ID16(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID16_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID16_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID17_MASK (0x20000U) +#define CAAM_PX_SMAG2_PG0_Gx_ID17_SHIFT (17U) +#define CAAM_PX_SMAG2_PG0_Gx_ID17(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID17_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID17_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID18_MASK (0x40000U) +#define CAAM_PX_SMAG2_PG0_Gx_ID18_SHIFT (18U) +#define CAAM_PX_SMAG2_PG0_Gx_ID18(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID18_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID18_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID19_MASK (0x80000U) +#define CAAM_PX_SMAG2_PG0_Gx_ID19_SHIFT (19U) +#define CAAM_PX_SMAG2_PG0_Gx_ID19(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID19_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID19_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID20_MASK (0x100000U) +#define CAAM_PX_SMAG2_PG0_Gx_ID20_SHIFT (20U) +#define CAAM_PX_SMAG2_PG0_Gx_ID20(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID20_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID20_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID21_MASK (0x200000U) +#define CAAM_PX_SMAG2_PG0_Gx_ID21_SHIFT (21U) +#define CAAM_PX_SMAG2_PG0_Gx_ID21(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID21_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID21_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID22_MASK (0x400000U) +#define CAAM_PX_SMAG2_PG0_Gx_ID22_SHIFT (22U) +#define CAAM_PX_SMAG2_PG0_Gx_ID22(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID22_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID22_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID23_MASK (0x800000U) +#define CAAM_PX_SMAG2_PG0_Gx_ID23_SHIFT (23U) +#define CAAM_PX_SMAG2_PG0_Gx_ID23(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID23_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID23_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID24_MASK (0x1000000U) +#define CAAM_PX_SMAG2_PG0_Gx_ID24_SHIFT (24U) +#define CAAM_PX_SMAG2_PG0_Gx_ID24(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID24_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID24_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID25_MASK (0x2000000U) +#define CAAM_PX_SMAG2_PG0_Gx_ID25_SHIFT (25U) +#define CAAM_PX_SMAG2_PG0_Gx_ID25(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID25_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID25_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID26_MASK (0x4000000U) +#define CAAM_PX_SMAG2_PG0_Gx_ID26_SHIFT (26U) +#define CAAM_PX_SMAG2_PG0_Gx_ID26(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID26_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID26_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID27_MASK (0x8000000U) +#define CAAM_PX_SMAG2_PG0_Gx_ID27_SHIFT (27U) +#define CAAM_PX_SMAG2_PG0_Gx_ID27(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID27_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID27_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID28_MASK (0x10000000U) +#define CAAM_PX_SMAG2_PG0_Gx_ID28_SHIFT (28U) +#define CAAM_PX_SMAG2_PG0_Gx_ID28(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID28_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID28_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID29_MASK (0x20000000U) +#define CAAM_PX_SMAG2_PG0_Gx_ID29_SHIFT (29U) +#define CAAM_PX_SMAG2_PG0_Gx_ID29(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID29_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID29_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID30_MASK (0x40000000U) +#define CAAM_PX_SMAG2_PG0_Gx_ID30_SHIFT (30U) +#define CAAM_PX_SMAG2_PG0_Gx_ID30(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID30_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID30_MASK) + +#define CAAM_PX_SMAG2_PG0_Gx_ID31_MASK (0x80000000U) +#define CAAM_PX_SMAG2_PG0_Gx_ID31_SHIFT (31U) +#define CAAM_PX_SMAG2_PG0_Gx_ID31(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID31_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID31_MASK) +/*! @} */ + +/* The count of CAAM_PX_SMAG2_PG0 */ +#define CAAM_PX_SMAG2_PG0_COUNT (16U) + +/*! @name PX_SMAG1_PG0 - Secure Memory Access Group Registers */ +/*! @{ */ + +#define CAAM_PX_SMAG1_PG0_Gx_ID00_MASK (0x1U) +#define CAAM_PX_SMAG1_PG0_Gx_ID00_SHIFT (0U) +#define CAAM_PX_SMAG1_PG0_Gx_ID00(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID00_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID00_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID01_MASK (0x2U) +#define CAAM_PX_SMAG1_PG0_Gx_ID01_SHIFT (1U) +#define CAAM_PX_SMAG1_PG0_Gx_ID01(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID01_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID01_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID02_MASK (0x4U) +#define CAAM_PX_SMAG1_PG0_Gx_ID02_SHIFT (2U) +#define CAAM_PX_SMAG1_PG0_Gx_ID02(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID02_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID02_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID03_MASK (0x8U) +#define CAAM_PX_SMAG1_PG0_Gx_ID03_SHIFT (3U) +#define CAAM_PX_SMAG1_PG0_Gx_ID03(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID03_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID03_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID04_MASK (0x10U) +#define CAAM_PX_SMAG1_PG0_Gx_ID04_SHIFT (4U) +#define CAAM_PX_SMAG1_PG0_Gx_ID04(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID04_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID04_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID05_MASK (0x20U) +#define CAAM_PX_SMAG1_PG0_Gx_ID05_SHIFT (5U) +#define CAAM_PX_SMAG1_PG0_Gx_ID05(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID05_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID05_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID06_MASK (0x40U) +#define CAAM_PX_SMAG1_PG0_Gx_ID06_SHIFT (6U) +#define CAAM_PX_SMAG1_PG0_Gx_ID06(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID06_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID06_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID07_MASK (0x80U) +#define CAAM_PX_SMAG1_PG0_Gx_ID07_SHIFT (7U) +#define CAAM_PX_SMAG1_PG0_Gx_ID07(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID07_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID07_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID08_MASK (0x100U) +#define CAAM_PX_SMAG1_PG0_Gx_ID08_SHIFT (8U) +#define CAAM_PX_SMAG1_PG0_Gx_ID08(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID08_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID08_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID09_MASK (0x200U) +#define CAAM_PX_SMAG1_PG0_Gx_ID09_SHIFT (9U) +#define CAAM_PX_SMAG1_PG0_Gx_ID09(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID09_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID09_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID10_MASK (0x400U) +#define CAAM_PX_SMAG1_PG0_Gx_ID10_SHIFT (10U) +#define CAAM_PX_SMAG1_PG0_Gx_ID10(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID10_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID10_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID11_MASK (0x800U) +#define CAAM_PX_SMAG1_PG0_Gx_ID11_SHIFT (11U) +#define CAAM_PX_SMAG1_PG0_Gx_ID11(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID11_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID11_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID12_MASK (0x1000U) +#define CAAM_PX_SMAG1_PG0_Gx_ID12_SHIFT (12U) +#define CAAM_PX_SMAG1_PG0_Gx_ID12(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID12_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID12_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID13_MASK (0x2000U) +#define CAAM_PX_SMAG1_PG0_Gx_ID13_SHIFT (13U) +#define CAAM_PX_SMAG1_PG0_Gx_ID13(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID13_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID13_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID14_MASK (0x4000U) +#define CAAM_PX_SMAG1_PG0_Gx_ID14_SHIFT (14U) +#define CAAM_PX_SMAG1_PG0_Gx_ID14(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID14_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID14_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID15_MASK (0x8000U) +#define CAAM_PX_SMAG1_PG0_Gx_ID15_SHIFT (15U) +#define CAAM_PX_SMAG1_PG0_Gx_ID15(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID15_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID15_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID16_MASK (0x10000U) +#define CAAM_PX_SMAG1_PG0_Gx_ID16_SHIFT (16U) +#define CAAM_PX_SMAG1_PG0_Gx_ID16(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID16_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID16_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID17_MASK (0x20000U) +#define CAAM_PX_SMAG1_PG0_Gx_ID17_SHIFT (17U) +#define CAAM_PX_SMAG1_PG0_Gx_ID17(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID17_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID17_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID18_MASK (0x40000U) +#define CAAM_PX_SMAG1_PG0_Gx_ID18_SHIFT (18U) +#define CAAM_PX_SMAG1_PG0_Gx_ID18(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID18_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID18_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID19_MASK (0x80000U) +#define CAAM_PX_SMAG1_PG0_Gx_ID19_SHIFT (19U) +#define CAAM_PX_SMAG1_PG0_Gx_ID19(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID19_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID19_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID20_MASK (0x100000U) +#define CAAM_PX_SMAG1_PG0_Gx_ID20_SHIFT (20U) +#define CAAM_PX_SMAG1_PG0_Gx_ID20(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID20_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID20_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID21_MASK (0x200000U) +#define CAAM_PX_SMAG1_PG0_Gx_ID21_SHIFT (21U) +#define CAAM_PX_SMAG1_PG0_Gx_ID21(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID21_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID21_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID22_MASK (0x400000U) +#define CAAM_PX_SMAG1_PG0_Gx_ID22_SHIFT (22U) +#define CAAM_PX_SMAG1_PG0_Gx_ID22(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID22_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID22_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID23_MASK (0x800000U) +#define CAAM_PX_SMAG1_PG0_Gx_ID23_SHIFT (23U) +#define CAAM_PX_SMAG1_PG0_Gx_ID23(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID23_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID23_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID24_MASK (0x1000000U) +#define CAAM_PX_SMAG1_PG0_Gx_ID24_SHIFT (24U) +#define CAAM_PX_SMAG1_PG0_Gx_ID24(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID24_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID24_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID25_MASK (0x2000000U) +#define CAAM_PX_SMAG1_PG0_Gx_ID25_SHIFT (25U) +#define CAAM_PX_SMAG1_PG0_Gx_ID25(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID25_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID25_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID26_MASK (0x4000000U) +#define CAAM_PX_SMAG1_PG0_Gx_ID26_SHIFT (26U) +#define CAAM_PX_SMAG1_PG0_Gx_ID26(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID26_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID26_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID27_MASK (0x8000000U) +#define CAAM_PX_SMAG1_PG0_Gx_ID27_SHIFT (27U) +#define CAAM_PX_SMAG1_PG0_Gx_ID27(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID27_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID27_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID28_MASK (0x10000000U) +#define CAAM_PX_SMAG1_PG0_Gx_ID28_SHIFT (28U) +#define CAAM_PX_SMAG1_PG0_Gx_ID28(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID28_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID28_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID29_MASK (0x20000000U) +#define CAAM_PX_SMAG1_PG0_Gx_ID29_SHIFT (29U) +#define CAAM_PX_SMAG1_PG0_Gx_ID29(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID29_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID29_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID30_MASK (0x40000000U) +#define CAAM_PX_SMAG1_PG0_Gx_ID30_SHIFT (30U) +#define CAAM_PX_SMAG1_PG0_Gx_ID30(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID30_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID30_MASK) + +#define CAAM_PX_SMAG1_PG0_Gx_ID31_MASK (0x80000000U) +#define CAAM_PX_SMAG1_PG0_Gx_ID31_SHIFT (31U) +#define CAAM_PX_SMAG1_PG0_Gx_ID31(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID31_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID31_MASK) +/*! @} */ + +/* The count of CAAM_PX_SMAG1_PG0 */ +#define CAAM_PX_SMAG1_PG0_COUNT (16U) /*! @name REIS - Recoverable Error Interrupt Status */ /*! @{ */ + #define CAAM_REIS_CWDE_MASK (0x1U) #define CAAM_REIS_CWDE_SHIFT (0U) #define CAAM_REIS_CWDE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_CWDE_SHIFT)) & CAAM_REIS_CWDE_MASK) + #define CAAM_REIS_RBAE_MASK (0x10000U) #define CAAM_REIS_RBAE_SHIFT (16U) #define CAAM_REIS_RBAE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_RBAE_SHIFT)) & CAAM_REIS_RBAE_MASK) + #define CAAM_REIS_JBAE0_MASK (0x1000000U) #define CAAM_REIS_JBAE0_SHIFT (24U) #define CAAM_REIS_JBAE0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_JBAE0_SHIFT)) & CAAM_REIS_JBAE0_MASK) + #define CAAM_REIS_JBAE1_MASK (0x2000000U) #define CAAM_REIS_JBAE1_SHIFT (25U) #define CAAM_REIS_JBAE1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_JBAE1_SHIFT)) & CAAM_REIS_JBAE1_MASK) + #define CAAM_REIS_JBAE2_MASK (0x4000000U) #define CAAM_REIS_JBAE2_SHIFT (26U) #define CAAM_REIS_JBAE2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_JBAE2_SHIFT)) & CAAM_REIS_JBAE2_MASK) + #define CAAM_REIS_JBAE3_MASK (0x8000000U) #define CAAM_REIS_JBAE3_SHIFT (27U) #define CAAM_REIS_JBAE3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_JBAE3_SHIFT)) & CAAM_REIS_JBAE3_MASK) @@ -12383,21 +13784,27 @@ typedef struct { /*! @name REIE - Recoverable Error Interrupt Enable */ /*! @{ */ + #define CAAM_REIE_CWDE_MASK (0x1U) #define CAAM_REIE_CWDE_SHIFT (0U) #define CAAM_REIE_CWDE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_CWDE_SHIFT)) & CAAM_REIE_CWDE_MASK) + #define CAAM_REIE_RBAE_MASK (0x10000U) #define CAAM_REIE_RBAE_SHIFT (16U) #define CAAM_REIE_RBAE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_RBAE_SHIFT)) & CAAM_REIE_RBAE_MASK) + #define CAAM_REIE_JBAE0_MASK (0x1000000U) #define CAAM_REIE_JBAE0_SHIFT (24U) #define CAAM_REIE_JBAE0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_JBAE0_SHIFT)) & CAAM_REIE_JBAE0_MASK) + #define CAAM_REIE_JBAE1_MASK (0x2000000U) #define CAAM_REIE_JBAE1_SHIFT (25U) #define CAAM_REIE_JBAE1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_JBAE1_SHIFT)) & CAAM_REIE_JBAE1_MASK) + #define CAAM_REIE_JBAE2_MASK (0x4000000U) #define CAAM_REIE_JBAE2_SHIFT (26U) #define CAAM_REIE_JBAE2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_JBAE2_SHIFT)) & CAAM_REIE_JBAE2_MASK) + #define CAAM_REIE_JBAE3_MASK (0x8000000U) #define CAAM_REIE_JBAE3_SHIFT (27U) #define CAAM_REIE_JBAE3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_JBAE3_SHIFT)) & CAAM_REIE_JBAE3_MASK) @@ -12405,21 +13812,27 @@ typedef struct { /*! @name REIF - Recoverable Error Interrupt Force */ /*! @{ */ + #define CAAM_REIF_CWDE_MASK (0x1U) #define CAAM_REIF_CWDE_SHIFT (0U) #define CAAM_REIF_CWDE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_CWDE_SHIFT)) & CAAM_REIF_CWDE_MASK) + #define CAAM_REIF_RBAE_MASK (0x10000U) #define CAAM_REIF_RBAE_SHIFT (16U) #define CAAM_REIF_RBAE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_RBAE_SHIFT)) & CAAM_REIF_RBAE_MASK) + #define CAAM_REIF_JBAE0_MASK (0x1000000U) #define CAAM_REIF_JBAE0_SHIFT (24U) #define CAAM_REIF_JBAE0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_JBAE0_SHIFT)) & CAAM_REIF_JBAE0_MASK) + #define CAAM_REIF_JBAE1_MASK (0x2000000U) #define CAAM_REIF_JBAE1_SHIFT (25U) #define CAAM_REIF_JBAE1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_JBAE1_SHIFT)) & CAAM_REIF_JBAE1_MASK) + #define CAAM_REIF_JBAE2_MASK (0x4000000U) #define CAAM_REIF_JBAE2_SHIFT (26U) #define CAAM_REIF_JBAE2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_JBAE2_SHIFT)) & CAAM_REIF_JBAE2_MASK) + #define CAAM_REIF_JBAE3_MASK (0x8000000U) #define CAAM_REIF_JBAE3_SHIFT (27U) #define CAAM_REIF_JBAE3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_JBAE3_SHIFT)) & CAAM_REIF_JBAE3_MASK) @@ -12427,6 +13840,7 @@ typedef struct { /*! @name REIH - Recoverable Error Interrupt Halt */ /*! @{ */ + #define CAAM_REIH_CWDE_MASK (0x1U) #define CAAM_REIH_CWDE_SHIFT (0U) /*! CWDE @@ -12434,6 +13848,7 @@ typedef struct { * 0b1..Halt CAAM if CAAM watchdog expired.. */ #define CAAM_REIH_CWDE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_CWDE_SHIFT)) & CAAM_REIH_CWDE_MASK) + #define CAAM_REIH_RBAE_MASK (0x10000U) #define CAAM_REIH_RBAE_SHIFT (16U) /*! RBAE @@ -12441,6 +13856,7 @@ typedef struct { * 0b1..Halt CAAM if RTIC-initiated job execution caused bus access error. */ #define CAAM_REIH_RBAE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_RBAE_SHIFT)) & CAAM_REIH_RBAE_MASK) + #define CAAM_REIH_JBAE0_MASK (0x1000000U) #define CAAM_REIH_JBAE0_SHIFT (24U) /*! JBAE0 @@ -12448,6 +13864,7 @@ typedef struct { * 0b1..Halt CAAM if JR0-initiated job execution caused bus access error. */ #define CAAM_REIH_JBAE0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_JBAE0_SHIFT)) & CAAM_REIH_JBAE0_MASK) + #define CAAM_REIH_JBAE1_MASK (0x2000000U) #define CAAM_REIH_JBAE1_SHIFT (25U) /*! JBAE1 @@ -12455,6 +13872,7 @@ typedef struct { * 0b1..Halt CAAM if JR1-initiated job execution caused bus access error. */ #define CAAM_REIH_JBAE1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_JBAE1_SHIFT)) & CAAM_REIH_JBAE1_MASK) + #define CAAM_REIH_JBAE2_MASK (0x4000000U) #define CAAM_REIH_JBAE2_SHIFT (26U) /*! JBAE2 @@ -12462,6 +13880,7 @@ typedef struct { * 0b1..Halt CAAM if JR2-initiated job execution caused bus access error. */ #define CAAM_REIH_JBAE2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_JBAE2_SHIFT)) & CAAM_REIH_JBAE2_MASK) + #define CAAM_REIH_JBAE3_MASK (0x8000000U) #define CAAM_REIH_JBAE3_SHIFT (27U) /*! JBAE3 @@ -12473,6 +13892,7 @@ typedef struct { /*! @name SMWPJRR - Secure Memory Write Protect Job Ring Register */ /*! @{ */ + #define CAAM_SMWPJRR_SMR_WP_JRa_MASK (0x1U) #define CAAM_SMWPJRR_SMR_WP_JRa_SHIFT (0U) #define CAAM_SMWPJRR_SMR_WP_JRa(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMWPJRR_SMR_WP_JRa_SHIFT)) & CAAM_SMWPJRR_SMR_WP_JRa_MASK) @@ -12483,12 +13903,15 @@ typedef struct { /*! @name SMCR_PG0 - Secure Memory Command Register */ /*! @{ */ + #define CAAM_SMCR_PG0_CMD_MASK (0xFU) #define CAAM_SMCR_PG0_CMD_SHIFT (0U) #define CAAM_SMCR_PG0_CMD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_PG0_CMD_SHIFT)) & CAAM_SMCR_PG0_CMD_MASK) + #define CAAM_SMCR_PG0_PRTN_MASK (0xF00U) #define CAAM_SMCR_PG0_PRTN_SHIFT (8U) #define CAAM_SMCR_PG0_PRTN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_PG0_PRTN_SHIFT)) & CAAM_SMCR_PG0_PRTN_MASK) + #define CAAM_SMCR_PG0_PAGE_MASK (0xFFFF0000U) #define CAAM_SMCR_PG0_PAGE_SHIFT (16U) #define CAAM_SMCR_PG0_PAGE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_PG0_PAGE_SHIFT)) & CAAM_SMCR_PG0_PAGE_MASK) @@ -12496,9 +13919,11 @@ typedef struct { /*! @name SMCSR_PG0 - Secure Memory Command Status Register */ /*! @{ */ + #define CAAM_SMCSR_PG0_PRTN_MASK (0xFU) #define CAAM_SMCSR_PG0_PRTN_SHIFT (0U) #define CAAM_SMCSR_PG0_PRTN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_PRTN_SHIFT)) & CAAM_SMCSR_PG0_PRTN_MASK) + #define CAAM_SMCSR_PG0_PO_MASK (0xC0U) #define CAAM_SMCSR_PG0_PO_SHIFT (6U) /*! PO @@ -12511,9 +13936,11 @@ typedef struct { * upon de-allocation. */ #define CAAM_SMCSR_PG0_PO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_PO_SHIFT)) & CAAM_SMCSR_PG0_PO_MASK) + #define CAAM_SMCSR_PG0_AERR_MASK (0x3000U) #define CAAM_SMCSR_PG0_AERR_SHIFT (12U) #define CAAM_SMCSR_PG0_AERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_AERR_SHIFT)) & CAAM_SMCSR_PG0_AERR_MASK) + #define CAAM_SMCSR_PG0_CERR_MASK (0xC000U) #define CAAM_SMCSR_PG0_CERR_SHIFT (14U) /*! CERR @@ -12524,6 +13951,7 @@ typedef struct { * command completed. The additional command was ignored. */ #define CAAM_SMCSR_PG0_CERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_CERR_SHIFT)) & CAAM_SMCSR_PG0_CERR_MASK) + #define CAAM_SMCSR_PG0_PAGE_MASK (0xFFF0000U) #define CAAM_SMCSR_PG0_PAGE_SHIFT (16U) #define CAAM_SMCSR_PG0_PAGE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_PAGE_SHIFT)) & CAAM_SMCSR_PG0_PAGE_MASK) @@ -12531,12 +13959,15 @@ typedef struct { /*! @name CAAMVID_MS_TRAD - CAAM Version ID Register, most-significant half */ /*! @{ */ + #define CAAM_CAAMVID_MS_TRAD_MIN_REV_MASK (0xFFU) #define CAAM_CAAMVID_MS_TRAD_MIN_REV_SHIFT (0U) #define CAAM_CAAMVID_MS_TRAD_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_MS_TRAD_MIN_REV_SHIFT)) & CAAM_CAAMVID_MS_TRAD_MIN_REV_MASK) + #define CAAM_CAAMVID_MS_TRAD_MAJ_REV_MASK (0xFF00U) #define CAAM_CAAMVID_MS_TRAD_MAJ_REV_SHIFT (8U) #define CAAM_CAAMVID_MS_TRAD_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_MS_TRAD_MAJ_REV_SHIFT)) & CAAM_CAAMVID_MS_TRAD_MAJ_REV_MASK) + #define CAAM_CAAMVID_MS_TRAD_IP_ID_MASK (0xFFFF0000U) #define CAAM_CAAMVID_MS_TRAD_IP_ID_SHIFT (16U) #define CAAM_CAAMVID_MS_TRAD_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_MS_TRAD_IP_ID_SHIFT)) & CAAM_CAAMVID_MS_TRAD_IP_ID_MASK) @@ -12544,15 +13975,19 @@ typedef struct { /*! @name CAAMVID_LS_TRAD - CAAM Version ID Register, least-significant half */ /*! @{ */ + #define CAAM_CAAMVID_LS_TRAD_CONFIG_OPT_MASK (0xFFU) #define CAAM_CAAMVID_LS_TRAD_CONFIG_OPT_SHIFT (0U) #define CAAM_CAAMVID_LS_TRAD_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_LS_TRAD_CONFIG_OPT_SHIFT)) & CAAM_CAAMVID_LS_TRAD_CONFIG_OPT_MASK) + #define CAAM_CAAMVID_LS_TRAD_ECO_REV_MASK (0xFF00U) #define CAAM_CAAMVID_LS_TRAD_ECO_REV_SHIFT (8U) #define CAAM_CAAMVID_LS_TRAD_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_LS_TRAD_ECO_REV_SHIFT)) & CAAM_CAAMVID_LS_TRAD_ECO_REV_MASK) + #define CAAM_CAAMVID_LS_TRAD_INTG_OPT_MASK (0xFF0000U) #define CAAM_CAAMVID_LS_TRAD_INTG_OPT_SHIFT (16U) #define CAAM_CAAMVID_LS_TRAD_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_LS_TRAD_INTG_OPT_SHIFT)) & CAAM_CAAMVID_LS_TRAD_INTG_OPT_MASK) + #define CAAM_CAAMVID_LS_TRAD_COMPILE_OPT_MASK (0xFF000000U) #define CAAM_CAAMVID_LS_TRAD_COMPILE_OPT_SHIFT (24U) #define CAAM_CAAMVID_LS_TRAD_COMPILE_OPT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_LS_TRAD_COMPILE_OPT_SHIFT)) & CAAM_CAAMVID_LS_TRAD_COMPILE_OPT_MASK) @@ -12560,6 +13995,7 @@ typedef struct { /*! @name HT_JD_ADDR - Holding Tank 0 Job Descriptor Address */ /*! @{ */ + #define CAAM_HT_JD_ADDR_JD_ADDR_MASK (0xFFFFFFFFFU) #define CAAM_HT_JD_ADDR_JD_ADDR_SHIFT (0U) #define CAAM_HT_JD_ADDR_JD_ADDR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_HT_JD_ADDR_JD_ADDR_SHIFT)) & CAAM_HT_JD_ADDR_JD_ADDR_MASK) @@ -12570,6 +14006,7 @@ typedef struct { /*! @name HT_SD_ADDR - Holding Tank 0 Shared Descriptor Address */ /*! @{ */ + #define CAAM_HT_SD_ADDR_SD_ADDR_MASK (0xFFFFFFFFFU) #define CAAM_HT_SD_ADDR_SD_ADDR_SHIFT (0U) #define CAAM_HT_SD_ADDR_SD_ADDR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_HT_SD_ADDR_SD_ADDR_SHIFT)) & CAAM_HT_SD_ADDR_SD_ADDR_MASK) @@ -12580,9 +14017,11 @@ typedef struct { /*! @name HT_JQ_CTRL_MS - Holding Tank 0 Job Queue Control, most-significant half */ /*! @{ */ + #define CAAM_HT_JQ_CTRL_MS_ID_MASK (0x7U) #define CAAM_HT_JQ_CTRL_MS_ID_SHIFT (0U) #define CAAM_HT_JQ_CTRL_MS_ID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_ID_SHIFT)) & CAAM_HT_JQ_CTRL_MS_ID_MASK) + #define CAAM_HT_JQ_CTRL_MS_SRC_MASK (0x700U) #define CAAM_HT_JQ_CTRL_MS_SRC_SHIFT (8U) /*! SRC @@ -12596,6 +14035,7 @@ typedef struct { * 0b111..Reserved */ #define CAAM_HT_JQ_CTRL_MS_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_SRC_SHIFT)) & CAAM_HT_JQ_CTRL_MS_SRC_MASK) + #define CAAM_HT_JQ_CTRL_MS_JDDS_MASK (0x4000U) #define CAAM_HT_JQ_CTRL_MS_JDDS_SHIFT (14U) /*! JDDS @@ -12603,12 +14043,15 @@ typedef struct { * 0b0..Non-SEQ DID */ #define CAAM_HT_JQ_CTRL_MS_JDDS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_JDDS_SHIFT)) & CAAM_HT_JQ_CTRL_MS_JDDS_MASK) + #define CAAM_HT_JQ_CTRL_MS_AMTD_MASK (0x8000U) #define CAAM_HT_JQ_CTRL_MS_AMTD_SHIFT (15U) #define CAAM_HT_JQ_CTRL_MS_AMTD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_AMTD_SHIFT)) & CAAM_HT_JQ_CTRL_MS_AMTD_MASK) + #define CAAM_HT_JQ_CTRL_MS_SOB_MASK (0x10000U) #define CAAM_HT_JQ_CTRL_MS_SOB_SHIFT (16U) #define CAAM_HT_JQ_CTRL_MS_SOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_SOB_SHIFT)) & CAAM_HT_JQ_CTRL_MS_SOB_MASK) + #define CAAM_HT_JQ_CTRL_MS_HT_ERROR_MASK (0x60000U) #define CAAM_HT_JQ_CTRL_MS_HT_ERROR_SHIFT (17U) /*! HT_ERROR @@ -12618,6 +14061,7 @@ typedef struct { * 0b11..reserved */ #define CAAM_HT_JQ_CTRL_MS_HT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_HT_ERROR_SHIFT)) & CAAM_HT_JQ_CTRL_MS_HT_ERROR_MASK) + #define CAAM_HT_JQ_CTRL_MS_DWORD_SWAP_MASK (0x80000U) #define CAAM_HT_JQ_CTRL_MS_DWORD_SWAP_SHIFT (19U) /*! DWORD_SWAP @@ -12625,9 +14069,11 @@ typedef struct { * 0b1..DWords are in the order least-significant word, most-significant word. */ #define CAAM_HT_JQ_CTRL_MS_DWORD_SWAP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_DWORD_SWAP_SHIFT)) & CAAM_HT_JQ_CTRL_MS_DWORD_SWAP_MASK) + #define CAAM_HT_JQ_CTRL_MS_SHR_FROM_MASK (0x7C00000U) #define CAAM_HT_JQ_CTRL_MS_SHR_FROM_SHIFT (22U) #define CAAM_HT_JQ_CTRL_MS_SHR_FROM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_SHR_FROM_SHIFT)) & CAAM_HT_JQ_CTRL_MS_SHR_FROM_MASK) + #define CAAM_HT_JQ_CTRL_MS_ILE_MASK (0x8000000U) #define CAAM_HT_JQ_CTRL_MS_ILE_SHIFT (27U) /*! ILE @@ -12635,9 +14081,11 @@ typedef struct { * 0b1..Byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer. */ #define CAAM_HT_JQ_CTRL_MS_ILE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_ILE_SHIFT)) & CAAM_HT_JQ_CTRL_MS_ILE_MASK) + #define CAAM_HT_JQ_CTRL_MS_FOUR_MASK (0x10000000U) #define CAAM_HT_JQ_CTRL_MS_FOUR_SHIFT (28U) #define CAAM_HT_JQ_CTRL_MS_FOUR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_FOUR_SHIFT)) & CAAM_HT_JQ_CTRL_MS_FOUR_MASK) + #define CAAM_HT_JQ_CTRL_MS_WHL_MASK (0x20000000U) #define CAAM_HT_JQ_CTRL_MS_WHL_SHIFT (29U) #define CAAM_HT_JQ_CTRL_MS_WHL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_WHL_SHIFT)) & CAAM_HT_JQ_CTRL_MS_WHL_MASK) @@ -12648,9 +14096,11 @@ typedef struct { /*! @name HT_JQ_CTRL_LS - Holding Tank 0 Job Queue Control, least-significant half */ /*! @{ */ + #define CAAM_HT_JQ_CTRL_LS_PRIM_DID_MASK (0xFU) #define CAAM_HT_JQ_CTRL_LS_PRIM_DID_SHIFT (0U) #define CAAM_HT_JQ_CTRL_LS_PRIM_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_PRIM_DID_SHIFT)) & CAAM_HT_JQ_CTRL_LS_PRIM_DID_MASK) + #define CAAM_HT_JQ_CTRL_LS_PRIM_TZ_MASK (0x10U) #define CAAM_HT_JQ_CTRL_LS_PRIM_TZ_SHIFT (4U) /*! PRIM_TZ @@ -12658,12 +14108,15 @@ typedef struct { * 0b1..TrustZone SecureWorld */ #define CAAM_HT_JQ_CTRL_LS_PRIM_TZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_PRIM_TZ_SHIFT)) & CAAM_HT_JQ_CTRL_LS_PRIM_TZ_MASK) + #define CAAM_HT_JQ_CTRL_LS_PRIM_ICID_MASK (0xFFE0U) #define CAAM_HT_JQ_CTRL_LS_PRIM_ICID_SHIFT (5U) #define CAAM_HT_JQ_CTRL_LS_PRIM_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_PRIM_ICID_SHIFT)) & CAAM_HT_JQ_CTRL_LS_PRIM_ICID_MASK) + #define CAAM_HT_JQ_CTRL_LS_OUT_DID_MASK (0xF0000U) #define CAAM_HT_JQ_CTRL_LS_OUT_DID_SHIFT (16U) #define CAAM_HT_JQ_CTRL_LS_OUT_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_OUT_DID_SHIFT)) & CAAM_HT_JQ_CTRL_LS_OUT_DID_MASK) + #define CAAM_HT_JQ_CTRL_LS_OUT_ICID_MASK (0xFFE00000U) #define CAAM_HT_JQ_CTRL_LS_OUT_ICID_SHIFT (21U) #define CAAM_HT_JQ_CTRL_LS_OUT_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_OUT_ICID_SHIFT)) & CAAM_HT_JQ_CTRL_LS_OUT_ICID_MASK) @@ -12674,12 +14127,15 @@ typedef struct { /*! @name HT_STATUS - Holding Tank Status */ /*! @{ */ + #define CAAM_HT_STATUS_PEND_0_MASK (0x1U) #define CAAM_HT_STATUS_PEND_0_SHIFT (0U) #define CAAM_HT_STATUS_PEND_0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_STATUS_PEND_0_SHIFT)) & CAAM_HT_STATUS_PEND_0_MASK) + #define CAAM_HT_STATUS_IN_USE_MASK (0x40000000U) #define CAAM_HT_STATUS_IN_USE_SHIFT (30U) #define CAAM_HT_STATUS_IN_USE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_STATUS_IN_USE_SHIFT)) & CAAM_HT_STATUS_IN_USE_MASK) + #define CAAM_HT_STATUS_BC_MASK (0x80000000U) #define CAAM_HT_STATUS_BC_SHIFT (31U) #define CAAM_HT_STATUS_BC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_STATUS_BC_SHIFT)) & CAAM_HT_STATUS_BC_MASK) @@ -12690,9 +14146,11 @@ typedef struct { /*! @name JQ_DEBUG_SEL - Job Queue Debug Select Register */ /*! @{ */ + #define CAAM_JQ_DEBUG_SEL_HT_SEL_MASK (0x1U) #define CAAM_JQ_DEBUG_SEL_HT_SEL_SHIFT (0U) #define CAAM_JQ_DEBUG_SEL_HT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JQ_DEBUG_SEL_HT_SEL_SHIFT)) & CAAM_JQ_DEBUG_SEL_HT_SEL_MASK) + #define CAAM_JQ_DEBUG_SEL_JOB_ID_MASK (0x70000U) #define CAAM_JQ_DEBUG_SEL_JOB_ID_SHIFT (16U) #define CAAM_JQ_DEBUG_SEL_JOB_ID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JQ_DEBUG_SEL_JOB_ID_SHIFT)) & CAAM_JQ_DEBUG_SEL_JOB_ID_MASK) @@ -12700,15 +14158,19 @@ typedef struct { /*! @name JRJIDU_LS - Job Ring Job IDs in Use Register, least-significant half */ /*! @{ */ + #define CAAM_JRJIDU_LS_JID00_MASK (0x1U) #define CAAM_JRJIDU_LS_JID00_SHIFT (0U) #define CAAM_JRJIDU_LS_JID00(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJIDU_LS_JID00_SHIFT)) & CAAM_JRJIDU_LS_JID00_MASK) + #define CAAM_JRJIDU_LS_JID01_MASK (0x2U) #define CAAM_JRJIDU_LS_JID01_SHIFT (1U) #define CAAM_JRJIDU_LS_JID01(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJIDU_LS_JID01_SHIFT)) & CAAM_JRJIDU_LS_JID01_MASK) + #define CAAM_JRJIDU_LS_JID02_MASK (0x4U) #define CAAM_JRJIDU_LS_JID02_SHIFT (2U) #define CAAM_JRJIDU_LS_JID02(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJIDU_LS_JID02_SHIFT)) & CAAM_JRJIDU_LS_JID02_MASK) + #define CAAM_JRJIDU_LS_JID03_MASK (0x8U) #define CAAM_JRJIDU_LS_JID03_SHIFT (3U) #define CAAM_JRJIDU_LS_JID03(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJIDU_LS_JID03_SHIFT)) & CAAM_JRJIDU_LS_JID03_MASK) @@ -12716,6 +14178,7 @@ typedef struct { /*! @name JRJDJIFBC - Job Ring Job-Done Job ID FIFO BC */ /*! @{ */ + #define CAAM_JRJDJIFBC_BC_MASK (0x80000000U) #define CAAM_JRJDJIFBC_BC_SHIFT (31U) #define CAAM_JRJDJIFBC_BC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJDJIFBC_BC_SHIFT)) & CAAM_JRJDJIFBC_BC_MASK) @@ -12723,6 +14186,7 @@ typedef struct { /*! @name JRJDJIF - Job Ring Job-Done Job ID FIFO */ /*! @{ */ + #define CAAM_JRJDJIF_JOB_ID_ENTRY_MASK (0x7U) #define CAAM_JRJDJIF_JOB_ID_ENTRY_SHIFT (0U) #define CAAM_JRJDJIF_JOB_ID_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJDJIF_JOB_ID_ENTRY_SHIFT)) & CAAM_JRJDJIF_JOB_ID_ENTRY_MASK) @@ -12730,9 +14194,11 @@ typedef struct { /*! @name JRJDS1 - Job Ring Job-Done Source 1 */ /*! @{ */ + #define CAAM_JRJDS1_SRC_MASK (0x3U) #define CAAM_JRJDS1_SRC_SHIFT (0U) #define CAAM_JRJDS1_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJDS1_SRC_SHIFT)) & CAAM_JRJDS1_SRC_MASK) + #define CAAM_JRJDS1_VALID_MASK (0x80000000U) #define CAAM_JRJDS1_VALID_SHIFT (31U) #define CAAM_JRJDS1_VALID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJDS1_VALID_SHIFT)) & CAAM_JRJDS1_VALID_MASK) @@ -12740,6 +14206,7 @@ typedef struct { /*! @name JRJDDA - Job Ring Job-Done Descriptor Address 0 Register */ /*! @{ */ + #define CAAM_JRJDDA_JD_ADDR_MASK (0xFFFFFFFFFU) #define CAAM_JRJDDA_JD_ADDR_SHIFT (0U) #define CAAM_JRJDDA_JD_ADDR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_JRJDDA_JD_ADDR_SHIFT)) & CAAM_JRJDDA_JD_ADDR_MASK) @@ -12750,21 +14217,27 @@ typedef struct { /*! @name CRNR_MS - CHA Revision Number Register, most-significant half */ /*! @{ */ + #define CAAM_CRNR_MS_CRCRN_MASK (0xFU) #define CAAM_CRNR_MS_CRCRN_SHIFT (0U) #define CAAM_CRNR_MS_CRCRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_CRCRN_SHIFT)) & CAAM_CRNR_MS_CRCRN_MASK) + #define CAAM_CRNR_MS_SNW9RN_MASK (0xF0U) #define CAAM_CRNR_MS_SNW9RN_SHIFT (4U) #define CAAM_CRNR_MS_SNW9RN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_SNW9RN_SHIFT)) & CAAM_CRNR_MS_SNW9RN_MASK) + #define CAAM_CRNR_MS_ZERN_MASK (0xF00U) #define CAAM_CRNR_MS_ZERN_SHIFT (8U) #define CAAM_CRNR_MS_ZERN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_ZERN_SHIFT)) & CAAM_CRNR_MS_ZERN_MASK) + #define CAAM_CRNR_MS_ZARN_MASK (0xF000U) #define CAAM_CRNR_MS_ZARN_SHIFT (12U) #define CAAM_CRNR_MS_ZARN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_ZARN_SHIFT)) & CAAM_CRNR_MS_ZARN_MASK) + #define CAAM_CRNR_MS_DECORN_MASK (0xF000000U) #define CAAM_CRNR_MS_DECORN_SHIFT (24U) #define CAAM_CRNR_MS_DECORN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_DECORN_SHIFT)) & CAAM_CRNR_MS_DECORN_MASK) + #define CAAM_CRNR_MS_JRRN_MASK (0xF0000000U) #define CAAM_CRNR_MS_JRRN_SHIFT (28U) #define CAAM_CRNR_MS_JRRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_JRRN_SHIFT)) & CAAM_CRNR_MS_JRRN_MASK) @@ -12772,24 +14245,31 @@ typedef struct { /*! @name CRNR_LS - CHA Revision Number Register, least-significant half */ /*! @{ */ + #define CAAM_CRNR_LS_AESRN_MASK (0xFU) #define CAAM_CRNR_LS_AESRN_SHIFT (0U) #define CAAM_CRNR_LS_AESRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_AESRN_SHIFT)) & CAAM_CRNR_LS_AESRN_MASK) + #define CAAM_CRNR_LS_DESRN_MASK (0xF0U) #define CAAM_CRNR_LS_DESRN_SHIFT (4U) #define CAAM_CRNR_LS_DESRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_DESRN_SHIFT)) & CAAM_CRNR_LS_DESRN_MASK) + #define CAAM_CRNR_LS_MDRN_MASK (0xF000U) #define CAAM_CRNR_LS_MDRN_SHIFT (12U) #define CAAM_CRNR_LS_MDRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_MDRN_SHIFT)) & CAAM_CRNR_LS_MDRN_MASK) + #define CAAM_CRNR_LS_RNGRN_MASK (0xF0000U) #define CAAM_CRNR_LS_RNGRN_SHIFT (16U) #define CAAM_CRNR_LS_RNGRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_RNGRN_SHIFT)) & CAAM_CRNR_LS_RNGRN_MASK) + #define CAAM_CRNR_LS_SNW8RN_MASK (0xF00000U) #define CAAM_CRNR_LS_SNW8RN_SHIFT (20U) #define CAAM_CRNR_LS_SNW8RN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_SNW8RN_SHIFT)) & CAAM_CRNR_LS_SNW8RN_MASK) + #define CAAM_CRNR_LS_KASRN_MASK (0xF000000U) #define CAAM_CRNR_LS_KASRN_SHIFT (24U) #define CAAM_CRNR_LS_KASRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_KASRN_SHIFT)) & CAAM_CRNR_LS_KASRN_MASK) + #define CAAM_CRNR_LS_PKRN_MASK (0xF0000000U) #define CAAM_CRNR_LS_PKRN_SHIFT (28U) /*! PKRN @@ -12803,60 +14283,79 @@ typedef struct { /*! @name CTPR_MS - Compile Time Parameters Register, most-significant half */ /*! @{ */ + #define CAAM_CTPR_MS_VIRT_EN_INCL_MASK (0x1U) #define CAAM_CTPR_MS_VIRT_EN_INCL_SHIFT (0U) #define CAAM_CTPR_MS_VIRT_EN_INCL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_VIRT_EN_INCL_SHIFT)) & CAAM_CTPR_MS_VIRT_EN_INCL_MASK) + #define CAAM_CTPR_MS_VIRT_EN_POR_VALUE_MASK (0x2U) #define CAAM_CTPR_MS_VIRT_EN_POR_VALUE_SHIFT (1U) #define CAAM_CTPR_MS_VIRT_EN_POR_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_VIRT_EN_POR_VALUE_SHIFT)) & CAAM_CTPR_MS_VIRT_EN_POR_VALUE_MASK) + #define CAAM_CTPR_MS_REG_PG_SIZE_MASK (0x10U) #define CAAM_CTPR_MS_REG_PG_SIZE_SHIFT (4U) #define CAAM_CTPR_MS_REG_PG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_REG_PG_SIZE_SHIFT)) & CAAM_CTPR_MS_REG_PG_SIZE_MASK) + #define CAAM_CTPR_MS_RNG_I_MASK (0x700U) #define CAAM_CTPR_MS_RNG_I_SHIFT (8U) #define CAAM_CTPR_MS_RNG_I(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_RNG_I_SHIFT)) & CAAM_CTPR_MS_RNG_I_MASK) + #define CAAM_CTPR_MS_AI_INCL_MASK (0x800U) #define CAAM_CTPR_MS_AI_INCL_SHIFT (11U) #define CAAM_CTPR_MS_AI_INCL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_AI_INCL_SHIFT)) & CAAM_CTPR_MS_AI_INCL_MASK) + #define CAAM_CTPR_MS_DPAA2_MASK (0x2000U) #define CAAM_CTPR_MS_DPAA2_SHIFT (13U) #define CAAM_CTPR_MS_DPAA2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_DPAA2_SHIFT)) & CAAM_CTPR_MS_DPAA2_MASK) + #define CAAM_CTPR_MS_IP_CLK_MASK (0x4000U) #define CAAM_CTPR_MS_IP_CLK_SHIFT (14U) #define CAAM_CTPR_MS_IP_CLK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_IP_CLK_SHIFT)) & CAAM_CTPR_MS_IP_CLK_MASK) + #define CAAM_CTPR_MS_MCFG_BURST_MASK (0x10000U) #define CAAM_CTPR_MS_MCFG_BURST_SHIFT (16U) #define CAAM_CTPR_MS_MCFG_BURST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_MCFG_BURST_SHIFT)) & CAAM_CTPR_MS_MCFG_BURST_MASK) + #define CAAM_CTPR_MS_MCFG_PS_MASK (0x20000U) #define CAAM_CTPR_MS_MCFG_PS_SHIFT (17U) #define CAAM_CTPR_MS_MCFG_PS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_MCFG_PS_SHIFT)) & CAAM_CTPR_MS_MCFG_PS_MASK) + #define CAAM_CTPR_MS_SG8_MASK (0x40000U) #define CAAM_CTPR_MS_SG8_SHIFT (18U) #define CAAM_CTPR_MS_SG8(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_SG8_SHIFT)) & CAAM_CTPR_MS_SG8_MASK) + #define CAAM_CTPR_MS_PM_EVT_BUS_MASK (0x80000U) #define CAAM_CTPR_MS_PM_EVT_BUS_SHIFT (19U) #define CAAM_CTPR_MS_PM_EVT_BUS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_PM_EVT_BUS_SHIFT)) & CAAM_CTPR_MS_PM_EVT_BUS_MASK) + #define CAAM_CTPR_MS_DECO_WD_MASK (0x100000U) #define CAAM_CTPR_MS_DECO_WD_SHIFT (20U) #define CAAM_CTPR_MS_DECO_WD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_DECO_WD_SHIFT)) & CAAM_CTPR_MS_DECO_WD_MASK) + #define CAAM_CTPR_MS_PC_MASK (0x200000U) #define CAAM_CTPR_MS_PC_SHIFT (21U) #define CAAM_CTPR_MS_PC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_PC_SHIFT)) & CAAM_CTPR_MS_PC_MASK) + #define CAAM_CTPR_MS_C1C2_MASK (0x800000U) #define CAAM_CTPR_MS_C1C2_SHIFT (23U) #define CAAM_CTPR_MS_C1C2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_C1C2_SHIFT)) & CAAM_CTPR_MS_C1C2_MASK) + #define CAAM_CTPR_MS_ACC_CTL_MASK (0x1000000U) #define CAAM_CTPR_MS_ACC_CTL_SHIFT (24U) #define CAAM_CTPR_MS_ACC_CTL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_ACC_CTL_SHIFT)) & CAAM_CTPR_MS_ACC_CTL_MASK) + #define CAAM_CTPR_MS_QI_MASK (0x2000000U) #define CAAM_CTPR_MS_QI_SHIFT (25U) #define CAAM_CTPR_MS_QI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_QI_SHIFT)) & CAAM_CTPR_MS_QI_MASK) + #define CAAM_CTPR_MS_AXI_PRI_MASK (0x4000000U) #define CAAM_CTPR_MS_AXI_PRI_SHIFT (26U) #define CAAM_CTPR_MS_AXI_PRI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_AXI_PRI_SHIFT)) & CAAM_CTPR_MS_AXI_PRI_MASK) + #define CAAM_CTPR_MS_AXI_LIODN_MASK (0x8000000U) #define CAAM_CTPR_MS_AXI_LIODN_SHIFT (27U) #define CAAM_CTPR_MS_AXI_LIODN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_AXI_LIODN_SHIFT)) & CAAM_CTPR_MS_AXI_LIODN_MASK) + #define CAAM_CTPR_MS_AXI_PIPE_DEPTH_MASK (0xF0000000U) #define CAAM_CTPR_MS_AXI_PIPE_DEPTH_SHIFT (28U) #define CAAM_CTPR_MS_AXI_PIPE_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_AXI_PIPE_DEPTH_SHIFT)) & CAAM_CTPR_MS_AXI_PIPE_DEPTH_MASK) @@ -12864,6 +14363,7 @@ typedef struct { /*! @name CTPR_LS - Compile Time Parameters Register, least-significant half */ /*! @{ */ + #define CAAM_CTPR_LS_KG_DS_MASK (0x1U) #define CAAM_CTPR_LS_KG_DS_SHIFT (0U) /*! KG_DS @@ -12871,6 +14371,7 @@ typedef struct { * 0b1..CAAM implements specialized support for Public Key Generation and Digital Signatures. */ #define CAAM_CTPR_LS_KG_DS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_KG_DS_SHIFT)) & CAAM_CTPR_LS_KG_DS_MASK) + #define CAAM_CTPR_LS_BLOB_MASK (0x2U) #define CAAM_CTPR_LS_BLOB_SHIFT (1U) /*! BLOB @@ -12878,6 +14379,7 @@ typedef struct { * 0b1..CAAM implements specialized support for encapsulating and decapsulating cryptographic blobs. */ #define CAAM_CTPR_LS_BLOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_BLOB_SHIFT)) & CAAM_CTPR_LS_BLOB_MASK) + #define CAAM_CTPR_LS_WIFI_MASK (0x4U) #define CAAM_CTPR_LS_WIFI_SHIFT (2U) /*! WIFI @@ -12885,6 +14387,7 @@ typedef struct { * 0b1..CAAM implements specialized support for the WIFI protocol. */ #define CAAM_CTPR_LS_WIFI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_WIFI_SHIFT)) & CAAM_CTPR_LS_WIFI_MASK) + #define CAAM_CTPR_LS_WIMAX_MASK (0x8U) #define CAAM_CTPR_LS_WIMAX_SHIFT (3U) /*! WIMAX @@ -12892,6 +14395,7 @@ typedef struct { * 0b1..CAAM implements specialized support for the WIMAX protocol. */ #define CAAM_CTPR_LS_WIMAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_WIMAX_SHIFT)) & CAAM_CTPR_LS_WIMAX_MASK) + #define CAAM_CTPR_LS_SRTP_MASK (0x10U) #define CAAM_CTPR_LS_SRTP_SHIFT (4U) /*! SRTP @@ -12899,6 +14403,7 @@ typedef struct { * 0b1..CAAM implements specialized support for the SRTP protocol. */ #define CAAM_CTPR_LS_SRTP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_SRTP_SHIFT)) & CAAM_CTPR_LS_SRTP_MASK) + #define CAAM_CTPR_LS_IPSEC_MASK (0x20U) #define CAAM_CTPR_LS_IPSEC_SHIFT (5U) /*! IPSEC @@ -12906,6 +14411,7 @@ typedef struct { * 0b1..CAAM implements specialized support for the IPSEC protocol. */ #define CAAM_CTPR_LS_IPSEC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_IPSEC_SHIFT)) & CAAM_CTPR_LS_IPSEC_MASK) + #define CAAM_CTPR_LS_IKE_MASK (0x40U) #define CAAM_CTPR_LS_IKE_SHIFT (6U) /*! IKE @@ -12913,6 +14419,7 @@ typedef struct { * 0b1..CAAM implements specialized support for the IKE protocol. */ #define CAAM_CTPR_LS_IKE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_IKE_SHIFT)) & CAAM_CTPR_LS_IKE_MASK) + #define CAAM_CTPR_LS_SSL_TLS_MASK (0x80U) #define CAAM_CTPR_LS_SSL_TLS_SHIFT (7U) /*! SSL_TLS @@ -12920,6 +14427,7 @@ typedef struct { * 0b1..CAAM implements specialized support for the SSL and TLS protocols. */ #define CAAM_CTPR_LS_SSL_TLS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_SSL_TLS_SHIFT)) & CAAM_CTPR_LS_SSL_TLS_MASK) + #define CAAM_CTPR_LS_TLS_PRF_MASK (0x100U) #define CAAM_CTPR_LS_TLS_PRF_SHIFT (8U) /*! TLS_PRF @@ -12927,6 +14435,7 @@ typedef struct { * 0b1..CAAM implements specialized support for the TLS protocol pseudo-random function. */ #define CAAM_CTPR_LS_TLS_PRF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_TLS_PRF_SHIFT)) & CAAM_CTPR_LS_TLS_PRF_MASK) + #define CAAM_CTPR_LS_MACSEC_MASK (0x200U) #define CAAM_CTPR_LS_MACSEC_SHIFT (9U) /*! MACSEC @@ -12934,6 +14443,7 @@ typedef struct { * 0b1..CAAM implements specialized support for the MACSEC protocol. */ #define CAAM_CTPR_LS_MACSEC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_MACSEC_SHIFT)) & CAAM_CTPR_LS_MACSEC_MASK) + #define CAAM_CTPR_LS_RSA_MASK (0x400U) #define CAAM_CTPR_LS_RSA_SHIFT (10U) /*! RSA @@ -12941,6 +14451,7 @@ typedef struct { * 0b1..CAAM implements specialized support for RSA encrypt and decrypt operations. */ #define CAAM_CTPR_LS_RSA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_RSA_SHIFT)) & CAAM_CTPR_LS_RSA_MASK) + #define CAAM_CTPR_LS_P3G_LTE_MASK (0x800U) #define CAAM_CTPR_LS_P3G_LTE_SHIFT (11U) /*! P3G_LTE @@ -12948,6 +14459,7 @@ typedef struct { * 0b1..CAAM implements specialized support for 3G and LTE protocols. */ #define CAAM_CTPR_LS_P3G_LTE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_P3G_LTE_SHIFT)) & CAAM_CTPR_LS_P3G_LTE_MASK) + #define CAAM_CTPR_LS_DBL_CRC_MASK (0x1000U) #define CAAM_CTPR_LS_DBL_CRC_SHIFT (12U) /*! DBL_CRC @@ -12955,6 +14467,7 @@ typedef struct { * 0b1..CAAM implements specialized support for Double CRC. */ #define CAAM_CTPR_LS_DBL_CRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_DBL_CRC_SHIFT)) & CAAM_CTPR_LS_DBL_CRC_MASK) + #define CAAM_CTPR_LS_MAN_PROT_MASK (0x2000U) #define CAAM_CTPR_LS_MAN_PROT_SHIFT (13U) /*! MAN_PROT @@ -12962,6 +14475,7 @@ typedef struct { * 0b1..CAAM implements Manufacturing Protection functions. */ #define CAAM_CTPR_LS_MAN_PROT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_MAN_PROT_SHIFT)) & CAAM_CTPR_LS_MAN_PROT_MASK) + #define CAAM_CTPR_LS_DKP_MASK (0x4000U) #define CAAM_CTPR_LS_DKP_SHIFT (14U) /*! DKP @@ -12973,6 +14487,7 @@ typedef struct { /*! @name SMSTA - Secure Memory Status Register */ /*! @{ */ + #define CAAM_SMSTA_STATE_MASK (0xFU) #define CAAM_SMSTA_STATE_SHIFT (0U) /*! STATE @@ -12982,6 +14497,7 @@ typedef struct { * 0b0011..Fail State */ #define CAAM_SMSTA_STATE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_STATE_SHIFT)) & CAAM_SMSTA_STATE_MASK) + #define CAAM_SMSTA_ACCERR_MASK (0xF0U) #define CAAM_SMSTA_ACCERR_SHIFT (4U) /*! ACCERR @@ -13001,18 +14517,23 @@ typedef struct { * 0b1101..An attempt was made to access a page while it was still being initialized. */ #define CAAM_SMSTA_ACCERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_ACCERR_SHIFT)) & CAAM_SMSTA_ACCERR_MASK) + #define CAAM_SMSTA_DID_MASK (0xF00U) #define CAAM_SMSTA_DID_SHIFT (8U) #define CAAM_SMSTA_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_DID_SHIFT)) & CAAM_SMSTA_DID_MASK) + #define CAAM_SMSTA_NS_MASK (0x1000U) #define CAAM_SMSTA_NS_SHIFT (12U) #define CAAM_SMSTA_NS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_NS_SHIFT)) & CAAM_SMSTA_NS_MASK) + #define CAAM_SMSTA_SMR_WP_MASK (0x8000U) #define CAAM_SMSTA_SMR_WP_SHIFT (15U) #define CAAM_SMSTA_SMR_WP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_SMR_WP_SHIFT)) & CAAM_SMSTA_SMR_WP_MASK) + #define CAAM_SMSTA_PAGE_MASK (0x7FF0000U) #define CAAM_SMSTA_PAGE_SHIFT (16U) #define CAAM_SMSTA_PAGE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_PAGE_SHIFT)) & CAAM_SMSTA_PAGE_MASK) + #define CAAM_SMSTA_PART_MASK (0xF0000000U) #define CAAM_SMSTA_PART_SHIFT (28U) #define CAAM_SMSTA_PART(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_PART_SHIFT)) & CAAM_SMSTA_PART_MASK) @@ -13020,6 +14541,7 @@ typedef struct { /*! @name SMPO - Secure Memory Partition Owners Register */ /*! @{ */ + #define CAAM_SMPO_PO0_MASK (0x3U) #define CAAM_SMPO_PO0_SHIFT (0U) /*! PO0 @@ -13036,48 +14558,63 @@ typedef struct { * permissions register (SMAPJR) of an available partition is first written. */ #define CAAM_SMPO_PO0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO0_SHIFT)) & CAAM_SMPO_PO0_MASK) + #define CAAM_SMPO_PO1_MASK (0xCU) #define CAAM_SMPO_PO1_SHIFT (2U) #define CAAM_SMPO_PO1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO1_SHIFT)) & CAAM_SMPO_PO1_MASK) + #define CAAM_SMPO_PO2_MASK (0x30U) #define CAAM_SMPO_PO2_SHIFT (4U) #define CAAM_SMPO_PO2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO2_SHIFT)) & CAAM_SMPO_PO2_MASK) + #define CAAM_SMPO_PO3_MASK (0xC0U) #define CAAM_SMPO_PO3_SHIFT (6U) #define CAAM_SMPO_PO3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO3_SHIFT)) & CAAM_SMPO_PO3_MASK) + #define CAAM_SMPO_PO4_MASK (0x300U) #define CAAM_SMPO_PO4_SHIFT (8U) #define CAAM_SMPO_PO4(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO4_SHIFT)) & CAAM_SMPO_PO4_MASK) + #define CAAM_SMPO_PO5_MASK (0xC00U) #define CAAM_SMPO_PO5_SHIFT (10U) #define CAAM_SMPO_PO5(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO5_SHIFT)) & CAAM_SMPO_PO5_MASK) + #define CAAM_SMPO_PO6_MASK (0x3000U) #define CAAM_SMPO_PO6_SHIFT (12U) #define CAAM_SMPO_PO6(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO6_SHIFT)) & CAAM_SMPO_PO6_MASK) + #define CAAM_SMPO_PO7_MASK (0xC000U) #define CAAM_SMPO_PO7_SHIFT (14U) #define CAAM_SMPO_PO7(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO7_SHIFT)) & CAAM_SMPO_PO7_MASK) + #define CAAM_SMPO_PO8_MASK (0x30000U) #define CAAM_SMPO_PO8_SHIFT (16U) #define CAAM_SMPO_PO8(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO8_SHIFT)) & CAAM_SMPO_PO8_MASK) + #define CAAM_SMPO_PO9_MASK (0xC0000U) #define CAAM_SMPO_PO9_SHIFT (18U) #define CAAM_SMPO_PO9(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO9_SHIFT)) & CAAM_SMPO_PO9_MASK) + #define CAAM_SMPO_PO10_MASK (0x300000U) #define CAAM_SMPO_PO10_SHIFT (20U) #define CAAM_SMPO_PO10(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO10_SHIFT)) & CAAM_SMPO_PO10_MASK) + #define CAAM_SMPO_PO11_MASK (0xC00000U) #define CAAM_SMPO_PO11_SHIFT (22U) #define CAAM_SMPO_PO11(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO11_SHIFT)) & CAAM_SMPO_PO11_MASK) + #define CAAM_SMPO_PO12_MASK (0x3000000U) #define CAAM_SMPO_PO12_SHIFT (24U) #define CAAM_SMPO_PO12(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO12_SHIFT)) & CAAM_SMPO_PO12_MASK) + #define CAAM_SMPO_PO13_MASK (0xC000000U) #define CAAM_SMPO_PO13_SHIFT (26U) #define CAAM_SMPO_PO13(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO13_SHIFT)) & CAAM_SMPO_PO13_MASK) + #define CAAM_SMPO_PO14_MASK (0x30000000U) #define CAAM_SMPO_PO14_SHIFT (28U) #define CAAM_SMPO_PO14(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO14_SHIFT)) & CAAM_SMPO_PO14_MASK) + #define CAAM_SMPO_PO15_MASK (0xC0000000U) #define CAAM_SMPO_PO15_SHIFT (30U) #define CAAM_SMPO_PO15(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO15_SHIFT)) & CAAM_SMPO_PO15_MASK) @@ -13085,6 +14622,7 @@ typedef struct { /*! @name FAR - Fault Address Register */ /*! @{ */ + #define CAAM_FAR_FAR_MASK (0xFFFFFFFFFU) #define CAAM_FAR_FAR_SHIFT (0U) #define CAAM_FAR_FAR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_FAR_FAR_SHIFT)) & CAAM_FAR_FAR_MASK) @@ -13092,12 +14630,15 @@ typedef struct { /*! @name FADID - Fault Address DID Register */ /*! @{ */ + #define CAAM_FADID_FDID_MASK (0xFU) #define CAAM_FADID_FDID_SHIFT (0U) #define CAAM_FADID_FDID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADID_FDID_SHIFT)) & CAAM_FADID_FDID_MASK) + #define CAAM_FADID_FNS_MASK (0x10U) #define CAAM_FADID_FNS_SHIFT (4U) #define CAAM_FADID_FNS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADID_FNS_SHIFT)) & CAAM_FADID_FNS_MASK) + #define CAAM_FADID_FICID_MASK (0xFFE0U) #define CAAM_FADID_FICID_SHIFT (5U) #define CAAM_FADID_FICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADID_FICID_SHIFT)) & CAAM_FADID_FICID_MASK) @@ -13105,9 +14646,11 @@ typedef struct { /*! @name FADR - Fault Address Detail Register */ /*! @{ */ + #define CAAM_FADR_FSZ_MASK (0x7FU) #define CAAM_FADR_FSZ_SHIFT (0U) #define CAAM_FADR_FSZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FSZ_SHIFT)) & CAAM_FADR_FSZ_MASK) + #define CAAM_FADR_TYP_MASK (0x80U) #define CAAM_FADR_TYP_SHIFT (7U) /*! TYP @@ -13115,6 +14658,7 @@ typedef struct { * 0b1..Write. */ #define CAAM_FADR_TYP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_TYP_SHIFT)) & CAAM_FADR_TYP_MASK) + #define CAAM_FADR_BLKID_MASK (0xF00U) #define CAAM_FADR_BLKID_SHIFT (8U) /*! BLKID @@ -13123,6 +14667,7 @@ typedef struct { * 0b1000..DECO0 */ #define CAAM_FADR_BLKID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_BLKID_SHIFT)) & CAAM_FADR_BLKID_MASK) + #define CAAM_FADR_JSRC_MASK (0x7000U) #define CAAM_FADR_JSRC_SHIFT (12U) /*! JSRC @@ -13136,6 +14681,7 @@ typedef struct { * 0b111..reserved */ #define CAAM_FADR_JSRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_JSRC_SHIFT)) & CAAM_FADR_JSRC_MASK) + #define CAAM_FADR_DTYP_MASK (0x8000U) #define CAAM_FADR_DTYP_SHIFT (15U) /*! DTYP @@ -13143,9 +14689,11 @@ typedef struct { * 0b1..control data */ #define CAAM_FADR_DTYP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_DTYP_SHIFT)) & CAAM_FADR_DTYP_MASK) + #define CAAM_FADR_FSZ_EXT_MASK (0x70000U) #define CAAM_FADR_FSZ_EXT_SHIFT (16U) #define CAAM_FADR_FSZ_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FSZ_EXT_SHIFT)) & CAAM_FADR_FSZ_EXT_MASK) + #define CAAM_FADR_FKMOD_MASK (0x1000000U) #define CAAM_FADR_FKMOD_SHIFT (24U) /*! FKMOD @@ -13153,6 +14701,7 @@ typedef struct { * 0b1..CAAM DMA was attempting to read the key modifier from Secure Memory at the time that the DMA error occurred. */ #define CAAM_FADR_FKMOD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FKMOD_SHIFT)) & CAAM_FADR_FKMOD_MASK) + #define CAAM_FADR_FKEY_MASK (0x2000000U) #define CAAM_FADR_FKEY_SHIFT (25U) /*! FKEY @@ -13160,6 +14709,7 @@ typedef struct { * 0b1..CAAM DMA was attempting to perform a key read from Secure Memory at the time of the DMA error. */ #define CAAM_FADR_FKEY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FKEY_SHIFT)) & CAAM_FADR_FKEY_MASK) + #define CAAM_FADR_FTDSC_MASK (0x4000000U) #define CAAM_FADR_FTDSC_SHIFT (26U) /*! FTDSC @@ -13167,6 +14717,7 @@ typedef struct { * 0b1..CAAM DMA was executing a Trusted Descriptor at the time of the DMA error. */ #define CAAM_FADR_FTDSC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FTDSC_SHIFT)) & CAAM_FADR_FTDSC_MASK) + #define CAAM_FADR_FBNDG_MASK (0x8000000U) #define CAAM_FADR_FBNDG_SHIFT (27U) /*! FBNDG @@ -13174,6 +14725,7 @@ typedef struct { * 0b1..CAAM DMA was reading access permissions from a Secure Memory partition at the time of the DMA error. */ #define CAAM_FADR_FBNDG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FBNDG_SHIFT)) & CAAM_FADR_FBNDG_MASK) + #define CAAM_FADR_FNS_MASK (0x10000000U) #define CAAM_FADR_FNS_SHIFT (28U) /*! FNS @@ -13181,6 +14733,7 @@ typedef struct { * 0b1..CAAM DMA was asserting ns=1 at the time of the DMA error. */ #define CAAM_FADR_FNS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FNS_SHIFT)) & CAAM_FADR_FNS_MASK) + #define CAAM_FADR_FERR_MASK (0xC0000000U) #define CAAM_FADR_FERR_SHIFT (30U) /*! FERR @@ -13194,15 +14747,19 @@ typedef struct { /*! @name CSTA - CAAM Status Register */ /*! @{ */ + #define CAAM_CSTA_BSY_MASK (0x1U) #define CAAM_CSTA_BSY_SHIFT (0U) #define CAAM_CSTA_BSY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_BSY_SHIFT)) & CAAM_CSTA_BSY_MASK) + #define CAAM_CSTA_IDLE_MASK (0x2U) #define CAAM_CSTA_IDLE_SHIFT (1U) #define CAAM_CSTA_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_IDLE_SHIFT)) & CAAM_CSTA_IDLE_MASK) + #define CAAM_CSTA_TRNG_IDLE_MASK (0x4U) #define CAAM_CSTA_TRNG_IDLE_SHIFT (2U) #define CAAM_CSTA_TRNG_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_TRNG_IDLE_SHIFT)) & CAAM_CSTA_TRNG_IDLE_MASK) + #define CAAM_CSTA_MOO_MASK (0x300U) #define CAAM_CSTA_MOO_SHIFT (8U) /*! MOO @@ -13212,6 +14769,7 @@ typedef struct { * 0b11..Fail */ #define CAAM_CSTA_MOO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_MOO_SHIFT)) & CAAM_CSTA_MOO_MASK) + #define CAAM_CSTA_PLEND_MASK (0x400U) #define CAAM_CSTA_PLEND_SHIFT (10U) /*! PLEND @@ -13223,12 +14781,15 @@ typedef struct { /*! @name SMVID_MS - Secure Memory Version ID Register, most-significant half */ /*! @{ */ + #define CAAM_SMVID_MS_NPAG_MASK (0x3FFU) #define CAAM_SMVID_MS_NPAG_SHIFT (0U) #define CAAM_SMVID_MS_NPAG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_MS_NPAG_SHIFT)) & CAAM_SMVID_MS_NPAG_MASK) + #define CAAM_SMVID_MS_NPRT_MASK (0xF000U) #define CAAM_SMVID_MS_NPRT_SHIFT (12U) #define CAAM_SMVID_MS_NPRT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_MS_NPRT_SHIFT)) & CAAM_SMVID_MS_NPRT_MASK) + #define CAAM_SMVID_MS_MAX_NPAG_MASK (0x3FF0000U) #define CAAM_SMVID_MS_MAX_NPAG_SHIFT (16U) #define CAAM_SMVID_MS_MAX_NPAG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_MS_MAX_NPAG_SHIFT)) & CAAM_SMVID_MS_MAX_NPAG_MASK) @@ -13236,12 +14797,15 @@ typedef struct { /*! @name SMVID_LS - Secure Memory Version ID Register, least-significant half */ /*! @{ */ + #define CAAM_SMVID_LS_SMNV_MASK (0xFFU) #define CAAM_SMVID_LS_SMNV_SHIFT (0U) #define CAAM_SMVID_LS_SMNV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_LS_SMNV_SHIFT)) & CAAM_SMVID_LS_SMNV_MASK) + #define CAAM_SMVID_LS_SMJV_MASK (0xFF00U) #define CAAM_SMVID_LS_SMJV_SHIFT (8U) #define CAAM_SMVID_LS_SMJV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_LS_SMJV_SHIFT)) & CAAM_SMVID_LS_SMJV_MASK) + #define CAAM_SMVID_LS_PSIZ_MASK (0x70000U) #define CAAM_SMVID_LS_PSIZ_SHIFT (16U) #define CAAM_SMVID_LS_PSIZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_LS_PSIZ_SHIFT)) & CAAM_SMVID_LS_PSIZ_MASK) @@ -13249,12 +14813,15 @@ typedef struct { /*! @name RVID - RTIC Version ID Register */ /*! @{ */ + #define CAAM_RVID_RMNV_MASK (0xFFU) #define CAAM_RVID_RMNV_SHIFT (0U) #define CAAM_RVID_RMNV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_RMNV_SHIFT)) & CAAM_RVID_RMNV_MASK) + #define CAAM_RVID_RMJV_MASK (0xFF00U) #define CAAM_RVID_RMJV_SHIFT (8U) #define CAAM_RVID_RMJV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_RMJV_SHIFT)) & CAAM_RVID_RMJV_MASK) + #define CAAM_RVID_SHA_256_MASK (0x20000U) #define CAAM_RVID_SHA_256_SHIFT (17U) /*! SHA_256 @@ -13262,6 +14829,7 @@ typedef struct { * 0b1..RTIC can use the SHA-256 hashing algorithm. */ #define CAAM_RVID_SHA_256(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_SHA_256_SHIFT)) & CAAM_RVID_SHA_256_MASK) + #define CAAM_RVID_SHA_512_MASK (0x80000U) #define CAAM_RVID_SHA_512_SHIFT (19U) /*! SHA_512 @@ -13269,15 +14837,19 @@ typedef struct { * 0b1..RTIC can use the SHA-512 hashing algorithm. */ #define CAAM_RVID_SHA_512(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_SHA_512_SHIFT)) & CAAM_RVID_SHA_512_MASK) + #define CAAM_RVID_MA_MASK (0x1000000U) #define CAAM_RVID_MA_SHIFT (24U) #define CAAM_RVID_MA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_MA_SHIFT)) & CAAM_RVID_MA_MASK) + #define CAAM_RVID_MB_MASK (0x2000000U) #define CAAM_RVID_MB_SHIFT (25U) #define CAAM_RVID_MB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_MB_SHIFT)) & CAAM_RVID_MB_MASK) + #define CAAM_RVID_MC_MASK (0x4000000U) #define CAAM_RVID_MC_SHIFT (26U) #define CAAM_RVID_MC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_MC_SHIFT)) & CAAM_RVID_MC_MASK) + #define CAAM_RVID_MD_MASK (0x8000000U) #define CAAM_RVID_MD_SHIFT (27U) #define CAAM_RVID_MD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_MD_SHIFT)) & CAAM_RVID_MD_MASK) @@ -13285,12 +14857,15 @@ typedef struct { /*! @name CCBVID - CHA Cluster Block Version ID Register */ /*! @{ */ + #define CAAM_CCBVID_AMNV_MASK (0xFFU) #define CAAM_CCBVID_AMNV_SHIFT (0U) #define CAAM_CCBVID_AMNV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCBVID_AMNV_SHIFT)) & CAAM_CCBVID_AMNV_MASK) + #define CAAM_CCBVID_AMJV_MASK (0xFF00U) #define CAAM_CCBVID_AMJV_SHIFT (8U) #define CAAM_CCBVID_AMJV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCBVID_AMJV_SHIFT)) & CAAM_CCBVID_AMJV_MASK) + #define CAAM_CCBVID_CAAM_ERA_MASK (0xFF000000U) #define CAAM_CCBVID_CAAM_ERA_SHIFT (24U) #define CAAM_CCBVID_CAAM_ERA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCBVID_CAAM_ERA_SHIFT)) & CAAM_CCBVID_CAAM_ERA_MASK) @@ -13298,21 +14873,27 @@ typedef struct { /*! @name CHAVID_MS - CHA Version ID Register, most-significant half */ /*! @{ */ + #define CAAM_CHAVID_MS_CRCVID_MASK (0xFU) #define CAAM_CHAVID_MS_CRCVID_SHIFT (0U) #define CAAM_CHAVID_MS_CRCVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_CRCVID_SHIFT)) & CAAM_CHAVID_MS_CRCVID_MASK) + #define CAAM_CHAVID_MS_SNW9VID_MASK (0xF0U) #define CAAM_CHAVID_MS_SNW9VID_SHIFT (4U) #define CAAM_CHAVID_MS_SNW9VID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_SNW9VID_SHIFT)) & CAAM_CHAVID_MS_SNW9VID_MASK) + #define CAAM_CHAVID_MS_ZEVID_MASK (0xF00U) #define CAAM_CHAVID_MS_ZEVID_SHIFT (8U) #define CAAM_CHAVID_MS_ZEVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_ZEVID_SHIFT)) & CAAM_CHAVID_MS_ZEVID_MASK) + #define CAAM_CHAVID_MS_ZAVID_MASK (0xF000U) #define CAAM_CHAVID_MS_ZAVID_SHIFT (12U) #define CAAM_CHAVID_MS_ZAVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_ZAVID_SHIFT)) & CAAM_CHAVID_MS_ZAVID_MASK) + #define CAAM_CHAVID_MS_DECOVID_MASK (0xF000000U) #define CAAM_CHAVID_MS_DECOVID_SHIFT (24U) #define CAAM_CHAVID_MS_DECOVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_DECOVID_SHIFT)) & CAAM_CHAVID_MS_DECOVID_MASK) + #define CAAM_CHAVID_MS_JRVID_MASK (0xF0000000U) #define CAAM_CHAVID_MS_JRVID_SHIFT (28U) #define CAAM_CHAVID_MS_JRVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_JRVID_SHIFT)) & CAAM_CHAVID_MS_JRVID_MASK) @@ -13320,6 +14901,7 @@ typedef struct { /*! @name CHAVID_LS - CHA Version ID Register, least-significant half */ /*! @{ */ + #define CAAM_CHAVID_LS_AESVID_MASK (0xFU) #define CAAM_CHAVID_LS_AESVID_SHIFT (0U) /*! AESVID @@ -13327,9 +14909,11 @@ typedef struct { * 0b0011..Low-power AESA, implementing ECB, CBC, CBC-CS2, CFB128, OFB, CTR, CCM, CMAC, XCBC-MAC, and GCM modes */ #define CAAM_CHAVID_LS_AESVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_AESVID_SHIFT)) & CAAM_CHAVID_LS_AESVID_MASK) + #define CAAM_CHAVID_LS_DESVID_MASK (0xF0U) #define CAAM_CHAVID_LS_DESVID_SHIFT (4U) #define CAAM_CHAVID_LS_DESVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_DESVID_SHIFT)) & CAAM_CHAVID_LS_DESVID_MASK) + #define CAAM_CHAVID_LS_MDVID_MASK (0xF000U) #define CAAM_CHAVID_LS_MDVID_SHIFT (12U) /*! MDVID @@ -13339,6 +14923,7 @@ typedef struct { * 0b0011..High-performance MDHA, with SHA-1, SHA-256, SHA 224, SHA-512, SHA-512/224, SHA-512/256, SHA-384, MD5, HMAC & SMAC */ #define CAAM_CHAVID_LS_MDVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_MDVID_SHIFT)) & CAAM_CHAVID_LS_MDVID_MASK) + #define CAAM_CHAVID_LS_RNGVID_MASK (0xF0000U) #define CAAM_CHAVID_LS_RNGVID_SHIFT (16U) /*! RNGVID @@ -13346,12 +14931,15 @@ typedef struct { * 0b0100..RNG4 */ #define CAAM_CHAVID_LS_RNGVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_RNGVID_SHIFT)) & CAAM_CHAVID_LS_RNGVID_MASK) + #define CAAM_CHAVID_LS_SNW8VID_MASK (0xF00000U) #define CAAM_CHAVID_LS_SNW8VID_SHIFT (20U) #define CAAM_CHAVID_LS_SNW8VID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_SNW8VID_SHIFT)) & CAAM_CHAVID_LS_SNW8VID_MASK) + #define CAAM_CHAVID_LS_KASVID_MASK (0xF000000U) #define CAAM_CHAVID_LS_KASVID_SHIFT (24U) #define CAAM_CHAVID_LS_KASVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_KASVID_SHIFT)) & CAAM_CHAVID_LS_KASVID_MASK) + #define CAAM_CHAVID_LS_PKVID_MASK (0xF0000000U) #define CAAM_CHAVID_LS_PKVID_SHIFT (28U) /*! PKVID @@ -13365,21 +14953,27 @@ typedef struct { /*! @name CHANUM_MS - CHA Number Register, most-significant half */ /*! @{ */ + #define CAAM_CHANUM_MS_CRCNUM_MASK (0xFU) #define CAAM_CHANUM_MS_CRCNUM_SHIFT (0U) #define CAAM_CHANUM_MS_CRCNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_CRCNUM_SHIFT)) & CAAM_CHANUM_MS_CRCNUM_MASK) + #define CAAM_CHANUM_MS_SNW9NUM_MASK (0xF0U) #define CAAM_CHANUM_MS_SNW9NUM_SHIFT (4U) #define CAAM_CHANUM_MS_SNW9NUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_SNW9NUM_SHIFT)) & CAAM_CHANUM_MS_SNW9NUM_MASK) + #define CAAM_CHANUM_MS_ZENUM_MASK (0xF00U) #define CAAM_CHANUM_MS_ZENUM_SHIFT (8U) #define CAAM_CHANUM_MS_ZENUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_ZENUM_SHIFT)) & CAAM_CHANUM_MS_ZENUM_MASK) + #define CAAM_CHANUM_MS_ZANUM_MASK (0xF000U) #define CAAM_CHANUM_MS_ZANUM_SHIFT (12U) #define CAAM_CHANUM_MS_ZANUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_ZANUM_SHIFT)) & CAAM_CHANUM_MS_ZANUM_MASK) + #define CAAM_CHANUM_MS_DECONUM_MASK (0xF000000U) #define CAAM_CHANUM_MS_DECONUM_SHIFT (24U) #define CAAM_CHANUM_MS_DECONUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_DECONUM_SHIFT)) & CAAM_CHANUM_MS_DECONUM_MASK) + #define CAAM_CHANUM_MS_JRNUM_MASK (0xF0000000U) #define CAAM_CHANUM_MS_JRNUM_SHIFT (28U) #define CAAM_CHANUM_MS_JRNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_JRNUM_SHIFT)) & CAAM_CHANUM_MS_JRNUM_MASK) @@ -13387,27 +14981,35 @@ typedef struct { /*! @name CHANUM_LS - CHA Number Register, least-significant half */ /*! @{ */ + #define CAAM_CHANUM_LS_AESNUM_MASK (0xFU) #define CAAM_CHANUM_LS_AESNUM_SHIFT (0U) #define CAAM_CHANUM_LS_AESNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_AESNUM_SHIFT)) & CAAM_CHANUM_LS_AESNUM_MASK) + #define CAAM_CHANUM_LS_DESNUM_MASK (0xF0U) #define CAAM_CHANUM_LS_DESNUM_SHIFT (4U) #define CAAM_CHANUM_LS_DESNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_DESNUM_SHIFT)) & CAAM_CHANUM_LS_DESNUM_MASK) + #define CAAM_CHANUM_LS_ARC4NUM_MASK (0xF00U) #define CAAM_CHANUM_LS_ARC4NUM_SHIFT (8U) #define CAAM_CHANUM_LS_ARC4NUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_ARC4NUM_SHIFT)) & CAAM_CHANUM_LS_ARC4NUM_MASK) + #define CAAM_CHANUM_LS_MDNUM_MASK (0xF000U) #define CAAM_CHANUM_LS_MDNUM_SHIFT (12U) #define CAAM_CHANUM_LS_MDNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_MDNUM_SHIFT)) & CAAM_CHANUM_LS_MDNUM_MASK) + #define CAAM_CHANUM_LS_RNGNUM_MASK (0xF0000U) #define CAAM_CHANUM_LS_RNGNUM_SHIFT (16U) #define CAAM_CHANUM_LS_RNGNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_RNGNUM_SHIFT)) & CAAM_CHANUM_LS_RNGNUM_MASK) + #define CAAM_CHANUM_LS_SNW8NUM_MASK (0xF00000U) #define CAAM_CHANUM_LS_SNW8NUM_SHIFT (20U) #define CAAM_CHANUM_LS_SNW8NUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_SNW8NUM_SHIFT)) & CAAM_CHANUM_LS_SNW8NUM_MASK) + #define CAAM_CHANUM_LS_KASNUM_MASK (0xF000000U) #define CAAM_CHANUM_LS_KASNUM_SHIFT (24U) #define CAAM_CHANUM_LS_KASNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_KASNUM_SHIFT)) & CAAM_CHANUM_LS_KASNUM_MASK) + #define CAAM_CHANUM_LS_PKNUM_MASK (0xF0000000U) #define CAAM_CHANUM_LS_PKNUM_SHIFT (28U) #define CAAM_CHANUM_LS_PKNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_PKNUM_SHIFT)) & CAAM_CHANUM_LS_PKNUM_MASK) @@ -13415,6 +15017,7 @@ typedef struct { /*! @name IRBAR_JR - Input Ring Base Address Register for Job Ring 0..Input Ring Base Address Register for Job Ring 3 */ /*! @{ */ + #define CAAM_IRBAR_JR_IRBA_MASK (0xFFFFFFFFFU) #define CAAM_IRBAR_JR_IRBA_SHIFT (0U) #define CAAM_IRBAR_JR_IRBA(x) (((uint64_t)(((uint64_t)(x)) << CAAM_IRBAR_JR_IRBA_SHIFT)) & CAAM_IRBAR_JR_IRBA_MASK) @@ -13425,6 +15028,7 @@ typedef struct { /*! @name IRSR_JR - Input Ring Size Register for Job Ring 0..Input Ring Size Register for Job Ring 3 */ /*! @{ */ + #define CAAM_IRSR_JR_IRS_MASK (0x3FFU) #define CAAM_IRSR_JR_IRS_SHIFT (0U) #define CAAM_IRSR_JR_IRS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_IRSR_JR_IRS_SHIFT)) & CAAM_IRSR_JR_IRS_MASK) @@ -13435,6 +15039,7 @@ typedef struct { /*! @name IRSAR_JR - Input Ring Slots Available Register for Job Ring 0..Input Ring Slots Available Register for Job Ring 3 */ /*! @{ */ + #define CAAM_IRSAR_JR_IRSA_MASK (0x3FFU) #define CAAM_IRSAR_JR_IRSA_SHIFT (0U) #define CAAM_IRSAR_JR_IRSA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_IRSAR_JR_IRSA_SHIFT)) & CAAM_IRSAR_JR_IRSA_MASK) @@ -13445,6 +15050,7 @@ typedef struct { /*! @name IRJAR_JR - Input Ring Jobs Added Register for Job Ring0..Input Ring Jobs Added Register for Job Ring3 */ /*! @{ */ + #define CAAM_IRJAR_JR_IRJA_MASK (0x3FFU) #define CAAM_IRJAR_JR_IRJA_SHIFT (0U) #define CAAM_IRJAR_JR_IRJA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_IRJAR_JR_IRJA_SHIFT)) & CAAM_IRJAR_JR_IRJA_MASK) @@ -13455,6 +15061,7 @@ typedef struct { /*! @name ORBAR_JR - Output Ring Base Address Register for Job Ring 0..Output Ring Base Address Register for Job Ring 3 */ /*! @{ */ + #define CAAM_ORBAR_JR_ORBA_MASK (0xFFFFFFFFFU) #define CAAM_ORBAR_JR_ORBA_SHIFT (0U) #define CAAM_ORBAR_JR_ORBA(x) (((uint64_t)(((uint64_t)(x)) << CAAM_ORBAR_JR_ORBA_SHIFT)) & CAAM_ORBAR_JR_ORBA_MASK) @@ -13465,6 +15072,7 @@ typedef struct { /*! @name ORSR_JR - Output Ring Size Register for Job Ring 0..Output Ring Size Register for Job Ring 3 */ /*! @{ */ + #define CAAM_ORSR_JR_ORS_MASK (0x3FFU) #define CAAM_ORSR_JR_ORS_SHIFT (0U) #define CAAM_ORSR_JR_ORS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_ORSR_JR_ORS_SHIFT)) & CAAM_ORSR_JR_ORS_MASK) @@ -13475,6 +15083,7 @@ typedef struct { /*! @name ORJRR_JR - Output Ring Jobs Removed Register for Job Ring 0..Output Ring Jobs Removed Register for Job Ring 3 */ /*! @{ */ + #define CAAM_ORJRR_JR_ORJR_MASK (0x3FFU) #define CAAM_ORJRR_JR_ORJR_SHIFT (0U) #define CAAM_ORJRR_JR_ORJR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_ORJRR_JR_ORJR_SHIFT)) & CAAM_ORJRR_JR_ORJR_MASK) @@ -13485,6 +15094,7 @@ typedef struct { /*! @name ORSFR_JR - Output Ring Slots Full Register for Job Ring 0..Output Ring Slots Full Register for Job Ring 3 */ /*! @{ */ + #define CAAM_ORSFR_JR_ORSF_MASK (0x3FFU) #define CAAM_ORSFR_JR_ORSF_SHIFT (0U) #define CAAM_ORSFR_JR_ORSF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_ORSFR_JR_ORSF_SHIFT)) & CAAM_ORSFR_JR_ORSF_MASK) @@ -13495,9 +15105,11 @@ typedef struct { /*! @name JRSTAR_JR - Job Ring Output Status Register for Job Ring 0..Job Ring Output Status Register for Job Ring 3 */ /*! @{ */ + #define CAAM_JRSTAR_JR_SSED_MASK (0xFFFFFFFU) #define CAAM_JRSTAR_JR_SSED_SHIFT (0U) #define CAAM_JRSTAR_JR_SSED(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTAR_JR_SSED_SHIFT)) & CAAM_JRSTAR_JR_SSED_MASK) + #define CAAM_JRSTAR_JR_SSRC_MASK (0xF0000000U) #define CAAM_JRSTAR_JR_SSRC_SHIFT (28U) /*! SSRC @@ -13518,21 +15130,27 @@ typedef struct { /*! @name JRINTR_JR - Job Ring Interrupt Status Register for Job Ring 0..Job Ring Interrupt Status Register for Job Ring 3 */ /*! @{ */ + #define CAAM_JRINTR_JR_JRI_MASK (0x1U) #define CAAM_JRINTR_JR_JRI_SHIFT (0U) #define CAAM_JRINTR_JR_JRI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_JRI_SHIFT)) & CAAM_JRINTR_JR_JRI_MASK) + #define CAAM_JRINTR_JR_JRE_MASK (0x2U) #define CAAM_JRINTR_JR_JRE_SHIFT (1U) #define CAAM_JRINTR_JR_JRE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_JRE_SHIFT)) & CAAM_JRINTR_JR_JRE_MASK) + #define CAAM_JRINTR_JR_HALT_MASK (0xCU) #define CAAM_JRINTR_JR_HALT_SHIFT (2U) #define CAAM_JRINTR_JR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_HALT_SHIFT)) & CAAM_JRINTR_JR_HALT_MASK) + #define CAAM_JRINTR_JR_ENTER_FAIL_MASK (0x10U) #define CAAM_JRINTR_JR_ENTER_FAIL_SHIFT (4U) #define CAAM_JRINTR_JR_ENTER_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_ENTER_FAIL_SHIFT)) & CAAM_JRINTR_JR_ENTER_FAIL_MASK) + #define CAAM_JRINTR_JR_EXIT_FAIL_MASK (0x20U) #define CAAM_JRINTR_JR_EXIT_FAIL_SHIFT (5U) #define CAAM_JRINTR_JR_EXIT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_EXIT_FAIL_SHIFT)) & CAAM_JRINTR_JR_EXIT_FAIL_MASK) + #define CAAM_JRINTR_JR_ERR_TYPE_MASK (0x1F00U) #define CAAM_JRINTR_JR_ERR_TYPE_SHIFT (8U) /*! ERR_TYPE @@ -13560,6 +15178,7 @@ typedef struct { * 0b10001..Writing ORWI when ring is active */ #define CAAM_JRINTR_JR_ERR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_ERR_TYPE_SHIFT)) & CAAM_JRINTR_JR_ERR_TYPE_MASK) + #define CAAM_JRINTR_JR_ERR_ORWI_MASK (0x3FFF0000U) #define CAAM_JRINTR_JR_ERR_ORWI_SHIFT (16U) #define CAAM_JRINTR_JR_ERR_ORWI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_ERR_ORWI_SHIFT)) & CAAM_JRINTR_JR_ERR_ORWI_MASK) @@ -13570,54 +15189,71 @@ typedef struct { /*! @name JRCFGR_JR_MS - Job Ring Configuration Register for Job Ring 0, most-significant half..Job Ring Configuration Register for Job Ring 3, most-significant half */ /*! @{ */ + #define CAAM_JRCFGR_JR_MS_MBSI_MASK (0x1U) #define CAAM_JRCFGR_JR_MS_MBSI_SHIFT (0U) #define CAAM_JRCFGR_JR_MS_MBSI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MBSI_SHIFT)) & CAAM_JRCFGR_JR_MS_MBSI_MASK) + #define CAAM_JRCFGR_JR_MS_MHWSI_MASK (0x2U) #define CAAM_JRCFGR_JR_MS_MHWSI_SHIFT (1U) #define CAAM_JRCFGR_JR_MS_MHWSI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MHWSI_SHIFT)) & CAAM_JRCFGR_JR_MS_MHWSI_MASK) + #define CAAM_JRCFGR_JR_MS_MWSI_MASK (0x4U) #define CAAM_JRCFGR_JR_MS_MWSI_SHIFT (2U) #define CAAM_JRCFGR_JR_MS_MWSI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MWSI_SHIFT)) & CAAM_JRCFGR_JR_MS_MWSI_MASK) + #define CAAM_JRCFGR_JR_MS_CBSI_MASK (0x10U) #define CAAM_JRCFGR_JR_MS_CBSI_SHIFT (4U) #define CAAM_JRCFGR_JR_MS_CBSI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CBSI_SHIFT)) & CAAM_JRCFGR_JR_MS_CBSI_MASK) + #define CAAM_JRCFGR_JR_MS_CHWSI_MASK (0x20U) #define CAAM_JRCFGR_JR_MS_CHWSI_SHIFT (5U) #define CAAM_JRCFGR_JR_MS_CHWSI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CHWSI_SHIFT)) & CAAM_JRCFGR_JR_MS_CHWSI_MASK) + #define CAAM_JRCFGR_JR_MS_CWSI_MASK (0x40U) #define CAAM_JRCFGR_JR_MS_CWSI_SHIFT (6U) #define CAAM_JRCFGR_JR_MS_CWSI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CWSI_SHIFT)) & CAAM_JRCFGR_JR_MS_CWSI_MASK) + #define CAAM_JRCFGR_JR_MS_MBSO_MASK (0x100U) #define CAAM_JRCFGR_JR_MS_MBSO_SHIFT (8U) #define CAAM_JRCFGR_JR_MS_MBSO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MBSO_SHIFT)) & CAAM_JRCFGR_JR_MS_MBSO_MASK) + #define CAAM_JRCFGR_JR_MS_MHWSO_MASK (0x200U) #define CAAM_JRCFGR_JR_MS_MHWSO_SHIFT (9U) #define CAAM_JRCFGR_JR_MS_MHWSO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MHWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_MHWSO_MASK) + #define CAAM_JRCFGR_JR_MS_MWSO_MASK (0x400U) #define CAAM_JRCFGR_JR_MS_MWSO_SHIFT (10U) #define CAAM_JRCFGR_JR_MS_MWSO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_MWSO_MASK) + #define CAAM_JRCFGR_JR_MS_CBSO_MASK (0x1000U) #define CAAM_JRCFGR_JR_MS_CBSO_SHIFT (12U) #define CAAM_JRCFGR_JR_MS_CBSO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CBSO_SHIFT)) & CAAM_JRCFGR_JR_MS_CBSO_MASK) + #define CAAM_JRCFGR_JR_MS_CHWSO_MASK (0x2000U) #define CAAM_JRCFGR_JR_MS_CHWSO_SHIFT (13U) #define CAAM_JRCFGR_JR_MS_CHWSO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CHWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_CHWSO_MASK) + #define CAAM_JRCFGR_JR_MS_CWSO_MASK (0x4000U) #define CAAM_JRCFGR_JR_MS_CWSO_SHIFT (14U) #define CAAM_JRCFGR_JR_MS_CWSO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_CWSO_MASK) + #define CAAM_JRCFGR_JR_MS_DMBS_MASK (0x10000U) #define CAAM_JRCFGR_JR_MS_DMBS_SHIFT (16U) #define CAAM_JRCFGR_JR_MS_DMBS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_DMBS_SHIFT)) & CAAM_JRCFGR_JR_MS_DMBS_MASK) + #define CAAM_JRCFGR_JR_MS_PEO_MASK (0x20000U) #define CAAM_JRCFGR_JR_MS_PEO_SHIFT (17U) #define CAAM_JRCFGR_JR_MS_PEO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_PEO_SHIFT)) & CAAM_JRCFGR_JR_MS_PEO_MASK) + #define CAAM_JRCFGR_JR_MS_DWSO_MASK (0x40000U) #define CAAM_JRCFGR_JR_MS_DWSO_SHIFT (18U) #define CAAM_JRCFGR_JR_MS_DWSO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_DWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_DWSO_MASK) + #define CAAM_JRCFGR_JR_MS_FAIL_MODE_MASK (0x20000000U) #define CAAM_JRCFGR_JR_MS_FAIL_MODE_SHIFT (29U) #define CAAM_JRCFGR_JR_MS_FAIL_MODE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_FAIL_MODE_SHIFT)) & CAAM_JRCFGR_JR_MS_FAIL_MODE_MASK) + #define CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT_MASK (0x40000000U) #define CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT_SHIFT (30U) #define CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT_SHIFT)) & CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT_MASK) @@ -13628,6 +15264,7 @@ typedef struct { /*! @name JRCFGR_JR_LS - Job Ring Configuration Register for Job Ring 0, least-significant half..Job Ring Configuration Register for Job Ring 3, least-significant half */ /*! @{ */ + #define CAAM_JRCFGR_JR_LS_IMSK_MASK (0x1U) #define CAAM_JRCFGR_JR_LS_IMSK_SHIFT (0U) /*! IMSK @@ -13635,6 +15272,7 @@ typedef struct { * 0b1..Interrupt masked. */ #define CAAM_JRCFGR_JR_LS_IMSK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_LS_IMSK_SHIFT)) & CAAM_JRCFGR_JR_LS_IMSK_MASK) + #define CAAM_JRCFGR_JR_LS_ICEN_MASK (0x2U) #define CAAM_JRCFGR_JR_LS_ICEN_SHIFT (1U) /*! ICEN @@ -13648,9 +15286,11 @@ typedef struct { * (ORSF >= ICDCT), then the interrupt will clear but reassert on the next clock cycle. */ #define CAAM_JRCFGR_JR_LS_ICEN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_LS_ICEN_SHIFT)) & CAAM_JRCFGR_JR_LS_ICEN_MASK) + #define CAAM_JRCFGR_JR_LS_ICDCT_MASK (0xFF00U) #define CAAM_JRCFGR_JR_LS_ICDCT_SHIFT (8U) #define CAAM_JRCFGR_JR_LS_ICDCT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_LS_ICDCT_SHIFT)) & CAAM_JRCFGR_JR_LS_ICDCT_MASK) + #define CAAM_JRCFGR_JR_LS_ICTT_MASK (0xFFFF0000U) #define CAAM_JRCFGR_JR_LS_ICTT_SHIFT (16U) #define CAAM_JRCFGR_JR_LS_ICTT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_LS_ICTT_SHIFT)) & CAAM_JRCFGR_JR_LS_ICTT_MASK) @@ -13661,6 +15301,7 @@ typedef struct { /*! @name IRRIR_JR - Input Ring Read Index Register for Job Ring 0..Input Ring Read Index Register for Job Ring 3 */ /*! @{ */ + #define CAAM_IRRIR_JR_IRRI_MASK (0x1FFFU) #define CAAM_IRRIR_JR_IRRI_SHIFT (0U) #define CAAM_IRRIR_JR_IRRI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_IRRIR_JR_IRRI_SHIFT)) & CAAM_IRRIR_JR_IRRI_MASK) @@ -13671,6 +15312,7 @@ typedef struct { /*! @name ORWIR_JR - Output Ring Write Index Register for Job Ring 0..Output Ring Write Index Register for Job Ring 3 */ /*! @{ */ + #define CAAM_ORWIR_JR_ORWI_MASK (0x3FFFU) #define CAAM_ORWIR_JR_ORWI_SHIFT (0U) #define CAAM_ORWIR_JR_ORWI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_ORWIR_JR_ORWI_SHIFT)) & CAAM_ORWIR_JR_ORWI_MASK) @@ -13681,9 +15323,11 @@ typedef struct { /*! @name JRCR_JR - Job Ring Command Register for Job Ring 0..Job Ring Command Register for Job Ring 3 */ /*! @{ */ + #define CAAM_JRCR_JR_RESET_MASK (0x1U) #define CAAM_JRCR_JR_RESET_SHIFT (0U) #define CAAM_JRCR_JR_RESET(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCR_JR_RESET_SHIFT)) & CAAM_JRCR_JR_RESET_MASK) + #define CAAM_JRCR_JR_PARK_MASK (0x2U) #define CAAM_JRCR_JR_PARK_SHIFT (1U) #define CAAM_JRCR_JR_PARK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCR_JR_PARK_SHIFT)) & CAAM_JRCR_JR_PARK_MASK) @@ -13694,18 +15338,23 @@ typedef struct { /*! @name JRAAV - Job Ring 0 Address-Array Valid Register..Job Ring 3 Address-Array Valid Register */ /*! @{ */ + #define CAAM_JRAAV_V0_MASK (0x1U) #define CAAM_JRAAV_V0_SHIFT (0U) #define CAAM_JRAAV_V0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_V0_SHIFT)) & CAAM_JRAAV_V0_MASK) + #define CAAM_JRAAV_V1_MASK (0x2U) #define CAAM_JRAAV_V1_SHIFT (1U) #define CAAM_JRAAV_V1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_V1_SHIFT)) & CAAM_JRAAV_V1_MASK) + #define CAAM_JRAAV_V2_MASK (0x4U) #define CAAM_JRAAV_V2_SHIFT (2U) #define CAAM_JRAAV_V2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_V2_SHIFT)) & CAAM_JRAAV_V2_MASK) + #define CAAM_JRAAV_V3_MASK (0x8U) #define CAAM_JRAAV_V3_SHIFT (3U) #define CAAM_JRAAV_V3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_V3_SHIFT)) & CAAM_JRAAV_V3_MASK) + #define CAAM_JRAAV_BC_MASK (0x80000000U) #define CAAM_JRAAV_BC_SHIFT (31U) #define CAAM_JRAAV_BC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_BC_SHIFT)) & CAAM_JRAAV_BC_MASK) @@ -13716,6 +15365,7 @@ typedef struct { /*! @name JRAAA - Job Ring 0 Address-Array Address 0 Register..Job Ring 3 Address-Array Address 3 Register */ /*! @{ */ + #define CAAM_JRAAA_JD_ADDR_MASK (0xFFFFFFFFFU) #define CAAM_JRAAA_JD_ADDR_SHIFT (0U) #define CAAM_JRAAA_JD_ADDR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_JRAAA_JD_ADDR_SHIFT)) & CAAM_JRAAA_JD_ADDR_MASK) @@ -13727,21 +15377,23 @@ typedef struct { /* The count of CAAM_JRAAA */ #define CAAM_JRAAA_COUNT2 (4U) -/*! @name PX_SDIDR_JR - Partition 0 SDID register..Partition 15 SDID register */ +/*! @name PX_SDID_JR - Partition 0 SDID register..Partition 15 SDID register */ /*! @{ */ -#define CAAM_PX_SDIDR_JR_SDID_MASK (0xFFFFU) -#define CAAM_PX_SDIDR_JR_SDID_SHIFT (0U) -#define CAAM_PX_SDIDR_JR_SDID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SDIDR_JR_SDID_SHIFT)) & CAAM_PX_SDIDR_JR_SDID_MASK) + +#define CAAM_PX_SDID_JR_SDID_MASK (0xFFFFU) +#define CAAM_PX_SDID_JR_SDID_SHIFT (0U) +#define CAAM_PX_SDID_JR_SDID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SDID_JR_SDID_SHIFT)) & CAAM_PX_SDID_JR_SDID_MASK) /*! @} */ -/* The count of CAAM_PX_SDIDR_JR */ -#define CAAM_PX_SDIDR_JR_COUNT (4U) +/* The count of CAAM_PX_SDID_JR */ +#define CAAM_PX_SDID_JR_COUNT (4U) -/* The count of CAAM_PX_SDIDR_JR */ -#define CAAM_PX_SDIDR_JR_COUNT2 (16U) +/* The count of CAAM_PX_SDID_JR */ +#define CAAM_PX_SDID_JR_COUNT2 (16U) /*! @name PX_SMAPR_JR - Secure Memory Access Permissions register */ /*! @{ */ + #define CAAM_PX_SMAPR_JR_G1_READ_MASK (0x1U) #define CAAM_PX_SMAPR_JR_G1_READ_SHIFT (0U) /*! G1_READ @@ -13752,6 +15404,7 @@ typedef struct { * G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0). */ #define CAAM_PX_SMAPR_JR_G1_READ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G1_READ_SHIFT)) & CAAM_PX_SMAPR_JR_G1_READ_MASK) + #define CAAM_PX_SMAPR_JR_G1_WRITE_MASK (0x2U) #define CAAM_PX_SMAPR_JR_G1_WRITE_SHIFT (1U) /*! G1_WRITE @@ -13761,6 +15414,7 @@ typedef struct { * not a Trusted Descriptor or if G1_TDO=0). */ #define CAAM_PX_SMAPR_JR_G1_WRITE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G1_WRITE_SHIFT)) & CAAM_PX_SMAPR_JR_G1_WRITE_MASK) + #define CAAM_PX_SMAPR_JR_G1_TDO_MASK (0x4U) #define CAAM_PX_SMAPR_JR_G1_TDO_SHIFT (2U) /*! G1_TDO @@ -13770,6 +15424,7 @@ typedef struct { * G1_WRITE and G1_READ settings. */ #define CAAM_PX_SMAPR_JR_G1_TDO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G1_TDO_SHIFT)) & CAAM_PX_SMAPR_JR_G1_TDO_MASK) + #define CAAM_PX_SMAPR_JR_G1_SMBLOB_MASK (0x8U) #define CAAM_PX_SMAPR_JR_G1_SMBLOB_SHIFT (3U) /*! G1_SMBLOB @@ -13777,6 +15432,7 @@ typedef struct { * 0b1..Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings. */ #define CAAM_PX_SMAPR_JR_G1_SMBLOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G1_SMBLOB_SHIFT)) & CAAM_PX_SMAPR_JR_G1_SMBLOB_MASK) + #define CAAM_PX_SMAPR_JR_G2_READ_MASK (0x10U) #define CAAM_PX_SMAPR_JR_G2_READ_SHIFT (4U) /*! G2_READ @@ -13787,6 +15443,7 @@ typedef struct { * G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0). */ #define CAAM_PX_SMAPR_JR_G2_READ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G2_READ_SHIFT)) & CAAM_PX_SMAPR_JR_G2_READ_MASK) + #define CAAM_PX_SMAPR_JR_G2_WRITE_MASK (0x20U) #define CAAM_PX_SMAPR_JR_G2_WRITE_SHIFT (5U) /*! G2_WRITE @@ -13796,6 +15453,7 @@ typedef struct { * not a Trusted Descriptor or if G2_TDO=0). */ #define CAAM_PX_SMAPR_JR_G2_WRITE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G2_WRITE_SHIFT)) & CAAM_PX_SMAPR_JR_G2_WRITE_MASK) + #define CAAM_PX_SMAPR_JR_G2_TDO_MASK (0x40U) #define CAAM_PX_SMAPR_JR_G2_TDO_SHIFT (6U) /*! G2_TDO @@ -13805,6 +15463,7 @@ typedef struct { * G2_WRITE and G2_READ settings. */ #define CAAM_PX_SMAPR_JR_G2_TDO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G2_TDO_SHIFT)) & CAAM_PX_SMAPR_JR_G2_TDO_MASK) + #define CAAM_PX_SMAPR_JR_G2_SMBLOB_MASK (0x80U) #define CAAM_PX_SMAPR_JR_G2_SMBLOB_SHIFT (7U) /*! G2_SMBLOB @@ -13812,6 +15471,7 @@ typedef struct { * 0b1..Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings. */ #define CAAM_PX_SMAPR_JR_G2_SMBLOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G2_SMBLOB_SHIFT)) & CAAM_PX_SMAPR_JR_G2_SMBLOB_MASK) + #define CAAM_PX_SMAPR_JR_SMAG_LCK_MASK (0x1000U) #define CAAM_PX_SMAPR_JR_SMAG_LCK_SHIFT (12U) /*! SMAG_LCK @@ -13820,6 +15480,7 @@ typedef struct { * until the partition is de-allocated or a POR occurs. */ #define CAAM_PX_SMAPR_JR_SMAG_LCK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_SMAG_LCK_SHIFT)) & CAAM_PX_SMAPR_JR_SMAG_LCK_MASK) + #define CAAM_PX_SMAPR_JR_SMAP_LCK_MASK (0x2000U) #define CAAM_PX_SMAPR_JR_SMAP_LCK_SHIFT (13U) /*! SMAP_LCK @@ -13829,6 +15490,7 @@ typedef struct { * still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0. */ #define CAAM_PX_SMAPR_JR_SMAP_LCK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_SMAP_LCK_SHIFT)) & CAAM_PX_SMAPR_JR_SMAP_LCK_MASK) + #define CAAM_PX_SMAPR_JR_PSP_MASK (0x4000U) #define CAAM_PX_SMAPR_JR_PSP_SHIFT (14U) /*! PSP @@ -13836,6 +15498,7 @@ typedef struct { * 0b1..The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated. */ #define CAAM_PX_SMAPR_JR_PSP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_PSP_SHIFT)) & CAAM_PX_SMAPR_JR_PSP_MASK) + #define CAAM_PX_SMAPR_JR_CSP_MASK (0x8000U) #define CAAM_PX_SMAPR_JR_CSP_SHIFT (15U) /*! CSP @@ -13845,6 +15508,7 @@ typedef struct { * partition is released or a security alarm occurs. */ #define CAAM_PX_SMAPR_JR_CSP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_CSP_SHIFT)) & CAAM_PX_SMAPR_JR_CSP_MASK) + #define CAAM_PX_SMAPR_JR_PARTITION_KMOD_MASK (0xFFFF0000U) #define CAAM_PX_SMAPR_JR_PARTITION_KMOD_SHIFT (16U) #define CAAM_PX_SMAPR_JR_PARTITION_KMOD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_PARTITION_KMOD_SHIFT)) & CAAM_PX_SMAPR_JR_PARTITION_KMOD_MASK) @@ -13856,123 +15520,293 @@ typedef struct { /* The count of CAAM_PX_SMAPR_JR */ #define CAAM_PX_SMAPR_JR_COUNT2 (16U) -/*! @name PX_SMAG_JR - Secure Memory Access Group Registers */ -/*! @{ */ -#define CAAM_PX_SMAG_JR_Gx_ID00_MASK (0x1U) -#define CAAM_PX_SMAG_JR_Gx_ID00_SHIFT (0U) -#define CAAM_PX_SMAG_JR_Gx_ID00(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID00_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID00_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID01_MASK (0x2U) -#define CAAM_PX_SMAG_JR_Gx_ID01_SHIFT (1U) -#define CAAM_PX_SMAG_JR_Gx_ID01(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID01_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID01_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID02_MASK (0x4U) -#define CAAM_PX_SMAG_JR_Gx_ID02_SHIFT (2U) -#define CAAM_PX_SMAG_JR_Gx_ID02(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID02_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID02_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID03_MASK (0x8U) -#define CAAM_PX_SMAG_JR_Gx_ID03_SHIFT (3U) -#define CAAM_PX_SMAG_JR_Gx_ID03(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID03_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID03_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID04_MASK (0x10U) -#define CAAM_PX_SMAG_JR_Gx_ID04_SHIFT (4U) -#define CAAM_PX_SMAG_JR_Gx_ID04(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID04_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID04_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID05_MASK (0x20U) -#define CAAM_PX_SMAG_JR_Gx_ID05_SHIFT (5U) -#define CAAM_PX_SMAG_JR_Gx_ID05(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID05_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID05_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID06_MASK (0x40U) -#define CAAM_PX_SMAG_JR_Gx_ID06_SHIFT (6U) -#define CAAM_PX_SMAG_JR_Gx_ID06(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID06_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID06_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID07_MASK (0x80U) -#define CAAM_PX_SMAG_JR_Gx_ID07_SHIFT (7U) -#define CAAM_PX_SMAG_JR_Gx_ID07(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID07_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID07_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID08_MASK (0x100U) -#define CAAM_PX_SMAG_JR_Gx_ID08_SHIFT (8U) -#define CAAM_PX_SMAG_JR_Gx_ID08(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID08_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID08_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID09_MASK (0x200U) -#define CAAM_PX_SMAG_JR_Gx_ID09_SHIFT (9U) -#define CAAM_PX_SMAG_JR_Gx_ID09(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID09_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID09_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID10_MASK (0x400U) -#define CAAM_PX_SMAG_JR_Gx_ID10_SHIFT (10U) -#define CAAM_PX_SMAG_JR_Gx_ID10(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID10_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID10_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID11_MASK (0x800U) -#define CAAM_PX_SMAG_JR_Gx_ID11_SHIFT (11U) -#define CAAM_PX_SMAG_JR_Gx_ID11(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID11_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID11_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID12_MASK (0x1000U) -#define CAAM_PX_SMAG_JR_Gx_ID12_SHIFT (12U) -#define CAAM_PX_SMAG_JR_Gx_ID12(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID12_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID12_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID13_MASK (0x2000U) -#define CAAM_PX_SMAG_JR_Gx_ID13_SHIFT (13U) -#define CAAM_PX_SMAG_JR_Gx_ID13(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID13_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID13_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID14_MASK (0x4000U) -#define CAAM_PX_SMAG_JR_Gx_ID14_SHIFT (14U) -#define CAAM_PX_SMAG_JR_Gx_ID14(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID14_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID14_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID15_MASK (0x8000U) -#define CAAM_PX_SMAG_JR_Gx_ID15_SHIFT (15U) -#define CAAM_PX_SMAG_JR_Gx_ID15(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID15_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID15_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID16_MASK (0x10000U) -#define CAAM_PX_SMAG_JR_Gx_ID16_SHIFT (16U) -#define CAAM_PX_SMAG_JR_Gx_ID16(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID16_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID16_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID17_MASK (0x20000U) -#define CAAM_PX_SMAG_JR_Gx_ID17_SHIFT (17U) -#define CAAM_PX_SMAG_JR_Gx_ID17(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID17_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID17_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID18_MASK (0x40000U) -#define CAAM_PX_SMAG_JR_Gx_ID18_SHIFT (18U) -#define CAAM_PX_SMAG_JR_Gx_ID18(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID18_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID18_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID19_MASK (0x80000U) -#define CAAM_PX_SMAG_JR_Gx_ID19_SHIFT (19U) -#define CAAM_PX_SMAG_JR_Gx_ID19(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID19_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID19_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID20_MASK (0x100000U) -#define CAAM_PX_SMAG_JR_Gx_ID20_SHIFT (20U) -#define CAAM_PX_SMAG_JR_Gx_ID20(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID20_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID20_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID21_MASK (0x200000U) -#define CAAM_PX_SMAG_JR_Gx_ID21_SHIFT (21U) -#define CAAM_PX_SMAG_JR_Gx_ID21(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID21_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID21_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID22_MASK (0x400000U) -#define CAAM_PX_SMAG_JR_Gx_ID22_SHIFT (22U) -#define CAAM_PX_SMAG_JR_Gx_ID22(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID22_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID22_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID23_MASK (0x800000U) -#define CAAM_PX_SMAG_JR_Gx_ID23_SHIFT (23U) -#define CAAM_PX_SMAG_JR_Gx_ID23(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID23_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID23_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID24_MASK (0x1000000U) -#define CAAM_PX_SMAG_JR_Gx_ID24_SHIFT (24U) -#define CAAM_PX_SMAG_JR_Gx_ID24(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID24_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID24_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID25_MASK (0x2000000U) -#define CAAM_PX_SMAG_JR_Gx_ID25_SHIFT (25U) -#define CAAM_PX_SMAG_JR_Gx_ID25(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID25_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID25_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID26_MASK (0x4000000U) -#define CAAM_PX_SMAG_JR_Gx_ID26_SHIFT (26U) -#define CAAM_PX_SMAG_JR_Gx_ID26(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID26_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID26_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID27_MASK (0x8000000U) -#define CAAM_PX_SMAG_JR_Gx_ID27_SHIFT (27U) -#define CAAM_PX_SMAG_JR_Gx_ID27(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID27_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID27_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID28_MASK (0x10000000U) -#define CAAM_PX_SMAG_JR_Gx_ID28_SHIFT (28U) -#define CAAM_PX_SMAG_JR_Gx_ID28(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID28_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID28_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID29_MASK (0x20000000U) -#define CAAM_PX_SMAG_JR_Gx_ID29_SHIFT (29U) -#define CAAM_PX_SMAG_JR_Gx_ID29(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID29_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID29_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID30_MASK (0x40000000U) -#define CAAM_PX_SMAG_JR_Gx_ID30_SHIFT (30U) -#define CAAM_PX_SMAG_JR_Gx_ID30(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID30_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID30_MASK) -#define CAAM_PX_SMAG_JR_Gx_ID31_MASK (0x80000000U) -#define CAAM_PX_SMAG_JR_Gx_ID31_SHIFT (31U) -#define CAAM_PX_SMAG_JR_Gx_ID31(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG_JR_Gx_ID31_SHIFT)) & CAAM_PX_SMAG_JR_Gx_ID31_MASK) -/*! @} */ - -/* The count of CAAM_PX_SMAG_JR */ -#define CAAM_PX_SMAG_JR_COUNT (4U) - -/* The count of CAAM_PX_SMAG_JR */ -#define CAAM_PX_SMAG_JR_COUNT2 (16U) - -/* The count of CAAM_PX_SMAG_JR */ -#define CAAM_PX_SMAG_JR_COUNT3 (2U) +/*! @name PX_SMAG2_JR - Secure Memory Access Group Registers */ +/*! @{ */ + +#define CAAM_PX_SMAG2_JR_Gx_ID00_MASK (0x1U) +#define CAAM_PX_SMAG2_JR_Gx_ID00_SHIFT (0U) +#define CAAM_PX_SMAG2_JR_Gx_ID00(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID00_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID00_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID01_MASK (0x2U) +#define CAAM_PX_SMAG2_JR_Gx_ID01_SHIFT (1U) +#define CAAM_PX_SMAG2_JR_Gx_ID01(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID01_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID01_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID02_MASK (0x4U) +#define CAAM_PX_SMAG2_JR_Gx_ID02_SHIFT (2U) +#define CAAM_PX_SMAG2_JR_Gx_ID02(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID02_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID02_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID03_MASK (0x8U) +#define CAAM_PX_SMAG2_JR_Gx_ID03_SHIFT (3U) +#define CAAM_PX_SMAG2_JR_Gx_ID03(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID03_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID03_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID04_MASK (0x10U) +#define CAAM_PX_SMAG2_JR_Gx_ID04_SHIFT (4U) +#define CAAM_PX_SMAG2_JR_Gx_ID04(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID04_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID04_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID05_MASK (0x20U) +#define CAAM_PX_SMAG2_JR_Gx_ID05_SHIFT (5U) +#define CAAM_PX_SMAG2_JR_Gx_ID05(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID05_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID05_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID06_MASK (0x40U) +#define CAAM_PX_SMAG2_JR_Gx_ID06_SHIFT (6U) +#define CAAM_PX_SMAG2_JR_Gx_ID06(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID06_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID06_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID07_MASK (0x80U) +#define CAAM_PX_SMAG2_JR_Gx_ID07_SHIFT (7U) +#define CAAM_PX_SMAG2_JR_Gx_ID07(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID07_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID07_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID08_MASK (0x100U) +#define CAAM_PX_SMAG2_JR_Gx_ID08_SHIFT (8U) +#define CAAM_PX_SMAG2_JR_Gx_ID08(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID08_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID08_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID09_MASK (0x200U) +#define CAAM_PX_SMAG2_JR_Gx_ID09_SHIFT (9U) +#define CAAM_PX_SMAG2_JR_Gx_ID09(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID09_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID09_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID10_MASK (0x400U) +#define CAAM_PX_SMAG2_JR_Gx_ID10_SHIFT (10U) +#define CAAM_PX_SMAG2_JR_Gx_ID10(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID10_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID10_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID11_MASK (0x800U) +#define CAAM_PX_SMAG2_JR_Gx_ID11_SHIFT (11U) +#define CAAM_PX_SMAG2_JR_Gx_ID11(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID11_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID11_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID12_MASK (0x1000U) +#define CAAM_PX_SMAG2_JR_Gx_ID12_SHIFT (12U) +#define CAAM_PX_SMAG2_JR_Gx_ID12(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID12_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID12_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID13_MASK (0x2000U) +#define CAAM_PX_SMAG2_JR_Gx_ID13_SHIFT (13U) +#define CAAM_PX_SMAG2_JR_Gx_ID13(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID13_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID13_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID14_MASK (0x4000U) +#define CAAM_PX_SMAG2_JR_Gx_ID14_SHIFT (14U) +#define CAAM_PX_SMAG2_JR_Gx_ID14(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID14_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID14_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID15_MASK (0x8000U) +#define CAAM_PX_SMAG2_JR_Gx_ID15_SHIFT (15U) +#define CAAM_PX_SMAG2_JR_Gx_ID15(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID15_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID15_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID16_MASK (0x10000U) +#define CAAM_PX_SMAG2_JR_Gx_ID16_SHIFT (16U) +#define CAAM_PX_SMAG2_JR_Gx_ID16(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID16_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID16_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID17_MASK (0x20000U) +#define CAAM_PX_SMAG2_JR_Gx_ID17_SHIFT (17U) +#define CAAM_PX_SMAG2_JR_Gx_ID17(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID17_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID17_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID18_MASK (0x40000U) +#define CAAM_PX_SMAG2_JR_Gx_ID18_SHIFT (18U) +#define CAAM_PX_SMAG2_JR_Gx_ID18(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID18_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID18_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID19_MASK (0x80000U) +#define CAAM_PX_SMAG2_JR_Gx_ID19_SHIFT (19U) +#define CAAM_PX_SMAG2_JR_Gx_ID19(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID19_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID19_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID20_MASK (0x100000U) +#define CAAM_PX_SMAG2_JR_Gx_ID20_SHIFT (20U) +#define CAAM_PX_SMAG2_JR_Gx_ID20(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID20_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID20_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID21_MASK (0x200000U) +#define CAAM_PX_SMAG2_JR_Gx_ID21_SHIFT (21U) +#define CAAM_PX_SMAG2_JR_Gx_ID21(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID21_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID21_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID22_MASK (0x400000U) +#define CAAM_PX_SMAG2_JR_Gx_ID22_SHIFT (22U) +#define CAAM_PX_SMAG2_JR_Gx_ID22(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID22_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID22_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID23_MASK (0x800000U) +#define CAAM_PX_SMAG2_JR_Gx_ID23_SHIFT (23U) +#define CAAM_PX_SMAG2_JR_Gx_ID23(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID23_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID23_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID24_MASK (0x1000000U) +#define CAAM_PX_SMAG2_JR_Gx_ID24_SHIFT (24U) +#define CAAM_PX_SMAG2_JR_Gx_ID24(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID24_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID24_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID25_MASK (0x2000000U) +#define CAAM_PX_SMAG2_JR_Gx_ID25_SHIFT (25U) +#define CAAM_PX_SMAG2_JR_Gx_ID25(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID25_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID25_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID26_MASK (0x4000000U) +#define CAAM_PX_SMAG2_JR_Gx_ID26_SHIFT (26U) +#define CAAM_PX_SMAG2_JR_Gx_ID26(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID26_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID26_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID27_MASK (0x8000000U) +#define CAAM_PX_SMAG2_JR_Gx_ID27_SHIFT (27U) +#define CAAM_PX_SMAG2_JR_Gx_ID27(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID27_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID27_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID28_MASK (0x10000000U) +#define CAAM_PX_SMAG2_JR_Gx_ID28_SHIFT (28U) +#define CAAM_PX_SMAG2_JR_Gx_ID28(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID28_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID28_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID29_MASK (0x20000000U) +#define CAAM_PX_SMAG2_JR_Gx_ID29_SHIFT (29U) +#define CAAM_PX_SMAG2_JR_Gx_ID29(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID29_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID29_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID30_MASK (0x40000000U) +#define CAAM_PX_SMAG2_JR_Gx_ID30_SHIFT (30U) +#define CAAM_PX_SMAG2_JR_Gx_ID30(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID30_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID30_MASK) + +#define CAAM_PX_SMAG2_JR_Gx_ID31_MASK (0x80000000U) +#define CAAM_PX_SMAG2_JR_Gx_ID31_SHIFT (31U) +#define CAAM_PX_SMAG2_JR_Gx_ID31(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID31_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID31_MASK) +/*! @} */ + +/* The count of CAAM_PX_SMAG2_JR */ +#define CAAM_PX_SMAG2_JR_COUNT (4U) + +/* The count of CAAM_PX_SMAG2_JR */ +#define CAAM_PX_SMAG2_JR_COUNT2 (16U) + +/*! @name PX_SMAG1_JR - Secure Memory Access Group Registers */ +/*! @{ */ + +#define CAAM_PX_SMAG1_JR_Gx_ID00_MASK (0x1U) +#define CAAM_PX_SMAG1_JR_Gx_ID00_SHIFT (0U) +#define CAAM_PX_SMAG1_JR_Gx_ID00(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID00_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID00_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID01_MASK (0x2U) +#define CAAM_PX_SMAG1_JR_Gx_ID01_SHIFT (1U) +#define CAAM_PX_SMAG1_JR_Gx_ID01(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID01_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID01_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID02_MASK (0x4U) +#define CAAM_PX_SMAG1_JR_Gx_ID02_SHIFT (2U) +#define CAAM_PX_SMAG1_JR_Gx_ID02(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID02_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID02_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID03_MASK (0x8U) +#define CAAM_PX_SMAG1_JR_Gx_ID03_SHIFT (3U) +#define CAAM_PX_SMAG1_JR_Gx_ID03(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID03_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID03_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID04_MASK (0x10U) +#define CAAM_PX_SMAG1_JR_Gx_ID04_SHIFT (4U) +#define CAAM_PX_SMAG1_JR_Gx_ID04(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID04_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID04_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID05_MASK (0x20U) +#define CAAM_PX_SMAG1_JR_Gx_ID05_SHIFT (5U) +#define CAAM_PX_SMAG1_JR_Gx_ID05(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID05_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID05_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID06_MASK (0x40U) +#define CAAM_PX_SMAG1_JR_Gx_ID06_SHIFT (6U) +#define CAAM_PX_SMAG1_JR_Gx_ID06(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID06_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID06_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID07_MASK (0x80U) +#define CAAM_PX_SMAG1_JR_Gx_ID07_SHIFT (7U) +#define CAAM_PX_SMAG1_JR_Gx_ID07(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID07_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID07_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID08_MASK (0x100U) +#define CAAM_PX_SMAG1_JR_Gx_ID08_SHIFT (8U) +#define CAAM_PX_SMAG1_JR_Gx_ID08(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID08_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID08_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID09_MASK (0x200U) +#define CAAM_PX_SMAG1_JR_Gx_ID09_SHIFT (9U) +#define CAAM_PX_SMAG1_JR_Gx_ID09(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID09_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID09_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID10_MASK (0x400U) +#define CAAM_PX_SMAG1_JR_Gx_ID10_SHIFT (10U) +#define CAAM_PX_SMAG1_JR_Gx_ID10(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID10_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID10_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID11_MASK (0x800U) +#define CAAM_PX_SMAG1_JR_Gx_ID11_SHIFT (11U) +#define CAAM_PX_SMAG1_JR_Gx_ID11(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID11_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID11_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID12_MASK (0x1000U) +#define CAAM_PX_SMAG1_JR_Gx_ID12_SHIFT (12U) +#define CAAM_PX_SMAG1_JR_Gx_ID12(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID12_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID12_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID13_MASK (0x2000U) +#define CAAM_PX_SMAG1_JR_Gx_ID13_SHIFT (13U) +#define CAAM_PX_SMAG1_JR_Gx_ID13(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID13_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID13_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID14_MASK (0x4000U) +#define CAAM_PX_SMAG1_JR_Gx_ID14_SHIFT (14U) +#define CAAM_PX_SMAG1_JR_Gx_ID14(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID14_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID14_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID15_MASK (0x8000U) +#define CAAM_PX_SMAG1_JR_Gx_ID15_SHIFT (15U) +#define CAAM_PX_SMAG1_JR_Gx_ID15(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID15_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID15_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID16_MASK (0x10000U) +#define CAAM_PX_SMAG1_JR_Gx_ID16_SHIFT (16U) +#define CAAM_PX_SMAG1_JR_Gx_ID16(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID16_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID16_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID17_MASK (0x20000U) +#define CAAM_PX_SMAG1_JR_Gx_ID17_SHIFT (17U) +#define CAAM_PX_SMAG1_JR_Gx_ID17(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID17_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID17_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID18_MASK (0x40000U) +#define CAAM_PX_SMAG1_JR_Gx_ID18_SHIFT (18U) +#define CAAM_PX_SMAG1_JR_Gx_ID18(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID18_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID18_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID19_MASK (0x80000U) +#define CAAM_PX_SMAG1_JR_Gx_ID19_SHIFT (19U) +#define CAAM_PX_SMAG1_JR_Gx_ID19(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID19_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID19_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID20_MASK (0x100000U) +#define CAAM_PX_SMAG1_JR_Gx_ID20_SHIFT (20U) +#define CAAM_PX_SMAG1_JR_Gx_ID20(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID20_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID20_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID21_MASK (0x200000U) +#define CAAM_PX_SMAG1_JR_Gx_ID21_SHIFT (21U) +#define CAAM_PX_SMAG1_JR_Gx_ID21(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID21_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID21_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID22_MASK (0x400000U) +#define CAAM_PX_SMAG1_JR_Gx_ID22_SHIFT (22U) +#define CAAM_PX_SMAG1_JR_Gx_ID22(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID22_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID22_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID23_MASK (0x800000U) +#define CAAM_PX_SMAG1_JR_Gx_ID23_SHIFT (23U) +#define CAAM_PX_SMAG1_JR_Gx_ID23(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID23_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID23_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID24_MASK (0x1000000U) +#define CAAM_PX_SMAG1_JR_Gx_ID24_SHIFT (24U) +#define CAAM_PX_SMAG1_JR_Gx_ID24(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID24_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID24_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID25_MASK (0x2000000U) +#define CAAM_PX_SMAG1_JR_Gx_ID25_SHIFT (25U) +#define CAAM_PX_SMAG1_JR_Gx_ID25(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID25_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID25_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID26_MASK (0x4000000U) +#define CAAM_PX_SMAG1_JR_Gx_ID26_SHIFT (26U) +#define CAAM_PX_SMAG1_JR_Gx_ID26(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID26_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID26_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID27_MASK (0x8000000U) +#define CAAM_PX_SMAG1_JR_Gx_ID27_SHIFT (27U) +#define CAAM_PX_SMAG1_JR_Gx_ID27(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID27_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID27_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID28_MASK (0x10000000U) +#define CAAM_PX_SMAG1_JR_Gx_ID28_SHIFT (28U) +#define CAAM_PX_SMAG1_JR_Gx_ID28(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID28_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID28_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID29_MASK (0x20000000U) +#define CAAM_PX_SMAG1_JR_Gx_ID29_SHIFT (29U) +#define CAAM_PX_SMAG1_JR_Gx_ID29(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID29_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID29_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID30_MASK (0x40000000U) +#define CAAM_PX_SMAG1_JR_Gx_ID30_SHIFT (30U) +#define CAAM_PX_SMAG1_JR_Gx_ID30(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID30_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID30_MASK) + +#define CAAM_PX_SMAG1_JR_Gx_ID31_MASK (0x80000000U) +#define CAAM_PX_SMAG1_JR_Gx_ID31_SHIFT (31U) +#define CAAM_PX_SMAG1_JR_Gx_ID31(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID31_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID31_MASK) +/*! @} */ + +/* The count of CAAM_PX_SMAG1_JR */ +#define CAAM_PX_SMAG1_JR_COUNT (4U) + +/* The count of CAAM_PX_SMAG1_JR */ +#define CAAM_PX_SMAG1_JR_COUNT2 (16U) /*! @name SMCR_JR - Secure Memory Command Register */ /*! @{ */ + #define CAAM_SMCR_JR_CMD_MASK (0xFU) #define CAAM_SMCR_JR_CMD_SHIFT (0U) #define CAAM_SMCR_JR_CMD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_JR_CMD_SHIFT)) & CAAM_SMCR_JR_CMD_MASK) + #define CAAM_SMCR_JR_PRTN_MASK (0xF00U) #define CAAM_SMCR_JR_PRTN_SHIFT (8U) #define CAAM_SMCR_JR_PRTN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_JR_PRTN_SHIFT)) & CAAM_SMCR_JR_PRTN_MASK) + #define CAAM_SMCR_JR_PAGE_MASK (0xFFFF0000U) #define CAAM_SMCR_JR_PAGE_SHIFT (16U) #define CAAM_SMCR_JR_PAGE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_JR_PAGE_SHIFT)) & CAAM_SMCR_JR_PAGE_MASK) @@ -13983,9 +15817,11 @@ typedef struct { /*! @name SMCSR_JR - Secure Memory Command Status Register */ /*! @{ */ + #define CAAM_SMCSR_JR_PRTN_MASK (0xFU) #define CAAM_SMCSR_JR_PRTN_SHIFT (0U) #define CAAM_SMCSR_JR_PRTN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_PRTN_SHIFT)) & CAAM_SMCSR_JR_PRTN_MASK) + #define CAAM_SMCSR_JR_PO_MASK (0xC0U) #define CAAM_SMCSR_JR_PO_SHIFT (6U) /*! PO @@ -13998,9 +15834,11 @@ typedef struct { * upon de-allocation. */ #define CAAM_SMCSR_JR_PO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_PO_SHIFT)) & CAAM_SMCSR_JR_PO_MASK) + #define CAAM_SMCSR_JR_AERR_MASK (0x3000U) #define CAAM_SMCSR_JR_AERR_SHIFT (12U) #define CAAM_SMCSR_JR_AERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_AERR_SHIFT)) & CAAM_SMCSR_JR_AERR_MASK) + #define CAAM_SMCSR_JR_CERR_MASK (0xC000U) #define CAAM_SMCSR_JR_CERR_SHIFT (14U) /*! CERR @@ -14011,6 +15849,7 @@ typedef struct { * command completed. The additional command was ignored. */ #define CAAM_SMCSR_JR_CERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_CERR_SHIFT)) & CAAM_SMCSR_JR_CERR_MASK) + #define CAAM_SMCSR_JR_PAGE_MASK (0xFFF0000U) #define CAAM_SMCSR_JR_PAGE_SHIFT (16U) #define CAAM_SMCSR_JR_PAGE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_PAGE_SHIFT)) & CAAM_SMCSR_JR_PAGE_MASK) @@ -14021,9 +15860,11 @@ typedef struct { /*! @name REIR0JR - Recoverable Error Interrupt Record 0 for Job Ring 0..Recoverable Error Interrupt Record 0 for Job Ring 3 */ /*! @{ */ + #define CAAM_REIR0JR_TYPE_MASK (0x3000000U) #define CAAM_REIR0JR_TYPE_SHIFT (24U) #define CAAM_REIR0JR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR0JR_TYPE_SHIFT)) & CAAM_REIR0JR_TYPE_MASK) + #define CAAM_REIR0JR_MISS_MASK (0x80000000U) #define CAAM_REIR0JR_MISS_SHIFT (31U) #define CAAM_REIR0JR_MISS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR0JR_MISS_SHIFT)) & CAAM_REIR0JR_MISS_MASK) @@ -14034,6 +15875,7 @@ typedef struct { /*! @name REIR2JR - Recoverable Error Interrupt Record 2 for Job Ring 0..Recoverable Error Interrupt Record 2 for Job Ring 3 */ /*! @{ */ + #define CAAM_REIR2JR_ADDR_MASK (0xFFFFFFFFFU) #define CAAM_REIR2JR_ADDR_SHIFT (0U) #define CAAM_REIR2JR_ADDR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_REIR2JR_ADDR_SHIFT)) & CAAM_REIR2JR_ADDR_MASK) @@ -14044,24 +15886,31 @@ typedef struct { /*! @name REIR4JR - Recoverable Error Interrupt Record 4 for Job Ring 0..Recoverable Error Interrupt Record 4 for Job Ring 3 */ /*! @{ */ + #define CAAM_REIR4JR_ICID_MASK (0x7FFU) #define CAAM_REIR4JR_ICID_SHIFT (0U) #define CAAM_REIR4JR_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_ICID_SHIFT)) & CAAM_REIR4JR_ICID_MASK) + #define CAAM_REIR4JR_DID_MASK (0x7800U) #define CAAM_REIR4JR_DID_SHIFT (11U) #define CAAM_REIR4JR_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_DID_SHIFT)) & CAAM_REIR4JR_DID_MASK) + #define CAAM_REIR4JR_AXCACHE_MASK (0xF0000U) #define CAAM_REIR4JR_AXCACHE_SHIFT (16U) #define CAAM_REIR4JR_AXCACHE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_AXCACHE_SHIFT)) & CAAM_REIR4JR_AXCACHE_MASK) + #define CAAM_REIR4JR_AXPROT_MASK (0x700000U) #define CAAM_REIR4JR_AXPROT_SHIFT (20U) #define CAAM_REIR4JR_AXPROT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_AXPROT_SHIFT)) & CAAM_REIR4JR_AXPROT_MASK) + #define CAAM_REIR4JR_RWB_MASK (0x800000U) #define CAAM_REIR4JR_RWB_SHIFT (23U) #define CAAM_REIR4JR_RWB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_RWB_SHIFT)) & CAAM_REIR4JR_RWB_MASK) + #define CAAM_REIR4JR_ERR_MASK (0x30000000U) #define CAAM_REIR4JR_ERR_SHIFT (28U) #define CAAM_REIR4JR_ERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_ERR_SHIFT)) & CAAM_REIR4JR_ERR_MASK) + #define CAAM_REIR4JR_MIX_MASK (0xC0000000U) #define CAAM_REIR4JR_MIX_SHIFT (30U) #define CAAM_REIR4JR_MIX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_MIX_SHIFT)) & CAAM_REIR4JR_MIX_MASK) @@ -14072,21 +15921,27 @@ typedef struct { /*! @name REIR5JR - Recoverable Error Interrupt Record 5 for Job Ring 0..Recoverable Error Interrupt Record 5 for Job Ring 3 */ /*! @{ */ + #define CAAM_REIR5JR_BID_MASK (0xF0000U) #define CAAM_REIR5JR_BID_SHIFT (16U) #define CAAM_REIR5JR_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_BID_SHIFT)) & CAAM_REIR5JR_BID_MASK) + #define CAAM_REIR5JR_BNDG_MASK (0x2000000U) #define CAAM_REIR5JR_BNDG_SHIFT (25U) #define CAAM_REIR5JR_BNDG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_BNDG_SHIFT)) & CAAM_REIR5JR_BNDG_MASK) + #define CAAM_REIR5JR_TDSC_MASK (0x4000000U) #define CAAM_REIR5JR_TDSC_SHIFT (26U) #define CAAM_REIR5JR_TDSC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_TDSC_SHIFT)) & CAAM_REIR5JR_TDSC_MASK) + #define CAAM_REIR5JR_KMOD_MASK (0x8000000U) #define CAAM_REIR5JR_KMOD_SHIFT (27U) #define CAAM_REIR5JR_KMOD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_KMOD_SHIFT)) & CAAM_REIR5JR_KMOD_MASK) + #define CAAM_REIR5JR_KEY_MASK (0x10000000U) #define CAAM_REIR5JR_KEY_SHIFT (28U) #define CAAM_REIR5JR_KEY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_KEY_SHIFT)) & CAAM_REIR5JR_KEY_MASK) + #define CAAM_REIR5JR_SMA_MASK (0x20000000U) #define CAAM_REIR5JR_SMA_SHIFT (29U) #define CAAM_REIR5JR_SMA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_SMA_SHIFT)) & CAAM_REIR5JR_SMA_MASK) @@ -14097,6 +15952,7 @@ typedef struct { /*! @name RSTA - RTIC Status Register */ /*! @{ */ + #define CAAM_RSTA_BSY_MASK (0x1U) #define CAAM_RSTA_BSY_SHIFT (0U) /*! BSY @@ -14104,6 +15960,7 @@ typedef struct { * 0b1..RTIC Busy. */ #define CAAM_RSTA_BSY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_BSY_SHIFT)) & CAAM_RSTA_BSY_MASK) + #define CAAM_RSTA_HD_MASK (0x2U) #define CAAM_RSTA_HD_SHIFT (1U) /*! HD @@ -14111,6 +15968,7 @@ typedef struct { * 0b1..Authenticate code/generate reference hash value. This bit cannot be modified during run-time checking mode. */ #define CAAM_RSTA_HD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_HD_SHIFT)) & CAAM_RSTA_HD_MASK) + #define CAAM_RSTA_SV_MASK (0x4U) #define CAAM_RSTA_SV_SHIFT (2U) /*! SV @@ -14118,6 +15976,7 @@ typedef struct { * 0b1..Memory block hash doesn't match reference value. */ #define CAAM_RSTA_SV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_SV_SHIFT)) & CAAM_RSTA_SV_MASK) + #define CAAM_RSTA_HE_MASK (0x8U) #define CAAM_RSTA_HE_SHIFT (3U) /*! HE @@ -14125,6 +15984,7 @@ typedef struct { * 0b1..Memory block hash doesn't match reference value. */ #define CAAM_RSTA_HE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_HE_SHIFT)) & CAAM_RSTA_HE_MASK) + #define CAAM_RSTA_MIS_MASK (0xF0U) #define CAAM_RSTA_MIS_SHIFT (4U) /*! MIS @@ -14132,6 +15992,7 @@ typedef struct { * 0b0001..Memory Block X has been corrupted */ #define CAAM_RSTA_MIS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_MIS_SHIFT)) & CAAM_RSTA_MIS_MASK) + #define CAAM_RSTA_AE_MASK (0xF00U) #define CAAM_RSTA_AE_SHIFT (8U) /*! AE @@ -14139,6 +16000,7 @@ typedef struct { * 0b0001..An illegal address was accessed by the RTIC */ #define CAAM_RSTA_AE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_AE_SHIFT)) & CAAM_RSTA_AE_MASK) + #define CAAM_RSTA_WE_MASK (0x10000U) #define CAAM_RSTA_WE_SHIFT (16U) /*! WE @@ -14146,15 +16008,19 @@ typedef struct { * 0b1..RTIC Watchdog timer has expired prior to completing a round of hashing. */ #define CAAM_RSTA_WE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_WE_SHIFT)) & CAAM_RSTA_WE_MASK) + #define CAAM_RSTA_ABH_MASK (0x20000U) #define CAAM_RSTA_ABH_SHIFT (17U) #define CAAM_RSTA_ABH(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_ABH_SHIFT)) & CAAM_RSTA_ABH_MASK) + #define CAAM_RSTA_HOD_MASK (0x40000U) #define CAAM_RSTA_HOD_SHIFT (18U) #define CAAM_RSTA_HOD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_HOD_SHIFT)) & CAAM_RSTA_HOD_MASK) + #define CAAM_RSTA_RTD_MASK (0x80000U) #define CAAM_RSTA_RTD_SHIFT (19U) #define CAAM_RSTA_RTD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_RTD_SHIFT)) & CAAM_RSTA_RTD_MASK) + #define CAAM_RSTA_CS_MASK (0x6000000U) #define CAAM_RSTA_CS_SHIFT (25U) /*! CS @@ -14168,6 +16034,7 @@ typedef struct { /*! @name RCMD - RTIC Command Register */ /*! @{ */ + #define CAAM_RCMD_CINT_MASK (0x1U) #define CAAM_RCMD_CINT_SHIFT (0U) /*! CINT @@ -14175,6 +16042,7 @@ typedef struct { * 0b1..Clear interrupt. This bit cannot be modified during run-time checking mode */ #define CAAM_RCMD_CINT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCMD_CINT_SHIFT)) & CAAM_RCMD_CINT_MASK) + #define CAAM_RCMD_HO_MASK (0x2U) #define CAAM_RCMD_HO_SHIFT (1U) /*! HO @@ -14182,6 +16050,7 @@ typedef struct { * 0b1..Authenticate code/generate reference hash value. This bit cannot be modified during run-time checking mode. */ #define CAAM_RCMD_HO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCMD_HO_SHIFT)) & CAAM_RCMD_HO_MASK) + #define CAAM_RCMD_RTC_MASK (0x4U) #define CAAM_RCMD_RTC_SHIFT (2U) /*! RTC @@ -14189,6 +16058,7 @@ typedef struct { * 0b1..Verify run-time memory blocks continually */ #define CAAM_RCMD_RTC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCMD_RTC_SHIFT)) & CAAM_RCMD_RTC_MASK) + #define CAAM_RCMD_RTD_MASK (0x8U) #define CAAM_RCMD_RTD_SHIFT (3U) /*! RTD @@ -14200,6 +16070,7 @@ typedef struct { /*! @name RCTL - RTIC Control Register */ /*! @{ */ + #define CAAM_RCTL_IE_MASK (0x1U) #define CAAM_RCTL_IE_SHIFT (0U) /*! IE @@ -14207,21 +16078,27 @@ typedef struct { * 0b1..Interrupts enabled */ #define CAAM_RCTL_IE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_IE_SHIFT)) & CAAM_RCTL_IE_MASK) + #define CAAM_RCTL_RREQS_MASK (0xEU) #define CAAM_RCTL_RREQS_SHIFT (1U) #define CAAM_RCTL_RREQS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RREQS_SHIFT)) & CAAM_RCTL_RREQS_MASK) + #define CAAM_RCTL_HOME_MASK (0xF0U) #define CAAM_RCTL_HOME_SHIFT (4U) #define CAAM_RCTL_HOME(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_HOME_SHIFT)) & CAAM_RCTL_HOME_MASK) + #define CAAM_RCTL_RTME_MASK (0xF00U) #define CAAM_RCTL_RTME_SHIFT (8U) #define CAAM_RCTL_RTME(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RTME_SHIFT)) & CAAM_RCTL_RTME_MASK) + #define CAAM_RCTL_RTMU_MASK (0xF000U) #define CAAM_RCTL_RTMU_SHIFT (12U) #define CAAM_RCTL_RTMU(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RTMU_SHIFT)) & CAAM_RCTL_RTMU_MASK) + #define CAAM_RCTL_RALG_MASK (0xF0000U) #define CAAM_RCTL_RALG_SHIFT (16U) #define CAAM_RCTL_RALG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RALG_SHIFT)) & CAAM_RCTL_RALG_MASK) + #define CAAM_RCTL_RIDLE_MASK (0x100000U) #define CAAM_RCTL_RIDLE_SHIFT (20U) #define CAAM_RCTL_RIDLE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RIDLE_SHIFT)) & CAAM_RCTL_RIDLE_MASK) @@ -14229,6 +16106,7 @@ typedef struct { /*! @name RTHR - RTIC Throttle Register */ /*! @{ */ + #define CAAM_RTHR_RTHR_MASK (0xFFFFU) #define CAAM_RTHR_RTHR_SHIFT (0U) #define CAAM_RTHR_RTHR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTHR_RTHR_SHIFT)) & CAAM_RTHR_RTHR_MASK) @@ -14236,6 +16114,7 @@ typedef struct { /*! @name RWDOG - RTIC Watchdog Timer */ /*! @{ */ + #define CAAM_RWDOG_RWDOG_MASK (0xFFFFFFFFU) #define CAAM_RWDOG_RWDOG_SHIFT (0U) #define CAAM_RWDOG_RWDOG(x) (((uint64_t)(((uint64_t)(x)) << CAAM_RWDOG_RWDOG_SHIFT)) & CAAM_RWDOG_RWDOG_MASK) @@ -14243,6 +16122,7 @@ typedef struct { /*! @name REND - RTIC Endian Register */ /*! @{ */ + #define CAAM_REND_REPO_MASK (0xFU) #define CAAM_REND_REPO_SHIFT (0U) /*! REPO @@ -14252,6 +16132,7 @@ typedef struct { * 0b1xxx..Byte Swap Memory Block D */ #define CAAM_REND_REPO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REND_REPO_SHIFT)) & CAAM_REND_REPO_MASK) + #define CAAM_REND_RBS_MASK (0xF0U) #define CAAM_REND_RBS_SHIFT (4U) /*! RBS @@ -14261,6 +16142,7 @@ typedef struct { * 0b1xxx..Byte Swap Memory Block D */ #define CAAM_REND_RBS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REND_RBS_SHIFT)) & CAAM_REND_RBS_MASK) + #define CAAM_REND_RHWS_MASK (0xF00U) #define CAAM_REND_RHWS_SHIFT (8U) /*! RHWS @@ -14270,6 +16152,7 @@ typedef struct { * 0b1xxx..Half-Word Swap Memory Block D */ #define CAAM_REND_RHWS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REND_RHWS_SHIFT)) & CAAM_REND_RHWS_MASK) + #define CAAM_REND_RWS_MASK (0xF000U) #define CAAM_REND_RWS_SHIFT (12U) /*! RWS @@ -14283,6 +16166,7 @@ typedef struct { /*! @name RMA - RTIC Memory Block A Address 0 Register..RTIC Memory Block D Address 1 Register */ /*! @{ */ + #define CAAM_RMA_MEMBLKADDR_MASK (0xFFFFFFFFFU) #define CAAM_RMA_MEMBLKADDR_SHIFT (0U) #define CAAM_RMA_MEMBLKADDR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_RMA_MEMBLKADDR_SHIFT)) & CAAM_RMA_MEMBLKADDR_MASK) @@ -14296,6 +16180,7 @@ typedef struct { /*! @name RML - RTIC Memory Block A Length 0 Register..RTIC Memory Block D Length 1 Register */ /*! @{ */ + #define CAAM_RML_MEMBLKLEN_MASK (0xFFFFFFFFU) #define CAAM_RML_MEMBLKLEN_SHIFT (0U) #define CAAM_RML_MEMBLKLEN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RML_MEMBLKLEN_SHIFT)) & CAAM_RML_MEMBLKLEN_MASK) @@ -14309,6 +16194,7 @@ typedef struct { /*! @name RMD - RTIC Memory Block A Big Endian Hash Result Word 0..RTIC Memory Block D Little Endian Hash Result Word 31 */ /*! @{ */ + #define CAAM_RMD_RTIC_Hash_Result_MASK (0xFFFFFFFFU) #define CAAM_RMD_RTIC_Hash_Result_SHIFT (0U) #define CAAM_RMD_RTIC_Hash_Result(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RMD_RTIC_Hash_Result_SHIFT)) & CAAM_RMD_RTIC_Hash_Result_MASK) @@ -14325,9 +16211,11 @@ typedef struct { /*! @name REIR0RTIC - Recoverable Error Interrupt Record 0 for RTIC */ /*! @{ */ + #define CAAM_REIR0RTIC_TYPE_MASK (0x3000000U) #define CAAM_REIR0RTIC_TYPE_SHIFT (24U) #define CAAM_REIR0RTIC_TYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR0RTIC_TYPE_SHIFT)) & CAAM_REIR0RTIC_TYPE_MASK) + #define CAAM_REIR0RTIC_MISS_MASK (0x80000000U) #define CAAM_REIR0RTIC_MISS_SHIFT (31U) #define CAAM_REIR0RTIC_MISS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR0RTIC_MISS_SHIFT)) & CAAM_REIR0RTIC_MISS_MASK) @@ -14335,6 +16223,7 @@ typedef struct { /*! @name REIR2RTIC - Recoverable Error Interrupt Record 2 for RTIC */ /*! @{ */ + #define CAAM_REIR2RTIC_ADDR_MASK (0xFFFFFFFFFFFFFFFFU) #define CAAM_REIR2RTIC_ADDR_SHIFT (0U) #define CAAM_REIR2RTIC_ADDR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_REIR2RTIC_ADDR_SHIFT)) & CAAM_REIR2RTIC_ADDR_MASK) @@ -14342,24 +16231,31 @@ typedef struct { /*! @name REIR4RTIC - Recoverable Error Interrupt Record 4 for RTIC */ /*! @{ */ + #define CAAM_REIR4RTIC_ICID_MASK (0x7FFU) #define CAAM_REIR4RTIC_ICID_SHIFT (0U) #define CAAM_REIR4RTIC_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_ICID_SHIFT)) & CAAM_REIR4RTIC_ICID_MASK) + #define CAAM_REIR4RTIC_DID_MASK (0x7800U) #define CAAM_REIR4RTIC_DID_SHIFT (11U) #define CAAM_REIR4RTIC_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_DID_SHIFT)) & CAAM_REIR4RTIC_DID_MASK) + #define CAAM_REIR4RTIC_AXCACHE_MASK (0xF0000U) #define CAAM_REIR4RTIC_AXCACHE_SHIFT (16U) #define CAAM_REIR4RTIC_AXCACHE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_AXCACHE_SHIFT)) & CAAM_REIR4RTIC_AXCACHE_MASK) + #define CAAM_REIR4RTIC_AXPROT_MASK (0x700000U) #define CAAM_REIR4RTIC_AXPROT_SHIFT (20U) #define CAAM_REIR4RTIC_AXPROT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_AXPROT_SHIFT)) & CAAM_REIR4RTIC_AXPROT_MASK) + #define CAAM_REIR4RTIC_RWB_MASK (0x800000U) #define CAAM_REIR4RTIC_RWB_SHIFT (23U) #define CAAM_REIR4RTIC_RWB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_RWB_SHIFT)) & CAAM_REIR4RTIC_RWB_MASK) + #define CAAM_REIR4RTIC_ERR_MASK (0x30000000U) #define CAAM_REIR4RTIC_ERR_SHIFT (28U) #define CAAM_REIR4RTIC_ERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_ERR_SHIFT)) & CAAM_REIR4RTIC_ERR_MASK) + #define CAAM_REIR4RTIC_MIX_MASK (0xC0000000U) #define CAAM_REIR4RTIC_MIX_SHIFT (30U) #define CAAM_REIR4RTIC_MIX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_MIX_SHIFT)) & CAAM_REIR4RTIC_MIX_MASK) @@ -14367,12 +16263,15 @@ typedef struct { /*! @name REIR5RTIC - Recoverable Error Interrupt Record 5 for RTIC */ /*! @{ */ + #define CAAM_REIR5RTIC_BID_MASK (0xF0000U) #define CAAM_REIR5RTIC_BID_SHIFT (16U) #define CAAM_REIR5RTIC_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5RTIC_BID_SHIFT)) & CAAM_REIR5RTIC_BID_MASK) + #define CAAM_REIR5RTIC_SAFE_MASK (0x1000000U) #define CAAM_REIR5RTIC_SAFE_SHIFT (24U) #define CAAM_REIR5RTIC_SAFE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5RTIC_SAFE_SHIFT)) & CAAM_REIR5RTIC_SAFE_MASK) + #define CAAM_REIR5RTIC_SMA_MASK (0x2000000U) #define CAAM_REIR5RTIC_SMA_SHIFT (25U) #define CAAM_REIR5RTIC_SMA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5RTIC_SMA_SHIFT)) & CAAM_REIR5RTIC_SMA_MASK) @@ -14380,6 +16279,7 @@ typedef struct { /*! @name CC1MR - CCB 0 Class 1 Mode Register Format for Non-Public Key Algorithms */ /*! @{ */ + #define CAAM_CC1MR_ENC_MASK (0x1U) #define CAAM_CC1MR_ENC_SHIFT (0U) /*! ENC @@ -14387,9 +16287,11 @@ typedef struct { * 0b1..Encrypt. */ #define CAAM_CC1MR_ENC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_ENC_SHIFT)) & CAAM_CC1MR_ENC_MASK) + #define CAAM_CC1MR_ICV_TEST_MASK (0x2U) #define CAAM_CC1MR_ICV_TEST_SHIFT (1U) #define CAAM_CC1MR_ICV_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_ICV_TEST_SHIFT)) & CAAM_CC1MR_ICV_TEST_MASK) + #define CAAM_CC1MR_AS_MASK (0xCU) #define CAAM_CC1MR_AS_SHIFT (2U) /*! AS @@ -14399,9 +16301,11 @@ typedef struct { * 0b11..Initialize/Finalize */ #define CAAM_CC1MR_AS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_AS_SHIFT)) & CAAM_CC1MR_AS_MASK) + #define CAAM_CC1MR_AAI_MASK (0x1FF0U) #define CAAM_CC1MR_AAI_SHIFT (4U) #define CAAM_CC1MR_AAI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_AAI_SHIFT)) & CAAM_CC1MR_AAI_MASK) + #define CAAM_CC1MR_ALG_MASK (0xFF0000U) #define CAAM_CC1MR_ALG_SHIFT (16U) /*! ALG @@ -14418,9 +16322,11 @@ typedef struct { /*! @name CC1MR_PK - CCB 0 Class 1 Mode Register Format for Public Key Algorithms */ /*! @{ */ + #define CAAM_CC1MR_PK_PKHA_MODE_LS_MASK (0xFFFU) #define CAAM_CC1MR_PK_PKHA_MODE_LS_SHIFT (0U) #define CAAM_CC1MR_PK_PKHA_MODE_LS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_PK_PKHA_MODE_LS_SHIFT)) & CAAM_CC1MR_PK_PKHA_MODE_LS_MASK) + #define CAAM_CC1MR_PK_PKHA_MODE_MS_MASK (0xF0000U) #define CAAM_CC1MR_PK_PKHA_MODE_MS_SHIFT (16U) #define CAAM_CC1MR_PK_PKHA_MODE_MS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_PK_PKHA_MODE_MS_SHIFT)) & CAAM_CC1MR_PK_PKHA_MODE_MS_MASK) @@ -14431,15 +16337,19 @@ typedef struct { /*! @name CC1MR_RNG - CCB 0 Class 1 Mode Register Format for RNG4 */ /*! @{ */ + #define CAAM_CC1MR_RNG_TST_MASK (0x1U) #define CAAM_CC1MR_RNG_TST_SHIFT (0U) #define CAAM_CC1MR_RNG_TST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_TST_SHIFT)) & CAAM_CC1MR_RNG_TST_MASK) + #define CAAM_CC1MR_RNG_PR_MASK (0x2U) #define CAAM_CC1MR_RNG_PR_SHIFT (1U) #define CAAM_CC1MR_RNG_PR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_PR_SHIFT)) & CAAM_CC1MR_RNG_PR_MASK) + #define CAAM_CC1MR_RNG_AS_MASK (0xCU) #define CAAM_CC1MR_RNG_AS_SHIFT (2U) #define CAAM_CC1MR_RNG_AS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_AS_SHIFT)) & CAAM_CC1MR_RNG_AS_MASK) + #define CAAM_CC1MR_RNG_SH_MASK (0x30U) #define CAAM_CC1MR_RNG_SH_SHIFT (4U) /*! SH @@ -14449,6 +16359,7 @@ typedef struct { * 0b11..Reserved */ #define CAAM_CC1MR_RNG_SH(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_SH_SHIFT)) & CAAM_CC1MR_RNG_SH_MASK) + #define CAAM_CC1MR_RNG_NZB_MASK (0x100U) #define CAAM_CC1MR_RNG_NZB_SHIFT (8U) /*! NZB @@ -14456,6 +16367,7 @@ typedef struct { * 0b1..Generate random data without any all-zero bytes. */ #define CAAM_CC1MR_RNG_NZB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_NZB_SHIFT)) & CAAM_CC1MR_RNG_NZB_MASK) + #define CAAM_CC1MR_RNG_OBP_MASK (0x200U) #define CAAM_CC1MR_RNG_OBP_SHIFT (9U) /*! OBP @@ -14463,6 +16375,7 @@ typedef struct { * 0b1..Generate random data with odd byte parity. */ #define CAAM_CC1MR_RNG_OBP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_OBP_SHIFT)) & CAAM_CC1MR_RNG_OBP_MASK) + #define CAAM_CC1MR_RNG_PS_MASK (0x400U) #define CAAM_CC1MR_RNG_PS_SHIFT (10U) /*! PS @@ -14470,6 +16383,7 @@ typedef struct { * 0b1..A personalization string is included. */ #define CAAM_CC1MR_RNG_PS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_PS_SHIFT)) & CAAM_CC1MR_RNG_PS_MASK) + #define CAAM_CC1MR_RNG_AI_MASK (0x800U) #define CAAM_CC1MR_RNG_AI_SHIFT (11U) /*! AI @@ -14477,6 +16391,7 @@ typedef struct { * 0b1..Additional entropy input has been provided. */ #define CAAM_CC1MR_RNG_AI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_AI_SHIFT)) & CAAM_CC1MR_RNG_AI_MASK) + #define CAAM_CC1MR_RNG_SK_MASK (0x1000U) #define CAAM_CC1MR_RNG_SK_SHIFT (12U) /*! SK @@ -14484,6 +16399,7 @@ typedef struct { * 0b1..The RNG data will go to the JDKEKR, TDKEKR and DSKR. */ #define CAAM_CC1MR_RNG_SK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_SK_SHIFT)) & CAAM_CC1MR_RNG_SK_MASK) + #define CAAM_CC1MR_RNG_ALG_MASK (0xFF0000U) #define CAAM_CC1MR_RNG_ALG_SHIFT (16U) /*! ALG @@ -14497,6 +16413,7 @@ typedef struct { /*! @name CC1KSR - CCB 0 Class 1 Key Size Register */ /*! @{ */ + #define CAAM_CC1KSR_C1KS_MASK (0x7FU) #define CAAM_CC1KSR_C1KS_SHIFT (0U) #define CAAM_CC1KSR_C1KS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1KSR_C1KS_SHIFT)) & CAAM_CC1KSR_C1KS_MASK) @@ -14507,9 +16424,11 @@ typedef struct { /*! @name CC1DSR - CCB 0 Class 1 Data Size Register */ /*! @{ */ + #define CAAM_CC1DSR_C1DS_MASK (0xFFFFFFFFU) #define CAAM_CC1DSR_C1DS_SHIFT (0U) #define CAAM_CC1DSR_C1DS(x) (((uint64_t)(((uint64_t)(x)) << CAAM_CC1DSR_C1DS_SHIFT)) & CAAM_CC1DSR_C1DS_MASK) + #define CAAM_CC1DSR_C1CY_MASK (0x100000000U) #define CAAM_CC1DSR_C1CY_SHIFT (32U) /*! C1CY @@ -14517,6 +16436,7 @@ typedef struct { * 0b1..There was a carry out of the C1 Data Size Reg. */ #define CAAM_CC1DSR_C1CY(x) (((uint64_t)(((uint64_t)(x)) << CAAM_CC1DSR_C1CY_SHIFT)) & CAAM_CC1DSR_C1CY_MASK) + #define CAAM_CC1DSR_NUMBITS_MASK (0xE000000000000000U) #define CAAM_CC1DSR_NUMBITS_SHIFT (61U) #define CAAM_CC1DSR_NUMBITS(x) (((uint64_t)(((uint64_t)(x)) << CAAM_CC1DSR_NUMBITS_SHIFT)) & CAAM_CC1DSR_NUMBITS_MASK) @@ -14527,6 +16447,7 @@ typedef struct { /*! @name CC1ICVSR - CCB 0 Class 1 ICV Size Register */ /*! @{ */ + #define CAAM_CC1ICVSR_C1ICVS_MASK (0x1FU) #define CAAM_CC1ICVSR_C1ICVS_SHIFT (0U) #define CAAM_CC1ICVSR_C1ICVS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1ICVSR_C1ICVS_SHIFT)) & CAAM_CC1ICVSR_C1ICVS_MASK) @@ -14537,6 +16458,7 @@ typedef struct { /*! @name CCCTRL - CCB 0 CHA Control Register */ /*! @{ */ + #define CAAM_CCCTRL_CCB_MASK (0x1U) #define CAAM_CCCTRL_CCB_SHIFT (0U) /*! CCB @@ -14544,6 +16466,7 @@ typedef struct { * 0b1..Reset CCB */ #define CAAM_CCCTRL_CCB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_CCB_SHIFT)) & CAAM_CCCTRL_CCB_MASK) + #define CAAM_CCCTRL_AES_MASK (0x2U) #define CAAM_CCCTRL_AES_SHIFT (1U) /*! AES @@ -14551,6 +16474,7 @@ typedef struct { * 0b1..Reset AES Accelerator */ #define CAAM_CCCTRL_AES(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_AES_SHIFT)) & CAAM_CCCTRL_AES_MASK) + #define CAAM_CCCTRL_DES_MASK (0x4U) #define CAAM_CCCTRL_DES_SHIFT (2U) /*! DES @@ -14558,6 +16482,7 @@ typedef struct { * 0b1..Reset DES Accelerator */ #define CAAM_CCCTRL_DES(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_DES_SHIFT)) & CAAM_CCCTRL_DES_MASK) + #define CAAM_CCCTRL_PK_MASK (0x40U) #define CAAM_CCCTRL_PK_SHIFT (6U) /*! PK @@ -14565,6 +16490,7 @@ typedef struct { * 0b1..Reset Public Key Hardware Accelerator */ #define CAAM_CCCTRL_PK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_PK_SHIFT)) & CAAM_CCCTRL_PK_MASK) + #define CAAM_CCCTRL_MD_MASK (0x80U) #define CAAM_CCCTRL_MD_SHIFT (7U) /*! MD @@ -14572,6 +16498,7 @@ typedef struct { * 0b1..Reset Message Digest Hardware Accelerator */ #define CAAM_CCCTRL_MD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_MD_SHIFT)) & CAAM_CCCTRL_MD_MASK) + #define CAAM_CCCTRL_CRC_MASK (0x100U) #define CAAM_CCCTRL_CRC_SHIFT (8U) /*! CRC @@ -14579,6 +16506,7 @@ typedef struct { * 0b1..Reset CRC Accelerator */ #define CAAM_CCCTRL_CRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_CRC_SHIFT)) & CAAM_CCCTRL_CRC_MASK) + #define CAAM_CCCTRL_RNG_MASK (0x200U) #define CAAM_CCCTRL_RNG_SHIFT (9U) /*! RNG @@ -14586,6 +16514,7 @@ typedef struct { * 0b1..Reset Random Number Generator Block. */ #define CAAM_CCCTRL_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_RNG_SHIFT)) & CAAM_CCCTRL_RNG_MASK) + #define CAAM_CCCTRL_UA0_MASK (0x10000U) #define CAAM_CCCTRL_UA0_SHIFT (16U) /*! UA0 @@ -14593,6 +16522,7 @@ typedef struct { * 0b1..Unload the PKHA A0 Memory into OFIFO. */ #define CAAM_CCCTRL_UA0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA0_SHIFT)) & CAAM_CCCTRL_UA0_MASK) + #define CAAM_CCCTRL_UA1_MASK (0x20000U) #define CAAM_CCCTRL_UA1_SHIFT (17U) /*! UA1 @@ -14600,6 +16530,7 @@ typedef struct { * 0b1..Unload the PKHA A1 Memory into OFIFO. */ #define CAAM_CCCTRL_UA1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA1_SHIFT)) & CAAM_CCCTRL_UA1_MASK) + #define CAAM_CCCTRL_UA2_MASK (0x40000U) #define CAAM_CCCTRL_UA2_SHIFT (18U) /*! UA2 @@ -14607,6 +16538,7 @@ typedef struct { * 0b1..Unload the PKHA A2 Memory into OFIFO. */ #define CAAM_CCCTRL_UA2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA2_SHIFT)) & CAAM_CCCTRL_UA2_MASK) + #define CAAM_CCCTRL_UA3_MASK (0x80000U) #define CAAM_CCCTRL_UA3_SHIFT (19U) /*! UA3 @@ -14614,6 +16546,7 @@ typedef struct { * 0b1..Unload the PKHA A3 Memory into OFIFO. */ #define CAAM_CCCTRL_UA3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA3_SHIFT)) & CAAM_CCCTRL_UA3_MASK) + #define CAAM_CCCTRL_UB0_MASK (0x100000U) #define CAAM_CCCTRL_UB0_SHIFT (20U) /*! UB0 @@ -14621,6 +16554,7 @@ typedef struct { * 0b1..Unload the PKHA B0 Memory into OFIFO. */ #define CAAM_CCCTRL_UB0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB0_SHIFT)) & CAAM_CCCTRL_UB0_MASK) + #define CAAM_CCCTRL_UB1_MASK (0x200000U) #define CAAM_CCCTRL_UB1_SHIFT (21U) /*! UB1 @@ -14628,6 +16562,7 @@ typedef struct { * 0b1..Unload the PKHA B1 Memory into OFIFO. */ #define CAAM_CCCTRL_UB1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB1_SHIFT)) & CAAM_CCCTRL_UB1_MASK) + #define CAAM_CCCTRL_UB2_MASK (0x400000U) #define CAAM_CCCTRL_UB2_SHIFT (22U) /*! UB2 @@ -14635,6 +16570,7 @@ typedef struct { * 0b1..Unload the PKHA B2 Memory into OFIFO. */ #define CAAM_CCCTRL_UB2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB2_SHIFT)) & CAAM_CCCTRL_UB2_MASK) + #define CAAM_CCCTRL_UB3_MASK (0x800000U) #define CAAM_CCCTRL_UB3_SHIFT (23U) /*! UB3 @@ -14642,6 +16578,7 @@ typedef struct { * 0b1..Unload the PKHA B3 Memory into OFIFO. */ #define CAAM_CCCTRL_UB3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB3_SHIFT)) & CAAM_CCCTRL_UB3_MASK) + #define CAAM_CCCTRL_UN_MASK (0x1000000U) #define CAAM_CCCTRL_UN_SHIFT (24U) /*! UN @@ -14649,6 +16586,7 @@ typedef struct { * 0b1..Unload the PKHA N Memory into OFIFO. */ #define CAAM_CCCTRL_UN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UN_SHIFT)) & CAAM_CCCTRL_UN_MASK) + #define CAAM_CCCTRL_UA_MASK (0x4000000U) #define CAAM_CCCTRL_UA_SHIFT (26U) /*! UA @@ -14656,6 +16594,7 @@ typedef struct { * 0b1..Unload the PKHA A Memory into OFIFO. */ #define CAAM_CCCTRL_UA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA_SHIFT)) & CAAM_CCCTRL_UA_MASK) + #define CAAM_CCCTRL_UB_MASK (0x8000000U) #define CAAM_CCCTRL_UB_SHIFT (27U) /*! UB @@ -14670,24 +16609,31 @@ typedef struct { /*! @name CICTL - CCB 0 Interrupt Control Register */ /*! @{ */ + #define CAAM_CICTL_ADI_MASK (0x2U) #define CAAM_CICTL_ADI_SHIFT (1U) #define CAAM_CICTL_ADI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_ADI_SHIFT)) & CAAM_CICTL_ADI_MASK) + #define CAAM_CICTL_DDI_MASK (0x4U) #define CAAM_CICTL_DDI_SHIFT (2U) #define CAAM_CICTL_DDI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_DDI_SHIFT)) & CAAM_CICTL_DDI_MASK) + #define CAAM_CICTL_PDI_MASK (0x40U) #define CAAM_CICTL_PDI_SHIFT (6U) #define CAAM_CICTL_PDI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_PDI_SHIFT)) & CAAM_CICTL_PDI_MASK) + #define CAAM_CICTL_MDI_MASK (0x80U) #define CAAM_CICTL_MDI_SHIFT (7U) #define CAAM_CICTL_MDI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_MDI_SHIFT)) & CAAM_CICTL_MDI_MASK) + #define CAAM_CICTL_CDI_MASK (0x100U) #define CAAM_CICTL_CDI_SHIFT (8U) #define CAAM_CICTL_CDI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_CDI_SHIFT)) & CAAM_CICTL_CDI_MASK) + #define CAAM_CICTL_RNDI_MASK (0x200U) #define CAAM_CICTL_RNDI_SHIFT (9U) #define CAAM_CICTL_RNDI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_RNDI_SHIFT)) & CAAM_CICTL_RNDI_MASK) + #define CAAM_CICTL_AEI_MASK (0x20000U) #define CAAM_CICTL_AEI_SHIFT (17U) /*! AEI @@ -14695,6 +16641,7 @@ typedef struct { * 0b1..AESA error detected */ #define CAAM_CICTL_AEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_AEI_SHIFT)) & CAAM_CICTL_AEI_MASK) + #define CAAM_CICTL_DEI_MASK (0x40000U) #define CAAM_CICTL_DEI_SHIFT (18U) /*! DEI @@ -14702,6 +16649,7 @@ typedef struct { * 0b1..DESA error detected */ #define CAAM_CICTL_DEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_DEI_SHIFT)) & CAAM_CICTL_DEI_MASK) + #define CAAM_CICTL_PEI_MASK (0x400000U) #define CAAM_CICTL_PEI_SHIFT (22U) /*! PEI @@ -14709,6 +16657,7 @@ typedef struct { * 0b1..PKHA error detected */ #define CAAM_CICTL_PEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_PEI_SHIFT)) & CAAM_CICTL_PEI_MASK) + #define CAAM_CICTL_MEI_MASK (0x800000U) #define CAAM_CICTL_MEI_SHIFT (23U) /*! MEI @@ -14716,6 +16665,7 @@ typedef struct { * 0b1..MDHA error detected */ #define CAAM_CICTL_MEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_MEI_SHIFT)) & CAAM_CICTL_MEI_MASK) + #define CAAM_CICTL_CEI_MASK (0x1000000U) #define CAAM_CICTL_CEI_SHIFT (24U) /*! CEI @@ -14723,6 +16673,7 @@ typedef struct { * 0b1..CRCA error detected */ #define CAAM_CICTL_CEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_CEI_SHIFT)) & CAAM_CICTL_CEI_MASK) + #define CAAM_CICTL_RNEI_MASK (0x2000000U) #define CAAM_CICTL_RNEI_SHIFT (25U) /*! RNEI @@ -14737,6 +16688,7 @@ typedef struct { /*! @name CCWR - CCB 0 Clear Written Register */ /*! @{ */ + #define CAAM_CCWR_C1M_MASK (0x1U) #define CAAM_CCWR_C1M_SHIFT (0U) /*! C1M @@ -14744,6 +16696,7 @@ typedef struct { * 0b1..Clear the Class 1 Mode Register. */ #define CAAM_CCWR_C1M(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1M_SHIFT)) & CAAM_CCWR_C1M_MASK) + #define CAAM_CCWR_C1DS_MASK (0x4U) #define CAAM_CCWR_C1DS_SHIFT (2U) /*! C1DS @@ -14751,6 +16704,7 @@ typedef struct { * 0b1..Clear the Class 1 Data Size Register. */ #define CAAM_CCWR_C1DS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1DS_SHIFT)) & CAAM_CCWR_C1DS_MASK) + #define CAAM_CCWR_C1ICV_MASK (0x8U) #define CAAM_CCWR_C1ICV_SHIFT (3U) /*! C1ICV @@ -14758,6 +16712,7 @@ typedef struct { * 0b1..Clear the Class 1 ICV Size Register. */ #define CAAM_CCWR_C1ICV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1ICV_SHIFT)) & CAAM_CCWR_C1ICV_MASK) + #define CAAM_CCWR_C1C_MASK (0x20U) #define CAAM_CCWR_C1C_SHIFT (5U) /*! C1C @@ -14765,6 +16720,7 @@ typedef struct { * 0b1..Clear the Class 1 Context Register. */ #define CAAM_CCWR_C1C(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1C_SHIFT)) & CAAM_CCWR_C1C_MASK) + #define CAAM_CCWR_C1K_MASK (0x40U) #define CAAM_CCWR_C1K_SHIFT (6U) /*! C1K @@ -14772,6 +16728,7 @@ typedef struct { * 0b1..Clear the Class 1 Key Register. */ #define CAAM_CCWR_C1K(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1K_SHIFT)) & CAAM_CCWR_C1K_MASK) + #define CAAM_CCWR_CPKA_MASK (0x1000U) #define CAAM_CCWR_CPKA_SHIFT (12U) /*! CPKA @@ -14779,6 +16736,7 @@ typedef struct { * 0b1..Clear the PKHA A Size Register. */ #define CAAM_CCWR_CPKA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CPKA_SHIFT)) & CAAM_CCWR_CPKA_MASK) + #define CAAM_CCWR_CPKB_MASK (0x2000U) #define CAAM_CCWR_CPKB_SHIFT (13U) /*! CPKB @@ -14786,6 +16744,7 @@ typedef struct { * 0b1..Clear the PKHA B Size Register. */ #define CAAM_CCWR_CPKB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CPKB_SHIFT)) & CAAM_CCWR_CPKB_MASK) + #define CAAM_CCWR_CPKN_MASK (0x4000U) #define CAAM_CCWR_CPKN_SHIFT (14U) /*! CPKN @@ -14793,6 +16752,7 @@ typedef struct { * 0b1..Clear the PKHA N Size Register. */ #define CAAM_CCWR_CPKN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CPKN_SHIFT)) & CAAM_CCWR_CPKN_MASK) + #define CAAM_CCWR_CPKE_MASK (0x8000U) #define CAAM_CCWR_CPKE_SHIFT (15U) /*! CPKE @@ -14800,6 +16760,7 @@ typedef struct { * 0b1..Clear the PKHA E Size Register. */ #define CAAM_CCWR_CPKE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CPKE_SHIFT)) & CAAM_CCWR_CPKE_MASK) + #define CAAM_CCWR_C2M_MASK (0x10000U) #define CAAM_CCWR_C2M_SHIFT (16U) /*! C2M @@ -14807,6 +16768,7 @@ typedef struct { * 0b1..Clear the Class 2 Mode Register. */ #define CAAM_CCWR_C2M(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2M_SHIFT)) & CAAM_CCWR_C2M_MASK) + #define CAAM_CCWR_C2DS_MASK (0x40000U) #define CAAM_CCWR_C2DS_SHIFT (18U) /*! C2DS @@ -14814,6 +16776,7 @@ typedef struct { * 0b1..Clear the Class 2 Data Size Register. */ #define CAAM_CCWR_C2DS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2DS_SHIFT)) & CAAM_CCWR_C2DS_MASK) + #define CAAM_CCWR_C2C_MASK (0x200000U) #define CAAM_CCWR_C2C_SHIFT (21U) /*! C2C @@ -14821,6 +16784,7 @@ typedef struct { * 0b1..Clear the Class 2 Context Register. */ #define CAAM_CCWR_C2C(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2C_SHIFT)) & CAAM_CCWR_C2C_MASK) + #define CAAM_CCWR_C2K_MASK (0x400000U) #define CAAM_CCWR_C2K_SHIFT (22U) /*! C2K @@ -14828,6 +16792,7 @@ typedef struct { * 0b1..Clear the Class 2 Key Register. */ #define CAAM_CCWR_C2K(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2K_SHIFT)) & CAAM_CCWR_C2K_MASK) + #define CAAM_CCWR_CDS_MASK (0x2000000U) #define CAAM_CCWR_CDS_SHIFT (25U) /*! CDS @@ -14835,6 +16800,7 @@ typedef struct { * 0b1..Clear the shared descriptor signal. */ #define CAAM_CCWR_CDS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CDS_SHIFT)) & CAAM_CCWR_CDS_MASK) + #define CAAM_CCWR_C2D_MASK (0x4000000U) #define CAAM_CCWR_C2D_SHIFT (26U) /*! C2D @@ -14842,6 +16808,7 @@ typedef struct { * 0b1..Clear the Class 2 done interrrupt. */ #define CAAM_CCWR_C2D(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2D_SHIFT)) & CAAM_CCWR_C2D_MASK) + #define CAAM_CCWR_C1D_MASK (0x8000000U) #define CAAM_CCWR_C1D_SHIFT (27U) /*! C1D @@ -14849,6 +16816,7 @@ typedef struct { * 0b1..Clear the Class 1 done interrrupt. */ #define CAAM_CCWR_C1D(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1D_SHIFT)) & CAAM_CCWR_C1D_MASK) + #define CAAM_CCWR_C2RST_MASK (0x10000000U) #define CAAM_CCWR_C2RST_SHIFT (28U) /*! C2RST @@ -14856,6 +16824,7 @@ typedef struct { * 0b1..Reset the Class 2 CHA. */ #define CAAM_CCWR_C2RST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2RST_SHIFT)) & CAAM_CCWR_C2RST_MASK) + #define CAAM_CCWR_C1RST_MASK (0x20000000U) #define CAAM_CCWR_C1RST_SHIFT (29U) /*! C1RST @@ -14863,6 +16832,7 @@ typedef struct { * 0b1..Reset the Class 1 CHA. */ #define CAAM_CCWR_C1RST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1RST_SHIFT)) & CAAM_CCWR_C1RST_MASK) + #define CAAM_CCWR_COF_MASK (0x40000000U) #define CAAM_CCWR_COF_SHIFT (30U) /*! COF @@ -14870,6 +16840,7 @@ typedef struct { * 0b1..Clear the OFIFO. */ #define CAAM_CCWR_COF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_COF_SHIFT)) & CAAM_CCWR_COF_MASK) + #define CAAM_CCWR_CIF_MASK (0x80000000U) #define CAAM_CCWR_CIF_SHIFT (31U) /*! CIF @@ -14884,6 +16855,7 @@ typedef struct { /*! @name CCSTA_MS - CCB 0 Status and Error Register, most-significant half */ /*! @{ */ + #define CAAM_CCSTA_MS_ERRID1_MASK (0xFU) #define CAAM_CCSTA_MS_ERRID1_SHIFT (0U) /*! ERRID1 @@ -14905,6 +16877,7 @@ typedef struct { * 0b1111..Invalid CHA Selected */ #define CAAM_CCSTA_MS_ERRID1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_MS_ERRID1_SHIFT)) & CAAM_CCSTA_MS_ERRID1_MASK) + #define CAAM_CCSTA_MS_CL1_MASK (0xF000U) #define CAAM_CCSTA_MS_CL1_SHIFT (12U) /*! CL1 @@ -14914,6 +16887,7 @@ typedef struct { * 0b1000..Public Key */ #define CAAM_CCSTA_MS_CL1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_MS_CL1_SHIFT)) & CAAM_CCSTA_MS_CL1_MASK) + #define CAAM_CCSTA_MS_ERRID2_MASK (0xF0000U) #define CAAM_CCSTA_MS_ERRID2_SHIFT (16U) /*! ERRID2 @@ -14927,6 +16901,7 @@ typedef struct { * 0b1111..Invalid CHA Selected */ #define CAAM_CCSTA_MS_ERRID2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_MS_ERRID2_SHIFT)) & CAAM_CCSTA_MS_ERRID2_MASK) + #define CAAM_CCSTA_MS_CL2_MASK (0xF0000000U) #define CAAM_CCSTA_MS_CL2_SHIFT (28U) /*! CL2 @@ -14941,6 +16916,7 @@ typedef struct { /*! @name CCSTA_LS - CCB 0 Status and Error Register, least-significant half */ /*! @{ */ + #define CAAM_CCSTA_LS_AB_MASK (0x2U) #define CAAM_CCSTA_LS_AB_SHIFT (1U) /*! AB @@ -14948,6 +16924,7 @@ typedef struct { * 0b1..AESA Busy */ #define CAAM_CCSTA_LS_AB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_AB_SHIFT)) & CAAM_CCSTA_LS_AB_MASK) + #define CAAM_CCSTA_LS_DB_MASK (0x4U) #define CAAM_CCSTA_LS_DB_SHIFT (2U) /*! DB @@ -14955,6 +16932,7 @@ typedef struct { * 0b1..DESA Busy */ #define CAAM_CCSTA_LS_DB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_DB_SHIFT)) & CAAM_CCSTA_LS_DB_MASK) + #define CAAM_CCSTA_LS_PB_MASK (0x40U) #define CAAM_CCSTA_LS_PB_SHIFT (6U) /*! PB @@ -14962,6 +16940,7 @@ typedef struct { * 0b1..PKHA Busy */ #define CAAM_CCSTA_LS_PB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PB_SHIFT)) & CAAM_CCSTA_LS_PB_MASK) + #define CAAM_CCSTA_LS_MB_MASK (0x80U) #define CAAM_CCSTA_LS_MB_SHIFT (7U) /*! MB @@ -14969,6 +16948,7 @@ typedef struct { * 0b1..MDHA Busy */ #define CAAM_CCSTA_LS_MB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_MB_SHIFT)) & CAAM_CCSTA_LS_MB_MASK) + #define CAAM_CCSTA_LS_CB_MASK (0x100U) #define CAAM_CCSTA_LS_CB_SHIFT (8U) /*! CB @@ -14976,6 +16956,7 @@ typedef struct { * 0b1..CRCA Busy */ #define CAAM_CCSTA_LS_CB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_CB_SHIFT)) & CAAM_CCSTA_LS_CB_MASK) + #define CAAM_CCSTA_LS_RNB_MASK (0x200U) #define CAAM_CCSTA_LS_RNB_SHIFT (9U) /*! RNB @@ -14983,6 +16964,7 @@ typedef struct { * 0b1..RNG Busy */ #define CAAM_CCSTA_LS_RNB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_RNB_SHIFT)) & CAAM_CCSTA_LS_RNB_MASK) + #define CAAM_CCSTA_LS_PDI_MASK (0x10000U) #define CAAM_CCSTA_LS_PDI_SHIFT (16U) /*! PDI @@ -14990,6 +16972,7 @@ typedef struct { * 0b1..Done Interrupt */ #define CAAM_CCSTA_LS_PDI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PDI_SHIFT)) & CAAM_CCSTA_LS_PDI_MASK) + #define CAAM_CCSTA_LS_SDI_MASK (0x20000U) #define CAAM_CCSTA_LS_SDI_SHIFT (17U) /*! SDI @@ -14997,6 +16980,7 @@ typedef struct { * 0b1..Done Interrupt */ #define CAAM_CCSTA_LS_SDI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_SDI_SHIFT)) & CAAM_CCSTA_LS_SDI_MASK) + #define CAAM_CCSTA_LS_PEI_MASK (0x100000U) #define CAAM_CCSTA_LS_PEI_SHIFT (20U) /*! PEI @@ -15004,6 +16988,7 @@ typedef struct { * 0b1..Error Interrupt */ #define CAAM_CCSTA_LS_PEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PEI_SHIFT)) & CAAM_CCSTA_LS_PEI_MASK) + #define CAAM_CCSTA_LS_SEI_MASK (0x200000U) #define CAAM_CCSTA_LS_SEI_SHIFT (21U) /*! SEI @@ -15011,6 +16996,7 @@ typedef struct { * 0b1..Error Interrupt */ #define CAAM_CCSTA_LS_SEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_SEI_SHIFT)) & CAAM_CCSTA_LS_SEI_MASK) + #define CAAM_CCSTA_LS_PRM_MASK (0x10000000U) #define CAAM_CCSTA_LS_PRM_SHIFT (28U) /*! PRM @@ -15018,6 +17004,7 @@ typedef struct { * 0b1..The given number is probably prime. */ #define CAAM_CCSTA_LS_PRM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PRM_SHIFT)) & CAAM_CCSTA_LS_PRM_MASK) + #define CAAM_CCSTA_LS_GCD_MASK (0x20000000U) #define CAAM_CCSTA_LS_GCD_SHIFT (29U) /*! GCD @@ -15025,6 +17012,7 @@ typedef struct { * 0b1..The greatest common divisor of two numbers is one. */ #define CAAM_CCSTA_LS_GCD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_GCD_SHIFT)) & CAAM_CCSTA_LS_GCD_MASK) + #define CAAM_CCSTA_LS_PIZ_MASK (0x40000000U) #define CAAM_CCSTA_LS_PIZ_SHIFT (30U) /*! PIZ @@ -15039,6 +17027,7 @@ typedef struct { /*! @name CC1AADSZR - CCB 0 Class 1 AAD Size Register */ /*! @{ */ + #define CAAM_CC1AADSZR_AASZ_MASK (0xFU) #define CAAM_CC1AADSZR_AASZ_SHIFT (0U) #define CAAM_CC1AADSZR_AASZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1AADSZR_AASZ_SHIFT)) & CAAM_CC1AADSZR_AASZ_MASK) @@ -15049,6 +17038,7 @@ typedef struct { /*! @name CC1IVSZR - CCB 0 Class 1 IV Size Register */ /*! @{ */ + #define CAAM_CC1IVSZR_IVSZ_MASK (0xFU) #define CAAM_CC1IVSZR_IVSZ_SHIFT (0U) #define CAAM_CC1IVSZR_IVSZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1IVSZR_IVSZ_SHIFT)) & CAAM_CC1IVSZR_IVSZ_MASK) @@ -15059,6 +17049,7 @@ typedef struct { /*! @name CPKASZR - PKHA A Size Register */ /*! @{ */ + #define CAAM_CPKASZR_PKASZ_MASK (0x3FFU) #define CAAM_CPKASZR_PKASZ_SHIFT (0U) #define CAAM_CPKASZR_PKASZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CPKASZR_PKASZ_SHIFT)) & CAAM_CPKASZR_PKASZ_MASK) @@ -15069,6 +17060,7 @@ typedef struct { /*! @name CPKBSZR - PKHA B Size Register */ /*! @{ */ + #define CAAM_CPKBSZR_PKBSZ_MASK (0x3FFU) #define CAAM_CPKBSZR_PKBSZ_SHIFT (0U) #define CAAM_CPKBSZR_PKBSZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CPKBSZR_PKBSZ_SHIFT)) & CAAM_CPKBSZR_PKBSZ_MASK) @@ -15079,6 +17071,7 @@ typedef struct { /*! @name CPKNSZR - PKHA N Size Register */ /*! @{ */ + #define CAAM_CPKNSZR_PKNSZ_MASK (0x3FFU) #define CAAM_CPKNSZR_PKNSZ_SHIFT (0U) #define CAAM_CPKNSZR_PKNSZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CPKNSZR_PKNSZ_SHIFT)) & CAAM_CPKNSZR_PKNSZ_MASK) @@ -15089,6 +17082,7 @@ typedef struct { /*! @name CPKESZR - PKHA E Size Register */ /*! @{ */ + #define CAAM_CPKESZR_PKESZ_MASK (0x3FFU) #define CAAM_CPKESZR_PKESZ_SHIFT (0U) #define CAAM_CPKESZR_PKESZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CPKESZR_PKESZ_SHIFT)) & CAAM_CPKESZR_PKESZ_MASK) @@ -15099,6 +17093,7 @@ typedef struct { /*! @name CC1CTXR - CCB 0 Class 1 Context Register Word 0..CCB 0 Class 1 Context Register Word 15 */ /*! @{ */ + #define CAAM_CC1CTXR_C1CTX_MASK (0xFFFFFFFFU) #define CAAM_CC1CTXR_C1CTX_SHIFT (0U) #define CAAM_CC1CTXR_C1CTX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1CTXR_C1CTX_SHIFT)) & CAAM_CC1CTXR_C1CTX_MASK) @@ -15112,6 +17107,7 @@ typedef struct { /*! @name CC1KR - CCB 0 Class 1 Key Registers Word 0..CCB 0 Class 1 Key Registers Word 7 */ /*! @{ */ + #define CAAM_CC1KR_C1KEY_MASK (0xFFFFFFFFU) #define CAAM_CC1KR_C1KEY_SHIFT (0U) #define CAAM_CC1KR_C1KEY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1KR_C1KEY_SHIFT)) & CAAM_CC1KR_C1KEY_MASK) @@ -15125,6 +17121,7 @@ typedef struct { /*! @name CC2MR - CCB 0 Class 2 Mode Register */ /*! @{ */ + #define CAAM_CC2MR_AP_MASK (0x1U) #define CAAM_CC2MR_AP_SHIFT (0U) /*! AP @@ -15132,6 +17129,7 @@ typedef struct { * 0b1..Protect */ #define CAAM_CC2MR_AP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_AP_SHIFT)) & CAAM_CC2MR_AP_MASK) + #define CAAM_CC2MR_ICV_MASK (0x2U) #define CAAM_CC2MR_ICV_SHIFT (1U) /*! ICV @@ -15139,6 +17137,7 @@ typedef struct { * 0b1..Compare the calculated ICV against a received ICV. */ #define CAAM_CC2MR_ICV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_ICV_SHIFT)) & CAAM_CC2MR_ICV_MASK) + #define CAAM_CC2MR_AS_MASK (0xCU) #define CAAM_CC2MR_AS_SHIFT (2U) /*! AS @@ -15148,9 +17147,11 @@ typedef struct { * 0b11..Initialize/Finalize. */ #define CAAM_CC2MR_AS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_AS_SHIFT)) & CAAM_CC2MR_AS_MASK) + #define CAAM_CC2MR_AAI_MASK (0x1FF0U) #define CAAM_CC2MR_AAI_SHIFT (4U) #define CAAM_CC2MR_AAI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_AAI_SHIFT)) & CAAM_CC2MR_AAI_MASK) + #define CAAM_CC2MR_ALG_MASK (0xFF0000U) #define CAAM_CC2MR_ALG_SHIFT (16U) /*! ALG @@ -15172,6 +17173,7 @@ typedef struct { /*! @name CC2KSR - CCB 0 Class 2 Key Size Register */ /*! @{ */ + #define CAAM_CC2KSR_C2KS_MASK (0xFFU) #define CAAM_CC2KSR_C2KS_SHIFT (0U) #define CAAM_CC2KSR_C2KS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2KSR_C2KS_SHIFT)) & CAAM_CC2KSR_C2KS_MASK) @@ -15182,9 +17184,11 @@ typedef struct { /*! @name CC2DSR - CCB 0 Class 2 Data Size Register */ /*! @{ */ + #define CAAM_CC2DSR_C2DS_MASK (0xFFFFFFFFU) #define CAAM_CC2DSR_C2DS_SHIFT (0U) #define CAAM_CC2DSR_C2DS(x) (((uint64_t)(((uint64_t)(x)) << CAAM_CC2DSR_C2DS_SHIFT)) & CAAM_CC2DSR_C2DS_MASK) + #define CAAM_CC2DSR_C2CY_MASK (0x100000000U) #define CAAM_CC2DSR_C2CY_SHIFT (32U) /*! C2CY @@ -15192,6 +17196,7 @@ typedef struct { * 0b1..A write to the Class 2 Data Size Register caused a carry. */ #define CAAM_CC2DSR_C2CY(x) (((uint64_t)(((uint64_t)(x)) << CAAM_CC2DSR_C2CY_SHIFT)) & CAAM_CC2DSR_C2CY_MASK) + #define CAAM_CC2DSR_NUMBITS_MASK (0xE000000000000000U) #define CAAM_CC2DSR_NUMBITS_SHIFT (61U) #define CAAM_CC2DSR_NUMBITS(x) (((uint64_t)(((uint64_t)(x)) << CAAM_CC2DSR_NUMBITS_SHIFT)) & CAAM_CC2DSR_NUMBITS_MASK) @@ -15202,6 +17207,7 @@ typedef struct { /*! @name CC2ICVSZR - CCB 0 Class 2 ICV Size Register */ /*! @{ */ + #define CAAM_CC2ICVSZR_ICVSZ_MASK (0xFU) #define CAAM_CC2ICVSZR_ICVSZ_SHIFT (0U) #define CAAM_CC2ICVSZR_ICVSZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2ICVSZR_ICVSZ_SHIFT)) & CAAM_CC2ICVSZR_ICVSZ_MASK) @@ -15212,6 +17218,7 @@ typedef struct { /*! @name CC2CTXR - CCB 0 Class 2 Context Register Word 0..CCB 0 Class 2 Context Register Word 17 */ /*! @{ */ + #define CAAM_CC2CTXR_C2CTXR_MASK (0xFFFFFFFFU) #define CAAM_CC2CTXR_C2CTXR_SHIFT (0U) #define CAAM_CC2CTXR_C2CTXR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2CTXR_C2CTXR_SHIFT)) & CAAM_CC2CTXR_C2CTXR_MASK) @@ -15225,6 +17232,7 @@ typedef struct { /*! @name CC2KEYR - CCB 0 Class 2 Key Register Word 0..CCB 0 Class 2 Key Register Word 31 */ /*! @{ */ + #define CAAM_CC2KEYR_C2KEY_MASK (0xFFFFFFFFU) #define CAAM_CC2KEYR_C2KEY_SHIFT (0U) #define CAAM_CC2KEYR_C2KEY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2KEYR_C2KEY_SHIFT)) & CAAM_CC2KEYR_C2KEY_MASK) @@ -15238,15 +17246,19 @@ typedef struct { /*! @name CFIFOSTA - CCB 0 FIFO Status Register */ /*! @{ */ + #define CAAM_CFIFOSTA_DECOOQHEAD_MASK (0xFFU) #define CAAM_CFIFOSTA_DECOOQHEAD_SHIFT (0U) #define CAAM_CFIFOSTA_DECOOQHEAD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CFIFOSTA_DECOOQHEAD_SHIFT)) & CAAM_CFIFOSTA_DECOOQHEAD_MASK) + #define CAAM_CFIFOSTA_DMAOQHEAD_MASK (0xFF00U) #define CAAM_CFIFOSTA_DMAOQHEAD_SHIFT (8U) #define CAAM_CFIFOSTA_DMAOQHEAD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CFIFOSTA_DMAOQHEAD_SHIFT)) & CAAM_CFIFOSTA_DMAOQHEAD_MASK) + #define CAAM_CFIFOSTA_C2IQHEAD_MASK (0xFF0000U) #define CAAM_CFIFOSTA_C2IQHEAD_SHIFT (16U) #define CAAM_CFIFOSTA_C2IQHEAD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CFIFOSTA_C2IQHEAD_SHIFT)) & CAAM_CFIFOSTA_C2IQHEAD_MASK) + #define CAAM_CFIFOSTA_C1IQHEAD_MASK (0xFF000000U) #define CAAM_CFIFOSTA_C1IQHEAD_SHIFT (24U) #define CAAM_CFIFOSTA_C1IQHEAD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CFIFOSTA_C1IQHEAD_SHIFT)) & CAAM_CFIFOSTA_C1IQHEAD_MASK) @@ -15257,12 +17269,15 @@ typedef struct { /*! @name CNFIFO - CCB 0 iNformation FIFO When STYPE != 10b */ /*! @{ */ + #define CAAM_CNFIFO_DL_MASK (0xFFFU) #define CAAM_CNFIFO_DL_SHIFT (0U) #define CAAM_CNFIFO_DL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_DL_SHIFT)) & CAAM_CNFIFO_DL_MASK) + #define CAAM_CNFIFO_AST_MASK (0x4000U) #define CAAM_CNFIFO_AST_SHIFT (14U) #define CAAM_CNFIFO_AST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_AST_SHIFT)) & CAAM_CNFIFO_AST_MASK) + #define CAAM_CNFIFO_OC_MASK (0x8000U) #define CAAM_CNFIFO_OC_SHIFT (15U) /*! OC @@ -15270,9 +17285,11 @@ typedef struct { * 0b1..Don't pop the final word from the Output Data FIFO. */ #define CAAM_CNFIFO_OC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_OC_SHIFT)) & CAAM_CNFIFO_OC_MASK) + #define CAAM_CNFIFO_PTYPE_MASK (0x70000U) #define CAAM_CNFIFO_PTYPE_SHIFT (16U) #define CAAM_CNFIFO_PTYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_PTYPE_SHIFT)) & CAAM_CNFIFO_PTYPE_MASK) + #define CAAM_CNFIFO_BND_MASK (0x80000U) #define CAAM_CNFIFO_BND_SHIFT (19U) /*! BND @@ -15280,12 +17297,15 @@ typedef struct { * 0b1..Pad to the next 16-byte boundary. */ #define CAAM_CNFIFO_BND(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_BND_SHIFT)) & CAAM_CNFIFO_BND_MASK) + #define CAAM_CNFIFO_DTYPE_MASK (0xF00000U) #define CAAM_CNFIFO_DTYPE_SHIFT (20U) #define CAAM_CNFIFO_DTYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_DTYPE_SHIFT)) & CAAM_CNFIFO_DTYPE_MASK) + #define CAAM_CNFIFO_STYPE_MASK (0x3000000U) #define CAAM_CNFIFO_STYPE_SHIFT (24U) #define CAAM_CNFIFO_STYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_STYPE_SHIFT)) & CAAM_CNFIFO_STYPE_MASK) + #define CAAM_CNFIFO_FC1_MASK (0x4000000U) #define CAAM_CNFIFO_FC1_SHIFT (26U) /*! FC1 @@ -15293,6 +17313,7 @@ typedef struct { * 0b1..Flush Class 1 data. */ #define CAAM_CNFIFO_FC1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_FC1_SHIFT)) & CAAM_CNFIFO_FC1_MASK) + #define CAAM_CNFIFO_FC2_MASK (0x8000000U) #define CAAM_CNFIFO_FC2_SHIFT (27U) /*! FC2 @@ -15300,6 +17321,7 @@ typedef struct { * 0b1..Flush Class 2 data. */ #define CAAM_CNFIFO_FC2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_FC2_SHIFT)) & CAAM_CNFIFO_FC2_MASK) + #define CAAM_CNFIFO_LC1_MASK (0x10000000U) #define CAAM_CNFIFO_LC1_SHIFT (28U) /*! LC1 @@ -15307,6 +17329,7 @@ typedef struct { * 0b1..This is the last Class 1 data. */ #define CAAM_CNFIFO_LC1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_LC1_SHIFT)) & CAAM_CNFIFO_LC1_MASK) + #define CAAM_CNFIFO_LC2_MASK (0x20000000U) #define CAAM_CNFIFO_LC2_SHIFT (29U) /*! LC2 @@ -15314,6 +17337,7 @@ typedef struct { * 0b1..This is the last Class 2 data. */ #define CAAM_CNFIFO_LC2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_LC2_SHIFT)) & CAAM_CNFIFO_LC2_MASK) + #define CAAM_CNFIFO_DEST_MASK (0xC0000000U) #define CAAM_CNFIFO_DEST_SHIFT (30U) /*! DEST @@ -15332,9 +17356,11 @@ typedef struct { /*! @name CNFIFO_2 - CCB 0 iNformation FIFO When STYPE == 10b */ /*! @{ */ + #define CAAM_CNFIFO_2_PL_MASK (0x7FU) #define CAAM_CNFIFO_2_PL_SHIFT (0U) #define CAAM_CNFIFO_2_PL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_PL_SHIFT)) & CAAM_CNFIFO_2_PL_MASK) + #define CAAM_CNFIFO_2_PS_MASK (0x400U) #define CAAM_CNFIFO_2_PS_SHIFT (10U) /*! PS @@ -15342,6 +17368,7 @@ typedef struct { * 0b1..C2 CHA snoops pad data from OFIFO. */ #define CAAM_CNFIFO_2_PS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_PS_SHIFT)) & CAAM_CNFIFO_2_PS_MASK) + #define CAAM_CNFIFO_2_BM_MASK (0x800U) #define CAAM_CNFIFO_2_BM_SHIFT (11U) /*! BM @@ -15349,6 +17376,7 @@ typedef struct { * 0b1..When padding, pad to power-of-2 boundary minus 1 byte. */ #define CAAM_CNFIFO_2_BM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_BM_SHIFT)) & CAAM_CNFIFO_2_BM_MASK) + #define CAAM_CNFIFO_2_PR_MASK (0x8000U) #define CAAM_CNFIFO_2_PR_SHIFT (15U) /*! PR @@ -15356,6 +17384,7 @@ typedef struct { * 0b1..Prediction resistance. */ #define CAAM_CNFIFO_2_PR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_PR_SHIFT)) & CAAM_CNFIFO_2_PR_MASK) + #define CAAM_CNFIFO_2_PTYPE_MASK (0x70000U) #define CAAM_CNFIFO_2_PTYPE_SHIFT (16U) /*! PTYPE @@ -15369,6 +17398,7 @@ typedef struct { * 0b111..Random with nonzero bytes, with the last byte containing the value N-1. */ #define CAAM_CNFIFO_2_PTYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_PTYPE_SHIFT)) & CAAM_CNFIFO_2_PTYPE_MASK) + #define CAAM_CNFIFO_2_BND_MASK (0x80000U) #define CAAM_CNFIFO_2_BND_SHIFT (19U) /*! BND @@ -15376,12 +17406,15 @@ typedef struct { * 0b1..Add boundary padding. */ #define CAAM_CNFIFO_2_BND(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_BND_SHIFT)) & CAAM_CNFIFO_2_BND_MASK) + #define CAAM_CNFIFO_2_DTYPE_MASK (0xF00000U) #define CAAM_CNFIFO_2_DTYPE_SHIFT (20U) #define CAAM_CNFIFO_2_DTYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_DTYPE_SHIFT)) & CAAM_CNFIFO_2_DTYPE_MASK) + #define CAAM_CNFIFO_2_STYPE_MASK (0x3000000U) #define CAAM_CNFIFO_2_STYPE_SHIFT (24U) #define CAAM_CNFIFO_2_STYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_STYPE_SHIFT)) & CAAM_CNFIFO_2_STYPE_MASK) + #define CAAM_CNFIFO_2_FC1_MASK (0x4000000U) #define CAAM_CNFIFO_2_FC1_SHIFT (26U) /*! FC1 @@ -15389,6 +17422,7 @@ typedef struct { * 0b1..Flush the Class 1 data. */ #define CAAM_CNFIFO_2_FC1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_FC1_SHIFT)) & CAAM_CNFIFO_2_FC1_MASK) + #define CAAM_CNFIFO_2_FC2_MASK (0x8000000U) #define CAAM_CNFIFO_2_FC2_SHIFT (27U) /*! FC2 @@ -15396,6 +17430,7 @@ typedef struct { * 0b1..Flush the Class 2 data. */ #define CAAM_CNFIFO_2_FC2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_FC2_SHIFT)) & CAAM_CNFIFO_2_FC2_MASK) + #define CAAM_CNFIFO_2_LC1_MASK (0x10000000U) #define CAAM_CNFIFO_2_LC1_SHIFT (28U) /*! LC1 @@ -15403,6 +17438,7 @@ typedef struct { * 0b1..This is the last Class 1 data. */ #define CAAM_CNFIFO_2_LC1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_LC1_SHIFT)) & CAAM_CNFIFO_2_LC1_MASK) + #define CAAM_CNFIFO_2_LC2_MASK (0x20000000U) #define CAAM_CNFIFO_2_LC2_SHIFT (29U) /*! LC2 @@ -15410,6 +17446,7 @@ typedef struct { * 0b1..This is the last Class 2 data. */ #define CAAM_CNFIFO_2_LC2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_LC2_SHIFT)) & CAAM_CNFIFO_2_LC2_MASK) + #define CAAM_CNFIFO_2_DEST_MASK (0xC0000000U) #define CAAM_CNFIFO_2_DEST_SHIFT (30U) /*! DEST @@ -15428,6 +17465,7 @@ typedef struct { /*! @name CIFIFO - CCB 0 Input Data FIFO */ /*! @{ */ + #define CAAM_CIFIFO_IFIFO_MASK (0xFFFFFFFFU) #define CAAM_CIFIFO_IFIFO_SHIFT (0U) #define CAAM_CIFIFO_IFIFO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CIFIFO_IFIFO_SHIFT)) & CAAM_CIFIFO_IFIFO_MASK) @@ -15438,6 +17476,7 @@ typedef struct { /*! @name COFIFO - CCB 0 Output Data FIFO */ /*! @{ */ + #define CAAM_COFIFO_OFIFO_MASK (0xFFFFFFFFFFFFFFFFU) #define CAAM_COFIFO_OFIFO_SHIFT (0U) #define CAAM_COFIFO_OFIFO(x) (((uint64_t)(((uint64_t)(x)) << CAAM_COFIFO_OFIFO_SHIFT)) & CAAM_COFIFO_OFIFO_MASK) @@ -15448,9 +17487,11 @@ typedef struct { /*! @name DJQCR_MS - DECO0 Job Queue Control Register, most-significant half */ /*! @{ */ + #define CAAM_DJQCR_MS_ID_MASK (0x7U) #define CAAM_DJQCR_MS_ID_SHIFT (0U) #define CAAM_DJQCR_MS_ID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_ID_SHIFT)) & CAAM_DJQCR_MS_ID_MASK) + #define CAAM_DJQCR_MS_SRC_MASK (0x700U) #define CAAM_DJQCR_MS_SRC_SHIFT (8U) /*! SRC @@ -15464,6 +17505,7 @@ typedef struct { * 0b111..Reserved */ #define CAAM_DJQCR_MS_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_SRC_SHIFT)) & CAAM_DJQCR_MS_SRC_MASK) + #define CAAM_DJQCR_MS_AMTD_MASK (0x8000U) #define CAAM_DJQCR_MS_AMTD_SHIFT (15U) /*! AMTD @@ -15471,6 +17513,7 @@ typedef struct { * 0b1..The Allowed Make Trusted Descriptor bit was set. */ #define CAAM_DJQCR_MS_AMTD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_AMTD_SHIFT)) & CAAM_DJQCR_MS_AMTD_MASK) + #define CAAM_DJQCR_MS_SOB_MASK (0x10000U) #define CAAM_DJQCR_MS_SOB_SHIFT (16U) /*! SOB @@ -15478,6 +17521,7 @@ typedef struct { * 0b1..Shared Descriptor HAS been loaded. */ #define CAAM_DJQCR_MS_SOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_SOB_SHIFT)) & CAAM_DJQCR_MS_SOB_MASK) + #define CAAM_DJQCR_MS_DWS_MASK (0x80000U) #define CAAM_DJQCR_MS_DWS_SHIFT (19U) /*! DWS @@ -15485,9 +17529,11 @@ typedef struct { * 0b1..Double Word Swap is set. */ #define CAAM_DJQCR_MS_DWS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_DWS_SHIFT)) & CAAM_DJQCR_MS_DWS_MASK) + #define CAAM_DJQCR_MS_SHR_FROM_MASK (0x7000000U) #define CAAM_DJQCR_MS_SHR_FROM_SHIFT (24U) #define CAAM_DJQCR_MS_SHR_FROM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_SHR_FROM_SHIFT)) & CAAM_DJQCR_MS_SHR_FROM_MASK) + #define CAAM_DJQCR_MS_ILE_MASK (0x8000000U) #define CAAM_DJQCR_MS_ILE_SHIFT (27U) /*! ILE @@ -15495,6 +17541,7 @@ typedef struct { * 0b1..Byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer. */ #define CAAM_DJQCR_MS_ILE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_ILE_SHIFT)) & CAAM_DJQCR_MS_ILE_MASK) + #define CAAM_DJQCR_MS_FOUR_MASK (0x10000000U) #define CAAM_DJQCR_MS_FOUR_SHIFT (28U) /*! FOUR @@ -15502,6 +17549,7 @@ typedef struct { * 0b1..DECO has been given at least four words of the descriptor. */ #define CAAM_DJQCR_MS_FOUR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_FOUR_SHIFT)) & CAAM_DJQCR_MS_FOUR_MASK) + #define CAAM_DJQCR_MS_WHL_MASK (0x20000000U) #define CAAM_DJQCR_MS_WHL_SHIFT (29U) /*! WHL @@ -15509,6 +17557,7 @@ typedef struct { * 0b1..DECO has been given the whole descriptor. */ #define CAAM_DJQCR_MS_WHL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_WHL_SHIFT)) & CAAM_DJQCR_MS_WHL_MASK) + #define CAAM_DJQCR_MS_SING_MASK (0x40000000U) #define CAAM_DJQCR_MS_SING_SHIFT (30U) /*! SING @@ -15516,6 +17565,7 @@ typedef struct { * 0b1..Tell DECO to execute the descriptor in single-step mode. */ #define CAAM_DJQCR_MS_SING(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_SING_SHIFT)) & CAAM_DJQCR_MS_SING_MASK) + #define CAAM_DJQCR_MS_STEP_MASK (0x80000000U) #define CAAM_DJQCR_MS_STEP_SHIFT (31U) /*! STEP @@ -15530,6 +17580,7 @@ typedef struct { /*! @name DJQCR_LS - DECO0 Job Queue Control Register, least-significant half */ /*! @{ */ + #define CAAM_DJQCR_LS_CMD_MASK (0xFFFFFFFFU) #define CAAM_DJQCR_LS_CMD_SHIFT (0U) #define CAAM_DJQCR_LS_CMD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_LS_CMD_SHIFT)) & CAAM_DJQCR_LS_CMD_MASK) @@ -15540,6 +17591,7 @@ typedef struct { /*! @name DDAR - DECO0 Descriptor Address Register */ /*! @{ */ + #define CAAM_DDAR_DPTR_MASK (0xFFFFFFFFFU) #define CAAM_DDAR_DPTR_SHIFT (0U) #define CAAM_DDAR_DPTR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DDAR_DPTR_SHIFT)) & CAAM_DDAR_DPTR_MASK) @@ -15550,12 +17602,15 @@ typedef struct { /*! @name DOPSTA_MS - DECO0 Operation Status Register, most-significant half */ /*! @{ */ + #define CAAM_DOPSTA_MS_STATUS_MASK (0xFFU) #define CAAM_DOPSTA_MS_STATUS_SHIFT (0U) #define CAAM_DOPSTA_MS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_MS_STATUS_SHIFT)) & CAAM_DOPSTA_MS_STATUS_MASK) + #define CAAM_DOPSTA_MS_COMMAND_INDEX_MASK (0x7F00U) #define CAAM_DOPSTA_MS_COMMAND_INDEX_SHIFT (8U) #define CAAM_DOPSTA_MS_COMMAND_INDEX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_MS_COMMAND_INDEX_SHIFT)) & CAAM_DOPSTA_MS_COMMAND_INDEX_MASK) + #define CAAM_DOPSTA_MS_NLJ_MASK (0x8000000U) #define CAAM_DOPSTA_MS_NLJ_SHIFT (27U) /*! NLJ @@ -15563,6 +17618,7 @@ typedef struct { * 0b1..The original job descriptor running in this DECO has caused another job descriptor to be executed. */ #define CAAM_DOPSTA_MS_NLJ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_MS_NLJ_SHIFT)) & CAAM_DOPSTA_MS_NLJ_MASK) + #define CAAM_DOPSTA_MS_STATUS_TYPE_MASK (0xF0000000U) #define CAAM_DOPSTA_MS_STATUS_TYPE_SHIFT (28U) /*! STATUS_TYPE @@ -15582,6 +17638,7 @@ typedef struct { /*! @name DOPSTA_LS - DECO0 Operation Status Register, least-significant half */ /*! @{ */ + #define CAAM_DOPSTA_LS_OUT_CT_MASK (0xFFFFFFFFU) #define CAAM_DOPSTA_LS_OUT_CT_SHIFT (0U) #define CAAM_DOPSTA_LS_OUT_CT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_LS_OUT_CT_SHIFT)) & CAAM_DOPSTA_LS_OUT_CT_MASK) @@ -15592,9 +17649,11 @@ typedef struct { /*! @name DPDIDSR - DECO0 Primary DID Status Register */ /*! @{ */ + #define CAAM_DPDIDSR_PRIM_DID_MASK (0xFU) #define CAAM_DPDIDSR_PRIM_DID_SHIFT (0U) #define CAAM_DPDIDSR_PRIM_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DPDIDSR_PRIM_DID_SHIFT)) & CAAM_DPDIDSR_PRIM_DID_MASK) + #define CAAM_DPDIDSR_PRIM_ICID_MASK (0x3FF80000U) #define CAAM_DPDIDSR_PRIM_ICID_SHIFT (19U) #define CAAM_DPDIDSR_PRIM_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DPDIDSR_PRIM_ICID_SHIFT)) & CAAM_DPDIDSR_PRIM_ICID_MASK) @@ -15605,9 +17664,11 @@ typedef struct { /*! @name DODIDSR - DECO0 Output DID Status Register */ /*! @{ */ + #define CAAM_DODIDSR_OUT_DID_MASK (0xFU) #define CAAM_DODIDSR_OUT_DID_SHIFT (0U) #define CAAM_DODIDSR_OUT_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DODIDSR_OUT_DID_SHIFT)) & CAAM_DODIDSR_OUT_DID_MASK) + #define CAAM_DODIDSR_OUT_ICID_MASK (0x3FF80000U) #define CAAM_DODIDSR_OUT_ICID_SHIFT (19U) #define CAAM_DODIDSR_OUT_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DODIDSR_OUT_ICID_SHIFT)) & CAAM_DODIDSR_OUT_ICID_MASK) @@ -15618,6 +17679,7 @@ typedef struct { /*! @name DMTH_MS - DECO0 Math Register 0_MS..DECO0 Math Register 3_MS */ /*! @{ */ + #define CAAM_DMTH_MS_MATH_MS_MASK (0xFFFFFFFFU) #define CAAM_DMTH_MS_MATH_MS_SHIFT (0U) #define CAAM_DMTH_MS_MATH_MS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMTH_MS_MATH_MS_SHIFT)) & CAAM_DMTH_MS_MATH_MS_MASK) @@ -15631,6 +17693,7 @@ typedef struct { /*! @name DMTH_LS - DECO0 Math Register 0_LS..DECO0 Math Register 3_LS */ /*! @{ */ + #define CAAM_DMTH_LS_MATH_LS_MASK (0xFFFFFFFFU) #define CAAM_DMTH_LS_MATH_LS_SHIFT (0U) #define CAAM_DMTH_LS_MATH_LS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMTH_LS_MATH_LS_SHIFT)) & CAAM_DMTH_LS_MATH_LS_MASK) @@ -15644,6 +17707,7 @@ typedef struct { /*! @name DGTR_0 - DECO0 Gather Table Register 0 Word 0 */ /*! @{ */ + #define CAAM_DGTR_0_ADDRESS_POINTER_MASK (0xFU) #define CAAM_DGTR_0_ADDRESS_POINTER_SHIFT (0U) /*! ADDRESS_POINTER - most-significant bits of memory address pointed to by table entry @@ -15659,6 +17723,7 @@ typedef struct { /*! @name DGTR_1 - DECO0 Gather Table Register 0 Word 1 */ /*! @{ */ + #define CAAM_DGTR_1_ADDRESS_POINTER_MASK (0xFFFFFFFFU) #define CAAM_DGTR_1_ADDRESS_POINTER_SHIFT (0U) #define CAAM_DGTR_1_ADDRESS_POINTER(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_1_ADDRESS_POINTER_SHIFT)) & CAAM_DGTR_1_ADDRESS_POINTER_MASK) @@ -15672,9 +17737,11 @@ typedef struct { /*! @name DGTR_2 - DECO0 Gather Table Register 0 Word 2 */ /*! @{ */ + #define CAAM_DGTR_2_Length_MASK (0x3FFFFFFFU) #define CAAM_DGTR_2_Length_SHIFT (0U) #define CAAM_DGTR_2_Length(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_2_Length_SHIFT)) & CAAM_DGTR_2_Length_MASK) + #define CAAM_DGTR_2_F_MASK (0x40000000U) #define CAAM_DGTR_2_F_SHIFT (30U) /*! F @@ -15682,6 +17749,7 @@ typedef struct { * 0b1..This is the last entry of the SGT. */ #define CAAM_DGTR_2_F(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_2_F_SHIFT)) & CAAM_DGTR_2_F_MASK) + #define CAAM_DGTR_2_E_MASK (0x80000000U) #define CAAM_DGTR_2_E_SHIFT (31U) /*! E @@ -15699,6 +17767,7 @@ typedef struct { /*! @name DGTR_3 - DECO0 Gather Table Register 0 Word 3 */ /*! @{ */ + #define CAAM_DGTR_3_Offset_MASK (0x1FFFU) #define CAAM_DGTR_3_Offset_SHIFT (0U) #define CAAM_DGTR_3_Offset(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_3_Offset_SHIFT)) & CAAM_DGTR_3_Offset_MASK) @@ -15712,6 +17781,7 @@ typedef struct { /*! @name DSTR_0 - DECO0 Scatter Table Register 0 Word 0 */ /*! @{ */ + #define CAAM_DSTR_0_ADDRESS_POINTER_MASK (0xFU) #define CAAM_DSTR_0_ADDRESS_POINTER_SHIFT (0U) /*! ADDRESS_POINTER - most-significant bits of memory address pointed to by table entry @@ -15727,6 +17797,7 @@ typedef struct { /*! @name DSTR_1 - DECO0 Scatter Table Register 0 Word 1 */ /*! @{ */ + #define CAAM_DSTR_1_ADDRESS_POINTER_MASK (0xFFFFFFFFU) #define CAAM_DSTR_1_ADDRESS_POINTER_SHIFT (0U) #define CAAM_DSTR_1_ADDRESS_POINTER(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_1_ADDRESS_POINTER_SHIFT)) & CAAM_DSTR_1_ADDRESS_POINTER_MASK) @@ -15740,9 +17811,11 @@ typedef struct { /*! @name DSTR_2 - DECO0 Scatter Table Register 0 Word 2 */ /*! @{ */ + #define CAAM_DSTR_2_Length_MASK (0x3FFFFFFFU) #define CAAM_DSTR_2_Length_SHIFT (0U) #define CAAM_DSTR_2_Length(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_2_Length_SHIFT)) & CAAM_DSTR_2_Length_MASK) + #define CAAM_DSTR_2_F_MASK (0x40000000U) #define CAAM_DSTR_2_F_SHIFT (30U) /*! F @@ -15750,6 +17823,7 @@ typedef struct { * 0b1..This is the last entry of the SGT. */ #define CAAM_DSTR_2_F(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_2_F_SHIFT)) & CAAM_DSTR_2_F_MASK) + #define CAAM_DSTR_2_E_MASK (0x80000000U) #define CAAM_DSTR_2_E_SHIFT (31U) /*! E @@ -15767,6 +17841,7 @@ typedef struct { /*! @name DSTR_3 - DECO0 Scatter Table Register 0 Word 3 */ /*! @{ */ + #define CAAM_DSTR_3_Offset_MASK (0x1FFFU) #define CAAM_DSTR_3_Offset_SHIFT (0U) #define CAAM_DSTR_3_Offset(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_3_Offset_SHIFT)) & CAAM_DSTR_3_Offset_MASK) @@ -15780,6 +17855,7 @@ typedef struct { /*! @name DDESB - DECO0 Descriptor Buffer Word 0..DECO0 Descriptor Buffer Word 63 */ /*! @{ */ + #define CAAM_DDESB_DESBW_MASK (0xFFFFFFFFU) #define CAAM_DDESB_DESBW_SHIFT (0U) #define CAAM_DDESB_DESBW(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDESB_DESBW_SHIFT)) & CAAM_DDESB_DESBW_MASK) @@ -15793,9 +17869,11 @@ typedef struct { /*! @name DDJR - DECO0 Debug Job Register */ /*! @{ */ + #define CAAM_DDJR_ID_MASK (0x7U) #define CAAM_DDJR_ID_SHIFT (0U) #define CAAM_DDJR_ID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_ID_SHIFT)) & CAAM_DDJR_ID_MASK) + #define CAAM_DDJR_SRC_MASK (0x700U) #define CAAM_DDJR_SRC_SHIFT (8U) /*! SRC @@ -15807,6 +17885,7 @@ typedef struct { * 0b101, 0b110, 0b111..Reserved */ #define CAAM_DDJR_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_SRC_SHIFT)) & CAAM_DDJR_SRC_MASK) + #define CAAM_DDJR_JDDS_MASK (0x4000U) #define CAAM_DDJR_JDDS_SHIFT (14U) /*! JDDS @@ -15814,6 +17893,7 @@ typedef struct { * 0b0..Non-SEQ DID */ #define CAAM_DDJR_JDDS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_JDDS_SHIFT)) & CAAM_DDJR_JDDS_MASK) + #define CAAM_DDJR_AMTD_MASK (0x8000U) #define CAAM_DDJR_AMTD_SHIFT (15U) /*! AMTD @@ -15821,6 +17901,7 @@ typedef struct { * 0b1..The Allowed Make Trusted Descriptor bit was set. */ #define CAAM_DDJR_AMTD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_AMTD_SHIFT)) & CAAM_DDJR_AMTD_MASK) + #define CAAM_DDJR_GSD_MASK (0x10000U) #define CAAM_DDJR_GSD_SHIFT (16U) /*! GSD @@ -15828,6 +17909,7 @@ typedef struct { * 0b1..Shared Descriptor was obtained from another DECO. */ #define CAAM_DDJR_GSD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_GSD_SHIFT)) & CAAM_DDJR_GSD_MASK) + #define CAAM_DDJR_DWS_MASK (0x80000U) #define CAAM_DDJR_DWS_SHIFT (19U) /*! DWS @@ -15835,9 +17917,11 @@ typedef struct { * 0b1..Double Word Swap is set. */ #define CAAM_DDJR_DWS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_DWS_SHIFT)) & CAAM_DDJR_DWS_MASK) + #define CAAM_DDJR_SHR_FROM_MASK (0x7000000U) #define CAAM_DDJR_SHR_FROM_SHIFT (24U) #define CAAM_DDJR_SHR_FROM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_SHR_FROM_SHIFT)) & CAAM_DDJR_SHR_FROM_MASK) + #define CAAM_DDJR_ILE_MASK (0x8000000U) #define CAAM_DDJR_ILE_SHIFT (27U) /*! ILE @@ -15845,6 +17929,7 @@ typedef struct { * 0b1..Byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer. */ #define CAAM_DDJR_ILE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_ILE_SHIFT)) & CAAM_DDJR_ILE_MASK) + #define CAAM_DDJR_FOUR_MASK (0x10000000U) #define CAAM_DDJR_FOUR_SHIFT (28U) /*! FOUR @@ -15852,6 +17937,7 @@ typedef struct { * 0b1..DECO has been given at least four words of the descriptor. */ #define CAAM_DDJR_FOUR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_FOUR_SHIFT)) & CAAM_DDJR_FOUR_MASK) + #define CAAM_DDJR_WHL_MASK (0x20000000U) #define CAAM_DDJR_WHL_SHIFT (29U) /*! WHL @@ -15859,6 +17945,7 @@ typedef struct { * 0b1..DECO has been given the whole descriptor. */ #define CAAM_DDJR_WHL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_WHL_SHIFT)) & CAAM_DDJR_WHL_MASK) + #define CAAM_DDJR_SING_MASK (0x40000000U) #define CAAM_DDJR_SING_SHIFT (30U) /*! SING @@ -15866,6 +17953,7 @@ typedef struct { * 0b1..DECO has been told to execute the descriptor in single-step mode. */ #define CAAM_DDJR_SING(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_SING_SHIFT)) & CAAM_DDJR_SING_MASK) + #define CAAM_DDJR_STEP_MASK (0x80000000U) #define CAAM_DDJR_STEP_SHIFT (31U) /*! STEP @@ -15880,6 +17968,7 @@ typedef struct { /*! @name DDDR - DECO0 Debug DECO Register */ /*! @{ */ + #define CAAM_DDDR_CT_MASK (0x1U) #define CAAM_DDDR_CT_SHIFT (0U) /*! CT @@ -15887,6 +17976,7 @@ typedef struct { * 0b1..This DECO is currently generating the signature of a Trusted Descriptor. */ #define CAAM_DDDR_CT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_CT_SHIFT)) & CAAM_DDDR_CT_MASK) + #define CAAM_DDDR_BRB_MASK (0x2U) #define CAAM_DDDR_BRB_SHIFT (1U) /*! BRB @@ -15894,6 +17984,7 @@ typedef struct { * 0b1..The READ machine in the Burster is busy. */ #define CAAM_DDDR_BRB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_BRB_SHIFT)) & CAAM_DDDR_BRB_MASK) + #define CAAM_DDDR_BWB_MASK (0x4U) #define CAAM_DDDR_BWB_SHIFT (2U) /*! BWB @@ -15901,6 +17992,7 @@ typedef struct { * 0b1..The WRITE machine in the Burster is busy. */ #define CAAM_DDDR_BWB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_BWB_SHIFT)) & CAAM_DDDR_BWB_MASK) + #define CAAM_DDDR_NC_MASK (0x8U) #define CAAM_DDDR_NC_SHIFT (3U) /*! NC @@ -15908,15 +18000,19 @@ typedef struct { * 0b1..This DECO is not currently executing a command. */ #define CAAM_DDDR_NC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_NC_SHIFT)) & CAAM_DDDR_NC_MASK) + #define CAAM_DDDR_CSA_MASK (0x10U) #define CAAM_DDDR_CSA_SHIFT (4U) #define CAAM_DDDR_CSA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_CSA_SHIFT)) & CAAM_DDDR_CSA_MASK) + #define CAAM_DDDR_CMD_STAGE_MASK (0xE0U) #define CAAM_DDDR_CMD_STAGE_SHIFT (5U) #define CAAM_DDDR_CMD_STAGE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_CMD_STAGE_SHIFT)) & CAAM_DDDR_CMD_STAGE_MASK) + #define CAAM_DDDR_CMD_INDEX_MASK (0x3F00U) #define CAAM_DDDR_CMD_INDEX_SHIFT (8U) #define CAAM_DDDR_CMD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_CMD_INDEX_SHIFT)) & CAAM_DDDR_CMD_INDEX_MASK) + #define CAAM_DDDR_NLJ_MASK (0x4000U) #define CAAM_DDDR_NLJ_SHIFT (14U) /*! NLJ @@ -15924,6 +18020,7 @@ typedef struct { * 0b1..The original job descriptor running in this DECO has caused another job descriptor to be executed. */ #define CAAM_DDDR_NLJ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_NLJ_SHIFT)) & CAAM_DDDR_NLJ_MASK) + #define CAAM_DDDR_PTCL_RUN_MASK (0x8000U) #define CAAM_DDDR_PTCL_RUN_SHIFT (15U) /*! PTCL_RUN @@ -15931,15 +18028,19 @@ typedef struct { * 0b1..A protocol is running in this DECO. */ #define CAAM_DDDR_PTCL_RUN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_PTCL_RUN_SHIFT)) & CAAM_DDDR_PTCL_RUN_MASK) + #define CAAM_DDDR_PDB_STALL_MASK (0x30000U) #define CAAM_DDDR_PDB_STALL_SHIFT (16U) #define CAAM_DDDR_PDB_STALL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_PDB_STALL_SHIFT)) & CAAM_DDDR_PDB_STALL_MASK) + #define CAAM_DDDR_PDB_WB_ST_MASK (0xC0000U) #define CAAM_DDDR_PDB_WB_ST_SHIFT (18U) #define CAAM_DDDR_PDB_WB_ST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_PDB_WB_ST_SHIFT)) & CAAM_DDDR_PDB_WB_ST_MASK) + #define CAAM_DDDR_DECO_STATE_MASK (0xF00000U) #define CAAM_DDDR_DECO_STATE_SHIFT (20U) #define CAAM_DDDR_DECO_STATE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_DECO_STATE_SHIFT)) & CAAM_DDDR_DECO_STATE_MASK) + #define CAAM_DDDR_NSEQLSEL_MASK (0x3000000U) #define CAAM_DDDR_NSEQLSEL_SHIFT (24U) /*! NSEQLSEL @@ -15948,6 +18049,7 @@ typedef struct { * 0b11..Trusted DID */ #define CAAM_DDDR_NSEQLSEL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_NSEQLSEL_SHIFT)) & CAAM_DDDR_NSEQLSEL_MASK) + #define CAAM_DDDR_SEQLSEL_MASK (0xC000000U) #define CAAM_DDDR_SEQLSEL_SHIFT (26U) /*! SEQLSEL @@ -15956,9 +18058,11 @@ typedef struct { * 0b11..Trusted DID */ #define CAAM_DDDR_SEQLSEL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_SEQLSEL_SHIFT)) & CAAM_DDDR_SEQLSEL_MASK) + #define CAAM_DDDR_TRCT_MASK (0x30000000U) #define CAAM_DDDR_TRCT_SHIFT (28U) #define CAAM_DDDR_TRCT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_TRCT_SHIFT)) & CAAM_DDDR_TRCT_MASK) + #define CAAM_DDDR_SD_MASK (0x40000000U) #define CAAM_DDDR_SD_SHIFT (30U) /*! SD @@ -15966,6 +18070,7 @@ typedef struct { * 0b1..This DECO has received a shared descriptor from another DECO. */ #define CAAM_DDDR_SD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_SD_SHIFT)) & CAAM_DDDR_SD_MASK) + #define CAAM_DDDR_VALID_MASK (0x80000000U) #define CAAM_DDDR_VALID_SHIFT (31U) /*! VALID @@ -15980,6 +18085,7 @@ typedef struct { /*! @name DDJP - DECO0 Debug Job Pointer */ /*! @{ */ + #define CAAM_DDJP_JDPTR_MASK (0xFFFFFFFFFU) #define CAAM_DDJP_JDPTR_SHIFT (0U) #define CAAM_DDJP_JDPTR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DDJP_JDPTR_SHIFT)) & CAAM_DDJP_JDPTR_MASK) @@ -15990,6 +18096,7 @@ typedef struct { /*! @name DSDP - DECO0 Debug Shared Pointer */ /*! @{ */ + #define CAAM_DSDP_SDPTR_MASK (0xFFFFFFFFFU) #define CAAM_DSDP_SDPTR_SHIFT (0U) #define CAAM_DSDP_SDPTR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DSDP_SDPTR_SHIFT)) & CAAM_DSDP_SDPTR_MASK) @@ -16000,9 +18107,11 @@ typedef struct { /*! @name DDDR_MS - DECO0 Debug DID, most-significant half */ /*! @{ */ + #define CAAM_DDDR_MS_PRIM_DID_MASK (0xFU) #define CAAM_DDDR_MS_PRIM_DID_SHIFT (0U) #define CAAM_DDDR_MS_PRIM_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_PRIM_DID_SHIFT)) & CAAM_DDDR_MS_PRIM_DID_MASK) + #define CAAM_DDDR_MS_PRIM_TZ_MASK (0x10U) #define CAAM_DDDR_MS_PRIM_TZ_SHIFT (4U) /*! PRIM_TZ @@ -16010,12 +18119,15 @@ typedef struct { * 0b1..TrustZone SecureWorld */ #define CAAM_DDDR_MS_PRIM_TZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_PRIM_TZ_SHIFT)) & CAAM_DDDR_MS_PRIM_TZ_MASK) + #define CAAM_DDDR_MS_PRIM_ICID_MASK (0xFFE0U) #define CAAM_DDDR_MS_PRIM_ICID_SHIFT (5U) #define CAAM_DDDR_MS_PRIM_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_PRIM_ICID_SHIFT)) & CAAM_DDDR_MS_PRIM_ICID_MASK) + #define CAAM_DDDR_MS_OUT_DID_MASK (0xF0000U) #define CAAM_DDDR_MS_OUT_DID_SHIFT (16U) #define CAAM_DDDR_MS_OUT_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_OUT_DID_SHIFT)) & CAAM_DDDR_MS_OUT_DID_MASK) + #define CAAM_DDDR_MS_OUT_ICID_MASK (0xFFE00000U) #define CAAM_DDDR_MS_OUT_ICID_SHIFT (21U) #define CAAM_DDDR_MS_OUT_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_OUT_ICID_SHIFT)) & CAAM_DDDR_MS_OUT_ICID_MASK) @@ -16026,9 +18138,11 @@ typedef struct { /*! @name DDDR_LS - DECO0 Debug DID, least-significant half */ /*! @{ */ + #define CAAM_DDDR_LS_OUT_DID_MASK (0xFU) #define CAAM_DDDR_LS_OUT_DID_SHIFT (0U) #define CAAM_DDDR_LS_OUT_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_LS_OUT_DID_SHIFT)) & CAAM_DDDR_LS_OUT_DID_MASK) + #define CAAM_DDDR_LS_OUT_ICID_MASK (0x3FF80000U) #define CAAM_DDDR_LS_OUT_ICID_SHIFT (19U) #define CAAM_DDDR_LS_OUT_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_LS_OUT_ICID_SHIFT)) & CAAM_DDDR_LS_OUT_ICID_MASK) @@ -16039,6 +18153,7 @@ typedef struct { /*! @name SOL - Sequence Output Length Register */ /*! @{ */ + #define CAAM_SOL_SOL_MASK (0xFFFFFFFFU) #define CAAM_SOL_SOL_SHIFT (0U) #define CAAM_SOL_SOL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SOL_SOL_SHIFT)) & CAAM_SOL_SOL_MASK) @@ -16049,6 +18164,7 @@ typedef struct { /*! @name VSOL - Variable Sequence Output Length Register */ /*! @{ */ + #define CAAM_VSOL_VSOL_MASK (0xFFFFFFFFU) #define CAAM_VSOL_VSOL_SHIFT (0U) #define CAAM_VSOL_VSOL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_VSOL_VSOL_SHIFT)) & CAAM_VSOL_VSOL_MASK) @@ -16059,6 +18175,7 @@ typedef struct { /*! @name SIL - Sequence Input Length Register */ /*! @{ */ + #define CAAM_SIL_SIL_MASK (0xFFFFFFFFU) #define CAAM_SIL_SIL_SHIFT (0U) #define CAAM_SIL_SIL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SIL_SIL_SHIFT)) & CAAM_SIL_SIL_MASK) @@ -16069,6 +18186,7 @@ typedef struct { /*! @name VSIL - Variable Sequence Input Length Register */ /*! @{ */ + #define CAAM_VSIL_VSIL_MASK (0xFFFFFFFFU) #define CAAM_VSIL_VSIL_SHIFT (0U) #define CAAM_VSIL_VSIL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_VSIL_VSIL_SHIFT)) & CAAM_VSIL_VSIL_MASK) @@ -16079,6 +18197,7 @@ typedef struct { /*! @name DPOVRD - Protocol Override Register */ /*! @{ */ + #define CAAM_DPOVRD_DPOVRD_MASK (0xFFFFFFFFU) #define CAAM_DPOVRD_DPOVRD_SHIFT (0U) #define CAAM_DPOVRD_DPOVRD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DPOVRD_DPOVRD_SHIFT)) & CAAM_DPOVRD_DPOVRD_MASK) @@ -16089,6 +18208,7 @@ typedef struct { /*! @name UVSOL - Variable Sequence Output Length Register; Upper 32 bits */ /*! @{ */ + #define CAAM_UVSOL_UVSOL_MASK (0xFFFFFFFFU) #define CAAM_UVSOL_UVSOL_SHIFT (0U) #define CAAM_UVSOL_UVSOL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_UVSOL_UVSOL_SHIFT)) & CAAM_UVSOL_UVSOL_MASK) @@ -16099,6 +18219,7 @@ typedef struct { /*! @name UVSIL - Variable Sequence Input Length Register; Upper 32 bits */ /*! @{ */ + #define CAAM_UVSIL_UVSIL_MASK (0xFFFFFFFFU) #define CAAM_UVSIL_UVSIL_SHIFT (0U) #define CAAM_UVSIL_UVSIL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_UVSIL_UVSIL_SHIFT)) & CAAM_UVSIL_UVSIL_MASK) @@ -16216,11 +18337,13 @@ typedef struct { /*! @name MCR - Module Configuration register */ /*! @{ */ + #define CAN_MCR_MAXMB_MASK (0x7FU) #define CAN_MCR_MAXMB_SHIFT (0U) /*! MAXMB - Number Of The Last Message Buffer */ #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK) + #define CAN_MCR_IDAM_MASK (0x300U) #define CAN_MCR_IDAM_SHIFT (8U) /*! IDAM - ID Acceptance Mode @@ -16230,6 +18353,7 @@ typedef struct { * 0b11..Format D: All frames rejected. */ #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK) + #define CAN_MCR_FDEN_MASK (0x800U) #define CAN_MCR_FDEN_SHIFT (11U) /*! FDEN - CAN FD operation enable @@ -16237,6 +18361,7 @@ typedef struct { * 0b0..CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format. */ #define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK) + #define CAN_MCR_AEN_MASK (0x1000U) #define CAN_MCR_AEN_SHIFT (12U) /*! AEN - Abort Enable @@ -16244,6 +18369,7 @@ typedef struct { * 0b1..Abort enabled. */ #define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK) + #define CAN_MCR_LPRIOEN_MASK (0x2000U) #define CAN_MCR_LPRIOEN_SHIFT (13U) /*! LPRIOEN - Local Priority Enable @@ -16251,6 +18377,7 @@ typedef struct { * 0b1..Local Priority enabled. */ #define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK) + #define CAN_MCR_DMA_MASK (0x8000U) #define CAN_MCR_DMA_SHIFT (15U) /*! DMA - DMA Enable @@ -16258,6 +18385,7 @@ typedef struct { * 0b1..DMA feature for RX FIFO enabled. */ #define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK) + #define CAN_MCR_IRMQ_MASK (0x10000U) #define CAN_MCR_IRMQ_SHIFT (16U) /*! IRMQ - Individual Rx Masking And Queue Enable @@ -16266,6 +18394,7 @@ typedef struct { * 0b1..Individual Rx masking and queue feature are enabled. */ #define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK) + #define CAN_MCR_SRXDIS_MASK (0x20000U) #define CAN_MCR_SRXDIS_SHIFT (17U) /*! SRXDIS - Self Reception Disable @@ -16273,6 +18402,7 @@ typedef struct { * 0b1..Self-reception disabled. */ #define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK) + #define CAN_MCR_DOZE_MASK (0x40000U) #define CAN_MCR_DOZE_SHIFT (18U) /*! DOZE - Doze Mode Enable @@ -16280,6 +18410,7 @@ typedef struct { * 0b1..FlexCAN is enabled to enter low-power mode when Doze mode is requested. */ #define CAN_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK) + #define CAN_MCR_WAKSRC_MASK (0x80000U) #define CAN_MCR_WAKSRC_SHIFT (19U) /*! WAKSRC - Wake Up Source @@ -16287,6 +18418,7 @@ typedef struct { * 0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus. */ #define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK) + #define CAN_MCR_LPMACK_MASK (0x100000U) #define CAN_MCR_LPMACK_SHIFT (20U) /*! LPMACK - Low-Power Mode Acknowledge @@ -16294,6 +18426,7 @@ typedef struct { * 0b1..FlexCAN is in a low-power mode. */ #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK) + #define CAN_MCR_WRNEN_MASK (0x200000U) #define CAN_MCR_WRNEN_SHIFT (21U) /*! WRNEN - Warning Interrupt Enable @@ -16301,6 +18434,7 @@ typedef struct { * 0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96. */ #define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK) + #define CAN_MCR_SLFWAK_MASK (0x400000U) #define CAN_MCR_SLFWAK_SHIFT (22U) /*! SLFWAK - Self Wake Up @@ -16308,6 +18442,7 @@ typedef struct { * 0b1..FlexCAN Self Wake Up feature is enabled. */ #define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK) + #define CAN_MCR_SUPV_MASK (0x800000U) #define CAN_MCR_SUPV_SHIFT (23U) /*! SUPV - Supervisor Mode @@ -16316,6 +18451,7 @@ typedef struct { * behaves as though the access was done to an unimplemented register location. */ #define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK) + #define CAN_MCR_FRZACK_MASK (0x1000000U) #define CAN_MCR_FRZACK_SHIFT (24U) /*! FRZACK - Freeze Mode Acknowledge @@ -16323,6 +18459,7 @@ typedef struct { * 0b1..FlexCAN in Freeze mode, prescaler stopped. */ #define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK) + #define CAN_MCR_SOFTRST_MASK (0x2000000U) #define CAN_MCR_SOFTRST_SHIFT (25U) /*! SOFTRST - Soft Reset @@ -16330,6 +18467,7 @@ typedef struct { * 0b1..Resets the registers affected by soft reset. */ #define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK) + #define CAN_MCR_WAKMSK_MASK (0x4000000U) #define CAN_MCR_WAKMSK_SHIFT (26U) /*! WAKMSK - Wake Up Interrupt Mask @@ -16337,6 +18475,7 @@ typedef struct { * 0b1..Wake Up interrupt is enabled. */ #define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK) + #define CAN_MCR_NOTRDY_MASK (0x8000000U) #define CAN_MCR_NOTRDY_SHIFT (27U) /*! NOTRDY - FlexCAN Not Ready @@ -16344,6 +18483,7 @@ typedef struct { * 0b1..FlexCAN module is either in Disable mode, Doze mode, Stop mode, or Freeze mode. */ #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK) + #define CAN_MCR_HALT_MASK (0x10000000U) #define CAN_MCR_HALT_SHIFT (28U) /*! HALT - Halt FlexCAN @@ -16351,6 +18491,7 @@ typedef struct { * 0b1..Enters Freeze mode if the FRZ bit is asserted. */ #define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK) + #define CAN_MCR_RFEN_MASK (0x20000000U) #define CAN_MCR_RFEN_SHIFT (29U) /*! RFEN - Rx FIFO Enable @@ -16358,6 +18499,7 @@ typedef struct { * 0b1..Rx FIFO enabled. */ #define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK) + #define CAN_MCR_FRZ_MASK (0x40000000U) #define CAN_MCR_FRZ_SHIFT (30U) /*! FRZ - Freeze Enable @@ -16365,6 +18507,7 @@ typedef struct { * 0b1..Enabled to enter Freeze mode. */ #define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK) + #define CAN_MCR_MDIS_MASK (0x80000000U) #define CAN_MCR_MDIS_SHIFT (31U) /*! MDIS - Module Disable @@ -16376,11 +18519,13 @@ typedef struct { /*! @name CTRL1 - Control 1 register */ /*! @{ */ + #define CAN_CTRL1_PROPSEG_MASK (0x7U) #define CAN_CTRL1_PROPSEG_SHIFT (0U) /*! PROPSEG - Propagation Segment */ #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) + #define CAN_CTRL1_LOM_MASK (0x8U) #define CAN_CTRL1_LOM_SHIFT (3U) /*! LOM - Listen-Only Mode @@ -16388,6 +18533,7 @@ typedef struct { * 0b1..FlexCAN module operates in Listen-Only mode. */ #define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK) + #define CAN_CTRL1_LBUF_MASK (0x10U) #define CAN_CTRL1_LBUF_SHIFT (4U) /*! LBUF - Lowest Buffer Transmitted First @@ -16395,6 +18541,7 @@ typedef struct { * 0b1..Lowest number buffer is transmitted first. */ #define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK) + #define CAN_CTRL1_TSYN_MASK (0x20U) #define CAN_CTRL1_TSYN_SHIFT (5U) /*! TSYN - Timer Sync @@ -16402,6 +18549,7 @@ typedef struct { * 0b1..Timer sync feature enabled */ #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK) + #define CAN_CTRL1_BOFFREC_MASK (0x40U) #define CAN_CTRL1_BOFFREC_SHIFT (6U) /*! BOFFREC - Bus Off Recovery @@ -16409,6 +18557,7 @@ typedef struct { * 0b1..Automatic recovering from Bus Off state disabled. */ #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK) + #define CAN_CTRL1_SMP_MASK (0x80U) #define CAN_CTRL1_SMP_SHIFT (7U) /*! SMP - CAN Bit Sampling @@ -16417,6 +18566,7 @@ typedef struct { * preceding samples; a majority rule is used. */ #define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK) + #define CAN_CTRL1_RWRNMSK_MASK (0x400U) #define CAN_CTRL1_RWRNMSK_SHIFT (10U) /*! RWRNMSK - Rx Warning Interrupt Mask @@ -16424,6 +18574,7 @@ typedef struct { * 0b1..Rx Warning interrupt enabled. */ #define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK) + #define CAN_CTRL1_TWRNMSK_MASK (0x800U) #define CAN_CTRL1_TWRNMSK_SHIFT (11U) /*! TWRNMSK - Tx Warning Interrupt Mask @@ -16431,6 +18582,7 @@ typedef struct { * 0b1..Tx Warning interrupt enabled. */ #define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK) + #define CAN_CTRL1_LPB_MASK (0x1000U) #define CAN_CTRL1_LPB_SHIFT (12U) /*! LPB - Loop Back Mode @@ -16438,6 +18590,7 @@ typedef struct { * 0b1..Loop Back enabled. */ #define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK) + #define CAN_CTRL1_CLKSRC_MASK (0x2000U) #define CAN_CTRL1_CLKSRC_SHIFT (13U) /*! CLKSRC - CAN Engine Clock Source @@ -16445,6 +18598,7 @@ typedef struct { * 0b1..The CAN engine clock source is the peripheral clock. */ #define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK) + #define CAN_CTRL1_ERRMSK_MASK (0x4000U) #define CAN_CTRL1_ERRMSK_SHIFT (14U) /*! ERRMSK - Error Interrupt Mask @@ -16452,6 +18606,7 @@ typedef struct { * 0b1..Error interrupt enabled. */ #define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK) + #define CAN_CTRL1_BOFFMSK_MASK (0x8000U) #define CAN_CTRL1_BOFFMSK_SHIFT (15U) /*! BOFFMSK - Bus Off Interrupt Mask @@ -16459,21 +18614,25 @@ typedef struct { * 0b1..Bus Off interrupt enabled. */ #define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK) + #define CAN_CTRL1_PSEG2_MASK (0x70000U) #define CAN_CTRL1_PSEG2_SHIFT (16U) /*! PSEG2 - Phase Segment 2 */ #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) + #define CAN_CTRL1_PSEG1_MASK (0x380000U) #define CAN_CTRL1_PSEG1_SHIFT (19U) /*! PSEG1 - Phase Segment 1 */ #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) + #define CAN_CTRL1_RJW_MASK (0xC00000U) #define CAN_CTRL1_RJW_SHIFT (22U) /*! RJW - Resync Jump Width */ #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) + #define CAN_CTRL1_PRESDIV_MASK (0xFF000000U) #define CAN_CTRL1_PRESDIV_SHIFT (24U) /*! PRESDIV - Prescaler Division Factor @@ -16483,6 +18642,7 @@ typedef struct { /*! @name TIMER - Free Running Timer */ /*! @{ */ + #define CAN_TIMER_TIMER_MASK (0xFFFFU) #define CAN_TIMER_TIMER_SHIFT (0U) /*! TIMER - Timer Value @@ -16492,6 +18652,7 @@ typedef struct { /*! @name RXMGMASK - Rx Mailboxes Global Mask register */ /*! @{ */ + #define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU) #define CAN_RXMGMASK_MG_SHIFT (0U) /*! MG - Rx Mailboxes Global Mask Bits @@ -16501,6 +18662,7 @@ typedef struct { /*! @name RX14MASK - Rx 14 Mask register */ /*! @{ */ + #define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU) #define CAN_RX14MASK_RX14M_SHIFT (0U) /*! RX14M - Rx Buffer 14 Mask Bits @@ -16510,6 +18672,7 @@ typedef struct { /*! @name RX15MASK - Rx 15 Mask register */ /*! @{ */ + #define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU) #define CAN_RX15MASK_RX15M_SHIFT (0U) /*! RX15M - Rx Buffer 15 Mask Bits @@ -16519,21 +18682,25 @@ typedef struct { /*! @name ECR - Error Counter */ /*! @{ */ + #define CAN_ECR_TXERRCNT_MASK (0xFFU) #define CAN_ECR_TXERRCNT_SHIFT (0U) /*! TXERRCNT - Transmit Error Counter */ #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK) + #define CAN_ECR_RXERRCNT_MASK (0xFF00U) #define CAN_ECR_RXERRCNT_SHIFT (8U) /*! RXERRCNT - Receive Error Counter */ #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK) + #define CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U) #define CAN_ECR_TXERRCNT_FAST_SHIFT (16U) /*! TXERRCNT_FAST - Transmit Error Counter for fast bits */ #define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK) + #define CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U) #define CAN_ECR_RXERRCNT_FAST_SHIFT (24U) /*! RXERRCNT_FAST - Receive Error Counter for fast bits @@ -16543,6 +18710,7 @@ typedef struct { /*! @name ESR1 - Error and Status 1 register */ /*! @{ */ + #define CAN_ESR1_WAKINT_MASK (0x1U) #define CAN_ESR1_WAKINT_SHIFT (0U) /*! WAKINT - Wake-Up Interrupt @@ -16550,6 +18718,7 @@ typedef struct { * 0b1..Indicates a recessive to dominant transition was received on the CAN bus. */ #define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK) + #define CAN_ESR1_ERRINT_MASK (0x2U) #define CAN_ESR1_ERRINT_SHIFT (1U) /*! ERRINT - Error Interrupt @@ -16557,6 +18726,7 @@ typedef struct { * 0b1..Indicates setting of any error bit in the Error and Status register. */ #define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK) + #define CAN_ESR1_BOFFINT_MASK (0x4U) #define CAN_ESR1_BOFFINT_SHIFT (2U) /*! BOFFINT - Bus Off Interrupt @@ -16564,6 +18734,7 @@ typedef struct { * 0b1..FlexCAN module entered Bus Off state. */ #define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK) + #define CAN_ESR1_RX_MASK (0x8U) #define CAN_ESR1_RX_SHIFT (3U) /*! RX - FlexCAN In Reception @@ -16571,6 +18742,7 @@ typedef struct { * 0b1..FlexCAN is receiving a message. */ #define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK) + #define CAN_ESR1_FLTCONF_MASK (0x30U) #define CAN_ESR1_FLTCONF_SHIFT (4U) /*! FLTCONF - Fault Confinement State @@ -16579,6 +18751,7 @@ typedef struct { * 0b1x..Bus Off */ #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK) + #define CAN_ESR1_TX_MASK (0x40U) #define CAN_ESR1_TX_SHIFT (6U) /*! TX - FlexCAN In Transmission @@ -16586,6 +18759,7 @@ typedef struct { * 0b1..FlexCAN is transmitting a message. */ #define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK) + #define CAN_ESR1_IDLE_MASK (0x80U) #define CAN_ESR1_IDLE_SHIFT (7U) /*! IDLE - IDLE @@ -16593,6 +18767,7 @@ typedef struct { * 0b1..CAN bus is now IDLE. */ #define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK) + #define CAN_ESR1_RXWRN_MASK (0x100U) #define CAN_ESR1_RXWRN_SHIFT (8U) /*! RXWRN - Rx Error Warning @@ -16600,6 +18775,7 @@ typedef struct { * 0b1..RXERRCNT is greater than or equal to 96. */ #define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK) + #define CAN_ESR1_TXWRN_MASK (0x200U) #define CAN_ESR1_TXWRN_SHIFT (9U) /*! TXWRN - TX Error Warning @@ -16607,6 +18783,7 @@ typedef struct { * 0b1..TXERRCNT is greater than or equal to 96. */ #define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK) + #define CAN_ESR1_STFERR_MASK (0x400U) #define CAN_ESR1_STFERR_SHIFT (10U) /*! STFERR - Stuffing Error @@ -16614,6 +18791,7 @@ typedef struct { * 0b1..A stuffing error occurred since last read of this register. */ #define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK) + #define CAN_ESR1_FRMERR_MASK (0x800U) #define CAN_ESR1_FRMERR_SHIFT (11U) /*! FRMERR - Form Error @@ -16621,6 +18799,7 @@ typedef struct { * 0b1..A Form Error occurred since last read of this register. */ #define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK) + #define CAN_ESR1_CRCERR_MASK (0x1000U) #define CAN_ESR1_CRCERR_SHIFT (12U) /*! CRCERR - Cyclic Redundancy Check Error @@ -16628,6 +18807,7 @@ typedef struct { * 0b1..A CRC error occurred since last read of this register. */ #define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK) + #define CAN_ESR1_ACKERR_MASK (0x2000U) #define CAN_ESR1_ACKERR_SHIFT (13U) /*! ACKERR - Acknowledge Error @@ -16635,6 +18815,7 @@ typedef struct { * 0b1..An ACK error occurred since last read of this register. */ #define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK) + #define CAN_ESR1_BIT0ERR_MASK (0x4000U) #define CAN_ESR1_BIT0ERR_SHIFT (14U) /*! BIT0ERR - Bit0 Error @@ -16642,6 +18823,7 @@ typedef struct { * 0b1..At least one bit sent as dominant is received as recessive. */ #define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK) + #define CAN_ESR1_BIT1ERR_MASK (0x8000U) #define CAN_ESR1_BIT1ERR_SHIFT (15U) /*! BIT1ERR - Bit1 Error @@ -16649,6 +18831,7 @@ typedef struct { * 0b1..At least one bit sent as recessive is received as dominant. */ #define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK) + #define CAN_ESR1_RWRNINT_MASK (0x10000U) #define CAN_ESR1_RWRNINT_SHIFT (16U) /*! RWRNINT - Rx Warning Interrupt Flag @@ -16656,6 +18839,7 @@ typedef struct { * 0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96. */ #define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK) + #define CAN_ESR1_TWRNINT_MASK (0x20000U) #define CAN_ESR1_TWRNINT_SHIFT (17U) /*! TWRNINT - Tx Warning Interrupt Flag @@ -16663,6 +18847,7 @@ typedef struct { * 0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96. */ #define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK) + #define CAN_ESR1_SYNCH_MASK (0x40000U) #define CAN_ESR1_SYNCH_SHIFT (18U) /*! SYNCH - CAN Synchronization Status @@ -16670,6 +18855,7 @@ typedef struct { * 0b1..FlexCAN is synchronized to the CAN bus. */ #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK) + #define CAN_ESR1_BOFFDONEINT_MASK (0x80000U) #define CAN_ESR1_BOFFDONEINT_SHIFT (19U) /*! BOFFDONEINT - Bus Off Done Interrupt @@ -16677,6 +18863,7 @@ typedef struct { * 0b1..FlexCAN module has completed Bus Off process. */ #define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK) + #define CAN_ESR1_ERRINT_FAST_MASK (0x100000U) #define CAN_ESR1_ERRINT_FAST_SHIFT (20U) /*! ERRINT_FAST - Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set @@ -16684,6 +18871,7 @@ typedef struct { * 0b1..Indicates setting of any error bit detected in the data phase of CAN FD frames with the BRS bit set. */ #define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK) + #define CAN_ESR1_ERROVR_MASK (0x200000U) #define CAN_ESR1_ERROVR_SHIFT (21U) /*! ERROVR - Error Overrun @@ -16691,6 +18879,7 @@ typedef struct { * 0b1..Overrun has occurred. */ #define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK) + #define CAN_ESR1_STFERR_FAST_MASK (0x4000000U) #define CAN_ESR1_STFERR_FAST_SHIFT (26U) /*! STFERR_FAST - Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set @@ -16698,6 +18887,7 @@ typedef struct { * 0b1..A stuffing error occurred since last read of this register. */ #define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK) + #define CAN_ESR1_FRMERR_FAST_MASK (0x8000000U) #define CAN_ESR1_FRMERR_FAST_SHIFT (27U) /*! FRMERR_FAST - Form Error in the Data Phase of CAN FD frames with the BRS bit set @@ -16705,6 +18895,7 @@ typedef struct { * 0b1..A form error occurred since last read of this register. */ #define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK) + #define CAN_ESR1_CRCERR_FAST_MASK (0x10000000U) #define CAN_ESR1_CRCERR_FAST_SHIFT (28U) /*! CRCERR_FAST - Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set @@ -16712,6 +18903,7 @@ typedef struct { * 0b1..A CRC error occurred since last read of this register. */ #define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK) + #define CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U) #define CAN_ESR1_BIT0ERR_FAST_SHIFT (30U) /*! BIT0ERR_FAST - Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set @@ -16719,6 +18911,7 @@ typedef struct { * 0b1..At least one bit sent as dominant is received as recessive. */ #define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK) + #define CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U) #define CAN_ESR1_BIT1ERR_FAST_SHIFT (31U) /*! BIT1ERR_FAST - Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set @@ -16730,6 +18923,7 @@ typedef struct { /*! @name IMASK2 - Interrupt Masks 2 register */ /*! @{ */ + #define CAN_IMASK2_BUF63TO32M_MASK (0xFFFFFFFFU) #define CAN_IMASK2_BUF63TO32M_SHIFT (0U) /*! BUF63TO32M - Buffer MBi Mask @@ -16739,6 +18933,7 @@ typedef struct { /*! @name IMASK1 - Interrupt Masks 1 register */ /*! @{ */ + #define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU) #define CAN_IMASK1_BUF31TO0M_SHIFT (0U) /*! BUF31TO0M - Buffer MBi Mask @@ -16748,6 +18943,7 @@ typedef struct { /*! @name IFLAG2 - Interrupt Flags 2 register */ /*! @{ */ + #define CAN_IFLAG2_BUF63TO32I_MASK (0xFFFFFFFFU) #define CAN_IFLAG2_BUF63TO32I_SHIFT (0U) /*! BUF63TO32I - Buffer MBi Interrupt @@ -16757,6 +18953,7 @@ typedef struct { /*! @name IFLAG1 - Interrupt Flags 1 register */ /*! @{ */ + #define CAN_IFLAG1_BUF0I_MASK (0x1U) #define CAN_IFLAG1_BUF0I_SHIFT (0U) /*! BUF0I - Buffer MB0 Interrupt Or Clear FIFO bit @@ -16764,11 +18961,13 @@ typedef struct { * 0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0. */ #define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK) + #define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU) #define CAN_IFLAG1_BUF4TO1I_SHIFT (1U) /*! BUF4TO1I - Buffer MBi Interrupt Or Reserved */ #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK) + #define CAN_IFLAG1_BUF5I_MASK (0x20U) #define CAN_IFLAG1_BUF5I_SHIFT (5U) /*! BUF5I - Buffer MB5 Interrupt Or Frames available in Rx FIFO @@ -16777,6 +18976,7 @@ typedef struct { * MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled. */ #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK) + #define CAN_IFLAG1_BUF6I_MASK (0x40U) #define CAN_IFLAG1_BUF6I_SHIFT (6U) /*! BUF6I - Buffer MB6 Interrupt Or Rx FIFO Warning @@ -16784,6 +18984,7 @@ typedef struct { * 0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1 */ #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK) + #define CAN_IFLAG1_BUF7I_MASK (0x80U) #define CAN_IFLAG1_BUF7I_SHIFT (7U) /*! BUF7I - Buffer MB7 Interrupt Or Rx FIFO Overflow @@ -16791,6 +18992,7 @@ typedef struct { * 0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1 */ #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK) + #define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U) #define CAN_IFLAG1_BUF31TO8I_SHIFT (8U) /*! BUF31TO8I - Buffer MBi Interrupt @@ -16800,6 +19002,7 @@ typedef struct { /*! @name CTRL2 - Control 2 register */ /*! @{ */ + #define CAN_CTRL2_EDFLTDIS_MASK (0x800U) #define CAN_CTRL2_EDFLTDIS_SHIFT (11U) /*! EDFLTDIS - Edge Filter Disable @@ -16807,6 +19010,7 @@ typedef struct { * 0b1..Edge filter is disabled */ #define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK) + #define CAN_CTRL2_ISOCANFDEN_MASK (0x1000U) #define CAN_CTRL2_ISOCANFDEN_SHIFT (12U) /*! ISOCANFDEN - ISO CAN FD Enable @@ -16814,6 +19018,7 @@ typedef struct { * 0b1..FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1). */ #define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK) + #define CAN_CTRL2_PREXCEN_MASK (0x4000U) #define CAN_CTRL2_PREXCEN_SHIFT (14U) /*! PREXCEN - Protocol Exception Enable @@ -16821,6 +19026,7 @@ typedef struct { * 0b1..Protocol exception is enabled. */ #define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK) + #define CAN_CTRL2_TIMER_SRC_MASK (0x8000U) #define CAN_CTRL2_TIMER_SRC_SHIFT (15U) /*! TIMER_SRC - Timer Source @@ -16830,6 +19036,7 @@ typedef struct { * details about the external time tick. */ #define CAN_CTRL2_TIMER_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TIMER_SRC_SHIFT)) & CAN_CTRL2_TIMER_SRC_MASK) + #define CAN_CTRL2_EACEN_MASK (0x10000U) #define CAN_CTRL2_EACEN_SHIFT (16U) /*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes @@ -16838,6 +19045,7 @@ typedef struct { * the incoming frame. Mask bits do apply. */ #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK) + #define CAN_CTRL2_RRS_MASK (0x20000U) #define CAN_CTRL2_RRS_SHIFT (17U) /*! RRS - Remote Request Storing @@ -16845,6 +19053,7 @@ typedef struct { * 0b1..Remote request frame is stored. */ #define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK) + #define CAN_CTRL2_MRP_MASK (0x40000U) #define CAN_CTRL2_MRP_SHIFT (18U) /*! MRP - Mailboxes Reception Priority @@ -16852,16 +19061,19 @@ typedef struct { * 0b1..Matching starts from mailboxes and continues on Rx FIFO. */ #define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK) + #define CAN_CTRL2_TASD_MASK (0xF80000U) #define CAN_CTRL2_TASD_SHIFT (19U) /*! TASD - Tx Arbitration Start Delay */ #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK) + #define CAN_CTRL2_RFFN_MASK (0xF000000U) #define CAN_CTRL2_RFFN_SHIFT (24U) /*! RFFN - Number Of Rx FIFO Filters */ #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK) + #define CAN_CTRL2_WRMFRZ_MASK (0x10000000U) #define CAN_CTRL2_WRMFRZ_SHIFT (28U) /*! WRMFRZ - Write-Access To Memory In Freeze Mode @@ -16869,6 +19081,7 @@ typedef struct { * 0b1..Enable unrestricted write access to FlexCAN memory. */ #define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK) + #define CAN_CTRL2_ECRWRE_MASK (0x20000000U) #define CAN_CTRL2_ECRWRE_SHIFT (29U) /*! ECRWRE - Error-correction Configuration Register Write Enable @@ -16876,6 +19089,7 @@ typedef struct { * 0b1..Enable update. */ #define CAN_CTRL2_ECRWRE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ECRWRE_SHIFT)) & CAN_CTRL2_ECRWRE_MASK) + #define CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U) #define CAN_CTRL2_BOFFDONEMSK_SHIFT (30U) /*! BOFFDONEMSK - Bus Off Done Interrupt Mask @@ -16883,6 +19097,7 @@ typedef struct { * 0b1..Bus off done interrupt enabled. */ #define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK) + #define CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U) #define CAN_CTRL2_ERRMSK_FAST_SHIFT (31U) /*! ERRMSK_FAST - Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames @@ -16894,6 +19109,7 @@ typedef struct { /*! @name ESR2 - Error and Status 2 register */ /*! @{ */ + #define CAN_ESR2_IMB_MASK (0x2000U) #define CAN_ESR2_IMB_SHIFT (13U) /*! IMB - Inactive Mailbox @@ -16901,6 +19117,7 @@ typedef struct { * 0b1..If ESR2[VPS] is asserted, there is at least one inactive mailbox. LPTM content is the number of the first one. */ #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK) + #define CAN_ESR2_VPS_MASK (0x4000U) #define CAN_ESR2_VPS_SHIFT (14U) /*! VPS - Valid Priority Status @@ -16908,6 +19125,7 @@ typedef struct { * 0b1..Contents of IMB and LPTM are valid. */ #define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK) + #define CAN_ESR2_LPTM_MASK (0x7F0000U) #define CAN_ESR2_LPTM_SHIFT (16U) /*! LPTM - Lowest Priority Tx Mailbox @@ -16917,11 +19135,13 @@ typedef struct { /*! @name CRCR - CRC register */ /*! @{ */ + #define CAN_CRCR_TXCRC_MASK (0x7FFFU) #define CAN_CRCR_TXCRC_SHIFT (0U) /*! TXCRC - Transmitted CRC value */ #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK) + #define CAN_CRCR_MBCRC_MASK (0x7F0000U) #define CAN_CRCR_MBCRC_SHIFT (16U) /*! MBCRC - CRC Mailbox @@ -16931,6 +19151,7 @@ typedef struct { /*! @name RXFGMASK - Rx FIFO Global Mask register */ /*! @{ */ + #define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU) #define CAN_RXFGMASK_FGM_SHIFT (0U) /*! FGM - Rx FIFO Global Mask Bits @@ -16940,6 +19161,7 @@ typedef struct { /*! @name RXFIR - Rx FIFO Information register */ /*! @{ */ + #define CAN_RXFIR_IDHIT_MASK (0x1FFU) #define CAN_RXFIR_IDHIT_SHIFT (0U) /*! IDHIT - Identifier Acceptance Filter Hit Indicator @@ -16949,31 +19171,37 @@ typedef struct { /*! @name CBT - CAN Bit Timing register */ /*! @{ */ + #define CAN_CBT_EPSEG2_MASK (0x1FU) #define CAN_CBT_EPSEG2_SHIFT (0U) /*! EPSEG2 - Extended Phase Segment 2 */ #define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK) + #define CAN_CBT_EPSEG1_MASK (0x3E0U) #define CAN_CBT_EPSEG1_SHIFT (5U) /*! EPSEG1 - Extended Phase Segment 1 */ #define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK) + #define CAN_CBT_EPROPSEG_MASK (0xFC00U) #define CAN_CBT_EPROPSEG_SHIFT (10U) /*! EPROPSEG - Extended Propagation Segment */ #define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK) + #define CAN_CBT_ERJW_MASK (0x1F0000U) #define CAN_CBT_ERJW_SHIFT (16U) /*! ERJW - Extended Resync Jump Width */ #define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK) + #define CAN_CBT_EPRESDIV_MASK (0x7FE00000U) #define CAN_CBT_EPRESDIV_SHIFT (21U) /*! EPRESDIV - Extended Prescaler Division Factor */ #define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK) + #define CAN_CBT_BTF_MASK (0x80000000U) #define CAN_CBT_BTF_SHIFT (31U) /*! BTF - Bit Timing Format Enable @@ -17021,6 +19249,7 @@ typedef struct { /*! @name CS - Message Buffer 0 CS Register..Message Buffer 13 CS Register */ /*! @{ */ + #define CAN_CS_TIME_STAMP_MASK (0xFFFFU) #define CAN_CS_TIME_STAMP_SHIFT (0U) /*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running @@ -17028,42 +19257,50 @@ typedef struct { * appears on the CAN bus. */ #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK) + #define CAN_CS_DLC_MASK (0xF0000U) #define CAN_CS_DLC_SHIFT (16U) /*! DLC - Length of the data to be stored/transmitted. */ #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK) + #define CAN_CS_RTR_MASK (0x100000U) #define CAN_CS_RTR_SHIFT (20U) /*! RTR - Remote Transmission Request. One/zero for remote/data frame. */ #define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK) + #define CAN_CS_IDE_MASK (0x200000U) #define CAN_CS_IDE_SHIFT (21U) /*! IDE - ID Extended. One/zero for extended/standard format frame. */ #define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK) + #define CAN_CS_SRR_MASK (0x400000U) #define CAN_CS_SRR_SHIFT (22U) /*! SRR - Substitute Remote Request. Contains a fixed recessive bit. */ #define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK) + #define CAN_CS_CODE_MASK (0xF000000U) #define CAN_CS_CODE_SHIFT (24U) /*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by * the FlexCAN module itself, as part of the message buffer matching and arbitration process. */ #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK) + #define CAN_CS_ESI_MASK (0x20000000U) #define CAN_CS_ESI_SHIFT (29U) /*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive. */ #define CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK) + #define CAN_CS_BRS_MASK (0x40000000U) #define CAN_CS_BRS_SHIFT (30U) /*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame. */ #define CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK) + #define CAN_CS_EDL_MASK (0x80000000U) #define CAN_CS_EDL_SHIFT (31U) /*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames. @@ -17077,16 +19314,19 @@ typedef struct { /*! @name ID - Message Buffer 0 ID Register..Message Buffer 13 ID Register */ /*! @{ */ + #define CAN_ID_EXT_MASK (0x3FFFFU) #define CAN_ID_EXT_SHIFT (0U) /*! EXT - Contains extended (LOW word) identifier of message buffer. */ #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK) + #define CAN_ID_STD_MASK (0x1FFC0000U) #define CAN_ID_STD_SHIFT (18U) /*! STD - Contains standard/extended (HIGH word) identifier of message buffer. */ #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK) + #define CAN_ID_PRIO_MASK (0xE0000000U) #define CAN_ID_PRIO_SHIFT (29U) /*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only @@ -17101,321 +19341,385 @@ typedef struct { /*! @name WORD - Message Buffer 0 WORD_64B Register..Message Buffer 13 WORD_64B Register */ /*! @{ */ + #define CAN_WORD_DATA_BYTE_3_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_3_SHIFT (0U) /*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK) + #define CAN_WORD_DATA_BYTE_7_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_7_SHIFT (0U) /*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK) + #define CAN_WORD_DATA_BYTE_11_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_11_SHIFT (0U) /*! DATA_BYTE_11 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_11(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK) + #define CAN_WORD_DATA_BYTE_15_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_15_SHIFT (0U) /*! DATA_BYTE_15 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_15(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK) + #define CAN_WORD_DATA_BYTE_19_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_19_SHIFT (0U) /*! DATA_BYTE_19 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_19(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK) + #define CAN_WORD_DATA_BYTE_23_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_23_SHIFT (0U) /*! DATA_BYTE_23 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_23(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK) + #define CAN_WORD_DATA_BYTE_27_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_27_SHIFT (0U) /*! DATA_BYTE_27 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_27(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK) + #define CAN_WORD_DATA_BYTE_31_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_31_SHIFT (0U) /*! DATA_BYTE_31 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_31(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK) + #define CAN_WORD_DATA_BYTE_35_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_35_SHIFT (0U) /*! DATA_BYTE_35 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_35(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK) + #define CAN_WORD_DATA_BYTE_39_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_39_SHIFT (0U) /*! DATA_BYTE_39 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_39(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK) + #define CAN_WORD_DATA_BYTE_43_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_43_SHIFT (0U) /*! DATA_BYTE_43 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_43(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK) + #define CAN_WORD_DATA_BYTE_47_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_47_SHIFT (0U) /*! DATA_BYTE_47 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_47(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK) + #define CAN_WORD_DATA_BYTE_51_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_51_SHIFT (0U) /*! DATA_BYTE_51 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_51(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK) + #define CAN_WORD_DATA_BYTE_55_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_55_SHIFT (0U) /*! DATA_BYTE_55 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_55(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK) + #define CAN_WORD_DATA_BYTE_59_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_59_SHIFT (0U) /*! DATA_BYTE_59 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_59(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK) + #define CAN_WORD_DATA_BYTE_63_MASK (0xFFU) #define CAN_WORD_DATA_BYTE_63_SHIFT (0U) /*! DATA_BYTE_63 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_63(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK) + #define CAN_WORD_DATA_BYTE_2_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_2_SHIFT (8U) /*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK) + #define CAN_WORD_DATA_BYTE_6_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_6_SHIFT (8U) /*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK) + #define CAN_WORD_DATA_BYTE_10_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_10_SHIFT (8U) /*! DATA_BYTE_10 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_10(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK) + #define CAN_WORD_DATA_BYTE_14_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_14_SHIFT (8U) /*! DATA_BYTE_14 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_14(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK) + #define CAN_WORD_DATA_BYTE_18_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_18_SHIFT (8U) /*! DATA_BYTE_18 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_18(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK) + #define CAN_WORD_DATA_BYTE_22_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_22_SHIFT (8U) /*! DATA_BYTE_22 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_22(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK) + #define CAN_WORD_DATA_BYTE_26_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_26_SHIFT (8U) /*! DATA_BYTE_26 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_26(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK) + #define CAN_WORD_DATA_BYTE_30_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_30_SHIFT (8U) /*! DATA_BYTE_30 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_30(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK) + #define CAN_WORD_DATA_BYTE_34_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_34_SHIFT (8U) /*! DATA_BYTE_34 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_34(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK) + #define CAN_WORD_DATA_BYTE_38_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_38_SHIFT (8U) /*! DATA_BYTE_38 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_38(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK) + #define CAN_WORD_DATA_BYTE_42_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_42_SHIFT (8U) /*! DATA_BYTE_42 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_42(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK) + #define CAN_WORD_DATA_BYTE_46_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_46_SHIFT (8U) /*! DATA_BYTE_46 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_46(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK) + #define CAN_WORD_DATA_BYTE_50_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_50_SHIFT (8U) /*! DATA_BYTE_50 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_50(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK) + #define CAN_WORD_DATA_BYTE_54_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_54_SHIFT (8U) /*! DATA_BYTE_54 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_54(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK) + #define CAN_WORD_DATA_BYTE_58_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_58_SHIFT (8U) /*! DATA_BYTE_58 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_58(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK) + #define CAN_WORD_DATA_BYTE_62_MASK (0xFF00U) #define CAN_WORD_DATA_BYTE_62_SHIFT (8U) /*! DATA_BYTE_62 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_62(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK) + #define CAN_WORD_DATA_BYTE_1_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_1_SHIFT (16U) /*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK) + #define CAN_WORD_DATA_BYTE_5_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_5_SHIFT (16U) /*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK) + #define CAN_WORD_DATA_BYTE_9_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_9_SHIFT (16U) /*! DATA_BYTE_9 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_9(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK) + #define CAN_WORD_DATA_BYTE_13_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_13_SHIFT (16U) /*! DATA_BYTE_13 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_13(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK) + #define CAN_WORD_DATA_BYTE_17_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_17_SHIFT (16U) /*! DATA_BYTE_17 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_17(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK) + #define CAN_WORD_DATA_BYTE_21_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_21_SHIFT (16U) /*! DATA_BYTE_21 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_21(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK) + #define CAN_WORD_DATA_BYTE_25_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_25_SHIFT (16U) /*! DATA_BYTE_25 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_25(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK) + #define CAN_WORD_DATA_BYTE_29_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_29_SHIFT (16U) /*! DATA_BYTE_29 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_29(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK) + #define CAN_WORD_DATA_BYTE_33_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_33_SHIFT (16U) /*! DATA_BYTE_33 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_33(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK) + #define CAN_WORD_DATA_BYTE_37_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_37_SHIFT (16U) /*! DATA_BYTE_37 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_37(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK) + #define CAN_WORD_DATA_BYTE_41_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_41_SHIFT (16U) /*! DATA_BYTE_41 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_41(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK) + #define CAN_WORD_DATA_BYTE_45_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_45_SHIFT (16U) /*! DATA_BYTE_45 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_45(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK) + #define CAN_WORD_DATA_BYTE_49_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_49_SHIFT (16U) /*! DATA_BYTE_49 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_49(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK) + #define CAN_WORD_DATA_BYTE_53_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_53_SHIFT (16U) /*! DATA_BYTE_53 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_53(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK) + #define CAN_WORD_DATA_BYTE_57_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_57_SHIFT (16U) /*! DATA_BYTE_57 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_57(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK) + #define CAN_WORD_DATA_BYTE_61_MASK (0xFF0000U) #define CAN_WORD_DATA_BYTE_61_SHIFT (16U) /*! DATA_BYTE_61 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_61(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK) + #define CAN_WORD_DATA_BYTE_0_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_0_SHIFT (24U) /*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK) + #define CAN_WORD_DATA_BYTE_4_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_4_SHIFT (24U) /*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK) + #define CAN_WORD_DATA_BYTE_8_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_8_SHIFT (24U) /*! DATA_BYTE_8 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_8(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK) + #define CAN_WORD_DATA_BYTE_12_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_12_SHIFT (24U) /*! DATA_BYTE_12 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_12(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK) + #define CAN_WORD_DATA_BYTE_16_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_16_SHIFT (24U) /*! DATA_BYTE_16 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_16(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK) + #define CAN_WORD_DATA_BYTE_20_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_20_SHIFT (24U) /*! DATA_BYTE_20 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_20(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK) + #define CAN_WORD_DATA_BYTE_24_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_24_SHIFT (24U) /*! DATA_BYTE_24 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_24(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK) + #define CAN_WORD_DATA_BYTE_28_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_28_SHIFT (24U) /*! DATA_BYTE_28 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_28(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK) + #define CAN_WORD_DATA_BYTE_32_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_32_SHIFT (24U) /*! DATA_BYTE_32 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_32(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK) + #define CAN_WORD_DATA_BYTE_36_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_36_SHIFT (24U) /*! DATA_BYTE_36 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_36(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK) + #define CAN_WORD_DATA_BYTE_40_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_40_SHIFT (24U) /*! DATA_BYTE_40 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_40(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK) + #define CAN_WORD_DATA_BYTE_44_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_44_SHIFT (24U) /*! DATA_BYTE_44 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_44(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK) + #define CAN_WORD_DATA_BYTE_48_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_48_SHIFT (24U) /*! DATA_BYTE_48 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_48(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK) + #define CAN_WORD_DATA_BYTE_52_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_52_SHIFT (24U) /*! DATA_BYTE_52 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_52(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK) + #define CAN_WORD_DATA_BYTE_56_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_56_SHIFT (24U) /*! DATA_BYTE_56 - Data byte 3 of Rx/Tx frame. */ #define CAN_WORD_DATA_BYTE_56(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK) + #define CAN_WORD_DATA_BYTE_60_MASK (0xFF000000U) #define CAN_WORD_DATA_BYTE_60_SHIFT (24U) /*! DATA_BYTE_60 - Data byte 3 of Rx/Tx frame. @@ -17437,21 +19741,25 @@ typedef struct { /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */ /*! @{ */ + #define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU) #define CAN_WORD0_DATA_BYTE_3_SHIFT (0U) /*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK) + #define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U) #define CAN_WORD0_DATA_BYTE_2_SHIFT (8U) /*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK) + #define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U) #define CAN_WORD0_DATA_BYTE_1_SHIFT (16U) /*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK) + #define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U) #define CAN_WORD0_DATA_BYTE_0_SHIFT (24U) /*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame. @@ -17464,21 +19772,25 @@ typedef struct { /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */ /*! @{ */ + #define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU) #define CAN_WORD1_DATA_BYTE_7_SHIFT (0U) /*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame. */ #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK) + #define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U) #define CAN_WORD1_DATA_BYTE_6_SHIFT (8U) /*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame. */ #define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK) + #define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U) #define CAN_WORD1_DATA_BYTE_5_SHIFT (16U) /*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame. */ #define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK) + #define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U) #define CAN_WORD1_DATA_BYTE_4_SHIFT (24U) /*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame. @@ -17491,6 +19803,7 @@ typedef struct { /*! @name RXIMR - Rx Individual Mask registers */ /*! @{ */ + #define CAN_RXIMR_MI_MASK (0xFFFFFFFFU) #define CAN_RXIMR_MI_SHIFT (0U) /*! MI - Individual Mask Bits @@ -17503,6 +19816,7 @@ typedef struct { /*! @name MECR - Memory Error Control register */ /*! @{ */ + #define CAN_MECR_NCEFAFRZ_MASK (0x80U) #define CAN_MECR_NCEFAFRZ_SHIFT (7U) /*! NCEFAFRZ - Non-Correctable Errors In FlexCAN Access Put Device In Freeze Mode @@ -17510,6 +19824,7 @@ typedef struct { * 0b1..Put FlexCAN in Freeze mode (see section "Freeze mode"). */ #define CAN_MECR_NCEFAFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_NCEFAFRZ_SHIFT)) & CAN_MECR_NCEFAFRZ_MASK) + #define CAN_MECR_ECCDIS_MASK (0x100U) #define CAN_MECR_ECCDIS_SHIFT (8U) /*! ECCDIS - Error Correction Disable @@ -17517,6 +19832,7 @@ typedef struct { * 0b1..Disable memory error correction. */ #define CAN_MECR_ECCDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECCDIS_SHIFT)) & CAN_MECR_ECCDIS_MASK) + #define CAN_MECR_RERRDIS_MASK (0x200U) #define CAN_MECR_RERRDIS_SHIFT (9U) /*! RERRDIS - Error Report Disable @@ -17524,6 +19840,7 @@ typedef struct { * 0b1..Disable updates of the error report registers. */ #define CAN_MECR_RERRDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_RERRDIS_SHIFT)) & CAN_MECR_RERRDIS_MASK) + #define CAN_MECR_EXTERRIE_MASK (0x2000U) #define CAN_MECR_EXTERRIE_SHIFT (13U) /*! EXTERRIE - Extended Error Injection Enable @@ -17531,6 +19848,7 @@ typedef struct { * 0b1..Error injection is applied to the 64-bit word. */ #define CAN_MECR_EXTERRIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_EXTERRIE_SHIFT)) & CAN_MECR_EXTERRIE_MASK) + #define CAN_MECR_FAERRIE_MASK (0x4000U) #define CAN_MECR_FAERRIE_SHIFT (14U) /*! FAERRIE - FlexCAN Access Error Injection Enable @@ -17538,6 +19856,7 @@ typedef struct { * 0b1..Injection is enabled. */ #define CAN_MECR_FAERRIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FAERRIE_SHIFT)) & CAN_MECR_FAERRIE_MASK) + #define CAN_MECR_HAERRIE_MASK (0x8000U) #define CAN_MECR_HAERRIE_SHIFT (15U) /*! HAERRIE - Host Access Error Injection Enable @@ -17545,6 +19864,7 @@ typedef struct { * 0b1..Injection is enabled. */ #define CAN_MECR_HAERRIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HAERRIE_SHIFT)) & CAN_MECR_HAERRIE_MASK) + #define CAN_MECR_CEI_MSK_MASK (0x10000U) #define CAN_MECR_CEI_MSK_SHIFT (16U) /*! CEI_MSK - Correctable Errors Interrupt Mask @@ -17552,6 +19872,7 @@ typedef struct { * 0b1..Interrupt is enabled. */ #define CAN_MECR_CEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_CEI_MSK_SHIFT)) & CAN_MECR_CEI_MSK_MASK) + #define CAN_MECR_FANCEI_MSK_MASK (0x40000U) #define CAN_MECR_FANCEI_MSK_SHIFT (18U) /*! FANCEI_MSK - FlexCAN Access With Non-Correctable Errors Interrupt Mask @@ -17559,6 +19880,7 @@ typedef struct { * 0b1..Interrupt is enabled. */ #define CAN_MECR_FANCEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FANCEI_MSK_SHIFT)) & CAN_MECR_FANCEI_MSK_MASK) + #define CAN_MECR_HANCEI_MSK_MASK (0x80000U) #define CAN_MECR_HANCEI_MSK_SHIFT (19U) /*! HANCEI_MSK - Host Access With Non-Correctable Errors Interrupt Mask @@ -17566,6 +19888,7 @@ typedef struct { * 0b1..Interrupt is enabled. */ #define CAN_MECR_HANCEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HANCEI_MSK_SHIFT)) & CAN_MECR_HANCEI_MSK_MASK) + #define CAN_MECR_ECRWRDIS_MASK (0x80000000U) #define CAN_MECR_ECRWRDIS_SHIFT (31U) /*! ECRWRDIS - Error Configuration Register Write Disable @@ -17577,11 +19900,13 @@ typedef struct { /*! @name ERRIAR - Error Injection Address register */ /*! @{ */ + #define CAN_ERRIAR_INJADDR_L_MASK (0x3U) #define CAN_ERRIAR_INJADDR_L_SHIFT (0U) /*! INJADDR_L - Error Injection Address Low */ #define CAN_ERRIAR_INJADDR_L(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_L_SHIFT)) & CAN_ERRIAR_INJADDR_L_MASK) + #define CAN_ERRIAR_INJADDR_H_MASK (0x3FFCU) #define CAN_ERRIAR_INJADDR_H_SHIFT (2U) /*! INJADDR_H - Error Injection Address High @@ -17591,6 +19916,7 @@ typedef struct { /*! @name ERRIDPR - Error Injection Data Pattern register */ /*! @{ */ + #define CAN_ERRIDPR_DFLIP_MASK (0xFFFFFFFFU) #define CAN_ERRIDPR_DFLIP_SHIFT (0U) /*! DFLIP - Data flip pattern @@ -17600,21 +19926,25 @@ typedef struct { /*! @name ERRIPPR - Error Injection Parity Pattern register */ /*! @{ */ + #define CAN_ERRIPPR_PFLIP0_MASK (0x1FU) #define CAN_ERRIPPR_PFLIP0_SHIFT (0U) /*! PFLIP0 - Parity Flip Pattern For Byte 0 (Least Significant) */ #define CAN_ERRIPPR_PFLIP0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP0_SHIFT)) & CAN_ERRIPPR_PFLIP0_MASK) + #define CAN_ERRIPPR_PFLIP1_MASK (0x1F00U) #define CAN_ERRIPPR_PFLIP1_SHIFT (8U) /*! PFLIP1 - Parity Flip Pattern For Byte 1 */ #define CAN_ERRIPPR_PFLIP1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP1_SHIFT)) & CAN_ERRIPPR_PFLIP1_MASK) + #define CAN_ERRIPPR_PFLIP2_MASK (0x1F0000U) #define CAN_ERRIPPR_PFLIP2_SHIFT (16U) /*! PFLIP2 - Parity Flip Pattern For Byte 2 */ #define CAN_ERRIPPR_PFLIP2(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP2_SHIFT)) & CAN_ERRIPPR_PFLIP2_MASK) + #define CAN_ERRIPPR_PFLIP3_MASK (0x1F000000U) #define CAN_ERRIPPR_PFLIP3_SHIFT (24U) /*! PFLIP3 - Parity Flip Pattern For Byte 3 (most significant) @@ -17624,16 +19954,19 @@ typedef struct { /*! @name RERRAR - Error Report Address register */ /*! @{ */ + #define CAN_RERRAR_ERRADDR_MASK (0x3FFFU) #define CAN_RERRAR_ERRADDR_SHIFT (0U) /*! ERRADDR - Address Where Error Detected */ #define CAN_RERRAR_ERRADDR(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_ERRADDR_SHIFT)) & CAN_RERRAR_ERRADDR_MASK) + #define CAN_RERRAR_SAID_MASK (0x70000U) #define CAN_RERRAR_SAID_SHIFT (16U) /*! SAID - SAID */ #define CAN_RERRAR_SAID(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_SAID_SHIFT)) & CAN_RERRAR_SAID_MASK) + #define CAN_RERRAR_NCE_MASK (0x1000000U) #define CAN_RERRAR_NCE_SHIFT (24U) /*! NCE - Non-Correctable Error @@ -17645,6 +19978,7 @@ typedef struct { /*! @name RERRDR - Error Report Data register */ /*! @{ */ + #define CAN_RERRDR_RDATA_MASK (0xFFFFFFFFU) #define CAN_RERRDR_RDATA_SHIFT (0U) /*! RDATA - Raw data word read from memory with error @@ -17654,11 +19988,13 @@ typedef struct { /*! @name RERRSYNR - Error Report Syndrome register */ /*! @{ */ + #define CAN_RERRSYNR_SYND0_MASK (0x1FU) #define CAN_RERRSYNR_SYND0_SHIFT (0U) /*! SYND0 - Error Syndrome For Byte 0 (least significant) */ #define CAN_RERRSYNR_SYND0(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND0_SHIFT)) & CAN_RERRSYNR_SYND0_MASK) + #define CAN_RERRSYNR_BE0_MASK (0x80U) #define CAN_RERRSYNR_BE0_SHIFT (7U) /*! BE0 - Byte Enabled For Byte 0 (least significant) @@ -17666,11 +20002,13 @@ typedef struct { * 0b1..The byte was read. */ #define CAN_RERRSYNR_BE0(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE0_SHIFT)) & CAN_RERRSYNR_BE0_MASK) + #define CAN_RERRSYNR_SYND1_MASK (0x1F00U) #define CAN_RERRSYNR_SYND1_SHIFT (8U) /*! SYND1 - Error Syndrome for Byte 1 */ #define CAN_RERRSYNR_SYND1(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND1_SHIFT)) & CAN_RERRSYNR_SYND1_MASK) + #define CAN_RERRSYNR_BE1_MASK (0x8000U) #define CAN_RERRSYNR_BE1_SHIFT (15U) /*! BE1 - Byte Enabled For Byte 1 @@ -17678,11 +20016,13 @@ typedef struct { * 0b1..The byte was read. */ #define CAN_RERRSYNR_BE1(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE1_SHIFT)) & CAN_RERRSYNR_BE1_MASK) + #define CAN_RERRSYNR_SYND2_MASK (0x1F0000U) #define CAN_RERRSYNR_SYND2_SHIFT (16U) /*! SYND2 - Error Syndrome For Byte 2 */ #define CAN_RERRSYNR_SYND2(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND2_SHIFT)) & CAN_RERRSYNR_SYND2_MASK) + #define CAN_RERRSYNR_BE2_MASK (0x800000U) #define CAN_RERRSYNR_BE2_SHIFT (23U) /*! BE2 - Byte Enabled For Byte 2 @@ -17690,11 +20030,13 @@ typedef struct { * 0b1..The byte was read. */ #define CAN_RERRSYNR_BE2(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE2_SHIFT)) & CAN_RERRSYNR_BE2_MASK) + #define CAN_RERRSYNR_SYND3_MASK (0x1F000000U) #define CAN_RERRSYNR_SYND3_SHIFT (24U) /*! SYND3 - Error Syndrome For Byte 3 (most significant) */ #define CAN_RERRSYNR_SYND3(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND3_SHIFT)) & CAN_RERRSYNR_SYND3_MASK) + #define CAN_RERRSYNR_BE3_MASK (0x80000000U) #define CAN_RERRSYNR_BE3_SHIFT (31U) /*! BE3 - Byte Enabled For Byte 3 (most significant) @@ -17706,6 +20048,7 @@ typedef struct { /*! @name ERRSR - Error Status register */ /*! @{ */ + #define CAN_ERRSR_CEIOF_MASK (0x1U) #define CAN_ERRSR_CEIOF_SHIFT (0U) /*! CEIOF - Correctable Error Interrupt Overrun Flag @@ -17713,6 +20056,7 @@ typedef struct { * 0b1..Overrun on correctable errors */ #define CAN_ERRSR_CEIOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIOF_SHIFT)) & CAN_ERRSR_CEIOF_MASK) + #define CAN_ERRSR_FANCEIOF_MASK (0x4U) #define CAN_ERRSR_FANCEIOF_SHIFT (2U) /*! FANCEIOF - FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag @@ -17720,6 +20064,7 @@ typedef struct { * 0b1..Overrun on non-correctable errors in FlexCAN access */ #define CAN_ERRSR_FANCEIOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIOF_SHIFT)) & CAN_ERRSR_FANCEIOF_MASK) + #define CAN_ERRSR_HANCEIOF_MASK (0x8U) #define CAN_ERRSR_HANCEIOF_SHIFT (3U) /*! HANCEIOF - Host Access With Non-Correctable Error Interrupt Overrun Flag @@ -17727,6 +20072,7 @@ typedef struct { * 0b1..Overrun on non-correctable errors in host access */ #define CAN_ERRSR_HANCEIOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIOF_SHIFT)) & CAN_ERRSR_HANCEIOF_MASK) + #define CAN_ERRSR_CEIF_MASK (0x10000U) #define CAN_ERRSR_CEIF_SHIFT (16U) /*! CEIF - Correctable Error Interrupt Flag @@ -17734,6 +20080,7 @@ typedef struct { * 0b1..A correctable error was detected. */ #define CAN_ERRSR_CEIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIF_SHIFT)) & CAN_ERRSR_CEIF_MASK) + #define CAN_ERRSR_FANCEIF_MASK (0x40000U) #define CAN_ERRSR_FANCEIF_SHIFT (18U) /*! FANCEIF - FlexCAN Access With Non-Correctable Error Interrupt Flag @@ -17741,6 +20088,7 @@ typedef struct { * 0b1..A non-correctable error was detected in a FlexCAN access. */ #define CAN_ERRSR_FANCEIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIF_SHIFT)) & CAN_ERRSR_FANCEIF_MASK) + #define CAN_ERRSR_HANCEIF_MASK (0x80000U) #define CAN_ERRSR_HANCEIF_SHIFT (19U) /*! HANCEIF - Host Access With Non-Correctable Error Interrupt Flag @@ -17752,16 +20100,19 @@ typedef struct { /*! @name FDCTRL - CAN FD Control register */ /*! @{ */ + #define CAN_FDCTRL_TDCVAL_MASK (0x3FU) #define CAN_FDCTRL_TDCVAL_SHIFT (0U) /*! TDCVAL - Transceiver Delay Compensation Value */ #define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK) + #define CAN_FDCTRL_TDCOFF_MASK (0x1F00U) #define CAN_FDCTRL_TDCOFF_SHIFT (8U) /*! TDCOFF - Transceiver Delay Compensation Offset */ #define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK) + #define CAN_FDCTRL_TDCFAIL_MASK (0x4000U) #define CAN_FDCTRL_TDCFAIL_SHIFT (14U) /*! TDCFAIL - Transceiver Delay Compensation Fail @@ -17769,6 +20120,7 @@ typedef struct { * 0b1..Measured loop delay is out of range. */ #define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK) + #define CAN_FDCTRL_TDCEN_MASK (0x8000U) #define CAN_FDCTRL_TDCEN_SHIFT (15U) /*! TDCEN - Transceiver Delay Compensation Enable @@ -17776,6 +20128,7 @@ typedef struct { * 0b1..TDC is enabled */ #define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK) + #define CAN_FDCTRL_MBDSR0_MASK (0x30000U) #define CAN_FDCTRL_MBDSR0_SHIFT (16U) /*! MBDSR0 - Message Buffer Data Size for Region 0 @@ -17785,6 +20138,7 @@ typedef struct { * 0b11..Selects 64 bytes per message buffer. */ #define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK) + #define CAN_FDCTRL_MBDSR1_MASK (0x180000U) #define CAN_FDCTRL_MBDSR1_SHIFT (19U) /*! MBDSR1 - Message Buffer Data Size for Region 1 @@ -17794,6 +20148,7 @@ typedef struct { * 0b11..Selects 64 bytes per message buffer. */ #define CAN_FDCTRL_MBDSR1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK) + #define CAN_FDCTRL_FDRATE_MASK (0x80000000U) #define CAN_FDCTRL_FDRATE_SHIFT (31U) /*! FDRATE - Bit Rate Switch Enable @@ -17805,26 +20160,31 @@ typedef struct { /*! @name FDCBT - CAN FD Bit Timing register */ /*! @{ */ + #define CAN_FDCBT_FPSEG2_MASK (0x7U) #define CAN_FDCBT_FPSEG2_SHIFT (0U) /*! FPSEG2 - Fast Phase Segment 2 */ #define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK) + #define CAN_FDCBT_FPSEG1_MASK (0xE0U) #define CAN_FDCBT_FPSEG1_SHIFT (5U) /*! FPSEG1 - Fast Phase Segment 1 */ #define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK) + #define CAN_FDCBT_FPROPSEG_MASK (0x7C00U) #define CAN_FDCBT_FPROPSEG_SHIFT (10U) /*! FPROPSEG - Fast Propagation Segment */ #define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK) + #define CAN_FDCBT_FRJW_MASK (0x70000U) #define CAN_FDCBT_FRJW_SHIFT (16U) /*! FRJW - Fast Resync Jump Width */ #define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK) + #define CAN_FDCBT_FPRESDIV_MASK (0x3FF00000U) #define CAN_FDCBT_FPRESDIV_SHIFT (20U) /*! FPRESDIV - Fast Prescaler Division Factor @@ -17834,11 +20194,13 @@ typedef struct { /*! @name FDCRC - CAN FD CRC register */ /*! @{ */ + #define CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU) #define CAN_FDCRC_FD_TXCRC_SHIFT (0U) /*! FD_TXCRC - Extended Transmitted CRC value */ #define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK) + #define CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U) #define CAN_FDCRC_FD_MBCRC_SHIFT (24U) /*! FD_MBCRC - CRC Mailbox Number for FD_TXCRC @@ -17882,6 +20244,69 @@ typedef struct { */ /* end of group CAN_Peripheral_Access_Layer */ +/* ---------------------------------------------------------------------------- + -- CAN_WRAPPER Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_WRAPPER_Peripheral_Access_Layer CAN_WRAPPER Peripheral Access Layer + * @{ + */ + +/** CAN_WRAPPER - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[2528]; + __IO uint32_t GFWR; /**< Glitch Filter Width Register, offset: 0x9E0 */ +} CAN_WRAPPER_Type; + +/* ---------------------------------------------------------------------------- + -- CAN_WRAPPER Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_WRAPPER_Register_Masks CAN_WRAPPER Register Masks + * @{ + */ + +/*! @name GFWR - Glitch Filter Width Register */ +/*! @{ */ + +#define CAN_WRAPPER_GFWR_GFWR_MASK (0xFFU) +#define CAN_WRAPPER_GFWR_GFWR_SHIFT (0U) +/*! GFWR - Glitch Filter Width + */ +#define CAN_WRAPPER_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_WRAPPER_GFWR_GFWR_SHIFT)) & CAN_WRAPPER_GFWR_GFWR_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CAN_WRAPPER_Register_Masks */ + + +/* CAN_WRAPPER - Peripheral instance base addresses */ +/** Peripheral CAN1_WRAPPER base address */ +#define CAN1_WRAPPER_BASE (0x400C4000u) +/** Peripheral CAN1_WRAPPER base pointer */ +#define CAN1_WRAPPER ((CAN_WRAPPER_Type *)CAN1_WRAPPER_BASE) +/** Peripheral CAN2_WRAPPER base address */ +#define CAN2_WRAPPER_BASE (0x400C8000u) +/** Peripheral CAN2_WRAPPER base pointer */ +#define CAN2_WRAPPER ((CAN_WRAPPER_Type *)CAN2_WRAPPER_BASE) +/** Peripheral CAN3_WRAPPER base address */ +#define CAN3_WRAPPER_BASE (0x40C3C000u) +/** Peripheral CAN3_WRAPPER base pointer */ +#define CAN3_WRAPPER ((CAN_WRAPPER_Type *)CAN3_WRAPPER_BASE) +/** Array initializer of CAN_WRAPPER peripheral base addresses */ +#define CAN_WRAPPER_BASE_ADDRS { 0u, CAN1_WRAPPER_BASE, CAN2_WRAPPER_BASE, CAN3_WRAPPER_BASE } +/** Array initializer of CAN_WRAPPER peripheral base pointers */ +#define CAN_WRAPPER_BASE_PTRS { (CAN_WRAPPER_Type *)0u, CAN1_WRAPPER, CAN2_WRAPPER, CAN3_WRAPPER } + +/*! + * @} + */ /* end of group CAN_WRAPPER_Peripheral_Access_Layer */ + + /* ---------------------------------------------------------------------------- -- CCM Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -17898,9 +20323,7 @@ typedef struct { __IO uint32_t CONTROL_SET; /**< Clock root control, array offset: 0x4, array step: 0x80 */ __IO uint32_t CONTROL_CLR; /**< Clock root control, array offset: 0x8, array step: 0x80 */ __IO uint32_t CONTROL_TOG; /**< Clock root control, array offset: 0xC, array step: 0x80 */ - __I uint32_t OPTIONS0; /**< Clock root low power status, array offset: 0x10, array step: 0x80 */ - __I uint32_t OPTIONS1; /**< Clock root low power status, array offset: 0x14, array step: 0x80 */ - uint8_t RESERVED_0[8]; + uint8_t RESERVED_0[16]; __I uint32_t STATUS0; /**< Clock root working status, array offset: 0x20, array step: 0x80 */ __I uint32_t STATUS1; /**< Clock root low power status, array offset: 0x24, array step: 0x80 */ uint8_t RESERVED_1[4]; @@ -17917,19 +20340,16 @@ typedef struct { __IO uint32_t CONTROL_SET; /**< Clock group control, array offset: 0x4004, array step: 0x80 */ __IO uint32_t CONTROL_CLR; /**< Clock group control, array offset: 0x4008, array step: 0x80 */ __IO uint32_t CONTROL_TOG; /**< Clock group control, array offset: 0x400C, array step: 0x80 */ - __IO uint32_t CONTROL_EXTEND; /**< Clock group control extend, array offset: 0x4010, array step: 0x80 */ - __IO uint32_t CONTROL_EXTEND_SET; /**< Clock group control extend, array offset: 0x4014, array step: 0x80 */ - __IO uint32_t CONTROL_EXTEND_CLR; /**< Clock group control extend, array offset: 0x4018, array step: 0x80 */ - __IO uint32_t CONTROL_EXTEND_TOG; /**< Clock group control extend, array offset: 0x401C, array step: 0x80 */ + uint8_t RESERVED_0[16]; __IO uint32_t STATUS0; /**< Clock group working status, array offset: 0x4020, array step: 0x80 */ - __IO uint32_t STATUS1; /**< Clock group low power/extend status, array offset: 0x4024, array step: 0x80 */ - uint8_t RESERVED_0[4]; + __I uint32_t STATUS1; /**< Clock group low power/extend status, array offset: 0x4024, array step: 0x80 */ + uint8_t RESERVED_1[4]; __I uint32_t CONFIG; /**< Clock group configuration, array offset: 0x402C, array step: 0x80 */ __IO uint32_t AUTHEN; /**< Clock group access control, array offset: 0x4030, array step: 0x80 */ __IO uint32_t AUTHEN_SET; /**< Clock group access control, array offset: 0x4034, array step: 0x80 */ __IO uint32_t AUTHEN_CLR; /**< Clock group access control, array offset: 0x4038, array step: 0x80 */ __IO uint32_t AUTHEN_TOG; /**< Clock group access control, array offset: 0x403C, array step: 0x80 */ - uint8_t RESERVED_1[64]; + __IO uint32_t SETPOINT[16]; /**< Setpoint setting, array offset: 0x4040, array step: index*0x80, index2*0x4 */ } CLOCK_GROUP[2]; uint8_t RESERVED_1[1792]; struct { /* offset: 0x4800, array step: 0x20 */ @@ -17942,22 +20362,68 @@ typedef struct { __IO uint32_t AUTHEN_CLR; /**< GPR access control, array offset: 0x4818, array step: 0x20 */ __IO uint32_t AUTHEN_TOG; /**< GPR access control, array offset: 0x481C, array step: 0x20 */ } GPR_SHARED[8]; - uint8_t RESERVED_2[768]; - struct { /* offset: 0x4C00, array step: 0x20 */ - __IO uint32_t GPR_PRIVATE; /**< General puspose register, array offset: 0x4C00, array step: 0x20 */ - __IO uint32_t SET; /**< General puspose register, array offset: 0x4C04, array step: 0x20 */ - __IO uint32_t CLR; /**< General puspose register, array offset: 0x4C08, array step: 0x20 */ - __IO uint32_t TOG; /**< General puspose register, array offset: 0x4C0C, array step: 0x20 */ - __IO uint32_t AUTHEN; /**< GPR access control, array offset: 0x4C10, array step: 0x20 */ - __IO uint32_t AUTHEN_SET; /**< GPR access control, array offset: 0x4C14, array step: 0x20 */ - __IO uint32_t AUTHEN_CLR; /**< GPR access control, array offset: 0x4C18, array step: 0x20 */ - __IO uint32_t AUTHEN_TOG; /**< GPR access control, array offset: 0x4C1C, array step: 0x20 */ - } GPR_PRIVATE[8]; + uint8_t RESERVED_2[800]; + __IO uint32_t GPR_PRIVATE1; /**< General Purpose Register, offset: 0x4C20 */ + __IO uint32_t GPR_PRIVATE1_SET; /**< General Purpose Register, offset: 0x4C24 */ + __IO uint32_t GPR_PRIVATE1_CLR; /**< General Purpose Register, offset: 0x4C28 */ + __IO uint32_t GPR_PRIVATE1_TOG; /**< General Purpose Register, offset: 0x4C2C */ + __IO uint32_t GPR_PRIVATE1_AUTHEN; /**< GPR access control, offset: 0x4C30 */ + __IO uint32_t GPR_PRIVATE1_AUTHEN_SET; /**< GPR access control, offset: 0x4C34 */ + __IO uint32_t GPR_PRIVATE1_AUTHEN_CLR; /**< GPR access control, offset: 0x4C38 */ + __IO uint32_t GPR_PRIVATE1_AUTHEN_TOG; /**< GPR access control, offset: 0x4C3C */ + __IO uint32_t GPR_PRIVATE2; /**< General Purpose Register, offset: 0x4C40 */ + __IO uint32_t GPR_PRIVATE2_SET; /**< General Purpose Register, offset: 0x4C44 */ + __IO uint32_t GPR_PRIVATE2_CLR; /**< General Purpose Register, offset: 0x4C48 */ + __IO uint32_t GPR_PRIVATE2_TOG; /**< General Purpose Register, offset: 0x4C4C */ + __IO uint32_t GPR_PRIVATE2_AUTHEN; /**< GPR access control, offset: 0x4C50 */ + __IO uint32_t GPR_PRIVATE2_AUTHEN_SET; /**< GPR access control, offset: 0x4C54 */ + __IO uint32_t GPR_PRIVATE2_AUTHEN_CLR; /**< GPR access control, offset: 0x4C58 */ + __IO uint32_t GPR_PRIVATE2_AUTHEN_TOG; /**< GPR access control, offset: 0x4C5C */ + __IO uint32_t GPR_PRIVATE3; /**< General Purpose Register, offset: 0x4C60 */ + __IO uint32_t GPR_PRIVATE3_SET; /**< General Purpose Register, offset: 0x4C64 */ + __IO uint32_t GPR_PRIVATE3_CLR; /**< General Purpose Register, offset: 0x4C68 */ + __IO uint32_t GPR_PRIVATE3_TOG; /**< General Purpose Register, offset: 0x4C6C */ + __IO uint32_t GPR_PRIVATE3_AUTHEN; /**< GPR access control, offset: 0x4C70 */ + __IO uint32_t GPR_PRIVATE3_AUTHEN_SET; /**< GPR access control, offset: 0x4C74 */ + __IO uint32_t GPR_PRIVATE3_AUTHEN_CLR; /**< GPR access control, offset: 0x4C78 */ + __IO uint32_t GPR_PRIVATE3_AUTHEN_TOG; /**< GPR access control, offset: 0x4C7C */ + __IO uint32_t GPR_PRIVATE4; /**< General Purpose Register, offset: 0x4C80 */ + __IO uint32_t GPR_PRIVATE4_SET; /**< General Purpose Register, offset: 0x4C84 */ + __IO uint32_t GPR_PRIVATE4_CLR; /**< General Purpose Register, offset: 0x4C88 */ + __IO uint32_t GPR_PRIVATE4_TOG; /**< General Purpose Register, offset: 0x4C8C */ + __IO uint32_t GPR_PRIVATE4_AUTHEN; /**< GPR access control, offset: 0x4C90 */ + __IO uint32_t GPR_PRIVATE4_AUTHEN_SET; /**< GPR access control, offset: 0x4C94 */ + __IO uint32_t GPR_PRIVATE4_AUTHEN_CLR; /**< GPR access control, offset: 0x4C98 */ + __IO uint32_t GPR_PRIVATE4_AUTHEN_TOG; /**< GPR access control, offset: 0x4C9C */ + __IO uint32_t GPR_PRIVATE5; /**< General Purpose Register, offset: 0x4CA0 */ + __IO uint32_t GPR_PRIVATE5_SET; /**< General Purpose Register, offset: 0x4CA4 */ + __IO uint32_t GPR_PRIVATE5_CLR; /**< General Purpose Register, offset: 0x4CA8 */ + __IO uint32_t GPR_PRIVATE5_TOG; /**< General Purpose Register, offset: 0x4CAC */ + __IO uint32_t GPR_PRIVATE5_AUTHEN; /**< GPR access control, offset: 0x4CB0 */ + __IO uint32_t GPR_PRIVATE5_AUTHEN_SET; /**< GPR access control, offset: 0x4CB4 */ + __IO uint32_t GPR_PRIVATE5_AUTHEN_CLR; /**< GPR access control, offset: 0x4CB8 */ + __IO uint32_t GPR_PRIVATE5_AUTHEN_TOG; /**< GPR access control, offset: 0x4CBC */ + __IO uint32_t GPR_PRIVATE6; /**< General Purpose Register, offset: 0x4CC0 */ + __IO uint32_t GPR_PRIVATE6_SET; /**< General Purpose Register, offset: 0x4CC4 */ + __IO uint32_t GPR_PRIVATE6_CLR; /**< General Purpose Register, offset: 0x4CC8 */ + __IO uint32_t GPR_PRIVATE6_TOG; /**< General Purpose Register, offset: 0x4CCC */ + __IO uint32_t GPR_PRIVATE6_AUTHEN; /**< GPR access control, offset: 0x4CD0 */ + __IO uint32_t GPR_PRIVATE6_AUTHEN_SET; /**< GPR access control, offset: 0x4CD4 */ + __IO uint32_t GPR_PRIVATE6_AUTHEN_CLR; /**< GPR access control, offset: 0x4CD8 */ + __IO uint32_t GPR_PRIVATE6_AUTHEN_TOG; /**< GPR access control, offset: 0x4CDC */ + __IO uint32_t GPR_PRIVATE7; /**< General Purpose Register, offset: 0x4CE0 */ + __IO uint32_t GPR_PRIVATE7_SET; /**< General Purpose Register, offset: 0x4CE4 */ + __IO uint32_t GPR_PRIVATE7_CLR; /**< General Purpose Register, offset: 0x4CE8 */ + __IO uint32_t GPR_PRIVATE7_TOG; /**< General Purpose Register, offset: 0x4CEC */ + __IO uint32_t GPR_PRIVATE7_AUTHEN; /**< GPR access control, offset: 0x4CF0 */ + __IO uint32_t GPR_PRIVATE7_AUTHEN_SET; /**< GPR access control, offset: 0x4CF4 */ + __IO uint32_t GPR_PRIVATE7_AUTHEN_CLR; /**< GPR access control, offset: 0x4CF8 */ + __IO uint32_t GPR_PRIVATE7_AUTHEN_TOG; /**< GPR access control, offset: 0x4CFC */ uint8_t RESERVED_3[768]; struct { /* offset: 0x5000, array step: 0x20 */ __IO uint32_t DIRECT; /**< Clock source direct control, array offset: 0x5000, array step: 0x20 */ __IO uint32_t DOMAINr; /**< Clock source domain control, array offset: 0x5004, array step: 0x20 */ - __IO uint32_t SETPOINT; /**< Clock source setpoint setting, array offset: 0x5008, array step: 0x20 */ + __IO uint32_t SETPOINT; /**< Clock source Setpoint setting, array offset: 0x5008, array step: 0x20 */ uint8_t RESERVED_0[4]; __I uint32_t STATUS0; /**< Clock source working status, array offset: 0x5010, array step: 0x20 */ __I uint32_t STATUS1; /**< Clock source low power status, array offset: 0x5014, array step: 0x20 */ @@ -17968,7 +20434,7 @@ typedef struct { struct { /* offset: 0x6000, array step: 0x20 */ __IO uint32_t DIRECT; /**< LPCG direct control, array offset: 0x6000, array step: 0x20 */ __IO uint32_t DOMAINr; /**< LPCG domain control, array offset: 0x6004, array step: 0x20 */ - __IO uint32_t SETPOINT; /**< LPCG setpoint setting, array offset: 0x6008, array step: 0x20 */ + __IO uint32_t SETPOINT; /**< LPCG Setpoint setting, array offset: 0x6008, array step: 0x20 */ uint8_t RESERVED_0[4]; __I uint32_t STATUS0; /**< LPCG working status, array offset: 0x6010, array step: 0x20 */ __I uint32_t STATUS1; /**< LPCG low power status, array offset: 0x6014, array step: 0x20 */ @@ -17988,31 +20454,24 @@ typedef struct { /*! @name CLOCK_ROOT_CONTROL - Clock root control */ /*! @{ */ + #define CCM_CLOCK_ROOT_CONTROL_DIV_MASK (0xFFU) #define CCM_CLOCK_ROOT_CONTROL_DIV_SHIFT (0U) /*! DIV - Clock divider */ #define CCM_CLOCK_ROOT_CONTROL_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_DIV_MASK) + #define CCM_CLOCK_ROOT_CONTROL_MUX_MASK (0x700U) #define CCM_CLOCK_ROOT_CONTROL_MUX_SHIFT (8U) /*! MUX - Clock multiplexer */ #define CCM_CLOCK_ROOT_CONTROL_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_MUX_MASK) -#define CCM_CLOCK_ROOT_CONTROL_MFD_MASK (0xF0000U) -#define CCM_CLOCK_ROOT_CONTROL_MFD_SHIFT (16U) -/*! MFD - Denominator - */ -#define CCM_CLOCK_ROOT_CONTROL_MFD(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_MFD_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_MFD_MASK) -#define CCM_CLOCK_ROOT_CONTROL_MFN_MASK (0xF00000U) -#define CCM_CLOCK_ROOT_CONTROL_MFN_SHIFT (20U) -/*! MFN - Nominator - */ -#define CCM_CLOCK_ROOT_CONTROL_MFN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_MFN_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_MFN_MASK) + #define CCM_CLOCK_ROOT_CONTROL_OFF_MASK (0x1000000U) #define CCM_CLOCK_ROOT_CONTROL_OFF_SHIFT (24U) /*! OFF - OFF - * 0b0..Clock is running. - * 0b1..Turn off clock. + * 0b0..Turn on clock + * 0b1..Turn off clock */ #define CCM_CLOCK_ROOT_CONTROL_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_OFF_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_OFF_MASK) /*! @} */ @@ -18022,26 +20481,19 @@ typedef struct { /*! @name CLOCK_ROOT_CONTROL_SET - Clock root control */ /*! @{ */ + #define CCM_CLOCK_ROOT_CONTROL_SET_DIV_MASK (0xFFU) #define CCM_CLOCK_ROOT_CONTROL_SET_DIV_SHIFT (0U) /*! DIV - Clock divider */ #define CCM_CLOCK_ROOT_CONTROL_SET_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_SET_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_SET_DIV_MASK) + #define CCM_CLOCK_ROOT_CONTROL_SET_MUX_MASK (0x700U) #define CCM_CLOCK_ROOT_CONTROL_SET_MUX_SHIFT (8U) /*! MUX - Clock multiplexer */ #define CCM_CLOCK_ROOT_CONTROL_SET_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_SET_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_SET_MUX_MASK) -#define CCM_CLOCK_ROOT_CONTROL_SET_MFD_MASK (0xF0000U) -#define CCM_CLOCK_ROOT_CONTROL_SET_MFD_SHIFT (16U) -/*! MFD - Denominator - */ -#define CCM_CLOCK_ROOT_CONTROL_SET_MFD(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_SET_MFD_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_SET_MFD_MASK) -#define CCM_CLOCK_ROOT_CONTROL_SET_MFN_MASK (0xF00000U) -#define CCM_CLOCK_ROOT_CONTROL_SET_MFN_SHIFT (20U) -/*! MFN - Nominator - */ -#define CCM_CLOCK_ROOT_CONTROL_SET_MFN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_SET_MFN_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_SET_MFN_MASK) + #define CCM_CLOCK_ROOT_CONTROL_SET_OFF_MASK (0x1000000U) #define CCM_CLOCK_ROOT_CONTROL_SET_OFF_SHIFT (24U) /*! OFF - OFF @@ -18054,26 +20506,19 @@ typedef struct { /*! @name CLOCK_ROOT_CONTROL_CLR - Clock root control */ /*! @{ */ + #define CCM_CLOCK_ROOT_CONTROL_CLR_DIV_MASK (0xFFU) #define CCM_CLOCK_ROOT_CONTROL_CLR_DIV_SHIFT (0U) /*! DIV - Clock divider */ #define CCM_CLOCK_ROOT_CONTROL_CLR_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_CLR_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_CLR_DIV_MASK) + #define CCM_CLOCK_ROOT_CONTROL_CLR_MUX_MASK (0x700U) #define CCM_CLOCK_ROOT_CONTROL_CLR_MUX_SHIFT (8U) /*! MUX - Clock multiplexer */ #define CCM_CLOCK_ROOT_CONTROL_CLR_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_CLR_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_CLR_MUX_MASK) -#define CCM_CLOCK_ROOT_CONTROL_CLR_MFD_MASK (0xF0000U) -#define CCM_CLOCK_ROOT_CONTROL_CLR_MFD_SHIFT (16U) -/*! MFD - Denominator - */ -#define CCM_CLOCK_ROOT_CONTROL_CLR_MFD(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_CLR_MFD_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_CLR_MFD_MASK) -#define CCM_CLOCK_ROOT_CONTROL_CLR_MFN_MASK (0xF00000U) -#define CCM_CLOCK_ROOT_CONTROL_CLR_MFN_SHIFT (20U) -/*! MFN - Nominator - */ -#define CCM_CLOCK_ROOT_CONTROL_CLR_MFN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_CLR_MFN_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_CLR_MFN_MASK) + #define CCM_CLOCK_ROOT_CONTROL_CLR_OFF_MASK (0x1000000U) #define CCM_CLOCK_ROOT_CONTROL_CLR_OFF_SHIFT (24U) /*! OFF - OFF @@ -18086,26 +20531,19 @@ typedef struct { /*! @name CLOCK_ROOT_CONTROL_TOG - Clock root control */ /*! @{ */ + #define CCM_CLOCK_ROOT_CONTROL_TOG_DIV_MASK (0xFFU) #define CCM_CLOCK_ROOT_CONTROL_TOG_DIV_SHIFT (0U) /*! DIV - Clock divider */ #define CCM_CLOCK_ROOT_CONTROL_TOG_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_TOG_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_TOG_DIV_MASK) + #define CCM_CLOCK_ROOT_CONTROL_TOG_MUX_MASK (0x700U) #define CCM_CLOCK_ROOT_CONTROL_TOG_MUX_SHIFT (8U) /*! MUX - Clock multiplexer */ #define CCM_CLOCK_ROOT_CONTROL_TOG_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_TOG_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_TOG_MUX_MASK) -#define CCM_CLOCK_ROOT_CONTROL_TOG_MFD_MASK (0xF0000U) -#define CCM_CLOCK_ROOT_CONTROL_TOG_MFD_SHIFT (16U) -/*! MFD - Denominator - */ -#define CCM_CLOCK_ROOT_CONTROL_TOG_MFD(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_TOG_MFD_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_TOG_MFD_MASK) -#define CCM_CLOCK_ROOT_CONTROL_TOG_MFN_MASK (0xF00000U) -#define CCM_CLOCK_ROOT_CONTROL_TOG_MFN_SHIFT (20U) -/*! MFN - Nominator - */ -#define CCM_CLOCK_ROOT_CONTROL_TOG_MFN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_TOG_MFN_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_TOG_MFN_MASK) + #define CCM_CLOCK_ROOT_CONTROL_TOG_OFF_MASK (0x1000000U) #define CCM_CLOCK_ROOT_CONTROL_TOG_OFF_SHIFT (24U) /*! OFF - OFF @@ -18116,288 +20554,66 @@ typedef struct { /* The count of CCM_CLOCK_ROOT_CONTROL_TOG */ #define CCM_CLOCK_ROOT_CONTROL_TOG_COUNT (79U) -/*! @name CLOCK_ROOT_OPTIONS0 - Clock root low power status */ -/*! @{ */ -#define CCM_CLOCK_ROOT_OPTIONS0_OPTION0_MASK (0x1FU) -#define CCM_CLOCK_ROOT_OPTIONS0_OPTION0_SHIFT (0U) -/*! OPTION0 - Clock input option 0 - * 0b00000..OSC_RC_16M - * 0b00001..OSC_RC_48M - * 0b00010..OSC_RC_48M_DIV2 - * 0b00011..OSC_RC_400M - * 0b00101..OSC_24M_OUT - * 0b00111..PLL_ARM_OUT - * 0b01001..PLL_528_OUT - * 0b01010..PLL_528_PFD0 - * 0b01011..PLL_528_PFD1 - * 0b01100..PLL_528_PFD2 - * 0b01101..PLL_528_PFD3 - * 0b01111..PLL_480_OUT - * 0b10000..PLL_480_DIV2 - * 0b10001..PLL_480_PFD0 - * 0b10010..PLL_480_PFD1 - * 0b10011..PLL_480_PFD2 - * 0b10100..PLL_480_PFD3 - * 0b10110..PLL_1G_OUT - * 0b10111..PLL_1G_DIV2 - * 0b11000..PLL_1G_DIV5 - * 0b11010..PLL_AUDIO_OUT - * 0b11100..PLL_VIDEO_OUT - */ -#define CCM_CLOCK_ROOT_OPTIONS0_OPTION0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_OPTIONS0_OPTION0_SHIFT)) & CCM_CLOCK_ROOT_OPTIONS0_OPTION0_MASK) -#define CCM_CLOCK_ROOT_OPTIONS0_OPTION1_MASK (0x1F00U) -#define CCM_CLOCK_ROOT_OPTIONS0_OPTION1_SHIFT (8U) -/*! OPTION1 - Clock input option 1 - * 0b00000..OSC_RC_16M - * 0b00001..OSC_RC_48M - * 0b00010..OSC_RC_48M_DIV2 - * 0b00011..OSC_RC_400M - * 0b00101..OSC_24M_OUT - * 0b00111..PLL_ARM_OUT - * 0b01001..PLL_528_OUT - * 0b01010..PLL_528_PFD0 - * 0b01011..PLL_528_PFD1 - * 0b01100..PLL_528_PFD2 - * 0b01101..PLL_528_PFD3 - * 0b01111..PLL_480_OUT - * 0b10000..PLL_480_DIV2 - * 0b10001..PLL_480_PFD0 - * 0b10010..PLL_480_PFD1 - * 0b10011..PLL_480_PFD2 - * 0b10100..PLL_480_PFD3 - * 0b10110..PLL_1G_OUT - * 0b10111..PLL_1G_DIV2 - * 0b11000..PLL_1G_DIV5 - * 0b11010..PLL_AUDIO_OUT - * 0b11100..PLL_VIDEO_OUT - */ -#define CCM_CLOCK_ROOT_OPTIONS0_OPTION1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_OPTIONS0_OPTION1_SHIFT)) & CCM_CLOCK_ROOT_OPTIONS0_OPTION1_MASK) -#define CCM_CLOCK_ROOT_OPTIONS0_OPTION2_MASK (0x1F0000U) -#define CCM_CLOCK_ROOT_OPTIONS0_OPTION2_SHIFT (16U) -/*! OPTION2 - Clock input option2 - * 0b00000..OSC_RC_16M - * 0b00001..OSC_RC_48M - * 0b00010..OSC_RC_48M_DIV2 - * 0b00011..OSC_RC_400M - * 0b00101..OSC_24M_OUT - * 0b00111..PLL_ARM_OUT - * 0b01001..PLL_528_OUT - * 0b01010..PLL_528_PFD0 - * 0b01011..PLL_528_PFD1 - * 0b01100..PLL_528_PFD2 - * 0b01101..PLL_528_PFD3 - * 0b01111..PLL_480_OUT - * 0b10000..PLL_480_DIV2 - * 0b10001..PLL_480_PFD0 - * 0b10010..PLL_480_PFD1 - * 0b10011..PLL_480_PFD2 - * 0b10100..PLL_480_PFD3 - * 0b10110..PLL_1G_OUT - * 0b10111..PLL_1G_DIV2 - * 0b11000..PLL_1G_DIV5 - * 0b11010..PLL_AUDIO_OUT - * 0b11100..PLL_VIDEO_OUT - */ -#define CCM_CLOCK_ROOT_OPTIONS0_OPTION2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_OPTIONS0_OPTION2_SHIFT)) & CCM_CLOCK_ROOT_OPTIONS0_OPTION2_MASK) -#define CCM_CLOCK_ROOT_OPTIONS0_OPTION3_MASK (0x1F000000U) -#define CCM_CLOCK_ROOT_OPTIONS0_OPTION3_SHIFT (24U) -/*! OPTION3 - Clock input option3 - * 0b00000..OSC_RC_16M - * 0b00001..OSC_RC_48M - * 0b00010..OSC_RC_48M_DIV2 - * 0b00011..OSC_RC_400M - * 0b00101..OSC_24M_OUT - * 0b00111..PLL_ARM_OUT - * 0b01001..PLL_528_OUT - * 0b01010..PLL_528_PFD0 - * 0b01011..PLL_528_PFD1 - * 0b01100..PLL_528_PFD2 - * 0b01101..PLL_528_PFD3 - * 0b01111..PLL_480_OUT - * 0b10000..PLL_480_DIV2 - * 0b10001..PLL_480_PFD0 - * 0b10010..PLL_480_PFD1 - * 0b10011..PLL_480_PFD2 - * 0b10100..PLL_480_PFD3 - * 0b10110..PLL_1G_OUT - * 0b10111..PLL_1G_DIV2 - * 0b11000..PLL_1G_DIV5 - * 0b11010..PLL_AUDIO_OUT - * 0b11100..PLL_VIDEO_OUT - */ -#define CCM_CLOCK_ROOT_OPTIONS0_OPTION3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_OPTIONS0_OPTION3_SHIFT)) & CCM_CLOCK_ROOT_OPTIONS0_OPTION3_MASK) -/*! @} */ - -/* The count of CCM_CLOCK_ROOT_OPTIONS0 */ -#define CCM_CLOCK_ROOT_OPTIONS0_COUNT (79U) - -/*! @name CLOCK_ROOT_OPTIONS1 - Clock root low power status */ -/*! @{ */ -#define CCM_CLOCK_ROOT_OPTIONS1_OPTION4_MASK (0x1FU) -#define CCM_CLOCK_ROOT_OPTIONS1_OPTION4_SHIFT (0U) -/*! OPTION4 - Clock input option4 - * 0b00000..OSC_RC_16M - * 0b00001..OSC_RC_48M - * 0b00010..OSC_RC_48M_DIV2 - * 0b00011..OSC_RC_400M - * 0b00101..OSC_24M_OUT - * 0b00111..PLL_ARM_OUT - * 0b01001..PLL_528_OUT - * 0b01010..PLL_528_PFD0 - * 0b01011..PLL_528_PFD1 - * 0b01100..PLL_528_PFD2 - * 0b01101..PLL_528_PFD3 - * 0b01111..PLL_480_OUT - * 0b10000..PLL_480_DIV2 - * 0b10001..PLL_480_PFD0 - * 0b10010..PLL_480_PFD1 - * 0b10011..PLL_480_PFD2 - * 0b10100..PLL_480_PFD3 - * 0b10110..PLL_1G_OUT - * 0b10111..PLL_1G_DIV2 - * 0b11000..PLL_1G_DIV5 - * 0b11010..PLL_AUDIO_OUT - * 0b11100..PLL_VIDEO_OUT - */ -#define CCM_CLOCK_ROOT_OPTIONS1_OPTION4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_OPTIONS1_OPTION4_SHIFT)) & CCM_CLOCK_ROOT_OPTIONS1_OPTION4_MASK) -#define CCM_CLOCK_ROOT_OPTIONS1_OPTION5_MASK (0x1F00U) -#define CCM_CLOCK_ROOT_OPTIONS1_OPTION5_SHIFT (8U) -/*! OPTION5 - Clock input option 5 - * 0b00000..OSC_RC_16M - * 0b00001..OSC_RC_48M - * 0b00010..OSC_RC_48M_DIV2 - * 0b00011..OSC_RC_400M - * 0b00101..OSC_24M_OUT - * 0b00111..PLL_ARM_OUT - * 0b01001..PLL_528_OUT - * 0b01010..PLL_528_PFD0 - * 0b01011..PLL_528_PFD1 - * 0b01100..PLL_528_PFD2 - * 0b01101..PLL_528_PFD3 - * 0b01111..PLL_480_OUT - * 0b10000..PLL_480_DIV2 - * 0b10001..PLL_480_PFD0 - * 0b10010..PLL_480_PFD1 - * 0b10011..PLL_480_PFD2 - * 0b10100..PLL_480_PFD3 - * 0b10110..PLL_1G_OUT - * 0b10111..PLL_1G_DIV2 - * 0b11000..PLL_1G_DIV5 - * 0b11010..PLL_AUDIO_OUT - * 0b11100..PLL_VIDEO_OUT - */ -#define CCM_CLOCK_ROOT_OPTIONS1_OPTION5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_OPTIONS1_OPTION5_SHIFT)) & CCM_CLOCK_ROOT_OPTIONS1_OPTION5_MASK) -#define CCM_CLOCK_ROOT_OPTIONS1_OPTION6_MASK (0x1F0000U) -#define CCM_CLOCK_ROOT_OPTIONS1_OPTION6_SHIFT (16U) -/*! OPTION6 - Clock input option 6 - * 0b00000..OSC_RC_16M - * 0b00001..OSC_RC_48M - * 0b00010..OSC_RC_48M_DIV2 - * 0b00011..OSC_RC_400M - * 0b00101..OSC_24M_OUT - * 0b00111..PLL_ARM_OUT - * 0b01001..PLL_528_OUT - * 0b01010..PLL_528_PFD0 - * 0b01011..PLL_528_PFD1 - * 0b01100..PLL_528_PFD2 - * 0b01101..PLL_528_PFD3 - * 0b01111..PLL_480_OUT - * 0b10000..PLL_480_DIV2 - * 0b10001..PLL_480_PFD0 - * 0b10010..PLL_480_PFD1 - * 0b10011..PLL_480_PFD2 - * 0b10100..PLL_480_PFD3 - * 0b10110..PLL_1G_OUT - * 0b10111..PLL_1G_DIV2 - * 0b11000..PLL_1G_DIV5 - * 0b11010..PLL_AUDIO_OUT - * 0b11100..PLL_VIDEO_OUT - */ -#define CCM_CLOCK_ROOT_OPTIONS1_OPTION6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_OPTIONS1_OPTION6_SHIFT)) & CCM_CLOCK_ROOT_OPTIONS1_OPTION6_MASK) -#define CCM_CLOCK_ROOT_OPTIONS1_OPTION7_MASK (0x1F000000U) -#define CCM_CLOCK_ROOT_OPTIONS1_OPTION7_SHIFT (24U) -/*! OPTION7 - Clock input option 7 - * 0b00000..OSC_RC_16M - * 0b00001..OSC_RC_48M - * 0b00010..OSC_RC_48M_DIV2 - * 0b00011..OSC_RC_400M - * 0b00101..OSC_24M_OUT - * 0b00111..PLL_ARM_OUT - * 0b01001..PLL_528_OUT - * 0b01010..PLL_528_PFD0 - * 0b01011..PLL_528_PFD1 - * 0b01100..PLL_528_PFD2 - * 0b01101..PLL_528_PFD3 - * 0b01111..PLL_480_OUT - * 0b10000..PLL_480_DIV2 - * 0b10001..PLL_480_PFD0 - * 0b10010..PLL_480_PFD1 - * 0b10011..PLL_480_PFD2 - * 0b10100..PLL_480_PFD3 - * 0b10110..PLL_1G_OUT - * 0b10111..PLL_1G_DIV2 - * 0b11000..PLL_1G_DIV5 - * 0b11010..PLL_AUDIO_OUT - * 0b11100..PLL_VIDEO_OUT - */ -#define CCM_CLOCK_ROOT_OPTIONS1_OPTION7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_OPTIONS1_OPTION7_SHIFT)) & CCM_CLOCK_ROOT_OPTIONS1_OPTION7_MASK) -/*! @} */ - -/* The count of CCM_CLOCK_ROOT_OPTIONS1 */ -#define CCM_CLOCK_ROOT_OPTIONS1_COUNT (79U) - /*! @name CLOCK_ROOT_STATUS0 - Clock root working status */ /*! @{ */ + #define CCM_CLOCK_ROOT_STATUS0_DIV_MASK (0xFFU) #define CCM_CLOCK_ROOT_STATUS0_DIV_SHIFT (0U) /*! DIV - Current clock root DIV setting */ #define CCM_CLOCK_ROOT_STATUS0_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_DIV_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_DIV_MASK) + #define CCM_CLOCK_ROOT_STATUS0_MUX_MASK (0x700U) #define CCM_CLOCK_ROOT_STATUS0_MUX_SHIFT (8U) /*! MUX - Current clock root MUX setting */ #define CCM_CLOCK_ROOT_STATUS0_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_MUX_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_MUX_MASK) -#define CCM_CLOCK_ROOT_STATUS0_MFD_MASK (0xF0000U) -#define CCM_CLOCK_ROOT_STATUS0_MFD_SHIFT (16U) -/*! MFD - Current clock root MFD setting - */ -#define CCM_CLOCK_ROOT_STATUS0_MFD(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_MFD_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_MFD_MASK) -#define CCM_CLOCK_ROOT_STATUS0_MFN_MASK (0xF00000U) -#define CCM_CLOCK_ROOT_STATUS0_MFN_SHIFT (20U) -/*! MFN - Current clock root MFN setting - */ -#define CCM_CLOCK_ROOT_STATUS0_MFN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_MFN_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_MFN_MASK) + #define CCM_CLOCK_ROOT_STATUS0_OFF_MASK (0x1000000U) #define CCM_CLOCK_ROOT_STATUS0_OFF_SHIFT (24U) /*! OFF - Current clock root OFF setting - * 0b0..Clock is running. - * 0b1..Turn off clock. + * 0b0..Clock is running + * 0b1..Clock is disabled/off */ #define CCM_CLOCK_ROOT_STATUS0_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_OFF_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_OFF_MASK) + #define CCM_CLOCK_ROOT_STATUS0_POWERDOWN_MASK (0x8000000U) #define CCM_CLOCK_ROOT_STATUS0_POWERDOWN_SHIFT (27U) /*! POWERDOWN - Current clock root POWERDOWN setting + * 0b1..Clock root is Powered Down + * 0b0..Clock root is running */ #define CCM_CLOCK_ROOT_STATUS0_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_POWERDOWN_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_POWERDOWN_MASK) + #define CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_MASK (0x10000000U) #define CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_SHIFT (28U) /*! SLICE_BUSY - Internal updating in generation logic + * 0b1..Clock generation logic is applying the new setting + * 0b0..Clock generation logic is not busy */ #define CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_MASK) + #define CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_MASK (0x20000000U) #define CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_SHIFT (29U) /*! UPDATE_FORWARD - Internal status synchronization to clock generation logic + * 0b1..Synchronization in process + * 0b0..Synchronization not in process */ #define CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_MASK) + #define CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE_MASK (0x40000000U) #define CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE_SHIFT (30U) /*! UPDATE_REVERSE - Internal status synchronization from clock generation logic + * 0b1..Synchronization in process + * 0b0..Synchronization not in process */ #define CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE_MASK) + #define CCM_CLOCK_ROOT_STATUS0_CHANGING_MASK (0x80000000U) #define CCM_CLOCK_ROOT_STATUS0_CHANGING_SHIFT (31U) /*! CHANGING - Internal updating in clock root + * 0b1..Clock generation logic is updating currently + * 0b0..Clock Status is not updating currently */ #define CCM_CLOCK_ROOT_STATUS0_CHANGING(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_CHANGING_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_CHANGING_MASK) /*! @} */ @@ -18407,34 +20623,48 @@ typedef struct { /*! @name CLOCK_ROOT_STATUS1 - Clock root low power status */ /*! @{ */ + #define CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT_MASK (0xF0000U) #define CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT_SHIFT (16U) -/*! TARGET_SETPOINT - Next setpoint to change to +/*! TARGET_SETPOINT - Target Setpoint */ #define CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT_MASK) + #define CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT_MASK (0xF00000U) #define CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT_SHIFT (20U) -/*! CURRENT_SETPOINT - Current setpoint +/*! CURRENT_SETPOINT - Current Setpoint */ #define CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT_MASK) + #define CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST_MASK (0x1000000U) #define CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST_SHIFT (24U) /*! DOWN_REQUEST - Clock frequency decrease request + * 0b1..Frequency decrease requested + * 0b0..Frequency decrease not requested */ #define CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST_MASK) + #define CCM_CLOCK_ROOT_STATUS1_DOWN_DONE_MASK (0x2000000U) #define CCM_CLOCK_ROOT_STATUS1_DOWN_DONE_SHIFT (25U) /*! DOWN_DONE - Clock frequency decrease finish + * 0b1..Frequency decrease completed + * 0b0..Frequency decrease not completed */ #define CCM_CLOCK_ROOT_STATUS1_DOWN_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_DOWN_DONE_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_DOWN_DONE_MASK) + #define CCM_CLOCK_ROOT_STATUS1_UP_REQUEST_MASK (0x4000000U) #define CCM_CLOCK_ROOT_STATUS1_UP_REQUEST_SHIFT (26U) /*! UP_REQUEST - Clock frequency increase request + * 0b1..Frequency increase requested + * 0b0..Frequency increase not requested */ #define CCM_CLOCK_ROOT_STATUS1_UP_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_UP_REQUEST_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_UP_REQUEST_MASK) + #define CCM_CLOCK_ROOT_STATUS1_UP_DONE_MASK (0x8000000U) #define CCM_CLOCK_ROOT_STATUS1_UP_DONE_SHIFT (27U) /*! UP_DONE - Clock frequency increase finish + * 0b1..Frequency increase completed + * 0b0..Frequency increase not completed */ #define CCM_CLOCK_ROOT_STATUS1_UP_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_UP_DONE_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_UP_DONE_MASK) /*! @} */ @@ -18444,8 +20674,9 @@ typedef struct { /*! @name CLOCK_ROOT_CONFIG - Clock root configuration */ /*! @{ */ -#define CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_MASK (0x1U) -#define CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_SHIFT (0U) + +#define CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_MASK (0x10U) +#define CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_SHIFT (4U) /*! SETPOINT_PRESENT - Setpoint present * 0b1..Setpoint is implemented. * 0b0..Setpoint is not implemented. @@ -18458,60 +20689,68 @@ typedef struct { /*! @name CLOCK_ROOT_AUTHEN - Clock root access control */ /*! @{ */ + #define CCM_CLOCK_ROOT_AUTHEN_TZ_USER_MASK (0x1U) #define CCM_CLOCK_ROOT_AUTHEN_TZ_USER_SHIFT (0U) /*! TZ_USER - User access - * 0b1..Clock can be changed in user mode. - * 0b0..Clock cannot be changed in user mode. + * 0b1..Clock can be changed in user mode + * 0b0..Clock cannot be changed in user mode */ #define CCM_CLOCK_ROOT_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TZ_USER_MASK) + #define CCM_CLOCK_ROOT_AUTHEN_TZ_NS_MASK (0x2U) #define CCM_CLOCK_ROOT_AUTHEN_TZ_NS_SHIFT (1U) /*! TZ_NS - Non-secure access - * 0b0..Cannot be changed in Non-secure mode. - * 0b1..Can be changed in Non-secure mode. + * 0b0..Cannot be changed in Non-secure mode + * 0b1..Can be changed in Non-secure mode */ #define CCM_CLOCK_ROOT_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TZ_NS_MASK) + #define CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_MASK (0x10U) #define CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_SHIFT (4U) /*! LOCK_TZ - Lock truszone setting - * 0b0..Trustzone setting is not locked. - * 0b1..Trustzone setting is locked. + * 0b0..Trustzone setting is not locked + * 0b1..Trustzone setting is locked */ #define CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_MASK) + #define CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_MASK (0xF00U) #define CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_SHIFT (8U) /*! WHITE_LIST - Whitelist - * 0b0000..This domain is NOT allowed to change clock. - * 0b0001..This domain is allowed to change clock. + * 0b0000..This domain is NOT allowed to change clock + * 0b0001..This domain is allowed to change clock */ #define CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_MASK) + #define CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_MASK (0x1000U) #define CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_SHIFT (12U) -/*! LOCK_LIST - Lock white list - * 0b0..Whitelist is not locked. - * 0b1..Whitelist is locked. +/*! LOCK_LIST - Lock Whitelist + * 0b0..Whitelist is not locked + * 0b1..Whitelist is locked */ #define CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_MASK) + #define CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_MASK (0x10000U) #define CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_SHIFT (16U) /*! DOMAIN_MODE - Low power and access control by domain - * 0b1..Clock works in domain mode. - * 0b0..Clock does NOT work in domain mode. + * 0b1..Clock works in Domain Mode + * 0b0..Clock does NOT work in Domain Mode */ #define CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_MASK) + #define CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_MASK (0x20000U) #define CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_SHIFT (17U) -/*! SETPOINT_MODE - Low power and access control by setpoint - * 0b1..Clock works in setpoint mode. - * 0b0..Clock does NOT work in setpoint mode. +/*! SETPOINT_MODE - Low power and access control by Setpoint + * 0b1..Clock works in Setpoint Mode + * 0b0..Clock does NOT work in Setpoint Mode */ #define CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_MASK) + #define CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_MASK (0x100000U) #define CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_SHIFT (20U) /*! LOCK_MODE - Lock low power and access mode - * 0b0..MODE is not locked. - * 0b1..MODE is locked. + * 0b0..MODE is not locked + * 0b1..MODE is locked */ #define CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_MASK) /*! @} */ @@ -18521,41 +20760,49 @@ typedef struct { /*! @name CLOCK_ROOT_AUTHEN_SET - Clock root access control */ /*! @{ */ + #define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER_MASK (0x1U) #define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER_SHIFT (0U) /*! TZ_USER - User access */ #define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER_MASK) + #define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS_MASK (0x2U) #define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS_SHIFT (1U) /*! TZ_NS - Non-secure access */ #define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS_MASK) + #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ_MASK (0x10U) #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ_SHIFT (4U) /*! LOCK_TZ - Lock truszone setting */ #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ_MASK) + #define CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST_MASK (0xF00U) #define CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST_SHIFT (8U) /*! WHITE_LIST - Whitelist */ #define CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST_MASK) + #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST_MASK (0x1000U) #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST_SHIFT (12U) -/*! LOCK_LIST - Lock white list +/*! LOCK_LIST - Lock Whitelist */ #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST_MASK) + #define CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U) #define CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U) /*! DOMAIN_MODE - Low power and access control by domain */ #define CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE_MASK) + #define CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE_MASK (0x20000U) #define CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE_SHIFT (17U) -/*! SETPOINT_MODE - Low power and access control by setpoint +/*! SETPOINT_MODE - Low power and access control by Setpoint */ #define CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE_MASK) + #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE_MASK (0x100000U) #define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE_SHIFT (20U) /*! LOCK_MODE - Lock low power and access mode @@ -18568,41 +20815,49 @@ typedef struct { /*! @name CLOCK_ROOT_AUTHEN_CLR - Clock root access control */ /*! @{ */ + #define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER_MASK (0x1U) #define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER_SHIFT (0U) /*! TZ_USER - User access */ #define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER_MASK) + #define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS_MASK (0x2U) #define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS_SHIFT (1U) /*! TZ_NS - Non-secure access */ #define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS_MASK) + #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ_MASK (0x10U) #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ_SHIFT (4U) /*! LOCK_TZ - Lock truszone setting */ #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ_MASK) + #define CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U) #define CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST_SHIFT (8U) /*! WHITE_LIST - Whitelist */ #define CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST_MASK) + #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U) #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST_SHIFT (12U) -/*! LOCK_LIST - Lock white list +/*! LOCK_LIST - Lock Whitelist */ #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST_MASK) + #define CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U) #define CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U) /*! DOMAIN_MODE - Low power and access control by domain */ #define CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE_MASK) + #define CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE_MASK (0x20000U) #define CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE_SHIFT (17U) -/*! SETPOINT_MODE - Low power and access control by setpoint +/*! SETPOINT_MODE - Low power and access control by Setpoint */ #define CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE_MASK) + #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U) #define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE_SHIFT (20U) /*! LOCK_MODE - Lock low power and access mode @@ -18615,41 +20870,49 @@ typedef struct { /*! @name CLOCK_ROOT_AUTHEN_TOG - Clock root access control */ /*! @{ */ + #define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER_MASK (0x1U) #define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER_SHIFT (0U) /*! TZ_USER - User access */ #define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER_MASK) + #define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS_MASK (0x2U) #define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS_SHIFT (1U) /*! TZ_NS - Non-secure access */ #define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS_MASK) + #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ_MASK (0x10U) #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ_SHIFT (4U) /*! LOCK_TZ - Lock truszone setting */ #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ_MASK) + #define CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U) #define CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST_SHIFT (8U) /*! WHITE_LIST - Whitelist */ #define CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST_MASK) + #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U) #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST_SHIFT (12U) -/*! LOCK_LIST - Lock white list +/*! LOCK_LIST - Lock Whitelist */ #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST_MASK) + #define CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U) #define CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U) /*! DOMAIN_MODE - Low power and access control by domain */ #define CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE_MASK) + #define CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE_MASK (0x20000U) #define CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE_SHIFT (17U) -/*! SETPOINT_MODE - Low power and access control by setpoint +/*! SETPOINT_MODE - Low power and access control by Setpoint */ #define CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE_MASK) + #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U) #define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE_SHIFT (20U) /*! LOCK_MODE - Lock low power and access mode @@ -18662,21 +20925,27 @@ typedef struct { /*! @name CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT - Setpoint setting */ /*! @{ */ + #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV_MASK (0xFFU) #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV_SHIFT (0U) /*! DIV - Clock divider */ #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV_SHIFT)) & CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV_MASK) + #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX_MASK (0x700U) #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX_SHIFT (8U) /*! MUX - Clock multiplexer */ #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX_SHIFT)) & CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX_MASK) + #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF_MASK (0x1000000U) #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF_SHIFT (24U) /*! OFF - OFF + * 0b1..OFF + * 0b0..ON */ #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF_SHIFT)) & CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF_MASK) + #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE_MASK (0xF0000000U) #define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE_SHIFT (28U) /*! GRADE - Grade @@ -18692,36 +20961,24 @@ typedef struct { /*! @name CLOCK_GROUP_CONTROL - Clock group control */ /*! @{ */ + #define CCM_CLOCK_GROUP_CONTROL_DIV0_MASK (0xFU) #define CCM_CLOCK_GROUP_CONTROL_DIV0_SHIFT (0U) /*! DIV0 - Clock divider0 */ #define CCM_CLOCK_GROUP_CONTROL_DIV0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_DIV0_MASK) -#define CCM_CLOCK_GROUP_CONTROL_DIV1_MASK (0xF0U) -#define CCM_CLOCK_GROUP_CONTROL_DIV1_SHIFT (4U) -/*! DIV1 - Clock divider1 - */ -#define CCM_CLOCK_GROUP_CONTROL_DIV1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_DIV1_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_DIV1_MASK) -#define CCM_CLOCK_GROUP_CONTROL_DIV2_MASK (0xF00U) -#define CCM_CLOCK_GROUP_CONTROL_DIV2_SHIFT (8U) -/*! DIV2 - Clock divider2 - */ -#define CCM_CLOCK_GROUP_CONTROL_DIV2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_DIV2_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_DIV2_MASK) -#define CCM_CLOCK_GROUP_CONTROL_DIV3_MASK (0xF000U) -#define CCM_CLOCK_GROUP_CONTROL_DIV3_SHIFT (12U) -/*! DIV3 - Clock divider3 - */ -#define CCM_CLOCK_GROUP_CONTROL_DIV3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_DIV3_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_DIV3_MASK) + #define CCM_CLOCK_GROUP_CONTROL_RSTDIV_MASK (0xFF0000U) #define CCM_CLOCK_GROUP_CONTROL_RSTDIV_SHIFT (16U) /*! RSTDIV - Clock group global restart count */ #define CCM_CLOCK_GROUP_CONTROL_RSTDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_RSTDIV_MASK) + #define CCM_CLOCK_GROUP_CONTROL_OFF_MASK (0x1000000U) #define CCM_CLOCK_GROUP_CONTROL_OFF_SHIFT (24U) /*! OFF - OFF - * 0b0..Clock is running. - * 0b1..Turn off clock. + * 0b0..Clock is running + * 0b1..Turn off clock */ #define CCM_CLOCK_GROUP_CONTROL_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_OFF_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_OFF_MASK) /*! @} */ @@ -18731,31 +20988,19 @@ typedef struct { /*! @name CLOCK_GROUP_CONTROL_SET - Clock group control */ /*! @{ */ + #define CCM_CLOCK_GROUP_CONTROL_SET_DIV0_MASK (0xFU) #define CCM_CLOCK_GROUP_CONTROL_SET_DIV0_SHIFT (0U) /*! DIV0 - Clock divider0 */ #define CCM_CLOCK_GROUP_CONTROL_SET_DIV0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_SET_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_SET_DIV0_MASK) -#define CCM_CLOCK_GROUP_CONTROL_SET_DIV1_MASK (0xF0U) -#define CCM_CLOCK_GROUP_CONTROL_SET_DIV1_SHIFT (4U) -/*! DIV1 - Clock divider1 - */ -#define CCM_CLOCK_GROUP_CONTROL_SET_DIV1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_SET_DIV1_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_SET_DIV1_MASK) -#define CCM_CLOCK_GROUP_CONTROL_SET_DIV2_MASK (0xF00U) -#define CCM_CLOCK_GROUP_CONTROL_SET_DIV2_SHIFT (8U) -/*! DIV2 - Clock divider2 - */ -#define CCM_CLOCK_GROUP_CONTROL_SET_DIV2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_SET_DIV2_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_SET_DIV2_MASK) -#define CCM_CLOCK_GROUP_CONTROL_SET_DIV3_MASK (0xF000U) -#define CCM_CLOCK_GROUP_CONTROL_SET_DIV3_SHIFT (12U) -/*! DIV3 - Clock divider3 - */ -#define CCM_CLOCK_GROUP_CONTROL_SET_DIV3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_SET_DIV3_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_SET_DIV3_MASK) + #define CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV_MASK (0xFF0000U) #define CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV_SHIFT (16U) /*! RSTDIV - Clock group global restart count */ #define CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV_MASK) + #define CCM_CLOCK_GROUP_CONTROL_SET_OFF_MASK (0x1000000U) #define CCM_CLOCK_GROUP_CONTROL_SET_OFF_SHIFT (24U) /*! OFF - OFF @@ -18768,31 +21013,19 @@ typedef struct { /*! @name CLOCK_GROUP_CONTROL_CLR - Clock group control */ /*! @{ */ + #define CCM_CLOCK_GROUP_CONTROL_CLR_DIV0_MASK (0xFU) #define CCM_CLOCK_GROUP_CONTROL_CLR_DIV0_SHIFT (0U) /*! DIV0 - Clock divider0 */ #define CCM_CLOCK_GROUP_CONTROL_CLR_DIV0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_CLR_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_CLR_DIV0_MASK) -#define CCM_CLOCK_GROUP_CONTROL_CLR_DIV1_MASK (0xF0U) -#define CCM_CLOCK_GROUP_CONTROL_CLR_DIV1_SHIFT (4U) -/*! DIV1 - Clock divider1 - */ -#define CCM_CLOCK_GROUP_CONTROL_CLR_DIV1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_CLR_DIV1_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_CLR_DIV1_MASK) -#define CCM_CLOCK_GROUP_CONTROL_CLR_DIV2_MASK (0xF00U) -#define CCM_CLOCK_GROUP_CONTROL_CLR_DIV2_SHIFT (8U) -/*! DIV2 - Clock divider2 - */ -#define CCM_CLOCK_GROUP_CONTROL_CLR_DIV2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_CLR_DIV2_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_CLR_DIV2_MASK) -#define CCM_CLOCK_GROUP_CONTROL_CLR_DIV3_MASK (0xF000U) -#define CCM_CLOCK_GROUP_CONTROL_CLR_DIV3_SHIFT (12U) -/*! DIV3 - Clock divider3 - */ -#define CCM_CLOCK_GROUP_CONTROL_CLR_DIV3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_CLR_DIV3_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_CLR_DIV3_MASK) + #define CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV_MASK (0xFF0000U) #define CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV_SHIFT (16U) /*! RSTDIV - Clock group global restart count */ #define CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV_MASK) + #define CCM_CLOCK_GROUP_CONTROL_CLR_OFF_MASK (0x1000000U) #define CCM_CLOCK_GROUP_CONTROL_CLR_OFF_SHIFT (24U) /*! OFF - OFF @@ -18805,31 +21038,19 @@ typedef struct { /*! @name CLOCK_GROUP_CONTROL_TOG - Clock group control */ /*! @{ */ + #define CCM_CLOCK_GROUP_CONTROL_TOG_DIV0_MASK (0xFU) #define CCM_CLOCK_GROUP_CONTROL_TOG_DIV0_SHIFT (0U) /*! DIV0 - Clock divider0 */ #define CCM_CLOCK_GROUP_CONTROL_TOG_DIV0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_TOG_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_TOG_DIV0_MASK) -#define CCM_CLOCK_GROUP_CONTROL_TOG_DIV1_MASK (0xF0U) -#define CCM_CLOCK_GROUP_CONTROL_TOG_DIV1_SHIFT (4U) -/*! DIV1 - Clock divider1 - */ -#define CCM_CLOCK_GROUP_CONTROL_TOG_DIV1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_TOG_DIV1_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_TOG_DIV1_MASK) -#define CCM_CLOCK_GROUP_CONTROL_TOG_DIV2_MASK (0xF00U) -#define CCM_CLOCK_GROUP_CONTROL_TOG_DIV2_SHIFT (8U) -/*! DIV2 - Clock divider2 - */ -#define CCM_CLOCK_GROUP_CONTROL_TOG_DIV2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_TOG_DIV2_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_TOG_DIV2_MASK) -#define CCM_CLOCK_GROUP_CONTROL_TOG_DIV3_MASK (0xF000U) -#define CCM_CLOCK_GROUP_CONTROL_TOG_DIV3_SHIFT (12U) -/*! DIV3 - Clock divider3 - */ -#define CCM_CLOCK_GROUP_CONTROL_TOG_DIV3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_TOG_DIV3_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_TOG_DIV3_MASK) + #define CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV_MASK (0xFF0000U) #define CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV_SHIFT (16U) /*! RSTDIV - Clock group global restart count */ #define CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV_MASK) + #define CCM_CLOCK_GROUP_CONTROL_TOG_OFF_MASK (0x1000000U) #define CCM_CLOCK_GROUP_CONTROL_TOG_OFF_SHIFT (24U) /*! OFF - OFF @@ -18840,221 +21061,21 @@ typedef struct { /* The count of CCM_CLOCK_GROUP_CONTROL_TOG */ #define CCM_CLOCK_GROUP_CONTROL_TOG_COUNT (2U) -/*! @name CLOCK_GROUP_CONTROL_EXTEND - Clock group control extend */ -/*! @{ */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV4_MASK (0xFU) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV4_SHIFT (0U) -/*! DIV4 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV4_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV4_MASK) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV5_MASK (0xF0U) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV5_SHIFT (4U) -/*! DIV5 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV5_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV5_MASK) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV6_MASK (0xF00U) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV6_SHIFT (8U) -/*! DIV6 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV6_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV6_MASK) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV7_MASK (0xF000U) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV7_SHIFT (12U) -/*! DIV7 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV7_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV7_MASK) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV8_MASK (0xF0000U) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV8_SHIFT (16U) -/*! DIV8 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV8_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV8_MASK) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV9_MASK (0xF00000U) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV9_SHIFT (20U) -/*! DIV9 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV9_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV9_MASK) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV10_MASK (0xF000000U) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV10_SHIFT (24U) -/*! DIV10 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV10_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV10_MASK) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV11_MASK (0xF0000000U) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV11_SHIFT (28U) -/*! DIV11 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV11_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV11_MASK) -/*! @} */ - -/* The count of CCM_CLOCK_GROUP_CONTROL_EXTEND */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_COUNT (2U) - -/*! @name CLOCK_GROUP_CONTROL_EXTEND_SET - Clock group control extend */ -/*! @{ */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV4_MASK (0xFU) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV4_SHIFT (0U) -/*! DIV4 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV4_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV4_MASK) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV5_MASK (0xF0U) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV5_SHIFT (4U) -/*! DIV5 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV5_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV5_MASK) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV6_MASK (0xF00U) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV6_SHIFT (8U) -/*! DIV6 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV6_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV6_MASK) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV7_MASK (0xF000U) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV7_SHIFT (12U) -/*! DIV7 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV7_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV7_MASK) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV8_MASK (0xF0000U) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV8_SHIFT (16U) -/*! DIV8 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV8_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV8_MASK) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV9_MASK (0xF00000U) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV9_SHIFT (20U) -/*! DIV9 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV9_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV9_MASK) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV10_MASK (0xF000000U) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV10_SHIFT (24U) -/*! DIV10 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV10_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV10_MASK) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV11_MASK (0xF0000000U) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV11_SHIFT (28U) -/*! DIV11 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV11_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_DIV11_MASK) -/*! @} */ - -/* The count of CCM_CLOCK_GROUP_CONTROL_EXTEND_SET */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_SET_COUNT (2U) - -/*! @name CLOCK_GROUP_CONTROL_EXTEND_CLR - Clock group control extend */ -/*! @{ */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV4_MASK (0xFU) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV4_SHIFT (0U) -/*! DIV4 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV4_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV4_MASK) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV5_MASK (0xF0U) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV5_SHIFT (4U) -/*! DIV5 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV5_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV5_MASK) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV6_MASK (0xF00U) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV6_SHIFT (8U) -/*! DIV6 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV6_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV6_MASK) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV7_MASK (0xF000U) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV7_SHIFT (12U) -/*! DIV7 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV7_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV7_MASK) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV8_MASK (0xF0000U) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV8_SHIFT (16U) -/*! DIV8 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV8_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV8_MASK) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV9_MASK (0xF00000U) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV9_SHIFT (20U) -/*! DIV9 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV9_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV9_MASK) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV10_MASK (0xF000000U) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV10_SHIFT (24U) -/*! DIV10 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV10_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV10_MASK) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV11_MASK (0xF0000000U) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV11_SHIFT (28U) -/*! DIV11 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV11_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_DIV11_MASK) -/*! @} */ - -/* The count of CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_CLR_COUNT (2U) - -/*! @name CLOCK_GROUP_CONTROL_EXTEND_TOG - Clock group control extend */ -/*! @{ */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV4_MASK (0xFU) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV4_SHIFT (0U) -/*! DIV4 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV4_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV4_MASK) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV5_MASK (0xF0U) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV5_SHIFT (4U) -/*! DIV5 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV5_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV5_MASK) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV6_MASK (0xF00U) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV6_SHIFT (8U) -/*! DIV6 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV6_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV6_MASK) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV7_MASK (0xF000U) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV7_SHIFT (12U) -/*! DIV7 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV7_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV7_MASK) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV8_MASK (0xF0000U) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV8_SHIFT (16U) -/*! DIV8 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV8_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV8_MASK) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV9_MASK (0xF00000U) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV9_SHIFT (20U) -/*! DIV9 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV9_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV9_MASK) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV10_MASK (0xF000000U) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV10_SHIFT (24U) -/*! DIV10 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV10_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV10_MASK) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV11_MASK (0xF0000000U) -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV11_SHIFT (28U) -/*! DIV11 - Clock divider - */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV11_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_DIV11_MASK) -/*! @} */ - -/* The count of CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG */ -#define CCM_CLOCK_GROUP_CONTROL_EXTEND_TOG_COUNT (2U) - /*! @name CLOCK_GROUP_STATUS0 - Clock group working status */ /*! @{ */ + #define CCM_CLOCK_GROUP_STATUS0_DIV0_MASK (0xFU) #define CCM_CLOCK_GROUP_STATUS0_DIV0_SHIFT (0U) /*! DIV0 - Clock divider */ #define CCM_CLOCK_GROUP_STATUS0_DIV0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_DIV0_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_DIV0_MASK) -#define CCM_CLOCK_GROUP_STATUS0_DIV1_MASK (0xF0U) -#define CCM_CLOCK_GROUP_STATUS0_DIV1_SHIFT (4U) -/*! DIV1 - Clock divider - */ -#define CCM_CLOCK_GROUP_STATUS0_DIV1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_DIV1_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_DIV1_MASK) -#define CCM_CLOCK_GROUP_STATUS0_DIV2_MASK (0xF00U) -#define CCM_CLOCK_GROUP_STATUS0_DIV2_SHIFT (8U) -/*! DIV2 - Clock divider - */ -#define CCM_CLOCK_GROUP_STATUS0_DIV2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_DIV2_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_DIV2_MASK) -#define CCM_CLOCK_GROUP_STATUS0_DIV3_MASK (0xF000U) -#define CCM_CLOCK_GROUP_STATUS0_DIV3_SHIFT (12U) -/*! DIV3 - Clock divider - */ -#define CCM_CLOCK_GROUP_STATUS0_DIV3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_DIV3_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_DIV3_MASK) + #define CCM_CLOCK_GROUP_STATUS0_RSTDIV_MASK (0xFF0000U) #define CCM_CLOCK_GROUP_STATUS0_RSTDIV_SHIFT (16U) /*! RSTDIV - Clock divider */ #define CCM_CLOCK_GROUP_STATUS0_RSTDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_RSTDIV_MASK) + #define CCM_CLOCK_GROUP_STATUS0_OFF_MASK (0x1000000U) #define CCM_CLOCK_GROUP_STATUS0_OFF_SHIFT (24U) /*! OFF - OFF @@ -19062,29 +21083,44 @@ typedef struct { * 0b1..Turn off clock. */ #define CCM_CLOCK_GROUP_STATUS0_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_OFF_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_OFF_MASK) + #define CCM_CLOCK_GROUP_STATUS0_POWERDOWN_MASK (0x8000000U) #define CCM_CLOCK_GROUP_STATUS0_POWERDOWN_SHIFT (27U) /*! POWERDOWN - Current clock root POWERDOWN setting + * 0b1..Clock root is Powered Down + * 0b0..Clock root is running */ #define CCM_CLOCK_GROUP_STATUS0_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_POWERDOWN_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_POWERDOWN_MASK) + #define CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY_MASK (0x10000000U) #define CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY_SHIFT (28U) /*! SLICE_BUSY - Internal updating in generation logic + * 0b1..Clock generation logic is applying the new setting + * 0b0..Clock generation logic is not busy */ #define CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY_MASK) + #define CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD_MASK (0x20000000U) #define CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD_SHIFT (29U) /*! UPDATE_FORWARD - Internal status synchronization to clock generation logic + * 0b1..Synchronization in process + * 0b0..Synchronization not in process */ #define CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD_MASK) + #define CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE_MASK (0x40000000U) #define CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE_SHIFT (30U) /*! UPDATE_REVERSE - Internal status synchronization from clock generation logic + * 0b1..Synchronization in process + * 0b0..Synchronization not in process */ #define CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE_MASK) + #define CCM_CLOCK_GROUP_STATUS0_CHANGING_MASK (0x80000000U) #define CCM_CLOCK_GROUP_STATUS0_CHANGING_SHIFT (31U) /*! CHANGING - Internal updating in clock group + * 0b1..Clock root logic is updating currently + * 0b0..Clock root is not updating currently */ #define CCM_CLOCK_GROUP_STATUS0_CHANGING(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_CHANGING_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_CHANGING_MASK) /*! @} */ @@ -19094,46 +21130,50 @@ typedef struct { /*! @name CLOCK_GROUP_STATUS1 - Clock group low power/extend status */ /*! @{ */ -#define CCM_CLOCK_GROUP_STATUS1_DIV4_MASK (0xFU) -#define CCM_CLOCK_GROUP_STATUS1_DIV4_SHIFT (0U) -/*! DIV4 - Clock divider - */ -#define CCM_CLOCK_GROUP_STATUS1_DIV4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_DIV4_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_DIV4_MASK) -#define CCM_CLOCK_GROUP_STATUS1_DIV5_MASK (0xF0U) -#define CCM_CLOCK_GROUP_STATUS1_DIV5_SHIFT (4U) -/*! DIV5 - Clock divider - */ -#define CCM_CLOCK_GROUP_STATUS1_DIV5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_DIV5_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_DIV5_MASK) -#define CCM_CLOCK_GROUP_STATUS1_DIV6_MASK (0xF00U) -#define CCM_CLOCK_GROUP_STATUS1_DIV6_SHIFT (8U) -/*! DIV6 - Clock divider + +#define CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT_MASK (0xF0000U) +#define CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT_SHIFT (16U) +/*! TARGET_SETPOINT - Next Setpoint to change to */ -#define CCM_CLOCK_GROUP_STATUS1_DIV6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_DIV6_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_DIV6_MASK) -#define CCM_CLOCK_GROUP_STATUS1_DIV7_MASK (0xF000U) -#define CCM_CLOCK_GROUP_STATUS1_DIV7_SHIFT (12U) -/*! DIV7 - Clock divider +#define CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT_MASK) + +#define CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT_MASK (0xF00000U) +#define CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT_SHIFT (20U) +/*! CURRENT_SETPOINT - Current Setpoint */ -#define CCM_CLOCK_GROUP_STATUS1_DIV7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_DIV7_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_DIV7_MASK) -#define CCM_CLOCK_GROUP_STATUS1_DIV8_MASK (0xF0000U) -#define CCM_CLOCK_GROUP_STATUS1_DIV8_SHIFT (16U) -/*! DIV8 - Clock divider +#define CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT_MASK) + +#define CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST_MASK (0x1000000U) +#define CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST_SHIFT (24U) +/*! DOWN_REQUEST - Clock frequency decrease request + * 0b1..Handshake signal with GPC status indicating frequency decrease is requested + * 0b0..No handshake signal is not requested */ -#define CCM_CLOCK_GROUP_STATUS1_DIV8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_DIV8_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_DIV8_MASK) -#define CCM_CLOCK_GROUP_STATUS1_DIV9_MASK (0xF00000U) -#define CCM_CLOCK_GROUP_STATUS1_DIV9_SHIFT (20U) -/*! DIV9 - Clock divider +#define CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST_MASK) + +#define CCM_CLOCK_GROUP_STATUS1_DOWN_DONE_MASK (0x2000000U) +#define CCM_CLOCK_GROUP_STATUS1_DOWN_DONE_SHIFT (25U) +/*! DOWN_DONE - Clock frequency decrease complete + * 0b1..Handshake signal with GPC status indicating frequency decrease is complete + * 0b0..Handshake signal with GPC status indicating frequency decrease is not complete */ -#define CCM_CLOCK_GROUP_STATUS1_DIV9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_DIV9_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_DIV9_MASK) -#define CCM_CLOCK_GROUP_STATUS1_DIV10_MASK (0xF000000U) -#define CCM_CLOCK_GROUP_STATUS1_DIV10_SHIFT (24U) -/*! DIV10 - Clock divider +#define CCM_CLOCK_GROUP_STATUS1_DOWN_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_DOWN_DONE_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_DOWN_DONE_MASK) + +#define CCM_CLOCK_GROUP_STATUS1_UP_REQUEST_MASK (0x4000000U) +#define CCM_CLOCK_GROUP_STATUS1_UP_REQUEST_SHIFT (26U) +/*! UP_REQUEST - Clock frequency increase request + * 0b1..Handshake signal with GPC status indicating frequency increase is requested + * 0b0..No handshake signal is not requested */ -#define CCM_CLOCK_GROUP_STATUS1_DIV10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_DIV10_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_DIV10_MASK) -#define CCM_CLOCK_GROUP_STATUS1_DIV11_MASK (0xF0000000U) -#define CCM_CLOCK_GROUP_STATUS1_DIV11_SHIFT (28U) -/*! DIV11 - Clock divider +#define CCM_CLOCK_GROUP_STATUS1_UP_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_UP_REQUEST_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_UP_REQUEST_MASK) + +#define CCM_CLOCK_GROUP_STATUS1_UP_DONE_MASK (0x8000000U) +#define CCM_CLOCK_GROUP_STATUS1_UP_DONE_SHIFT (27U) +/*! UP_DONE - Clock frequency increase complete + * 0b1..Handshake signal with GPC status indicating frequency increase is complete + * 0b0..Handshake signal with GPC status indicating frequency increase is not complete */ -#define CCM_CLOCK_GROUP_STATUS1_DIV11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_DIV11_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_DIV11_MASK) +#define CCM_CLOCK_GROUP_STATUS1_UP_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_UP_DONE_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_UP_DONE_MASK) /*! @} */ /* The count of CCM_CLOCK_GROUP_STATUS1 */ @@ -19141,8 +21181,9 @@ typedef struct { /*! @name CLOCK_GROUP_CONFIG - Clock group configuration */ /*! @{ */ -#define CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT_MASK (0x1U) -#define CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT_SHIFT (0U) + +#define CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT_MASK (0x10U) +#define CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT_SHIFT (4U) /*! SETPOINT_PRESENT - Setpoint present * 0b1..Setpoint is implemented. * 0b0..Setpoint is not implemented. @@ -19155,6 +21196,7 @@ typedef struct { /*! @name CLOCK_GROUP_AUTHEN - Clock group access control */ /*! @{ */ + #define CCM_CLOCK_GROUP_AUTHEN_TZ_USER_MASK (0x1U) #define CCM_CLOCK_GROUP_AUTHEN_TZ_USER_SHIFT (0U) /*! TZ_USER - User access @@ -19162,6 +21204,7 @@ typedef struct { * 0b0..Clock cannot be changed in user mode. */ #define CCM_CLOCK_GROUP_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TZ_USER_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TZ_USER_MASK) + #define CCM_CLOCK_GROUP_AUTHEN_TZ_NS_MASK (0x2U) #define CCM_CLOCK_GROUP_AUTHEN_TZ_NS_SHIFT (1U) /*! TZ_NS - Non-secure access @@ -19169,6 +21212,7 @@ typedef struct { * 0b1..Can be changed in Non-secure mode. */ #define CCM_CLOCK_GROUP_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TZ_NS_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TZ_NS_MASK) + #define CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ_MASK (0x10U) #define CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ_SHIFT (4U) /*! LOCK_TZ - Lock truszone setting @@ -19176,30 +21220,35 @@ typedef struct { * 0b1..Trustzone setting is locked. */ #define CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ_MASK) + #define CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST_MASK (0xF00U) #define CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST_SHIFT (8U) /*! WHITE_LIST - Whitelist */ #define CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST_MASK) + #define CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST_MASK (0x1000U) #define CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST_SHIFT (12U) -/*! LOCK_LIST - Lock whitelist +/*! LOCK_LIST - Lock Whitelist * 0b0..Whitelist is not locked. * 0b1..Whitelist is locked. */ #define CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST_MASK) + #define CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE_MASK (0x10000U) #define CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE_SHIFT (16U) /*! DOMAIN_MODE - Low power and access control by domain - * 0b1..Clock works in domain mode. - * 0b0..Clock does not work in domain mode. + * 0b1..Clock works in Domain Mode. + * 0b0..Clock does not work in Domain Mode. */ #define CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE_MASK) + #define CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE_MASK (0x20000U) #define CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE_SHIFT (17U) -/*! SETPOINT_MODE - Low power and access control by setpoint +/*! SETPOINT_MODE - Low power and access control by Setpoint */ #define CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE_MASK) + #define CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE_MASK (0x100000U) #define CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE_SHIFT (20U) /*! LOCK_MODE - Lock low power and access mode @@ -19214,41 +21263,49 @@ typedef struct { /*! @name CLOCK_GROUP_AUTHEN_SET - Clock group access control */ /*! @{ */ + #define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER_MASK (0x1U) #define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER_SHIFT (0U) /*! TZ_USER - User access */ #define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER_MASK) + #define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS_MASK (0x2U) #define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS_SHIFT (1U) /*! TZ_NS - Non-secure access */ #define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS_MASK) + #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ_MASK (0x10U) #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ_SHIFT (4U) /*! LOCK_TZ - Lock truszone setting */ #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ_MASK) + #define CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST_MASK (0xF00U) #define CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST_SHIFT (8U) /*! WHITE_LIST - Whitelist */ #define CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST_MASK) + #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST_MASK (0x1000U) #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST_SHIFT (12U) -/*! LOCK_LIST - Lock whitelist +/*! LOCK_LIST - Lock Whitelist */ #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST_MASK) + #define CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U) #define CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U) /*! DOMAIN_MODE - Low power and access control by domain */ #define CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE_MASK) + #define CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE_MASK (0x20000U) #define CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE_SHIFT (17U) -/*! SETPOINT_MODE - Low power and access control by setpoint +/*! SETPOINT_MODE - Low power and access control by Setpoint */ #define CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE_MASK) + #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE_MASK (0x100000U) #define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE_SHIFT (20U) /*! LOCK_MODE - Lock low power and access mode @@ -19261,41 +21318,49 @@ typedef struct { /*! @name CLOCK_GROUP_AUTHEN_CLR - Clock group access control */ /*! @{ */ + #define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER_MASK (0x1U) #define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER_SHIFT (0U) /*! TZ_USER - User access */ #define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER_MASK) + #define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS_MASK (0x2U) #define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS_SHIFT (1U) /*! TZ_NS - Non-secure access */ #define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS_MASK) + #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ_MASK (0x10U) #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ_SHIFT (4U) /*! LOCK_TZ - Lock truszone setting */ #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ_MASK) + #define CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U) #define CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST_SHIFT (8U) /*! WHITE_LIST - Whitelist */ #define CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST_MASK) + #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U) #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST_SHIFT (12U) -/*! LOCK_LIST - Lock whitelist +/*! LOCK_LIST - Lock Whitelist */ #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST_MASK) + #define CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U) #define CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U) /*! DOMAIN_MODE - Low power and access control by domain */ #define CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE_MASK) + #define CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE_MASK (0x20000U) #define CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE_SHIFT (17U) -/*! SETPOINT_MODE - Low power and access control by setpoint +/*! SETPOINT_MODE - Low power and access control by Setpoint */ #define CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE_MASK) + #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U) #define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE_SHIFT (20U) /*! LOCK_MODE - Lock low power and access mode @@ -19308,41 +21373,49 @@ typedef struct { /*! @name CLOCK_GROUP_AUTHEN_TOG - Clock group access control */ /*! @{ */ + #define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER_MASK (0x1U) #define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER_SHIFT (0U) /*! TZ_USER - User access */ #define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER_MASK) + #define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS_MASK (0x2U) #define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS_SHIFT (1U) /*! TZ_NS - Non-secure access */ #define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS_MASK) + #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ_MASK (0x10U) #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ_SHIFT (4U) /*! LOCK_TZ - Lock truszone setting */ #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ_MASK) + #define CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U) #define CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST_SHIFT (8U) /*! WHITE_LIST - Whitelist */ #define CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST_MASK) + #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U) #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST_SHIFT (12U) -/*! LOCK_LIST - Lock whitelist +/*! LOCK_LIST - Lock Whitelist */ #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST_MASK) + #define CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U) #define CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U) /*! DOMAIN_MODE - Low power and access control by domain */ #define CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE_MASK) + #define CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE_MASK (0x20000U) #define CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE_SHIFT (17U) -/*! SETPOINT_MODE - Low power and access control by setpoint +/*! SETPOINT_MODE - Low power and access control by Setpoint */ #define CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE_MASK) + #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U) #define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE_SHIFT (20U) /*! LOCK_MODE - Lock low power and access mode @@ -19353,8 +21426,50 @@ typedef struct { /* The count of CCM_CLOCK_GROUP_AUTHEN_TOG */ #define CCM_CLOCK_GROUP_AUTHEN_TOG_COUNT (2U) +/*! @name CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT - Setpoint setting */ +/*! @{ */ + +#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0_MASK (0xFU) +#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0_SHIFT (0U) +/*! DIV0 - Clock divider + * 0b0000..Direct output. + * 0b0001..Divide by 2. + * 0b0010..Divide by 3. + * 0b0011..Divide by 4. + * 0b1111..Divide by 16. + */ +#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0_MASK) + +#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV_MASK (0xFF0000U) +#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV_SHIFT (16U) +/*! RSTDIV - Clock group global restart count + */ +#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV_MASK) + +#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF_MASK (0x1000000U) +#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF_SHIFT (24U) +/*! OFF - OFF + * 0b0..Clock is running. + * 0b1..Turn off clock. + */ +#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF_SHIFT)) & CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF_MASK) + +#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE_MASK (0xF0000000U) +#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE_SHIFT (28U) +/*! GRADE - Grade + */ +#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE_SHIFT)) & CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE_MASK) +/*! @} */ + +/* The count of CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT */ +#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_COUNT (2U) + +/* The count of CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT */ +#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_COUNT2 (16U) + /*! @name GPR_SHARED - General Purpose Register */ /*! @{ */ + #define CCM_GPR_SHARED_GPR_MASK (0xFFFFFFFFU) #define CCM_GPR_SHARED_GPR_SHIFT (0U) /*! GPR - GP register @@ -19367,6 +21482,7 @@ typedef struct { /*! @name GPR_SHARED_SET - General Purpose Register */ /*! @{ */ + #define CCM_GPR_SHARED_SET_GPR_MASK (0xFFFFFFFFU) #define CCM_GPR_SHARED_SET_GPR_SHIFT (0U) /*! GPR - GP register @@ -19379,6 +21495,7 @@ typedef struct { /*! @name GPR_SHARED_CLR - General Purpose Register */ /*! @{ */ + #define CCM_GPR_SHARED_CLR_GPR_MASK (0xFFFFFFFFU) #define CCM_GPR_SHARED_CLR_GPR_SHIFT (0U) /*! GPR - GP register @@ -19391,6 +21508,7 @@ typedef struct { /*! @name GPR_SHARED_TOG - General Purpose Register */ /*! @{ */ + #define CCM_GPR_SHARED_TOG_GPR_MASK (0xFFFFFFFFU) #define CCM_GPR_SHARED_TOG_GPR_SHIFT (0U) /*! GPR - GP register @@ -19403,6 +21521,7 @@ typedef struct { /*! @name GPR_SHARED_AUTHEN - GPR access control */ /*! @{ */ + #define CCM_GPR_SHARED_AUTHEN_TZ_USER_MASK (0x1U) #define CCM_GPR_SHARED_AUTHEN_TZ_USER_SHIFT (0U) /*! TZ_USER - User access @@ -19410,6 +21529,7 @@ typedef struct { * 0b0..Clock cannot be changed in user mode. */ #define CCM_GPR_SHARED_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TZ_USER_MASK) + #define CCM_GPR_SHARED_AUTHEN_TZ_NS_MASK (0x2U) #define CCM_GPR_SHARED_AUTHEN_TZ_NS_SHIFT (1U) /*! TZ_NS - Non-secure access @@ -19417,6 +21537,7 @@ typedef struct { * 0b1..Can be changed in Non-secure mode. */ #define CCM_GPR_SHARED_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TZ_NS_MASK) + #define CCM_GPR_SHARED_AUTHEN_LOCK_TZ_MASK (0x10U) #define CCM_GPR_SHARED_AUTHEN_LOCK_TZ_SHIFT (4U) /*! LOCK_TZ - Lock truszone setting @@ -19424,6 +21545,7 @@ typedef struct { * 0b1..Trustzone setting is locked. */ #define CCM_GPR_SHARED_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_AUTHEN_LOCK_TZ_MASK) + #define CCM_GPR_SHARED_AUTHEN_WHITE_LIST_MASK (0xF00U) #define CCM_GPR_SHARED_AUTHEN_WHITE_LIST_SHIFT (8U) /*! WHITE_LIST - Whitelist @@ -19431,6 +21553,7 @@ typedef struct { * 0b0001..This domain is allowed to change clock. */ #define CCM_GPR_SHARED_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_WHITE_LIST_MASK) + #define CCM_GPR_SHARED_AUTHEN_LOCK_LIST_MASK (0x1000U) #define CCM_GPR_SHARED_AUTHEN_LOCK_LIST_SHIFT (12U) /*! LOCK_LIST - Lock Whitelist @@ -19438,13 +21561,15 @@ typedef struct { * 0b1..Whitelist is locked. */ #define CCM_GPR_SHARED_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_LOCK_LIST_MASK) + #define CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE_MASK (0x10000U) #define CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE_SHIFT (16U) /*! DOMAIN_MODE - Low power and access control by domain - * 0b1..Clock works in domain mode. - * 0b0..Clock does NOT work in domain mode. + * 0b1..Clock works in Domain Mode. + * 0b0..Clock does NOT work in Domain Mode. */ #define CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE_MASK) + #define CCM_GPR_SHARED_AUTHEN_LOCK_MODE_MASK (0x100000U) #define CCM_GPR_SHARED_AUTHEN_LOCK_MODE_SHIFT (20U) /*! LOCK_MODE - Lock low power and access mode @@ -19459,36 +21584,43 @@ typedef struct { /*! @name GPR_SHARED_AUTHEN_SET - GPR access control */ /*! @{ */ + #define CCM_GPR_SHARED_AUTHEN_SET_TZ_USER_MASK (0x1U) #define CCM_GPR_SHARED_AUTHEN_SET_TZ_USER_SHIFT (0U) /*! TZ_USER - User access */ #define CCM_GPR_SHARED_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_TZ_USER_MASK) + #define CCM_GPR_SHARED_AUTHEN_SET_TZ_NS_MASK (0x2U) #define CCM_GPR_SHARED_AUTHEN_SET_TZ_NS_SHIFT (1U) /*! TZ_NS - Non-secure access */ #define CCM_GPR_SHARED_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_TZ_NS_MASK) + #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ_MASK (0x10U) #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ_SHIFT (4U) /*! LOCK_TZ - Lock truszone setting */ #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ_MASK) + #define CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST_MASK (0xF00U) #define CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST_SHIFT (8U) /*! WHITE_LIST - Whitelist */ #define CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST_MASK) + #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST_MASK (0x1000U) #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST_SHIFT (12U) /*! LOCK_LIST - Lock Whitelist */ #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST_MASK) + #define CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U) #define CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U) /*! DOMAIN_MODE - Low power and access control by domain */ #define CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE_MASK) + #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE_MASK (0x100000U) #define CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE_SHIFT (20U) /*! LOCK_MODE - Lock low power and access mode @@ -19501,36 +21633,43 @@ typedef struct { /*! @name GPR_SHARED_AUTHEN_CLR - GPR access control */ /*! @{ */ + #define CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER_MASK (0x1U) #define CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER_SHIFT (0U) /*! TZ_USER - User access */ #define CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER_MASK) + #define CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS_MASK (0x2U) #define CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS_SHIFT (1U) /*! TZ_NS - Non-secure access */ #define CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS_MASK) + #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ_MASK (0x10U) #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ_SHIFT (4U) /*! LOCK_TZ - Lock truszone setting */ #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ_MASK) + #define CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U) #define CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST_SHIFT (8U) /*! WHITE_LIST - Whitelist */ #define CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST_MASK) + #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U) #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST_SHIFT (12U) /*! LOCK_LIST - Lock Whitelist */ #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST_MASK) + #define CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U) #define CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U) /*! DOMAIN_MODE - Low power and access control by domain */ #define CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE_MASK) + #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U) #define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE_SHIFT (20U) /*! LOCK_MODE - Lock low power and access mode @@ -19543,36 +21682,43 @@ typedef struct { /*! @name GPR_SHARED_AUTHEN_TOG - GPR access control */ /*! @{ */ + #define CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER_MASK (0x1U) #define CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER_SHIFT (0U) /*! TZ_USER - User access */ #define CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER_MASK) + #define CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS_MASK (0x2U) #define CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS_SHIFT (1U) /*! TZ_NS - Non-secure access */ #define CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS_MASK) + #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ_MASK (0x10U) #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ_SHIFT (4U) /*! LOCK_TZ - Lock truszone setting */ #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ_MASK) + #define CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U) #define CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST_SHIFT (8U) /*! WHITE_LIST - Whitelist */ #define CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST_MASK) + #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U) #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST_SHIFT (12U) /*! LOCK_LIST - Lock Whitelist */ #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST_MASK) + #define CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U) #define CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U) /*! DOMAIN_MODE - Low power and access control by domain */ #define CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE_MASK) + #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U) #define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE_SHIFT (20U) /*! LOCK_MODE - Lock low power and access mode @@ -19583,7127 +21729,11763 @@ typedef struct { /* The count of CCM_GPR_SHARED_AUTHEN_TOG */ #define CCM_GPR_SHARED_AUTHEN_TOG_COUNT (8U) -/*! @name GPR_PRIVATE - General puspose register */ +/*! @name GPR_PRIVATE1 - General Purpose Register */ /*! @{ */ -#define CCM_GPR_PRIVATE_GPR_MASK (0xFFFFFFFFU) -#define CCM_GPR_PRIVATE_GPR_SHIFT (0U) + +#define CCM_GPR_PRIVATE1_GPR_MASK (0xFFFFFFFFU) +#define CCM_GPR_PRIVATE1_GPR_SHIFT (0U) /*! GPR - GP register */ -#define CCM_GPR_PRIVATE_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_GPR_SHIFT)) & CCM_GPR_PRIVATE_GPR_MASK) +#define CCM_GPR_PRIVATE1_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_GPR_SHIFT)) & CCM_GPR_PRIVATE1_GPR_MASK) /*! @} */ -/* The count of CCM_GPR_PRIVATE */ -#define CCM_GPR_PRIVATE_COUNT (8U) - -/*! @name GPR_PRIVATE_SET - General puspose register */ +/*! @name GPR_PRIVATE1_SET - General Purpose Register */ /*! @{ */ -#define CCM_GPR_PRIVATE_SET_GPR_MASK (0xFFFFFFFFU) -#define CCM_GPR_PRIVATE_SET_GPR_SHIFT (0U) + +#define CCM_GPR_PRIVATE1_SET_GPR_MASK (0xFFFFFFFFU) +#define CCM_GPR_PRIVATE1_SET_GPR_SHIFT (0U) /*! GPR - GP register */ -#define CCM_GPR_PRIVATE_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE_SET_GPR_MASK) +#define CCM_GPR_PRIVATE1_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE1_SET_GPR_MASK) /*! @} */ -/* The count of CCM_GPR_PRIVATE_SET */ -#define CCM_GPR_PRIVATE_SET_COUNT (8U) - -/*! @name GPR_PRIVATE_CLR - General puspose register */ +/*! @name GPR_PRIVATE1_CLR - General Purpose Register */ /*! @{ */ -#define CCM_GPR_PRIVATE_CLR_GPR_MASK (0xFFFFFFFFU) -#define CCM_GPR_PRIVATE_CLR_GPR_SHIFT (0U) + +#define CCM_GPR_PRIVATE1_CLR_GPR_MASK (0xFFFFFFFFU) +#define CCM_GPR_PRIVATE1_CLR_GPR_SHIFT (0U) /*! GPR - GP register */ -#define CCM_GPR_PRIVATE_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE_CLR_GPR_MASK) +#define CCM_GPR_PRIVATE1_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE1_CLR_GPR_MASK) /*! @} */ -/* The count of CCM_GPR_PRIVATE_CLR */ -#define CCM_GPR_PRIVATE_CLR_COUNT (8U) - -/*! @name GPR_PRIVATE_TOG - General puspose register */ +/*! @name GPR_PRIVATE1_TOG - General Purpose Register */ /*! @{ */ -#define CCM_GPR_PRIVATE_TOG_GPR_MASK (0xFFFFFFFFU) -#define CCM_GPR_PRIVATE_TOG_GPR_SHIFT (0U) + +#define CCM_GPR_PRIVATE1_TOG_GPR_MASK (0xFFFFFFFFU) +#define CCM_GPR_PRIVATE1_TOG_GPR_SHIFT (0U) /*! GPR - GP register */ -#define CCM_GPR_PRIVATE_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE_TOG_GPR_MASK) +#define CCM_GPR_PRIVATE1_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE1_TOG_GPR_MASK) /*! @} */ -/* The count of CCM_GPR_PRIVATE_TOG */ -#define CCM_GPR_PRIVATE_TOG_COUNT (8U) - -/*! @name GPR_PRIVATE_AUTHEN - GPR access control */ +/*! @name GPR_PRIVATE1_AUTHEN - GPR access control */ /*! @{ */ -#define CCM_GPR_PRIVATE_AUTHEN_TZ_USER_MASK (0x1U) -#define CCM_GPR_PRIVATE_AUTHEN_TZ_USER_SHIFT (0U) + +#define CCM_GPR_PRIVATE1_AUTHEN_TZ_USER_MASK (0x1U) +#define CCM_GPR_PRIVATE1_AUTHEN_TZ_USER_SHIFT (0U) /*! TZ_USER - User access * 0b1..Clock can be changed in user mode. * 0b0..Clock cannot be changed in user mode. */ -#define CCM_GPR_PRIVATE_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_TZ_USER_MASK) -#define CCM_GPR_PRIVATE_AUTHEN_TZ_NS_MASK (0x2U) -#define CCM_GPR_PRIVATE_AUTHEN_TZ_NS_SHIFT (1U) +#define CCM_GPR_PRIVATE1_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TZ_USER_MASK) + +#define CCM_GPR_PRIVATE1_AUTHEN_TZ_NS_MASK (0x2U) +#define CCM_GPR_PRIVATE1_AUTHEN_TZ_NS_SHIFT (1U) /*! TZ_NS - Non-secure access * 0b0..Cannot be changed in Non-secure mode. * 0b1..Can be changed in Non-secure mode. */ -#define CCM_GPR_PRIVATE_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_TZ_NS_MASK) -#define CCM_GPR_PRIVATE_AUTHEN_LOCK_TZ_MASK (0x10U) -#define CCM_GPR_PRIVATE_AUTHEN_LOCK_TZ_SHIFT (4U) +#define CCM_GPR_PRIVATE1_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TZ_NS_MASK) + +#define CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ_MASK (0x10U) +#define CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ_SHIFT (4U) /*! LOCK_TZ - Lock truszone setting * 0b0..Trustzone setting is not locked. * 0b1..Trustzone setting is locked. */ -#define CCM_GPR_PRIVATE_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_LOCK_TZ_MASK) -#define CCM_GPR_PRIVATE_AUTHEN_WHITE_LIST_MASK (0xF00U) -#define CCM_GPR_PRIVATE_AUTHEN_WHITE_LIST_SHIFT (8U) +#define CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ_MASK) + +#define CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST_MASK (0xF00U) +#define CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST_SHIFT (8U) /*! WHITE_LIST - Whitelist * 0b0000..This domain is NOT allowed to change clock. * 0b0001..This domain is allowed to change clock. */ -#define CCM_GPR_PRIVATE_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_WHITE_LIST_MASK) -#define CCM_GPR_PRIVATE_AUTHEN_LOCK_LIST_MASK (0x1000U) -#define CCM_GPR_PRIVATE_AUTHEN_LOCK_LIST_SHIFT (12U) -/*! LOCK_LIST - Lock white list +#define CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST_MASK) + +#define CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST_MASK (0x1000U) +#define CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock Whitelist * 0b0..Whitelist is not locked. * 0b1..Whitelist is locked. */ -#define CCM_GPR_PRIVATE_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_LOCK_LIST_MASK) -#define CCM_GPR_PRIVATE_AUTHEN_DOMAIN_MODE_MASK (0x10000U) -#define CCM_GPR_PRIVATE_AUTHEN_DOMAIN_MODE_SHIFT (16U) -/*! DOMAIN_MODE - Low power and access control by domain - * 0b1..Clock works in domain mode. - * 0b0..Clock does NOT work in domain mode. +#define CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST_MASK) + +#define CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE_MASK (0x10000U) +#define CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by Domain + * 0b1..Clock works in Domain Mode. + * 0b0..Clock does NOT work in Domain Mode. */ -#define CCM_GPR_PRIVATE_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_DOMAIN_MODE_MASK) -#define CCM_GPR_PRIVATE_AUTHEN_LOCK_MODE_MASK (0x100000U) -#define CCM_GPR_PRIVATE_AUTHEN_LOCK_MODE_SHIFT (20U) +#define CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE_MASK) + +#define CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE_MASK (0x100000U) +#define CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE_SHIFT (20U) /*! LOCK_MODE - Lock low power and access mode * 0b0..MODE is not locked. * 0b1..MODE is locked. */ -#define CCM_GPR_PRIVATE_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_LOCK_MODE_MASK) +#define CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE_MASK) /*! @} */ -/* The count of CCM_GPR_PRIVATE_AUTHEN */ -#define CCM_GPR_PRIVATE_AUTHEN_COUNT (8U) - -/*! @name GPR_PRIVATE_AUTHEN_SET - GPR access control */ +/*! @name GPR_PRIVATE1_AUTHEN_SET - GPR access control */ /*! @{ */ -#define CCM_GPR_PRIVATE_AUTHEN_SET_TZ_USER_MASK (0x1U) -#define CCM_GPR_PRIVATE_AUTHEN_SET_TZ_USER_SHIFT (0U) + +#define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER_MASK (0x1U) +#define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER_SHIFT (0U) /*! TZ_USER - User access */ -#define CCM_GPR_PRIVATE_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_SET_TZ_USER_MASK) -#define CCM_GPR_PRIVATE_AUTHEN_SET_TZ_NS_MASK (0x2U) -#define CCM_GPR_PRIVATE_AUTHEN_SET_TZ_NS_SHIFT (1U) +#define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER_MASK) + +#define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS_MASK (0x2U) +#define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS_SHIFT (1U) /*! TZ_NS - Non-secure access */ -#define CCM_GPR_PRIVATE_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_SET_TZ_NS_MASK) -#define CCM_GPR_PRIVATE_AUTHEN_SET_LOCK_TZ_MASK (0x10U) -#define CCM_GPR_PRIVATE_AUTHEN_SET_LOCK_TZ_SHIFT (4U) +#define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS_MASK) + +#define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ_MASK (0x10U) +#define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ_SHIFT (4U) /*! LOCK_TZ - Lock truszone setting */ -#define CCM_GPR_PRIVATE_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_SET_LOCK_TZ_MASK) -#define CCM_GPR_PRIVATE_AUTHEN_SET_WHITE_LIST_MASK (0xF00U) -#define CCM_GPR_PRIVATE_AUTHEN_SET_WHITE_LIST_SHIFT (8U) +#define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ_MASK) + +#define CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST_MASK (0xF00U) +#define CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST_SHIFT (8U) /*! WHITE_LIST - Whitelist */ -#define CCM_GPR_PRIVATE_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_SET_WHITE_LIST_MASK) -#define CCM_GPR_PRIVATE_AUTHEN_SET_LOCK_LIST_MASK (0x1000U) -#define CCM_GPR_PRIVATE_AUTHEN_SET_LOCK_LIST_SHIFT (12U) -/*! LOCK_LIST - Lock white list +#define CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST_MASK) + +#define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST_MASK (0x1000U) +#define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock Whitelist */ -#define CCM_GPR_PRIVATE_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_SET_LOCK_LIST_MASK) -#define CCM_GPR_PRIVATE_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U) -#define CCM_GPR_PRIVATE_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U) -/*! DOMAIN_MODE - Low power and access control by domain +#define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST_MASK) + +#define CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U) +#define CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by Domain */ -#define CCM_GPR_PRIVATE_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_SET_DOMAIN_MODE_MASK) -#define CCM_GPR_PRIVATE_AUTHEN_SET_LOCK_MODE_MASK (0x100000U) -#define CCM_GPR_PRIVATE_AUTHEN_SET_LOCK_MODE_SHIFT (20U) +#define CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE_MASK) + +#define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE_MASK (0x100000U) +#define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE_SHIFT (20U) /*! LOCK_MODE - Lock low power and access mode */ -#define CCM_GPR_PRIVATE_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_SET_LOCK_MODE_MASK) +#define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE_MASK) /*! @} */ -/* The count of CCM_GPR_PRIVATE_AUTHEN_SET */ -#define CCM_GPR_PRIVATE_AUTHEN_SET_COUNT (8U) - -/*! @name GPR_PRIVATE_AUTHEN_CLR - GPR access control */ +/*! @name GPR_PRIVATE1_AUTHEN_CLR - GPR access control */ /*! @{ */ -#define CCM_GPR_PRIVATE_AUTHEN_CLR_TZ_USER_MASK (0x1U) -#define CCM_GPR_PRIVATE_AUTHEN_CLR_TZ_USER_SHIFT (0U) + +#define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER_MASK (0x1U) +#define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER_SHIFT (0U) /*! TZ_USER - User access */ -#define CCM_GPR_PRIVATE_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_CLR_TZ_USER_MASK) -#define CCM_GPR_PRIVATE_AUTHEN_CLR_TZ_NS_MASK (0x2U) -#define CCM_GPR_PRIVATE_AUTHEN_CLR_TZ_NS_SHIFT (1U) +#define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER_MASK) + +#define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS_MASK (0x2U) +#define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS_SHIFT (1U) /*! TZ_NS - Non-secure access */ -#define CCM_GPR_PRIVATE_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_CLR_TZ_NS_MASK) -#define CCM_GPR_PRIVATE_AUTHEN_CLR_LOCK_TZ_MASK (0x10U) -#define CCM_GPR_PRIVATE_AUTHEN_CLR_LOCK_TZ_SHIFT (4U) +#define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS_MASK) + +#define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ_MASK (0x10U) +#define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ_SHIFT (4U) /*! LOCK_TZ - Lock truszone setting */ -#define CCM_GPR_PRIVATE_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_CLR_LOCK_TZ_MASK) -#define CCM_GPR_PRIVATE_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U) -#define CCM_GPR_PRIVATE_AUTHEN_CLR_WHITE_LIST_SHIFT (8U) +#define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ_MASK) + +#define CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U) +#define CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST_SHIFT (8U) /*! WHITE_LIST - Whitelist */ -#define CCM_GPR_PRIVATE_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_CLR_WHITE_LIST_MASK) -#define CCM_GPR_PRIVATE_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U) -#define CCM_GPR_PRIVATE_AUTHEN_CLR_LOCK_LIST_SHIFT (12U) -/*! LOCK_LIST - Lock white list +#define CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST_MASK) + +#define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U) +#define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock Whitelist */ -#define CCM_GPR_PRIVATE_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_CLR_LOCK_LIST_MASK) -#define CCM_GPR_PRIVATE_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U) -#define CCM_GPR_PRIVATE_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U) -/*! DOMAIN_MODE - Low power and access control by domain +#define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST_MASK) + +#define CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U) +#define CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by Domain */ -#define CCM_GPR_PRIVATE_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_CLR_DOMAIN_MODE_MASK) -#define CCM_GPR_PRIVATE_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U) -#define CCM_GPR_PRIVATE_AUTHEN_CLR_LOCK_MODE_SHIFT (20U) +#define CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE_MASK) + +#define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U) +#define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE_SHIFT (20U) /*! LOCK_MODE - Lock low power and access mode */ -#define CCM_GPR_PRIVATE_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_CLR_LOCK_MODE_MASK) +#define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE_MASK) /*! @} */ -/* The count of CCM_GPR_PRIVATE_AUTHEN_CLR */ -#define CCM_GPR_PRIVATE_AUTHEN_CLR_COUNT (8U) - -/*! @name GPR_PRIVATE_AUTHEN_TOG - GPR access control */ +/*! @name GPR_PRIVATE1_AUTHEN_TOG - GPR access control */ /*! @{ */ -#define CCM_GPR_PRIVATE_AUTHEN_TOG_TZ_USER_MASK (0x1U) -#define CCM_GPR_PRIVATE_AUTHEN_TOG_TZ_USER_SHIFT (0U) + +#define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER_MASK (0x1U) +#define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER_SHIFT (0U) /*! TZ_USER - User access */ -#define CCM_GPR_PRIVATE_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_TOG_TZ_USER_MASK) -#define CCM_GPR_PRIVATE_AUTHEN_TOG_TZ_NS_MASK (0x2U) -#define CCM_GPR_PRIVATE_AUTHEN_TOG_TZ_NS_SHIFT (1U) +#define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER_MASK) + +#define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS_MASK (0x2U) +#define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS_SHIFT (1U) /*! TZ_NS - Non-secure access */ -#define CCM_GPR_PRIVATE_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_TOG_TZ_NS_MASK) -#define CCM_GPR_PRIVATE_AUTHEN_TOG_LOCK_TZ_MASK (0x10U) -#define CCM_GPR_PRIVATE_AUTHEN_TOG_LOCK_TZ_SHIFT (4U) +#define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS_MASK) + +#define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ_MASK (0x10U) +#define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ_SHIFT (4U) /*! LOCK_TZ - Lock truszone setting */ -#define CCM_GPR_PRIVATE_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_TOG_LOCK_TZ_MASK) -#define CCM_GPR_PRIVATE_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U) -#define CCM_GPR_PRIVATE_AUTHEN_TOG_WHITE_LIST_SHIFT (8U) +#define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ_MASK) + +#define CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U) +#define CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST_SHIFT (8U) /*! WHITE_LIST - Whitelist */ -#define CCM_GPR_PRIVATE_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_TOG_WHITE_LIST_MASK) -#define CCM_GPR_PRIVATE_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U) -#define CCM_GPR_PRIVATE_AUTHEN_TOG_LOCK_LIST_SHIFT (12U) -/*! LOCK_LIST - Lock white list +#define CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST_MASK) + +#define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U) +#define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock Whitelist */ -#define CCM_GPR_PRIVATE_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_TOG_LOCK_LIST_MASK) -#define CCM_GPR_PRIVATE_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U) -#define CCM_GPR_PRIVATE_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U) -/*! DOMAIN_MODE - Low power and access control by domain +#define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST_MASK) + +#define CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U) +#define CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by Domain */ -#define CCM_GPR_PRIVATE_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_TOG_DOMAIN_MODE_MASK) -#define CCM_GPR_PRIVATE_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U) -#define CCM_GPR_PRIVATE_AUTHEN_TOG_LOCK_MODE_SHIFT (20U) +#define CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE_MASK) + +#define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U) +#define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE_SHIFT (20U) /*! LOCK_MODE - Lock low power and access mode */ -#define CCM_GPR_PRIVATE_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE_AUTHEN_TOG_LOCK_MODE_MASK) +#define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE_MASK) /*! @} */ -/* The count of CCM_GPR_PRIVATE_AUTHEN_TOG */ -#define CCM_GPR_PRIVATE_AUTHEN_TOG_COUNT (8U) - -/*! @name OSCPLL_DIRECT - Clock source direct control */ +/*! @name GPR_PRIVATE2 - General Purpose Register */ /*! @{ */ -#define CCM_OSCPLL_DIRECT_ON_MASK (0x1U) -#define CCM_OSCPLL_DIRECT_ON_SHIFT (0U) -/*! ON - turn on clock source - * 0b0..LPCG is OFF. - * 0b1..LPCG is ON. + +#define CCM_GPR_PRIVATE2_GPR_MASK (0xFFFFFFFFU) +#define CCM_GPR_PRIVATE2_GPR_SHIFT (0U) +/*! GPR - GP register */ -#define CCM_OSCPLL_DIRECT_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DIRECT_ON_SHIFT)) & CCM_OSCPLL_DIRECT_ON_MASK) +#define CCM_GPR_PRIVATE2_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_GPR_SHIFT)) & CCM_GPR_PRIVATE2_GPR_MASK) /*! @} */ -/* The count of CCM_OSCPLL_DIRECT */ -#define CCM_OSCPLL_DIRECT_COUNT (29U) - -/*! @name OSCPLL_DOMAIN - Clock source domain control */ +/*! @name GPR_PRIVATE2_SET - General Purpose Register */ /*! @{ */ -#define CCM_OSCPLL_DOMAIN_LEVEL_MASK (0x3U) -#define CCM_OSCPLL_DOMAIN_LEVEL_SHIFT (0U) -/*! LEVEL - Current level - */ -#define CCM_OSCPLL_DOMAIN_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL_MASK) -#define CCM_OSCPLL_DOMAIN_LEVEL0_MASK (0x30000U) -#define CCM_OSCPLL_DOMAIN_LEVEL0_SHIFT (16U) -/*! LEVEL0 - Depend level - * 0b00..No need, can be off. - * 0b01..Need on when RUN. - * 0b10..Need on when RUN and WAIT. - * 0b11..Need on when RUN, WAIT and STOP. - */ -#define CCM_OSCPLL_DOMAIN_LEVEL0(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL0_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL0_MASK) -#define CCM_OSCPLL_DOMAIN_LEVEL1_MASK (0x300000U) -#define CCM_OSCPLL_DOMAIN_LEVEL1_SHIFT (20U) -/*! LEVEL1 - Depend level - * 0b00..No need, can be off. - * 0b01..Need on when RUN. - * 0b10..Need on when RUN and WAIT. - * 0b11..Need on when RUN, WAIT and STOP. - */ -#define CCM_OSCPLL_DOMAIN_LEVEL1(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL1_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL1_MASK) -#define CCM_OSCPLL_DOMAIN_LEVEL2_MASK (0x3000000U) -#define CCM_OSCPLL_DOMAIN_LEVEL2_SHIFT (24U) -/*! LEVEL2 - Depend level - * 0b00..No need, can be off. - * 0b01..Need on when RUN. - * 0b10..Need on when RUN and WAIT. - * 0b11..Need on when RUN, WAIT and STOP. - */ -#define CCM_OSCPLL_DOMAIN_LEVEL2(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL2_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL2_MASK) -#define CCM_OSCPLL_DOMAIN_LEVEL3_MASK (0x30000000U) -#define CCM_OSCPLL_DOMAIN_LEVEL3_SHIFT (28U) -/*! LEVEL3 - Depend level - * 0b00..No need, can be off. - * 0b01..Need on when RUN. - * 0b10..Need on when RUN and WAIT. - * 0b11..Need on when RUN, WAIT and STOP. + +#define CCM_GPR_PRIVATE2_SET_GPR_MASK (0xFFFFFFFFU) +#define CCM_GPR_PRIVATE2_SET_GPR_SHIFT (0U) +/*! GPR - GP register */ -#define CCM_OSCPLL_DOMAIN_LEVEL3(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL3_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL3_MASK) +#define CCM_GPR_PRIVATE2_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE2_SET_GPR_MASK) /*! @} */ -/* The count of CCM_OSCPLL_DOMAIN */ -#define CCM_OSCPLL_DOMAIN_COUNT (29U) - -/*! @name OSCPLL_SETPOINT - Clock source setpoint setting */ +/*! @name GPR_PRIVATE2_CLR - General Purpose Register */ /*! @{ */ -#define CCM_OSCPLL_SETPOINT_SETPOINT_MASK (0xFFFFU) -#define CCM_OSCPLL_SETPOINT_SETPOINT_SHIFT (0U) -/*! SETPOINT - Setpoint - */ -#define CCM_OSCPLL_SETPOINT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_SETPOINT_SETPOINT_SHIFT)) & CCM_OSCPLL_SETPOINT_SETPOINT_MASK) -#define CCM_OSCPLL_SETPOINT_STANDBY_MASK (0xFFFF0000U) -#define CCM_OSCPLL_SETPOINT_STANDBY_SHIFT (16U) -/*! STANDBY - Standby + +#define CCM_GPR_PRIVATE2_CLR_GPR_MASK (0xFFFFFFFFU) +#define CCM_GPR_PRIVATE2_CLR_GPR_SHIFT (0U) +/*! GPR - GP register */ -#define CCM_OSCPLL_SETPOINT_STANDBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_SETPOINT_STANDBY_SHIFT)) & CCM_OSCPLL_SETPOINT_STANDBY_MASK) +#define CCM_GPR_PRIVATE2_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE2_CLR_GPR_MASK) /*! @} */ -/* The count of CCM_OSCPLL_SETPOINT */ -#define CCM_OSCPLL_SETPOINT_COUNT (29U) +/*! @name GPR_PRIVATE2_TOG - General Purpose Register */ +/*! @{ */ -/*! @name OSCPLL_STATUS0 - Clock source working status */ +#define CCM_GPR_PRIVATE2_TOG_GPR_MASK (0xFFFFFFFFU) +#define CCM_GPR_PRIVATE2_TOG_GPR_SHIFT (0U) +/*! GPR - GP register + */ +#define CCM_GPR_PRIVATE2_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE2_TOG_GPR_MASK) +/*! @} */ + +/*! @name GPR_PRIVATE2_AUTHEN - GPR access control */ /*! @{ */ -#define CCM_OSCPLL_STATUS0_ON_MASK (0x1U) -#define CCM_OSCPLL_STATUS0_ON_SHIFT (0U) -/*! ON - Clock source current state - * 0b0..Clock source is OFF. - * 0b1..Clock source is ON. + +#define CCM_GPR_PRIVATE2_AUTHEN_TZ_USER_MASK (0x1U) +#define CCM_GPR_PRIVATE2_AUTHEN_TZ_USER_SHIFT (0U) +/*! TZ_USER - User access + * 0b1..Clock can be changed in user mode. + * 0b0..Clock cannot be changed in user mode. */ -#define CCM_OSCPLL_STATUS0_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_ON_SHIFT)) & CCM_OSCPLL_STATUS0_ON_MASK) -#define CCM_OSCPLL_STATUS0_STATUS_EARLY_MASK (0x10U) -#define CCM_OSCPLL_STATUS0_STATUS_EARLY_SHIFT (4U) -/*! STATUS_EARLY - Clock source active +#define CCM_GPR_PRIVATE2_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TZ_USER_MASK) + +#define CCM_GPR_PRIVATE2_AUTHEN_TZ_NS_MASK (0x2U) +#define CCM_GPR_PRIVATE2_AUTHEN_TZ_NS_SHIFT (1U) +/*! TZ_NS - Non-secure access + * 0b0..Cannot be changed in Non-secure mode. + * 0b1..Can be changed in Non-secure mode. */ -#define CCM_OSCPLL_STATUS0_STATUS_EARLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_STATUS_EARLY_SHIFT)) & CCM_OSCPLL_STATUS0_STATUS_EARLY_MASK) -#define CCM_OSCPLL_STATUS0_STATUS_LATE_MASK (0x20U) -#define CCM_OSCPLL_STATUS0_STATUS_LATE_SHIFT (5U) -/*! STATUS_LATE - Clock source ready +#define CCM_GPR_PRIVATE2_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TZ_NS_MASK) + +#define CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ_MASK (0x10U) +#define CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ_SHIFT (4U) +/*! LOCK_TZ - Lock truszone setting + * 0b0..Trustzone setting is not locked. + * 0b1..Trustzone setting is locked. */ -#define CCM_OSCPLL_STATUS0_STATUS_LATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_STATUS_LATE_SHIFT)) & CCM_OSCPLL_STATUS0_STATUS_LATE_MASK) -#define CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_MASK (0xF00U) -#define CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_SHIFT (8U) -/*! ACTIVE_DOMAIN - Domains that own this clock source +#define CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ_MASK) + +#define CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST_MASK (0xF00U) +#define CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST_SHIFT (8U) +/*! WHITE_LIST - Whitelist + * 0b0000..This domain is NOT allowed to change clock. + * 0b0001..This domain is allowed to change clock. */ -#define CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_SHIFT)) & CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_MASK) -#define CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_MASK (0xF000U) -#define CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_SHIFT (12U) -/*! DOMAIN_ENABLE - Enable status from each domain +#define CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST_MASK) + +#define CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST_MASK (0x1000U) +#define CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock Whitelist + * 0b0..Whitelist is not locked. + * 0b1..Whitelist is locked. */ -#define CCM_OSCPLL_STATUS0_DOMAIN_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_SHIFT)) & CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_MASK) -#define CCM_OSCPLL_STATUS0_IN_USE_MASK (0x10000000U) -#define CCM_OSCPLL_STATUS0_IN_USE_SHIFT (28U) -/*! IN_USE - In use +#define CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST_MASK) + +#define CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE_MASK (0x10000U) +#define CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by Domain + * 0b1..Clock works in Domain Mode. + * 0b0..Clock does NOT work in Domain Mode. */ -#define CCM_OSCPLL_STATUS0_IN_USE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_IN_USE_SHIFT)) & CCM_OSCPLL_STATUS0_IN_USE_MASK) -/*! @} */ +#define CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE_MASK) -/* The count of CCM_OSCPLL_STATUS0 */ -#define CCM_OSCPLL_STATUS0_COUNT (29U) +#define CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE_MASK (0x100000U) +#define CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE_SHIFT (20U) +/*! LOCK_MODE - Lock low power and access mode + * 0b0..MODE is not locked. + * 0b1..MODE is locked. + */ +#define CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE_MASK) +/*! @} */ -/*! @name OSCPLL_STATUS1 - Clock source low power status */ +/*! @name GPR_PRIVATE2_AUTHEN_SET - GPR access control */ /*! @{ */ -#define CCM_OSCPLL_STATUS1_CPU0_MODE_MASK (0x3U) -#define CCM_OSCPLL_STATUS1_CPU0_MODE_SHIFT (0U) -/*! CPU0_MODE - Domain0 low power mode + +#define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER_MASK (0x1U) +#define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER_SHIFT (0U) +/*! TZ_USER - User access */ -#define CCM_OSCPLL_STATUS1_CPU0_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU0_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU0_MODE_MASK) -#define CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_MASK (0x4U) -#define CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_SHIFT (2U) -/*! CPU0_MODE_REQUEST - Domain0 request enter low power mode +#define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER_MASK) + +#define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS_MASK (0x2U) +#define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS_SHIFT (1U) +/*! TZ_NS - Non-secure access */ -#define CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_MASK) -#define CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_MASK (0x8U) -#define CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_SHIFT (3U) -/*! CPU0_MODE_DONE - Domain0 low power mode task done +#define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS_MASK) + +#define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ_MASK (0x10U) +#define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ_SHIFT (4U) +/*! LOCK_TZ - Lock truszone setting */ -#define CCM_OSCPLL_STATUS1_CPU0_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_MASK) -#define CCM_OSCPLL_STATUS1_CPU1_MODE_MASK (0x30U) -#define CCM_OSCPLL_STATUS1_CPU1_MODE_SHIFT (4U) -/*! CPU1_MODE - Domain1 low power mode +#define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ_MASK) + +#define CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST_MASK (0xF00U) +#define CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST_SHIFT (8U) +/*! WHITE_LIST - Whitelist */ -#define CCM_OSCPLL_STATUS1_CPU1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU1_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU1_MODE_MASK) -#define CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_MASK (0x40U) -#define CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_SHIFT (6U) -/*! CPU1_MODE_REQUEST - Domain1 request enter low power mode +#define CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST_MASK) + +#define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST_MASK (0x1000U) +#define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock Whitelist */ -#define CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_MASK) -#define CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_MASK (0x80U) -#define CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_SHIFT (7U) -/*! CPU1_MODE_DONE - Domain1 low power mode task done +#define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST_MASK) + +#define CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U) +#define CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by Domain */ -#define CCM_OSCPLL_STATUS1_CPU1_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_MASK) -#define CCM_OSCPLL_STATUS1_CPU2_MODE_MASK (0x300U) -#define CCM_OSCPLL_STATUS1_CPU2_MODE_SHIFT (8U) -/*! CPU2_MODE - Domain2 low power mode +#define CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE_MASK) + +#define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE_MASK (0x100000U) +#define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE_SHIFT (20U) +/*! LOCK_MODE - Lock low power and access mode */ -#define CCM_OSCPLL_STATUS1_CPU2_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU2_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU2_MODE_MASK) -#define CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_MASK (0x400U) -#define CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_SHIFT (10U) -/*! CPU2_MODE_REQUEST - Domain2 request enter low power mode +#define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE_MASK) +/*! @} */ + +/*! @name GPR_PRIVATE2_AUTHEN_CLR - GPR access control */ +/*! @{ */ + +#define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER_MASK (0x1U) +#define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER_SHIFT (0U) +/*! TZ_USER - User access */ -#define CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_MASK) -#define CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_MASK (0x800U) -#define CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_SHIFT (11U) -/*! CPU2_MODE_DONE - Domain2 low power mode task done +#define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER_MASK) + +#define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS_MASK (0x2U) +#define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS_SHIFT (1U) +/*! TZ_NS - Non-secure access */ -#define CCM_OSCPLL_STATUS1_CPU2_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_MASK) -#define CCM_OSCPLL_STATUS1_CPU3_MODE_MASK (0x3000U) -#define CCM_OSCPLL_STATUS1_CPU3_MODE_SHIFT (12U) -/*! CPU3_MODE - Domain3 low power mode +#define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS_MASK) + +#define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ_MASK (0x10U) +#define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ_SHIFT (4U) +/*! LOCK_TZ - Lock truszone setting */ -#define CCM_OSCPLL_STATUS1_CPU3_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU3_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU3_MODE_MASK) -#define CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_MASK (0x4000U) -#define CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_SHIFT (14U) -/*! CPU3_MODE_REQUEST - Domain3 request enter low power mode +#define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ_MASK) + +#define CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U) +#define CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST_SHIFT (8U) +/*! WHITE_LIST - Whitelist */ -#define CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_MASK) -#define CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_MASK (0x8000U) -#define CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_SHIFT (15U) -/*! CPU3_MODE_DONE - Domain3 low power mode task done +#define CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST_MASK) + +#define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U) +#define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock Whitelist */ -#define CCM_OSCPLL_STATUS1_CPU3_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_MASK) -#define CCM_OSCPLL_STATUS1_TARGET_SETPOINT_MASK (0xF0000U) -#define CCM_OSCPLL_STATUS1_TARGET_SETPOINT_SHIFT (16U) -/*! TARGET_SETPOINT - Next setpoint to change to +#define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST_MASK) + +#define CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U) +#define CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by Domain */ -#define CCM_OSCPLL_STATUS1_TARGET_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_TARGET_SETPOINT_SHIFT)) & CCM_OSCPLL_STATUS1_TARGET_SETPOINT_MASK) -#define CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_MASK (0xF00000U) -#define CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_SHIFT (20U) -/*! CURRENT_SETPOINT - Current setpoint +#define CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE_MASK) + +#define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U) +#define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE_SHIFT (20U) +/*! LOCK_MODE - Lock low power and access mode */ -#define CCM_OSCPLL_STATUS1_CURRENT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_SHIFT)) & CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_MASK) -#define CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_MASK (0x1000000U) -#define CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_SHIFT (24U) -/*! SETPOINT_OFF_REQUEST - Clock gate turn off request from GPC setpoint +#define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE_MASK) +/*! @} */ + +/*! @name GPR_PRIVATE2_AUTHEN_TOG - GPR access control */ +/*! @{ */ + +#define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER_MASK (0x1U) +#define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER_SHIFT (0U) +/*! TZ_USER - User access */ -#define CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_MASK) -#define CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_MASK (0x2000000U) -#define CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_SHIFT (25U) -/*! SETPOINT_OFF_DONE - Clock source turn off finish from GPC setpoint +#define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER_MASK) + +#define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS_MASK (0x2U) +#define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS_SHIFT (1U) +/*! TZ_NS - Non-secure access */ -#define CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_MASK) -#define CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_MASK (0x4000000U) -#define CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_SHIFT (26U) -/*! SETPOINT_ON_REQUEST - Clock gate turn on request from GPC setpoint +#define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS_MASK) + +#define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ_MASK (0x10U) +#define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ_SHIFT (4U) +/*! LOCK_TZ - Lock truszone setting */ -#define CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_MASK) -#define CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_MASK (0x8000000U) -#define CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_SHIFT (27U) -/*! SETPOINT_ON_DONE - Clock gate turn on finish from GPC setpoint +#define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ_MASK) + +#define CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U) +#define CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST_SHIFT (8U) +/*! WHITE_LIST - Whitelist */ -#define CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_MASK) -#define CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_MASK (0x10000000U) -#define CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_SHIFT (28U) -/*! STANDBY_IN_REQUEST - Clock gate turn off request from GPC standby +#define CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST_MASK) + +#define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U) +#define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock Whitelist */ -#define CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_MASK) -#define CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_MASK (0x20000000U) -#define CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_SHIFT (29U) -/*! STANDBY_IN_DONE - Clock source turn off finish from GPC standby +#define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST_MASK) + +#define CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U) +#define CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by Domain */ -#define CCM_OSCPLL_STATUS1_STANDBY_IN_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_MASK) -#define CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_MASK (0x40000000U) -#define CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_SHIFT (30U) -/*! STANDBY_OUT_DONE - Clock gate turn on finish from GPC standby +#define CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE_MASK) + +#define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U) +#define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE_SHIFT (20U) +/*! LOCK_MODE - Lock low power and access mode */ -#define CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_MASK) -#define CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_MASK (0x80000000U) -#define CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_SHIFT (31U) -/*! STANDBY_OUT_REQUEST - Clock gate turn on request from GPC standby +#define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE_MASK) +/*! @} */ + +/*! @name GPR_PRIVATE3 - General Purpose Register */ +/*! @{ */ + +#define CCM_GPR_PRIVATE3_GPR_MASK (0xFFFFFFFFU) +#define CCM_GPR_PRIVATE3_GPR_SHIFT (0U) +/*! GPR - GP register */ -#define CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_MASK) +#define CCM_GPR_PRIVATE3_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_GPR_SHIFT)) & CCM_GPR_PRIVATE3_GPR_MASK) /*! @} */ -/* The count of CCM_OSCPLL_STATUS1 */ -#define CCM_OSCPLL_STATUS1_COUNT (29U) +/*! @name GPR_PRIVATE3_SET - General Purpose Register */ +/*! @{ */ -/*! @name OSCPLL_CONFIG - Clock source configuration */ +#define CCM_GPR_PRIVATE3_SET_GPR_MASK (0xFFFFFFFFU) +#define CCM_GPR_PRIVATE3_SET_GPR_SHIFT (0U) +/*! GPR - GP register + */ +#define CCM_GPR_PRIVATE3_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE3_SET_GPR_MASK) +/*! @} */ + +/*! @name GPR_PRIVATE3_CLR - General Purpose Register */ /*! @{ */ -#define CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_MASK (0x1U) -#define CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_SHIFT (0U) -/*! SETPOINT_PRESENT - Setpoint present - * 0b1..Setpoint is implemented. - * 0b0..Setpoint is not implemented. + +#define CCM_GPR_PRIVATE3_CLR_GPR_MASK (0xFFFFFFFFU) +#define CCM_GPR_PRIVATE3_CLR_GPR_SHIFT (0U) +/*! GPR - GP register */ -#define CCM_OSCPLL_CONFIG_SETPOINT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_SHIFT)) & CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_MASK) -#define CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_MASK (0x2U) -#define CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_SHIFT (1U) -#define CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_SHIFT)) & CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_MASK) +#define CCM_GPR_PRIVATE3_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE3_CLR_GPR_MASK) /*! @} */ -/* The count of CCM_OSCPLL_CONFIG */ -#define CCM_OSCPLL_CONFIG_COUNT (29U) +/*! @name GPR_PRIVATE3_TOG - General Purpose Register */ +/*! @{ */ -/*! @name OSCPLL_AUTHEN - Clock source access control */ +#define CCM_GPR_PRIVATE3_TOG_GPR_MASK (0xFFFFFFFFU) +#define CCM_GPR_PRIVATE3_TOG_GPR_SHIFT (0U) +/*! GPR - GP register + */ +#define CCM_GPR_PRIVATE3_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE3_TOG_GPR_MASK) +/*! @} */ + +/*! @name GPR_PRIVATE3_AUTHEN - GPR access control */ /*! @{ */ -#define CCM_OSCPLL_AUTHEN_TZ_USER_MASK (0x1U) -#define CCM_OSCPLL_AUTHEN_TZ_USER_SHIFT (0U) + +#define CCM_GPR_PRIVATE3_AUTHEN_TZ_USER_MASK (0x1U) +#define CCM_GPR_PRIVATE3_AUTHEN_TZ_USER_SHIFT (0U) /*! TZ_USER - User access * 0b1..Clock can be changed in user mode. * 0b0..Clock cannot be changed in user mode. */ -#define CCM_OSCPLL_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_TZ_USER_SHIFT)) & CCM_OSCPLL_AUTHEN_TZ_USER_MASK) -#define CCM_OSCPLL_AUTHEN_TZ_NS_MASK (0x2U) -#define CCM_OSCPLL_AUTHEN_TZ_NS_SHIFT (1U) +#define CCM_GPR_PRIVATE3_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TZ_USER_MASK) + +#define CCM_GPR_PRIVATE3_AUTHEN_TZ_NS_MASK (0x2U) +#define CCM_GPR_PRIVATE3_AUTHEN_TZ_NS_SHIFT (1U) /*! TZ_NS - Non-secure access * 0b0..Cannot be changed in Non-secure mode. * 0b1..Can be changed in Non-secure mode. */ -#define CCM_OSCPLL_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_TZ_NS_SHIFT)) & CCM_OSCPLL_AUTHEN_TZ_NS_MASK) -#define CCM_OSCPLL_AUTHEN_LOCK_TZ_MASK (0x10U) -#define CCM_OSCPLL_AUTHEN_LOCK_TZ_SHIFT (4U) -/*! LOCK_TZ - lock truszone setting +#define CCM_GPR_PRIVATE3_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TZ_NS_MASK) + +#define CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ_MASK (0x10U) +#define CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ_SHIFT (4U) +/*! LOCK_TZ - Lock truszone setting * 0b0..Trustzone setting is not locked. * 0b1..Trustzone setting is locked. */ -#define CCM_OSCPLL_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_TZ_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_TZ_MASK) -#define CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK (0xF00U) -#define CCM_OSCPLL_AUTHEN_WHITE_LIST_SHIFT (8U) +#define CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ_MASK) + +#define CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST_MASK (0xF00U) +#define CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST_SHIFT (8U) /*! WHITE_LIST - Whitelist + * 0b0000..This domain is NOT allowed to change clock. + * 0b0001..This domain is allowed to change clock. */ -#define CCM_OSCPLL_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_WHITE_LIST_SHIFT)) & CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK) -#define CCM_OSCPLL_AUTHEN_LOCK_LIST_MASK (0x1000U) -#define CCM_OSCPLL_AUTHEN_LOCK_LIST_SHIFT (12U) -/*! LOCK_LIST - Lock white list +#define CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST_MASK) + +#define CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST_MASK (0x1000U) +#define CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock Whitelist * 0b0..Whitelist is not locked. * 0b1..Whitelist is locked. */ -#define CCM_OSCPLL_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_LIST_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_LIST_MASK) -#define CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK (0x10000U) -#define CCM_OSCPLL_AUTHEN_DOMAIN_MODE_SHIFT (16U) -/*! DOMAIN_MODE - Low power and access control by domain - * 0b1..Clock works in domain mode. - * 0b0..Clock does not work in domain mode. - */ -#define CCM_OSCPLL_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK) -#define CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK (0x20000U) -#define CCM_OSCPLL_AUTHEN_SETPOINT_MODE_SHIFT (17U) -/*! SETPOINT_MODE - LPCG works in setpoint controlled mode. +#define CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST_MASK) + +#define CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE_MASK (0x10000U) +#define CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by Domain + * 0b1..Clock works in Domain Mode. + * 0b0..Clock does NOT work in Domain Mode. */ -#define CCM_OSCPLL_AUTHEN_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_SETPOINT_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK) -#define CCM_OSCPLL_AUTHEN_AUTO_MODE_MASK (0x40000U) -#define CCM_OSCPLL_AUTHEN_AUTO_MODE_SHIFT (18U) -#define CCM_OSCPLL_AUTHEN_AUTO_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_AUTO_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_AUTO_MODE_MASK) -#define CCM_OSCPLL_AUTHEN_LOCK_MODE_MASK (0x100000U) -#define CCM_OSCPLL_AUTHEN_LOCK_MODE_SHIFT (20U) +#define CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE_MASK) + +#define CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE_MASK (0x100000U) +#define CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE_SHIFT (20U) /*! LOCK_MODE - Lock low power and access mode * 0b0..MODE is not locked. * 0b1..MODE is locked. */ -#define CCM_OSCPLL_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_MODE_MASK) +#define CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE_MASK) /*! @} */ -/* The count of CCM_OSCPLL_AUTHEN */ -#define CCM_OSCPLL_AUTHEN_COUNT (29U) - -/*! @name LPCG_DIRECT - LPCG direct control */ +/*! @name GPR_PRIVATE3_AUTHEN_SET - GPR access control */ /*! @{ */ -#define CCM_LPCG_DIRECT_ON_MASK (0x1U) -#define CCM_LPCG_DIRECT_ON_SHIFT (0U) -/*! ON - LPCG on - * 0b0..LPCG is OFF. - * 0b1..LPCG is ON. - */ -#define CCM_LPCG_DIRECT_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DIRECT_ON_SHIFT)) & CCM_LPCG_DIRECT_ON_MASK) -/*! @} */ - -/* The count of CCM_LPCG_DIRECT */ -#define CCM_LPCG_DIRECT_COUNT (138U) -/*! @name LPCG_DOMAIN - LPCG domain control */ -/*! @{ */ -#define CCM_LPCG_DOMAIN_LEVEL_MASK (0x3U) -#define CCM_LPCG_DOMAIN_LEVEL_SHIFT (0U) -/*! LEVEL - Current level - */ -#define CCM_LPCG_DOMAIN_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL_MASK) -#define CCM_LPCG_DOMAIN_LEVEL0_MASK (0x30000U) -#define CCM_LPCG_DOMAIN_LEVEL0_SHIFT (16U) -/*! LEVEL0 - Depend level - * 0b00..No need, can be off. - * 0b01..Need on when RUN. - * 0b10..Need on when RUN and WAIT. - * 0b11..Need on when RUN, WAIT and STOP. - */ -#define CCM_LPCG_DOMAIN_LEVEL0(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL0_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL0_MASK) -#define CCM_LPCG_DOMAIN_LEVEL1_MASK (0x300000U) -#define CCM_LPCG_DOMAIN_LEVEL1_SHIFT (20U) -/*! LEVEL1 - Depend level - * 0b00..No need, can be off. - * 0b01..Need on when RUN. - * 0b10..Need on when RUN and WAIT. - * 0b11..Need on when RUN, WAIT and STOP. - */ -#define CCM_LPCG_DOMAIN_LEVEL1(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL1_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL1_MASK) -#define CCM_LPCG_DOMAIN_LEVEL2_MASK (0x3000000U) -#define CCM_LPCG_DOMAIN_LEVEL2_SHIFT (24U) -/*! LEVEL2 - Depend level - * 0b00..No need, can be off. - * 0b01..Need on when RUN. - * 0b10..Need on when RUN and WAIT. - * 0b11..Need on when RUN, WAIT and STOP. - */ -#define CCM_LPCG_DOMAIN_LEVEL2(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL2_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL2_MASK) -#define CCM_LPCG_DOMAIN_LEVEL3_MASK (0x30000000U) -#define CCM_LPCG_DOMAIN_LEVEL3_SHIFT (28U) -/*! LEVEL3 - Depend level - * 0b00..No need, can be off. - * 0b01..Need on when RUN. - * 0b10..Need on when RUN and WAIT. - * 0b11..Need on when RUN, WAIT and STOP. +#define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER_MASK (0x1U) +#define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER_SHIFT (0U) +/*! TZ_USER - User access */ -#define CCM_LPCG_DOMAIN_LEVEL3(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL3_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL3_MASK) -/*! @} */ +#define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER_MASK) -/* The count of CCM_LPCG_DOMAIN */ -#define CCM_LPCG_DOMAIN_COUNT (138U) +#define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS_MASK (0x2U) +#define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS_SHIFT (1U) +/*! TZ_NS - Non-secure access + */ +#define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS_MASK) -/*! @name LPCG_SETPOINT - LPCG setpoint setting */ -/*! @{ */ -#define CCM_LPCG_SETPOINT_SETPOINT_MASK (0xFFFFU) -#define CCM_LPCG_SETPOINT_SETPOINT_SHIFT (0U) -/*! SETPOINT - Setpoints - * 0b0000000000000000..Clock is off in setpoint. - * 0b0000000000000001..Clock is on in setpoint. +#define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ_MASK (0x10U) +#define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ_SHIFT (4U) +/*! LOCK_TZ - Lock truszone setting */ -#define CCM_LPCG_SETPOINT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_SETPOINT_SETPOINT_SHIFT)) & CCM_LPCG_SETPOINT_SETPOINT_MASK) -/*! @} */ +#define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ_MASK) -/* The count of CCM_LPCG_SETPOINT */ -#define CCM_LPCG_SETPOINT_COUNT (138U) +#define CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST_MASK (0xF00U) +#define CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST_SHIFT (8U) +/*! WHITE_LIST - Whitelist + */ +#define CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST_MASK) -/*! @name LPCG_STATUS0 - LPCG working status */ -/*! @{ */ -#define CCM_LPCG_STATUS0_ON_MASK (0x1U) -#define CCM_LPCG_STATUS0_ON_SHIFT (0U) -/*! ON - LPCG current state - * 0b0..LPCG is OFF. - * 0b1..LPCG is ON. +#define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST_MASK (0x1000U) +#define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock Whitelist */ -#define CCM_LPCG_STATUS0_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS0_ON_SHIFT)) & CCM_LPCG_STATUS0_ON_MASK) -#define CCM_LPCG_STATUS0_ACTIVE_DOMAIN_MASK (0xF00U) -#define CCM_LPCG_STATUS0_ACTIVE_DOMAIN_SHIFT (8U) -/*! ACTIVE_DOMAIN - Domains that own this clock gate +#define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST_MASK) + +#define CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U) +#define CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by Domain */ -#define CCM_LPCG_STATUS0_ACTIVE_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS0_ACTIVE_DOMAIN_SHIFT)) & CCM_LPCG_STATUS0_ACTIVE_DOMAIN_MASK) -#define CCM_LPCG_STATUS0_DOMAIN_ENABLE_MASK (0xF000U) -#define CCM_LPCG_STATUS0_DOMAIN_ENABLE_SHIFT (12U) -/*! DOMAIN_ENABLE - Enable status from each domain +#define CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE_MASK) + +#define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE_MASK (0x100000U) +#define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE_SHIFT (20U) +/*! LOCK_MODE - Lock low power and access mode */ -#define CCM_LPCG_STATUS0_DOMAIN_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS0_DOMAIN_ENABLE_SHIFT)) & CCM_LPCG_STATUS0_DOMAIN_ENABLE_MASK) +#define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE_MASK) /*! @} */ -/* The count of CCM_LPCG_STATUS0 */ -#define CCM_LPCG_STATUS0_COUNT (138U) - -/*! @name LPCG_STATUS1 - LPCG low power status */ +/*! @name GPR_PRIVATE3_AUTHEN_CLR - GPR access control */ /*! @{ */ -#define CCM_LPCG_STATUS1_CPU0_MODE_MASK (0x3U) -#define CCM_LPCG_STATUS1_CPU0_MODE_SHIFT (0U) -/*! CPU0_MODE - Domain0 low power mode - */ -#define CCM_LPCG_STATUS1_CPU0_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_MASK) -#define CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_MASK (0x4U) -#define CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_SHIFT (2U) -/*! CPU0_MODE_REQUEST - Domain0 request enter low power mode - */ -#define CCM_LPCG_STATUS1_CPU0_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_MASK) -#define CCM_LPCG_STATUS1_CPU0_MODE_DONE_MASK (0x8U) -#define CCM_LPCG_STATUS1_CPU0_MODE_DONE_SHIFT (3U) -/*! CPU0_MODE_DONE - Domain0 low power mode task done - */ -#define CCM_LPCG_STATUS1_CPU0_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_DONE_MASK) -#define CCM_LPCG_STATUS1_CPU1_MODE_MASK (0x30U) -#define CCM_LPCG_STATUS1_CPU1_MODE_SHIFT (4U) -/*! CPU1_MODE - Domain1 low power mode + +#define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER_MASK (0x1U) +#define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER_SHIFT (0U) +/*! TZ_USER - User access */ -#define CCM_LPCG_STATUS1_CPU1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU1_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU1_MODE_MASK) -#define CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_MASK (0x40U) -#define CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_SHIFT (6U) -/*! CPU1_MODE_REQUEST - Domain1 request enter low power mode +#define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER_MASK) + +#define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS_MASK (0x2U) +#define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS_SHIFT (1U) +/*! TZ_NS - Non-secure access */ -#define CCM_LPCG_STATUS1_CPU1_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_MASK) -#define CCM_LPCG_STATUS1_CPU1_MODE_DONE_MASK (0x80U) -#define CCM_LPCG_STATUS1_CPU1_MODE_DONE_SHIFT (7U) -/*! CPU1_MODE_DONE - Domain1 low power mode task done +#define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS_MASK) + +#define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ_MASK (0x10U) +#define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ_SHIFT (4U) +/*! LOCK_TZ - Lock truszone setting */ -#define CCM_LPCG_STATUS1_CPU1_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU1_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU1_MODE_DONE_MASK) -#define CCM_LPCG_STATUS1_CPU2_MODE_MASK (0x300U) -#define CCM_LPCG_STATUS1_CPU2_MODE_SHIFT (8U) -/*! CPU2_MODE - Domain2 low power mode +#define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ_MASK) + +#define CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U) +#define CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST_SHIFT (8U) +/*! WHITE_LIST - Whitelist */ -#define CCM_LPCG_STATUS1_CPU2_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU2_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU2_MODE_MASK) -#define CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_MASK (0x400U) -#define CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_SHIFT (10U) -/*! CPU2_MODE_REQUEST - Domain2 request enter low power mode +#define CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST_MASK) + +#define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U) +#define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock Whitelist */ -#define CCM_LPCG_STATUS1_CPU2_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_MASK) -#define CCM_LPCG_STATUS1_CPU2_MODE_DONE_MASK (0x800U) -#define CCM_LPCG_STATUS1_CPU2_MODE_DONE_SHIFT (11U) -/*! CPU2_MODE_DONE - Domain2 low power mode task done +#define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST_MASK) + +#define CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U) +#define CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by Domain */ -#define CCM_LPCG_STATUS1_CPU2_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU2_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU2_MODE_DONE_MASK) -#define CCM_LPCG_STATUS1_CPU3_MODE_MASK (0x3000U) -#define CCM_LPCG_STATUS1_CPU3_MODE_SHIFT (12U) -/*! CPU3_MODE - Domain3 low power mode +#define CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE_MASK) + +#define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U) +#define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE_SHIFT (20U) +/*! LOCK_MODE - Lock low power and access mode */ -#define CCM_LPCG_STATUS1_CPU3_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU3_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU3_MODE_MASK) -#define CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_MASK (0x4000U) -#define CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_SHIFT (14U) -/*! CPU3_MODE_REQUEST - Domain3 request enter low power mode +#define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE_MASK) +/*! @} */ + +/*! @name GPR_PRIVATE3_AUTHEN_TOG - GPR access control */ +/*! @{ */ + +#define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER_MASK (0x1U) +#define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER_SHIFT (0U) +/*! TZ_USER - User access */ -#define CCM_LPCG_STATUS1_CPU3_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_MASK) -#define CCM_LPCG_STATUS1_CPU3_MODE_DONE_MASK (0x8000U) -#define CCM_LPCG_STATUS1_CPU3_MODE_DONE_SHIFT (15U) -/*! CPU3_MODE_DONE - Domain3 low power mode task done +#define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER_MASK) + +#define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS_MASK (0x2U) +#define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS_SHIFT (1U) +/*! TZ_NS - Non-secure access */ -#define CCM_LPCG_STATUS1_CPU3_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU3_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU3_MODE_DONE_MASK) -#define CCM_LPCG_STATUS1_TARGET_SETPOINT_MASK (0xF0000U) -#define CCM_LPCG_STATUS1_TARGET_SETPOINT_SHIFT (16U) -/*! TARGET_SETPOINT - Next setpoint to change to +#define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS_MASK) + +#define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ_MASK (0x10U) +#define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ_SHIFT (4U) +/*! LOCK_TZ - Lock truszone setting */ -#define CCM_LPCG_STATUS1_TARGET_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_TARGET_SETPOINT_SHIFT)) & CCM_LPCG_STATUS1_TARGET_SETPOINT_MASK) -#define CCM_LPCG_STATUS1_CURRENT_SETPOINT_MASK (0xF00000U) -#define CCM_LPCG_STATUS1_CURRENT_SETPOINT_SHIFT (20U) -/*! CURRENT_SETPOINT - Current setpoint +#define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ_MASK) + +#define CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U) +#define CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST_SHIFT (8U) +/*! WHITE_LIST - Whitelist */ -#define CCM_LPCG_STATUS1_CURRENT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CURRENT_SETPOINT_SHIFT)) & CCM_LPCG_STATUS1_CURRENT_SETPOINT_MASK) -#define CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_MASK (0x1000000U) -#define CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_SHIFT (24U) -/*! SETPOINT_OFF_REQUEST - Clock gate turn off request from GPC setpoint +#define CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST_MASK) + +#define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U) +#define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock Whitelist */ -#define CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_MASK) -#define CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_MASK (0x2000000U) -#define CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_SHIFT (25U) -/*! SETPOINT_OFF_DONE - Clock gate turn off finish from GPC setpoint +#define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST_MASK) + +#define CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U) +#define CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by Domain */ -#define CCM_LPCG_STATUS1_SETPOINT_OFF_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_MASK) -#define CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_MASK (0x4000000U) -#define CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_SHIFT (26U) -/*! SETPOINT_ON_REQUEST - Clock gate turn on request from GPC setpoint +#define CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE_MASK) + +#define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U) +#define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE_SHIFT (20U) +/*! LOCK_MODE - Lock low power and access mode */ -#define CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_MASK) -#define CCM_LPCG_STATUS1_SETPOINT_ON_DONE_MASK (0x8000000U) -#define CCM_LPCG_STATUS1_SETPOINT_ON_DONE_SHIFT (27U) -/*! SETPOINT_ON_DONE - Clock gate turn on finish from GPC setpoint +#define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE_MASK) +/*! @} */ + +/*! @name GPR_PRIVATE4 - General Purpose Register */ +/*! @{ */ + +#define CCM_GPR_PRIVATE4_GPR_MASK (0xFFFFFFFFU) +#define CCM_GPR_PRIVATE4_GPR_SHIFT (0U) +/*! GPR - GP register */ -#define CCM_LPCG_STATUS1_SETPOINT_ON_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_ON_DONE_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_ON_DONE_MASK) +#define CCM_GPR_PRIVATE4_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_GPR_SHIFT)) & CCM_GPR_PRIVATE4_GPR_MASK) /*! @} */ -/* The count of CCM_LPCG_STATUS1 */ -#define CCM_LPCG_STATUS1_COUNT (138U) +/*! @name GPR_PRIVATE4_SET - General Purpose Register */ +/*! @{ */ -/*! @name LPCG_CONFIG - LPCG configuration */ +#define CCM_GPR_PRIVATE4_SET_GPR_MASK (0xFFFFFFFFU) +#define CCM_GPR_PRIVATE4_SET_GPR_SHIFT (0U) +/*! GPR - GP register + */ +#define CCM_GPR_PRIVATE4_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE4_SET_GPR_MASK) +/*! @} */ + +/*! @name GPR_PRIVATE4_CLR - General Purpose Register */ /*! @{ */ -#define CCM_LPCG_CONFIG_SETPOINT_PRESENT_MASK (0x1U) -#define CCM_LPCG_CONFIG_SETPOINT_PRESENT_SHIFT (0U) -/*! SETPOINT_PRESENT - Setpoint present - * 0b1..Setpoint is implemented. - * 0b0..Setpoint is not implemented. + +#define CCM_GPR_PRIVATE4_CLR_GPR_MASK (0xFFFFFFFFU) +#define CCM_GPR_PRIVATE4_CLR_GPR_SHIFT (0U) +/*! GPR - GP register */ -#define CCM_LPCG_CONFIG_SETPOINT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_CONFIG_SETPOINT_PRESENT_SHIFT)) & CCM_LPCG_CONFIG_SETPOINT_PRESENT_MASK) +#define CCM_GPR_PRIVATE4_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE4_CLR_GPR_MASK) /*! @} */ -/* The count of CCM_LPCG_CONFIG */ -#define CCM_LPCG_CONFIG_COUNT (138U) +/*! @name GPR_PRIVATE4_TOG - General Purpose Register */ +/*! @{ */ -/*! @name LPCG_AUTHEN - LPCG access control */ +#define CCM_GPR_PRIVATE4_TOG_GPR_MASK (0xFFFFFFFFU) +#define CCM_GPR_PRIVATE4_TOG_GPR_SHIFT (0U) +/*! GPR - GP register + */ +#define CCM_GPR_PRIVATE4_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE4_TOG_GPR_MASK) +/*! @} */ + +/*! @name GPR_PRIVATE4_AUTHEN - GPR access control */ /*! @{ */ -#define CCM_LPCG_AUTHEN_TZ_USER_MASK (0x1U) -#define CCM_LPCG_AUTHEN_TZ_USER_SHIFT (0U) + +#define CCM_GPR_PRIVATE4_AUTHEN_TZ_USER_MASK (0x1U) +#define CCM_GPR_PRIVATE4_AUTHEN_TZ_USER_SHIFT (0U) /*! TZ_USER - User access - * 0b1..LPCG can be changed in user mode. - * 0b0..LPCG cannot be changed in user mode. + * 0b1..Clock can be changed in user mode. + * 0b0..Clock cannot be changed in user mode. */ -#define CCM_LPCG_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_TZ_USER_SHIFT)) & CCM_LPCG_AUTHEN_TZ_USER_MASK) -#define CCM_LPCG_AUTHEN_TZ_NS_MASK (0x2U) -#define CCM_LPCG_AUTHEN_TZ_NS_SHIFT (1U) +#define CCM_GPR_PRIVATE4_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TZ_USER_MASK) + +#define CCM_GPR_PRIVATE4_AUTHEN_TZ_NS_MASK (0x2U) +#define CCM_GPR_PRIVATE4_AUTHEN_TZ_NS_SHIFT (1U) /*! TZ_NS - Non-secure access * 0b0..Cannot be changed in Non-secure mode. * 0b1..Can be changed in Non-secure mode. */ -#define CCM_LPCG_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_TZ_NS_SHIFT)) & CCM_LPCG_AUTHEN_TZ_NS_MASK) -#define CCM_LPCG_AUTHEN_LOCK_TZ_MASK (0x10U) -#define CCM_LPCG_AUTHEN_LOCK_TZ_SHIFT (4U) -/*! LOCK_TZ - lock truszone setting +#define CCM_GPR_PRIVATE4_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TZ_NS_MASK) + +#define CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ_MASK (0x10U) +#define CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ_SHIFT (4U) +/*! LOCK_TZ - Lock truszone setting * 0b0..Trustzone setting is not locked. * 0b1..Trustzone setting is locked. */ -#define CCM_LPCG_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_TZ_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_TZ_MASK) -#define CCM_LPCG_AUTHEN_WHITE_LIST_MASK (0xF00U) -#define CCM_LPCG_AUTHEN_WHITE_LIST_SHIFT (8U) +#define CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ_MASK) + +#define CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST_MASK (0xF00U) +#define CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST_SHIFT (8U) /*! WHITE_LIST - Whitelist + * 0b0000..This domain is NOT allowed to change clock. + * 0b0001..This domain is allowed to change clock. */ -#define CCM_LPCG_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_WHITE_LIST_SHIFT)) & CCM_LPCG_AUTHEN_WHITE_LIST_MASK) -#define CCM_LPCG_AUTHEN_LOCK_LIST_MASK (0x1000U) -#define CCM_LPCG_AUTHEN_LOCK_LIST_SHIFT (12U) -/*! LOCK_LIST - Lock white list +#define CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST_MASK) + +#define CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST_MASK (0x1000U) +#define CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock Whitelist * 0b0..Whitelist is not locked. * 0b1..Whitelist is locked. */ -#define CCM_LPCG_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_LIST_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_LIST_MASK) -#define CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK (0x10000U) -#define CCM_LPCG_AUTHEN_DOMAIN_MODE_SHIFT (16U) -/*! DOMAIN_MODE - Low power and access control by domain - * 0b1..Clock works in domain mode. - * 0b0..Clock does not work in domain mode. - */ -#define CCM_LPCG_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK) -#define CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK (0x20000U) -#define CCM_LPCG_AUTHEN_SETPOINT_MODE_SHIFT (17U) -/*! SETPOINT_MODE - Low power and access control by setpoint +#define CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST_MASK) + +#define CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE_MASK (0x10000U) +#define CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by Domain + * 0b1..Clock works in Domain Mode. + * 0b0..Clock does NOT work in Domain Mode. */ -#define CCM_LPCG_AUTHEN_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_SETPOINT_MODE_SHIFT)) & CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK) -#define CCM_LPCG_AUTHEN_LOCK_MODE_MASK (0x100000U) -#define CCM_LPCG_AUTHEN_LOCK_MODE_SHIFT (20U) +#define CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE_MASK) + +#define CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE_MASK (0x100000U) +#define CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE_SHIFT (20U) /*! LOCK_MODE - Lock low power and access mode * 0b0..MODE is not locked. * 0b1..MODE is locked. */ -#define CCM_LPCG_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_MODE_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_MODE_MASK) +#define CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE_MASK) /*! @} */ -/* The count of CCM_LPCG_AUTHEN */ -#define CCM_LPCG_AUTHEN_COUNT (138U) +/*! @name GPR_PRIVATE4_AUTHEN_SET - GPR access control */ +/*! @{ */ +#define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER_MASK (0x1U) +#define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER_SHIFT (0U) +/*! TZ_USER - User access + */ +#define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER_MASK) -/*! - * @} - */ /* end of group CCM_Register_Masks */ +#define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS_MASK (0x2U) +#define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS_SHIFT (1U) +/*! TZ_NS - Non-secure access + */ +#define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS_MASK) +#define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ_MASK (0x10U) +#define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ_SHIFT (4U) +/*! LOCK_TZ - Lock truszone setting + */ +#define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ_MASK) -/* CCM - Peripheral instance base addresses */ -/** Peripheral CCM base address */ -#define CCM_BASE (0x40CC0000u) -/** Peripheral CCM base pointer */ -#define CCM ((CCM_Type *)CCM_BASE) -/** Array initializer of CCM peripheral base addresses */ -#define CCM_BASE_ADDRS { CCM_BASE } -/** Array initializer of CCM peripheral base pointers */ -#define CCM_BASE_PTRS { CCM } +#define CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST_MASK (0xF00U) +#define CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST_SHIFT (8U) +/*! WHITE_LIST - Whitelist + */ +#define CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST_MASK) -/*! - * @} - */ /* end of group CCM_Peripheral_Access_Layer */ +#define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST_MASK (0x1000U) +#define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock Whitelist + */ +#define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST_MASK) +#define CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U) +#define CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by Domain + */ +#define CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE_MASK) -/* ---------------------------------------------------------------------------- - -- CCM_OBS Peripheral Access Layer - ---------------------------------------------------------------------------- */ +#define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE_MASK (0x100000U) +#define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE_SHIFT (20U) +/*! LOCK_MODE - Lock low power and access mode + */ +#define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE_MASK) +/*! @} */ -/*! - * @addtogroup CCM_OBS_Peripheral_Access_Layer CCM_OBS Peripheral Access Layer - * @{ +/*! @name GPR_PRIVATE4_AUTHEN_CLR - GPR access control */ +/*! @{ */ + +#define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER_MASK (0x1U) +#define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER_SHIFT (0U) +/*! TZ_USER - User access */ +#define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER_MASK) -/** CCM_OBS - Register Layout Typedef */ -typedef struct { - struct { /* offset: 0x0, array step: 0x80 */ - __IO uint32_t CONTROL; /**< Observe control, array offset: 0x0, array step: 0x80 */ - __IO uint32_t CONTROL_SET; /**< Observe control, array offset: 0x4, array step: 0x80 */ - __IO uint32_t CONTROL_CLR; /**< Observe control, array offset: 0x8, array step: 0x80 */ - __IO uint32_t CONTROL_TOG; /**< Observe control, array offset: 0xC, array step: 0x80 */ - uint8_t RESERVED_0[16]; - __I uint32_t STATUS0; /**< Observe status, array offset: 0x20, array step: 0x80 */ - uint32_t STATUS1; /**< Observe low power status, array offset: 0x24, array step: 0x80 */ - __I uint32_t NAME; /**< Observe name, array offset: 0x28, array step: 0x80 */ - uint32_t CONFIG; /**< Observe configuration, array offset: 0x2C, array step: 0x80 */ - __IO uint32_t AUTHEN; /**< Observe access control, array offset: 0x30, array step: 0x80 */ - __IO uint32_t AUTHEN_SET; /**< Observe access control, array offset: 0x34, array step: 0x80 */ - __IO uint32_t AUTHEN_CLR; /**< Observe access control, array offset: 0x38, array step: 0x80 */ - __IO uint32_t AUTHEN_TOG; /**< Observe access control, array offset: 0x3C, array step: 0x80 */ - __I uint32_t FREQUENCY_CURRENT; /**< Current frequency detected, array offset: 0x40, array step: 0x80 */ - __I uint32_t FREQUENCY_MIN; /**< Minimum frequency detected, array offset: 0x44, array step: 0x80 */ - __I uint32_t FREQUENCY_MAX; /**< Maximum frequency detected, array offset: 0x48, array step: 0x80 */ - uint8_t RESERVED_1[4]; - __I uint32_t PERIOD_CURRENT; /**< Current period time detected, array offset: 0x50, array step: 0x80 */ - __I uint32_t PERIOD_MIN; /**< Minimum period time detected, array offset: 0x54, array step: 0x80 */ - __I uint32_t PERIOD_MAX; /**< Maximum period time detected, array offset: 0x58, array step: 0x80 */ - uint8_t RESERVED_2[4]; - __I uint32_t HIGH_CURRENT; /**< Current high level time detected, array offset: 0x60, array step: 0x80 */ - __I uint32_t HIGH_MIN; /**< Minimum high level time detected, array offset: 0x64, array step: 0x80 */ - __I uint32_t HIGH_MAX; /**< Maximum high level time detected, array offset: 0x68, array step: 0x80 */ - uint8_t RESERVED_3[4]; - __I uint32_t LOW_CURRENT; /**< Current high level time detected, array offset: 0x70, array step: 0x80 */ - __I uint32_t LOW_MIN; /**< Minimum high level time detected, array offset: 0x74, array step: 0x80 */ - __I uint32_t LOW_MAX; /**< Maximum high level time detected, array offset: 0x78, array step: 0x80 */ - uint8_t RESERVED_4[4]; - } OBSERVE[6]; -} CCM_OBS_Type; - -/* ---------------------------------------------------------------------------- - -- CCM_OBS Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup CCM_OBS_Register_Masks CCM_OBS Register Masks - * @{ +#define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS_MASK (0x2U) +#define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS_SHIFT (1U) +/*! TZ_NS - Non-secure access */ +#define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS_MASK) -/*! @name OBSERVE_CONTROL - Observe control */ -/*! @{ */ -#define CCM_OBS_OBSERVE_CONTROL_SELECT_MASK (0x1FFU) -#define CCM_OBS_OBSERVE_CONTROL_SELECT_SHIFT (0U) -/*! SELECT - Observe signal selector - */ -#define CCM_OBS_OBSERVE_CONTROL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SELECT_MASK) -#define CCM_OBS_OBSERVE_CONTROL_RAW_MASK (0x1000U) -#define CCM_OBS_OBSERVE_CONTROL_RAW_SHIFT (12U) -/*! RAW - Observe raw signal - * 0b0..Select divided signal. - * 0b1..Select raw signal. +#define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ_MASK (0x10U) +#define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ_SHIFT (4U) +/*! LOCK_TZ - Lock truszone setting */ -#define CCM_OBS_OBSERVE_CONTROL_RAW(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_RAW_MASK) -#define CCM_OBS_OBSERVE_CONTROL_INV_MASK (0x2000U) -#define CCM_OBS_OBSERVE_CONTROL_INV_SHIFT (13U) -/*! INV - Invert - * 0b0..Clock phase remain same. - * 0b1..Invert clock phase before measurement or send to IO. +#define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ_MASK) + +#define CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U) +#define CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST_SHIFT (8U) +/*! WHITE_LIST - Whitelist */ -#define CCM_OBS_OBSERVE_CONTROL_INV(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_INV_MASK) -#define CCM_OBS_OBSERVE_CONTROL_RESET_MASK (0x8000U) -#define CCM_OBS_OBSERVE_CONTROL_RESET_SHIFT (15U) -/*! RESET - Reset observe divider - * 0b0..Clock phase remain same. - * 0b1..Invert clock phase before measurement or send to IO. +#define CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST_MASK) + +#define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U) +#define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock Whitelist */ -#define CCM_OBS_OBSERVE_CONTROL_RESET(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_RESET_MASK) -#define CCM_OBS_OBSERVE_CONTROL_DIVIDE_MASK (0xFF0000U) -#define CCM_OBS_OBSERVE_CONTROL_DIVIDE_SHIFT (16U) -/*! DIVIDE - Dividerfor observe signal +#define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST_MASK) + +#define CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U) +#define CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by Domain */ -#define CCM_OBS_OBSERVE_CONTROL_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_DIVIDE_MASK) -#define CCM_OBS_OBSERVE_CONTROL_OFF_MASK (0x1000000U) -#define CCM_OBS_OBSERVE_CONTROL_OFF_SHIFT (24U) -/*! OFF - Turn off - * 0b0..observe slice is on - * 0b1..observe slice is off +#define CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE_MASK) + +#define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U) +#define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE_SHIFT (20U) +/*! LOCK_MODE - Lock low power and access mode */ -#define CCM_OBS_OBSERVE_CONTROL_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_OFF_MASK) +#define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE_MASK) /*! @} */ -/* The count of CCM_OBS_OBSERVE_CONTROL */ -#define CCM_OBS_OBSERVE_CONTROL_COUNT (6U) - -/*! @name OBSERVE_CONTROL_SET - Observe control */ +/*! @name GPR_PRIVATE4_AUTHEN_TOG - GPR access control */ /*! @{ */ -#define CCM_OBS_OBSERVE_CONTROL_SET_SELECT_MASK (0x1FFU) -#define CCM_OBS_OBSERVE_CONTROL_SET_SELECT_SHIFT (0U) -/*! SELECT - Observe signal selector - */ -#define CCM_OBS_OBSERVE_CONTROL_SET_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_SELECT_MASK) -#define CCM_OBS_OBSERVE_CONTROL_SET_RAW_MASK (0x1000U) -#define CCM_OBS_OBSERVE_CONTROL_SET_RAW_SHIFT (12U) -/*! RAW - Observe raw signal - */ -#define CCM_OBS_OBSERVE_CONTROL_SET_RAW(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_RAW_MASK) -#define CCM_OBS_OBSERVE_CONTROL_SET_INV_MASK (0x2000U) -#define CCM_OBS_OBSERVE_CONTROL_SET_INV_SHIFT (13U) -/*! INV - Invert - */ -#define CCM_OBS_OBSERVE_CONTROL_SET_INV(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_INV_MASK) -#define CCM_OBS_OBSERVE_CONTROL_SET_RESET_MASK (0x8000U) -#define CCM_OBS_OBSERVE_CONTROL_SET_RESET_SHIFT (15U) -/*! RESET - Reset observe divider - */ -#define CCM_OBS_OBSERVE_CONTROL_SET_RESET(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_RESET_MASK) -#define CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_MASK (0xFF0000U) -#define CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_SHIFT (16U) -/*! DIVIDE - Dividerfor observe signal - */ -#define CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_MASK) -#define CCM_OBS_OBSERVE_CONTROL_SET_OFF_MASK (0x1000000U) -#define CCM_OBS_OBSERVE_CONTROL_SET_OFF_SHIFT (24U) -/*! OFF - Turn off - */ -#define CCM_OBS_OBSERVE_CONTROL_SET_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_OFF_MASK) -/*! @} */ -/* The count of CCM_OBS_OBSERVE_CONTROL_SET */ -#define CCM_OBS_OBSERVE_CONTROL_SET_COUNT (6U) +#define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER_MASK (0x1U) +#define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER_SHIFT (0U) +/*! TZ_USER - User access + */ +#define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER_MASK) -/*! @name OBSERVE_CONTROL_CLR - Observe control */ -/*! @{ */ -#define CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_MASK (0x1FFU) -#define CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_SHIFT (0U) -/*! SELECT - Observe signal selector +#define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS_MASK (0x2U) +#define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS_SHIFT (1U) +/*! TZ_NS - Non-secure access */ -#define CCM_OBS_OBSERVE_CONTROL_CLR_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_MASK) -#define CCM_OBS_OBSERVE_CONTROL_CLR_RAW_MASK (0x1000U) -#define CCM_OBS_OBSERVE_CONTROL_CLR_RAW_SHIFT (12U) -/*! RAW - Observe raw signal +#define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS_MASK) + +#define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ_MASK (0x10U) +#define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ_SHIFT (4U) +/*! LOCK_TZ - Lock truszone setting */ -#define CCM_OBS_OBSERVE_CONTROL_CLR_RAW(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_RAW_MASK) -#define CCM_OBS_OBSERVE_CONTROL_CLR_INV_MASK (0x2000U) -#define CCM_OBS_OBSERVE_CONTROL_CLR_INV_SHIFT (13U) -/*! INV - Invert +#define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ_MASK) + +#define CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U) +#define CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST_SHIFT (8U) +/*! WHITE_LIST - Whitelist */ -#define CCM_OBS_OBSERVE_CONTROL_CLR_INV(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_INV_MASK) -#define CCM_OBS_OBSERVE_CONTROL_CLR_RESET_MASK (0x8000U) -#define CCM_OBS_OBSERVE_CONTROL_CLR_RESET_SHIFT (15U) -/*! RESET - Reset observe divider +#define CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST_MASK) + +#define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U) +#define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock Whitelist */ -#define CCM_OBS_OBSERVE_CONTROL_CLR_RESET(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_RESET_MASK) -#define CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_MASK (0xFF0000U) -#define CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_SHIFT (16U) -/*! DIVIDE - Dividerfor observe signal +#define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST_MASK) + +#define CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U) +#define CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by Domain */ -#define CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_MASK) -#define CCM_OBS_OBSERVE_CONTROL_CLR_OFF_MASK (0x1000000U) -#define CCM_OBS_OBSERVE_CONTROL_CLR_OFF_SHIFT (24U) -/*! OFF - Turn off +#define CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE_MASK) + +#define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U) +#define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE_SHIFT (20U) +/*! LOCK_MODE - Lock low power and access mode */ -#define CCM_OBS_OBSERVE_CONTROL_CLR_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_OFF_MASK) +#define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE_MASK) /*! @} */ -/* The count of CCM_OBS_OBSERVE_CONTROL_CLR */ -#define CCM_OBS_OBSERVE_CONTROL_CLR_COUNT (6U) - -/*! @name OBSERVE_CONTROL_TOG - Observe control */ +/*! @name GPR_PRIVATE5 - General Purpose Register */ /*! @{ */ -#define CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_MASK (0x1FFU) -#define CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_SHIFT (0U) -/*! SELECT - Observe signal selector - */ -#define CCM_OBS_OBSERVE_CONTROL_TOG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_MASK) -#define CCM_OBS_OBSERVE_CONTROL_TOG_RAW_MASK (0x1000U) -#define CCM_OBS_OBSERVE_CONTROL_TOG_RAW_SHIFT (12U) -/*! RAW - Observe raw signal - */ -#define CCM_OBS_OBSERVE_CONTROL_TOG_RAW(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_RAW_MASK) -#define CCM_OBS_OBSERVE_CONTROL_TOG_INV_MASK (0x2000U) -#define CCM_OBS_OBSERVE_CONTROL_TOG_INV_SHIFT (13U) -/*! INV - Invert - */ -#define CCM_OBS_OBSERVE_CONTROL_TOG_INV(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_INV_MASK) -#define CCM_OBS_OBSERVE_CONTROL_TOG_RESET_MASK (0x8000U) -#define CCM_OBS_OBSERVE_CONTROL_TOG_RESET_SHIFT (15U) -/*! RESET - Reset observe divider - */ -#define CCM_OBS_OBSERVE_CONTROL_TOG_RESET(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_RESET_MASK) -#define CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_MASK (0xFF0000U) -#define CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_SHIFT (16U) -/*! DIVIDE - Dividerfor observe signal - */ -#define CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_MASK) -#define CCM_OBS_OBSERVE_CONTROL_TOG_OFF_MASK (0x1000000U) -#define CCM_OBS_OBSERVE_CONTROL_TOG_OFF_SHIFT (24U) -/*! OFF - Turn off + +#define CCM_GPR_PRIVATE5_GPR_MASK (0xFFFFFFFFU) +#define CCM_GPR_PRIVATE5_GPR_SHIFT (0U) +/*! GPR - GP register */ -#define CCM_OBS_OBSERVE_CONTROL_TOG_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_OFF_MASK) +#define CCM_GPR_PRIVATE5_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_GPR_SHIFT)) & CCM_GPR_PRIVATE5_GPR_MASK) /*! @} */ -/* The count of CCM_OBS_OBSERVE_CONTROL_TOG */ -#define CCM_OBS_OBSERVE_CONTROL_TOG_COUNT (6U) - -/*! @name OBSERVE_STATUS0 - Observe status */ +/*! @name GPR_PRIVATE5_SET - General Purpose Register */ /*! @{ */ -#define CCM_OBS_OBSERVE_STATUS0_SELECT_MASK (0x1FFU) -#define CCM_OBS_OBSERVE_STATUS0_SELECT_SHIFT (0U) -#define CCM_OBS_OBSERVE_STATUS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_SELECT_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_SELECT_MASK) -#define CCM_OBS_OBSERVE_STATUS0_Reserved1_MASK (0xE00U) -#define CCM_OBS_OBSERVE_STATUS0_Reserved1_SHIFT (9U) -#define CCM_OBS_OBSERVE_STATUS0_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_Reserved1_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_Reserved1_MASK) -#define CCM_OBS_OBSERVE_STATUS0_RAW_MASK (0x1000U) -#define CCM_OBS_OBSERVE_STATUS0_RAW_SHIFT (12U) -#define CCM_OBS_OBSERVE_STATUS0_RAW(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_RAW_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_RAW_MASK) -#define CCM_OBS_OBSERVE_STATUS0_INV_MASK (0x2000U) -#define CCM_OBS_OBSERVE_STATUS0_INV_SHIFT (13U) -#define CCM_OBS_OBSERVE_STATUS0_INV(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_INV_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_INV_MASK) -#define CCM_OBS_OBSERVE_STATUS0_Reserved2_MASK (0x4000U) -#define CCM_OBS_OBSERVE_STATUS0_Reserved2_SHIFT (14U) -#define CCM_OBS_OBSERVE_STATUS0_Reserved2(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_Reserved2_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_Reserved2_MASK) -#define CCM_OBS_OBSERVE_STATUS0_RESET_MASK (0x8000U) -#define CCM_OBS_OBSERVE_STATUS0_RESET_SHIFT (15U) -#define CCM_OBS_OBSERVE_STATUS0_RESET(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_RESET_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_RESET_MASK) -#define CCM_OBS_OBSERVE_STATUS0_DIVIDE_MASK (0xFF0000U) -#define CCM_OBS_OBSERVE_STATUS0_DIVIDE_SHIFT (16U) -#define CCM_OBS_OBSERVE_STATUS0_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_DIVIDE_MASK) -#define CCM_OBS_OBSERVE_STATUS0_OFF_MASK (0x1000000U) -#define CCM_OBS_OBSERVE_STATUS0_OFF_SHIFT (24U) -#define CCM_OBS_OBSERVE_STATUS0_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_OFF_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_OFF_MASK) -#define CCM_OBS_OBSERVE_STATUS0_Reserved3_MASK (0x6000000U) -#define CCM_OBS_OBSERVE_STATUS0_Reserved3_SHIFT (25U) -#define CCM_OBS_OBSERVE_STATUS0_Reserved3(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_Reserved3_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_Reserved3_MASK) -#define CCM_OBS_OBSERVE_STATUS0_POWERDOWN_MASK (0x8000000U) -#define CCM_OBS_OBSERVE_STATUS0_POWERDOWN_SHIFT (27U) -#define CCM_OBS_OBSERVE_STATUS0_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_POWERDOWN_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_POWERDOWN_MASK) -#define CCM_OBS_OBSERVE_STATUS0_UPDATE_FORWARD_MASK (0x20000000U) -#define CCM_OBS_OBSERVE_STATUS0_UPDATE_FORWARD_SHIFT (29U) -#define CCM_OBS_OBSERVE_STATUS0_UPDATE_FORWARD(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_UPDATE_FORWARD_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_UPDATE_FORWARD_MASK) -#define CCM_OBS_OBSERVE_STATUS0_BUSY_MASK (0x80000000U) -#define CCM_OBS_OBSERVE_STATUS0_BUSY_SHIFT (31U) -/*! BUSY - Busy + +#define CCM_GPR_PRIVATE5_SET_GPR_MASK (0xFFFFFFFFU) +#define CCM_GPR_PRIVATE5_SET_GPR_SHIFT (0U) +/*! GPR - GP register */ -#define CCM_OBS_OBSERVE_STATUS0_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_BUSY_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_BUSY_MASK) +#define CCM_GPR_PRIVATE5_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE5_SET_GPR_MASK) /*! @} */ -/* The count of CCM_OBS_OBSERVE_STATUS0 */ -#define CCM_OBS_OBSERVE_STATUS0_COUNT (6U) - -/* The count of CCM_OBS_OBSERVE_STATUS1 */ -#define CCM_OBS_OBSERVE_STATUS1_COUNT (6U) - -/*! @name OBSERVE_NAME - Observe name */ +/*! @name GPR_PRIVATE5_CLR - General Purpose Register */ /*! @{ */ -#define CCM_OBS_OBSERVE_NAME_NAME_MASK (0xFFFFFFFFU) -#define CCM_OBS_OBSERVE_NAME_NAME_SHIFT (0U) -#define CCM_OBS_OBSERVE_NAME_NAME(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_NAME_NAME_SHIFT)) & CCM_OBS_OBSERVE_NAME_NAME_MASK) + +#define CCM_GPR_PRIVATE5_CLR_GPR_MASK (0xFFFFFFFFU) +#define CCM_GPR_PRIVATE5_CLR_GPR_SHIFT (0U) +/*! GPR - GP register + */ +#define CCM_GPR_PRIVATE5_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE5_CLR_GPR_MASK) /*! @} */ -/* The count of CCM_OBS_OBSERVE_NAME */ -#define CCM_OBS_OBSERVE_NAME_COUNT (6U) +/*! @name GPR_PRIVATE5_TOG - General Purpose Register */ +/*! @{ */ -/* The count of CCM_OBS_OBSERVE_CONFIG */ -#define CCM_OBS_OBSERVE_CONFIG_COUNT (6U) +#define CCM_GPR_PRIVATE5_TOG_GPR_MASK (0xFFFFFFFFU) +#define CCM_GPR_PRIVATE5_TOG_GPR_SHIFT (0U) +/*! GPR - GP register + */ +#define CCM_GPR_PRIVATE5_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE5_TOG_GPR_MASK) +/*! @} */ -/*! @name OBSERVE_AUTHEN - Observe access control */ +/*! @name GPR_PRIVATE5_AUTHEN - GPR access control */ /*! @{ */ -#define CCM_OBS_OBSERVE_AUTHEN_TZ_USER_MASK (0x1U) -#define CCM_OBS_OBSERVE_AUTHEN_TZ_USER_SHIFT (0U) + +#define CCM_GPR_PRIVATE5_AUTHEN_TZ_USER_MASK (0x1U) +#define CCM_GPR_PRIVATE5_AUTHEN_TZ_USER_SHIFT (0U) /*! TZ_USER - User access * 0b1..Clock can be changed in user mode. * 0b0..Clock cannot be changed in user mode. */ -#define CCM_OBS_OBSERVE_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TZ_USER_MASK) -#define CCM_OBS_OBSERVE_AUTHEN_TZ_NS_MASK (0x2U) -#define CCM_OBS_OBSERVE_AUTHEN_TZ_NS_SHIFT (1U) +#define CCM_GPR_PRIVATE5_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TZ_USER_MASK) + +#define CCM_GPR_PRIVATE5_AUTHEN_TZ_NS_MASK (0x2U) +#define CCM_GPR_PRIVATE5_AUTHEN_TZ_NS_SHIFT (1U) /*! TZ_NS - Non-secure access * 0b0..Cannot be changed in Non-secure mode. * 0b1..Can be changed in Non-secure mode. */ -#define CCM_OBS_OBSERVE_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TZ_NS_MASK) -#define CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_MASK (0x10U) -#define CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_SHIFT (4U) +#define CCM_GPR_PRIVATE5_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TZ_NS_MASK) + +#define CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ_MASK (0x10U) +#define CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ_SHIFT (4U) /*! LOCK_TZ - Lock truszone setting * 0b0..Trustzone setting is not locked. * 0b1..Trustzone setting is locked. */ -#define CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_MASK) -#define CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_MASK (0xF00U) -#define CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_SHIFT (8U) -/*! WHITE_LIST - White list - * 0b1111..All domain can change. - * 0b0010..Domain 1 can change. - * 0b0011..Domain 0 and domain 1 can change. - * 0b0000..No domain can change. - * 0b0100..Domain 2 can change. - * 0b0001..Domain 0 can change. +#define CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ_MASK) + +#define CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST_MASK (0xF00U) +#define CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST_SHIFT (8U) +/*! WHITE_LIST - Whitelist + * 0b0000..This domain is NOT allowed to change clock. + * 0b0001..This domain is allowed to change clock. */ -#define CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_MASK) -#define CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_MASK (0x1000U) -#define CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_SHIFT (12U) -/*! LOCK_LIST - Lock white list - * 0b0..White list is not locked. - * 0b1..White list is locked. +#define CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST_MASK) + +#define CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST_MASK (0x1000U) +#define CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock Whitelist + * 0b0..Whitelist is not locked. + * 0b1..Whitelist is locked. */ -#define CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_MASK) -#define CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_MASK (0x10000U) -#define CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_SHIFT (16U) -/*! DOMAIN_MODE - Low power and access control by domain - * 0b1..Clock works in domain mode. - * 0b0..Clock does not work in domain mode. +#define CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST_MASK) + +#define CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE_MASK (0x10000U) +#define CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by Domain + * 0b1..Clock works in Domain Mode. + * 0b0..Clock does NOT work in Domain Mode. */ -#define CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_MASK) -#define CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_MASK (0x100000U) -#define CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_SHIFT (20U) +#define CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE_MASK) + +#define CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE_MASK (0x100000U) +#define CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE_SHIFT (20U) /*! LOCK_MODE - Lock low power and access mode * 0b0..MODE is not locked. * 0b1..MODE is locked. */ -#define CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_MASK) +#define CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE_MASK) /*! @} */ -/* The count of CCM_OBS_OBSERVE_AUTHEN */ -#define CCM_OBS_OBSERVE_AUTHEN_COUNT (6U) - -/*! @name OBSERVE_AUTHEN_SET - Observe access control */ +/*! @name GPR_PRIVATE5_AUTHEN_SET - GPR access control */ /*! @{ */ -#define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_MASK (0x1U) -#define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_SHIFT (0U) + +#define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER_MASK (0x1U) +#define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER_SHIFT (0U) /*! TZ_USER - User access */ -#define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_MASK) -#define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_MASK (0x2U) -#define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_SHIFT (1U) +#define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER_MASK) + +#define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS_MASK (0x2U) +#define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS_SHIFT (1U) /*! TZ_NS - Non-secure access */ -#define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_MASK) -#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_MASK (0x10U) -#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_SHIFT (4U) +#define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS_MASK) + +#define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ_MASK (0x10U) +#define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ_SHIFT (4U) /*! LOCK_TZ - Lock truszone setting */ -#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_MASK) -#define CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_MASK (0xF00U) -#define CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_SHIFT (8U) -/*! WHITE_LIST - White list +#define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ_MASK) + +#define CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST_MASK (0xF00U) +#define CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST_SHIFT (8U) +/*! WHITE_LIST - Whitelist */ -#define CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_MASK) -#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_MASK (0x1000U) -#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_SHIFT (12U) -/*! LOCK_LIST - Lock white list +#define CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST_MASK) + +#define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST_MASK (0x1000U) +#define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock Whitelist */ -#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_MASK) -#define CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U) -#define CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U) -/*! DOMAIN_MODE - Low power and access control by domain +#define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST_MASK) + +#define CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U) +#define CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by Domain */ -#define CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_MASK) -#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_MASK (0x100000U) -#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_SHIFT (20U) +#define CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE_MASK) + +#define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE_MASK (0x100000U) +#define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE_SHIFT (20U) /*! LOCK_MODE - Lock low power and access mode */ -#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_MASK) +#define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE_MASK) /*! @} */ -/* The count of CCM_OBS_OBSERVE_AUTHEN_SET */ -#define CCM_OBS_OBSERVE_AUTHEN_SET_COUNT (6U) - -/*! @name OBSERVE_AUTHEN_CLR - Observe access control */ +/*! @name GPR_PRIVATE5_AUTHEN_CLR - GPR access control */ /*! @{ */ -#define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_MASK (0x1U) -#define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_SHIFT (0U) + +#define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER_MASK (0x1U) +#define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER_SHIFT (0U) /*! TZ_USER - User access */ -#define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_MASK) -#define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_MASK (0x2U) -#define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_SHIFT (1U) +#define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER_MASK) + +#define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS_MASK (0x2U) +#define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS_SHIFT (1U) /*! TZ_NS - Non-secure access */ -#define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_MASK) -#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_MASK (0x10U) -#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_SHIFT (4U) +#define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS_MASK) + +#define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ_MASK (0x10U) +#define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ_SHIFT (4U) /*! LOCK_TZ - Lock truszone setting */ -#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_MASK) -#define CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U) -#define CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_SHIFT (8U) -/*! WHITE_LIST - White list +#define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ_MASK) + +#define CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U) +#define CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST_SHIFT (8U) +/*! WHITE_LIST - Whitelist */ -#define CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_MASK) -#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U) -#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_SHIFT (12U) -/*! LOCK_LIST - Lock white list +#define CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST_MASK) + +#define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U) +#define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock Whitelist */ -#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_MASK) -#define CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U) -#define CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U) -/*! DOMAIN_MODE - Low power and access control by domain +#define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST_MASK) + +#define CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U) +#define CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by Domain */ -#define CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_MASK) -#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U) -#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_SHIFT (20U) +#define CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE_MASK) + +#define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U) +#define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE_SHIFT (20U) /*! LOCK_MODE - Lock low power and access mode */ -#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_MASK) +#define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE_MASK) /*! @} */ -/* The count of CCM_OBS_OBSERVE_AUTHEN_CLR */ -#define CCM_OBS_OBSERVE_AUTHEN_CLR_COUNT (6U) - -/*! @name OBSERVE_AUTHEN_TOG - Observe access control */ +/*! @name GPR_PRIVATE5_AUTHEN_TOG - GPR access control */ /*! @{ */ -#define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_MASK (0x1U) -#define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_SHIFT (0U) + +#define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER_MASK (0x1U) +#define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER_SHIFT (0U) /*! TZ_USER - User access */ -#define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_MASK) -#define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_MASK (0x2U) -#define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_SHIFT (1U) +#define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER_MASK) + +#define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS_MASK (0x2U) +#define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS_SHIFT (1U) /*! TZ_NS - Non-secure access */ -#define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_MASK) -#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_MASK (0x10U) -#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_SHIFT (4U) +#define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS_MASK) + +#define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ_MASK (0x10U) +#define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ_SHIFT (4U) /*! LOCK_TZ - Lock truszone setting */ -#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_MASK) -#define CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U) -#define CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_SHIFT (8U) -/*! WHITE_LIST - White list +#define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ_MASK) + +#define CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U) +#define CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST_SHIFT (8U) +/*! WHITE_LIST - Whitelist */ -#define CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_MASK) -#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U) -#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_SHIFT (12U) -/*! LOCK_LIST - Lock white list +#define CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST_MASK) + +#define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U) +#define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock Whitelist */ -#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_MASK) -#define CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U) -#define CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U) -/*! DOMAIN_MODE - Low power and access control by domain +#define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST_MASK) + +#define CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U) +#define CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by Domain */ -#define CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_MASK) -#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U) -#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_SHIFT (20U) +#define CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE_MASK) + +#define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U) +#define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE_SHIFT (20U) /*! LOCK_MODE - Lock low power and access mode */ -#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_MASK) +#define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE_MASK) /*! @} */ -/* The count of CCM_OBS_OBSERVE_AUTHEN_TOG */ -#define CCM_OBS_OBSERVE_AUTHEN_TOG_COUNT (6U) - -/*! @name OBSERVE_FREQUENCY_CURRENT - Current frequency detected */ +/*! @name GPR_PRIVATE6 - General Purpose Register */ /*! @{ */ -#define CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_MASK (0xFFFFFFFFU) -#define CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_SHIFT (0U) -/*! FREQUENCY - Frequency + +#define CCM_GPR_PRIVATE6_GPR_MASK (0xFFFFFFFFU) +#define CCM_GPR_PRIVATE6_GPR_SHIFT (0U) +/*! GPR - GP register */ -#define CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_SHIFT)) & CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_MASK) +#define CCM_GPR_PRIVATE6_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_GPR_SHIFT)) & CCM_GPR_PRIVATE6_GPR_MASK) /*! @} */ -/* The count of CCM_OBS_OBSERVE_FREQUENCY_CURRENT */ -#define CCM_OBS_OBSERVE_FREQUENCY_CURRENT_COUNT (6U) - -/*! @name OBSERVE_FREQUENCY_MIN - Minimum frequency detected */ +/*! @name GPR_PRIVATE6_SET - General Purpose Register */ /*! @{ */ -#define CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_MASK (0xFFFFFFFFU) -#define CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_SHIFT (0U) -/*! FREQUENCY - Frequency + +#define CCM_GPR_PRIVATE6_SET_GPR_MASK (0xFFFFFFFFU) +#define CCM_GPR_PRIVATE6_SET_GPR_SHIFT (0U) +/*! GPR - GP register */ -#define CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_SHIFT)) & CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_MASK) +#define CCM_GPR_PRIVATE6_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE6_SET_GPR_MASK) /*! @} */ -/* The count of CCM_OBS_OBSERVE_FREQUENCY_MIN */ -#define CCM_OBS_OBSERVE_FREQUENCY_MIN_COUNT (6U) - -/*! @name OBSERVE_FREQUENCY_MAX - Maximum frequency detected */ +/*! @name GPR_PRIVATE6_CLR - General Purpose Register */ /*! @{ */ -#define CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_MASK (0xFFFFFFFFU) -#define CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_SHIFT (0U) -/*! FREQUENCY - Frequency + +#define CCM_GPR_PRIVATE6_CLR_GPR_MASK (0xFFFFFFFFU) +#define CCM_GPR_PRIVATE6_CLR_GPR_SHIFT (0U) +/*! GPR - GP register */ -#define CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_SHIFT)) & CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_MASK) +#define CCM_GPR_PRIVATE6_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE6_CLR_GPR_MASK) /*! @} */ -/* The count of CCM_OBS_OBSERVE_FREQUENCY_MAX */ -#define CCM_OBS_OBSERVE_FREQUENCY_MAX_COUNT (6U) - -/*! @name OBSERVE_PERIOD_CURRENT - Current period time detected */ +/*! @name GPR_PRIVATE6_TOG - General Purpose Register */ /*! @{ */ -#define CCM_OBS_OBSERVE_PERIOD_CURRENT_PERIOD_MASK (0xFFFFFFFFU) -#define CCM_OBS_OBSERVE_PERIOD_CURRENT_PERIOD_SHIFT (0U) -/*! PERIOD - Period time + +#define CCM_GPR_PRIVATE6_TOG_GPR_MASK (0xFFFFFFFFU) +#define CCM_GPR_PRIVATE6_TOG_GPR_SHIFT (0U) +/*! GPR - GP register */ -#define CCM_OBS_OBSERVE_PERIOD_CURRENT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_PERIOD_CURRENT_PERIOD_SHIFT)) & CCM_OBS_OBSERVE_PERIOD_CURRENT_PERIOD_MASK) +#define CCM_GPR_PRIVATE6_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE6_TOG_GPR_MASK) /*! @} */ -/* The count of CCM_OBS_OBSERVE_PERIOD_CURRENT */ -#define CCM_OBS_OBSERVE_PERIOD_CURRENT_COUNT (6U) - -/*! @name OBSERVE_PERIOD_MIN - Minimum period time detected */ +/*! @name GPR_PRIVATE6_AUTHEN - GPR access control */ /*! @{ */ -#define CCM_OBS_OBSERVE_PERIOD_MIN_PERIOD_MASK (0xFFFFFFFFU) -#define CCM_OBS_OBSERVE_PERIOD_MIN_PERIOD_SHIFT (0U) -/*! PERIOD - Period time + +#define CCM_GPR_PRIVATE6_AUTHEN_TZ_USER_MASK (0x1U) +#define CCM_GPR_PRIVATE6_AUTHEN_TZ_USER_SHIFT (0U) +/*! TZ_USER - User access + * 0b1..Clock can be changed in user mode. + * 0b0..Clock cannot be changed in user mode. */ -#define CCM_OBS_OBSERVE_PERIOD_MIN_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_PERIOD_MIN_PERIOD_SHIFT)) & CCM_OBS_OBSERVE_PERIOD_MIN_PERIOD_MASK) -/*! @} */ +#define CCM_GPR_PRIVATE6_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TZ_USER_MASK) -/* The count of CCM_OBS_OBSERVE_PERIOD_MIN */ -#define CCM_OBS_OBSERVE_PERIOD_MIN_COUNT (6U) +#define CCM_GPR_PRIVATE6_AUTHEN_TZ_NS_MASK (0x2U) +#define CCM_GPR_PRIVATE6_AUTHEN_TZ_NS_SHIFT (1U) +/*! TZ_NS - Non-secure access + * 0b0..Cannot be changed in Non-secure mode. + * 0b1..Can be changed in Non-secure mode. + */ +#define CCM_GPR_PRIVATE6_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TZ_NS_MASK) -/*! @name OBSERVE_PERIOD_MAX - Maximum period time detected */ -/*! @{ */ -#define CCM_OBS_OBSERVE_PERIOD_MAX_PERIOD_MASK (0xFFFFFFFFU) -#define CCM_OBS_OBSERVE_PERIOD_MAX_PERIOD_SHIFT (0U) -/*! PERIOD - Period time +#define CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ_MASK (0x10U) +#define CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ_SHIFT (4U) +/*! LOCK_TZ - Lock truszone setting + * 0b0..Trustzone setting is not locked. + * 0b1..Trustzone setting is locked. */ -#define CCM_OBS_OBSERVE_PERIOD_MAX_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_PERIOD_MAX_PERIOD_SHIFT)) & CCM_OBS_OBSERVE_PERIOD_MAX_PERIOD_MASK) -/*! @} */ +#define CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ_MASK) -/* The count of CCM_OBS_OBSERVE_PERIOD_MAX */ -#define CCM_OBS_OBSERVE_PERIOD_MAX_COUNT (6U) +#define CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST_MASK (0xF00U) +#define CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST_SHIFT (8U) +/*! WHITE_LIST - Whitelist + * 0b0000..This domain is NOT allowed to change clock. + * 0b0001..This domain is allowed to change clock. + */ +#define CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST_MASK) -/*! @name OBSERVE_HIGH_CURRENT - Current high level time detected */ -/*! @{ */ -#define CCM_OBS_OBSERVE_HIGH_CURRENT_HIGH_MASK (0xFFFFFFFFU) -#define CCM_OBS_OBSERVE_HIGH_CURRENT_HIGH_SHIFT (0U) -/*! HIGH - High level time +#define CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST_MASK (0x1000U) +#define CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock Whitelist + * 0b0..Whitelist is not locked. + * 0b1..Whitelist is locked. */ -#define CCM_OBS_OBSERVE_HIGH_CURRENT_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_HIGH_CURRENT_HIGH_SHIFT)) & CCM_OBS_OBSERVE_HIGH_CURRENT_HIGH_MASK) -/*! @} */ +#define CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST_MASK) -/* The count of CCM_OBS_OBSERVE_HIGH_CURRENT */ -#define CCM_OBS_OBSERVE_HIGH_CURRENT_COUNT (6U) +#define CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE_MASK (0x10000U) +#define CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by Domain + * 0b1..Clock works in Domain Mode. + * 0b0..Clock does NOT work in Domain Mode. + */ +#define CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE_MASK) -/*! @name OBSERVE_HIGH_MIN - Minimum high level time detected */ -/*! @{ */ -#define CCM_OBS_OBSERVE_HIGH_MIN_HIGH_MASK (0xFFFFFFFFU) -#define CCM_OBS_OBSERVE_HIGH_MIN_HIGH_SHIFT (0U) -/*! HIGH - High level time +#define CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE_MASK (0x100000U) +#define CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE_SHIFT (20U) +/*! LOCK_MODE - Lock low power and access mode + * 0b0..MODE is not locked. + * 0b1..MODE is locked. */ -#define CCM_OBS_OBSERVE_HIGH_MIN_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_HIGH_MIN_HIGH_SHIFT)) & CCM_OBS_OBSERVE_HIGH_MIN_HIGH_MASK) +#define CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE_MASK) /*! @} */ -/* The count of CCM_OBS_OBSERVE_HIGH_MIN */ -#define CCM_OBS_OBSERVE_HIGH_MIN_COUNT (6U) - -/*! @name OBSERVE_HIGH_MAX - Maximum high level time detected */ +/*! @name GPR_PRIVATE6_AUTHEN_SET - GPR access control */ /*! @{ */ -#define CCM_OBS_OBSERVE_HIGH_MAX_HIGH_MASK (0xFFFFFFFFU) -#define CCM_OBS_OBSERVE_HIGH_MAX_HIGH_SHIFT (0U) -/*! HIGH - High level time + +#define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER_MASK (0x1U) +#define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER_SHIFT (0U) +/*! TZ_USER - User access */ -#define CCM_OBS_OBSERVE_HIGH_MAX_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_HIGH_MAX_HIGH_SHIFT)) & CCM_OBS_OBSERVE_HIGH_MAX_HIGH_MASK) -/*! @} */ +#define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER_MASK) -/* The count of CCM_OBS_OBSERVE_HIGH_MAX */ -#define CCM_OBS_OBSERVE_HIGH_MAX_COUNT (6U) +#define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS_MASK (0x2U) +#define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS_SHIFT (1U) +/*! TZ_NS - Non-secure access + */ +#define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS_MASK) -/*! @name OBSERVE_LOW_CURRENT - Current high level time detected */ -/*! @{ */ -#define CCM_OBS_OBSERVE_LOW_CURRENT_LOW_MASK (0xFFFFFFFFU) -#define CCM_OBS_OBSERVE_LOW_CURRENT_LOW_SHIFT (0U) -/*! LOW - High level time +#define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ_MASK (0x10U) +#define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ_SHIFT (4U) +/*! LOCK_TZ - Lock truszone setting */ -#define CCM_OBS_OBSERVE_LOW_CURRENT_LOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_LOW_CURRENT_LOW_SHIFT)) & CCM_OBS_OBSERVE_LOW_CURRENT_LOW_MASK) -/*! @} */ +#define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ_MASK) -/* The count of CCM_OBS_OBSERVE_LOW_CURRENT */ -#define CCM_OBS_OBSERVE_LOW_CURRENT_COUNT (6U) +#define CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST_MASK (0xF00U) +#define CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST_SHIFT (8U) +/*! WHITE_LIST - Whitelist + */ +#define CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST_MASK) -/*! @name OBSERVE_LOW_MIN - Minimum high level time detected */ -/*! @{ */ -#define CCM_OBS_OBSERVE_LOW_MIN_LOW_MASK (0xFFFFFFFFU) -#define CCM_OBS_OBSERVE_LOW_MIN_LOW_SHIFT (0U) -/*! LOW - High level time +#define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST_MASK (0x1000U) +#define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock Whitelist */ -#define CCM_OBS_OBSERVE_LOW_MIN_LOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_LOW_MIN_LOW_SHIFT)) & CCM_OBS_OBSERVE_LOW_MIN_LOW_MASK) -/*! @} */ +#define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST_MASK) -/* The count of CCM_OBS_OBSERVE_LOW_MIN */ -#define CCM_OBS_OBSERVE_LOW_MIN_COUNT (6U) +#define CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U) +#define CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by Domain + */ +#define CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE_MASK) -/*! @name OBSERVE_LOW_MAX - Maximum high level time detected */ -/*! @{ */ -#define CCM_OBS_OBSERVE_LOW_MAX_LOW_MASK (0xFFFFFFFFU) -#define CCM_OBS_OBSERVE_LOW_MAX_LOW_SHIFT (0U) -/*! LOW - High level time +#define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE_MASK (0x100000U) +#define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE_SHIFT (20U) +/*! LOCK_MODE - Lock low power and access mode */ -#define CCM_OBS_OBSERVE_LOW_MAX_LOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_LOW_MAX_LOW_SHIFT)) & CCM_OBS_OBSERVE_LOW_MAX_LOW_MASK) +#define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE_MASK) /*! @} */ -/* The count of CCM_OBS_OBSERVE_LOW_MAX */ -#define CCM_OBS_OBSERVE_LOW_MAX_COUNT (6U) +/*! @name GPR_PRIVATE6_AUTHEN_CLR - GPR access control */ +/*! @{ */ +#define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER_MASK (0x1U) +#define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER_SHIFT (0U) +/*! TZ_USER - User access + */ +#define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER_MASK) -/*! - * @} - */ /* end of group CCM_OBS_Register_Masks */ +#define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS_MASK (0x2U) +#define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS_SHIFT (1U) +/*! TZ_NS - Non-secure access + */ +#define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS_MASK) +#define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ_MASK (0x10U) +#define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ_SHIFT (4U) +/*! LOCK_TZ - Lock truszone setting + */ +#define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ_MASK) -/* CCM_OBS - Peripheral instance base addresses */ -/** Peripheral CCM_OBS base address */ -#define CCM_OBS_BASE (0x40150000u) -/** Peripheral CCM_OBS base pointer */ -#define CCM_OBS ((CCM_OBS_Type *)CCM_OBS_BASE) -/** Array initializer of CCM_OBS peripheral base addresses */ -#define CCM_OBS_BASE_ADDRS { CCM_OBS_BASE } -/** Array initializer of CCM_OBS peripheral base pointers */ -#define CCM_OBS_BASE_PTRS { CCM_OBS } +#define CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U) +#define CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST_SHIFT (8U) +/*! WHITE_LIST - Whitelist + */ +#define CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST_MASK) -/*! - * @} - */ /* end of group CCM_OBS_Peripheral_Access_Layer */ +#define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U) +#define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock Whitelist + */ +#define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST_MASK) +#define CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U) +#define CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by Domain + */ +#define CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE_MASK) -/* ---------------------------------------------------------------------------- - -- CMP Peripheral Access Layer - ---------------------------------------------------------------------------- */ +#define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U) +#define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE_SHIFT (20U) +/*! LOCK_MODE - Lock low power and access mode + */ +#define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE_MASK) +/*! @} */ -/*! - * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer - * @{ +/*! @name GPR_PRIVATE6_AUTHEN_TOG - GPR access control */ +/*! @{ */ + +#define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER_MASK (0x1U) +#define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER_SHIFT (0U) +/*! TZ_USER - User access */ +#define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER_MASK) -/** CMP - Register Layout Typedef */ -typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __IO uint32_t C0; /**< CMP Control Register 0, offset: 0x8 */ - __IO uint32_t C1; /**< CMP Control Register 1, offset: 0xC */ - __IO uint32_t C2; /**< CMP Control Register 2, offset: 0x10 */ - __IO uint32_t C3; /**< CMP Control Register 3, offset: 0x14 */ -} CMP_Type; +#define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS_MASK (0x2U) +#define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS_SHIFT (1U) +/*! TZ_NS - Non-secure access + */ +#define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS_MASK) -/* ---------------------------------------------------------------------------- - -- CMP Register Masks - ---------------------------------------------------------------------------- */ +#define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ_MASK (0x10U) +#define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ_SHIFT (4U) +/*! LOCK_TZ - Lock truszone setting + */ +#define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ_MASK) -/*! - * @addtogroup CMP_Register_Masks CMP Register Masks - * @{ +#define CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U) +#define CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST_SHIFT (8U) +/*! WHITE_LIST - Whitelist */ +#define CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST_MASK) -/*! @name VERID - Version ID Register */ -/*! @{ */ -#define CMP_VERID_FEATURE_MASK (0xFFFFU) -#define CMP_VERID_FEATURE_SHIFT (0U) -/*! FEATURE - Feature Specification Number. This read only filed returns the feature set number. +#define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U) +#define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock Whitelist */ -#define CMP_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_FEATURE_SHIFT)) & CMP_VERID_FEATURE_MASK) -#define CMP_VERID_MINOR_MASK (0xFF0000U) -#define CMP_VERID_MINOR_SHIFT (16U) -/*! MINOR - Minor Version Number. This read only field returns the minor version number for the module specification. +#define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST_MASK) + +#define CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U) +#define CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by Domain */ -#define CMP_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MINOR_SHIFT)) & CMP_VERID_MINOR_MASK) -#define CMP_VERID_MAJOR_MASK (0xFF000000U) -#define CMP_VERID_MAJOR_SHIFT (24U) -/*! MAJOR - Major Version Number. This read only field returns the major version number for the module specification. +#define CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE_MASK) + +#define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U) +#define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE_SHIFT (20U) +/*! LOCK_MODE - Lock low power and access mode */ -#define CMP_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MAJOR_SHIFT)) & CMP_VERID_MAJOR_MASK) +#define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE_MASK) /*! @} */ -/*! @name PARAM - Parameter Register */ +/*! @name GPR_PRIVATE7 - General Purpose Register */ /*! @{ */ -#define CMP_PARAM_PARAM_MASK (0xFFFFFFFFU) -#define CMP_PARAM_PARAM_SHIFT (0U) -/*! PARAM - Parameter Registers. This read only filed returns the feature parameters implemented along with the Version ID register. + +#define CCM_GPR_PRIVATE7_GPR_MASK (0xFFFFFFFFU) +#define CCM_GPR_PRIVATE7_GPR_SHIFT (0U) +/*! GPR - GP register */ -#define CMP_PARAM_PARAM(x) (((uint32_t)(((uint32_t)(x)) << CMP_PARAM_PARAM_SHIFT)) & CMP_PARAM_PARAM_MASK) +#define CCM_GPR_PRIVATE7_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_GPR_SHIFT)) & CCM_GPR_PRIVATE7_GPR_MASK) /*! @} */ -/*! @name C0 - CMP Control Register 0 */ +/*! @name GPR_PRIVATE7_SET - General Purpose Register */ /*! @{ */ -#define CMP_C0_HYSTCTR_MASK (0x3U) -#define CMP_C0_HYSTCTR_SHIFT (0U) -/*! HYSTCTR - Comparator hard block hysteresis control. See chip data sheet to get the actual hystersis value with each level - * 0b00..The hard block output has level 0 hysteresis internally. - * 0b01..The hard block output has level 1 hysteresis internally. - * 0b10..The hard block output has level 2 hysteresis internally. - * 0b11..The hard block output has level 3 hysteresis internally. + +#define CCM_GPR_PRIVATE7_SET_GPR_MASK (0xFFFFFFFFU) +#define CCM_GPR_PRIVATE7_SET_GPR_SHIFT (0U) +/*! GPR - GP register */ -#define CMP_C0_HYSTCTR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_HYSTCTR_SHIFT)) & CMP_C0_HYSTCTR_MASK) -#define CMP_C0_FILTER_CNT_MASK (0x70U) -#define CMP_C0_FILTER_CNT_SHIFT (4U) -/*! FILTER_CNT - Filter Sample Count - * 0b000..Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA. - * 0b001..1 consecutive sample must agree (comparator output is simply sampled). - * 0b010..2 consecutive samples must agree. - * 0b011..3 consecutive samples must agree. - * 0b100..4 consecutive samples must agree. - * 0b101..5 consecutive samples must agree. - * 0b110..6 consecutive samples must agree. - * 0b111..7 consecutive samples must agree. +#define CCM_GPR_PRIVATE7_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE7_SET_GPR_MASK) +/*! @} */ + +/*! @name GPR_PRIVATE7_CLR - General Purpose Register */ +/*! @{ */ + +#define CCM_GPR_PRIVATE7_CLR_GPR_MASK (0xFFFFFFFFU) +#define CCM_GPR_PRIVATE7_CLR_GPR_SHIFT (0U) +/*! GPR - GP register */ -#define CMP_C0_FILTER_CNT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FILTER_CNT_SHIFT)) & CMP_C0_FILTER_CNT_MASK) -#define CMP_C0_EN_MASK (0x100U) -#define CMP_C0_EN_SHIFT (8U) -/*! EN - Comparator Module Enable - * 0b0..Analog Comparator is disabled. - * 0b1..Analog Comparator is enabled. +#define CCM_GPR_PRIVATE7_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE7_CLR_GPR_MASK) +/*! @} */ + +/*! @name GPR_PRIVATE7_TOG - General Purpose Register */ +/*! @{ */ + +#define CCM_GPR_PRIVATE7_TOG_GPR_MASK (0xFFFFFFFFU) +#define CCM_GPR_PRIVATE7_TOG_GPR_SHIFT (0U) +/*! GPR - GP register */ -#define CMP_C0_EN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_EN_SHIFT)) & CMP_C0_EN_MASK) -#define CMP_C0_OPE_MASK (0x200U) -#define CMP_C0_OPE_SHIFT (9U) -/*! OPE - Comparator Output Pin Enable - * 0b0..When OPE is 0, the comparator output (after window/filter settings dependent on software configuration) is not available to a packaged pin. - * 0b1..When OPE is 1, and if the software has configured the comparator to own a packaged pin, the comparator is available in a packaged pin. +#define CCM_GPR_PRIVATE7_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE7_TOG_GPR_MASK) +/*! @} */ + +/*! @name GPR_PRIVATE7_AUTHEN - GPR access control */ +/*! @{ */ + +#define CCM_GPR_PRIVATE7_AUTHEN_TZ_USER_MASK (0x1U) +#define CCM_GPR_PRIVATE7_AUTHEN_TZ_USER_SHIFT (0U) +/*! TZ_USER - User access + * 0b1..Clock can be changed in user mode. + * 0b0..Clock cannot be changed in user mode. */ -#define CMP_C0_OPE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_OPE_SHIFT)) & CMP_C0_OPE_MASK) -#define CMP_C0_COS_MASK (0x400U) -#define CMP_C0_COS_SHIFT (10U) -/*! COS - Comparator Output Select - * 0b0..Set CMPO to equal COUT (filtered comparator output). - * 0b1..Set CMPO to equal COUTA (unfiltered comparator output). +#define CCM_GPR_PRIVATE7_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TZ_USER_MASK) + +#define CCM_GPR_PRIVATE7_AUTHEN_TZ_NS_MASK (0x2U) +#define CCM_GPR_PRIVATE7_AUTHEN_TZ_NS_SHIFT (1U) +/*! TZ_NS - Non-secure access + * 0b0..Cannot be changed in Non-secure mode. + * 0b1..Can be changed in Non-secure mode. */ -#define CMP_C0_COS(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COS_SHIFT)) & CMP_C0_COS_MASK) -#define CMP_C0_INVT_MASK (0x800U) -#define CMP_C0_INVT_SHIFT (11U) -/*! INVT - Comparator invert - * 0b0..Does not invert the comparator output. - * 0b1..Inverts the comparator output. +#define CCM_GPR_PRIVATE7_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TZ_NS_MASK) + +#define CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ_MASK (0x10U) +#define CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ_SHIFT (4U) +/*! LOCK_TZ - Lock truszone setting + * 0b0..Trustzone setting is not locked. + * 0b1..Trustzone setting is locked. */ -#define CMP_C0_INVT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_INVT_SHIFT)) & CMP_C0_INVT_MASK) -#define CMP_C0_PMODE_MASK (0x1000U) -#define CMP_C0_PMODE_SHIFT (12U) -/*! PMODE - Power Mode Select - * 0b0..Low Speed (LS) comparison mode is selected. - * 0b1..High Speed (HS) comparison mode is selected. +#define CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ_MASK) + +#define CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST_MASK (0xF00U) +#define CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST_SHIFT (8U) +/*! WHITE_LIST - Whitelist + * 0b0000..This domain is NOT allowed to change clock. + * 0b0001..This domain is allowed to change clock. */ -#define CMP_C0_PMODE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_PMODE_SHIFT)) & CMP_C0_PMODE_MASK) -#define CMP_C0_WE_MASK (0x4000U) -#define CMP_C0_WE_SHIFT (14U) -/*! WE - Windowing Enable - * 0b0..Windowing mode is not selected. - * 0b1..Windowing mode is selected. +#define CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST_MASK) + +#define CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST_MASK (0x1000U) +#define CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock Whitelist + * 0b0..Whitelist is not locked. + * 0b1..Whitelist is locked. */ -#define CMP_C0_WE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_WE_SHIFT)) & CMP_C0_WE_MASK) -#define CMP_C0_SE_MASK (0x8000U) -#define CMP_C0_SE_SHIFT (15U) -/*! SE - Sample Enable - * 0b0..Sampling mode is not selected. - * 0b1..Sampling mode is selected. +#define CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST_MASK) + +#define CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE_MASK (0x10000U) +#define CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by Domain + * 0b1..Clock works in Domain Mode. + * 0b0..Clock does NOT work in Domain Mode. */ -#define CMP_C0_SE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_SE_SHIFT)) & CMP_C0_SE_MASK) -#define CMP_C0_FPR_MASK (0xFF0000U) -#define CMP_C0_FPR_SHIFT (16U) -/*! FPR - Filter Sample Period +#define CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE_MASK) + +#define CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE_MASK (0x100000U) +#define CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE_SHIFT (20U) +/*! LOCK_MODE - Lock low power and access mode + * 0b0..MODE is not locked. + * 0b1..MODE is locked. */ -#define CMP_C0_FPR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FPR_SHIFT)) & CMP_C0_FPR_MASK) -#define CMP_C0_COUT_MASK (0x1000000U) -#define CMP_C0_COUT_SHIFT (24U) -/*! COUT - Analog Comparator Output +#define CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE_MASK) +/*! @} */ + +/*! @name GPR_PRIVATE7_AUTHEN_SET - GPR access control */ +/*! @{ */ + +#define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER_MASK (0x1U) +#define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER_SHIFT (0U) +/*! TZ_USER - User access */ -#define CMP_C0_COUT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COUT_SHIFT)) & CMP_C0_COUT_MASK) -#define CMP_C0_CFF_MASK (0x2000000U) -#define CMP_C0_CFF_SHIFT (25U) -/*! CFF - Analog Comparator Flag Falling - * 0b0..A falling edge has not been detected on COUT. - * 0b1..A falling edge on COUT has occurred. +#define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER_MASK) + +#define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS_MASK (0x2U) +#define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS_SHIFT (1U) +/*! TZ_NS - Non-secure access */ -#define CMP_C0_CFF(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFF_SHIFT)) & CMP_C0_CFF_MASK) -#define CMP_C0_CFR_MASK (0x4000000U) -#define CMP_C0_CFR_SHIFT (26U) -/*! CFR - Analog Comparator Flag Rising - * 0b0..A rising edge has not been detected on COUT. - * 0b1..A rising edge on COUT has occurred. +#define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS_MASK) + +#define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ_MASK (0x10U) +#define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ_SHIFT (4U) +/*! LOCK_TZ - Lock truszone setting */ -#define CMP_C0_CFR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK) -#define CMP_C0_IEF_MASK (0x8000000U) -#define CMP_C0_IEF_SHIFT (27U) -/*! IEF - Comparator Interrupt Enable Falling - * 0b0..Interrupt is disabled. - * 0b1..Interrupt is enabled. +#define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ_MASK) + +#define CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST_MASK (0xF00U) +#define CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST_SHIFT (8U) +/*! WHITE_LIST - Whitelist */ -#define CMP_C0_IEF(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IEF_SHIFT)) & CMP_C0_IEF_MASK) -#define CMP_C0_IER_MASK (0x10000000U) -#define CMP_C0_IER_SHIFT (28U) -/*! IER - Comparator Interrupt Enable Rising - * 0b0..Interrupt is disabled. - * 0b1..Interrupt is enabled. +#define CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST_MASK) + +#define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST_MASK (0x1000U) +#define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock Whitelist */ -#define CMP_C0_IER(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IER_SHIFT)) & CMP_C0_IER_MASK) -#define CMP_C0_DMAEN_MASK (0x40000000U) -#define CMP_C0_DMAEN_SHIFT (30U) -/*! DMAEN - DMA Enable - * 0b0..DMA is disabled. - * 0b1..DMA is enabled. +#define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST_MASK) + +#define CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U) +#define CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by Domain */ -#define CMP_C0_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_DMAEN_SHIFT)) & CMP_C0_DMAEN_MASK) -#define CMP_C0_LINKEN_MASK (0x80000000U) -#define CMP_C0_LINKEN_SHIFT (31U) -/*! LINKEN - CMP to DAC link enable. - * 0b0..CMP to DAC link is disabled - * 0b1..CMP to DAC link is enabled. +#define CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE_MASK) + +#define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE_MASK (0x100000U) +#define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE_SHIFT (20U) +/*! LOCK_MODE - Lock low power and access mode */ -#define CMP_C0_LINKEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_LINKEN_SHIFT)) & CMP_C0_LINKEN_MASK) +#define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE_MASK) /*! @} */ -/*! @name C1 - CMP Control Register 1 */ +/*! @name GPR_PRIVATE7_AUTHEN_CLR - GPR access control */ /*! @{ */ -#define CMP_C1_VOSEL_MASK (0xFFU) -#define CMP_C1_VOSEL_SHIFT (0U) -/*! VOSEL - DAC Output Voltage Select + +#define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER_MASK (0x1U) +#define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER_SHIFT (0U) +/*! TZ_USER - User access */ -#define CMP_C1_VOSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VOSEL_SHIFT)) & CMP_C1_VOSEL_MASK) -#define CMP_C1_DMODE_MASK (0x100U) -#define CMP_C1_DMODE_SHIFT (8U) -/*! DMODE - DAC Mode Selection - * 0b0..DAC is selected to work in low speed and low power mode. - * 0b1..DAC is selected to work in high speed high power mode. +#define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER_MASK) + +#define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS_MASK (0x2U) +#define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS_SHIFT (1U) +/*! TZ_NS - Non-secure access */ -#define CMP_C1_DMODE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DMODE_SHIFT)) & CMP_C1_DMODE_MASK) -#define CMP_C1_VRSEL_MASK (0x200U) -#define CMP_C1_VRSEL_SHIFT (9U) -/*! VRSEL - Supply Voltage Reference Source Select - * 0b0..Vin1 is selected as resistor ladder network supply reference Vin. Vin1 is from internal PMC. - * 0b1..Vin2 is selected as resistor ladder network supply reference Vin. Vin2 is from PAD. +#define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS_MASK) + +#define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ_MASK (0x10U) +#define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ_SHIFT (4U) +/*! LOCK_TZ - Lock truszone setting */ -#define CMP_C1_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VRSEL_SHIFT)) & CMP_C1_VRSEL_MASK) -#define CMP_C1_DACEN_MASK (0x400U) -#define CMP_C1_DACEN_SHIFT (10U) -/*! DACEN - DAC Enable - * 0b0..DAC is disabled. - * 0b1..DAC is enabled. +#define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ_MASK) + +#define CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U) +#define CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST_SHIFT (8U) +/*! WHITE_LIST - Whitelist */ -#define CMP_C1_DACEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DACEN_SHIFT)) & CMP_C1_DACEN_MASK) -#define CMP_C1_DACOE_MASK (0x800U) -#define CMP_C1_DACOE_SHIFT (11U) -/*! DACOE - DAC Output Enable - * 0b0..DAC output is enabled - * 0b1..DAC output is disabled +#define CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST_MASK) + +#define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U) +#define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock Whitelist */ -#define CMP_C1_DACOE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DACOE_SHIFT)) & CMP_C1_DACOE_MASK) -#define CMP_C1_CHN0_MASK (0x10000U) -#define CMP_C1_CHN0_SHIFT (16U) -/*! CHN0 - Channel 0 input enable +#define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST_MASK) + +#define CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U) +#define CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by Domain */ -#define CMP_C1_CHN0(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN0_SHIFT)) & CMP_C1_CHN0_MASK) -#define CMP_C1_CHN1_MASK (0x20000U) -#define CMP_C1_CHN1_SHIFT (17U) -/*! CHN1 - Channel 1 input enable +#define CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE_MASK) + +#define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U) +#define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE_SHIFT (20U) +/*! LOCK_MODE - Lock low power and access mode */ -#define CMP_C1_CHN1(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN1_SHIFT)) & CMP_C1_CHN1_MASK) -#define CMP_C1_CHN2_MASK (0x40000U) -#define CMP_C1_CHN2_SHIFT (18U) -/*! CHN2 - Channel 2 input enable +#define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE_MASK) +/*! @} */ + +/*! @name GPR_PRIVATE7_AUTHEN_TOG - GPR access control */ +/*! @{ */ + +#define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER_MASK (0x1U) +#define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER_SHIFT (0U) +/*! TZ_USER - User access */ -#define CMP_C1_CHN2(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN2_SHIFT)) & CMP_C1_CHN2_MASK) -#define CMP_C1_CHN3_MASK (0x80000U) -#define CMP_C1_CHN3_SHIFT (19U) -/*! CHN3 - Channel 3 input enable +#define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER_MASK) + +#define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS_MASK (0x2U) +#define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS_SHIFT (1U) +/*! TZ_NS - Non-secure access */ -#define CMP_C1_CHN3(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN3_SHIFT)) & CMP_C1_CHN3_MASK) -#define CMP_C1_CHN4_MASK (0x100000U) -#define CMP_C1_CHN4_SHIFT (20U) -/*! CHN4 - Channel 4 input enable +#define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS_MASK) + +#define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ_MASK (0x10U) +#define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ_SHIFT (4U) +/*! LOCK_TZ - Lock truszone setting */ -#define CMP_C1_CHN4(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN4_SHIFT)) & CMP_C1_CHN4_MASK) -#define CMP_C1_CHN5_MASK (0x200000U) -#define CMP_C1_CHN5_SHIFT (21U) -/*! CHN5 - Channel 5 input enable +#define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ_MASK) + +#define CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U) +#define CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST_SHIFT (8U) +/*! WHITE_LIST - Whitelist */ -#define CMP_C1_CHN5(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN5_SHIFT)) & CMP_C1_CHN5_MASK) -#define CMP_C1_MSEL_MASK (0x7000000U) -#define CMP_C1_MSEL_SHIFT (24U) -/*! MSEL - Minus Input MUX Control - * 0b000..Internal Negative Input 0 for Minus Channel -- Internal Minus Input - * 0b001..External Input 1 for Minus Channel -- Reference Input 0 - * 0b010..External Input 2 for Minus Channel -- Reference Input 1 - * 0b011..External Input 3 for Minus Channel -- Reference Input 2 - * 0b100..External Input 4 for Minus Channel -- Reference Input 3 - * 0b101..External Input 5 for Minus Channel -- Reference Input 4 - * 0b110..External Input 6 for Minus Channel -- Reference Input 5 - * 0b111..Internal 8b DAC output +#define CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST_MASK) + +#define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U) +#define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock Whitelist */ -#define CMP_C1_MSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_MSEL_SHIFT)) & CMP_C1_MSEL_MASK) -#define CMP_C1_PSEL_MASK (0x70000000U) -#define CMP_C1_PSEL_SHIFT (28U) -/*! PSEL - Plus Input MUX Control - * 0b000..Internal Positive Input 0 for Plus Channel -- Internal Plus Input - * 0b001..External Input 1 for Plus Channel -- Reference Input 0 - * 0b010..External Input 2 for Plus Channel -- Reference Input 1 - * 0b011..External Input 3 for Plus Channel -- Reference Input 2 - * 0b100..External Input 4 for Plus Channel -- Reference Input 3 - * 0b101..External Input 5 for Plus Channel -- Reference Input 4 - * 0b110..External Input 6 for Plus Channel -- Reference Input 5 - * 0b111..Internal 8b DAC output +#define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST_MASK) + +#define CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U) +#define CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by Domain */ -#define CMP_C1_PSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_PSEL_SHIFT)) & CMP_C1_PSEL_MASK) +#define CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE_MASK) + +#define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U) +#define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE_SHIFT (20U) +/*! LOCK_MODE - Lock low power and access mode + */ +#define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE_MASK) /*! @} */ -/*! @name C2 - CMP Control Register 2 */ +/*! @name OSCPLL_DIRECT - Clock source direct control */ /*! @{ */ -#define CMP_C2_ACOn_MASK (0x3FU) -#define CMP_C2_ACOn_SHIFT (0U) -/*! ACOn - ACOn - */ -#define CMP_C2_ACOn(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_ACOn_SHIFT)) & CMP_C2_ACOn_MASK) -#define CMP_C2_INITMOD_MASK (0x3F00U) -#define CMP_C2_INITMOD_SHIFT (8U) -/*! INITMOD - Comparator and DAC initialization delay modulus. - */ -#define CMP_C2_INITMOD(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_INITMOD_SHIFT)) & CMP_C2_INITMOD_MASK) -#define CMP_C2_NSAM_MASK (0xC000U) -#define CMP_C2_NSAM_SHIFT (14U) -/*! NSAM - Number of sample clocks - * 0b00..The comparison result is sampled as soon as the active channel is scanned in one round-robin clock. - * 0b01..The sampling takes place 1 round-robin clock cycle after the next cycle of the round-robin clock. - * 0b10..The sampling takes place 2 round-robin clock cycles after the next cycle of the round-robin clock. - * 0b11..The sampling takes place 3 round-robin clock cycles after the next cycle of the round-robin clock. - */ -#define CMP_C2_NSAM(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_NSAM_SHIFT)) & CMP_C2_NSAM_MASK) -#define CMP_C2_CH0F_MASK (0x10000U) -#define CMP_C2_CH0F_SHIFT (16U) -/*! CH0F - CH0F - */ -#define CMP_C2_CH0F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH0F_SHIFT)) & CMP_C2_CH0F_MASK) -#define CMP_C2_CH1F_MASK (0x20000U) -#define CMP_C2_CH1F_SHIFT (17U) -/*! CH1F - CH1F + +#define CCM_OSCPLL_DIRECT_ON_MASK (0x1U) +#define CCM_OSCPLL_DIRECT_ON_SHIFT (0U) +/*! ON - turn on clock source + * 0b0..OSCPLL is OFF + * 0b1..OSCPLL is ON */ -#define CMP_C2_CH1F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH1F_SHIFT)) & CMP_C2_CH1F_MASK) -#define CMP_C2_CH2F_MASK (0x40000U) -#define CMP_C2_CH2F_SHIFT (18U) -/*! CH2F - CH2F +#define CCM_OSCPLL_DIRECT_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DIRECT_ON_SHIFT)) & CCM_OSCPLL_DIRECT_ON_MASK) +/*! @} */ + +/* The count of CCM_OSCPLL_DIRECT */ +#define CCM_OSCPLL_DIRECT_COUNT (29U) + +/*! @name OSCPLL_DOMAIN - Clock source domain control */ +/*! @{ */ + +#define CCM_OSCPLL_DOMAIN_LEVEL_MASK (0x7U) +#define CCM_OSCPLL_DOMAIN_LEVEL_SHIFT (0U) +/*! LEVEL - Current dependence level + * 0b000..This clock source is not needed in any mode, and can be turned off + * 0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode + * 0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode + * 0b011..This clock source is needed in RUN, WAIT and STOP mode + * 0b100..This clock source is always on in any mode (including SUSPEND) + * 0b101, 0b110, 0b111..Reserved */ -#define CMP_C2_CH2F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH2F_SHIFT)) & CMP_C2_CH2F_MASK) -#define CMP_C2_CH3F_MASK (0x80000U) -#define CMP_C2_CH3F_SHIFT (19U) -/*! CH3F - CH3F +#define CCM_OSCPLL_DOMAIN_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL_MASK) + +#define CCM_OSCPLL_DOMAIN_LEVEL0_MASK (0x70000U) +#define CCM_OSCPLL_DOMAIN_LEVEL0_SHIFT (16U) +/*! LEVEL0 - Dependence level + * 0b000..This clock source is not needed in any mode, and can be turned off + * 0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode + * 0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode + * 0b011..This clock source is needed in RUN, WAIT and STOP mode + * 0b100..This clock source is always on in any mode (including SUSPEND) + * 0b101, 0b110, 0b111..Reserved */ -#define CMP_C2_CH3F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH3F_SHIFT)) & CMP_C2_CH3F_MASK) -#define CMP_C2_CH4F_MASK (0x100000U) -#define CMP_C2_CH4F_SHIFT (20U) -/*! CH4F - CH4F +#define CCM_OSCPLL_DOMAIN_LEVEL0(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL0_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL0_MASK) + +#define CCM_OSCPLL_DOMAIN_LEVEL1_MASK (0x700000U) +#define CCM_OSCPLL_DOMAIN_LEVEL1_SHIFT (20U) +/*! LEVEL1 - Depend level + * 0b000..This clock source is not needed in any mode, and can be turned off + * 0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode + * 0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode + * 0b011..This clock source is needed in RUN, WAIT and STOP mode + * 0b100..This clock source is always on in any mode (including SUSPEND) + * 0b101, 0b110, 0b111..Reserved */ -#define CMP_C2_CH4F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH4F_SHIFT)) & CMP_C2_CH4F_MASK) -#define CMP_C2_CH5F_MASK (0x200000U) -#define CMP_C2_CH5F_SHIFT (21U) -/*! CH5F - CH5F +#define CCM_OSCPLL_DOMAIN_LEVEL1(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL1_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL1_MASK) + +#define CCM_OSCPLL_DOMAIN_LEVEL2_MASK (0x7000000U) +#define CCM_OSCPLL_DOMAIN_LEVEL2_SHIFT (24U) +/*! LEVEL2 - Depend level + * 0b000..This clock source is not needed in any mode, and can be turned off + * 0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode + * 0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode + * 0b011..This clock source is needed in RUN, WAIT and STOP mode + * 0b100..This clock source is always on in any mode (including SUSPEND) + * 0b101, 0b110, 0b111..Reserved */ -#define CMP_C2_CH5F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH5F_SHIFT)) & CMP_C2_CH5F_MASK) -#define CMP_C2_FXMXCH_MASK (0xE000000U) -#define CMP_C2_FXMXCH_SHIFT (25U) -/*! FXMXCH - Fixed channel selection - * 0b000..External Reference Input 0 is selected as the fixed reference input for the fixed mux port. - * 0b001..External Reference Input 1 is selected as the fixed reference input for the fixed mux port. - * 0b010..External Reference Input 2 is selected as the fixed reference input for the fixed mux port. - * 0b011..External Reference Input 3 is selected as the fixed reference input for the fixed mux port. - * 0b100..External Reference Input 4 is selected as the fixed reference input for the fixed mux port. - * 0b101..External Reference Input 5 is selected as the fixed reference input for the fixed mux port. - * 0b110..Reserved. - * 0b111..The 8bit DAC is selected as the fixed reference input for the fixed mux port. +#define CCM_OSCPLL_DOMAIN_LEVEL2(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL2_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL2_MASK) + +#define CCM_OSCPLL_DOMAIN_LEVEL3_MASK (0x70000000U) +#define CCM_OSCPLL_DOMAIN_LEVEL3_SHIFT (28U) +/*! LEVEL3 - Depend level + * 0b000..This clock source is not needed in any mode, and can be turned off + * 0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode + * 0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode + * 0b011..This clock source is needed in RUN, WAIT and STOP mode + * 0b100..This clock source is always on in any mode (including SUSPEND) + * 0b101, 0b110, 0b111..Reserved */ -#define CMP_C2_FXMXCH(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMXCH_SHIFT)) & CMP_C2_FXMXCH_MASK) -#define CMP_C2_FXMP_MASK (0x20000000U) -#define CMP_C2_FXMP_SHIFT (29U) -/*! FXMP - Fixed MUX Port - * 0b0..The Plus port is fixed. Only the inputs to the Minus port are swept in each round. - * 0b1..The Minus port is fixed. Only the inputs to the Plus port are swept in each round. +#define CCM_OSCPLL_DOMAIN_LEVEL3(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL3_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL3_MASK) +/*! @} */ + +/* The count of CCM_OSCPLL_DOMAIN */ +#define CCM_OSCPLL_DOMAIN_COUNT (29U) + +/*! @name OSCPLL_SETPOINT - Clock source Setpoint setting */ +/*! @{ */ + +#define CCM_OSCPLL_SETPOINT_SETPOINT_MASK (0xFFFFU) +#define CCM_OSCPLL_SETPOINT_SETPOINT_SHIFT (0U) +/*! SETPOINT - Setpoint */ -#define CMP_C2_FXMP(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMP_SHIFT)) & CMP_C2_FXMP_MASK) -#define CMP_C2_RRIE_MASK (0x40000000U) -#define CMP_C2_RRIE_SHIFT (30U) -/*! RRIE - Round-Robin interrupt enable - * 0b0..The round-robin interrupt is disabled. - * 0b1..The round-robin interrupt is enabled when a comparison result changes from the last sample. +#define CCM_OSCPLL_SETPOINT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_SETPOINT_SETPOINT_SHIFT)) & CCM_OSCPLL_SETPOINT_SETPOINT_MASK) + +#define CCM_OSCPLL_SETPOINT_STANDBY_MASK (0xFFFF0000U) +#define CCM_OSCPLL_SETPOINT_STANDBY_SHIFT (16U) +/*! STANDBY - Standby */ -#define CMP_C2_RRIE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_RRIE_SHIFT)) & CMP_C2_RRIE_MASK) +#define CCM_OSCPLL_SETPOINT_STANDBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_SETPOINT_STANDBY_SHIFT)) & CCM_OSCPLL_SETPOINT_STANDBY_MASK) /*! @} */ -/*! @name C3 - CMP Control Register 3 */ +/* The count of CCM_OSCPLL_SETPOINT */ +#define CCM_OSCPLL_SETPOINT_COUNT (29U) + +/*! @name OSCPLL_STATUS0 - Clock source working status */ /*! @{ */ -#define CMP_C3_ACPH2TC_MASK (0x70U) -#define CMP_C3_ACPH2TC_SHIFT (4U) -/*! ACPH2TC - Analog Comparator Phase2 Timing Control. - * 0b000..Phase2 active time in one sampling period equals to T - * 0b001..Phase2 active time in one sampling period equals to 2*T - * 0b010..Phase2 active time in one sampling period equals to 4*T - * 0b011..Phase2 active time in one sampling period equals to 8*T - * 0b100..Phase2 active time in one sampling period equals to 16*T - * 0b101..Phase2 active time in one sampling period equals to 32*T - * 0b110..Phase2 active time in one sampling period equals to 64*T - * 0b111..Phase2 active time in one sampling period equals to 16*T - */ -#define CMP_C3_ACPH2TC(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH2TC_SHIFT)) & CMP_C3_ACPH2TC_MASK) -#define CMP_C3_ACPH1TC_MASK (0x700U) -#define CMP_C3_ACPH1TC_SHIFT (8U) -/*! ACPH1TC - Analog Comparator Phase1 Timing Control. - * 0b000..Phase1 active time in one sampling period equals to T - * 0b001..Phase1 active time in one sampling period equals to 2*T - * 0b010..Phase1 active time in one sampling period equals to 4*T - * 0b011..Phase1 active time in one sampling period equals to 8*T - * 0b100..Phase1 active time in one sampling period equals to T - * 0b101..Phase1 active time in one sampling period equals to T - * 0b110..Phase1 active time in one sampling period equals to T - * 0b111..Phase1 active time in one sampling period equals to 0 + +#define CCM_OSCPLL_STATUS0_ON_MASK (0x1U) +#define CCM_OSCPLL_STATUS0_ON_SHIFT (0U) +/*! ON - Clock source current state + * 0b0..Clock source is OFF + * 0b1..Clock source is ON */ -#define CMP_C3_ACPH1TC(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH1TC_SHIFT)) & CMP_C3_ACPH1TC_MASK) -#define CMP_C3_ACSAT_MASK (0x7000U) -#define CMP_C3_ACSAT_SHIFT (12U) -/*! ACSAT - Analog Comparator Sampling Time control. - * 0b000..The sampling time equals to T - * 0b001..The sampling time equasl to 2*T - * 0b010..The sampling time equasl to 4*T - * 0b011..The sampling time equasl to 8*T - * 0b100..The sampling time equasl to 16*T - * 0b101..The sampling time equasl to 32*T - * 0b110..The sampling time equasl to 64*T - * 0b111..The sampling time equasl to 256*T +#define CCM_OSCPLL_STATUS0_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_ON_SHIFT)) & CCM_OSCPLL_STATUS0_ON_MASK) + +#define CCM_OSCPLL_STATUS0_STATUS_EARLY_MASK (0x10U) +#define CCM_OSCPLL_STATUS0_STATUS_EARLY_SHIFT (4U) +/*! STATUS_EARLY - Clock source active + * 0b1..Clock source is active + * 0b0..Clock source is not active */ -#define CMP_C3_ACSAT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACSAT_SHIFT)) & CMP_C3_ACSAT_MASK) -#define CMP_C3_DMCS_MASK (0x10000U) -#define CMP_C3_DMCS_SHIFT (16U) -/*! DMCS - Discrete Mode Clock Selection - * 0b0..Slow clock is selected for the timing generation. - * 0b1..Fast clock is selected for the timing generation. +#define CCM_OSCPLL_STATUS0_STATUS_EARLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_STATUS_EARLY_SHIFT)) & CCM_OSCPLL_STATUS0_STATUS_EARLY_MASK) + +#define CCM_OSCPLL_STATUS0_STATUS_LATE_MASK (0x20U) +#define CCM_OSCPLL_STATUS0_STATUS_LATE_SHIFT (5U) +/*! STATUS_LATE - Clock source ready + * 0b1..Clock source is ready to use + * 0b0..Clock source is not ready to use */ -#define CMP_C3_DMCS(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_DMCS_SHIFT)) & CMP_C3_DMCS_MASK) -#define CMP_C3_RDIVE_MASK (0x100000U) -#define CMP_C3_RDIVE_SHIFT (20U) -/*! RDIVE - Resistor Divider Enable - * 0b0..The resistor is not enabled even when either NCHEN or PCHEN is set to1 but the actual input is in the range of 0 - 1.8v. - * 0b1..The resistor is enabled because the inputs are above 1.8v. +#define CCM_OSCPLL_STATUS0_STATUS_LATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_STATUS_LATE_SHIFT)) & CCM_OSCPLL_STATUS0_STATUS_LATE_MASK) + +#define CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_MASK (0xF00U) +#define CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_SHIFT (8U) +/*! ACTIVE_DOMAIN - Domains that own this clock source + * 0b0000..Clock not owned by any domain + * 0b0001..Clock owned by Domain0 + * 0b0010..Clock owned by Domain1 + * 0b0011..Clock owned by Domain0 and Domain1 + * 0b0100..Clock owned by Domain2 + * 0b0101..Clock owned by Domain0 and Domain2 + * 0b0110..Clock owned by Domain1 and Domain2 + * 0b0111..Clock owned by Domain0, Domain1 and Domain 2 + * 0b1000..Clock owned by Domain3 + * 0b1001..Clock owned by Domain0 and Domain3 + * 0b1010..Clock owned by Domain1 and Domain3 + * 0b1011..Clock owned by Domain2 and Domain3 + * 0b1100..Clock owned by Domain0, Domain 1, and Domain3 + * 0b1101..Clock owned by Domain0, Domain 2, and Domain3 + * 0b1110..Clock owned by Domain1, Domain 2, and Domain3 + * 0b1111..Clock owned by all domains */ -#define CMP_C3_RDIVE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_RDIVE_SHIFT)) & CMP_C3_RDIVE_MASK) -#define CMP_C3_NCHCTEN_MASK (0x1000000U) -#define CMP_C3_NCHCTEN_SHIFT (24U) -/*! NCHCTEN - Negative Channel Continuous Mode Enable. - * 0b0..Negative channel is in Discrete Mode and special timing needs to be configured. - * 0b1..Negative channel is in Continuous Mode and no special timing is requried. +#define CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_SHIFT)) & CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_MASK) + +#define CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_MASK (0xF000U) +#define CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_SHIFT (12U) +/*! DOMAIN_ENABLE - Enable status from each domain + * 0b0000..No domain request + * 0b0001..Request from Domain0 + * 0b0010..Request from Domain1 + * 0b0011..Request from Domain0 and Domain1 + * 0b0100..Request from Domain2 + * 0b0101..Request from Domain0 and Domain2 + * 0b0110..Request from Domain1 and Domain2 + * 0b0111..Request from Domain0, Domain1 and Domain 2 + * 0b1000..Request from Domain3 + * 0b1001..Request from Domain0 and Domain3 + * 0b1010..Request from Domain1 and Domain3 + * 0b1011..Request from Domain2 and Domain3 + * 0b1100..Request from Domain0, Domain 1, and Domain3 + * 0b1101..Request from Domain0, Domain 2, and Domain3 + * 0b1110..Request from Domain1, Domain 2, and Domain3 + * 0b1111..Request from all domains */ -#define CMP_C3_NCHCTEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_NCHCTEN_SHIFT)) & CMP_C3_NCHCTEN_MASK) -#define CMP_C3_PCHCTEN_MASK (0x10000000U) -#define CMP_C3_PCHCTEN_SHIFT (28U) -/*! PCHCTEN - Positive Channel Continuous Mode Enable. - * 0b0..Positive channel is in Discrete Mode and special timing needs to be configured. - * 0b1..Positive channel is in Continuous Mode and no special timing is requried. +#define CCM_OSCPLL_STATUS0_DOMAIN_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_SHIFT)) & CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_MASK) + +#define CCM_OSCPLL_STATUS0_IN_USE_MASK (0x10000000U) +#define CCM_OSCPLL_STATUS0_IN_USE_SHIFT (28U) +/*! IN_USE - In use + * 0b1..Clock source is being used by clock roots + * 0b0..Clock source is not being used by clock roots */ -#define CMP_C3_PCHCTEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_PCHCTEN_SHIFT)) & CMP_C3_PCHCTEN_MASK) +#define CCM_OSCPLL_STATUS0_IN_USE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_IN_USE_SHIFT)) & CCM_OSCPLL_STATUS0_IN_USE_MASK) /*! @} */ +/* The count of CCM_OSCPLL_STATUS0 */ +#define CCM_OSCPLL_STATUS0_COUNT (29U) -/*! - * @} - */ /* end of group CMP_Register_Masks */ +/*! @name OSCPLL_STATUS1 - Clock source low power status */ +/*! @{ */ +#define CCM_OSCPLL_STATUS1_CPU0_MODE_MASK (0x3U) +#define CCM_OSCPLL_STATUS1_CPU0_MODE_SHIFT (0U) +/*! CPU0_MODE - Domain0 Low Power Mode + * 0b00..Run + * 0b01..Wait + * 0b10..Stop + * 0b11..Suspend + */ +#define CCM_OSCPLL_STATUS1_CPU0_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU0_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU0_MODE_MASK) -/* CMP - Peripheral instance base addresses */ -/** Peripheral CMP1 base address */ -#define CMP1_BASE (0x401A4000u) -/** Peripheral CMP1 base pointer */ -#define CMP1 ((CMP_Type *)CMP1_BASE) -/** Peripheral CMP2 base address */ -#define CMP2_BASE (0x401A8000u) -/** Peripheral CMP2 base pointer */ -#define CMP2 ((CMP_Type *)CMP2_BASE) -/** Peripheral CMP3 base address */ -#define CMP3_BASE (0x401AC000u) -/** Peripheral CMP3 base pointer */ -#define CMP3 ((CMP_Type *)CMP3_BASE) -/** Peripheral CMP4 base address */ -#define CMP4_BASE (0x401B0000u) -/** Peripheral CMP4 base pointer */ -#define CMP4 ((CMP_Type *)CMP4_BASE) -/** Array initializer of CMP peripheral base addresses */ -#define CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE } -/** Array initializer of CMP peripheral base pointers */ -#define CMP_BASE_PTRS { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 } -/** Interrupt vectors for the CMP peripheral type */ -#define CMP_IRQS { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn } +#define CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_MASK (0x4U) +#define CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_SHIFT (2U) +/*! CPU0_MODE_REQUEST - Domain0 request enter Low Power Mode + * 0b1..Request from domain to enter Low Power Mode + * 0b0..No request + */ +#define CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_MASK) -/*! - * @} - */ /* end of group CMP_Peripheral_Access_Layer */ +#define CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_MASK (0x8U) +#define CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_SHIFT (3U) +/*! CPU0_MODE_DONE - Domain0 Low Power Mode task done + * 0b1..Clock is gated-off + * 0b0..Clock is not gated + */ +#define CCM_OSCPLL_STATUS1_CPU0_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_MASK) +#define CCM_OSCPLL_STATUS1_CPU1_MODE_MASK (0x30U) +#define CCM_OSCPLL_STATUS1_CPU1_MODE_SHIFT (4U) +/*! CPU1_MODE - Domain1 Low Power Mode + * 0b00..Run + * 0b01..Wait + * 0b10..Stop + * 0b11..Suspend + */ +#define CCM_OSCPLL_STATUS1_CPU1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU1_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU1_MODE_MASK) -/* ---------------------------------------------------------------------------- - -- CSI Peripheral Access Layer - ---------------------------------------------------------------------------- */ +#define CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_MASK (0x40U) +#define CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_SHIFT (6U) +/*! CPU1_MODE_REQUEST - Domain1 request enter Low Power Mode + * 0b1..Request from domain to enter Low Power Mode + * 0b0..No request + */ +#define CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_MASK) -/*! - * @addtogroup CSI_Peripheral_Access_Layer CSI Peripheral Access Layer - * @{ +#define CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_MASK (0x80U) +#define CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_SHIFT (7U) +/*! CPU1_MODE_DONE - Domain1 Low Power Mode task done + * 0b1..Clock is gated-off + * 0b0..Clock is not gated */ +#define CCM_OSCPLL_STATUS1_CPU1_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_MASK) -/** CSI - Register Layout Typedef */ -typedef struct { - __IO uint32_t CSICR1; /**< CSI Control Register 1, offset: 0x0 */ - __IO uint32_t CSICR2; /**< CSI Control Register 2, offset: 0x4 */ - __IO uint32_t CSICR3; /**< CSI Control Register 3, offset: 0x8 */ - __I uint32_t CSISTATFIFO; /**< CSI Statistic FIFO Register, offset: 0xC */ - __I uint32_t CSIRFIFO; /**< CSI RX FIFO Register, offset: 0x10 */ - __IO uint32_t CSIRXCNT; /**< CSI RX Count Register, offset: 0x14 */ - __IO uint32_t CSISR; /**< CSI Status Register, offset: 0x18 */ - uint8_t RESERVED_0[4]; - __IO uint32_t CSIDMASA_STATFIFO; /**< CSI DMA Start Address Register - for STATFIFO, offset: 0x20 */ - __IO uint32_t CSIDMATS_STATFIFO; /**< CSI DMA Transfer Size Register - for STATFIFO, offset: 0x24 */ - __IO uint32_t CSIDMASA_FB1; /**< CSI DMA Start Address Register - for Frame Buffer1, offset: 0x28 */ - __IO uint32_t CSIDMASA_FB2; /**< CSI DMA Transfer Size Register - for Frame Buffer2, offset: 0x2C */ - __IO uint32_t CSIFBUF_PARA; /**< CSI Frame Buffer Parameter Register, offset: 0x30 */ - __IO uint32_t CSIIMAG_PARA; /**< CSI Image Parameter Register, offset: 0x34 */ - uint8_t RESERVED_1[16]; - __IO uint32_t CSICR18; /**< CSI Control Register 18, offset: 0x48 */ - __IO uint32_t CSICR19; /**< CSI Control Register 19, offset: 0x4C */ - __IO uint32_t CSICR20; /**< CSI Control Register 20, offset: 0x50 */ - __IO uint32_t CSICR[256]; /**< CSI Control Register n, array offset: 0x54, array step: 0x4 */ -} CSI_Type; +#define CCM_OSCPLL_STATUS1_CPU2_MODE_MASK (0x300U) +#define CCM_OSCPLL_STATUS1_CPU2_MODE_SHIFT (8U) +/*! CPU2_MODE - Domain2 Low Power Mode + * 0b00..Run + * 0b01..Wait + * 0b10..Stop + * 0b11..Suspend + */ +#define CCM_OSCPLL_STATUS1_CPU2_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU2_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU2_MODE_MASK) -/* ---------------------------------------------------------------------------- - -- CSI Register Masks - ---------------------------------------------------------------------------- */ +#define CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_MASK (0x400U) +#define CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_SHIFT (10U) +/*! CPU2_MODE_REQUEST - Domain2 request enter Low Power Mode + * 0b1..Request from domain to enter Low Power Mode + * 0b0..No request + */ +#define CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_MASK) -/*! - * @addtogroup CSI_Register_Masks CSI Register Masks - * @{ +#define CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_MASK (0x800U) +#define CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_SHIFT (11U) +/*! CPU2_MODE_DONE - Domain2 Low Power Mode task done + * 0b1..Clock is gated-off + * 0b0..Clock is not gated */ +#define CCM_OSCPLL_STATUS1_CPU2_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_MASK) -/*! @name CSICR1 - CSI Control Register 1 */ -/*! @{ */ -#define CSI_CSICR1_PIXEL_BIT_MASK (0x1U) -#define CSI_CSICR1_PIXEL_BIT_SHIFT (0U) -/*! PIXEL_BIT - * 0b0..8-bit data for each pixel - * 0b1..10-bit data for each pixel +#define CCM_OSCPLL_STATUS1_CPU3_MODE_MASK (0x3000U) +#define CCM_OSCPLL_STATUS1_CPU3_MODE_SHIFT (12U) +/*! CPU3_MODE - Domain3 Low Power Mode + * 0b00..Run + * 0b01..Wait + * 0b10..Stop + * 0b11..Suspend */ -#define CSI_CSICR1_PIXEL_BIT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PIXEL_BIT_SHIFT)) & CSI_CSICR1_PIXEL_BIT_MASK) -#define CSI_CSICR1_REDGE_MASK (0x2U) -#define CSI_CSICR1_REDGE_SHIFT (1U) -/*! REDGE - * 0b0..Pixel data is latched at the falling edge of CSI_PIXCLK - * 0b1..Pixel data is latched at the rising edge of CSI_PIXCLK +#define CCM_OSCPLL_STATUS1_CPU3_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU3_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU3_MODE_MASK) + +#define CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_MASK (0x4000U) +#define CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_SHIFT (14U) +/*! CPU3_MODE_REQUEST - Domain3 request enter Low Power Mode + * 0b1..Request from domain to enter Low Power Mode + * 0b0..No request */ -#define CSI_CSICR1_REDGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_REDGE_SHIFT)) & CSI_CSICR1_REDGE_MASK) -#define CSI_CSICR1_INV_PCLK_MASK (0x4U) -#define CSI_CSICR1_INV_PCLK_SHIFT (2U) -/*! INV_PCLK - * 0b0..CSI_PIXCLK is directly applied to internal circuitry - * 0b1..CSI_PIXCLK is inverted before applied to internal circuitry +#define CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_MASK) + +#define CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_MASK (0x8000U) +#define CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_SHIFT (15U) +/*! CPU3_MODE_DONE - Domain3 Low Power Mode task done + * 0b1..Clock is gated-off + * 0b0..Clock is not gated */ -#define CSI_CSICR1_INV_PCLK(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_PCLK_SHIFT)) & CSI_CSICR1_INV_PCLK_MASK) -#define CSI_CSICR1_INV_DATA_MASK (0x8U) -#define CSI_CSICR1_INV_DATA_SHIFT (3U) -/*! INV_DATA - * 0b0..CSI_D[7:0] data lines are directly applied to internal circuitry - * 0b1..CSI_D[7:0] data lines are inverted before applied to internal circuitry +#define CCM_OSCPLL_STATUS1_CPU3_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_MASK) + +#define CCM_OSCPLL_STATUS1_TARGET_SETPOINT_MASK (0xF0000U) +#define CCM_OSCPLL_STATUS1_TARGET_SETPOINT_SHIFT (16U) +/*! TARGET_SETPOINT - Next Setpoint to change to */ -#define CSI_CSICR1_INV_DATA(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_DATA_SHIFT)) & CSI_CSICR1_INV_DATA_MASK) -#define CSI_CSICR1_GCLK_MODE_MASK (0x10U) -#define CSI_CSICR1_GCLK_MODE_SHIFT (4U) -/*! GCLK_MODE - * 0b0..Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored. - * 0b1..Gated clock mode. Pixel clock signal is valid only when HSYNC is active. +#define CCM_OSCPLL_STATUS1_TARGET_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_TARGET_SETPOINT_SHIFT)) & CCM_OSCPLL_STATUS1_TARGET_SETPOINT_MASK) + +#define CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_MASK (0xF00000U) +#define CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_SHIFT (20U) +/*! CURRENT_SETPOINT - Current Setpoint */ -#define CSI_CSICR1_GCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_GCLK_MODE_SHIFT)) & CSI_CSICR1_GCLK_MODE_MASK) -#define CSI_CSICR1_CLR_RXFIFO_MASK (0x20U) -#define CSI_CSICR1_CLR_RXFIFO_SHIFT (5U) -#define CSI_CSICR1_CLR_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_RXFIFO_SHIFT)) & CSI_CSICR1_CLR_RXFIFO_MASK) -#define CSI_CSICR1_CLR_STATFIFO_MASK (0x40U) -#define CSI_CSICR1_CLR_STATFIFO_SHIFT (6U) -#define CSI_CSICR1_CLR_STATFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_STATFIFO_SHIFT)) & CSI_CSICR1_CLR_STATFIFO_MASK) -#define CSI_CSICR1_PACK_DIR_MASK (0x80U) -#define CSI_CSICR1_PACK_DIR_SHIFT (7U) -/*! PACK_DIR - * 0b0..Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. For - * stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO. - * 0b1..Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. For - * stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO. +#define CCM_OSCPLL_STATUS1_CURRENT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_SHIFT)) & CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_MASK) + +#define CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_MASK (0x1000000U) +#define CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_SHIFT (24U) +/*! SETPOINT_OFF_REQUEST - Clock gate turn off request from GPC Setpoint + * 0b1..Clock gate requested to be turned off + * 0b0..No request */ -#define CSI_CSICR1_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PACK_DIR_SHIFT)) & CSI_CSICR1_PACK_DIR_MASK) -#define CSI_CSICR1_FCC_MASK (0x100U) -#define CSI_CSICR1_FCC_SHIFT (8U) -/*! FCC - * 0b0..Asynchronous FIFO clear is selected. - * 0b1..Synchronous FIFO clear is selected. +#define CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_MASK) + +#define CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_MASK (0x2000000U) +#define CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_SHIFT (25U) +/*! SETPOINT_OFF_DONE - Clock source turn off finish from GPC Setpoint + * 0b1..Clock source is turned off + * 0b0..Clock source is not turned off */ -#define CSI_CSICR1_FCC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FCC_SHIFT)) & CSI_CSICR1_FCC_MASK) -#define CSI_CSICR1_CCIR_EN_MASK (0x400U) -#define CSI_CSICR1_CCIR_EN_SHIFT (10U) -/*! CCIR_EN - * 0b0..Traditional interface is selected. Timing interface logic is used to latch data. - * 0b1..CCIR656 interface is selected. +#define CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_MASK) + +#define CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_MASK (0x4000000U) +#define CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_SHIFT (26U) +/*! SETPOINT_ON_REQUEST - Clock gate turn on request from GPC Setpoint + * 0b1..Clock gate requested to be turned on + * 0b0..No request */ -#define CSI_CSICR1_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_EN_SHIFT)) & CSI_CSICR1_CCIR_EN_MASK) -#define CSI_CSICR1_HSYNC_POL_MASK (0x800U) -#define CSI_CSICR1_HSYNC_POL_SHIFT (11U) -/*! HSYNC_POL - * 0b0..HSYNC is active low - * 0b1..HSYNC is active high +#define CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_MASK) + +#define CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_MASK (0x8000000U) +#define CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_SHIFT (27U) +/*! SETPOINT_ON_DONE - Clock gate turn on finish from GPC Setpoint + * 0b1..Request to turn on clock gate + * 0b0..No request */ -#define CSI_CSICR1_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_HSYNC_POL_SHIFT)) & CSI_CSICR1_HSYNC_POL_MASK) -#define CSI_CSICR1_HISTOGRAM_CALC_DONE_IE_MASK (0x1000U) -#define CSI_CSICR1_HISTOGRAM_CALC_DONE_IE_SHIFT (12U) -/*! HISTOGRAM_CALC_DONE_IE - * 0b0..Histogram done interrupt disable - * 0b1..Histogram done interrupt enable +#define CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_MASK) + +#define CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_MASK (0x10000000U) +#define CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_SHIFT (28U) +/*! STANDBY_IN_REQUEST - Clock gate turn off request from GPC standby + * 0b1..Clock gate requested to be turned off + * 0b0..No request */ -#define CSI_CSICR1_HISTOGRAM_CALC_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_HISTOGRAM_CALC_DONE_IE_SHIFT)) & CSI_CSICR1_HISTOGRAM_CALC_DONE_IE_MASK) -#define CSI_CSICR1_SOF_INTEN_MASK (0x10000U) -#define CSI_CSICR1_SOF_INTEN_SHIFT (16U) -/*! SOF_INTEN - * 0b0..SOF interrupt disable - * 0b1..SOF interrupt enable +#define CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_MASK) + +#define CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_MASK (0x20000000U) +#define CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_SHIFT (29U) +/*! STANDBY_IN_DONE - Clock source turn off finish from GPC standby + * 0b1..Clock source is turned off + * 0b0..Clock source is not turned off */ -#define CSI_CSICR1_SOF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_INTEN_SHIFT)) & CSI_CSICR1_SOF_INTEN_MASK) -#define CSI_CSICR1_SOF_POL_MASK (0x20000U) -#define CSI_CSICR1_SOF_POL_SHIFT (17U) -/*! SOF_POL - * 0b0..SOF interrupt is generated on SOF falling edge - * 0b1..SOF interrupt is generated on SOF rising edge +#define CCM_OSCPLL_STATUS1_STANDBY_IN_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_MASK) + +#define CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_MASK (0x40000000U) +#define CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_SHIFT (30U) +/*! STANDBY_OUT_DONE - Clock gate turn on finish from GPC standby + * 0b1..Request to turn on Clock gate is complete + * 0b0..Request to turn on Clock gate is not complete */ -#define CSI_CSICR1_SOF_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_POL_SHIFT)) & CSI_CSICR1_SOF_POL_MASK) -#define CSI_CSICR1_RXFF_INTEN_MASK (0x40000U) -#define CSI_CSICR1_RXFF_INTEN_SHIFT (18U) -/*! RXFF_INTEN - * 0b0..RxFIFO full interrupt disable - * 0b1..RxFIFO full interrupt enable +#define CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_MASK) + +#define CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_MASK (0x80000000U) +#define CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_SHIFT (31U) +/*! STANDBY_OUT_REQUEST - Clock gate turn on request from GPC standby + * 0b1..Clock gate requested to be turned on + * 0b0..No request */ -#define CSI_CSICR1_RXFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RXFF_INTEN_SHIFT)) & CSI_CSICR1_RXFF_INTEN_MASK) -#define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK (0x80000U) -#define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT (19U) -/*! FB1_DMA_DONE_INTEN - * 0b0..Frame Buffer1 DMA Transfer Done interrupt disable - * 0b1..Frame Buffer1 DMA Transfer Done interrupt enable +#define CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_MASK) +/*! @} */ + +/* The count of CCM_OSCPLL_STATUS1 */ +#define CCM_OSCPLL_STATUS1_COUNT (29U) + +/*! @name OSCPLL_CONFIG - Clock source configuration */ +/*! @{ */ + +#define CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_MASK (0x2U) +#define CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_SHIFT (1U) +/*! AUTOMODE_PRESENT - Automode Present + * 0b1..Present + * 0b0..Not present */ -#define CSI_CSICR1_FB1_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK) -#define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK (0x100000U) -#define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT (20U) -/*! FB2_DMA_DONE_INTEN - * 0b0..Frame Buffer2 DMA Transfer Done interrupt disable - * 0b1..Frame Buffer2 DMA Transfer Done interrupt enable +#define CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_SHIFT)) & CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_MASK) + +#define CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_MASK (0x10U) +#define CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_SHIFT (4U) +/*! SETPOINT_PRESENT - Setpoint present + * 0b1..Setpoint is implemented. + * 0b0..Setpoint is not implemented. */ -#define CSI_CSICR1_FB2_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK) -#define CSI_CSICR1_STATFF_INTEN_MASK (0x200000U) -#define CSI_CSICR1_STATFF_INTEN_SHIFT (21U) -/*! STATFF_INTEN - * 0b0..STATFIFO full interrupt disable - * 0b1..STATFIFO full interrupt enable +#define CCM_OSCPLL_CONFIG_SETPOINT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_SHIFT)) & CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_MASK) +/*! @} */ + +/* The count of CCM_OSCPLL_CONFIG */ +#define CCM_OSCPLL_CONFIG_COUNT (29U) + +/*! @name OSCPLL_AUTHEN - Clock source access control */ +/*! @{ */ + +#define CCM_OSCPLL_AUTHEN_TZ_USER_MASK (0x1U) +#define CCM_OSCPLL_AUTHEN_TZ_USER_SHIFT (0U) +/*! TZ_USER - User access + * 0b1..Clock can be changed in user mode. + * 0b0..Clock cannot be changed in user mode. */ -#define CSI_CSICR1_STATFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_STATFF_INTEN_SHIFT)) & CSI_CSICR1_STATFF_INTEN_MASK) -#define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK (0x400000U) -#define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT (22U) -/*! SFF_DMA_DONE_INTEN - * 0b0..STATFIFO DMA Transfer Done interrupt disable - * 0b1..STATFIFO DMA Transfer Done interrupt enable +#define CCM_OSCPLL_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_TZ_USER_SHIFT)) & CCM_OSCPLL_AUTHEN_TZ_USER_MASK) + +#define CCM_OSCPLL_AUTHEN_TZ_NS_MASK (0x2U) +#define CCM_OSCPLL_AUTHEN_TZ_NS_SHIFT (1U) +/*! TZ_NS - Non-secure access + * 0b0..Cannot be changed in Non-secure mode. + * 0b1..Can be changed in Non-secure mode. */ -#define CSI_CSICR1_SFF_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK) -#define CSI_CSICR1_RF_OR_INTEN_MASK (0x1000000U) -#define CSI_CSICR1_RF_OR_INTEN_SHIFT (24U) -/*! RF_OR_INTEN - * 0b0..RxFIFO overrun interrupt is disabled - * 0b1..RxFIFO overrun interrupt is enabled +#define CCM_OSCPLL_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_TZ_NS_SHIFT)) & CCM_OSCPLL_AUTHEN_TZ_NS_MASK) + +#define CCM_OSCPLL_AUTHEN_LOCK_TZ_MASK (0x10U) +#define CCM_OSCPLL_AUTHEN_LOCK_TZ_SHIFT (4U) +/*! LOCK_TZ - lock truszone setting + * 0b0..Trustzone setting is not locked. + * 0b1..Trustzone setting is locked. */ -#define CSI_CSICR1_RF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RF_OR_INTEN_SHIFT)) & CSI_CSICR1_RF_OR_INTEN_MASK) -#define CSI_CSICR1_SF_OR_INTEN_MASK (0x2000000U) -#define CSI_CSICR1_SF_OR_INTEN_SHIFT (25U) -/*! SF_OR_INTEN - * 0b0..STATFIFO overrun interrupt is disabled - * 0b1..STATFIFO overrun interrupt is enabled +#define CCM_OSCPLL_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_TZ_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_TZ_MASK) + +#define CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK (0xF00U) +#define CCM_OSCPLL_AUTHEN_WHITE_LIST_SHIFT (8U) +/*! WHITE_LIST - Whitelist */ -#define CSI_CSICR1_SF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SF_OR_INTEN_SHIFT)) & CSI_CSICR1_SF_OR_INTEN_MASK) -#define CSI_CSICR1_COF_INT_EN_MASK (0x4000000U) -#define CSI_CSICR1_COF_INT_EN_SHIFT (26U) -/*! COF_INT_EN - * 0b0..COF interrupt is disabled - * 0b1..COF interrupt is enabled +#define CCM_OSCPLL_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_WHITE_LIST_SHIFT)) & CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK) + +#define CCM_OSCPLL_AUTHEN_LOCK_LIST_MASK (0x1000U) +#define CCM_OSCPLL_AUTHEN_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock Whitelist + * 0b0..Whitelist is not locked. + * 0b1..Whitelist is locked. */ -#define CSI_CSICR1_COF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_COF_INT_EN_SHIFT)) & CSI_CSICR1_COF_INT_EN_MASK) -#define CSI_CSICR1_CCIR_MODE_MASK (0x8000000U) -#define CSI_CSICR1_CCIR_MODE_SHIFT (27U) -/*! CCIR_MODE - * 0b0..Progressive mode is selected - * 0b1..Interlace mode is selected +#define CCM_OSCPLL_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_LIST_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_LIST_MASK) + +#define CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK (0x10000U) +#define CCM_OSCPLL_AUTHEN_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by domain + * 0b1..Clock works in Domain Mode. + * 0b0..Clock does not work in Domain Mode. */ -#define CSI_CSICR1_CCIR_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_MODE_SHIFT)) & CSI_CSICR1_CCIR_MODE_MASK) -#define CSI_CSICR1_PrP_IF_EN_MASK (0x10000000U) -#define CSI_CSICR1_PrP_IF_EN_SHIFT (28U) -/*! PrP_IF_EN - * 0b0..CSI to PrP bus is disabled - * 0b1..CSI to PrP bus is enabled +#define CCM_OSCPLL_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK) + +#define CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK (0x20000U) +#define CCM_OSCPLL_AUTHEN_SETPOINT_MODE_SHIFT (17U) +/*! SETPOINT_MODE - LPCG works in Setpoint controlled Mode. */ -#define CSI_CSICR1_PrP_IF_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PrP_IF_EN_SHIFT)) & CSI_CSICR1_PrP_IF_EN_MASK) -#define CSI_CSICR1_EOF_INT_EN_MASK (0x20000000U) -#define CSI_CSICR1_EOF_INT_EN_SHIFT (29U) -/*! EOF_INT_EN - * 0b0..EOF interrupt is disabled. - * 0b1..EOF interrupt is generated when RX count value is reached. +#define CCM_OSCPLL_AUTHEN_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_SETPOINT_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK) + +#define CCM_OSCPLL_AUTHEN_CPULPM_MASK (0x40000U) +#define CCM_OSCPLL_AUTHEN_CPULPM_SHIFT (18U) +/*! CPULPM - CPU Low Power Mode + * 0b1..PLL functions in Low Power Mode + * 0b0..PLL does not function in Low power Mode */ -#define CSI_CSICR1_EOF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EOF_INT_EN_SHIFT)) & CSI_CSICR1_EOF_INT_EN_MASK) -#define CSI_CSICR1_EXT_VSYNC_MASK (0x40000000U) -#define CSI_CSICR1_EXT_VSYNC_SHIFT (30U) -/*! EXT_VSYNC - * 0b0..Internal VSYNC mode - * 0b1..External VSYNC mode +#define CCM_OSCPLL_AUTHEN_CPULPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_CPULPM_SHIFT)) & CCM_OSCPLL_AUTHEN_CPULPM_MASK) + +#define CCM_OSCPLL_AUTHEN_LOCK_MODE_MASK (0x100000U) +#define CCM_OSCPLL_AUTHEN_LOCK_MODE_SHIFT (20U) +/*! LOCK_MODE - Lock low power and access mode + * 0b0..MODE is not locked. + * 0b1..MODE is locked. */ -#define CSI_CSICR1_EXT_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EXT_VSYNC_SHIFT)) & CSI_CSICR1_EXT_VSYNC_MASK) -#define CSI_CSICR1_SWAP16_EN_MASK (0x80000000U) -#define CSI_CSICR1_SWAP16_EN_SHIFT (31U) -/*! SWAP16_EN - * 0b0..Disable swapping - * 0b1..Enable swapping +#define CCM_OSCPLL_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_MODE_MASK) +/*! @} */ + +/* The count of CCM_OSCPLL_AUTHEN */ +#define CCM_OSCPLL_AUTHEN_COUNT (29U) + +/*! @name LPCG_DIRECT - LPCG direct control */ +/*! @{ */ + +#define CCM_LPCG_DIRECT_ON_MASK (0x1U) +#define CCM_LPCG_DIRECT_ON_SHIFT (0U) +/*! ON - LPCG on + * 0b0..LPCG is OFF. + * 0b1..LPCG is ON. */ -#define CSI_CSICR1_SWAP16_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SWAP16_EN_SHIFT)) & CSI_CSICR1_SWAP16_EN_MASK) +#define CCM_LPCG_DIRECT_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DIRECT_ON_SHIFT)) & CCM_LPCG_DIRECT_ON_MASK) /*! @} */ -/*! @name CSICR2 - CSI Control Register 2 */ +/* The count of CCM_LPCG_DIRECT */ +#define CCM_LPCG_DIRECT_COUNT (138U) + +/*! @name LPCG_DOMAIN - LPCG domain control */ /*! @{ */ -#define CSI_CSICR2_HSC_MASK (0xFFU) -#define CSI_CSICR2_HSC_SHIFT (0U) -#define CSI_CSICR2_HSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_HSC_SHIFT)) & CSI_CSICR2_HSC_MASK) -#define CSI_CSICR2_VSC_MASK (0xFF00U) -#define CSI_CSICR2_VSC_SHIFT (8U) -#define CSI_CSICR2_VSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_VSC_SHIFT)) & CSI_CSICR2_VSC_MASK) -#define CSI_CSICR2_LVRM_MASK (0x70000U) -#define CSI_CSICR2_LVRM_SHIFT (16U) -/*! LVRM - * 0b000..512 x 384 - * 0b001..448 x 336 - * 0b010..384 x 288 - * 0b011..384 x 256 - * 0b100..320 x 240 - * 0b101..288 x 216 - * 0b110..400 x 300 + +#define CCM_LPCG_DOMAIN_LEVEL_MASK (0x7U) +#define CCM_LPCG_DOMAIN_LEVEL_SHIFT (0U) +/*! LEVEL - Current dependence level + * 0b000..This clock source is not needed in any mode, and can be turned off + * 0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode + * 0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode + * 0b011..This clock source is needed in RUN, WAIT and STOP mode + * 0b100..This clock source is always on in any mode (including SUSPEND) + * 0b101, 0b110, 0b111..Reserved */ -#define CSI_CSICR2_LVRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_LVRM_SHIFT)) & CSI_CSICR2_LVRM_MASK) -#define CSI_CSICR2_BTS_MASK (0x180000U) -#define CSI_CSICR2_BTS_SHIFT (19U) -/*! BTS - * 0b00..GR - * 0b01..RG - * 0b10..BG - * 0b11..GB +#define CCM_LPCG_DOMAIN_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL_MASK) + +#define CCM_LPCG_DOMAIN_LEVEL0_MASK (0x70000U) +#define CCM_LPCG_DOMAIN_LEVEL0_SHIFT (16U) +/*! LEVEL0 - Depend level + * 0b000..This clock source is not needed in any mode, and can be turned off + * 0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode + * 0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode + * 0b011..This clock source is needed in RUN, WAIT and STOP mode + * 0b100..This clock source is always on in any mode (including SUSPEND) + * 0b101, 0b110, 0b111..Reserved */ -#define CSI_CSICR2_BTS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_BTS_SHIFT)) & CSI_CSICR2_BTS_MASK) -#define CSI_CSICR2_SCE_MASK (0x800000U) -#define CSI_CSICR2_SCE_SHIFT (23U) -/*! SCE - * 0b0..Skip count disable - * 0b1..Skip count enable +#define CCM_LPCG_DOMAIN_LEVEL0(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL0_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL0_MASK) + +#define CCM_LPCG_DOMAIN_LEVEL1_MASK (0x700000U) +#define CCM_LPCG_DOMAIN_LEVEL1_SHIFT (20U) +/*! LEVEL1 - Depend level + * 0b000..This clock source is not needed in any mode, and can be turned off + * 0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode + * 0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode + * 0b011..This clock source is needed in RUN, WAIT and STOP mode + * 0b100..This clock source is always on in any mode (including SUSPEND) + * 0b101, 0b110, 0b111..Reserved */ -#define CSI_CSICR2_SCE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_SCE_SHIFT)) & CSI_CSICR2_SCE_MASK) -#define CSI_CSICR2_AFS_MASK (0x3000000U) -#define CSI_CSICR2_AFS_SHIFT (24U) -/*! AFS - * 0b00..Abs Diff on consecutive green pixels - * 0b01..Abs Diff on every third green pixels - * 0b1x..Abs Diff on every four green pixels +#define CCM_LPCG_DOMAIN_LEVEL1(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL1_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL1_MASK) + +#define CCM_LPCG_DOMAIN_LEVEL2_MASK (0x7000000U) +#define CCM_LPCG_DOMAIN_LEVEL2_SHIFT (24U) +/*! LEVEL2 - Depend level + * 0b000..This clock source is not needed in any mode, and can be turned off + * 0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode + * 0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode + * 0b011..This clock source is needed in RUN, WAIT and STOP mode + * 0b100..This clock source is always on in any mode (including SUSPEND) + * 0b101, 0b110, 0b111..Reserved */ -#define CSI_CSICR2_AFS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_AFS_SHIFT)) & CSI_CSICR2_AFS_MASK) -#define CSI_CSICR2_DRM_MASK (0x4000000U) -#define CSI_CSICR2_DRM_SHIFT (26U) -/*! DRM - * 0b0..Stats grid of 8 x 6 - * 0b1..Stats grid of 8 x 12 +#define CCM_LPCG_DOMAIN_LEVEL2(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL2_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL2_MASK) + +#define CCM_LPCG_DOMAIN_LEVEL3_MASK (0x70000000U) +#define CCM_LPCG_DOMAIN_LEVEL3_SHIFT (28U) +/*! LEVEL3 - Depend level + * 0b000..This clock source is not needed in any mode, and can be turned off + * 0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode + * 0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode + * 0b011..This clock source is needed in RUN, WAIT and STOP mode + * 0b100..This clock source is always on in any mode (including SUSPEND) + * 0b101, 0b110, 0b111..Reserved */ -#define CSI_CSICR2_DRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DRM_SHIFT)) & CSI_CSICR2_DRM_MASK) -#define CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK (0x30000000U) -#define CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT (28U) -/*! DMA_BURST_TYPE_SFF - * 0bx0..INCR8 - * 0b01..INCR4 - * 0b11..INCR16 +#define CCM_LPCG_DOMAIN_LEVEL3(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL3_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL3_MASK) +/*! @} */ + +/* The count of CCM_LPCG_DOMAIN */ +#define CCM_LPCG_DOMAIN_COUNT (138U) + +/*! @name LPCG_SETPOINT - LPCG Setpoint setting */ +/*! @{ */ + +#define CCM_LPCG_SETPOINT_SETPOINT_MASK (0xFFFFU) +#define CCM_LPCG_SETPOINT_SETPOINT_SHIFT (0U) +/*! SETPOINT - Setpoints */ -#define CSI_CSICR2_DMA_BURST_TYPE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK) -#define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U) -#define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT (30U) -/*! DMA_BURST_TYPE_RFF - * 0bx0..INCR8 - * 0b01..INCR4 - * 0b11..INCR16 +#define CCM_LPCG_SETPOINT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_SETPOINT_SETPOINT_SHIFT)) & CCM_LPCG_SETPOINT_SETPOINT_MASK) + +#define CCM_LPCG_SETPOINT_STANDBY_MASK (0xFFFF0000U) +#define CCM_LPCG_SETPOINT_STANDBY_SHIFT (16U) +/*! STANDBY - Standby */ -#define CSI_CSICR2_DMA_BURST_TYPE_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK) +#define CCM_LPCG_SETPOINT_STANDBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_SETPOINT_STANDBY_SHIFT)) & CCM_LPCG_SETPOINT_STANDBY_MASK) /*! @} */ -/*! @name CSICR3 - CSI Control Register 3 */ +/* The count of CCM_LPCG_SETPOINT */ +#define CCM_LPCG_SETPOINT_COUNT (138U) + +/*! @name LPCG_STATUS0 - LPCG working status */ /*! @{ */ -#define CSI_CSICR3_ECC_AUTO_EN_MASK (0x1U) -#define CSI_CSICR3_ECC_AUTO_EN_SHIFT (0U) -/*! ECC_AUTO_EN - * 0b0..Auto Error correction is disabled. - * 0b1..Auto Error correction is enabled. - */ -#define CSI_CSICR3_ECC_AUTO_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_AUTO_EN_SHIFT)) & CSI_CSICR3_ECC_AUTO_EN_MASK) -#define CSI_CSICR3_ECC_INT_EN_MASK (0x2U) -#define CSI_CSICR3_ECC_INT_EN_SHIFT (1U) -/*! ECC_INT_EN - * 0b0..No interrupt is generated when error is detected. Only the status bit ECC_INT is set. - * 0b1..Interrupt is generated when error is detected. + +#define CCM_LPCG_STATUS0_ON_MASK (0x1U) +#define CCM_LPCG_STATUS0_ON_SHIFT (0U) +/*! ON - LPCG current state + * 0b0..LPCG is OFF. + * 0b1..LPCG is ON. */ -#define CSI_CSICR3_ECC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_INT_EN_SHIFT)) & CSI_CSICR3_ECC_INT_EN_MASK) -#define CSI_CSICR3_ZERO_PACK_EN_MASK (0x4U) -#define CSI_CSICR3_ZERO_PACK_EN_SHIFT (2U) -/*! ZERO_PACK_EN - * 0b0..Zero packing disabled - * 0b1..Zero packing enabled +#define CCM_LPCG_STATUS0_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS0_ON_SHIFT)) & CCM_LPCG_STATUS0_ON_MASK) + +#define CCM_LPCG_STATUS0_ACTIVE_DOMAIN_MASK (0xF00U) +#define CCM_LPCG_STATUS0_ACTIVE_DOMAIN_SHIFT (8U) +/*! ACTIVE_DOMAIN - Domains that own this clock gate + * 0b0000..Clock not owned by any domain + * 0b0001..Clock owned by Domain0 + * 0b0010..Clock owned by Domain1 + * 0b0011..Clock owned by Domain0 and Domain1 + * 0b0100..Clock owned by Domain2 + * 0b0101..Clock owned by Domain0 and Domain2 + * 0b0110..Clock owned by Domain1 and Domain2 + * 0b0111..Clock owned by Domain0, Domain1 and Domain 2 + * 0b1000..Clock owned by Domain3 + * 0b1001..Clock owned by Domain0 and Domain3 + * 0b1010..Clock owned by Domain1 and Domain3 + * 0b1011..Clock owned by Domain2 and Domain3 + * 0b1100..Clock owned by Domain0, Domain 1, and Domain3 + * 0b1101..Clock owned by Domain0, Domain 2, and Domain3 + * 0b1110..Clock owned by Domain1, Domain 2, and Domain3 + * 0b1111..Clock owned by all domains */ -#define CSI_CSICR3_ZERO_PACK_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ZERO_PACK_EN_SHIFT)) & CSI_CSICR3_ZERO_PACK_EN_MASK) -#define CSI_CSICR3_TWO_8BIT_SENSOR_MASK (0x8U) -#define CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT (3U) -/*! TWO_8BIT_SENSOR - * 0b0..Only one 8-bit sensor is connected. - * 0b1..One 16-bit sensor is connected. +#define CCM_LPCG_STATUS0_ACTIVE_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS0_ACTIVE_DOMAIN_SHIFT)) & CCM_LPCG_STATUS0_ACTIVE_DOMAIN_MASK) + +#define CCM_LPCG_STATUS0_DOMAIN_ENABLE_MASK (0xF000U) +#define CCM_LPCG_STATUS0_DOMAIN_ENABLE_SHIFT (12U) +/*! DOMAIN_ENABLE - Enable status from each domain + * 0b0000..No domain request + * 0b0001..Request from Domain0 + * 0b0010..Request from Domain1 + * 0b0011..Request from Domain0 and Domain1 + * 0b0100..Request from Domain2 + * 0b0101..Request from Domain0 and Domain2 + * 0b0110..Request from Domain1 and Domain2 + * 0b0111..Request from Domain0, Domain1 and Domain 2 + * 0b1000..Request from Domain3 + * 0b1001..Request from Domain0 and Domain3 + * 0b1010..Request from Domain1 and Domain3 + * 0b1011..Request from Domain2 and Domain3 + * 0b1100..Request from Domain0, Domain 1, and Domain3 + * 0b1101..Request from Domain0, Domain 2, and Domain3 + * 0b1110..Request from Domain1, Domain 2, and Domain3 + * 0b1111..Request from all domains */ -#define CSI_CSICR3_TWO_8BIT_SENSOR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT)) & CSI_CSICR3_TWO_8BIT_SENSOR_MASK) -#define CSI_CSICR3_RxFF_LEVEL_MASK (0x70U) -#define CSI_CSICR3_RxFF_LEVEL_SHIFT (4U) -/*! RxFF_LEVEL - * 0b000..4 Double words - * 0b001..8 Double words - * 0b010..16 Double words - * 0b011..24 Double words - * 0b100..32 Double words - * 0b101..48 Double words - * 0b110..64 Double words - * 0b111..96 Double words +#define CCM_LPCG_STATUS0_DOMAIN_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS0_DOMAIN_ENABLE_SHIFT)) & CCM_LPCG_STATUS0_DOMAIN_ENABLE_MASK) +/*! @} */ + +/* The count of CCM_LPCG_STATUS0 */ +#define CCM_LPCG_STATUS0_COUNT (138U) + +/*! @name LPCG_STATUS1 - LPCG low power status */ +/*! @{ */ + +#define CCM_LPCG_STATUS1_CPU0_MODE_MASK (0x3U) +#define CCM_LPCG_STATUS1_CPU0_MODE_SHIFT (0U) +/*! CPU0_MODE - Domain0 Low Power Mode + * 0b00..Run + * 0b01..Wait + * 0b10..Stop + * 0b11..Suspend */ -#define CSI_CSICR3_RxFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_RxFF_LEVEL_SHIFT)) & CSI_CSICR3_RxFF_LEVEL_MASK) -#define CSI_CSICR3_HRESP_ERR_EN_MASK (0x80U) -#define CSI_CSICR3_HRESP_ERR_EN_SHIFT (7U) -/*! HRESP_ERR_EN - * 0b0..Disable hresponse error interrupt - * 0b1..Enable hresponse error interrupt +#define CCM_LPCG_STATUS1_CPU0_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_MASK) + +#define CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_MASK (0x4U) +#define CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_SHIFT (2U) +/*! CPU0_MODE_REQUEST - Domain0 request enter Low Power Mode + * 0b1..Request from domain to enter Low Power Mode + * 0b0..No request */ -#define CSI_CSICR3_HRESP_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_HRESP_ERR_EN_SHIFT)) & CSI_CSICR3_HRESP_ERR_EN_MASK) -#define CSI_CSICR3_STATFF_LEVEL_MASK (0x700U) -#define CSI_CSICR3_STATFF_LEVEL_SHIFT (8U) -/*! STATFF_LEVEL - * 0b000..4 Double words - * 0b001..8 Double words - * 0b010..12 Double words - * 0b011..16 Double words - * 0b100..24 Double words - * 0b101..32 Double words - * 0b110..48 Double words - * 0b111..64 Double words +#define CCM_LPCG_STATUS1_CPU0_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_MASK) + +#define CCM_LPCG_STATUS1_CPU0_MODE_DONE_MASK (0x8U) +#define CCM_LPCG_STATUS1_CPU0_MODE_DONE_SHIFT (3U) +/*! CPU0_MODE_DONE - Domain0 Low Power Mode task done + * 0b1..Clock is gated-off + * 0b0..Clock is not gated */ -#define CSI_CSICR3_STATFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_STATFF_LEVEL_SHIFT)) & CSI_CSICR3_STATFF_LEVEL_MASK) -#define CSI_CSICR3_DMA_REQ_EN_SFF_MASK (0x800U) -#define CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT (11U) -/*! DMA_REQ_EN_SFF - * 0b0..Disable the dma request - * 0b1..Enable the dma request +#define CCM_LPCG_STATUS1_CPU0_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_DONE_MASK) + +#define CCM_LPCG_STATUS1_CPU1_MODE_MASK (0x30U) +#define CCM_LPCG_STATUS1_CPU1_MODE_SHIFT (4U) +/*! CPU1_MODE - Domain1 Low Power Mode + * 0b00..Run + * 0b01..Wait + * 0b10..Stop + * 0b11..Suspend */ -#define CSI_CSICR3_DMA_REQ_EN_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_SFF_MASK) -#define CSI_CSICR3_DMA_REQ_EN_RFF_MASK (0x1000U) -#define CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT (12U) -/*! DMA_REQ_EN_RFF - * 0b0..Disable the dma request - * 0b1..Enable the dma request +#define CCM_LPCG_STATUS1_CPU1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU1_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU1_MODE_MASK) + +#define CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_MASK (0x40U) +#define CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_SHIFT (6U) +/*! CPU1_MODE_REQUEST - Domain1 request enter Low Power Mode + * 0b1..Request from domain to enter Low Power Mode + * 0b0..No request */ -#define CSI_CSICR3_DMA_REQ_EN_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_RFF_MASK) -#define CSI_CSICR3_DMA_REFLASH_SFF_MASK (0x2000U) -#define CSI_CSICR3_DMA_REFLASH_SFF_SHIFT (13U) -/*! DMA_REFLASH_SFF - * 0b0..No reflashing - * 0b1..Reflash the embedded DMA controller +#define CCM_LPCG_STATUS1_CPU1_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_MASK) + +#define CCM_LPCG_STATUS1_CPU1_MODE_DONE_MASK (0x80U) +#define CCM_LPCG_STATUS1_CPU1_MODE_DONE_SHIFT (7U) +/*! CPU1_MODE_DONE - Domain1 Low Power Mode task done + * 0b1..Clock is gated-off + * 0b0..Clock is not gated */ -#define CSI_CSICR3_DMA_REFLASH_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_SFF_MASK) -#define CSI_CSICR3_DMA_REFLASH_RFF_MASK (0x4000U) -#define CSI_CSICR3_DMA_REFLASH_RFF_SHIFT (14U) -/*! DMA_REFLASH_RFF - * 0b0..No reflashing - * 0b1..Reflash the embedded DMA controller +#define CCM_LPCG_STATUS1_CPU1_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU1_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU1_MODE_DONE_MASK) + +#define CCM_LPCG_STATUS1_CPU2_MODE_MASK (0x300U) +#define CCM_LPCG_STATUS1_CPU2_MODE_SHIFT (8U) +/*! CPU2_MODE - Domain2 Low Power Mode + * 0b00..Run + * 0b01..Wait + * 0b10..Stop + * 0b11..Suspend */ -#define CSI_CSICR3_DMA_REFLASH_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_RFF_MASK) -#define CSI_CSICR3_FRMCNT_RST_MASK (0x8000U) -#define CSI_CSICR3_FRMCNT_RST_SHIFT (15U) -/*! FRMCNT_RST - * 0b0..Do not reset - * 0b1..Reset frame counter immediately +#define CCM_LPCG_STATUS1_CPU2_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU2_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU2_MODE_MASK) + +#define CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_MASK (0x400U) +#define CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_SHIFT (10U) +/*! CPU2_MODE_REQUEST - Domain2 request enter Low Power Mode + * 0b1..Request from domain to enter Low Power Mode + * 0b0..No request */ -#define CSI_CSICR3_FRMCNT_RST(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_RST_SHIFT)) & CSI_CSICR3_FRMCNT_RST_MASK) -#define CSI_CSICR3_FRMCNT_MASK (0xFFFF0000U) -#define CSI_CSICR3_FRMCNT_SHIFT (16U) -#define CSI_CSICR3_FRMCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_SHIFT)) & CSI_CSICR3_FRMCNT_MASK) -/*! @} */ +#define CCM_LPCG_STATUS1_CPU2_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_MASK) -/*! @name CSISTATFIFO - CSI Statistic FIFO Register */ -/*! @{ */ -#define CSI_CSISTATFIFO_STAT_MASK (0xFFFFFFFFU) -#define CSI_CSISTATFIFO_STAT_SHIFT (0U) -#define CSI_CSISTATFIFO_STAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISTATFIFO_STAT_SHIFT)) & CSI_CSISTATFIFO_STAT_MASK) -/*! @} */ +#define CCM_LPCG_STATUS1_CPU2_MODE_DONE_MASK (0x800U) +#define CCM_LPCG_STATUS1_CPU2_MODE_DONE_SHIFT (11U) +/*! CPU2_MODE_DONE - Domain2 Low Power Mode task done + * 0b1..Clock is gated-off + * 0b0..Clock is not gated + */ +#define CCM_LPCG_STATUS1_CPU2_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU2_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU2_MODE_DONE_MASK) -/*! @name CSIRFIFO - CSI RX FIFO Register */ -/*! @{ */ -#define CSI_CSIRFIFO_IMAGE_MASK (0xFFFFFFFFU) -#define CSI_CSIRFIFO_IMAGE_SHIFT (0U) -#define CSI_CSIRFIFO_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRFIFO_IMAGE_SHIFT)) & CSI_CSIRFIFO_IMAGE_MASK) -/*! @} */ +#define CCM_LPCG_STATUS1_CPU3_MODE_MASK (0x3000U) +#define CCM_LPCG_STATUS1_CPU3_MODE_SHIFT (12U) +/*! CPU3_MODE - Domain3 Low Power Mode + * 0b00..Run + * 0b01..Wait + * 0b10..Stop + * 0b11..Suspend + */ +#define CCM_LPCG_STATUS1_CPU3_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU3_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU3_MODE_MASK) -/*! @name CSIRXCNT - CSI RX Count Register */ -/*! @{ */ -#define CSI_CSIRXCNT_RXCNT_MASK (0x3FFFFFU) -#define CSI_CSIRXCNT_RXCNT_SHIFT (0U) -#define CSI_CSIRXCNT_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRXCNT_RXCNT_SHIFT)) & CSI_CSIRXCNT_RXCNT_MASK) -/*! @} */ +#define CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_MASK (0x4000U) +#define CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_SHIFT (14U) +/*! CPU3_MODE_REQUEST - Domain3 request enter Low Power Mode + * 0b1..Request from domain to enter Low Power Mode + * 0b0..No request + */ +#define CCM_LPCG_STATUS1_CPU3_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_MASK) -/*! @name CSISR - CSI Status Register */ -/*! @{ */ -#define CSI_CSISR_DRDY_MASK (0x1U) -#define CSI_CSISR_DRDY_SHIFT (0U) -/*! DRDY - * 0b0..No data (word) is ready - * 0b1..At least 1 datum (word) is ready in RXFIFO. +#define CCM_LPCG_STATUS1_CPU3_MODE_DONE_MASK (0x8000U) +#define CCM_LPCG_STATUS1_CPU3_MODE_DONE_SHIFT (15U) +/*! CPU3_MODE_DONE - Domain3 Low Power Mode task done + * 0b1..Clock is gated-off + * 0b0..Clock is not gated */ -#define CSI_CSISR_DRDY(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DRDY_SHIFT)) & CSI_CSISR_DRDY_MASK) -#define CSI_CSISR_ECC_INT_MASK (0x2U) -#define CSI_CSISR_ECC_INT_SHIFT (1U) -/*! ECC_INT - * 0b0..No error detected - * 0b1..Error is detected in CCIR coding +#define CCM_LPCG_STATUS1_CPU3_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU3_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU3_MODE_DONE_MASK) + +#define CCM_LPCG_STATUS1_TARGET_SETPOINT_MASK (0xF0000U) +#define CCM_LPCG_STATUS1_TARGET_SETPOINT_SHIFT (16U) +/*! TARGET_SETPOINT - Next Setpoint to change to */ -#define CSI_CSISR_ECC_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_ECC_INT_SHIFT)) & CSI_CSISR_ECC_INT_MASK) -#define CSI_CSISR_HISTOGRAM_CALC_DONE_INT_MASK (0x4U) -#define CSI_CSISR_HISTOGRAM_CALC_DONE_INT_SHIFT (2U) -/*! HISTOGRAM_CALC_DONE_INT - * 0b0..Histogram calculation is not finished - * 0b1..Histogram calculation is done and driver can access the PIXEL_COUNTERS(CSI_CSICR21~CSI_CSICR276) to get the gray level +#define CCM_LPCG_STATUS1_TARGET_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_TARGET_SETPOINT_SHIFT)) & CCM_LPCG_STATUS1_TARGET_SETPOINT_MASK) + +#define CCM_LPCG_STATUS1_CURRENT_SETPOINT_MASK (0xF00000U) +#define CCM_LPCG_STATUS1_CURRENT_SETPOINT_SHIFT (20U) +/*! CURRENT_SETPOINT - Current Setpoint */ -#define CSI_CSISR_HISTOGRAM_CALC_DONE_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_HISTOGRAM_CALC_DONE_INT_SHIFT)) & CSI_CSISR_HISTOGRAM_CALC_DONE_INT_MASK) -#define CSI_CSISR_HRESP_ERR_INT_MASK (0x80U) -#define CSI_CSISR_HRESP_ERR_INT_SHIFT (7U) -/*! HRESP_ERR_INT - * 0b0..No hresponse error. - * 0b1..Hresponse error is detected. +#define CCM_LPCG_STATUS1_CURRENT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CURRENT_SETPOINT_SHIFT)) & CCM_LPCG_STATUS1_CURRENT_SETPOINT_MASK) + +#define CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_MASK (0x1000000U) +#define CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_SHIFT (24U) +/*! SETPOINT_OFF_REQUEST - Clock gate turn off request from GPC Setpoint + * 0b1..Clock gate requested to be turned off + * 0b0..No request */ -#define CSI_CSISR_HRESP_ERR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_HRESP_ERR_INT_SHIFT)) & CSI_CSISR_HRESP_ERR_INT_MASK) -#define CSI_CSISR_COF_INT_MASK (0x2000U) -#define CSI_CSISR_COF_INT_SHIFT (13U) -/*! COF_INT - * 0b0..Video field has no change. - * 0b1..Change of video field is detected. +#define CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_MASK) + +#define CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_MASK (0x2000000U) +#define CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_SHIFT (25U) +/*! SETPOINT_OFF_DONE - Clock gate turn off finish from GPC Setpoint + * 0b1..Clock gate is turned off + * 0b0..Clock gate is not turned off */ -#define CSI_CSISR_COF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_COF_INT_SHIFT)) & CSI_CSISR_COF_INT_MASK) -#define CSI_CSISR_F1_INT_MASK (0x4000U) -#define CSI_CSISR_F1_INT_SHIFT (14U) -/*! F1_INT - * 0b0..Field 1 of video is not detected. - * 0b1..Field 1 of video is about to start. - */ -#define CSI_CSISR_F1_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F1_INT_SHIFT)) & CSI_CSISR_F1_INT_MASK) -#define CSI_CSISR_F2_INT_MASK (0x8000U) -#define CSI_CSISR_F2_INT_SHIFT (15U) -/*! F2_INT - * 0b0..Field 2 of video is not detected - * 0b1..Field 2 of video is about to start - */ -#define CSI_CSISR_F2_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F2_INT_SHIFT)) & CSI_CSISR_F2_INT_MASK) -#define CSI_CSISR_SOF_INT_MASK (0x10000U) -#define CSI_CSISR_SOF_INT_SHIFT (16U) -/*! SOF_INT - * 0b0..SOF is not detected. - * 0b1..SOF is detected. - */ -#define CSI_CSISR_SOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SOF_INT_SHIFT)) & CSI_CSISR_SOF_INT_MASK) -#define CSI_CSISR_EOF_INT_MASK (0x20000U) -#define CSI_CSISR_EOF_INT_SHIFT (17U) -/*! EOF_INT - * 0b0..EOF is not detected. - * 0b1..EOF is detected. - */ -#define CSI_CSISR_EOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_EOF_INT_SHIFT)) & CSI_CSISR_EOF_INT_MASK) -#define CSI_CSISR_RxFF_INT_MASK (0x40000U) -#define CSI_CSISR_RxFF_INT_SHIFT (18U) -/*! RxFF_INT - * 0b0..RxFIFO is not full. - * 0b1..RxFIFO is full. - */ -#define CSI_CSISR_RxFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RxFF_INT_SHIFT)) & CSI_CSISR_RxFF_INT_MASK) -#define CSI_CSISR_DMA_TSF_DONE_FB1_MASK (0x80000U) -#define CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT (19U) -/*! DMA_TSF_DONE_FB1 - * 0b0..DMA transfer is not completed. - * 0b1..DMA transfer is completed. - */ -#define CSI_CSISR_DMA_TSF_DONE_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB1_MASK) -#define CSI_CSISR_DMA_TSF_DONE_FB2_MASK (0x100000U) -#define CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT (20U) -/*! DMA_TSF_DONE_FB2 - * 0b0..DMA transfer is not completed. - * 0b1..DMA transfer is completed. - */ -#define CSI_CSISR_DMA_TSF_DONE_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB2_MASK) -#define CSI_CSISR_STATFF_INT_MASK (0x200000U) -#define CSI_CSISR_STATFF_INT_SHIFT (21U) -/*! STATFF_INT - * 0b0..STATFIFO is not full. - * 0b1..STATFIFO is full. - */ -#define CSI_CSISR_STATFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_STATFF_INT_SHIFT)) & CSI_CSISR_STATFF_INT_MASK) -#define CSI_CSISR_DMA_TSF_DONE_SFF_MASK (0x400000U) -#define CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT (22U) -/*! DMA_TSF_DONE_SFF - * 0b0..DMA transfer is not completed. - * 0b1..DMA transfer is completed. - */ -#define CSI_CSISR_DMA_TSF_DONE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_SFF_MASK) -#define CSI_CSISR_RF_OR_INT_MASK (0x1000000U) -#define CSI_CSISR_RF_OR_INT_SHIFT (24U) -/*! RF_OR_INT - * 0b0..RXFIFO has not overflowed. - * 0b1..RXFIFO has overflowed. - */ -#define CSI_CSISR_RF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RF_OR_INT_SHIFT)) & CSI_CSISR_RF_OR_INT_MASK) -#define CSI_CSISR_SF_OR_INT_MASK (0x2000000U) -#define CSI_CSISR_SF_OR_INT_SHIFT (25U) -/*! SF_OR_INT - * 0b0..STATFIFO has not overflowed. - * 0b1..STATFIFO has overflowed. +#define CCM_LPCG_STATUS1_SETPOINT_OFF_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_MASK) + +#define CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_MASK (0x4000000U) +#define CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_SHIFT (26U) +/*! SETPOINT_ON_REQUEST - Clock gate turn on request from GPC Setpoint + * 0b1..Clock gate requested to be turned on + * 0b0..No request */ -#define CSI_CSISR_SF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SF_OR_INT_SHIFT)) & CSI_CSISR_SF_OR_INT_MASK) -#define CSI_CSISR_DMA_FIELD1_DONE_MASK (0x4000000U) -#define CSI_CSISR_DMA_FIELD1_DONE_SHIFT (26U) -#define CSI_CSISR_DMA_FIELD1_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD1_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD1_DONE_MASK) -#define CSI_CSISR_DMA_FIELD0_DONE_MASK (0x8000000U) -#define CSI_CSISR_DMA_FIELD0_DONE_SHIFT (27U) -#define CSI_CSISR_DMA_FIELD0_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD0_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD0_DONE_MASK) -#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U) -#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT (28U) -#define CSI_CSISR_BASEADDR_CHHANGE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK) -/*! @} */ +#define CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_MASK) -/*! @name CSIDMASA_STATFIFO - CSI DMA Start Address Register - for STATFIFO */ -/*! @{ */ -#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU) -#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U) -#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK) +#define CCM_LPCG_STATUS1_SETPOINT_ON_DONE_MASK (0x8000000U) +#define CCM_LPCG_STATUS1_SETPOINT_ON_DONE_SHIFT (27U) +/*! SETPOINT_ON_DONE - Clock gate turn on finish from GPC Setpoint + * 0b1..Clock gate is turned on + * 0b0..Clock gate is not turned on + */ +#define CCM_LPCG_STATUS1_SETPOINT_ON_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_ON_DONE_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_ON_DONE_MASK) /*! @} */ -/*! @name CSIDMATS_STATFIFO - CSI DMA Transfer Size Register - for STATFIFO */ -/*! @{ */ -#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU) -#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U) -#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK) -/*! @} */ +/* The count of CCM_LPCG_STATUS1 */ +#define CCM_LPCG_STATUS1_COUNT (138U) -/*! @name CSIDMASA_FB1 - CSI DMA Start Address Register - for Frame Buffer1 */ +/*! @name LPCG_CONFIG - LPCG configuration */ /*! @{ */ -#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU) -#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U) -#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK) -/*! @} */ -/*! @name CSIDMASA_FB2 - CSI DMA Transfer Size Register - for Frame Buffer2 */ -/*! @{ */ -#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU) -#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U) -#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK) +#define CCM_LPCG_CONFIG_SETPOINT_PRESENT_MASK (0x10U) +#define CCM_LPCG_CONFIG_SETPOINT_PRESENT_SHIFT (4U) +/*! SETPOINT_PRESENT - Setpoint present + * 0b1..Setpoint is implemented. + * 0b0..Setpoint is not implemented. + */ +#define CCM_LPCG_CONFIG_SETPOINT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_CONFIG_SETPOINT_PRESENT_SHIFT)) & CCM_LPCG_CONFIG_SETPOINT_PRESENT_MASK) /*! @} */ -/*! @name CSIFBUF_PARA - CSI Frame Buffer Parameter Register */ -/*! @{ */ -#define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU) -#define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT (0U) -#define CSI_CSIFBUF_PARA_FBUF_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK) -#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U) -#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U) -#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK) -/*! @} */ +/* The count of CCM_LPCG_CONFIG */ +#define CCM_LPCG_CONFIG_COUNT (138U) -/*! @name CSIIMAG_PARA - CSI Image Parameter Register */ +/*! @name LPCG_AUTHEN - LPCG access control */ /*! @{ */ -#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU) -#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT (0U) -#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK) -#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U) -#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT (16U) -#define CSI_CSIIMAG_PARA_IMAGE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK) -/*! @} */ -/*! @name CSICR18 - CSI Control Register 18 */ -/*! @{ */ -#define CSI_CSICR18_DEINTERLACE_EN_MASK (0x4U) -#define CSI_CSICR18_DEINTERLACE_EN_SHIFT (2U) -/*! DEINTERLACE_EN - * 0b0..Deinterlace disabled - * 0b1..Deinterlace enabled - */ -#define CSI_CSICR18_DEINTERLACE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DEINTERLACE_EN_SHIFT)) & CSI_CSICR18_DEINTERLACE_EN_MASK) -#define CSI_CSICR18_PARALLEL24_EN_MASK (0x8U) -#define CSI_CSICR18_PARALLEL24_EN_SHIFT (3U) -#define CSI_CSICR18_PARALLEL24_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_PARALLEL24_EN_SHIFT)) & CSI_CSICR18_PARALLEL24_EN_MASK) -#define CSI_CSICR18_BASEADDR_SWITCH_EN_MASK (0x10U) -#define CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT (4U) -#define CSI_CSICR18_BASEADDR_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_EN_MASK) -#define CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK (0x20U) -#define CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT (5U) -/*! BASEADDR_SWITCH_SEL - * 0b0..Switching base address at the edge of the vsync - * 0b1..Switching base address at the edge of the first data of each frame - */ -#define CSI_CSICR18_BASEADDR_SWITCH_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK) -#define CSI_CSICR18_FIELD0_DONE_IE_MASK (0x40U) -#define CSI_CSICR18_FIELD0_DONE_IE_SHIFT (6U) -/*! FIELD0_DONE_IE - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CSI_CSICR18_FIELD0_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_FIELD0_DONE_IE_SHIFT)) & CSI_CSICR18_FIELD0_DONE_IE_MASK) -#define CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK (0x80U) -#define CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT (7U) -/*! DMA_FIELD1_DONE_IE - * 0b0..Interrupt disabled - * 0b1..Interrupt enabled - */ -#define CSI_CSICR18_DMA_FIELD1_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK) -#define CSI_CSICR18_LAST_DMA_REQ_SEL_MASK (0x100U) -#define CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT (8U) -/*! LAST_DMA_REQ_SEL - * 0b0..fifo_full_level - * 0b1..hburst_length - */ -#define CSI_CSICR18_LAST_DMA_REQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CSICR18_LAST_DMA_REQ_SEL_MASK) -#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U) -#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U) -#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK) -#define CSI_CSICR18_RGB888A_FORMAT_SEL_MASK (0x400U) -#define CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT (10U) -/*! RGB888A_FORMAT_SEL - * 0b0..{8'h0, data[23:0]} - * 0b1..{data[23:0], 8'h0} - */ -#define CSI_CSICR18_RGB888A_FORMAT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CSICR18_RGB888A_FORMAT_SEL_MASK) -#define CSI_CSICR18_AHB_HPROT_MASK (0xF000U) -#define CSI_CSICR18_AHB_HPROT_SHIFT (12U) -#define CSI_CSICR18_AHB_HPROT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_AHB_HPROT_SHIFT)) & CSI_CSICR18_AHB_HPROT_MASK) -#define CSI_CSICR18_MASK_OPTION_MASK (0xC0000U) -#define CSI_CSICR18_MASK_OPTION_SHIFT (18U) -/*! MASK_OPTION - * 0b00..Writing to memory from first completely frame, when using this option, the CSI_ENABLE should be 1. - * 0b01..Writing to memory when CSI_ENABLE is 1. - * 0b10..Writing to memory from second completely frame, when using this option, the CSI_ENABLE should be 1. - * 0b11..Writing to memory when data comes in, not matter the CSI_ENABLE is 1 or 0. +#define CCM_LPCG_AUTHEN_TZ_USER_MASK (0x1U) +#define CCM_LPCG_AUTHEN_TZ_USER_SHIFT (0U) +/*! TZ_USER - User access + * 0b1..LPCG can be changed in user mode. + * 0b0..LPCG cannot be changed in user mode. */ -#define CSI_CSICR18_MASK_OPTION(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MASK_OPTION_SHIFT)) & CSI_CSICR18_MASK_OPTION_MASK) -#define CSI_CSICR18_CSI_ENABLE_MASK (0x80000000U) -#define CSI_CSICR18_CSI_ENABLE_SHIFT (31U) -#define CSI_CSICR18_CSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_ENABLE_SHIFT)) & CSI_CSICR18_CSI_ENABLE_MASK) -/*! @} */ +#define CCM_LPCG_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_TZ_USER_SHIFT)) & CCM_LPCG_AUTHEN_TZ_USER_MASK) -/*! @name CSICR19 - CSI Control Register 19 */ -/*! @{ */ -#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU) -#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U) -#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK) -/*! @} */ +#define CCM_LPCG_AUTHEN_TZ_NS_MASK (0x2U) +#define CCM_LPCG_AUTHEN_TZ_NS_SHIFT (1U) +/*! TZ_NS - Non-secure access + * 0b0..Cannot be changed in Non-secure mode. + * 0b1..Can be changed in Non-secure mode. + */ +#define CCM_LPCG_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_TZ_NS_SHIFT)) & CCM_LPCG_AUTHEN_TZ_NS_MASK) -/*! @name CSICR20 - CSI Control Register 20 */ -/*! @{ */ -#define CSI_CSICR20_THRESHOLD_MASK (0xFFU) -#define CSI_CSICR20_THRESHOLD_SHIFT (0U) -#define CSI_CSICR20_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR20_THRESHOLD_SHIFT)) & CSI_CSICR20_THRESHOLD_MASK) -#define CSI_CSICR20_BINARY_EN_MASK (0x100U) -#define CSI_CSICR20_BINARY_EN_SHIFT (8U) -/*! BINARY_EN - * 0b0..Output is Y8 format(8 bits each pixel) - * 0b1..Output is Y1 format(1 bit each pixel) +#define CCM_LPCG_AUTHEN_LOCK_TZ_MASK (0x10U) +#define CCM_LPCG_AUTHEN_LOCK_TZ_SHIFT (4U) +/*! LOCK_TZ - lock truszone setting + * 0b0..Trustzone setting is not locked. + * 0b1..Trustzone setting is locked. */ -#define CSI_CSICR20_BINARY_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR20_BINARY_EN_SHIFT)) & CSI_CSICR20_BINARY_EN_MASK) -#define CSI_CSICR20_QR_DATA_FORMAT_MASK (0xE00U) -#define CSI_CSICR20_QR_DATA_FORMAT_SHIFT (9U) -/*! QR_DATA_FORMAT - * 0b000..YU YV one cycle per 1 pixel input - * 0b001..UY VY one cycle per1 pixel input - * 0b010..Y U Y V two cycles per 1 pixel input - * 0b011..U Y V Y two cycles per 1 pixel input - * 0b100..YUV one cycle per 1 pixel input - * 0b101..Y U V three cycles per 1 pixel input +#define CCM_LPCG_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_TZ_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_TZ_MASK) + +#define CCM_LPCG_AUTHEN_WHITE_LIST_MASK (0xF00U) +#define CCM_LPCG_AUTHEN_WHITE_LIST_SHIFT (8U) +/*! WHITE_LIST - Whitelist */ -#define CSI_CSICR20_QR_DATA_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR20_QR_DATA_FORMAT_SHIFT)) & CSI_CSICR20_QR_DATA_FORMAT_MASK) -#define CSI_CSICR20_BIG_END_MASK (0x1000U) -#define CSI_CSICR20_BIG_END_SHIFT (12U) -/*! BIG_END - * 0b0..The latest data will put to the lowest position when store to memory. - * 0b1..The latest data will put to the highest position when store to memory. +#define CCM_LPCG_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_WHITE_LIST_SHIFT)) & CCM_LPCG_AUTHEN_WHITE_LIST_MASK) + +#define CCM_LPCG_AUTHEN_LOCK_LIST_MASK (0x1000U) +#define CCM_LPCG_AUTHEN_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock Whitelist + * 0b0..Whitelist is not locked. + * 0b1..Whitelist is locked. */ -#define CSI_CSICR20_BIG_END(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR20_BIG_END_SHIFT)) & CSI_CSICR20_BIG_END_MASK) -#define CSI_CSICR20_10BIT_NEW_EN_MASK (0x20000000U) -#define CSI_CSICR20_10BIT_NEW_EN_SHIFT (29U) -/*! 10BIT_NEW_EN - * 0b0..When input 8bits data, it will use the data[9:2] - * 0b1..When input 10bits data, it will use the data[7:0] +#define CCM_LPCG_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_LIST_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_LIST_MASK) + +#define CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK (0x10000U) +#define CCM_LPCG_AUTHEN_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by domain + * 0b1..Clock works in Domain Mode + * 0b0..Clock does not work in Domain Mode */ -#define CSI_CSICR20_10BIT_NEW_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR20_10BIT_NEW_EN_SHIFT)) & CSI_CSICR20_10BIT_NEW_EN_MASK) -#define CSI_CSICR20_HISTOGRAM_EN_MASK (0x40000000U) -#define CSI_CSICR20_HISTOGRAM_EN_SHIFT (30U) -/*! HISTOGRAM_EN - * 0b0..Histogram disable - * 0b1..Histogram enable +#define CCM_LPCG_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK) + +#define CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK (0x20000U) +#define CCM_LPCG_AUTHEN_SETPOINT_MODE_SHIFT (17U) +/*! SETPOINT_MODE - Low power and access control by Setpoint + * 0b1..LPCG is functioning in Setpoint controlled Mode + * 0b0..LPCG is not functioning in Setpoint controlled Mode */ -#define CSI_CSICR20_HISTOGRAM_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR20_HISTOGRAM_EN_SHIFT)) & CSI_CSICR20_HISTOGRAM_EN_MASK) -#define CSI_CSICR20_QRCODE_EN_MASK (0x80000000U) -#define CSI_CSICR20_QRCODE_EN_SHIFT (31U) -/*! QRCODE_EN - * 0b0..Normal mode - * 0b1..grcode mode +#define CCM_LPCG_AUTHEN_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_SETPOINT_MODE_SHIFT)) & CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK) + +#define CCM_LPCG_AUTHEN_CPULPM_MASK (0x40000U) +#define CCM_LPCG_AUTHEN_CPULPM_SHIFT (18U) +/*! CPULPM - CPU Low Power Mode + * 0b1..LPCG is functioning in Low Power Mode + * 0b0..LPCG is not functioning in Low power Mode */ -#define CSI_CSICR20_QRCODE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR20_QRCODE_EN_SHIFT)) & CSI_CSICR20_QRCODE_EN_MASK) -/*! @} */ +#define CCM_LPCG_AUTHEN_CPULPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_CPULPM_SHIFT)) & CCM_LPCG_AUTHEN_CPULPM_MASK) -/*! @name CSICR - CSI Control Register n */ -/*! @{ */ -#define CSI_CSICR_PIXEL_COUNTERS_MASK (0xFFFFFFU) -#define CSI_CSICR_PIXEL_COUNTERS_SHIFT (0U) -#define CSI_CSICR_PIXEL_COUNTERS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR_PIXEL_COUNTERS_SHIFT)) & CSI_CSICR_PIXEL_COUNTERS_MASK) +#define CCM_LPCG_AUTHEN_LOCK_MODE_MASK (0x100000U) +#define CCM_LPCG_AUTHEN_LOCK_MODE_SHIFT (20U) +/*! LOCK_MODE - Lock low power and access mode + * 0b0..MODE is not locked. + * 0b1..MODE is locked. + */ +#define CCM_LPCG_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_MODE_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_MODE_MASK) /*! @} */ -/* The count of CSI_CSICR */ -#define CSI_CSICR_COUNT (256U) +/* The count of CCM_LPCG_AUTHEN */ +#define CCM_LPCG_AUTHEN_COUNT (138U) /*! * @} - */ /* end of group CSI_Register_Masks */ + */ /* end of group CCM_Register_Masks */ -/* CSI - Peripheral instance base addresses */ -/** Peripheral CSI base address */ -#define CSI_BASE (0x40800000u) -/** Peripheral CSI base pointer */ -#define CSI ((CSI_Type *)CSI_BASE) -/** Array initializer of CSI peripheral base addresses */ -#define CSI_BASE_ADDRS { CSI_BASE } -/** Array initializer of CSI peripheral base pointers */ -#define CSI_BASE_PTRS { CSI } -/** Interrupt vectors for the CSI peripheral type */ -#define CSI_IRQS { CSI_IRQn } +/* CCM - Peripheral instance base addresses */ +/** Peripheral CCM base address */ +#define CCM_BASE (0x40CC0000u) +/** Peripheral CCM base pointer */ +#define CCM ((CCM_Type *)CCM_BASE) +/** Array initializer of CCM peripheral base addresses */ +#define CCM_BASE_ADDRS { CCM_BASE } +/** Array initializer of CCM peripheral base pointers */ +#define CCM_BASE_PTRS { CCM } /*! * @} - */ /* end of group CSI_Peripheral_Access_Layer */ + */ /* end of group CCM_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- - -- DAC Peripheral Access Layer + -- CCM_OBS Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! - * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer + * @addtogroup CCM_OBS_Peripheral_Access_Layer CCM_OBS Peripheral Access Layer * @{ */ -/** DAC - Register Layout Typedef */ +/** CCM_OBS - Register Layout Typedef */ typedef struct { - __I uint32_t VERID; /**< Version Identifier Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __O uint32_t DATA; /**< DAC Data Register, offset: 0x8 */ - __IO uint32_t CR; /**< DAC Status and Control Register, offset: 0xC */ - __I uint32_t PTR; /**< DAC FIFO Pointer Register, offset: 0x10 */ - __IO uint32_t CR2; /**< DAC Status and Control Register 2, offset: 0x14 */ - __IO uint32_t ITRM; /**< Internal Current Reference Trim Register, offset: 0x18 */ -} DAC_Type; + struct { /* offset: 0x0, array step: 0x80 */ + __IO uint32_t CONTROL; /**< Observe control, array offset: 0x0, array step: 0x80 */ + __IO uint32_t CONTROL_SET; /**< Observe control, array offset: 0x4, array step: 0x80 */ + __IO uint32_t CONTROL_CLR; /**< Observe control, array offset: 0x8, array step: 0x80 */ + __IO uint32_t CONTROL_TOG; /**< Observe control, array offset: 0xC, array step: 0x80 */ + uint8_t RESERVED_0[16]; + __I uint32_t STATUS0; /**< Observe status, array offset: 0x20, array step: 0x80 */ + uint8_t RESERVED_1[12]; + __IO uint32_t AUTHEN; /**< Observe access control, array offset: 0x30, array step: 0x80 */ + __IO uint32_t AUTHEN_SET; /**< Observe access control, array offset: 0x34, array step: 0x80 */ + __IO uint32_t AUTHEN_CLR; /**< Observe access control, array offset: 0x38, array step: 0x80 */ + __IO uint32_t AUTHEN_TOG; /**< Observe access control, array offset: 0x3C, array step: 0x80 */ + __I uint32_t FREQUENCY_CURRENT; /**< Current frequency detected, array offset: 0x40, array step: 0x80 */ + __I uint32_t FREQUENCY_MIN; /**< Minimum frequency detected, array offset: 0x44, array step: 0x80 */ + __I uint32_t FREQUENCY_MAX; /**< Maximum frequency detected, array offset: 0x48, array step: 0x80 */ + uint8_t RESERVED_2[52]; + } OBSERVE[6]; +} CCM_OBS_Type; /* ---------------------------------------------------------------------------- - -- DAC Register Masks + -- CCM_OBS Register Masks ---------------------------------------------------------------------------- */ /*! - * @addtogroup DAC_Register_Masks DAC Register Masks + * @addtogroup CCM_OBS_Register_Masks CCM_OBS Register Masks * @{ */ -/*! @name VERID - Version Identifier Register */ +/*! @name OBSERVE_CONTROL - Observe control */ /*! @{ */ -#define DAC_VERID_FEATURE_MASK (0xFFFFU) -#define DAC_VERID_FEATURE_SHIFT (0U) -/*! FEATURE - Feature Identification Number - * 0b0000000000000000..Standard feature set - * 0b0000000000000001..C40 feature set - * 0b0000000000000010..5V DAC feature set - * 0b0000000000000100..ADC BIST feature set + +#define CCM_OBS_OBSERVE_CONTROL_SELECT_MASK (0x1FFU) +#define CCM_OBS_OBSERVE_CONTROL_SELECT_SHIFT (0U) +/*! SELECT - Observe signal selector */ -#define DAC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_FEATURE_SHIFT)) & DAC_VERID_FEATURE_MASK) -#define DAC_VERID_MINOR_MASK (0xFF0000U) -#define DAC_VERID_MINOR_SHIFT (16U) -/*! MINOR - Minor version number +#define CCM_OBS_OBSERVE_CONTROL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SELECT_MASK) + +#define CCM_OBS_OBSERVE_CONTROL_RAW_MASK (0x1000U) +#define CCM_OBS_OBSERVE_CONTROL_RAW_SHIFT (12U) +/*! RAW - Observe raw signal + * 0b0..Select divided signal. + * 0b1..Select raw signal. */ -#define DAC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MINOR_SHIFT)) & DAC_VERID_MINOR_MASK) -#define DAC_VERID_MAJOR_MASK (0xFF000000U) -#define DAC_VERID_MAJOR_SHIFT (24U) -/*! MAJOR - Major version number +#define CCM_OBS_OBSERVE_CONTROL_RAW(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_RAW_MASK) + +#define CCM_OBS_OBSERVE_CONTROL_INV_MASK (0x2000U) +#define CCM_OBS_OBSERVE_CONTROL_INV_SHIFT (13U) +/*! INV - Invert + * 0b0..Clock phase remain same. + * 0b1..Invert clock phase before measurement or send to IO. */ -#define DAC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MAJOR_SHIFT)) & DAC_VERID_MAJOR_MASK) -/*! @} */ +#define CCM_OBS_OBSERVE_CONTROL_INV(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_INV_MASK) -/*! @name PARAM - Parameter Register */ -/*! @{ */ -#define DAC_PARAM_FIFOSZ_MASK (0x7U) -#define DAC_PARAM_FIFOSZ_SHIFT (0U) -/*! FIFOSZ - FIFO size - * 0b000..FIFO depth is 2 - * 0b001..FIFO depth is 4 - * 0b010..FIFO depth is 8 - * 0b011..FIFO depth is 16 - * 0b100..FIFO depth is 32 - * 0b101..FIFO depth is 64 - * 0b110..FIFO depth is 128 - * 0b111..FIFO depth is 256 +#define CCM_OBS_OBSERVE_CONTROL_RESET_MASK (0x8000U) +#define CCM_OBS_OBSERVE_CONTROL_RESET_SHIFT (15U) +/*! RESET - Reset observe divider + * 0b0..No reset + * 0b1..Reset observe divider */ -#define DAC_PARAM_FIFOSZ(x) (((uint32_t)(((uint32_t)(x)) << DAC_PARAM_FIFOSZ_SHIFT)) & DAC_PARAM_FIFOSZ_MASK) -/*! @} */ +#define CCM_OBS_OBSERVE_CONTROL_RESET(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_RESET_MASK) -/*! @name DATA - DAC Data Register */ -/*! @{ */ -#define DAC_DATA_DATA0_MASK (0xFFFU) -#define DAC_DATA_DATA0_SHIFT (0U) -/*! DATA0 - FIFO DATA0 +#define CCM_OBS_OBSERVE_CONTROL_DIVIDE_MASK (0xFF0000U) +#define CCM_OBS_OBSERVE_CONTROL_DIVIDE_SHIFT (16U) +/*! DIVIDE - Divider for observe signal */ -#define DAC_DATA_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DAC_DATA_DATA0_SHIFT)) & DAC_DATA_DATA0_MASK) +#define CCM_OBS_OBSERVE_CONTROL_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_DIVIDE_MASK) + +#define CCM_OBS_OBSERVE_CONTROL_OFF_MASK (0x1000000U) +#define CCM_OBS_OBSERVE_CONTROL_OFF_SHIFT (24U) +/*! OFF - Turn off + * 0b0..observe slice is on + * 0b1..observe slice is off + */ +#define CCM_OBS_OBSERVE_CONTROL_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_OFF_MASK) /*! @} */ -/*! @name CR - DAC Status and Control Register */ +/* The count of CCM_OBS_OBSERVE_CONTROL */ +#define CCM_OBS_OBSERVE_CONTROL_COUNT (6U) + +/*! @name OBSERVE_CONTROL_SET - Observe control */ /*! @{ */ -#define DAC_CR_FULLF_MASK (0x1U) -#define DAC_CR_FULLF_SHIFT (0U) -/*! FULLF - Full Flag - * 0b0..FIFO is not full. - * 0b1..FIFO is full. + +#define CCM_OBS_OBSERVE_CONTROL_SET_SELECT_MASK (0x1FFU) +#define CCM_OBS_OBSERVE_CONTROL_SET_SELECT_SHIFT (0U) +/*! SELECT - Observe signal selector */ -#define DAC_CR_FULLF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLF_SHIFT)) & DAC_CR_FULLF_MASK) -#define DAC_CR_NEMPTF_MASK (0x2U) -#define DAC_CR_NEMPTF_SHIFT (1U) -/*! NEMPTF - Nearly Empty Flag - * 0b0..More than one data is available in the FIFO. - * 0b1..One data is available in the FIFO. +#define CCM_OBS_OBSERVE_CONTROL_SET_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_SELECT_MASK) + +#define CCM_OBS_OBSERVE_CONTROL_SET_RAW_MASK (0x1000U) +#define CCM_OBS_OBSERVE_CONTROL_SET_RAW_SHIFT (12U) +/*! RAW - Observe raw signal */ -#define DAC_CR_NEMPTF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_NEMPTF_SHIFT)) & DAC_CR_NEMPTF_MASK) -#define DAC_CR_WMF_MASK (0x4U) -#define DAC_CR_WMF_SHIFT (2U) -/*! WMF - FIFO Watermark Status Flag - * 0b0..The DAC buffer read pointer has not reached the watermark level. - * 0b1..The DAC buffer read pointer has reached the watermark level. +#define CCM_OBS_OBSERVE_CONTROL_SET_RAW(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_RAW_MASK) + +#define CCM_OBS_OBSERVE_CONTROL_SET_INV_MASK (0x2000U) +#define CCM_OBS_OBSERVE_CONTROL_SET_INV_SHIFT (13U) +/*! INV - Invert */ -#define DAC_CR_WMF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WMF_SHIFT)) & DAC_CR_WMF_MASK) -#define DAC_CR_UDFF_MASK (0x8U) -#define DAC_CR_UDFF_SHIFT (3U) -/*! UDFF - Underflow Flag - * 0b0..No underflow has occurred since the last time the flag was cleared. - * 0b1..At least one trigger underflow has occurred since the last time the flag was cleared. +#define CCM_OBS_OBSERVE_CONTROL_SET_INV(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_INV_MASK) + +#define CCM_OBS_OBSERVE_CONTROL_SET_RESET_MASK (0x8000U) +#define CCM_OBS_OBSERVE_CONTROL_SET_RESET_SHIFT (15U) +/*! RESET - Reset observe divider */ -#define DAC_CR_UDFF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_UDFF_SHIFT)) & DAC_CR_UDFF_MASK) -#define DAC_CR_OVFF_MASK (0x10U) -#define DAC_CR_OVFF_SHIFT (4U) -/*! OVFF - Overflow Flag - * 0b0..No overflow has occurred since the last time the flag was cleared. - * 0b1..At least one FIFO overflow has occurred since the last time the flag was cleared. +#define CCM_OBS_OBSERVE_CONTROL_SET_RESET(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_RESET_MASK) + +#define CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_MASK (0xFF0000U) +#define CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_SHIFT (16U) +/*! DIVIDE - Divider for observe signal */ -#define DAC_CR_OVFF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_OVFF_SHIFT)) & DAC_CR_OVFF_MASK) -#define DAC_CR_FULLIE_MASK (0x100U) -#define DAC_CR_FULLIE_SHIFT (8U) -/*! FULLIE - Full Interrupt Enable - * 0b0..FIFO Full interrupt is disabled. - * 0b1..FIFO Full interrupt is enabled. +#define CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_MASK) + +#define CCM_OBS_OBSERVE_CONTROL_SET_OFF_MASK (0x1000000U) +#define CCM_OBS_OBSERVE_CONTROL_SET_OFF_SHIFT (24U) +/*! OFF - Turn off */ -#define DAC_CR_FULLIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLIE_SHIFT)) & DAC_CR_FULLIE_MASK) -#define DAC_CR_EMPTIE_MASK (0x200U) -#define DAC_CR_EMPTIE_SHIFT (9U) -/*! EMPTIE - Nearly Empty Interrupt Enable - * 0b0..FIFO Nearly Empty interrupt is disabled. - * 0b1..FIFO Nearly Empty interrupt is enabled. +#define CCM_OBS_OBSERVE_CONTROL_SET_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_OFF_MASK) +/*! @} */ + +/* The count of CCM_OBS_OBSERVE_CONTROL_SET */ +#define CCM_OBS_OBSERVE_CONTROL_SET_COUNT (6U) + +/*! @name OBSERVE_CONTROL_CLR - Observe control */ +/*! @{ */ + +#define CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_MASK (0x1FFU) +#define CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_SHIFT (0U) +/*! SELECT - Observe signal selector */ -#define DAC_CR_EMPTIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_EMPTIE_SHIFT)) & DAC_CR_EMPTIE_MASK) -#define DAC_CR_WTMIE_MASK (0x400U) -#define DAC_CR_WTMIE_SHIFT (10U) -/*! WTMIE - Watermark Interrupt Enable - * 0b0..Watermark interrupt is disabled. - * 0b1..Watermark interrupt is enabled. +#define CCM_OBS_OBSERVE_CONTROL_CLR_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_MASK) + +#define CCM_OBS_OBSERVE_CONTROL_CLR_RAW_MASK (0x1000U) +#define CCM_OBS_OBSERVE_CONTROL_CLR_RAW_SHIFT (12U) +/*! RAW - Observe raw signal */ -#define DAC_CR_WTMIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WTMIE_SHIFT)) & DAC_CR_WTMIE_MASK) -#define DAC_CR_SWTRG_MASK (0x1000U) -#define DAC_CR_SWTRG_SHIFT (12U) -/*! SWTRG - DAC Software Trigger - * 0b0..The DAC soft trigger is not valid. - * 0b1..The DAC soft trigger is valid. +#define CCM_OBS_OBSERVE_CONTROL_CLR_RAW(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_RAW_MASK) + +#define CCM_OBS_OBSERVE_CONTROL_CLR_INV_MASK (0x2000U) +#define CCM_OBS_OBSERVE_CONTROL_CLR_INV_SHIFT (13U) +/*! INV - Invert */ -#define DAC_CR_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWTRG_SHIFT)) & DAC_CR_SWTRG_MASK) -#define DAC_CR_TRGSEL_MASK (0x2000U) -#define DAC_CR_TRGSEL_SHIFT (13U) -/*! TRGSEL - DAC Trigger Select - * 0b0..The DAC hardware trigger is selected. - * 0b1..The DAC software trigger is selected. +#define CCM_OBS_OBSERVE_CONTROL_CLR_INV(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_INV_MASK) + +#define CCM_OBS_OBSERVE_CONTROL_CLR_RESET_MASK (0x8000U) +#define CCM_OBS_OBSERVE_CONTROL_CLR_RESET_SHIFT (15U) +/*! RESET - Reset observe divider */ -#define DAC_CR_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_TRGSEL_SHIFT)) & DAC_CR_TRGSEL_MASK) -#define DAC_CR_DACRFS_MASK (0x4000U) -#define DAC_CR_DACRFS_SHIFT (14U) -/*! DACRFS - DAC Reference Select - * 0b0..The DAC selects DACREF_1 as the reference voltage. - * 0b1..The DAC selects DACREF_2 as the reference voltage. +#define CCM_OBS_OBSERVE_CONTROL_CLR_RESET(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_RESET_MASK) + +#define CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_MASK (0xFF0000U) +#define CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_SHIFT (16U) +/*! DIVIDE - Divider for observe signal */ -#define DAC_CR_DACRFS(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACRFS_SHIFT)) & DAC_CR_DACRFS_MASK) -#define DAC_CR_DACEN_MASK (0x8000U) -#define DAC_CR_DACEN_SHIFT (15U) -/*! DACEN - DAC Enable - * 0b0..The DAC system is disabled. - * 0b1..The DAC system is enabled. +#define CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_MASK) + +#define CCM_OBS_OBSERVE_CONTROL_CLR_OFF_MASK (0x1000000U) +#define CCM_OBS_OBSERVE_CONTROL_CLR_OFF_SHIFT (24U) +/*! OFF - Turn off */ -#define DAC_CR_DACEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACEN_SHIFT)) & DAC_CR_DACEN_MASK) -#define DAC_CR_FIFOEN_MASK (0x10000U) -#define DAC_CR_FIFOEN_SHIFT (16U) -/*! FIFOEN - FIFO Enable - * 0b0..FIFO is disabled and only one level buffer is enabled. Any data written from this buffer goes to conversion. - * 0b1..FIFO is enabled. Data will first read from FIFO to buffer then go to conversion. +#define CCM_OBS_OBSERVE_CONTROL_CLR_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_OFF_MASK) +/*! @} */ + +/* The count of CCM_OBS_OBSERVE_CONTROL_CLR */ +#define CCM_OBS_OBSERVE_CONTROL_CLR_COUNT (6U) + +/*! @name OBSERVE_CONTROL_TOG - Observe control */ +/*! @{ */ + +#define CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_MASK (0x1FFU) +#define CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_SHIFT (0U) +/*! SELECT - Observe signal selector */ -#define DAC_CR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFOEN_SHIFT)) & DAC_CR_FIFOEN_MASK) -#define DAC_CR_SWMD_MASK (0x20000U) -#define DAC_CR_SWMD_SHIFT (17U) -/*! SWMD - DAC FIFO Mode Select - * 0b0..Normal mode - * 0b1..Swing back mode +#define CCM_OBS_OBSERVE_CONTROL_TOG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_MASK) + +#define CCM_OBS_OBSERVE_CONTROL_TOG_RAW_MASK (0x1000U) +#define CCM_OBS_OBSERVE_CONTROL_TOG_RAW_SHIFT (12U) +/*! RAW - Observe raw signal */ -#define DAC_CR_SWMD(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWMD_SHIFT)) & DAC_CR_SWMD_MASK) -#define DAC_CR_UVIE_MASK (0x40000U) -#define DAC_CR_UVIE_SHIFT (18U) -/*! UVIE - Underflow and overflow interrupt enable - * 0b0..Underflow and overflow interrupt is disabled. - * 0b1..Underflow and overflow interrupt is enabled. +#define CCM_OBS_OBSERVE_CONTROL_TOG_RAW(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_RAW_MASK) + +#define CCM_OBS_OBSERVE_CONTROL_TOG_INV_MASK (0x2000U) +#define CCM_OBS_OBSERVE_CONTROL_TOG_INV_SHIFT (13U) +/*! INV - Invert */ -#define DAC_CR_UVIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_UVIE_SHIFT)) & DAC_CR_UVIE_MASK) -#define DAC_CR_FIFORST_MASK (0x200000U) -#define DAC_CR_FIFORST_SHIFT (21U) -/*! FIFORST - FIFO Reset - * 0b0..No effect - * 0b1..FIFO reset +#define CCM_OBS_OBSERVE_CONTROL_TOG_INV(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_INV_MASK) + +#define CCM_OBS_OBSERVE_CONTROL_TOG_RESET_MASK (0x8000U) +#define CCM_OBS_OBSERVE_CONTROL_TOG_RESET_SHIFT (15U) +/*! RESET - Reset observe divider */ -#define DAC_CR_FIFORST(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFORST_SHIFT)) & DAC_CR_FIFORST_MASK) -#define DAC_CR_SWRST_MASK (0x400000U) -#define DAC_CR_SWRST_SHIFT (22U) -/*! SWRST - Software reset +#define CCM_OBS_OBSERVE_CONTROL_TOG_RESET(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_RESET_MASK) + +#define CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_MASK (0xFF0000U) +#define CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_SHIFT (16U) +/*! DIVIDE - Divider for observe signal */ -#define DAC_CR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWRST_SHIFT)) & DAC_CR_SWRST_MASK) -#define DAC_CR_DMAEN_MASK (0x800000U) -#define DAC_CR_DMAEN_SHIFT (23U) -/*! DMAEN - DMA Enable Select - * 0b0..DMA is disabled. - * 0b1..DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The - * interrupts will not be presented on this module at the same time. +#define CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_MASK) + +#define CCM_OBS_OBSERVE_CONTROL_TOG_OFF_MASK (0x1000000U) +#define CCM_OBS_OBSERVE_CONTROL_TOG_OFF_SHIFT (24U) +/*! OFF - Turn off */ -#define DAC_CR_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DMAEN_SHIFT)) & DAC_CR_DMAEN_MASK) -#define DAC_CR_WML_MASK (0xFF000000U) -#define DAC_CR_WML_SHIFT (24U) -/*! WML - Watermark Level Select +#define CCM_OBS_OBSERVE_CONTROL_TOG_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_OFF_MASK) +/*! @} */ + +/* The count of CCM_OBS_OBSERVE_CONTROL_TOG */ +#define CCM_OBS_OBSERVE_CONTROL_TOG_COUNT (6U) + +/*! @name OBSERVE_STATUS0 - Observe status */ +/*! @{ */ + +#define CCM_OBS_OBSERVE_STATUS0_SELECT_MASK (0x1FFU) +#define CCM_OBS_OBSERVE_STATUS0_SELECT_SHIFT (0U) +/*! SELECT - Select value */ -#define DAC_CR_WML(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WML_SHIFT)) & DAC_CR_WML_MASK) +#define CCM_OBS_OBSERVE_STATUS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_SELECT_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_SELECT_MASK) + +#define CCM_OBS_OBSERVE_STATUS0_RAW_MASK (0x1000U) +#define CCM_OBS_OBSERVE_STATUS0_RAW_SHIFT (12U) +/*! RAW - Observe raw signal + * 0b0..Divided signal is selected + * 0b1..Raw signal is selected + */ +#define CCM_OBS_OBSERVE_STATUS0_RAW(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_RAW_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_RAW_MASK) + +#define CCM_OBS_OBSERVE_STATUS0_INV_MASK (0x2000U) +#define CCM_OBS_OBSERVE_STATUS0_INV_SHIFT (13U) +/*! INV - Polarity of the observe target + * 0b1..Polarity of the observe target is inverted + * 0b0..Polarity is not inverted + */ +#define CCM_OBS_OBSERVE_STATUS0_INV(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_INV_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_INV_MASK) + +#define CCM_OBS_OBSERVE_STATUS0_RESET_MASK (0x8000U) +#define CCM_OBS_OBSERVE_STATUS0_RESET_SHIFT (15U) +/*! RESET - Reset state + * 0b1..Observe divider is in reset state + * 0b0..Observe divider is not in reset state + */ +#define CCM_OBS_OBSERVE_STATUS0_RESET(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_RESET_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_RESET_MASK) + +#define CCM_OBS_OBSERVE_STATUS0_DIVIDE_MASK (0xFF0000U) +#define CCM_OBS_OBSERVE_STATUS0_DIVIDE_SHIFT (16U) +/*! DIVIDE - Divide value status. The clock will be divided by DIVIDE + 1. + */ +#define CCM_OBS_OBSERVE_STATUS0_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_DIVIDE_MASK) + +#define CCM_OBS_OBSERVE_STATUS0_OFF_MASK (0x1000000U) +#define CCM_OBS_OBSERVE_STATUS0_OFF_SHIFT (24U) +/*! OFF - Turn off slice + * 0b0..observe slice is on + * 0b1..observe slice is off + */ +#define CCM_OBS_OBSERVE_STATUS0_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_OFF_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_OFF_MASK) /*! @} */ -/*! @name PTR - DAC FIFO Pointer Register */ +/* The count of CCM_OBS_OBSERVE_STATUS0 */ +#define CCM_OBS_OBSERVE_STATUS0_COUNT (6U) + +/*! @name OBSERVE_AUTHEN - Observe access control */ /*! @{ */ -#define DAC_PTR_DACWFP_MASK (0xFFU) -#define DAC_PTR_DACWFP_SHIFT (0U) -/*! DACWFP - DACWFP + +#define CCM_OBS_OBSERVE_AUTHEN_TZ_USER_MASK (0x1U) +#define CCM_OBS_OBSERVE_AUTHEN_TZ_USER_SHIFT (0U) +/*! TZ_USER - User access + * 0b1..Clock can be changed in user mode. + * 0b0..Clock cannot be changed in user mode. */ -#define DAC_PTR_DACWFP(x) (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACWFP_SHIFT)) & DAC_PTR_DACWFP_MASK) -#define DAC_PTR_DACRFP_MASK (0xFF0000U) -#define DAC_PTR_DACRFP_SHIFT (16U) -/*! DACRFP - DACRFP +#define CCM_OBS_OBSERVE_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TZ_USER_MASK) + +#define CCM_OBS_OBSERVE_AUTHEN_TZ_NS_MASK (0x2U) +#define CCM_OBS_OBSERVE_AUTHEN_TZ_NS_SHIFT (1U) +/*! TZ_NS - Non-secure access + * 0b0..Cannot be changed in Non-secure mode. + * 0b1..Can be changed in Non-secure mode. */ -#define DAC_PTR_DACRFP(x) (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACRFP_SHIFT)) & DAC_PTR_DACRFP_MASK) +#define CCM_OBS_OBSERVE_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TZ_NS_MASK) + +#define CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_MASK (0x10U) +#define CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_SHIFT (4U) +/*! LOCK_TZ - Lock truszone setting + * 0b0..Trustzone setting is not locked. + * 0b1..Trustzone setting is locked. + */ +#define CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_MASK) + +#define CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_MASK (0xF00U) +#define CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_SHIFT (8U) +/*! WHITE_LIST - White list + * 0b1111..All domain can change. + * 0b0010..Domain 1 can change. + * 0b0011..Domain 0 and domain 1 can change. + * 0b0000..No domain can change. + * 0b0100..Domain 2 can change. + * 0b0001..Domain 0 can change. + */ +#define CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_MASK) + +#define CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_MASK (0x1000U) +#define CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock white list + * 0b0..White list is not locked. + * 0b1..White list is locked. + */ +#define CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_MASK) + +#define CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_MASK (0x10000U) +#define CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by domain + * 0b1..Clock works in domain mode. + * 0b0..Clock does not work in domain mode. + */ +#define CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_MASK) + +#define CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_MASK (0x100000U) +#define CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_SHIFT (20U) +/*! LOCK_MODE - Lock low power and access mode + * 0b0..MODE is not locked. + * 0b1..MODE is locked. + */ +#define CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_MASK) /*! @} */ -/*! @name CR2 - DAC Status and Control Register 2 */ +/* The count of CCM_OBS_OBSERVE_AUTHEN */ +#define CCM_OBS_OBSERVE_AUTHEN_COUNT (6U) + +/*! @name OBSERVE_AUTHEN_SET - Observe access control */ /*! @{ */ -#define DAC_CR2_BFEN_MASK (0x1U) -#define DAC_CR2_BFEN_SHIFT (0U) -/*! BFEN - Buffer Enable - * 0b0..Opamp is not used as buffer - * 0b1..Opamp is used as buffer + +#define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_MASK (0x1U) +#define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_SHIFT (0U) +/*! TZ_USER - User access */ -#define DAC_CR2_BFEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFEN_SHIFT)) & DAC_CR2_BFEN_MASK) -#define DAC_CR2_OEN_MASK (0x2U) -#define DAC_CR2_OEN_SHIFT (1U) -/*! OEN - Optional Enable - * 0b0..Output buffer is not bypassed - * 0b1..Output buffer is bypassed +#define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_MASK) + +#define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_MASK (0x2U) +#define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_SHIFT (1U) +/*! TZ_NS - Non-secure access */ -#define DAC_CR2_OEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_OEN_SHIFT)) & DAC_CR2_OEN_MASK) -#define DAC_CR2_BFMS_MASK (0x4U) -#define DAC_CR2_BFMS_SHIFT (2U) -/*! BFMS - Buffer Middle Speed Select - * 0b0..Buffer middle speed not selected - * 0b1..Buffer middle speed selected +#define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_MASK) + +#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_MASK (0x10U) +#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_SHIFT (4U) +/*! LOCK_TZ - Lock truszone setting */ -#define DAC_CR2_BFMS(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFMS_SHIFT)) & DAC_CR2_BFMS_MASK) -#define DAC_CR2_BFHS_MASK (0x8U) -#define DAC_CR2_BFHS_SHIFT (3U) -/*! BFHS - Buffer High Speed Select - * 0b0..Buffer high speed not selected - * 0b1..Buffer high speed selected +#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_MASK) + +#define CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_MASK (0xF00U) +#define CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_SHIFT (8U) +/*! WHITE_LIST - White list */ -#define DAC_CR2_BFHS(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFHS_SHIFT)) & DAC_CR2_BFHS_MASK) -#define DAC_CR2_IREF2_MASK (0x10U) -#define DAC_CR2_IREF2_SHIFT (4U) -/*! IREF2 - Internal PTAT (Proportional To Absolute Temperature) Current Reference Select - * 0b0..Internal PTAT Current Reference not selected - * 0b1..Internal PTAT Current Reference selected +#define CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_MASK) + +#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_MASK (0x1000U) +#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock white list */ -#define DAC_CR2_IREF2(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF2_SHIFT)) & DAC_CR2_IREF2_MASK) -#define DAC_CR2_IREF1_MASK (0x20U) -#define DAC_CR2_IREF1_SHIFT (5U) -/*! IREF1 - Internal ZTC (Zero Temperature Coefficient) Current Reference Select - * 0b0..Internal ZTC Current Reference not selected - * 0b1..Internal ZTC Current Reference selected +#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_MASK) + +#define CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U) +#define CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by domain */ -#define DAC_CR2_IREF1(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF1_SHIFT)) & DAC_CR2_IREF1_MASK) -#define DAC_CR2_IREF_MASK (0x40U) -#define DAC_CR2_IREF_SHIFT (6U) -/*! IREF - Internal Current Reference Select - * 0b0..Internal Current Reference not selected - * 0b1..Internal Current Reference selected +#define CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_MASK) + +#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_MASK (0x100000U) +#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_SHIFT (20U) +/*! LOCK_MODE - Lock low power and access mode */ -#define DAC_CR2_IREF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF_SHIFT)) & DAC_CR2_IREF_MASK) +#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_MASK) +/*! @} */ + +/* The count of CCM_OBS_OBSERVE_AUTHEN_SET */ +#define CCM_OBS_OBSERVE_AUTHEN_SET_COUNT (6U) + +/*! @name OBSERVE_AUTHEN_CLR - Observe access control */ +/*! @{ */ + +#define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_MASK (0x1U) +#define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_SHIFT (0U) +/*! TZ_USER - User access + */ +#define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_MASK) + +#define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_MASK (0x2U) +#define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_SHIFT (1U) +/*! TZ_NS - Non-secure access + */ +#define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_MASK) + +#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_MASK (0x10U) +#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_SHIFT (4U) +/*! LOCK_TZ - Lock truszone setting + */ +#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_MASK) + +#define CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U) +#define CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_SHIFT (8U) +/*! WHITE_LIST - White list + */ +#define CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_MASK) + +#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U) +#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock white list + */ +#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_MASK) + +#define CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U) +#define CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by domain + */ +#define CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_MASK) + +#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U) +#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_SHIFT (20U) +/*! LOCK_MODE - Lock low power and access mode + */ +#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_MASK) +/*! @} */ + +/* The count of CCM_OBS_OBSERVE_AUTHEN_CLR */ +#define CCM_OBS_OBSERVE_AUTHEN_CLR_COUNT (6U) + +/*! @name OBSERVE_AUTHEN_TOG - Observe access control */ +/*! @{ */ + +#define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_MASK (0x1U) +#define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_SHIFT (0U) +/*! TZ_USER - User access + */ +#define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_MASK) + +#define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_MASK (0x2U) +#define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_SHIFT (1U) +/*! TZ_NS - Non-secure access + */ +#define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_MASK) + +#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_MASK (0x10U) +#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_SHIFT (4U) +/*! LOCK_TZ - Lock truszone setting + */ +#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_MASK) + +#define CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U) +#define CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_SHIFT (8U) +/*! WHITE_LIST - White list + */ +#define CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_MASK) + +#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U) +#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_SHIFT (12U) +/*! LOCK_LIST - Lock white list + */ +#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_MASK) + +#define CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U) +#define CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U) +/*! DOMAIN_MODE - Low power and access control by domain + */ +#define CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_MASK) + +#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U) +#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_SHIFT (20U) +/*! LOCK_MODE - Lock low power and access mode + */ +#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_MASK) +/*! @} */ + +/* The count of CCM_OBS_OBSERVE_AUTHEN_TOG */ +#define CCM_OBS_OBSERVE_AUTHEN_TOG_COUNT (6U) + +/*! @name OBSERVE_FREQUENCY_CURRENT - Current frequency detected */ +/*! @{ */ + +#define CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_MASK (0xFFFFFFFFU) +#define CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_SHIFT (0U) +/*! FREQUENCY - Frequency + */ +#define CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_SHIFT)) & CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_MASK) +/*! @} */ + +/* The count of CCM_OBS_OBSERVE_FREQUENCY_CURRENT */ +#define CCM_OBS_OBSERVE_FREQUENCY_CURRENT_COUNT (6U) + +/*! @name OBSERVE_FREQUENCY_MIN - Minimum frequency detected */ +/*! @{ */ + +#define CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_MASK (0xFFFFFFFFU) +#define CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_SHIFT (0U) +/*! FREQUENCY - Frequency + */ +#define CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_SHIFT)) & CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_MASK) /*! @} */ -/*! @name ITRM - Internal Current Reference Trim Register */ +/* The count of CCM_OBS_OBSERVE_FREQUENCY_MIN */ +#define CCM_OBS_OBSERVE_FREQUENCY_MIN_COUNT (6U) + +/*! @name OBSERVE_FREQUENCY_MAX - Maximum frequency detected */ /*! @{ */ -#define DAC_ITRM_TRIM_MASK (0x7U) -#define DAC_ITRM_TRIM_SHIFT (0U) -/*! TRIM - Internal Current Trim Register + +#define CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_MASK (0xFFFFFFFFU) +#define CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_SHIFT (0U) +/*! FREQUENCY - Frequency */ -#define DAC_ITRM_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DAC_ITRM_TRIM_SHIFT)) & DAC_ITRM_TRIM_MASK) +#define CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_SHIFT)) & CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_MASK) /*! @} */ +/* The count of CCM_OBS_OBSERVE_FREQUENCY_MAX */ +#define CCM_OBS_OBSERVE_FREQUENCY_MAX_COUNT (6U) + /*! * @} - */ /* end of group DAC_Register_Masks */ + */ /* end of group CCM_OBS_Register_Masks */ -/* DAC - Peripheral instance base addresses */ -/** Peripheral DAC base address */ -#define DAC_BASE (0x40064000u) -/** Peripheral DAC base pointer */ -#define DAC ((DAC_Type *)DAC_BASE) -/** Array initializer of DAC peripheral base addresses */ -#define DAC_BASE_ADDRS { DAC_BASE } -/** Array initializer of DAC peripheral base pointers */ -#define DAC_BASE_PTRS { DAC } -/** Interrupt vectors for the DAC peripheral type */ -#define DAC_IRQS { DAC_IRQn } +/* CCM_OBS - Peripheral instance base addresses */ +/** Peripheral CCM_OBS base address */ +#define CCM_OBS_BASE (0x40150000u) +/** Peripheral CCM_OBS base pointer */ +#define CCM_OBS ((CCM_OBS_Type *)CCM_OBS_BASE) +/** Array initializer of CCM_OBS peripheral base addresses */ +#define CCM_OBS_BASE_ADDRS { CCM_OBS_BASE } +/** Array initializer of CCM_OBS peripheral base pointers */ +#define CCM_OBS_BASE_PTRS { CCM_OBS } /*! * @} - */ /* end of group DAC_Peripheral_Access_Layer */ + */ /* end of group CCM_OBS_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- - -- DCDC Peripheral Access Layer + -- CDOG Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! - * @addtogroup DCDC_Peripheral_Access_Layer DCDC Peripheral Access Layer + * @addtogroup CDOG_Peripheral_Access_Layer CDOG Peripheral Access Layer * @{ */ -/** DCDC - Register Layout Typedef */ +/** CDOG - Register Layout Typedef */ typedef struct { - __IO uint32_t CTRL0; /**< DCDC Control Register 0, offset: 0x0 */ - __IO uint32_t CTRL1; /**< DCDC Control Register 1, offset: 0x4 */ - __IO uint32_t REG0; /**< DCDC Register 0, offset: 0x8 */ - __IO uint32_t REG1; /**< DCDC Register 1, offset: 0xC */ - __IO uint32_t REG2; /**< DCDC Register 2, offset: 0x10 */ - __IO uint32_t REG3; /**< DCDC Register 3, offset: 0x14 */ - __IO uint32_t REG4; /**< DCDC Register 4, offset: 0x18 */ - __IO uint32_t REG5; /**< DCDC Register 5, offset: 0x1C */ - __IO uint32_t REG6; /**< DCDC Register 6, offset: 0x20 */ - __IO uint32_t REG7; /**< DCDC Register 7, offset: 0x24 */ - __IO uint32_t REG7P; /**< DCDC Register 7 plus, offset: 0x28 */ - __IO uint32_t REG8; /**< DCDC Register 8, offset: 0x2C */ - __IO uint32_t REG9; /**< DCDC Register 9, offset: 0x30 */ - __IO uint32_t REG10; /**< DCDC Register 10, offset: 0x34 */ - __IO uint32_t REG11; /**< DCDC Register 11, offset: 0x38 */ - __IO uint32_t REG12; /**< DCDC Register 12, offset: 0x3C */ - __IO uint32_t REG13; /**< DCDC Register 13, offset: 0x40 */ - __IO uint32_t REG14; /**< DCDC Register 14, offset: 0x44 */ - __IO uint32_t REG15; /**< DCDC Register 15, offset: 0x48 */ - __IO uint32_t REG16; /**< DCDC Register 16, offset: 0x4C */ - __IO uint32_t REG17; /**< DCDC Register 17, offset: 0x50 */ - __IO uint32_t REG18; /**< DCDC Register 18, offset: 0x54 */ - __IO uint32_t REG19; /**< DCDC Register 19, offset: 0x58 */ - __IO uint32_t REG20; /**< DCDC Register 20, offset: 0x5C */ - __IO uint32_t REG21; /**< DCDC Register 21, offset: 0x60 */ - __IO uint32_t REG22; /**< DCDC Register 22, offset: 0x64 */ - __IO uint32_t REG23; /**< DCDC Register 23, offset: 0x68 */ - __IO uint32_t REG24; /**< DCDC Register 24, offset: 0x6C */ -} DCDC_Type; + __IO uint32_t CONTROL; /**< Control, offset: 0x0 */ + __IO uint32_t RELOAD; /**< Instruction Timer reload, offset: 0x4 */ + __IO uint32_t INSTRUCTION_TIMER; /**< Instruction Timer, offset: 0x8 */ + __O uint32_t SECURE_COUNTER; /**< Secure Counter, offset: 0xC */ + __I uint32_t STATUS; /**< Status 1, offset: 0x10 */ + __I uint32_t STATUS2; /**< Status 2, offset: 0x14 */ + __IO uint32_t FLAGS; /**< Flags, offset: 0x18 */ + __IO uint32_t PERSISTENT; /**< Persistent Data Storage, offset: 0x1C */ + __O uint32_t START; /**< START Command, offset: 0x20 */ + __O uint32_t STOP; /**< STOP Command, offset: 0x24 */ + __O uint32_t RESTART; /**< RESTART Command, offset: 0x28 */ + __O uint32_t ADD; /**< ADD Command, offset: 0x2C */ + __O uint32_t ADD1; /**< ADD1 Command, offset: 0x30 */ + __O uint32_t ADD16; /**< ADD16 Command, offset: 0x34 */ + __O uint32_t ADD256; /**< ADD256 Command, offset: 0x38 */ + __O uint32_t SUB; /**< SUB Command, offset: 0x3C */ + __O uint32_t SUB1; /**< SUB1 Command, offset: 0x40 */ + __O uint32_t SUB16; /**< SUB16 Command, offset: 0x44 */ + __O uint32_t SUB256; /**< SUB256 Command, offset: 0x48 */ +} CDOG_Type; /* ---------------------------------------------------------------------------- - -- DCDC Register Masks + -- CDOG Register Masks ---------------------------------------------------------------------------- */ /*! - * @addtogroup DCDC_Register_Masks DCDC Register Masks + * @addtogroup CDOG_Register_Masks CDOG Register Masks * @{ */ -/*! @name CTRL0 - DCDC Control Register 0 */ +/*! @name CONTROL - Control */ /*! @{ */ -#define DCDC_CTRL0_ENABLE_MASK (0x1U) -#define DCDC_CTRL0_ENABLE_SHIFT (0U) -#define DCDC_CTRL0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_SHIFT)) & DCDC_CTRL0_ENABLE_MASK) -#define DCDC_CTRL0_DIG_EN_MASK (0x2U) -#define DCDC_CTRL0_DIG_EN_SHIFT (1U) -/*! DIG_EN - * 0b0..Disable - * 0b1..Enable + +#define CDOG_CONTROL_LOCK_CTRL_MASK (0x3U) +#define CDOG_CONTROL_LOCK_CTRL_SHIFT (0U) +/*! LOCK_CTRL - Lock control + * 0b01..Locked + * 0b10..Unlocked */ -#define DCDC_CTRL0_DIG_EN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_DIG_EN_SHIFT)) & DCDC_CTRL0_DIG_EN_MASK) -#define DCDC_CTRL0_STBY_EN_MASK (0x4U) -#define DCDC_CTRL0_STBY_EN_SHIFT (2U) -#define DCDC_CTRL0_STBY_EN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_STBY_EN_SHIFT)) & DCDC_CTRL0_STBY_EN_MASK) -#define DCDC_CTRL0_LP_MODE_EN_MASK (0x8U) -#define DCDC_CTRL0_LP_MODE_EN_SHIFT (3U) -#define DCDC_CTRL0_LP_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_LP_MODE_EN_SHIFT)) & DCDC_CTRL0_LP_MODE_EN_MASK) -#define DCDC_CTRL0_STBY_LP_MODE_EN_MASK (0x10U) -#define DCDC_CTRL0_STBY_LP_MODE_EN_SHIFT (4U) -#define DCDC_CTRL0_STBY_LP_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_STBY_LP_MODE_EN_SHIFT)) & DCDC_CTRL0_STBY_LP_MODE_EN_MASK) -#define DCDC_CTRL0_ENABLE_DCDC_CNT_MASK (0x20U) -#define DCDC_CTRL0_ENABLE_DCDC_CNT_SHIFT (5U) -/*! ENABLE_DCDC_CNT - Enable internal count for DCDC_OK timeout - * 0b0..Wait DCDC_OK for ACK - * 0b1..Enable internal count for DCDC_OK timeout +#define CDOG_CONTROL_LOCK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_LOCK_CTRL_SHIFT)) & CDOG_CONTROL_LOCK_CTRL_MASK) + +#define CDOG_CONTROL_TIMEOUT_CTRL_MASK (0x1CU) +#define CDOG_CONTROL_TIMEOUT_CTRL_SHIFT (2U) +/*! TIMEOUT_CTRL - TIMEOUT fault control + * 0b100..Disable both reset and interrupt + * 0b001..Enable reset + * 0b010..Enable interrupt */ -#define DCDC_CTRL0_ENABLE_DCDC_CNT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_DCDC_CNT_SHIFT)) & DCDC_CTRL0_ENABLE_DCDC_CNT_MASK) -#define DCDC_CTRL0_TRIM_HOLD_MASK (0x40U) -#define DCDC_CTRL0_TRIM_HOLD_SHIFT (6U) -/*! TRIM_HOLD - Hold trim input - * 0b0..Sample trim input - * 0b1..Hold trim input +#define CDOG_CONTROL_TIMEOUT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_TIMEOUT_CTRL_SHIFT)) & CDOG_CONTROL_TIMEOUT_CTRL_MASK) + +#define CDOG_CONTROL_MISCOMPARE_CTRL_MASK (0xE0U) +#define CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT (5U) +/*! MISCOMPARE_CTRL - MISCOMPARE fault control + * 0b100..Disable both reset and interrupt + * 0b001..Enable reset + * 0b010..Enable interrupt */ -#define DCDC_CTRL0_TRIM_HOLD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_TRIM_HOLD_SHIFT)) & DCDC_CTRL0_TRIM_HOLD_MASK) -#define DCDC_CTRL0_CONTROL_MODE_MASK (0x80000000U) -#define DCDC_CTRL0_CONTROL_MODE_SHIFT (31U) -/*! CONTROL_MODE - Control mode - * 0b0..Static control - * 0b1..Controlled by GPC set points +#define CDOG_CONTROL_MISCOMPARE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT)) & CDOG_CONTROL_MISCOMPARE_CTRL_MASK) + +#define CDOG_CONTROL_SEQUENCE_CTRL_MASK (0x700U) +#define CDOG_CONTROL_SEQUENCE_CTRL_SHIFT (8U) +/*! SEQUENCE_CTRL - SEQUENCE fault control + * 0b001..Enable reset + * 0b010..Enable interrupt + * 0b100..Disable both reset and interrupt */ -#define DCDC_CTRL0_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_CONTROL_MODE_SHIFT)) & DCDC_CTRL0_CONTROL_MODE_MASK) +#define CDOG_CONTROL_SEQUENCE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_SEQUENCE_CTRL_SHIFT)) & CDOG_CONTROL_SEQUENCE_CTRL_MASK) + +#define CDOG_CONTROL_CONTROL_CTRL_MASK (0x3800U) +#define CDOG_CONTROL_CONTROL_CTRL_SHIFT (11U) +/*! CONTROL_CTRL - CONTROL fault control + * 0b001..Enable reset + * 0b100..Disable reset + */ +#define CDOG_CONTROL_CONTROL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_CONTROL_CTRL_SHIFT)) & CDOG_CONTROL_CONTROL_CTRL_MASK) + +#define CDOG_CONTROL_STATE_CTRL_MASK (0x1C000U) +#define CDOG_CONTROL_STATE_CTRL_SHIFT (14U) +/*! STATE_CTRL - STATE fault control + * 0b001..Enable reset + * 0b010..Enable interrupt + * 0b100..Disable both reset and interrupt + */ +#define CDOG_CONTROL_STATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_STATE_CTRL_SHIFT)) & CDOG_CONTROL_STATE_CTRL_MASK) + +#define CDOG_CONTROL_ADDRESS_CTRL_MASK (0xE0000U) +#define CDOG_CONTROL_ADDRESS_CTRL_SHIFT (17U) +/*! ADDRESS_CTRL - ADDRESS fault control + * 0b001..Enable reset + * 0b010..Enable interrupt + * 0b100..Disable both reset and interrupt + */ +#define CDOG_CONTROL_ADDRESS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_ADDRESS_CTRL_SHIFT)) & CDOG_CONTROL_ADDRESS_CTRL_MASK) + +#define CDOG_CONTROL_IRQ_PAUSE_MASK (0x30000000U) +#define CDOG_CONTROL_IRQ_PAUSE_SHIFT (28U) +/*! IRQ_PAUSE - IRQ pause control + * 0b01..Keep the timer running + * 0b10..Stop the timer + */ +#define CDOG_CONTROL_IRQ_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_IRQ_PAUSE_SHIFT)) & CDOG_CONTROL_IRQ_PAUSE_MASK) + +#define CDOG_CONTROL_DEBUG_HALT_CTRL_MASK (0xC0000000U) +#define CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT (30U) +/*! DEBUG_HALT_CTRL - DEBUG_HALT control + * 0b01..Keep the timer running + * 0b10..Stop the timer + */ +#define CDOG_CONTROL_DEBUG_HALT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT)) & CDOG_CONTROL_DEBUG_HALT_CTRL_MASK) /*! @} */ -/*! @name CTRL1 - DCDC Control Register 1 */ +/*! @name RELOAD - Instruction Timer reload */ /*! @{ */ -#define DCDC_CTRL1_VDD1P8CTRL_TRG_MASK (0x1FU) -#define DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT (0U) -#define DCDC_CTRL1_VDD1P8CTRL_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT)) & DCDC_CTRL1_VDD1P8CTRL_TRG_MASK) -#define DCDC_CTRL1_VDD1P0CTRL_TRG_MASK (0x1F00U) -#define DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT (8U) -#define DCDC_CTRL1_VDD1P0CTRL_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT)) & DCDC_CTRL1_VDD1P0CTRL_TRG_MASK) -#define DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK (0x1F0000U) -#define DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT (16U) -#define DCDC_CTRL1_VDD1P8CTRL_STBY_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT)) & DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK) -#define DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK (0x1F000000U) -#define DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT (24U) -#define DCDC_CTRL1_VDD1P0CTRL_STBY_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT)) & DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK) + +#define CDOG_RELOAD_RLOAD_MASK (0xFFFFFFFFU) +#define CDOG_RELOAD_RLOAD_SHIFT (0U) +/*! RLOAD - Instruction Timer reload value + */ +#define CDOG_RELOAD_RLOAD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RELOAD_RLOAD_SHIFT)) & CDOG_RELOAD_RLOAD_MASK) /*! @} */ -/*! @name REG0 - DCDC Register 0 */ +/*! @name INSTRUCTION_TIMER - Instruction Timer */ /*! @{ */ -#define DCDC_REG0_PWD_ZCD_MASK (0x1U) -#define DCDC_REG0_PWD_ZCD_SHIFT (0U) -/*! PWD_ZCD - Power Down Zero Cross Detection - * 0b0..Zero cross detetion function powered up - * 0b1..Zero cross detetion function powered down - */ -#define DCDC_REG0_PWD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK) -#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U) -#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U) -/*! DISABLE_AUTO_CLK_SWITCH - Disable Auto Clock Switch - * 0b0..If DISABLE_AUTO_CLK_SWITCH is set to 0 and 24M xtal is OK, the clock source will switch from internal ring OSC to 24M xtal automatically - * 0b1..If DISABLE_AUTO_CLK_SWITCH is set to 1, SEL_CLK will determine which clock source the DCDC uses + +#define CDOG_INSTRUCTION_TIMER_INSTIM_MASK (0xFFFFFFFFU) +#define CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT (0U) +/*! INSTIM - Current value of the Instruction Timer */ -#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK) -#define DCDC_REG0_SEL_CLK_MASK (0x4U) -#define DCDC_REG0_SEL_CLK_SHIFT (2U) -/*! SEL_CLK - Select Clock - * 0b0..DCDC uses internal ring oscillator - * 0b1..DCDC uses 24M xtal +#define CDOG_INSTRUCTION_TIMER_INSTIM(x) (((uint32_t)(((uint32_t)(x)) << CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT)) & CDOG_INSTRUCTION_TIMER_INSTIM_MASK) +/*! @} */ + +/*! @name SECURE_COUNTER - Secure Counter */ +/*! @{ */ + +#define CDOG_SECURE_COUNTER_SECCNT_MASK (0xFFFFFFFFU) +#define CDOG_SECURE_COUNTER_SECCNT_SHIFT (0U) +/*! SECCNT - Secure Counter */ -#define DCDC_REG0_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK) -#define DCDC_REG0_PWD_OSC_INT_MASK (0x8U) -#define DCDC_REG0_PWD_OSC_INT_SHIFT (3U) -/*! PWD_OSC_INT - Power down internal osc - * 0b0..Internal oscillator powered up - * 0b1..Internal oscillator powered down +#define CDOG_SECURE_COUNTER_SECCNT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SECURE_COUNTER_SECCNT_SHIFT)) & CDOG_SECURE_COUNTER_SECCNT_MASK) +/*! @} */ + +/*! @name STATUS - Status 1 */ +/*! @{ */ + +#define CDOG_STATUS_NUMTOF_MASK (0xFFU) +#define CDOG_STATUS_NUMTOF_SHIFT (0U) +/*! NUMTOF - Number of TIMEOUT faults since the last POR */ -#define DCDC_REG0_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK) -#define DCDC_REG0_PWD_CUR_SNS_CMP_MASK (0x10U) -#define DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT (4U) -/*! PWD_CUR_SNS_CMP - Power down signal of the current detector - * 0b0..Current Detector powered up - * 0b1..Current Detector powered down +#define CDOG_STATUS_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMTOF_SHIFT)) & CDOG_STATUS_NUMTOF_MASK) + +#define CDOG_STATUS_NUMMISCOMPF_MASK (0xFF00U) +#define CDOG_STATUS_NUMMISCOMPF_SHIFT (8U) +/*! NUMMISCOMPF - Number of MISCOMPARE faults since the last POR */ -#define DCDC_REG0_PWD_CUR_SNS_CMP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK) -#define DCDC_REG0_CUR_SNS_THRSH_MASK (0xE0U) -#define DCDC_REG0_CUR_SNS_THRSH_SHIFT (5U) -/*! CUR_SNS_THRSH - Current Sense (detector) Threshold +#define CDOG_STATUS_NUMMISCOMPF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMMISCOMPF_SHIFT)) & CDOG_STATUS_NUMMISCOMPF_MASK) + +#define CDOG_STATUS_NUMILSEQF_MASK (0xFF0000U) +#define CDOG_STATUS_NUMILSEQF_SHIFT (16U) +/*! NUMILSEQF - Number of SEQUENCE faults since the last POR */ -#define DCDC_REG0_CUR_SNS_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK) -#define DCDC_REG0_PWD_OVERCUR_DET_MASK (0x100U) -#define DCDC_REG0_PWD_OVERCUR_DET_SHIFT (8U) -/*! PWD_OVERCUR_DET - Power down overcurrent detection comparator - * 0b0..Overcurrent detection comparator is enabled - * 0b1..Overcurrent detection comparator is disabled +#define CDOG_STATUS_NUMILSEQF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMILSEQF_SHIFT)) & CDOG_STATUS_NUMILSEQF_MASK) + +#define CDOG_STATUS_CURST_MASK (0xF0000000U) +#define CDOG_STATUS_CURST_SHIFT (28U) +/*! CURST - Current State */ -#define DCDC_REG0_PWD_OVERCUR_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK) -#define DCDC_REG0_OVERCUR_TRIG_ADJ_MASK (0x600U) -#define DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT (9U) -/*! OVERCUR_TRIG_ADJ - Overcurrent Trigger Adjust - */ -#define DCDC_REG0_OVERCUR_TRIG_ADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT)) & DCDC_REG0_OVERCUR_TRIG_ADJ_MASK) -#define DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK (0x800U) -#define DCDC_REG0_PWD_CMP_DCDC_IN_DET_SHIFT (11U) -/*! PWD_CMP_DCDC_IN_DET - * 0b0..Low voltage detection comparator is enabled - * 0b1..Low voltage detection comparator is disabled - */ -#define DCDC_REG0_PWD_CMP_DCDC_IN_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_DCDC_IN_DET_SHIFT)) & DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK) -#define DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK (0x10000U) -#define DCDC_REG0_PWD_HIGH_VDD1P8_DET_SHIFT (16U) -/*! PWD_HIGH_VDD1P8_DET - Power Down High Voltage Detection for VDD1P8 - * 0b0..Overvoltage detection comparator for the VDD1P8 output is enabled - * 0b1..Overvoltage detection comparator for the VDD1P8 output is disabled - */ -#define DCDC_REG0_PWD_HIGH_VDD1P8_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VDD1P8_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK) -#define DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK (0x20000U) -#define DCDC_REG0_PWD_HIGH_VDD1P0_DET_SHIFT (17U) -/*! PWD_HIGH_VDD1P0_DET - Power Down High Voltage Detection for VDD1P0 - * 0b0..Overvoltage detection comparator for the VDD1P0 output is enabled - * 0b1..Overvoltage detection comparator for the VDD1P0 output is disabled - */ -#define DCDC_REG0_PWD_HIGH_VDD1P0_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VDD1P0_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK) -#define DCDC_REG0_LP_OVERLOAD_THRSH_MASK (0xC0000U) -#define DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT (18U) -/*! LP_OVERLOAD_THRSH - Low Power Overload Threshold - */ -#define DCDC_REG0_LP_OVERLOAD_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)) & DCDC_REG0_LP_OVERLOAD_THRSH_MASK) -#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK (0x100000U) -#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT (20U) -/*! LP_OVERLOAD_FREQ_SEL - Low Power Overload Frequency Select - */ -#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT)) & DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK) -#define DCDC_REG0_LP_HIGH_HYS_MASK (0x200000U) -#define DCDC_REG0_LP_HIGH_HYS_SHIFT (21U) -/*! LP_HIGH_HYS - Low Power High Hysteric Value - * 0b0..Adjust hysteretic value in low power to 12.5mV - * 0b1..Adjust hysteretic value in low power to 25mV - */ -#define DCDC_REG0_LP_HIGH_HYS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK) -#define DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U) -#define DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U) -/*! PWD_CMP_OFFSET - power down the out-of-range detection comparator - * 0b0..Out-of-range comparator powered up - * 0b1..Out-of-range comparator powered down - */ -#define DCDC_REG0_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK) -#define DCDC_REG0_XTALOK_DISABLE_MASK (0x8000000U) -#define DCDC_REG0_XTALOK_DISABLE_SHIFT (27U) -/*! XTALOK_DISABLE - Disable xtalok detection circuit - * 0b0..Enable xtalok detection circuit - * 0b1..Disable xtalok detection circuit and always outputs OK signal "1" - */ -#define DCDC_REG0_XTALOK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK) -#define DCDC_REG0_XTAL_24M_OK_MASK (0x20000000U) -#define DCDC_REG0_XTAL_24M_OK_SHIFT (29U) -/*! XTAL_24M_OK - 24M XTAL OK - * 0b0..DCDC uses internal ring OSC - * 0b1..DCDC uses xtal 24M - */ -#define DCDC_REG0_XTAL_24M_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK) -#define DCDC_REG0_STS_DC_OK_MASK (0x80000000U) -#define DCDC_REG0_STS_DC_OK_SHIFT (31U) -/*! STS_DC_OK - DCDC Output OK - * 0b0..DCDC is settling - * 0b1..DCDC already settled - */ -#define DCDC_REG0_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK) +#define CDOG_STATUS_CURST(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_CURST_SHIFT)) & CDOG_STATUS_CURST_MASK) /*! @} */ -/*! @name REG1 - DCDC Register 1 */ +/*! @name STATUS2 - Status 2 */ /*! @{ */ -#define DCDC_REG1_RLOAD_REG_EN_LPSR_MASK (0x10U) -#define DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT (4U) -#define DCDC_REG1_RLOAD_REG_EN_LPSR(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT)) & DCDC_REG1_RLOAD_REG_EN_LPSR_MASK) -#define DCDC_REG1_REG_RLOAD_SW_MASK (0x20U) -#define DCDC_REG1_REG_RLOAD_SW_SHIFT (5U) -/*! REG_RLOAD_SW - * 0b0..Load resistor disconnected - * 0b1..Load resistor connected - */ -#define DCDC_REG1_REG_RLOAD_SW(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_RLOAD_SW_SHIFT)) & DCDC_REG1_REG_RLOAD_SW_MASK) -#define DCDC_REG1_VBG_TRIM_MASK (0x7C0U) -#define DCDC_REG1_VBG_TRIM_SHIFT (6U) -#define DCDC_REG1_VBG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK) -#define DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x1800U) -#define DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (11U) -/*! LP_CMP_ISRC_SEL - Low Power Comparator Current Bias - * 0b00..50nA - * 0b01..100nA - * 0b10..200nA - * 0b11..400nA - */ -#define DCDC_REG1_LP_CMP_ISRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK) -#define DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK (0x8000000U) -#define DCDC_REG1_LOOPCTRL_CM_HST_THRESH_SHIFT (27U) -/*! LOOPCTRL_CM_HST_THRESH - Increase Threshold Detection - */ -#define DCDC_REG1_LOOPCTRL_CM_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_CM_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK) -#define DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK (0x10000000U) -#define DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT (28U) -/*! LOOPCTRL_DF_HST_THRESH - Increase Threshold Detection + +#define CDOG_STATUS2_NUMCNTF_MASK (0xFFU) +#define CDOG_STATUS2_NUMCNTF_SHIFT (0U) +/*! NUMCNTF - Number of CONTROL faults since the last POR */ -#define DCDC_REG1_LOOPCTRL_DF_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK) -#define DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK (0x20000000U) -#define DCDC_REG1_LOOPCTRL_EN_CM_HYST_SHIFT (29U) -/*! LOOPCTRL_EN_CM_HYST - * 0b0..Disable hysteresis in switching converter common mode analog comparators - * 0b1..Enable hysteresis in switching converter common mode analog comparators +#define CDOG_STATUS2_NUMCNTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMCNTF_SHIFT)) & CDOG_STATUS2_NUMCNTF_MASK) + +#define CDOG_STATUS2_NUMILLSTF_MASK (0xFF00U) +#define CDOG_STATUS2_NUMILLSTF_SHIFT (8U) +/*! NUMILLSTF - Number of STATE faults since the last POR */ -#define DCDC_REG1_LOOPCTRL_EN_CM_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_CM_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK) -#define DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK (0x40000000U) -#define DCDC_REG1_LOOPCTRL_EN_DF_HYST_SHIFT (30U) -/*! LOOPCTRL_EN_DF_HYST - * 0b0..Disable hysteresis in switching converter differential mode analog comparators - * 0b1..Enable hysteresis in switching converter differential mode analog comparators +#define CDOG_STATUS2_NUMILLSTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLSTF_SHIFT)) & CDOG_STATUS2_NUMILLSTF_MASK) + +#define CDOG_STATUS2_NUMILLA_MASK (0xFF0000U) +#define CDOG_STATUS2_NUMILLA_SHIFT (16U) +/*! NUMILLA - Number of ADDRESS faults since the last POR */ -#define DCDC_REG1_LOOPCTRL_EN_DF_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_DF_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK) +#define CDOG_STATUS2_NUMILLA(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLA_SHIFT)) & CDOG_STATUS2_NUMILLA_MASK) /*! @} */ -/*! @name REG2 - DCDC Register 2 */ +/*! @name FLAGS - Flags */ /*! @{ */ -#define DCDC_REG2_LOOPCTRL_DC_C_MASK (0x3U) -#define DCDC_REG2_LOOPCTRL_DC_C_SHIFT (0U) -#define DCDC_REG2_LOOPCTRL_DC_C(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK) -#define DCDC_REG2_LOOPCTRL_DC_R_MASK (0x3CU) -#define DCDC_REG2_LOOPCTRL_DC_R_SHIFT (2U) -#define DCDC_REG2_LOOPCTRL_DC_R(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK) -#define DCDC_REG2_LOOPCTRL_DC_FF_MASK (0x1C0U) -#define DCDC_REG2_LOOPCTRL_DC_FF_SHIFT (6U) -#define DCDC_REG2_LOOPCTRL_DC_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK) -#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK (0xE00U) -#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT (9U) -/*! LOOPCTRL_EN_RCSCALE - Enable RC Scale + +#define CDOG_FLAGS_TO_FLAG_MASK (0x1U) +#define CDOG_FLAGS_TO_FLAG_SHIFT (0U) +/*! TO_FLAG - TIMEOUT fault flag + * 0b0..A TIMEOUT fault has not occurred + * 0b1..A TIMEOUT fault has occurred */ -#define DCDC_REG2_LOOPCTRL_EN_RCSCALE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK) -#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK (0x1000U) -#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT (12U) -#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK) -#define DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK (0x2000U) -#define DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT (13U) -#define DCDC_REG2_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK) -#define DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK (0x8000U) -#define DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT (15U) -#define DCDC_REG2_BATTMONITOR_EN_BATADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT)) & DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK) -#define DCDC_REG2_BATTMONITOR_BATT_VAL_MASK (0x3FF0000U) -#define DCDC_REG2_BATTMONITOR_BATT_VAL_SHIFT (16U) -#define DCDC_REG2_BATTMONITOR_BATT_VAL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_BATTMONITOR_BATT_VAL_SHIFT)) & DCDC_REG2_BATTMONITOR_BATT_VAL_MASK) -#define DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U) -#define DCDC_REG2_DCM_SET_CTRL_SHIFT (28U) -/*! DCM_SET_CTRL - DCM Set Control +#define CDOG_FLAGS_TO_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_TO_FLAG_SHIFT)) & CDOG_FLAGS_TO_FLAG_MASK) + +#define CDOG_FLAGS_MISCOM_FLAG_MASK (0x2U) +#define CDOG_FLAGS_MISCOM_FLAG_SHIFT (1U) +/*! MISCOM_FLAG - MISCOMPARE fault flag + * 0b0..A MISCOMPARE fault has not occurred + * 0b1..A MISCOMPARE fault has occurred */ -#define DCDC_REG2_DCM_SET_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK) -#define DCDC_REG2_LOOPCTRL_TOGGLE_DIF_MASK (0x40000000U) -#define DCDC_REG2_LOOPCTRL_TOGGLE_DIF_SHIFT (30U) -#define DCDC_REG2_LOOPCTRL_TOGGLE_DIF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_TOGGLE_DIF_SHIFT)) & DCDC_REG2_LOOPCTRL_TOGGLE_DIF_MASK) -/*! @} */ +#define CDOG_FLAGS_MISCOM_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_MISCOM_FLAG_SHIFT)) & CDOG_FLAGS_MISCOM_FLAG_MASK) -/*! @name REG3 - DCDC Register 3 */ -/*! @{ */ -#define DCDC_REG3_VDD1P0CTRL_ADJTN_MASK (0x3C00U) -#define DCDC_REG3_VDD1P0CTRL_ADJTN_SHIFT (10U) -#define DCDC_REG3_VDD1P0CTRL_ADJTN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_VDD1P0CTRL_ADJTN_SHIFT)) & DCDC_REG3_VDD1P0CTRL_ADJTN_MASK) -#define DCDC_REG3_IN_BROWNOUT_MASK (0x4000U) -#define DCDC_REG3_IN_BROWNOUT_SHIFT (14U) -#define DCDC_REG3_IN_BROWNOUT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_IN_BROWNOUT_SHIFT)) & DCDC_REG3_IN_BROWNOUT_MASK) -#define DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_MASK (0x8000U) -#define DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_SHIFT (15U) -#define DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_SHIFT)) & DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_MASK) -#define DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_MASK (0x10000U) -#define DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_SHIFT (16U) -#define DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_SHIFT)) & DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_MASK) -#define DCDC_REG3_OVERCUR_DETECT_OUT_MASK (0x20000U) -#define DCDC_REG3_OVERCUR_DETECT_OUT_SHIFT (17U) -#define DCDC_REG3_OVERCUR_DETECT_OUT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERCUR_DETECT_OUT_SHIFT)) & DCDC_REG3_OVERCUR_DETECT_OUT_MASK) -#define DCDC_REG3_ENABLE_FF_MASK (0x40000U) -#define DCDC_REG3_ENABLE_FF_SHIFT (18U) -#define DCDC_REG3_ENABLE_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_ENABLE_FF_SHIFT)) & DCDC_REG3_ENABLE_FF_MASK) -#define DCDC_REG3_DISABLE_PULSE_SKIP_MASK (0x80000U) -#define DCDC_REG3_DISABLE_PULSE_SKIP_SHIFT (19U) -/*! DISABLE_PULSE_SKIP - Disable Pulse Skip +#define CDOG_FLAGS_SEQ_FLAG_MASK (0x4U) +#define CDOG_FLAGS_SEQ_FLAG_SHIFT (2U) +/*! SEQ_FLAG - SEQUENCE fault flag + * 0b0..A SEQUENCE fault has not occurred + * 0b1..A SEQUENCE fault has occurred */ -#define DCDC_REG3_DISABLE_PULSE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG3_DISABLE_PULSE_SKIP_MASK) -#define DCDC_REG3_DISABLE_IDLE_SKIP_MASK (0x100000U) -#define DCDC_REG3_DISABLE_IDLE_SKIP_SHIFT (20U) -#define DCDC_REG3_DISABLE_IDLE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_IDLE_SKIP_SHIFT)) & DCDC_REG3_DISABLE_IDLE_SKIP_MASK) -#define DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_MASK (0x200000U) -#define DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_SHIFT (21U) -#define DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_SHIFT)) & DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_MASK) -#define DCDC_REG3_REG_FBK_SEL_MASK (0xC00000U) -#define DCDC_REG3_REG_FBK_SEL_SHIFT (22U) -#define DCDC_REG3_REG_FBK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_REG_FBK_SEL_SHIFT)) & DCDC_REG3_REG_FBK_SEL_MASK) -#define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) -#define DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT (24U) -/*! MINPWR_DC_HALFCLK - * 0b0..DCDC clock remains at full frequency for continuous mode - * 0b1..DCDC clock set to half frequency for continuous mode +#define CDOG_FLAGS_SEQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_SEQ_FLAG_SHIFT)) & CDOG_FLAGS_SEQ_FLAG_MASK) + +#define CDOG_FLAGS_CNT_FLAG_MASK (0x8U) +#define CDOG_FLAGS_CNT_FLAG_SHIFT (3U) +/*! CNT_FLAG - CONTROL fault flag + * 0b0..A CONTROL fault has not occurred + * 0b1..A CONTROL fault has occurred */ -#define DCDC_REG3_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK) -#define DCDC_REG3_MINPWR_HALF_FETS_MASK (0x4000000U) -#define DCDC_REG3_MINPWR_HALF_FETS_SHIFT (26U) -#define DCDC_REG3_MINPWR_HALF_FETS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_HALF_FETS_SHIFT)) & DCDC_REG3_MINPWR_HALF_FETS_MASK) -#define DCDC_REG3_MISC_DELAY_TIMING_MASK (0x8000000U) -#define DCDC_REG3_MISC_DELAY_TIMING_SHIFT (27U) -/*! MISC_DELAY_TIMING - Miscellaneous Delay Timing +#define CDOG_FLAGS_CNT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_CNT_FLAG_SHIFT)) & CDOG_FLAGS_CNT_FLAG_MASK) + +#define CDOG_FLAGS_STATE_FLAG_MASK (0x10U) +#define CDOG_FLAGS_STATE_FLAG_SHIFT (4U) +/*! STATE_FLAG - STATE fault flag + * 0b0..A STATE fault has not occurred + * 0b1..A STATE fault has occurred */ -#define DCDC_REG3_MISC_DELAY_TIMING(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK) -#define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK (0x20000000U) -#define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT (29U) -/*! VDD1P0CTRL_DISABLE_STEP - Disable Step for VDD1P0 - * 0b0..Enable stepping for VDD1P0 - * 0b1..Disable stepping for VDD1P0 +#define CDOG_FLAGS_STATE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_STATE_FLAG_SHIFT)) & CDOG_FLAGS_STATE_FLAG_MASK) + +#define CDOG_FLAGS_ADDR_FLAG_MASK (0x20U) +#define CDOG_FLAGS_ADDR_FLAG_SHIFT (5U) +/*! ADDR_FLAG - ADDRESS fault flag + * 0b0..An ADDRESS fault has not occurred + * 0b1..An ADDRESS fault has occurred */ -#define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK) -#define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK (0x40000000U) -#define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_SHIFT (30U) -/*! VDD1P8CTRL_DISABLE_STEP - Disable Step for VDD1P8 - * 0b0..Enable stepping for VDD1P8 - * 0b1..Disable stepping for VDD1P8 +#define CDOG_FLAGS_ADDR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_ADDR_FLAG_SHIFT)) & CDOG_FLAGS_ADDR_FLAG_MASK) + +#define CDOG_FLAGS_POR_FLAG_MASK (0x10000U) +#define CDOG_FLAGS_POR_FLAG_SHIFT (16U) +/*! POR_FLAG - Power-on reset flag + * 0b0..A Power-on reset event has not occurred + * 0b1..A Power-on reset event has occurred */ -#define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK) +#define CDOG_FLAGS_POR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_POR_FLAG_SHIFT)) & CDOG_FLAGS_POR_FLAG_MASK) /*! @} */ -/*! @name REG4 - DCDC Register 4 */ +/*! @name PERSISTENT - Persistent Data Storage */ /*! @{ */ -#define DCDC_REG4_ENABLE_SP_MASK (0xFFFFU) -#define DCDC_REG4_ENABLE_SP_SHIFT (0U) -#define DCDC_REG4_ENABLE_SP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG4_ENABLE_SP_SHIFT)) & DCDC_REG4_ENABLE_SP_MASK) -/*! @} */ -/*! @name REG5 - DCDC Register 5 */ -/*! @{ */ -#define DCDC_REG5_DIG_EN_SP_MASK (0xFFFFU) -#define DCDC_REG5_DIG_EN_SP_SHIFT (0U) -#define DCDC_REG5_DIG_EN_SP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG5_DIG_EN_SP_SHIFT)) & DCDC_REG5_DIG_EN_SP_MASK) +#define CDOG_PERSISTENT_PERSIS_MASK (0xFFFFFFFFU) +#define CDOG_PERSISTENT_PERSIS_SHIFT (0U) +/*! PERSIS - Persistent Storage + */ +#define CDOG_PERSISTENT_PERSIS(x) (((uint32_t)(((uint32_t)(x)) << CDOG_PERSISTENT_PERSIS_SHIFT)) & CDOG_PERSISTENT_PERSIS_MASK) /*! @} */ -/*! @name REG6 - DCDC Register 6 */ +/*! @name START - START Command */ /*! @{ */ -#define DCDC_REG6_LP_MODE_SP_MASK (0xFFFFU) -#define DCDC_REG6_LP_MODE_SP_SHIFT (0U) -#define DCDC_REG6_LP_MODE_SP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG6_LP_MODE_SP_SHIFT)) & DCDC_REG6_LP_MODE_SP_MASK) -/*! @} */ -/*! @name REG7 - DCDC Register 7 */ -/*! @{ */ -#define DCDC_REG7_STBY_EN_SP_MASK (0xFFFFU) -#define DCDC_REG7_STBY_EN_SP_SHIFT (0U) -#define DCDC_REG7_STBY_EN_SP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG7_STBY_EN_SP_SHIFT)) & DCDC_REG7_STBY_EN_SP_MASK) +#define CDOG_START_STRT_MASK (0xFFFFFFFFU) +#define CDOG_START_STRT_SHIFT (0U) +/*! STRT - Start command + */ +#define CDOG_START_STRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_START_STRT_SHIFT)) & CDOG_START_STRT_MASK) /*! @} */ -/*! @name REG7P - DCDC Register 7 plus */ +/*! @name STOP - STOP Command */ /*! @{ */ -#define DCDC_REG7P_STBY_LP_MODE_SP_MASK (0xFFFFU) -#define DCDC_REG7P_STBY_LP_MODE_SP_SHIFT (0U) -#define DCDC_REG7P_STBY_LP_MODE_SP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG7P_STBY_LP_MODE_SP_SHIFT)) & DCDC_REG7P_STBY_LP_MODE_SP_MASK) -/*! @} */ -/*! @name REG8 - DCDC Register 8 */ -/*! @{ */ -#define DCDC_REG8_ANA_TRG_SP0_MASK (0xFFFFFFFFU) -#define DCDC_REG8_ANA_TRG_SP0_SHIFT (0U) -#define DCDC_REG8_ANA_TRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG8_ANA_TRG_SP0_SHIFT)) & DCDC_REG8_ANA_TRG_SP0_MASK) +#define CDOG_STOP_STP_MASK (0xFFFFFFFFU) +#define CDOG_STOP_STP_SHIFT (0U) +/*! STP - Stop command + */ +#define CDOG_STOP_STP(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STOP_STP_SHIFT)) & CDOG_STOP_STP_MASK) /*! @} */ -/*! @name REG9 - DCDC Register 9 */ +/*! @name RESTART - RESTART Command */ /*! @{ */ -#define DCDC_REG9_ANA_TRG_SP1_MASK (0xFFFFFFFFU) -#define DCDC_REG9_ANA_TRG_SP1_SHIFT (0U) -#define DCDC_REG9_ANA_TRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG9_ANA_TRG_SP1_SHIFT)) & DCDC_REG9_ANA_TRG_SP1_MASK) -/*! @} */ -/*! @name REG10 - DCDC Register 10 */ -/*! @{ */ -#define DCDC_REG10_ANA_TRG_SP2_MASK (0xFFFFFFFFU) -#define DCDC_REG10_ANA_TRG_SP2_SHIFT (0U) -#define DCDC_REG10_ANA_TRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG10_ANA_TRG_SP2_SHIFT)) & DCDC_REG10_ANA_TRG_SP2_MASK) +#define CDOG_RESTART_RSTRT_MASK (0xFFFFFFFFU) +#define CDOG_RESTART_RSTRT_SHIFT (0U) +/*! RSTRT - Restart command + */ +#define CDOG_RESTART_RSTRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RESTART_RSTRT_SHIFT)) & CDOG_RESTART_RSTRT_MASK) /*! @} */ -/*! @name REG11 - DCDC Register 11 */ +/*! @name ADD - ADD Command */ /*! @{ */ -#define DCDC_REG11_ANA_TRG_SP3_MASK (0xFFFFFFFFU) -#define DCDC_REG11_ANA_TRG_SP3_SHIFT (0U) -#define DCDC_REG11_ANA_TRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG11_ANA_TRG_SP3_SHIFT)) & DCDC_REG11_ANA_TRG_SP3_MASK) -/*! @} */ -/*! @name REG12 - DCDC Register 12 */ -/*! @{ */ -#define DCDC_REG12_DIG_TRG_SP0_MASK (0xFFFFFFFFU) -#define DCDC_REG12_DIG_TRG_SP0_SHIFT (0U) -#define DCDC_REG12_DIG_TRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG12_DIG_TRG_SP0_SHIFT)) & DCDC_REG12_DIG_TRG_SP0_MASK) +#define CDOG_ADD_AD_MASK (0xFFFFFFFFU) +#define CDOG_ADD_AD_SHIFT (0U) +/*! AD - ADD Write Value + */ +#define CDOG_ADD_AD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD_AD_SHIFT)) & CDOG_ADD_AD_MASK) /*! @} */ -/*! @name REG13 - DCDC Register 13 */ +/*! @name ADD1 - ADD1 Command */ /*! @{ */ -#define DCDC_REG13_DIG_TRG_SP1_MASK (0xFFFFFFFFU) -#define DCDC_REG13_DIG_TRG_SP1_SHIFT (0U) -#define DCDC_REG13_DIG_TRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG13_DIG_TRG_SP1_SHIFT)) & DCDC_REG13_DIG_TRG_SP1_MASK) -/*! @} */ -/*! @name REG14 - DCDC Register 14 */ -/*! @{ */ -#define DCDC_REG14_DIG_TRG_SP2_MASK (0xFFFFFFFFU) -#define DCDC_REG14_DIG_TRG_SP2_SHIFT (0U) -#define DCDC_REG14_DIG_TRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG14_DIG_TRG_SP2_SHIFT)) & DCDC_REG14_DIG_TRG_SP2_MASK) +#define CDOG_ADD1_AD1_MASK (0xFFFFFFFFU) +#define CDOG_ADD1_AD1_SHIFT (0U) +/*! AD1 - ADD 1 + */ +#define CDOG_ADD1_AD1(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD1_AD1_SHIFT)) & CDOG_ADD1_AD1_MASK) /*! @} */ -/*! @name REG15 - DCDC Register 15 */ +/*! @name ADD16 - ADD16 Command */ /*! @{ */ -#define DCDC_REG15_DIG_TRG_SP3_MASK (0xFFFFFFFFU) -#define DCDC_REG15_DIG_TRG_SP3_SHIFT (0U) -#define DCDC_REG15_DIG_TRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG15_DIG_TRG_SP3_SHIFT)) & DCDC_REG15_DIG_TRG_SP3_MASK) -/*! @} */ -/*! @name REG16 - DCDC Register 16 */ -/*! @{ */ -#define DCDC_REG16_ANA_STBY_TRG_SP0_MASK (0xFFFFFFFFU) -#define DCDC_REG16_ANA_STBY_TRG_SP0_SHIFT (0U) -#define DCDC_REG16_ANA_STBY_TRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG16_ANA_STBY_TRG_SP0_SHIFT)) & DCDC_REG16_ANA_STBY_TRG_SP0_MASK) +#define CDOG_ADD16_AD16_MASK (0xFFFFFFFFU) +#define CDOG_ADD16_AD16_SHIFT (0U) +/*! AD16 - ADD 16 + */ +#define CDOG_ADD16_AD16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD16_AD16_SHIFT)) & CDOG_ADD16_AD16_MASK) /*! @} */ -/*! @name REG17 - DCDC Register 17 */ +/*! @name ADD256 - ADD256 Command */ /*! @{ */ -#define DCDC_REG17_ANA_STBY_TRG_SP1_MASK (0xFFFFFFFFU) -#define DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT (0U) -#define DCDC_REG17_ANA_STBY_TRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT)) & DCDC_REG17_ANA_STBY_TRG_SP1_MASK) -/*! @} */ -/*! @name REG18 - DCDC Register 18 */ -/*! @{ */ -#define DCDC_REG18_ANA_STBY_TRG_SP2_MASK (0xFFFFFFFFU) -#define DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT (0U) -#define DCDC_REG18_ANA_STBY_TRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT)) & DCDC_REG18_ANA_STBY_TRG_SP2_MASK) +#define CDOG_ADD256_AD256_MASK (0xFFFFFFFFU) +#define CDOG_ADD256_AD256_SHIFT (0U) +/*! AD256 - ADD 256 + */ +#define CDOG_ADD256_AD256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD256_AD256_SHIFT)) & CDOG_ADD256_AD256_MASK) /*! @} */ -/*! @name REG19 - DCDC Register 19 */ +/*! @name SUB - SUB Command */ /*! @{ */ -#define DCDC_REG19_ANA_STBY_TRG_SP3_MASK (0xFFFFFFFFU) -#define DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT (0U) -#define DCDC_REG19_ANA_STBY_TRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT)) & DCDC_REG19_ANA_STBY_TRG_SP3_MASK) -/*! @} */ -/*! @name REG20 - DCDC Register 20 */ -/*! @{ */ -#define DCDC_REG20_DIG_STBY_TRG_SP0_MASK (0xFFFFFFFFU) -#define DCDC_REG20_DIG_STBY_TRG_SP0_SHIFT (0U) -#define DCDC_REG20_DIG_STBY_TRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG20_DIG_STBY_TRG_SP0_SHIFT)) & DCDC_REG20_DIG_STBY_TRG_SP0_MASK) +#define CDOG_SUB_S0B_MASK (0xFFFFFFFFU) +#define CDOG_SUB_S0B_SHIFT (0U) +/*! S0B - Subtract Write Value + */ +#define CDOG_SUB_S0B(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK) /*! @} */ -/*! @name REG21 - DCDC Register 21 */ +/*! @name SUB1 - SUB1 Command */ /*! @{ */ -#define DCDC_REG21_DIG_STBY_TRG_SP1_MASK (0xFFFFFFFFU) -#define DCDC_REG21_DIG_STBY_TRG_SP1_SHIFT (0U) -#define DCDC_REG21_DIG_STBY_TRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG21_DIG_STBY_TRG_SP1_SHIFT)) & DCDC_REG21_DIG_STBY_TRG_SP1_MASK) -/*! @} */ -/*! @name REG22 - DCDC Register 22 */ -/*! @{ */ -#define DCDC_REG22_DIG_STBY_TRG_SP2_MASK (0xFFFFFFFFU) -#define DCDC_REG22_DIG_STBY_TRG_SP2_SHIFT (0U) -#define DCDC_REG22_DIG_STBY_TRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG22_DIG_STBY_TRG_SP2_SHIFT)) & DCDC_REG22_DIG_STBY_TRG_SP2_MASK) +#define CDOG_SUB1_S1B_MASK (0xFFFFFFFFU) +#define CDOG_SUB1_S1B_SHIFT (0U) +/*! S1B - Subtract 1 + */ +#define CDOG_SUB1_S1B(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB1_S1B_SHIFT)) & CDOG_SUB1_S1B_MASK) /*! @} */ -/*! @name REG23 - DCDC Register 23 */ +/*! @name SUB16 - SUB16 Command */ /*! @{ */ -#define DCDC_REG23_DIG_STBY_TRG_SP3_MASK (0xFFFFFFFFU) -#define DCDC_REG23_DIG_STBY_TRG_SP3_SHIFT (0U) -#define DCDC_REG23_DIG_STBY_TRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG23_DIG_STBY_TRG_SP3_SHIFT)) & DCDC_REG23_DIG_STBY_TRG_SP3_MASK) + +#define CDOG_SUB16_SB16_MASK (0xFFFFFFFFU) +#define CDOG_SUB16_SB16_SHIFT (0U) +/*! SB16 - Subtract 16 + */ +#define CDOG_SUB16_SB16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB16_SB16_SHIFT)) & CDOG_SUB16_SB16_MASK) /*! @} */ -/*! @name REG24 - DCDC Register 24 */ +/*! @name SUB256 - SUB256 Command */ /*! @{ */ -#define DCDC_REG24_OK_COUNT_MASK (0xFFFFFFFFU) -#define DCDC_REG24_OK_COUNT_SHIFT (0U) -#define DCDC_REG24_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG24_OK_COUNT_SHIFT)) & DCDC_REG24_OK_COUNT_MASK) + +#define CDOG_SUB256_SB256_MASK (0xFFFFFFFFU) +#define CDOG_SUB256_SB256_SHIFT (0U) +/*! SB256 - Subtract 256 + */ +#define CDOG_SUB256_SB256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB256_SB256_SHIFT)) & CDOG_SUB256_SB256_MASK) /*! @} */ /*! * @} - */ /* end of group DCDC_Register_Masks */ + */ /* end of group CDOG_Register_Masks */ -/* DCDC - Peripheral instance base addresses */ -/** Peripheral DCDC base address */ -#define DCDC_BASE (0x40CA8000u) -/** Peripheral DCDC base pointer */ -#define DCDC ((DCDC_Type *)DCDC_BASE) -/** Array initializer of DCDC peripheral base addresses */ -#define DCDC_BASE_ADDRS { DCDC_BASE } -/** Array initializer of DCDC peripheral base pointers */ -#define DCDC_BASE_PTRS { DCDC } +/* CDOG - Peripheral instance base addresses */ +/** Peripheral CDOG base address */ +#define CDOG_BASE (0x41900000u) +/** Peripheral CDOG base pointer */ +#define CDOG ((CDOG_Type *)CDOG_BASE) +/** Array initializer of CDOG peripheral base addresses */ +#define CDOG_BASE_ADDRS { CDOG_BASE } +/** Array initializer of CDOG peripheral base pointers */ +#define CDOG_BASE_PTRS { CDOG } /*! * @} - */ /* end of group DCDC_Peripheral_Access_Layer */ + */ /* end of group CDOG_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- - -- DMA Peripheral Access Layer + -- CMP Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! - * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer * @{ */ -/** DMA - Register Layout Typedef */ +/** CMP - Register Layout Typedef */ typedef struct { - __IO uint32_t CR; /**< Control, offset: 0x0 */ - __I uint32_t ES; /**< Error Status, offset: 0x4 */ - uint8_t RESERVED_0[4]; - __IO uint32_t ERQ; /**< Enable Request, offset: 0xC */ - uint8_t RESERVED_1[4]; - __IO uint32_t EEI; /**< Enable Error Interrupt, offset: 0x14 */ - __O uint8_t CEEI; /**< Clear Enable Error Interrupt, offset: 0x18 */ - __O uint8_t SEEI; /**< Set Enable Error Interrupt, offset: 0x19 */ - __O uint8_t CERQ; /**< Clear Enable Request, offset: 0x1A */ - __O uint8_t SERQ; /**< Set Enable Request, offset: 0x1B */ - __O uint8_t CDNE; /**< Clear DONE Status Bit, offset: 0x1C */ - __O uint8_t SSRT; /**< Set START Bit, offset: 0x1D */ - __O uint8_t CERR; /**< Clear Error, offset: 0x1E */ - __O uint8_t CINT; /**< Clear Interrupt Request, offset: 0x1F */ - uint8_t RESERVED_2[4]; - __IO uint32_t INT; /**< Interrupt Request, offset: 0x24 */ - uint8_t RESERVED_3[4]; - __IO uint32_t ERR; /**< Error, offset: 0x2C */ - uint8_t RESERVED_4[4]; - __I uint32_t HRS; /**< Hardware Request Status, offset: 0x34 */ - uint8_t RESERVED_5[12]; - __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop, offset: 0x44 */ - uint8_t RESERVED_6[184]; - __IO uint8_t DCHPRI3; /**< Channel Priority, offset: 0x100 */ - __IO uint8_t DCHPRI2; /**< Channel Priority, offset: 0x101 */ - __IO uint8_t DCHPRI1; /**< Channel Priority, offset: 0x102 */ - __IO uint8_t DCHPRI0; /**< Channel Priority, offset: 0x103 */ - __IO uint8_t DCHPRI7; /**< Channel Priority, offset: 0x104 */ - __IO uint8_t DCHPRI6; /**< Channel Priority, offset: 0x105 */ - __IO uint8_t DCHPRI5; /**< Channel Priority, offset: 0x106 */ - __IO uint8_t DCHPRI4; /**< Channel Priority, offset: 0x107 */ - __IO uint8_t DCHPRI11; /**< Channel Priority, offset: 0x108 */ - __IO uint8_t DCHPRI10; /**< Channel Priority, offset: 0x109 */ - __IO uint8_t DCHPRI9; /**< Channel Priority, offset: 0x10A */ - __IO uint8_t DCHPRI8; /**< Channel Priority, offset: 0x10B */ - __IO uint8_t DCHPRI15; /**< Channel Priority, offset: 0x10C */ - __IO uint8_t DCHPRI14; /**< Channel Priority, offset: 0x10D */ - __IO uint8_t DCHPRI13; /**< Channel Priority, offset: 0x10E */ - __IO uint8_t DCHPRI12; /**< Channel Priority, offset: 0x10F */ - __IO uint8_t DCHPRI19; /**< Channel Priority, offset: 0x110 */ - __IO uint8_t DCHPRI18; /**< Channel Priority, offset: 0x111 */ - __IO uint8_t DCHPRI17; /**< Channel Priority, offset: 0x112 */ - __IO uint8_t DCHPRI16; /**< Channel Priority, offset: 0x113 */ - __IO uint8_t DCHPRI23; /**< Channel Priority, offset: 0x114 */ - __IO uint8_t DCHPRI22; /**< Channel Priority, offset: 0x115 */ - __IO uint8_t DCHPRI21; /**< Channel Priority, offset: 0x116 */ - __IO uint8_t DCHPRI20; /**< Channel Priority, offset: 0x117 */ - __IO uint8_t DCHPRI27; /**< Channel Priority, offset: 0x118 */ - __IO uint8_t DCHPRI26; /**< Channel Priority, offset: 0x119 */ - __IO uint8_t DCHPRI25; /**< Channel Priority, offset: 0x11A */ - __IO uint8_t DCHPRI24; /**< Channel Priority, offset: 0x11B */ - __IO uint8_t DCHPRI31; /**< Channel Priority, offset: 0x11C */ - __IO uint8_t DCHPRI30; /**< Channel Priority, offset: 0x11D */ - __IO uint8_t DCHPRI29; /**< Channel Priority, offset: 0x11E */ - __IO uint8_t DCHPRI28; /**< Channel Priority, offset: 0x11F */ - uint8_t RESERVED_7[3808]; - struct { /* offset: 0x1000, array step: 0x20 */ - __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ - __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ - __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */ - union { /* offset: 0x1008, array step: 0x20 */ - __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */ - __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */ - __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */ - }; - __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */ - __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */ - __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */ - union { /* offset: 0x1016, array step: 0x20 */ - __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */ - __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */ - }; - __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */ - __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */ - union { /* offset: 0x101E, array step: 0x20 */ - __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ - __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ - }; - } TCD[32]; -} DMA_Type; + __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __IO uint32_t C0; /**< CMP Control Register 0, offset: 0x8 */ + __IO uint32_t C1; /**< CMP Control Register 1, offset: 0xC */ + __IO uint32_t C2; /**< CMP Control Register 2, offset: 0x10 */ + __IO uint32_t C3; /**< CMP Control Register 3, offset: 0x14 */ +} CMP_Type; /* ---------------------------------------------------------------------------- - -- DMA Register Masks + -- CMP Register Masks ---------------------------------------------------------------------------- */ /*! - * @addtogroup DMA_Register_Masks DMA Register Masks + * @addtogroup CMP_Register_Masks CMP Register Masks * @{ */ -/*! @name CR - Control */ +/*! @name VERID - Version ID Register */ /*! @{ */ -#define DMA_CR_EDBG_MASK (0x2U) -#define DMA_CR_EDBG_SHIFT (1U) -/*! EDBG - Enable Debug - * 0b0..When the chip is in Debug mode, the eDMA continues to operate. - * 0b1..Entry of the chip into Debug mode is effective + +#define CMP_VERID_FEATURE_MASK (0xFFFFU) +#define CMP_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Specification Number. This read only filed returns the feature set number. */ -#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) -#define DMA_CR_ERCA_MASK (0x4U) -#define DMA_CR_ERCA_SHIFT (2U) -/*! ERCA - Enable Round Robin Channel Arbitration - * 0b0..Fixed priority arbitration within each group - * 0b1..Round robin arbitration within each group +#define CMP_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_FEATURE_SHIFT)) & CMP_VERID_FEATURE_MASK) + +#define CMP_VERID_MINOR_MASK (0xFF0000U) +#define CMP_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor Version Number. This read only field returns the minor version number for the module specification. */ -#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) -#define DMA_CR_ERGA_MASK (0x8U) -#define DMA_CR_ERGA_SHIFT (3U) -/*! ERGA - Enable Round Robin Group Arbitration - * 0b0..Fixed priority arbitration - * 0b1..Round robin arbitration +#define CMP_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MINOR_SHIFT)) & CMP_VERID_MINOR_MASK) + +#define CMP_VERID_MAJOR_MASK (0xFF000000U) +#define CMP_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major Version Number. This read only field returns the major version number for the module specification. */ -#define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK) -#define DMA_CR_HOE_MASK (0x10U) -#define DMA_CR_HOE_SHIFT (4U) -/*! HOE - Halt On Error - * 0b0..Normal operation - * 0b1..Error causes HALT field to be automatically set to 1 +#define CMP_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MAJOR_SHIFT)) & CMP_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ + +#define CMP_PARAM_PARAM_MASK (0xFFFFFFFFU) +#define CMP_PARAM_PARAM_SHIFT (0U) +/*! PARAM - Parameter Registers. This read only filed returns the feature parameters implemented along with the Version ID register. */ -#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK) -#define DMA_CR_HALT_MASK (0x20U) -#define DMA_CR_HALT_SHIFT (5U) -/*! HALT - Halt eDMA Operations - * 0b0..Normal operation - * 0b1..eDMA operations halted +#define CMP_PARAM_PARAM(x) (((uint32_t)(((uint32_t)(x)) << CMP_PARAM_PARAM_SHIFT)) & CMP_PARAM_PARAM_MASK) +/*! @} */ + +/*! @name C0 - CMP Control Register 0 */ +/*! @{ */ + +#define CMP_C0_HYSTCTR_MASK (0x3U) +#define CMP_C0_HYSTCTR_SHIFT (0U) +/*! HYSTCTR - Comparator hard block hysteresis control. See chip data sheet to get the actual hystersis value with each level + * 0b00..The hard block output has level 0 hysteresis internally. + * 0b01..The hard block output has level 1 hysteresis internally. + * 0b10..The hard block output has level 2 hysteresis internally. + * 0b11..The hard block output has level 3 hysteresis internally. */ -#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK) -#define DMA_CR_CLM_MASK (0x40U) -#define DMA_CR_CLM_SHIFT (6U) -/*! CLM - Continuous Link Mode - * 0b0..Continuous link mode is off - * 0b1..Continuous link mode is on +#define CMP_C0_HYSTCTR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_HYSTCTR_SHIFT)) & CMP_C0_HYSTCTR_MASK) + +#define CMP_C0_FILTER_CNT_MASK (0x70U) +#define CMP_C0_FILTER_CNT_SHIFT (4U) +/*! FILTER_CNT - Filter Sample Count + * 0b000..Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA. + * 0b001..1 consecutive sample must agree (comparator output is simply sampled). + * 0b010..2 consecutive samples must agree. + * 0b011..3 consecutive samples must agree. + * 0b100..4 consecutive samples must agree. + * 0b101..5 consecutive samples must agree. + * 0b110..6 consecutive samples must agree. + * 0b111..7 consecutive samples must agree. */ -#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK) -#define DMA_CR_EMLM_MASK (0x80U) -#define DMA_CR_EMLM_SHIFT (7U) -/*! EMLM - Enable Minor Loop Mapping - * 0b0..Disabled - * 0b1..Enabled - */ -#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK) -#define DMA_CR_GRP0PRI_MASK (0x100U) -#define DMA_CR_GRP0PRI_SHIFT (8U) -/*! GRP0PRI - Channel Group 0 Priority - */ -#define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK) -#define DMA_CR_GRP1PRI_MASK (0x400U) -#define DMA_CR_GRP1PRI_SHIFT (10U) -/*! GRP1PRI - Channel Group 1 Priority - */ -#define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK) -#define DMA_CR_ECX_MASK (0x10000U) -#define DMA_CR_ECX_SHIFT (16U) -/*! ECX - Error Cancel Transfer - * 0b0..Normal operation - * 0b1..Cancel the remaining data transfer - */ -#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK) -#define DMA_CR_CX_MASK (0x20000U) -#define DMA_CR_CX_SHIFT (17U) -/*! CX - Cancel Transfer - * 0b0..Normal operation - * 0b1..Cancel the remaining data transfer +#define CMP_C0_FILTER_CNT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FILTER_CNT_SHIFT)) & CMP_C0_FILTER_CNT_MASK) + +#define CMP_C0_EN_MASK (0x100U) +#define CMP_C0_EN_SHIFT (8U) +/*! EN - Comparator Module Enable + * 0b0..Analog Comparator is disabled. + * 0b1..Analog Comparator is enabled. */ -#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK) -#define DMA_CR_ACTIVE_MASK (0x80000000U) -#define DMA_CR_ACTIVE_SHIFT (31U) -/*! ACTIVE - eDMA Active Status - * 0b0..eDMA is idle - * 0b1..eDMA is executing a channel +#define CMP_C0_EN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_EN_SHIFT)) & CMP_C0_EN_MASK) + +#define CMP_C0_OPE_MASK (0x200U) +#define CMP_C0_OPE_SHIFT (9U) +/*! OPE - Comparator Output Pin Enable + * 0b0..When OPE is 0, the comparator output (after window/filter settings dependent on software configuration) is not available to a packaged pin. + * 0b1..When OPE is 1, and if the software has configured the comparator to own a packaged pin, the comparator is available in a packaged pin. */ -#define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK) -/*! @} */ +#define CMP_C0_OPE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_OPE_SHIFT)) & CMP_C0_OPE_MASK) -/*! @name ES - Error Status */ -/*! @{ */ -#define DMA_ES_DBE_MASK (0x1U) -#define DMA_ES_DBE_SHIFT (0U) -/*! DBE - Destination Bus Error - * 0b0..No destination bus error. - * 0b1..The most-recently recorded error was a bus error on a destination write. +#define CMP_C0_COS_MASK (0x400U) +#define CMP_C0_COS_SHIFT (10U) +/*! COS - Comparator Output Select + * 0b0..Set CMPO to equal COUT (filtered comparator output). + * 0b1..Set CMPO to equal COUTA (unfiltered comparator output). */ -#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) -#define DMA_ES_SBE_MASK (0x2U) -#define DMA_ES_SBE_SHIFT (1U) -/*! SBE - Source Bus Error - * 0b0..No source bus error. - * 0b1..The most-recently recorded error was a bus error on a source read. +#define CMP_C0_COS(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COS_SHIFT)) & CMP_C0_COS_MASK) + +#define CMP_C0_INVT_MASK (0x800U) +#define CMP_C0_INVT_SHIFT (11U) +/*! INVT - Comparator invert + * 0b0..Does not invert the comparator output. + * 0b1..Inverts the comparator output. */ -#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK) -#define DMA_ES_SGE_MASK (0x4U) -#define DMA_ES_SGE_SHIFT (2U) -/*! SGE - Scatter/Gather Configuration Error - * 0b0..No scatter/gather configuration error. - * 0b1..The most-recently recorded error was a configuration error detected in the TCDn_DLASTSGA field. +#define CMP_C0_INVT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_INVT_SHIFT)) & CMP_C0_INVT_MASK) + +#define CMP_C0_PMODE_MASK (0x1000U) +#define CMP_C0_PMODE_SHIFT (12U) +/*! PMODE - Power Mode Select + * 0b0..Low Speed (LS) comparison mode is selected. + * 0b1..High Speed (HS) comparison mode is selected. */ -#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK) -#define DMA_ES_NCE_MASK (0x8U) -#define DMA_ES_NCE_SHIFT (3U) -/*! NCE - NBYTES/CITER Configuration Error - * 0b0..No NBYTES/CITER configuration error. - * 0b1..The most-recently recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER - * fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] = 0, or - * TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]. +#define CMP_C0_PMODE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_PMODE_SHIFT)) & CMP_C0_PMODE_MASK) + +#define CMP_C0_WE_MASK (0x4000U) +#define CMP_C0_WE_SHIFT (14U) +/*! WE - Windowing Enable + * 0b0..Windowing mode is not selected. + * 0b1..Windowing mode is selected. */ -#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) -#define DMA_ES_DOE_MASK (0x10U) -#define DMA_ES_DOE_SHIFT (4U) -/*! DOE - Destination Offset Error - * 0b0..No destination offset configuration error. - * 0b1..The most-recently recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. +#define CMP_C0_WE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_WE_SHIFT)) & CMP_C0_WE_MASK) + +#define CMP_C0_SE_MASK (0x8000U) +#define CMP_C0_SE_SHIFT (15U) +/*! SE - Sample Enable + * 0b0..Sampling mode is not selected. + * 0b1..Sampling mode is selected. */ -#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK) -#define DMA_ES_DAE_MASK (0x20U) -#define DMA_ES_DAE_SHIFT (5U) -/*! DAE - Destination Address Error - * 0b0..No destination address configuration error. - * 0b1..The most-recently recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR - * is inconsistent with TCDn_ATTR[DSIZE]. +#define CMP_C0_SE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_SE_SHIFT)) & CMP_C0_SE_MASK) + +#define CMP_C0_FPR_MASK (0xFF0000U) +#define CMP_C0_FPR_SHIFT (16U) +/*! FPR - Filter Sample Period */ -#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK) -#define DMA_ES_SOE_MASK (0x40U) -#define DMA_ES_SOE_SHIFT (6U) -/*! SOE - Source Offset Error - * 0b0..No source offset configuration error. - * 0b1..The most-recently recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. +#define CMP_C0_FPR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FPR_SHIFT)) & CMP_C0_FPR_MASK) + +#define CMP_C0_COUT_MASK (0x1000000U) +#define CMP_C0_COUT_SHIFT (24U) +/*! COUT - Analog Comparator Output */ -#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK) -#define DMA_ES_SAE_MASK (0x80U) -#define DMA_ES_SAE_SHIFT (7U) -/*! SAE - Source Address Error - * 0b0..No source address configuration error. - * 0b1..The most-recently recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR - * is inconsistent with TCDn_ATTR[SSIZE]. +#define CMP_C0_COUT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COUT_SHIFT)) & CMP_C0_COUT_MASK) + +#define CMP_C0_CFF_MASK (0x2000000U) +#define CMP_C0_CFF_SHIFT (25U) +/*! CFF - Analog Comparator Flag Falling + * 0b0..A falling edge has not been detected on COUT. + * 0b1..A falling edge on COUT has occurred. */ -#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK) -#define DMA_ES_ERRCHN_MASK (0x1F00U) -#define DMA_ES_ERRCHN_SHIFT (8U) -/*! ERRCHN - Error Channel Number or Canceled Channel Number +#define CMP_C0_CFF(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFF_SHIFT)) & CMP_C0_CFF_MASK) + +#define CMP_C0_CFR_MASK (0x4000000U) +#define CMP_C0_CFR_SHIFT (26U) +/*! CFR - Analog Comparator Flag Rising + * 0b0..A rising edge has not been detected on COUT. + * 0b1..A rising edge on COUT has occurred. */ -#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK) -#define DMA_ES_CPE_MASK (0x4000U) -#define DMA_ES_CPE_SHIFT (14U) -/*! CPE - Channel Priority Error - * 0b0..No channel priority error. - * 0b1..The most-recently recorded error was a configuration error in the channel priorities within a group. - * Channel priorities within a group are not unique. +#define CMP_C0_CFR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK) + +#define CMP_C0_IEF_MASK (0x8000000U) +#define CMP_C0_IEF_SHIFT (27U) +/*! IEF - Comparator Interrupt Enable Falling + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. */ -#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) -#define DMA_ES_GPE_MASK (0x8000U) -#define DMA_ES_GPE_SHIFT (15U) -/*! GPE - Group Priority Error - * 0b0..No group priority error. - * 0b1..The most-recently recorded error was a configuration error among the group priorities. All group priorities are not unique. +#define CMP_C0_IEF(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IEF_SHIFT)) & CMP_C0_IEF_MASK) + +#define CMP_C0_IER_MASK (0x10000000U) +#define CMP_C0_IER_SHIFT (28U) +/*! IER - Comparator Interrupt Enable Rising + * 0b0..Interrupt is disabled. + * 0b1..Interrupt is enabled. */ -#define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK) -#define DMA_ES_ECX_MASK (0x10000U) -#define DMA_ES_ECX_SHIFT (16U) -/*! ECX - Transfer Canceled - * 0b0..No canceled transfers - * 0b1..The most-recently recorded entry was a canceled transfer initiated by the error cancel transfer field +#define CMP_C0_IER(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IER_SHIFT)) & CMP_C0_IER_MASK) + +#define CMP_C0_DMAEN_MASK (0x40000000U) +#define CMP_C0_DMAEN_SHIFT (30U) +/*! DMAEN - DMA Enable + * 0b0..DMA is disabled. + * 0b1..DMA is enabled. */ -#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK) -#define DMA_ES_VLD_MASK (0x80000000U) -#define DMA_ES_VLD_SHIFT (31U) -/*! VLD - Logical OR of all ERR status fields - * 0b0..No ERR fields are 1 - * 0b1..At least one ERR field has a value of 1, indicating a valid error exists that has not been cleared +#define CMP_C0_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_DMAEN_SHIFT)) & CMP_C0_DMAEN_MASK) + +#define CMP_C0_LINKEN_MASK (0x80000000U) +#define CMP_C0_LINKEN_SHIFT (31U) +/*! LINKEN - CMP to DAC link enable. + * 0b0..CMP to DAC link is disabled + * 0b1..CMP to DAC link is enabled. */ -#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) +#define CMP_C0_LINKEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_LINKEN_SHIFT)) & CMP_C0_LINKEN_MASK) /*! @} */ -/*! @name ERQ - Enable Request */ +/*! @name C1 - CMP Control Register 1 */ /*! @{ */ -#define DMA_ERQ_ERQ0_MASK (0x1U) -#define DMA_ERQ_ERQ0_SHIFT (0U) -/*! ERQ0 - Enable DMA Request 0 - * 0b0..The DMA request signal for channel 0 is disabled - * 0b1..The DMA request signal for channel 0 is enabled + +#define CMP_C1_VOSEL_MASK (0xFFU) +#define CMP_C1_VOSEL_SHIFT (0U) +/*! VOSEL - DAC Output Voltage Select */ -#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) -#define DMA_ERQ_ERQ1_MASK (0x2U) -#define DMA_ERQ_ERQ1_SHIFT (1U) -/*! ERQ1 - Enable DMA Request 1 - * 0b0..The DMA request signal for channel 1 is disabled - * 0b1..The DMA request signal for channel 1 is enabled +#define CMP_C1_VOSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VOSEL_SHIFT)) & CMP_C1_VOSEL_MASK) + +#define CMP_C1_DMODE_MASK (0x100U) +#define CMP_C1_DMODE_SHIFT (8U) +/*! DMODE - DAC Mode Selection + * 0b0..DAC is selected to work in low speed and low power mode. + * 0b1..DAC is selected to work in high speed high power mode. */ -#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK) -#define DMA_ERQ_ERQ2_MASK (0x4U) -#define DMA_ERQ_ERQ2_SHIFT (2U) -/*! ERQ2 - Enable DMA Request 2 - * 0b0..The DMA request signal for channel 2 is disabled - * 0b1..The DMA request signal for channel 2 is enabled +#define CMP_C1_DMODE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DMODE_SHIFT)) & CMP_C1_DMODE_MASK) + +#define CMP_C1_VRSEL_MASK (0x200U) +#define CMP_C1_VRSEL_SHIFT (9U) +/*! VRSEL - Supply Voltage Reference Source Select + * 0b0..Vin1 is selected as resistor ladder network supply reference Vin. Vin1 is from internal PMC. + * 0b1..Vin2 is selected as resistor ladder network supply reference Vin. Vin2 is from PAD. */ -#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK) -#define DMA_ERQ_ERQ3_MASK (0x8U) -#define DMA_ERQ_ERQ3_SHIFT (3U) -/*! ERQ3 - Enable DMA Request 3 - * 0b0..The DMA request signal for channel 3 is disabled - * 0b1..The DMA request signal for channel 3 is enabled +#define CMP_C1_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VRSEL_SHIFT)) & CMP_C1_VRSEL_MASK) + +#define CMP_C1_DACEN_MASK (0x400U) +#define CMP_C1_DACEN_SHIFT (10U) +/*! DACEN - DAC Enable + * 0b0..DAC is disabled. + * 0b1..DAC is enabled. */ -#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK) -#define DMA_ERQ_ERQ4_MASK (0x10U) -#define DMA_ERQ_ERQ4_SHIFT (4U) -/*! ERQ4 - Enable DMA Request 4 - * 0b0..The DMA request signal for channel 4 is disabled - * 0b1..The DMA request signal for channel 4 is enabled +#define CMP_C1_DACEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DACEN_SHIFT)) & CMP_C1_DACEN_MASK) + +#define CMP_C1_CHN0_MASK (0x10000U) +#define CMP_C1_CHN0_SHIFT (16U) +/*! CHN0 - Channel 0 input enable */ -#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK) -#define DMA_ERQ_ERQ5_MASK (0x20U) -#define DMA_ERQ_ERQ5_SHIFT (5U) -/*! ERQ5 - Enable DMA Request 5 - * 0b0..The DMA request signal for channel 5 is disabled - * 0b1..The DMA request signal for channel 5 is enabled +#define CMP_C1_CHN0(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN0_SHIFT)) & CMP_C1_CHN0_MASK) + +#define CMP_C1_CHN1_MASK (0x20000U) +#define CMP_C1_CHN1_SHIFT (17U) +/*! CHN1 - Channel 1 input enable */ -#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK) -#define DMA_ERQ_ERQ6_MASK (0x40U) -#define DMA_ERQ_ERQ6_SHIFT (6U) -/*! ERQ6 - Enable DMA Request 6 - * 0b0..The DMA request signal for channel 6 is disabled - * 0b1..The DMA request signal for channel 6 is enabled +#define CMP_C1_CHN1(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN1_SHIFT)) & CMP_C1_CHN1_MASK) + +#define CMP_C1_CHN2_MASK (0x40000U) +#define CMP_C1_CHN2_SHIFT (18U) +/*! CHN2 - Channel 2 input enable */ -#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK) -#define DMA_ERQ_ERQ7_MASK (0x80U) -#define DMA_ERQ_ERQ7_SHIFT (7U) -/*! ERQ7 - Enable DMA Request 7 - * 0b0..The DMA request signal for channel 7 is disabled - * 0b1..The DMA request signal for channel 7 is enabled +#define CMP_C1_CHN2(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN2_SHIFT)) & CMP_C1_CHN2_MASK) + +#define CMP_C1_CHN3_MASK (0x80000U) +#define CMP_C1_CHN3_SHIFT (19U) +/*! CHN3 - Channel 3 input enable */ -#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK) -#define DMA_ERQ_ERQ8_MASK (0x100U) -#define DMA_ERQ_ERQ8_SHIFT (8U) -/*! ERQ8 - Enable DMA Request 8 - * 0b0..The DMA request signal for channel 8 is disabled - * 0b1..The DMA request signal for channel 8 is enabled +#define CMP_C1_CHN3(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN3_SHIFT)) & CMP_C1_CHN3_MASK) + +#define CMP_C1_CHN4_MASK (0x100000U) +#define CMP_C1_CHN4_SHIFT (20U) +/*! CHN4 - Channel 4 input enable */ -#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK) -#define DMA_ERQ_ERQ9_MASK (0x200U) -#define DMA_ERQ_ERQ9_SHIFT (9U) -/*! ERQ9 - Enable DMA Request 9 - * 0b0..The DMA request signal for channel 9 is disabled - * 0b1..The DMA request signal for channel 9 is enabled +#define CMP_C1_CHN4(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN4_SHIFT)) & CMP_C1_CHN4_MASK) + +#define CMP_C1_CHN5_MASK (0x200000U) +#define CMP_C1_CHN5_SHIFT (21U) +/*! CHN5 - Channel 5 input enable */ -#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK) -#define DMA_ERQ_ERQ10_MASK (0x400U) -#define DMA_ERQ_ERQ10_SHIFT (10U) -/*! ERQ10 - Enable DMA Request 10 - * 0b0..The DMA request signal for channel 10 is disabled - * 0b1..The DMA request signal for channel 10 is enabled +#define CMP_C1_CHN5(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN5_SHIFT)) & CMP_C1_CHN5_MASK) + +#define CMP_C1_MSEL_MASK (0x7000000U) +#define CMP_C1_MSEL_SHIFT (24U) +/*! MSEL - Minus Input MUX Control + * 0b000..Internal Negative Input 0 for Minus Channel -- Internal Minus Input + * 0b001..External Input 1 for Minus Channel -- Reference Input 0 + * 0b010..External Input 2 for Minus Channel -- Reference Input 1 + * 0b011..External Input 3 for Minus Channel -- Reference Input 2 + * 0b100..External Input 4 for Minus Channel -- Reference Input 3 + * 0b101..External Input 5 for Minus Channel -- Reference Input 4 + * 0b110..External Input 6 for Minus Channel -- Reference Input 5 + * 0b111..Internal 8b DAC output */ -#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK) -#define DMA_ERQ_ERQ11_MASK (0x800U) -#define DMA_ERQ_ERQ11_SHIFT (11U) -/*! ERQ11 - Enable DMA Request 11 - * 0b0..The DMA request signal for channel 11 is disabled - * 0b1..The DMA request signal for channel 11 is enabled +#define CMP_C1_MSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_MSEL_SHIFT)) & CMP_C1_MSEL_MASK) + +#define CMP_C1_PSEL_MASK (0x70000000U) +#define CMP_C1_PSEL_SHIFT (28U) +/*! PSEL - Plus Input MUX Control + * 0b000..Internal Positive Input 0 for Plus Channel -- Internal Plus Input + * 0b001..External Input 1 for Plus Channel -- Reference Input 0 + * 0b010..External Input 2 for Plus Channel -- Reference Input 1 + * 0b011..External Input 3 for Plus Channel -- Reference Input 2 + * 0b100..External Input 4 for Plus Channel -- Reference Input 3 + * 0b101..External Input 5 for Plus Channel -- Reference Input 4 + * 0b110..External Input 6 for Plus Channel -- Reference Input 5 + * 0b111..Internal 8b DAC output */ -#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK) -#define DMA_ERQ_ERQ12_MASK (0x1000U) -#define DMA_ERQ_ERQ12_SHIFT (12U) -/*! ERQ12 - Enable DMA Request 12 - * 0b0..The DMA request signal for channel 12 is disabled - * 0b1..The DMA request signal for channel 12 is enabled +#define CMP_C1_PSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_PSEL_SHIFT)) & CMP_C1_PSEL_MASK) +/*! @} */ + +/*! @name C2 - CMP Control Register 2 */ +/*! @{ */ + +#define CMP_C2_ACOn_MASK (0x3FU) +#define CMP_C2_ACOn_SHIFT (0U) +/*! ACOn - ACOn */ -#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK) -#define DMA_ERQ_ERQ13_MASK (0x2000U) -#define DMA_ERQ_ERQ13_SHIFT (13U) -/*! ERQ13 - Enable DMA Request 13 - * 0b0..The DMA request signal for channel 13 is disabled - * 0b1..The DMA request signal for channel 13 is enabled +#define CMP_C2_ACOn(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_ACOn_SHIFT)) & CMP_C2_ACOn_MASK) + +#define CMP_C2_INITMOD_MASK (0x3F00U) +#define CMP_C2_INITMOD_SHIFT (8U) +/*! INITMOD - Comparator and DAC initialization delay modulus. */ -#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK) -#define DMA_ERQ_ERQ14_MASK (0x4000U) -#define DMA_ERQ_ERQ14_SHIFT (14U) -/*! ERQ14 - Enable DMA Request 14 - * 0b0..The DMA request signal for channel 14 is disabled - * 0b1..The DMA request signal for channel 14 is enabled +#define CMP_C2_INITMOD(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_INITMOD_SHIFT)) & CMP_C2_INITMOD_MASK) + +#define CMP_C2_NSAM_MASK (0xC000U) +#define CMP_C2_NSAM_SHIFT (14U) +/*! NSAM - Number of sample clocks + * 0b00..The comparison result is sampled as soon as the active channel is scanned in one round-robin clock. + * 0b01..The sampling takes place 1 round-robin clock cycle after the next cycle of the round-robin clock. + * 0b10..The sampling takes place 2 round-robin clock cycles after the next cycle of the round-robin clock. + * 0b11..The sampling takes place 3 round-robin clock cycles after the next cycle of the round-robin clock. */ -#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK) -#define DMA_ERQ_ERQ15_MASK (0x8000U) -#define DMA_ERQ_ERQ15_SHIFT (15U) -/*! ERQ15 - Enable DMA Request 15 - * 0b0..The DMA request signal for channel 15 is disabled - * 0b1..The DMA request signal for channel 15 is enabled +#define CMP_C2_NSAM(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_NSAM_SHIFT)) & CMP_C2_NSAM_MASK) + +#define CMP_C2_CH0F_MASK (0x10000U) +#define CMP_C2_CH0F_SHIFT (16U) +/*! CH0F - CH0F */ -#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK) -#define DMA_ERQ_ERQ16_MASK (0x10000U) -#define DMA_ERQ_ERQ16_SHIFT (16U) -/*! ERQ16 - Enable DMA Request 16 - * 0b0..The DMA request signal for channel 16 is disabled - * 0b1..The DMA request signal for channel 16 is enabled +#define CMP_C2_CH0F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH0F_SHIFT)) & CMP_C2_CH0F_MASK) + +#define CMP_C2_CH1F_MASK (0x20000U) +#define CMP_C2_CH1F_SHIFT (17U) +/*! CH1F - CH1F */ -#define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK) -#define DMA_ERQ_ERQ17_MASK (0x20000U) -#define DMA_ERQ_ERQ17_SHIFT (17U) -/*! ERQ17 - Enable DMA Request 17 - * 0b0..The DMA request signal for channel 17 is disabled - * 0b1..The DMA request signal for channel 17 is enabled +#define CMP_C2_CH1F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH1F_SHIFT)) & CMP_C2_CH1F_MASK) + +#define CMP_C2_CH2F_MASK (0x40000U) +#define CMP_C2_CH2F_SHIFT (18U) +/*! CH2F - CH2F */ -#define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK) -#define DMA_ERQ_ERQ18_MASK (0x40000U) -#define DMA_ERQ_ERQ18_SHIFT (18U) -/*! ERQ18 - Enable DMA Request 18 - * 0b0..The DMA request signal for channel 18 is disabled - * 0b1..The DMA request signal for channel 18 is enabled +#define CMP_C2_CH2F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH2F_SHIFT)) & CMP_C2_CH2F_MASK) + +#define CMP_C2_CH3F_MASK (0x80000U) +#define CMP_C2_CH3F_SHIFT (19U) +/*! CH3F - CH3F */ -#define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK) -#define DMA_ERQ_ERQ19_MASK (0x80000U) -#define DMA_ERQ_ERQ19_SHIFT (19U) -/*! ERQ19 - Enable DMA Request 19 - * 0b0..The DMA request signal for channel 19 is disabled - * 0b1..The DMA request signal for channel 19 is enabled +#define CMP_C2_CH3F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH3F_SHIFT)) & CMP_C2_CH3F_MASK) + +#define CMP_C2_CH4F_MASK (0x100000U) +#define CMP_C2_CH4F_SHIFT (20U) +/*! CH4F - CH4F */ -#define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK) -#define DMA_ERQ_ERQ20_MASK (0x100000U) -#define DMA_ERQ_ERQ20_SHIFT (20U) -/*! ERQ20 - Enable DMA Request 20 - * 0b0..The DMA request signal for channel 20 is disabled - * 0b1..The DMA request signal for channel 20 is enabled +#define CMP_C2_CH4F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH4F_SHIFT)) & CMP_C2_CH4F_MASK) + +#define CMP_C2_CH5F_MASK (0x200000U) +#define CMP_C2_CH5F_SHIFT (21U) +/*! CH5F - CH5F */ -#define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK) -#define DMA_ERQ_ERQ21_MASK (0x200000U) -#define DMA_ERQ_ERQ21_SHIFT (21U) -/*! ERQ21 - Enable DMA Request 21 - * 0b0..The DMA request signal for channel 21 is disabled - * 0b1..The DMA request signal for channel 21 is enabled +#define CMP_C2_CH5F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH5F_SHIFT)) & CMP_C2_CH5F_MASK) + +#define CMP_C2_FXMXCH_MASK (0xE000000U) +#define CMP_C2_FXMXCH_SHIFT (25U) +/*! FXMXCH - Fixed channel selection + * 0b000..External Reference Input 0 is selected as the fixed reference input for the fixed mux port. + * 0b001..External Reference Input 1 is selected as the fixed reference input for the fixed mux port. + * 0b010..External Reference Input 2 is selected as the fixed reference input for the fixed mux port. + * 0b011..External Reference Input 3 is selected as the fixed reference input for the fixed mux port. + * 0b100..External Reference Input 4 is selected as the fixed reference input for the fixed mux port. + * 0b101..External Reference Input 5 is selected as the fixed reference input for the fixed mux port. + * 0b110..Reserved. + * 0b111..The 8bit DAC is selected as the fixed reference input for the fixed mux port. */ -#define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK) -#define DMA_ERQ_ERQ22_MASK (0x400000U) -#define DMA_ERQ_ERQ22_SHIFT (22U) -/*! ERQ22 - Enable DMA Request 22 - * 0b0..The DMA request signal for channel 22 is disabled - * 0b1..The DMA request signal for channel 22 is enabled +#define CMP_C2_FXMXCH(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMXCH_SHIFT)) & CMP_C2_FXMXCH_MASK) + +#define CMP_C2_FXMP_MASK (0x20000000U) +#define CMP_C2_FXMP_SHIFT (29U) +/*! FXMP - Fixed MUX Port + * 0b0..The Plus port is fixed. Only the inputs to the Minus port are swept in each round. + * 0b1..The Minus port is fixed. Only the inputs to the Plus port are swept in each round. */ -#define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK) -#define DMA_ERQ_ERQ23_MASK (0x800000U) -#define DMA_ERQ_ERQ23_SHIFT (23U) -/*! ERQ23 - Enable DMA Request 23 - * 0b0..The DMA request signal for channel 23 is disabled - * 0b1..The DMA request signal for channel 23 is enabled - */ -#define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK) -#define DMA_ERQ_ERQ24_MASK (0x1000000U) -#define DMA_ERQ_ERQ24_SHIFT (24U) -/*! ERQ24 - Enable DMA Request 24 - * 0b0..The DMA request signal for channel 24 is disabled - * 0b1..The DMA request signal for channel 24 is enabled - */ -#define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK) -#define DMA_ERQ_ERQ25_MASK (0x2000000U) -#define DMA_ERQ_ERQ25_SHIFT (25U) -/*! ERQ25 - Enable DMA Request 25 - * 0b0..The DMA request signal for channel 25 is disabled - * 0b1..The DMA request signal for channel 25 is enabled - */ -#define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK) -#define DMA_ERQ_ERQ26_MASK (0x4000000U) -#define DMA_ERQ_ERQ26_SHIFT (26U) -/*! ERQ26 - Enable DMA Request 26 - * 0b0..The DMA request signal for channel 26 is disabled - * 0b1..The DMA request signal for channel 26 is enabled - */ -#define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK) -#define DMA_ERQ_ERQ27_MASK (0x8000000U) -#define DMA_ERQ_ERQ27_SHIFT (27U) -/*! ERQ27 - Enable DMA Request 27 - * 0b0..The DMA request signal for channel 27 is disabled - * 0b1..The DMA request signal for channel 27 is enabled - */ -#define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK) -#define DMA_ERQ_ERQ28_MASK (0x10000000U) -#define DMA_ERQ_ERQ28_SHIFT (28U) -/*! ERQ28 - Enable DMA Request 28 - * 0b0..The DMA request signal for channel 28 is disabled - * 0b1..The DMA request signal for channel 28 is enabled - */ -#define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK) -#define DMA_ERQ_ERQ29_MASK (0x20000000U) -#define DMA_ERQ_ERQ29_SHIFT (29U) -/*! ERQ29 - Enable DMA Request 29 - * 0b0..The DMA request signal for channel 29 is disabled - * 0b1..The DMA request signal for channel 29 is enabled - */ -#define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK) -#define DMA_ERQ_ERQ30_MASK (0x40000000U) -#define DMA_ERQ_ERQ30_SHIFT (30U) -/*! ERQ30 - Enable DMA Request 30 - * 0b0..The DMA request signal for channel 30 is disabled - * 0b1..The DMA request signal for channel 30 is enabled - */ -#define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK) -#define DMA_ERQ_ERQ31_MASK (0x80000000U) -#define DMA_ERQ_ERQ31_SHIFT (31U) -/*! ERQ31 - Enable DMA Request 31 - * 0b0..The DMA request signal for channel 31 is disabled - * 0b1..The DMA request signal for channel 31 is enabled +#define CMP_C2_FXMP(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMP_SHIFT)) & CMP_C2_FXMP_MASK) + +#define CMP_C2_RRIE_MASK (0x40000000U) +#define CMP_C2_RRIE_SHIFT (30U) +/*! RRIE - Round-Robin interrupt enable + * 0b0..The round-robin interrupt is disabled. + * 0b1..The round-robin interrupt is enabled when a comparison result changes from the last sample. */ -#define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK) +#define CMP_C2_RRIE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_RRIE_SHIFT)) & CMP_C2_RRIE_MASK) /*! @} */ -/*! @name EEI - Enable Error Interrupt */ +/*! @name C3 - CMP Control Register 3 */ /*! @{ */ -#define DMA_EEI_EEI0_MASK (0x1U) -#define DMA_EEI_EEI0_SHIFT (0U) -/*! EEI0 - Enable Error Interrupt 0 - * 0b0..An error on channel 0 does not generate an error interrupt - * 0b1..An error on channel 0 generates an error interrupt request - */ -#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) -#define DMA_EEI_EEI1_MASK (0x2U) -#define DMA_EEI_EEI1_SHIFT (1U) -/*! EEI1 - Enable Error Interrupt 1 - * 0b0..An error on channel 1 does not generate an error interrupt - * 0b1..An error on channel 1 generates an error interrupt request - */ -#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK) -#define DMA_EEI_EEI2_MASK (0x4U) -#define DMA_EEI_EEI2_SHIFT (2U) -/*! EEI2 - Enable Error Interrupt 2 - * 0b0..An error on channel 2 does not generate an error interrupt - * 0b1..An error on channel 2 generates an error interrupt request + +#define CMP_C3_ACPH2TC_MASK (0x70U) +#define CMP_C3_ACPH2TC_SHIFT (4U) +/*! ACPH2TC - Analog Comparator Phase2 Timing Control. + * 0b000..Phase2 active time in one sampling period equals to T + * 0b001..Phase2 active time in one sampling period equals to 2*T + * 0b010..Phase2 active time in one sampling period equals to 4*T + * 0b011..Phase2 active time in one sampling period equals to 8*T + * 0b100..Phase2 active time in one sampling period equals to 16*T + * 0b101..Phase2 active time in one sampling period equals to 32*T + * 0b110..Phase2 active time in one sampling period equals to 64*T + * 0b111..Phase2 active time in one sampling period equals to 16*T */ -#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK) -#define DMA_EEI_EEI3_MASK (0x8U) -#define DMA_EEI_EEI3_SHIFT (3U) -/*! EEI3 - Enable Error Interrupt 3 - * 0b0..An error on channel 3 does not generate an error interrupt - * 0b1..An error on channel 3 generates an error interrupt request +#define CMP_C3_ACPH2TC(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH2TC_SHIFT)) & CMP_C3_ACPH2TC_MASK) + +#define CMP_C3_ACPH1TC_MASK (0x700U) +#define CMP_C3_ACPH1TC_SHIFT (8U) +/*! ACPH1TC - Analog Comparator Phase1 Timing Control. + * 0b000..Phase1 active time in one sampling period equals to T + * 0b001..Phase1 active time in one sampling period equals to 2*T + * 0b010..Phase1 active time in one sampling period equals to 4*T + * 0b011..Phase1 active time in one sampling period equals to 8*T + * 0b100..Phase1 active time in one sampling period equals to T + * 0b101..Phase1 active time in one sampling period equals to T + * 0b110..Phase1 active time in one sampling period equals to T + * 0b111..Phase1 active time in one sampling period equals to 0 */ -#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK) -#define DMA_EEI_EEI4_MASK (0x10U) -#define DMA_EEI_EEI4_SHIFT (4U) -/*! EEI4 - Enable Error Interrupt 4 - * 0b0..An error on channel 4 does not generate an error interrupt - * 0b1..An error on channel 4 generates an error interrupt request +#define CMP_C3_ACPH1TC(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH1TC_SHIFT)) & CMP_C3_ACPH1TC_MASK) + +#define CMP_C3_ACSAT_MASK (0x7000U) +#define CMP_C3_ACSAT_SHIFT (12U) +/*! ACSAT - Analog Comparator Sampling Time control. + * 0b000..The sampling time equals to T + * 0b001..The sampling time equasl to 2*T + * 0b010..The sampling time equasl to 4*T + * 0b011..The sampling time equasl to 8*T + * 0b100..The sampling time equasl to 16*T + * 0b101..The sampling time equasl to 32*T + * 0b110..The sampling time equasl to 64*T + * 0b111..The sampling time equasl to 256*T */ -#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK) -#define DMA_EEI_EEI5_MASK (0x20U) -#define DMA_EEI_EEI5_SHIFT (5U) -/*! EEI5 - Enable Error Interrupt 5 - * 0b0..An error on channel 5 does not generate an error interrupt - * 0b1..An error on channel 5 generates an error interrupt request +#define CMP_C3_ACSAT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACSAT_SHIFT)) & CMP_C3_ACSAT_MASK) + +#define CMP_C3_DMCS_MASK (0x10000U) +#define CMP_C3_DMCS_SHIFT (16U) +/*! DMCS - Discrete Mode Clock Selection + * 0b0..Slow clock is selected for the timing generation. + * 0b1..Fast clock is selected for the timing generation. */ -#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK) -#define DMA_EEI_EEI6_MASK (0x40U) -#define DMA_EEI_EEI6_SHIFT (6U) -/*! EEI6 - Enable Error Interrupt 6 - * 0b0..An error on channel 6 does not generate an error interrupt - * 0b1..An error on channel 6 generates an error interrupt request +#define CMP_C3_DMCS(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_DMCS_SHIFT)) & CMP_C3_DMCS_MASK) + +#define CMP_C3_RDIVE_MASK (0x100000U) +#define CMP_C3_RDIVE_SHIFT (20U) +/*! RDIVE - Resistor Divider Enable + * 0b0..The resistor is not enabled even when either NCHEN or PCHEN is set to1 but the actual input is in the range of 0 - 1.8v. + * 0b1..The resistor is enabled because the inputs are above 1.8v. */ -#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK) -#define DMA_EEI_EEI7_MASK (0x80U) -#define DMA_EEI_EEI7_SHIFT (7U) -/*! EEI7 - Enable Error Interrupt 7 - * 0b0..An error on channel 7 does not generate an error interrupt - * 0b1..An error on channel 7 generates an error interrupt request +#define CMP_C3_RDIVE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_RDIVE_SHIFT)) & CMP_C3_RDIVE_MASK) + +#define CMP_C3_NCHCTEN_MASK (0x1000000U) +#define CMP_C3_NCHCTEN_SHIFT (24U) +/*! NCHCTEN - Negative Channel Continuous Mode Enable. + * 0b0..Negative channel is in Discrete Mode and special timing needs to be configured. + * 0b1..Negative channel is in Continuous Mode and no special timing is requried. */ -#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK) -#define DMA_EEI_EEI8_MASK (0x100U) -#define DMA_EEI_EEI8_SHIFT (8U) -/*! EEI8 - Enable Error Interrupt 8 - * 0b0..An error on channel 8 does not generate an error interrupt - * 0b1..An error on channel 8 generates an error interrupt request +#define CMP_C3_NCHCTEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_NCHCTEN_SHIFT)) & CMP_C3_NCHCTEN_MASK) + +#define CMP_C3_PCHCTEN_MASK (0x10000000U) +#define CMP_C3_PCHCTEN_SHIFT (28U) +/*! PCHCTEN - Positive Channel Continuous Mode Enable. + * 0b0..Positive channel is in Discrete Mode and special timing needs to be configured. + * 0b1..Positive channel is in Continuous Mode and no special timing is requried. */ -#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK) -#define DMA_EEI_EEI9_MASK (0x200U) -#define DMA_EEI_EEI9_SHIFT (9U) -/*! EEI9 - Enable Error Interrupt 9 - * 0b0..An error on channel 9 does not generate an error interrupt - * 0b1..An error on channel 9 generates an error interrupt request +#define CMP_C3_PCHCTEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_PCHCTEN_SHIFT)) & CMP_C3_PCHCTEN_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group CMP_Register_Masks */ + + +/* CMP - Peripheral instance base addresses */ +/** Peripheral CMP1 base address */ +#define CMP1_BASE (0x401A4000u) +/** Peripheral CMP1 base pointer */ +#define CMP1 ((CMP_Type *)CMP1_BASE) +/** Peripheral CMP2 base address */ +#define CMP2_BASE (0x401A8000u) +/** Peripheral CMP2 base pointer */ +#define CMP2 ((CMP_Type *)CMP2_BASE) +/** Peripheral CMP3 base address */ +#define CMP3_BASE (0x401AC000u) +/** Peripheral CMP3 base pointer */ +#define CMP3 ((CMP_Type *)CMP3_BASE) +/** Peripheral CMP4 base address */ +#define CMP4_BASE (0x401B0000u) +/** Peripheral CMP4 base pointer */ +#define CMP4 ((CMP_Type *)CMP4_BASE) +/** Array initializer of CMP peripheral base addresses */ +#define CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE } +/** Array initializer of CMP peripheral base pointers */ +#define CMP_BASE_PTRS { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 } +/** Interrupt vectors for the CMP peripheral type */ +#define CMP_IRQS { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn } + +/*! + * @} + */ /* end of group CMP_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- CSI Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSI_Peripheral_Access_Layer CSI Peripheral Access Layer + * @{ */ -#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK) -#define DMA_EEI_EEI10_MASK (0x400U) -#define DMA_EEI_EEI10_SHIFT (10U) -/*! EEI10 - Enable Error Interrupt 10 - * 0b0..An error on channel 10 does not generate an error interrupt - * 0b1..An error on channel 10 generates an error interrupt request + +/** CSI - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR1; /**< CSI Control Register 1, offset: 0x0 */ + __IO uint32_t CR2; /**< CSI Control Register 2, offset: 0x4 */ + __IO uint32_t CR3; /**< CSI Control Register 3, offset: 0x8 */ + __I uint32_t STATFIFO; /**< CSI Statistic FIFO Register, offset: 0xC */ + __I uint32_t RFIFO; /**< CSI RX FIFO Register, offset: 0x10 */ + __IO uint32_t RXCNT; /**< CSI RX Count Register, offset: 0x14 */ + __IO uint32_t SR; /**< CSI Status Register, offset: 0x18 */ + uint8_t RESERVED_0[4]; + __IO uint32_t DMASA_STATFIFO; /**< CSI DMA Start Address Register - for STATFIFO, offset: 0x20 */ + __IO uint32_t DMATS_STATFIFO; /**< CSI DMA Transfer Size Register - for STATFIFO, offset: 0x24 */ + __IO uint32_t DMASA_FB1; /**< CSI DMA Start Address Register - for Frame Buffer1, offset: 0x28 */ + __IO uint32_t DMASA_FB2; /**< CSI DMA Transfer Size Register - for Frame Buffer2, offset: 0x2C */ + __IO uint32_t FBUF_PARA; /**< CSI Frame Buffer Parameter Register, offset: 0x30 */ + __IO uint32_t IMAG_PARA; /**< CSI Image Parameter Register, offset: 0x34 */ + uint8_t RESERVED_1[16]; + __IO uint32_t CR18; /**< CSI Control Register 18, offset: 0x48 */ + __IO uint32_t CR19; /**< CSI Control Register 19, offset: 0x4C */ + __IO uint32_t CR20; /**< CSI Control Register 20, offset: 0x50 */ + __IO uint32_t CR[256]; /**< CSI Control Register, array offset: 0x54, array step: 0x4 */ +} CSI_Type; + +/* ---------------------------------------------------------------------------- + -- CSI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSI_Register_Masks CSI Register Masks + * @{ */ -#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK) -#define DMA_EEI_EEI11_MASK (0x800U) -#define DMA_EEI_EEI11_SHIFT (11U) -/*! EEI11 - Enable Error Interrupt 11 - * 0b0..An error on channel 11 does not generate an error interrupt - * 0b1..An error on channel 11 generates an error interrupt request + +/*! @name CR1 - CSI Control Register 1 */ +/*! @{ */ + +#define CSI_CR1_PIXEL_BIT_MASK (0x1U) +#define CSI_CR1_PIXEL_BIT_SHIFT (0U) +/*! PIXEL_BIT + * 0b0..8-bit data for each pixel + * 0b1..10-bit data for each pixel */ -#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK) -#define DMA_EEI_EEI12_MASK (0x1000U) -#define DMA_EEI_EEI12_SHIFT (12U) -/*! EEI12 - Enable Error Interrupt 12 - * 0b0..An error on channel 12 does not generate an error interrupt - * 0b1..An error on channel 12 generates an error interrupt request +#define CSI_CR1_PIXEL_BIT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_PIXEL_BIT_SHIFT)) & CSI_CR1_PIXEL_BIT_MASK) + +#define CSI_CR1_REDGE_MASK (0x2U) +#define CSI_CR1_REDGE_SHIFT (1U) +/*! REDGE + * 0b0..Pixel data is latched at the falling edge of CSI_PIXCLK + * 0b1..Pixel data is latched at the rising edge of CSI_PIXCLK */ -#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK) -#define DMA_EEI_EEI13_MASK (0x2000U) -#define DMA_EEI_EEI13_SHIFT (13U) -/*! EEI13 - Enable Error Interrupt 13 - * 0b0..An error on channel 13 does not generate an error interrupt - * 0b1..An error on channel 13 generates an error interrupt request +#define CSI_CR1_REDGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_REDGE_SHIFT)) & CSI_CR1_REDGE_MASK) + +#define CSI_CR1_INV_PCLK_MASK (0x4U) +#define CSI_CR1_INV_PCLK_SHIFT (2U) +/*! INV_PCLK + * 0b0..CSI_PIXCLK is directly applied to internal circuitry + * 0b1..CSI_PIXCLK is inverted before applied to internal circuitry */ -#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK) -#define DMA_EEI_EEI14_MASK (0x4000U) -#define DMA_EEI_EEI14_SHIFT (14U) -/*! EEI14 - Enable Error Interrupt 14 - * 0b0..An error on channel 14 does not generate an error interrupt - * 0b1..An error on channel 14 generates an error interrupt request +#define CSI_CR1_INV_PCLK(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_INV_PCLK_SHIFT)) & CSI_CR1_INV_PCLK_MASK) + +#define CSI_CR1_INV_DATA_MASK (0x8U) +#define CSI_CR1_INV_DATA_SHIFT (3U) +/*! INV_DATA + * 0b0..CSI_D[7:0] data lines are directly applied to internal circuitry + * 0b1..CSI_D[7:0] data lines are inverted before applied to internal circuitry */ -#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK) -#define DMA_EEI_EEI15_MASK (0x8000U) -#define DMA_EEI_EEI15_SHIFT (15U) -/*! EEI15 - Enable Error Interrupt 15 - * 0b0..An error on channel 15 does not generate an error interrupt - * 0b1..An error on channel 15 generates an error interrupt request +#define CSI_CR1_INV_DATA(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_INV_DATA_SHIFT)) & CSI_CR1_INV_DATA_MASK) + +#define CSI_CR1_GCLK_MODE_MASK (0x10U) +#define CSI_CR1_GCLK_MODE_SHIFT (4U) +/*! GCLK_MODE + * 0b0..Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored. + * 0b1..Gated clock mode. Pixel clock signal is valid only when HSYNC is active. */ -#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK) -#define DMA_EEI_EEI16_MASK (0x10000U) -#define DMA_EEI_EEI16_SHIFT (16U) -/*! EEI16 - Enable Error Interrupt 16 - * 0b0..An error on channel 16 does not generate an error interrupt - * 0b1..An error on channel 16 generates an error interrupt request +#define CSI_CR1_GCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_GCLK_MODE_SHIFT)) & CSI_CR1_GCLK_MODE_MASK) + +#define CSI_CR1_CLR_RXFIFO_MASK (0x20U) +#define CSI_CR1_CLR_RXFIFO_SHIFT (5U) +#define CSI_CR1_CLR_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_CLR_RXFIFO_SHIFT)) & CSI_CR1_CLR_RXFIFO_MASK) + +#define CSI_CR1_CLR_STATFIFO_MASK (0x40U) +#define CSI_CR1_CLR_STATFIFO_SHIFT (6U) +#define CSI_CR1_CLR_STATFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_CLR_STATFIFO_SHIFT)) & CSI_CR1_CLR_STATFIFO_MASK) + +#define CSI_CR1_PACK_DIR_MASK (0x80U) +#define CSI_CR1_PACK_DIR_SHIFT (7U) +/*! PACK_DIR + * 0b0..Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. For + * stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO. + * 0b1..Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. For + * stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO. */ -#define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK) -#define DMA_EEI_EEI17_MASK (0x20000U) -#define DMA_EEI_EEI17_SHIFT (17U) -/*! EEI17 - Enable Error Interrupt 17 - * 0b0..An error on channel 17 does not generate an error interrupt - * 0b1..An error on channel 17 generates an error interrupt request +#define CSI_CR1_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_PACK_DIR_SHIFT)) & CSI_CR1_PACK_DIR_MASK) + +#define CSI_CR1_FCC_MASK (0x100U) +#define CSI_CR1_FCC_SHIFT (8U) +/*! FCC + * 0b0..Asynchronous FIFO clear is selected. + * 0b1..Synchronous FIFO clear is selected. */ -#define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK) -#define DMA_EEI_EEI18_MASK (0x40000U) -#define DMA_EEI_EEI18_SHIFT (18U) -/*! EEI18 - Enable Error Interrupt 18 - * 0b0..An error on channel 18 does not generate an error interrupt - * 0b1..An error on channel 18 generates an error interrupt request +#define CSI_CR1_FCC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_FCC_SHIFT)) & CSI_CR1_FCC_MASK) + +#define CSI_CR1_CCIR_EN_MASK (0x400U) +#define CSI_CR1_CCIR_EN_SHIFT (10U) +/*! CCIR_EN + * 0b0..Traditional interface is selected. + * 0b1..BT.656 interface is selected. */ -#define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK) -#define DMA_EEI_EEI19_MASK (0x80000U) -#define DMA_EEI_EEI19_SHIFT (19U) -/*! EEI19 - Enable Error Interrupt 19 - * 0b0..An error on channel 19 does not generate an error interrupt - * 0b1..An error on channel 19 generates an error interrupt request +#define CSI_CR1_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_CCIR_EN_SHIFT)) & CSI_CR1_CCIR_EN_MASK) + +#define CSI_CR1_HSYNC_POL_MASK (0x800U) +#define CSI_CR1_HSYNC_POL_SHIFT (11U) +/*! HSYNC_POL + * 0b0..HSYNC is active low + * 0b1..HSYNC is active high */ -#define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK) -#define DMA_EEI_EEI20_MASK (0x100000U) -#define DMA_EEI_EEI20_SHIFT (20U) -/*! EEI20 - Enable Error Interrupt 20 - * 0b0..An error on channel 20 does not generate an error interrupt - * 0b1..An error on channel 20 generates an error interrupt request +#define CSI_CR1_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_HSYNC_POL_SHIFT)) & CSI_CR1_HSYNC_POL_MASK) + +#define CSI_CR1_HISTOGRAM_CALC_DONE_IE_MASK (0x1000U) +#define CSI_CR1_HISTOGRAM_CALC_DONE_IE_SHIFT (12U) +/*! HISTOGRAM_CALC_DONE_IE + * 0b0..Histogram done interrupt disable + * 0b1..Histogram done interrupt enable */ -#define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK) -#define DMA_EEI_EEI21_MASK (0x200000U) -#define DMA_EEI_EEI21_SHIFT (21U) -/*! EEI21 - Enable Error Interrupt 21 - * 0b0..An error on channel 21 does not generate an error interrupt - * 0b1..An error on channel 21 generates an error interrupt request +#define CSI_CR1_HISTOGRAM_CALC_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_HISTOGRAM_CALC_DONE_IE_SHIFT)) & CSI_CR1_HISTOGRAM_CALC_DONE_IE_MASK) + +#define CSI_CR1_SOF_INTEN_MASK (0x10000U) +#define CSI_CR1_SOF_INTEN_SHIFT (16U) +/*! SOF_INTEN + * 0b0..SOF interrupt disable + * 0b1..SOF interrupt enable */ -#define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK) -#define DMA_EEI_EEI22_MASK (0x400000U) -#define DMA_EEI_EEI22_SHIFT (22U) -/*! EEI22 - Enable Error Interrupt 22 - * 0b0..An error on channel 22 does not generate an error interrupt - * 0b1..An error on channel 22 generates an error interrupt request +#define CSI_CR1_SOF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SOF_INTEN_SHIFT)) & CSI_CR1_SOF_INTEN_MASK) + +#define CSI_CR1_SOF_POL_MASK (0x20000U) +#define CSI_CR1_SOF_POL_SHIFT (17U) +/*! SOF_POL + * 0b0..SOF interrupt is generated on SOF falling edge + * 0b1..SOF interrupt is generated on SOF rising edge */ -#define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK) -#define DMA_EEI_EEI23_MASK (0x800000U) -#define DMA_EEI_EEI23_SHIFT (23U) -/*! EEI23 - Enable Error Interrupt 23 - * 0b0..An error on channel 23 does not generate an error interrupt - * 0b1..An error on channel 23 generates an error interrupt request +#define CSI_CR1_SOF_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SOF_POL_SHIFT)) & CSI_CR1_SOF_POL_MASK) + +#define CSI_CR1_RXFF_INTEN_MASK (0x40000U) +#define CSI_CR1_RXFF_INTEN_SHIFT (18U) +/*! RXFF_INTEN + * 0b0..RxFIFO full interrupt disable + * 0b1..RxFIFO full interrupt enable */ -#define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK) -#define DMA_EEI_EEI24_MASK (0x1000000U) -#define DMA_EEI_EEI24_SHIFT (24U) -/*! EEI24 - Enable Error Interrupt 24 - * 0b0..An error on channel 24 does not generate an error interrupt - * 0b1..An error on channel 24 generates an error interrupt request +#define CSI_CR1_RXFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_RXFF_INTEN_SHIFT)) & CSI_CR1_RXFF_INTEN_MASK) + +#define CSI_CR1_FB1_DMA_DONE_INTEN_MASK (0x80000U) +#define CSI_CR1_FB1_DMA_DONE_INTEN_SHIFT (19U) +/*! FB1_DMA_DONE_INTEN + * 0b0..Frame Buffer1 DMA Transfer Done interrupt disable + * 0b1..Frame Buffer1 DMA Transfer Done interrupt enable */ -#define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK) -#define DMA_EEI_EEI25_MASK (0x2000000U) -#define DMA_EEI_EEI25_SHIFT (25U) -/*! EEI25 - Enable Error Interrupt 25 - * 0b0..An error on channel 25 does not generate an error interrupt - * 0b1..An error on channel 25 generates an error interrupt request +#define CSI_CR1_FB1_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CR1_FB1_DMA_DONE_INTEN_MASK) + +#define CSI_CR1_FB2_DMA_DONE_INTEN_MASK (0x100000U) +#define CSI_CR1_FB2_DMA_DONE_INTEN_SHIFT (20U) +/*! FB2_DMA_DONE_INTEN + * 0b0..Frame Buffer2 DMA Transfer Done interrupt disable + * 0b1..Frame Buffer2 DMA Transfer Done interrupt enable */ -#define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK) -#define DMA_EEI_EEI26_MASK (0x4000000U) -#define DMA_EEI_EEI26_SHIFT (26U) -/*! EEI26 - Enable Error Interrupt 26 - * 0b0..An error on channel 26 does not generate an error interrupt - * 0b1..An error on channel 26 generates an error interrupt request +#define CSI_CR1_FB2_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CR1_FB2_DMA_DONE_INTEN_MASK) + +#define CSI_CR1_STATFF_INTEN_MASK (0x200000U) +#define CSI_CR1_STATFF_INTEN_SHIFT (21U) +/*! STATFF_INTEN + * 0b0..STATFIFO full interrupt disable + * 0b1..STATFIFO full interrupt enable */ -#define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK) -#define DMA_EEI_EEI27_MASK (0x8000000U) -#define DMA_EEI_EEI27_SHIFT (27U) -/*! EEI27 - Enable Error Interrupt 27 - * 0b0..An error on channel 27 does not generate an error interrupt - * 0b1..An error on channel 27 generates an error interrupt request +#define CSI_CR1_STATFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_STATFF_INTEN_SHIFT)) & CSI_CR1_STATFF_INTEN_MASK) + +#define CSI_CR1_SFF_DMA_DONE_INTEN_MASK (0x400000U) +#define CSI_CR1_SFF_DMA_DONE_INTEN_SHIFT (22U) +/*! SFF_DMA_DONE_INTEN + * 0b0..STATFIFO DMA Transfer Done interrupt disable + * 0b1..STATFIFO DMA Transfer Done interrupt enable */ -#define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK) -#define DMA_EEI_EEI28_MASK (0x10000000U) -#define DMA_EEI_EEI28_SHIFT (28U) -/*! EEI28 - Enable Error Interrupt 28 - * 0b0..An error on channel 28 does not generate an error interrupt - * 0b1..An error on channel 28 generates an error interrupt request +#define CSI_CR1_SFF_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CR1_SFF_DMA_DONE_INTEN_MASK) + +#define CSI_CR1_RF_OR_INTEN_MASK (0x1000000U) +#define CSI_CR1_RF_OR_INTEN_SHIFT (24U) +/*! RF_OR_INTEN + * 0b0..RxFIFO overrun interrupt is disabled + * 0b1..RxFIFO overrun interrupt is enabled */ -#define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK) -#define DMA_EEI_EEI29_MASK (0x20000000U) -#define DMA_EEI_EEI29_SHIFT (29U) -/*! EEI29 - Enable Error Interrupt 29 - * 0b0..An error on channel 29 does not generate an error interrupt - * 0b1..An error on channel 29 generates an error interrupt request +#define CSI_CR1_RF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_RF_OR_INTEN_SHIFT)) & CSI_CR1_RF_OR_INTEN_MASK) + +#define CSI_CR1_SF_OR_INTEN_MASK (0x2000000U) +#define CSI_CR1_SF_OR_INTEN_SHIFT (25U) +/*! SF_OR_INTEN + * 0b0..STATFIFO overrun interrupt is disabled + * 0b1..STATFIFO overrun interrupt is enabled */ -#define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK) -#define DMA_EEI_EEI30_MASK (0x40000000U) -#define DMA_EEI_EEI30_SHIFT (30U) -/*! EEI30 - Enable Error Interrupt 30 - * 0b0..An error on channel 30 does not generate an error interrupt - * 0b1..An error on channel 30 generates an error interrupt request +#define CSI_CR1_SF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SF_OR_INTEN_SHIFT)) & CSI_CR1_SF_OR_INTEN_MASK) + +#define CSI_CR1_COF_INT_EN_MASK (0x4000000U) +#define CSI_CR1_COF_INT_EN_SHIFT (26U) +/*! COF_INT_EN + * 0b0..COF interrupt is disabled + * 0b1..COF interrupt is enabled */ -#define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK) -#define DMA_EEI_EEI31_MASK (0x80000000U) -#define DMA_EEI_EEI31_SHIFT (31U) -/*! EEI31 - Enable Error Interrupt 31 - * 0b0..An error on channel 31 does not generate an error interrupt - * 0b1..An error on channel 31 generates an error interrupt request +#define CSI_CR1_COF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_COF_INT_EN_SHIFT)) & CSI_CR1_COF_INT_EN_MASK) + +#define CSI_CR1_VIDEO_MODE_MASK (0x8000000U) +#define CSI_CR1_VIDEO_MODE_SHIFT (27U) +/*! VIDEO_MODE + * 0b0..Progressive mode is selected + * 0b1..Interlace mode is selected */ -#define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK) -/*! @} */ +#define CSI_CR1_VIDEO_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_VIDEO_MODE_SHIFT)) & CSI_CR1_VIDEO_MODE_MASK) -/*! @name CEEI - Clear Enable Error Interrupt */ -/*! @{ */ -#define DMA_CEEI_CEEI_MASK (0x1FU) -#define DMA_CEEI_CEEI_SHIFT (0U) -/*! CEEI - Clear Enable Error Interrupt +#define CSI_CR1_EOF_INT_EN_MASK (0x20000000U) +#define CSI_CR1_EOF_INT_EN_SHIFT (29U) +/*! EOF_INT_EN + * 0b0..EOF interrupt is disabled. + * 0b1..EOF interrupt is generated when RX count value is reached. */ -#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) -#define DMA_CEEI_CAEE_MASK (0x40U) -#define DMA_CEEI_CAEE_SHIFT (6U) -/*! CAEE - Clear All Enable Error Interrupts - * 0b0..Write 0 only to the EEI field specified in the CEEI field - * 0b1..Write 0 to all fields in EEI +#define CSI_CR1_EOF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_EOF_INT_EN_SHIFT)) & CSI_CR1_EOF_INT_EN_MASK) + +#define CSI_CR1_EXT_VSYNC_MASK (0x40000000U) +#define CSI_CR1_EXT_VSYNC_SHIFT (30U) +/*! EXT_VSYNC + * 0b0..Internal VSYNC mode + * 0b1..External VSYNC mode */ -#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) -#define DMA_CEEI_NOP_MASK (0x80U) -#define DMA_CEEI_NOP_SHIFT (7U) -/*! NOP - No Op Enable - * 0b0..Normal operation - * 0b1..No operation, ignore the other fields in this register +#define CSI_CR1_EXT_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_EXT_VSYNC_SHIFT)) & CSI_CR1_EXT_VSYNC_MASK) + +#define CSI_CR1_SWAP16_EN_MASK (0x80000000U) +#define CSI_CR1_SWAP16_EN_SHIFT (31U) +/*! SWAP16_EN + * 0b0..Disable swapping + * 0b1..Enable swapping */ -#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) +#define CSI_CR1_SWAP16_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SWAP16_EN_SHIFT)) & CSI_CR1_SWAP16_EN_MASK) /*! @} */ -/*! @name SEEI - Set Enable Error Interrupt */ +/*! @name CR2 - CSI Control Register 2 */ /*! @{ */ -#define DMA_SEEI_SEEI_MASK (0x1FU) -#define DMA_SEEI_SEEI_SHIFT (0U) -/*! SEEI - Set Enable Error Interrupt - */ -#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) -#define DMA_SEEI_SAEE_MASK (0x40U) -#define DMA_SEEI_SAEE_SHIFT (6U) -/*! SAEE - Set All Enable Error Interrupts - * 0b0..Write 1 only to the EEI field specified in the SEEI field - * 0b1..Writes 1 to all fields in EEI - */ -#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) -#define DMA_SEEI_NOP_MASK (0x80U) -#define DMA_SEEI_NOP_SHIFT (7U) -/*! NOP - No Op Enable - * 0b0..Normal operation - * 0b1..No operation, ignore the other fields in this register + +#define CSI_CR2_HSC_MASK (0xFFU) +#define CSI_CR2_HSC_SHIFT (0U) +#define CSI_CR2_HSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_HSC_SHIFT)) & CSI_CR2_HSC_MASK) + +#define CSI_CR2_VSC_MASK (0xFF00U) +#define CSI_CR2_VSC_SHIFT (8U) +#define CSI_CR2_VSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_VSC_SHIFT)) & CSI_CR2_VSC_MASK) + +#define CSI_CR2_LVRM_MASK (0x70000U) +#define CSI_CR2_LVRM_SHIFT (16U) +/*! LVRM + * 0b000..512 x 384 + * 0b001..448 x 336 + * 0b010..384 x 288 + * 0b011..384 x 256 + * 0b100..320 x 240 + * 0b101..288 x 216 + * 0b110..400 x 300 */ -#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) -/*! @} */ +#define CSI_CR2_LVRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_LVRM_SHIFT)) & CSI_CR2_LVRM_MASK) -/*! @name CERQ - Clear Enable Request */ -/*! @{ */ -#define DMA_CERQ_CERQ_MASK (0x1FU) -#define DMA_CERQ_CERQ_SHIFT (0U) -/*! CERQ - Clear Enable Request +#define CSI_CR2_BTS_MASK (0x180000U) +#define CSI_CR2_BTS_SHIFT (19U) +/*! BTS + * 0b00..GR + * 0b01..RG + * 0b10..BG + * 0b11..GB */ -#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) -#define DMA_CERQ_CAER_MASK (0x40U) -#define DMA_CERQ_CAER_SHIFT (6U) -/*! CAER - Clear All Enable Requests - * 0b0..Write 0 to only the ERQ field specified in the CERQ field - * 0b1..Write 0 to all fields in ERQ +#define CSI_CR2_BTS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_BTS_SHIFT)) & CSI_CR2_BTS_MASK) + +#define CSI_CR2_SCE_MASK (0x800000U) +#define CSI_CR2_SCE_SHIFT (23U) +/*! SCE + * 0b0..Skip count disable + * 0b1..Skip count enable */ -#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) -#define DMA_CERQ_NOP_MASK (0x80U) -#define DMA_CERQ_NOP_SHIFT (7U) -/*! NOP - No Op Enable - * 0b0..Normal operation - * 0b1..No operation, ignore the other fields in this register +#define CSI_CR2_SCE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_SCE_SHIFT)) & CSI_CR2_SCE_MASK) + +#define CSI_CR2_AFS_MASK (0x3000000U) +#define CSI_CR2_AFS_SHIFT (24U) +/*! AFS + * 0b00..Abs Diff on consecutive green pixels + * 0b01..Abs Diff on every third green pixels + * 0b1x..Abs Diff on every four green pixels */ -#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) -/*! @} */ +#define CSI_CR2_AFS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_AFS_SHIFT)) & CSI_CR2_AFS_MASK) -/*! @name SERQ - Set Enable Request */ -/*! @{ */ -#define DMA_SERQ_SERQ_MASK (0x1FU) -#define DMA_SERQ_SERQ_SHIFT (0U) -/*! SERQ - Set Enable Request +#define CSI_CR2_DRM_MASK (0x4000000U) +#define CSI_CR2_DRM_SHIFT (26U) +/*! DRM + * 0b0..Stats grid of 8 x 6 + * 0b1..Stats grid of 8 x 12 */ -#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) -#define DMA_SERQ_SAER_MASK (0x40U) -#define DMA_SERQ_SAER_SHIFT (6U) -/*! SAER - Set All Enable Requests - * 0b0..Write 1 to only the ERQ field specified in the SERQ field - * 0b1..Write 1 to all fields in ERQ +#define CSI_CR2_DRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_DRM_SHIFT)) & CSI_CR2_DRM_MASK) + +#define CSI_CR2_DMA_BURST_TYPE_SFF_MASK (0x30000000U) +#define CSI_CR2_DMA_BURST_TYPE_SFF_SHIFT (28U) +/*! DMA_BURST_TYPE_SFF + * 0bx0..INCR8 + * 0b01..INCR4 + * 0b11..INCR16 */ -#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) -#define DMA_SERQ_NOP_MASK (0x80U) -#define DMA_SERQ_NOP_SHIFT (7U) -/*! NOP - No Op Enable - * 0b0..Normal operation - * 0b1..No operation, ignore the other fields in this register +#define CSI_CR2_DMA_BURST_TYPE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CR2_DMA_BURST_TYPE_SFF_MASK) + +#define CSI_CR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U) +#define CSI_CR2_DMA_BURST_TYPE_RFF_SHIFT (30U) +/*! DMA_BURST_TYPE_RFF + * 0bx0..INCR8 + * 0b01..INCR4 + * 0b11..INCR16 */ -#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) +#define CSI_CR2_DMA_BURST_TYPE_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CR2_DMA_BURST_TYPE_RFF_MASK) /*! @} */ -/*! @name CDNE - Clear DONE Status Bit */ +/*! @name CR3 - CSI Control Register 3 */ /*! @{ */ -#define DMA_CDNE_CDNE_MASK (0x1FU) -#define DMA_CDNE_CDNE_SHIFT (0U) -/*! CDNE - Clear DONE field + +#define CSI_CR3_ECC_AUTO_EN_MASK (0x1U) +#define CSI_CR3_ECC_AUTO_EN_SHIFT (0U) +/*! ECC_AUTO_EN + * 0b0..Auto Error correction is disabled. + * 0b1..Auto Error correction is enabled. */ -#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) -#define DMA_CDNE_CADN_MASK (0x40U) -#define DMA_CDNE_CADN_SHIFT (6U) -/*! CADN - Clears All DONE fields - * 0b0..Writes 0 to only the TCDn_CSR[DONE] field specified in the CDNE field - * 0b1..Writes 0 to all bits in TCDn_CSR[DONE] +#define CSI_CR3_ECC_AUTO_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_ECC_AUTO_EN_SHIFT)) & CSI_CR3_ECC_AUTO_EN_MASK) + +#define CSI_CR3_ECC_INT_EN_MASK (0x2U) +#define CSI_CR3_ECC_INT_EN_SHIFT (1U) +/*! ECC_INT_EN + * 0b0..No interrupt is generated when error is detected. Only the status bit ECC_INT is set. + * 0b1..Interrupt is generated when error is detected. */ -#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK) -#define DMA_CDNE_NOP_MASK (0x80U) -#define DMA_CDNE_NOP_SHIFT (7U) -/*! NOP - No Op Enable - * 0b0..Normal operation - * 0b1..No operation; all other fields in this register are ignored. +#define CSI_CR3_ECC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_ECC_INT_EN_SHIFT)) & CSI_CR3_ECC_INT_EN_MASK) + +#define CSI_CR3_ZERO_PACK_EN_MASK (0x4U) +#define CSI_CR3_ZERO_PACK_EN_SHIFT (2U) +/*! ZERO_PACK_EN + * 0b0..Zero packing disabled + * 0b1..Zero packing enabled */ -#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) -/*! @} */ +#define CSI_CR3_ZERO_PACK_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_ZERO_PACK_EN_SHIFT)) & CSI_CR3_ZERO_PACK_EN_MASK) -/*! @name SSRT - Set START Bit */ -/*! @{ */ -#define DMA_SSRT_SSRT_MASK (0x1FU) -#define DMA_SSRT_SSRT_SHIFT (0U) -/*! SSRT - Set START field +#define CSI_CR3_SENSOR_16BITS_MASK (0x8U) +#define CSI_CR3_SENSOR_16BITS_SHIFT (3U) +/*! SENSOR_16BITS + * 0b0..Only one 8-bit sensor is connected. + * 0b1..One 16-bit sensor is connected. */ -#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) -#define DMA_SSRT_SAST_MASK (0x40U) -#define DMA_SSRT_SAST_SHIFT (6U) -/*! SAST - Set All START fields (activates all channels) - * 0b0..Write 1 to only the TCDn_CSR[START] field specified in the SSRT field - * 0b1..Write 1 to all bits in TCDn_CSR[START] +#define CSI_CR3_SENSOR_16BITS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_SENSOR_16BITS_SHIFT)) & CSI_CR3_SENSOR_16BITS_MASK) + +#define CSI_CR3_RxFF_LEVEL_MASK (0x70U) +#define CSI_CR3_RxFF_LEVEL_SHIFT (4U) +/*! RxFF_LEVEL + * 0b000..4 Double words + * 0b001..8 Double words + * 0b010..16 Double words + * 0b011..24 Double words + * 0b100..32 Double words + * 0b101..48 Double words + * 0b110..64 Double words + * 0b111..96 Double words */ -#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK) -#define DMA_SSRT_NOP_MASK (0x80U) -#define DMA_SSRT_NOP_SHIFT (7U) -/*! NOP - No Op Enable - * 0b0..Normal operation - * 0b1..No operation; all other fields in this register are ignored. +#define CSI_CR3_RxFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_RxFF_LEVEL_SHIFT)) & CSI_CR3_RxFF_LEVEL_MASK) + +#define CSI_CR3_HRESP_ERR_EN_MASK (0x80U) +#define CSI_CR3_HRESP_ERR_EN_SHIFT (7U) +/*! HRESP_ERR_EN + * 0b0..Disable hresponse error interrupt + * 0b1..Enable hresponse error interrupt */ -#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) -/*! @} */ +#define CSI_CR3_HRESP_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_HRESP_ERR_EN_SHIFT)) & CSI_CR3_HRESP_ERR_EN_MASK) -/*! @name CERR - Clear Error */ -/*! @{ */ -#define DMA_CERR_CERR_MASK (0x1FU) -#define DMA_CERR_CERR_SHIFT (0U) -/*! CERR - Clear Error Indicator +#define CSI_CR3_STATFF_LEVEL_MASK (0x700U) +#define CSI_CR3_STATFF_LEVEL_SHIFT (8U) +/*! STATFF_LEVEL + * 0b000..4 Double words + * 0b001..8 Double words + * 0b010..12 Double words + * 0b011..16 Double words + * 0b100..24 Double words + * 0b101..32 Double words + * 0b110..48 Double words + * 0b111..64 Double words */ -#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) -#define DMA_CERR_CAEI_MASK (0x40U) -#define DMA_CERR_CAEI_SHIFT (6U) -/*! CAEI - Clear All Error Indicators - * 0b0..Write 0 to only the ERR field specified in the CERR field - * 0b1..Write 0 to all fields in ERR +#define CSI_CR3_STATFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_STATFF_LEVEL_SHIFT)) & CSI_CR3_STATFF_LEVEL_MASK) + +#define CSI_CR3_DMA_REQ_EN_SFF_MASK (0x800U) +#define CSI_CR3_DMA_REQ_EN_SFF_SHIFT (11U) +/*! DMA_REQ_EN_SFF + * 0b0..Disable the dma request + * 0b1..Enable the dma request */ -#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) -#define DMA_CERR_NOP_MASK (0x80U) -#define DMA_CERR_NOP_SHIFT (7U) -/*! NOP - No Op Enable - * 0b0..Normal operation - * 0b1..No operation; all other fields in this register are ignored. +#define CSI_CR3_DMA_REQ_EN_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CR3_DMA_REQ_EN_SFF_MASK) + +#define CSI_CR3_DMA_REQ_EN_RFF_MASK (0x1000U) +#define CSI_CR3_DMA_REQ_EN_RFF_SHIFT (12U) +/*! DMA_REQ_EN_RFF + * 0b0..Disable the dma request + * 0b1..Enable the dma request */ -#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) -/*! @} */ +#define CSI_CR3_DMA_REQ_EN_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CR3_DMA_REQ_EN_RFF_MASK) -/*! @name CINT - Clear Interrupt Request */ -/*! @{ */ -#define DMA_CINT_CINT_MASK (0x1FU) -#define DMA_CINT_CINT_SHIFT (0U) -/*! CINT - Clear Interrupt Request +#define CSI_CR3_DMA_REFLASH_SFF_MASK (0x2000U) +#define CSI_CR3_DMA_REFLASH_SFF_SHIFT (13U) +/*! DMA_REFLASH_SFF + * 0b0..No reflashing + * 0b1..Reflash the embedded DMA controller */ -#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) -#define DMA_CINT_CAIR_MASK (0x40U) -#define DMA_CINT_CAIR_SHIFT (6U) -/*! CAIR - Clear All Interrupt Requests - * 0b0..Clear only the INT field specified in the CINT field - * 0b1..Clear all bits in INT +#define CSI_CR3_DMA_REFLASH_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CR3_DMA_REFLASH_SFF_MASK) + +#define CSI_CR3_DMA_REFLASH_RFF_MASK (0x4000U) +#define CSI_CR3_DMA_REFLASH_RFF_SHIFT (14U) +/*! DMA_REFLASH_RFF + * 0b0..No reflashing + * 0b1..Reflash the embedded DMA controller */ -#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) -#define DMA_CINT_NOP_MASK (0x80U) -#define DMA_CINT_NOP_SHIFT (7U) -/*! NOP - No Op Enable - * 0b0..Normal operation - * 0b1..No operation; all other fields in this register are ignored. +#define CSI_CR3_DMA_REFLASH_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CR3_DMA_REFLASH_RFF_MASK) + +#define CSI_CR3_FRMCNT_RST_MASK (0x8000U) +#define CSI_CR3_FRMCNT_RST_SHIFT (15U) +/*! FRMCNT_RST + * 0b0..Do not reset + * 0b1..Reset frame counter immediately */ -#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) +#define CSI_CR3_FRMCNT_RST(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_FRMCNT_RST_SHIFT)) & CSI_CR3_FRMCNT_RST_MASK) + +#define CSI_CR3_FRMCNT_MASK (0xFFFF0000U) +#define CSI_CR3_FRMCNT_SHIFT (16U) +#define CSI_CR3_FRMCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_FRMCNT_SHIFT)) & CSI_CR3_FRMCNT_MASK) /*! @} */ -/*! @name INT - Interrupt Request */ +/*! @name STATFIFO - CSI Statistic FIFO Register */ /*! @{ */ -#define DMA_INT_INT0_MASK (0x1U) -#define DMA_INT_INT0_SHIFT (0U) -/*! INT0 - Interrupt Request 0 - * 0b0..The interrupt request for channel 0 is cleared - * 0b1..The interrupt request for channel 0 is active + +#define CSI_STATFIFO_STAT_MASK (0xFFFFFFFFU) +#define CSI_STATFIFO_STAT_SHIFT (0U) +#define CSI_STATFIFO_STAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_STATFIFO_STAT_SHIFT)) & CSI_STATFIFO_STAT_MASK) +/*! @} */ + +/*! @name RFIFO - CSI RX FIFO Register */ +/*! @{ */ + +#define CSI_RFIFO_IMAGE_MASK (0xFFFFFFFFU) +#define CSI_RFIFO_IMAGE_SHIFT (0U) +#define CSI_RFIFO_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_RFIFO_IMAGE_SHIFT)) & CSI_RFIFO_IMAGE_MASK) +/*! @} */ + +/*! @name RXCNT - CSI RX Count Register */ +/*! @{ */ + +#define CSI_RXCNT_RXCNT_MASK (0x3FFFFFU) +#define CSI_RXCNT_RXCNT_SHIFT (0U) +#define CSI_RXCNT_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_RXCNT_RXCNT_SHIFT)) & CSI_RXCNT_RXCNT_MASK) +/*! @} */ + +/*! @name SR - CSI Status Register */ +/*! @{ */ + +#define CSI_SR_DRDY_MASK (0x1U) +#define CSI_SR_DRDY_SHIFT (0U) +/*! DRDY + * 0b0..No data (word) is ready + * 0b1..At least 1 datum (word) is ready in RXFIFO. */ -#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) -#define DMA_INT_INT1_MASK (0x2U) -#define DMA_INT_INT1_SHIFT (1U) -/*! INT1 - Interrupt Request 1 - * 0b0..The interrupt request for channel 1 is cleared - * 0b1..The interrupt request for channel 1 is active +#define CSI_SR_DRDY(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_DRDY_SHIFT)) & CSI_SR_DRDY_MASK) + +#define CSI_SR_ECC_INT_MASK (0x2U) +#define CSI_SR_ECC_INT_SHIFT (1U) +/*! ECC_INT + * 0b0..No error detected + * 0b1..Error is detected in BT.656 coding */ -#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK) -#define DMA_INT_INT2_MASK (0x4U) -#define DMA_INT_INT2_SHIFT (2U) -/*! INT2 - Interrupt Request 2 - * 0b0..The interrupt request for channel 2 is cleared - * 0b1..The interrupt request for channel 2 is active +#define CSI_SR_ECC_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_ECC_INT_SHIFT)) & CSI_SR_ECC_INT_MASK) + +#define CSI_SR_HISTOGRAM_CALC_DONE_INT_MASK (0x4U) +#define CSI_SR_HISTOGRAM_CALC_DONE_INT_SHIFT (2U) +/*! HISTOGRAM_CALC_DONE_INT + * 0b0..Histogram calculation is not finished + * 0b1..Histogram calculation is done and driver can access the PIXEL_COUNTERS(CSI_CSICR21~CSI_CSICR276) to get the gray level */ -#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK) -#define DMA_INT_INT3_MASK (0x8U) -#define DMA_INT_INT3_SHIFT (3U) -/*! INT3 - Interrupt Request 3 - * 0b0..The interrupt request for channel 3 is cleared - * 0b1..The interrupt request for channel 3 is active +#define CSI_SR_HISTOGRAM_CALC_DONE_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_HISTOGRAM_CALC_DONE_INT_SHIFT)) & CSI_SR_HISTOGRAM_CALC_DONE_INT_MASK) + +#define CSI_SR_HRESP_ERR_INT_MASK (0x80U) +#define CSI_SR_HRESP_ERR_INT_SHIFT (7U) +/*! HRESP_ERR_INT + * 0b0..No hresponse error. + * 0b1..Hresponse error is detected. */ -#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK) -#define DMA_INT_INT4_MASK (0x10U) -#define DMA_INT_INT4_SHIFT (4U) -/*! INT4 - Interrupt Request 4 - * 0b0..The interrupt request for channel 4 is cleared - * 0b1..The interrupt request for channel 4 is active +#define CSI_SR_HRESP_ERR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_HRESP_ERR_INT_SHIFT)) & CSI_SR_HRESP_ERR_INT_MASK) + +#define CSI_SR_COF_INT_MASK (0x2000U) +#define CSI_SR_COF_INT_SHIFT (13U) +/*! COF_INT + * 0b0..Video field has no change. + * 0b1..Change of video field is detected. */ -#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK) -#define DMA_INT_INT5_MASK (0x20U) -#define DMA_INT_INT5_SHIFT (5U) -/*! INT5 - Interrupt Request 5 - * 0b0..The interrupt request for channel 5 is cleared - * 0b1..The interrupt request for channel 5 is active +#define CSI_SR_COF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_COF_INT_SHIFT)) & CSI_SR_COF_INT_MASK) + +#define CSI_SR_F1_INT_MASK (0x4000U) +#define CSI_SR_F1_INT_SHIFT (14U) +/*! F1_INT + * 0b0..Field 1 of video is not detected. + * 0b1..Field 1 of video is about to start. */ -#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK) -#define DMA_INT_INT6_MASK (0x40U) -#define DMA_INT_INT6_SHIFT (6U) -/*! INT6 - Interrupt Request 6 - * 0b0..The interrupt request for channel 6 is cleared - * 0b1..The interrupt request for channel 6 is active +#define CSI_SR_F1_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_F1_INT_SHIFT)) & CSI_SR_F1_INT_MASK) + +#define CSI_SR_F2_INT_MASK (0x8000U) +#define CSI_SR_F2_INT_SHIFT (15U) +/*! F2_INT + * 0b0..Field 2 of video is not detected + * 0b1..Field 2 of video is about to start */ -#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK) -#define DMA_INT_INT7_MASK (0x80U) -#define DMA_INT_INT7_SHIFT (7U) -/*! INT7 - Interrupt Request 7 - * 0b0..The interrupt request for channel 7 is cleared - * 0b1..The interrupt request for channel 7 is active +#define CSI_SR_F2_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_F2_INT_SHIFT)) & CSI_SR_F2_INT_MASK) + +#define CSI_SR_SOF_INT_MASK (0x10000U) +#define CSI_SR_SOF_INT_SHIFT (16U) +/*! SOF_INT + * 0b0..SOF is not detected. + * 0b1..SOF is detected. */ -#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK) -#define DMA_INT_INT8_MASK (0x100U) -#define DMA_INT_INT8_SHIFT (8U) -/*! INT8 - Interrupt Request 8 - * 0b0..The interrupt request for channel 8 is cleared - * 0b1..The interrupt request for channel 8 is active +#define CSI_SR_SOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_SOF_INT_SHIFT)) & CSI_SR_SOF_INT_MASK) + +#define CSI_SR_EOF_INT_MASK (0x20000U) +#define CSI_SR_EOF_INT_SHIFT (17U) +/*! EOF_INT + * 0b0..EOF is not detected. + * 0b1..EOF is detected. */ -#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK) -#define DMA_INT_INT9_MASK (0x200U) -#define DMA_INT_INT9_SHIFT (9U) -/*! INT9 - Interrupt Request 9 - * 0b0..The interrupt request for channel 9 is cleared - * 0b1..The interrupt request for channel 9 is active +#define CSI_SR_EOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_EOF_INT_SHIFT)) & CSI_SR_EOF_INT_MASK) + +#define CSI_SR_RxFF_INT_MASK (0x40000U) +#define CSI_SR_RxFF_INT_SHIFT (18U) +/*! RxFF_INT + * 0b0..RxFIFO is not full. + * 0b1..RxFIFO is full. */ -#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK) -#define DMA_INT_INT10_MASK (0x400U) -#define DMA_INT_INT10_SHIFT (10U) -/*! INT10 - Interrupt Request 10 - * 0b0..The interrupt request for channel 10 is cleared - * 0b1..The interrupt request for channel 10 is active +#define CSI_SR_RxFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_RxFF_INT_SHIFT)) & CSI_SR_RxFF_INT_MASK) + +#define CSI_SR_DMA_TSF_DONE_FB1_MASK (0x80000U) +#define CSI_SR_DMA_TSF_DONE_FB1_SHIFT (19U) +/*! DMA_TSF_DONE_FB1 + * 0b0..DMA transfer is not completed. + * 0b1..DMA transfer is completed. */ -#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK) -#define DMA_INT_INT11_MASK (0x800U) -#define DMA_INT_INT11_SHIFT (11U) -/*! INT11 - Interrupt Request 11 - * 0b0..The interrupt request for channel 11 is cleared - * 0b1..The interrupt request for channel 11 is active +#define CSI_SR_DMA_TSF_DONE_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_SR_DMA_TSF_DONE_FB1_MASK) + +#define CSI_SR_DMA_TSF_DONE_FB2_MASK (0x100000U) +#define CSI_SR_DMA_TSF_DONE_FB2_SHIFT (20U) +/*! DMA_TSF_DONE_FB2 + * 0b0..DMA transfer is not completed. + * 0b1..DMA transfer is completed. */ -#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK) -#define DMA_INT_INT12_MASK (0x1000U) -#define DMA_INT_INT12_SHIFT (12U) -/*! INT12 - Interrupt Request 12 - * 0b0..The interrupt request for channel 12 is cleared - * 0b1..The interrupt request for channel 12 is active +#define CSI_SR_DMA_TSF_DONE_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_SR_DMA_TSF_DONE_FB2_MASK) + +#define CSI_SR_STATFF_INT_MASK (0x200000U) +#define CSI_SR_STATFF_INT_SHIFT (21U) +/*! STATFF_INT + * 0b0..STATFIFO is not full. + * 0b1..STATFIFO is full. */ -#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK) -#define DMA_INT_INT13_MASK (0x2000U) -#define DMA_INT_INT13_SHIFT (13U) -/*! INT13 - Interrupt Request 13 - * 0b0..The interrupt request for channel 13 is cleared - * 0b1..The interrupt request for channel 13 is active +#define CSI_SR_STATFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_STATFF_INT_SHIFT)) & CSI_SR_STATFF_INT_MASK) + +#define CSI_SR_DMA_TSF_DONE_SFF_MASK (0x400000U) +#define CSI_SR_DMA_TSF_DONE_SFF_SHIFT (22U) +/*! DMA_TSF_DONE_SFF + * 0b0..DMA transfer is not completed. + * 0b1..DMA transfer is completed. */ -#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK) -#define DMA_INT_INT14_MASK (0x4000U) -#define DMA_INT_INT14_SHIFT (14U) -/*! INT14 - Interrupt Request 14 - * 0b0..The interrupt request for channel 14 is cleared - * 0b1..The interrupt request for channel 14 is active +#define CSI_SR_DMA_TSF_DONE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_SR_DMA_TSF_DONE_SFF_MASK) + +#define CSI_SR_RF_OR_INT_MASK (0x1000000U) +#define CSI_SR_RF_OR_INT_SHIFT (24U) +/*! RF_OR_INT + * 0b0..RXFIFO has not overflowed. + * 0b1..RXFIFO has overflowed. */ -#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK) -#define DMA_INT_INT15_MASK (0x8000U) -#define DMA_INT_INT15_SHIFT (15U) -/*! INT15 - Interrupt Request 15 - * 0b0..The interrupt request for channel 15 is cleared - * 0b1..The interrupt request for channel 15 is active +#define CSI_SR_RF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_RF_OR_INT_SHIFT)) & CSI_SR_RF_OR_INT_MASK) + +#define CSI_SR_SF_OR_INT_MASK (0x2000000U) +#define CSI_SR_SF_OR_INT_SHIFT (25U) +/*! SF_OR_INT + * 0b0..STATFIFO has not overflowed. + * 0b1..STATFIFO has overflowed. */ -#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK) -#define DMA_INT_INT16_MASK (0x10000U) -#define DMA_INT_INT16_SHIFT (16U) -/*! INT16 - Interrupt Request 16 - * 0b0..The interrupt request for channel 16 is cleared - * 0b1..The interrupt request for channel 16 is active +#define CSI_SR_SF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_SF_OR_INT_SHIFT)) & CSI_SR_SF_OR_INT_MASK) + +#define CSI_SR_DMA_FIELD1_DONE_MASK (0x4000000U) +#define CSI_SR_DMA_FIELD1_DONE_SHIFT (26U) +#define CSI_SR_DMA_FIELD1_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_FIELD1_DONE_SHIFT)) & CSI_SR_DMA_FIELD1_DONE_MASK) + +#define CSI_SR_DMA_FIELD0_DONE_MASK (0x8000000U) +#define CSI_SR_DMA_FIELD0_DONE_SHIFT (27U) +#define CSI_SR_DMA_FIELD0_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_FIELD0_DONE_SHIFT)) & CSI_SR_DMA_FIELD0_DONE_MASK) + +#define CSI_SR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U) +#define CSI_SR_BASEADDR_CHHANGE_ERROR_SHIFT (28U) +#define CSI_SR_BASEADDR_CHHANGE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_SR_BASEADDR_CHHANGE_ERROR_MASK) +/*! @} */ + +/*! @name DMASA_STATFIFO - CSI DMA Start Address Register - for STATFIFO */ +/*! @{ */ + +#define CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU) +#define CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U) +#define CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_MASK) +/*! @} */ + +/*! @name DMATS_STATFIFO - CSI DMA Transfer Size Register - for STATFIFO */ +/*! @{ */ + +#define CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU) +#define CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U) +#define CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK) +/*! @} */ + +/*! @name DMASA_FB1 - CSI DMA Start Address Register - for Frame Buffer1 */ +/*! @{ */ + +#define CSI_DMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU) +#define CSI_DMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U) +#define CSI_DMASA_FB1_DMA_START_ADDR_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_DMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_DMASA_FB1_DMA_START_ADDR_FB1_MASK) +/*! @} */ + +/*! @name DMASA_FB2 - CSI DMA Transfer Size Register - for Frame Buffer2 */ +/*! @{ */ + +#define CSI_DMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU) +#define CSI_DMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U) +#define CSI_DMASA_FB2_DMA_START_ADDR_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_DMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_DMASA_FB2_DMA_START_ADDR_FB2_MASK) +/*! @} */ + +/*! @name FBUF_PARA - CSI Frame Buffer Parameter Register */ +/*! @{ */ + +#define CSI_FBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU) +#define CSI_FBUF_PARA_FBUF_STRIDE_SHIFT (0U) +#define CSI_FBUF_PARA_FBUF_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_FBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_FBUF_PARA_FBUF_STRIDE_MASK) + +#define CSI_FBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U) +#define CSI_FBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U) +#define CSI_FBUF_PARA_DEINTERLACE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_FBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_FBUF_PARA_DEINTERLACE_STRIDE_MASK) +/*! @} */ + +/*! @name IMAG_PARA - CSI Image Parameter Register */ +/*! @{ */ + +#define CSI_IMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU) +#define CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT (0U) +#define CSI_IMAG_PARA_IMAGE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_IMAG_PARA_IMAGE_HEIGHT_MASK) + +#define CSI_IMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U) +#define CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT (16U) +#define CSI_IMAG_PARA_IMAGE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_IMAG_PARA_IMAGE_WIDTH_MASK) +/*! @} */ + +/*! @name CR18 - CSI Control Register 18 */ +/*! @{ */ + +#define CSI_CR18_NTSC_EN_MASK (0x1U) +#define CSI_CR18_NTSC_EN_SHIFT (0U) +/*! NTSC_EN + * 0b0..PAL + * 0b1..NTSC */ -#define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK) -#define DMA_INT_INT17_MASK (0x20000U) -#define DMA_INT_INT17_SHIFT (17U) -/*! INT17 - Interrupt Request 17 - * 0b0..The interrupt request for channel 17 is cleared - * 0b1..The interrupt request for channel 17 is active +#define CSI_CR18_NTSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_NTSC_EN_SHIFT)) & CSI_CR18_NTSC_EN_MASK) + +#define CSI_CR18_TVDECODER_IN_EN_MASK (0x2U) +#define CSI_CR18_TVDECODER_IN_EN_SHIFT (1U) +#define CSI_CR18_TVDECODER_IN_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_TVDECODER_IN_EN_SHIFT)) & CSI_CR18_TVDECODER_IN_EN_MASK) + +#define CSI_CR18_DEINTERLACE_EN_MASK (0x4U) +#define CSI_CR18_DEINTERLACE_EN_SHIFT (2U) +/*! DEINTERLACE_EN + * 0b0..Deinterlace disabled + * 0b1..Deinterlace enabled */ -#define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK) -#define DMA_INT_INT18_MASK (0x40000U) -#define DMA_INT_INT18_SHIFT (18U) -/*! INT18 - Interrupt Request 18 - * 0b0..The interrupt request for channel 18 is cleared - * 0b1..The interrupt request for channel 18 is active +#define CSI_CR18_DEINTERLACE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_DEINTERLACE_EN_SHIFT)) & CSI_CR18_DEINTERLACE_EN_MASK) + +#define CSI_CR18_PARALLEL24_EN_MASK (0x8U) +#define CSI_CR18_PARALLEL24_EN_SHIFT (3U) +/*! PARALLEL24_EN + * 0b0..Input is disabled + * 0b1..Input is enabled */ -#define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK) -#define DMA_INT_INT19_MASK (0x80000U) -#define DMA_INT_INT19_SHIFT (19U) -/*! INT19 - Interrupt Request 19 - * 0b0..The interrupt request for channel 19 is cleared - * 0b1..The interrupt request for channel 19 is active +#define CSI_CR18_PARALLEL24_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_PARALLEL24_EN_SHIFT)) & CSI_CR18_PARALLEL24_EN_MASK) + +#define CSI_CR18_BASEADDR_SWITCH_EN_MASK (0x10U) +#define CSI_CR18_BASEADDR_SWITCH_EN_SHIFT (4U) +#define CSI_CR18_BASEADDR_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CR18_BASEADDR_SWITCH_EN_MASK) + +#define CSI_CR18_BASEADDR_SWITCH_SEL_MASK (0x20U) +#define CSI_CR18_BASEADDR_SWITCH_SEL_SHIFT (5U) +/*! BASEADDR_SWITCH_SEL + * 0b0..Switching base address at the edge of the vsync + * 0b1..Switching base address at the edge of the first data of each frame */ -#define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK) -#define DMA_INT_INT20_MASK (0x100000U) -#define DMA_INT_INT20_SHIFT (20U) -/*! INT20 - Interrupt Request 20 - * 0b0..The interrupt request for channel 20 is cleared - * 0b1..The interrupt request for channel 20 is active +#define CSI_CR18_BASEADDR_SWITCH_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CR18_BASEADDR_SWITCH_SEL_MASK) + +#define CSI_CR18_FIELD0_DONE_IE_MASK (0x40U) +#define CSI_CR18_FIELD0_DONE_IE_SHIFT (6U) +/*! FIELD0_DONE_IE + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled */ -#define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK) -#define DMA_INT_INT21_MASK (0x200000U) -#define DMA_INT_INT21_SHIFT (21U) -/*! INT21 - Interrupt Request 21 - * 0b0..The interrupt request for channel 21 is cleared - * 0b1..The interrupt request for channel 21 is active +#define CSI_CR18_FIELD0_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_FIELD0_DONE_IE_SHIFT)) & CSI_CR18_FIELD0_DONE_IE_MASK) + +#define CSI_CR18_DMA_FIELD1_DONE_IE_MASK (0x80U) +#define CSI_CR18_DMA_FIELD1_DONE_IE_SHIFT (7U) +/*! DMA_FIELD1_DONE_IE + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled */ -#define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK) -#define DMA_INT_INT22_MASK (0x400000U) -#define DMA_INT_INT22_SHIFT (22U) -/*! INT22 - Interrupt Request 22 - * 0b0..The interrupt request for channel 22 is cleared - * 0b1..The interrupt request for channel 22 is active +#define CSI_CR18_DMA_FIELD1_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CR18_DMA_FIELD1_DONE_IE_MASK) + +#define CSI_CR18_LAST_DMA_REQ_SEL_MASK (0x100U) +#define CSI_CR18_LAST_DMA_REQ_SEL_SHIFT (8U) +/*! LAST_DMA_REQ_SEL + * 0b0..fifo_full_level + * 0b1..hburst_length */ -#define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK) -#define DMA_INT_INT23_MASK (0x800000U) -#define DMA_INT_INT23_SHIFT (23U) -/*! INT23 - Interrupt Request 23 - * 0b0..The interrupt request for channel 23 is cleared - * 0b1..The interrupt request for channel 23 is active +#define CSI_CR18_LAST_DMA_REQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CR18_LAST_DMA_REQ_SEL_MASK) + +#define CSI_CR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U) +#define CSI_CR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U) +/*! BASEADDR_CHANGE_ERROR_IE + * 0b0..Interrupt disabled + * 0b1..Interrupt enabled */ -#define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK) -#define DMA_INT_INT24_MASK (0x1000000U) -#define DMA_INT_INT24_SHIFT (24U) -/*! INT24 - Interrupt Request 24 - * 0b0..The interrupt request for channel 24 is cleared - * 0b1..The interrupt request for channel 24 is active +#define CSI_CR18_BASEADDR_CHANGE_ERROR_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CR18_BASEADDR_CHANGE_ERROR_IE_MASK) + +#define CSI_CR18_RGB888A_FORMAT_SEL_MASK (0x400U) +#define CSI_CR18_RGB888A_FORMAT_SEL_SHIFT (10U) +/*! RGB888A_FORMAT_SEL + * 0b0..{8'h0, data[23:0]} + * 0b1..{data[23:0], 8'h0} */ -#define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK) -#define DMA_INT_INT25_MASK (0x2000000U) -#define DMA_INT_INT25_SHIFT (25U) +#define CSI_CR18_RGB888A_FORMAT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CR18_RGB888A_FORMAT_SEL_MASK) + +#define CSI_CR18_AHB_HPROT_MASK (0xF000U) +#define CSI_CR18_AHB_HPROT_SHIFT (12U) +#define CSI_CR18_AHB_HPROT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_AHB_HPROT_SHIFT)) & CSI_CR18_AHB_HPROT_MASK) + +#define CSI_CR18_MASK_OPTION_MASK (0xC0000U) +#define CSI_CR18_MASK_OPTION_SHIFT (18U) +/*! MASK_OPTION + * 0b00..Writing to memory (OCRAM or external DDR) from first completely frame, when using this option, the CSI_ENABLE should be 1. + * 0b01..Writing to memory when CSI_ENABLE is 1. + * 0b10..Writing to memory from second completely frame, when using this option, the CSI_ENABLE should be 1. + * 0b11..Writing to memory when data comes in, not matter the CSI_ENABLE is 1 or 0. + */ +#define CSI_CR18_MASK_OPTION(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_MASK_OPTION_SHIFT)) & CSI_CR18_MASK_OPTION_MASK) + +#define CSI_CR18_MIPI_DOUBLE_CMPNT_MASK (0x100000U) +#define CSI_CR18_MIPI_DOUBLE_CMPNT_SHIFT (20U) +/*! MIPI_DOUBLE_CMPNT + * 0b0..Single component per clock cycle (half pixel per clock cycle) + * 0b1..Double component per clock cycle (a pixel per clock cycle) + */ +#define CSI_CR18_MIPI_DOUBLE_CMPNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_MIPI_DOUBLE_CMPNT_SHIFT)) & CSI_CR18_MIPI_DOUBLE_CMPNT_MASK) + +#define CSI_CR18_MIPI_YU_SWAP_MASK (0x200000U) +#define CSI_CR18_MIPI_YU_SWAP_SHIFT (21U) +/*! MIPI_YU_SWAP - It only works in MIPI CSI YUV422 double component mode. + */ +#define CSI_CR18_MIPI_YU_SWAP(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_MIPI_YU_SWAP_SHIFT)) & CSI_CR18_MIPI_YU_SWAP_MASK) + +#define CSI_CR18_DATA_FROM_MIPI_MASK (0x400000U) +#define CSI_CR18_DATA_FROM_MIPI_SHIFT (22U) +/*! DATA_FROM_MIPI + * 0b0..Data from parallel sensor + * 0b1..Data from MIPI + */ +#define CSI_CR18_DATA_FROM_MIPI(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_DATA_FROM_MIPI_SHIFT)) & CSI_CR18_DATA_FROM_MIPI_MASK) + +#define CSI_CR18_LINE_STRIDE_EN_MASK (0x1000000U) +#define CSI_CR18_LINE_STRIDE_EN_SHIFT (24U) +#define CSI_CR18_LINE_STRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_LINE_STRIDE_EN_SHIFT)) & CSI_CR18_LINE_STRIDE_EN_MASK) + +#define CSI_CR18_MIPI_DATA_FORMAT_MASK (0x7E000000U) +#define CSI_CR18_MIPI_DATA_FORMAT_SHIFT (25U) +/*! MIPI_DATA_FORMAT - Image Data Format + */ +#define CSI_CR18_MIPI_DATA_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_MIPI_DATA_FORMAT_SHIFT)) & CSI_CR18_MIPI_DATA_FORMAT_MASK) + +#define CSI_CR18_CSI_ENABLE_MASK (0x80000000U) +#define CSI_CR18_CSI_ENABLE_SHIFT (31U) +#define CSI_CR18_CSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_CSI_ENABLE_SHIFT)) & CSI_CR18_CSI_ENABLE_MASK) +/*! @} */ + +/*! @name CR19 - CSI Control Register 19 */ +/*! @{ */ + +#define CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU) +#define CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U) +#define CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK) +/*! @} */ + +/*! @name CR20 - CSI Control Register 20 */ +/*! @{ */ + +#define CSI_CR20_THRESHOLD_MASK (0xFFU) +#define CSI_CR20_THRESHOLD_SHIFT (0U) +#define CSI_CR20_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR20_THRESHOLD_SHIFT)) & CSI_CR20_THRESHOLD_MASK) + +#define CSI_CR20_BINARY_EN_MASK (0x100U) +#define CSI_CR20_BINARY_EN_SHIFT (8U) +/*! BINARY_EN + * 0b0..Output is Y8 format(8 bits each pixel) + * 0b1..Output is Y1 format(1 bit each pixel) + */ +#define CSI_CR20_BINARY_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR20_BINARY_EN_SHIFT)) & CSI_CR20_BINARY_EN_MASK) + +#define CSI_CR20_QR_DATA_FORMAT_MASK (0xE00U) +#define CSI_CR20_QR_DATA_FORMAT_SHIFT (9U) +/*! QR_DATA_FORMAT + * 0b000..YU YV one cycle per 1 pixel input + * 0b001..UY VY one cycle per1 pixel input + * 0b010..Y U Y V two cycles per 1 pixel input + * 0b011..U Y V Y two cycles per 1 pixel input + * 0b100..YUV one cycle per 1 pixel input + * 0b101..Y U V three cycles per 1 pixel input + */ +#define CSI_CR20_QR_DATA_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR20_QR_DATA_FORMAT_SHIFT)) & CSI_CR20_QR_DATA_FORMAT_MASK) + +#define CSI_CR20_BIG_END_MASK (0x1000U) +#define CSI_CR20_BIG_END_SHIFT (12U) +/*! BIG_END + * 0b0..The newest (most recent) data will be assigned the lowest position when store to memory. + * 0b1..The newest (most recent) data will be assigned the highest position when store to memory. + */ +#define CSI_CR20_BIG_END(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR20_BIG_END_SHIFT)) & CSI_CR20_BIG_END_MASK) + +#define CSI_CR20_10BIT_NEW_EN_MASK (0x20000000U) +#define CSI_CR20_10BIT_NEW_EN_SHIFT (29U) +/*! 10BIT_NEW_EN + * 0b0..When input 8bits data, it will use the data[9:2] + * 0b1..If input is 10bits data, it will use the data[7:0] (optional) + */ +#define CSI_CR20_10BIT_NEW_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR20_10BIT_NEW_EN_SHIFT)) & CSI_CR20_10BIT_NEW_EN_MASK) + +#define CSI_CR20_HISTOGRAM_EN_MASK (0x40000000U) +#define CSI_CR20_HISTOGRAM_EN_SHIFT (30U) +/*! HISTOGRAM_EN + * 0b0..Histogram disable + * 0b1..Histogram enable + */ +#define CSI_CR20_HISTOGRAM_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR20_HISTOGRAM_EN_SHIFT)) & CSI_CR20_HISTOGRAM_EN_MASK) + +#define CSI_CR20_QRCODE_EN_MASK (0x80000000U) +#define CSI_CR20_QRCODE_EN_SHIFT (31U) +/*! QRCODE_EN + * 0b0..Normal mode + * 0b1..Gray scale mode + */ +#define CSI_CR20_QRCODE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR20_QRCODE_EN_SHIFT)) & CSI_CR20_QRCODE_EN_MASK) +/*! @} */ + +/*! @name CR - CSI Control Register */ +/*! @{ */ + +#define CSI_CR_PIXEL_COUNTERS_MASK (0xFFFFFFU) +#define CSI_CR_PIXEL_COUNTERS_SHIFT (0U) +#define CSI_CR_PIXEL_COUNTERS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR_PIXEL_COUNTERS_SHIFT)) & CSI_CR_PIXEL_COUNTERS_MASK) +/*! @} */ + +/* The count of CSI_CR */ +#define CSI_CR_COUNT (256U) + + +/*! + * @} + */ /* end of group CSI_Register_Masks */ + + +/* CSI - Peripheral instance base addresses */ +/** Peripheral CSI base address */ +#define CSI_BASE (0x40800000u) +/** Peripheral CSI base pointer */ +#define CSI ((CSI_Type *)CSI_BASE) +/** Array initializer of CSI peripheral base addresses */ +#define CSI_BASE_ADDRS { CSI_BASE } +/** Array initializer of CSI peripheral base pointers */ +#define CSI_BASE_PTRS { CSI } +/** Interrupt vectors for the CSI peripheral type */ +#define CSI_IRQS { CSI_IRQn } +/* Backward compatibility */ +#define CSI_CSICR1_PIXEL_BIT_MASK CSI_CR1_PIXEL_BIT_MASK +#define CSI_CSICR1_PIXEL_BIT_SHIFT CSI_CR1_PIXEL_BIT_SHIFT +#define CSI_CSICR1_PIXEL_BIT(x) CSI_CR1_PIXEL_BIT(x) +#define CSI_CSICR1_REDGE_MASK CSI_CR1_REDGE_MASK +#define CSI_CSICR1_REDGE_SHIFT CSI_CR1_REDGE_SHIFT +#define CSI_CSICR1_REDGE(x) CSI_CR1_REDGE(x) +#define CSI_CSICR1_INV_PCLK_MASK CSI_CR1_INV_PCLK_MASK +#define CSI_CSICR1_INV_PCLK_SHIFT CSI_CR1_INV_PCLK_SHIFT +#define CSI_CSICR1_INV_PCLK(x) CSI_CR1_INV_PCLK(x) +#define CSI_CSICR1_INV_DATA_MASK CSI_CR1_INV_DATA_MASK +#define CSI_CSICR1_INV_DATA_SHIFT CSI_CR1_INV_DATA_SHIFT +#define CSI_CSICR1_INV_DATA(x) CSI_CR1_INV_DATA(x) +#define CSI_CSICR1_GCLK_MODE_MASK CSI_CR1_GCLK_MODE_MASK +#define CSI_CSICR1_GCLK_MODE_SHIFT CSI_CR1_GCLK_MODE_SHIFT +#define CSI_CSICR1_GCLK_MODE(x) CSI_CR1_GCLK_MODE(x) +#define CSI_CSICR1_CLR_RXFIFO_MASK CSI_CR1_CLR_RXFIFO_MASK +#define CSI_CSICR1_CLR_RXFIFO_SHIFT CSI_CR1_CLR_RXFIFO_SHIFT +#define CSI_CSICR1_CLR_RXFIFO(x) CSI_CR1_CLR_RXFIFO(x) +#define CSI_CSICR1_CLR_STATFIFO_MASK CSI_CR1_CLR_STATFIFO_MASK +#define CSI_CSICR1_CLR_STATFIFO_SHIFT CSI_CR1_CLR_STATFIFO_SHIFT +#define CSI_CSICR1_CLR_STATFIFO(x) CSI_CR1_CLR_STATFIFO(x) +#define CSI_CSICR1_PACK_DIR_MASK CSI_CR1_PACK_DIR_MASK +#define CSI_CSICR1_PACK_DIR_SHIFT CSI_CR1_PACK_DIR_SHIFT +#define CSI_CSICR1_PACK_DIR(x) CSI_CR1_PACK_DIR(x) +#define CSI_CSICR1_FCC_MASK CSI_CR1_FCC_MASK +#define CSI_CSICR1_FCC_SHIFT CSI_CR1_FCC_SHIFT +#define CSI_CSICR1_FCC(x) CSI_CR1_FCC(x) +#define CSI_CSICR1_CCIR_EN_MASK CSI_CR1_CCIR_EN_MASK +#define CSI_CSICR1_CCIR_EN_SHIFT CSI_CR1_CCIR_EN_SHIFT +#define CSI_CSICR1_CCIR_EN(x) CSI_CR1_CCIR_EN(x) +#define CSI_CSICR1_HSYNC_POL_MASK CSI_CR1_HSYNC_POL_MASK +#define CSI_CSICR1_HSYNC_POL_SHIFT CSI_CR1_HSYNC_POL_SHIFT +#define CSI_CSICR1_HSYNC_POL(x) CSI_CR1_HSYNC_POL(x) +#define CSI_CSICR1_HISTOGRAM_CALC_DONE_IE_MASK CSI_CR1_HISTOGRAM_CALC_DONE_IE_MASK +#define CSI_CSICR1_HISTOGRAM_CALC_DONE_IE_SHIFT CSI_CR1_HISTOGRAM_CALC_DONE_IE_SHIFT +#define CSI_CSICR1_HISTOGRAM_CALC_DONE_IE(x) CSI_CR1_HISTOGRAM_CALC_DONE_IE(x) +#define CSI_CSICR1_SOF_INTEN_MASK CSI_CR1_SOF_INTEN_MASK +#define CSI_CSICR1_SOF_INTEN_SHIFT CSI_CR1_SOF_INTEN_SHIFT +#define CSI_CSICR1_SOF_INTEN(x) CSI_CR1_SOF_INTEN(x) +#define CSI_CSICR1_SOF_POL_MASK CSI_CR1_SOF_POL_MASK +#define CSI_CSICR1_SOF_POL_SHIFT CSI_CR1_SOF_POL_SHIFT +#define CSI_CSICR1_SOF_POL(x) CSI_CR1_SOF_POL(x) +#define CSI_CSICR1_RXFF_INTEN_MASK CSI_CR1_RXFF_INTEN_MASK +#define CSI_CSICR1_RXFF_INTEN_SHIFT CSI_CR1_RXFF_INTEN_SHIFT +#define CSI_CSICR1_RXFF_INTEN(x) CSI_CR1_RXFF_INTEN(x) +#define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK CSI_CR1_FB1_DMA_DONE_INTEN_MASK +#define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT CSI_CR1_FB1_DMA_DONE_INTEN_SHIFT +#define CSI_CSICR1_FB1_DMA_DONE_INTEN(x) CSI_CR1_FB1_DMA_DONE_INTEN(x) +#define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK CSI_CR1_FB2_DMA_DONE_INTEN_MASK +#define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT CSI_CR1_FB2_DMA_DONE_INTEN_SHIFT +#define CSI_CSICR1_FB2_DMA_DONE_INTEN(x) CSI_CR1_FB2_DMA_DONE_INTEN(x) +#define CSI_CSICR1_STATFF_INTEN_MASK CSI_CR1_STATFF_INTEN_MASK +#define CSI_CSICR1_STATFF_INTEN_SHIFT CSI_CR1_STATFF_INTEN_SHIFT +#define CSI_CSICR1_STATFF_INTEN(x) CSI_CR1_STATFF_INTEN(x) +#define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK CSI_CR1_SFF_DMA_DONE_INTEN_MASK +#define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT CSI_CR1_SFF_DMA_DONE_INTEN_SHIFT +#define CSI_CSICR1_SFF_DMA_DONE_INTEN(x) CSI_CR1_SFF_DMA_DONE_INTEN(x) +#define CSI_CSICR1_RF_OR_INTEN_MASK CSI_CR1_RF_OR_INTEN_MASK +#define CSI_CSICR1_RF_OR_INTEN_SHIFT CSI_CR1_RF_OR_INTEN_SHIFT +#define CSI_CSICR1_RF_OR_INTEN(x) CSI_CR1_RF_OR_INTEN(x) +#define CSI_CSICR1_SF_OR_INTEN_MASK CSI_CR1_SF_OR_INTEN_MASK +#define CSI_CSICR1_SF_OR_INTEN_SHIFT CSI_CR1_SF_OR_INTEN_SHIFT +#define CSI_CSICR1_SF_OR_INTEN(x) CSI_CR1_SF_OR_INTEN(x) +#define CSI_CSICR1_COF_INT_EN_MASK CSI_CR1_COF_INT_EN_MASK +#define CSI_CSICR1_COF_INT_EN_SHIFT CSI_CR1_COF_INT_EN_SHIFT +#define CSI_CSICR1_COF_INT_EN(x) CSI_CR1_COF_INT_EN(x) +#define CSI_CSICR1_VIDEO_MODE_MASK CSI_CR1_VIDEO_MODE_MASK +#define CSI_CSICR1_VIDEO_MODE_SHIFT CSI_CR1_VIDEO_MODE_SHIFT +#define CSI_CSICR1_VIDEO_MODE(x) CSI_CR1_VIDEO_MODE(x) +#define CSI_CSICR1_EOF_INT_EN_MASK CSI_CR1_EOF_INT_EN_MASK +#define CSI_CSICR1_EOF_INT_EN_SHIFT CSI_CR1_EOF_INT_EN_SHIFT +#define CSI_CSICR1_EOF_INT_EN(x) CSI_CR1_EOF_INT_EN(x) +#define CSI_CSICR1_EXT_VSYNC_MASK CSI_CR1_EXT_VSYNC_MASK +#define CSI_CSICR1_EXT_VSYNC_SHIFT CSI_CR1_EXT_VSYNC_SHIFT +#define CSI_CSICR1_EXT_VSYNC(x) CSI_CR1_EXT_VSYNC(x) +#define CSI_CSICR1_SWAP16_EN_MASK CSI_CR1_SWAP16_EN_MASK +#define CSI_CSICR1_SWAP16_EN_SHIFT CSI_CR1_SWAP16_EN_SHIFT +#define CSI_CSICR1_SWAP16_EN(x) CSI_CR1_SWAP16_EN(x) +#define CSI_CSICR2_HSC_MASK CSI_CR2_HSC_MASK +#define CSI_CSICR2_HSC_SHIFT CSI_CR2_HSC_SHIFT +#define CSI_CSICR2_HSC(x) CSI_CR2_HSC(x) +#define CSI_CSICR2_VSC_MASK CSI_CR2_VSC_MASK +#define CSI_CSICR2_VSC_SHIFT CSI_CR2_VSC_SHIFT +#define CSI_CSICR2_VSC(x) CSI_CR2_VSC(x) +#define CSI_CSICR2_LVRM_MASK CSI_CR2_LVRM_MASK +#define CSI_CSICR2_LVRM_SHIFT CSI_CR2_LVRM_SHIFT +#define CSI_CSICR2_LVRM(x) CSI_CR2_LVRM(x) +#define CSI_CSICR2_BTS_MASK CSI_CR2_BTS_MASK +#define CSI_CSICR2_BTS_SHIFT CSI_CR2_BTS_SHIFT +#define CSI_CSICR2_BTS(x) CSI_CR2_BTS(x) +#define CSI_CSICR2_SCE_MASK CSI_CR2_SCE_MASK +#define CSI_CSICR2_SCE_SHIFT CSI_CR2_SCE_SHIFT +#define CSI_CSICR2_SCE(x) CSI_CR2_SCE(x) +#define CSI_CSICR2_AFS_MASK CSI_CR2_AFS_MASK +#define CSI_CSICR2_AFS_SHIFT CSI_CR2_AFS_SHIFT +#define CSI_CSICR2_AFS(x) CSI_CR2_AFS(x) +#define CSI_CSICR2_DRM_MASK CSI_CR2_DRM_MASK +#define CSI_CSICR2_DRM_SHIFT CSI_CR2_DRM_SHIFT +#define CSI_CSICR2_DRM(x) CSI_CR2_DRM(x) +#define CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK CSI_CR2_DMA_BURST_TYPE_SFF_MASK +#define CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT CSI_CR2_DMA_BURST_TYPE_SFF_SHIFT +#define CSI_CSICR2_DMA_BURST_TYPE_SFF(x) CSI_CR2_DMA_BURST_TYPE_SFF(x) +#define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK CSI_CR2_DMA_BURST_TYPE_RFF_MASK +#define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT CSI_CR2_DMA_BURST_TYPE_RFF_SHIFT +#define CSI_CSICR2_DMA_BURST_TYPE_RFF(x) CSI_CR2_DMA_BURST_TYPE_RFF(x) +#define CSI_CSICR3_ECC_AUTO_EN_MASK CSI_CR3_ECC_AUTO_EN_MASK +#define CSI_CSICR3_ECC_AUTO_EN_SHIFT CSI_CR3_ECC_AUTO_EN_SHIFT +#define CSI_CSICR3_ECC_AUTO_EN(x) CSI_CR3_ECC_AUTO_EN(x) +#define CSI_CSICR3_ECC_INT_EN_MASK CSI_CR3_ECC_INT_EN_MASK +#define CSI_CSICR3_ECC_INT_EN_SHIFT CSI_CR3_ECC_INT_EN_SHIFT +#define CSI_CSICR3_ECC_INT_EN(x) CSI_CR3_ECC_INT_EN(x) +#define CSI_CSICR3_ZERO_PACK_EN_MASK CSI_CR3_ZERO_PACK_EN_MASK +#define CSI_CSICR3_ZERO_PACK_EN_SHIFT CSI_CR3_ZERO_PACK_EN_SHIFT +#define CSI_CSICR3_ZERO_PACK_EN(x) CSI_CR3_ZERO_PACK_EN(x) +#define CSI_CSICR3_SENSOR_16BITS_MASK CSI_CR3_SENSOR_16BITS_MASK +#define CSI_CSICR3_SENSOR_16BITS_SHIFT CSI_CR3_SENSOR_16BITS_SHIFT +#define CSI_CSICR3_SENSOR_16BITS(x) CSI_CR3_SENSOR_16BITS(x) +#define CSI_CSICR3_RxFF_LEVEL_MASK CSI_CR3_RxFF_LEVEL_MASK +#define CSI_CSICR3_RxFF_LEVEL_SHIFT CSI_CR3_RxFF_LEVEL_SHIFT +#define CSI_CSICR3_RxFF_LEVEL(x) CSI_CR3_RxFF_LEVEL(x) +#define CSI_CSICR3_HRESP_ERR_EN_MASK CSI_CR3_HRESP_ERR_EN_MASK +#define CSI_CSICR3_HRESP_ERR_EN_SHIFT CSI_CR3_HRESP_ERR_EN_SHIFT +#define CSI_CSICR3_HRESP_ERR_EN(x) CSI_CR3_HRESP_ERR_EN(x) +#define CSI_CSICR3_STATFF_LEVEL_MASK CSI_CR3_STATFF_LEVEL_MASK +#define CSI_CSICR3_STATFF_LEVEL_SHIFT CSI_CR3_STATFF_LEVEL_SHIFT +#define CSI_CSICR3_STATFF_LEVEL(x) CSI_CR3_STATFF_LEVEL(x) +#define CSI_CSICR3_DMA_REQ_EN_SFF_MASK CSI_CR3_DMA_REQ_EN_SFF_MASK +#define CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT CSI_CR3_DMA_REQ_EN_SFF_SHIFT +#define CSI_CSICR3_DMA_REQ_EN_SFF(x) CSI_CR3_DMA_REQ_EN_SFF(x) +#define CSI_CSICR3_DMA_REQ_EN_RFF_MASK CSI_CR3_DMA_REQ_EN_RFF_MASK +#define CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT CSI_CR3_DMA_REQ_EN_RFF_SHIFT +#define CSI_CSICR3_DMA_REQ_EN_RFF(x) CSI_CR3_DMA_REQ_EN_RFF(x) +#define CSI_CSICR3_DMA_REFLASH_SFF_MASK CSI_CR3_DMA_REFLASH_SFF_MASK +#define CSI_CSICR3_DMA_REFLASH_SFF_SHIFT CSI_CR3_DMA_REFLASH_SFF_SHIFT +#define CSI_CSICR3_DMA_REFLASH_SFF(x) CSI_CR3_DMA_REFLASH_SFF(x) +#define CSI_CSICR3_DMA_REFLASH_RFF_MASK CSI_CR3_DMA_REFLASH_RFF_MASK +#define CSI_CSICR3_DMA_REFLASH_RFF_SHIFT CSI_CR3_DMA_REFLASH_RFF_SHIFT +#define CSI_CSICR3_DMA_REFLASH_RFF(x) CSI_CR3_DMA_REFLASH_RFF(x) +#define CSI_CSICR3_FRMCNT_RST_MASK CSI_CR3_FRMCNT_RST_MASK +#define CSI_CSICR3_FRMCNT_RST_SHIFT CSI_CR3_FRMCNT_RST_SHIFT +#define CSI_CSICR3_FRMCNT_RST(x) CSI_CR3_FRMCNT_RST(x) +#define CSI_CSICR3_FRMCNT_MASK CSI_CR3_FRMCNT_MASK +#define CSI_CSICR3_FRMCNT_SHIFT CSI_CR3_FRMCNT_SHIFT +#define CSI_CSICR3_FRMCNT(x) CSI_CR3_FRMCNT(x) +#define CSI_CSISTATFIFO_STAT_MASK CSI_STATFIFO_STAT_MASK +#define CSI_CSISTATFIFO_STAT_SHIFT CSI_STATFIFO_STAT_SHIFT +#define CSI_CSISTATFIFO_STAT(x) CSI_STATFIFO_STAT(x) +#define CSI_CSIRFIFO_IMAGE_MASK CSI_RFIFO_IMAGE_MASK +#define CSI_CSIRFIFO_IMAGE_SHIFT CSI_RFIFO_IMAGE_SHIFT +#define CSI_CSIRFIFO_IMAGE(x) CSI_RFIFO_IMAGE(x) +#define CSI_CSIRXCNT_RXCNT_MASK CSI_RXCNT_RXCNT_MASK +#define CSI_CSIRXCNT_RXCNT_SHIFT CSI_RXCNT_RXCNT_SHIFT +#define CSI_CSIRXCNT_RXCNT(x) CSI_RXCNT_RXCNT(x) +#define CSI_CSISR_DRDY_MASK CSI_SR_DRDY_MASK +#define CSI_CSISR_DRDY_SHIFT CSI_SR_DRDY_SHIFT +#define CSI_CSISR_DRDY(x) CSI_SR_DRDY(x) +#define CSI_CSISR_ECC_INT_MASK CSI_SR_ECC_INT_MASK +#define CSI_CSISR_ECC_INT_SHIFT CSI_SR_ECC_INT_SHIFT +#define CSI_CSISR_ECC_INT(x) CSI_SR_ECC_INT(x) +#define CSI_CSISR_HISTOGRAM_CALC_DONE_INT_MASK CSI_SR_HISTOGRAM_CALC_DONE_INT_MASK +#define CSI_CSISR_HISTOGRAM_CALC_DONE_INT_SHIFT CSI_SR_HISTOGRAM_CALC_DONE_INT_SHIFT +#define CSI_CSISR_HISTOGRAM_CALC_DONE_INT(x) CSI_SR_HISTOGRAM_CALC_DONE_INT(x) +#define CSI_CSISR_HRESP_ERR_INT_MASK CSI_SR_HRESP_ERR_INT_MASK +#define CSI_CSISR_HRESP_ERR_INT_SHIFT CSI_SR_HRESP_ERR_INT_SHIFT +#define CSI_CSISR_HRESP_ERR_INT(x) CSI_SR_HRESP_ERR_INT(x) +#define CSI_CSISR_COF_INT_MASK CSI_SR_COF_INT_MASK +#define CSI_CSISR_COF_INT_SHIFT CSI_SR_COF_INT_SHIFT +#define CSI_CSISR_COF_INT(x) CSI_SR_COF_INT(x) +#define CSI_CSISR_F1_INT_MASK CSI_SR_F1_INT_MASK +#define CSI_CSISR_F1_INT_SHIFT CSI_SR_F1_INT_SHIFT +#define CSI_CSISR_F1_INT(x) CSI_SR_F1_INT(x) +#define CSI_CSISR_F2_INT_MASK CSI_SR_F2_INT_MASK +#define CSI_CSISR_F2_INT_SHIFT CSI_SR_F2_INT_SHIFT +#define CSI_CSISR_F2_INT(x) CSI_SR_F2_INT(x) +#define CSI_CSISR_SOF_INT_MASK CSI_SR_SOF_INT_MASK +#define CSI_CSISR_SOF_INT_SHIFT CSI_SR_SOF_INT_SHIFT +#define CSI_CSISR_SOF_INT(x) CSI_SR_SOF_INT(x) +#define CSI_CSISR_EOF_INT_MASK CSI_SR_EOF_INT_MASK +#define CSI_CSISR_EOF_INT_SHIFT CSI_SR_EOF_INT_SHIFT +#define CSI_CSISR_EOF_INT(x) CSI_SR_EOF_INT(x) +#define CSI_CSISR_RxFF_INT_MASK CSI_SR_RxFF_INT_MASK +#define CSI_CSISR_RxFF_INT_SHIFT CSI_SR_RxFF_INT_SHIFT +#define CSI_CSISR_RxFF_INT(x) CSI_SR_RxFF_INT(x) +#define CSI_CSISR_DMA_TSF_DONE_FB1_MASK CSI_SR_DMA_TSF_DONE_FB1_MASK +#define CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT CSI_SR_DMA_TSF_DONE_FB1_SHIFT +#define CSI_CSISR_DMA_TSF_DONE_FB1(x) CSI_SR_DMA_TSF_DONE_FB1(x) +#define CSI_CSISR_DMA_TSF_DONE_FB2_MASK CSI_SR_DMA_TSF_DONE_FB2_MASK +#define CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT CSI_SR_DMA_TSF_DONE_FB2_SHIFT +#define CSI_CSISR_DMA_TSF_DONE_FB2(x) CSI_SR_DMA_TSF_DONE_FB2(x) +#define CSI_CSISR_STATFF_INT_MASK CSI_SR_STATFF_INT_MASK +#define CSI_CSISR_STATFF_INT_SHIFT CSI_SR_STATFF_INT_SHIFT +#define CSI_CSISR_STATFF_INT(x) CSI_SR_STATFF_INT(x) +#define CSI_CSISR_DMA_TSF_DONE_SFF_MASK CSI_SR_DMA_TSF_DONE_SFF_MASK +#define CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT CSI_SR_DMA_TSF_DONE_SFF_SHIFT +#define CSI_CSISR_DMA_TSF_DONE_SFF(x) CSI_SR_DMA_TSF_DONE_SFF(x) +#define CSI_CSISR_RF_OR_INT_MASK CSI_SR_RF_OR_INT_MASK +#define CSI_CSISR_RF_OR_INT_SHIFT CSI_SR_RF_OR_INT_SHIFT +#define CSI_CSISR_RF_OR_INT(x) CSI_SR_RF_OR_INT(x) +#define CSI_CSISR_SF_OR_INT_MASK CSI_SR_SF_OR_INT_MASK +#define CSI_CSISR_SF_OR_INT_SHIFT CSI_SR_SF_OR_INT_SHIFT +#define CSI_CSISR_SF_OR_INT(x) CSI_SR_SF_OR_INT(x) +#define CSI_CSISR_DMA_FIELD1_DONE_MASK CSI_SR_DMA_FIELD1_DONE_MASK +#define CSI_CSISR_DMA_FIELD1_DONE_SHIFT CSI_SR_DMA_FIELD1_DONE_SHIFT +#define CSI_CSISR_DMA_FIELD1_DONE(x) CSI_SR_DMA_FIELD1_DONE(x) +#define CSI_CSISR_DMA_FIELD0_DONE_MASK CSI_SR_DMA_FIELD0_DONE_MASK +#define CSI_CSISR_DMA_FIELD0_DONE_SHIFT CSI_SR_DMA_FIELD0_DONE_SHIFT +#define CSI_CSISR_DMA_FIELD0_DONE(x) CSI_SR_DMA_FIELD0_DONE(x) +#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK CSI_SR_BASEADDR_CHHANGE_ERROR_MASK +#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT CSI_SR_BASEADDR_CHHANGE_ERROR_SHIFT +#define CSI_CSISR_BASEADDR_CHHANGE_ERROR(x) CSI_SR_BASEADDR_CHHANGE_ERROR(x) +#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_MASK +#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT +#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF(x) +#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK +#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT +#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) +#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK CSI_DMASA_FB1_DMA_START_ADDR_FB1_MASK +#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT CSI_DMASA_FB1_DMA_START_ADDR_FB1_SHIFT +#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x) CSI_DMASA_FB1_DMA_START_ADDR_FB1(x) +#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK CSI_DMASA_FB2_DMA_START_ADDR_FB2_MASK +#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT CSI_DMASA_FB2_DMA_START_ADDR_FB2_SHIFT +#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x) CSI_DMASA_FB2_DMA_START_ADDR_FB2(x) +#define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK CSI_FBUF_PARA_FBUF_STRIDE_MASK +#define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT CSI_FBUF_PARA_FBUF_STRIDE_SHIFT +#define CSI_CSIFBUF_PARA_FBUF_STRIDE(x) CSI_FBUF_PARA_FBUF_STRIDE(x) +#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK CSI_FBUF_PARA_DEINTERLACE_STRIDE_MASK +#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT CSI_FBUF_PARA_DEINTERLACE_STRIDE_SHIFT +#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x) CSI_FBUF_PARA_DEINTERLACE_STRIDE(x) +#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK CSI_IMAG_PARA_IMAGE_HEIGHT_MASK +#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT +#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x) CSI_IMAG_PARA_IMAGE_HEIGHT(x) +#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK CSI_IMAG_PARA_IMAGE_WIDTH_MASK +#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT +#define CSI_CSIIMAG_PARA_IMAGE_WIDTH(x) CSI_IMAG_PARA_IMAGE_WIDTH(x) +#define CSI_CSICR18_NTSC_EN_MASK CSI_CR18_NTSC_EN_MASK +#define CSI_CSICR18_NTSC_EN_SHIFT CSI_CR18_NTSC_EN_SHIFT +#define CSI_CSICR18_NTSC_EN(x) CSI_CR18_NTSC_EN(x) +#define CSI_CSICR18_TVDECODER_IN_EN_MASK CSI_CR18_TVDECODER_IN_EN_MASK +#define CSI_CSICR18_TVDECODER_IN_EN_SHIFT CSI_CR18_TVDECODER_IN_EN_SHIFT +#define CSI_CSICR18_TVDECODER_IN_EN(x) CSI_CR18_TVDECODER_IN_EN(x) +#define CSI_CSICR18_DEINTERLACE_EN_MASK CSI_CR18_DEINTERLACE_EN_MASK +#define CSI_CSICR18_DEINTERLACE_EN_SHIFT CSI_CR18_DEINTERLACE_EN_SHIFT +#define CSI_CSICR18_DEINTERLACE_EN(x) CSI_CR18_DEINTERLACE_EN(x) +#define CSI_CSICR18_PARALLEL24_EN_MASK CSI_CR18_PARALLEL24_EN_MASK +#define CSI_CSICR18_PARALLEL24_EN_SHIFT CSI_CR18_PARALLEL24_EN_SHIFT +#define CSI_CSICR18_PARALLEL24_EN(x) CSI_CR18_PARALLEL24_EN(x) +#define CSI_CSICR18_BASEADDR_SWITCH_EN_MASK CSI_CR18_BASEADDR_SWITCH_EN_MASK +#define CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT CSI_CR18_BASEADDR_SWITCH_EN_SHIFT +#define CSI_CSICR18_BASEADDR_SWITCH_EN(x) CSI_CR18_BASEADDR_SWITCH_EN(x) +#define CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK CSI_CR18_BASEADDR_SWITCH_SEL_MASK +#define CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT CSI_CR18_BASEADDR_SWITCH_SEL_SHIFT +#define CSI_CSICR18_BASEADDR_SWITCH_SEL(x) CSI_CR18_BASEADDR_SWITCH_SEL(x) +#define CSI_CSICR18_FIELD0_DONE_IE_MASK CSI_CR18_FIELD0_DONE_IE_MASK +#define CSI_CSICR18_FIELD0_DONE_IE_SHIFT CSI_CR18_FIELD0_DONE_IE_SHIFT +#define CSI_CSICR18_FIELD0_DONE_IE(x) CSI_CR18_FIELD0_DONE_IE(x) +#define CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK CSI_CR18_DMA_FIELD1_DONE_IE_MASK +#define CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT CSI_CR18_DMA_FIELD1_DONE_IE_SHIFT +#define CSI_CSICR18_DMA_FIELD1_DONE_IE(x) CSI_CR18_DMA_FIELD1_DONE_IE(x) +#define CSI_CSICR18_LAST_DMA_REQ_SEL_MASK CSI_CR18_LAST_DMA_REQ_SEL_MASK +#define CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT CSI_CR18_LAST_DMA_REQ_SEL_SHIFT +#define CSI_CSICR18_LAST_DMA_REQ_SEL(x) CSI_CR18_LAST_DMA_REQ_SEL(x) +#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK CSI_CR18_BASEADDR_CHANGE_ERROR_IE_MASK +#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT CSI_CR18_BASEADDR_CHANGE_ERROR_IE_SHIFT +#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x) CSI_CR18_BASEADDR_CHANGE_ERROR_IE(x) +#define CSI_CSICR18_RGB888A_FORMAT_SEL_MASK CSI_CR18_RGB888A_FORMAT_SEL_MASK +#define CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT CSI_CR18_RGB888A_FORMAT_SEL_SHIFT +#define CSI_CSICR18_RGB888A_FORMAT_SEL(x) CSI_CR18_RGB888A_FORMAT_SEL(x) +#define CSI_CSICR18_AHB_HPROT_MASK CSI_CR18_AHB_HPROT_MASK +#define CSI_CSICR18_AHB_HPROT_SHIFT CSI_CR18_AHB_HPROT_SHIFT +#define CSI_CSICR18_AHB_HPROT(x) CSI_CR18_AHB_HPROT(x) +#define CSI_CSICR18_MASK_OPTION_MASK CSI_CR18_MASK_OPTION_MASK +#define CSI_CSICR18_MASK_OPTION_SHIFT CSI_CR18_MASK_OPTION_SHIFT +#define CSI_CSICR18_MASK_OPTION(x) CSI_CR18_MASK_OPTION(x) +#define CSI_CSICR18_MIPI_DOUBLE_CMPNT_MASK CSI_CR18_MIPI_DOUBLE_CMPNT_MASK +#define CSI_CSICR18_MIPI_DOUBLE_CMPNT_SHIFT CSI_CR18_MIPI_DOUBLE_CMPNT_SHIFT +#define CSI_CSICR18_MIPI_DOUBLE_CMPNT(x) CSI_CR18_MIPI_DOUBLE_CMPNT(x) +#define CSI_CSICR18_MIPI_YU_SWAP_MASK CSI_CR18_MIPI_YU_SWAP_MASK +#define CSI_CSICR18_MIPI_YU_SWAP_SHIFT CSI_CR18_MIPI_YU_SWAP_SHIFT +#define CSI_CSICR18_MIPI_YU_SWAP(x) CSI_CR18_MIPI_YU_SWAP(x) +#define CSI_CSICR18_DATA_FROM_MIPI_MASK CSI_CR18_DATA_FROM_MIPI_MASK +#define CSI_CSICR18_DATA_FROM_MIPI_SHIFT CSI_CR18_DATA_FROM_MIPI_SHIFT +#define CSI_CSICR18_DATA_FROM_MIPI(x) CSI_CR18_DATA_FROM_MIPI(x) +#define CSI_CSICR18_LINE_STRIDE_EN_MASK CSI_CR18_LINE_STRIDE_EN_MASK +#define CSI_CSICR18_LINE_STRIDE_EN_SHIFT CSI_CR18_LINE_STRIDE_EN_SHIFT +#define CSI_CSICR18_LINE_STRIDE_EN(x) CSI_CR18_LINE_STRIDE_EN(x) +#define CSI_CSICR18_MIPI_DATA_FORMAT_MASK CSI_CR18_MIPI_DATA_FORMAT_MASK +#define CSI_CSICR18_MIPI_DATA_FORMAT_SHIFT CSI_CR18_MIPI_DATA_FORMAT_SHIFT +#define CSI_CSICR18_MIPI_DATA_FORMAT(x) CSI_CR18_MIPI_DATA_FORMAT(x) +#define CSI_CSICR18_CSI_ENABLE_MASK CSI_CR18_CSI_ENABLE_MASK +#define CSI_CSICR18_CSI_ENABLE_SHIFT CSI_CR18_CSI_ENABLE_SHIFT +#define CSI_CSICR18_CSI_ENABLE(x) CSI_CR18_CSI_ENABLE(x) +#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK +#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT +#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) +#define CSI_CSICR20_THRESHOLD_MASK CSI_CR20_THRESHOLD_MASK +#define CSI_CSICR20_THRESHOLD_SHIFT CSI_CR20_THRESHOLD_SHIFT +#define CSI_CSICR20_THRESHOLD(x) CSI_CR20_THRESHOLD(x) +#define CSI_CSICR20_BINARY_EN_MASK CSI_CR20_BINARY_EN_MASK +#define CSI_CSICR20_BINARY_EN_SHIFT CSI_CR20_BINARY_EN_SHIFT +#define CSI_CSICR20_BINARY_EN(x) CSI_CR20_BINARY_EN(x) +#define CSI_CSICR20_QR_DATA_FORMAT_MASK CSI_CR20_QR_DATA_FORMAT_MASK +#define CSI_CSICR20_QR_DATA_FORMAT_SHIFT CSI_CR20_QR_DATA_FORMAT_SHIFT +#define CSI_CSICR20_QR_DATA_FORMAT(x) CSI_CR20_QR_DATA_FORMAT(x) +#define CSI_CSICR20_BIG_END_MASK CSI_CR20_BIG_END_MASK +#define CSI_CSICR20_BIG_END_SHIFT CSI_CR20_BIG_END_SHIFT +#define CSI_CSICR20_BIG_END(x) CSI_CR20_BIG_END(x) +#define CSI_CSICR20_10BIT_NEW_EN_MASK CSI_CR20_10BIT_NEW_EN_MASK +#define CSI_CSICR20_10BIT_NEW_EN_SHIFT CSI_CR20_10BIT_NEW_EN_SHIFT +#define CSI_CSICR20_10BIT_NEW_EN(x) CSI_CR20_10BIT_NEW_EN(x) +#define CSI_CSICR20_HISTOGRAM_EN_MASK CSI_CR20_HISTOGRAM_EN_MASK +#define CSI_CSICR20_HISTOGRAM_EN_SHIFT CSI_CR20_HISTOGRAM_EN_SHIFT +#define CSI_CSICR20_HISTOGRAM_EN(x) CSI_CR20_HISTOGRAM_EN(x) +#define CSI_CSICR20_QRCODE_EN_MASK CSI_CR20_QRCODE_EN_MASK +#define CSI_CSICR20_QRCODE_EN_SHIFT CSI_CR20_QRCODE_EN_SHIFT +#define CSI_CSICR20_QRCODE_EN(x) CSI_CR20_QRCODE_EN(x) +#define CSI_CSICR21_PIXEL_COUNTERS_MASK CSI_CR21_PIXEL_COUNTERS_MASK +#define CSI_CSICR21_PIXEL_COUNTERS_SHIFT CSI_CR21_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR21_PIXEL_COUNTERS(x) CSI_CR21_PIXEL_COUNTERS(x) +#define CSI_CSICR22_PIXEL_COUNTERS_MASK CSI_CR22_PIXEL_COUNTERS_MASK +#define CSI_CSICR22_PIXEL_COUNTERS_SHIFT CSI_CR22_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR22_PIXEL_COUNTERS(x) CSI_CR22_PIXEL_COUNTERS(x) +#define CSI_CSICR23_PIXEL_COUNTERS_MASK CSI_CR23_PIXEL_COUNTERS_MASK +#define CSI_CSICR23_PIXEL_COUNTERS_SHIFT CSI_CR23_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR23_PIXEL_COUNTERS(x) CSI_CR23_PIXEL_COUNTERS(x) +#define CSI_CSICR24_PIXEL_COUNTERS_MASK CSI_CR24_PIXEL_COUNTERS_MASK +#define CSI_CSICR24_PIXEL_COUNTERS_SHIFT CSI_CR24_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR24_PIXEL_COUNTERS(x) CSI_CR24_PIXEL_COUNTERS(x) +#define CSI_CSICR25_PIXEL_COUNTERS_MASK CSI_CR25_PIXEL_COUNTERS_MASK +#define CSI_CSICR25_PIXEL_COUNTERS_SHIFT CSI_CR25_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR25_PIXEL_COUNTERS(x) CSI_CR25_PIXEL_COUNTERS(x) +#define CSI_CSICR26_PIXEL_COUNTERS_MASK CSI_CR26_PIXEL_COUNTERS_MASK +#define CSI_CSICR26_PIXEL_COUNTERS_SHIFT CSI_CR26_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR26_PIXEL_COUNTERS(x) CSI_CR26_PIXEL_COUNTERS(x) +#define CSI_CSICR27_PIXEL_COUNTERS_MASK CSI_CR27_PIXEL_COUNTERS_MASK +#define CSI_CSICR27_PIXEL_COUNTERS_SHIFT CSI_CR27_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR27_PIXEL_COUNTERS(x) CSI_CR27_PIXEL_COUNTERS(x) +#define CSI_CSICR28_PIXEL_COUNTERS_MASK CSI_CR28_PIXEL_COUNTERS_MASK +#define CSI_CSICR28_PIXEL_COUNTERS_SHIFT CSI_CR28_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR28_PIXEL_COUNTERS(x) CSI_CR28_PIXEL_COUNTERS(x) +#define CSI_CSICR29_PIXEL_COUNTERS_MASK CSI_CR29_PIXEL_COUNTERS_MASK +#define CSI_CSICR29_PIXEL_COUNTERS_SHIFT CSI_CR29_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR29_PIXEL_COUNTERS(x) CSI_CR29_PIXEL_COUNTERS(x) +#define CSI_CSICR30_PIXEL_COUNTERS_MASK CSI_CR30_PIXEL_COUNTERS_MASK +#define CSI_CSICR30_PIXEL_COUNTERS_SHIFT CSI_CR30_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR30_PIXEL_COUNTERS(x) CSI_CR30_PIXEL_COUNTERS(x) +#define CSI_CSICR31_PIXEL_COUNTERS_MASK CSI_CR31_PIXEL_COUNTERS_MASK +#define CSI_CSICR31_PIXEL_COUNTERS_SHIFT CSI_CR31_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR31_PIXEL_COUNTERS(x) CSI_CR31_PIXEL_COUNTERS(x) +#define CSI_CSICR32_PIXEL_COUNTERS_MASK CSI_CR32_PIXEL_COUNTERS_MASK +#define CSI_CSICR32_PIXEL_COUNTERS_SHIFT CSI_CR32_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR32_PIXEL_COUNTERS(x) CSI_CR32_PIXEL_COUNTERS(x) +#define CSI_CSICR33_PIXEL_COUNTERS_MASK CSI_CR33_PIXEL_COUNTERS_MASK +#define CSI_CSICR33_PIXEL_COUNTERS_SHIFT CSI_CR33_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR33_PIXEL_COUNTERS(x) CSI_CR33_PIXEL_COUNTERS(x) +#define CSI_CSICR34_PIXEL_COUNTERS_MASK CSI_CR34_PIXEL_COUNTERS_MASK +#define CSI_CSICR34_PIXEL_COUNTERS_SHIFT CSI_CR34_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR34_PIXEL_COUNTERS(x) CSI_CR34_PIXEL_COUNTERS(x) +#define CSI_CSICR35_PIXEL_COUNTERS_MASK CSI_CR35_PIXEL_COUNTERS_MASK +#define CSI_CSICR35_PIXEL_COUNTERS_SHIFT CSI_CR35_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR35_PIXEL_COUNTERS(x) CSI_CR35_PIXEL_COUNTERS(x) +#define CSI_CSICR36_PIXEL_COUNTERS_MASK CSI_CR36_PIXEL_COUNTERS_MASK +#define CSI_CSICR36_PIXEL_COUNTERS_SHIFT CSI_CR36_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR36_PIXEL_COUNTERS(x) CSI_CR36_PIXEL_COUNTERS(x) +#define CSI_CSICR37_PIXEL_COUNTERS_MASK CSI_CR37_PIXEL_COUNTERS_MASK +#define CSI_CSICR37_PIXEL_COUNTERS_SHIFT CSI_CR37_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR37_PIXEL_COUNTERS(x) CSI_CR37_PIXEL_COUNTERS(x) +#define CSI_CSICR38_PIXEL_COUNTERS_MASK CSI_CR38_PIXEL_COUNTERS_MASK +#define CSI_CSICR38_PIXEL_COUNTERS_SHIFT CSI_CR38_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR38_PIXEL_COUNTERS(x) CSI_CR38_PIXEL_COUNTERS(x) +#define CSI_CSICR39_PIXEL_COUNTERS_MASK CSI_CR39_PIXEL_COUNTERS_MASK +#define CSI_CSICR39_PIXEL_COUNTERS_SHIFT CSI_CR39_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR39_PIXEL_COUNTERS(x) CSI_CR39_PIXEL_COUNTERS(x) +#define CSI_CSICR40_PIXEL_COUNTERS_MASK CSI_CR40_PIXEL_COUNTERS_MASK +#define CSI_CSICR40_PIXEL_COUNTERS_SHIFT CSI_CR40_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR40_PIXEL_COUNTERS(x) CSI_CR40_PIXEL_COUNTERS(x) +#define CSI_CSICR41_PIXEL_COUNTERS_MASK CSI_CR41_PIXEL_COUNTERS_MASK +#define CSI_CSICR41_PIXEL_COUNTERS_SHIFT CSI_CR41_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR41_PIXEL_COUNTERS(x) CSI_CR41_PIXEL_COUNTERS(x) +#define CSI_CSICR42_PIXEL_COUNTERS_MASK CSI_CR42_PIXEL_COUNTERS_MASK +#define CSI_CSICR42_PIXEL_COUNTERS_SHIFT CSI_CR42_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR42_PIXEL_COUNTERS(x) CSI_CR42_PIXEL_COUNTERS(x) +#define CSI_CSICR43_PIXEL_COUNTERS_MASK CSI_CR43_PIXEL_COUNTERS_MASK +#define CSI_CSICR43_PIXEL_COUNTERS_SHIFT CSI_CR43_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR43_PIXEL_COUNTERS(x) CSI_CR43_PIXEL_COUNTERS(x) +#define CSI_CSICR44_PIXEL_COUNTERS_MASK CSI_CR44_PIXEL_COUNTERS_MASK +#define CSI_CSICR44_PIXEL_COUNTERS_SHIFT CSI_CR44_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR44_PIXEL_COUNTERS(x) CSI_CR44_PIXEL_COUNTERS(x) +#define CSI_CSICR45_PIXEL_COUNTERS_MASK CSI_CR45_PIXEL_COUNTERS_MASK +#define CSI_CSICR45_PIXEL_COUNTERS_SHIFT CSI_CR45_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR45_PIXEL_COUNTERS(x) CSI_CR45_PIXEL_COUNTERS(x) +#define CSI_CSICR46_PIXEL_COUNTERS_MASK CSI_CR46_PIXEL_COUNTERS_MASK +#define CSI_CSICR46_PIXEL_COUNTERS_SHIFT CSI_CR46_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR46_PIXEL_COUNTERS(x) CSI_CR46_PIXEL_COUNTERS(x) +#define CSI_CSICR47_PIXEL_COUNTERS_MASK CSI_CR47_PIXEL_COUNTERS_MASK +#define CSI_CSICR47_PIXEL_COUNTERS_SHIFT CSI_CR47_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR47_PIXEL_COUNTERS(x) CSI_CR47_PIXEL_COUNTERS(x) +#define CSI_CSICR48_PIXEL_COUNTERS_MASK CSI_CR48_PIXEL_COUNTERS_MASK +#define CSI_CSICR48_PIXEL_COUNTERS_SHIFT CSI_CR48_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR48_PIXEL_COUNTERS(x) CSI_CR48_PIXEL_COUNTERS(x) +#define CSI_CSICR49_PIXEL_COUNTERS_MASK CSI_CR49_PIXEL_COUNTERS_MASK +#define CSI_CSICR49_PIXEL_COUNTERS_SHIFT CSI_CR49_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR49_PIXEL_COUNTERS(x) CSI_CR49_PIXEL_COUNTERS(x) +#define CSI_CSICR50_PIXEL_COUNTERS_MASK CSI_CR50_PIXEL_COUNTERS_MASK +#define CSI_CSICR50_PIXEL_COUNTERS_SHIFT CSI_CR50_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR50_PIXEL_COUNTERS(x) CSI_CR50_PIXEL_COUNTERS(x) +#define CSI_CSICR51_PIXEL_COUNTERS_MASK CSI_CR51_PIXEL_COUNTERS_MASK +#define CSI_CSICR51_PIXEL_COUNTERS_SHIFT CSI_CR51_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR51_PIXEL_COUNTERS(x) CSI_CR51_PIXEL_COUNTERS(x) +#define CSI_CSICR52_PIXEL_COUNTERS_MASK CSI_CR52_PIXEL_COUNTERS_MASK +#define CSI_CSICR52_PIXEL_COUNTERS_SHIFT CSI_CR52_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR52_PIXEL_COUNTERS(x) CSI_CR52_PIXEL_COUNTERS(x) +#define CSI_CSICR53_PIXEL_COUNTERS_MASK CSI_CR53_PIXEL_COUNTERS_MASK +#define CSI_CSICR53_PIXEL_COUNTERS_SHIFT CSI_CR53_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR53_PIXEL_COUNTERS(x) CSI_CR53_PIXEL_COUNTERS(x) +#define CSI_CSICR54_PIXEL_COUNTERS_MASK CSI_CR54_PIXEL_COUNTERS_MASK +#define CSI_CSICR54_PIXEL_COUNTERS_SHIFT CSI_CR54_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR54_PIXEL_COUNTERS(x) CSI_CR54_PIXEL_COUNTERS(x) +#define CSI_CSICR55_PIXEL_COUNTERS_MASK CSI_CR55_PIXEL_COUNTERS_MASK +#define CSI_CSICR55_PIXEL_COUNTERS_SHIFT CSI_CR55_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR55_PIXEL_COUNTERS(x) CSI_CR55_PIXEL_COUNTERS(x) +#define CSI_CSICR56_PIXEL_COUNTERS_MASK CSI_CR56_PIXEL_COUNTERS_MASK +#define CSI_CSICR56_PIXEL_COUNTERS_SHIFT CSI_CR56_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR56_PIXEL_COUNTERS(x) CSI_CR56_PIXEL_COUNTERS(x) +#define CSI_CSICR57_PIXEL_COUNTERS_MASK CSI_CR57_PIXEL_COUNTERS_MASK +#define CSI_CSICR57_PIXEL_COUNTERS_SHIFT CSI_CR57_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR57_PIXEL_COUNTERS(x) CSI_CR57_PIXEL_COUNTERS(x) +#define CSI_CSICR58_PIXEL_COUNTERS_MASK CSI_CR58_PIXEL_COUNTERS_MASK +#define CSI_CSICR58_PIXEL_COUNTERS_SHIFT CSI_CR58_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR58_PIXEL_COUNTERS(x) CSI_CR58_PIXEL_COUNTERS(x) +#define CSI_CSICR59_PIXEL_COUNTERS_MASK CSI_CR59_PIXEL_COUNTERS_MASK +#define CSI_CSICR59_PIXEL_COUNTERS_SHIFT CSI_CR59_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR59_PIXEL_COUNTERS(x) CSI_CR59_PIXEL_COUNTERS(x) +#define CSI_CSICR60_PIXEL_COUNTERS_MASK CSI_CR60_PIXEL_COUNTERS_MASK +#define CSI_CSICR60_PIXEL_COUNTERS_SHIFT CSI_CR60_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR60_PIXEL_COUNTERS(x) CSI_CR60_PIXEL_COUNTERS(x) +#define CSI_CSICR61_PIXEL_COUNTERS_MASK CSI_CR61_PIXEL_COUNTERS_MASK +#define CSI_CSICR61_PIXEL_COUNTERS_SHIFT CSI_CR61_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR61_PIXEL_COUNTERS(x) CSI_CR61_PIXEL_COUNTERS(x) +#define CSI_CSICR62_PIXEL_COUNTERS_MASK CSI_CR62_PIXEL_COUNTERS_MASK +#define CSI_CSICR62_PIXEL_COUNTERS_SHIFT CSI_CR62_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR62_PIXEL_COUNTERS(x) CSI_CR62_PIXEL_COUNTERS(x) +#define CSI_CSICR63_PIXEL_COUNTERS_MASK CSI_CR63_PIXEL_COUNTERS_MASK +#define CSI_CSICR63_PIXEL_COUNTERS_SHIFT CSI_CR63_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR63_PIXEL_COUNTERS(x) CSI_CR63_PIXEL_COUNTERS(x) +#define CSI_CSICR64_PIXEL_COUNTERS_MASK CSI_CR64_PIXEL_COUNTERS_MASK +#define CSI_CSICR64_PIXEL_COUNTERS_SHIFT CSI_CR64_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR64_PIXEL_COUNTERS(x) CSI_CR64_PIXEL_COUNTERS(x) +#define CSI_CSICR65_PIXEL_COUNTERS_MASK CSI_CR65_PIXEL_COUNTERS_MASK +#define CSI_CSICR65_PIXEL_COUNTERS_SHIFT CSI_CR65_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR65_PIXEL_COUNTERS(x) CSI_CR65_PIXEL_COUNTERS(x) +#define CSI_CSICR66_PIXEL_COUNTERS_MASK CSI_CR66_PIXEL_COUNTERS_MASK +#define CSI_CSICR66_PIXEL_COUNTERS_SHIFT CSI_CR66_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR66_PIXEL_COUNTERS(x) CSI_CR66_PIXEL_COUNTERS(x) +#define CSI_CSICR67_PIXEL_COUNTERS_MASK CSI_CR67_PIXEL_COUNTERS_MASK +#define CSI_CSICR67_PIXEL_COUNTERS_SHIFT CSI_CR67_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR67_PIXEL_COUNTERS(x) CSI_CR67_PIXEL_COUNTERS(x) +#define CSI_CSICR68_PIXEL_COUNTERS_MASK CSI_CR68_PIXEL_COUNTERS_MASK +#define CSI_CSICR68_PIXEL_COUNTERS_SHIFT CSI_CR68_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR68_PIXEL_COUNTERS(x) CSI_CR68_PIXEL_COUNTERS(x) +#define CSI_CSICR69_PIXEL_COUNTERS_MASK CSI_CR69_PIXEL_COUNTERS_MASK +#define CSI_CSICR69_PIXEL_COUNTERS_SHIFT CSI_CR69_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR69_PIXEL_COUNTERS(x) CSI_CR69_PIXEL_COUNTERS(x) +#define CSI_CSICR70_PIXEL_COUNTERS_MASK CSI_CR70_PIXEL_COUNTERS_MASK +#define CSI_CSICR70_PIXEL_COUNTERS_SHIFT CSI_CR70_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR70_PIXEL_COUNTERS(x) CSI_CR70_PIXEL_COUNTERS(x) +#define CSI_CSICR71_PIXEL_COUNTERS_MASK CSI_CR71_PIXEL_COUNTERS_MASK +#define CSI_CSICR71_PIXEL_COUNTERS_SHIFT CSI_CR71_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR71_PIXEL_COUNTERS(x) CSI_CR71_PIXEL_COUNTERS(x) +#define CSI_CSICR72_PIXEL_COUNTERS_MASK CSI_CR72_PIXEL_COUNTERS_MASK +#define CSI_CSICR72_PIXEL_COUNTERS_SHIFT CSI_CR72_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR72_PIXEL_COUNTERS(x) CSI_CR72_PIXEL_COUNTERS(x) +#define CSI_CSICR73_PIXEL_COUNTERS_MASK CSI_CR73_PIXEL_COUNTERS_MASK +#define CSI_CSICR73_PIXEL_COUNTERS_SHIFT CSI_CR73_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR73_PIXEL_COUNTERS(x) CSI_CR73_PIXEL_COUNTERS(x) +#define CSI_CSICR74_PIXEL_COUNTERS_MASK CSI_CR74_PIXEL_COUNTERS_MASK +#define CSI_CSICR74_PIXEL_COUNTERS_SHIFT CSI_CR74_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR74_PIXEL_COUNTERS(x) CSI_CR74_PIXEL_COUNTERS(x) +#define CSI_CSICR75_PIXEL_COUNTERS_MASK CSI_CR75_PIXEL_COUNTERS_MASK +#define CSI_CSICR75_PIXEL_COUNTERS_SHIFT CSI_CR75_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR75_PIXEL_COUNTERS(x) CSI_CR75_PIXEL_COUNTERS(x) +#define CSI_CSICR76_PIXEL_COUNTERS_MASK CSI_CR76_PIXEL_COUNTERS_MASK +#define CSI_CSICR76_PIXEL_COUNTERS_SHIFT CSI_CR76_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR76_PIXEL_COUNTERS(x) CSI_CR76_PIXEL_COUNTERS(x) +#define CSI_CSICR77_PIXEL_COUNTERS_MASK CSI_CR77_PIXEL_COUNTERS_MASK +#define CSI_CSICR77_PIXEL_COUNTERS_SHIFT CSI_CR77_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR77_PIXEL_COUNTERS(x) CSI_CR77_PIXEL_COUNTERS(x) +#define CSI_CSICR78_PIXEL_COUNTERS_MASK CSI_CR78_PIXEL_COUNTERS_MASK +#define CSI_CSICR78_PIXEL_COUNTERS_SHIFT CSI_CR78_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR78_PIXEL_COUNTERS(x) CSI_CR78_PIXEL_COUNTERS(x) +#define CSI_CSICR79_PIXEL_COUNTERS_MASK CSI_CR79_PIXEL_COUNTERS_MASK +#define CSI_CSICR79_PIXEL_COUNTERS_SHIFT CSI_CR79_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR79_PIXEL_COUNTERS(x) CSI_CR79_PIXEL_COUNTERS(x) +#define CSI_CSICR80_PIXEL_COUNTERS_MASK CSI_CR80_PIXEL_COUNTERS_MASK +#define CSI_CSICR80_PIXEL_COUNTERS_SHIFT CSI_CR80_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR80_PIXEL_COUNTERS(x) CSI_CR80_PIXEL_COUNTERS(x) +#define CSI_CSICR81_PIXEL_COUNTERS_MASK CSI_CR81_PIXEL_COUNTERS_MASK +#define CSI_CSICR81_PIXEL_COUNTERS_SHIFT CSI_CR81_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR81_PIXEL_COUNTERS(x) CSI_CR81_PIXEL_COUNTERS(x) +#define CSI_CSICR82_PIXEL_COUNTERS_MASK CSI_CR82_PIXEL_COUNTERS_MASK +#define CSI_CSICR82_PIXEL_COUNTERS_SHIFT CSI_CR82_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR82_PIXEL_COUNTERS(x) CSI_CR82_PIXEL_COUNTERS(x) +#define CSI_CSICR83_PIXEL_COUNTERS_MASK CSI_CR83_PIXEL_COUNTERS_MASK +#define CSI_CSICR83_PIXEL_COUNTERS_SHIFT CSI_CR83_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR83_PIXEL_COUNTERS(x) CSI_CR83_PIXEL_COUNTERS(x) +#define CSI_CSICR84_PIXEL_COUNTERS_MASK CSI_CR84_PIXEL_COUNTERS_MASK +#define CSI_CSICR84_PIXEL_COUNTERS_SHIFT CSI_CR84_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR84_PIXEL_COUNTERS(x) CSI_CR84_PIXEL_COUNTERS(x) +#define CSI_CSICR85_PIXEL_COUNTERS_MASK CSI_CR85_PIXEL_COUNTERS_MASK +#define CSI_CSICR85_PIXEL_COUNTERS_SHIFT CSI_CR85_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR85_PIXEL_COUNTERS(x) CSI_CR85_PIXEL_COUNTERS(x) +#define CSI_CSICR86_PIXEL_COUNTERS_MASK CSI_CR86_PIXEL_COUNTERS_MASK +#define CSI_CSICR86_PIXEL_COUNTERS_SHIFT CSI_CR86_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR86_PIXEL_COUNTERS(x) CSI_CR86_PIXEL_COUNTERS(x) +#define CSI_CSICR87_PIXEL_COUNTERS_MASK CSI_CR87_PIXEL_COUNTERS_MASK +#define CSI_CSICR87_PIXEL_COUNTERS_SHIFT CSI_CR87_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR87_PIXEL_COUNTERS(x) CSI_CR87_PIXEL_COUNTERS(x) +#define CSI_CSICR88_PIXEL_COUNTERS_MASK CSI_CR88_PIXEL_COUNTERS_MASK +#define CSI_CSICR88_PIXEL_COUNTERS_SHIFT CSI_CR88_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR88_PIXEL_COUNTERS(x) CSI_CR88_PIXEL_COUNTERS(x) +#define CSI_CSICR89_PIXEL_COUNTERS_MASK CSI_CR89_PIXEL_COUNTERS_MASK +#define CSI_CSICR89_PIXEL_COUNTERS_SHIFT CSI_CR89_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR89_PIXEL_COUNTERS(x) CSI_CR89_PIXEL_COUNTERS(x) +#define CSI_CSICR90_PIXEL_COUNTERS_MASK CSI_CR90_PIXEL_COUNTERS_MASK +#define CSI_CSICR90_PIXEL_COUNTERS_SHIFT CSI_CR90_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR90_PIXEL_COUNTERS(x) CSI_CR90_PIXEL_COUNTERS(x) +#define CSI_CSICR91_PIXEL_COUNTERS_MASK CSI_CR91_PIXEL_COUNTERS_MASK +#define CSI_CSICR91_PIXEL_COUNTERS_SHIFT CSI_CR91_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR91_PIXEL_COUNTERS(x) CSI_CR91_PIXEL_COUNTERS(x) +#define CSI_CSICR92_PIXEL_COUNTERS_MASK CSI_CR92_PIXEL_COUNTERS_MASK +#define CSI_CSICR92_PIXEL_COUNTERS_SHIFT CSI_CR92_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR92_PIXEL_COUNTERS(x) CSI_CR92_PIXEL_COUNTERS(x) +#define CSI_CSICR93_PIXEL_COUNTERS_MASK CSI_CR93_PIXEL_COUNTERS_MASK +#define CSI_CSICR93_PIXEL_COUNTERS_SHIFT CSI_CR93_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR93_PIXEL_COUNTERS(x) CSI_CR93_PIXEL_COUNTERS(x) +#define CSI_CSICR94_PIXEL_COUNTERS_MASK CSI_CR94_PIXEL_COUNTERS_MASK +#define CSI_CSICR94_PIXEL_COUNTERS_SHIFT CSI_CR94_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR94_PIXEL_COUNTERS(x) CSI_CR94_PIXEL_COUNTERS(x) +#define CSI_CSICR95_PIXEL_COUNTERS_MASK CSI_CR95_PIXEL_COUNTERS_MASK +#define CSI_CSICR95_PIXEL_COUNTERS_SHIFT CSI_CR95_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR95_PIXEL_COUNTERS(x) CSI_CR95_PIXEL_COUNTERS(x) +#define CSI_CSICR96_PIXEL_COUNTERS_MASK CSI_CR96_PIXEL_COUNTERS_MASK +#define CSI_CSICR96_PIXEL_COUNTERS_SHIFT CSI_CR96_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR96_PIXEL_COUNTERS(x) CSI_CR96_PIXEL_COUNTERS(x) +#define CSI_CSICR97_PIXEL_COUNTERS_MASK CSI_CR97_PIXEL_COUNTERS_MASK +#define CSI_CSICR97_PIXEL_COUNTERS_SHIFT CSI_CR97_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR97_PIXEL_COUNTERS(x) CSI_CR97_PIXEL_COUNTERS(x) +#define CSI_CSICR98_PIXEL_COUNTERS_MASK CSI_CR98_PIXEL_COUNTERS_MASK +#define CSI_CSICR98_PIXEL_COUNTERS_SHIFT CSI_CR98_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR98_PIXEL_COUNTERS(x) CSI_CR98_PIXEL_COUNTERS(x) +#define CSI_CSICR99_PIXEL_COUNTERS_MASK CSI_CR99_PIXEL_COUNTERS_MASK +#define CSI_CSICR99_PIXEL_COUNTERS_SHIFT CSI_CR99_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR99_PIXEL_COUNTERS(x) CSI_CR99_PIXEL_COUNTERS(x) +#define CSI_CSICR100_PIXEL_COUNTERS_MASK CSI_CR100_PIXEL_COUNTERS_MASK +#define CSI_CSICR100_PIXEL_COUNTERS_SHIFT CSI_CR100_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR100_PIXEL_COUNTERS(x) CSI_CR100_PIXEL_COUNTERS(x) +#define CSI_CSICR101_PIXEL_COUNTERS_MASK CSI_CR101_PIXEL_COUNTERS_MASK +#define CSI_CSICR101_PIXEL_COUNTERS_SHIFT CSI_CR101_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR101_PIXEL_COUNTERS(x) CSI_CR101_PIXEL_COUNTERS(x) +#define CSI_CSICR102_PIXEL_COUNTERS_MASK CSI_CR102_PIXEL_COUNTERS_MASK +#define CSI_CSICR102_PIXEL_COUNTERS_SHIFT CSI_CR102_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR102_PIXEL_COUNTERS(x) CSI_CR102_PIXEL_COUNTERS(x) +#define CSI_CSICR103_PIXEL_COUNTERS_MASK CSI_CR103_PIXEL_COUNTERS_MASK +#define CSI_CSICR103_PIXEL_COUNTERS_SHIFT CSI_CR103_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR103_PIXEL_COUNTERS(x) CSI_CR103_PIXEL_COUNTERS(x) +#define CSI_CSICR104_PIXEL_COUNTERS_MASK CSI_CR104_PIXEL_COUNTERS_MASK +#define CSI_CSICR104_PIXEL_COUNTERS_SHIFT CSI_CR104_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR104_PIXEL_COUNTERS(x) CSI_CR104_PIXEL_COUNTERS(x) +#define CSI_CSICR105_PIXEL_COUNTERS_MASK CSI_CR105_PIXEL_COUNTERS_MASK +#define CSI_CSICR105_PIXEL_COUNTERS_SHIFT CSI_CR105_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR105_PIXEL_COUNTERS(x) CSI_CR105_PIXEL_COUNTERS(x) +#define CSI_CSICR106_PIXEL_COUNTERS_MASK CSI_CR106_PIXEL_COUNTERS_MASK +#define CSI_CSICR106_PIXEL_COUNTERS_SHIFT CSI_CR106_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR106_PIXEL_COUNTERS(x) CSI_CR106_PIXEL_COUNTERS(x) +#define CSI_CSICR107_PIXEL_COUNTERS_MASK CSI_CR107_PIXEL_COUNTERS_MASK +#define CSI_CSICR107_PIXEL_COUNTERS_SHIFT CSI_CR107_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR107_PIXEL_COUNTERS(x) CSI_CR107_PIXEL_COUNTERS(x) +#define CSI_CSICR108_PIXEL_COUNTERS_MASK CSI_CR108_PIXEL_COUNTERS_MASK +#define CSI_CSICR108_PIXEL_COUNTERS_SHIFT CSI_CR108_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR108_PIXEL_COUNTERS(x) CSI_CR108_PIXEL_COUNTERS(x) +#define CSI_CSICR109_PIXEL_COUNTERS_MASK CSI_CR109_PIXEL_COUNTERS_MASK +#define CSI_CSICR109_PIXEL_COUNTERS_SHIFT CSI_CR109_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR109_PIXEL_COUNTERS(x) CSI_CR109_PIXEL_COUNTERS(x) +#define CSI_CSICR110_PIXEL_COUNTERS_MASK CSI_CR110_PIXEL_COUNTERS_MASK +#define CSI_CSICR110_PIXEL_COUNTERS_SHIFT CSI_CR110_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR110_PIXEL_COUNTERS(x) CSI_CR110_PIXEL_COUNTERS(x) +#define CSI_CSICR111_PIXEL_COUNTERS_MASK CSI_CR111_PIXEL_COUNTERS_MASK +#define CSI_CSICR111_PIXEL_COUNTERS_SHIFT CSI_CR111_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR111_PIXEL_COUNTERS(x) CSI_CR111_PIXEL_COUNTERS(x) +#define CSI_CSICR112_PIXEL_COUNTERS_MASK CSI_CR112_PIXEL_COUNTERS_MASK +#define CSI_CSICR112_PIXEL_COUNTERS_SHIFT CSI_CR112_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR112_PIXEL_COUNTERS(x) CSI_CR112_PIXEL_COUNTERS(x) +#define CSI_CSICR113_PIXEL_COUNTERS_MASK CSI_CR113_PIXEL_COUNTERS_MASK +#define CSI_CSICR113_PIXEL_COUNTERS_SHIFT CSI_CR113_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR113_PIXEL_COUNTERS(x) CSI_CR113_PIXEL_COUNTERS(x) +#define CSI_CSICR114_PIXEL_COUNTERS_MASK CSI_CR114_PIXEL_COUNTERS_MASK +#define CSI_CSICR114_PIXEL_COUNTERS_SHIFT CSI_CR114_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR114_PIXEL_COUNTERS(x) CSI_CR114_PIXEL_COUNTERS(x) +#define CSI_CSICR115_PIXEL_COUNTERS_MASK CSI_CR115_PIXEL_COUNTERS_MASK +#define CSI_CSICR115_PIXEL_COUNTERS_SHIFT CSI_CR115_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR115_PIXEL_COUNTERS(x) CSI_CR115_PIXEL_COUNTERS(x) +#define CSI_CSICR116_PIXEL_COUNTERS_MASK CSI_CR116_PIXEL_COUNTERS_MASK +#define CSI_CSICR116_PIXEL_COUNTERS_SHIFT CSI_CR116_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR116_PIXEL_COUNTERS(x) CSI_CR116_PIXEL_COUNTERS(x) +#define CSI_CSICR117_PIXEL_COUNTERS_MASK CSI_CR117_PIXEL_COUNTERS_MASK +#define CSI_CSICR117_PIXEL_COUNTERS_SHIFT CSI_CR117_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR117_PIXEL_COUNTERS(x) CSI_CR117_PIXEL_COUNTERS(x) +#define CSI_CSICR118_PIXEL_COUNTERS_MASK CSI_CR118_PIXEL_COUNTERS_MASK +#define CSI_CSICR118_PIXEL_COUNTERS_SHIFT CSI_CR118_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR118_PIXEL_COUNTERS(x) CSI_CR118_PIXEL_COUNTERS(x) +#define CSI_CSICR119_PIXEL_COUNTERS_MASK CSI_CR119_PIXEL_COUNTERS_MASK +#define CSI_CSICR119_PIXEL_COUNTERS_SHIFT CSI_CR119_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR119_PIXEL_COUNTERS(x) CSI_CR119_PIXEL_COUNTERS(x) +#define CSI_CSICR120_PIXEL_COUNTERS_MASK CSI_CR120_PIXEL_COUNTERS_MASK +#define CSI_CSICR120_PIXEL_COUNTERS_SHIFT CSI_CR120_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR120_PIXEL_COUNTERS(x) CSI_CR120_PIXEL_COUNTERS(x) +#define CSI_CSICR121_PIXEL_COUNTERS_MASK CSI_CR121_PIXEL_COUNTERS_MASK +#define CSI_CSICR121_PIXEL_COUNTERS_SHIFT CSI_CR121_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR121_PIXEL_COUNTERS(x) CSI_CR121_PIXEL_COUNTERS(x) +#define CSI_CSICR122_PIXEL_COUNTERS_MASK CSI_CR122_PIXEL_COUNTERS_MASK +#define CSI_CSICR122_PIXEL_COUNTERS_SHIFT CSI_CR122_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR122_PIXEL_COUNTERS(x) CSI_CR122_PIXEL_COUNTERS(x) +#define CSI_CSICR123_PIXEL_COUNTERS_MASK CSI_CR123_PIXEL_COUNTERS_MASK +#define CSI_CSICR123_PIXEL_COUNTERS_SHIFT CSI_CR123_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR123_PIXEL_COUNTERS(x) CSI_CR123_PIXEL_COUNTERS(x) +#define CSI_CSICR124_PIXEL_COUNTERS_MASK CSI_CR124_PIXEL_COUNTERS_MASK +#define CSI_CSICR124_PIXEL_COUNTERS_SHIFT CSI_CR124_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR124_PIXEL_COUNTERS(x) CSI_CR124_PIXEL_COUNTERS(x) +#define CSI_CSICR125_PIXEL_COUNTERS_MASK CSI_CR125_PIXEL_COUNTERS_MASK +#define CSI_CSICR125_PIXEL_COUNTERS_SHIFT CSI_CR125_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR125_PIXEL_COUNTERS(x) CSI_CR125_PIXEL_COUNTERS(x) +#define CSI_CSICR126_PIXEL_COUNTERS_MASK CSI_CR126_PIXEL_COUNTERS_MASK +#define CSI_CSICR126_PIXEL_COUNTERS_SHIFT CSI_CR126_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR126_PIXEL_COUNTERS(x) CSI_CR126_PIXEL_COUNTERS(x) +#define CSI_CSICR127_PIXEL_COUNTERS_MASK CSI_CR127_PIXEL_COUNTERS_MASK +#define CSI_CSICR127_PIXEL_COUNTERS_SHIFT CSI_CR127_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR127_PIXEL_COUNTERS(x) CSI_CR127_PIXEL_COUNTERS(x) +#define CSI_CSICR128_PIXEL_COUNTERS_MASK CSI_CR128_PIXEL_COUNTERS_MASK +#define CSI_CSICR128_PIXEL_COUNTERS_SHIFT CSI_CR128_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR128_PIXEL_COUNTERS(x) CSI_CR128_PIXEL_COUNTERS(x) +#define CSI_CSICR129_PIXEL_COUNTERS_MASK CSI_CR129_PIXEL_COUNTERS_MASK +#define CSI_CSICR129_PIXEL_COUNTERS_SHIFT CSI_CR129_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR129_PIXEL_COUNTERS(x) CSI_CR129_PIXEL_COUNTERS(x) +#define CSI_CSICR130_PIXEL_COUNTERS_MASK CSI_CR130_PIXEL_COUNTERS_MASK +#define CSI_CSICR130_PIXEL_COUNTERS_SHIFT CSI_CR130_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR130_PIXEL_COUNTERS(x) CSI_CR130_PIXEL_COUNTERS(x) +#define CSI_CSICR131_PIXEL_COUNTERS_MASK CSI_CR131_PIXEL_COUNTERS_MASK +#define CSI_CSICR131_PIXEL_COUNTERS_SHIFT CSI_CR131_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR131_PIXEL_COUNTERS(x) CSI_CR131_PIXEL_COUNTERS(x) +#define CSI_CSICR132_PIXEL_COUNTERS_MASK CSI_CR132_PIXEL_COUNTERS_MASK +#define CSI_CSICR132_PIXEL_COUNTERS_SHIFT CSI_CR132_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR132_PIXEL_COUNTERS(x) CSI_CR132_PIXEL_COUNTERS(x) +#define CSI_CSICR133_PIXEL_COUNTERS_MASK CSI_CR133_PIXEL_COUNTERS_MASK +#define CSI_CSICR133_PIXEL_COUNTERS_SHIFT CSI_CR133_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR133_PIXEL_COUNTERS(x) CSI_CR133_PIXEL_COUNTERS(x) +#define CSI_CSICR134_PIXEL_COUNTERS_MASK CSI_CR134_PIXEL_COUNTERS_MASK +#define CSI_CSICR134_PIXEL_COUNTERS_SHIFT CSI_CR134_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR134_PIXEL_COUNTERS(x) CSI_CR134_PIXEL_COUNTERS(x) +#define CSI_CSICR135_PIXEL_COUNTERS_MASK CSI_CR135_PIXEL_COUNTERS_MASK +#define CSI_CSICR135_PIXEL_COUNTERS_SHIFT CSI_CR135_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR135_PIXEL_COUNTERS(x) CSI_CR135_PIXEL_COUNTERS(x) +#define CSI_CSICR136_PIXEL_COUNTERS_MASK CSI_CR136_PIXEL_COUNTERS_MASK +#define CSI_CSICR136_PIXEL_COUNTERS_SHIFT CSI_CR136_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR136_PIXEL_COUNTERS(x) CSI_CR136_PIXEL_COUNTERS(x) +#define CSI_CSICR137_PIXEL_COUNTERS_MASK CSI_CR137_PIXEL_COUNTERS_MASK +#define CSI_CSICR137_PIXEL_COUNTERS_SHIFT CSI_CR137_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR137_PIXEL_COUNTERS(x) CSI_CR137_PIXEL_COUNTERS(x) +#define CSI_CSICR138_PIXEL_COUNTERS_MASK CSI_CR138_PIXEL_COUNTERS_MASK +#define CSI_CSICR138_PIXEL_COUNTERS_SHIFT CSI_CR138_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR138_PIXEL_COUNTERS(x) CSI_CR138_PIXEL_COUNTERS(x) +#define CSI_CSICR139_PIXEL_COUNTERS_MASK CSI_CR139_PIXEL_COUNTERS_MASK +#define CSI_CSICR139_PIXEL_COUNTERS_SHIFT CSI_CR139_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR139_PIXEL_COUNTERS(x) CSI_CR139_PIXEL_COUNTERS(x) +#define CSI_CSICR140_PIXEL_COUNTERS_MASK CSI_CR140_PIXEL_COUNTERS_MASK +#define CSI_CSICR140_PIXEL_COUNTERS_SHIFT CSI_CR140_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR140_PIXEL_COUNTERS(x) CSI_CR140_PIXEL_COUNTERS(x) +#define CSI_CSICR141_PIXEL_COUNTERS_MASK CSI_CR141_PIXEL_COUNTERS_MASK +#define CSI_CSICR141_PIXEL_COUNTERS_SHIFT CSI_CR141_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR141_PIXEL_COUNTERS(x) CSI_CR141_PIXEL_COUNTERS(x) +#define CSI_CSICR142_PIXEL_COUNTERS_MASK CSI_CR142_PIXEL_COUNTERS_MASK +#define CSI_CSICR142_PIXEL_COUNTERS_SHIFT CSI_CR142_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR142_PIXEL_COUNTERS(x) CSI_CR142_PIXEL_COUNTERS(x) +#define CSI_CSICR143_PIXEL_COUNTERS_MASK CSI_CR143_PIXEL_COUNTERS_MASK +#define CSI_CSICR143_PIXEL_COUNTERS_SHIFT CSI_CR143_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR143_PIXEL_COUNTERS(x) CSI_CR143_PIXEL_COUNTERS(x) +#define CSI_CSICR144_PIXEL_COUNTERS_MASK CSI_CR144_PIXEL_COUNTERS_MASK +#define CSI_CSICR144_PIXEL_COUNTERS_SHIFT CSI_CR144_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR144_PIXEL_COUNTERS(x) CSI_CR144_PIXEL_COUNTERS(x) +#define CSI_CSICR145_PIXEL_COUNTERS_MASK CSI_CR145_PIXEL_COUNTERS_MASK +#define CSI_CSICR145_PIXEL_COUNTERS_SHIFT CSI_CR145_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR145_PIXEL_COUNTERS(x) CSI_CR145_PIXEL_COUNTERS(x) +#define CSI_CSICR146_PIXEL_COUNTERS_MASK CSI_CR146_PIXEL_COUNTERS_MASK +#define CSI_CSICR146_PIXEL_COUNTERS_SHIFT CSI_CR146_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR146_PIXEL_COUNTERS(x) CSI_CR146_PIXEL_COUNTERS(x) +#define CSI_CSICR147_PIXEL_COUNTERS_MASK CSI_CR147_PIXEL_COUNTERS_MASK +#define CSI_CSICR147_PIXEL_COUNTERS_SHIFT CSI_CR147_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR147_PIXEL_COUNTERS(x) CSI_CR147_PIXEL_COUNTERS(x) +#define CSI_CSICR148_PIXEL_COUNTERS_MASK CSI_CR148_PIXEL_COUNTERS_MASK +#define CSI_CSICR148_PIXEL_COUNTERS_SHIFT CSI_CR148_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR148_PIXEL_COUNTERS(x) CSI_CR148_PIXEL_COUNTERS(x) +#define CSI_CSICR149_PIXEL_COUNTERS_MASK CSI_CR149_PIXEL_COUNTERS_MASK +#define CSI_CSICR149_PIXEL_COUNTERS_SHIFT CSI_CR149_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR149_PIXEL_COUNTERS(x) CSI_CR149_PIXEL_COUNTERS(x) +#define CSI_CSICR150_PIXEL_COUNTERS_MASK CSI_CR150_PIXEL_COUNTERS_MASK +#define CSI_CSICR150_PIXEL_COUNTERS_SHIFT CSI_CR150_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR150_PIXEL_COUNTERS(x) CSI_CR150_PIXEL_COUNTERS(x) +#define CSI_CSICR151_PIXEL_COUNTERS_MASK CSI_CR151_PIXEL_COUNTERS_MASK +#define CSI_CSICR151_PIXEL_COUNTERS_SHIFT CSI_CR151_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR151_PIXEL_COUNTERS(x) CSI_CR151_PIXEL_COUNTERS(x) +#define CSI_CSICR152_PIXEL_COUNTERS_MASK CSI_CR152_PIXEL_COUNTERS_MASK +#define CSI_CSICR152_PIXEL_COUNTERS_SHIFT CSI_CR152_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR152_PIXEL_COUNTERS(x) CSI_CR152_PIXEL_COUNTERS(x) +#define CSI_CSICR153_PIXEL_COUNTERS_MASK CSI_CR153_PIXEL_COUNTERS_MASK +#define CSI_CSICR153_PIXEL_COUNTERS_SHIFT CSI_CR153_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR153_PIXEL_COUNTERS(x) CSI_CR153_PIXEL_COUNTERS(x) +#define CSI_CSICR154_PIXEL_COUNTERS_MASK CSI_CR154_PIXEL_COUNTERS_MASK +#define CSI_CSICR154_PIXEL_COUNTERS_SHIFT CSI_CR154_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR154_PIXEL_COUNTERS(x) CSI_CR154_PIXEL_COUNTERS(x) +#define CSI_CSICR155_PIXEL_COUNTERS_MASK CSI_CR155_PIXEL_COUNTERS_MASK +#define CSI_CSICR155_PIXEL_COUNTERS_SHIFT CSI_CR155_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR155_PIXEL_COUNTERS(x) CSI_CR155_PIXEL_COUNTERS(x) +#define CSI_CSICR156_PIXEL_COUNTERS_MASK CSI_CR156_PIXEL_COUNTERS_MASK +#define CSI_CSICR156_PIXEL_COUNTERS_SHIFT CSI_CR156_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR156_PIXEL_COUNTERS(x) CSI_CR156_PIXEL_COUNTERS(x) +#define CSI_CSICR157_PIXEL_COUNTERS_MASK CSI_CR157_PIXEL_COUNTERS_MASK +#define CSI_CSICR157_PIXEL_COUNTERS_SHIFT CSI_CR157_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR157_PIXEL_COUNTERS(x) CSI_CR157_PIXEL_COUNTERS(x) +#define CSI_CSICR158_PIXEL_COUNTERS_MASK CSI_CR158_PIXEL_COUNTERS_MASK +#define CSI_CSICR158_PIXEL_COUNTERS_SHIFT CSI_CR158_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR158_PIXEL_COUNTERS(x) CSI_CR158_PIXEL_COUNTERS(x) +#define CSI_CSICR159_PIXEL_COUNTERS_MASK CSI_CR159_PIXEL_COUNTERS_MASK +#define CSI_CSICR159_PIXEL_COUNTERS_SHIFT CSI_CR159_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR159_PIXEL_COUNTERS(x) CSI_CR159_PIXEL_COUNTERS(x) +#define CSI_CSICR160_PIXEL_COUNTERS_MASK CSI_CR160_PIXEL_COUNTERS_MASK +#define CSI_CSICR160_PIXEL_COUNTERS_SHIFT CSI_CR160_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR160_PIXEL_COUNTERS(x) CSI_CR160_PIXEL_COUNTERS(x) +#define CSI_CSICR161_PIXEL_COUNTERS_MASK CSI_CR161_PIXEL_COUNTERS_MASK +#define CSI_CSICR161_PIXEL_COUNTERS_SHIFT CSI_CR161_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR161_PIXEL_COUNTERS(x) CSI_CR161_PIXEL_COUNTERS(x) +#define CSI_CSICR162_PIXEL_COUNTERS_MASK CSI_CR162_PIXEL_COUNTERS_MASK +#define CSI_CSICR162_PIXEL_COUNTERS_SHIFT CSI_CR162_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR162_PIXEL_COUNTERS(x) CSI_CR162_PIXEL_COUNTERS(x) +#define CSI_CSICR163_PIXEL_COUNTERS_MASK CSI_CR163_PIXEL_COUNTERS_MASK +#define CSI_CSICR163_PIXEL_COUNTERS_SHIFT CSI_CR163_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR163_PIXEL_COUNTERS(x) CSI_CR163_PIXEL_COUNTERS(x) +#define CSI_CSICR164_PIXEL_COUNTERS_MASK CSI_CR164_PIXEL_COUNTERS_MASK +#define CSI_CSICR164_PIXEL_COUNTERS_SHIFT CSI_CR164_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR164_PIXEL_COUNTERS(x) CSI_CR164_PIXEL_COUNTERS(x) +#define CSI_CSICR165_PIXEL_COUNTERS_MASK CSI_CR165_PIXEL_COUNTERS_MASK +#define CSI_CSICR165_PIXEL_COUNTERS_SHIFT CSI_CR165_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR165_PIXEL_COUNTERS(x) CSI_CR165_PIXEL_COUNTERS(x) +#define CSI_CSICR166_PIXEL_COUNTERS_MASK CSI_CR166_PIXEL_COUNTERS_MASK +#define CSI_CSICR166_PIXEL_COUNTERS_SHIFT CSI_CR166_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR166_PIXEL_COUNTERS(x) CSI_CR166_PIXEL_COUNTERS(x) +#define CSI_CSICR167_PIXEL_COUNTERS_MASK CSI_CR167_PIXEL_COUNTERS_MASK +#define CSI_CSICR167_PIXEL_COUNTERS_SHIFT CSI_CR167_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR167_PIXEL_COUNTERS(x) CSI_CR167_PIXEL_COUNTERS(x) +#define CSI_CSICR168_PIXEL_COUNTERS_MASK CSI_CR168_PIXEL_COUNTERS_MASK +#define CSI_CSICR168_PIXEL_COUNTERS_SHIFT CSI_CR168_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR168_PIXEL_COUNTERS(x) CSI_CR168_PIXEL_COUNTERS(x) +#define CSI_CSICR169_PIXEL_COUNTERS_MASK CSI_CR169_PIXEL_COUNTERS_MASK +#define CSI_CSICR169_PIXEL_COUNTERS_SHIFT CSI_CR169_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR169_PIXEL_COUNTERS(x) CSI_CR169_PIXEL_COUNTERS(x) +#define CSI_CSICR170_PIXEL_COUNTERS_MASK CSI_CR170_PIXEL_COUNTERS_MASK +#define CSI_CSICR170_PIXEL_COUNTERS_SHIFT CSI_CR170_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR170_PIXEL_COUNTERS(x) CSI_CR170_PIXEL_COUNTERS(x) +#define CSI_CSICR171_PIXEL_COUNTERS_MASK CSI_CR171_PIXEL_COUNTERS_MASK +#define CSI_CSICR171_PIXEL_COUNTERS_SHIFT CSI_CR171_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR171_PIXEL_COUNTERS(x) CSI_CR171_PIXEL_COUNTERS(x) +#define CSI_CSICR172_PIXEL_COUNTERS_MASK CSI_CR172_PIXEL_COUNTERS_MASK +#define CSI_CSICR172_PIXEL_COUNTERS_SHIFT CSI_CR172_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR172_PIXEL_COUNTERS(x) CSI_CR172_PIXEL_COUNTERS(x) +#define CSI_CSICR173_PIXEL_COUNTERS_MASK CSI_CR173_PIXEL_COUNTERS_MASK +#define CSI_CSICR173_PIXEL_COUNTERS_SHIFT CSI_CR173_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR173_PIXEL_COUNTERS(x) CSI_CR173_PIXEL_COUNTERS(x) +#define CSI_CSICR174_PIXEL_COUNTERS_MASK CSI_CR174_PIXEL_COUNTERS_MASK +#define CSI_CSICR174_PIXEL_COUNTERS_SHIFT CSI_CR174_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR174_PIXEL_COUNTERS(x) CSI_CR174_PIXEL_COUNTERS(x) +#define CSI_CSICR175_PIXEL_COUNTERS_MASK CSI_CR175_PIXEL_COUNTERS_MASK +#define CSI_CSICR175_PIXEL_COUNTERS_SHIFT CSI_CR175_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR175_PIXEL_COUNTERS(x) CSI_CR175_PIXEL_COUNTERS(x) +#define CSI_CSICR176_PIXEL_COUNTERS_MASK CSI_CR176_PIXEL_COUNTERS_MASK +#define CSI_CSICR176_PIXEL_COUNTERS_SHIFT CSI_CR176_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR176_PIXEL_COUNTERS(x) CSI_CR176_PIXEL_COUNTERS(x) +#define CSI_CSICR177_PIXEL_COUNTERS_MASK CSI_CR177_PIXEL_COUNTERS_MASK +#define CSI_CSICR177_PIXEL_COUNTERS_SHIFT CSI_CR177_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR177_PIXEL_COUNTERS(x) CSI_CR177_PIXEL_COUNTERS(x) +#define CSI_CSICR178_PIXEL_COUNTERS_MASK CSI_CR178_PIXEL_COUNTERS_MASK +#define CSI_CSICR178_PIXEL_COUNTERS_SHIFT CSI_CR178_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR178_PIXEL_COUNTERS(x) CSI_CR178_PIXEL_COUNTERS(x) +#define CSI_CSICR179_PIXEL_COUNTERS_MASK CSI_CR179_PIXEL_COUNTERS_MASK +#define CSI_CSICR179_PIXEL_COUNTERS_SHIFT CSI_CR179_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR179_PIXEL_COUNTERS(x) CSI_CR179_PIXEL_COUNTERS(x) +#define CSI_CSICR180_PIXEL_COUNTERS_MASK CSI_CR180_PIXEL_COUNTERS_MASK +#define CSI_CSICR180_PIXEL_COUNTERS_SHIFT CSI_CR180_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR180_PIXEL_COUNTERS(x) CSI_CR180_PIXEL_COUNTERS(x) +#define CSI_CSICR181_PIXEL_COUNTERS_MASK CSI_CR181_PIXEL_COUNTERS_MASK +#define CSI_CSICR181_PIXEL_COUNTERS_SHIFT CSI_CR181_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR181_PIXEL_COUNTERS(x) CSI_CR181_PIXEL_COUNTERS(x) +#define CSI_CSICR182_PIXEL_COUNTERS_MASK CSI_CR182_PIXEL_COUNTERS_MASK +#define CSI_CSICR182_PIXEL_COUNTERS_SHIFT CSI_CR182_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR182_PIXEL_COUNTERS(x) CSI_CR182_PIXEL_COUNTERS(x) +#define CSI_CSICR183_PIXEL_COUNTERS_MASK CSI_CR183_PIXEL_COUNTERS_MASK +#define CSI_CSICR183_PIXEL_COUNTERS_SHIFT CSI_CR183_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR183_PIXEL_COUNTERS(x) CSI_CR183_PIXEL_COUNTERS(x) +#define CSI_CSICR184_PIXEL_COUNTERS_MASK CSI_CR184_PIXEL_COUNTERS_MASK +#define CSI_CSICR184_PIXEL_COUNTERS_SHIFT CSI_CR184_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR184_PIXEL_COUNTERS(x) CSI_CR184_PIXEL_COUNTERS(x) +#define CSI_CSICR185_PIXEL_COUNTERS_MASK CSI_CR185_PIXEL_COUNTERS_MASK +#define CSI_CSICR185_PIXEL_COUNTERS_SHIFT CSI_CR185_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR185_PIXEL_COUNTERS(x) CSI_CR185_PIXEL_COUNTERS(x) +#define CSI_CSICR186_PIXEL_COUNTERS_MASK CSI_CR186_PIXEL_COUNTERS_MASK +#define CSI_CSICR186_PIXEL_COUNTERS_SHIFT CSI_CR186_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR186_PIXEL_COUNTERS(x) CSI_CR186_PIXEL_COUNTERS(x) +#define CSI_CSICR187_PIXEL_COUNTERS_MASK CSI_CR187_PIXEL_COUNTERS_MASK +#define CSI_CSICR187_PIXEL_COUNTERS_SHIFT CSI_CR187_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR187_PIXEL_COUNTERS(x) CSI_CR187_PIXEL_COUNTERS(x) +#define CSI_CSICR188_PIXEL_COUNTERS_MASK CSI_CR188_PIXEL_COUNTERS_MASK +#define CSI_CSICR188_PIXEL_COUNTERS_SHIFT CSI_CR188_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR188_PIXEL_COUNTERS(x) CSI_CR188_PIXEL_COUNTERS(x) +#define CSI_CSICR189_PIXEL_COUNTERS_MASK CSI_CR189_PIXEL_COUNTERS_MASK +#define CSI_CSICR189_PIXEL_COUNTERS_SHIFT CSI_CR189_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR189_PIXEL_COUNTERS(x) CSI_CR189_PIXEL_COUNTERS(x) +#define CSI_CSICR190_PIXEL_COUNTERS_MASK CSI_CR190_PIXEL_COUNTERS_MASK +#define CSI_CSICR190_PIXEL_COUNTERS_SHIFT CSI_CR190_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR190_PIXEL_COUNTERS(x) CSI_CR190_PIXEL_COUNTERS(x) +#define CSI_CSICR191_PIXEL_COUNTERS_MASK CSI_CR191_PIXEL_COUNTERS_MASK +#define CSI_CSICR191_PIXEL_COUNTERS_SHIFT CSI_CR191_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR191_PIXEL_COUNTERS(x) CSI_CR191_PIXEL_COUNTERS(x) +#define CSI_CSICR192_PIXEL_COUNTERS_MASK CSI_CR192_PIXEL_COUNTERS_MASK +#define CSI_CSICR192_PIXEL_COUNTERS_SHIFT CSI_CR192_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR192_PIXEL_COUNTERS(x) CSI_CR192_PIXEL_COUNTERS(x) +#define CSI_CSICR193_PIXEL_COUNTERS_MASK CSI_CR193_PIXEL_COUNTERS_MASK +#define CSI_CSICR193_PIXEL_COUNTERS_SHIFT CSI_CR193_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR193_PIXEL_COUNTERS(x) CSI_CR193_PIXEL_COUNTERS(x) +#define CSI_CSICR194_PIXEL_COUNTERS_MASK CSI_CR194_PIXEL_COUNTERS_MASK +#define CSI_CSICR194_PIXEL_COUNTERS_SHIFT CSI_CR194_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR194_PIXEL_COUNTERS(x) CSI_CR194_PIXEL_COUNTERS(x) +#define CSI_CSICR195_PIXEL_COUNTERS_MASK CSI_CR195_PIXEL_COUNTERS_MASK +#define CSI_CSICR195_PIXEL_COUNTERS_SHIFT CSI_CR195_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR195_PIXEL_COUNTERS(x) CSI_CR195_PIXEL_COUNTERS(x) +#define CSI_CSICR196_PIXEL_COUNTERS_MASK CSI_CR196_PIXEL_COUNTERS_MASK +#define CSI_CSICR196_PIXEL_COUNTERS_SHIFT CSI_CR196_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR196_PIXEL_COUNTERS(x) CSI_CR196_PIXEL_COUNTERS(x) +#define CSI_CSICR197_PIXEL_COUNTERS_MASK CSI_CR197_PIXEL_COUNTERS_MASK +#define CSI_CSICR197_PIXEL_COUNTERS_SHIFT CSI_CR197_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR197_PIXEL_COUNTERS(x) CSI_CR197_PIXEL_COUNTERS(x) +#define CSI_CSICR198_PIXEL_COUNTERS_MASK CSI_CR198_PIXEL_COUNTERS_MASK +#define CSI_CSICR198_PIXEL_COUNTERS_SHIFT CSI_CR198_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR198_PIXEL_COUNTERS(x) CSI_CR198_PIXEL_COUNTERS(x) +#define CSI_CSICR199_PIXEL_COUNTERS_MASK CSI_CR199_PIXEL_COUNTERS_MASK +#define CSI_CSICR199_PIXEL_COUNTERS_SHIFT CSI_CR199_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR199_PIXEL_COUNTERS(x) CSI_CR199_PIXEL_COUNTERS(x) +#define CSI_CSICR200_PIXEL_COUNTERS_MASK CSI_CR200_PIXEL_COUNTERS_MASK +#define CSI_CSICR200_PIXEL_COUNTERS_SHIFT CSI_CR200_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR200_PIXEL_COUNTERS(x) CSI_CR200_PIXEL_COUNTERS(x) +#define CSI_CSICR201_PIXEL_COUNTERS_MASK CSI_CR201_PIXEL_COUNTERS_MASK +#define CSI_CSICR201_PIXEL_COUNTERS_SHIFT CSI_CR201_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR201_PIXEL_COUNTERS(x) CSI_CR201_PIXEL_COUNTERS(x) +#define CSI_CSICR202_PIXEL_COUNTERS_MASK CSI_CR202_PIXEL_COUNTERS_MASK +#define CSI_CSICR202_PIXEL_COUNTERS_SHIFT CSI_CR202_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR202_PIXEL_COUNTERS(x) CSI_CR202_PIXEL_COUNTERS(x) +#define CSI_CSICR203_PIXEL_COUNTERS_MASK CSI_CR203_PIXEL_COUNTERS_MASK +#define CSI_CSICR203_PIXEL_COUNTERS_SHIFT CSI_CR203_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR203_PIXEL_COUNTERS(x) CSI_CR203_PIXEL_COUNTERS(x) +#define CSI_CSICR204_PIXEL_COUNTERS_MASK CSI_CR204_PIXEL_COUNTERS_MASK +#define CSI_CSICR204_PIXEL_COUNTERS_SHIFT CSI_CR204_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR204_PIXEL_COUNTERS(x) CSI_CR204_PIXEL_COUNTERS(x) +#define CSI_CSICR205_PIXEL_COUNTERS_MASK CSI_CR205_PIXEL_COUNTERS_MASK +#define CSI_CSICR205_PIXEL_COUNTERS_SHIFT CSI_CR205_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR205_PIXEL_COUNTERS(x) CSI_CR205_PIXEL_COUNTERS(x) +#define CSI_CSICR206_PIXEL_COUNTERS_MASK CSI_CR206_PIXEL_COUNTERS_MASK +#define CSI_CSICR206_PIXEL_COUNTERS_SHIFT CSI_CR206_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR206_PIXEL_COUNTERS(x) CSI_CR206_PIXEL_COUNTERS(x) +#define CSI_CSICR207_PIXEL_COUNTERS_MASK CSI_CR207_PIXEL_COUNTERS_MASK +#define CSI_CSICR207_PIXEL_COUNTERS_SHIFT CSI_CR207_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR207_PIXEL_COUNTERS(x) CSI_CR207_PIXEL_COUNTERS(x) +#define CSI_CSICR208_PIXEL_COUNTERS_MASK CSI_CR208_PIXEL_COUNTERS_MASK +#define CSI_CSICR208_PIXEL_COUNTERS_SHIFT CSI_CR208_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR208_PIXEL_COUNTERS(x) CSI_CR208_PIXEL_COUNTERS(x) +#define CSI_CSICR209_PIXEL_COUNTERS_MASK CSI_CR209_PIXEL_COUNTERS_MASK +#define CSI_CSICR209_PIXEL_COUNTERS_SHIFT CSI_CR209_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR209_PIXEL_COUNTERS(x) CSI_CR209_PIXEL_COUNTERS(x) +#define CSI_CSICR210_PIXEL_COUNTERS_MASK CSI_CR210_PIXEL_COUNTERS_MASK +#define CSI_CSICR210_PIXEL_COUNTERS_SHIFT CSI_CR210_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR210_PIXEL_COUNTERS(x) CSI_CR210_PIXEL_COUNTERS(x) +#define CSI_CSICR211_PIXEL_COUNTERS_MASK CSI_CR211_PIXEL_COUNTERS_MASK +#define CSI_CSICR211_PIXEL_COUNTERS_SHIFT CSI_CR211_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR211_PIXEL_COUNTERS(x) CSI_CR211_PIXEL_COUNTERS(x) +#define CSI_CSICR212_PIXEL_COUNTERS_MASK CSI_CR212_PIXEL_COUNTERS_MASK +#define CSI_CSICR212_PIXEL_COUNTERS_SHIFT CSI_CR212_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR212_PIXEL_COUNTERS(x) CSI_CR212_PIXEL_COUNTERS(x) +#define CSI_CSICR213_PIXEL_COUNTERS_MASK CSI_CR213_PIXEL_COUNTERS_MASK +#define CSI_CSICR213_PIXEL_COUNTERS_SHIFT CSI_CR213_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR213_PIXEL_COUNTERS(x) CSI_CR213_PIXEL_COUNTERS(x) +#define CSI_CSICR214_PIXEL_COUNTERS_MASK CSI_CR214_PIXEL_COUNTERS_MASK +#define CSI_CSICR214_PIXEL_COUNTERS_SHIFT CSI_CR214_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR214_PIXEL_COUNTERS(x) CSI_CR214_PIXEL_COUNTERS(x) +#define CSI_CSICR215_PIXEL_COUNTERS_MASK CSI_CR215_PIXEL_COUNTERS_MASK +#define CSI_CSICR215_PIXEL_COUNTERS_SHIFT CSI_CR215_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR215_PIXEL_COUNTERS(x) CSI_CR215_PIXEL_COUNTERS(x) +#define CSI_CSICR216_PIXEL_COUNTERS_MASK CSI_CR216_PIXEL_COUNTERS_MASK +#define CSI_CSICR216_PIXEL_COUNTERS_SHIFT CSI_CR216_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR216_PIXEL_COUNTERS(x) CSI_CR216_PIXEL_COUNTERS(x) +#define CSI_CSICR217_PIXEL_COUNTERS_MASK CSI_CR217_PIXEL_COUNTERS_MASK +#define CSI_CSICR217_PIXEL_COUNTERS_SHIFT CSI_CR217_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR217_PIXEL_COUNTERS(x) CSI_CR217_PIXEL_COUNTERS(x) +#define CSI_CSICR218_PIXEL_COUNTERS_MASK CSI_CR218_PIXEL_COUNTERS_MASK +#define CSI_CSICR218_PIXEL_COUNTERS_SHIFT CSI_CR218_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR218_PIXEL_COUNTERS(x) CSI_CR218_PIXEL_COUNTERS(x) +#define CSI_CSICR219_PIXEL_COUNTERS_MASK CSI_CR219_PIXEL_COUNTERS_MASK +#define CSI_CSICR219_PIXEL_COUNTERS_SHIFT CSI_CR219_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR219_PIXEL_COUNTERS(x) CSI_CR219_PIXEL_COUNTERS(x) +#define CSI_CSICR220_PIXEL_COUNTERS_MASK CSI_CR220_PIXEL_COUNTERS_MASK +#define CSI_CSICR220_PIXEL_COUNTERS_SHIFT CSI_CR220_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR220_PIXEL_COUNTERS(x) CSI_CR220_PIXEL_COUNTERS(x) +#define CSI_CSICR221_PIXEL_COUNTERS_MASK CSI_CR221_PIXEL_COUNTERS_MASK +#define CSI_CSICR221_PIXEL_COUNTERS_SHIFT CSI_CR221_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR221_PIXEL_COUNTERS(x) CSI_CR221_PIXEL_COUNTERS(x) +#define CSI_CSICR222_PIXEL_COUNTERS_MASK CSI_CR222_PIXEL_COUNTERS_MASK +#define CSI_CSICR222_PIXEL_COUNTERS_SHIFT CSI_CR222_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR222_PIXEL_COUNTERS(x) CSI_CR222_PIXEL_COUNTERS(x) +#define CSI_CSICR223_PIXEL_COUNTERS_MASK CSI_CR223_PIXEL_COUNTERS_MASK +#define CSI_CSICR223_PIXEL_COUNTERS_SHIFT CSI_CR223_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR223_PIXEL_COUNTERS(x) CSI_CR223_PIXEL_COUNTERS(x) +#define CSI_CSICR224_PIXEL_COUNTERS_MASK CSI_CR224_PIXEL_COUNTERS_MASK +#define CSI_CSICR224_PIXEL_COUNTERS_SHIFT CSI_CR224_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR224_PIXEL_COUNTERS(x) CSI_CR224_PIXEL_COUNTERS(x) +#define CSI_CSICR225_PIXEL_COUNTERS_MASK CSI_CR225_PIXEL_COUNTERS_MASK +#define CSI_CSICR225_PIXEL_COUNTERS_SHIFT CSI_CR225_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR225_PIXEL_COUNTERS(x) CSI_CR225_PIXEL_COUNTERS(x) +#define CSI_CSICR226_PIXEL_COUNTERS_MASK CSI_CR226_PIXEL_COUNTERS_MASK +#define CSI_CSICR226_PIXEL_COUNTERS_SHIFT CSI_CR226_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR226_PIXEL_COUNTERS(x) CSI_CR226_PIXEL_COUNTERS(x) +#define CSI_CSICR227_PIXEL_COUNTERS_MASK CSI_CR227_PIXEL_COUNTERS_MASK +#define CSI_CSICR227_PIXEL_COUNTERS_SHIFT CSI_CR227_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR227_PIXEL_COUNTERS(x) CSI_CR227_PIXEL_COUNTERS(x) +#define CSI_CSICR228_PIXEL_COUNTERS_MASK CSI_CR228_PIXEL_COUNTERS_MASK +#define CSI_CSICR228_PIXEL_COUNTERS_SHIFT CSI_CR228_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR228_PIXEL_COUNTERS(x) CSI_CR228_PIXEL_COUNTERS(x) +#define CSI_CSICR229_PIXEL_COUNTERS_MASK CSI_CR229_PIXEL_COUNTERS_MASK +#define CSI_CSICR229_PIXEL_COUNTERS_SHIFT CSI_CR229_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR229_PIXEL_COUNTERS(x) CSI_CR229_PIXEL_COUNTERS(x) +#define CSI_CSICR230_PIXEL_COUNTERS_MASK CSI_CR230_PIXEL_COUNTERS_MASK +#define CSI_CSICR230_PIXEL_COUNTERS_SHIFT CSI_CR230_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR230_PIXEL_COUNTERS(x) CSI_CR230_PIXEL_COUNTERS(x) +#define CSI_CSICR231_PIXEL_COUNTERS_MASK CSI_CR231_PIXEL_COUNTERS_MASK +#define CSI_CSICR231_PIXEL_COUNTERS_SHIFT CSI_CR231_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR231_PIXEL_COUNTERS(x) CSI_CR231_PIXEL_COUNTERS(x) +#define CSI_CSICR232_PIXEL_COUNTERS_MASK CSI_CR232_PIXEL_COUNTERS_MASK +#define CSI_CSICR232_PIXEL_COUNTERS_SHIFT CSI_CR232_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR232_PIXEL_COUNTERS(x) CSI_CR232_PIXEL_COUNTERS(x) +#define CSI_CSICR233_PIXEL_COUNTERS_MASK CSI_CR233_PIXEL_COUNTERS_MASK +#define CSI_CSICR233_PIXEL_COUNTERS_SHIFT CSI_CR233_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR233_PIXEL_COUNTERS(x) CSI_CR233_PIXEL_COUNTERS(x) +#define CSI_CSICR234_PIXEL_COUNTERS_MASK CSI_CR234_PIXEL_COUNTERS_MASK +#define CSI_CSICR234_PIXEL_COUNTERS_SHIFT CSI_CR234_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR234_PIXEL_COUNTERS(x) CSI_CR234_PIXEL_COUNTERS(x) +#define CSI_CSICR235_PIXEL_COUNTERS_MASK CSI_CR235_PIXEL_COUNTERS_MASK +#define CSI_CSICR235_PIXEL_COUNTERS_SHIFT CSI_CR235_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR235_PIXEL_COUNTERS(x) CSI_CR235_PIXEL_COUNTERS(x) +#define CSI_CSICR236_PIXEL_COUNTERS_MASK CSI_CR236_PIXEL_COUNTERS_MASK +#define CSI_CSICR236_PIXEL_COUNTERS_SHIFT CSI_CR236_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR236_PIXEL_COUNTERS(x) CSI_CR236_PIXEL_COUNTERS(x) +#define CSI_CSICR237_PIXEL_COUNTERS_MASK CSI_CR237_PIXEL_COUNTERS_MASK +#define CSI_CSICR237_PIXEL_COUNTERS_SHIFT CSI_CR237_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR237_PIXEL_COUNTERS(x) CSI_CR237_PIXEL_COUNTERS(x) +#define CSI_CSICR238_PIXEL_COUNTERS_MASK CSI_CR238_PIXEL_COUNTERS_MASK +#define CSI_CSICR238_PIXEL_COUNTERS_SHIFT CSI_CR238_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR238_PIXEL_COUNTERS(x) CSI_CR238_PIXEL_COUNTERS(x) +#define CSI_CSICR239_PIXEL_COUNTERS_MASK CSI_CR239_PIXEL_COUNTERS_MASK +#define CSI_CSICR239_PIXEL_COUNTERS_SHIFT CSI_CR239_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR239_PIXEL_COUNTERS(x) CSI_CR239_PIXEL_COUNTERS(x) +#define CSI_CSICR240_PIXEL_COUNTERS_MASK CSI_CR240_PIXEL_COUNTERS_MASK +#define CSI_CSICR240_PIXEL_COUNTERS_SHIFT CSI_CR240_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR240_PIXEL_COUNTERS(x) CSI_CR240_PIXEL_COUNTERS(x) +#define CSI_CSICR241_PIXEL_COUNTERS_MASK CSI_CR241_PIXEL_COUNTERS_MASK +#define CSI_CSICR241_PIXEL_COUNTERS_SHIFT CSI_CR241_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR241_PIXEL_COUNTERS(x) CSI_CR241_PIXEL_COUNTERS(x) +#define CSI_CSICR242_PIXEL_COUNTERS_MASK CSI_CR242_PIXEL_COUNTERS_MASK +#define CSI_CSICR242_PIXEL_COUNTERS_SHIFT CSI_CR242_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR242_PIXEL_COUNTERS(x) CSI_CR242_PIXEL_COUNTERS(x) +#define CSI_CSICR243_PIXEL_COUNTERS_MASK CSI_CR243_PIXEL_COUNTERS_MASK +#define CSI_CSICR243_PIXEL_COUNTERS_SHIFT CSI_CR243_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR243_PIXEL_COUNTERS(x) CSI_CR243_PIXEL_COUNTERS(x) +#define CSI_CSICR244_PIXEL_COUNTERS_MASK CSI_CR244_PIXEL_COUNTERS_MASK +#define CSI_CSICR244_PIXEL_COUNTERS_SHIFT CSI_CR244_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR244_PIXEL_COUNTERS(x) CSI_CR244_PIXEL_COUNTERS(x) +#define CSI_CSICR245_PIXEL_COUNTERS_MASK CSI_CR245_PIXEL_COUNTERS_MASK +#define CSI_CSICR245_PIXEL_COUNTERS_SHIFT CSI_CR245_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR245_PIXEL_COUNTERS(x) CSI_CR245_PIXEL_COUNTERS(x) +#define CSI_CSICR246_PIXEL_COUNTERS_MASK CSI_CR246_PIXEL_COUNTERS_MASK +#define CSI_CSICR246_PIXEL_COUNTERS_SHIFT CSI_CR246_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR246_PIXEL_COUNTERS(x) CSI_CR246_PIXEL_COUNTERS(x) +#define CSI_CSICR247_PIXEL_COUNTERS_MASK CSI_CR247_PIXEL_COUNTERS_MASK +#define CSI_CSICR247_PIXEL_COUNTERS_SHIFT CSI_CR247_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR247_PIXEL_COUNTERS(x) CSI_CR247_PIXEL_COUNTERS(x) +#define CSI_CSICR248_PIXEL_COUNTERS_MASK CSI_CR248_PIXEL_COUNTERS_MASK +#define CSI_CSICR248_PIXEL_COUNTERS_SHIFT CSI_CR248_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR248_PIXEL_COUNTERS(x) CSI_CR248_PIXEL_COUNTERS(x) +#define CSI_CSICR249_PIXEL_COUNTERS_MASK CSI_CR249_PIXEL_COUNTERS_MASK +#define CSI_CSICR249_PIXEL_COUNTERS_SHIFT CSI_CR249_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR249_PIXEL_COUNTERS(x) CSI_CR249_PIXEL_COUNTERS(x) +#define CSI_CSICR250_PIXEL_COUNTERS_MASK CSI_CR250_PIXEL_COUNTERS_MASK +#define CSI_CSICR250_PIXEL_COUNTERS_SHIFT CSI_CR250_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR250_PIXEL_COUNTERS(x) CSI_CR250_PIXEL_COUNTERS(x) +#define CSI_CSICR251_PIXEL_COUNTERS_MASK CSI_CR251_PIXEL_COUNTERS_MASK +#define CSI_CSICR251_PIXEL_COUNTERS_SHIFT CSI_CR251_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR251_PIXEL_COUNTERS(x) CSI_CR251_PIXEL_COUNTERS(x) +#define CSI_CSICR252_PIXEL_COUNTERS_MASK CSI_CR252_PIXEL_COUNTERS_MASK +#define CSI_CSICR252_PIXEL_COUNTERS_SHIFT CSI_CR252_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR252_PIXEL_COUNTERS(x) CSI_CR252_PIXEL_COUNTERS(x) +#define CSI_CSICR253_PIXEL_COUNTERS_MASK CSI_CR253_PIXEL_COUNTERS_MASK +#define CSI_CSICR253_PIXEL_COUNTERS_SHIFT CSI_CR253_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR253_PIXEL_COUNTERS(x) CSI_CR253_PIXEL_COUNTERS(x) +#define CSI_CSICR254_PIXEL_COUNTERS_MASK CSI_CR254_PIXEL_COUNTERS_MASK +#define CSI_CSICR254_PIXEL_COUNTERS_SHIFT CSI_CR254_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR254_PIXEL_COUNTERS(x) CSI_CR254_PIXEL_COUNTERS(x) +#define CSI_CSICR255_PIXEL_COUNTERS_MASK CSI_CR255_PIXEL_COUNTERS_MASK +#define CSI_CSICR255_PIXEL_COUNTERS_SHIFT CSI_CR255_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR255_PIXEL_COUNTERS(x) CSI_CR255_PIXEL_COUNTERS(x) +#define CSI_CSICR256_PIXEL_COUNTERS_MASK CSI_CR256_PIXEL_COUNTERS_MASK +#define CSI_CSICR256_PIXEL_COUNTERS_SHIFT CSI_CR256_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR256_PIXEL_COUNTERS(x) CSI_CR256_PIXEL_COUNTERS(x) +#define CSI_CSICR257_PIXEL_COUNTERS_MASK CSI_CR257_PIXEL_COUNTERS_MASK +#define CSI_CSICR257_PIXEL_COUNTERS_SHIFT CSI_CR257_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR257_PIXEL_COUNTERS(x) CSI_CR257_PIXEL_COUNTERS(x) +#define CSI_CSICR258_PIXEL_COUNTERS_MASK CSI_CR258_PIXEL_COUNTERS_MASK +#define CSI_CSICR258_PIXEL_COUNTERS_SHIFT CSI_CR258_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR258_PIXEL_COUNTERS(x) CSI_CR258_PIXEL_COUNTERS(x) +#define CSI_CSICR259_PIXEL_COUNTERS_MASK CSI_CR259_PIXEL_COUNTERS_MASK +#define CSI_CSICR259_PIXEL_COUNTERS_SHIFT CSI_CR259_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR259_PIXEL_COUNTERS(x) CSI_CR259_PIXEL_COUNTERS(x) +#define CSI_CSICR260_PIXEL_COUNTERS_MASK CSI_CR260_PIXEL_COUNTERS_MASK +#define CSI_CSICR260_PIXEL_COUNTERS_SHIFT CSI_CR260_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR260_PIXEL_COUNTERS(x) CSI_CR260_PIXEL_COUNTERS(x) +#define CSI_CSICR261_PIXEL_COUNTERS_MASK CSI_CR261_PIXEL_COUNTERS_MASK +#define CSI_CSICR261_PIXEL_COUNTERS_SHIFT CSI_CR261_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR261_PIXEL_COUNTERS(x) CSI_CR261_PIXEL_COUNTERS(x) +#define CSI_CSICR262_PIXEL_COUNTERS_MASK CSI_CR262_PIXEL_COUNTERS_MASK +#define CSI_CSICR262_PIXEL_COUNTERS_SHIFT CSI_CR262_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR262_PIXEL_COUNTERS(x) CSI_CR262_PIXEL_COUNTERS(x) +#define CSI_CSICR263_PIXEL_COUNTERS_MASK CSI_CR263_PIXEL_COUNTERS_MASK +#define CSI_CSICR263_PIXEL_COUNTERS_SHIFT CSI_CR263_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR263_PIXEL_COUNTERS(x) CSI_CR263_PIXEL_COUNTERS(x) +#define CSI_CSICR264_PIXEL_COUNTERS_MASK CSI_CR264_PIXEL_COUNTERS_MASK +#define CSI_CSICR264_PIXEL_COUNTERS_SHIFT CSI_CR264_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR264_PIXEL_COUNTERS(x) CSI_CR264_PIXEL_COUNTERS(x) +#define CSI_CSICR265_PIXEL_COUNTERS_MASK CSI_CR265_PIXEL_COUNTERS_MASK +#define CSI_CSICR265_PIXEL_COUNTERS_SHIFT CSI_CR265_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR265_PIXEL_COUNTERS(x) CSI_CR265_PIXEL_COUNTERS(x) +#define CSI_CSICR266_PIXEL_COUNTERS_MASK CSI_CR266_PIXEL_COUNTERS_MASK +#define CSI_CSICR266_PIXEL_COUNTERS_SHIFT CSI_CR266_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR266_PIXEL_COUNTERS(x) CSI_CR266_PIXEL_COUNTERS(x) +#define CSI_CSICR267_PIXEL_COUNTERS_MASK CSI_CR267_PIXEL_COUNTERS_MASK +#define CSI_CSICR267_PIXEL_COUNTERS_SHIFT CSI_CR267_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR267_PIXEL_COUNTERS(x) CSI_CR267_PIXEL_COUNTERS(x) +#define CSI_CSICR268_PIXEL_COUNTERS_MASK CSI_CR268_PIXEL_COUNTERS_MASK +#define CSI_CSICR268_PIXEL_COUNTERS_SHIFT CSI_CR268_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR268_PIXEL_COUNTERS(x) CSI_CR268_PIXEL_COUNTERS(x) +#define CSI_CSICR269_PIXEL_COUNTERS_MASK CSI_CR269_PIXEL_COUNTERS_MASK +#define CSI_CSICR269_PIXEL_COUNTERS_SHIFT CSI_CR269_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR269_PIXEL_COUNTERS(x) CSI_CR269_PIXEL_COUNTERS(x) +#define CSI_CSICR270_PIXEL_COUNTERS_MASK CSI_CR270_PIXEL_COUNTERS_MASK +#define CSI_CSICR270_PIXEL_COUNTERS_SHIFT CSI_CR270_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR270_PIXEL_COUNTERS(x) CSI_CR270_PIXEL_COUNTERS(x) +#define CSI_CSICR271_PIXEL_COUNTERS_MASK CSI_CR271_PIXEL_COUNTERS_MASK +#define CSI_CSICR271_PIXEL_COUNTERS_SHIFT CSI_CR271_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR271_PIXEL_COUNTERS(x) CSI_CR271_PIXEL_COUNTERS(x) +#define CSI_CSICR272_PIXEL_COUNTERS_MASK CSI_CR272_PIXEL_COUNTERS_MASK +#define CSI_CSICR272_PIXEL_COUNTERS_SHIFT CSI_CR272_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR272_PIXEL_COUNTERS(x) CSI_CR272_PIXEL_COUNTERS(x) +#define CSI_CSICR273_PIXEL_COUNTERS_MASK CSI_CR273_PIXEL_COUNTERS_MASK +#define CSI_CSICR273_PIXEL_COUNTERS_SHIFT CSI_CR273_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR273_PIXEL_COUNTERS(x) CSI_CR273_PIXEL_COUNTERS(x) +#define CSI_CSICR274_PIXEL_COUNTERS_MASK CSI_CR274_PIXEL_COUNTERS_MASK +#define CSI_CSICR274_PIXEL_COUNTERS_SHIFT CSI_CR274_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR274_PIXEL_COUNTERS(x) CSI_CR274_PIXEL_COUNTERS(x) +#define CSI_CSICR275_PIXEL_COUNTERS_MASK CSI_CR275_PIXEL_COUNTERS_MASK +#define CSI_CSICR275_PIXEL_COUNTERS_SHIFT CSI_CR275_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR275_PIXEL_COUNTERS(x) CSI_CR275_PIXEL_COUNTERS(x) +#define CSI_CSICR276_PIXEL_COUNTERS_MASK CSI_CR276_PIXEL_COUNTERS_MASK +#define CSI_CSICR276_PIXEL_COUNTERS_SHIFT CSI_CR276_PIXEL_COUNTERS_SHIFT +#define CSI_CSICR276_PIXEL_COUNTERS(x) CSI_CR276_PIXEL_COUNTERS(x) + + +/*! + * @} + */ /* end of group CSI_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DAC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer + * @{ + */ + +/** DAC - Register Layout Typedef */ +typedef struct { + __I uint32_t VERID; /**< Version Identifier Register, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __O uint32_t DATA; /**< DAC Data Register, offset: 0x8 */ + __IO uint32_t CR; /**< DAC Status and Control Register, offset: 0xC */ + __I uint32_t PTR; /**< DAC FIFO Pointer Register, offset: 0x10 */ + __IO uint32_t CR2; /**< DAC Status and Control Register 2, offset: 0x14 */ +} DAC_Type; + +/* ---------------------------------------------------------------------------- + -- DAC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DAC_Register_Masks DAC Register Masks + * @{ + */ + +/*! @name VERID - Version Identifier Register */ +/*! @{ */ + +#define DAC_VERID_FEATURE_MASK (0xFFFFU) +#define DAC_VERID_FEATURE_SHIFT (0U) +/*! FEATURE - Feature Identification Number + * 0b0000000000000000..Standard feature set + * 0b0000000000000001..C40 feature set + * 0b0000000000000010..5V DAC feature set + * 0b0000000000000100..ADC BIST feature set + */ +#define DAC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_FEATURE_SHIFT)) & DAC_VERID_FEATURE_MASK) + +#define DAC_VERID_MINOR_MASK (0xFF0000U) +#define DAC_VERID_MINOR_SHIFT (16U) +/*! MINOR - Minor version number + */ +#define DAC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MINOR_SHIFT)) & DAC_VERID_MINOR_MASK) + +#define DAC_VERID_MAJOR_MASK (0xFF000000U) +#define DAC_VERID_MAJOR_SHIFT (24U) +/*! MAJOR - Major version number + */ +#define DAC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MAJOR_SHIFT)) & DAC_VERID_MAJOR_MASK) +/*! @} */ + +/*! @name PARAM - Parameter Register */ +/*! @{ */ + +#define DAC_PARAM_FIFOSZ_MASK (0x7U) +#define DAC_PARAM_FIFOSZ_SHIFT (0U) +/*! FIFOSZ - FIFO size + * 0b000..FIFO depth is 2 + * 0b001..FIFO depth is 4 + * 0b010..FIFO depth is 8 + * 0b011..FIFO depth is 16 + * 0b100..FIFO depth is 32 + * 0b101..FIFO depth is 64 + * 0b110..FIFO depth is 128 + * 0b111..FIFO depth is 256 + */ +#define DAC_PARAM_FIFOSZ(x) (((uint32_t)(((uint32_t)(x)) << DAC_PARAM_FIFOSZ_SHIFT)) & DAC_PARAM_FIFOSZ_MASK) +/*! @} */ + +/*! @name DATA - DAC Data Register */ +/*! @{ */ + +#define DAC_DATA_DATA0_MASK (0xFFFU) +#define DAC_DATA_DATA0_SHIFT (0U) +/*! DATA0 - FIFO DATA0 + */ +#define DAC_DATA_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DAC_DATA_DATA0_SHIFT)) & DAC_DATA_DATA0_MASK) +/*! @} */ + +/*! @name CR - DAC Status and Control Register */ +/*! @{ */ + +#define DAC_CR_FULLF_MASK (0x1U) +#define DAC_CR_FULLF_SHIFT (0U) +/*! FULLF - Full Flag + * 0b0..FIFO is not full. + * 0b1..FIFO is full. + */ +#define DAC_CR_FULLF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLF_SHIFT)) & DAC_CR_FULLF_MASK) + +#define DAC_CR_NEMPTF_MASK (0x2U) +#define DAC_CR_NEMPTF_SHIFT (1U) +/*! NEMPTF - Nearly Empty Flag + * 0b0..More than one data is available in the FIFO. + * 0b1..One data is available in the FIFO. + */ +#define DAC_CR_NEMPTF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_NEMPTF_SHIFT)) & DAC_CR_NEMPTF_MASK) + +#define DAC_CR_WMF_MASK (0x4U) +#define DAC_CR_WMF_SHIFT (2U) +/*! WMF - FIFO Watermark Status Flag + * 0b0..The DAC buffer read pointer has not reached the watermark level. + * 0b1..The DAC buffer read pointer has reached the watermark level. + */ +#define DAC_CR_WMF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WMF_SHIFT)) & DAC_CR_WMF_MASK) + +#define DAC_CR_UDFF_MASK (0x8U) +#define DAC_CR_UDFF_SHIFT (3U) +/*! UDFF - Underflow Flag + * 0b0..No underflow has occurred since the last time the flag was cleared. + * 0b1..At least one trigger underflow has occurred since the last time the flag was cleared. + */ +#define DAC_CR_UDFF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_UDFF_SHIFT)) & DAC_CR_UDFF_MASK) + +#define DAC_CR_OVFF_MASK (0x10U) +#define DAC_CR_OVFF_SHIFT (4U) +/*! OVFF - Overflow Flag + * 0b0..No overflow has occurred since the last time the flag was cleared. + * 0b1..At least one FIFO overflow has occurred since the last time the flag was cleared. + */ +#define DAC_CR_OVFF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_OVFF_SHIFT)) & DAC_CR_OVFF_MASK) + +#define DAC_CR_FULLIE_MASK (0x100U) +#define DAC_CR_FULLIE_SHIFT (8U) +/*! FULLIE - Full Interrupt Enable + * 0b0..FIFO Full interrupt is disabled. + * 0b1..FIFO Full interrupt is enabled. + */ +#define DAC_CR_FULLIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLIE_SHIFT)) & DAC_CR_FULLIE_MASK) + +#define DAC_CR_EMPTIE_MASK (0x200U) +#define DAC_CR_EMPTIE_SHIFT (9U) +/*! EMPTIE - Nearly Empty Interrupt Enable + * 0b0..FIFO Nearly Empty interrupt is disabled. + * 0b1..FIFO Nearly Empty interrupt is enabled. + */ +#define DAC_CR_EMPTIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_EMPTIE_SHIFT)) & DAC_CR_EMPTIE_MASK) + +#define DAC_CR_WTMIE_MASK (0x400U) +#define DAC_CR_WTMIE_SHIFT (10U) +/*! WTMIE - Watermark Interrupt Enable + * 0b0..Watermark interrupt is disabled. + * 0b1..Watermark interrupt is enabled. + */ +#define DAC_CR_WTMIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WTMIE_SHIFT)) & DAC_CR_WTMIE_MASK) + +#define DAC_CR_SWTRG_MASK (0x1000U) +#define DAC_CR_SWTRG_SHIFT (12U) +/*! SWTRG - DAC Software Trigger + * 0b0..The DAC soft trigger is not valid. + * 0b1..The DAC soft trigger is valid. + */ +#define DAC_CR_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWTRG_SHIFT)) & DAC_CR_SWTRG_MASK) + +#define DAC_CR_TRGSEL_MASK (0x2000U) +#define DAC_CR_TRGSEL_SHIFT (13U) +/*! TRGSEL - DAC Trigger Select + * 0b0..The DAC hardware trigger is selected. + * 0b1..The DAC software trigger is selected. + */ +#define DAC_CR_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_TRGSEL_SHIFT)) & DAC_CR_TRGSEL_MASK) + +#define DAC_CR_DACRFS_MASK (0x4000U) +#define DAC_CR_DACRFS_SHIFT (14U) +/*! DACRFS - DAC Reference Select + * 0b0..The DAC selects DACREF_1 as the reference voltage. + * 0b1..The DAC selects DACREF_2 as the reference voltage. + */ +#define DAC_CR_DACRFS(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACRFS_SHIFT)) & DAC_CR_DACRFS_MASK) + +#define DAC_CR_DACEN_MASK (0x8000U) +#define DAC_CR_DACEN_SHIFT (15U) +/*! DACEN - DAC Enable + * 0b0..The DAC system is disabled. + * 0b1..The DAC system is enabled. + */ +#define DAC_CR_DACEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACEN_SHIFT)) & DAC_CR_DACEN_MASK) + +#define DAC_CR_FIFOEN_MASK (0x10000U) +#define DAC_CR_FIFOEN_SHIFT (16U) +/*! FIFOEN - FIFO Enable + * 0b0..FIFO is disabled and only one level buffer is enabled. Any data written from this buffer goes to conversion. + * 0b1..FIFO is enabled. Data will first read from FIFO to buffer then go to conversion. + */ +#define DAC_CR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFOEN_SHIFT)) & DAC_CR_FIFOEN_MASK) + +#define DAC_CR_SWMD_MASK (0x20000U) +#define DAC_CR_SWMD_SHIFT (17U) +/*! SWMD - DAC FIFO Mode Select + * 0b0..Normal mode + * 0b1..Swing back mode + */ +#define DAC_CR_SWMD(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWMD_SHIFT)) & DAC_CR_SWMD_MASK) + +#define DAC_CR_UVIE_MASK (0x40000U) +#define DAC_CR_UVIE_SHIFT (18U) +/*! UVIE - Underflow and overflow interrupt enable + * 0b0..Underflow and overflow interrupt is disabled. + * 0b1..Underflow and overflow interrupt is enabled. + */ +#define DAC_CR_UVIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_UVIE_SHIFT)) & DAC_CR_UVIE_MASK) + +#define DAC_CR_FIFORST_MASK (0x200000U) +#define DAC_CR_FIFORST_SHIFT (21U) +/*! FIFORST - FIFO Reset + * 0b0..No effect + * 0b1..FIFO reset + */ +#define DAC_CR_FIFORST(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFORST_SHIFT)) & DAC_CR_FIFORST_MASK) + +#define DAC_CR_SWRST_MASK (0x400000U) +#define DAC_CR_SWRST_SHIFT (22U) +/*! SWRST - Software reset + */ +#define DAC_CR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWRST_SHIFT)) & DAC_CR_SWRST_MASK) + +#define DAC_CR_DMAEN_MASK (0x800000U) +#define DAC_CR_DMAEN_SHIFT (23U) +/*! DMAEN - DMA Enable Select + * 0b0..DMA is disabled. + * 0b1..DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The + * interrupts will not be presented on this module at the same time. + */ +#define DAC_CR_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DMAEN_SHIFT)) & DAC_CR_DMAEN_MASK) + +#define DAC_CR_WML_MASK (0xFF000000U) +#define DAC_CR_WML_SHIFT (24U) +/*! WML - Watermark Level Select + */ +#define DAC_CR_WML(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WML_SHIFT)) & DAC_CR_WML_MASK) +/*! @} */ + +/*! @name PTR - DAC FIFO Pointer Register */ +/*! @{ */ + +#define DAC_PTR_DACWFP_MASK (0xFFU) +#define DAC_PTR_DACWFP_SHIFT (0U) +/*! DACWFP - DACWFP + */ +#define DAC_PTR_DACWFP(x) (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACWFP_SHIFT)) & DAC_PTR_DACWFP_MASK) + +#define DAC_PTR_DACRFP_MASK (0xFF0000U) +#define DAC_PTR_DACRFP_SHIFT (16U) +/*! DACRFP - DACRFP + */ +#define DAC_PTR_DACRFP(x) (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACRFP_SHIFT)) & DAC_PTR_DACRFP_MASK) +/*! @} */ + +/*! @name CR2 - DAC Status and Control Register 2 */ +/*! @{ */ + +#define DAC_CR2_BFEN_MASK (0x1U) +#define DAC_CR2_BFEN_SHIFT (0U) +/*! BFEN - Buffer Enable + * 0b0..Opamp is not used as buffer + * 0b1..Opamp is used as buffer + */ +#define DAC_CR2_BFEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFEN_SHIFT)) & DAC_CR2_BFEN_MASK) + +#define DAC_CR2_OEN_MASK (0x2U) +#define DAC_CR2_OEN_SHIFT (1U) +/*! OEN - Optional Enable + * 0b0..Output buffer is not bypassed + * 0b1..Output buffer is bypassed + */ +#define DAC_CR2_OEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_OEN_SHIFT)) & DAC_CR2_OEN_MASK) + +#define DAC_CR2_BFMS_MASK (0x4U) +#define DAC_CR2_BFMS_SHIFT (2U) +/*! BFMS - Buffer Middle Speed Select + * 0b0..Buffer middle speed not selected + * 0b1..Buffer middle speed selected + */ +#define DAC_CR2_BFMS(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFMS_SHIFT)) & DAC_CR2_BFMS_MASK) + +#define DAC_CR2_BFHS_MASK (0x8U) +#define DAC_CR2_BFHS_SHIFT (3U) +/*! BFHS - Buffer High Speed Select + * 0b0..Buffer high speed not selected + * 0b1..Buffer high speed selected + */ +#define DAC_CR2_BFHS(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFHS_SHIFT)) & DAC_CR2_BFHS_MASK) + +#define DAC_CR2_IREF2_MASK (0x10U) +#define DAC_CR2_IREF2_SHIFT (4U) +/*! IREF2 - Internal PTAT (Proportional To Absolute Temperature) Current Reference Select + * 0b0..Internal PTAT Current Reference not selected + * 0b1..Internal PTAT Current Reference selected + */ +#define DAC_CR2_IREF2(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF2_SHIFT)) & DAC_CR2_IREF2_MASK) + +#define DAC_CR2_IREF1_MASK (0x20U) +#define DAC_CR2_IREF1_SHIFT (5U) +/*! IREF1 - Internal ZTC (Zero Temperature Coefficient) Current Reference Select + * 0b0..Internal ZTC Current Reference not selected + * 0b1..Internal ZTC Current Reference selected + */ +#define DAC_CR2_IREF1(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF1_SHIFT)) & DAC_CR2_IREF1_MASK) + +#define DAC_CR2_IREF_MASK (0x40U) +#define DAC_CR2_IREF_SHIFT (6U) +/*! IREF - Internal Current Reference Select + * 0b0..Internal Current Reference not selected + * 0b1..Internal Current Reference selected + */ +#define DAC_CR2_IREF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF_SHIFT)) & DAC_CR2_IREF_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DAC_Register_Masks */ + + +/* DAC - Peripheral instance base addresses */ +/** Peripheral DAC base address */ +#define DAC_BASE (0x40064000u) +/** Peripheral DAC base pointer */ +#define DAC ((DAC_Type *)DAC_BASE) +/** Array initializer of DAC peripheral base addresses */ +#define DAC_BASE_ADDRS { DAC_BASE } +/** Array initializer of DAC peripheral base pointers */ +#define DAC_BASE_PTRS { DAC } +/** Interrupt vectors for the DAC peripheral type */ +#define DAC_IRQS { DAC_IRQn } + +/*! + * @} + */ /* end of group DAC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DCDC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCDC_Peripheral_Access_Layer DCDC Peripheral Access Layer + * @{ + */ + +/** DCDC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CTRL0; /**< DCDC Control Register 0, offset: 0x0 */ + __IO uint32_t CTRL1; /**< DCDC Control Register 1, offset: 0x4 */ + __IO uint32_t REG0; /**< DCDC Register 0, offset: 0x8 */ + __IO uint32_t REG1; /**< DCDC Register 1, offset: 0xC */ + __IO uint32_t REG2; /**< DCDC Register 2, offset: 0x10 */ + __IO uint32_t REG3; /**< DCDC Register 3, offset: 0x14 */ + __IO uint32_t REG4; /**< DCDC Register 4, offset: 0x18 */ + __IO uint32_t REG5; /**< DCDC Register 5, offset: 0x1C */ + __IO uint32_t REG6; /**< DCDC Register 6, offset: 0x20 */ + __IO uint32_t REG7; /**< DCDC Register 7, offset: 0x24 */ + __IO uint32_t REG7P; /**< DCDC Register 7 plus, offset: 0x28 */ + __IO uint32_t REG8; /**< DCDC Register 8, offset: 0x2C */ + __IO uint32_t REG9; /**< DCDC Register 9, offset: 0x30 */ + __IO uint32_t REG10; /**< DCDC Register 10, offset: 0x34 */ + __IO uint32_t REG11; /**< DCDC Register 11, offset: 0x38 */ + __IO uint32_t REG12; /**< DCDC Register 12, offset: 0x3C */ + __IO uint32_t REG13; /**< DCDC Register 13, offset: 0x40 */ + __IO uint32_t REG14; /**< DCDC Register 14, offset: 0x44 */ + __IO uint32_t REG15; /**< DCDC Register 15, offset: 0x48 */ + __IO uint32_t REG16; /**< DCDC Register 16, offset: 0x4C */ + __IO uint32_t REG17; /**< DCDC Register 17, offset: 0x50 */ + __IO uint32_t REG18; /**< DCDC Register 18, offset: 0x54 */ + __IO uint32_t REG19; /**< DCDC Register 19, offset: 0x58 */ + __IO uint32_t REG20; /**< DCDC Register 20, offset: 0x5C */ + __IO uint32_t REG21; /**< DCDC Register 21, offset: 0x60 */ + __IO uint32_t REG22; /**< DCDC Register 22, offset: 0x64 */ + __IO uint32_t REG23; /**< DCDC Register 23, offset: 0x68 */ + __IO uint32_t REG24; /**< DCDC Register 24, offset: 0x6C */ +} DCDC_Type; + +/* ---------------------------------------------------------------------------- + -- DCDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCDC_Register_Masks DCDC Register Masks + * @{ + */ + +/*! @name CTRL0 - DCDC Control Register 0 */ +/*! @{ */ + +#define DCDC_CTRL0_ENABLE_MASK (0x1U) +#define DCDC_CTRL0_ENABLE_SHIFT (0U) +/*! ENABLE + * 0b0..Disable (Bypass) + * 0b1..Enable + */ +#define DCDC_CTRL0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_SHIFT)) & DCDC_CTRL0_ENABLE_MASK) + +#define DCDC_CTRL0_DIG_EN_MASK (0x2U) +#define DCDC_CTRL0_DIG_EN_SHIFT (1U) +/*! DIG_EN + * 0b0..Reserved + * 0b1..Enable + */ +#define DCDC_CTRL0_DIG_EN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_DIG_EN_SHIFT)) & DCDC_CTRL0_DIG_EN_MASK) + +#define DCDC_CTRL0_STBY_EN_MASK (0x4U) +#define DCDC_CTRL0_STBY_EN_SHIFT (2U) +/*! STBY_EN + * 0b1..Enter into standby mode + */ +#define DCDC_CTRL0_STBY_EN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_STBY_EN_SHIFT)) & DCDC_CTRL0_STBY_EN_MASK) + +#define DCDC_CTRL0_LP_MODE_EN_MASK (0x8U) +#define DCDC_CTRL0_LP_MODE_EN_SHIFT (3U) +/*! LP_MODE_EN + * 0b1..Enter into low-power mode + */ +#define DCDC_CTRL0_LP_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_LP_MODE_EN_SHIFT)) & DCDC_CTRL0_LP_MODE_EN_MASK) + +#define DCDC_CTRL0_STBY_LP_MODE_EN_MASK (0x10U) +#define DCDC_CTRL0_STBY_LP_MODE_EN_SHIFT (4U) +/*! STBY_LP_MODE_EN + * 0b0..Disable DCDC entry into low-power mode from a GPC standby request + * 0b1..Enable DCDC to enter into low-power mode from a GPC standby request + */ +#define DCDC_CTRL0_STBY_LP_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_STBY_LP_MODE_EN_SHIFT)) & DCDC_CTRL0_STBY_LP_MODE_EN_MASK) + +#define DCDC_CTRL0_ENABLE_DCDC_CNT_MASK (0x20U) +#define DCDC_CTRL0_ENABLE_DCDC_CNT_SHIFT (5U) +/*! ENABLE_DCDC_CNT - Enable internal count for DCDC_OK timeout + * 0b0..Wait DCDC_OK for ACK + * 0b1..Enable internal count for DCDC_OK timeout + */ +#define DCDC_CTRL0_ENABLE_DCDC_CNT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_DCDC_CNT_SHIFT)) & DCDC_CTRL0_ENABLE_DCDC_CNT_MASK) + +#define DCDC_CTRL0_TRIM_HOLD_MASK (0x40U) +#define DCDC_CTRL0_TRIM_HOLD_SHIFT (6U) +/*! TRIM_HOLD - Hold trim input + * 0b0..Sample trim input + * 0b1..Hold trim input + */ +#define DCDC_CTRL0_TRIM_HOLD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_TRIM_HOLD_SHIFT)) & DCDC_CTRL0_TRIM_HOLD_MASK) + +#define DCDC_CTRL0_DEBUG_BITS_MASK (0x7FF80000U) +#define DCDC_CTRL0_DEBUG_BITS_SHIFT (19U) +/*! DEBUG_BITS - DEBUG_BITS[11:0] + */ +#define DCDC_CTRL0_DEBUG_BITS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_DEBUG_BITS_SHIFT)) & DCDC_CTRL0_DEBUG_BITS_MASK) + +#define DCDC_CTRL0_CONTROL_MODE_MASK (0x80000000U) +#define DCDC_CTRL0_CONTROL_MODE_SHIFT (31U) +/*! CONTROL_MODE - Control mode + * 0b0..Software control mode + * 0b1..Hardware control mode (controlled by GPC Setpoints) + */ +#define DCDC_CTRL0_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_CONTROL_MODE_SHIFT)) & DCDC_CTRL0_CONTROL_MODE_MASK) +/*! @} */ + +/*! @name CTRL1 - DCDC Control Register 1 */ +/*! @{ */ + +#define DCDC_CTRL1_VDD1P8CTRL_TRG_MASK (0x1FU) +#define DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT (0U) +/*! VDD1P8CTRL_TRG + * 0b11111..2.275V + * 0b01100..1.8V + * 0b00000..1.5V + */ +#define DCDC_CTRL1_VDD1P8CTRL_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT)) & DCDC_CTRL1_VDD1P8CTRL_TRG_MASK) + +#define DCDC_CTRL1_VDD1P0CTRL_TRG_MASK (0x1F00U) +#define DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT (8U) +/*! VDD1P0CTRL_TRG + * 0b11111..1.375V + * 0b10000..1.0V + * 0b00000..0.6V + */ +#define DCDC_CTRL1_VDD1P0CTRL_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT)) & DCDC_CTRL1_VDD1P0CTRL_TRG_MASK) + +#define DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK (0x1F0000U) +#define DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT (16U) +/*! VDD1P8CTRL_STBY_TRG + * 0b11111..2.3V + * 0b01011..1.8V + * 0b00000..1.525V + */ +#define DCDC_CTRL1_VDD1P8CTRL_STBY_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT)) & DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK) + +#define DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK (0x1F000000U) +#define DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT (24U) +/*! VDD1P0CTRL_STBY_TRG + * 0b11111..1.4V + * 0b01111..1.0V + * 0b00000..0.625V + */ +#define DCDC_CTRL1_VDD1P0CTRL_STBY_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT)) & DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK) +/*! @} */ + +/*! @name REG0 - DCDC Register 0 */ +/*! @{ */ + +#define DCDC_REG0_PWD_ZCD_MASK (0x1U) +#define DCDC_REG0_PWD_ZCD_SHIFT (0U) +/*! PWD_ZCD - Power Down Zero Cross Detection + * 0b0..Zero cross detetion function powered up + * 0b1..Zero cross detetion function powered down + */ +#define DCDC_REG0_PWD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK) + +#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U) +#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U) +/*! DISABLE_AUTO_CLK_SWITCH - Disable Auto Clock Switch + * 0b0..If DISABLE_AUTO_CLK_SWITCH is set to 0 and 24M xtal is OK, the clock source will switch from internal + * ring oscillator to 24M xtal automatically + * 0b1..If DISABLE_AUTO_CLK_SWITCH is set to 1, SEL_CLK will determine which clock source the DCDC uses + */ +#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK) + +#define DCDC_REG0_SEL_CLK_MASK (0x4U) +#define DCDC_REG0_SEL_CLK_SHIFT (2U) +/*! SEL_CLK - Select Clock + * 0b0..DCDC uses internal ring oscillator + * 0b1..DCDC uses 24M xtal + */ +#define DCDC_REG0_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK) + +#define DCDC_REG0_PWD_OSC_INT_MASK (0x8U) +#define DCDC_REG0_PWD_OSC_INT_SHIFT (3U) +/*! PWD_OSC_INT - Power down internal ring oscillator + * 0b0..Internal ring oscillator powered up + * 0b1..Internal ring oscillator powered down + */ +#define DCDC_REG0_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK) + +#define DCDC_REG0_PWD_CUR_SNS_CMP_MASK (0x10U) +#define DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT (4U) +/*! PWD_CUR_SNS_CMP - Power down signal of the current detector + * 0b0..Current Detector powered up + * 0b1..Current Detector powered down + */ +#define DCDC_REG0_PWD_CUR_SNS_CMP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK) + +#define DCDC_REG0_CUR_SNS_THRSH_MASK (0xE0U) +#define DCDC_REG0_CUR_SNS_THRSH_SHIFT (5U) +/*! CUR_SNS_THRSH - Current Sense (detector) Threshold + */ +#define DCDC_REG0_CUR_SNS_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK) + +#define DCDC_REG0_PWD_OVERCUR_DET_MASK (0x100U) +#define DCDC_REG0_PWD_OVERCUR_DET_SHIFT (8U) +/*! PWD_OVERCUR_DET - Power down overcurrent detection comparator + * 0b0..Overcurrent detection comparator is enabled + * 0b1..Overcurrent detection comparator is disabled + */ +#define DCDC_REG0_PWD_OVERCUR_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK) + +#define DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK (0x800U) +#define DCDC_REG0_PWD_CMP_DCDC_IN_DET_SHIFT (11U) +/*! PWD_CMP_DCDC_IN_DET + * 0b0..Low voltage detection comparator is enabled + * 0b1..Low voltage detection comparator is disabled + */ +#define DCDC_REG0_PWD_CMP_DCDC_IN_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_DCDC_IN_DET_SHIFT)) & DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK) + +#define DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK (0x10000U) +#define DCDC_REG0_PWD_HIGH_VDD1P8_DET_SHIFT (16U) +/*! PWD_HIGH_VDD1P8_DET - Power Down High Voltage Detection for VDD1P8 + * 0b0..Overvoltage detection comparator for the VDD1P8 output is enabled + * 0b1..Overvoltage detection comparator for the VDD1P8 output is disabled + */ +#define DCDC_REG0_PWD_HIGH_VDD1P8_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VDD1P8_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK) + +#define DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK (0x20000U) +#define DCDC_REG0_PWD_HIGH_VDD1P0_DET_SHIFT (17U) +/*! PWD_HIGH_VDD1P0_DET - Power Down High Voltage Detection for VDD1P0 + * 0b0..Overvoltage detection comparator for the VDD1P0 output is enabled + * 0b1..Overvoltage detection comparator for the VDD1P0 output is disabled + */ +#define DCDC_REG0_PWD_HIGH_VDD1P0_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VDD1P0_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK) + +#define DCDC_REG0_LP_HIGH_HYS_MASK (0x200000U) +#define DCDC_REG0_LP_HIGH_HYS_SHIFT (21U) +/*! LP_HIGH_HYS - Low Power High Hysteric Value + * 0b0..Adjust hysteretic value in low power to 12.5mV + * 0b1..Adjust hysteretic value in low power to 25mV + */ +#define DCDC_REG0_LP_HIGH_HYS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK) + +#define DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U) +#define DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U) +/*! PWD_CMP_OFFSET - power down the out-of-range detection comparator + * 0b0..Out-of-range comparator powered up + * 0b1..Out-of-range comparator powered down + */ +#define DCDC_REG0_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK) + +#define DCDC_REG0_XTALOK_DISABLE_MASK (0x8000000U) +#define DCDC_REG0_XTALOK_DISABLE_SHIFT (27U) +/*! XTALOK_DISABLE - Disable xtalok detection circuit + * 0b0..Enable xtalok detection circuit + * 0b1..Disable xtalok detection circuit and always outputs OK signal "1" + */ +#define DCDC_REG0_XTALOK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK) + +#define DCDC_REG0_XTAL_24M_OK_MASK (0x20000000U) +#define DCDC_REG0_XTAL_24M_OK_SHIFT (29U) +/*! XTAL_24M_OK - 24M XTAL OK + * 0b0..DCDC uses internal ring oscillator + * 0b1..DCDC uses xtal 24M + */ +#define DCDC_REG0_XTAL_24M_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK) + +#define DCDC_REG0_STS_DC_OK_MASK (0x80000000U) +#define DCDC_REG0_STS_DC_OK_SHIFT (31U) +/*! STS_DC_OK - DCDC Output OK + * 0b0..DCDC is settling + * 0b1..DCDC already settled + */ +#define DCDC_REG0_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK) +/*! @} */ + +/*! @name REG1 - DCDC Register 1 */ +/*! @{ */ + +#define DCDC_REG1_DM_CTRL_MASK (0x8U) +#define DCDC_REG1_DM_CTRL_SHIFT (3U) +/*! DM_CTRL - DM Control + * 0b0..No change to ripple when the discontinuous current is present in DCM. + * 0b1..Improves ripple when the inductor current goes to zero in DCM. + */ +#define DCDC_REG1_DM_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_DM_CTRL_SHIFT)) & DCDC_REG1_DM_CTRL_MASK) + +#define DCDC_REG1_RLOAD_REG_EN_LPSR_MASK (0x10U) +#define DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT (4U) +/*! RLOAD_REG_EN_LPSR - Load Resistor Enable + * 0b0..Disconnect load resistor + * 0b1..Connect load resistor + */ +#define DCDC_REG1_RLOAD_REG_EN_LPSR(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT)) & DCDC_REG1_RLOAD_REG_EN_LPSR_MASK) + +#define DCDC_REG1_VBG_TRIM_MASK (0x7C0U) +#define DCDC_REG1_VBG_TRIM_SHIFT (6U) +/*! VBG_TRIM - Trim Bandgap Voltage + * 0b00000..0.452V + * 0b10000..0.5V + * 0b11111..0.545V + */ +#define DCDC_REG1_VBG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK) + +#define DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x1800U) +#define DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (11U) +/*! LP_CMP_ISRC_SEL - Low Power Comparator Current Bias + * 0b00..50nA + * 0b01..100nA + * 0b10..200nA + * 0b11..400nA + */ +#define DCDC_REG1_LP_CMP_ISRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK) + +#define DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK (0x8000000U) +#define DCDC_REG1_LOOPCTRL_CM_HST_THRESH_SHIFT (27U) +/*! LOOPCTRL_CM_HST_THRESH - Increase Threshold Detection + */ +#define DCDC_REG1_LOOPCTRL_CM_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_CM_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK) + +#define DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK (0x10000000U) +#define DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT (28U) +/*! LOOPCTRL_DF_HST_THRESH - Increase Threshold Detection + */ +#define DCDC_REG1_LOOPCTRL_DF_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK) + +#define DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK (0x20000000U) +#define DCDC_REG1_LOOPCTRL_EN_CM_HYST_SHIFT (29U) +/*! LOOPCTRL_EN_CM_HYST + * 0b0..Disable hysteresis in switching converter common mode analog comparators + * 0b1..Enable hysteresis in switching converter common mode analog comparators + */ +#define DCDC_REG1_LOOPCTRL_EN_CM_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_CM_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK) + +#define DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK (0x40000000U) +#define DCDC_REG1_LOOPCTRL_EN_DF_HYST_SHIFT (30U) +/*! LOOPCTRL_EN_DF_HYST + * 0b0..Disable hysteresis in switching converter differential mode analog comparators + * 0b1..Enable hysteresis in switching converter differential mode analog comparators + */ +#define DCDC_REG1_LOOPCTRL_EN_DF_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_DF_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK) +/*! @} */ + +/*! @name REG2 - DCDC Register 2 */ +/*! @{ */ + +#define DCDC_REG2_LOOPCTRL_DC_C_MASK (0x3U) +#define DCDC_REG2_LOOPCTRL_DC_C_SHIFT (0U) +#define DCDC_REG2_LOOPCTRL_DC_C(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK) + +#define DCDC_REG2_LOOPCTRL_DC_R_MASK (0x3CU) +#define DCDC_REG2_LOOPCTRL_DC_R_SHIFT (2U) +#define DCDC_REG2_LOOPCTRL_DC_R(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK) + +#define DCDC_REG2_LOOPCTRL_DC_FF_MASK (0x1C0U) +#define DCDC_REG2_LOOPCTRL_DC_FF_SHIFT (6U) +#define DCDC_REG2_LOOPCTRL_DC_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK) + +#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK (0xE00U) +#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT (9U) +/*! LOOPCTRL_EN_RCSCALE - Enable RC Scale + */ +#define DCDC_REG2_LOOPCTRL_EN_RCSCALE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK) + +#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK (0x1000U) +#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT (12U) +#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK) + +#define DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK (0x2000U) +#define DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT (13U) +#define DCDC_REG2_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK) + +#define DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK (0x8000U) +#define DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT (15U) +#define DCDC_REG2_BATTMONITOR_EN_BATADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT)) & DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK) + +#define DCDC_REG2_BATTMONITOR_BATT_VAL_MASK (0x3FF0000U) +#define DCDC_REG2_BATTMONITOR_BATT_VAL_SHIFT (16U) +#define DCDC_REG2_BATTMONITOR_BATT_VAL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_BATTMONITOR_BATT_VAL_SHIFT)) & DCDC_REG2_BATTMONITOR_BATT_VAL_MASK) + +#define DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U) +#define DCDC_REG2_DCM_SET_CTRL_SHIFT (28U) +/*! DCM_SET_CTRL - DCM Set Control + */ +#define DCDC_REG2_DCM_SET_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK) + +#define DCDC_REG2_LOOPCTRL_TOGGLE_DIF_MASK (0x40000000U) +#define DCDC_REG2_LOOPCTRL_TOGGLE_DIF_SHIFT (30U) +#define DCDC_REG2_LOOPCTRL_TOGGLE_DIF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_TOGGLE_DIF_SHIFT)) & DCDC_REG2_LOOPCTRL_TOGGLE_DIF_MASK) +/*! @} */ + +/*! @name REG3 - DCDC Register 3 */ +/*! @{ */ + +#define DCDC_REG3_IN_BROWNOUT_MASK (0x4000U) +#define DCDC_REG3_IN_BROWNOUT_SHIFT (14U) +/*! IN_BROWNOUT + * 0b1..DCDC_IN is lower than 2.6V + */ +#define DCDC_REG3_IN_BROWNOUT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_IN_BROWNOUT_SHIFT)) & DCDC_REG3_IN_BROWNOUT_MASK) + +#define DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_MASK (0x8000U) +#define DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_SHIFT (15U) +/*! OVERVOLT_VDD1P8_DET_OUT + * 0b1..VDD1P8 Overvoltage + */ +#define DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_SHIFT)) & DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_MASK) + +#define DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_MASK (0x10000U) +#define DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_SHIFT (16U) +/*! OVERVOLT_VDD1P0_DET_OUT + * 0b1..VDD1P0 Overvoltage + */ +#define DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_SHIFT)) & DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_MASK) + +#define DCDC_REG3_OVERCUR_DETECT_OUT_MASK (0x20000U) +#define DCDC_REG3_OVERCUR_DETECT_OUT_SHIFT (17U) +/*! OVERCUR_DETECT_OUT + * 0b1..Overcurrent + */ +#define DCDC_REG3_OVERCUR_DETECT_OUT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERCUR_DETECT_OUT_SHIFT)) & DCDC_REG3_OVERCUR_DETECT_OUT_MASK) + +#define DCDC_REG3_ENABLE_FF_MASK (0x40000U) +#define DCDC_REG3_ENABLE_FF_SHIFT (18U) +/*! ENABLE_FF + * 0b1..Enable feed-forward (FF) function that can speed up transient settling. + */ +#define DCDC_REG3_ENABLE_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_ENABLE_FF_SHIFT)) & DCDC_REG3_ENABLE_FF_MASK) + +#define DCDC_REG3_DISABLE_PULSE_SKIP_MASK (0x80000U) +#define DCDC_REG3_DISABLE_PULSE_SKIP_SHIFT (19U) +/*! DISABLE_PULSE_SKIP - Disable Pulse Skip + * 0b0..Stop charging if the duty cycle is lower than what is set by NEGLIMIT_IN + */ +#define DCDC_REG3_DISABLE_PULSE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG3_DISABLE_PULSE_SKIP_MASK) + +#define DCDC_REG3_DISABLE_IDLE_SKIP_MASK (0x100000U) +#define DCDC_REG3_DISABLE_IDLE_SKIP_SHIFT (20U) +/*! DISABLE_IDLE_SKIP + * 0b0..Enable the idle skip function. The DCDC will be idle when out-of-range comparator detects the output + * voltage is higher than the target by 25mV. This function requires the out-of-range comparator to be enabled + * (PWD_CMP_OFFSET=0). + */ +#define DCDC_REG3_DISABLE_IDLE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_IDLE_SKIP_SHIFT)) & DCDC_REG3_DISABLE_IDLE_SKIP_MASK) + +#define DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_MASK (0x200000U) +#define DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_SHIFT (21U) +/*! DOUBLE_IBIAS_CMP_LP_LPSR + * 0b1..Double the bias current of the comparator for low-voltage detector in LP (low-power) mode + */ +#define DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_SHIFT)) & DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_MASK) + +#define DCDC_REG3_REG_FBK_SEL_MASK (0xC00000U) +#define DCDC_REG3_REG_FBK_SEL_SHIFT (22U) +#define DCDC_REG3_REG_FBK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_REG_FBK_SEL_SHIFT)) & DCDC_REG3_REG_FBK_SEL_MASK) + +#define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U) +#define DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT (24U) +/*! MINPWR_DC_HALFCLK + * 0b0..DCDC clock remains at full frequency for continuous mode + * 0b1..DCDC clock set to half frequency for continuous mode + */ +#define DCDC_REG3_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK) + +#define DCDC_REG3_MINPWR_HALF_FETS_MASK (0x4000000U) +#define DCDC_REG3_MINPWR_HALF_FETS_SHIFT (26U) +#define DCDC_REG3_MINPWR_HALF_FETS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_HALF_FETS_SHIFT)) & DCDC_REG3_MINPWR_HALF_FETS_MASK) + +#define DCDC_REG3_MISC_DELAY_TIMING_MASK (0x8000000U) +#define DCDC_REG3_MISC_DELAY_TIMING_SHIFT (27U) +/*! MISC_DELAY_TIMING - Miscellaneous Delay Timing + */ +#define DCDC_REG3_MISC_DELAY_TIMING(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK) + +#define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK (0x20000000U) +#define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT (29U) +/*! VDD1P0CTRL_DISABLE_STEP - Disable Step for VDD1P0 + * 0b0..Enable stepping for VDD1P0 + * 0b1..Disable stepping for VDD1P0 + */ +#define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK) + +#define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK (0x40000000U) +#define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_SHIFT (30U) +/*! VDD1P8CTRL_DISABLE_STEP - Disable Step for VDD1P8 + * 0b0..Enable stepping for VDD1P8 + * 0b1..Disable stepping for VDD1P8 + */ +#define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK) +/*! @} */ + +/*! @name REG4 - DCDC Register 4 */ +/*! @{ */ + +#define DCDC_REG4_ENABLE_SP_MASK (0xFFFFU) +#define DCDC_REG4_ENABLE_SP_SHIFT (0U) +#define DCDC_REG4_ENABLE_SP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG4_ENABLE_SP_SHIFT)) & DCDC_REG4_ENABLE_SP_MASK) +/*! @} */ + +/*! @name REG5 - DCDC Register 5 */ +/*! @{ */ + +#define DCDC_REG5_DIG_EN_SP_MASK (0xFFFFU) +#define DCDC_REG5_DIG_EN_SP_SHIFT (0U) +#define DCDC_REG5_DIG_EN_SP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG5_DIG_EN_SP_SHIFT)) & DCDC_REG5_DIG_EN_SP_MASK) +/*! @} */ + +/*! @name REG6 - DCDC Register 6 */ +/*! @{ */ + +#define DCDC_REG6_LP_MODE_SP_MASK (0xFFFFU) +#define DCDC_REG6_LP_MODE_SP_SHIFT (0U) +#define DCDC_REG6_LP_MODE_SP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG6_LP_MODE_SP_SHIFT)) & DCDC_REG6_LP_MODE_SP_MASK) +/*! @} */ + +/*! @name REG7 - DCDC Register 7 */ +/*! @{ */ + +#define DCDC_REG7_STBY_EN_SP_MASK (0xFFFFU) +#define DCDC_REG7_STBY_EN_SP_SHIFT (0U) +#define DCDC_REG7_STBY_EN_SP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG7_STBY_EN_SP_SHIFT)) & DCDC_REG7_STBY_EN_SP_MASK) +/*! @} */ + +/*! @name REG7P - DCDC Register 7 plus */ +/*! @{ */ + +#define DCDC_REG7P_STBY_LP_MODE_SP_MASK (0xFFFFU) +#define DCDC_REG7P_STBY_LP_MODE_SP_SHIFT (0U) +#define DCDC_REG7P_STBY_LP_MODE_SP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG7P_STBY_LP_MODE_SP_SHIFT)) & DCDC_REG7P_STBY_LP_MODE_SP_MASK) +/*! @} */ + +/*! @name REG8 - DCDC Register 8 */ +/*! @{ */ + +#define DCDC_REG8_ANA_TRG_SP0_MASK (0xFFFFFFFFU) +#define DCDC_REG8_ANA_TRG_SP0_SHIFT (0U) +#define DCDC_REG8_ANA_TRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG8_ANA_TRG_SP0_SHIFT)) & DCDC_REG8_ANA_TRG_SP0_MASK) +/*! @} */ + +/*! @name REG9 - DCDC Register 9 */ +/*! @{ */ + +#define DCDC_REG9_ANA_TRG_SP1_MASK (0xFFFFFFFFU) +#define DCDC_REG9_ANA_TRG_SP1_SHIFT (0U) +#define DCDC_REG9_ANA_TRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG9_ANA_TRG_SP1_SHIFT)) & DCDC_REG9_ANA_TRG_SP1_MASK) +/*! @} */ + +/*! @name REG10 - DCDC Register 10 */ +/*! @{ */ + +#define DCDC_REG10_ANA_TRG_SP2_MASK (0xFFFFFFFFU) +#define DCDC_REG10_ANA_TRG_SP2_SHIFT (0U) +#define DCDC_REG10_ANA_TRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG10_ANA_TRG_SP2_SHIFT)) & DCDC_REG10_ANA_TRG_SP2_MASK) +/*! @} */ + +/*! @name REG11 - DCDC Register 11 */ +/*! @{ */ + +#define DCDC_REG11_ANA_TRG_SP3_MASK (0xFFFFFFFFU) +#define DCDC_REG11_ANA_TRG_SP3_SHIFT (0U) +#define DCDC_REG11_ANA_TRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG11_ANA_TRG_SP3_SHIFT)) & DCDC_REG11_ANA_TRG_SP3_MASK) +/*! @} */ + +/*! @name REG12 - DCDC Register 12 */ +/*! @{ */ + +#define DCDC_REG12_DIG_TRG_SP0_MASK (0xFFFFFFFFU) +#define DCDC_REG12_DIG_TRG_SP0_SHIFT (0U) +#define DCDC_REG12_DIG_TRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG12_DIG_TRG_SP0_SHIFT)) & DCDC_REG12_DIG_TRG_SP0_MASK) +/*! @} */ + +/*! @name REG13 - DCDC Register 13 */ +/*! @{ */ + +#define DCDC_REG13_DIG_TRG_SP1_MASK (0xFFFFFFFFU) +#define DCDC_REG13_DIG_TRG_SP1_SHIFT (0U) +#define DCDC_REG13_DIG_TRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG13_DIG_TRG_SP1_SHIFT)) & DCDC_REG13_DIG_TRG_SP1_MASK) +/*! @} */ + +/*! @name REG14 - DCDC Register 14 */ +/*! @{ */ + +#define DCDC_REG14_DIG_TRG_SP2_MASK (0xFFFFFFFFU) +#define DCDC_REG14_DIG_TRG_SP2_SHIFT (0U) +#define DCDC_REG14_DIG_TRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG14_DIG_TRG_SP2_SHIFT)) & DCDC_REG14_DIG_TRG_SP2_MASK) +/*! @} */ + +/*! @name REG15 - DCDC Register 15 */ +/*! @{ */ + +#define DCDC_REG15_DIG_TRG_SP3_MASK (0xFFFFFFFFU) +#define DCDC_REG15_DIG_TRG_SP3_SHIFT (0U) +#define DCDC_REG15_DIG_TRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG15_DIG_TRG_SP3_SHIFT)) & DCDC_REG15_DIG_TRG_SP3_MASK) +/*! @} */ + +/*! @name REG16 - DCDC Register 16 */ +/*! @{ */ + +#define DCDC_REG16_ANA_STBY_TRG_SP0_MASK (0xFFFFFFFFU) +#define DCDC_REG16_ANA_STBY_TRG_SP0_SHIFT (0U) +#define DCDC_REG16_ANA_STBY_TRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG16_ANA_STBY_TRG_SP0_SHIFT)) & DCDC_REG16_ANA_STBY_TRG_SP0_MASK) +/*! @} */ + +/*! @name REG17 - DCDC Register 17 */ +/*! @{ */ + +#define DCDC_REG17_ANA_STBY_TRG_SP1_MASK (0xFFFFFFFFU) +#define DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT (0U) +#define DCDC_REG17_ANA_STBY_TRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT)) & DCDC_REG17_ANA_STBY_TRG_SP1_MASK) +/*! @} */ + +/*! @name REG18 - DCDC Register 18 */ +/*! @{ */ + +#define DCDC_REG18_ANA_STBY_TRG_SP2_MASK (0xFFFFFFFFU) +#define DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT (0U) +#define DCDC_REG18_ANA_STBY_TRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT)) & DCDC_REG18_ANA_STBY_TRG_SP2_MASK) +/*! @} */ + +/*! @name REG19 - DCDC Register 19 */ +/*! @{ */ + +#define DCDC_REG19_ANA_STBY_TRG_SP3_MASK (0xFFFFFFFFU) +#define DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT (0U) +#define DCDC_REG19_ANA_STBY_TRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT)) & DCDC_REG19_ANA_STBY_TRG_SP3_MASK) +/*! @} */ + +/*! @name REG20 - DCDC Register 20 */ +/*! @{ */ + +#define DCDC_REG20_DIG_STBY_TRG_SP0_MASK (0xFFFFFFFFU) +#define DCDC_REG20_DIG_STBY_TRG_SP0_SHIFT (0U) +#define DCDC_REG20_DIG_STBY_TRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG20_DIG_STBY_TRG_SP0_SHIFT)) & DCDC_REG20_DIG_STBY_TRG_SP0_MASK) +/*! @} */ + +/*! @name REG21 - DCDC Register 21 */ +/*! @{ */ + +#define DCDC_REG21_DIG_STBY_TRG_SP1_MASK (0xFFFFFFFFU) +#define DCDC_REG21_DIG_STBY_TRG_SP1_SHIFT (0U) +#define DCDC_REG21_DIG_STBY_TRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG21_DIG_STBY_TRG_SP1_SHIFT)) & DCDC_REG21_DIG_STBY_TRG_SP1_MASK) +/*! @} */ + +/*! @name REG22 - DCDC Register 22 */ +/*! @{ */ + +#define DCDC_REG22_DIG_STBY_TRG_SP2_MASK (0xFFFFFFFFU) +#define DCDC_REG22_DIG_STBY_TRG_SP2_SHIFT (0U) +#define DCDC_REG22_DIG_STBY_TRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG22_DIG_STBY_TRG_SP2_SHIFT)) & DCDC_REG22_DIG_STBY_TRG_SP2_MASK) +/*! @} */ + +/*! @name REG23 - DCDC Register 23 */ +/*! @{ */ + +#define DCDC_REG23_DIG_STBY_TRG_SP3_MASK (0xFFFFFFFFU) +#define DCDC_REG23_DIG_STBY_TRG_SP3_SHIFT (0U) +#define DCDC_REG23_DIG_STBY_TRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG23_DIG_STBY_TRG_SP3_SHIFT)) & DCDC_REG23_DIG_STBY_TRG_SP3_MASK) +/*! @} */ + +/*! @name REG24 - DCDC Register 24 */ +/*! @{ */ + +#define DCDC_REG24_OK_COUNT_MASK (0xFFFFFFFFU) +#define DCDC_REG24_OK_COUNT_SHIFT (0U) +#define DCDC_REG24_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG24_OK_COUNT_SHIFT)) & DCDC_REG24_OK_COUNT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DCDC_Register_Masks */ + + +/* DCDC - Peripheral instance base addresses */ +/** Peripheral DCDC base address */ +#define DCDC_BASE (0x40CA8000u) +/** Peripheral DCDC base pointer */ +#define DCDC ((DCDC_Type *)DCDC_BASE) +/** Array initializer of DCDC peripheral base addresses */ +#define DCDC_BASE_ADDRS { DCDC_BASE } +/** Array initializer of DCDC peripheral base pointers */ +#define DCDC_BASE_PTRS { DCDC } + +/*! + * @} + */ /* end of group DCDC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DCIC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCIC_Peripheral_Access_Layer DCIC Peripheral Access Layer + * @{ + */ + +/** DCIC - Register Layout Typedef */ +typedef struct { + __IO uint32_t DCICC; /**< DCIC Control Register, offset: 0x0 */ + __IO uint32_t DCICIC; /**< DCIC Interrupt Control Register, offset: 0x4 */ + __IO uint32_t DCICS; /**< DCIC Status Register, offset: 0x8 */ + uint8_t RESERVED_0[4]; + struct { /* offset: 0x10, array step: 0x10 */ + __IO uint32_t DCICRC; /**< DCIC ROI Config Register, array offset: 0x10, array step: 0x10 */ + __IO uint32_t DCICRS; /**< DCIC ROI Size Register, array offset: 0x14, array step: 0x10 */ + __IO uint32_t DCICRRS; /**< DCIC ROI Reference Signature Register, array offset: 0x18, array step: 0x10 */ + __I uint32_t DCICRCS; /**< DCIC ROI Calculated Signature Register, array offset: 0x1C, array step: 0x10 */ + } REGION[16]; +} DCIC_Type; + +/* ---------------------------------------------------------------------------- + -- DCIC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCIC_Register_Masks DCIC Register Masks + * @{ + */ + +/*! @name DCICC - DCIC Control Register */ +/*! @{ */ + +#define DCIC_DCICC_IC_EN_MASK (0x1U) +#define DCIC_DCICC_IC_EN_SHIFT (0U) +/*! IC_EN + * 0b0..Disabled + * 0b1..Enabled + */ +#define DCIC_DCICC_IC_EN(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_IC_EN_SHIFT)) & DCIC_DCICC_IC_EN_MASK) + +#define DCIC_DCICC_DE_POL_MASK (0x10U) +#define DCIC_DCICC_DE_POL_SHIFT (4U) +/*! DE_POL + * 0b0..Active High. + * 0b1..Active Low. + */ +#define DCIC_DCICC_DE_POL(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_DE_POL_SHIFT)) & DCIC_DCICC_DE_POL_MASK) + +#define DCIC_DCICC_HSYNC_POL_MASK (0x20U) +#define DCIC_DCICC_HSYNC_POL_SHIFT (5U) +/*! HSYNC_POL + * 0b0..Active High. + * 0b1..Active Low. + */ +#define DCIC_DCICC_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_HSYNC_POL_SHIFT)) & DCIC_DCICC_HSYNC_POL_MASK) + +#define DCIC_DCICC_VSYNC_POL_MASK (0x40U) +#define DCIC_DCICC_VSYNC_POL_SHIFT (6U) +/*! VSYNC_POL + * 0b0..Active High. + * 0b1..Active Low. + */ +#define DCIC_DCICC_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_VSYNC_POL_SHIFT)) & DCIC_DCICC_VSYNC_POL_MASK) + +#define DCIC_DCICC_CLK_POL_MASK (0x80U) +#define DCIC_DCICC_CLK_POL_SHIFT (7U) +/*! CLK_POL + * 0b0..Not inverted (default). + * 0b1..Inverted. + */ +#define DCIC_DCICC_CLK_POL(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_CLK_POL_SHIFT)) & DCIC_DCICC_CLK_POL_MASK) +/*! @} */ + +/*! @name DCICIC - DCIC Interrupt Control Register */ +/*! @{ */ + +#define DCIC_DCICIC_EI_MASK_MASK (0x1U) +#define DCIC_DCICIC_EI_MASK_SHIFT (0U) +/*! EI_MASK + * 0b0..Mask disabled - Interrupt assertion enabled + * 0b1..Mask enabled - Interrupt assertion disabled + */ +#define DCIC_DCICIC_EI_MASK(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICIC_EI_MASK_SHIFT)) & DCIC_DCICIC_EI_MASK_MASK) + +#define DCIC_DCICIC_FI_MASK_MASK (0x2U) +#define DCIC_DCICIC_FI_MASK_SHIFT (1U) +/*! FI_MASK + * 0b0..Mask disabled - Interrupt assertion enabled + * 0b1..Mask enabled - Interrupt assertion disabled + */ +#define DCIC_DCICIC_FI_MASK(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICIC_FI_MASK_SHIFT)) & DCIC_DCICIC_FI_MASK_MASK) + +#define DCIC_DCICIC_FREEZE_MASK_MASK (0x8U) +#define DCIC_DCICIC_FREEZE_MASK_SHIFT (3U) +/*! FREEZE_MASK + * 0b0..Masks change allowed + * 0b1..Masks are frozen + */ +#define DCIC_DCICIC_FREEZE_MASK(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICIC_FREEZE_MASK_SHIFT)) & DCIC_DCICIC_FREEZE_MASK_MASK) + +#define DCIC_DCICIC_EXT_SIG_EN_MASK (0x10000U) +#define DCIC_DCICIC_EXT_SIG_EN_SHIFT (16U) +/*! EXT_SIG_EN + * 0b0..Disabled + * 0b1..Enabled + */ +#define DCIC_DCICIC_EXT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICIC_EXT_SIG_EN_SHIFT)) & DCIC_DCICIC_EXT_SIG_EN_MASK) +/*! @} */ + +/*! @name DCICS - DCIC Status Register */ +/*! @{ */ + +#define DCIC_DCICS_ROI_MATCH_STAT_MASK (0xFFFFU) +#define DCIC_DCICS_ROI_MATCH_STAT_SHIFT (0U) +/*! ROI_MATCH_STAT + * 0b0000000000000000..ROI calculated CRC matches expected signature + * 0b0000000000000001..Mismatch at ROI calculated CRC + */ +#define DCIC_DCICS_ROI_MATCH_STAT(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICS_ROI_MATCH_STAT_SHIFT)) & DCIC_DCICS_ROI_MATCH_STAT_MASK) + +#define DCIC_DCICS_EI_STAT_MASK (0x10000U) +#define DCIC_DCICS_EI_STAT_SHIFT (16U) +/*! EI_STAT + * 0b0..No pending Interrupt + * 0b1..Pending Interrupt + */ +#define DCIC_DCICS_EI_STAT(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICS_EI_STAT_SHIFT)) & DCIC_DCICS_EI_STAT_MASK) + +#define DCIC_DCICS_FI_STAT_MASK (0x20000U) +#define DCIC_DCICS_FI_STAT_SHIFT (17U) +/*! FI_STAT + * 0b0..No pending Interrupt + * 0b1..Pending Interrupt + */ +#define DCIC_DCICS_FI_STAT(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICS_FI_STAT_SHIFT)) & DCIC_DCICS_FI_STAT_MASK) +/*! @} */ + +/*! @name DCICRC - DCIC ROI Config Register */ +/*! @{ */ + +#define DCIC_DCICRC_START_OFFSET_X_MASK (0x1FFFU) +#define DCIC_DCICRC_START_OFFSET_X_SHIFT (0U) +#define DCIC_DCICRC_START_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRC_START_OFFSET_X_SHIFT)) & DCIC_DCICRC_START_OFFSET_X_MASK) + +#define DCIC_DCICRC_START_OFFSET_Y_MASK (0xFFF0000U) +#define DCIC_DCICRC_START_OFFSET_Y_SHIFT (16U) +#define DCIC_DCICRC_START_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRC_START_OFFSET_Y_SHIFT)) & DCIC_DCICRC_START_OFFSET_Y_MASK) + +#define DCIC_DCICRC_ROI_FREEZE_MASK (0x40000000U) +#define DCIC_DCICRC_ROI_FREEZE_SHIFT (30U) +/*! ROI_FREEZE + * 0b0..ROI configuration can be changed + * 0b1..ROI configuration is frozen + */ +#define DCIC_DCICRC_ROI_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRC_ROI_FREEZE_SHIFT)) & DCIC_DCICRC_ROI_FREEZE_MASK) + +#define DCIC_DCICRC_ROI_EN_MASK (0x80000000U) +#define DCIC_DCICRC_ROI_EN_SHIFT (31U) +/*! ROI_EN + * 0b0..Disabled + * 0b1..Enabled + */ +#define DCIC_DCICRC_ROI_EN(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRC_ROI_EN_SHIFT)) & DCIC_DCICRC_ROI_EN_MASK) +/*! @} */ + +/* The count of DCIC_DCICRC */ +#define DCIC_DCICRC_COUNT (16U) + +/*! @name DCICRS - DCIC ROI Size Register */ +/*! @{ */ + +#define DCIC_DCICRS_END_OFFSET_X_MASK (0x1FFFU) +#define DCIC_DCICRS_END_OFFSET_X_SHIFT (0U) +#define DCIC_DCICRS_END_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRS_END_OFFSET_X_SHIFT)) & DCIC_DCICRS_END_OFFSET_X_MASK) + +#define DCIC_DCICRS_END_OFFSET_Y_MASK (0xFFF0000U) +#define DCIC_DCICRS_END_OFFSET_Y_SHIFT (16U) +#define DCIC_DCICRS_END_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRS_END_OFFSET_Y_SHIFT)) & DCIC_DCICRS_END_OFFSET_Y_MASK) +/*! @} */ + +/* The count of DCIC_DCICRS */ +#define DCIC_DCICRS_COUNT (16U) + +/*! @name DCICRRS - DCIC ROI Reference Signature Register */ +/*! @{ */ + +#define DCIC_DCICRRS_REFERENCE_SIGNATURE_MASK (0xFFFFFFFFU) +#define DCIC_DCICRRS_REFERENCE_SIGNATURE_SHIFT (0U) +#define DCIC_DCICRRS_REFERENCE_SIGNATURE(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRRS_REFERENCE_SIGNATURE_SHIFT)) & DCIC_DCICRRS_REFERENCE_SIGNATURE_MASK) +/*! @} */ + +/* The count of DCIC_DCICRRS */ +#define DCIC_DCICRRS_COUNT (16U) + +/*! @name DCICRCS - DCIC ROI Calculated Signature Register */ +/*! @{ */ + +#define DCIC_DCICRCS_CALCULATED_SIGNATURE_MASK (0xFFFFFFFFU) +#define DCIC_DCICRCS_CALCULATED_SIGNATURE_SHIFT (0U) +#define DCIC_DCICRCS_CALCULATED_SIGNATURE(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRCS_CALCULATED_SIGNATURE_SHIFT)) & DCIC_DCICRCS_CALCULATED_SIGNATURE_MASK) +/*! @} */ + +/* The count of DCIC_DCICRCS */ +#define DCIC_DCICRCS_COUNT (16U) + + +/*! + * @} + */ /* end of group DCIC_Register_Masks */ + + +/* DCIC - Peripheral instance base addresses */ +/** Peripheral DCIC1 base address */ +#define DCIC1_BASE (0x40819000u) +/** Peripheral DCIC1 base pointer */ +#define DCIC1 ((DCIC_Type *)DCIC1_BASE) +/** Peripheral DCIC2 base address */ +#define DCIC2_BASE (0x4081A000u) +/** Peripheral DCIC2 base pointer */ +#define DCIC2 ((DCIC_Type *)DCIC2_BASE) +/** Array initializer of DCIC peripheral base addresses */ +#define DCIC_BASE_ADDRS { 0u, DCIC1_BASE, DCIC2_BASE } +/** Array initializer of DCIC peripheral base pointers */ +#define DCIC_BASE_PTRS { (DCIC_Type *)0u, DCIC1, DCIC2 } + +/*! + * @} + */ /* end of group DCIC_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMA Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer + * @{ + */ + +/** DMA - Register Layout Typedef */ +typedef struct { + __IO uint32_t CR; /**< Control, offset: 0x0 */ + __I uint32_t ES; /**< Error Status, offset: 0x4 */ + uint8_t RESERVED_0[4]; + __IO uint32_t ERQ; /**< Enable Request, offset: 0xC */ + uint8_t RESERVED_1[4]; + __IO uint32_t EEI; /**< Enable Error Interrupt, offset: 0x14 */ + __O uint8_t CEEI; /**< Clear Enable Error Interrupt, offset: 0x18 */ + __O uint8_t SEEI; /**< Set Enable Error Interrupt, offset: 0x19 */ + __O uint8_t CERQ; /**< Clear Enable Request, offset: 0x1A */ + __O uint8_t SERQ; /**< Set Enable Request, offset: 0x1B */ + __O uint8_t CDNE; /**< Clear DONE Status Bit, offset: 0x1C */ + __O uint8_t SSRT; /**< Set START Bit, offset: 0x1D */ + __O uint8_t CERR; /**< Clear Error, offset: 0x1E */ + __O uint8_t CINT; /**< Clear Interrupt Request, offset: 0x1F */ + uint8_t RESERVED_2[4]; + __IO uint32_t INT; /**< Interrupt Request, offset: 0x24 */ + uint8_t RESERVED_3[4]; + __IO uint32_t ERR; /**< Error, offset: 0x2C */ + uint8_t RESERVED_4[4]; + __I uint32_t HRS; /**< Hardware Request Status, offset: 0x34 */ + uint8_t RESERVED_5[12]; + __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop, offset: 0x44 */ + uint8_t RESERVED_6[184]; + __IO uint8_t DCHPRI3; /**< Channel Priority, offset: 0x100 */ + __IO uint8_t DCHPRI2; /**< Channel Priority, offset: 0x101 */ + __IO uint8_t DCHPRI1; /**< Channel Priority, offset: 0x102 */ + __IO uint8_t DCHPRI0; /**< Channel Priority, offset: 0x103 */ + __IO uint8_t DCHPRI7; /**< Channel Priority, offset: 0x104 */ + __IO uint8_t DCHPRI6; /**< Channel Priority, offset: 0x105 */ + __IO uint8_t DCHPRI5; /**< Channel Priority, offset: 0x106 */ + __IO uint8_t DCHPRI4; /**< Channel Priority, offset: 0x107 */ + __IO uint8_t DCHPRI11; /**< Channel Priority, offset: 0x108 */ + __IO uint8_t DCHPRI10; /**< Channel Priority, offset: 0x109 */ + __IO uint8_t DCHPRI9; /**< Channel Priority, offset: 0x10A */ + __IO uint8_t DCHPRI8; /**< Channel Priority, offset: 0x10B */ + __IO uint8_t DCHPRI15; /**< Channel Priority, offset: 0x10C */ + __IO uint8_t DCHPRI14; /**< Channel Priority, offset: 0x10D */ + __IO uint8_t DCHPRI13; /**< Channel Priority, offset: 0x10E */ + __IO uint8_t DCHPRI12; /**< Channel Priority, offset: 0x10F */ + __IO uint8_t DCHPRI19; /**< Channel Priority, offset: 0x110 */ + __IO uint8_t DCHPRI18; /**< Channel Priority, offset: 0x111 */ + __IO uint8_t DCHPRI17; /**< Channel Priority, offset: 0x112 */ + __IO uint8_t DCHPRI16; /**< Channel Priority, offset: 0x113 */ + __IO uint8_t DCHPRI23; /**< Channel Priority, offset: 0x114 */ + __IO uint8_t DCHPRI22; /**< Channel Priority, offset: 0x115 */ + __IO uint8_t DCHPRI21; /**< Channel Priority, offset: 0x116 */ + __IO uint8_t DCHPRI20; /**< Channel Priority, offset: 0x117 */ + __IO uint8_t DCHPRI27; /**< Channel Priority, offset: 0x118 */ + __IO uint8_t DCHPRI26; /**< Channel Priority, offset: 0x119 */ + __IO uint8_t DCHPRI25; /**< Channel Priority, offset: 0x11A */ + __IO uint8_t DCHPRI24; /**< Channel Priority, offset: 0x11B */ + __IO uint8_t DCHPRI31; /**< Channel Priority, offset: 0x11C */ + __IO uint8_t DCHPRI30; /**< Channel Priority, offset: 0x11D */ + __IO uint8_t DCHPRI29; /**< Channel Priority, offset: 0x11E */ + __IO uint8_t DCHPRI28; /**< Channel Priority, offset: 0x11F */ + uint8_t RESERVED_7[3808]; + struct { /* offset: 0x1000, array step: 0x20 */ + __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ + __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ + __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */ + union { /* offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */ + __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */ + }; + __IO int32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */ + __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */ + __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */ + union { /* offset: 0x1016, array step: 0x20 */ + __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */ + __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */ + }; + __IO int32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */ + __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */ + union { /* offset: 0x101E, array step: 0x20 */ + __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ + __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ + }; + } TCD[32]; +} DMA_Type; + +/* ---------------------------------------------------------------------------- + -- DMA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMA_Register_Masks DMA Register Masks + * @{ + */ + +/*! @name CR - Control */ +/*! @{ */ + +#define DMA_CR_EDBG_MASK (0x2U) +#define DMA_CR_EDBG_SHIFT (1U) +/*! EDBG - Enable Debug + * 0b0..When the chip is in Debug mode, the eDMA continues to operate. + * 0b1..When the chip is in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. + */ +#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) + +#define DMA_CR_ERCA_MASK (0x4U) +#define DMA_CR_ERCA_SHIFT (2U) +/*! ERCA - Enable Round Robin Channel Arbitration + * 0b0..Fixed priority arbitration within each group + * 0b1..Round robin arbitration within each group + */ +#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) + +#define DMA_CR_ERGA_MASK (0x8U) +#define DMA_CR_ERGA_SHIFT (3U) +/*! ERGA - Enable Round Robin Group Arbitration + * 0b0..Fixed priority arbitration + * 0b1..Round robin arbitration + */ +#define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK) + +#define DMA_CR_HOE_MASK (0x10U) +#define DMA_CR_HOE_SHIFT (4U) +/*! HOE - Halt On Error + * 0b0..Normal operation + * 0b1..Error causes HALT field to be automatically set to 1 + */ +#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK) + +#define DMA_CR_HALT_MASK (0x20U) +#define DMA_CR_HALT_SHIFT (5U) +/*! HALT - Halt eDMA Operations + * 0b0..Normal operation + * 0b1..eDMA operations halted + */ +#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK) + +#define DMA_CR_CLM_MASK (0x40U) +#define DMA_CR_CLM_SHIFT (6U) +/*! CLM - Continuous Link Mode + * 0b0..Continuous link mode is off + * 0b1..Continuous link mode is on + */ +#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK) + +#define DMA_CR_EMLM_MASK (0x80U) +#define DMA_CR_EMLM_SHIFT (7U) +/*! EMLM - Enable Minor Loop Mapping + * 0b0..Disabled + * 0b1..Enabled + */ +#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK) + +#define DMA_CR_GRP0PRI_MASK (0x100U) +#define DMA_CR_GRP0PRI_SHIFT (8U) +/*! GRP0PRI - Channel Group 0 Priority + */ +#define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK) + +#define DMA_CR_GRP1PRI_MASK (0x400U) +#define DMA_CR_GRP1PRI_SHIFT (10U) +/*! GRP1PRI - Channel Group 1 Priority + */ +#define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK) + +#define DMA_CR_ECX_MASK (0x10000U) +#define DMA_CR_ECX_SHIFT (16U) +/*! ECX - Error Cancel Transfer + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer + */ +#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK) + +#define DMA_CR_CX_MASK (0x20000U) +#define DMA_CR_CX_SHIFT (17U) +/*! CX - Cancel Transfer + * 0b0..Normal operation + * 0b1..Cancel the remaining data transfer + */ +#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK) + +#define DMA_CR_VERSION_MASK (0x7F000000U) +#define DMA_CR_VERSION_SHIFT (24U) +/*! VERSION - eDMA version number + */ +#define DMA_CR_VERSION(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_VERSION_SHIFT)) & DMA_CR_VERSION_MASK) + +#define DMA_CR_ACTIVE_MASK (0x80000000U) +#define DMA_CR_ACTIVE_SHIFT (31U) +/*! ACTIVE - eDMA Active Status + * 0b0..eDMA is idle + * 0b1..eDMA is executing a channel + */ +#define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK) +/*! @} */ + +/*! @name ES - Error Status */ +/*! @{ */ + +#define DMA_ES_DBE_MASK (0x1U) +#define DMA_ES_DBE_SHIFT (0U) +/*! DBE - Destination Bus Error + * 0b0..No destination bus error. + * 0b1..The most-recently recorded error was a bus error on a destination write. + */ +#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) + +#define DMA_ES_SBE_MASK (0x2U) +#define DMA_ES_SBE_SHIFT (1U) +/*! SBE - Source Bus Error + * 0b0..No source bus error. + * 0b1..The most-recently recorded error was a bus error on a source read. + */ +#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK) + +#define DMA_ES_SGE_MASK (0x4U) +#define DMA_ES_SGE_SHIFT (2U) +/*! SGE - Scatter/Gather Configuration Error + * 0b0..No scatter/gather configuration error. + * 0b1..The most-recently recorded error was a configuration error detected in the TCDn_DLASTSGA field. + */ +#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK) + +#define DMA_ES_NCE_MASK (0x8U) +#define DMA_ES_NCE_SHIFT (3U) +/*! NCE - NBYTES/CITER Configuration Error + * 0b0..No NBYTES/CITER configuration error. + * 0b1..The most-recently recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER + * fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] = 0, or + * TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]. + */ +#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) + +#define DMA_ES_DOE_MASK (0x10U) +#define DMA_ES_DOE_SHIFT (4U) +/*! DOE - Destination Offset Error + * 0b0..No destination offset configuration error. + * 0b1..The most-recently recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. + */ +#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK) + +#define DMA_ES_DAE_MASK (0x20U) +#define DMA_ES_DAE_SHIFT (5U) +/*! DAE - Destination Address Error + * 0b0..No destination address configuration error. + * 0b1..The most-recently recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR + * is inconsistent with TCDn_ATTR[DSIZE]. + */ +#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK) + +#define DMA_ES_SOE_MASK (0x40U) +#define DMA_ES_SOE_SHIFT (6U) +/*! SOE - Source Offset Error + * 0b0..No source offset configuration error. + * 0b1..The most-recently recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. + */ +#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK) + +#define DMA_ES_SAE_MASK (0x80U) +#define DMA_ES_SAE_SHIFT (7U) +/*! SAE - Source Address Error + * 0b0..No source address configuration error. + * 0b1..The most-recently recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR + * is inconsistent with TCDn_ATTR[SSIZE]. + */ +#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK) + +#define DMA_ES_ERRCHN_MASK (0x1F00U) +#define DMA_ES_ERRCHN_SHIFT (8U) +/*! ERRCHN - Error Channel Number or Canceled Channel Number + */ +#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK) + +#define DMA_ES_CPE_MASK (0x4000U) +#define DMA_ES_CPE_SHIFT (14U) +/*! CPE - Channel Priority Error + * 0b0..No channel priority error. + * 0b1..The most-recently recorded error was a configuration error in the channel priorities within a group. + * Channel priorities within a group are not unique. + */ +#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) + +#define DMA_ES_GPE_MASK (0x8000U) +#define DMA_ES_GPE_SHIFT (15U) +/*! GPE - Group Priority Error + * 0b0..No group priority error. + * 0b1..The most-recently recorded error was a configuration error among the group priorities. All group priorities are not unique. + */ +#define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK) + +#define DMA_ES_ECX_MASK (0x10000U) +#define DMA_ES_ECX_SHIFT (16U) +/*! ECX - Transfer Canceled + * 0b0..No canceled transfers + * 0b1..The most-recently recorded entry was a canceled transfer initiated by the error cancel transfer field + */ +#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK) + +#define DMA_ES_VLD_MASK (0x80000000U) +#define DMA_ES_VLD_SHIFT (31U) +/*! VLD - Logical OR of all ERR status fields + * 0b0..No ERR fields are 1 + * 0b1..At least one ERR field has a value of 1, indicating a valid error exists that has not been cleared + */ +#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) +/*! @} */ + +/*! @name ERQ - Enable Request */ +/*! @{ */ + +#define DMA_ERQ_ERQ0_MASK (0x1U) +#define DMA_ERQ_ERQ0_SHIFT (0U) +/*! ERQ0 - Enable DMA Request 0 + * 0b0..The DMA request signal for channel 0 is disabled + * 0b1..The DMA request signal for channel 0 is enabled + */ +#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) + +#define DMA_ERQ_ERQ1_MASK (0x2U) +#define DMA_ERQ_ERQ1_SHIFT (1U) +/*! ERQ1 - Enable DMA Request 1 + * 0b0..The DMA request signal for channel 1 is disabled + * 0b1..The DMA request signal for channel 1 is enabled + */ +#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK) + +#define DMA_ERQ_ERQ2_MASK (0x4U) +#define DMA_ERQ_ERQ2_SHIFT (2U) +/*! ERQ2 - Enable DMA Request 2 + * 0b0..The DMA request signal for channel 2 is disabled + * 0b1..The DMA request signal for channel 2 is enabled + */ +#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK) + +#define DMA_ERQ_ERQ3_MASK (0x8U) +#define DMA_ERQ_ERQ3_SHIFT (3U) +/*! ERQ3 - Enable DMA Request 3 + * 0b0..The DMA request signal for channel 3 is disabled + * 0b1..The DMA request signal for channel 3 is enabled + */ +#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK) + +#define DMA_ERQ_ERQ4_MASK (0x10U) +#define DMA_ERQ_ERQ4_SHIFT (4U) +/*! ERQ4 - Enable DMA Request 4 + * 0b0..The DMA request signal for channel 4 is disabled + * 0b1..The DMA request signal for channel 4 is enabled + */ +#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK) + +#define DMA_ERQ_ERQ5_MASK (0x20U) +#define DMA_ERQ_ERQ5_SHIFT (5U) +/*! ERQ5 - Enable DMA Request 5 + * 0b0..The DMA request signal for channel 5 is disabled + * 0b1..The DMA request signal for channel 5 is enabled + */ +#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK) + +#define DMA_ERQ_ERQ6_MASK (0x40U) +#define DMA_ERQ_ERQ6_SHIFT (6U) +/*! ERQ6 - Enable DMA Request 6 + * 0b0..The DMA request signal for channel 6 is disabled + * 0b1..The DMA request signal for channel 6 is enabled + */ +#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK) + +#define DMA_ERQ_ERQ7_MASK (0x80U) +#define DMA_ERQ_ERQ7_SHIFT (7U) +/*! ERQ7 - Enable DMA Request 7 + * 0b0..The DMA request signal for channel 7 is disabled + * 0b1..The DMA request signal for channel 7 is enabled + */ +#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK) + +#define DMA_ERQ_ERQ8_MASK (0x100U) +#define DMA_ERQ_ERQ8_SHIFT (8U) +/*! ERQ8 - Enable DMA Request 8 + * 0b0..The DMA request signal for channel 8 is disabled + * 0b1..The DMA request signal for channel 8 is enabled + */ +#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK) + +#define DMA_ERQ_ERQ9_MASK (0x200U) +#define DMA_ERQ_ERQ9_SHIFT (9U) +/*! ERQ9 - Enable DMA Request 9 + * 0b0..The DMA request signal for channel 9 is disabled + * 0b1..The DMA request signal for channel 9 is enabled + */ +#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK) + +#define DMA_ERQ_ERQ10_MASK (0x400U) +#define DMA_ERQ_ERQ10_SHIFT (10U) +/*! ERQ10 - Enable DMA Request 10 + * 0b0..The DMA request signal for channel 10 is disabled + * 0b1..The DMA request signal for channel 10 is enabled + */ +#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK) + +#define DMA_ERQ_ERQ11_MASK (0x800U) +#define DMA_ERQ_ERQ11_SHIFT (11U) +/*! ERQ11 - Enable DMA Request 11 + * 0b0..The DMA request signal for channel 11 is disabled + * 0b1..The DMA request signal for channel 11 is enabled + */ +#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK) + +#define DMA_ERQ_ERQ12_MASK (0x1000U) +#define DMA_ERQ_ERQ12_SHIFT (12U) +/*! ERQ12 - Enable DMA Request 12 + * 0b0..The DMA request signal for channel 12 is disabled + * 0b1..The DMA request signal for channel 12 is enabled + */ +#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK) + +#define DMA_ERQ_ERQ13_MASK (0x2000U) +#define DMA_ERQ_ERQ13_SHIFT (13U) +/*! ERQ13 - Enable DMA Request 13 + * 0b0..The DMA request signal for channel 13 is disabled + * 0b1..The DMA request signal for channel 13 is enabled + */ +#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK) + +#define DMA_ERQ_ERQ14_MASK (0x4000U) +#define DMA_ERQ_ERQ14_SHIFT (14U) +/*! ERQ14 - Enable DMA Request 14 + * 0b0..The DMA request signal for channel 14 is disabled + * 0b1..The DMA request signal for channel 14 is enabled + */ +#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK) + +#define DMA_ERQ_ERQ15_MASK (0x8000U) +#define DMA_ERQ_ERQ15_SHIFT (15U) +/*! ERQ15 - Enable DMA Request 15 + * 0b0..The DMA request signal for channel 15 is disabled + * 0b1..The DMA request signal for channel 15 is enabled + */ +#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK) + +#define DMA_ERQ_ERQ16_MASK (0x10000U) +#define DMA_ERQ_ERQ16_SHIFT (16U) +/*! ERQ16 - Enable DMA Request 16 + * 0b0..The DMA request signal for channel 16 is disabled + * 0b1..The DMA request signal for channel 16 is enabled + */ +#define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK) + +#define DMA_ERQ_ERQ17_MASK (0x20000U) +#define DMA_ERQ_ERQ17_SHIFT (17U) +/*! ERQ17 - Enable DMA Request 17 + * 0b0..The DMA request signal for channel 17 is disabled + * 0b1..The DMA request signal for channel 17 is enabled + */ +#define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK) + +#define DMA_ERQ_ERQ18_MASK (0x40000U) +#define DMA_ERQ_ERQ18_SHIFT (18U) +/*! ERQ18 - Enable DMA Request 18 + * 0b0..The DMA request signal for channel 18 is disabled + * 0b1..The DMA request signal for channel 18 is enabled + */ +#define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK) + +#define DMA_ERQ_ERQ19_MASK (0x80000U) +#define DMA_ERQ_ERQ19_SHIFT (19U) +/*! ERQ19 - Enable DMA Request 19 + * 0b0..The DMA request signal for channel 19 is disabled + * 0b1..The DMA request signal for channel 19 is enabled + */ +#define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK) + +#define DMA_ERQ_ERQ20_MASK (0x100000U) +#define DMA_ERQ_ERQ20_SHIFT (20U) +/*! ERQ20 - Enable DMA Request 20 + * 0b0..The DMA request signal for channel 20 is disabled + * 0b1..The DMA request signal for channel 20 is enabled + */ +#define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK) + +#define DMA_ERQ_ERQ21_MASK (0x200000U) +#define DMA_ERQ_ERQ21_SHIFT (21U) +/*! ERQ21 - Enable DMA Request 21 + * 0b0..The DMA request signal for channel 21 is disabled + * 0b1..The DMA request signal for channel 21 is enabled + */ +#define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK) + +#define DMA_ERQ_ERQ22_MASK (0x400000U) +#define DMA_ERQ_ERQ22_SHIFT (22U) +/*! ERQ22 - Enable DMA Request 22 + * 0b0..The DMA request signal for channel 22 is disabled + * 0b1..The DMA request signal for channel 22 is enabled + */ +#define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK) + +#define DMA_ERQ_ERQ23_MASK (0x800000U) +#define DMA_ERQ_ERQ23_SHIFT (23U) +/*! ERQ23 - Enable DMA Request 23 + * 0b0..The DMA request signal for channel 23 is disabled + * 0b1..The DMA request signal for channel 23 is enabled + */ +#define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK) + +#define DMA_ERQ_ERQ24_MASK (0x1000000U) +#define DMA_ERQ_ERQ24_SHIFT (24U) +/*! ERQ24 - Enable DMA Request 24 + * 0b0..The DMA request signal for channel 24 is disabled + * 0b1..The DMA request signal for channel 24 is enabled + */ +#define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK) + +#define DMA_ERQ_ERQ25_MASK (0x2000000U) +#define DMA_ERQ_ERQ25_SHIFT (25U) +/*! ERQ25 - Enable DMA Request 25 + * 0b0..The DMA request signal for channel 25 is disabled + * 0b1..The DMA request signal for channel 25 is enabled + */ +#define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK) + +#define DMA_ERQ_ERQ26_MASK (0x4000000U) +#define DMA_ERQ_ERQ26_SHIFT (26U) +/*! ERQ26 - Enable DMA Request 26 + * 0b0..The DMA request signal for channel 26 is disabled + * 0b1..The DMA request signal for channel 26 is enabled + */ +#define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK) + +#define DMA_ERQ_ERQ27_MASK (0x8000000U) +#define DMA_ERQ_ERQ27_SHIFT (27U) +/*! ERQ27 - Enable DMA Request 27 + * 0b0..The DMA request signal for channel 27 is disabled + * 0b1..The DMA request signal for channel 27 is enabled + */ +#define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK) + +#define DMA_ERQ_ERQ28_MASK (0x10000000U) +#define DMA_ERQ_ERQ28_SHIFT (28U) +/*! ERQ28 - Enable DMA Request 28 + * 0b0..The DMA request signal for channel 28 is disabled + * 0b1..The DMA request signal for channel 28 is enabled + */ +#define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK) + +#define DMA_ERQ_ERQ29_MASK (0x20000000U) +#define DMA_ERQ_ERQ29_SHIFT (29U) +/*! ERQ29 - Enable DMA Request 29 + * 0b0..The DMA request signal for channel 29 is disabled + * 0b1..The DMA request signal for channel 29 is enabled + */ +#define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK) + +#define DMA_ERQ_ERQ30_MASK (0x40000000U) +#define DMA_ERQ_ERQ30_SHIFT (30U) +/*! ERQ30 - Enable DMA Request 30 + * 0b0..The DMA request signal for channel 30 is disabled + * 0b1..The DMA request signal for channel 30 is enabled + */ +#define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK) + +#define DMA_ERQ_ERQ31_MASK (0x80000000U) +#define DMA_ERQ_ERQ31_SHIFT (31U) +/*! ERQ31 - Enable DMA Request 31 + * 0b0..The DMA request signal for channel 31 is disabled + * 0b1..The DMA request signal for channel 31 is enabled + */ +#define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK) +/*! @} */ + +/*! @name EEI - Enable Error Interrupt */ +/*! @{ */ + +#define DMA_EEI_EEI0_MASK (0x1U) +#define DMA_EEI_EEI0_SHIFT (0U) +/*! EEI0 - Enable Error Interrupt 0 + * 0b0..An error on channel 0 does not generate an error interrupt + * 0b1..An error on channel 0 generates an error interrupt request + */ +#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) + +#define DMA_EEI_EEI1_MASK (0x2U) +#define DMA_EEI_EEI1_SHIFT (1U) +/*! EEI1 - Enable Error Interrupt 1 + * 0b0..An error on channel 1 does not generate an error interrupt + * 0b1..An error on channel 1 generates an error interrupt request + */ +#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK) + +#define DMA_EEI_EEI2_MASK (0x4U) +#define DMA_EEI_EEI2_SHIFT (2U) +/*! EEI2 - Enable Error Interrupt 2 + * 0b0..An error on channel 2 does not generate an error interrupt + * 0b1..An error on channel 2 generates an error interrupt request + */ +#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK) + +#define DMA_EEI_EEI3_MASK (0x8U) +#define DMA_EEI_EEI3_SHIFT (3U) +/*! EEI3 - Enable Error Interrupt 3 + * 0b0..An error on channel 3 does not generate an error interrupt + * 0b1..An error on channel 3 generates an error interrupt request + */ +#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK) + +#define DMA_EEI_EEI4_MASK (0x10U) +#define DMA_EEI_EEI4_SHIFT (4U) +/*! EEI4 - Enable Error Interrupt 4 + * 0b0..An error on channel 4 does not generate an error interrupt + * 0b1..An error on channel 4 generates an error interrupt request + */ +#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK) + +#define DMA_EEI_EEI5_MASK (0x20U) +#define DMA_EEI_EEI5_SHIFT (5U) +/*! EEI5 - Enable Error Interrupt 5 + * 0b0..An error on channel 5 does not generate an error interrupt + * 0b1..An error on channel 5 generates an error interrupt request + */ +#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK) + +#define DMA_EEI_EEI6_MASK (0x40U) +#define DMA_EEI_EEI6_SHIFT (6U) +/*! EEI6 - Enable Error Interrupt 6 + * 0b0..An error on channel 6 does not generate an error interrupt + * 0b1..An error on channel 6 generates an error interrupt request + */ +#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK) + +#define DMA_EEI_EEI7_MASK (0x80U) +#define DMA_EEI_EEI7_SHIFT (7U) +/*! EEI7 - Enable Error Interrupt 7 + * 0b0..An error on channel 7 does not generate an error interrupt + * 0b1..An error on channel 7 generates an error interrupt request + */ +#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK) + +#define DMA_EEI_EEI8_MASK (0x100U) +#define DMA_EEI_EEI8_SHIFT (8U) +/*! EEI8 - Enable Error Interrupt 8 + * 0b0..An error on channel 8 does not generate an error interrupt + * 0b1..An error on channel 8 generates an error interrupt request + */ +#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK) + +#define DMA_EEI_EEI9_MASK (0x200U) +#define DMA_EEI_EEI9_SHIFT (9U) +/*! EEI9 - Enable Error Interrupt 9 + * 0b0..An error on channel 9 does not generate an error interrupt + * 0b1..An error on channel 9 generates an error interrupt request + */ +#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK) + +#define DMA_EEI_EEI10_MASK (0x400U) +#define DMA_EEI_EEI10_SHIFT (10U) +/*! EEI10 - Enable Error Interrupt 10 + * 0b0..An error on channel 10 does not generate an error interrupt + * 0b1..An error on channel 10 generates an error interrupt request + */ +#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK) + +#define DMA_EEI_EEI11_MASK (0x800U) +#define DMA_EEI_EEI11_SHIFT (11U) +/*! EEI11 - Enable Error Interrupt 11 + * 0b0..An error on channel 11 does not generate an error interrupt + * 0b1..An error on channel 11 generates an error interrupt request + */ +#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK) + +#define DMA_EEI_EEI12_MASK (0x1000U) +#define DMA_EEI_EEI12_SHIFT (12U) +/*! EEI12 - Enable Error Interrupt 12 + * 0b0..An error on channel 12 does not generate an error interrupt + * 0b1..An error on channel 12 generates an error interrupt request + */ +#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK) + +#define DMA_EEI_EEI13_MASK (0x2000U) +#define DMA_EEI_EEI13_SHIFT (13U) +/*! EEI13 - Enable Error Interrupt 13 + * 0b0..An error on channel 13 does not generate an error interrupt + * 0b1..An error on channel 13 generates an error interrupt request + */ +#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK) + +#define DMA_EEI_EEI14_MASK (0x4000U) +#define DMA_EEI_EEI14_SHIFT (14U) +/*! EEI14 - Enable Error Interrupt 14 + * 0b0..An error on channel 14 does not generate an error interrupt + * 0b1..An error on channel 14 generates an error interrupt request + */ +#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK) + +#define DMA_EEI_EEI15_MASK (0x8000U) +#define DMA_EEI_EEI15_SHIFT (15U) +/*! EEI15 - Enable Error Interrupt 15 + * 0b0..An error on channel 15 does not generate an error interrupt + * 0b1..An error on channel 15 generates an error interrupt request + */ +#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK) + +#define DMA_EEI_EEI16_MASK (0x10000U) +#define DMA_EEI_EEI16_SHIFT (16U) +/*! EEI16 - Enable Error Interrupt 16 + * 0b0..An error on channel 16 does not generate an error interrupt + * 0b1..An error on channel 16 generates an error interrupt request + */ +#define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK) + +#define DMA_EEI_EEI17_MASK (0x20000U) +#define DMA_EEI_EEI17_SHIFT (17U) +/*! EEI17 - Enable Error Interrupt 17 + * 0b0..An error on channel 17 does not generate an error interrupt + * 0b1..An error on channel 17 generates an error interrupt request + */ +#define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK) + +#define DMA_EEI_EEI18_MASK (0x40000U) +#define DMA_EEI_EEI18_SHIFT (18U) +/*! EEI18 - Enable Error Interrupt 18 + * 0b0..An error on channel 18 does not generate an error interrupt + * 0b1..An error on channel 18 generates an error interrupt request + */ +#define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK) + +#define DMA_EEI_EEI19_MASK (0x80000U) +#define DMA_EEI_EEI19_SHIFT (19U) +/*! EEI19 - Enable Error Interrupt 19 + * 0b0..An error on channel 19 does not generate an error interrupt + * 0b1..An error on channel 19 generates an error interrupt request + */ +#define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK) + +#define DMA_EEI_EEI20_MASK (0x100000U) +#define DMA_EEI_EEI20_SHIFT (20U) +/*! EEI20 - Enable Error Interrupt 20 + * 0b0..An error on channel 20 does not generate an error interrupt + * 0b1..An error on channel 20 generates an error interrupt request + */ +#define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK) + +#define DMA_EEI_EEI21_MASK (0x200000U) +#define DMA_EEI_EEI21_SHIFT (21U) +/*! EEI21 - Enable Error Interrupt 21 + * 0b0..An error on channel 21 does not generate an error interrupt + * 0b1..An error on channel 21 generates an error interrupt request + */ +#define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK) + +#define DMA_EEI_EEI22_MASK (0x400000U) +#define DMA_EEI_EEI22_SHIFT (22U) +/*! EEI22 - Enable Error Interrupt 22 + * 0b0..An error on channel 22 does not generate an error interrupt + * 0b1..An error on channel 22 generates an error interrupt request + */ +#define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK) + +#define DMA_EEI_EEI23_MASK (0x800000U) +#define DMA_EEI_EEI23_SHIFT (23U) +/*! EEI23 - Enable Error Interrupt 23 + * 0b0..An error on channel 23 does not generate an error interrupt + * 0b1..An error on channel 23 generates an error interrupt request + */ +#define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK) + +#define DMA_EEI_EEI24_MASK (0x1000000U) +#define DMA_EEI_EEI24_SHIFT (24U) +/*! EEI24 - Enable Error Interrupt 24 + * 0b0..An error on channel 24 does not generate an error interrupt + * 0b1..An error on channel 24 generates an error interrupt request + */ +#define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK) + +#define DMA_EEI_EEI25_MASK (0x2000000U) +#define DMA_EEI_EEI25_SHIFT (25U) +/*! EEI25 - Enable Error Interrupt 25 + * 0b0..An error on channel 25 does not generate an error interrupt + * 0b1..An error on channel 25 generates an error interrupt request + */ +#define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK) + +#define DMA_EEI_EEI26_MASK (0x4000000U) +#define DMA_EEI_EEI26_SHIFT (26U) +/*! EEI26 - Enable Error Interrupt 26 + * 0b0..An error on channel 26 does not generate an error interrupt + * 0b1..An error on channel 26 generates an error interrupt request + */ +#define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK) + +#define DMA_EEI_EEI27_MASK (0x8000000U) +#define DMA_EEI_EEI27_SHIFT (27U) +/*! EEI27 - Enable Error Interrupt 27 + * 0b0..An error on channel 27 does not generate an error interrupt + * 0b1..An error on channel 27 generates an error interrupt request + */ +#define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK) + +#define DMA_EEI_EEI28_MASK (0x10000000U) +#define DMA_EEI_EEI28_SHIFT (28U) +/*! EEI28 - Enable Error Interrupt 28 + * 0b0..An error on channel 28 does not generate an error interrupt + * 0b1..An error on channel 28 generates an error interrupt request + */ +#define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK) + +#define DMA_EEI_EEI29_MASK (0x20000000U) +#define DMA_EEI_EEI29_SHIFT (29U) +/*! EEI29 - Enable Error Interrupt 29 + * 0b0..An error on channel 29 does not generate an error interrupt + * 0b1..An error on channel 29 generates an error interrupt request + */ +#define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK) + +#define DMA_EEI_EEI30_MASK (0x40000000U) +#define DMA_EEI_EEI30_SHIFT (30U) +/*! EEI30 - Enable Error Interrupt 30 + * 0b0..An error on channel 30 does not generate an error interrupt + * 0b1..An error on channel 30 generates an error interrupt request + */ +#define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK) + +#define DMA_EEI_EEI31_MASK (0x80000000U) +#define DMA_EEI_EEI31_SHIFT (31U) +/*! EEI31 - Enable Error Interrupt 31 + * 0b0..An error on channel 31 does not generate an error interrupt + * 0b1..An error on channel 31 generates an error interrupt request + */ +#define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK) +/*! @} */ + +/*! @name CEEI - Clear Enable Error Interrupt */ +/*! @{ */ + +#define DMA_CEEI_CEEI_MASK (0x1FU) +#define DMA_CEEI_CEEI_SHIFT (0U) +/*! CEEI - Clear Enable Error Interrupt + */ +#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) + +#define DMA_CEEI_CAEE_MASK (0x40U) +#define DMA_CEEI_CAEE_SHIFT (6U) +/*! CAEE - Clear All Enable Error Interrupts + * 0b0..Write 0 only to the EEI field specified in the CEEI field + * 0b1..Write 0 to all fields in EEI + */ +#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) + +#define DMA_CEEI_NOP_MASK (0x80U) +#define DMA_CEEI_NOP_SHIFT (7U) +/*! NOP - No Op Enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other fields in this register + */ +#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) +/*! @} */ + +/*! @name SEEI - Set Enable Error Interrupt */ +/*! @{ */ + +#define DMA_SEEI_SEEI_MASK (0x1FU) +#define DMA_SEEI_SEEI_SHIFT (0U) +/*! SEEI - Set Enable Error Interrupt + */ +#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) + +#define DMA_SEEI_SAEE_MASK (0x40U) +#define DMA_SEEI_SAEE_SHIFT (6U) +/*! SAEE - Set All Enable Error Interrupts + * 0b0..Write 1 only to the EEI field specified in the SEEI field + * 0b1..Writes 1 to all fields in EEI + */ +#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) + +#define DMA_SEEI_NOP_MASK (0x80U) +#define DMA_SEEI_NOP_SHIFT (7U) +/*! NOP - No Op Enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other fields in this register + */ +#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) +/*! @} */ + +/*! @name CERQ - Clear Enable Request */ +/*! @{ */ + +#define DMA_CERQ_CERQ_MASK (0x1FU) +#define DMA_CERQ_CERQ_SHIFT (0U) +/*! CERQ - Clear Enable Request + */ +#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) + +#define DMA_CERQ_CAER_MASK (0x40U) +#define DMA_CERQ_CAER_SHIFT (6U) +/*! CAER - Clear All Enable Requests + * 0b0..Write 0 to only the ERQ field specified in the CERQ field + * 0b1..Write 0 to all fields in ERQ + */ +#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) + +#define DMA_CERQ_NOP_MASK (0x80U) +#define DMA_CERQ_NOP_SHIFT (7U) +/*! NOP - No Op Enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other fields in this register + */ +#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) +/*! @} */ + +/*! @name SERQ - Set Enable Request */ +/*! @{ */ + +#define DMA_SERQ_SERQ_MASK (0x1FU) +#define DMA_SERQ_SERQ_SHIFT (0U) +/*! SERQ - Set Enable Request + */ +#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) + +#define DMA_SERQ_SAER_MASK (0x40U) +#define DMA_SERQ_SAER_SHIFT (6U) +/*! SAER - Set All Enable Requests + * 0b0..Write 1 to only the ERQ field specified in the SERQ field + * 0b1..Write 1 to all fields in ERQ + */ +#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) + +#define DMA_SERQ_NOP_MASK (0x80U) +#define DMA_SERQ_NOP_SHIFT (7U) +/*! NOP - No Op Enable + * 0b0..Normal operation + * 0b1..No operation, ignore the other fields in this register + */ +#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) +/*! @} */ + +/*! @name CDNE - Clear DONE Status Bit */ +/*! @{ */ + +#define DMA_CDNE_CDNE_MASK (0x1FU) +#define DMA_CDNE_CDNE_SHIFT (0U) +/*! CDNE - Clear DONE field + */ +#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) + +#define DMA_CDNE_CADN_MASK (0x40U) +#define DMA_CDNE_CADN_SHIFT (6U) +/*! CADN - Clears All DONE fields + * 0b0..Writes 0 to only the TCDn_CSR[DONE] field specified in the CDNE field + * 0b1..Writes 0 to all bits in TCDn_CSR[DONE] + */ +#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK) + +#define DMA_CDNE_NOP_MASK (0x80U) +#define DMA_CDNE_NOP_SHIFT (7U) +/*! NOP - No Op Enable + * 0b0..Normal operation + * 0b1..No operation; all other fields in this register are ignored. + */ +#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) +/*! @} */ + +/*! @name SSRT - Set START Bit */ +/*! @{ */ + +#define DMA_SSRT_SSRT_MASK (0x1FU) +#define DMA_SSRT_SSRT_SHIFT (0U) +/*! SSRT - Set START field + */ +#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) + +#define DMA_SSRT_SAST_MASK (0x40U) +#define DMA_SSRT_SAST_SHIFT (6U) +/*! SAST - Set All START fields (activates all channels) + * 0b0..Write 1 to only the TCDn_CSR[START] field specified in the SSRT field + * 0b1..Write 1 to all bits in TCDn_CSR[START] + */ +#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK) + +#define DMA_SSRT_NOP_MASK (0x80U) +#define DMA_SSRT_NOP_SHIFT (7U) +/*! NOP - No Op Enable + * 0b0..Normal operation + * 0b1..No operation; all other fields in this register are ignored. + */ +#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) +/*! @} */ + +/*! @name CERR - Clear Error */ +/*! @{ */ + +#define DMA_CERR_CERR_MASK (0x1FU) +#define DMA_CERR_CERR_SHIFT (0U) +/*! CERR - Clear Error Indicator + */ +#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) + +#define DMA_CERR_CAEI_MASK (0x40U) +#define DMA_CERR_CAEI_SHIFT (6U) +/*! CAEI - Clear All Error Indicators + * 0b0..Write 0 to only the ERR field specified in the CERR field + * 0b1..Write 0 to all fields in ERR + */ +#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) + +#define DMA_CERR_NOP_MASK (0x80U) +#define DMA_CERR_NOP_SHIFT (7U) +/*! NOP - No Op Enable + * 0b0..Normal operation + * 0b1..No operation; all other fields in this register are ignored. + */ +#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) +/*! @} */ + +/*! @name CINT - Clear Interrupt Request */ +/*! @{ */ + +#define DMA_CINT_CINT_MASK (0x1FU) +#define DMA_CINT_CINT_SHIFT (0U) +/*! CINT - Clear Interrupt Request + */ +#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) + +#define DMA_CINT_CAIR_MASK (0x40U) +#define DMA_CINT_CAIR_SHIFT (6U) +/*! CAIR - Clear All Interrupt Requests + * 0b0..Clear only the INT field specified in the CINT field + * 0b1..Clear all bits in INT + */ +#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) + +#define DMA_CINT_NOP_MASK (0x80U) +#define DMA_CINT_NOP_SHIFT (7U) +/*! NOP - No Op Enable + * 0b0..Normal operation + * 0b1..No operation; all other fields in this register are ignored. + */ +#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) +/*! @} */ + +/*! @name INT - Interrupt Request */ +/*! @{ */ + +#define DMA_INT_INT0_MASK (0x1U) +#define DMA_INT_INT0_SHIFT (0U) +/*! INT0 - Interrupt Request 0 + * 0b0..The interrupt request for channel 0 is cleared + * 0b1..The interrupt request for channel 0 is active + */ +#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) + +#define DMA_INT_INT1_MASK (0x2U) +#define DMA_INT_INT1_SHIFT (1U) +/*! INT1 - Interrupt Request 1 + * 0b0..The interrupt request for channel 1 is cleared + * 0b1..The interrupt request for channel 1 is active + */ +#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK) + +#define DMA_INT_INT2_MASK (0x4U) +#define DMA_INT_INT2_SHIFT (2U) +/*! INT2 - Interrupt Request 2 + * 0b0..The interrupt request for channel 2 is cleared + * 0b1..The interrupt request for channel 2 is active + */ +#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK) + +#define DMA_INT_INT3_MASK (0x8U) +#define DMA_INT_INT3_SHIFT (3U) +/*! INT3 - Interrupt Request 3 + * 0b0..The interrupt request for channel 3 is cleared + * 0b1..The interrupt request for channel 3 is active + */ +#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK) + +#define DMA_INT_INT4_MASK (0x10U) +#define DMA_INT_INT4_SHIFT (4U) +/*! INT4 - Interrupt Request 4 + * 0b0..The interrupt request for channel 4 is cleared + * 0b1..The interrupt request for channel 4 is active + */ +#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK) + +#define DMA_INT_INT5_MASK (0x20U) +#define DMA_INT_INT5_SHIFT (5U) +/*! INT5 - Interrupt Request 5 + * 0b0..The interrupt request for channel 5 is cleared + * 0b1..The interrupt request for channel 5 is active + */ +#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK) + +#define DMA_INT_INT6_MASK (0x40U) +#define DMA_INT_INT6_SHIFT (6U) +/*! INT6 - Interrupt Request 6 + * 0b0..The interrupt request for channel 6 is cleared + * 0b1..The interrupt request for channel 6 is active + */ +#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK) + +#define DMA_INT_INT7_MASK (0x80U) +#define DMA_INT_INT7_SHIFT (7U) +/*! INT7 - Interrupt Request 7 + * 0b0..The interrupt request for channel 7 is cleared + * 0b1..The interrupt request for channel 7 is active + */ +#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK) + +#define DMA_INT_INT8_MASK (0x100U) +#define DMA_INT_INT8_SHIFT (8U) +/*! INT8 - Interrupt Request 8 + * 0b0..The interrupt request for channel 8 is cleared + * 0b1..The interrupt request for channel 8 is active + */ +#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK) + +#define DMA_INT_INT9_MASK (0x200U) +#define DMA_INT_INT9_SHIFT (9U) +/*! INT9 - Interrupt Request 9 + * 0b0..The interrupt request for channel 9 is cleared + * 0b1..The interrupt request for channel 9 is active + */ +#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK) + +#define DMA_INT_INT10_MASK (0x400U) +#define DMA_INT_INT10_SHIFT (10U) +/*! INT10 - Interrupt Request 10 + * 0b0..The interrupt request for channel 10 is cleared + * 0b1..The interrupt request for channel 10 is active + */ +#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK) + +#define DMA_INT_INT11_MASK (0x800U) +#define DMA_INT_INT11_SHIFT (11U) +/*! INT11 - Interrupt Request 11 + * 0b0..The interrupt request for channel 11 is cleared + * 0b1..The interrupt request for channel 11 is active + */ +#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK) + +#define DMA_INT_INT12_MASK (0x1000U) +#define DMA_INT_INT12_SHIFT (12U) +/*! INT12 - Interrupt Request 12 + * 0b0..The interrupt request for channel 12 is cleared + * 0b1..The interrupt request for channel 12 is active + */ +#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK) + +#define DMA_INT_INT13_MASK (0x2000U) +#define DMA_INT_INT13_SHIFT (13U) +/*! INT13 - Interrupt Request 13 + * 0b0..The interrupt request for channel 13 is cleared + * 0b1..The interrupt request for channel 13 is active + */ +#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK) + +#define DMA_INT_INT14_MASK (0x4000U) +#define DMA_INT_INT14_SHIFT (14U) +/*! INT14 - Interrupt Request 14 + * 0b0..The interrupt request for channel 14 is cleared + * 0b1..The interrupt request for channel 14 is active + */ +#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK) + +#define DMA_INT_INT15_MASK (0x8000U) +#define DMA_INT_INT15_SHIFT (15U) +/*! INT15 - Interrupt Request 15 + * 0b0..The interrupt request for channel 15 is cleared + * 0b1..The interrupt request for channel 15 is active + */ +#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK) + +#define DMA_INT_INT16_MASK (0x10000U) +#define DMA_INT_INT16_SHIFT (16U) +/*! INT16 - Interrupt Request 16 + * 0b0..The interrupt request for channel 16 is cleared + * 0b1..The interrupt request for channel 16 is active + */ +#define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK) + +#define DMA_INT_INT17_MASK (0x20000U) +#define DMA_INT_INT17_SHIFT (17U) +/*! INT17 - Interrupt Request 17 + * 0b0..The interrupt request for channel 17 is cleared + * 0b1..The interrupt request for channel 17 is active + */ +#define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK) + +#define DMA_INT_INT18_MASK (0x40000U) +#define DMA_INT_INT18_SHIFT (18U) +/*! INT18 - Interrupt Request 18 + * 0b0..The interrupt request for channel 18 is cleared + * 0b1..The interrupt request for channel 18 is active + */ +#define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK) + +#define DMA_INT_INT19_MASK (0x80000U) +#define DMA_INT_INT19_SHIFT (19U) +/*! INT19 - Interrupt Request 19 + * 0b0..The interrupt request for channel 19 is cleared + * 0b1..The interrupt request for channel 19 is active + */ +#define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK) + +#define DMA_INT_INT20_MASK (0x100000U) +#define DMA_INT_INT20_SHIFT (20U) +/*! INT20 - Interrupt Request 20 + * 0b0..The interrupt request for channel 20 is cleared + * 0b1..The interrupt request for channel 20 is active + */ +#define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK) + +#define DMA_INT_INT21_MASK (0x200000U) +#define DMA_INT_INT21_SHIFT (21U) +/*! INT21 - Interrupt Request 21 + * 0b0..The interrupt request for channel 21 is cleared + * 0b1..The interrupt request for channel 21 is active + */ +#define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK) + +#define DMA_INT_INT22_MASK (0x400000U) +#define DMA_INT_INT22_SHIFT (22U) +/*! INT22 - Interrupt Request 22 + * 0b0..The interrupt request for channel 22 is cleared + * 0b1..The interrupt request for channel 22 is active + */ +#define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK) + +#define DMA_INT_INT23_MASK (0x800000U) +#define DMA_INT_INT23_SHIFT (23U) +/*! INT23 - Interrupt Request 23 + * 0b0..The interrupt request for channel 23 is cleared + * 0b1..The interrupt request for channel 23 is active + */ +#define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK) + +#define DMA_INT_INT24_MASK (0x1000000U) +#define DMA_INT_INT24_SHIFT (24U) +/*! INT24 - Interrupt Request 24 + * 0b0..The interrupt request for channel 24 is cleared + * 0b1..The interrupt request for channel 24 is active + */ +#define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK) + +#define DMA_INT_INT25_MASK (0x2000000U) +#define DMA_INT_INT25_SHIFT (25U) /*! INT25 - Interrupt Request 25 * 0b0..The interrupt request for channel 25 is cleared * 0b1..The interrupt request for channel 25 is active */ -#define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK) -#define DMA_INT_INT26_MASK (0x4000000U) -#define DMA_INT_INT26_SHIFT (26U) -/*! INT26 - Interrupt Request 26 - * 0b0..The interrupt request for channel 26 is cleared - * 0b1..The interrupt request for channel 26 is active +#define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK) + +#define DMA_INT_INT26_MASK (0x4000000U) +#define DMA_INT_INT26_SHIFT (26U) +/*! INT26 - Interrupt Request 26 + * 0b0..The interrupt request for channel 26 is cleared + * 0b1..The interrupt request for channel 26 is active + */ +#define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK) + +#define DMA_INT_INT27_MASK (0x8000000U) +#define DMA_INT_INT27_SHIFT (27U) +/*! INT27 - Interrupt Request 27 + * 0b0..The interrupt request for channel 27 is cleared + * 0b1..The interrupt request for channel 27 is active + */ +#define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK) + +#define DMA_INT_INT28_MASK (0x10000000U) +#define DMA_INT_INT28_SHIFT (28U) +/*! INT28 - Interrupt Request 28 + * 0b0..The interrupt request for channel 28 is cleared + * 0b1..The interrupt request for channel 28 is active + */ +#define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK) + +#define DMA_INT_INT29_MASK (0x20000000U) +#define DMA_INT_INT29_SHIFT (29U) +/*! INT29 - Interrupt Request 29 + * 0b0..The interrupt request for channel 29 is cleared + * 0b1..The interrupt request for channel 29 is active + */ +#define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK) + +#define DMA_INT_INT30_MASK (0x40000000U) +#define DMA_INT_INT30_SHIFT (30U) +/*! INT30 - Interrupt Request 30 + * 0b0..The interrupt request for channel 30 is cleared + * 0b1..The interrupt request for channel 30 is active + */ +#define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK) + +#define DMA_INT_INT31_MASK (0x80000000U) +#define DMA_INT_INT31_SHIFT (31U) +/*! INT31 - Interrupt Request 31 + * 0b0..The interrupt request for channel 31 is cleared + * 0b1..The interrupt request for channel 31 is active + */ +#define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK) +/*! @} */ + +/*! @name ERR - Error */ +/*! @{ */ + +#define DMA_ERR_ERR0_MASK (0x1U) +#define DMA_ERR_ERR0_SHIFT (0U) +/*! ERR0 - Error In Channel 0 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) + +#define DMA_ERR_ERR1_MASK (0x2U) +#define DMA_ERR_ERR1_SHIFT (1U) +/*! ERR1 - Error In Channel 1 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK) + +#define DMA_ERR_ERR2_MASK (0x4U) +#define DMA_ERR_ERR2_SHIFT (2U) +/*! ERR2 - Error In Channel 2 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK) + +#define DMA_ERR_ERR3_MASK (0x8U) +#define DMA_ERR_ERR3_SHIFT (3U) +/*! ERR3 - Error In Channel 3 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK) + +#define DMA_ERR_ERR4_MASK (0x10U) +#define DMA_ERR_ERR4_SHIFT (4U) +/*! ERR4 - Error In Channel 4 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK) + +#define DMA_ERR_ERR5_MASK (0x20U) +#define DMA_ERR_ERR5_SHIFT (5U) +/*! ERR5 - Error In Channel 5 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK) + +#define DMA_ERR_ERR6_MASK (0x40U) +#define DMA_ERR_ERR6_SHIFT (6U) +/*! ERR6 - Error In Channel 6 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK) + +#define DMA_ERR_ERR7_MASK (0x80U) +#define DMA_ERR_ERR7_SHIFT (7U) +/*! ERR7 - Error In Channel 7 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK) + +#define DMA_ERR_ERR8_MASK (0x100U) +#define DMA_ERR_ERR8_SHIFT (8U) +/*! ERR8 - Error In Channel 8 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK) + +#define DMA_ERR_ERR9_MASK (0x200U) +#define DMA_ERR_ERR9_SHIFT (9U) +/*! ERR9 - Error In Channel 9 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK) + +#define DMA_ERR_ERR10_MASK (0x400U) +#define DMA_ERR_ERR10_SHIFT (10U) +/*! ERR10 - Error In Channel 10 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK) + +#define DMA_ERR_ERR11_MASK (0x800U) +#define DMA_ERR_ERR11_SHIFT (11U) +/*! ERR11 - Error In Channel 11 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK) + +#define DMA_ERR_ERR12_MASK (0x1000U) +#define DMA_ERR_ERR12_SHIFT (12U) +/*! ERR12 - Error In Channel 12 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK) + +#define DMA_ERR_ERR13_MASK (0x2000U) +#define DMA_ERR_ERR13_SHIFT (13U) +/*! ERR13 - Error In Channel 13 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK) + +#define DMA_ERR_ERR14_MASK (0x4000U) +#define DMA_ERR_ERR14_SHIFT (14U) +/*! ERR14 - Error In Channel 14 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK) + +#define DMA_ERR_ERR15_MASK (0x8000U) +#define DMA_ERR_ERR15_SHIFT (15U) +/*! ERR15 - Error In Channel 15 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK) + +#define DMA_ERR_ERR16_MASK (0x10000U) +#define DMA_ERR_ERR16_SHIFT (16U) +/*! ERR16 - Error In Channel 16 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK) + +#define DMA_ERR_ERR17_MASK (0x20000U) +#define DMA_ERR_ERR17_SHIFT (17U) +/*! ERR17 - Error In Channel 17 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK) + +#define DMA_ERR_ERR18_MASK (0x40000U) +#define DMA_ERR_ERR18_SHIFT (18U) +/*! ERR18 - Error In Channel 18 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK) + +#define DMA_ERR_ERR19_MASK (0x80000U) +#define DMA_ERR_ERR19_SHIFT (19U) +/*! ERR19 - Error In Channel 19 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK) + +#define DMA_ERR_ERR20_MASK (0x100000U) +#define DMA_ERR_ERR20_SHIFT (20U) +/*! ERR20 - Error In Channel 20 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK) + +#define DMA_ERR_ERR21_MASK (0x200000U) +#define DMA_ERR_ERR21_SHIFT (21U) +/*! ERR21 - Error In Channel 21 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK) + +#define DMA_ERR_ERR22_MASK (0x400000U) +#define DMA_ERR_ERR22_SHIFT (22U) +/*! ERR22 - Error In Channel 22 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK) + +#define DMA_ERR_ERR23_MASK (0x800000U) +#define DMA_ERR_ERR23_SHIFT (23U) +/*! ERR23 - Error In Channel 23 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK) + +#define DMA_ERR_ERR24_MASK (0x1000000U) +#define DMA_ERR_ERR24_SHIFT (24U) +/*! ERR24 - Error In Channel 24 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK) + +#define DMA_ERR_ERR25_MASK (0x2000000U) +#define DMA_ERR_ERR25_SHIFT (25U) +/*! ERR25 - Error In Channel 25 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK) + +#define DMA_ERR_ERR26_MASK (0x4000000U) +#define DMA_ERR_ERR26_SHIFT (26U) +/*! ERR26 - Error In Channel 26 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK) + +#define DMA_ERR_ERR27_MASK (0x8000000U) +#define DMA_ERR_ERR27_SHIFT (27U) +/*! ERR27 - Error In Channel 27 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK) + +#define DMA_ERR_ERR28_MASK (0x10000000U) +#define DMA_ERR_ERR28_SHIFT (28U) +/*! ERR28 - Error In Channel 28 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK) + +#define DMA_ERR_ERR29_MASK (0x20000000U) +#define DMA_ERR_ERR29_SHIFT (29U) +/*! ERR29 - Error In Channel 29 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK) + +#define DMA_ERR_ERR30_MASK (0x40000000U) +#define DMA_ERR_ERR30_SHIFT (30U) +/*! ERR30 - Error In Channel 30 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK) + +#define DMA_ERR_ERR31_MASK (0x80000000U) +#define DMA_ERR_ERR31_SHIFT (31U) +/*! ERR31 - Error In Channel 31 + * 0b0..No error in this channel has occurred + * 0b1..An error in this channel has occurred + */ +#define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK) +/*! @} */ + +/*! @name HRS - Hardware Request Status */ +/*! @{ */ + +#define DMA_HRS_HRS0_MASK (0x1U) +#define DMA_HRS_HRS0_SHIFT (0U) +/*! HRS0 - Hardware Request Status Channel 0 + * 0b0..A hardware service request for channel 0 is not present + * 0b1..A hardware service request for channel 0 is present + */ +#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) + +#define DMA_HRS_HRS1_MASK (0x2U) +#define DMA_HRS_HRS1_SHIFT (1U) +/*! HRS1 - Hardware Request Status Channel 1 + * 0b0..A hardware service request for channel 1 is not present + * 0b1..A hardware service request for channel 1 is present + */ +#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK) + +#define DMA_HRS_HRS2_MASK (0x4U) +#define DMA_HRS_HRS2_SHIFT (2U) +/*! HRS2 - Hardware Request Status Channel 2 + * 0b0..A hardware service request for channel 2 is not present + * 0b1..A hardware service request for channel 2 is present + */ +#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK) + +#define DMA_HRS_HRS3_MASK (0x8U) +#define DMA_HRS_HRS3_SHIFT (3U) +/*! HRS3 - Hardware Request Status Channel 3 + * 0b0..A hardware service request for channel 3 is not present + * 0b1..A hardware service request for channel 3 is present + */ +#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK) + +#define DMA_HRS_HRS4_MASK (0x10U) +#define DMA_HRS_HRS4_SHIFT (4U) +/*! HRS4 - Hardware Request Status Channel 4 + * 0b0..A hardware service request for channel 4 is not present + * 0b1..A hardware service request for channel 4 is present + */ +#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK) + +#define DMA_HRS_HRS5_MASK (0x20U) +#define DMA_HRS_HRS5_SHIFT (5U) +/*! HRS5 - Hardware Request Status Channel 5 + * 0b0..A hardware service request for channel 5 is not present + * 0b1..A hardware service request for channel 5 is present + */ +#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK) + +#define DMA_HRS_HRS6_MASK (0x40U) +#define DMA_HRS_HRS6_SHIFT (6U) +/*! HRS6 - Hardware Request Status Channel 6 + * 0b0..A hardware service request for channel 6 is not present + * 0b1..A hardware service request for channel 6 is present + */ +#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK) + +#define DMA_HRS_HRS7_MASK (0x80U) +#define DMA_HRS_HRS7_SHIFT (7U) +/*! HRS7 - Hardware Request Status Channel 7 + * 0b0..A hardware service request for channel 7 is not present + * 0b1..A hardware service request for channel 7 is present + */ +#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK) + +#define DMA_HRS_HRS8_MASK (0x100U) +#define DMA_HRS_HRS8_SHIFT (8U) +/*! HRS8 - Hardware Request Status Channel 8 + * 0b0..A hardware service request for channel 8 is not present + * 0b1..A hardware service request for channel 8 is present + */ +#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK) + +#define DMA_HRS_HRS9_MASK (0x200U) +#define DMA_HRS_HRS9_SHIFT (9U) +/*! HRS9 - Hardware Request Status Channel 9 + * 0b0..A hardware service request for channel 9 is not present + * 0b1..A hardware service request for channel 9 is present + */ +#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK) + +#define DMA_HRS_HRS10_MASK (0x400U) +#define DMA_HRS_HRS10_SHIFT (10U) +/*! HRS10 - Hardware Request Status Channel 10 + * 0b0..A hardware service request for channel 10 is not present + * 0b1..A hardware service request for channel 10 is present + */ +#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK) + +#define DMA_HRS_HRS11_MASK (0x800U) +#define DMA_HRS_HRS11_SHIFT (11U) +/*! HRS11 - Hardware Request Status Channel 11 + * 0b0..A hardware service request for channel 11 is not present + * 0b1..A hardware service request for channel 11 is present + */ +#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK) + +#define DMA_HRS_HRS12_MASK (0x1000U) +#define DMA_HRS_HRS12_SHIFT (12U) +/*! HRS12 - Hardware Request Status Channel 12 + * 0b0..A hardware service request for channel 12 is not present + * 0b1..A hardware service request for channel 12 is present + */ +#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK) + +#define DMA_HRS_HRS13_MASK (0x2000U) +#define DMA_HRS_HRS13_SHIFT (13U) +/*! HRS13 - Hardware Request Status Channel 13 + * 0b0..A hardware service request for channel 13 is not present + * 0b1..A hardware service request for channel 13 is present + */ +#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK) + +#define DMA_HRS_HRS14_MASK (0x4000U) +#define DMA_HRS_HRS14_SHIFT (14U) +/*! HRS14 - Hardware Request Status Channel 14 + * 0b0..A hardware service request for channel 14 is not present + * 0b1..A hardware service request for channel 14 is present + */ +#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK) + +#define DMA_HRS_HRS15_MASK (0x8000U) +#define DMA_HRS_HRS15_SHIFT (15U) +/*! HRS15 - Hardware Request Status Channel 15 + * 0b0..A hardware service request for channel 15 is not present + * 0b1..A hardware service request for channel 15 is present + */ +#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK) + +#define DMA_HRS_HRS16_MASK (0x10000U) +#define DMA_HRS_HRS16_SHIFT (16U) +/*! HRS16 - Hardware Request Status Channel 16 + * 0b0..A hardware service request for channel 16 is not present + * 0b1..A hardware service request for channel 16 is present + */ +#define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK) + +#define DMA_HRS_HRS17_MASK (0x20000U) +#define DMA_HRS_HRS17_SHIFT (17U) +/*! HRS17 - Hardware Request Status Channel 17 + * 0b0..A hardware service request for channel 17 is not present + * 0b1..A hardware service request for channel 17 is present + */ +#define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK) + +#define DMA_HRS_HRS18_MASK (0x40000U) +#define DMA_HRS_HRS18_SHIFT (18U) +/*! HRS18 - Hardware Request Status Channel 18 + * 0b0..A hardware service request for channel 18 is not present + * 0b1..A hardware service request for channel 18 is present + */ +#define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK) + +#define DMA_HRS_HRS19_MASK (0x80000U) +#define DMA_HRS_HRS19_SHIFT (19U) +/*! HRS19 - Hardware Request Status Channel 19 + * 0b0..A hardware service request for channel 19 is not present + * 0b1..A hardware service request for channel 19 is present */ -#define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK) -#define DMA_INT_INT27_MASK (0x8000000U) -#define DMA_INT_INT27_SHIFT (27U) -/*! INT27 - Interrupt Request 27 - * 0b0..The interrupt request for channel 27 is cleared - * 0b1..The interrupt request for channel 27 is active +#define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK) + +#define DMA_HRS_HRS20_MASK (0x100000U) +#define DMA_HRS_HRS20_SHIFT (20U) +/*! HRS20 - Hardware Request Status Channel 20 + * 0b0..A hardware service request for channel 20 is not present + * 0b1..A hardware service request for channel 20 is present */ -#define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK) -#define DMA_INT_INT28_MASK (0x10000000U) -#define DMA_INT_INT28_SHIFT (28U) -/*! INT28 - Interrupt Request 28 - * 0b0..The interrupt request for channel 28 is cleared - * 0b1..The interrupt request for channel 28 is active +#define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK) + +#define DMA_HRS_HRS21_MASK (0x200000U) +#define DMA_HRS_HRS21_SHIFT (21U) +/*! HRS21 - Hardware Request Status Channel 21 + * 0b0..A hardware service request for channel 21 is not present + * 0b1..A hardware service request for channel 21 is present */ -#define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK) -#define DMA_INT_INT29_MASK (0x20000000U) -#define DMA_INT_INT29_SHIFT (29U) -/*! INT29 - Interrupt Request 29 - * 0b0..The interrupt request for channel 29 is cleared - * 0b1..The interrupt request for channel 29 is active +#define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK) + +#define DMA_HRS_HRS22_MASK (0x400000U) +#define DMA_HRS_HRS22_SHIFT (22U) +/*! HRS22 - Hardware Request Status Channel 22 + * 0b0..A hardware service request for channel 22 is not present + * 0b1..A hardware service request for channel 22 is present */ -#define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK) -#define DMA_INT_INT30_MASK (0x40000000U) -#define DMA_INT_INT30_SHIFT (30U) -/*! INT30 - Interrupt Request 30 - * 0b0..The interrupt request for channel 30 is cleared - * 0b1..The interrupt request for channel 30 is active +#define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK) + +#define DMA_HRS_HRS23_MASK (0x800000U) +#define DMA_HRS_HRS23_SHIFT (23U) +/*! HRS23 - Hardware Request Status Channel 23 + * 0b0..A hardware service request for channel 23 is not present + * 0b1..A hardware service request for channel 23 is present */ -#define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK) -#define DMA_INT_INT31_MASK (0x80000000U) -#define DMA_INT_INT31_SHIFT (31U) -/*! INT31 - Interrupt Request 31 - * 0b0..The interrupt request for channel 31 is cleared - * 0b1..The interrupt request for channel 31 is active +#define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK) + +#define DMA_HRS_HRS24_MASK (0x1000000U) +#define DMA_HRS_HRS24_SHIFT (24U) +/*! HRS24 - Hardware Request Status Channel 24 + * 0b0..A hardware service request for channel 24 is not present + * 0b1..A hardware service request for channel 24 is present */ -#define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK) +#define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK) + +#define DMA_HRS_HRS25_MASK (0x2000000U) +#define DMA_HRS_HRS25_SHIFT (25U) +/*! HRS25 - Hardware Request Status Channel 25 + * 0b0..A hardware service request for channel 25 is not present + * 0b1..A hardware service request for channel 25 is present + */ +#define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK) + +#define DMA_HRS_HRS26_MASK (0x4000000U) +#define DMA_HRS_HRS26_SHIFT (26U) +/*! HRS26 - Hardware Request Status Channel 26 + * 0b0..A hardware service request for channel 26 is not present + * 0b1..A hardware service request for channel 26 is present + */ +#define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK) + +#define DMA_HRS_HRS27_MASK (0x8000000U) +#define DMA_HRS_HRS27_SHIFT (27U) +/*! HRS27 - Hardware Request Status Channel 27 + * 0b0..A hardware service request for channel 27 is not present + * 0b1..A hardware service request for channel 27 is present + */ +#define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK) + +#define DMA_HRS_HRS28_MASK (0x10000000U) +#define DMA_HRS_HRS28_SHIFT (28U) +/*! HRS28 - Hardware Request Status Channel 28 + * 0b0..A hardware service request for channel 28 is not present + * 0b1..A hardware service request for channel 28 is present + */ +#define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK) + +#define DMA_HRS_HRS29_MASK (0x20000000U) +#define DMA_HRS_HRS29_SHIFT (29U) +/*! HRS29 - Hardware Request Status Channel 29 + * 0b0..A hardware service request for channel 29 is not preset + * 0b1..A hardware service request for channel 29 is present + */ +#define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK) + +#define DMA_HRS_HRS30_MASK (0x40000000U) +#define DMA_HRS_HRS30_SHIFT (30U) +/*! HRS30 - Hardware Request Status Channel 30 + * 0b0..A hardware service request for channel 30 is not present + * 0b1..A hardware service request for channel 30 is present + */ +#define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK) + +#define DMA_HRS_HRS31_MASK (0x80000000U) +#define DMA_HRS_HRS31_SHIFT (31U) +/*! HRS31 - Hardware Request Status Channel 31 + * 0b0..A hardware service request for channel 31 is not present + * 0b1..A hardware service request for channel 31 is present + */ +#define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK) /*! @} */ -/*! @name ERR - Error */ +/*! @name EARS - Enable Asynchronous Request in Stop */ /*! @{ */ -#define DMA_ERR_ERR0_MASK (0x1U) -#define DMA_ERR_ERR0_SHIFT (0U) -/*! ERR0 - Error In Channel 0 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred + +#define DMA_EARS_EDREQ_0_MASK (0x1U) +#define DMA_EARS_EDREQ_0_SHIFT (0U) +/*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0. + * 0b0..Disable asynchronous DMA request for channel 0 + * 0b1..Enable asynchronous DMA request for channel 0 */ -#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) -#define DMA_ERR_ERR1_MASK (0x2U) -#define DMA_ERR_ERR1_SHIFT (1U) -/*! ERR1 - Error In Channel 1 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK) + +#define DMA_EARS_EDREQ_1_MASK (0x2U) +#define DMA_EARS_EDREQ_1_SHIFT (1U) +/*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1. + * 0b0..Disable asynchronous DMA request for channel 1 + * 0b1..Enable asynchronous DMA request for channel 1 */ -#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK) -#define DMA_ERR_ERR2_MASK (0x4U) -#define DMA_ERR_ERR2_SHIFT (2U) -/*! ERR2 - Error In Channel 2 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK) + +#define DMA_EARS_EDREQ_2_MASK (0x4U) +#define DMA_EARS_EDREQ_2_SHIFT (2U) +/*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2. + * 0b0..Disable asynchronous DMA request for channel 2 + * 0b1..Enable asynchronous DMA request for channel 2 */ -#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK) -#define DMA_ERR_ERR3_MASK (0x8U) -#define DMA_ERR_ERR3_SHIFT (3U) -/*! ERR3 - Error In Channel 3 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK) + +#define DMA_EARS_EDREQ_3_MASK (0x8U) +#define DMA_EARS_EDREQ_3_SHIFT (3U) +/*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3. + * 0b0..Disable asynchronous DMA request for channel 3 + * 0b1..Enable asynchronous DMA request for channel 3 */ -#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK) -#define DMA_ERR_ERR4_MASK (0x10U) -#define DMA_ERR_ERR4_SHIFT (4U) -/*! ERR4 - Error In Channel 4 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK) + +#define DMA_EARS_EDREQ_4_MASK (0x10U) +#define DMA_EARS_EDREQ_4_SHIFT (4U) +/*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4. + * 0b0..Disable asynchronous DMA request for channel 4 + * 0b1..Enable asynchronous DMA request for channel 4 */ -#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK) -#define DMA_ERR_ERR5_MASK (0x20U) -#define DMA_ERR_ERR5_SHIFT (5U) -/*! ERR5 - Error In Channel 5 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK) + +#define DMA_EARS_EDREQ_5_MASK (0x20U) +#define DMA_EARS_EDREQ_5_SHIFT (5U) +/*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5. + * 0b0..Disable asynchronous DMA request for channel 5 + * 0b1..Enable asynchronous DMA request for channel 5 */ -#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK) -#define DMA_ERR_ERR6_MASK (0x40U) -#define DMA_ERR_ERR6_SHIFT (6U) -/*! ERR6 - Error In Channel 6 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK) + +#define DMA_EARS_EDREQ_6_MASK (0x40U) +#define DMA_EARS_EDREQ_6_SHIFT (6U) +/*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6. + * 0b0..Disable asynchronous DMA request for channel 6 + * 0b1..Enable asynchronous DMA request for channel 6 */ -#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK) -#define DMA_ERR_ERR7_MASK (0x80U) -#define DMA_ERR_ERR7_SHIFT (7U) -/*! ERR7 - Error In Channel 7 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK) + +#define DMA_EARS_EDREQ_7_MASK (0x80U) +#define DMA_EARS_EDREQ_7_SHIFT (7U) +/*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7. + * 0b0..Disable asynchronous DMA request for channel 7 + * 0b1..Enable asynchronous DMA request for channel 7 */ -#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK) -#define DMA_ERR_ERR8_MASK (0x100U) -#define DMA_ERR_ERR8_SHIFT (8U) -/*! ERR8 - Error In Channel 8 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK) + +#define DMA_EARS_EDREQ_8_MASK (0x100U) +#define DMA_EARS_EDREQ_8_SHIFT (8U) +/*! EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8. + * 0b0..Disable asynchronous DMA request for channel 8 + * 0b1..Enable asynchronous DMA request for channel 8 */ -#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK) -#define DMA_ERR_ERR9_MASK (0x200U) -#define DMA_ERR_ERR9_SHIFT (9U) -/*! ERR9 - Error In Channel 9 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK) + +#define DMA_EARS_EDREQ_9_MASK (0x200U) +#define DMA_EARS_EDREQ_9_SHIFT (9U) +/*! EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9. + * 0b0..Disable asynchronous DMA request for channel 9 + * 0b1..Enable asynchronous DMA request for channel 9 */ -#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK) -#define DMA_ERR_ERR10_MASK (0x400U) -#define DMA_ERR_ERR10_SHIFT (10U) -/*! ERR10 - Error In Channel 10 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK) + +#define DMA_EARS_EDREQ_10_MASK (0x400U) +#define DMA_EARS_EDREQ_10_SHIFT (10U) +/*! EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10. + * 0b0..Disable asynchronous DMA request for channel 10 + * 0b1..Enable asynchronous DMA request for channel 10 */ -#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK) -#define DMA_ERR_ERR11_MASK (0x800U) -#define DMA_ERR_ERR11_SHIFT (11U) -/*! ERR11 - Error In Channel 11 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK) + +#define DMA_EARS_EDREQ_11_MASK (0x800U) +#define DMA_EARS_EDREQ_11_SHIFT (11U) +/*! EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11. + * 0b0..Disable asynchronous DMA request for channel 11 + * 0b1..Enable asynchronous DMA request for channel 11 + */ +#define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK) + +#define DMA_EARS_EDREQ_12_MASK (0x1000U) +#define DMA_EARS_EDREQ_12_SHIFT (12U) +/*! EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12. + * 0b0..Disable asynchronous DMA request for channel 12 + * 0b1..Enable asynchronous DMA request for channel 12 + */ +#define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK) + +#define DMA_EARS_EDREQ_13_MASK (0x2000U) +#define DMA_EARS_EDREQ_13_SHIFT (13U) +/*! EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13. + * 0b0..Disable asynchronous DMA request for channel 13 + * 0b1..Enable asynchronous DMA request for channel 13 + */ +#define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK) + +#define DMA_EARS_EDREQ_14_MASK (0x4000U) +#define DMA_EARS_EDREQ_14_SHIFT (14U) +/*! EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14. + * 0b0..Disable asynchronous DMA request for channel 14 + * 0b1..Enable asynchronous DMA request for channel 14 + */ +#define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK) + +#define DMA_EARS_EDREQ_15_MASK (0x8000U) +#define DMA_EARS_EDREQ_15_SHIFT (15U) +/*! EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15. + * 0b0..Disable asynchronous DMA request for channel 15 + * 0b1..Enable asynchronous DMA request for channel 15 + */ +#define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK) + +#define DMA_EARS_EDREQ_16_MASK (0x10000U) +#define DMA_EARS_EDREQ_16_SHIFT (16U) +/*! EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16. + * 0b0..Disable asynchronous DMA request for channel 16 + * 0b1..Enable asynchronous DMA request for channel 16 + */ +#define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK) + +#define DMA_EARS_EDREQ_17_MASK (0x20000U) +#define DMA_EARS_EDREQ_17_SHIFT (17U) +/*! EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17. + * 0b0..Disable asynchronous DMA request for channel 17 + * 0b1..Enable asynchronous DMA request for channel 17 + */ +#define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK) + +#define DMA_EARS_EDREQ_18_MASK (0x40000U) +#define DMA_EARS_EDREQ_18_SHIFT (18U) +/*! EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18. + * 0b0..Disable asynchronous DMA request for channel 18 + * 0b1..Enable asynchronous DMA request for channel 18 + */ +#define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK) + +#define DMA_EARS_EDREQ_19_MASK (0x80000U) +#define DMA_EARS_EDREQ_19_SHIFT (19U) +/*! EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19. + * 0b0..Disable asynchronous DMA request for channel 19 + * 0b1..Enable asynchronous DMA request for channel 19 + */ +#define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK) + +#define DMA_EARS_EDREQ_20_MASK (0x100000U) +#define DMA_EARS_EDREQ_20_SHIFT (20U) +/*! EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20. + * 0b0..Disable asynchronous DMA request for channel 20 + * 0b1..Enable asynchronous DMA request for channel 20 + */ +#define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK) + +#define DMA_EARS_EDREQ_21_MASK (0x200000U) +#define DMA_EARS_EDREQ_21_SHIFT (21U) +/*! EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21. + * 0b0..Disable asynchronous DMA request for channel 21 + * 0b1..Enable asynchronous DMA request for channel 21 + */ +#define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK) + +#define DMA_EARS_EDREQ_22_MASK (0x400000U) +#define DMA_EARS_EDREQ_22_SHIFT (22U) +/*! EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22. + * 0b0..Disable asynchronous DMA request for channel 22 + * 0b1..Enable asynchronous DMA request for channel 22 + */ +#define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK) + +#define DMA_EARS_EDREQ_23_MASK (0x800000U) +#define DMA_EARS_EDREQ_23_SHIFT (23U) +/*! EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23. + * 0b0..Disable asynchronous DMA request for channel 23 + * 0b1..Enable asynchronous DMA request for channel 23 + */ +#define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK) + +#define DMA_EARS_EDREQ_24_MASK (0x1000000U) +#define DMA_EARS_EDREQ_24_SHIFT (24U) +/*! EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24. + * 0b0..Disable asynchronous DMA request for channel 24 + * 0b1..Enable asynchronous DMA request for channel 24 + */ +#define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK) + +#define DMA_EARS_EDREQ_25_MASK (0x2000000U) +#define DMA_EARS_EDREQ_25_SHIFT (25U) +/*! EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25. + * 0b0..Disable asynchronous DMA request for channel 25 + * 0b1..Enable asynchronous DMA request for channel 25 + */ +#define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK) + +#define DMA_EARS_EDREQ_26_MASK (0x4000000U) +#define DMA_EARS_EDREQ_26_SHIFT (26U) +/*! EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26. + * 0b0..Disable asynchronous DMA request for channel 26 + * 0b1..Enable asynchronous DMA request for channel 26 + */ +#define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK) + +#define DMA_EARS_EDREQ_27_MASK (0x8000000U) +#define DMA_EARS_EDREQ_27_SHIFT (27U) +/*! EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27. + * 0b0..Disable asynchronous DMA request for channel 27 + * 0b1..Enable asynchronous DMA request for channel 27 + */ +#define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK) + +#define DMA_EARS_EDREQ_28_MASK (0x10000000U) +#define DMA_EARS_EDREQ_28_SHIFT (28U) +/*! EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28. + * 0b0..Disable asynchronous DMA request for channel 28 + * 0b1..Enable asynchronous DMA request for channel 28 + */ +#define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK) + +#define DMA_EARS_EDREQ_29_MASK (0x20000000U) +#define DMA_EARS_EDREQ_29_SHIFT (29U) +/*! EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29. + * 0b0..Disable asynchronous DMA request for channel 29 + * 0b1..Enable asynchronous DMA request for channel 29 + */ +#define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK) + +#define DMA_EARS_EDREQ_30_MASK (0x40000000U) +#define DMA_EARS_EDREQ_30_SHIFT (30U) +/*! EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30. + * 0b0..Disable asynchronous DMA request for channel 30 + * 0b1..Enable asynchronous DMA request for channel 30 + */ +#define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK) + +#define DMA_EARS_EDREQ_31_MASK (0x80000000U) +#define DMA_EARS_EDREQ_31_SHIFT (31U) +/*! EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31. + * 0b0..Disable asynchronous DMA request for channel 31 + * 0b1..Enable asynchronous DMA request for channel 31 + */ +#define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK) +/*! @} */ + +/*! @name DCHPRI3 - Channel Priority */ +/*! @{ */ + +#define DMA_DCHPRI3_CHPRI_MASK (0xFU) +#define DMA_DCHPRI3_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK) + +#define DMA_DCHPRI3_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI3_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK) + +#define DMA_DCHPRI3_DPA_MASK (0x40U) +#define DMA_DCHPRI3_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority + */ +#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK) + +#define DMA_DCHPRI3_ECP_MASK (0x80U) +#define DMA_DCHPRI3_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + */ +#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI2 - Channel Priority */ +/*! @{ */ + +#define DMA_DCHPRI2_CHPRI_MASK (0xFU) +#define DMA_DCHPRI2_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority + */ +#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK) + +#define DMA_DCHPRI2_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI2_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority + */ +#define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK) + +#define DMA_DCHPRI2_DPA_MASK (0x40U) +#define DMA_DCHPRI2_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK) -#define DMA_ERR_ERR12_MASK (0x1000U) -#define DMA_ERR_ERR12_SHIFT (12U) -/*! ERR12 - Error In Channel 12 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK) + +#define DMA_DCHPRI2_ECP_MASK (0x80U) +#define DMA_DCHPRI2_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel */ -#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK) -#define DMA_ERR_ERR13_MASK (0x2000U) -#define DMA_ERR_ERR13_SHIFT (13U) -/*! ERR13 - Error In Channel 13 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI1 - Channel Priority */ +/*! @{ */ + +#define DMA_DCHPRI1_CHPRI_MASK (0xFU) +#define DMA_DCHPRI1_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority */ -#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK) -#define DMA_ERR_ERR14_MASK (0x4000U) -#define DMA_ERR_ERR14_SHIFT (14U) -/*! ERR14 - Error In Channel 14 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK) + +#define DMA_DCHPRI1_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI1_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority */ -#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK) -#define DMA_ERR_ERR15_MASK (0x8000U) -#define DMA_ERR_ERR15_SHIFT (15U) -/*! ERR15 - Error In Channel 15 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK) + +#define DMA_DCHPRI1_DPA_MASK (0x40U) +#define DMA_DCHPRI1_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK) -#define DMA_ERR_ERR16_MASK (0x10000U) -#define DMA_ERR_ERR16_SHIFT (16U) -/*! ERR16 - Error In Channel 16 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK) + +#define DMA_DCHPRI1_ECP_MASK (0x80U) +#define DMA_DCHPRI1_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel */ -#define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK) -#define DMA_ERR_ERR17_MASK (0x20000U) -#define DMA_ERR_ERR17_SHIFT (17U) -/*! ERR17 - Error In Channel 17 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI0 - Channel Priority */ +/*! @{ */ + +#define DMA_DCHPRI0_CHPRI_MASK (0xFU) +#define DMA_DCHPRI0_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority */ -#define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK) -#define DMA_ERR_ERR18_MASK (0x40000U) -#define DMA_ERR_ERR18_SHIFT (18U) -/*! ERR18 - Error In Channel 18 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK) + +#define DMA_DCHPRI0_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI0_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority */ -#define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK) -#define DMA_ERR_ERR19_MASK (0x80000U) -#define DMA_ERR_ERR19_SHIFT (19U) -/*! ERR19 - Error In Channel 19 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK) + +#define DMA_DCHPRI0_DPA_MASK (0x40U) +#define DMA_DCHPRI0_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK) -#define DMA_ERR_ERR20_MASK (0x100000U) -#define DMA_ERR_ERR20_SHIFT (20U) -/*! ERR20 - Error In Channel 20 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK) + +#define DMA_DCHPRI0_ECP_MASK (0x80U) +#define DMA_DCHPRI0_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel */ -#define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK) -#define DMA_ERR_ERR21_MASK (0x200000U) -#define DMA_ERR_ERR21_SHIFT (21U) -/*! ERR21 - Error In Channel 21 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI7 - Channel Priority */ +/*! @{ */ + +#define DMA_DCHPRI7_CHPRI_MASK (0xFU) +#define DMA_DCHPRI7_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority */ -#define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK) -#define DMA_ERR_ERR22_MASK (0x400000U) -#define DMA_ERR_ERR22_SHIFT (22U) -/*! ERR22 - Error In Channel 22 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK) + +#define DMA_DCHPRI7_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI7_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority */ -#define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK) -#define DMA_ERR_ERR23_MASK (0x800000U) -#define DMA_ERR_ERR23_SHIFT (23U) -/*! ERR23 - Error In Channel 23 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK) + +#define DMA_DCHPRI7_DPA_MASK (0x40U) +#define DMA_DCHPRI7_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK) -#define DMA_ERR_ERR24_MASK (0x1000000U) -#define DMA_ERR_ERR24_SHIFT (24U) -/*! ERR24 - Error In Channel 24 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK) + +#define DMA_DCHPRI7_ECP_MASK (0x80U) +#define DMA_DCHPRI7_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel */ -#define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK) -#define DMA_ERR_ERR25_MASK (0x2000000U) -#define DMA_ERR_ERR25_SHIFT (25U) -/*! ERR25 - Error In Channel 25 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI6 - Channel Priority */ +/*! @{ */ + +#define DMA_DCHPRI6_CHPRI_MASK (0xFU) +#define DMA_DCHPRI6_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority */ -#define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK) -#define DMA_ERR_ERR26_MASK (0x4000000U) -#define DMA_ERR_ERR26_SHIFT (26U) -/*! ERR26 - Error In Channel 26 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK) + +#define DMA_DCHPRI6_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI6_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority */ -#define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK) -#define DMA_ERR_ERR27_MASK (0x8000000U) -#define DMA_ERR_ERR27_SHIFT (27U) -/*! ERR27 - Error In Channel 27 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK) + +#define DMA_DCHPRI6_DPA_MASK (0x40U) +#define DMA_DCHPRI6_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK) -#define DMA_ERR_ERR28_MASK (0x10000000U) -#define DMA_ERR_ERR28_SHIFT (28U) -/*! ERR28 - Error In Channel 28 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK) + +#define DMA_DCHPRI6_ECP_MASK (0x80U) +#define DMA_DCHPRI6_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel */ -#define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK) -#define DMA_ERR_ERR29_MASK (0x20000000U) -#define DMA_ERR_ERR29_SHIFT (29U) -/*! ERR29 - Error In Channel 29 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI5 - Channel Priority */ +/*! @{ */ + +#define DMA_DCHPRI5_CHPRI_MASK (0xFU) +#define DMA_DCHPRI5_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority */ -#define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK) -#define DMA_ERR_ERR30_MASK (0x40000000U) -#define DMA_ERR_ERR30_SHIFT (30U) -/*! ERR30 - Error In Channel 30 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK) + +#define DMA_DCHPRI5_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI5_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority */ -#define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK) -#define DMA_ERR_ERR31_MASK (0x80000000U) -#define DMA_ERR_ERR31_SHIFT (31U) -/*! ERR31 - Error In Channel 31 - * 0b0..No error in this channel has occurred - * 0b1..An error in this channel has occurred +#define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK) + +#define DMA_DCHPRI5_DPA_MASK (0x40U) +#define DMA_DCHPRI5_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK) +#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK) + +#define DMA_DCHPRI5_ECP_MASK (0x80U) +#define DMA_DCHPRI5_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + */ +#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK) /*! @} */ -/*! @name HRS - Hardware Request Status */ +/*! @name DCHPRI4 - Channel Priority */ /*! @{ */ -#define DMA_HRS_HRS0_MASK (0x1U) -#define DMA_HRS_HRS0_SHIFT (0U) -/*! HRS0 - Hardware Request Status Channel 0 - * 0b0..A hardware service request for channel 0 is not present - * 0b1..A hardware service request for channel 0 is present + +#define DMA_DCHPRI4_CHPRI_MASK (0xFU) +#define DMA_DCHPRI4_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority */ -#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) -#define DMA_HRS_HRS1_MASK (0x2U) -#define DMA_HRS_HRS1_SHIFT (1U) -/*! HRS1 - Hardware Request Status Channel 1 - * 0b0..A hardware service request for channel 1 is not present - * 0b1..A hardware service request for channel 1 is present +#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK) + +#define DMA_DCHPRI4_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI4_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority */ -#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK) -#define DMA_HRS_HRS2_MASK (0x4U) -#define DMA_HRS_HRS2_SHIFT (2U) -/*! HRS2 - Hardware Request Status Channel 2 - * 0b0..A hardware service request for channel 2 is not present - * 0b1..A hardware service request for channel 2 is present +#define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK) + +#define DMA_DCHPRI4_DPA_MASK (0x40U) +#define DMA_DCHPRI4_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK) -#define DMA_HRS_HRS3_MASK (0x8U) -#define DMA_HRS_HRS3_SHIFT (3U) -/*! HRS3 - Hardware Request Status Channel 3 - * 0b0..A hardware service request for channel 3 is not present - * 0b1..A hardware service request for channel 3 is present +#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK) + +#define DMA_DCHPRI4_ECP_MASK (0x80U) +#define DMA_DCHPRI4_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel */ -#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK) -#define DMA_HRS_HRS4_MASK (0x10U) -#define DMA_HRS_HRS4_SHIFT (4U) -/*! HRS4 - Hardware Request Status Channel 4 - * 0b0..A hardware service request for channel 4 is not present - * 0b1..A hardware service request for channel 4 is present +#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI11 - Channel Priority */ +/*! @{ */ + +#define DMA_DCHPRI11_CHPRI_MASK (0xFU) +#define DMA_DCHPRI11_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority */ -#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK) -#define DMA_HRS_HRS5_MASK (0x20U) -#define DMA_HRS_HRS5_SHIFT (5U) -/*! HRS5 - Hardware Request Status Channel 5 - * 0b0..A hardware service request for channel 5 is not present - * 0b1..A hardware service request for channel 5 is present +#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK) + +#define DMA_DCHPRI11_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI11_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority */ -#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK) -#define DMA_HRS_HRS6_MASK (0x40U) -#define DMA_HRS_HRS6_SHIFT (6U) -/*! HRS6 - Hardware Request Status Channel 6 - * 0b0..A hardware service request for channel 6 is not present - * 0b1..A hardware service request for channel 6 is present +#define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK) + +#define DMA_DCHPRI11_DPA_MASK (0x40U) +#define DMA_DCHPRI11_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK) -#define DMA_HRS_HRS7_MASK (0x80U) -#define DMA_HRS_HRS7_SHIFT (7U) -/*! HRS7 - Hardware Request Status Channel 7 - * 0b0..A hardware service request for channel 7 is not present - * 0b1..A hardware service request for channel 7 is present +#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK) + +#define DMA_DCHPRI11_ECP_MASK (0x80U) +#define DMA_DCHPRI11_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel */ -#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK) -#define DMA_HRS_HRS8_MASK (0x100U) -#define DMA_HRS_HRS8_SHIFT (8U) -/*! HRS8 - Hardware Request Status Channel 8 - * 0b0..A hardware service request for channel 8 is not present - * 0b1..A hardware service request for channel 8 is present +#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI10 - Channel Priority */ +/*! @{ */ + +#define DMA_DCHPRI10_CHPRI_MASK (0xFU) +#define DMA_DCHPRI10_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority */ -#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK) -#define DMA_HRS_HRS9_MASK (0x200U) -#define DMA_HRS_HRS9_SHIFT (9U) -/*! HRS9 - Hardware Request Status Channel 9 - * 0b0..A hardware service request for channel 9 is not present - * 0b1..A hardware service request for channel 9 is present +#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK) + +#define DMA_DCHPRI10_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI10_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority */ -#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK) -#define DMA_HRS_HRS10_MASK (0x400U) -#define DMA_HRS_HRS10_SHIFT (10U) -/*! HRS10 - Hardware Request Status Channel 10 - * 0b0..A hardware service request for channel 10 is not present - * 0b1..A hardware service request for channel 10 is present +#define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK) + +#define DMA_DCHPRI10_DPA_MASK (0x40U) +#define DMA_DCHPRI10_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK) -#define DMA_HRS_HRS11_MASK (0x800U) -#define DMA_HRS_HRS11_SHIFT (11U) -/*! HRS11 - Hardware Request Status Channel 11 - * 0b0..A hardware service request for channel 11 is not present - * 0b1..A hardware service request for channel 11 is present +#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK) + +#define DMA_DCHPRI10_ECP_MASK (0x80U) +#define DMA_DCHPRI10_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel */ -#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK) -#define DMA_HRS_HRS12_MASK (0x1000U) -#define DMA_HRS_HRS12_SHIFT (12U) -/*! HRS12 - Hardware Request Status Channel 12 - * 0b0..A hardware service request for channel 12 is not present - * 0b1..A hardware service request for channel 12 is present +#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI9 - Channel Priority */ +/*! @{ */ + +#define DMA_DCHPRI9_CHPRI_MASK (0xFU) +#define DMA_DCHPRI9_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority */ -#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK) -#define DMA_HRS_HRS13_MASK (0x2000U) -#define DMA_HRS_HRS13_SHIFT (13U) -/*! HRS13 - Hardware Request Status Channel 13 - * 0b0..A hardware service request for channel 13 is not present - * 0b1..A hardware service request for channel 13 is present +#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK) + +#define DMA_DCHPRI9_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI9_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority */ -#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK) -#define DMA_HRS_HRS14_MASK (0x4000U) -#define DMA_HRS_HRS14_SHIFT (14U) -/*! HRS14 - Hardware Request Status Channel 14 - * 0b0..A hardware service request for channel 14 is not present - * 0b1..A hardware service request for channel 14 is present +#define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK) + +#define DMA_DCHPRI9_DPA_MASK (0x40U) +#define DMA_DCHPRI9_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK) -#define DMA_HRS_HRS15_MASK (0x8000U) -#define DMA_HRS_HRS15_SHIFT (15U) -/*! HRS15 - Hardware Request Status Channel 15 - * 0b0..A hardware service request for channel 15 is not present - * 0b1..A hardware service request for channel 15 is present +#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK) + +#define DMA_DCHPRI9_ECP_MASK (0x80U) +#define DMA_DCHPRI9_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel */ -#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK) -#define DMA_HRS_HRS16_MASK (0x10000U) -#define DMA_HRS_HRS16_SHIFT (16U) -/*! HRS16 - Hardware Request Status Channel 16 - * 0b0..A hardware service request for channel 16 is not present - * 0b1..A hardware service request for channel 16 is present +#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI8 - Channel Priority */ +/*! @{ */ + +#define DMA_DCHPRI8_CHPRI_MASK (0xFU) +#define DMA_DCHPRI8_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority */ -#define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK) -#define DMA_HRS_HRS17_MASK (0x20000U) -#define DMA_HRS_HRS17_SHIFT (17U) -/*! HRS17 - Hardware Request Status Channel 17 - * 0b0..A hardware service request for channel 17 is not present - * 0b1..A hardware service request for channel 17 is present +#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK) + +#define DMA_DCHPRI8_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI8_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority */ -#define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK) -#define DMA_HRS_HRS18_MASK (0x40000U) -#define DMA_HRS_HRS18_SHIFT (18U) -/*! HRS18 - Hardware Request Status Channel 18 - * 0b0..A hardware service request for channel 18 is not present - * 0b1..A hardware service request for channel 18 is present +#define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK) + +#define DMA_DCHPRI8_DPA_MASK (0x40U) +#define DMA_DCHPRI8_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK) -#define DMA_HRS_HRS19_MASK (0x80000U) -#define DMA_HRS_HRS19_SHIFT (19U) -/*! HRS19 - Hardware Request Status Channel 19 - * 0b0..A hardware service request for channel 19 is not present - * 0b1..A hardware service request for channel 19 is present +#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK) + +#define DMA_DCHPRI8_ECP_MASK (0x80U) +#define DMA_DCHPRI8_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel */ -#define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK) -#define DMA_HRS_HRS20_MASK (0x100000U) -#define DMA_HRS_HRS20_SHIFT (20U) -/*! HRS20 - Hardware Request Status Channel 20 - * 0b0..A hardware service request for channel 20 is not present - * 0b1..A hardware service request for channel 20 is present +#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI15 - Channel Priority */ +/*! @{ */ + +#define DMA_DCHPRI15_CHPRI_MASK (0xFU) +#define DMA_DCHPRI15_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority */ -#define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK) -#define DMA_HRS_HRS21_MASK (0x200000U) -#define DMA_HRS_HRS21_SHIFT (21U) -/*! HRS21 - Hardware Request Status Channel 21 - * 0b0..A hardware service request for channel 21 is not present - * 0b1..A hardware service request for channel 21 is present +#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK) + +#define DMA_DCHPRI15_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI15_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority */ -#define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK) -#define DMA_HRS_HRS22_MASK (0x400000U) -#define DMA_HRS_HRS22_SHIFT (22U) -/*! HRS22 - Hardware Request Status Channel 22 - * 0b0..A hardware service request for channel 22 is not present - * 0b1..A hardware service request for channel 22 is present +#define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK) + +#define DMA_DCHPRI15_DPA_MASK (0x40U) +#define DMA_DCHPRI15_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK) -#define DMA_HRS_HRS23_MASK (0x800000U) -#define DMA_HRS_HRS23_SHIFT (23U) -/*! HRS23 - Hardware Request Status Channel 23 - * 0b0..A hardware service request for channel 23 is not present - * 0b1..A hardware service request for channel 23 is present +#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK) + +#define DMA_DCHPRI15_ECP_MASK (0x80U) +#define DMA_DCHPRI15_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel */ -#define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK) -#define DMA_HRS_HRS24_MASK (0x1000000U) -#define DMA_HRS_HRS24_SHIFT (24U) -/*! HRS24 - Hardware Request Status Channel 24 - * 0b0..A hardware service request for channel 24 is not present - * 0b1..A hardware service request for channel 24 is present +#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI14 - Channel Priority */ +/*! @{ */ + +#define DMA_DCHPRI14_CHPRI_MASK (0xFU) +#define DMA_DCHPRI14_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority */ -#define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK) -#define DMA_HRS_HRS25_MASK (0x2000000U) -#define DMA_HRS_HRS25_SHIFT (25U) -/*! HRS25 - Hardware Request Status Channel 25 - * 0b0..A hardware service request for channel 25 is not present - * 0b1..A hardware service request for channel 25 is present +#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK) + +#define DMA_DCHPRI14_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI14_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority */ -#define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK) -#define DMA_HRS_HRS26_MASK (0x4000000U) -#define DMA_HRS_HRS26_SHIFT (26U) -/*! HRS26 - Hardware Request Status Channel 26 - * 0b0..A hardware service request for channel 26 is not present - * 0b1..A hardware service request for channel 26 is present +#define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK) + +#define DMA_DCHPRI14_DPA_MASK (0x40U) +#define DMA_DCHPRI14_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK) -#define DMA_HRS_HRS27_MASK (0x8000000U) -#define DMA_HRS_HRS27_SHIFT (27U) -/*! HRS27 - Hardware Request Status Channel 27 - * 0b0..A hardware service request for channel 27 is not present - * 0b1..A hardware service request for channel 27 is present +#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK) + +#define DMA_DCHPRI14_ECP_MASK (0x80U) +#define DMA_DCHPRI14_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel */ -#define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK) -#define DMA_HRS_HRS28_MASK (0x10000000U) -#define DMA_HRS_HRS28_SHIFT (28U) -/*! HRS28 - Hardware Request Status Channel 28 - * 0b0..A hardware service request for channel 28 is not present - * 0b1..A hardware service request for channel 28 is present +#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI13 - Channel Priority */ +/*! @{ */ + +#define DMA_DCHPRI13_CHPRI_MASK (0xFU) +#define DMA_DCHPRI13_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority */ -#define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK) -#define DMA_HRS_HRS29_MASK (0x20000000U) -#define DMA_HRS_HRS29_SHIFT (29U) -/*! HRS29 - Hardware Request Status Channel 29 - * 0b0..A hardware service request for channel 29 is not preset - * 0b1..A hardware service request for channel 29 is present +#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK) + +#define DMA_DCHPRI13_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI13_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority */ -#define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK) -#define DMA_HRS_HRS30_MASK (0x40000000U) -#define DMA_HRS_HRS30_SHIFT (30U) -/*! HRS30 - Hardware Request Status Channel 30 - * 0b0..A hardware service request for channel 30 is not present - * 0b1..A hardware service request for channel 30 is present +#define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK) + +#define DMA_DCHPRI13_DPA_MASK (0x40U) +#define DMA_DCHPRI13_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK) -#define DMA_HRS_HRS31_MASK (0x80000000U) -#define DMA_HRS_HRS31_SHIFT (31U) -/*! HRS31 - Hardware Request Status Channel 31 - * 0b0..A hardware service request for channel 31 is not present - * 0b1..A hardware service request for channel 31 is present +#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK) + +#define DMA_DCHPRI13_ECP_MASK (0x80U) +#define DMA_DCHPRI13_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel */ -#define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK) +#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK) /*! @} */ -/*! @name EARS - Enable Asynchronous Request in Stop */ +/*! @name DCHPRI12 - Channel Priority */ /*! @{ */ -#define DMA_EARS_EDREQ_0_MASK (0x1U) -#define DMA_EARS_EDREQ_0_SHIFT (0U) -/*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0. - * 0b0..Disable asynchronous DMA request for channel 0 - * 0b1..Enable asynchronous DMA request for channel 0 - */ -#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK) -#define DMA_EARS_EDREQ_1_MASK (0x2U) -#define DMA_EARS_EDREQ_1_SHIFT (1U) -/*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1. - * 0b0..Disable asynchronous DMA request for channel 1 - * 0b1..Enable asynchronous DMA request for channel 1 + +#define DMA_DCHPRI12_CHPRI_MASK (0xFU) +#define DMA_DCHPRI12_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority */ -#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK) -#define DMA_EARS_EDREQ_2_MASK (0x4U) -#define DMA_EARS_EDREQ_2_SHIFT (2U) -/*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2. - * 0b0..Disable asynchronous DMA request for channel 2 - * 0b1..Enable asynchronous DMA request for channel 2 +#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK) + +#define DMA_DCHPRI12_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI12_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority */ -#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK) -#define DMA_EARS_EDREQ_3_MASK (0x8U) -#define DMA_EARS_EDREQ_3_SHIFT (3U) -/*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3. - * 0b0..Disable asynchronous DMA request for channel 3 - * 0b1..Enable asynchronous DMA request for channel 3 +#define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK) + +#define DMA_DCHPRI12_DPA_MASK (0x40U) +#define DMA_DCHPRI12_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK) -#define DMA_EARS_EDREQ_4_MASK (0x10U) -#define DMA_EARS_EDREQ_4_SHIFT (4U) -/*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4. - * 0b0..Disable asynchronous DMA request for channel 4 - * 0b1..Enable asynchronous DMA request for channel 4 +#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK) + +#define DMA_DCHPRI12_ECP_MASK (0x80U) +#define DMA_DCHPRI12_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel */ -#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK) -#define DMA_EARS_EDREQ_5_MASK (0x20U) -#define DMA_EARS_EDREQ_5_SHIFT (5U) -/*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5. - * 0b0..Disable asynchronous DMA request for channel 5 - * 0b1..Enable asynchronous DMA request for channel 5 +#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI19 - Channel Priority */ +/*! @{ */ + +#define DMA_DCHPRI19_CHPRI_MASK (0xFU) +#define DMA_DCHPRI19_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority */ -#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK) -#define DMA_EARS_EDREQ_6_MASK (0x40U) -#define DMA_EARS_EDREQ_6_SHIFT (6U) -/*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6. - * 0b0..Disable asynchronous DMA request for channel 6 - * 0b1..Enable asynchronous DMA request for channel 6 +#define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK) + +#define DMA_DCHPRI19_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI19_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority */ -#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK) -#define DMA_EARS_EDREQ_7_MASK (0x80U) -#define DMA_EARS_EDREQ_7_SHIFT (7U) -/*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7. - * 0b0..Disable asynchronous DMA request for channel 7 - * 0b1..Enable asynchronous DMA request for channel 7 +#define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK) + +#define DMA_DCHPRI19_DPA_MASK (0x40U) +#define DMA_DCHPRI19_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK) -#define DMA_EARS_EDREQ_8_MASK (0x100U) -#define DMA_EARS_EDREQ_8_SHIFT (8U) -/*! EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8. - * 0b0..Disable asynchronous DMA request for channel 8 - * 0b1..Enable asynchronous DMA request for channel 8 +#define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK) + +#define DMA_DCHPRI19_ECP_MASK (0x80U) +#define DMA_DCHPRI19_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel */ -#define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK) -#define DMA_EARS_EDREQ_9_MASK (0x200U) -#define DMA_EARS_EDREQ_9_SHIFT (9U) -/*! EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9. - * 0b0..Disable asynchronous DMA request for channel 9 - * 0b1..Enable asynchronous DMA request for channel 9 +#define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI18 - Channel Priority */ +/*! @{ */ + +#define DMA_DCHPRI18_CHPRI_MASK (0xFU) +#define DMA_DCHPRI18_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority */ -#define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK) -#define DMA_EARS_EDREQ_10_MASK (0x400U) -#define DMA_EARS_EDREQ_10_SHIFT (10U) -/*! EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10. - * 0b0..Disable asynchronous DMA request for channel 10 - * 0b1..Enable asynchronous DMA request for channel 10 +#define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK) + +#define DMA_DCHPRI18_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI18_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority */ -#define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK) -#define DMA_EARS_EDREQ_11_MASK (0x800U) -#define DMA_EARS_EDREQ_11_SHIFT (11U) -/*! EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11. - * 0b0..Disable asynchronous DMA request for channel 11 - * 0b1..Enable asynchronous DMA request for channel 11 +#define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK) + +#define DMA_DCHPRI18_DPA_MASK (0x40U) +#define DMA_DCHPRI18_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK) -#define DMA_EARS_EDREQ_12_MASK (0x1000U) -#define DMA_EARS_EDREQ_12_SHIFT (12U) -/*! EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12. - * 0b0..Disable asynchronous DMA request for channel 12 - * 0b1..Enable asynchronous DMA request for channel 12 +#define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK) + +#define DMA_DCHPRI18_ECP_MASK (0x80U) +#define DMA_DCHPRI18_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel */ -#define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK) -#define DMA_EARS_EDREQ_13_MASK (0x2000U) -#define DMA_EARS_EDREQ_13_SHIFT (13U) -/*! EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13. - * 0b0..Disable asynchronous DMA request for channel 13 - * 0b1..Enable asynchronous DMA request for channel 13 +#define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI17 - Channel Priority */ +/*! @{ */ + +#define DMA_DCHPRI17_CHPRI_MASK (0xFU) +#define DMA_DCHPRI17_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority */ -#define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK) -#define DMA_EARS_EDREQ_14_MASK (0x4000U) -#define DMA_EARS_EDREQ_14_SHIFT (14U) -/*! EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14. - * 0b0..Disable asynchronous DMA request for channel 14 - * 0b1..Enable asynchronous DMA request for channel 14 +#define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK) + +#define DMA_DCHPRI17_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI17_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority */ -#define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK) -#define DMA_EARS_EDREQ_15_MASK (0x8000U) -#define DMA_EARS_EDREQ_15_SHIFT (15U) -/*! EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15. - * 0b0..Disable asynchronous DMA request for channel 15 - * 0b1..Enable asynchronous DMA request for channel 15 +#define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK) + +#define DMA_DCHPRI17_DPA_MASK (0x40U) +#define DMA_DCHPRI17_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK) -#define DMA_EARS_EDREQ_16_MASK (0x10000U) -#define DMA_EARS_EDREQ_16_SHIFT (16U) -/*! EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16. - * 0b0..Disable asynchronous DMA request for channel 16 - * 0b1..Enable asynchronous DMA request for channel 16 +#define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK) + +#define DMA_DCHPRI17_ECP_MASK (0x80U) +#define DMA_DCHPRI17_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel */ -#define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK) -#define DMA_EARS_EDREQ_17_MASK (0x20000U) -#define DMA_EARS_EDREQ_17_SHIFT (17U) -/*! EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17. - * 0b0..Disable asynchronous DMA request for channel 17 - * 0b1..Enable asynchronous DMA request for channel 17 +#define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI16 - Channel Priority */ +/*! @{ */ + +#define DMA_DCHPRI16_CHPRI_MASK (0xFU) +#define DMA_DCHPRI16_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority */ -#define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK) -#define DMA_EARS_EDREQ_18_MASK (0x40000U) -#define DMA_EARS_EDREQ_18_SHIFT (18U) -/*! EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18. - * 0b0..Disable asynchronous DMA request for channel 18 - * 0b1..Enable asynchronous DMA request for channel 18 +#define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK) + +#define DMA_DCHPRI16_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI16_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority */ -#define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK) -#define DMA_EARS_EDREQ_19_MASK (0x80000U) -#define DMA_EARS_EDREQ_19_SHIFT (19U) -/*! EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19. - * 0b0..Disable asynchronous DMA request for channel 19 - * 0b1..Enable asynchronous DMA request for channel 19 +#define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK) + +#define DMA_DCHPRI16_DPA_MASK (0x40U) +#define DMA_DCHPRI16_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK) -#define DMA_EARS_EDREQ_20_MASK (0x100000U) -#define DMA_EARS_EDREQ_20_SHIFT (20U) -/*! EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20. - * 0b0..Disable asynchronous DMA request for channel 20 - * 0b1..Enable asynchronous DMA request for channel 20 +#define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK) + +#define DMA_DCHPRI16_ECP_MASK (0x80U) +#define DMA_DCHPRI16_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel */ -#define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK) -#define DMA_EARS_EDREQ_21_MASK (0x200000U) -#define DMA_EARS_EDREQ_21_SHIFT (21U) -/*! EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21. - * 0b0..Disable asynchronous DMA request for channel 21 - * 0b1..Enable asynchronous DMA request for channel 21 +#define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI23 - Channel Priority */ +/*! @{ */ + +#define DMA_DCHPRI23_CHPRI_MASK (0xFU) +#define DMA_DCHPRI23_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority */ -#define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK) -#define DMA_EARS_EDREQ_22_MASK (0x400000U) -#define DMA_EARS_EDREQ_22_SHIFT (22U) -/*! EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22. - * 0b0..Disable asynchronous DMA request for channel 22 - * 0b1..Enable asynchronous DMA request for channel 22 +#define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK) + +#define DMA_DCHPRI23_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI23_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority */ -#define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK) -#define DMA_EARS_EDREQ_23_MASK (0x800000U) -#define DMA_EARS_EDREQ_23_SHIFT (23U) -/*! EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23. - * 0b0..Disable asynchronous DMA request for channel 23 - * 0b1..Enable asynchronous DMA request for channel 23 +#define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK) + +#define DMA_DCHPRI23_DPA_MASK (0x40U) +#define DMA_DCHPRI23_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK) -#define DMA_EARS_EDREQ_24_MASK (0x1000000U) -#define DMA_EARS_EDREQ_24_SHIFT (24U) -/*! EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24. - * 0b0..Disable asynchronous DMA request for channel 24 - * 0b1..Enable asynchronous DMA request for channel 24 +#define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK) + +#define DMA_DCHPRI23_ECP_MASK (0x80U) +#define DMA_DCHPRI23_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel */ -#define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK) -#define DMA_EARS_EDREQ_25_MASK (0x2000000U) -#define DMA_EARS_EDREQ_25_SHIFT (25U) -/*! EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25. - * 0b0..Disable asynchronous DMA request for channel 25 - * 0b1..Enable asynchronous DMA request for channel 25 +#define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI22 - Channel Priority */ +/*! @{ */ + +#define DMA_DCHPRI22_CHPRI_MASK (0xFU) +#define DMA_DCHPRI22_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority */ -#define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK) -#define DMA_EARS_EDREQ_26_MASK (0x4000000U) -#define DMA_EARS_EDREQ_26_SHIFT (26U) -/*! EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26. - * 0b0..Disable asynchronous DMA request for channel 26 - * 0b1..Enable asynchronous DMA request for channel 26 +#define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK) + +#define DMA_DCHPRI22_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI22_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority */ -#define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK) -#define DMA_EARS_EDREQ_27_MASK (0x8000000U) -#define DMA_EARS_EDREQ_27_SHIFT (27U) -/*! EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27. - * 0b0..Disable asynchronous DMA request for channel 27 - * 0b1..Enable asynchronous DMA request for channel 27 +#define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK) + +#define DMA_DCHPRI22_DPA_MASK (0x40U) +#define DMA_DCHPRI22_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK) -#define DMA_EARS_EDREQ_28_MASK (0x10000000U) -#define DMA_EARS_EDREQ_28_SHIFT (28U) -/*! EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28. - * 0b0..Disable asynchronous DMA request for channel 28 - * 0b1..Enable asynchronous DMA request for channel 28 +#define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK) + +#define DMA_DCHPRI22_ECP_MASK (0x80U) +#define DMA_DCHPRI22_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel */ -#define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK) -#define DMA_EARS_EDREQ_29_MASK (0x20000000U) -#define DMA_EARS_EDREQ_29_SHIFT (29U) -/*! EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29. - * 0b0..Disable asynchronous DMA request for channel 29 - * 0b1..Enable asynchronous DMA request for channel 29 +#define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK) +/*! @} */ + +/*! @name DCHPRI21 - Channel Priority */ +/*! @{ */ + +#define DMA_DCHPRI21_CHPRI_MASK (0xFU) +#define DMA_DCHPRI21_CHPRI_SHIFT (0U) +/*! CHPRI - Channel n Arbitration Priority */ -#define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK) -#define DMA_EARS_EDREQ_30_MASK (0x40000000U) -#define DMA_EARS_EDREQ_30_SHIFT (30U) -/*! EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30. - * 0b0..Disable asynchronous DMA request for channel 30 - * 0b1..Enable asynchronous DMA request for channel 30 +#define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK) + +#define DMA_DCHPRI21_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI21_GRPPRI_SHIFT (4U) +/*! GRPPRI - Channel n Current Group Priority */ -#define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK) -#define DMA_EARS_EDREQ_31_MASK (0x80000000U) -#define DMA_EARS_EDREQ_31_SHIFT (31U) -/*! EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31. - * 0b0..Disable asynchronous DMA request for channel 31 - * 0b1..Enable asynchronous DMA request for channel 31 +#define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK) + +#define DMA_DCHPRI21_DPA_MASK (0x40U) +#define DMA_DCHPRI21_DPA_SHIFT (6U) +/*! DPA - Disable Preempt Ability. This field resets to 0. + * 0b0..Channel n can suspend a lower priority channel + * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK) +#define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK) + +#define DMA_DCHPRI21_ECP_MASK (0x80U) +#define DMA_DCHPRI21_ECP_SHIFT (7U) +/*! ECP - Enable Channel Preemption. This field resets to 0. + * 0b0..Channel n cannot be suspended by a higher priority channel's service request + * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + */ +#define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK) /*! @} */ -/*! @name DCHPRI3 - Channel Priority */ +/*! @name DCHPRI20 - Channel Priority */ /*! @{ */ -#define DMA_DCHPRI3_CHPRI_MASK (0xFU) -#define DMA_DCHPRI3_CHPRI_SHIFT (0U) + +#define DMA_DCHPRI20_CHPRI_MASK (0xFU) +#define DMA_DCHPRI20_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ -#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK) -#define DMA_DCHPRI3_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI3_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK) + +#define DMA_DCHPRI20_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI20_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ -#define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK) -#define DMA_DCHPRI3_DPA_MASK (0x40U) -#define DMA_DCHPRI3_DPA_SHIFT (6U) +#define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK) + +#define DMA_DCHPRI20_DPA_MASK (0x40U) +#define DMA_DCHPRI20_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK) -#define DMA_DCHPRI3_ECP_MASK (0x80U) -#define DMA_DCHPRI3_ECP_SHIFT (7U) +#define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK) + +#define DMA_DCHPRI20_ECP_MASK (0x80U) +#define DMA_DCHPRI20_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel */ -#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK) +#define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK) /*! @} */ -/*! @name DCHPRI2 - Channel Priority */ +/*! @name DCHPRI27 - Channel Priority */ /*! @{ */ -#define DMA_DCHPRI2_CHPRI_MASK (0xFU) -#define DMA_DCHPRI2_CHPRI_SHIFT (0U) + +#define DMA_DCHPRI27_CHPRI_MASK (0xFU) +#define DMA_DCHPRI27_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ -#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK) -#define DMA_DCHPRI2_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI2_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK) + +#define DMA_DCHPRI27_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI27_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ -#define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK) -#define DMA_DCHPRI2_DPA_MASK (0x40U) -#define DMA_DCHPRI2_DPA_SHIFT (6U) +#define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK) + +#define DMA_DCHPRI27_DPA_MASK (0x40U) +#define DMA_DCHPRI27_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK) -#define DMA_DCHPRI2_ECP_MASK (0x80U) -#define DMA_DCHPRI2_ECP_SHIFT (7U) +#define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK) + +#define DMA_DCHPRI27_ECP_MASK (0x80U) +#define DMA_DCHPRI27_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel */ -#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK) +#define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK) /*! @} */ -/*! @name DCHPRI1 - Channel Priority */ +/*! @name DCHPRI26 - Channel Priority */ /*! @{ */ -#define DMA_DCHPRI1_CHPRI_MASK (0xFU) -#define DMA_DCHPRI1_CHPRI_SHIFT (0U) + +#define DMA_DCHPRI26_CHPRI_MASK (0xFU) +#define DMA_DCHPRI26_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ -#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK) -#define DMA_DCHPRI1_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI1_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK) + +#define DMA_DCHPRI26_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI26_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ -#define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK) -#define DMA_DCHPRI1_DPA_MASK (0x40U) -#define DMA_DCHPRI1_DPA_SHIFT (6U) +#define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK) + +#define DMA_DCHPRI26_DPA_MASK (0x40U) +#define DMA_DCHPRI26_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK) -#define DMA_DCHPRI1_ECP_MASK (0x80U) -#define DMA_DCHPRI1_ECP_SHIFT (7U) +#define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK) + +#define DMA_DCHPRI26_ECP_MASK (0x80U) +#define DMA_DCHPRI26_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel */ -#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK) +#define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK) /*! @} */ -/*! @name DCHPRI0 - Channel Priority */ +/*! @name DCHPRI25 - Channel Priority */ /*! @{ */ -#define DMA_DCHPRI0_CHPRI_MASK (0xFU) -#define DMA_DCHPRI0_CHPRI_SHIFT (0U) + +#define DMA_DCHPRI25_CHPRI_MASK (0xFU) +#define DMA_DCHPRI25_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ -#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK) -#define DMA_DCHPRI0_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI0_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK) + +#define DMA_DCHPRI25_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI25_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ -#define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK) -#define DMA_DCHPRI0_DPA_MASK (0x40U) -#define DMA_DCHPRI0_DPA_SHIFT (6U) +#define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK) + +#define DMA_DCHPRI25_DPA_MASK (0x40U) +#define DMA_DCHPRI25_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK) -#define DMA_DCHPRI0_ECP_MASK (0x80U) -#define DMA_DCHPRI0_ECP_SHIFT (7U) +#define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK) + +#define DMA_DCHPRI25_ECP_MASK (0x80U) +#define DMA_DCHPRI25_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel */ -#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK) +#define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK) /*! @} */ -/*! @name DCHPRI7 - Channel Priority */ +/*! @name DCHPRI24 - Channel Priority */ /*! @{ */ -#define DMA_DCHPRI7_CHPRI_MASK (0xFU) -#define DMA_DCHPRI7_CHPRI_SHIFT (0U) + +#define DMA_DCHPRI24_CHPRI_MASK (0xFU) +#define DMA_DCHPRI24_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ -#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK) -#define DMA_DCHPRI7_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI7_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK) + +#define DMA_DCHPRI24_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI24_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ -#define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK) -#define DMA_DCHPRI7_DPA_MASK (0x40U) -#define DMA_DCHPRI7_DPA_SHIFT (6U) +#define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK) + +#define DMA_DCHPRI24_DPA_MASK (0x40U) +#define DMA_DCHPRI24_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK) -#define DMA_DCHPRI7_ECP_MASK (0x80U) -#define DMA_DCHPRI7_ECP_SHIFT (7U) +#define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK) + +#define DMA_DCHPRI24_ECP_MASK (0x80U) +#define DMA_DCHPRI24_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel */ -#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK) +#define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK) /*! @} */ -/*! @name DCHPRI6 - Channel Priority */ +/*! @name DCHPRI31 - Channel Priority */ /*! @{ */ -#define DMA_DCHPRI6_CHPRI_MASK (0xFU) -#define DMA_DCHPRI6_CHPRI_SHIFT (0U) + +#define DMA_DCHPRI31_CHPRI_MASK (0xFU) +#define DMA_DCHPRI31_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ -#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK) -#define DMA_DCHPRI6_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI6_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK) + +#define DMA_DCHPRI31_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI31_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ -#define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK) -#define DMA_DCHPRI6_DPA_MASK (0x40U) -#define DMA_DCHPRI6_DPA_SHIFT (6U) +#define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK) + +#define DMA_DCHPRI31_DPA_MASK (0x40U) +#define DMA_DCHPRI31_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK) -#define DMA_DCHPRI6_ECP_MASK (0x80U) -#define DMA_DCHPRI6_ECP_SHIFT (7U) +#define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK) + +#define DMA_DCHPRI31_ECP_MASK (0x80U) +#define DMA_DCHPRI31_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel */ -#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK) +#define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK) /*! @} */ -/*! @name DCHPRI5 - Channel Priority */ +/*! @name DCHPRI30 - Channel Priority */ /*! @{ */ -#define DMA_DCHPRI5_CHPRI_MASK (0xFU) -#define DMA_DCHPRI5_CHPRI_SHIFT (0U) + +#define DMA_DCHPRI30_CHPRI_MASK (0xFU) +#define DMA_DCHPRI30_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ -#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK) -#define DMA_DCHPRI5_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI5_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK) + +#define DMA_DCHPRI30_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI30_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ -#define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK) -#define DMA_DCHPRI5_DPA_MASK (0x40U) -#define DMA_DCHPRI5_DPA_SHIFT (6U) +#define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK) + +#define DMA_DCHPRI30_DPA_MASK (0x40U) +#define DMA_DCHPRI30_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK) -#define DMA_DCHPRI5_ECP_MASK (0x80U) -#define DMA_DCHPRI5_ECP_SHIFT (7U) +#define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK) + +#define DMA_DCHPRI30_ECP_MASK (0x80U) +#define DMA_DCHPRI30_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel */ -#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK) +#define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK) /*! @} */ -/*! @name DCHPRI4 - Channel Priority */ +/*! @name DCHPRI29 - Channel Priority */ /*! @{ */ -#define DMA_DCHPRI4_CHPRI_MASK (0xFU) -#define DMA_DCHPRI4_CHPRI_SHIFT (0U) + +#define DMA_DCHPRI29_CHPRI_MASK (0xFU) +#define DMA_DCHPRI29_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ -#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK) -#define DMA_DCHPRI4_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI4_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK) + +#define DMA_DCHPRI29_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI29_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ -#define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK) -#define DMA_DCHPRI4_DPA_MASK (0x40U) -#define DMA_DCHPRI4_DPA_SHIFT (6U) +#define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK) + +#define DMA_DCHPRI29_DPA_MASK (0x40U) +#define DMA_DCHPRI29_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK) -#define DMA_DCHPRI4_ECP_MASK (0x80U) -#define DMA_DCHPRI4_ECP_SHIFT (7U) +#define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK) + +#define DMA_DCHPRI29_ECP_MASK (0x80U) +#define DMA_DCHPRI29_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel */ -#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK) +#define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK) /*! @} */ -/*! @name DCHPRI11 - Channel Priority */ +/*! @name DCHPRI28 - Channel Priority */ /*! @{ */ -#define DMA_DCHPRI11_CHPRI_MASK (0xFU) -#define DMA_DCHPRI11_CHPRI_SHIFT (0U) + +#define DMA_DCHPRI28_CHPRI_MASK (0xFU) +#define DMA_DCHPRI28_CHPRI_SHIFT (0U) /*! CHPRI - Channel n Arbitration Priority */ -#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK) -#define DMA_DCHPRI11_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI11_GRPPRI_SHIFT (4U) +#define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK) + +#define DMA_DCHPRI28_GRPPRI_MASK (0x30U) +#define DMA_DCHPRI28_GRPPRI_SHIFT (4U) /*! GRPPRI - Channel n Current Group Priority */ -#define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK) -#define DMA_DCHPRI11_DPA_MASK (0x40U) -#define DMA_DCHPRI11_DPA_SHIFT (6U) +#define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK) + +#define DMA_DCHPRI28_DPA_MASK (0x40U) +#define DMA_DCHPRI28_DPA_SHIFT (6U) /*! DPA - Disable Preempt Ability. This field resets to 0. * 0b0..Channel n can suspend a lower priority channel * 0b1..Channel n cannot suspend any channel, regardless of channel priority */ -#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK) -#define DMA_DCHPRI11_ECP_MASK (0x80U) -#define DMA_DCHPRI11_ECP_SHIFT (7U) +#define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK) + +#define DMA_DCHPRI28_ECP_MASK (0x80U) +#define DMA_DCHPRI28_ECP_SHIFT (7U) /*! ECP - Enable Channel Preemption. This field resets to 0. * 0b0..Channel n cannot be suspended by a higher priority channel's service request * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel */ -#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK) +#define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK) +/*! @} */ + +/*! @name SADDR - TCD Source Address */ +/*! @{ */ + +#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU) +#define DMA_SADDR_SADDR_SHIFT (0U) +/*! SADDR - Source Address + */ +#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK) +/*! @} */ + +/* The count of DMA_SADDR */ +#define DMA_SADDR_COUNT (32U) + +/*! @name SOFF - TCD Signed Source Address Offset */ +/*! @{ */ + +#define DMA_SOFF_SOFF_MASK (0xFFFFU) +#define DMA_SOFF_SOFF_SHIFT (0U) +/*! SOFF - Source address signed offset + */ +#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK) +/*! @} */ + +/* The count of DMA_SOFF */ +#define DMA_SOFF_COUNT (32U) + +/*! @name ATTR - TCD Transfer Attributes */ +/*! @{ */ + +#define DMA_ATTR_DSIZE_MASK (0x7U) +#define DMA_ATTR_DSIZE_SHIFT (0U) +/*! DSIZE - Destination data transfer size + */ +#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK) + +#define DMA_ATTR_DMOD_MASK (0xF8U) +#define DMA_ATTR_DMOD_SHIFT (3U) +/*! DMOD - Destination Address Modulo + */ +#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK) + +#define DMA_ATTR_SSIZE_MASK (0x700U) +#define DMA_ATTR_SSIZE_SHIFT (8U) +/*! SSIZE - Source data transfer size + * 0b000..8-bit + * 0b001..16-bit + * 0b010..32-bit + * 0b011..64-bit + * 0b100..Reserved + * 0b101..32-byte burst (4 beats of 64 bits) + * 0b110..Reserved + * 0b111..Reserved + */ +#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK) + +#define DMA_ATTR_SMOD_MASK (0xF800U) +#define DMA_ATTR_SMOD_SHIFT (11U) +/*! SMOD - Source Address Modulo + * 0b00000..Source address modulo feature is disabled + * 0b00001-0b11111..Value defines address range used to set up circular data queue + */ +#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK) +/*! @} */ + +/* The count of DMA_ATTR */ +#define DMA_ATTR_COUNT (32U) + +/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */ +/*! @{ */ + +#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU) +#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U) +/*! NBYTES - Minor Byte Transfer Count + */ +#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK) +/*! @} */ + +/* The count of DMA_NBYTES_MLNO */ +#define DMA_NBYTES_MLNO_COUNT (32U) + +/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */ +/*! @{ */ + +#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) +#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) +/*! NBYTES - Minor Byte Transfer Count + */ +#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) + +#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) +#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset Enable + * 0b0..The minor loop offset is not applied to the DADDR + * 0b1..The minor loop offset is applied to the DADDR + */ +#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) + +#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) +#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..The minor loop offset is not applied to the SADDR + * 0b1..The minor loop offset is applied to the SADDR + */ +#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) +/*! @} */ + +/* The count of DMA_NBYTES_MLOFFNO */ +#define DMA_NBYTES_MLOFFNO_COUNT (32U) + +/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */ +/*! @{ */ + +#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) +#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) +/*! NBYTES - Minor Byte Transfer Count + */ +#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) + +#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) +#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) +/*! MLOFF - If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the + * source or destination address to form the next-state value after the minor loop completes. + */ +#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) + +#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) +#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) +/*! DMLOE - Destination Minor Loop Offset Enable + * 0b0..The minor loop offset is not applied to the DADDR + * 0b1..The minor loop offset is applied to the DADDR + */ +#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) + +#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) +#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) +/*! SMLOE - Source Minor Loop Offset Enable + * 0b0..The minor loop offset is not applied to the SADDR + * 0b1..The minor loop offset is applied to the SADDR + */ +#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) +/*! @} */ + +/* The count of DMA_NBYTES_MLOFFYES */ +#define DMA_NBYTES_MLOFFYES_COUNT (32U) + +/*! @name SLAST - TCD Last Source Address Adjustment */ +/*! @{ */ + +#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU) +#define DMA_SLAST_SLAST_SHIFT (0U) +/*! SLAST - Last Source Address Adjustment + */ +#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK) +/*! @} */ + +/* The count of DMA_SLAST */ +#define DMA_SLAST_COUNT (32U) + +/*! @name DADDR - TCD Destination Address */ +/*! @{ */ + +#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU) +#define DMA_DADDR_DADDR_SHIFT (0U) +/*! DADDR - Destination Address + */ +#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK) /*! @} */ -/*! @name DCHPRI10 - Channel Priority */ +/* The count of DMA_DADDR */ +#define DMA_DADDR_COUNT (32U) + +/*! @name DOFF - TCD Signed Destination Address Offset */ /*! @{ */ -#define DMA_DCHPRI10_CHPRI_MASK (0xFU) -#define DMA_DCHPRI10_CHPRI_SHIFT (0U) -/*! CHPRI - Channel n Arbitration Priority - */ -#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK) -#define DMA_DCHPRI10_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI10_GRPPRI_SHIFT (4U) -/*! GRPPRI - Channel n Current Group Priority - */ -#define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK) -#define DMA_DCHPRI10_DPA_MASK (0x40U) -#define DMA_DCHPRI10_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel - * 0b1..Channel n cannot suspend any channel, regardless of channel priority - */ -#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK) -#define DMA_DCHPRI10_ECP_MASK (0x80U) -#define DMA_DCHPRI10_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + +#define DMA_DOFF_DOFF_MASK (0xFFFFU) +#define DMA_DOFF_DOFF_SHIFT (0U) +/*! DOFF - Destination Address Signed Offset */ -#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK) +#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK) /*! @} */ -/*! @name DCHPRI9 - Channel Priority */ +/* The count of DMA_DOFF */ +#define DMA_DOFF_COUNT (32U) + +/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ /*! @{ */ -#define DMA_DCHPRI9_CHPRI_MASK (0xFU) -#define DMA_DCHPRI9_CHPRI_SHIFT (0U) -/*! CHPRI - Channel n Arbitration Priority - */ -#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK) -#define DMA_DCHPRI9_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI9_GRPPRI_SHIFT (4U) -/*! GRPPRI - Channel n Current Group Priority - */ -#define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK) -#define DMA_DCHPRI9_DPA_MASK (0x40U) -#define DMA_DCHPRI9_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel - * 0b1..Channel n cannot suspend any channel, regardless of channel priority + +#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) +#define DMA_CITER_ELINKNO_CITER_SHIFT (0U) +/*! CITER - Current Major Iteration Count */ -#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK) -#define DMA_DCHPRI9_ECP_MASK (0x80U) -#define DMA_DCHPRI9_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel +#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK) + +#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enable channel-to-channel linking on minor-loop complete + * 0b0..Channel-to-channel linking is disabled + * 0b1..Channel-to-channel linking is enabled */ -#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK) +#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK) /*! @} */ -/*! @name DCHPRI8 - Channel Priority */ +/* The count of DMA_CITER_ELINKNO */ +#define DMA_CITER_ELINKNO_COUNT (32U) + +/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ /*! @{ */ -#define DMA_DCHPRI8_CHPRI_MASK (0xFU) -#define DMA_DCHPRI8_CHPRI_SHIFT (0U) -/*! CHPRI - Channel n Arbitration Priority - */ -#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK) -#define DMA_DCHPRI8_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI8_GRPPRI_SHIFT (4U) -/*! GRPPRI - Channel n Current Group Priority + +#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) +#define DMA_CITER_ELINKYES_CITER_SHIFT (0U) +/*! CITER - Current Major Iteration Count */ -#define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK) -#define DMA_DCHPRI8_DPA_MASK (0x40U) -#define DMA_DCHPRI8_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel - * 0b1..Channel n cannot suspend any channel, regardless of channel priority +#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK) + +#define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U) +#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U) +/*! LINKCH - Minor Loop Link Channel Number */ -#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK) -#define DMA_DCHPRI8_ECP_MASK (0x80U) -#define DMA_DCHPRI8_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel +#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK) + +#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enable channel-to-channel linking on minor-loop complete + * 0b0..Channel-to-channel linking is disabled + * 0b1..Channel-to-channel linking is enabled */ -#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK) +#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK) /*! @} */ -/*! @name DCHPRI15 - Channel Priority */ +/* The count of DMA_CITER_ELINKYES */ +#define DMA_CITER_ELINKYES_COUNT (32U) + +/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */ /*! @{ */ -#define DMA_DCHPRI15_CHPRI_MASK (0xFU) -#define DMA_DCHPRI15_CHPRI_SHIFT (0U) -/*! CHPRI - Channel n Arbitration Priority - */ -#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK) -#define DMA_DCHPRI15_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI15_GRPPRI_SHIFT (4U) -/*! GRPPRI - Channel n Current Group Priority - */ -#define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK) -#define DMA_DCHPRI15_DPA_MASK (0x40U) -#define DMA_DCHPRI15_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel - * 0b1..Channel n cannot suspend any channel, regardless of channel priority - */ -#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK) -#define DMA_DCHPRI15_ECP_MASK (0x80U) -#define DMA_DCHPRI15_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + +#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU) +#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U) +/*! DLASTSGA - Destination last address adjustment, or next memory address TCD for channel (scatter/gather) */ -#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK) +#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK) /*! @} */ -/*! @name DCHPRI14 - Channel Priority */ +/* The count of DMA_DLAST_SGA */ +#define DMA_DLAST_SGA_COUNT (32U) + +/*! @name CSR - TCD Control and Status */ /*! @{ */ -#define DMA_DCHPRI14_CHPRI_MASK (0xFU) -#define DMA_DCHPRI14_CHPRI_SHIFT (0U) -/*! CHPRI - Channel n Arbitration Priority + +#define DMA_CSR_START_MASK (0x1U) +#define DMA_CSR_START_SHIFT (0U) +/*! START - Channel Start + * 0b0..Channel is not explicitly started + * 0b1..Channel is explicitly started via a software initiated service request */ -#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK) -#define DMA_DCHPRI14_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI14_GRPPRI_SHIFT (4U) -/*! GRPPRI - Channel n Current Group Priority +#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK) + +#define DMA_CSR_INTMAJOR_MASK (0x2U) +#define DMA_CSR_INTMAJOR_SHIFT (1U) +/*! INTMAJOR - Enable an interrupt when major iteration count completes. + * 0b0..End of major loop interrupt is disabled + * 0b1..End of major loop interrupt is enabled */ -#define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK) -#define DMA_DCHPRI14_DPA_MASK (0x40U) -#define DMA_DCHPRI14_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel - * 0b1..Channel n cannot suspend any channel, regardless of channel priority +#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK) + +#define DMA_CSR_INTHALF_MASK (0x4U) +#define DMA_CSR_INTHALF_SHIFT (2U) +/*! INTHALF - Enable an interrupt when major counter is half complete. + * 0b0..Half-point interrupt is disabled + * 0b1..Half-point interrupt is enabled */ -#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK) -#define DMA_DCHPRI14_ECP_MASK (0x80U) -#define DMA_DCHPRI14_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel +#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK) + +#define DMA_CSR_DREQ_MASK (0x8U) +#define DMA_CSR_DREQ_SHIFT (3U) +/*! DREQ - Disable Request + * 0b0..The channel's ERQ field is not affected + * 0b1..The channel's ERQ field value changes to 0 when the major loop is complete */ -#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK) -/*! @} */ +#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK) -/*! @name DCHPRI13 - Channel Priority */ -/*! @{ */ -#define DMA_DCHPRI13_CHPRI_MASK (0xFU) -#define DMA_DCHPRI13_CHPRI_SHIFT (0U) -/*! CHPRI - Channel n Arbitration Priority +#define DMA_CSR_ESG_MASK (0x10U) +#define DMA_CSR_ESG_SHIFT (4U) +/*! ESG - Enable Scatter/Gather Processing + * 0b0..The current channel's TCD is normal format + * 0b1..The current channel's TCD specifies a scatter gather format */ -#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK) -#define DMA_DCHPRI13_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI13_GRPPRI_SHIFT (4U) -/*! GRPPRI - Channel n Current Group Priority +#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK) + +#define DMA_CSR_MAJORELINK_MASK (0x20U) +#define DMA_CSR_MAJORELINK_SHIFT (5U) +/*! MAJORELINK - Enable channel-to-channel linking on major loop complete + * 0b0..Channel-to-channel linking is disabled + * 0b1..Channel-to-channel linking is enabled */ -#define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK) -#define DMA_DCHPRI13_DPA_MASK (0x40U) -#define DMA_DCHPRI13_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel - * 0b1..Channel n cannot suspend any channel, regardless of channel priority +#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK) + +#define DMA_CSR_ACTIVE_MASK (0x40U) +#define DMA_CSR_ACTIVE_SHIFT (6U) +/*! ACTIVE - Channel Active */ -#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK) -#define DMA_DCHPRI13_ECP_MASK (0x80U) -#define DMA_DCHPRI13_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel +#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK) + +#define DMA_CSR_DONE_MASK (0x80U) +#define DMA_CSR_DONE_SHIFT (7U) +/*! DONE - Channel Done */ -#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK) -/*! @} */ +#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK) -/*! @name DCHPRI12 - Channel Priority */ -/*! @{ */ -#define DMA_DCHPRI12_CHPRI_MASK (0xFU) -#define DMA_DCHPRI12_CHPRI_SHIFT (0U) -/*! CHPRI - Channel n Arbitration Priority +#define DMA_CSR_MAJORLINKCH_MASK (0x1F00U) +#define DMA_CSR_MAJORLINKCH_SHIFT (8U) +/*! MAJORLINKCH - Major Loop Link Channel Number */ -#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK) -#define DMA_DCHPRI12_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI12_GRPPRI_SHIFT (4U) -/*! GRPPRI - Channel n Current Group Priority +#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK) + +#define DMA_CSR_BWC_MASK (0xC000U) +#define DMA_CSR_BWC_SHIFT (14U) +/*! BWC - Bandwidth Control + * 0b00..No eDMA engine stalls + * 0b01..Reserved + * 0b10..eDMA engine stalls for 4 cycles after each R/W + * 0b11..eDMA engine stalls for 8 cycles after each R/W */ -#define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK) -#define DMA_DCHPRI12_DPA_MASK (0x40U) -#define DMA_DCHPRI12_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel - * 0b1..Channel n cannot suspend any channel, regardless of channel priority +#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK) +/*! @} */ + +/* The count of DMA_CSR */ +#define DMA_CSR_COUNT (32U) + +/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ +/*! @{ */ + +#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) +#define DMA_BITER_ELINKNO_BITER_SHIFT (0U) +/*! BITER - Starting Major Iteration Count */ -#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK) -#define DMA_DCHPRI12_ECP_MASK (0x80U) -#define DMA_DCHPRI12_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel +#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK) + +#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U) +#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U) +/*! ELINK - Enables channel-to-channel linking on minor loop complete + * 0b0..Channel-to-channel linking is disabled + * 0b1..Channel-to-channel linking is enabled */ -#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK) +#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK) /*! @} */ -/*! @name DCHPRI19 - Channel Priority */ +/* The count of DMA_BITER_ELINKNO */ +#define DMA_BITER_ELINKNO_COUNT (32U) + +/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ /*! @{ */ -#define DMA_DCHPRI19_CHPRI_MASK (0xFU) -#define DMA_DCHPRI19_CHPRI_SHIFT (0U) -/*! CHPRI - Channel n Arbitration Priority - */ -#define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK) -#define DMA_DCHPRI19_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI19_GRPPRI_SHIFT (4U) -/*! GRPPRI - Channel n Current Group Priority + +#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU) +#define DMA_BITER_ELINKYES_BITER_SHIFT (0U) +/*! BITER - Starting major iteration count */ -#define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK) -#define DMA_DCHPRI19_DPA_MASK (0x40U) -#define DMA_DCHPRI19_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel - * 0b1..Channel n cannot suspend any channel, regardless of channel priority +#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK) + +#define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U) +#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U) +/*! LINKCH - Link Channel Number */ -#define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK) -#define DMA_DCHPRI19_ECP_MASK (0x80U) -#define DMA_DCHPRI19_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel +#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK) + +#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) +#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U) +/*! ELINK - Enables channel-to-channel linking on minor loop complete + * 0b0..Channel-to-channel linking is disabled + * 0b1..Channel-to-channel linking is enabled */ -#define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK) +#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK) /*! @} */ -/*! @name DCHPRI18 - Channel Priority */ +/* The count of DMA_BITER_ELINKYES */ +#define DMA_BITER_ELINKYES_COUNT (32U) + + +/*! + * @} + */ /* end of group DMA_Register_Masks */ + + +/* DMA - Peripheral instance base addresses */ +/** Peripheral DMA0 base address */ +#define DMA0_BASE (0x40070000u) +/** Peripheral DMA0 base pointer */ +#define DMA0 ((DMA_Type *)DMA0_BASE) +/** Array initializer of DMA peripheral base addresses */ +#define DMA_BASE_ADDRS { DMA0_BASE } +/** Array initializer of DMA peripheral base pointers */ +#define DMA_BASE_PTRS { DMA0 } +/** Interrupt vectors for the DMA peripheral type */ +#define DMA_CHN_IRQS { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } } +#define DMA_ERROR_IRQS { DMA_ERROR_IRQn } + +/*! + * @} + */ /* end of group DMA_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DMAMUX Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer + * @{ + */ + +/** DMAMUX - Register Layout Typedef */ +typedef struct { + __IO uint32_t CHCFG[32]; /**< Channel 0 Configuration Register..Channel 31 Configuration Register, array offset: 0x0, array step: 0x4 */ +} DMAMUX_Type; + +/* ---------------------------------------------------------------------------- + -- DMAMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks + * @{ + */ + +/*! @name CHCFG - Channel 0 Configuration Register..Channel 31 Configuration Register */ /*! @{ */ -#define DMA_DCHPRI18_CHPRI_MASK (0xFU) -#define DMA_DCHPRI18_CHPRI_SHIFT (0U) -/*! CHPRI - Channel n Arbitration Priority + +#define DMAMUX_CHCFG_SOURCE_MASK (0xFFU) +#define DMAMUX_CHCFG_SOURCE_SHIFT (0U) +/*! SOURCE - DMA Channel Source (Slot Number) */ -#define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK) -#define DMA_DCHPRI18_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI18_GRPPRI_SHIFT (4U) -/*! GRPPRI - Channel n Current Group Priority +#define DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) + +#define DMAMUX_CHCFG_A_ON_MASK (0x20000000U) +#define DMAMUX_CHCFG_A_ON_SHIFT (29U) +/*! A_ON - DMA Channel Always Enable + * 0b0..DMA Channel Always ON function is disabled + * 0b1..DMA Channel Always ON function is enabled */ -#define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK) -#define DMA_DCHPRI18_DPA_MASK (0x40U) -#define DMA_DCHPRI18_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel - * 0b1..Channel n cannot suspend any channel, regardless of channel priority +#define DMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK) + +#define DMAMUX_CHCFG_TRIG_MASK (0x40000000U) +#define DMAMUX_CHCFG_TRIG_SHIFT (30U) +/*! TRIG - DMA Channel Trigger Enable + * 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the + * specified source to the DMA channel. (Normal mode) + * 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. */ -#define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK) -#define DMA_DCHPRI18_ECP_MASK (0x80U) -#define DMA_DCHPRI18_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel +#define DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) + +#define DMAMUX_CHCFG_ENBL_MASK (0x80000000U) +#define DMAMUX_CHCFG_ENBL_SHIFT (31U) +/*! ENBL - DMA Mux Channel Enable + * 0b0..DMA Mux channel is disabled + * 0b1..DMA Mux channel is enabled */ -#define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK) +#define DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) /*! @} */ -/*! @name DCHPRI17 - Channel Priority */ -/*! @{ */ -#define DMA_DCHPRI17_CHPRI_MASK (0xFU) -#define DMA_DCHPRI17_CHPRI_SHIFT (0U) -/*! CHPRI - Channel n Arbitration Priority - */ -#define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK) -#define DMA_DCHPRI17_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI17_GRPPRI_SHIFT (4U) -/*! GRPPRI - Channel n Current Group Priority +/* The count of DMAMUX_CHCFG */ +#define DMAMUX_CHCFG_COUNT (32U) + + +/*! + * @} + */ /* end of group DMAMUX_Register_Masks */ + + +/* DMAMUX - Peripheral instance base addresses */ +/** Peripheral DMAMUX0 base address */ +#define DMAMUX0_BASE (0x40074000u) +/** Peripheral DMAMUX0 base pointer */ +#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE) +/** Array initializer of DMAMUX peripheral base addresses */ +#define DMAMUX_BASE_ADDRS { DMAMUX0_BASE } +/** Array initializer of DMAMUX peripheral base pointers */ +#define DMAMUX_BASE_PTRS { DMAMUX0 } + +/*! + * @} + */ /* end of group DMAMUX_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DSI_HOST Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DSI_HOST_Peripheral_Access_Layer DSI_HOST Peripheral Access Layer + * @{ */ -#define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK) -#define DMA_DCHPRI17_DPA_MASK (0x40U) -#define DMA_DCHPRI17_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel - * 0b1..Channel n cannot suspend any channel, regardless of channel priority + +/** DSI_HOST - Register Layout Typedef */ +typedef struct { + __IO uint32_t CFG_NUM_LANES; /**< , offset: 0x0 */ + __IO uint32_t CFG_NONCONTINUOUS_CLK; /**< , offset: 0x4 */ + __IO uint32_t CFG_T_PRE; /**< , offset: 0x8 */ + __IO uint32_t CFG_T_POST; /**< , offset: 0xC */ + __IO uint32_t CFG_TX_GAP; /**< , offset: 0x10 */ + __IO uint32_t CFG_AUTOINSERT_EOTP; /**< , offset: 0x14 */ + __IO uint32_t CFG_EXTRA_CMDS_AFTER_EOTP; /**< , offset: 0x18 */ + __IO uint32_t CFG_HTX_TO_COUNT; /**< , offset: 0x1C */ + __IO uint32_t CFG_LRX_H_TO_COUNT; /**< , offset: 0x20 */ + __IO uint32_t CFG_BTA_H_TO_COUNT; /**< , offset: 0x24 */ + __IO uint32_t CFG_TWAKEUP; /**< , offset: 0x28 */ + __I uint32_t CFG_STATUS_OUT; /**< , offset: 0x2C */ + __I uint32_t RX_ERROR_STATUS; /**< , offset: 0x30 */ +} DSI_HOST_Type; + +/* ---------------------------------------------------------------------------- + -- DSI_HOST Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DSI_HOST_Register_Masks DSI_HOST Register Masks + * @{ */ -#define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK) -#define DMA_DCHPRI17_ECP_MASK (0x80U) -#define DMA_DCHPRI17_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + +/*! @name CFG_NUM_LANES - */ +/*! @{ */ + +#define DSI_HOST_CFG_NUM_LANES_NUM_LANES_MASK (0x3U) +#define DSI_HOST_CFG_NUM_LANES_NUM_LANES_SHIFT (0U) +/*! NUM_LANES - Sets the number of active lanes that are to be used for transmitting data. + * 0b00..1 lane + * 0b01..2 lanes */ -#define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK) +#define DSI_HOST_CFG_NUM_LANES_NUM_LANES(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_NUM_LANES_NUM_LANES_SHIFT)) & DSI_HOST_CFG_NUM_LANES_NUM_LANES_MASK) /*! @} */ -/*! @name DCHPRI16 - Channel Priority */ +/*! @name CFG_NONCONTINUOUS_CLK - */ /*! @{ */ -#define DMA_DCHPRI16_CHPRI_MASK (0xFU) -#define DMA_DCHPRI16_CHPRI_SHIFT (0U) -/*! CHPRI - Channel n Arbitration Priority - */ -#define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK) -#define DMA_DCHPRI16_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI16_GRPPRI_SHIFT (4U) -/*! GRPPRI - Channel n Current Group Priority - */ -#define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK) -#define DMA_DCHPRI16_DPA_MASK (0x40U) -#define DMA_DCHPRI16_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel - * 0b1..Channel n cannot suspend any channel, regardless of channel priority - */ -#define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK) -#define DMA_DCHPRI16_ECP_MASK (0x80U) -#define DMA_DCHPRI16_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + +#define DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_MASK (0x1U) +#define DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_SHIFT (0U) +/*! CLK_MODE - Sets the Host Controller into non-continuous MIPI clock mode. When in non-continuous + * clock mode, the high speed clock will transition into low power mode between transmissions. + * 0b0..Continuous high speed clock + * 0b1..Non-Continuous high speed clock */ -#define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK) +#define DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_SHIFT)) & DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_MASK) /*! @} */ -/*! @name DCHPRI23 - Channel Priority */ +/*! @name CFG_T_PRE - */ /*! @{ */ -#define DMA_DCHPRI23_CHPRI_MASK (0xFU) -#define DMA_DCHPRI23_CHPRI_SHIFT (0U) -/*! CHPRI - Channel n Arbitration Priority - */ -#define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK) -#define DMA_DCHPRI23_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI23_GRPPRI_SHIFT (4U) -/*! GRPPRI - Channel n Current Group Priority - */ -#define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK) -#define DMA_DCHPRI23_DPA_MASK (0x40U) -#define DMA_DCHPRI23_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel - * 0b1..Channel n cannot suspend any channel, regardless of channel priority - */ -#define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK) -#define DMA_DCHPRI23_ECP_MASK (0x80U) -#define DMA_DCHPRI23_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + +#define DSI_HOST_CFG_T_PRE_NUM_PERIODS_MASK (0xFFU) +#define DSI_HOST_CFG_T_PRE_NUM_PERIODS_SHIFT (0U) +/*! NUM_PERIODS - Sets the number of byte clock periods ('clk_byte' input) that the controller will + * wait after enabling the clock lane for HS operation before enabling the data lanes for HS + * operation. This setting represents the TCLK-PRE DPHY timing parameter. The minimum value for this + * port is 1. */ -#define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK) +#define DSI_HOST_CFG_T_PRE_NUM_PERIODS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_T_PRE_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_T_PRE_NUM_PERIODS_MASK) /*! @} */ -/*! @name DCHPRI22 - Channel Priority */ +/*! @name CFG_T_POST - */ /*! @{ */ -#define DMA_DCHPRI22_CHPRI_MASK (0xFU) -#define DMA_DCHPRI22_CHPRI_SHIFT (0U) -/*! CHPRI - Channel n Arbitration Priority - */ -#define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK) -#define DMA_DCHPRI22_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI22_GRPPRI_SHIFT (4U) -/*! GRPPRI - Channel n Current Group Priority - */ -#define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK) -#define DMA_DCHPRI22_DPA_MASK (0x40U) -#define DMA_DCHPRI22_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel - * 0b1..Channel n cannot suspend any channel, regardless of channel priority - */ -#define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK) -#define DMA_DCHPRI22_ECP_MASK (0x80U) -#define DMA_DCHPRI22_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + +#define DSI_HOST_CFG_T_POST_NUM_PERIODS_MASK (0xFFU) +#define DSI_HOST_CFG_T_POST_NUM_PERIODS_SHIFT (0U) +/*! NUM_PERIODS - Sets the number of byte clock periods ('clk_byte' input) to wait before putting + * the clock lane into LP mode after the data lanes have been detected to be in Stop State. This + * setting represents the DPHY timing parameters TLPX + TCLK-PREPARE + TCLK-ZERO + TCLK-PRE + * requirement for the clock lane before the data lane is allowed to change from LP11 to start a high + * speed transmission. The minimum value for this port is 1. */ -#define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK) +#define DSI_HOST_CFG_T_POST_NUM_PERIODS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_T_POST_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_T_POST_NUM_PERIODS_MASK) /*! @} */ -/*! @name DCHPRI21 - Channel Priority */ +/*! @name CFG_TX_GAP - */ /*! @{ */ -#define DMA_DCHPRI21_CHPRI_MASK (0xFU) -#define DMA_DCHPRI21_CHPRI_SHIFT (0U) -/*! CHPRI - Channel n Arbitration Priority - */ -#define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK) -#define DMA_DCHPRI21_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI21_GRPPRI_SHIFT (4U) -/*! GRPPRI - Channel n Current Group Priority - */ -#define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK) -#define DMA_DCHPRI21_DPA_MASK (0x40U) -#define DMA_DCHPRI21_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel - * 0b1..Channel n cannot suspend any channel, regardless of channel priority - */ -#define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK) -#define DMA_DCHPRI21_ECP_MASK (0x80U) -#define DMA_DCHPRI21_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + +#define DSI_HOST_CFG_TX_GAP_NUM_PERIODS_MASK (0xFFU) +#define DSI_HOST_CFG_TX_GAP_NUM_PERIODS_SHIFT (0U) +/*! NUM_PERIODS - Sets the number of byte clock periods ('clk_byte' input) that the controller will + * wait after the clock lane has been put into LP mode before enabling the clock lane for HS mode + * again. This setting represents the THS-EXIT DPHY timing parameter. The minimum value for this + * port is 1. */ -#define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK) +#define DSI_HOST_CFG_TX_GAP_NUM_PERIODS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_TX_GAP_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_TX_GAP_NUM_PERIODS_MASK) /*! @} */ -/*! @name DCHPRI20 - Channel Priority */ +/*! @name CFG_AUTOINSERT_EOTP - */ /*! @{ */ -#define DMA_DCHPRI20_CHPRI_MASK (0xFU) -#define DMA_DCHPRI20_CHPRI_SHIFT (0U) -/*! CHPRI - Channel n Arbitration Priority - */ -#define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK) -#define DMA_DCHPRI20_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI20_GRPPRI_SHIFT (4U) -/*! GRPPRI - Channel n Current Group Priority - */ -#define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK) -#define DMA_DCHPRI20_DPA_MASK (0x40U) -#define DMA_DCHPRI20_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel - * 0b1..Channel n cannot suspend any channel, regardless of channel priority - */ -#define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK) -#define DMA_DCHPRI20_ECP_MASK (0x80U) -#define DMA_DCHPRI20_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + +#define DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_MASK (0x1U) +#define DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_SHIFT (0U) +/*! AUTOINSERT - Enables the Host Controller to automatically insert an EoTp short packet when switching from HS to LP mode. + * 0b0..EoTp is not automatically inserted + * 0b1..EoTp is automatically inserted */ -#define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK) +#define DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_SHIFT)) & DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_MASK) /*! @} */ -/*! @name DCHPRI27 - Channel Priority */ +/*! @name CFG_EXTRA_CMDS_AFTER_EOTP - */ /*! @{ */ -#define DMA_DCHPRI27_CHPRI_MASK (0xFU) -#define DMA_DCHPRI27_CHPRI_SHIFT (0U) -/*! CHPRI - Channel n Arbitration Priority - */ -#define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK) -#define DMA_DCHPRI27_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI27_GRPPRI_SHIFT (4U) -/*! GRPPRI - Channel n Current Group Priority - */ -#define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK) -#define DMA_DCHPRI27_DPA_MASK (0x40U) -#define DMA_DCHPRI27_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel - * 0b1..Channel n cannot suspend any channel, regardless of channel priority - */ -#define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK) -#define DMA_DCHPRI27_ECP_MASK (0x80U) -#define DMA_DCHPRI27_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + +#define DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_MASK (0xFFU) +#define DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_SHIFT (0U) +/*! EXTRA_EOTP - Configures the DSI Host Controller to send extra End Of Transmission Packets after + * the end of a packet. The value is the number of extra EOTP packets sent. */ -#define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK) +#define DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_SHIFT)) & DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_MASK) /*! @} */ -/*! @name DCHPRI26 - Channel Priority */ +/*! @name CFG_HTX_TO_COUNT - */ /*! @{ */ -#define DMA_DCHPRI26_CHPRI_MASK (0xFU) -#define DMA_DCHPRI26_CHPRI_SHIFT (0U) -/*! CHPRI - Channel n Arbitration Priority - */ -#define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK) -#define DMA_DCHPRI26_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI26_GRPPRI_SHIFT (4U) -/*! GRPPRI - Channel n Current Group Priority - */ -#define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK) -#define DMA_DCHPRI26_DPA_MASK (0x40U) -#define DMA_DCHPRI26_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel - * 0b1..Channel n cannot suspend any channel, regardless of channel priority - */ -#define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK) -#define DMA_DCHPRI26_ECP_MASK (0x80U) -#define DMA_DCHPRI26_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + +#define DSI_HOST_CFG_HTX_TO_COUNT_COUNT_MASK (0xFFFFFFU) +#define DSI_HOST_CFG_HTX_TO_COUNT_COUNT_SHIFT (0U) +/*! COUNT - Sets the value of the DSI Host High Speed TX timeout count in clk_byte clock periods + * that once reached will initiate a timeout error and follow the recovery procedure documented in + * the DSI specification. */ -#define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK) +#define DSI_HOST_CFG_HTX_TO_COUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_HTX_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_HTX_TO_COUNT_COUNT_MASK) /*! @} */ -/*! @name DCHPRI25 - Channel Priority */ +/*! @name CFG_LRX_H_TO_COUNT - */ /*! @{ */ -#define DMA_DCHPRI25_CHPRI_MASK (0xFU) -#define DMA_DCHPRI25_CHPRI_SHIFT (0U) -/*! CHPRI - Channel n Arbitration Priority - */ -#define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK) -#define DMA_DCHPRI25_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI25_GRPPRI_SHIFT (4U) -/*! GRPPRI - Channel n Current Group Priority - */ -#define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK) -#define DMA_DCHPRI25_DPA_MASK (0x40U) -#define DMA_DCHPRI25_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel - * 0b1..Channel n cannot suspend any channel, regardless of channel priority - */ -#define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK) -#define DMA_DCHPRI25_ECP_MASK (0x80U) -#define DMA_DCHPRI25_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + +#define DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_MASK (0xFFFFFFU) +#define DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_SHIFT (0U) +/*! COUNT - Sets the value of the DSI Host low power RX timeout count in clk_byte clock periods that + * once reached will initiate a timeout error and follow the recovery procedure documented in + * the DSI specification. */ -#define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK) +#define DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_MASK) /*! @} */ -/*! @name DCHPRI24 - Channel Priority */ +/*! @name CFG_BTA_H_TO_COUNT - */ /*! @{ */ -#define DMA_DCHPRI24_CHPRI_MASK (0xFU) -#define DMA_DCHPRI24_CHPRI_SHIFT (0U) -/*! CHPRI - Channel n Arbitration Priority - */ -#define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK) -#define DMA_DCHPRI24_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI24_GRPPRI_SHIFT (4U) -/*! GRPPRI - Channel n Current Group Priority - */ -#define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK) -#define DMA_DCHPRI24_DPA_MASK (0x40U) -#define DMA_DCHPRI24_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel - * 0b1..Channel n cannot suspend any channel, regardless of channel priority - */ -#define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK) -#define DMA_DCHPRI24_ECP_MASK (0x80U) -#define DMA_DCHPRI24_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + +#define DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_MASK (0xFFFFFFU) +#define DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_SHIFT (0U) +/*! COUNT - Sets the value of the DSI Host Bus Turn Around (BTA) timeout in clk_byte clock periods + * that once reached will initiate a timeout error. */ -#define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK) +#define DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_MASK) /*! @} */ -/*! @name DCHPRI31 - Channel Priority */ +/*! @name CFG_TWAKEUP - */ /*! @{ */ -#define DMA_DCHPRI31_CHPRI_MASK (0xFU) -#define DMA_DCHPRI31_CHPRI_SHIFT (0U) -/*! CHPRI - Channel n Arbitration Priority - */ -#define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK) -#define DMA_DCHPRI31_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI31_GRPPRI_SHIFT (4U) -/*! GRPPRI - Channel n Current Group Priority - */ -#define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK) -#define DMA_DCHPRI31_DPA_MASK (0x40U) -#define DMA_DCHPRI31_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel - * 0b1..Channel n cannot suspend any channel, regardless of channel priority - */ -#define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK) -#define DMA_DCHPRI31_ECP_MASK (0x80U) -#define DMA_DCHPRI31_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + +#define DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_MASK (0x7FFFFU) +#define DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_SHIFT (0U) +/*! NUM_PERIODS - DPHY Twakeup timing parameter. Sets the number of clk_esc clock periods to keep a + * clock or data lane in Mark-1 state after exiting ULPS. The MIPI DPHY spec requires a minimum + * of 1ms in Mark-1 state after leaving ULPS. */ -#define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK) +#define DSI_HOST_CFG_TWAKEUP_NUM_PERIODS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_MASK) /*! @} */ -/*! @name DCHPRI30 - Channel Priority */ +/*! @name CFG_STATUS_OUT - */ /*! @{ */ -#define DMA_DCHPRI30_CHPRI_MASK (0xFU) -#define DMA_DCHPRI30_CHPRI_SHIFT (0U) -/*! CHPRI - Channel n Arbitration Priority - */ -#define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK) -#define DMA_DCHPRI30_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI30_GRPPRI_SHIFT (4U) -/*! GRPPRI - Channel n Current Group Priority - */ -#define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK) -#define DMA_DCHPRI30_DPA_MASK (0x40U) -#define DMA_DCHPRI30_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel - * 0b1..Channel n cannot suspend any channel, regardless of channel priority - */ -#define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK) -#define DMA_DCHPRI30_ECP_MASK (0x80U) -#define DMA_DCHPRI30_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + +#define DSI_HOST_CFG_STATUS_OUT_STATUS_MASK (0xFFFFFFFFU) +#define DSI_HOST_CFG_STATUS_OUT_STATUS_SHIFT (0U) +/*! STATUS - Status Register */ -#define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK) +#define DSI_HOST_CFG_STATUS_OUT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_STATUS_OUT_STATUS_SHIFT)) & DSI_HOST_CFG_STATUS_OUT_STATUS_MASK) /*! @} */ -/*! @name DCHPRI29 - Channel Priority */ +/*! @name RX_ERROR_STATUS - */ /*! @{ */ -#define DMA_DCHPRI29_CHPRI_MASK (0xFU) -#define DMA_DCHPRI29_CHPRI_SHIFT (0U) -/*! CHPRI - Channel n Arbitration Priority + +#define DSI_HOST_RX_ERROR_STATUS_STATUS_MASK (0x7FFU) +#define DSI_HOST_RX_ERROR_STATUS_STATUS_SHIFT (0U) +/*! STATUS - Status Register for Host receive error detection, ECC errors, CRC errors and for timeout indicators */ -#define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK) -#define DMA_DCHPRI29_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI29_GRPPRI_SHIFT (4U) -/*! GRPPRI - Channel n Current Group Priority +#define DSI_HOST_RX_ERROR_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_RX_ERROR_STATUS_STATUS_SHIFT)) & DSI_HOST_RX_ERROR_STATUS_STATUS_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group DSI_HOST_Register_Masks */ + + +/* DSI_HOST - Peripheral instance base addresses */ +/** Peripheral MIPI_DSI__DSI_HOST base address */ +#define MIPI_DSI__DSI_HOST_BASE (0x4080C000u) +/** Peripheral MIPI_DSI__DSI_HOST base pointer */ +#define MIPI_DSI__DSI_HOST ((DSI_HOST_Type *)MIPI_DSI__DSI_HOST_BASE) +/** Array initializer of DSI_HOST peripheral base addresses */ +#define DSI_HOST_BASE_ADDRS { MIPI_DSI__DSI_HOST_BASE } +/** Array initializer of DSI_HOST peripheral base pointers */ +#define DSI_HOST_BASE_PTRS { MIPI_DSI__DSI_HOST } +/** Interrupt vectors for the DSI_HOST peripheral type */ +#define DSI_HOST_DSI_IRQS { MIPI_DSI_IRQn } + +/*! + * @} + */ /* end of group DSI_HOST_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DSI_HOST_APB_PKT_IF Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DSI_HOST_APB_PKT_IF_Peripheral_Access_Layer DSI_HOST_APB_PKT_IF Peripheral Access Layer + * @{ */ -#define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK) -#define DMA_DCHPRI29_DPA_MASK (0x40U) -#define DMA_DCHPRI29_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel - * 0b1..Channel n cannot suspend any channel, regardless of channel priority + +/** DSI_HOST_APB_PKT_IF - Register Layout Typedef */ +typedef struct { + __IO uint32_t TX_PAYLOAD; /**< , offset: 0x0 */ + __IO uint32_t PKT_CONTROL; /**< , offset: 0x4 */ + __IO uint32_t SEND_PACKET; /**< , offset: 0x8 */ + __I uint32_t PKT_STATUS; /**< , offset: 0xC */ + __I uint32_t PKT_FIFO_WR_LEVEL; /**< , offset: 0x10 */ + __I uint32_t PKT_FIFO_RD_LEVEL; /**< , offset: 0x14 */ + __I uint32_t PKT_RX_PAYLOAD; /**< , offset: 0x18 */ + __I uint32_t PKT_RX_PKT_HEADER; /**< , offset: 0x1C */ + __I uint32_t IRQ_STATUS; /**< , offset: 0x20 */ + __I uint32_t IRQ_STATUS2; /**< , offset: 0x24 */ + __IO uint32_t IRQ_MASK; /**< , offset: 0x28 */ + __IO uint32_t IRQ_MASK2; /**< , offset: 0x2C */ +} DSI_HOST_APB_PKT_IF_Type; + +/* ---------------------------------------------------------------------------- + -- DSI_HOST_APB_PKT_IF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DSI_HOST_APB_PKT_IF_Register_Masks DSI_HOST_APB_PKT_IF Register Masks + * @{ */ -#define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK) -#define DMA_DCHPRI29_ECP_MASK (0x80U) -#define DMA_DCHPRI29_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + +/*! @name TX_PAYLOAD - */ +/*! @{ */ + +#define DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD_MASK (0xFFFFFFFFU) +#define DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD_SHIFT (0U) +/*! PAYLOAD - Tx Payload data write register. Write to this register loads the payload FIFO with 32 bit values. */ -#define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK) +#define DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD_SHIFT)) & DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD_MASK) /*! @} */ -/*! @name DCHPRI28 - Channel Priority */ +/*! @name PKT_CONTROL - */ /*! @{ */ -#define DMA_DCHPRI28_CHPRI_MASK (0xFU) -#define DMA_DCHPRI28_CHPRI_SHIFT (0U) -/*! CHPRI - Channel n Arbitration Priority - */ -#define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK) -#define DMA_DCHPRI28_GRPPRI_MASK (0x30U) -#define DMA_DCHPRI28_GRPPRI_SHIFT (4U) -/*! GRPPRI - Channel n Current Group Priority - */ -#define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK) -#define DMA_DCHPRI28_DPA_MASK (0x40U) -#define DMA_DCHPRI28_DPA_SHIFT (6U) -/*! DPA - Disable Preempt Ability. This field resets to 0. - * 0b0..Channel n can suspend a lower priority channel - * 0b1..Channel n cannot suspend any channel, regardless of channel priority - */ -#define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK) -#define DMA_DCHPRI28_ECP_MASK (0x80U) -#define DMA_DCHPRI28_ECP_SHIFT (7U) -/*! ECP - Enable Channel Preemption. This field resets to 0. - * 0b0..Channel n cannot be suspended by a higher priority channel's service request - * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel + +#define DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL_MASK (0x7FFFFFFU) +#define DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL_SHIFT (0U) +/*! CTRL - Tx packet control */ -#define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK) +#define DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL_MASK) /*! @} */ -/*! @name SADDR - TCD Source Address */ +/*! @name SEND_PACKET - */ /*! @{ */ -#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU) -#define DMA_SADDR_SADDR_SHIFT (0U) -/*! SADDR - Source Address + +#define DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND_MASK (0x1U) +#define DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND_SHIFT (0U) +/*! TX_SEND - Tx send packet, writing to this register causes the packet described in dsi_host_pkt_control to be sent. + * 0b0..Packet not sent + * 0b1..Packet is sent */ -#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK) +#define DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND_SHIFT)) & DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND_MASK) /*! @} */ -/* The count of DMA_SADDR */ -#define DMA_SADDR_COUNT (32U) +/*! @name PKT_STATUS - */ +/*! @{ */ -/*! @name SOFF - TCD Signed Source Address Offset */ +#define DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS_MASK (0x1FFU) +#define DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS_SHIFT (0U) +/*! STATUS - Status of APB to packet interface. + */ +#define DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS_MASK) +/*! @} */ + +/*! @name PKT_FIFO_WR_LEVEL - */ /*! @{ */ -#define DMA_SOFF_SOFF_MASK (0xFFFFU) -#define DMA_SOFF_SOFF_SHIFT (0U) -/*! SOFF - Source address signed offset + +#define DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR_MASK (0xFFFFU) +#define DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR_SHIFT (0U) +/*! WR - Write level of APB to pkt interface FIFO */ -#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK) +#define DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR_MASK) /*! @} */ -/* The count of DMA_SOFF */ -#define DMA_SOFF_COUNT (32U) +/*! @name PKT_FIFO_RD_LEVEL - */ +/*! @{ */ -/*! @name ATTR - TCD Transfer Attributes */ +#define DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD_MASK (0xFFFFU) +#define DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD_SHIFT (0U) +/*! RD - Read level of APB to pkt interface FIFO + */ +#define DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD_MASK) +/*! @} */ + +/*! @name PKT_RX_PAYLOAD - */ /*! @{ */ -#define DMA_ATTR_DSIZE_MASK (0x7U) -#define DMA_ATTR_DSIZE_SHIFT (0U) -/*! DSIZE - Destination data transfer size + +#define DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD_MASK (0xFFFFFFFFU) +#define DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD_SHIFT (0U) +/*! PAYLOAD - APB to pkt interface Rx payload read */ -#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK) -#define DMA_ATTR_DMOD_MASK (0xF8U) -#define DMA_ATTR_DMOD_SHIFT (3U) -/*! DMOD - Destination Address Modulo +#define DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD_MASK) +/*! @} */ + +/*! @name PKT_RX_PKT_HEADER - */ +/*! @{ */ + +#define DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER_MASK (0xFFFFFFU) +#define DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER_SHIFT (0U) +/*! HEADER - APB to pkt interface Rx packet header */ -#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK) -#define DMA_ATTR_SSIZE_MASK (0x700U) -#define DMA_ATTR_SSIZE_SHIFT (8U) -/*! SSIZE - Source data transfer size - * 0b000..8-bit - * 0b001..16-bit - * 0b010..32-bit - * 0b011..64-bit - * 0b100..Reserved - * 0b101..32-byte burst (4 beats of 64 bits) - * 0b110..Reserved - * 0b111..Reserved +#define DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER_MASK) +/*! @} */ + +/*! @name IRQ_STATUS - */ +/*! @{ */ + +#define DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS_MASK (0xFFFFFFFFU) +#define DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS_SHIFT (0U) +/*! STATUS - Status of APB to packet interface. */ -#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK) -#define DMA_ATTR_SMOD_MASK (0xF800U) -#define DMA_ATTR_SMOD_SHIFT (11U) -/*! SMOD - Source Address Modulo - * 0b00000..Source address modulo feature is disabled - * 0b00001-0b11111..Value defines address range used to set up circular data queue +#define DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS_SHIFT)) & DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS_MASK) +/*! @} */ + +/*! @name IRQ_STATUS2 - */ +/*! @{ */ + +#define DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2_MASK (0x7U) +#define DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2_SHIFT (0U) +/*! STATUS2 - Status of APB to packet interface part 2, read part 2 first then dsi_host_irq_status. + * Reading dsi_host_irq_status will clear both status and status2. */ -#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK) +#define DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2_SHIFT)) & DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2_MASK) /*! @} */ -/* The count of DMA_ATTR */ -#define DMA_ATTR_COUNT (32U) +/*! @name IRQ_MASK - */ +/*! @{ */ -/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */ +#define DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK_MASK (0xFFFFFFFFU) +#define DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK_SHIFT (0U) +/*! MASK - IRQ Mask + */ +#define DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK_SHIFT)) & DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK_MASK) +/*! @} */ + +/*! @name IRQ_MASK2 - */ /*! @{ */ -#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU) -#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U) -/*! NBYTES - Minor Byte Transfer Count + +#define DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2_MASK (0x7U) +#define DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2_SHIFT (0U) +/*! MASK2 - IRQ mask 2 */ -#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK) +#define DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2_SHIFT)) & DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2_MASK) /*! @} */ -/* The count of DMA_NBYTES_MLNO */ -#define DMA_NBYTES_MLNO_COUNT (32U) -/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */ -/*! @{ */ -#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) -#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) -/*! NBYTES - Minor Byte Transfer Count +/*! + * @} + */ /* end of group DSI_HOST_APB_PKT_IF_Register_Masks */ + + +/* DSI_HOST_APB_PKT_IF - Peripheral instance base addresses */ +/** Peripheral MIPI_DSI__DSI_HOST_APB_PKT_IF base address */ +#define MIPI_DSI__DSI_HOST_APB_PKT_IF_BASE (0x4080C280u) +/** Peripheral MIPI_DSI__DSI_HOST_APB_PKT_IF base pointer */ +#define MIPI_DSI__DSI_HOST_APB_PKT_IF ((DSI_HOST_APB_PKT_IF_Type *)MIPI_DSI__DSI_HOST_APB_PKT_IF_BASE) +/** Array initializer of DSI_HOST_APB_PKT_IF peripheral base addresses */ +#define DSI_HOST_APB_PKT_IF_BASE_ADDRS { MIPI_DSI__DSI_HOST_APB_PKT_IF_BASE } +/** Array initializer of DSI_HOST_APB_PKT_IF peripheral base pointers */ +#define DSI_HOST_APB_PKT_IF_BASE_PTRS { MIPI_DSI__DSI_HOST_APB_PKT_IF } + +/*! + * @} + */ /* end of group DSI_HOST_APB_PKT_IF_Peripheral_Access_Layer */ + + +/* ---------------------------------------------------------------------------- + -- DSI_HOST_DPI_INTFC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DSI_HOST_DPI_INTFC_Peripheral_Access_Layer DSI_HOST_DPI_INTFC Peripheral Access Layer + * @{ */ -#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) -#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) -#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) -/*! DMLOE - Destination Minor Loop Offset Enable - * 0b0..The minor loop offset is not applied to the DADDR - * 0b1..The minor loop offset is applied to the DADDR + +/** DSI_HOST_DPI_INTFC - Register Layout Typedef */ +typedef struct { + __IO uint32_t PIXEL_PAYLOAD_SIZE; /**< , offset: 0x0 */ + __IO uint32_t PIXEL_FIFO_SEND_LEVEL; /**< , offset: 0x4 */ + __IO uint32_t INTERFACE_COLOR_CODING; /**< , offset: 0x8 */ + __IO uint32_t PIXEL_FORMAT; /**< , offset: 0xC */ + __IO uint32_t VSYNC_POLARITY; /**< , offset: 0x10 */ + __IO uint32_t HSYNC_POLARITY; /**< , offset: 0x14 */ + __IO uint32_t VIDEO_MODE; /**< , offset: 0x18 */ + __IO uint32_t HFP; /**< , offset: 0x1C */ + __IO uint32_t HBP; /**< , offset: 0x20 */ + __IO uint32_t HSA; /**< , offset: 0x24 */ + __IO uint32_t ENABLE_MULT_PKTS; /**< , offset: 0x28 */ + __IO uint32_t VBP; /**< , offset: 0x2C */ + __IO uint32_t VFP; /**< , offset: 0x30 */ + __IO uint32_t BLLP_MODE; /**< , offset: 0x34 */ + __IO uint32_t USE_NULL_PKT_BLLP; /**< , offset: 0x38 */ + __IO uint32_t VACTIVE; /**< , offset: 0x3C */ +} DSI_HOST_DPI_INTFC_Type; + +/* ---------------------------------------------------------------------------- + -- DSI_HOST_DPI_INTFC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DSI_HOST_DPI_INTFC_Register_Masks DSI_HOST_DPI_INTFC Register Masks + * @{ */ -#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) -#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) -#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) -/*! SMLOE - Source Minor Loop Offset Enable - * 0b0..The minor loop offset is not applied to the SADDR - * 0b1..The minor loop offset is applied to the SADDR + +/*! @name PIXEL_PAYLOAD_SIZE - */ +/*! @{ */ + +#define DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_MASK (0xFFFFU) +#define DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_SHIFT (0U) +/*! PAYLOAD_SIZE - Maximum number of pixels that should be sent as one DSI packet. Recommended to be + * evenly divisible by the line size (in pixels). */ -#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) +#define DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_MASK) /*! @} */ -/* The count of DMA_NBYTES_MLOFFNO */ -#define DMA_NBYTES_MLOFFNO_COUNT (32U) - -/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */ +/*! @name PIXEL_FIFO_SEND_LEVEL - */ /*! @{ */ -#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) -#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) -/*! NBYTES - Minor Byte Transfer Count - */ -#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) -#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) -#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) -/*! MLOFF - If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the - * source or destination address to form the next-state value after the minor loop completes. + +#define DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_MASK (0xFFFFU) +#define DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_SHIFT (0U) +/*! FIFO_SEND_LEVEL - In order to optimize DSI utility, the DPI bridge buffers a certain number of + * DPI pixels before initiating a DSI packet. This configuration port controls the level at which + * the DPI Host bridge begins sending pixels. */ -#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) -#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) -#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) -/*! DMLOE - Destination Minor Loop Offset Enable - * 0b0..The minor loop offset is not applied to the DADDR - * 0b1..The minor loop offset is applied to the DADDR +#define DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_MASK) +/*! @} */ + +/*! @name INTERFACE_COLOR_CODING - */ +/*! @{ */ + +#define DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_MASK (0x7U) +#define DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_SHIFT (0U) +/*! RGB_CONFIG - Sets the distribution of RGB bits within the 24-bit d bus, as specified by the DPI specification. + * 0b000..16-bit Configuration 1 + * 0b001..16-bit Configuration 2 + * 0b010..16-bit Configuration 3 + * 0b011..18-bit Configuration 1 + * 0b100..18-bit Configuration 2 + * 0b101..24-bit + * 0b110, 0b111..Reserved */ -#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) -#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) -#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) -/*! SMLOE - Source Minor Loop Offset Enable - * 0b0..The minor loop offset is not applied to the SADDR - * 0b1..The minor loop offset is applied to the SADDR +#define DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_SHIFT)) & DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_MASK) +/*! @} */ + +/*! @name PIXEL_FORMAT - */ +/*! @{ */ + +#define DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_MASK (0x3U) +#define DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_SHIFT (0U) +/*! PIXEL_FORMAT - Sets the DSI packet type of the pixels + * 0b00..16 bit + * 0b01..18 bit + * 0b10..18 bit loosely packed + * 0b11..24 bit */ -#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) +#define DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_MASK) /*! @} */ -/* The count of DMA_NBYTES_MLOFFYES */ -#define DMA_NBYTES_MLOFFYES_COUNT (32U) +/*! @name VSYNC_POLARITY - */ +/*! @{ */ + +#define DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_MASK (0x1U) +#define DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_SHIFT (0U) +/*! VSYNC_POLARITY - Sets polarity of dpi_vsync_input + * 0b0..active low + * 0b1..active high + */ +#define DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_SHIFT)) & DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_MASK) +/*! @} */ -/*! @name SLAST - TCD Last Source Address Adjustment */ +/*! @name HSYNC_POLARITY - */ /*! @{ */ -#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU) -#define DMA_SLAST_SLAST_SHIFT (0U) -/*! SLAST - Last Source Address Adjustment + +#define DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_MASK (0x1U) +#define DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_SHIFT (0U) +/*! HSYNC_POLARITY - Sets polarity of dpi_hsync_input + * 0b0..active low + * 0b1..active high */ -#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK) +#define DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_SHIFT)) & DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_MASK) /*! @} */ -/* The count of DMA_SLAST */ -#define DMA_SLAST_COUNT (32U) - -/*! @name DADDR - TCD Destination Address */ +/*! @name VIDEO_MODE - */ /*! @{ */ -#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU) -#define DMA_DADDR_DADDR_SHIFT (0U) -/*! DADDR - Destination Address + +#define DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_MASK (0x3U) +#define DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_SHIFT (0U) +/*! VIDEO_MODE - Select DSI video mode that the host DPI module should generate packets for. + * 0b00..Non-Burst mode with Sync Pulses + * 0b01..Non-Burst mode with Sync Events + * 0b10..Burst mode + * 0b11..Reserved, not valid */ -#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK) +#define DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_SHIFT)) & DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_MASK) /*! @} */ -/* The count of DMA_DADDR */ -#define DMA_DADDR_COUNT (32U) - -/*! @name DOFF - TCD Signed Destination Address Offset */ +/*! @name HFP - */ /*! @{ */ -#define DMA_DOFF_DOFF_MASK (0xFFFFU) -#define DMA_DOFF_DOFF_SHIFT (0U) -/*! DOFF - Destination Address Signed Offset + +#define DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_MASK (0xFFFFU) +#define DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_SHIFT (0U) +/*! PAYLOAD_SIZE - Sets the DSI packet payload size, in bytes, of the horizontal front porch blanking packet. */ -#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK) +#define DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_MASK) /*! @} */ -/* The count of DMA_DOFF */ -#define DMA_DOFF_COUNT (32U) - -/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ +/*! @name HBP - */ /*! @{ */ -#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) -#define DMA_CITER_ELINKNO_CITER_SHIFT (0U) -/*! CITER - Current Major Iteration Count - */ -#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK) -#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) -#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U) -/*! ELINK - Enable channel-to-channel linking on minor-loop complete - * 0b0..Channel-to-channel linking is disabled - * 0b1..Channel-to-channel linking is enabled + +#define DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_MASK (0xFFFFU) +#define DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_SHIFT (0U) +/*! PAYLOAD_SIZE - Sets the DSI packet payload size, in bytes, of the horizontal back porch blanking packet. */ -#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK) +#define DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_MASK) /*! @} */ -/* The count of DMA_CITER_ELINKNO */ -#define DMA_CITER_ELINKNO_COUNT (32U) - -/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ +/*! @name HSA - */ /*! @{ */ -#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) -#define DMA_CITER_ELINKYES_CITER_SHIFT (0U) -/*! CITER - Current Major Iteration Count - */ -#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK) -#define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U) -#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U) -/*! LINKCH - Minor Loop Link Channel Number - */ -#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK) -#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) -#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U) -/*! ELINK - Enable channel-to-channel linking on minor-loop complete - * 0b0..Channel-to-channel linking is disabled - * 0b1..Channel-to-channel linking is enabled + +#define DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_MASK (0xFFFFU) +#define DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_SHIFT (0U) +/*! PAYLOAD_SIZE - Sets the DSI packet payload size, in bytes, of the horizontal sync width filler blanking packet. */ -#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK) +#define DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_MASK) /*! @} */ -/* The count of DMA_CITER_ELINKYES */ -#define DMA_CITER_ELINKYES_COUNT (32U) - -/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */ +/*! @name ENABLE_MULT_PKTS - */ /*! @{ */ -#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU) -#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U) -/*! DLASTSGA - Destination last address adjustment, or next memory address TCD for channel (scatter/gather) + +#define DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_MASK (0x1U) +#define DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_SHIFT (0U) +/*! ENABLE_MULT_PKTS - Enable Multiple packets per video line. When enabled, + * PIXEL_PAYLOAD_SIZE[PAYLOAD_SIZE] must be set to exactly half the size of the video line + * 0b0..Video Line is sent in a single packet + * 0b1..Video Line is sent in two packets */ -#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK) +#define DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_SHIFT)) & DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_MASK) /*! @} */ -/* The count of DMA_DLAST_SGA */ -#define DMA_DLAST_SGA_COUNT (32U) - -/*! @name CSR - TCD Control and Status */ +/*! @name VBP - */ /*! @{ */ -#define DMA_CSR_START_MASK (0x1U) -#define DMA_CSR_START_SHIFT (0U) -/*! START - Channel Start - * 0b0..Channel is not explicitly started - * 0b1..Channel is explicitly started via a software initiated service request - */ -#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK) -#define DMA_CSR_INTMAJOR_MASK (0x2U) -#define DMA_CSR_INTMAJOR_SHIFT (1U) -/*! INTMAJOR - Enable an interrupt when major iteration count completes. - * 0b0..End of major loop interrupt is disabled - * 0b1..End of major loop interrupt is enabled - */ -#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK) -#define DMA_CSR_INTHALF_MASK (0x4U) -#define DMA_CSR_INTHALF_SHIFT (2U) -/*! INTHALF - Enable an interrupt when major counter is half complete. - * 0b0..Half-point interrupt is disabled - * 0b1..Half-point interrupt is enabled - */ -#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK) -#define DMA_CSR_DREQ_MASK (0x8U) -#define DMA_CSR_DREQ_SHIFT (3U) -/*! DREQ - Disable Request - * 0b0..The channel's ERQ field is not affected - * 0b1..The channel's ERQ field value changes to 0 when the major loop is complete - */ -#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK) -#define DMA_CSR_ESG_MASK (0x10U) -#define DMA_CSR_ESG_SHIFT (4U) -/*! ESG - Enable Scatter/Gather Processing - * 0b0..The current channel's TCD is normal format - * 0b1..The current channel's TCD specifies a scatter gather format - */ -#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK) -#define DMA_CSR_MAJORELINK_MASK (0x20U) -#define DMA_CSR_MAJORELINK_SHIFT (5U) -/*! MAJORELINK - Enable channel-to-channel linking on major loop complete - * 0b0..Channel-to-channel linking is disabled - * 0b1..Channel-to-channel linking is enabled - */ -#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK) -#define DMA_CSR_ACTIVE_MASK (0x40U) -#define DMA_CSR_ACTIVE_SHIFT (6U) -/*! ACTIVE - Channel Active - */ -#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK) -#define DMA_CSR_DONE_MASK (0x80U) -#define DMA_CSR_DONE_SHIFT (7U) -/*! DONE - Channel Done - */ -#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK) -#define DMA_CSR_MAJORLINKCH_MASK (0x1F00U) -#define DMA_CSR_MAJORLINKCH_SHIFT (8U) -/*! MAJORLINKCH - Major Loop Link Channel Number - */ -#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK) -#define DMA_CSR_BWC_MASK (0xC000U) -#define DMA_CSR_BWC_SHIFT (14U) -/*! BWC - Bandwidth Control - * 0b00..No eDMA engine stalls - * 0b01..Reserved - * 0b10..eDMA engine stalls for 4 cycles after each R/W - * 0b11..eDMA engine stalls for 8 cycles after each R/W + +#define DSI_HOST_DPI_INTFC_VBP_NUM_LINES_MASK (0xFFU) +#define DSI_HOST_DPI_INTFC_VBP_NUM_LINES_SHIFT (0U) +/*! NUM_LINES - Sets the number of lines in the vertical back porch. */ -#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK) +#define DSI_HOST_DPI_INTFC_VBP_NUM_LINES(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VBP_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VBP_NUM_LINES_MASK) /*! @} */ -/* The count of DMA_CSR */ -#define DMA_CSR_COUNT (32U) - -/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ +/*! @name VFP - */ /*! @{ */ -#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) -#define DMA_BITER_ELINKNO_BITER_SHIFT (0U) -/*! BITER - Starting Major Iteration Count - */ -#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK) -#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U) -#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U) -/*! ELINK - Enables channel-to-channel linking on minor loop complete - * 0b0..Channel-to-channel linking is disabled - * 0b1..Channel-to-channel linking is enabled + +#define DSI_HOST_DPI_INTFC_VFP_NUM_LINES_MASK (0xFFU) +#define DSI_HOST_DPI_INTFC_VFP_NUM_LINES_SHIFT (0U) +/*! NUM_LINES - Sets the number of lines in the vertical front porch. */ -#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK) +#define DSI_HOST_DPI_INTFC_VFP_NUM_LINES(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VFP_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VFP_NUM_LINES_MASK) /*! @} */ -/* The count of DMA_BITER_ELINKNO */ -#define DMA_BITER_ELINKNO_COUNT (32U) - -/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ +/*! @name BLLP_MODE - */ /*! @{ */ -#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU) -#define DMA_BITER_ELINKYES_BITER_SHIFT (0U) -/*! BITER - Starting major iteration count - */ -#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK) -#define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U) -#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U) -/*! LINKCH - Link Channel Number + +#define DSI_HOST_DPI_INTFC_BLLP_MODE_LP_MASK (0x1U) +#define DSI_HOST_DPI_INTFC_BLLP_MODE_LP_SHIFT (0U) +/*! LP - Optimize bllp periods to Low Power mode when possible + * 0b0..Blanking packets are sent during BLLP periods + * 0b1..LP mode is used for BLLP periods */ -#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK) -#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) -#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U) -/*! ELINK - Enables channel-to-channel linking on minor loop complete - * 0b0..Channel-to-channel linking is disabled - * 0b1..Channel-to-channel linking is enabled +#define DSI_HOST_DPI_INTFC_BLLP_MODE_LP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_BLLP_MODE_LP_SHIFT)) & DSI_HOST_DPI_INTFC_BLLP_MODE_LP_MASK) +/*! @} */ + +/*! @name USE_NULL_PKT_BLLP - */ +/*! @{ */ + +#define DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_MASK (0x1U) +#define DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_SHIFT (0U) +/*! NULL - Selects type of blanking packet to be sent during bllp + * 0b0..Blanking packet used in bllp region 1 + * 0b1..Null packet used in bllp region */ -#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK) +#define DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_SHIFT)) & DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_MASK) /*! @} */ -/* The count of DMA_BITER_ELINKYES */ -#define DMA_BITER_ELINKYES_COUNT (32U) +/*! @name VACTIVE - */ +/*! @{ */ + +#define DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_MASK (0x3FFFU) +#define DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_SHIFT (0U) +/*! NUM_LINES - Sets the number of lines in the vertical active aread. + */ +#define DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_MASK) +/*! @} */ /*! * @} - */ /* end of group DMA_Register_Masks */ + */ /* end of group DSI_HOST_DPI_INTFC_Register_Masks */ -/* DMA - Peripheral instance base addresses */ -/** Peripheral DMA0 base address */ -#define DMA0_BASE (0x40070000u) -/** Peripheral DMA0 base pointer */ -#define DMA0 ((DMA_Type *)DMA0_BASE) -/** Array initializer of DMA peripheral base addresses */ -#define DMA_BASE_ADDRS { DMA0_BASE } -/** Array initializer of DMA peripheral base pointers */ -#define DMA_BASE_PTRS { DMA0 } -/** Interrupt vectors for the DMA peripheral type */ -#define DMA_CHN_IRQS { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } } -#define DMA_ERROR_IRQS { DMA_ERROR_IRQn } +/* DSI_HOST_DPI_INTFC - Peripheral instance base addresses */ +/** Peripheral MIPI_DSI__DSI_HOST_DPI_INTFC base address */ +#define MIPI_DSI__DSI_HOST_DPI_INTFC_BASE (0x4080C200u) +/** Peripheral MIPI_DSI__DSI_HOST_DPI_INTFC base pointer */ +#define MIPI_DSI__DSI_HOST_DPI_INTFC ((DSI_HOST_DPI_INTFC_Type *)MIPI_DSI__DSI_HOST_DPI_INTFC_BASE) +/** Array initializer of DSI_HOST_DPI_INTFC peripheral base addresses */ +#define DSI_HOST_DPI_INTFC_BASE_ADDRS { MIPI_DSI__DSI_HOST_DPI_INTFC_BASE } +/** Array initializer of DSI_HOST_DPI_INTFC peripheral base pointers */ +#define DSI_HOST_DPI_INTFC_BASE_PTRS { MIPI_DSI__DSI_HOST_DPI_INTFC } /*! * @} - */ /* end of group DMA_Peripheral_Access_Layer */ + */ /* end of group DSI_HOST_DPI_INTFC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- - -- DMAMUX Peripheral Access Layer + -- DSI_HOST_NXP_FDSOI28_DPHY_INTFC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! - * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer + * @addtogroup DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Peripheral_Access_Layer DSI_HOST_NXP_FDSOI28_DPHY_INTFC Peripheral Access Layer * @{ */ -/** DMAMUX - Register Layout Typedef */ +/** DSI_HOST_NXP_FDSOI28_DPHY_INTFC - Register Layout Typedef */ typedef struct { - __IO uint32_t CHCFG[32]; /**< Channel 0 Configuration Register..Channel 31 Configuration Register, array offset: 0x0, array step: 0x4 */ -} DMAMUX_Type; + __IO uint32_t PD_TX; /**< , offset: 0x0 */ + __IO uint32_t M_PRG_HS_PREPARE; /**< , offset: 0x4 */ + __IO uint32_t MC_PRG_HS_PREPARE; /**< , offset: 0x8 */ + __IO uint32_t M_PRG_HS_ZERO; /**< , offset: 0xC */ + __IO uint32_t MC_PRG_HS_ZERO; /**< , offset: 0x10 */ + __IO uint32_t M_PRG_HS_TRAIL; /**< , offset: 0x14 */ + __IO uint32_t MC_PRG_HS_TRAIL; /**< , offset: 0x18 */ + __IO uint32_t PD_PLL; /**< , offset: 0x1C */ + __IO uint32_t TST; /**< , offset: 0x20 */ + __IO uint32_t CN; /**< , offset: 0x24 */ + __IO uint32_t CM; /**< , offset: 0x28 */ + __IO uint32_t CO; /**< , offset: 0x2C */ + __I uint32_t LOCK; /**< , offset: 0x30 */ + __IO uint32_t LOCK_BYP; /**< , offset: 0x34 */ + __IO uint32_t TX_RCAL; /**< , offset: 0x38 */ + __IO uint32_t AUTO_PD_EN; /**< , offset: 0x3C */ + __IO uint32_t RXLPRP; /**< , offset: 0x40 */ + __IO uint32_t RXCDRP; /**< , offset: 0x44 */ +} DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type; /* ---------------------------------------------------------------------------- - -- DMAMUX Register Masks + -- DSI_HOST_NXP_FDSOI28_DPHY_INTFC Register Masks ---------------------------------------------------------------------------- */ /*! - * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks + * @addtogroup DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Register_Masks DSI_HOST_NXP_FDSOI28_DPHY_INTFC Register Masks * @{ */ -/*! @name CHCFG - Channel 0 Configuration Register..Channel 31 Configuration Register */ +/*! @name PD_TX - */ /*! @{ */ -#define DMAMUX_CHCFG_SOURCE_MASK (0xFFU) -#define DMAMUX_CHCFG_SOURCE_SHIFT (0U) -/*! SOURCE - DMA Channel Source (Slot Number) + +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX_MASK (0x1U) +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX_SHIFT (0U) +/*! PD_TX - Power Down input for D-PHY + * 0b1..Power Down + * 0b0..Power Up */ -#define DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) -#define DMAMUX_CHCFG_A_ON_MASK (0x20000000U) -#define DMAMUX_CHCFG_A_ON_SHIFT (29U) -/*! A_ON - DMA Channel Always Enable - * 0b0..DMA Channel Always ON function is disabled - * 0b1..DMA Channel Always ON function is enabled +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX_MASK) +/*! @} */ + +/*! @name M_PRG_HS_PREPARE - */ +/*! @{ */ + +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_MASK (0x3U) +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_SHIFT (0U) +/*! M_PRG_HS_PREPARE - DPHY m_PRG_HS_PREPARE input */ -#define DMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK) -#define DMAMUX_CHCFG_TRIG_MASK (0x40000000U) -#define DMAMUX_CHCFG_TRIG_SHIFT (30U) -/*! TRIG - DMA Channel Trigger Enable - * 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the - * specified source to the DMA channel. (Normal mode) - * 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode. +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_MASK) +/*! @} */ + +/*! @name MC_PRG_HS_PREPARE - */ +/*! @{ */ + +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_MASK (0x1U) +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_SHIFT (0U) +/*! MC_PRG_HS_PREPARE - DPHY mc_PRG_HS_PREPARE input */ -#define DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) -#define DMAMUX_CHCFG_ENBL_MASK (0x80000000U) -#define DMAMUX_CHCFG_ENBL_SHIFT (31U) -/*! ENBL - DMA Mux Channel Enable - * 0b0..DMA Mux channel is disabled - * 0b1..DMA Mux channel is enabled +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_MASK) +/*! @} */ + +/*! @name M_PRG_HS_ZERO - */ +/*! @{ */ + +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO_MASK (0x1FU) +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO_SHIFT (0U) +/*! M_PRG_HS_ZERO - DPHY m_PRG_HS_ZERO input */ -#define DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO_MASK) /*! @} */ -/* The count of DMAMUX_CHCFG */ -#define DMAMUX_CHCFG_COUNT (32U) +/*! @name MC_PRG_HS_ZERO - */ +/*! @{ */ +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_MASK (0x3FU) +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_SHIFT (0U) +/*! MC_PRG_HS_ZERO - DPHY mc_PRG_HS_ZERO input + */ +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_MASK) +/*! @} */ -/*! - * @} - */ /* end of group DMAMUX_Register_Masks */ +/*! @name M_PRG_HS_TRAIL - */ +/*! @{ */ +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_MASK (0xFU) +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_SHIFT (0U) +/*! M_PRG_HS_TRAIL - DPHY m_PRG_HS_TRAIL input + */ +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_MASK) +/*! @} */ -/* DMAMUX - Peripheral instance base addresses */ -/** Peripheral DMAMUX0 base address */ -#define DMAMUX0_BASE (0x40074000u) -/** Peripheral DMAMUX0 base pointer */ -#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE) -/** Array initializer of DMAMUX peripheral base addresses */ -#define DMAMUX_BASE_ADDRS { DMAMUX0_BASE } -/** Array initializer of DMAMUX peripheral base pointers */ -#define DMAMUX_BASE_PTRS { DMAMUX0 } +/*! @name MC_PRG_HS_TRAIL - */ +/*! @{ */ -/*! - * @} - */ /* end of group DMAMUX_Peripheral_Access_Layer */ +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_MASK (0xFU) +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_SHIFT (0U) +/*! MC_PRG_HS_TRAIL - DPHY mc_PRG_HS_TRAIL input + */ +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_MASK) +/*! @} */ +/*! @name PD_PLL - */ +/*! @{ */ -/* ---------------------------------------------------------------------------- - -- MIPI_DSI_HOST Peripheral Access Layer - ---------------------------------------------------------------------------- */ +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL_MASK (0x1U) +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL_SHIFT (0U) +/*! PD_PLL - Power-down signal + * 0b1..Power down PLL + * 0b0..Power up PLL + */ +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL_MASK) +/*! @} */ -/*! - * @addtogroup MIPI_DSI_HOST_Peripheral_Access_Layer MIPI_DSI_HOST Peripheral Access Layer - * @{ +/*! @name TST - */ +/*! @{ */ + +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST_MASK (0x3FU) +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST_SHIFT (0U) +/*! TST - Test */ +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST_MASK) +/*! @} */ -/** MIPI_DSI_HOST - Register Layout Typedef */ -typedef struct { - __IO uint32_t DSI_HOST_CFG_NUM_LANES; /**< DSI_HOST_CFG_NUM_LANES, offset: 0x0 */ - __IO uint32_t DSI_HOST_CFG_NONCONTINUOUS_CLK; /**< DSI_HOST_CFG_NONCONTINUOUS_CLK, offset: 0x4 */ - __IO uint32_t DSI_HOST_CFG_T_PRE; /**< DSI_HOST_CFG_T_PRE, offset: 0x8 */ - __IO uint32_t DSI_HOST_CFG_T_POST; /**< DSI_HOST_CFG_T_POST, offset: 0xC */ - __IO uint32_t DSI_HOST_CFG_TX_GAP; /**< DSI_HOST_CFG_TX_GAP, offset: 0x10 */ - __IO uint32_t DSI_HOST_CFG_AUTOINSERT_EOTP; /**< DSI_HOST_CFG_AUTOINSERT_EOTP, offset: 0x14 */ - __IO uint32_t DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP; /**< DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP, offset: 0x18 */ - __IO uint32_t DSI_HOST_CFG_HTX_TO_COUNT; /**< DSI_HOST_CFG_HTX_TO_COUNT, offset: 0x1C */ - __IO uint32_t DSI_HOST_CFG_LRX_H_TO_COUNT; /**< DSI_HOST_CFG_LRX_H_TO_COUNT, offset: 0x20 */ - __IO uint32_t DSI_HOST_CFG_BTA_H_TO_COUNT; /**< DSI_HOST_CFG_BTA_H_TO_COUNT, offset: 0x24 */ - __IO uint32_t DSI_HOST_CFG_TWAKEUP; /**< DSI_HOST_CFG_TWAKEUP, offset: 0x28 */ - __I uint32_t DSI_HOST_CFG_STATUS_OUT; /**< DSI_HOST_CFG_STATUS_OUT, offset: 0x2C */ - __IO uint32_t DSI_HOST_RX_ERROR_STATUS; /**< DSI_HOST_RX_ERROR_STATUS, offset: 0x30 */ - uint8_t RESERVED_0[460]; - __IO uint32_t DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE; /**< DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE, offset: 0x200 */ - __IO uint32_t DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL; /**< DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL, offset: 0x204 */ - __IO uint32_t DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING; /**< DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING, offset: 0x208 */ - __IO uint32_t DSI_HOST_CFG_DPI_PIXEL_FORMAT; /**< DSI_HOST_CFG_DPI_PIXEL_FORMAT, offset: 0x20C */ - __IO uint32_t DSI_HOST_CFG_DPI_VSYNC_POLARITY; /**< DSI_HOST_CFG_DPI_VSYNC_POLARITY, offset: 0x210 */ - __IO uint32_t DSI_HOST_CFG_DPI_HSYNC_POLARITY; /**< DSI_HOST_CFG_DPI_HSYNC_POLARITY, offset: 0x214 */ - __IO uint32_t DSI_HOST_CFG_DPI_VIDEO_MODE; /**< DSI_HOST_CFG_DPI_VIDEO_MODE, offset: 0x218 */ - __IO uint32_t DSI_HOST_CFG_DPI_HFP; /**< DSI_HOST_CFG_DPI_HFP, offset: 0x21C */ - __IO uint32_t DSI_HOST_CFG_DPI_HBP; /**< DSI_HOST_CFG_DPI_HBP, offset: 0x220 */ - __IO uint32_t DSI_HOST_CFG_DPI_HSA; /**< DSI_HOST_CFG_DPI_HSA, offset: 0x224 */ - __IO uint32_t DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS; /**< DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS, offset: 0x228 */ - __IO uint32_t DSI_HOST_CFG_DPI_VBP; /**< DSI_HOST_CFG_DPI_VBP, offset: 0x22C */ - __IO uint32_t DSI_HOST_CFG_DPI_VFP; /**< DSI_HOST_CFG_DPI_VFP, offset: 0x230 */ - __IO uint32_t DSI_HOST_CFG_DPI_BLLP_MODE; /**< DSI_HOST_CFG_DPI_BLLP_MODE, offset: 0x234 */ - __IO uint32_t DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP; /**< DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP, offset: 0x238 */ - __IO uint32_t DSI_HOST_CFG_DPI_VACTIVE; /**< DSI_HOST_CFG_DPI_VACTIVE, offset: 0x23C */ - __IO uint32_t DSI_HOST_CFG_DPI_VC; /**< DSI_HOST_CFG_DPI_VC, offset: 0x240 */ - uint8_t RESERVED_1[60]; - __IO uint32_t DSI_HOST_TX_PAYLOAD; /**< DSI_HOST_TX_PAYLOAD, offset: 0x280 */ - __IO uint32_t DSI_HOST_PKT_CONTROL; /**< DSI_HOST_PKT_CONTROL, offset: 0x284 */ - __IO uint32_t DSI_HOST_SEND_PACKET; /**< DSI_HOST_SEND_PACKET, offset: 0x288 */ - __IO uint32_t DSI_HOST_PKT_STATUS; /**< DSI_HOST_PKT_STATUS, offset: 0x28C */ - __IO uint32_t DSI_HOST_PKT_FIFO_WR_LEVEL; /**< DSI_HOST_PKT_FIFO_WR_LEVEL, offset: 0x290 */ - __IO uint32_t DSI_HOST_PKT_FIFO_RD_LEVEL; /**< DSI_HOST_PKT_FIFO_RD_LEVEL, offset: 0x294 */ - __I uint32_t DSI_HOST_PKT_RX_PAYLOAD; /**< DSI_HOST_PKT_RX_PAYLOAD, offset: 0x298 */ - __IO uint32_t DSI_HOST_PKT_RX_PKT_HEADER; /**< DSI_HOST_PKT_RX_PKT_HEADER, offset: 0x29C */ - __I uint32_t DSI_HOST_IRQ_STATUS; /**< DSI_HOST_IRQ_STATUS, offset: 0x2A0 */ - __IO uint32_t DSI_HOST_IRQ_STATUS2; /**< DSI_HOST_IRQ_STATUS2, offset: 0x2A4 */ - __IO uint32_t DSI_HOST_IRQ_MASK; /**< DSI_HOST_IRQ_MASK, offset: 0x2A8 */ - __IO uint32_t DSI_HOST_IRQ_MASK2; /**< DSI_HOST_IRQ_MASK2, offset: 0x2AC */ - uint8_t RESERVED_2[80]; - __IO uint32_t DPHY_PD_TX; /**< DPHY_PD_TX, offset: 0x300 */ - __IO uint32_t DPHY_M_PRG_HS_PREPARE; /**< DPHY_M_PRG_HS_PREPARE, offset: 0x304 */ - __IO uint32_t DPHY_MC_PRG_HS_PREPARE; /**< DPHY_MC_PRG_HS_PREPARE, offset: 0x308 */ - __IO uint32_t DPHY_M_PRG_HS_ZERO; /**< DPHY_M_PRG_HS_ZERO, offset: 0x30C */ - __IO uint32_t DPHY_MC_PRG_HS_ZERO; /**< DPHY_MC_PRG_HS_ZERO, offset: 0x310 */ - __IO uint32_t DPHY_M_PRG_HS_TRAIL; /**< DPHY_M_PRG_HS_TRAIL, offset: 0x314 */ - __IO uint32_t DPHY_MC_PRG_HS_TRAIL; /**< DPHY_MC_PRG_HS_TRAIL, offset: 0x318 */ - __IO uint32_t DPHY_PD_PLL; /**< DPHY_PD_PLL, offset: 0x31C */ - __IO uint32_t DPHY_TST; /**< DPHY_TST, offset: 0x320 */ - __IO uint32_t DPHY_CN; /**< DPHY_CN, offset: 0x324 */ - __IO uint32_t DPHY_CM; /**< DPHY_CM, offset: 0x328 */ - __IO uint32_t DPHY_CO; /**< DPHY_CO, offset: 0x32C */ - __IO uint32_t DPHY_LOCK; /**< DPHY_LOCK, offset: 0x330 */ - __IO uint32_t DPHY_LOCK_BYP; /**< DPHY_LOCK_BYP, offset: 0x334 */ - __IO uint32_t DPHY_TX_RCAL; /**< DPHY_TX_RCAL, offset: 0x338 */ - __IO uint32_t DPHY_AUTO_PD_EN; /**< DPHY_AUTO_PD_EN, offset: 0x33C */ - __IO uint32_t DPHY_RXLPRP; /**< DPHY_RXLPRP, offset: 0x340 */ - __IO uint32_t DPHY_RXCDRP; /**< DPHY_RXCDRP, offset: 0x344 */ -} MIPI_DSI_HOST_Type; +/*! @name CN - */ +/*! @{ */ -/* ---------------------------------------------------------------------------- - -- MIPI_DSI_HOST Register Masks - ---------------------------------------------------------------------------- */ +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN_MASK (0x1FU) +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN_SHIFT (0U) +/*! CN - Control N divider + */ +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN_MASK) +/*! @} */ -/*! - * @addtogroup MIPI_DSI_HOST_Register_Masks MIPI_DSI_HOST Register Masks - * @{ +/*! @name CM - */ +/*! @{ */ + +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM_MASK (0xFFU) +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM_SHIFT (0U) +/*! CM - Control M divider + */ +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM_MASK) +/*! @} */ + +/*! @name CO - */ +/*! @{ */ + +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO_MASK (0x3U) +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO_SHIFT (0U) +/*! CO - Control O divider + * 0b00..Divide by 1 + * 0b01..Divide by 2 + * 0b10..Divide by 4 + * 0b11..Divide by 8 + */ +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO_MASK) +/*! @} */ + +/*! @name LOCK - */ +/*! @{ */ + +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK_MASK (0x1U) +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK_SHIFT (0U) +/*! LOCK - Lock Detect output + * 0b1..PLL has achieved frequency lock + * 0b0..PLL not locked + */ +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK_MASK) +/*! @} */ + +/*! @name LOCK_BYP - */ +/*! @{ */ + +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP_MASK (0x1U) +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP_SHIFT (0U) +/*! LOCK_BYP - DPHY LOCK_BYP input + * 0b0..PLL LOCK signal will gate TxByteClkHS clock + * 0b1..PLL LOCK signal will not gate TxByteClkHS clock, CIL based counter will be used to gate the TxByteClkHS + */ +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP_MASK) +/*! @} */ + +/*! @name TX_RCAL - */ +/*! @{ */ + +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL_MASK (0x3U) +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL_SHIFT (0U) +/*! TX_RCAL - On-chip termination control bits for manual calibration of HS-TX + * 0b00..20% higher than mid-range. Highest impedance setting + * 0b01..Mid-range impedance setting (default) + * 0b10..15% lower than mid-range + * 0b11..25% lower than mid-range. Lowest impedance setting + */ +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL_MASK) +/*! @} */ + +/*! @name AUTO_PD_EN - */ +/*! @{ */ + +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN_MASK (0x1U) +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN_SHIFT (0U) +/*! AUTO_PD_EN - DPHY AUTO_PD_EN input + * 0b0..Inactive lanes are powered up and driving LP11 + * 0b1..inactive lanes are powered down + */ +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN_MASK) +/*! @} */ + +/*! @name RXLPRP - */ +/*! @{ */ + +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP_MASK (0x3U) +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP_SHIFT (0U) +/*! RXLPRP - DPHY RXLPRP input */ +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP_MASK) +/*! @} */ + +/*! @name RXCDRP - */ +/*! @{ */ -/*! @name DSI_HOST_CFG_NUM_LANES - DSI_HOST_CFG_NUM_LANES */ -#define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_MASK (0x3U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_NUM_LANES_dsi_host_cfg_num_lanes_MASK) - -/*! @name DSI_HOST_CFG_NONCONTINUOUS_CLK - DSI_HOST_CFG_NONCONTINUOUS_CLK */ -#define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_MASK (0x1U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_NONCONTINUOUS_CLK_dsi_host_cfg_noncontinuous_clk_MASK) - -/*! @name DSI_HOST_CFG_T_PRE - DSI_HOST_CFG_T_PRE */ -#define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_MASK (0xFFU) -#define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_T_PRE_dsi_host_cfg_t_pre_MASK) - -/*! @name DSI_HOST_CFG_T_POST - DSI_HOST_CFG_T_POST */ -#define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_MASK (0xFFU) -#define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_T_POST_dsi_host_cfg_t_post_MASK) - -/*! @name DSI_HOST_CFG_TX_GAP - DSI_HOST_CFG_TX_GAP */ -#define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_ap_MASK (0xFFU) -#define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_ap_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_ap(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_ap_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_TX_GAP_dsi_host_cfg_tx_ap_MASK) - -/*! @name DSI_HOST_CFG_AUTOINSERT_EOTP - DSI_HOST_CFG_AUTOINSERT_EOTP */ -#define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_MASK (0x1U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_AUTOINSERT_EOTP_dsi_host_cfg_autoinsert_eotp_MASK) - -/*! @name DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP - DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP */ -#define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_MASK (0xFFU) -#define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_dsi_host_cfg_extra_cmds_after_eotp_MASK) - -/*! @name DSI_HOST_CFG_HTX_TO_COUNT - DSI_HOST_CFG_HTX_TO_COUNT */ -#define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_MASK (0xFFFFFFU) -#define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_HTX_TO_COUNT_dsi_host_cfg_htx_to_count_MASK) - -/*! @name DSI_HOST_CFG_LRX_H_TO_COUNT - DSI_HOST_CFG_LRX_H_TO_COUNT */ -#define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_MASK (0xFFFFFFU) -#define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_LRX_H_TO_COUNT_dsi_host_cfg_lrx_h_to_count_MASK) - -/*! @name DSI_HOST_CFG_BTA_H_TO_COUNT - DSI_HOST_CFG_BTA_H_TO_COUNT */ -#define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_MASK (0xFFFFFFU) -#define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_BTA_H_TO_COUNT_dsi_host_cfg_bta_h_to_count_MASK) - -/*! @name DSI_HOST_CFG_TWAKEUP - DSI_HOST_CFG_TWAKEUP */ -#define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_MASK (0x7FFFFU) -#define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_TWAKEUP_dsi_host_cfg_twakeup_MASK) - -/*! @name DSI_HOST_CFG_STATUS_OUT - DSI_HOST_CFG_STATUS_OUT */ -#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_dsi_host_cfg_status_out_MASK (0xFFFFFFFFU) -#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_dsi_host_cfg_status_out_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_dsi_host_cfg_status_out(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_dsi_host_cfg_status_out_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_STATUS_OUT_dsi_host_cfg_status_out_MASK) - -/*! @name DSI_HOST_RX_ERROR_STATUS - DSI_HOST_RX_ERROR_STATUS */ -#define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_MASK (0x7FFU) -#define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_RX_ERROR_STATUS_dsi_host_rx_error_status_MASK) - -/*! @name DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE - DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE */ -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_MASK (0xFFFFU) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_PAYLOAD_SIZE_dsi_host_cfg_dpi_pixel_payload_size_MASK) - -/*! @name DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL - DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL */ -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_MASK (0xFFFFU) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FIFO_SEND_LEVEL_dsi_host_cfg_dpi_pixel_fifo_send_level_MASK) - -/*! @name DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING - DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING */ -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_MASK (0x7U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_INTERFACE_COLOR_CODING_dsi_host_cfg_dpi_interface_color_coding_MASK) - -/*! @name DSI_HOST_CFG_DPI_PIXEL_FORMAT - DSI_HOST_CFG_DPI_PIXEL_FORMAT */ -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_MASK (0x3U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_PIXEL_FORMAT_dsi_host_cfg_dpi_pixel_format_MASK) - -/*! @name DSI_HOST_CFG_DPI_VSYNC_POLARITY - DSI_HOST_CFG_DPI_VSYNC_POLARITY */ -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_MASK (0x1U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VSYNC_POLARITY_dsi_host_cfg_dpi_vsync_polarity_MASK) - -/*! @name DSI_HOST_CFG_DPI_HSYNC_POLARITY - DSI_HOST_CFG_DPI_HSYNC_POLARITY */ -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_MASK (0x1U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSYNC_POLARITY_dsi_host_cfg_dpi_hsync_polarity_MASK) - -/*! @name DSI_HOST_CFG_DPI_VIDEO_MODE - DSI_HOST_CFG_DPI_VIDEO_MODE */ -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_MASK (0x3U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VIDEO_MODE_dsi_host_cfg_dpi_video_mode_MASK) - -/*! @name DSI_HOST_CFG_DPI_HFP - DSI_HOST_CFG_DPI_HFP */ -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_MASK (0xFFFFU) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HFP_dsi_host_cfg_dpi_hfp_MASK) - -/*! @name DSI_HOST_CFG_DPI_HBP - DSI_HOST_CFG_DPI_HBP */ -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_MASK (0xFFFFU) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HBP_dsi_host_cfg_dpi_hbp_MASK) - -/*! @name DSI_HOST_CFG_DPI_HSA - DSI_HOST_CFG_DPI_HSA */ -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_MASK (0xFFFFU) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_HSA_dsi_host_cfg_dpi_hsa_MASK) - -/*! @name DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS - DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS */ -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_MASK (0x1U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_ENABLE_MULT_PKTS_dsi_host_cfg_dpi_enable_mult_pkts_MASK) - -/*! @name DSI_HOST_CFG_DPI_VBP - DSI_HOST_CFG_DPI_VBP */ -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_MASK (0xFFU) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VBP_dsi_host_cfg_dpi_vbp_MASK) - -/*! @name DSI_HOST_CFG_DPI_VFP - DSI_HOST_CFG_DPI_VFP */ -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_MASK (0xFFU) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VFP_dsi_host_cfg_dpi_vfp_MASK) - -/*! @name DSI_HOST_CFG_DPI_BLLP_MODE - DSI_HOST_CFG_DPI_BLLP_MODE */ -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_MASK (0x1U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_BLLP_MODE_dsi_host_cfg_dpi_bllp_mode_MASK) - -/*! @name DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP - DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP */ -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_MASK (0x1U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_USE_NULL_PKT_BLLP_dsi_host_cfg_dpi_use_null_pkt_bllp_MASK) - -/*! @name DSI_HOST_CFG_DPI_VACTIVE - DSI_HOST_CFG_DPI_VACTIVE */ -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_MASK (0x3FFFU) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VACTIVE_dsi_host_cfg_dpi_vactive_MASK) - -/*! @name DSI_HOST_CFG_DPI_VC - DSI_HOST_CFG_DPI_VC */ -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_MASK (0x3U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_CFG_DPI_VC_dsi_host_cfg_dpi_vc_MASK) - -/*! @name DSI_HOST_TX_PAYLOAD - DSI_HOST_TX_PAYLOAD */ -#define MIPI_DSI_HOST_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_MASK (0xFFFFFFFFU) -#define MIPI_DSI_HOST_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_TX_PAYLOAD_dsi_host_tx_payload_MASK) - -/*! @name DSI_HOST_PKT_CONTROL - DSI_HOST_PKT_CONTROL */ -#define MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_MASK (0x7FFFFFFU) -#define MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_CONTROL_dsi_host_pkt_control_MASK) - -/*! @name DSI_HOST_SEND_PACKET - DSI_HOST_SEND_PACKET */ -#define MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_dsi_host_send_packet_MASK (0x1U) -#define MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_dsi_host_send_packet_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_dsi_host_send_packet(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_dsi_host_send_packet_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_SEND_PACKET_dsi_host_send_packet_MASK) - -/*! @name DSI_HOST_PKT_STATUS - DSI_HOST_PKT_STATUS */ -#define MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_MASK (0x1FFU) -#define MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_dsi_host_pkt_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_STATUS_dsi_host_pkt_status_MASK) - -/*! @name DSI_HOST_PKT_FIFO_WR_LEVEL - DSI_HOST_PKT_FIFO_WR_LEVEL */ -#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_MASK (0xFFFFU) -#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_WR_LEVEL_dsi_host_pkt_fifo_wr_level_MASK) - -/*! @name DSI_HOST_PKT_FIFO_RD_LEVEL - DSI_HOST_PKT_FIFO_RD_LEVEL */ -#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_MASK (0xFFFFU) -#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_FIFO_RD_LEVEL_dsi_host_pkt_fifo_rd_level_MASK) - -/*! @name DSI_HOST_PKT_RX_PAYLOAD - DSI_HOST_PKT_RX_PAYLOAD */ -#define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_MASK (0xFFFFFFFFU) -#define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_RX_PAYLOAD_dsi_host_pkt_rx_payload_MASK) - -/*! @name DSI_HOST_PKT_RX_PKT_HEADER - DSI_HOST_PKT_RX_PKT_HEADER */ -#define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_MASK (0xFFFFFFU) -#define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_PKT_RX_PKT_HEADER_dsi_host_pkt_rx_pkt_header_MASK) - -/*! @name DSI_HOST_IRQ_STATUS - DSI_HOST_IRQ_STATUS */ -#define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_MASK (0xFFFFFFFFU) -#define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS_dsi_host_irq_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS_dsi_host_irq_status_MASK) - -/*! @name DSI_HOST_IRQ_STATUS2 - DSI_HOST_IRQ_STATUS2 */ -#define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_MASK (0x7U) -#define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_STATUS2_dsi_host_irq_status2_MASK) - -/*! @name DSI_HOST_IRQ_MASK - DSI_HOST_IRQ_MASK */ -#define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_MASK (0xFFFFFFFFU) -#define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK_dsi_host_irq_mask(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_MASK_dsi_host_irq_mask_MASK) - -/*! @name DSI_HOST_IRQ_MASK2 - DSI_HOST_IRQ_MASK2 */ -#define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_MASK (0x7U) -#define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_SHIFT (0U) -#define MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_SHIFT)) & MIPI_DSI_HOST_DSI_HOST_IRQ_MASK2_dsi_host_irq_mask2_MASK) - -/*! @name DPHY_PD_TX - DPHY_PD_TX */ -#define MIPI_DSI_HOST_DPHY_PD_TX_dphy_pd_tx_MASK (0x1U) -#define MIPI_DSI_HOST_DPHY_PD_TX_dphy_pd_tx_SHIFT (0U) -#define MIPI_DSI_HOST_DPHY_PD_TX_dphy_pd_tx(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_PD_TX_dphy_pd_tx_SHIFT)) & MIPI_DSI_HOST_DPHY_PD_TX_dphy_pd_tx_MASK) - -/*! @name DPHY_M_PRG_HS_PREPARE - DPHY_M_PRG_HS_PREPARE */ -#define MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_MASK (0x3U) -#define MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_SHIFT (0U) -#define MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_SHIFT)) & MIPI_DSI_HOST_DPHY_M_PRG_HS_PREPARE_dphy_m_prg_hs_prepare_MASK) - -/*! @name DPHY_MC_PRG_HS_PREPARE - DPHY_MC_PRG_HS_PREPARE */ -#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_MASK (0x1U) -#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_SHIFT (0U) -#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_SHIFT)) & MIPI_DSI_HOST_DPHY_MC_PRG_HS_PREPARE_dphy_mc_prg_hs_prepare_MASK) - -/*! @name DPHY_M_PRG_HS_ZERO - DPHY_M_PRG_HS_ZERO */ -#define MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_MASK (0x1FU) -#define MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_SHIFT (0U) -#define MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_SHIFT)) & MIPI_DSI_HOST_DPHY_M_PRG_HS_ZERO_dphy_m_prg_hs_zero_MASK) - -/*! @name DPHY_MC_PRG_HS_ZERO - DPHY_MC_PRG_HS_ZERO */ -#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_MASK (0x3FU) -#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_SHIFT (0U) -#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_SHIFT)) & MIPI_DSI_HOST_DPHY_MC_PRG_HS_ZERO_dphy_mc_prg_hs_zero_MASK) - -/*! @name DPHY_M_PRG_HS_TRAIL - DPHY_M_PRG_HS_TRAIL */ -#define MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_MASK (0xFU) -#define MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_SHIFT (0U) -#define MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_SHIFT)) & MIPI_DSI_HOST_DPHY_M_PRG_HS_TRAIL_dphy_m_prg_hs_trail_MASK) - -/*! @name DPHY_MC_PRG_HS_TRAIL - DPHY_MC_PRG_HS_TRAIL */ -#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_MASK (0xFU) -#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_SHIFT (0U) -#define MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_SHIFT)) & MIPI_DSI_HOST_DPHY_MC_PRG_HS_TRAIL_dphy_mc_prg_hs_trail_MASK) - -/*! @name DPHY_PD_PLL - DPHY_PD_PLL */ -#define MIPI_DSI_HOST_DPHY_PD_PLL_dphy_pd_pll_MASK (0x1U) -#define MIPI_DSI_HOST_DPHY_PD_PLL_dphy_pd_pll_SHIFT (0U) -#define MIPI_DSI_HOST_DPHY_PD_PLL_dphy_pd_pll(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_PD_PLL_dphy_pd_pll_SHIFT)) & MIPI_DSI_HOST_DPHY_PD_PLL_dphy_pd_pll_MASK) - -/*! @name DPHY_TST - DPHY_TST */ -#define MIPI_DSI_HOST_DPHY_TST_dphy_tst_MASK (0x3FU) -#define MIPI_DSI_HOST_DPHY_TST_dphy_tst_SHIFT (0U) -#define MIPI_DSI_HOST_DPHY_TST_dphy_tst(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_TST_dphy_tst_SHIFT)) & MIPI_DSI_HOST_DPHY_TST_dphy_tst_MASK) - -/*! @name DPHY_CN - DPHY_CN */ -#define MIPI_DSI_HOST_DPHY_CN_dphy_cn_MASK (0x1FU) -#define MIPI_DSI_HOST_DPHY_CN_dphy_cn_SHIFT (0U) -#define MIPI_DSI_HOST_DPHY_CN_dphy_cn(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_CN_dphy_cn_SHIFT)) & MIPI_DSI_HOST_DPHY_CN_dphy_cn_MASK) - -/*! @name DPHY_CM - DPHY_CM */ -#define MIPI_DSI_HOST_DPHY_CM_dphy_cm_MASK (0xFFU) -#define MIPI_DSI_HOST_DPHY_CM_dphy_cm_SHIFT (0U) -#define MIPI_DSI_HOST_DPHY_CM_dphy_cm(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_CM_dphy_cm_SHIFT)) & MIPI_DSI_HOST_DPHY_CM_dphy_cm_MASK) - -/*! @name DPHY_CO - DPHY_CO */ -#define MIPI_DSI_HOST_DPHY_CO_dphy_co_MASK (0x3U) -#define MIPI_DSI_HOST_DPHY_CO_dphy_co_SHIFT (0U) -#define MIPI_DSI_HOST_DPHY_CO_dphy_co(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_CO_dphy_co_SHIFT)) & MIPI_DSI_HOST_DPHY_CO_dphy_co_MASK) - -/*! @name DPHY_LOCK - DPHY_LOCK */ -#define MIPI_DSI_HOST_DPHY_LOCK_dphy_lock_MASK (0x1U) -#define MIPI_DSI_HOST_DPHY_LOCK_dphy_lock_SHIFT (0U) -#define MIPI_DSI_HOST_DPHY_LOCK_dphy_lock(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_LOCK_dphy_lock_SHIFT)) & MIPI_DSI_HOST_DPHY_LOCK_dphy_lock_MASK) - -/*! @name DPHY_LOCK_BYP - DPHY_LOCK_BYP */ -#define MIPI_DSI_HOST_DPHY_LOCK_BYP_dphy_lock_byp_MASK (0x1U) -#define MIPI_DSI_HOST_DPHY_LOCK_BYP_dphy_lock_byp_SHIFT (0U) -#define MIPI_DSI_HOST_DPHY_LOCK_BYP_dphy_lock_byp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_LOCK_BYP_dphy_lock_byp_SHIFT)) & MIPI_DSI_HOST_DPHY_LOCK_BYP_dphy_lock_byp_MASK) - -/*! @name DPHY_TX_RCAL - DPHY_TX_RCAL */ -#define MIPI_DSI_HOST_DPHY_TX_RCAL_dphy_tx_rcal_MASK (0x3U) -#define MIPI_DSI_HOST_DPHY_TX_RCAL_dphy_tx_rcal_SHIFT (0U) -#define MIPI_DSI_HOST_DPHY_TX_RCAL_dphy_tx_rcal(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_TX_RCAL_dphy_tx_rcal_SHIFT)) & MIPI_DSI_HOST_DPHY_TX_RCAL_dphy_tx_rcal_MASK) - -/*! @name DPHY_AUTO_PD_EN - DPHY_AUTO_PD_EN */ -#define MIPI_DSI_HOST_DPHY_AUTO_PD_EN_dphy_auto_pd_en_MASK (0x1U) -#define MIPI_DSI_HOST_DPHY_AUTO_PD_EN_dphy_auto_pd_en_SHIFT (0U) -#define MIPI_DSI_HOST_DPHY_AUTO_PD_EN_dphy_auto_pd_en(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_AUTO_PD_EN_dphy_auto_pd_en_SHIFT)) & MIPI_DSI_HOST_DPHY_AUTO_PD_EN_dphy_auto_pd_en_MASK) - -/*! @name DPHY_RXLPRP - DPHY_RXLPRP */ -#define MIPI_DSI_HOST_DPHY_RXLPRP_dphy_rxlprp_MASK (0x3U) -#define MIPI_DSI_HOST_DPHY_RXLPRP_dphy_rxlprp_SHIFT (0U) -#define MIPI_DSI_HOST_DPHY_RXLPRP_dphy_rxlprp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_RXLPRP_dphy_rxlprp_SHIFT)) & MIPI_DSI_HOST_DPHY_RXLPRP_dphy_rxlprp_MASK) - -/*! @name DPHY_RXCDRP - DPHY_RXCDRP */ -#define MIPI_DSI_HOST_DPHY_RXCDRP_dphy_rxcdrp_MASK (0x3U) -#define MIPI_DSI_HOST_DPHY_RXCDRP_dphy_rxcdrp_SHIFT (0U) -#define MIPI_DSI_HOST_DPHY_RXCDRP_dphy_rxcdrp(x) (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_HOST_DPHY_RXCDRP_dphy_rxcdrp_SHIFT)) & MIPI_DSI_HOST_DPHY_RXCDRP_dphy_rxcdrp_MASK) +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP_MASK (0x3U) +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP_SHIFT (0U) +/*! RXCDRP - DPHY RXCDRP input + * 0b00..344mV + * 0b01..325mV (Default) + * 0b10..307mV + * 0b11..Invalid + */ +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP_MASK) +/*! @} */ /*! * @} - */ /* end of group MIPI_DSI_HOST_Register_Masks */ + */ /* end of group DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Register_Masks */ -/* MIPI_DSI_HOST - Peripheral instance base addresses */ -/** Peripheral MIPI_DSI_HOST base address */ -#define MIPI_DSI_HOST_BASE (0x4080C000U) -/** Peripheral MIPI_DSI_HOST base pointer */ -#define MIPI_DSI_HOST ((MIPI_DSI_HOST_Type *)MIPI_DSI_HOST_BASE) -/** Array initializer of MIPI_DSI_HOST peripheral base addresses */ -#define MIPI_DSI_HOST_BASE_ADDRS { MIPI_DSI_HOST_BASE} -/** Array initializer of MIPI_DSI_HOST peripheral base pointers */ -#define MIPI_DSI_HOST_BASE_PTRS { MIPI_DSI_HOST} +/* DSI_HOST_NXP_FDSOI28_DPHY_INTFC - Peripheral instance base addresses */ +/** Peripheral MIPI_DSI__DSI_HOST_DPHY_INTFC base address */ +#define MIPI_DSI__DSI_HOST_DPHY_INTFC_BASE (0x4080C300u) +/** Peripheral MIPI_DSI__DSI_HOST_DPHY_INTFC base pointer */ +#define MIPI_DSI__DSI_HOST_DPHY_INTFC ((DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type *)MIPI_DSI__DSI_HOST_DPHY_INTFC_BASE) +/** Array initializer of DSI_HOST_NXP_FDSOI28_DPHY_INTFC peripheral base + * addresses */ +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_BASE_ADDRS { MIPI_DSI__DSI_HOST_DPHY_INTFC_BASE } +/** Array initializer of DSI_HOST_NXP_FDSOI28_DPHY_INTFC peripheral base + * pointers */ +#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_BASE_PTRS { MIPI_DSI__DSI_HOST_DPHY_INTFC } /*! * @} - */ /* end of group MIPI_DSI_HOST_Peripheral_Access_Layer */ + */ /* end of group DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- @@ -26749,6 +33531,7 @@ typedef struct { /*! @name VER_ID - Version ID Register */ /*! @{ */ + #define EMVSIM_VER_ID_VER_MASK (0xFFFFFFFFU) #define EMVSIM_VER_ID_VER_SHIFT (0U) /*! VER - Version ID of the module @@ -26758,11 +33541,13 @@ typedef struct { /*! @name PARAM - Parameter Register */ /*! @{ */ + #define EMVSIM_PARAM_RX_FIFO_DEPTH_MASK (0xFFU) #define EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT (0U) /*! RX_FIFO_DEPTH - Receive FIFO Depth */ #define EMVSIM_PARAM_RX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK) + #define EMVSIM_PARAM_TX_FIFO_DEPTH_MASK (0xFF00U) #define EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT (8U) /*! TX_FIFO_DEPTH - Transmit FIFO Depth @@ -26772,25 +33557,27 @@ typedef struct { /*! @name CLKCFG - Clock Configuration Register */ /*! @{ */ + #define EMVSIM_CLKCFG_CLK_PRSC_MASK (0xFFU) #define EMVSIM_CLKCFG_CLK_PRSC_SHIFT (0U) /*! CLK_PRSC - Clock Prescaler Value - * 0b00000010..Divide by 2 */ #define EMVSIM_CLKCFG_CLK_PRSC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_CLK_PRSC_SHIFT)) & EMVSIM_CLKCFG_CLK_PRSC_MASK) + #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK (0x300U) #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT (8U) /*! GPCNT1_CLK_SEL - General Purpose Counter 1 Clock Select - * 0b00..Disabled / Reset (default) + * 0b00..Disabled / Reset * 0b01..Card Clock * 0b10..Receive Clock * 0b11..ETU Clock (transmit clock) */ #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK) + #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK (0xC00U) #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT (10U) /*! GPCNT0_CLK_SEL - General Purpose Counter 0 Clock Select - * 0b00..Disabled / Reset (default) + * 0b00..Disabled / Reset * 0b01..Card Clock * 0b10..Receive Clock * 0b11..ETU Clock (transmit clock) @@ -26800,175 +33587,199 @@ typedef struct { /*! @name DIVISOR - Baud Rate Divisor Register */ /*! @{ */ + #define EMVSIM_DIVISOR_DIVISOR_VALUE_MASK (0x1FFU) #define EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT (0U) /*! DIVISOR_VALUE - Divisor (F/D) Value * 0b000000000-0b000000100..Invalid. As per ISO 7816 specification, minimum value of F/D is 5 - * 0b101110100..Divisor value for F = 372 and D = 1 (default) + * 0b000000101-0b011111111..Divisor value F/D */ #define EMVSIM_DIVISOR_DIVISOR_VALUE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT)) & EMVSIM_DIVISOR_DIVISOR_VALUE_MASK) /*! @} */ /*! @name CTRL - Control Register */ /*! @{ */ + #define EMVSIM_CTRL_IC_MASK (0x1U) #define EMVSIM_CTRL_IC_SHIFT (0U) /*! IC - Inverse Convention - * 0b0..Direction convention transfers enabled (default) + * 0b0..Direction convention transfers enabled * 0b1..Inverse convention transfers enabled */ #define EMVSIM_CTRL_IC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_IC_SHIFT)) & EMVSIM_CTRL_IC_MASK) + #define EMVSIM_CTRL_ICM_MASK (0x2U) #define EMVSIM_CTRL_ICM_SHIFT (1U) /*! ICM - Initial Character Mode * 0b0..Initial Character Mode disabled - * 0b1..Initial Character Mode enabled (default) + * 0b1..Initial Character Mode enabled */ #define EMVSIM_CTRL_ICM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ICM_SHIFT)) & EMVSIM_CTRL_ICM_MASK) + #define EMVSIM_CTRL_ANACK_MASK (0x4U) #define EMVSIM_CTRL_ANACK_SHIFT (2U) /*! ANACK - Auto NACK Enable * 0b0..NACK generation on errors disabled - * 0b1..NACK generation on errors enabled (default) + * 0b1..NACK generation on errors enabled */ #define EMVSIM_CTRL_ANACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ANACK_SHIFT)) & EMVSIM_CTRL_ANACK_MASK) + #define EMVSIM_CTRL_ONACK_MASK (0x8U) #define EMVSIM_CTRL_ONACK_SHIFT (3U) /*! ONACK - Overrun NACK Enable - * 0b0..NACK generation on overrun is disabled (default) + * 0b0..NACK generation on overrun is disabled * 0b1..NACK generation on overrun is enabled */ #define EMVSIM_CTRL_ONACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ONACK_SHIFT)) & EMVSIM_CTRL_ONACK_MASK) + #define EMVSIM_CTRL_FLSH_RX_MASK (0x100U) #define EMVSIM_CTRL_FLSH_RX_SHIFT (8U) /*! FLSH_RX - Flush Receiver Bit - * 0b0..EMV SIM Receiver normal operation (default) - * 0b1..EMV SIM Receiver held in Reset + * 0b0..EMVSIM Receiver normal operation + * 0b1..EMVSIM Receiver held in Reset */ #define EMVSIM_CTRL_FLSH_RX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_RX_SHIFT)) & EMVSIM_CTRL_FLSH_RX_MASK) + #define EMVSIM_CTRL_FLSH_TX_MASK (0x200U) #define EMVSIM_CTRL_FLSH_TX_SHIFT (9U) /*! FLSH_TX - Flush Transmitter Bit - * 0b0..EMV SIM Transmitter normal operation (default) - * 0b1..EMV SIM Transmitter held in Reset + * 0b0..EMVSIM Transmitter normal operation + * 0b1..EMVSIM Transmitter held in Reset */ #define EMVSIM_CTRL_FLSH_TX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_TX_SHIFT)) & EMVSIM_CTRL_FLSH_TX_MASK) + #define EMVSIM_CTRL_SW_RST_MASK (0x400U) #define EMVSIM_CTRL_SW_RST_SHIFT (10U) /*! SW_RST - Software Reset Bit - * 0b0..EMV SIM Normal operation (default) - * 0b1..EMV SIM held in Reset + * 0b0..EMVSIM Normal operation + * 0b1..EMVSIM held in Reset */ #define EMVSIM_CTRL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_SW_RST_SHIFT)) & EMVSIM_CTRL_SW_RST_MASK) + #define EMVSIM_CTRL_KILL_CLOCKS_MASK (0x800U) #define EMVSIM_CTRL_KILL_CLOCKS_SHIFT (11U) /*! KILL_CLOCKS - Kill all internal clocks - * 0b0..EMV SIM input clock enabled (default) - * 0b1..EMV SIM input clock is disabled + * 0b0..EMVSIM input clock enabled + * 0b1..EMVSIM input clock is disabled */ #define EMVSIM_CTRL_KILL_CLOCKS(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_KILL_CLOCKS_SHIFT)) & EMVSIM_CTRL_KILL_CLOCKS_MASK) + #define EMVSIM_CTRL_DOZE_EN_MASK (0x1000U) #define EMVSIM_CTRL_DOZE_EN_SHIFT (12U) /*! DOZE_EN - Doze Enable - * 0b0..DOZE instruction will gate all internal EMV SIM clocks as well as the Smart Card clock when the transmit FIFO is empty (default) - * 0b1..DOZE instruction has no effect on EMV SIM module + * 0b0..DOZE instruction gates all internal EMVSIM clocks as well as the Smart Card clock when the transmit FIFO is empty + * 0b1..DOZE instruction has no effect on EMVSIM module */ #define EMVSIM_CTRL_DOZE_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_DOZE_EN_SHIFT)) & EMVSIM_CTRL_DOZE_EN_MASK) + #define EMVSIM_CTRL_STOP_EN_MASK (0x2000U) #define EMVSIM_CTRL_STOP_EN_SHIFT (13U) /*! STOP_EN - STOP Enable - * 0b0..STOP instruction shuts down all EMV SIM clocks (default) + * 0b0..STOP instruction shuts down all EMVSIM clocks * 0b1..STOP instruction shuts down all clocks except for the Smart Card Clock (SCK) (clock provided to Smart Card) */ #define EMVSIM_CTRL_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_STOP_EN_SHIFT)) & EMVSIM_CTRL_STOP_EN_MASK) + #define EMVSIM_CTRL_RCV_EN_MASK (0x10000U) #define EMVSIM_CTRL_RCV_EN_SHIFT (16U) /*! RCV_EN - Receiver Enable - * 0b0..EMV SIM Receiver disabled (default) - * 0b1..EMV SIM Receiver enabled + * 0b0..EMVSIM Receiver disabled + * 0b1..EMVSIM Receiver enabled */ #define EMVSIM_CTRL_RCV_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCV_EN_SHIFT)) & EMVSIM_CTRL_RCV_EN_MASK) + #define EMVSIM_CTRL_XMT_EN_MASK (0x20000U) #define EMVSIM_CTRL_XMT_EN_SHIFT (17U) /*! XMT_EN - Transmitter Enable - * 0b0..EMV SIM Transmitter disabled (default) - * 0b1..EMV SIM Transmitter enabled + * 0b0..EMVSIM Transmitter disabled + * 0b1..EMVSIM Transmitter enabled */ #define EMVSIM_CTRL_XMT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_EN_SHIFT)) & EMVSIM_CTRL_XMT_EN_MASK) + #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) #define EMVSIM_CTRL_RCVR_11_SHIFT (18U) /*! RCVR_11 - Receiver 11 ETU Mode Enable - * 0b0..Receiver configured for 12 ETU operation mode (default) + * 0b0..Receiver configured for 12 ETU operation mode * 0b1..Receiver configured for 11 ETU operation mode */ #define EMVSIM_CTRL_RCVR_11(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK) + #define EMVSIM_CTRL_RX_DMA_EN_MASK (0x80000U) #define EMVSIM_CTRL_RX_DMA_EN_SHIFT (19U) /*! RX_DMA_EN - Receive DMA Enable - * 0b0..No DMA Read Request asserted for Receiver (default) + * 0b0..No DMA Read Request asserted for Receiver * 0b1..DMA Read Request asserted for Receiver */ #define EMVSIM_CTRL_RX_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RX_DMA_EN_SHIFT)) & EMVSIM_CTRL_RX_DMA_EN_MASK) + #define EMVSIM_CTRL_TX_DMA_EN_MASK (0x100000U) #define EMVSIM_CTRL_TX_DMA_EN_SHIFT (20U) /*! TX_DMA_EN - Transmit DMA Enable - * 0b0..No DMA Write Request asserted for Transmitter (default) + * 0b0..No DMA Write Request asserted for Transmitter * 0b1..DMA Write Request asserted for Transmitter */ #define EMVSIM_CTRL_TX_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_TX_DMA_EN_SHIFT)) & EMVSIM_CTRL_TX_DMA_EN_MASK) + #define EMVSIM_CTRL_INV_CRC_VAL_MASK (0x1000000U) #define EMVSIM_CTRL_INV_CRC_VAL_SHIFT (24U) /*! INV_CRC_VAL - Invert bits in the CRC Output Value - * 0b0..Bits in CRC Output value will not be inverted. - * 0b1..Bits in CRC Output value will be inverted. (default) + * 0b0..Bits in CRC Output value are not inverted. + * 0b1..Bits in CRC Output value are inverted. */ #define EMVSIM_CTRL_INV_CRC_VAL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_INV_CRC_VAL_SHIFT)) & EMVSIM_CTRL_INV_CRC_VAL_MASK) + #define EMVSIM_CTRL_CRC_OUT_FLIP_MASK (0x2000000U) #define EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT (25U) /*! CRC_OUT_FLIP - CRC Output Value Bit Reversal or Flip - * 0b0..Bits within the CRC output bytes will not be reversed i.e. 15:0 will remain 15:0 (default) - * 0b1..Bits within the CRC output bytes will be reversed i.e. 15:0 will become {8:15,0:7} + * 0b0..Bits within the CRC output bytes are not reversed i.e. 15:0 remains 15:0 + * 0b1..Bits within the CRC output bytes are reversed i.e. 15:0 becomes {8:15,0:7} */ #define EMVSIM_CTRL_CRC_OUT_FLIP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_OUT_FLIP_MASK) + #define EMVSIM_CTRL_CRC_IN_FLIP_MASK (0x4000000U) #define EMVSIM_CTRL_CRC_IN_FLIP_SHIFT (26U) /*! CRC_IN_FLIP - CRC Input Byte's Bit Reversal or Flip Control - * 0b0..Bits in the input byte will not be reversed (i.e. 7:0 will remain 7:0) before the CRC calculation (default) - * 0b1..Bits in the input byte will be reversed (i.e. 7:0 will become 0:7) before CRC calculation + * 0b0..Bits in the input byte are not reversed (i.e. 7:0 remain 7:0) before the CRC calculation + * 0b1..Bits in the input byte are reversed (i.e. 7:0 becomes 0:7) before CRC calculation */ #define EMVSIM_CTRL_CRC_IN_FLIP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_IN_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_IN_FLIP_MASK) + #define EMVSIM_CTRL_CWT_EN_MASK (0x8000000U) #define EMVSIM_CTRL_CWT_EN_SHIFT (27U) /*! CWT_EN - Character Wait Time Counter Enable - * 0b0..Character Wait time Counter is disabled (default) + * 0b0..Character Wait time Counter is disabled * 0b1..Character Wait time counter is enabled */ #define EMVSIM_CTRL_CWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CWT_EN_SHIFT)) & EMVSIM_CTRL_CWT_EN_MASK) + #define EMVSIM_CTRL_LRC_EN_MASK (0x10000000U) #define EMVSIM_CTRL_LRC_EN_SHIFT (28U) /*! LRC_EN - LRC Enable - * 0b0..8-bit Linear Redundancy Checking disabled (default) + * 0b0..8-bit Linear Redundancy Checking disabled * 0b1..8-bit Linear Redundancy Checking enabled */ #define EMVSIM_CTRL_LRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_LRC_EN_SHIFT)) & EMVSIM_CTRL_LRC_EN_MASK) + #define EMVSIM_CTRL_CRC_EN_MASK (0x20000000U) #define EMVSIM_CTRL_CRC_EN_SHIFT (29U) /*! CRC_EN - CRC Enable - * 0b0..16-bit Cyclic Redundancy Checking disabled (default) + * 0b0..16-bit Cyclic Redundancy Checking disabled * 0b1..16-bit Cyclic Redundancy Checking enabled */ #define EMVSIM_CTRL_CRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_EN_SHIFT)) & EMVSIM_CTRL_CRC_EN_MASK) + #define EMVSIM_CTRL_XMT_CRC_LRC_MASK (0x40000000U) #define EMVSIM_CTRL_XMT_CRC_LRC_SHIFT (30U) /*! XMT_CRC_LRC - Transmit CRC or LRC Enable - * 0b0..No CRC or LRC value is transmitted (default) + * 0b0..No CRC or LRC value is transmitted * 0b1..Transmit LRC or CRC info when FIFO empties (whichever is enabled) */ #define EMVSIM_CTRL_XMT_CRC_LRC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_CRC_LRC_SHIFT)) & EMVSIM_CTRL_XMT_CRC_LRC_MASK) + #define EMVSIM_CTRL_BWT_EN_MASK (0x80000000U) #define EMVSIM_CTRL_BWT_EN_SHIFT (31U) /*! BWT_EN - Block Wait Time Counter Enable - * 0b0..Disable BWT, BGT Counters (default) + * 0b0..Disable BWT, BGT Counters * 0b1..Enable BWT, BGT Counters */ #define EMVSIM_CTRL_BWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_BWT_EN_SHIFT)) & EMVSIM_CTRL_BWT_EN_MASK) @@ -26976,163 +33787,179 @@ typedef struct { /*! @name INT_MASK - Interrupt Mask Register */ /*! @{ */ + #define EMVSIM_INT_MASK_RDT_IM_MASK (0x1U) #define EMVSIM_INT_MASK_RDT_IM_SHIFT (0U) /*! RDT_IM - Receive Data Threshold Interrupt Mask * 0b0..RDTF interrupt enabled - * 0b1..RDTF interrupt masked (default) + * 0b1..RDTF interrupt masked */ #define EMVSIM_INT_MASK_RDT_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RDT_IM_SHIFT)) & EMVSIM_INT_MASK_RDT_IM_MASK) + #define EMVSIM_INT_MASK_TC_IM_MASK (0x2U) #define EMVSIM_INT_MASK_TC_IM_SHIFT (1U) /*! TC_IM - Transmit Complete Interrupt Mask * 0b0..TCF interrupt enabled - * 0b1..TCF interrupt masked (default) + * 0b1..TCF interrupt masked */ #define EMVSIM_INT_MASK_TC_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TC_IM_SHIFT)) & EMVSIM_INT_MASK_TC_IM_MASK) + #define EMVSIM_INT_MASK_RFO_IM_MASK (0x4U) #define EMVSIM_INT_MASK_RFO_IM_SHIFT (2U) /*! RFO_IM - Receive FIFO Overflow Interrupt Mask * 0b0..RFO interrupt enabled - * 0b1..RFO interrupt masked (default) + * 0b1..RFO interrupt masked */ #define EMVSIM_INT_MASK_RFO_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RFO_IM_SHIFT)) & EMVSIM_INT_MASK_RFO_IM_MASK) + #define EMVSIM_INT_MASK_ETC_IM_MASK (0x8U) #define EMVSIM_INT_MASK_ETC_IM_SHIFT (3U) /*! ETC_IM - Early Transmit Complete Interrupt Mask * 0b0..ETC interrupt enabled - * 0b1..ETC interrupt masked (default) + * 0b1..ETC interrupt masked */ #define EMVSIM_INT_MASK_ETC_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_ETC_IM_SHIFT)) & EMVSIM_INT_MASK_ETC_IM_MASK) + #define EMVSIM_INT_MASK_TFE_IM_MASK (0x10U) #define EMVSIM_INT_MASK_TFE_IM_SHIFT (4U) /*! TFE_IM - Transmit FIFO Empty Interrupt Mask * 0b0..TFE interrupt enabled - * 0b1..TFE interrupt masked (default) + * 0b1..TFE interrupt masked */ #define EMVSIM_INT_MASK_TFE_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFE_IM_SHIFT)) & EMVSIM_INT_MASK_TFE_IM_MASK) + #define EMVSIM_INT_MASK_TNACK_IM_MASK (0x20U) #define EMVSIM_INT_MASK_TNACK_IM_SHIFT (5U) /*! TNACK_IM - Transmit NACK Threshold Interrupt Mask * 0b0..TNTE interrupt enabled - * 0b1..TNTE interrupt masked (default) + * 0b1..TNTE interrupt masked */ #define EMVSIM_INT_MASK_TNACK_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TNACK_IM_SHIFT)) & EMVSIM_INT_MASK_TNACK_IM_MASK) + #define EMVSIM_INT_MASK_TFF_IM_MASK (0x40U) #define EMVSIM_INT_MASK_TFF_IM_SHIFT (6U) /*! TFF_IM - Transmit FIFO Full Interrupt Mask * 0b0..TFF interrupt enabled - * 0b1..TFF interrupt masked (default) + * 0b1..TFF interrupt masked */ #define EMVSIM_INT_MASK_TFF_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFF_IM_SHIFT)) & EMVSIM_INT_MASK_TFF_IM_MASK) + #define EMVSIM_INT_MASK_TDT_IM_MASK (0x80U) #define EMVSIM_INT_MASK_TDT_IM_SHIFT (7U) /*! TDT_IM - Transmit Data Threshold Interrupt Mask * 0b0..TDTF interrupt enabled - * 0b1..TDTF interrupt masked (default) + * 0b1..TDTF interrupt masked */ #define EMVSIM_INT_MASK_TDT_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TDT_IM_SHIFT)) & EMVSIM_INT_MASK_TDT_IM_MASK) + #define EMVSIM_INT_MASK_GPCNT0_IM_MASK (0x100U) #define EMVSIM_INT_MASK_GPCNT0_IM_SHIFT (8U) /*! GPCNT0_IM - General Purpose Timer 0 Timeout Interrupt Mask * 0b0..GPCNT0_TO interrupt enabled - * 0b1..GPCNT0_TO interrupt masked (default) + * 0b1..GPCNT0_TO interrupt masked */ #define EMVSIM_INT_MASK_GPCNT0_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT0_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT0_IM_MASK) + #define EMVSIM_INT_MASK_CWT_ERR_IM_MASK (0x200U) #define EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT (9U) /*! CWT_ERR_IM - Character Wait Time Error Interrupt Mask * 0b0..CWT_ERR interrupt enabled - * 0b1..CWT_ERR interrupt masked (default) + * 0b1..CWT_ERR interrupt masked */ #define EMVSIM_INT_MASK_CWT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_CWT_ERR_IM_MASK) + #define EMVSIM_INT_MASK_RNACK_IM_MASK (0x400U) #define EMVSIM_INT_MASK_RNACK_IM_SHIFT (10U) /*! RNACK_IM - Receiver NACK Threshold Interrupt Mask * 0b0..RTE interrupt enabled - * 0b1..RTE interrupt masked (default) + * 0b1..RTE interrupt masked */ #define EMVSIM_INT_MASK_RNACK_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RNACK_IM_SHIFT)) & EMVSIM_INT_MASK_RNACK_IM_MASK) + #define EMVSIM_INT_MASK_BWT_ERR_IM_MASK (0x800U) #define EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT (11U) /*! BWT_ERR_IM - Block Wait Time Error Interrupt Mask * 0b0..BWT_ERR interrupt enabled - * 0b1..BWT_ERR interrupt masked (default) + * 0b1..BWT_ERR interrupt masked */ #define EMVSIM_INT_MASK_BWT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BWT_ERR_IM_MASK) + #define EMVSIM_INT_MASK_BGT_ERR_IM_MASK (0x1000U) #define EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT (12U) /*! BGT_ERR_IM - Block Guard Time Error Interrupt * 0b0..BGT_ERR interrupt enabled - * 0b1..BGT_ERR interrupt masked (default) + * 0b1..BGT_ERR interrupt masked */ #define EMVSIM_INT_MASK_BGT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BGT_ERR_IM_MASK) + #define EMVSIM_INT_MASK_GPCNT1_IM_MASK (0x2000U) #define EMVSIM_INT_MASK_GPCNT1_IM_SHIFT (13U) /*! GPCNT1_IM - General Purpose Counter 1 Timeout Interrupt Mask * 0b0..GPCNT1_TO interrupt enabled - * 0b1..GPCNT1_TO interrupt masked (default) + * 0b1..GPCNT1_TO interrupt masked */ #define EMVSIM_INT_MASK_GPCNT1_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT1_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT1_IM_MASK) + #define EMVSIM_INT_MASK_RX_DATA_IM_MASK (0x4000U) #define EMVSIM_INT_MASK_RX_DATA_IM_SHIFT (14U) /*! RX_DATA_IM - Receive Data Interrupt Mask * 0b0..RX_DATA interrupt enabled - * 0b1..RX_DATA interrupt masked (default) + * 0b1..RX_DATA interrupt masked */ #define EMVSIM_INT_MASK_RX_DATA_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RX_DATA_IM_SHIFT)) & EMVSIM_INT_MASK_RX_DATA_IM_MASK) + #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) #define EMVSIM_INT_MASK_PEF_IM_SHIFT (15U) /*! PEF_IM - Parity Error Interrupt Mask * 0b0..PEF interrupt enabled - * 0b1..PEF interrupt masked (default) + * 0b1..PEF interrupt masked */ #define EMVSIM_INT_MASK_PEF_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK) /*! @} */ /*! @name RX_THD - Receiver Threshold Register */ /*! @{ */ + #define EMVSIM_RX_THD_RDT_MASK (0xFU) #define EMVSIM_RX_THD_RDT_SHIFT (0U) /*! RDT - Receiver Data Threshold Value */ #define EMVSIM_RX_THD_RDT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK) + #define EMVSIM_RX_THD_RNCK_THD_MASK (0xF00U) #define EMVSIM_RX_THD_RNCK_THD_SHIFT (8U) /*! RNCK_THD - Receiver NACK Threshold Value - * 0b0000..Zero Threshold. RTE will not be set */ #define EMVSIM_RX_THD_RNCK_THD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RNCK_THD_SHIFT)) & EMVSIM_RX_THD_RNCK_THD_MASK) /*! @} */ /*! @name TX_THD - Transmitter Threshold Register */ /*! @{ */ + #define EMVSIM_TX_THD_TDT_MASK (0xFU) #define EMVSIM_TX_THD_TDT_SHIFT (0U) /*! TDT - Transmitter Data Threshold Value */ #define EMVSIM_TX_THD_TDT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TDT_SHIFT)) & EMVSIM_TX_THD_TDT_MASK) + #define EMVSIM_TX_THD_TNCK_THD_MASK (0xF00U) #define EMVSIM_TX_THD_TNCK_THD_SHIFT (8U) /*! TNCK_THD - Transmitter NACK Threshold Value - * 0b0000..TNTE will never be set; retransmission after NACK reception is disabled. - * 0b0001..TNTE will be set after 1 nack is received; 0 retransmissions occurs. - * 0b0010..TNTE will be set after 2 nacks are received; at most 1 retransmission occurs. - * 0b0011..TNTE will be set after 3 nacks are received; at most 2 retransmissions occurs. - * 0b1111..TNTE will be set after 15 nacks are received; at most 14 retransmissions occurs. */ #define EMVSIM_TX_THD_TNCK_THD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TNCK_THD_SHIFT)) & EMVSIM_TX_THD_TNCK_THD_MASK) /*! @} */ /*! @name RX_STATUS - Receive Status Register */ /*! @{ */ + #define EMVSIM_RX_STATUS_RFO_MASK (0x1U) #define EMVSIM_RX_STATUS_RFO_SHIFT (0U) /*! RFO - Receive FIFO Overflow Flag - * 0b0..No overrun error has occurred (default) + * 0b0..No overrun error has occurred * 0b1..A byte was received when the received FIFO was already full */ #define EMVSIM_RX_STATUS_RFO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RFO_SHIFT)) & EMVSIM_RX_STATUS_RFO_MASK) + #define EMVSIM_RX_STATUS_RX_DATA_MASK (0x10U) #define EMVSIM_RX_STATUS_RX_DATA_SHIFT (4U) /*! RX_DATA - Receive Data Interrupt Flag @@ -27140,13 +33967,15 @@ typedef struct { * 0b1..New byte is received ans stored in Receive FIFO */ #define EMVSIM_RX_STATUS_RX_DATA(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_DATA_SHIFT)) & EMVSIM_RX_STATUS_RX_DATA_MASK) + #define EMVSIM_RX_STATUS_RDTF_MASK (0x20U) #define EMVSIM_RX_STATUS_RDTF_SHIFT (5U) /*! RDTF - Receive Data Threshold Interrupt Flag - * 0b0..Number of unread bytes in receive FIFO less than the value set by RDT[3:0] (default). - * 0b1..Number of unread bytes in receive FIFO greater or than equal to value set by RDT[3:0]. + * 0b0..Number of unread bytes in receive FIFO less than the value set by RDT + * 0b1..Number of unread bytes in receive FIFO greater or than equal to value set by RDT. */ #define EMVSIM_RX_STATUS_RDTF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RDTF_SHIFT)) & EMVSIM_RX_STATUS_RDTF_MASK) + #define EMVSIM_RX_STATUS_LRC_OK_MASK (0x40U) #define EMVSIM_RX_STATUS_LRC_OK_SHIFT (6U) /*! LRC_OK - LRC Check OK Flag @@ -27154,6 +33983,7 @@ typedef struct { * 0b1..Current calculated LRC value matches the expected result (i.e. zero). */ #define EMVSIM_RX_STATUS_LRC_OK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_LRC_OK_SHIFT)) & EMVSIM_RX_STATUS_LRC_OK_MASK) + #define EMVSIM_RX_STATUS_CRC_OK_MASK (0x80U) #define EMVSIM_RX_STATUS_CRC_OK_SHIFT (7U) /*! CRC_OK - CRC Check OK Flag @@ -27161,20 +33991,23 @@ typedef struct { * 0b1..Current calculated CRC value matches the expected result. */ #define EMVSIM_RX_STATUS_CRC_OK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CRC_OK_SHIFT)) & EMVSIM_RX_STATUS_CRC_OK_MASK) + #define EMVSIM_RX_STATUS_CWT_ERR_MASK (0x100U) #define EMVSIM_RX_STATUS_CWT_ERR_SHIFT (8U) /*! CWT_ERR - Character Wait Time Error Flag - * 0b0..No CWT violation has occurred (default). - * 0b1..Time between two consecutive characters has exceeded the value in CHAR_WAIT. + * 0b0..No CWT violation has occurred + * 0b1..Time between two consecutive characters has exceeded the value in CWT_VAL. */ #define EMVSIM_RX_STATUS_CWT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_CWT_ERR_MASK) + #define EMVSIM_RX_STATUS_RTE_MASK (0x200U) #define EMVSIM_RX_STATUS_RTE_SHIFT (9U) /*! RTE - Received NACK Threshold Error Flag - * 0b0..Number of NACKs generated by the receiver is less than the value programmed in RTH[3:0] - * 0b1..Number of NACKs generated by the receiver is equal to the value programmed in RTH[3:0] + * 0b0..Number of NACKs generated by the receiver is less than the value programmed in RNCK_THD + * 0b1..Number of NACKs generated by the receiver is equal to the value programmed in RNCK_THD */ #define EMVSIM_RX_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RTE_SHIFT)) & EMVSIM_RX_STATUS_RTE_MASK) + #define EMVSIM_RX_STATUS_BWT_ERR_MASK (0x400U) #define EMVSIM_RX_STATUS_BWT_ERR_SHIFT (10U) /*! BWT_ERR - Block Wait Time Error Flag @@ -27182,6 +34015,7 @@ typedef struct { * 0b1..Block wait time was exceeded */ #define EMVSIM_RX_STATUS_BWT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BWT_ERR_MASK) + #define EMVSIM_RX_STATUS_BGT_ERR_MASK (0x800U) #define EMVSIM_RX_STATUS_BGT_ERR_SHIFT (11U) /*! BGT_ERR - Block Guard Time Error Flag @@ -27189,6 +34023,7 @@ typedef struct { * 0b1..Block guard time was too small */ #define EMVSIM_RX_STATUS_BGT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BGT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BGT_ERR_MASK) + #define EMVSIM_RX_STATUS_PEF_MASK (0x1000U) #define EMVSIM_RX_STATUS_PEF_SHIFT (12U) /*! PEF - Parity Error Flag @@ -27196,6 +34031,7 @@ typedef struct { * 0b1..Parity error detected */ #define EMVSIM_RX_STATUS_PEF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_PEF_SHIFT)) & EMVSIM_RX_STATUS_PEF_MASK) + #define EMVSIM_RX_STATUS_FEF_MASK (0x2000U) #define EMVSIM_RX_STATUS_FEF_SHIFT (13U) /*! FEF - Frame Error Flag @@ -27203,11 +34039,13 @@ typedef struct { * 0b1..Frame error detected */ #define EMVSIM_RX_STATUS_FEF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_FEF_SHIFT)) & EMVSIM_RX_STATUS_FEF_MASK) + #define EMVSIM_RX_STATUS_RX_WPTR_MASK (0xF0000U) #define EMVSIM_RX_STATUS_RX_WPTR_SHIFT (16U) /*! RX_WPTR - Receive FIFO Write Pointer Value */ #define EMVSIM_RX_STATUS_RX_WPTR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_WPTR_SHIFT)) & EMVSIM_RX_STATUS_RX_WPTR_MASK) + #define EMVSIM_RX_STATUS_RX_CNT_MASK (0xF000000U) #define EMVSIM_RX_STATUS_RX_CNT_SHIFT (24U) /*! RX_CNT - Receive FIFO Byte Count @@ -27218,67 +34056,77 @@ typedef struct { /*! @name TX_STATUS - Transmitter Status Register */ /*! @{ */ + #define EMVSIM_TX_STATUS_TNTE_MASK (0x1U) #define EMVSIM_TX_STATUS_TNTE_SHIFT (0U) /*! TNTE - Transmit NACK Threshold Error Flag - * 0b0..Transmit NACK threshold has not been reached (default) + * 0b0..Transmit NACK threshold has not been reached * 0b1..Transmit NACK threshold reached; transmitter frozen */ #define EMVSIM_TX_STATUS_TNTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TNTE_SHIFT)) & EMVSIM_TX_STATUS_TNTE_MASK) + #define EMVSIM_TX_STATUS_TFE_MASK (0x8U) #define EMVSIM_TX_STATUS_TFE_SHIFT (3U) /*! TFE - Transmit FIFO Empty Flag * 0b0..Transmit FIFO is not empty - * 0b1..Transmit FIFO is empty (default) + * 0b1..Transmit FIFO is empty */ #define EMVSIM_TX_STATUS_TFE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFE_SHIFT)) & EMVSIM_TX_STATUS_TFE_MASK) + #define EMVSIM_TX_STATUS_ETCF_MASK (0x10U) #define EMVSIM_TX_STATUS_ETCF_SHIFT (4U) /*! ETCF - Early Transmit Complete Flag * 0b0..Transmit pending or in progress - * 0b1..Transmit complete (default) + * 0b1..Transmit complete */ #define EMVSIM_TX_STATUS_ETCF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_ETCF_SHIFT)) & EMVSIM_TX_STATUS_ETCF_MASK) + #define EMVSIM_TX_STATUS_TCF_MASK (0x20U) #define EMVSIM_TX_STATUS_TCF_SHIFT (5U) /*! TCF - Transmit Complete Flag * 0b0..Transmit pending or in progress - * 0b1..Transmit complete (default) + * 0b1..Transmit complete */ #define EMVSIM_TX_STATUS_TCF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TCF_SHIFT)) & EMVSIM_TX_STATUS_TCF_MASK) + #define EMVSIM_TX_STATUS_TFF_MASK (0x40U) #define EMVSIM_TX_STATUS_TFF_SHIFT (6U) /*! TFF - Transmit FIFO Full Flag - * 0b0..Transmit FIFO Full condition has not occurred (default) + * 0b0..Transmit FIFO Full condition has not occurred * 0b1..A Transmit FIFO Full condition has occurred */ #define EMVSIM_TX_STATUS_TFF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFF_SHIFT)) & EMVSIM_TX_STATUS_TFF_MASK) + #define EMVSIM_TX_STATUS_TDTF_MASK (0x80U) #define EMVSIM_TX_STATUS_TDTF_SHIFT (7U) /*! TDTF - Transmit Data Threshold Flag - * 0b0..Number of bytes in FIFO is greater than TDT[3:0], or bit has been cleared - * 0b1..Number of bytes in FIFO is less than or equal to TDT[3:0] (default) + * 0b0..Number of bytes in FIFO is greater than TDT, or bit has been cleared + * 0b1..Number of bytes in FIFO is less than or equal to TDT */ #define EMVSIM_TX_STATUS_TDTF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TDTF_SHIFT)) & EMVSIM_TX_STATUS_TDTF_MASK) + #define EMVSIM_TX_STATUS_GPCNT0_TO_MASK (0x100U) #define EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT (8U) /*! GPCNT0_TO - General Purpose Counter 0 Timeout Flag - * 0b0..GPCNT0_VAL time not reached, or bit has been cleared. (default) - * 0b1..General Purpose counter has reached the GPCNT0_VAL value + * 0b0..GPCNT0 time not reached, or bit has been cleared. + * 0b1..General Purpose counter has reached the GPCNT0 value */ #define EMVSIM_TX_STATUS_GPCNT0_TO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT0_TO_MASK) + #define EMVSIM_TX_STATUS_GPCNT1_TO_MASK (0x200U) #define EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT (9U) /*! GPCNT1_TO - General Purpose Counter 1 Timeout Flag - * 0b0..GPCNT1_VAL time not reached, or bit has been cleared. (default) - * 0b1..General Purpose counter has reached the GPCNT1_VAL value + * 0b0..GPCNT1 time not reached, or bit has been cleared. + * 0b1..General Purpose counter has reached the GPCNT1 value */ #define EMVSIM_TX_STATUS_GPCNT1_TO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT1_TO_MASK) + #define EMVSIM_TX_STATUS_TX_RPTR_MASK (0xF0000U) #define EMVSIM_TX_STATUS_TX_RPTR_SHIFT (16U) /*! TX_RPTR - Transmit FIFO Read Pointer */ #define EMVSIM_TX_STATUS_TX_RPTR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_RPTR_SHIFT)) & EMVSIM_TX_STATUS_TX_RPTR_MASK) + #define EMVSIM_TX_STATUS_TX_CNT_MASK (0xF000000U) #define EMVSIM_TX_STATUS_TX_CNT_SHIFT (24U) /*! TX_CNT - Transmit FIFO Byte Count @@ -27289,34 +34137,39 @@ typedef struct { /*! @name PCSR - Port Control and Status Register */ /*! @{ */ + #define EMVSIM_PCSR_SAPD_MASK (0x1U) #define EMVSIM_PCSR_SAPD_SHIFT (0U) /*! SAPD - Auto Power Down Enable - * 0b0..Auto power down disabled (default) + * 0b0..Auto power down disabled * 0b1..Auto power down enabled */ #define EMVSIM_PCSR_SAPD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SAPD_SHIFT)) & EMVSIM_PCSR_SAPD_MASK) + #define EMVSIM_PCSR_SVCC_EN_MASK (0x2U) #define EMVSIM_PCSR_SVCC_EN_SHIFT (1U) /*! SVCC_EN - Vcc Enable for Smart Card - * 0b0..Smart Card Voltage disabled (default) + * 0b0..Smart Card Voltage disabled * 0b1..Smart Card Voltage enabled */ #define EMVSIM_PCSR_SVCC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SVCC_EN_SHIFT)) & EMVSIM_PCSR_SVCC_EN_MASK) + #define EMVSIM_PCSR_VCCENP_MASK (0x4U) #define EMVSIM_PCSR_VCCENP_SHIFT (2U) /*! VCCENP - VCC Enable Polarity Control - * 0b0..VCC_EN is active high. Polarity of SVCC_EN is unchanged. - * 0b1..VCC_EN is active low. Polarity of SVCC_EN is inverted. + * 0b0..SVCC_EN is active high. Polarity of SVCC_EN is unchanged. + * 0b1..SVCC_EN is active low. Polarity of SVCC_EN is inverted. */ #define EMVSIM_PCSR_VCCENP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_VCCENP_SHIFT)) & EMVSIM_PCSR_VCCENP_MASK) + #define EMVSIM_PCSR_SRST_MASK (0x8U) #define EMVSIM_PCSR_SRST_SHIFT (3U) /*! SRST - Reset to Smart Card - * 0b0..Smart Card Reset is asserted (default) + * 0b0..Smart Card Reset is asserted * 0b1..Smart Card Reset is de-asserted */ #define EMVSIM_PCSR_SRST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SRST_SHIFT)) & EMVSIM_PCSR_SRST_MASK) + #define EMVSIM_PCSR_SCEN_MASK (0x10U) #define EMVSIM_PCSR_SCEN_SHIFT (4U) /*! SCEN - Clock Enable for Smart Card @@ -27324,6 +34177,7 @@ typedef struct { * 0b1..Smart Card Clock Enabled */ #define EMVSIM_PCSR_SCEN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCEN_SHIFT)) & EMVSIM_PCSR_SCEN_MASK) + #define EMVSIM_PCSR_SCSP_MASK (0x20U) #define EMVSIM_PCSR_SCSP_SHIFT (5U) /*! SCSP - Smart Card Clock Stop Polarity @@ -27331,27 +34185,31 @@ typedef struct { * 0b1..Clock is logic 1 when stopped by SCEN */ #define EMVSIM_PCSR_SCSP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCSP_SHIFT)) & EMVSIM_PCSR_SCSP_MASK) + #define EMVSIM_PCSR_SPD_MASK (0x80U) #define EMVSIM_PCSR_SPD_SHIFT (7U) /*! SPD - Auto Power Down Control - * 0b0..No effect (default) + * 0b0..No effect * 0b1..Start Auto Powerdown or Power Down is in progress */ #define EMVSIM_PCSR_SPD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPD_SHIFT)) & EMVSIM_PCSR_SPD_MASK) + #define EMVSIM_PCSR_SPDIM_MASK (0x1000000U) #define EMVSIM_PCSR_SPDIM_SHIFT (24U) /*! SPDIM - Smart Card Presence Detect Interrupt Mask * 0b0..SIM presence detect interrupt is enabled - * 0b1..SIM presence detect interrupt is masked (default) + * 0b1..SIM presence detect interrupt is masked */ #define EMVSIM_PCSR_SPDIM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIM_SHIFT)) & EMVSIM_PCSR_SPDIM_MASK) + #define EMVSIM_PCSR_SPDIF_MASK (0x2000000U) #define EMVSIM_PCSR_SPDIF_SHIFT (25U) /*! SPDIF - Smart Card Presence Detect Interrupt Flag - * 0b0..No insertion or removal of Smart Card detected on Port (default) + * 0b0..No insertion or removal of Smart Card detected on Port * 0b1..Insertion or removal of Smart Card detected on Port */ #define EMVSIM_PCSR_SPDIF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIF_SHIFT)) & EMVSIM_PCSR_SPDIF_MASK) + #define EMVSIM_PCSR_SPDP_MASK (0x4000000U) #define EMVSIM_PCSR_SPDP_SHIFT (26U) /*! SPDP - Smart Card Presence Detect Pin Status @@ -27359,10 +34217,11 @@ typedef struct { * 0b1..SIM Presence Detectpin is logic high */ #define EMVSIM_PCSR_SPDP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDP_SHIFT)) & EMVSIM_PCSR_SPDP_MASK) + #define EMVSIM_PCSR_SPDES_MASK (0x8000000U) #define EMVSIM_PCSR_SPDES_SHIFT (27U) /*! SPDES - SIM Presence Detect Edge Select - * 0b0..Falling edge on the pin (default) + * 0b0..Falling edge on the pin * 0b1..Rising edge on the pin */ #define EMVSIM_PCSR_SPDES(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDES_SHIFT)) & EMVSIM_PCSR_SPDES_MASK) @@ -27370,6 +34229,7 @@ typedef struct { /*! @name RX_BUF - Receive Data Read Buffer */ /*! @{ */ + #define EMVSIM_RX_BUF_RX_BYTE_MASK (0xFFU) #define EMVSIM_RX_BUF_RX_BYTE_SHIFT (0U) /*! RX_BYTE - Receive Data Byte Read @@ -27379,6 +34239,7 @@ typedef struct { /*! @name TX_BUF - Transmit Data Buffer */ /*! @{ */ + #define EMVSIM_TX_BUF_TX_BYTE_MASK (0xFFU) #define EMVSIM_TX_BUF_TX_BYTE_SHIFT (0U) /*! TX_BYTE - Transmit Data Byte @@ -27388,19 +34249,17 @@ typedef struct { /*! @name TX_GETU - Transmitter Guard ETU Value Register */ /*! @{ */ + #define EMVSIM_TX_GETU_GETU_MASK (0xFFU) #define EMVSIM_TX_GETU_GETU_SHIFT (0U) /*! GETU - Transmitter Guard Time Value in ETU - * 0b00000000..no additional ETUs inserted (default) - * 0b00000001..1 additional ETU inserted - * 0b11111110..254 additional ETUs inserted - * 0b11111111..Subtracts one ETU by reducing the number of STOP bits from two to one */ #define EMVSIM_TX_GETU_GETU(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK) /*! @} */ /*! @name CWT_VAL - Character Wait Time Value Register */ /*! @{ */ + #define EMVSIM_CWT_VAL_CWT_MASK (0xFFFFU) #define EMVSIM_CWT_VAL_CWT_SHIFT (0U) /*! CWT - Character Wait Time Value @@ -27410,6 +34269,7 @@ typedef struct { /*! @name BWT_VAL - Block Wait Time Value Register */ /*! @{ */ + #define EMVSIM_BWT_VAL_BWT_MASK (0xFFFFFFFFU) #define EMVSIM_BWT_VAL_BWT_SHIFT (0U) /*! BWT - Block Wait Time Value @@ -27419,6 +34279,7 @@ typedef struct { /*! @name BGT_VAL - Block Guard Time Value Register */ /*! @{ */ + #define EMVSIM_BGT_VAL_BGT_MASK (0xFFFFU) #define EMVSIM_BGT_VAL_BGT_SHIFT (0U) /*! BGT - Block Guard Time Value @@ -27428,6 +34289,7 @@ typedef struct { /*! @name GPCNT0_VAL - General Purpose Counter 0 Timeout Value Register */ /*! @{ */ + #define EMVSIM_GPCNT0_VAL_GPCNT0_MASK (0xFFFFU) #define EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT (0U) /*! GPCNT0 - General Purpose Counter 0 Timeout Value @@ -27437,6 +34299,7 @@ typedef struct { /*! @name GPCNT1_VAL - General Purpose Counter 1 Timeout Value */ /*! @{ */ + #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) #define EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT (0U) /*! GPCNT1 - General Purpose Counter 1 Timeout Value @@ -27502,6 +34365,12 @@ typedef struct { __IO uint16_t LMOD; /**< Lower Modulus Register, offset: 0x22 */ __IO uint16_t UCOMP; /**< Upper Position Compare Register, offset: 0x24 */ __IO uint16_t LCOMP; /**< Lower Position Compare Register, offset: 0x26 */ + __I uint16_t LASTEDGE; /**< Last Edge Time Register, offset: 0x28 */ + __I uint16_t LASTEDGEH; /**< Last Edge Time Hold Register, offset: 0x2A */ + __I uint16_t POSDPER; /**< Position Difference Period Counter Register, offset: 0x2C */ + __I uint16_t POSDPERBFR; /**< Position Difference Period Buffer Register, offset: 0x2E */ + __I uint16_t POSDPERH; /**< Position Difference Period Hold Register, offset: 0x30 */ + __IO uint16_t CTRL3; /**< Control 3 Register, offset: 0x32 */ } ENC_Type; /* ---------------------------------------------------------------------------- @@ -27515,6 +34384,7 @@ typedef struct { /*! @name CTRL - Control Register */ /*! @{ */ + #define ENC_CTRL_CMPIE_MASK (0x1U) #define ENC_CTRL_CMPIE_SHIFT (0U) /*! CMPIE - Compare Interrupt Enable @@ -27522,6 +34392,7 @@ typedef struct { * 0b1..Enabled */ #define ENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK) + #define ENC_CTRL_CMPIRQ_MASK (0x2U) #define ENC_CTRL_CMPIRQ_SHIFT (1U) /*! CMPIRQ - Compare Interrupt Request @@ -27529,6 +34400,7 @@ typedef struct { * 0b1..COMP match has occurred (the counter matches the COMP value) */ #define ENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK) + #define ENC_CTRL_WDE_MASK (0x4U) #define ENC_CTRL_WDE_SHIFT (2U) /*! WDE - Watchdog Enable @@ -27536,6 +34408,7 @@ typedef struct { * 0b1..Enabled */ #define ENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK) + #define ENC_CTRL_DIE_MASK (0x8U) #define ENC_CTRL_DIE_SHIFT (3U) /*! DIE - Watchdog Timeout Interrupt Enable @@ -27543,6 +34416,7 @@ typedef struct { * 0b1..Enabled */ #define ENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK) + #define ENC_CTRL_DIRQ_MASK (0x10U) #define ENC_CTRL_DIRQ_SHIFT (4U) /*! DIRQ - Watchdog Timeout Interrupt Request @@ -27550,6 +34424,7 @@ typedef struct { * 0b1..Watchdog timeout interrupt has occurred */ #define ENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK) + #define ENC_CTRL_XNE_MASK (0x20U) #define ENC_CTRL_XNE_SHIFT (5U) /*! XNE - Use Negative Edge of INDEX Pulse @@ -27557,6 +34432,7 @@ typedef struct { * 0b1..Use negative edge of INDEX pulse */ #define ENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK) + #define ENC_CTRL_XIP_MASK (0x40U) #define ENC_CTRL_XIP_SHIFT (6U) /*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS @@ -27564,6 +34440,7 @@ typedef struct { * 0b1..INDEX pulse initializes the position counter */ #define ENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK) + #define ENC_CTRL_XIE_MASK (0x80U) #define ENC_CTRL_XIE_SHIFT (7U) /*! XIE - INDEX Pulse Interrupt Enable @@ -27571,6 +34448,7 @@ typedef struct { * 0b1..Enabled */ #define ENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK) + #define ENC_CTRL_XIRQ_MASK (0x100U) #define ENC_CTRL_XIRQ_SHIFT (8U) /*! XIRQ - INDEX Pulse Interrupt Request @@ -27578,6 +34456,7 @@ typedef struct { * 0b1..INDEX pulse has occurred */ #define ENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK) + #define ENC_CTRL_PH1_MASK (0x200U) #define ENC_CTRL_PH1_SHIFT (9U) /*! PH1 - Enable Signal Phase Count Mode @@ -27588,6 +34467,7 @@ typedef struct { * PHASEB = 0, then count down */ #define ENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK) + #define ENC_CTRL_REV_MASK (0x400U) #define ENC_CTRL_REV_SHIFT (10U) /*! REV - Enable Reverse Direction Counting @@ -27595,6 +34475,7 @@ typedef struct { * 0b1..Count in the reverse direction */ #define ENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK) + #define ENC_CTRL_SWIP_MASK (0x800U) #define ENC_CTRL_SWIP_SHIFT (11U) /*! SWIP - Software-Triggered Initialization of Position Counters UPOS and LPOS @@ -27602,6 +34483,7 @@ typedef struct { * 0b1..Initialize position counter (using upper and lower initialization registers, UINIT and LINIT) */ #define ENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK) + #define ENC_CTRL_HNE_MASK (0x1000U) #define ENC_CTRL_HNE_SHIFT (12U) /*! HNE - Use Negative Edge of HOME Input @@ -27609,6 +34491,7 @@ typedef struct { * 0b1..Use negative-going edge-to-trigger initialization of position counters UPOS and LPOS */ #define ENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK) + #define ENC_CTRL_HIP_MASK (0x2000U) #define ENC_CTRL_HIP_SHIFT (13U) /*! HIP - Enable HOME to Initialize Position Counters UPOS and LPOS @@ -27616,6 +34499,7 @@ typedef struct { * 0b1..HOME signal initializes the position counter */ #define ENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK) + #define ENC_CTRL_HIE_MASK (0x4000U) #define ENC_CTRL_HIE_SHIFT (14U) /*! HIE - HOME Interrupt Enable @@ -27623,6 +34507,7 @@ typedef struct { * 0b1..Enabled */ #define ENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK) + #define ENC_CTRL_HIRQ_MASK (0x8000U) #define ENC_CTRL_HIRQ_SHIFT (15U) /*! HIRQ - HOME Signal Transition Interrupt Request @@ -27634,16 +34519,19 @@ typedef struct { /*! @name FILT - Input Filter Register */ /*! @{ */ + #define ENC_FILT_FILT_PER_MASK (0xFFU) #define ENC_FILT_FILT_PER_SHIFT (0U) /*! FILT_PER - Input Filter Sample Period */ #define ENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK) + #define ENC_FILT_FILT_CNT_MASK (0x700U) #define ENC_FILT_FILT_CNT_SHIFT (8U) /*! FILT_CNT - Input Filter Sample Count */ #define ENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK) + #define ENC_FILT_FILT_PRSC_MASK (0xE000U) #define ENC_FILT_FILT_PRSC_SHIFT (13U) /*! FILT_PRSC - prescaler divide IPbus clock to FILT clk @@ -27653,6 +34541,7 @@ typedef struct { /*! @name WTR - Watchdog Timeout Register */ /*! @{ */ + #define ENC_WTR_WDOG_MASK (0xFFFFU) #define ENC_WTR_WDOG_SHIFT (0U) /*! WDOG - WDOG @@ -27662,6 +34551,7 @@ typedef struct { /*! @name POSD - Position Difference Counter Register */ /*! @{ */ + #define ENC_POSD_POSD_MASK (0xFFFFU) #define ENC_POSD_POSD_SHIFT (0U) /*! POSD - POSD @@ -27671,6 +34561,7 @@ typedef struct { /*! @name POSDH - Position Difference Hold Register */ /*! @{ */ + #define ENC_POSDH_POSDH_MASK (0xFFFFU) #define ENC_POSDH_POSDH_SHIFT (0U) /*! POSDH - POSDH @@ -27680,6 +34571,7 @@ typedef struct { /*! @name REV - Revolution Counter Register */ /*! @{ */ + #define ENC_REV_REV_MASK (0xFFFFU) #define ENC_REV_REV_SHIFT (0U) /*! REV - REV @@ -27689,6 +34581,7 @@ typedef struct { /*! @name REVH - Revolution Hold Register */ /*! @{ */ + #define ENC_REVH_REVH_MASK (0xFFFFU) #define ENC_REVH_REVH_SHIFT (0U) /*! REVH - REVH @@ -27698,6 +34591,7 @@ typedef struct { /*! @name UPOS - Upper Position Counter Register */ /*! @{ */ + #define ENC_UPOS_POS_MASK (0xFFFFU) #define ENC_UPOS_POS_SHIFT (0U) /*! POS - POS @@ -27707,6 +34601,7 @@ typedef struct { /*! @name LPOS - Lower Position Counter Register */ /*! @{ */ + #define ENC_LPOS_POS_MASK (0xFFFFU) #define ENC_LPOS_POS_SHIFT (0U) /*! POS - POS @@ -27716,6 +34611,7 @@ typedef struct { /*! @name UPOSH - Upper Position Hold Register */ /*! @{ */ + #define ENC_UPOSH_POSH_MASK (0xFFFFU) #define ENC_UPOSH_POSH_SHIFT (0U) /*! POSH - POSH @@ -27725,6 +34621,7 @@ typedef struct { /*! @name LPOSH - Lower Position Hold Register */ /*! @{ */ + #define ENC_LPOSH_POSH_MASK (0xFFFFU) #define ENC_LPOSH_POSH_SHIFT (0U) /*! POSH - POSH @@ -27734,6 +34631,7 @@ typedef struct { /*! @name UINIT - Upper Initialization Register */ /*! @{ */ + #define ENC_UINIT_INIT_MASK (0xFFFFU) #define ENC_UINIT_INIT_SHIFT (0U) /*! INIT - INIT @@ -27743,6 +34641,7 @@ typedef struct { /*! @name LINIT - Lower Initialization Register */ /*! @{ */ + #define ENC_LINIT_INIT_MASK (0xFFFFU) #define ENC_LINIT_INIT_SHIFT (0U) /*! INIT - INIT @@ -27752,41 +34651,49 @@ typedef struct { /*! @name IMR - Input Monitor Register */ /*! @{ */ + #define ENC_IMR_HOME_MASK (0x1U) #define ENC_IMR_HOME_SHIFT (0U) /*! HOME - HOME */ #define ENC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK) + #define ENC_IMR_INDEX_MASK (0x2U) #define ENC_IMR_INDEX_SHIFT (1U) /*! INDEX - INDEX */ #define ENC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK) + #define ENC_IMR_PHB_MASK (0x4U) #define ENC_IMR_PHB_SHIFT (2U) /*! PHB - PHB */ #define ENC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK) + #define ENC_IMR_PHA_MASK (0x8U) #define ENC_IMR_PHA_SHIFT (3U) /*! PHA - PHA */ #define ENC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK) + #define ENC_IMR_FHOM_MASK (0x10U) #define ENC_IMR_FHOM_SHIFT (4U) /*! FHOM - FHOM */ #define ENC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK) + #define ENC_IMR_FIND_MASK (0x20U) #define ENC_IMR_FIND_SHIFT (5U) /*! FIND - FIND */ #define ENC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK) + #define ENC_IMR_FPHB_MASK (0x40U) #define ENC_IMR_FPHB_SHIFT (6U) /*! FPHB - FPHB */ #define ENC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK) + #define ENC_IMR_FPHA_MASK (0x80U) #define ENC_IMR_FPHA_SHIFT (7U) /*! FPHA - FPHA @@ -27796,16 +34703,19 @@ typedef struct { /*! @name TST - Test Register */ /*! @{ */ + #define ENC_TST_TEST_COUNT_MASK (0xFFU) #define ENC_TST_TEST_COUNT_SHIFT (0U) /*! TEST_COUNT - TEST_COUNT */ #define ENC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK) + #define ENC_TST_TEST_PERIOD_MASK (0x1F00U) #define ENC_TST_TEST_PERIOD_SHIFT (8U) /*! TEST_PERIOD - TEST_PERIOD */ #define ENC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK) + #define ENC_TST_QDN_MASK (0x2000U) #define ENC_TST_QDN_SHIFT (13U) /*! QDN - Quadrature Decoder Negative Signal @@ -27813,6 +34723,7 @@ typedef struct { * 0b1..Generates a negative quadrature decoder signal */ #define ENC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK) + #define ENC_TST_TCE_MASK (0x4000U) #define ENC_TST_TCE_SHIFT (14U) /*! TCE - Test Counter Enable @@ -27820,6 +34731,7 @@ typedef struct { * 0b1..Enabled */ #define ENC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK) + #define ENC_TST_TEN_MASK (0x8000U) #define ENC_TST_TEN_SHIFT (15U) /*! TEN - Test Mode Enable @@ -27831,6 +34743,7 @@ typedef struct { /*! @name CTRL2 - Control 2 Register */ /*! @{ */ + #define ENC_CTRL2_UPDHLD_MASK (0x1U) #define ENC_CTRL2_UPDHLD_SHIFT (0U) /*! UPDHLD - Update Hold Registers @@ -27838,6 +34751,7 @@ typedef struct { * 0b1..Enable updates of hold registers on the rising edge of TRIGGER input signal */ #define ENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK) + #define ENC_CTRL2_UPDPOS_MASK (0x2U) #define ENC_CTRL2_UPDPOS_SHIFT (1U) /*! UPDPOS - Update Position Registers @@ -27845,6 +34759,7 @@ typedef struct { * 0b1..Clear POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER */ #define ENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK) + #define ENC_CTRL2_MOD_MASK (0x4U) #define ENC_CTRL2_MOD_SHIFT (2U) /*! MOD - Enable Modulo Counting @@ -27852,6 +34767,7 @@ typedef struct { * 0b1..Enable modulo counting */ #define ENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK) + #define ENC_CTRL2_DIR_MASK (0x8U) #define ENC_CTRL2_DIR_SHIFT (3U) /*! DIR - Count Direction Flag @@ -27859,6 +34775,7 @@ typedef struct { * 0b1..Last count was in the up direction */ #define ENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK) + #define ENC_CTRL2_RUIE_MASK (0x10U) #define ENC_CTRL2_RUIE_SHIFT (4U) /*! RUIE - Roll-under Interrupt Enable @@ -27866,6 +34783,7 @@ typedef struct { * 0b1..Enabled */ #define ENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK) + #define ENC_CTRL2_RUIRQ_MASK (0x20U) #define ENC_CTRL2_RUIRQ_SHIFT (5U) /*! RUIRQ - Roll-under Interrupt Request @@ -27873,6 +34791,7 @@ typedef struct { * 0b1..Roll-under has occurred */ #define ENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK) + #define ENC_CTRL2_ROIE_MASK (0x40U) #define ENC_CTRL2_ROIE_SHIFT (6U) /*! ROIE - Roll-over Interrupt Enable @@ -27880,6 +34799,7 @@ typedef struct { * 0b1..Enabled */ #define ENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK) + #define ENC_CTRL2_ROIRQ_MASK (0x80U) #define ENC_CTRL2_ROIRQ_SHIFT (7U) /*! ROIRQ - Roll-over Interrupt Request @@ -27887,6 +34807,7 @@ typedef struct { * 0b1..Roll-over has occurred */ #define ENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK) + #define ENC_CTRL2_REVMOD_MASK (0x100U) #define ENC_CTRL2_REVMOD_SHIFT (8U) /*! REVMOD - Revolution Counter Modulus Enable @@ -27894,6 +34815,7 @@ typedef struct { * 0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV) */ #define ENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK) + #define ENC_CTRL2_OUTCTL_MASK (0x200U) #define ENC_CTRL2_OUTCTL_SHIFT (9U) /*! OUTCTL - Output Control @@ -27901,6 +34823,7 @@ typedef struct { * 0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read */ #define ENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK) + #define ENC_CTRL2_SABIE_MASK (0x400U) #define ENC_CTRL2_SABIE_SHIFT (10U) /*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable @@ -27908,6 +34831,7 @@ typedef struct { * 0b1..Enabled */ #define ENC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK) + #define ENC_CTRL2_SABIRQ_MASK (0x800U) #define ENC_CTRL2_SABIRQ_SHIFT (11U) /*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request @@ -27919,6 +34843,7 @@ typedef struct { /*! @name UMOD - Upper Modulus Register */ /*! @{ */ + #define ENC_UMOD_MOD_MASK (0xFFFFU) #define ENC_UMOD_MOD_SHIFT (0U) /*! MOD - MOD @@ -27928,6 +34853,7 @@ typedef struct { /*! @name LMOD - Lower Modulus Register */ /*! @{ */ + #define ENC_LMOD_MOD_MASK (0xFFFFU) #define ENC_LMOD_MOD_SHIFT (0U) /*! MOD - MOD @@ -27937,6 +34863,7 @@ typedef struct { /*! @name UCOMP - Upper Position Compare Register */ /*! @{ */ + #define ENC_UCOMP_COMP_MASK (0xFFFFU) #define ENC_UCOMP_COMP_SHIFT (0U) /*! COMP - COMP @@ -27946,6 +34873,7 @@ typedef struct { /*! @name LCOMP - Lower Position Compare Register */ /*! @{ */ + #define ENC_LCOMP_COMP_MASK (0xFFFFU) #define ENC_LCOMP_COMP_SHIFT (0U) /*! COMP - COMP @@ -27953,6 +34881,74 @@ typedef struct { #define ENC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK) /*! @} */ +/*! @name LASTEDGE - Last Edge Time Register */ +/*! @{ */ + +#define ENC_LASTEDGE_LASTEDGE_MASK (0xFFFFU) +#define ENC_LASTEDGE_LASTEDGE_SHIFT (0U) +/*! LASTEDGE - Last Edge Time Counter + */ +#define ENC_LASTEDGE_LASTEDGE(x) (((uint16_t)(((uint16_t)(x)) << ENC_LASTEDGE_LASTEDGE_SHIFT)) & ENC_LASTEDGE_LASTEDGE_MASK) +/*! @} */ + +/*! @name LASTEDGEH - Last Edge Time Hold Register */ +/*! @{ */ + +#define ENC_LASTEDGEH_LASTEDGEH_MASK (0xFFFFU) +#define ENC_LASTEDGEH_LASTEDGEH_SHIFT (0U) +/*! LASTEDGEH - Last Edge Time Hold + */ +#define ENC_LASTEDGEH_LASTEDGEH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LASTEDGEH_LASTEDGEH_SHIFT)) & ENC_LASTEDGEH_LASTEDGEH_MASK) +/*! @} */ + +/*! @name POSDPER - Position Difference Period Counter Register */ +/*! @{ */ + +#define ENC_POSDPER_POSDPER_MASK (0xFFFFU) +#define ENC_POSDPER_POSDPER_SHIFT (0U) +/*! POSDPER - Position difference period + */ +#define ENC_POSDPER_POSDPER(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDPER_POSDPER_SHIFT)) & ENC_POSDPER_POSDPER_MASK) +/*! @} */ + +/*! @name POSDPERBFR - Position Difference Period Buffer Register */ +/*! @{ */ + +#define ENC_POSDPERBFR_POSDPERBFR_MASK (0xFFFFU) +#define ENC_POSDPERBFR_POSDPERBFR_SHIFT (0U) +/*! POSDPERBFR - Position difference period buffer + */ +#define ENC_POSDPERBFR_POSDPERBFR(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDPERBFR_POSDPERBFR_SHIFT)) & ENC_POSDPERBFR_POSDPERBFR_MASK) +/*! @} */ + +/*! @name POSDPERH - Position Difference Period Hold Register */ +/*! @{ */ + +#define ENC_POSDPERH_POSDPERH_MASK (0xFFFFU) +#define ENC_POSDPERH_POSDPERH_SHIFT (0U) +/*! POSDPERH - Position difference period hold + */ +#define ENC_POSDPERH_POSDPERH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDPERH_POSDPERH_SHIFT)) & ENC_POSDPERH_POSDPERH_MASK) +/*! @} */ + +/*! @name CTRL3 - Control 3 Register */ +/*! @{ */ + +#define ENC_CTRL3_PMEN_MASK (0x1U) +#define ENC_CTRL3_PMEN_SHIFT (0U) +/*! PMEN - Period measurement function enable + * 0b0..Period measurement functions are not used. POSD is loaded to POSDH and then cleared whenever POSD, UPOS, LPOS, or REV is read. + * 0b1..Period measurement functions are used. POSD is loaded to POSDH and then cleared only when POSD is read. + */ +#define ENC_CTRL3_PMEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL3_PMEN_SHIFT)) & ENC_CTRL3_PMEN_MASK) + +#define ENC_CTRL3_PRSC_MASK (0xF0U) +#define ENC_CTRL3_PRSC_SHIFT (4U) +/*! PRSC - Prescaler + */ +#define ENC_CTRL3_PRSC(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL3_PRSC_SHIFT)) & ENC_CTRL3_PRSC_MASK) +/*! @} */ + /*! * @} @@ -28066,8 +35062,7 @@ typedef struct { __IO uint32_t RDAR2; /**< Receive Descriptor Active Register - Ring 2, offset: 0x1E8 */ __IO uint32_t TDAR2; /**< Transmit Descriptor Active Register - Ring 2, offset: 0x1EC */ __IO uint32_t QOS; /**< QOS Scheme, offset: 0x1F0 */ - uint8_t RESERVED_16[12]; - uint32_t RMON_T_DROP; /**< Reserved Statistic Register, offset: 0x200 */ + uint8_t RESERVED_16[16]; __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */ __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */ __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */ @@ -28106,7 +35101,7 @@ typedef struct { __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */ __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */ __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */ - uint32_t RMON_R_RESVD_0; /**< Reserved Statistic Register, offset: 0x2A4 */ + uint8_t RESERVED_18[4]; __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */ __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */ __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */ @@ -28122,7 +35117,7 @@ typedef struct { __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */ __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */ __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */ - uint8_t RESERVED_18[284]; + uint8_t RESERVED_19[284]; __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */ __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */ __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */ @@ -28130,7 +35125,7 @@ typedef struct { __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */ __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */ __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */ - uint8_t RESERVED_19[488]; + uint8_t RESERVED_20[488]; __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */ struct { /* offset: 0x608, array step: 0x8 */ __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */ @@ -28149,130 +35144,157 @@ typedef struct { /*! @name EIR - Interrupt Event Register */ /*! @{ */ + #define ENET_EIR_RXB1_MASK (0x1U) #define ENET_EIR_RXB1_SHIFT (0U) /*! RXB1 - Receive buffer interrupt, class 1 */ #define ENET_EIR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB1_SHIFT)) & ENET_EIR_RXB1_MASK) + #define ENET_EIR_RXF1_MASK (0x2U) #define ENET_EIR_RXF1_SHIFT (1U) /*! RXF1 - Receive frame interrupt, class 1 */ #define ENET_EIR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF1_SHIFT)) & ENET_EIR_RXF1_MASK) + #define ENET_EIR_TXB1_MASK (0x4U) #define ENET_EIR_TXB1_SHIFT (2U) /*! TXB1 - Transmit buffer interrupt, class 1 */ #define ENET_EIR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB1_SHIFT)) & ENET_EIR_TXB1_MASK) + #define ENET_EIR_TXF1_MASK (0x8U) #define ENET_EIR_TXF1_SHIFT (3U) /*! TXF1 - Transmit frame interrupt, class 1 */ #define ENET_EIR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF1_SHIFT)) & ENET_EIR_TXF1_MASK) + #define ENET_EIR_RXB2_MASK (0x10U) #define ENET_EIR_RXB2_SHIFT (4U) /*! RXB2 - Receive buffer interrupt, class 2 */ #define ENET_EIR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB2_SHIFT)) & ENET_EIR_RXB2_MASK) + #define ENET_EIR_RXF2_MASK (0x20U) #define ENET_EIR_RXF2_SHIFT (5U) /*! RXF2 - Receive frame interrupt, class 2 */ #define ENET_EIR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF2_SHIFT)) & ENET_EIR_RXF2_MASK) + #define ENET_EIR_TXB2_MASK (0x40U) #define ENET_EIR_TXB2_SHIFT (6U) /*! TXB2 - Transmit buffer interrupt, class 2 */ #define ENET_EIR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB2_SHIFT)) & ENET_EIR_TXB2_MASK) + #define ENET_EIR_TXF2_MASK (0x80U) #define ENET_EIR_TXF2_SHIFT (7U) /*! TXF2 - Transmit frame interrupt, class 2 */ #define ENET_EIR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF2_SHIFT)) & ENET_EIR_TXF2_MASK) + #define ENET_EIR_RXFLUSH_0_MASK (0x1000U) #define ENET_EIR_RXFLUSH_0_SHIFT (12U) #define ENET_EIR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_0_SHIFT)) & ENET_EIR_RXFLUSH_0_MASK) + #define ENET_EIR_RXFLUSH_1_MASK (0x2000U) #define ENET_EIR_RXFLUSH_1_SHIFT (13U) #define ENET_EIR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_1_SHIFT)) & ENET_EIR_RXFLUSH_1_MASK) + #define ENET_EIR_RXFLUSH_2_MASK (0x4000U) #define ENET_EIR_RXFLUSH_2_SHIFT (14U) #define ENET_EIR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_2_SHIFT)) & ENET_EIR_RXFLUSH_2_MASK) + #define ENET_EIR_TS_TIMER_MASK (0x8000U) #define ENET_EIR_TS_TIMER_SHIFT (15U) /*! TS_TIMER - Timestamp Timer */ #define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK) + #define ENET_EIR_TS_AVAIL_MASK (0x10000U) #define ENET_EIR_TS_AVAIL_SHIFT (16U) /*! TS_AVAIL - Transmit Timestamp Available */ #define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK) + #define ENET_EIR_WAKEUP_MASK (0x20000U) #define ENET_EIR_WAKEUP_SHIFT (17U) /*! WAKEUP - Node Wakeup Request Indication */ #define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK) + #define ENET_EIR_PLR_MASK (0x40000U) #define ENET_EIR_PLR_SHIFT (18U) /*! PLR - Payload Receive Error */ #define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK) + #define ENET_EIR_UN_MASK (0x80000U) #define ENET_EIR_UN_SHIFT (19U) /*! UN - Transmit FIFO Underrun */ #define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK) + #define ENET_EIR_RL_MASK (0x100000U) #define ENET_EIR_RL_SHIFT (20U) /*! RL - Collision Retry Limit */ #define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK) + #define ENET_EIR_LC_MASK (0x200000U) #define ENET_EIR_LC_SHIFT (21U) /*! LC - Late Collision */ #define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK) + #define ENET_EIR_EBERR_MASK (0x400000U) #define ENET_EIR_EBERR_SHIFT (22U) /*! EBERR - Ethernet Bus Error */ #define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK) + #define ENET_EIR_MII_MASK (0x800000U) #define ENET_EIR_MII_SHIFT (23U) /*! MII - MII Interrupt. */ #define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK) + #define ENET_EIR_RXB_MASK (0x1000000U) #define ENET_EIR_RXB_SHIFT (24U) /*! RXB - Receive Buffer Interrupt */ #define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK) + #define ENET_EIR_RXF_MASK (0x2000000U) #define ENET_EIR_RXF_SHIFT (25U) /*! RXF - Receive Frame Interrupt */ #define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK) + #define ENET_EIR_TXB_MASK (0x4000000U) #define ENET_EIR_TXB_SHIFT (26U) /*! TXB - Transmit Buffer Interrupt */ #define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK) + #define ENET_EIR_TXF_MASK (0x8000000U) #define ENET_EIR_TXF_SHIFT (27U) /*! TXF - Transmit Frame Interrupt */ #define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK) + #define ENET_EIR_GRA_MASK (0x10000000U) #define ENET_EIR_GRA_SHIFT (28U) /*! GRA - Graceful Stop Complete */ #define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK) + #define ENET_EIR_BABT_MASK (0x20000000U) #define ENET_EIR_BABT_SHIFT (29U) /*! BABT - Babbling Transmit Error */ #define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK) + #define ENET_EIR_BABR_MASK (0x40000000U) #define ENET_EIR_BABR_SHIFT (30U) /*! BABR - Babbling Receive Error @@ -28282,110 +35304,183 @@ typedef struct { /*! @name EIMR - Interrupt Mask Register */ /*! @{ */ + #define ENET_EIMR_RXB1_MASK (0x1U) #define ENET_EIMR_RXB1_SHIFT (0U) /*! RXB1 - Receive buffer interrupt, class 1 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB1_SHIFT)) & ENET_EIMR_RXB1_MASK) + #define ENET_EIMR_RXF1_MASK (0x2U) #define ENET_EIMR_RXF1_SHIFT (1U) /*! RXF1 - Receive frame interrupt, class 1 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF1_SHIFT)) & ENET_EIMR_RXF1_MASK) + #define ENET_EIMR_TXB1_MASK (0x4U) #define ENET_EIMR_TXB1_SHIFT (2U) /*! TXB1 - Transmit buffer interrupt, class 1 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB1_SHIFT)) & ENET_EIMR_TXB1_MASK) + #define ENET_EIMR_TXF1_MASK (0x8U) #define ENET_EIMR_TXF1_SHIFT (3U) /*! TXF1 - Transmit frame interrupt, class 1 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF1_SHIFT)) & ENET_EIMR_TXF1_MASK) + #define ENET_EIMR_RXB2_MASK (0x10U) #define ENET_EIMR_RXB2_SHIFT (4U) /*! RXB2 - Receive buffer interrupt, class 2 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB2_SHIFT)) & ENET_EIMR_RXB2_MASK) + #define ENET_EIMR_RXF2_MASK (0x20U) #define ENET_EIMR_RXF2_SHIFT (5U) /*! RXF2 - Receive frame interrupt, class 2 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF2_SHIFT)) & ENET_EIMR_RXF2_MASK) + #define ENET_EIMR_TXB2_MASK (0x40U) #define ENET_EIMR_TXB2_SHIFT (6U) /*! TXB2 - Transmit buffer interrupt, class 2 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB2_SHIFT)) & ENET_EIMR_TXB2_MASK) + #define ENET_EIMR_TXF2_MASK (0x80U) #define ENET_EIMR_TXF2_SHIFT (7U) /*! TXF2 - Transmit frame interrupt, class 2 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF2_SHIFT)) & ENET_EIMR_TXF2_MASK) + #define ENET_EIMR_RXFLUSH_0_MASK (0x1000U) #define ENET_EIMR_RXFLUSH_0_SHIFT (12U) +/*! RXFLUSH_0 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ #define ENET_EIMR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_0_SHIFT)) & ENET_EIMR_RXFLUSH_0_MASK) + #define ENET_EIMR_RXFLUSH_1_MASK (0x2000U) #define ENET_EIMR_RXFLUSH_1_SHIFT (13U) +/*! RXFLUSH_1 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ #define ENET_EIMR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_1_SHIFT)) & ENET_EIMR_RXFLUSH_1_MASK) + #define ENET_EIMR_RXFLUSH_2_MASK (0x4000U) #define ENET_EIMR_RXFLUSH_2_SHIFT (14U) +/*! RXFLUSH_2 + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. + */ #define ENET_EIMR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_2_SHIFT)) & ENET_EIMR_RXFLUSH_2_MASK) + #define ENET_EIMR_TS_TIMER_MASK (0x8000U) #define ENET_EIMR_TS_TIMER_SHIFT (15U) /*! TS_TIMER - TS_TIMER Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK) + #define ENET_EIMR_TS_AVAIL_MASK (0x10000U) #define ENET_EIMR_TS_AVAIL_SHIFT (16U) /*! TS_AVAIL - TS_AVAIL Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK) + #define ENET_EIMR_WAKEUP_MASK (0x20000U) #define ENET_EIMR_WAKEUP_SHIFT (17U) /*! WAKEUP - WAKEUP Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK) + #define ENET_EIMR_PLR_MASK (0x40000U) #define ENET_EIMR_PLR_SHIFT (18U) /*! PLR - PLR Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK) + #define ENET_EIMR_UN_MASK (0x80000U) #define ENET_EIMR_UN_SHIFT (19U) /*! UN - UN Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK) + #define ENET_EIMR_RL_MASK (0x100000U) #define ENET_EIMR_RL_SHIFT (20U) /*! RL - RL Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK) + #define ENET_EIMR_LC_MASK (0x200000U) #define ENET_EIMR_LC_SHIFT (21U) /*! LC - LC Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK) + #define ENET_EIMR_EBERR_MASK (0x400000U) #define ENET_EIMR_EBERR_SHIFT (22U) /*! EBERR - EBERR Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK) + #define ENET_EIMR_MII_MASK (0x800000U) #define ENET_EIMR_MII_SHIFT (23U) /*! MII - MII Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK) + #define ENET_EIMR_RXB_MASK (0x1000000U) #define ENET_EIMR_RXB_SHIFT (24U) /*! RXB - RXB Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK) + #define ENET_EIMR_RXF_MASK (0x2000000U) #define ENET_EIMR_RXF_SHIFT (25U) /*! RXF - RXF Interrupt Mask + * 0b0..The corresponding interrupt source is masked. + * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK) + #define ENET_EIMR_TXB_MASK (0x4000000U) #define ENET_EIMR_TXB_SHIFT (26U) /*! TXB - TXB Interrupt Mask @@ -28393,6 +35488,7 @@ typedef struct { * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK) + #define ENET_EIMR_TXF_MASK (0x8000000U) #define ENET_EIMR_TXF_SHIFT (27U) /*! TXF - TXF Interrupt Mask @@ -28400,6 +35496,7 @@ typedef struct { * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK) + #define ENET_EIMR_GRA_MASK (0x10000000U) #define ENET_EIMR_GRA_SHIFT (28U) /*! GRA - GRA Interrupt Mask @@ -28407,6 +35504,7 @@ typedef struct { * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK) + #define ENET_EIMR_BABT_MASK (0x20000000U) #define ENET_EIMR_BABT_SHIFT (29U) /*! BABT - BABT Interrupt Mask @@ -28414,6 +35512,7 @@ typedef struct { * 0b1..The corresponding interrupt source is not masked. */ #define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK) + #define ENET_EIMR_BABR_MASK (0x40000000U) #define ENET_EIMR_BABR_SHIFT (30U) /*! BABR - BABR Interrupt Mask @@ -28425,6 +35524,7 @@ typedef struct { /*! @name RDAR - Receive Descriptor Active Register - Ring 0 */ /*! @{ */ + #define ENET_RDAR_RDAR_MASK (0x1000000U) #define ENET_RDAR_RDAR_SHIFT (24U) /*! RDAR - Receive Descriptor Active @@ -28434,6 +35534,7 @@ typedef struct { /*! @name TDAR - Transmit Descriptor Active Register - Ring 0 */ /*! @{ */ + #define ENET_TDAR_TDAR_MASK (0x1000000U) #define ENET_TDAR_TDAR_SHIFT (24U) /*! TDAR - Transmit Descriptor Active @@ -28443,11 +35544,13 @@ typedef struct { /*! @name ECR - Ethernet Control Register */ /*! @{ */ + #define ENET_ECR_RESET_MASK (0x1U) #define ENET_ECR_RESET_SHIFT (0U) /*! RESET - Ethernet MAC Reset */ #define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK) + #define ENET_ECR_ETHEREN_MASK (0x2U) #define ENET_ECR_ETHEREN_SHIFT (1U) /*! ETHEREN - Ethernet Enable @@ -28455,6 +35558,7 @@ typedef struct { * 0b1..MAC is enabled, and reception and transmission are possible. */ #define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK) + #define ENET_ECR_MAGICEN_MASK (0x4U) #define ENET_ECR_MAGICEN_SHIFT (2U) /*! MAGICEN - Magic Packet Detection Enable @@ -28462,6 +35566,7 @@ typedef struct { * 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected. */ #define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK) + #define ENET_ECR_SLEEP_MASK (0x8U) #define ENET_ECR_SLEEP_SHIFT (3U) /*! SLEEP - Sleep Mode Enable @@ -28469,6 +35574,7 @@ typedef struct { * 0b1..Sleep mode. */ #define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK) + #define ENET_ECR_EN1588_MASK (0x10U) #define ENET_ECR_EN1588_SHIFT (4U) /*! EN1588 - EN1588 Enable @@ -28476,6 +35582,7 @@ typedef struct { * 0b1..Enhanced frame time-stamping functions enabled. Has no effect within the MAC besides controlling the DMA control bit ena_1588. */ #define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK) + #define ENET_ECR_SPEED_MASK (0x20U) #define ENET_ECR_SPEED_SHIFT (5U) /*! SPEED @@ -28483,6 +35590,7 @@ typedef struct { * 0b1..1000-Mbit/s mode */ #define ENET_ECR_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SPEED_SHIFT)) & ENET_ECR_SPEED_MASK) + #define ENET_ECR_DBGEN_MASK (0x40U) #define ENET_ECR_DBGEN_SHIFT (6U) /*! DBGEN - Debug Enable @@ -28490,6 +35598,7 @@ typedef struct { * 0b1..MAC enters hardware freeze mode when the processor is in debug mode. */ #define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK) + #define ENET_ECR_DBSWP_MASK (0x100U) #define ENET_ECR_DBSWP_SHIFT (8U) /*! DBSWP - Descriptor Byte Swapping Enable @@ -28497,6 +35606,7 @@ typedef struct { * 0b1..The buffer descriptor bytes are swapped to support little-endian devices. */ #define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK) + #define ENET_ECR_SVLANEN_MASK (0x200U) #define ENET_ECR_SVLANEN_SHIFT (9U) /*! SVLANEN - S-VLAN enable @@ -28506,6 +35616,7 @@ typedef struct { * classification match comparators, RCMRn. */ #define ENET_ECR_SVLANEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANEN_SHIFT)) & ENET_ECR_SVLANEN_MASK) + #define ENET_ECR_VLANUSE2ND_MASK (0x400U) #define ENET_ECR_VLANUSE2ND_SHIFT (10U) /*! VLANUSE2ND - VLAN use second tag @@ -28515,11 +35626,15 @@ typedef struct { * second tag must be a C-VLAN */ #define ENET_ECR_VLANUSE2ND(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_VLANUSE2ND_SHIFT)) & ENET_ECR_VLANUSE2ND_MASK) + #define ENET_ECR_SVLANDBL_MASK (0x800U) #define ENET_ECR_SVLANDBL_SHIFT (11U) /*! SVLANDBL - S-VLAN double tag + * 0b0..Disable S-VLAN double tag + * 0b1..Enable S-VLAN double tag */ #define ENET_ECR_SVLANDBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANDBL_SHIFT)) & ENET_ECR_SVLANDBL_MASK) + #define ENET_ECR_TXC_DLY_MASK (0x10000U) #define ENET_ECR_TXC_DLY_SHIFT (16U) /*! TXC_DLY - Transmit clock delay @@ -28527,42 +35642,41 @@ typedef struct { * 0b1..Generate delayed version of RGMII_TXC. */ #define ENET_ECR_TXC_DLY(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_TXC_DLY_SHIFT)) & ENET_ECR_TXC_DLY_MASK) -#define ENET_ECR_RXC_DLY_MASK (0x20000U) -#define ENET_ECR_RXC_DLY_SHIFT (17U) -/*! RXC_DLY - Receive clock delay - * 0b0..Use non-delayed version of RGMII_RXC. - * 0b1..Use delayed version of RGMII_RXC. - */ -#define ENET_ECR_RXC_DLY(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RXC_DLY_SHIFT)) & ENET_ECR_RXC_DLY_MASK) /*! @} */ /*! @name MMFR - MII Management Frame Register */ /*! @{ */ + #define ENET_MMFR_DATA_MASK (0xFFFFU) #define ENET_MMFR_DATA_SHIFT (0U) /*! DATA - Management Frame Data */ #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK) + #define ENET_MMFR_TA_MASK (0x30000U) #define ENET_MMFR_TA_SHIFT (16U) /*! TA - Turn Around */ #define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK) + #define ENET_MMFR_RA_MASK (0x7C0000U) #define ENET_MMFR_RA_SHIFT (18U) /*! RA - Register Address */ #define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK) + #define ENET_MMFR_PA_MASK (0xF800000U) #define ENET_MMFR_PA_SHIFT (23U) /*! PA - PHY Address */ #define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK) + #define ENET_MMFR_OP_MASK (0x30000000U) #define ENET_MMFR_OP_SHIFT (28U) /*! OP - Operation Code */ #define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK) + #define ENET_MMFR_ST_MASK (0xC0000000U) #define ENET_MMFR_ST_SHIFT (30U) /*! ST - Start Of Frame Delimiter @@ -28572,11 +35686,13 @@ typedef struct { /*! @name MSCR - MII Speed Control Register */ /*! @{ */ + #define ENET_MSCR_MII_SPEED_MASK (0x7EU) #define ENET_MSCR_MII_SPEED_SHIFT (1U) /*! MII_SPEED - MII Speed */ #define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK) + #define ENET_MSCR_DIS_PRE_MASK (0x80U) #define ENET_MSCR_DIS_PRE_SHIFT (7U) /*! DIS_PRE - Disable Preamble @@ -28584,6 +35700,7 @@ typedef struct { * 0b1..Preamble (32 ones) is not prepended to the MII management frame. */ #define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK) + #define ENET_MSCR_HOLDTIME_MASK (0x700U) #define ENET_MSCR_HOLDTIME_SHIFT (8U) /*! HOLDTIME - Hold time On MDIO Output @@ -28597,6 +35714,7 @@ typedef struct { /*! @name MIBC - MIB Control Register */ /*! @{ */ + #define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U) #define ENET_MIBC_MIB_CLEAR_SHIFT (29U) /*! MIB_CLEAR - MIB Clear @@ -28604,6 +35722,7 @@ typedef struct { * 0b1..All statistics counters are reset to 0. */ #define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK) + #define ENET_MIBC_MIB_IDLE_MASK (0x40000000U) #define ENET_MIBC_MIB_IDLE_SHIFT (30U) /*! MIB_IDLE - MIB Idle @@ -28611,6 +35730,7 @@ typedef struct { * 0b1..The MIB block is not currently updating any MIB counters. */ #define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK) + #define ENET_MIBC_MIB_DIS_MASK (0x80000000U) #define ENET_MIBC_MIB_DIS_SHIFT (31U) /*! MIB_DIS - Disable MIB Logic @@ -28622,6 +35742,7 @@ typedef struct { /*! @name RCR - Receive Control Register */ /*! @{ */ + #define ENET_RCR_LOOP_MASK (0x1U) #define ENET_RCR_LOOP_SHIFT (0U) /*! LOOP - Internal Loopback @@ -28629,6 +35750,7 @@ typedef struct { * 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared. */ #define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK) + #define ENET_RCR_DRT_MASK (0x2U) #define ENET_RCR_DRT_SHIFT (1U) /*! DRT - Disable Receive On Transmit @@ -28636,6 +35758,7 @@ typedef struct { * 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.) */ #define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK) + #define ENET_RCR_MII_MODE_MASK (0x4U) #define ENET_RCR_MII_MODE_SHIFT (2U) /*! MII_MODE - Media Independent Interface Mode @@ -28643,6 +35766,7 @@ typedef struct { * 0b1..MII or RMII mode, as indicated by the RMII_MODE field. */ #define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK) + #define ENET_RCR_PROM_MASK (0x8U) #define ENET_RCR_PROM_SHIFT (3U) /*! PROM - Promiscuous Mode @@ -28650,16 +35774,23 @@ typedef struct { * 0b1..Enabled. */ #define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK) + #define ENET_RCR_BC_REJ_MASK (0x10U) #define ENET_RCR_BC_REJ_SHIFT (4U) /*! BC_REJ - Broadcast Frame Reject + * 0b0..Will not reject frames as described above + * 0b1..Will reject frames as described above */ #define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK) + #define ENET_RCR_FCE_MASK (0x20U) #define ENET_RCR_FCE_SHIFT (5U) /*! FCE - Flow Control Enable + * 0b0..Disable flow control + * 0b1..Enable flow control */ #define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK) + #define ENET_RCR_RGMII_EN_MASK (0x40U) #define ENET_RCR_RGMII_EN_SHIFT (6U) /*! RGMII_EN - RGMII Mode Enable @@ -28668,6 +35799,7 @@ typedef struct { * ECR[SPEED] is cleared, the MAC is in RGMII 10/100-Mbit/s mode. */ #define ENET_RCR_RGMII_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RGMII_EN_SHIFT)) & ENET_RCR_RGMII_EN_MASK) + #define ENET_RCR_RMII_MODE_MASK (0x100U) #define ENET_RCR_RMII_MODE_SHIFT (8U) /*! RMII_MODE - RMII Mode Enable @@ -28675,13 +35807,15 @@ typedef struct { * 0b1..MAC configured for RMII operation. */ #define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK) + #define ENET_RCR_RMII_10T_MASK (0x200U) #define ENET_RCR_RMII_10T_SHIFT (9U) /*! RMII_10T - * 0b0..100-Mbit/s operation. + * 0b0..100-Mbit/s or 1-Gbit/s operation. * 0b1..10-Mbit/s operation. */ #define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK) + #define ENET_RCR_PADEN_MASK (0x1000U) #define ENET_RCR_PADEN_SHIFT (12U) /*! PADEN - Enable Frame Padding Remove On Receive @@ -28689,6 +35823,7 @@ typedef struct { * 0b1..Padding is removed from received frames. */ #define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK) + #define ENET_RCR_PAUFWD_MASK (0x2000U) #define ENET_RCR_PAUFWD_SHIFT (13U) /*! PAUFWD - Terminate/Forward Pause Frames @@ -28696,6 +35831,7 @@ typedef struct { * 0b1..Pause frames are forwarded to the user application. */ #define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK) + #define ENET_RCR_CRCFWD_MASK (0x4000U) #define ENET_RCR_CRCFWD_SHIFT (14U) /*! CRCFWD - Terminate/Forward Received CRC @@ -28703,6 +35839,7 @@ typedef struct { * 0b1..The CRC field is stripped from the frame. */ #define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK) + #define ENET_RCR_CFEN_MASK (0x8000U) #define ENET_RCR_CFEN_SHIFT (15U) /*! CFEN - MAC Control Frame Enable @@ -28710,11 +35847,13 @@ typedef struct { * 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded. */ #define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK) + #define ENET_RCR_MAX_FL_MASK (0x3FFF0000U) #define ENET_RCR_MAX_FL_SHIFT (16U) /*! MAX_FL - Maximum Frame Length */ #define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK) + #define ENET_RCR_NLC_MASK (0x40000000U) #define ENET_RCR_NLC_SHIFT (30U) /*! NLC - Payload Length Check Disable @@ -28722,25 +35861,35 @@ typedef struct { * 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field. */ #define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK) + #define ENET_RCR_GRS_MASK (0x80000000U) #define ENET_RCR_GRS_SHIFT (31U) /*! GRS - Graceful Receive Stopped + * 0b0..Receive not stopped + * 0b1..Receive stopped */ #define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK) /*! @} */ /*! @name TCR - Transmit Control Register */ /*! @{ */ + #define ENET_TCR_GTS_MASK (0x1U) #define ENET_TCR_GTS_SHIFT (0U) /*! GTS - Graceful Transmit Stop + * 0b0..Disable graceful transmit stop + * 0b1..Enable graceful transmit stop */ #define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK) + #define ENET_TCR_FDEN_MASK (0x4U) #define ENET_TCR_FDEN_SHIFT (2U) /*! FDEN - Full-Duplex Enable + * 0b0..Disable full-duplex + * 0b1..Enable full-duplex */ #define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK) + #define ENET_TCR_TFC_PAUSE_MASK (0x8U) #define ENET_TCR_TFC_PAUSE_SHIFT (3U) /*! TFC_PAUSE - Transmit Frame Control Pause @@ -28748,11 +35897,13 @@ typedef struct { * 0b1..The MAC stops transmission of data frames after the current transmission is complete. */ #define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK) + #define ENET_TCR_RFC_PAUSE_MASK (0x10U) #define ENET_TCR_RFC_PAUSE_SHIFT (4U) /*! RFC_PAUSE - Receive Frame Control Pause */ #define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK) + #define ENET_TCR_ADDSEL_MASK (0xE0U) #define ENET_TCR_ADDSEL_SHIFT (5U) /*! ADDSEL - Source MAC Address Select On Transmit @@ -28762,6 +35913,7 @@ typedef struct { * 0b110..Reserved. */ #define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK) + #define ENET_TCR_ADDINS_MASK (0x100U) #define ENET_TCR_ADDINS_SHIFT (8U) /*! ADDINS - Set MAC Address On Transmit @@ -28769,6 +35921,7 @@ typedef struct { * 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL. */ #define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK) + #define ENET_TCR_CRCFWD_MASK (0x200U) #define ENET_TCR_CRCFWD_SHIFT (9U) /*! CRCFWD - Forward Frame From Application With CRC @@ -28780,6 +35933,7 @@ typedef struct { /*! @name PALR - Physical Address Lower Register */ /*! @{ */ + #define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU) #define ENET_PALR_PADDR1_SHIFT (0U) /*! PADDR1 - Pause Address @@ -28789,11 +35943,13 @@ typedef struct { /*! @name PAUR - Physical Address Upper Register */ /*! @{ */ + #define ENET_PAUR_TYPE_MASK (0xFFFFU) #define ENET_PAUR_TYPE_SHIFT (0U) /*! TYPE - Type Field In PAUSE Frames */ #define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK) + #define ENET_PAUR_PADDR2_MASK (0xFFFF0000U) #define ENET_PAUR_PADDR2_SHIFT (16U) #define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK) @@ -28801,11 +35957,13 @@ typedef struct { /*! @name OPD - Opcode/Pause Duration Register */ /*! @{ */ + #define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU) #define ENET_OPD_PAUSE_DUR_SHIFT (0U) /*! PAUSE_DUR - Pause Duration */ #define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK) + #define ENET_OPD_OPCODE_MASK (0xFFFF0000U) #define ENET_OPD_OPCODE_SHIFT (16U) /*! OPCODE - Opcode Field In PAUSE Frames @@ -28815,16 +35973,19 @@ typedef struct { /*! @name TXIC - Transmit Interrupt Coalescing Register */ /*! @{ */ + #define ENET_TXIC_ICTT_MASK (0xFFFFU) #define ENET_TXIC_ICTT_SHIFT (0U) /*! ICTT - Interrupt coalescing timer threshold */ #define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK) + #define ENET_TXIC_ICFT_MASK (0xFF00000U) #define ENET_TXIC_ICFT_SHIFT (20U) /*! ICFT - Interrupt coalescing frame count threshold */ #define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK) + #define ENET_TXIC_ICCS_MASK (0x40000000U) #define ENET_TXIC_ICCS_SHIFT (30U) /*! ICCS - Interrupt Coalescing Timer Clock Source Select @@ -28832,6 +35993,7 @@ typedef struct { * 0b1..Use ENET system clock. */ #define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK) + #define ENET_TXIC_ICEN_MASK (0x80000000U) #define ENET_TXIC_ICEN_SHIFT (31U) /*! ICEN - Interrupt Coalescing Enable @@ -28846,16 +36008,19 @@ typedef struct { /*! @name RXIC - Receive Interrupt Coalescing Register */ /*! @{ */ + #define ENET_RXIC_ICTT_MASK (0xFFFFU) #define ENET_RXIC_ICTT_SHIFT (0U) /*! ICTT - Interrupt coalescing timer threshold */ #define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK) + #define ENET_RXIC_ICFT_MASK (0xFF00000U) #define ENET_RXIC_ICFT_SHIFT (20U) /*! ICFT - Interrupt coalescing frame count threshold */ #define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK) + #define ENET_RXIC_ICCS_MASK (0x40000000U) #define ENET_RXIC_ICCS_SHIFT (30U) /*! ICCS - Interrupt Coalescing Timer Clock Source Select @@ -28863,6 +36028,7 @@ typedef struct { * 0b1..Use ENET system clock. */ #define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK) + #define ENET_RXIC_ICEN_MASK (0x80000000U) #define ENET_RXIC_ICEN_SHIFT (31U) /*! ICEN - Interrupt Coalescing Enable @@ -28877,6 +36043,7 @@ typedef struct { /*! @name IAUR - Descriptor Individual Upper Address Register */ /*! @{ */ + #define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU) #define ENET_IAUR_IADDR1_SHIFT (0U) #define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK) @@ -28884,6 +36051,7 @@ typedef struct { /*! @name IALR - Descriptor Individual Lower Address Register */ /*! @{ */ + #define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU) #define ENET_IALR_IADDR2_SHIFT (0U) #define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK) @@ -28891,6 +36059,7 @@ typedef struct { /*! @name GAUR - Descriptor Group Upper Address Register */ /*! @{ */ + #define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU) #define ENET_GAUR_GADDR1_SHIFT (0U) #define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK) @@ -28898,6 +36067,7 @@ typedef struct { /*! @name GALR - Descriptor Group Lower Address Register */ /*! @{ */ + #define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU) #define ENET_GALR_GADDR2_SHIFT (0U) #define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK) @@ -28905,6 +36075,7 @@ typedef struct { /*! @name TFWR - Transmit FIFO Watermark Register */ /*! @{ */ + #define ENET_TFWR_TFWR_MASK (0x3FU) #define ENET_TFWR_TFWR_SHIFT (0U) /*! TFWR - Transmit FIFO Write @@ -28915,6 +36086,7 @@ typedef struct { * 0b111111..4032 bytes written. */ #define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK) + #define ENET_TFWR_STRFWD_MASK (0x100U) #define ENET_TFWR_STRFWD_SHIFT (8U) /*! STRFWD - Store And Forward Enable @@ -28926,6 +36098,7 @@ typedef struct { /*! @name RDSR1 - Receive Descriptor Ring 1 Start Register */ /*! @{ */ + #define ENET_RDSR1_R_DES_START_MASK (0xFFFFFFF8U) #define ENET_RDSR1_R_DES_START_SHIFT (3U) #define ENET_RDSR1_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR1_R_DES_START_SHIFT)) & ENET_RDSR1_R_DES_START_MASK) @@ -28933,6 +36106,7 @@ typedef struct { /*! @name TDSR1 - Transmit Buffer Descriptor Ring 1 Start Register */ /*! @{ */ + #define ENET_TDSR1_X_DES_START_MASK (0xFFFFFFF8U) #define ENET_TDSR1_X_DES_START_SHIFT (3U) #define ENET_TDSR1_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR1_X_DES_START_SHIFT)) & ENET_TDSR1_X_DES_START_MASK) @@ -28940,6 +36114,7 @@ typedef struct { /*! @name MRBR1 - Maximum Receive Buffer Size Register - Ring 1 */ /*! @{ */ + #define ENET_MRBR1_R_BUF_SIZE_MASK (0x7F0U) #define ENET_MRBR1_R_BUF_SIZE_SHIFT (4U) #define ENET_MRBR1_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR1_R_BUF_SIZE_SHIFT)) & ENET_MRBR1_R_BUF_SIZE_MASK) @@ -28947,6 +36122,7 @@ typedef struct { /*! @name RDSR2 - Receive Descriptor Ring 2 Start Register */ /*! @{ */ + #define ENET_RDSR2_R_DES_START_MASK (0xFFFFFFF8U) #define ENET_RDSR2_R_DES_START_SHIFT (3U) #define ENET_RDSR2_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR2_R_DES_START_SHIFT)) & ENET_RDSR2_R_DES_START_MASK) @@ -28954,6 +36130,7 @@ typedef struct { /*! @name TDSR2 - Transmit Buffer Descriptor Ring 2 Start Register */ /*! @{ */ + #define ENET_TDSR2_X_DES_START_MASK (0xFFFFFFF8U) #define ENET_TDSR2_X_DES_START_SHIFT (3U) #define ENET_TDSR2_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR2_X_DES_START_SHIFT)) & ENET_TDSR2_X_DES_START_MASK) @@ -28961,6 +36138,7 @@ typedef struct { /*! @name MRBR2 - Maximum Receive Buffer Size Register - Ring 2 */ /*! @{ */ + #define ENET_MRBR2_R_BUF_SIZE_MASK (0x7F0U) #define ENET_MRBR2_R_BUF_SIZE_SHIFT (4U) #define ENET_MRBR2_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR2_R_BUF_SIZE_SHIFT)) & ENET_MRBR2_R_BUF_SIZE_MASK) @@ -28968,6 +36146,7 @@ typedef struct { /*! @name RDSR - Receive Descriptor Ring 0 Start Register */ /*! @{ */ + #define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U) #define ENET_RDSR_R_DES_START_SHIFT (3U) #define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK) @@ -28975,6 +36154,7 @@ typedef struct { /*! @name TDSR - Transmit Buffer Descriptor Ring 0 Start Register */ /*! @{ */ + #define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U) #define ENET_TDSR_X_DES_START_SHIFT (3U) #define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK) @@ -28982,6 +36162,7 @@ typedef struct { /*! @name MRBR - Maximum Receive Buffer Size Register - Ring 0 */ /*! @{ */ + #define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U) /* Merged from fields with different position or width, of widths (7, 10), largest definition used */ #define ENET_MRBR_R_BUF_SIZE_SHIFT (4U) #define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK) /* Merged from fields with different position or width, of widths (7, 10), largest definition used */ @@ -28989,6 +36170,7 @@ typedef struct { /*! @name RSFL - Receive FIFO Section Full Threshold */ /*! @{ */ + #define ENET_RSFL_RX_SECTION_FULL_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */ #define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U) /*! RX_SECTION_FULL - Value Of Receive FIFO Section Full Threshold @@ -28998,11 +36180,13 @@ typedef struct { /*! @name RSEM - Receive FIFO Section Empty Threshold */ /*! @{ */ + #define ENET_RSEM_RX_SECTION_EMPTY_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */ #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U) /*! RX_SECTION_EMPTY - Value Of The Receive FIFO Section Empty Threshold */ #define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */ + #define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U) #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U) /*! STAT_SECTION_EMPTY - RX Status FIFO Section Empty Threshold @@ -29012,6 +36196,7 @@ typedef struct { /*! @name RAEM - Receive FIFO Almost Empty Threshold */ /*! @{ */ + #define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */ #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U) /*! RX_ALMOST_EMPTY - Value Of The Receive FIFO Almost Empty Threshold @@ -29021,6 +36206,7 @@ typedef struct { /*! @name RAFL - Receive FIFO Almost Full Threshold */ /*! @{ */ + #define ENET_RAFL_RX_ALMOST_FULL_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */ #define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U) /*! RX_ALMOST_FULL - Value Of The Receive FIFO Almost Full Threshold @@ -29030,6 +36216,7 @@ typedef struct { /*! @name TSEM - Transmit FIFO Section Empty Threshold */ /*! @{ */ + #define ENET_TSEM_TX_SECTION_EMPTY_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */ #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U) /*! TX_SECTION_EMPTY - Value Of The Transmit FIFO Section Empty Threshold @@ -29039,6 +36226,7 @@ typedef struct { /*! @name TAEM - Transmit FIFO Almost Empty Threshold */ /*! @{ */ + #define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */ #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U) /*! TX_ALMOST_EMPTY - Value of Transmit FIFO Almost Empty Threshold @@ -29048,6 +36236,7 @@ typedef struct { /*! @name TAFL - Transmit FIFO Almost Full Threshold */ /*! @{ */ + #define ENET_TAFL_TX_ALMOST_FULL_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */ #define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U) /*! TX_ALMOST_FULL - Value Of The Transmit FIFO Almost Full Threshold @@ -29057,6 +36246,7 @@ typedef struct { /*! @name TIPG - Transmit Inter-Packet Gap */ /*! @{ */ + #define ENET_TIPG_IPG_MASK (0x1FU) #define ENET_TIPG_IPG_SHIFT (0U) /*! IPG - Transmit Inter-Packet Gap @@ -29066,6 +36256,7 @@ typedef struct { /*! @name FTRL - Frame Truncation Length */ /*! @{ */ + #define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU) #define ENET_FTRL_TRUNC_FL_SHIFT (0U) /*! TRUNC_FL - Frame Truncation Length @@ -29075,6 +36266,7 @@ typedef struct { /*! @name TACC - Transmit Accelerator Function Configuration */ /*! @{ */ + #define ENET_TACC_SHIFT16_MASK (0x1U) #define ENET_TACC_SHIFT16_SHIFT (0U) /*! SHIFT16 - TX FIFO Shift-16 @@ -29085,6 +36277,7 @@ typedef struct { * extended to a 16-byte header. */ #define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK) + #define ENET_TACC_IPCHK_MASK (0x8U) #define ENET_TACC_IPCHK_SHIFT (3U) /*! IPCHK @@ -29093,6 +36286,7 @@ typedef struct { * be cleared. If a non-IP frame is transmitted the frame is not modified. */ #define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK) + #define ENET_TACC_PROCHK_MASK (0x10U) #define ENET_TACC_PROCHK_SHIFT (4U) /*! PROCHK @@ -29105,6 +36299,7 @@ typedef struct { /*! @name RACC - Receive Accelerator Function Configuration */ /*! @{ */ + #define ENET_RACC_PADREM_MASK (0x1U) #define ENET_RACC_PADREM_SHIFT (0U) /*! PADREM - Enable Padding Removal For Short IP Frames @@ -29112,6 +36307,7 @@ typedef struct { * 0b1..Any bytes following the IP payload section of the frame are removed from the frame. */ #define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK) + #define ENET_RACC_IPDIS_MASK (0x2U) #define ENET_RACC_IPDIS_SHIFT (1U) /*! IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum @@ -29121,6 +36317,7 @@ typedef struct { * store and forward mode (RSFL cleared). */ #define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK) + #define ENET_RACC_PRODIS_MASK (0x4U) #define ENET_RACC_PRODIS_SHIFT (2U) /*! PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum @@ -29130,6 +36327,7 @@ typedef struct { * cleared). */ #define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK) + #define ENET_RACC_LINEDIS_MASK (0x40U) #define ENET_RACC_LINEDIS_SHIFT (6U) /*! LINEDIS - Enable Discard Of Frames With MAC Layer Errors @@ -29137,6 +36335,7 @@ typedef struct { * 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface. */ #define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK) + #define ENET_RACC_SHIFT16_MASK (0x80U) #define ENET_RACC_SHIFT16_SHIFT (7U) /*! SHIFT16 - RX FIFO Shift-16 @@ -29148,26 +36347,31 @@ typedef struct { /*! @name RCMR - Receive Classification Match Register for Class n */ /*! @{ */ + #define ENET_RCMR_CMP0_MASK (0x7U) #define ENET_RCMR_CMP0_SHIFT (0U) /*! CMP0 - Compare 0 */ #define ENET_RCMR_CMP0(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP0_SHIFT)) & ENET_RCMR_CMP0_MASK) + #define ENET_RCMR_CMP1_MASK (0x70U) #define ENET_RCMR_CMP1_SHIFT (4U) /*! CMP1 - Compare 1 */ #define ENET_RCMR_CMP1(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP1_SHIFT)) & ENET_RCMR_CMP1_MASK) + #define ENET_RCMR_CMP2_MASK (0x700U) #define ENET_RCMR_CMP2_SHIFT (8U) /*! CMP2 - Compare 2 */ #define ENET_RCMR_CMP2(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP2_SHIFT)) & ENET_RCMR_CMP2_MASK) + #define ENET_RCMR_CMP3_MASK (0x7000U) #define ENET_RCMR_CMP3_SHIFT (12U) /*! CMP3 - Compare 3 */ #define ENET_RCMR_CMP3(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP3_SHIFT)) & ENET_RCMR_CMP3_MASK) + #define ENET_RCMR_MATCHEN_MASK (0x10000U) #define ENET_RCMR_MATCHEN_SHIFT (16U) /*! MATCHEN - Match Enable @@ -29182,11 +36386,13 @@ typedef struct { /*! @name DMACFG - DMA Class Based Configuration */ /*! @{ */ + #define ENET_DMACFG_IDLE_SLOPE_MASK (0xFFFFU) #define ENET_DMACFG_IDLE_SLOPE_SHIFT (0U) /*! IDLE_SLOPE - Idle slope */ #define ENET_DMACFG_IDLE_SLOPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_IDLE_SLOPE_SHIFT)) & ENET_DMACFG_IDLE_SLOPE_MASK) + #define ENET_DMACFG_DMA_CLASS_EN_MASK (0x10000U) #define ENET_DMACFG_DMA_CLASS_EN_SHIFT (16U) /*! DMA_CLASS_EN - DMA class enable @@ -29196,6 +36402,7 @@ typedef struct { * 0b1..Enable the DMA controller to support the corresponding descriptor ring for this class of traffic. */ #define ENET_DMACFG_DMA_CLASS_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_DMA_CLASS_EN_SHIFT)) & ENET_DMACFG_DMA_CLASS_EN_MASK) + #define ENET_DMACFG_CALC_NOIPG_MASK (0x20000U) #define ENET_DMACFG_CALC_NOIPG_SHIFT (17U) /*! CALC_NOIPG - Calculate no IPG @@ -29214,6 +36421,7 @@ typedef struct { /*! @name RDAR1 - Receive Descriptor Active Register - Ring 1 */ /*! @{ */ + #define ENET_RDAR1_RDAR_MASK (0x1000000U) #define ENET_RDAR1_RDAR_SHIFT (24U) /*! RDAR - Receive Descriptor Active @@ -29223,6 +36431,7 @@ typedef struct { /*! @name TDAR1 - Transmit Descriptor Active Register - Ring 1 */ /*! @{ */ + #define ENET_TDAR1_TDAR_MASK (0x1000000U) #define ENET_TDAR1_TDAR_SHIFT (24U) /*! TDAR - Transmit Descriptor Active @@ -29232,6 +36441,7 @@ typedef struct { /*! @name RDAR2 - Receive Descriptor Active Register - Ring 2 */ /*! @{ */ + #define ENET_RDAR2_RDAR_MASK (0x1000000U) #define ENET_RDAR2_RDAR_SHIFT (24U) /*! RDAR - Receive Descriptor Active @@ -29241,6 +36451,7 @@ typedef struct { /*! @name TDAR2 - Transmit Descriptor Active Register - Ring 2 */ /*! @{ */ + #define ENET_TDAR2_TDAR_MASK (0x1000000U) #define ENET_TDAR2_TDAR_SHIFT (24U) /*! TDAR - Transmit Descriptor Active @@ -29250,6 +36461,7 @@ typedef struct { /*! @name QOS - QOS Scheme */ /*! @{ */ + #define ENET_QOS_TX_SCHEME_MASK (0x7U) #define ENET_QOS_TX_SCHEME_SHIFT (0U) /*! TX_SCHEME - TX scheme configuration @@ -29258,6 +36470,7 @@ typedef struct { * 0b010-0b111..Reserved */ #define ENET_QOS_TX_SCHEME(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_TX_SCHEME_SHIFT)) & ENET_QOS_TX_SCHEME_MASK) + #define ENET_QOS_RX_FLUSH0_MASK (0x8U) #define ENET_QOS_RX_FLUSH0_SHIFT (3U) /*! RX_FLUSH0 - RX Flush Ring 0 @@ -29265,6 +36478,7 @@ typedef struct { * 0b1..Enable */ #define ENET_QOS_RX_FLUSH0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH0_SHIFT)) & ENET_QOS_RX_FLUSH0_MASK) + #define ENET_QOS_RX_FLUSH1_MASK (0x10U) #define ENET_QOS_RX_FLUSH1_SHIFT (4U) /*! RX_FLUSH1 - RX Flush Ring 1 @@ -29272,6 +36486,7 @@ typedef struct { * 0b1..Enable */ #define ENET_QOS_RX_FLUSH1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH1_SHIFT)) & ENET_QOS_RX_FLUSH1_MASK) + #define ENET_QOS_RX_FLUSH2_MASK (0x20U) #define ENET_QOS_RX_FLUSH2_SHIFT (5U) /*! RX_FLUSH2 - RX Flush Ring 2 @@ -29283,6 +36498,7 @@ typedef struct { /*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */ /*! @{ */ + #define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U) /*! TXPKTS - Packet count @@ -29292,6 +36508,7 @@ typedef struct { /*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */ /*! @{ */ + #define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U) /*! TXPKTS - Broadcast packets @@ -29301,6 +36518,7 @@ typedef struct { /*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */ /*! @{ */ + #define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U) /*! TXPKTS - Multicast packets @@ -29310,6 +36528,7 @@ typedef struct { /*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */ /*! @{ */ + #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U) /*! TXPKTS - Packets with CRC/align error @@ -29319,6 +36538,7 @@ typedef struct { /*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */ /*! @{ */ + #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U) /*! TXPKTS - Number of transmit packets less than 64 bytes with good CRC @@ -29328,6 +36548,7 @@ typedef struct { /*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */ /*! @{ */ + #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U) /*! TXPKTS - Number of transmit packets greater than MAX_FL bytes with good CRC @@ -29337,6 +36558,7 @@ typedef struct { /*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ /*! @{ */ + #define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U) /*! TXPKTS - Number of packets less than 64 bytes with bad CRC @@ -29346,6 +36568,7 @@ typedef struct { /*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */ /*! @{ */ + #define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U) /*! TXPKTS - Number of transmit packets greater than MAX_FL bytes and bad CRC @@ -29355,6 +36578,7 @@ typedef struct { /*! @name RMON_T_COL - Tx Collision Count Statistic Register */ /*! @{ */ + #define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_COL_TXPKTS_SHIFT (0U) /*! TXPKTS - Number of transmit collisions @@ -29364,6 +36588,7 @@ typedef struct { /*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */ /*! @{ */ + #define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P64_TXPKTS_SHIFT (0U) /*! TXPKTS - Number of 64-byte transmit packets @@ -29373,6 +36598,7 @@ typedef struct { /*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */ /*! @{ */ + #define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U) /*! TXPKTS - Number of 65- to 127-byte transmit packets @@ -29382,6 +36608,7 @@ typedef struct { /*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */ /*! @{ */ + #define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U) /*! TXPKTS - Number of 128- to 255-byte transmit packets @@ -29391,6 +36618,7 @@ typedef struct { /*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */ /*! @{ */ + #define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U) /*! TXPKTS - Number of 256- to 511-byte transmit packets @@ -29400,6 +36628,7 @@ typedef struct { /*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */ /*! @{ */ + #define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U) /*! TXPKTS - Number of 512- to 1023-byte transmit packets @@ -29409,6 +36638,7 @@ typedef struct { /*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */ /*! @{ */ + #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U) /*! TXPKTS - Number of 1024- to 2047-byte transmit packets @@ -29418,6 +36648,7 @@ typedef struct { /*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */ /*! @{ */ + #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU) #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U) /*! TXPKTS - Number of transmit packets greater than 2048 bytes @@ -29427,6 +36658,7 @@ typedef struct { /*! @name RMON_T_OCTETS - Tx Octets Statistic Register */ /*! @{ */ + #define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU) #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U) /*! TXOCTS - Number of transmit octets @@ -29436,6 +36668,7 @@ typedef struct { /*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */ /*! @{ */ + #define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U) /*! COUNT - Number of frames transmitted OK @@ -29445,6 +36678,7 @@ typedef struct { /*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */ /*! @{ */ + #define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_1COL_COUNT_SHIFT (0U) /*! COUNT - Number of frames transmitted with one collision @@ -29454,6 +36688,7 @@ typedef struct { /*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */ /*! @{ */ + #define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U) /*! COUNT - Number of frames transmitted with multiple collisions @@ -29463,6 +36698,7 @@ typedef struct { /*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */ /*! @{ */ + #define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_DEF_COUNT_SHIFT (0U) /*! COUNT - Number of frames transmitted with deferral delay @@ -29472,6 +36708,7 @@ typedef struct { /*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */ /*! @{ */ + #define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U) /*! COUNT - Number of frames transmitted with late collision @@ -29481,6 +36718,7 @@ typedef struct { /*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */ /*! @{ */ + #define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U) /*! COUNT - Number of frames transmitted with excessive collisions @@ -29490,6 +36728,7 @@ typedef struct { /*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */ /*! @{ */ + #define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U) /*! COUNT - Number of frames transmitted with transmit FIFO underrun @@ -29499,6 +36738,7 @@ typedef struct { /*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */ /*! @{ */ + #define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U) /*! COUNT - Number of frames transmitted with carrier sense error @@ -29508,6 +36748,7 @@ typedef struct { /*! @name IEEE_T_SQE - Reserved Statistic Register */ /*! @{ */ + #define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_SQE_COUNT_SHIFT (0U) /*! COUNT - This read-only field is reserved and always has the value 0 @@ -29517,6 +36758,7 @@ typedef struct { /*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */ /*! @{ */ + #define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU) #define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U) /*! COUNT - Number of flow-control pause frames transmitted @@ -29526,6 +36768,7 @@ typedef struct { /*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */ /*! @{ */ + #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U) /*! COUNT - Octet count for frames transmitted without error Counts total octets (includes header and FCS fields). @@ -29535,6 +36778,7 @@ typedef struct { /*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */ /*! @{ */ + #define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U) /*! COUNT - Number of packets received @@ -29544,6 +36788,7 @@ typedef struct { /*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */ /*! @{ */ + #define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U) /*! COUNT - Number of receive broadcast packets @@ -29553,6 +36798,7 @@ typedef struct { /*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */ /*! @{ */ + #define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U) /*! COUNT - Number of receive multicast packets @@ -29562,6 +36808,7 @@ typedef struct { /*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */ /*! @{ */ + #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U) /*! COUNT - Number of receive packets with CRC or align error @@ -29571,6 +36818,7 @@ typedef struct { /*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */ /*! @{ */ + #define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U) /*! COUNT - Number of receive packets with less than 64 bytes and good CRC @@ -29580,6 +36828,7 @@ typedef struct { /*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */ /*! @{ */ + #define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U) /*! COUNT - Number of receive packets greater than MAX_FL and good CRC @@ -29589,6 +36838,7 @@ typedef struct { /*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */ /*! @{ */ + #define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_FRAG_COUNT_SHIFT (0U) /*! COUNT - Number of receive packets with less than 64 bytes and bad CRC @@ -29598,6 +36848,7 @@ typedef struct { /*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */ /*! @{ */ + #define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_JAB_COUNT_SHIFT (0U) /*! COUNT - Number of receive packets greater than MAX_FL and bad CRC @@ -29607,6 +36858,7 @@ typedef struct { /*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */ /*! @{ */ + #define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P64_COUNT_SHIFT (0U) /*! COUNT - Number of 64-byte receive packets @@ -29616,6 +36868,7 @@ typedef struct { /*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */ /*! @{ */ + #define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U) /*! COUNT - Number of 65- to 127-byte recieve packets @@ -29625,6 +36878,7 @@ typedef struct { /*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */ /*! @{ */ + #define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U) /*! COUNT - Number of 128- to 255-byte recieve packets @@ -29634,6 +36888,7 @@ typedef struct { /*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */ /*! @{ */ + #define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U) /*! COUNT - Number of 256- to 511-byte recieve packets @@ -29643,6 +36898,7 @@ typedef struct { /*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */ /*! @{ */ + #define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U) /*! COUNT - Number of 512- to 1023-byte recieve packets @@ -29652,6 +36908,7 @@ typedef struct { /*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */ /*! @{ */ + #define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U) /*! COUNT - Number of 1024- to 2047-byte recieve packets @@ -29661,6 +36918,7 @@ typedef struct { /*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */ /*! @{ */ + #define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU) #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U) /*! COUNT - Number of greater-than-2048-byte recieve packets @@ -29670,6 +36928,7 @@ typedef struct { /*! @name RMON_R_OCTETS - Rx Octets Statistic Register */ /*! @{ */ + #define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU) #define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U) /*! COUNT - Number of receive octets @@ -29679,6 +36938,7 @@ typedef struct { /*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */ /*! @{ */ + #define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_DROP_COUNT_SHIFT (0U) /*! COUNT - Frame count @@ -29688,6 +36948,7 @@ typedef struct { /*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */ /*! @{ */ + #define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U) /*! COUNT - Number of frames received OK @@ -29697,6 +36958,7 @@ typedef struct { /*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */ /*! @{ */ + #define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_CRC_COUNT_SHIFT (0U) /*! COUNT - Number of frames received with CRC error @@ -29706,6 +36968,7 @@ typedef struct { /*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */ /*! @{ */ + #define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U) /*! COUNT - Number of frames received with alignment error @@ -29715,6 +36978,7 @@ typedef struct { /*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */ /*! @{ */ + #define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U) /*! COUNT - Receive FIFO overflow count @@ -29724,6 +36988,7 @@ typedef struct { /*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */ /*! @{ */ + #define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU) #define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U) /*! COUNT - Number of flow-control pause frames received @@ -29733,6 +36998,7 @@ typedef struct { /*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */ /*! @{ */ + #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU) #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U) /*! COUNT - Number of octets for frames received without error @@ -29742,6 +37008,7 @@ typedef struct { /*! @name ATCR - Adjustable Timer Control Register */ /*! @{ */ + #define ENET_ATCR_EN_MASK (0x1U) #define ENET_ATCR_EN_SHIFT (0U) /*! EN - Enable Timer @@ -29749,6 +37016,7 @@ typedef struct { * 0b1..The timer starts incrementing. */ #define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK) + #define ENET_ATCR_OFFEN_MASK (0x4U) #define ENET_ATCR_OFFEN_SHIFT (2U) /*! OFFEN - Enable One-Shot Offset Event @@ -29758,6 +37026,7 @@ typedef struct { * offset value must be set before setting this field. */ #define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK) + #define ENET_ATCR_OFFRST_MASK (0x8U) #define ENET_ATCR_OFFRST_SHIFT (3U) /*! OFFRST - Reset Timer On Offset Event @@ -29765,6 +37034,7 @@ typedef struct { * 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt. */ #define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK) + #define ENET_ATCR_PEREN_MASK (0x10U) #define ENET_ATCR_PEREN_SHIFT (4U) /*! PEREN - Enable Periodical Event @@ -29774,6 +37044,7 @@ typedef struct { * setting this bit. Not all devices contain the event signal output. See the chip configuration details. */ #define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK) + #define ENET_ATCR_PINPER_MASK (0x80U) #define ENET_ATCR_PINPER_SHIFT (7U) /*! PINPER - Enables event signal output external pin frc_evt_period assertion on period event @@ -29781,11 +37052,13 @@ typedef struct { * 0b1..Enable. */ #define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK) + #define ENET_ATCR_RESTART_MASK (0x200U) #define ENET_ATCR_RESTART_SHIFT (9U) /*! RESTART - Reset Timer */ #define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK) + #define ENET_ATCR_CAPTURE_MASK (0x800U) #define ENET_ATCR_CAPTURE_SHIFT (11U) /*! CAPTURE - Capture Timer Value @@ -29793,6 +37066,7 @@ typedef struct { * 0b1..The current time is captured and can be read from the ATVR register. */ #define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK) + #define ENET_ATCR_SLAVE_MASK (0x2000U) #define ENET_ATCR_SLAVE_SHIFT (13U) /*! SLAVE - Enable Timer Slave Mode @@ -29805,6 +37079,7 @@ typedef struct { /*! @name ATVR - Timer Value Register */ /*! @{ */ + #define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU) #define ENET_ATVR_ATIME_SHIFT (0U) #define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK) @@ -29812,6 +37087,7 @@ typedef struct { /*! @name ATOFF - Timer Offset Register */ /*! @{ */ + #define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU) #define ENET_ATOFF_OFFSET_SHIFT (0U) #define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK) @@ -29819,6 +37095,7 @@ typedef struct { /*! @name ATPER - Timer Period Register */ /*! @{ */ + #define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU) #define ENET_ATPER_PERIOD_SHIFT (0U) /*! PERIOD - Value for generating periodic events @@ -29828,6 +37105,7 @@ typedef struct { /*! @name ATCOR - Timer Correction Register */ /*! @{ */ + #define ENET_ATCOR_COR_MASK (0x7FFFFFFFU) #define ENET_ATCOR_COR_SHIFT (0U) /*! COR - Correction Counter Wrap-Around Value @@ -29837,11 +37115,13 @@ typedef struct { /*! @name ATINC - Time-Stamping Clock Period Register */ /*! @{ */ + #define ENET_ATINC_INC_MASK (0x7FU) #define ENET_ATINC_INC_SHIFT (0U) /*! INC - Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds */ #define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK) + #define ENET_ATINC_INC_CORR_MASK (0x7F00U) #define ENET_ATINC_INC_CORR_SHIFT (8U) /*! INC_CORR - Correction Increment Value @@ -29851,6 +37131,7 @@ typedef struct { /*! @name ATSTMP - Timestamp of Last Transmitted Frame */ /*! @{ */ + #define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU) #define ENET_ATSTMP_TIMESTAMP_SHIFT (0U) /*! TIMESTAMP - Timestamp of the last frame transmitted by the core that had TxBD[TS] set the @@ -29861,6 +37142,7 @@ typedef struct { /*! @name TGSR - Timer Global Status Register */ /*! @{ */ + #define ENET_TGSR_TF0_MASK (0x1U) #define ENET_TGSR_TF0_SHIFT (0U) /*! TF0 - Copy Of Timer Flag For Channel 0 @@ -29868,6 +37150,7 @@ typedef struct { * 0b1..Timer Flag for Channel 0 is set */ #define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK) + #define ENET_TGSR_TF1_MASK (0x2U) #define ENET_TGSR_TF1_SHIFT (1U) /*! TF1 - Copy Of Timer Flag For Channel 1 @@ -29875,6 +37158,7 @@ typedef struct { * 0b1..Timer Flag for Channel 1 is set */ #define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK) + #define ENET_TGSR_TF2_MASK (0x4U) #define ENET_TGSR_TF2_SHIFT (2U) /*! TF2 - Copy Of Timer Flag For Channel 2 @@ -29882,6 +37166,7 @@ typedef struct { * 0b1..Timer Flag for Channel 2 is set */ #define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK) + #define ENET_TGSR_TF3_MASK (0x8U) #define ENET_TGSR_TF3_SHIFT (3U) /*! TF3 - Copy Of Timer Flag For Channel 3 @@ -29893,6 +37178,7 @@ typedef struct { /*! @name TCSR - Timer Control Status Register */ /*! @{ */ + #define ENET_TCSR_TDRE_MASK (0x1U) #define ENET_TCSR_TDRE_SHIFT (0U) /*! TDRE - Timer DMA Request Enable @@ -29900,6 +37186,7 @@ typedef struct { * 0b1..DMA request is enabled */ #define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK) + #define ENET_TCSR_TMODE_MASK (0x3CU) #define ENET_TCSR_TMODE_SHIFT (2U) /*! TMODE - Timer Mode @@ -29919,6 +37206,7 @@ typedef struct { * 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588-clock cycle. */ #define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK) + #define ENET_TCSR_TIE_MASK (0x40U) #define ENET_TCSR_TIE_SHIFT (6U) /*! TIE - Timer Interrupt Enable @@ -29926,6 +37214,7 @@ typedef struct { * 0b1..Interrupt is enabled */ #define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK) + #define ENET_TCSR_TF_MASK (0x80U) #define ENET_TCSR_TF_SHIFT (7U) /*! TF - Timer Flag @@ -29933,6 +37222,7 @@ typedef struct { * 0b1..Input Capture or Output Compare has occurred. */ #define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK) + #define ENET_TCSR_TPWC_MASK (0xF800U) #define ENET_TCSR_TPWC_SHIFT (11U) /*! TPWC - Timer PulseWidth Control @@ -29950,6 +37240,7 @@ typedef struct { /*! @name TCCR - Timer Compare Capture Register */ /*! @{ */ + #define ENET_TCCR_TCC_MASK (0xFFFFFFFFU) #define ENET_TCCR_TCC_SHIFT (0U) /*! TCC - Timer Capture Compare @@ -30007,7 +37298,7 @@ typedef struct { typedef struct { __IO uint32_t MAC_CONFIGURATION; /**< MAC Configuration Register, offset: 0x0 */ __IO uint32_t MAC_EXT_CONFIGURATION; /**< MAC Extended Configuration Register, offset: 0x4 */ - __IO uint32_t MAC_PACKET_FILTER; /**< MAC_Packet_Filter, offset: 0x8 */ + __IO uint32_t MAC_PACKET_FILTER; /**< MAC Packet Filter, offset: 0x8 */ __IO uint32_t MAC_WATCHDOG_TIMEOUT; /**< Watchdog Timeout, offset: 0xC */ __IO uint32_t MAC_HASH_TABLE_REG0; /**< MAC Hash Table Register 0, offset: 0x10 */ __IO uint32_t MAC_HASH_TABLE_REG1; /**< MAC Hash Table Register 1, offset: 0x14 */ @@ -30019,7 +37310,7 @@ typedef struct { __IO uint32_t MAC_VLAN_INCL; /**< VLAN Tag Inclusion or Replacement, offset: 0x60 */ __IO uint32_t MAC_INNER_VLAN_INCL; /**< MAC Inner VLAN Tag Inclusion or Replacement, offset: 0x64 */ uint8_t RESERVED_2[8]; - __IO uint32_t MAC_TX_FLOW_CTRL_Q[5]; /**< MAC Q0 Tx Flow Control, array offset: 0x70, array step: 0x4 */ + __IO uint32_t MAC_TX_FLOW_CTRL_Q[5]; /**< MAC Q0 Tx Flow Control..MAC Q4 Tx Flow Control, array offset: 0x70, array step: 0x4 */ uint8_t RESERVED_3[12]; __IO uint32_t MAC_RX_FLOW_CTRL; /**< MAC Rx Flow Control, offset: 0x90 */ __IO uint32_t MAC_RXQ_CTRL4; /**< Receive Queue Control 4, offset: 0x94 */ @@ -30390,6 +37681,7 @@ typedef struct { /*! @name MAC_CONFIGURATION - MAC Configuration Register */ /*! @{ */ + #define ENET_QOS_MAC_CONFIGURATION_RE_MASK (0x1U) #define ENET_QOS_MAC_CONFIGURATION_RE_SHIFT (0U) /*! RE - Receiver Enable @@ -30397,102 +37689,107 @@ typedef struct { * 0b1..Receiver is enabled */ #define ENET_QOS_MAC_CONFIGURATION_RE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_RE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_RE_MASK) + #define ENET_QOS_MAC_CONFIGURATION_TE_MASK (0x2U) #define ENET_QOS_MAC_CONFIGURATION_TE_SHIFT (1U) -/*! TE - Transmitter Enable When this bit is set, the Tx state machine of the MAC is enabled for - * transmission on the GMII or MII interface. +/*! TE - Transmitter Enable * 0b0..Transmitter is disabled * 0b1..Transmitter is enabled */ #define ENET_QOS_MAC_CONFIGURATION_TE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_TE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_TE_MASK) + #define ENET_QOS_MAC_CONFIGURATION_PRELEN_MASK (0xCU) #define ENET_QOS_MAC_CONFIGURATION_PRELEN_SHIFT (2U) -/*! PRELEN - Preamble Length for Transmit packets These bits control the number of preamble bytes - * that are added to the beginning of every Tx packet. +/*! PRELEN - Preamble Length for Transmit packets * 0b10..3 bytes of preamble * 0b01..5 bytes of preamble * 0b00..7 bytes of preamble * 0b11..Reserved */ #define ENET_QOS_MAC_CONFIGURATION_PRELEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_PRELEN_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_PRELEN_MASK) + #define ENET_QOS_MAC_CONFIGURATION_DC_MASK (0x10U) #define ENET_QOS_MAC_CONFIGURATION_DC_SHIFT (4U) -/*! DC - Deferral Check When this bit is set, the deferral check function is enabled in the MAC. +/*! DC - Deferral Check * 0b0..Deferral check function is disabled * 0b1..Deferral check function is enabled */ #define ENET_QOS_MAC_CONFIGURATION_DC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DC_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DC_MASK) + #define ENET_QOS_MAC_CONFIGURATION_BL_MASK (0x60U) #define ENET_QOS_MAC_CONFIGURATION_BL_SHIFT (5U) -/*! BL - Back-Off Limit The back-off limit determines the random integer number (r) of slot time - * delays (4,096 bit times for 1000/2500 Mbps; 512 bit times for 10/100 Mbps) for which the MAC - * waits before rescheduling a transmission attempt during retries after a collision. +/*! BL - Back-Off Limit * 0b11..k = min(n,1) * 0b00..k = min(n,10) * 0b10..k = min(n,4) * 0b01..k = min(n,8) */ #define ENET_QOS_MAC_CONFIGURATION_BL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_BL_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_BL_MASK) + #define ENET_QOS_MAC_CONFIGURATION_DR_MASK (0x100U) #define ENET_QOS_MAC_CONFIGURATION_DR_SHIFT (8U) -/*! DR - Disable Retry When this bit is set, the MAC attempts only one transmission. +/*! DR - Disable Retry * 0b1..Disable Retry * 0b0..Enable Retry */ #define ENET_QOS_MAC_CONFIGURATION_DR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DR_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DR_MASK) + #define ENET_QOS_MAC_CONFIGURATION_DCRS_MASK (0x200U) #define ENET_QOS_MAC_CONFIGURATION_DCRS_SHIFT (9U) -/*! DCRS - Disable Carrier Sense During Transmission When this bit is set, the MAC transmitter - * ignores the (G)MII CRS signal during packet transmission in the half-duplex mode. +/*! DCRS - Disable Carrier Sense During Transmission * 0b1..Disable Carrier Sense During Transmission * 0b0..Enable Carrier Sense During Transmission */ #define ENET_QOS_MAC_CONFIGURATION_DCRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DCRS_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DCRS_MASK) + #define ENET_QOS_MAC_CONFIGURATION_DO_MASK (0x400U) #define ENET_QOS_MAC_CONFIGURATION_DO_SHIFT (10U) -/*! DO - Disable Receive Own When this bit is set, the MAC disables the reception of packets when - * the gmii_txen_o is asserted in the half-duplex mode. +/*! DO - Disable Receive Own * 0b1..Disable Receive Own * 0b0..Enable Receive Own */ #define ENET_QOS_MAC_CONFIGURATION_DO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DO_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DO_MASK) + #define ENET_QOS_MAC_CONFIGURATION_ECRSFD_MASK (0x800U) #define ENET_QOS_MAC_CONFIGURATION_ECRSFD_SHIFT (11U) -/*! ECRSFD - Enable Carrier Sense Before Transmission in Full-Duplex Mode When this bit is set, the - * MAC transmitter checks the CRS signal before packet transmission in the full-duplex mode. +/*! ECRSFD - Enable Carrier Sense Before Transmission in Full-Duplex Mode * 0b0..ECRSFD is disabled * 0b1..ECRSFD is enabled */ #define ENET_QOS_MAC_CONFIGURATION_ECRSFD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_ECRSFD_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_ECRSFD_MASK) + #define ENET_QOS_MAC_CONFIGURATION_LM_MASK (0x1000U) #define ENET_QOS_MAC_CONFIGURATION_LM_SHIFT (12U) -/*! LM - Loopback Mode When this bit is set, the MAC operates in the loopback mode at GMII or MII. +/*! LM - Loopback Mode * 0b0..Loopback is disabled * 0b1..Loopback is enabled */ #define ENET_QOS_MAC_CONFIGURATION_LM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_LM_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_LM_MASK) + #define ENET_QOS_MAC_CONFIGURATION_DM_MASK (0x2000U) #define ENET_QOS_MAC_CONFIGURATION_DM_SHIFT (13U) -/*! DM - Duplex Mode When this bit is set, the MAC operates in the full-duplex mode in which it can - * transmit and receive simultaneously. +/*! DM - Duplex Mode * 0b1..Full-duplex mode * 0b0..Half-duplex mode */ #define ENET_QOS_MAC_CONFIGURATION_DM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DM_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DM_MASK) + #define ENET_QOS_MAC_CONFIGURATION_FES_MASK (0x4000U) #define ENET_QOS_MAC_CONFIGURATION_FES_SHIFT (14U) -/*! FES - Speed This bit selects the speed mode. +/*! FES - Speed * 0b1..100 Mbps when PS bit is 1 and 2.5 Gbps when PS bit is 0 * 0b0..10 Mbps when PS bit is 1 and 1 Gbps when PS bit is 0 */ #define ENET_QOS_MAC_CONFIGURATION_FES(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_FES_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_FES_MASK) + #define ENET_QOS_MAC_CONFIGURATION_PS_MASK (0x8000U) #define ENET_QOS_MAC_CONFIGURATION_PS_SHIFT (15U) -/*! PS - Port Select This bit selects the Ethernet line speed. +/*! PS - Port Select * 0b0..For 1000 or 2500 Mbps operations * 0b1..For 10 or 100 Mbps operations */ #define ENET_QOS_MAC_CONFIGURATION_PS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_PS_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_PS_MASK) + #define ENET_QOS_MAC_CONFIGURATION_JE_MASK (0x10000U) #define ENET_QOS_MAC_CONFIGURATION_JE_SHIFT (16U) /*! JE - Jumbo Packet Enable When this bit is set, the MAC allows jumbo packets of 9,018 bytes @@ -30502,13 +37799,15 @@ typedef struct { * 0b1..Jumbo packet is enabled */ #define ENET_QOS_MAC_CONFIGURATION_JE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_JE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_JE_MASK) + #define ENET_QOS_MAC_CONFIGURATION_JD_MASK (0x20000U) #define ENET_QOS_MAC_CONFIGURATION_JD_SHIFT (17U) -/*! JD - Jabber Disable When this bit is set, the MAC disables the jabber timer on the transmitter. +/*! JD - Jabber Disable * 0b1..Jabber is disabled * 0b0..Jabber is enabled */ #define ENET_QOS_MAC_CONFIGURATION_JD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_JD_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_JD_MASK) + #define ENET_QOS_MAC_CONFIGURATION_BE_MASK (0x40000U) #define ENET_QOS_MAC_CONFIGURATION_BE_SHIFT (18U) /*! BE - Packet Burst Enable When this bit is set, the MAC allows packet bursting during @@ -30517,13 +37816,15 @@ typedef struct { * 0b1..Packet Burst is enabled */ #define ENET_QOS_MAC_CONFIGURATION_BE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_BE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_BE_MASK) + #define ENET_QOS_MAC_CONFIGURATION_WD_MASK (0x80000U) #define ENET_QOS_MAC_CONFIGURATION_WD_SHIFT (19U) -/*! WD - Watchdog Disable When this bit is set, the MAC disables the watchdog timer on the receiver. +/*! WD - Watchdog Disable * 0b1..Watchdog is disabled * 0b0..Watchdog is enabled */ #define ENET_QOS_MAC_CONFIGURATION_WD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_WD_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_WD_MASK) + #define ENET_QOS_MAC_CONFIGURATION_ACS_MASK (0x100000U) #define ENET_QOS_MAC_CONFIGURATION_ACS_SHIFT (20U) /*! ACS - Automatic Pad or CRC Stripping When this bit is set, the MAC strips the Pad or FCS field @@ -30532,6 +37833,7 @@ typedef struct { * 0b1..Automatic Pad or CRC Stripping is enabled */ #define ENET_QOS_MAC_CONFIGURATION_ACS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_ACS_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_ACS_MASK) + #define ENET_QOS_MAC_CONFIGURATION_CST_MASK (0x200000U) #define ENET_QOS_MAC_CONFIGURATION_CST_SHIFT (21U) /*! CST - CRC stripping for Type packets When this bit is set, the last four bytes (FCS) of all @@ -30541,6 +37843,7 @@ typedef struct { * 0b1..CRC stripping for Type packets is enabled */ #define ENET_QOS_MAC_CONFIGURATION_CST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_CST_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_CST_MASK) + #define ENET_QOS_MAC_CONFIGURATION_S2KP_MASK (0x400000U) #define ENET_QOS_MAC_CONFIGURATION_S2KP_SHIFT (22U) /*! S2KP - IEEE 802. @@ -30548,14 +37851,15 @@ typedef struct { * 0b1..Support upto 2K packet is Enabled */ #define ENET_QOS_MAC_CONFIGURATION_S2KP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_S2KP_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_S2KP_MASK) + #define ENET_QOS_MAC_CONFIGURATION_GPSLCE_MASK (0x800000U) #define ENET_QOS_MAC_CONFIGURATION_GPSLCE_SHIFT (23U) -/*! GPSLCE - Giant Packet Size Limit Control Enable When this bit is set, the MAC considers the - * value in GPSL field in MAC_EXT_CONFIGURATION register to declare a received packet as Giant packet. +/*! GPSLCE - Giant Packet Size Limit Control Enable * 0b0..Giant Packet Size Limit Control is disabled * 0b1..Giant Packet Size Limit Control is enabled */ #define ENET_QOS_MAC_CONFIGURATION_GPSLCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_GPSLCE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_GPSLCE_MASK) + #define ENET_QOS_MAC_CONFIGURATION_IPG_MASK (0x7000000U) #define ENET_QOS_MAC_CONFIGURATION_IPG_SHIFT (24U) /*! IPG - Inter-Packet Gap These bits control the minimum IPG between packets during transmission. @@ -30569,18 +37873,18 @@ typedef struct { * 0b000..96 bit times IPG */ #define ENET_QOS_MAC_CONFIGURATION_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_IPG_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_IPG_MASK) + #define ENET_QOS_MAC_CONFIGURATION_IPC_MASK (0x8000000U) #define ENET_QOS_MAC_CONFIGURATION_IPC_SHIFT (27U) -/*! IPC - Checksum Offload When set, this bit enables the IPv4 header checksum checking and IPv4 or - * IPv6 TCP, UDP, or ICMP payload checksum checking. +/*! IPC - Checksum Offload * 0b0..IP header/payload checksum checking is disabled * 0b1..IP header/payload checksum checking is enabled */ #define ENET_QOS_MAC_CONFIGURATION_IPC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_IPC_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_IPC_MASK) + #define ENET_QOS_MAC_CONFIGURATION_SARC_MASK (0x70000000U) #define ENET_QOS_MAC_CONFIGURATION_SARC_SHIFT (28U) -/*! SARC - Source Address Insertion or Replacement Control This field controls the source address - * insertion or replacement for all transmitted packets. +/*! SARC - Source Address Insertion or Replacement Control * 0b010..Contents of MAC Addr-0 inserted in SA field * 0b011..Contents of MAC Addr-0 replaces SA field * 0b110..Contents of MAC Addr-1 inserted in SA field @@ -30592,110 +37896,111 @@ typedef struct { /*! @name MAC_EXT_CONFIGURATION - MAC Extended Configuration Register */ /*! @{ */ + #define ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_MASK (0x3FFFU) #define ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_SHIFT (0U) -/*! GPSL - Giant Packet Size Limit If the received packet size is greater than the value programmed - * in this field in units of bytes, the MAC declares the received packet as Giant packet. +/*! GPSL - Giant Packet Size Limit */ #define ENET_QOS_MAC_EXT_CONFIGURATION_GPSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_MASK) + #define ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_MASK (0x10000U) #define ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_SHIFT (16U) -/*! DCRCC - Disable CRC Checking for Received Packets When this bit is set, the MAC receiver does - * not check the CRC field in the received packets. +/*! DCRCC - Disable CRC Checking for Received Packets * 0b1..CRC Checking is disabled * 0b0..CRC Checking is enabled */ #define ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_MASK) + #define ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_MASK (0x20000U) #define ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_SHIFT (17U) -/*! SPEN - Slow Protocol Detection Enable When this bit is set, MAC processes the Slow Protocol - * packets (Ether Type 0x8809) and provides the Rx status. +/*! SPEN - Slow Protocol Detection Enable * 0b0..Slow Protocol Detection is disabled * 0b1..Slow Protocol Detection is enabled */ #define ENET_QOS_MAC_EXT_CONFIGURATION_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_MASK) + #define ENET_QOS_MAC_EXT_CONFIGURATION_USP_MASK (0x40000U) #define ENET_QOS_MAC_EXT_CONFIGURATION_USP_SHIFT (18U) -/*! USP - Unicast Slow Protocol Packet Detect When this bit is set, the MAC detects the Slow - * Protocol packets with unicast address of the station specified in the MAC_ADDRESS0_HIGH and - * MAC_ADDRESS0_LOW registers. +/*! USP - Unicast Slow Protocol Packet Detect * 0b0..Unicast Slow Protocol Packet Detection is disabled * 0b1..Unicast Slow Protocol Packet Detection is enabled */ #define ENET_QOS_MAC_EXT_CONFIGURATION_USP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_USP_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_USP_MASK) + #define ENET_QOS_MAC_EXT_CONFIGURATION_PDC_MASK (0x80000U) #define ENET_QOS_MAC_EXT_CONFIGURATION_PDC_SHIFT (19U) -/*! PDC - Packet Duplication Control When this bit is set, the received packet with - * Multicast/Broadcast Destination address is routed to multiple Receive DMA Channels. +/*! PDC - Packet Duplication Control * 0b0..Packet Duplication Control is disabled * 0b1..Packet Duplication Control is enabled */ #define ENET_QOS_MAC_EXT_CONFIGURATION_PDC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_PDC_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_PDC_MASK) + #define ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_MASK (0x1000000U) #define ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT (24U) -/*! EIPGEN - Extended Inter-Packet Gap Enable When this bit is set, the MAC interprets EIPG field - * and IPG field in CONFIGURATION register together as minimum IPG greater than 96 bit times in - * steps of 8 bit times. +/*! EIPGEN - Extended Inter-Packet Gap Enable * 0b0..Extended Inter-Packet Gap is disabled * 0b1..Extended Inter-Packet Gap is enabled */ #define ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_MASK) + #define ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_MASK (0x3E000000U) #define ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_SHIFT (25U) -/*! EIPG - Extended Inter-Packet Gap The value in this field is applicable when the EIPGEN bit is set. +/*! EIPG - Extended Inter-Packet Gap */ #define ENET_QOS_MAC_EXT_CONFIGURATION_EIPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_MASK) /*! @} */ -/*! @name MAC_PACKET_FILTER - MAC_Packet_Filter */ +/*! @name MAC_PACKET_FILTER - MAC Packet Filter */ /*! @{ */ + #define ENET_QOS_MAC_PACKET_FILTER_PR_MASK (0x1U) #define ENET_QOS_MAC_PACKET_FILTER_PR_SHIFT (0U) -/*! PR - Promiscuous Mode When this bit is set, the Address Filtering module passes all incoming - * packets irrespective of the destination or source address. +/*! PR - Promiscuous Mode * 0b0..Promiscuous Mode is disabled * 0b1..Promiscuous Mode is enabled */ #define ENET_QOS_MAC_PACKET_FILTER_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_PR_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_PR_MASK) + #define ENET_QOS_MAC_PACKET_FILTER_HUC_MASK (0x2U) #define ENET_QOS_MAC_PACKET_FILTER_HUC_SHIFT (1U) -/*! HUC - Hash Unicast When this bit is set, the MAC performs the destination address filtering of - * unicast packets according to the hash table. +/*! HUC - Hash Unicast * 0b0..Hash Unicast is disabled * 0b1..Hash Unicast is enabled */ #define ENET_QOS_MAC_PACKET_FILTER_HUC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_HUC_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_HUC_MASK) + #define ENET_QOS_MAC_PACKET_FILTER_HMC_MASK (0x4U) #define ENET_QOS_MAC_PACKET_FILTER_HMC_SHIFT (2U) -/*! HMC - Hash Multicast When this bit is set, the MAC performs the destination address filtering of - * received multicast packets according to the hash table. +/*! HMC - Hash Multicast * 0b0..Hash Multicast is disabled * 0b1..Hash Multicast is enabled */ #define ENET_QOS_MAC_PACKET_FILTER_HMC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_HMC_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_HMC_MASK) + #define ENET_QOS_MAC_PACKET_FILTER_DAIF_MASK (0x8U) #define ENET_QOS_MAC_PACKET_FILTER_DAIF_SHIFT (3U) -/*! DAIF - DA Inverse Filtering When this bit is set, the Address Check block operates in inverse - * filtering mode for the DA address comparison for both unicast and multicast packets. +/*! DAIF - DA Inverse Filtering * 0b0..DA Inverse Filtering is disabled * 0b1..DA Inverse Filtering is enabled */ #define ENET_QOS_MAC_PACKET_FILTER_DAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_DAIF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_DAIF_MASK) + #define ENET_QOS_MAC_PACKET_FILTER_PM_MASK (0x10U) #define ENET_QOS_MAC_PACKET_FILTER_PM_SHIFT (4U) -/*! PM - Pass All Multicast When this bit is set, it indicates that all received packets with a - * multicast destination address (first bit in the destination address field is '1') are passed. +/*! PM - Pass All Multicast * 0b0..Pass All Multicast is disabled * 0b1..Pass All Multicast is enabled */ #define ENET_QOS_MAC_PACKET_FILTER_PM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_PM_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_PM_MASK) + #define ENET_QOS_MAC_PACKET_FILTER_DBF_MASK (0x20U) #define ENET_QOS_MAC_PACKET_FILTER_DBF_SHIFT (5U) -/*! DBF - Disable Broadcast Packets When this bit is set, the AFM module blocks all incoming broadcast packets. +/*! DBF - Disable Broadcast Packets * 0b1..Disable Broadcast Packets * 0b0..Enable Broadcast Packets */ #define ENET_QOS_MAC_PACKET_FILTER_DBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_DBF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_DBF_MASK) + #define ENET_QOS_MAC_PACKET_FILTER_PCF_MASK (0xC0U) #define ENET_QOS_MAC_PACKET_FILTER_PCF_SHIFT (6U) /*! PCF - Pass Control Packets These bits control the forwarding of all control packets (including @@ -30706,56 +38011,58 @@ typedef struct { * 0b01..MAC forwards all control packets except Pause packets to the application even if they fail the Address filter */ #define ENET_QOS_MAC_PACKET_FILTER_PCF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_PCF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_PCF_MASK) + #define ENET_QOS_MAC_PACKET_FILTER_SAIF_MASK (0x100U) #define ENET_QOS_MAC_PACKET_FILTER_SAIF_SHIFT (8U) -/*! SAIF - SA Inverse Filtering When this bit is set, the Address Check block operates in the - * inverse filtering mode for SA address comparison. +/*! SAIF - SA Inverse Filtering * 0b0..SA Inverse Filtering is disabled * 0b1..SA Inverse Filtering is enabled */ #define ENET_QOS_MAC_PACKET_FILTER_SAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_SAIF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_SAIF_MASK) + #define ENET_QOS_MAC_PACKET_FILTER_SAF_MASK (0x200U) #define ENET_QOS_MAC_PACKET_FILTER_SAF_SHIFT (9U) -/*! SAF - Source Address Filter Enable When this bit is set, the MAC compares the SA field of the - * received packets with the values programmed in the enabled SA registers. +/*! SAF - Source Address Filter Enable * 0b0..SA Filtering is disabled * 0b1..SA Filtering is enabled */ #define ENET_QOS_MAC_PACKET_FILTER_SAF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_SAF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_SAF_MASK) + #define ENET_QOS_MAC_PACKET_FILTER_HPF_MASK (0x400U) #define ENET_QOS_MAC_PACKET_FILTER_HPF_SHIFT (10U) -/*! HPF - Hash or Perfect Filter When this bit is set, the address filter passes a packet if it - * matches either the perfect filtering or hash filtering as set by the HMC or HUC bit. +/*! HPF - Hash or Perfect Filter * 0b0..Hash or Perfect Filter is disabled * 0b1..Hash or Perfect Filter is enabled */ #define ENET_QOS_MAC_PACKET_FILTER_HPF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_HPF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_HPF_MASK) + #define ENET_QOS_MAC_PACKET_FILTER_VTFE_MASK (0x10000U) #define ENET_QOS_MAC_PACKET_FILTER_VTFE_SHIFT (16U) -/*! VTFE - VLAN Tag Filter Enable When this bit is set, the MAC drops the VLAN tagged packets that do not match the VLAN Tag. +/*! VTFE - VLAN Tag Filter Enable * 0b0..VLAN Tag Filter is disabled * 0b1..VLAN Tag Filter is enabled */ #define ENET_QOS_MAC_PACKET_FILTER_VTFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_VTFE_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_VTFE_MASK) + #define ENET_QOS_MAC_PACKET_FILTER_IPFE_MASK (0x100000U) #define ENET_QOS_MAC_PACKET_FILTER_IPFE_SHIFT (20U) -/*! IPFE - Layer 3 and Layer 4 Filter Enable When this bit is set, the MAC drops packets that do not - * match the enabled Layer 3 and Layer 4 filters. +/*! IPFE - Layer 3 and Layer 4 Filter Enable * 0b0..Layer 3 and Layer 4 Filters are disabled * 0b1..Layer 3 and Layer 4 Filters are enabled */ #define ENET_QOS_MAC_PACKET_FILTER_IPFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_IPFE_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_IPFE_MASK) + #define ENET_QOS_MAC_PACKET_FILTER_DNTU_MASK (0x200000U) #define ENET_QOS_MAC_PACKET_FILTER_DNTU_SHIFT (21U) -/*! DNTU - Drop Non-TCP/UDP over IP Packets When this bit is set, the MAC drops the non-TCP or UDP over IP packets. +/*! DNTU - Drop Non-TCP/UDP over IP Packets * 0b1..Drop Non-TCP/UDP over IP Packets * 0b0..Forward Non-TCP/UDP over IP Packets */ #define ENET_QOS_MAC_PACKET_FILTER_DNTU(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_DNTU_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_DNTU_MASK) + #define ENET_QOS_MAC_PACKET_FILTER_RA_MASK (0x80000000U) #define ENET_QOS_MAC_PACKET_FILTER_RA_SHIFT (31U) -/*! RA - Receive All When this bit is set, the MAC Receiver module passes all received packets to - * the application, irrespective of whether they pass the address filter or not. +/*! RA - Receive All * 0b0..Receive All is disabled * 0b1..Receive All is enabled */ @@ -30764,10 +38071,10 @@ typedef struct { /*! @name MAC_WATCHDOG_TIMEOUT - Watchdog Timeout */ /*! @{ */ + #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_MASK (0xFU) #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT (0U) -/*! WTO - Watchdog Timeout When the PWE bit is set and the WD bit of the MAC_CONFIGURATION register - * is reset, this field is used as watchdog timeout for a received packet. +/*! WTO - Watchdog Timeout * 0b1000..10 KB * 0b1001..11 KB * 0b1010..12 KB @@ -30786,10 +38093,10 @@ typedef struct { * 0b1111..Reserved */ #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT)) & ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_MASK) + #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_MASK (0x100U) #define ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT (8U) -/*! PWE - Programmable Watchdog Enable When this bit is set and the WD bit of the MAC_CONFIGURATION - * register is reset, the WTO field is used as watchdog timeout for a received packet. +/*! PWE - Programmable Watchdog Enable * 0b0..Programmable Watchdog is disabled * 0b1..Programmable Watchdog is enabled */ @@ -30798,6 +38105,7 @@ typedef struct { /*! @name MAC_HASH_TABLE_REG0 - MAC Hash Table Register 0 */ /*! @{ */ + #define ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_SHIFT (0U) /*! HT31T0 - MAC Hash Table First 32 Bits This field contains the first 32 Bits [31:0] of the Hash table. @@ -30807,6 +38115,7 @@ typedef struct { /*! @name MAC_HASH_TABLE_REG1 - MAC Hash Table Register 1 */ /*! @{ */ + #define ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_SHIFT (0U) /*! HT63T32 - MAC Hash Table Second 32 Bits This field contains the second 32 Bits [63:32] of the Hash table. @@ -30816,34 +38125,37 @@ typedef struct { /*! @name MAC_VLAN_TAG_CTRL - MAC VLAN Tag Control */ /*! @{ */ + #define ENET_QOS_MAC_VLAN_TAG_CTRL_OB_MASK (0x1U) #define ENET_QOS_MAC_VLAN_TAG_CTRL_OB_SHIFT (0U) -/*! OB - Operation Busy This bit is set along with a read or write command for initiating the - * indirect access to per VLAN Tag Filter register. +/*! OB - Operation Busy * 0b0..Operation Busy is disabled * 0b1..Operation Busy is enabled */ #define ENET_QOS_MAC_VLAN_TAG_CTRL_OB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_OB_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_OB_MASK) + #define ENET_QOS_MAC_VLAN_TAG_CTRL_CT_MASK (0x2U) #define ENET_QOS_MAC_VLAN_TAG_CTRL_CT_SHIFT (1U) -/*! CT - Command Type This bit indicates if the current register access is a read or a write. +/*! CT - Command Type * 0b1..Read operation * 0b0..Write operation */ #define ENET_QOS_MAC_VLAN_TAG_CTRL_CT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_CT_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_CT_MASK) + #define ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_MASK (0x7CU) #define ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_SHIFT (2U) -/*! OFS - Offset This field holds the address offset of the MAC VLAN Tag Filter Register which the - * application is trying to access. +/*! OFS - Offset */ #define ENET_QOS_MAC_VLAN_TAG_CTRL_OFS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_MASK) + #define ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_MASK (0x20000U) #define ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_SHIFT (17U) -/*! VTIM - VLAN Tag Inverse Match Enable When this bit is set, this bit enables the VLAN Tag inverse matching. +/*! VTIM - VLAN Tag Inverse Match Enable * 0b0..VLAN Tag Inverse Match is disabled * 0b1..VLAN Tag Inverse Match is enabled */ #define ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_MASK) + #define ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_MASK (0x40000U) #define ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_SHIFT (18U) /*! ESVL - Enable S-VLAN When this bit is set, the MAC transmitter and receiver consider the S-VLAN @@ -30852,6 +38164,7 @@ typedef struct { * 0b1..S-VLAN is enabled */ #define ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_MASK) + #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_MASK (0x600000U) #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_SHIFT (21U) /*! EVLS - Enable VLAN Tag Stripping on Receive This field indicates the stripping operation on the @@ -30862,30 +38175,31 @@ typedef struct { * 0b01..Strip if VLAN filter passes */ #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_MASK) + #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_MASK (0x1000000U) #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_SHIFT (24U) -/*! EVLRXS - Enable VLAN Tag in Rx status When this bit is set, MAC provides the outer VLAN Tag in the Rx status. +/*! EVLRXS - Enable VLAN Tag in Rx status * 0b0..VLAN Tag in Rx status is disabled * 0b1..VLAN Tag in Rx status is enabled */ #define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_MASK) + #define ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_MASK (0x2000000U) #define ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_SHIFT (25U) -/*! VTHM - VLAN Tag Hash Table Match Enable When this bit is set, the most significant four bits of - * CRC of VLAN Tag (ones-complement of most significant four bits of CRC of VLAN Tag when ETV bit - * is reset) are used to index the content of the MAC_VLAN_Hash_Table register. +/*! VTHM - VLAN Tag Hash Table Match Enable * 0b0..VLAN Tag Hash Table Match is disabled * 0b1..VLAN Tag Hash Table Match is enabled */ #define ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_MASK) + #define ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_MASK (0x4000000U) #define ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_SHIFT (26U) -/*! EDVLP - Enable Double VLAN Processing When this bit is set, the MAC enables processing of up to - * two VLAN Tags on Tx and Rx (if present). +/*! EDVLP - Enable Double VLAN Processing * 0b0..Double VLAN Processing is disabled * 0b1..Double VLAN Processing is enabled */ #define ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_MASK) + #define ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_MASK (0x8000000U) #define ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_SHIFT (27U) /*! ERIVLT - ERIVLT @@ -30893,6 +38207,7 @@ typedef struct { * 0b1..Inner VLAN tag is enabled */ #define ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_MASK) + #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_MASK (0x30000000U) #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT (28U) /*! EIVLS - Enable Inner VLAN Tag Stripping on Receive This field indicates the stripping operation @@ -30903,9 +38218,10 @@ typedef struct { * 0b01..Strip if VLAN filter passes */ #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_MASK) + #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_MASK (0x80000000U) #define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_SHIFT (31U) -/*! EIVLRXS - Enable Inner VLAN Tag in Rx Status When this bit is set, the MAC provides the inner VLAN Tag in the Rx status. +/*! EIVLRXS - Enable Inner VLAN Tag in Rx Status * 0b0..Inner VLAN Tag in Rx status is disabled * 0b1..Inner VLAN Tag in Rx status is enabled */ @@ -30914,63 +38230,71 @@ typedef struct { /*! @name MAC_VLAN_TAG_DATA - MAC VLAN Tag Data */ /*! @{ */ + #define ENET_QOS_MAC_VLAN_TAG_DATA_VID_MASK (0xFFFFU) #define ENET_QOS_MAC_VLAN_TAG_DATA_VID_SHIFT (0U) -/*! VID - VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison. +/*! VID - VLAN Tag ID */ #define ENET_QOS_MAC_VLAN_TAG_DATA_VID(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_VID_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_VID_MASK) + #define ENET_QOS_MAC_VLAN_TAG_DATA_VEN_MASK (0x10000U) #define ENET_QOS_MAC_VLAN_TAG_DATA_VEN_SHIFT (16U) -/*! VEN - VLAN Tag Enable This bit is used to enable or disable the VLAN Tag. +/*! VEN - VLAN Tag Enable * 0b0..VLAN Tag is disabled * 0b1..VLAN Tag is enabled */ #define ENET_QOS_MAC_VLAN_TAG_DATA_VEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_VEN_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_VEN_MASK) + #define ENET_QOS_MAC_VLAN_TAG_DATA_ETV_MASK (0x20000U) #define ENET_QOS_MAC_VLAN_TAG_DATA_ETV_SHIFT (17U) -/*! ETV - 12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set. +/*! ETV - 12bits or 16bits VLAN comparison * 0b1..12 bit VLAN comparison * 0b0..16 bit VLAN comparison */ #define ENET_QOS_MAC_VLAN_TAG_DATA_ETV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_ETV_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_ETV_MASK) + #define ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_MASK (0x40000U) #define ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_SHIFT (18U) -/*! DOVLTC - Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set. +/*! DOVLTC - Disable VLAN Type Comparison * 0b1..VLAN type comparison is disabled * 0b0..VLAN type comparison is enabled */ #define ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_MASK) + #define ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_MASK (0x80000U) #define ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_SHIFT (19U) -/*! ERSVLM - Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set. +/*! ERSVLM - Enable S-VLAN Match for received Frames * 0b0..Receive S-VLAN Match is disabled * 0b1..Receive S-VLAN Match is enabled */ #define ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_MASK) + #define ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_MASK (0x100000U) #define ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_SHIFT (20U) -/*! ERIVLT - Enable Inner VLAN Tag Comparison This bit is valid only when VLAN Tag Enable of the Filter is set. +/*! ERIVLT - Enable Inner VLAN Tag Comparison * 0b0..Inner VLAN tag comparison is disabled * 0b1..Inner VLAN tag comparison is enabled */ #define ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_MASK) + #define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_MASK (0x1000000U) #define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_SHIFT (24U) -/*! DMACHEN - DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH. +/*! DMACHEN - DMA Channel Number Enable * 0b0..DMA Channel Number is disabled * 0b1..DMA Channel Number is enabled */ #define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_MASK) + #define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_MASK (0xE000000U) #define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_SHIFT (25U) -/*! DMACHN - DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be - * routed if it passes this VLAN Tag Filter is programmed in this field. +/*! DMACHN - DMA Channel Number */ #define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_MASK) /*! @} */ /*! @name MAC_VLAN_HASH_TABLE - MAC VLAN Hash Table */ /*! @{ */ + #define ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_MASK (0xFFFFU) #define ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_SHIFT (0U) /*! VLHT - VLAN Hash Table This field contains the 16-bit VLAN Hash Table. @@ -30980,11 +38304,13 @@ typedef struct { /*! @name MAC_VLAN_INCL - VLAN Tag Inclusion or Replacement */ /*! @{ */ + #define ENET_QOS_MAC_VLAN_INCL_VLT_MASK (0xFFFFU) #define ENET_QOS_MAC_VLAN_INCL_VLT_SHIFT (0U) -/*! VLT - VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted or replaced. +/*! VLT - VLAN Tag for Transmit Packets */ #define ENET_QOS_MAC_VLAN_INCL_VLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLT_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLT_MASK) + #define ENET_QOS_MAC_VLAN_INCL_VLC_MASK (0x30000U) #define ENET_QOS_MAC_VLAN_INCL_VLC_SHIFT (16U) /*! VLC - VLAN Tag Control in Transmit Packets - 2'b00: No VLAN tag deletion, insertion, or @@ -30996,22 +38322,23 @@ typedef struct { * 0b11..VLAN tag replacement */ #define ENET_QOS_MAC_VLAN_INCL_VLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLC_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLC_MASK) + #define ENET_QOS_MAC_VLAN_INCL_VLP_MASK (0x40000U) #define ENET_QOS_MAC_VLAN_INCL_VLP_SHIFT (18U) -/*! VLP - VLAN Priority Control When this bit is set, the control bits[17:16] are used for VLAN - * deletion, insertion, or replacement. +/*! VLP - VLAN Priority Control * 0b0..VLAN Priority Control is disabled * 0b1..VLAN Priority Control is enabled */ #define ENET_QOS_MAC_VLAN_INCL_VLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLP_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLP_MASK) + #define ENET_QOS_MAC_VLAN_INCL_CSVL_MASK (0x80000U) #define ENET_QOS_MAC_VLAN_INCL_CSVL_SHIFT (19U) -/*! CSVL - C-VLAN or S-VLAN When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in - * the 13th and 14th bytes of transmitted packets. +/*! CSVL - C-VLAN or S-VLAN * 0b0..C-VLAN type (0x8100) is inserted or replaced * 0b1..S-VLAN type (0x88A8) is inserted or replaced */ #define ENET_QOS_MAC_VLAN_INCL_CSVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_CSVL_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_CSVL_MASK) + #define ENET_QOS_MAC_VLAN_INCL_VLTI_MASK (0x100000U) #define ENET_QOS_MAC_VLAN_INCL_VLTI_SHIFT (20U) /*! VLTI - VLAN Tag Input When this bit is set, it indicates that the VLAN tag to be inserted or @@ -31020,30 +38347,32 @@ typedef struct { * 0b1..VLAN Tag Input is enabled */ #define ENET_QOS_MAC_VLAN_INCL_VLTI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLTI_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLTI_MASK) + #define ENET_QOS_MAC_VLAN_INCL_CBTI_MASK (0x200000U) #define ENET_QOS_MAC_VLAN_INCL_CBTI_SHIFT (21U) -/*! CBTI - Channel based tag insertion When this bit is set, outer VLAN tag is inserted for every packets transmitted by the MAC. +/*! CBTI - Channel based tag insertion * 0b0..Channel based tag insertion is disabled * 0b1..Channel based tag insertion is enabled */ #define ENET_QOS_MAC_VLAN_INCL_CBTI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_CBTI_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_CBTI_MASK) + #define ENET_QOS_MAC_VLAN_INCL_ADDR_MASK (0x7000000U) #define ENET_QOS_MAC_VLAN_INCL_ADDR_SHIFT (24U) -/*! ADDR - Address This field selects one of the queue/channel specific VLAN Inclusion register for read/write access. +/*! ADDR - Address */ #define ENET_QOS_MAC_VLAN_INCL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_ADDR_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_ADDR_MASK) + #define ENET_QOS_MAC_VLAN_INCL_RDWR_MASK (0x40000000U) #define ENET_QOS_MAC_VLAN_INCL_RDWR_SHIFT (30U) -/*! RDWR - Read write control This bit controls the read or write operation for indirectly accessing - * the queue/channel specific VLAN Inclusion register. +/*! RDWR - Read write control * 0b0..Read operation of indirect access * 0b1..Write operation of indirect access */ #define ENET_QOS_MAC_VLAN_INCL_RDWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_RDWR_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_RDWR_MASK) + #define ENET_QOS_MAC_VLAN_INCL_BUSY_MASK (0x80000000U) #define ENET_QOS_MAC_VLAN_INCL_BUSY_SHIFT (31U) -/*! BUSY - Busy This bit indicates the status of the read/write operation of indirect access to the - * queue/channel specific VLAN inclusion register. +/*! BUSY - Busy * 0b1..Busy status detected * 0b0..Busy status not detected */ @@ -31052,37 +38381,39 @@ typedef struct { /*! @name MAC_INNER_VLAN_INCL - MAC Inner VLAN Tag Inclusion or Replacement */ /*! @{ */ + #define ENET_QOS_MAC_INNER_VLAN_INCL_VLT_MASK (0xFFFFU) #define ENET_QOS_MAC_INNER_VLAN_INCL_VLT_SHIFT (0U) -/*! VLT - VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted or replaced. +/*! VLT - VLAN Tag for Transmit Packets */ #define ENET_QOS_MAC_INNER_VLAN_INCL_VLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLT_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLT_MASK) + #define ENET_QOS_MAC_INNER_VLAN_INCL_VLC_MASK (0x30000U) #define ENET_QOS_MAC_INNER_VLAN_INCL_VLC_SHIFT (16U) -/*! VLC - VLAN Tag Control in Transmit Packets - 2'b00: No VLAN tag deletion, insertion, or - * replacement - 2'b01: VLAN tag deletion The MAC removes the VLAN type (bytes 17 and 18) and VLAN tag - * (bytes 19 and 20) of all transmitted packets with VLAN tags. +/*! VLC - VLAN Tag Control in Transmit Packets * 0b01..VLAN tag deletion * 0b10..VLAN tag insertion * 0b00..No VLAN tag deletion, insertion, or replacement * 0b11..VLAN tag replacement */ #define ENET_QOS_MAC_INNER_VLAN_INCL_VLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLC_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLC_MASK) + #define ENET_QOS_MAC_INNER_VLAN_INCL_VLP_MASK (0x40000U) #define ENET_QOS_MAC_INNER_VLAN_INCL_VLP_SHIFT (18U) -/*! VLP - VLAN Priority Control When this bit is set, the VLC field is used for VLAN deletion, insertion, or replacement. +/*! VLP - VLAN Priority Control * 0b0..VLAN Priority Control is disabled * 0b1..VLAN Priority Control is enabled */ #define ENET_QOS_MAC_INNER_VLAN_INCL_VLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLP_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLP_MASK) + #define ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_MASK (0x80000U) #define ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_SHIFT (19U) -/*! CSVL - C-VLAN or S-VLAN When this bit is set, S-VLAN type (0x88A8) is inserted or replaced in - * the 13th and 14th bytes of transmitted packets. +/*! CSVL - C-VLAN or S-VLAN * 0b0..C-VLAN type (0x8100) is inserted * 0b1..S-VLAN type (0x88A8) is inserted */ #define ENET_QOS_MAC_INNER_VLAN_INCL_CSVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_MASK) + #define ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_MASK (0x100000U) #define ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_SHIFT (20U) /*! VLTI - VLAN Tag Input When this bit is set, it indicates that the VLAN tag to be inserted or @@ -31093,30 +38424,28 @@ typedef struct { #define ENET_QOS_MAC_INNER_VLAN_INCL_VLTI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_MASK) /*! @} */ -/*! @name MAC_TX_FLOW_CTRL_Q - MAC Q0 Tx Flow Control */ +/*! @name MAC_TX_FLOW_CTRL_Q - MAC Q0 Tx Flow Control..MAC Q4 Tx Flow Control */ /*! @{ */ + #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_MASK (0x1U) #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_SHIFT (0U) -/*! FCB_BPA - Flow Control Busy or Backpressure Activate This bit initiates a Pause packet in the - * full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit - * is set. +/*! FCB_BPA - Flow Control Busy or Backpressure Activate * 0b0..Flow Control Busy or Backpressure Activate is disabled * 0b1..Flow Control Busy or Backpressure Activate is enabled */ #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_MASK) + #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_MASK (0x2U) #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT (1U) -/*! TFE - Transmit Flow Control Enable Full-Duplex Mode: In the full-duplex mode, when this bit is - * set, the MAC enables the flow control operation to Tx Pause packets. +/*! TFE - Transmit Flow Control Enable * 0b0..Transmit Flow Control is disabled * 0b1..Transmit Flow Control is enabled */ #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_MASK) + #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_MASK (0x70U) #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT (4U) -/*! PLT - Pause Low Threshold This field configures the threshold of the Pause timer at which the - * input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic - * retransmission of the Pause packet. +/*! PLT - Pause Low Threshold * 0b011..Pause Time minus 144 Slot Times (PT -144 slot times) * 0b100..Pause Time minus 256 Slot Times (PT -256 slot times) * 0b001..Pause Time minus 28 Slot Times (PT -28 slot times) @@ -31126,18 +38455,18 @@ typedef struct { * 0b110..Reserved */ #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_MASK) + #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK (0x80U) #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT (7U) -/*! DZPQ - Disable Zero-Quanta Pause When this bit is set, it disables the automatic generation of - * the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer - * (MTL or external sideband flow control signal sbd_flowctrl_i or mti_flowctrl_i). +/*! DZPQ - Disable Zero-Quanta Pause * 0b1..Zero-Quanta Pause packet generation is disabled * 0b0..Zero-Quanta Pause packet generation is enabled */ #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK) + #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_MASK (0xFFFF0000U) #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_SHIFT (16U) -/*! PT - Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet. +/*! PT - Pause Time */ #define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_MASK) /*! @} */ @@ -31147,27 +38476,26 @@ typedef struct { /*! @name MAC_RX_FLOW_CTRL - MAC Rx Flow Control */ /*! @{ */ + #define ENET_QOS_MAC_RX_FLOW_CTRL_RFE_MASK (0x1U) #define ENET_QOS_MAC_RX_FLOW_CTRL_RFE_SHIFT (0U) -/*! RFE - Receive Flow Control Enable When this bit is set and the MAC is operating in full-duplex - * mode, the MAC decodes the received Pause packet and disables its transmitter for a specified - * (Pause) time. +/*! RFE - Receive Flow Control Enable * 0b0..Receive Flow Control is disabled * 0b1..Receive Flow Control is enabled */ #define ENET_QOS_MAC_RX_FLOW_CTRL_RFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FLOW_CTRL_RFE_SHIFT)) & ENET_QOS_MAC_RX_FLOW_CTRL_RFE_MASK) + #define ENET_QOS_MAC_RX_FLOW_CTRL_UP_MASK (0x2U) #define ENET_QOS_MAC_RX_FLOW_CTRL_UP_SHIFT (1U) -/*! UP - Unicast Pause Packet Detect A pause packet is processed when it has the unique multicast - * address specified in the IEEE 802. +/*! UP - Unicast Pause Packet Detect * 0b0..Unicast Pause Packet Detect disabled * 0b1..Unicast Pause Packet Detect enabled */ #define ENET_QOS_MAC_RX_FLOW_CTRL_UP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FLOW_CTRL_UP_SHIFT)) & ENET_QOS_MAC_RX_FLOW_CTRL_UP_MASK) + #define ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_MASK (0x100U) #define ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_SHIFT (8U) -/*! PFCE - Priority Based Flow Control Enable When this bit is set, it enables generation and - * reception of priority-based flow control (PFC) packets. +/*! PFCE - Priority Based Flow Control Enable * 0b0..Priority Based Flow Control is disabled * 0b1..Priority Based Flow Control is enabled */ @@ -31176,6 +38504,7 @@ typedef struct { /*! @name MAC_RXQ_CTRL4 - Receive Queue Control 4 */ /*! @{ */ + #define ENET_QOS_MAC_RXQ_CTRL4_UFFQE_MASK (0x1U) #define ENET_QOS_MAC_RXQ_CTRL4_UFFQE_SHIFT (0U) /*! UFFQE - Unicast Address Filter Fail Packets Queuing Enable. @@ -31183,11 +38512,13 @@ typedef struct { * 0b1..Unicast Address Filter Fail Packets Queuing is enabled */ #define ENET_QOS_MAC_RXQ_CTRL4_UFFQE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_UFFQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_UFFQE_MASK) + #define ENET_QOS_MAC_RXQ_CTRL4_UFFQ_MASK (0xEU) #define ENET_QOS_MAC_RXQ_CTRL4_UFFQ_SHIFT (1U) /*! UFFQ - Unicast Address Filter Fail Packets Queue. */ #define ENET_QOS_MAC_RXQ_CTRL4_UFFQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_UFFQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_UFFQ_MASK) + #define ENET_QOS_MAC_RXQ_CTRL4_MFFQE_MASK (0x100U) #define ENET_QOS_MAC_RXQ_CTRL4_MFFQE_SHIFT (8U) /*! MFFQE - Multicast Address Filter Fail Packets Queuing Enable. @@ -31195,46 +38526,49 @@ typedef struct { * 0b1..Multicast Address Filter Fail Packets Queuing is enabled */ #define ENET_QOS_MAC_RXQ_CTRL4_MFFQE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_MFFQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_MFFQE_MASK) + #define ENET_QOS_MAC_RXQ_CTRL4_MFFQ_MASK (0xE00U) #define ENET_QOS_MAC_RXQ_CTRL4_MFFQ_SHIFT (9U) /*! MFFQ - Multicast Address Filter Fail Packets Queue. */ #define ENET_QOS_MAC_RXQ_CTRL4_MFFQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_MFFQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_MFFQ_MASK) + #define ENET_QOS_MAC_RXQ_CTRL4_VFFQE_MASK (0x10000U) #define ENET_QOS_MAC_RXQ_CTRL4_VFFQE_SHIFT (16U) -/*! VFFQE - VLAN Tag Filter Fail Packets Queuing Enable When this bit is set, the tagged packets - * which fail the Destination or Source address filter or fail the VLAN tag filter, are routed to - * the Rx Queue Number programmed in the VFFQ. +/*! VFFQE - VLAN Tag Filter Fail Packets Queuing Enable * 0b0..VLAN tag Filter Fail Packets Queuing is disabled * 0b1..VLAN tag Filter Fail Packets Queuing is enabled */ #define ENET_QOS_MAC_RXQ_CTRL4_VFFQE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_VFFQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_VFFQE_MASK) + #define ENET_QOS_MAC_RXQ_CTRL4_VFFQ_MASK (0xE0000U) #define ENET_QOS_MAC_RXQ_CTRL4_VFFQ_SHIFT (17U) -/*! VFFQ - VLAN Tag Filter Fail Packets Queue This field holds the Rx queue number to which the - * tagged packets failing the Destination or Source Address filter (and UFFQE/MFFQE not enabled) or - * failing the VLAN tag filter must be routed to. +/*! VFFQ - VLAN Tag Filter Fail Packets Queue */ #define ENET_QOS_MAC_RXQ_CTRL4_VFFQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_VFFQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_VFFQ_MASK) /*! @} */ /*! @name MAC_TXQ_PRTY_MAP0 - Transmit Queue Priority Mapping 0 */ /*! @{ */ + #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK (0xFFU) #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT (0U) -/*! PSTQ0 - Priorities Selected in Transmit Queue 0 This field holds the priorities assigned to Tx Queue 0 by the software. +/*! PSTQ0 - Priorities Selected in Transmit Queue 0 */ #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK) + #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_MASK (0xFF00U) #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_SHIFT (8U) /*! PSTQ1 - Priorities Selected in Transmit Queue 1 This bit is similar to the PSTQ0 bit. */ #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_MASK) + #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_MASK (0xFF0000U) #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_SHIFT (16U) /*! PSTQ2 - Priorities Selected in Transmit Queue 2 This bit is similar to the PSTQ0 bit. */ #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_MASK) + #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_MASK (0xFF000000U) #define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_SHIFT (24U) /*! PSTQ3 - Priorities Selected in Transmit Queue 3 This bit is similar to the PSTQ0 bit. @@ -31244,39 +38578,43 @@ typedef struct { /*! @name MAC_TXQ_PRTY_MAP1 - Transmit Queue Priority Mapping 1 */ /*! @{ */ + #define ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_MASK (0xFFU) #define ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_SHIFT (0U) -/*! PSTQ4 - Priorities Selected in Transmit Queue 4 This field holds the priorities assigned to Tx Queue 4 by the software. +/*! PSTQ4 - Priorities Selected in Transmit Queue 4 */ #define ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_MASK) /*! @} */ /*! @name MAC_RXQ_CTRL - Receive Queue Control 0..Receive Queue Control 3 */ /*! @{ */ + #define ENET_QOS_MAC_RXQ_CTRL_AVCPQ_MASK (0x7U) #define ENET_QOS_MAC_RXQ_CTRL_AVCPQ_SHIFT (0U) -/*! AVCPQ - AV Untagged Control Packets Queue This field specifies the Receive queue on which the - * received AV tagged and untagged control packets are routed. +/*! AVCPQ - AV Untagged Control Packets Queue * 0b000..Receive Queue 0 * 0b001..Receive Queue 1 * 0b010..Receive Queue 2 * 0b011..Receive Queue 3 * 0b100..Receive Queue 4 - * 0b101..Receive Queue 5 - * 0b110..Receive Queue 6 - * 0b111..Receive Queue 7 + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved */ #define ENET_QOS_MAC_RXQ_CTRL_AVCPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_AVCPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_AVCPQ_MASK) + #define ENET_QOS_MAC_RXQ_CTRL_PSRQ0_MASK (0xFFU) #define ENET_QOS_MAC_RXQ_CTRL_PSRQ0_SHIFT (0U) -/*! PSRQ0 - Priorities Selected in the Receive Queue 0 This field decides the priorities assigned to Rx Queue 0. +/*! PSRQ0 - Priorities Selected in the Receive Queue 0 */ #define ENET_QOS_MAC_RXQ_CTRL_PSRQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ0_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ0_MASK) + #define ENET_QOS_MAC_RXQ_CTRL_PSRQ4_MASK (0xFFU) #define ENET_QOS_MAC_RXQ_CTRL_PSRQ4_SHIFT (0U) -/*! PSRQ4 - Priorities Selected in the Receive Queue 4 This field decides the priorities assigned to Rx Queue 4. +/*! PSRQ4 - Priorities Selected in the Receive Queue 4 */ #define ENET_QOS_MAC_RXQ_CTRL_PSRQ4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ4_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ4_MASK) + #define ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_MASK (0x3U) #define ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_SHIFT (0U) /*! RXQ0EN - Receive Queue 0 Enable This field indicates whether Rx Queue 0 is enabled for AV or DCB. @@ -31286,6 +38624,7 @@ typedef struct { * 0b11..Reserved */ #define ENET_QOS_MAC_RXQ_CTRL_RXQ0EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_MASK) + #define ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_MASK (0xCU) #define ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_SHIFT (2U) /*! RXQ1EN - Receive Queue 1 Enable This field is similar to the RXQ0EN field. @@ -31295,20 +38634,21 @@ typedef struct { * 0b11..Reserved */ #define ENET_QOS_MAC_RXQ_CTRL_RXQ1EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_MASK) + #define ENET_QOS_MAC_RXQ_CTRL_PTPQ_MASK (0x70U) #define ENET_QOS_MAC_RXQ_CTRL_PTPQ_SHIFT (4U) -/*! PTPQ - PTP Packets Queue This field specifies the Rx queue on which the PTP packets sent over - * the Ethernet payload (not over IPv4 or IPv6) are routed. +/*! PTPQ - PTP Packets Queue * 0b000..Receive Queue 0 * 0b001..Receive Queue 1 * 0b010..Receive Queue 2 * 0b011..Receive Queue 3 * 0b100..Receive Queue 4 - * 0b101..Receive Queue 5 - * 0b110..Receive Queue 6 - * 0b111..Receive Queue 7 + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved */ #define ENET_QOS_MAC_RXQ_CTRL_PTPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PTPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PTPQ_MASK) + #define ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_MASK (0x30U) #define ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_SHIFT (4U) /*! RXQ2EN - Receive Queue 2 Enable This field is similar to the RXQ0EN field. @@ -31318,6 +38658,7 @@ typedef struct { * 0b11..Reserved */ #define ENET_QOS_MAC_RXQ_CTRL_RXQ2EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_MASK) + #define ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_MASK (0xC0U) #define ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_SHIFT (6U) /*! RXQ3EN - Receive Queue 3 Enable This field is similar to the RXQ0EN field. @@ -31327,24 +38668,27 @@ typedef struct { * 0b11..Reserved */ #define ENET_QOS_MAC_RXQ_CTRL_RXQ3EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_MASK) + #define ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_MASK (0x700U) #define ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_SHIFT (8U) -/*! DCBCPQ - DCB Control Packets Queue This field specifies the Rx queue on which the received DCB control packets are routed. +/*! DCBCPQ - DCB Control Packets Queue * 0b000..Receive Queue 0 * 0b001..Receive Queue 1 * 0b010..Receive Queue 2 * 0b011..Receive Queue 3 * 0b100..Receive Queue 4 - * 0b101..Receive Queue 5 - * 0b110..Receive Queue 6 - * 0b111..Receive Queue 7 + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved */ #define ENET_QOS_MAC_RXQ_CTRL_DCBCPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_MASK) + #define ENET_QOS_MAC_RXQ_CTRL_PSRQ1_MASK (0xFF00U) #define ENET_QOS_MAC_RXQ_CTRL_PSRQ1_SHIFT (8U) -/*! PSRQ1 - Priorities Selected in the Receive Queue 1 This field decides the priorities assigned to Rx Queue 1. +/*! PSRQ1 - Priorities Selected in the Receive Queue 1 */ #define ENET_QOS_MAC_RXQ_CTRL_PSRQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ1_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ1_MASK) + #define ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_MASK (0x300U) #define ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_SHIFT (8U) /*! RXQ4EN - Receive Queue 4 Enable This field is similar to the RXQ0EN field. @@ -31354,37 +38698,41 @@ typedef struct { * 0b11..Reserved */ #define ENET_QOS_MAC_RXQ_CTRL_RXQ4EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_MASK) + #define ENET_QOS_MAC_RXQ_CTRL_UPQ_MASK (0x7000U) #define ENET_QOS_MAC_RXQ_CTRL_UPQ_SHIFT (12U) -/*! UPQ - Untagged Packet Queue This field indicates the Rx Queue to which Untagged Packets are to be routed. +/*! UPQ - Untagged Packet Queue * 0b000..Receive Queue 0 * 0b001..Receive Queue 1 * 0b010..Receive Queue 2 * 0b011..Receive Queue 3 * 0b100..Receive Queue 4 - * 0b101..Receive Queue 5 - * 0b110..Receive Queue 6 - * 0b111..Receive Queue 7 + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved */ #define ENET_QOS_MAC_RXQ_CTRL_UPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_UPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_UPQ_MASK) + #define ENET_QOS_MAC_RXQ_CTRL_MCBCQ_MASK (0x70000U) #define ENET_QOS_MAC_RXQ_CTRL_MCBCQ_SHIFT (16U) -/*! MCBCQ - Multicast and Broadcast Queue This field specifies the Rx Queue onto which Multicast or Broadcast Packets are routed. +/*! MCBCQ - Multicast and Broadcast Queue * 0b000..Receive Queue 0 * 0b001..Receive Queue 1 * 0b010..Receive Queue 2 * 0b011..Receive Queue 3 * 0b100..Receive Queue 4 - * 0b101..Receive Queue 5 - * 0b110..Receive Queue 6 - * 0b111..Receive Queue 7 + * 0b101..Reserved + * 0b110..Reserved + * 0b111..Reserved */ #define ENET_QOS_MAC_RXQ_CTRL_MCBCQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_MCBCQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_MCBCQ_MASK) + #define ENET_QOS_MAC_RXQ_CTRL_PSRQ2_MASK (0xFF0000U) #define ENET_QOS_MAC_RXQ_CTRL_PSRQ2_SHIFT (16U) -/*! PSRQ2 - Priorities Selected in the Receive Queue 2 This field decides the priorities assigned to Rx Queue 2. +/*! PSRQ2 - Priorities Selected in the Receive Queue 2 */ #define ENET_QOS_MAC_RXQ_CTRL_PSRQ2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ2_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ2_MASK) + #define ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_MASK (0x100000U) #define ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_SHIFT (20U) /*! MCBCQEN - Multicast and Broadcast Queue Enable This bit specifies that Multicast or Broadcast @@ -31394,6 +38742,7 @@ typedef struct { * 0b1..Multicast and Broadcast Queue is enabled */ #define ENET_QOS_MAC_RXQ_CTRL_MCBCQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_MASK) + #define ENET_QOS_MAC_RXQ_CTRL_TACPQE_MASK (0x200000U) #define ENET_QOS_MAC_RXQ_CTRL_TACPQE_SHIFT (21U) /*! TACPQE - Tagged AV Control Packets Queuing Enable. @@ -31401,20 +38750,22 @@ typedef struct { * 0b1..Tagged AV Control Packets Queuing is enabled */ #define ENET_QOS_MAC_RXQ_CTRL_TACPQE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_TACPQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_TACPQE_MASK) + #define ENET_QOS_MAC_RXQ_CTRL_TPQC_MASK (0xC00000U) #define ENET_QOS_MAC_RXQ_CTRL_TPQC_SHIFT (22U) /*! TPQC - Tagged PTP over Ethernet Packets Queuing Control. */ #define ENET_QOS_MAC_RXQ_CTRL_TPQC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_TPQC_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_TPQC_MASK) + #define ENET_QOS_MAC_RXQ_CTRL_FPRQ_MASK (0x7000000U) #define ENET_QOS_MAC_RXQ_CTRL_FPRQ_SHIFT (24U) -/*! FPRQ - Frame Preemption Residue Queue This field holds the Rx queue number to which the residual - * preemption frames must be forwarded. +/*! FPRQ - Frame Preemption Residue Queue */ #define ENET_QOS_MAC_RXQ_CTRL_FPRQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_FPRQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_FPRQ_MASK) + #define ENET_QOS_MAC_RXQ_CTRL_PSRQ3_MASK (0xFF000000U) #define ENET_QOS_MAC_RXQ_CTRL_PSRQ3_SHIFT (24U) -/*! PSRQ3 - Priorities Selected in the Receive Queue 3 This field decides the priorities assigned to Rx Queue 3. +/*! PSRQ3 - Priorities Selected in the Receive Queue 3 */ #define ENET_QOS_MAC_RXQ_CTRL_PSRQ3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ3_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ3_MASK) /*! @} */ @@ -31424,117 +38775,122 @@ typedef struct { /*! @name MAC_INTERRUPT_STATUS - Interrupt Status */ /*! @{ */ + #define ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_MASK (0x1U) #define ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_SHIFT (0U) -/*! RGSMIIIS - RGMII or SMII Interrupt Status This bit is set because of any change in value of the - * Link Status of RGMII or SMII interface (LNKSTS bit in MAC_PHYIF_CONTROL_STATUS register). +/*! RGSMIIIS - RGMII or SMII Interrupt Status * 0b1..RGMII or SMII Interrupt Status is active * 0b0..RGMII or SMII Interrupt Status is not active */ #define ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_MASK) + #define ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_MASK (0x8U) #define ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_SHIFT (3U) -/*! PHYIS - PHY Interrupt This bit is set when rising edge is detected on the phy_intr_i input. +/*! PHYIS - PHY Interrupt * 0b1..PHY Interrupt detected * 0b0..PHY Interrupt not detected */ #define ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_MASK) + #define ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_MASK (0x10U) #define ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_SHIFT (4U) -/*! PMTIS - PMT Interrupt Status This bit is set when a Magic packet or Wake-on-LAN packet is - * received in the power-down mode (RWKPRCVD and MGKPRCVD bits in MAC_PMT_CONTROL_STATUS register). +/*! PMTIS - PMT Interrupt Status * 0b1..PMT Interrupt status active * 0b0..PMT Interrupt status not active */ #define ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_MASK) + #define ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_MASK (0x20U) #define ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_SHIFT (5U) -/*! LPIIS - LPI Interrupt Status When the Energy Efficient Ethernet feature is enabled, this bit is - * set for any LPI state entry or exit in the MAC Transmitter or Receiver. +/*! LPIIS - LPI Interrupt Status * 0b1..LPI Interrupt status active * 0b0..LPI Interrupt status not active */ #define ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_MASK) + #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_MASK (0x100U) #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_SHIFT (8U) -/*! MMCIS - MMC Interrupt Status This bit is set high when Bit 11, Bit 10, or Bit 9 is set high. +/*! MMCIS - MMC Interrupt Status * 0b1..MMC Interrupt status active * 0b0..MMC Interrupt status not active */ #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_MASK) + #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_MASK (0x200U) #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT (9U) -/*! MMCRXIS - MMC Receive Interrupt Status This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register. +/*! MMCRXIS - MMC Receive Interrupt Status * 0b1..MMC Receive Interrupt status active * 0b0..MMC Receive Interrupt status not active */ #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_MASK) + #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_MASK (0x400U) #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT (10U) -/*! MMCTXIS - MMC Transmit Interrupt Status This bit is set high when an interrupt is generated in - * the MMC Transmit Interrupt Register. +/*! MMCTXIS - MMC Transmit Interrupt Status * 0b1..MMC Transmit Interrupt status active * 0b0..MMC Transmit Interrupt status not active */ #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_MASK) + #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_MASK (0x800U) #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_SHIFT (11U) -/*! MMCRXIPIS - MMC Receive Checksum Offload Interrupt Status This bit is set high when an interrupt - * is generated in the MMC Receive Checksum Offload Interrupt Register. +/*! MMCRXIPIS - MMC Receive Checksum Offload Interrupt Status * 0b1..MMC Receive Checksum Offload Interrupt status active * 0b0..MMC Receive Checksum Offload Interrupt status not active */ #define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_MASK) + #define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_MASK (0x1000U) #define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_SHIFT (12U) -/*! TSIS - Timestamp Interrupt Status If the Timestamp feature is enabled, this bit is set when any - * of the following conditions is true: - The system time value is equal to or exceeds the value - * specified in the Target Time High and Low registers. +/*! TSIS - Timestamp Interrupt Status * 0b1..Timestamp Interrupt status active * 0b0..Timestamp Interrupt status not active */ #define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_MASK) + #define ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_MASK (0x2000U) #define ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT (13U) -/*! TXSTSIS - Transmit Status Interrupt This bit indicates the status of transmitted packets. +/*! TXSTSIS - Transmit Status Interrupt * 0b1..Transmit Interrupt status active * 0b0..Transmit Interrupt status not active */ #define ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_MASK) + #define ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_MASK (0x4000U) #define ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT (14U) -/*! RXSTSIS - Receive Status Interrupt This bit indicates the status of received packets. +/*! RXSTSIS - Receive Status Interrupt * 0b1..Receive Interrupt status active * 0b0..Receive Interrupt status not active */ #define ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_MASK) + #define ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_MASK (0x20000U) #define ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_SHIFT (17U) -/*! FPEIS - Frame Preemption Interrupt Status This bit indicates an interrupt event during the - * operation of Frame Preemption (Bits[19:16] of MAC_FPE_CTRL_STS register is set). +/*! FPEIS - Frame Preemption Interrupt Status * 0b1..Frame Preemption Interrupt status active * 0b0..Frame Preemption Interrupt status not active */ #define ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_MASK) + #define ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_MASK (0x40000U) #define ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT (18U) -/*! MDIOIS - MDIO Interrupt Status This bit indicates an interrupt event after the completion of MDIO operation. +/*! MDIOIS - MDIO Interrupt Status * 0b1..MDIO Interrupt status active * 0b0..MDIO Interrupt status not active */ #define ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_MASK) + #define ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_MASK (0x80000U) #define ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_SHIFT (19U) -/*! MFTIS - MMC FPE Transmit Interrupt Status This bit is set high when an interrupt is generated in - * the MMC FPE Transmit Interrupt Register. +/*! MFTIS - MMC FPE Transmit Interrupt Status * 0b1..MMC FPE Transmit Interrupt status active * 0b0..MMC FPE Transmit Interrupt status not active */ #define ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_MASK) + #define ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_MASK (0x100000U) #define ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_SHIFT (20U) -/*! MFRIS - MMC FPE Receive Interrupt Status This bit is set high when an interrupt is generated in - * the MMC FPE Receive Interrupt Register. +/*! MFRIS - MMC FPE Receive Interrupt Status * 0b1..MMC FPE Receive Interrupt status active * 0b0..MMC FPE Receive Interrupt status not active */ @@ -31543,6 +38899,7 @@ typedef struct { /*! @name MAC_INTERRUPT_ENABLE - Interrupt Enable */ /*! @{ */ + #define ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_MASK (0x1U) #define ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_SHIFT (0U) /*! RGSMIIIE - RGMII or SMII Interrupt Enable When this bit is set, it enables the assertion of the @@ -31551,6 +38908,7 @@ typedef struct { * 0b1..RGMII or SMII Interrupt is enabled */ #define ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_MASK) + #define ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_MASK (0x8U) #define ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT (3U) /*! PHYIE - PHY Interrupt Enable When this bit is set, it enables the assertion of the interrupt @@ -31559,6 +38917,7 @@ typedef struct { * 0b1..PHY Interrupt is enabled */ #define ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_MASK) + #define ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_MASK (0x10U) #define ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_SHIFT (4U) /*! PMTIE - PMT Interrupt Enable When this bit is set, it enables the assertion of the interrupt @@ -31567,6 +38926,7 @@ typedef struct { * 0b1..PMT Interrupt is enabled */ #define ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_MASK) + #define ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_MASK (0x20U) #define ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_SHIFT (5U) /*! LPIIE - LPI Interrupt Enable When this bit is set, it enables the assertion of the interrupt @@ -31575,6 +38935,7 @@ typedef struct { * 0b1..LPI Interrupt is enabled */ #define ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_MASK) + #define ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_MASK (0x1000U) #define ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_SHIFT (12U) /*! TSIE - Timestamp Interrupt Enable When this bit is set, it enables the assertion of the @@ -31583,6 +38944,7 @@ typedef struct { * 0b1..Timestamp Interrupt is enabled */ #define ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_MASK) + #define ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK (0x2000U) #define ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT (13U) /*! TXSTSIE - Transmit Status Interrupt Enable When this bit is set, it enables the assertion of the @@ -31591,6 +38953,7 @@ typedef struct { * 0b1..Timestamp Status Interrupt is enabled */ #define ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK) + #define ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK (0x4000U) #define ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT (14U) /*! RXSTSIE - Receive Status Interrupt Enable When this bit is set, it enables the assertion of the @@ -31599,6 +38962,7 @@ typedef struct { * 0b1..Receive Status Interrupt is enabled */ #define ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK) + #define ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_MASK (0x20000U) #define ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_SHIFT (17U) /*! FPEIE - Frame Preemption Interrupt Enable When this bit is set, it enables the assertion of the @@ -31607,6 +38971,7 @@ typedef struct { * 0b1..Frame Preemption Interrupt is enabled */ #define ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_MASK) + #define ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_MASK (0x40000U) #define ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT (18U) /*! MDIOIE - MDIO Interrupt Enable When this bit is set, it enables the assertion of the interrupt @@ -31619,6 +38984,7 @@ typedef struct { /*! @name MAC_RX_TX_STATUS - Receive Transmit Status */ /*! @{ */ + #define ENET_QOS_MAC_RX_TX_STATUS_TJT_MASK (0x1U) #define ENET_QOS_MAC_RX_TX_STATUS_TJT_SHIFT (0U) /*! TJT - Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired which @@ -31628,6 +38994,7 @@ typedef struct { * 0b0..No Transmit Jabber Timeout */ #define ENET_QOS_MAC_RX_TX_STATUS_TJT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_TJT_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_TJT_MASK) + #define ENET_QOS_MAC_RX_TX_STATUS_NCARR_MASK (0x2U) #define ENET_QOS_MAC_RX_TX_STATUS_NCARR_SHIFT (1U) /*! NCARR - No Carrier When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit @@ -31636,6 +39003,7 @@ typedef struct { * 0b0..Carrier is present */ #define ENET_QOS_MAC_RX_TX_STATUS_NCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_NCARR_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_NCARR_MASK) + #define ENET_QOS_MAC_RX_TX_STATUS_LCARR_MASK (0x4U) #define ENET_QOS_MAC_RX_TX_STATUS_LCARR_SHIFT (2U) /*! LCARR - Loss of Carrier When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit @@ -31645,6 +39013,7 @@ typedef struct { * 0b0..Carrier is present */ #define ENET_QOS_MAC_RX_TX_STATUS_LCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_LCARR_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_LCARR_MASK) + #define ENET_QOS_MAC_RX_TX_STATUS_EXDEF_MASK (0x8U) #define ENET_QOS_MAC_RX_TX_STATUS_EXDEF_SHIFT (3U) /*! EXDEF - Excessive Deferral When the DTXSTS bit is set in the MAC_OPERATION_MODE register and the @@ -31655,6 +39024,7 @@ typedef struct { * 0b0..No Excessive deferral */ #define ENET_QOS_MAC_RX_TX_STATUS_EXDEF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_EXDEF_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_EXDEF_MASK) + #define ENET_QOS_MAC_RX_TX_STATUS_LCOL_MASK (0x10U) #define ENET_QOS_MAC_RX_TX_STATUS_LCOL_SHIFT (4U) /*! LCOL - Late Collision When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit @@ -31665,6 +39035,7 @@ typedef struct { * 0b0..No collision */ #define ENET_QOS_MAC_RX_TX_STATUS_LCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_LCOL_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_LCOL_MASK) + #define ENET_QOS_MAC_RX_TX_STATUS_EXCOL_MASK (0x20U) #define ENET_QOS_MAC_RX_TX_STATUS_EXCOL_SHIFT (5U) /*! EXCOL - Excessive Collisions When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this @@ -31674,6 +39045,7 @@ typedef struct { * 0b0..No collision */ #define ENET_QOS_MAC_RX_TX_STATUS_EXCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_EXCOL_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_EXCOL_MASK) + #define ENET_QOS_MAC_RX_TX_STATUS_RWT_MASK (0x100U) #define ENET_QOS_MAC_RX_TX_STATUS_RWT_SHIFT (8U) /*! RWT - Receive Watchdog Timeout This bit is set when a packet with length greater than 2,048 @@ -31687,6 +39059,7 @@ typedef struct { /*! @name MAC_PMT_CONTROL_STATUS - PMT Control and Status */ /*! @{ */ + #define ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK (0x1U) #define ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_SHIFT (0U) /*! PWRDWN - Power Down When this bit is set, the MAC receiver drops all received packets until it @@ -31695,6 +39068,7 @@ typedef struct { * 0b1..Power down is enabled */ #define ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK) + #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_MASK (0x2U) #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_SHIFT (1U) /*! MGKPKTEN - Magic Packet Enable When this bit is set, a power management event is generated when the MAC receives a magic packet. @@ -31702,6 +39076,7 @@ typedef struct { * 0b1..Magic Packet is enabled */ #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_MASK) + #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_MASK (0x4U) #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_SHIFT (2U) /*! RWKPKTEN - Remote Wake-Up Packet Enable When this bit is set, a power management event is @@ -31710,6 +39085,7 @@ typedef struct { * 0b1..Remote wake-up packet is enabled */ #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_MASK) + #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_MASK (0x20U) #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_SHIFT (5U) /*! MGKPRCVD - Magic Packet Received When this bit is set, it indicates that the power management @@ -31718,6 +39094,7 @@ typedef struct { * 0b0..No Magic packet is received */ #define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_MASK) + #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_MASK (0x40U) #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_SHIFT (6U) /*! RWKPRCVD - Remote Wake-Up Packet Received When this bit is set, it indicates that the power @@ -31726,6 +39103,7 @@ typedef struct { * 0b0..Remote wake-up packet is received */ #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_MASK) + #define ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_MASK (0x200U) #define ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_SHIFT (9U) /*! GLBLUCAST - Global Unicast When this bit set, any unicast packet filtered by the MAC (DAF) @@ -31734,6 +39112,7 @@ typedef struct { * 0b1..Global unicast is enabled */ #define ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_MASK) + #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_MASK (0x400U) #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_SHIFT (10U) /*! RWKPFE - Remote Wake-up Packet Forwarding Enable When this bit is set along with RWKPKTEN, the @@ -31742,6 +39121,7 @@ typedef struct { * 0b1..Remote Wake-up Packet Forwarding is enabled */ #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_MASK) + #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_MASK (0x1F000000U) #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_SHIFT (24U) /*! RWKPTR - Remote Wake-up FIFO Pointer This field gives the current value (0 to 7, 15, or 31 when @@ -31749,6 +39129,7 @@ typedef struct { * register pointer. */ #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_MASK) + #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_MASK (0x80000000U) #define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_SHIFT (31U) /*! RWKFILTRST - Remote Wake-Up Packet Filter Register Pointer Reset When this bit is set, the @@ -31761,6 +39142,7 @@ typedef struct { /*! @name MAC_RWK_PACKET_FILTER - Remote Wakeup Filter */ /*! @{ */ + #define ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_SHIFT (0U) /*! WKUPFRMFTR - RWK Packet Filter This field contains the various controls of RWK Packet filter. @@ -31770,6 +39152,7 @@ typedef struct { /*! @name MAC_LPI_CONTROL_STATUS - LPI Control and Status */ /*! @{ */ + #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_MASK (0x1U) #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_SHIFT (0U) /*! TLPIEN - Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has @@ -31778,6 +39161,7 @@ typedef struct { * 0b0..Transmit LPI entry not detected */ #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_MASK) + #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_MASK (0x2U) #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_SHIFT (1U) /*! TLPIEX - Transmit LPI Exit When this bit is set, it indicates that the MAC transmitter exited @@ -31786,6 +39170,7 @@ typedef struct { * 0b0..Transmit LPI exit not detected */ #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_MASK) + #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_MASK (0x4U) #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_SHIFT (2U) /*! RLPIEN - Receive LPI Entry When this bit is set, it indicates that the MAC Receiver has received @@ -31794,6 +39179,7 @@ typedef struct { * 0b0..Receive LPI entry not detected */ #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_MASK) + #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_MASK (0x8U) #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_SHIFT (3U) /*! RLPIEX - Receive LPI Exit When this bit is set, it indicates that the MAC Receiver has stopped @@ -31803,6 +39189,7 @@ typedef struct { * 0b0..Receive LPI exit not detected */ #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_MASK) + #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_MASK (0x100U) #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_SHIFT (8U) /*! TLPIST - Transmit LPI State When this bit is set, it indicates that the MAC is transmitting the @@ -31811,6 +39198,7 @@ typedef struct { * 0b0..Transmit LPI state not detected */ #define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_MASK) + #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_MASK (0x200U) #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_SHIFT (9U) /*! RLPIST - Receive LPI State When this bit is set, it indicates that the MAC is receiving the LPI @@ -31819,6 +39207,7 @@ typedef struct { * 0b0..Receive LPI state not detected */ #define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_MASK) + #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_MASK (0x10000U) #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_SHIFT (16U) /*! LPIEN - LPI Enable When this bit is set, it instructs the MAC Transmitter to enter the LPI state. @@ -31826,6 +39215,7 @@ typedef struct { * 0b1..LPI state is enabled */ #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_MASK) + #define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_MASK (0x20000U) #define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_SHIFT (17U) /*! PLS - PHY Link Status This bit indicates the link status of the PHY. @@ -31833,6 +39223,7 @@ typedef struct { * 0b1..link is okay (UP) */ #define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_MASK) + #define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_MASK (0x40000U) #define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_SHIFT (18U) /*! PLSEN - PHY Link Status Enable This bit enables the link status received on the RGMII, SGMII, or @@ -31841,6 +39232,7 @@ typedef struct { * 0b1..PHY Link Status is enabled */ #define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_MASK) + #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_MASK (0x80000U) #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_SHIFT (19U) /*! LPITXA - LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming @@ -31849,6 +39241,7 @@ typedef struct { * 0b1..LPI Tx Automate is enabled */ #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_MASK) + #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_MASK (0x100000U) #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_SHIFT (20U) /*! LPIATE - LPI Timer Enable This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state. @@ -31856,6 +39249,7 @@ typedef struct { * 0b1..LPI Timer is enabled */ #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_MASK) + #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_MASK (0x200000U) #define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_SHIFT (21U) /*! LPITCSE - LPI Tx Clock Stop Enable When this bit is set, the MAC asserts @@ -31868,6 +39262,7 @@ typedef struct { /*! @name MAC_LPI_TIMERS_CONTROL - LPI Timers Control */ /*! @{ */ + #define ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_MASK (0xFFFFU) #define ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_SHIFT (0U) /*! TWT - LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC @@ -31875,6 +39270,7 @@ typedef struct { * transmission. */ #define ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_SHIFT)) & ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_MASK) + #define ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_MASK (0x3FF0000U) #define ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_SHIFT (16U) /*! LST - LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link @@ -31885,6 +39281,7 @@ typedef struct { /*! @name MAC_LPI_ENTRY_TIMER - Tx LPI Entry Timer Control */ /*! @{ */ + #define ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_MASK (0xFFFF8U) #define ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_SHIFT (3U) /*! LPIET - LPI Entry Timer This field specifies the time in microseconds the MAC waits to enter LPI @@ -31895,6 +39292,7 @@ typedef struct { /*! @name MAC_ONEUS_TIC_COUNTER - One-microsecond Reference Timer */ /*! @{ */ + #define ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_MASK (0xFFFU) #define ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_SHIFT (0U) /*! TIC_1US_CNTR - 1US TIC Counter The application must program this counter so that the number of clock cycles of CSR clock is 1us. @@ -31904,6 +39302,7 @@ typedef struct { /*! @name MAC_PHYIF_CONTROL_STATUS - PHY Interface Control and Status */ /*! @{ */ + #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_MASK (0x1U) #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_SHIFT (0U) /*! TC - Transmit Configuration in RGMII, SGMII, or SMII When set, this bit enables the transmission @@ -31913,6 +39312,7 @@ typedef struct { * 0b1..Enable Transmit Configuration in RGMII, SGMII, or SMII */ #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_MASK) + #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_MASK (0x2U) #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_SHIFT (1U) /*! LUD - Link Up or Down This bit indicates whether the link is up or down during transmission of @@ -31921,6 +39321,7 @@ typedef struct { * 0b1..Link up */ #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_MASK) + #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_MASK (0x10000U) #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_SHIFT (16U) /*! LNKMOD - Link Mode This bit indicates the current mode of operation of the link. @@ -31928,6 +39329,7 @@ typedef struct { * 0b0..Half-duplex mode */ #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_MASK) + #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_MASK (0x60000U) #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_SHIFT (17U) /*! LNKSPEED - Link Speed This bit indicates the current speed of the link. @@ -31937,6 +39339,7 @@ typedef struct { * 0b11..Reserved */ #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_MASK) + #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_MASK (0x80000U) #define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_SHIFT (19U) /*! LNKSTS - Link Status This bit indicates whether the link is up (1'b1) or down (1'b0). @@ -31948,20 +39351,23 @@ typedef struct { /*! @name MAC_VERSION - MAC Version */ /*! @{ */ + #define ENET_QOS_MAC_VERSION_SNPSVER_MASK (0xFFU) #define ENET_QOS_MAC_VERSION_SNPSVER_SHIFT (0U) /*! SNPSVER - Synopsys-defined Version */ #define ENET_QOS_MAC_VERSION_SNPSVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VERSION_SNPSVER_SHIFT)) & ENET_QOS_MAC_VERSION_SNPSVER_MASK) + #define ENET_QOS_MAC_VERSION_USERVER_MASK (0xFF00U) #define ENET_QOS_MAC_VERSION_USERVER_SHIFT (8U) -/*! USERVER - User-defined Version (configured with coreConsultant) +/*! USERVER - User-defined Version (8'h10) */ #define ENET_QOS_MAC_VERSION_USERVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VERSION_USERVER_SHIFT)) & ENET_QOS_MAC_VERSION_USERVER_MASK) /*! @} */ /*! @name MAC_DEBUG - MAC Debug */ /*! @{ */ + #define ENET_QOS_MAC_DEBUG_RPESTS_MASK (0x1U) #define ENET_QOS_MAC_DEBUG_RPESTS_SHIFT (0U) /*! RPESTS - MAC GMII or MII Receive Protocol Engine Status When this bit is set, it indicates that @@ -31971,6 +39377,7 @@ typedef struct { * 0b0..MAC GMII or MII Receive Protocol Engine Status not detected */ #define ENET_QOS_MAC_DEBUG_RPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_RPESTS_SHIFT)) & ENET_QOS_MAC_DEBUG_RPESTS_MASK) + #define ENET_QOS_MAC_DEBUG_RFCFCSTS_MASK (0x6U) #define ENET_QOS_MAC_DEBUG_RFCFCSTS_SHIFT (1U) /*! RFCFCSTS - MAC Receive Packet Controller FIFO Status When this bit is set, this field indicates @@ -31978,6 +39385,7 @@ typedef struct { * Controller module. */ #define ENET_QOS_MAC_DEBUG_RFCFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_RFCFCSTS_SHIFT)) & ENET_QOS_MAC_DEBUG_RFCFCSTS_MASK) + #define ENET_QOS_MAC_DEBUG_TPESTS_MASK (0x10000U) #define ENET_QOS_MAC_DEBUG_TPESTS_SHIFT (16U) /*! TPESTS - MAC GMII or MII Transmit Protocol Engine Status When this bit is set, it indicates that @@ -31987,6 +39395,7 @@ typedef struct { * 0b0..MAC GMII or MII Transmit Protocol Engine Status not detected */ #define ENET_QOS_MAC_DEBUG_TPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_TPESTS_SHIFT)) & ENET_QOS_MAC_DEBUG_TPESTS_MASK) + #define ENET_QOS_MAC_DEBUG_TFCSTS_MASK (0x60000U) #define ENET_QOS_MAC_DEBUG_TFCSTS_SHIFT (17U) /*! TFCSTS - MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module. @@ -32000,6 +39409,7 @@ typedef struct { /*! @name MAC_HW_FEAT - Optional Features or Functions 0..Optional Features or Functions 3 */ /*! @{ */ + #define ENET_QOS_MAC_HW_FEAT_MIISEL_MASK (0x1U) #define ENET_QOS_MAC_HW_FEAT_MIISEL_SHIFT (0U) /*! MIISEL - 10 or 100 Mbps Support This bit is set to 1 when 10/100 Mbps is selected as the Mode of Operation @@ -32007,6 +39417,7 @@ typedef struct { * 0b0..No 10 or 100 Mbps support */ #define ENET_QOS_MAC_HW_FEAT_MIISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MIISEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MIISEL_MASK) + #define ENET_QOS_MAC_HW_FEAT_NRVF_MASK (0x7U) #define ENET_QOS_MAC_HW_FEAT_NRVF_SHIFT (0U) /*! NRVF - Number of Extended VLAN Tag Filters Enabled This field indicates the Number of Extended VLAN Tag Filters selected: @@ -32019,6 +39430,7 @@ typedef struct { * 0b110..Reserved */ #define ENET_QOS_MAC_HW_FEAT_NRVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_NRVF_SHIFT)) & ENET_QOS_MAC_HW_FEAT_NRVF_MASK) + #define ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_MASK (0x1FU) #define ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_SHIFT (0U) /*! RXFIFOSIZE - MTL Receive FIFO Size This field contains the configured value of MTL Rx FIFO in @@ -32038,6 +39450,7 @@ typedef struct { * 0b01100..Reserved */ #define ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_MASK) + #define ENET_QOS_MAC_HW_FEAT_RXQCNT_MASK (0xFU) #define ENET_QOS_MAC_HW_FEAT_RXQCNT_SHIFT (0U) /*! RXQCNT - Number of MTL Receive Queues This field indicates the number of MTL Receive queues: @@ -32046,11 +39459,12 @@ typedef struct { * 0b0010..3 MTL Rx Queues * 0b0011..4 MTL Rx Queues * 0b0100..5 MTL Rx Queues - * 0b0101..6 MTL Rx Queues - * 0b0110..7 MTL Rx Queues - * 0b0111..8 MTL Rx Queues + * 0b0101..Reserved + * 0b0110..Reserved + * 0b0111..Reserved */ #define ENET_QOS_MAC_HW_FEAT_RXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXQCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXQCNT_MASK) + #define ENET_QOS_MAC_HW_FEAT_GMIISEL_MASK (0x2U) #define ENET_QOS_MAC_HW_FEAT_GMIISEL_SHIFT (1U) /*! GMIISEL - 1000 Mbps Support This bit is set to 1 when 1000 Mbps is selected as the Mode of Operation @@ -32058,6 +39472,7 @@ typedef struct { * 0b0..No 1000 Mbps support */ #define ENET_QOS_MAC_HW_FEAT_GMIISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_GMIISEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_GMIISEL_MASK) + #define ENET_QOS_MAC_HW_FEAT_HDSEL_MASK (0x4U) #define ENET_QOS_MAC_HW_FEAT_HDSEL_SHIFT (2U) /*! HDSEL - Half-duplex Support This bit is set to 1 when the half-duplex mode is selected @@ -32065,6 +39480,7 @@ typedef struct { * 0b0..No Half-duplex support */ #define ENET_QOS_MAC_HW_FEAT_HDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_HDSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_HDSEL_MASK) + #define ENET_QOS_MAC_HW_FEAT_PCSSEL_MASK (0x8U) #define ENET_QOS_MAC_HW_FEAT_PCSSEL_SHIFT (3U) /*! PCSSEL - PCS Registers (TBI, SGMII, or RTBI PHY interface) This bit is set to 1 when the TBI, @@ -32073,6 +39489,7 @@ typedef struct { * 0b0..No PCS Registers (TBI, SGMII, or RTBI PHY interface) */ #define ENET_QOS_MAC_HW_FEAT_PCSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PCSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PCSSEL_MASK) + #define ENET_QOS_MAC_HW_FEAT_CBTISEL_MASK (0x10U) #define ENET_QOS_MAC_HW_FEAT_CBTISEL_SHIFT (4U) /*! CBTISEL - Queue/Channel based VLAN tag insertion on Tx Enable This bit is set to 1 when the @@ -32081,6 +39498,7 @@ typedef struct { * 0b0..Enable Queue/Channel based VLAN tag insertion on Tx feature is not selected */ #define ENET_QOS_MAC_HW_FEAT_CBTISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_CBTISEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_CBTISEL_MASK) + #define ENET_QOS_MAC_HW_FEAT_VLHASH_MASK (0x10U) #define ENET_QOS_MAC_HW_FEAT_VLHASH_SHIFT (4U) /*! VLHASH - VLAN Hash Filter Selected This bit is set to 1 when the Enable VLAN Hash Table Based Filtering option is selected @@ -32088,6 +39506,7 @@ typedef struct { * 0b0..VLAN Hash Filter not selected */ #define ENET_QOS_MAC_HW_FEAT_VLHASH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_VLHASH_SHIFT)) & ENET_QOS_MAC_HW_FEAT_VLHASH_MASK) + #define ENET_QOS_MAC_HW_FEAT_DVLAN_MASK (0x20U) #define ENET_QOS_MAC_HW_FEAT_DVLAN_SHIFT (5U) /*! DVLAN - Double VLAN Tag Processing Selected This bit is set to 1 when the Enable Double VLAN Processing Feature is selected. @@ -32095,6 +39514,7 @@ typedef struct { * 0b0..Double VLAN option is not selected */ #define ENET_QOS_MAC_HW_FEAT_DVLAN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_DVLAN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_DVLAN_MASK) + #define ENET_QOS_MAC_HW_FEAT_SMASEL_MASK (0x20U) #define ENET_QOS_MAC_HW_FEAT_SMASEL_SHIFT (5U) /*! SMASEL - SMA (MDIO) Interface This bit is set to 1 when the Enable Station Management (MDIO Interface) option is selected @@ -32102,6 +39522,7 @@ typedef struct { * 0b0..SMA (MDIO) Interface not selected */ #define ENET_QOS_MAC_HW_FEAT_SMASEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SMASEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SMASEL_MASK) + #define ENET_QOS_MAC_HW_FEAT_SPRAM_MASK (0x20U) #define ENET_QOS_MAC_HW_FEAT_SPRAM_SHIFT (5U) /*! SPRAM - Single Port RAM Enable This bit is set to 1 when the Use single port RAM Feature is selected. @@ -32109,6 +39530,7 @@ typedef struct { * 0b0..Single Port RAM feature is not selected */ #define ENET_QOS_MAC_HW_FEAT_SPRAM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SPRAM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SPRAM_MASK) + #define ENET_QOS_MAC_HW_FEAT_RWKSEL_MASK (0x40U) #define ENET_QOS_MAC_HW_FEAT_RWKSEL_SHIFT (6U) /*! RWKSEL - PMT Remote Wake-up Packet Enable This bit is set to 1 when the Enable Remote Wake-Up Packet Detection option is selected @@ -32116,6 +39538,7 @@ typedef struct { * 0b0..PMT Remote Wake-up Packet Enable option is not selected */ #define ENET_QOS_MAC_HW_FEAT_RWKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RWKSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RWKSEL_MASK) + #define ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_MASK (0x7C0U) #define ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_SHIFT (6U) /*! TXFIFOSIZE - MTL Transmit FIFO Size This field contains the configured value of MTL Tx FIFO in @@ -32134,6 +39557,7 @@ typedef struct { * 0b01011..Reserved */ #define ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_MASK) + #define ENET_QOS_MAC_HW_FEAT_TXQCNT_MASK (0x3C0U) #define ENET_QOS_MAC_HW_FEAT_TXQCNT_SHIFT (6U) /*! TXQCNT - Number of MTL Transmit Queues This field indicates the number of MTL Transmit queues: @@ -32142,11 +39566,12 @@ typedef struct { * 0b0010..3 MTL Tx Queues * 0b0011..4 MTL Tx Queues * 0b0100..5 MTL Tx Queues - * 0b0101..6 MTL Tx Queues - * 0b0110..7 MTL Tx Queues - * 0b0111..8 MTL Tx Queues + * 0b0101..Reserved + * 0b0110..Reserved + * 0b0111..Reserved */ #define ENET_QOS_MAC_HW_FEAT_TXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXQCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXQCNT_MASK) + #define ENET_QOS_MAC_HW_FEAT_MGKSEL_MASK (0x80U) #define ENET_QOS_MAC_HW_FEAT_MGKSEL_SHIFT (7U) /*! MGKSEL - PMT Magic Packet Enable This bit is set to 1 when the Enable Magic Packet Detection option is selected @@ -32154,6 +39579,7 @@ typedef struct { * 0b0..PMT Magic Packet Enable option is not selected */ #define ENET_QOS_MAC_HW_FEAT_MGKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MGKSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MGKSEL_MASK) + #define ENET_QOS_MAC_HW_FEAT_MMCSEL_MASK (0x100U) #define ENET_QOS_MAC_HW_FEAT_MMCSEL_SHIFT (8U) /*! MMCSEL - RMON Module Enable This bit is set to 1 when the Enable MAC Management Counters (MMC) option is selected @@ -32161,6 +39587,7 @@ typedef struct { * 0b0..RMON Module Enable option is not selected */ #define ENET_QOS_MAC_HW_FEAT_MMCSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MMCSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MMCSEL_MASK) + #define ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_MASK (0x200U) #define ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_SHIFT (9U) /*! ARPOFFSEL - ARP Offload Enabled This bit is set to 1 when the Enable IPv4 ARP Offload option is selected @@ -32168,6 +39595,7 @@ typedef struct { * 0b0..ARP Offload Enable option is not selected */ #define ENET_QOS_MAC_HW_FEAT_ARPOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_MASK) + #define ENET_QOS_MAC_HW_FEAT_PDUPSEL_MASK (0x200U) #define ENET_QOS_MAC_HW_FEAT_PDUPSEL_SHIFT (9U) /*! PDUPSEL - Broadcast/Multicast Packet Duplication This bit is set to 1 when the @@ -32176,6 +39604,7 @@ typedef struct { * 0b0..Broadcast/Multicast Packet Duplication feature is not selected */ #define ENET_QOS_MAC_HW_FEAT_PDUPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PDUPSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PDUPSEL_MASK) + #define ENET_QOS_MAC_HW_FEAT_FRPSEL_MASK (0x400U) #define ENET_QOS_MAC_HW_FEAT_FRPSEL_SHIFT (10U) /*! FRPSEL - Flexible Receive Parser Selected This bit is set to 1 when the Enable Flexible @@ -32184,6 +39613,7 @@ typedef struct { * 0b0..Flexible Receive Parser feature is not selected */ #define ENET_QOS_MAC_HW_FEAT_FRPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FRPSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FRPSEL_MASK) + #define ENET_QOS_MAC_HW_FEAT_FRPBS_MASK (0x1800U) #define ENET_QOS_MAC_HW_FEAT_FRPBS_SHIFT (11U) /*! FRPBS - Flexible Receive Parser Buffer size This field indicates the supported Max Number of @@ -32194,6 +39624,7 @@ typedef struct { * 0b11..Reserved */ #define ENET_QOS_MAC_HW_FEAT_FRPBS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FRPBS_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FRPBS_MASK) + #define ENET_QOS_MAC_HW_FEAT_OSTEN_MASK (0x800U) #define ENET_QOS_MAC_HW_FEAT_OSTEN_SHIFT (11U) /*! OSTEN - One-Step Timestamping Enable This bit is set to 1 when the Enable One-Step Timestamp Feature is selected. @@ -32201,6 +39632,7 @@ typedef struct { * 0b0..One-Step Timestamping feature is not selected */ #define ENET_QOS_MAC_HW_FEAT_OSTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_OSTEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_OSTEN_MASK) + #define ENET_QOS_MAC_HW_FEAT_PTOEN_MASK (0x1000U) #define ENET_QOS_MAC_HW_FEAT_PTOEN_SHIFT (12U) /*! PTOEN - PTP Offload Enable This bit is set to 1 when the Enable PTP Timestamp Offload Feature is selected. @@ -32208,6 +39640,7 @@ typedef struct { * 0b0..PTP Offload feature is not selected */ #define ENET_QOS_MAC_HW_FEAT_PTOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PTOEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PTOEN_MASK) + #define ENET_QOS_MAC_HW_FEAT_RXCHCNT_MASK (0xF000U) #define ENET_QOS_MAC_HW_FEAT_RXCHCNT_SHIFT (12U) /*! RXCHCNT - Number of DMA Receive Channels This field indicates the number of DMA Receive channels: @@ -32216,11 +39649,12 @@ typedef struct { * 0b0010..3 MTL Rx Channels * 0b0011..4 MTL Rx Channels * 0b0100..5 MTL Rx Channels - * 0b0101..6 MTL Rx Channels - * 0b0110..7 MTL Rx Channels - * 0b0111..8 MTL Rx Channels + * 0b0101..Reserved + * 0b0110..Reserved + * 0b0111..Reserved */ #define ENET_QOS_MAC_HW_FEAT_RXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXCHCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXCHCNT_MASK) + #define ENET_QOS_MAC_HW_FEAT_TSSEL_MASK (0x1000U) #define ENET_QOS_MAC_HW_FEAT_TSSEL_SHIFT (12U) /*! TSSEL - IEEE 1588-2008 Timestamp Enabled This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected @@ -32228,6 +39662,7 @@ typedef struct { * 0b0..IEEE 1588-2008 Timestamp Enable option is not selected */ #define ENET_QOS_MAC_HW_FEAT_TSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TSSEL_MASK) + #define ENET_QOS_MAC_HW_FEAT_ADVTHWORD_MASK (0x2000U) #define ENET_QOS_MAC_HW_FEAT_ADVTHWORD_SHIFT (13U) /*! ADVTHWORD - IEEE 1588 High Word Register Enable This bit is set to 1 when the Add IEEE 1588 Higher Word Register option is selected @@ -32235,6 +39670,7 @@ typedef struct { * 0b0..IEEE 1588 High Word Register option is not selected */ #define ENET_QOS_MAC_HW_FEAT_ADVTHWORD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ADVTHWORD_MASK) + #define ENET_QOS_MAC_HW_FEAT_EEESEL_MASK (0x2000U) #define ENET_QOS_MAC_HW_FEAT_EEESEL_SHIFT (13U) /*! EEESEL - Energy Efficient Ethernet Enabled This bit is set to 1 when the Enable Energy Efficient @@ -32243,6 +39679,7 @@ typedef struct { * 0b0..Energy Efficient Ethernet Enable option is not selected */ #define ENET_QOS_MAC_HW_FEAT_EEESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_EEESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_EEESEL_MASK) + #define ENET_QOS_MAC_HW_FEAT_FRPES_MASK (0x6000U) #define ENET_QOS_MAC_HW_FEAT_FRPES_SHIFT (13U) /*! FRPES - Flexible Receive Parser Table Entries size This field indicates the Max Number of Parser @@ -32253,6 +39690,7 @@ typedef struct { * 0b11..Reserved */ #define ENET_QOS_MAC_HW_FEAT_FRPES(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FRPES_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FRPES_MASK) + #define ENET_QOS_MAC_HW_FEAT_ADDR64_MASK (0xC000U) #define ENET_QOS_MAC_HW_FEAT_ADDR64_SHIFT (14U) /*! ADDR64 - Address Width. @@ -32262,6 +39700,7 @@ typedef struct { * 0b11..Reserved */ #define ENET_QOS_MAC_HW_FEAT_ADDR64(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ADDR64_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ADDR64_MASK) + #define ENET_QOS_MAC_HW_FEAT_TXCOESEL_MASK (0x4000U) #define ENET_QOS_MAC_HW_FEAT_TXCOESEL_SHIFT (14U) /*! TXCOESEL - Transmit Checksum Offload Enabled This bit is set to 1 when the Enable Transmit @@ -32270,6 +39709,7 @@ typedef struct { * 0b0..Transmit Checksum Offload Enable option is not selected */ #define ENET_QOS_MAC_HW_FEAT_TXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXCOESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXCOESEL_MASK) + #define ENET_QOS_MAC_HW_FEAT_DCBEN_MASK (0x10000U) #define ENET_QOS_MAC_HW_FEAT_DCBEN_SHIFT (16U) /*! DCBEN - DCB Feature Enable This bit is set to 1 when the Enable Data Center Bridging option is selected @@ -32277,6 +39717,7 @@ typedef struct { * 0b0..DCB Feature is not selected */ #define ENET_QOS_MAC_HW_FEAT_DCBEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_DCBEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_DCBEN_MASK) + #define ENET_QOS_MAC_HW_FEAT_ESTSEL_MASK (0x10000U) #define ENET_QOS_MAC_HW_FEAT_ESTSEL_SHIFT (16U) /*! ESTSEL - Enhancements to Scheduling Traffic Enable This bit is set to 1 when the Enable @@ -32285,6 +39726,7 @@ typedef struct { * 0b0..Enable Enhancements to Scheduling Traffic feature is not selected */ #define ENET_QOS_MAC_HW_FEAT_ESTSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ESTSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ESTSEL_MASK) + #define ENET_QOS_MAC_HW_FEAT_RXCOESEL_MASK (0x10000U) #define ENET_QOS_MAC_HW_FEAT_RXCOESEL_SHIFT (16U) /*! RXCOESEL - Receive Checksum Offload Enabled This bit is set to 1 when the Enable Receive TCP/IP Checksum Check option is selected @@ -32292,6 +39734,7 @@ typedef struct { * 0b0..Receive Checksum Offload Enable option is not selected */ #define ENET_QOS_MAC_HW_FEAT_RXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXCOESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXCOESEL_MASK) + #define ENET_QOS_MAC_HW_FEAT_ESTDEP_MASK (0xE0000U) #define ENET_QOS_MAC_HW_FEAT_ESTDEP_SHIFT (17U) /*! ESTDEP - Depth of the Gate Control List This field indicates the depth of Gate Control list expressed as Log2(DWC_EQOS_EST_DEP)-5 @@ -32304,6 +39747,7 @@ typedef struct { * 0b110..Reserved */ #define ENET_QOS_MAC_HW_FEAT_ESTDEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ESTDEP_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ESTDEP_MASK) + #define ENET_QOS_MAC_HW_FEAT_SPHEN_MASK (0x20000U) #define ENET_QOS_MAC_HW_FEAT_SPHEN_SHIFT (17U) /*! SPHEN - Split Header Feature Enable This bit is set to 1 when the Enable Split Header Structure option is selected @@ -32311,12 +39755,14 @@ typedef struct { * 0b0..Split Header Feature is not selected */ #define ENET_QOS_MAC_HW_FEAT_SPHEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SPHEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SPHEN_MASK) + #define ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_MASK (0x7C0000U) #define ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_SHIFT (18U) /*! ADDMACADRSEL - MAC Addresses 1-31 Selected This bit is set to 1 when the non-zero value is * selected for Enable Additional 1-31 MAC Address Registers option */ #define ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_MASK) + #define ENET_QOS_MAC_HW_FEAT_TSOEN_MASK (0x40000U) #define ENET_QOS_MAC_HW_FEAT_TSOEN_SHIFT (18U) /*! TSOEN - TCP Segmentation Offload Enable This bit is set to 1 when the Enable TCP Segmentation @@ -32325,6 +39771,7 @@ typedef struct { * 0b0..TCP Segmentation Offload Feature is not selected */ #define ENET_QOS_MAC_HW_FEAT_TSOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TSOEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TSOEN_MASK) + #define ENET_QOS_MAC_HW_FEAT_TXCHCNT_MASK (0x3C0000U) #define ENET_QOS_MAC_HW_FEAT_TXCHCNT_SHIFT (18U) /*! TXCHCNT - Number of DMA Transmit Channels This field indicates the number of DMA Transmit channels: @@ -32333,11 +39780,12 @@ typedef struct { * 0b0010..3 MTL Tx Channels * 0b0011..4 MTL Tx Channels * 0b0100..5 MTL Tx Channels - * 0b0101..6 MTL Tx Channels - * 0b0110..7 MTL Tx Channels - * 0b0111..8 MTL Tx Channels + * 0b0101..Reserved + * 0b0110..Reserved + * 0b0111..Reserved */ #define ENET_QOS_MAC_HW_FEAT_TXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXCHCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXCHCNT_MASK) + #define ENET_QOS_MAC_HW_FEAT_DBGMEMA_MASK (0x80000U) #define ENET_QOS_MAC_HW_FEAT_DBGMEMA_SHIFT (19U) /*! DBGMEMA - DMA Debug Registers Enable This bit is set to 1 when the Debug Mode Enable option is selected @@ -32345,6 +39793,7 @@ typedef struct { * 0b0..DMA Debug Registers option is not selected */ #define ENET_QOS_MAC_HW_FEAT_DBGMEMA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_DBGMEMA_SHIFT)) & ENET_QOS_MAC_HW_FEAT_DBGMEMA_MASK) + #define ENET_QOS_MAC_HW_FEAT_AVSEL_MASK (0x100000U) #define ENET_QOS_MAC_HW_FEAT_AVSEL_SHIFT (20U) /*! AVSEL - AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option is selected. @@ -32352,6 +39801,7 @@ typedef struct { * 0b0..AV Feature is not selected */ #define ENET_QOS_MAC_HW_FEAT_AVSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_AVSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_AVSEL_MASK) + #define ENET_QOS_MAC_HW_FEAT_ESTWID_MASK (0x300000U) #define ENET_QOS_MAC_HW_FEAT_ESTWID_SHIFT (20U) /*! ESTWID - Width of the Time Interval field in the Gate Control List This field indicates the @@ -32362,6 +39812,7 @@ typedef struct { * 0b11..24 */ #define ENET_QOS_MAC_HW_FEAT_ESTWID(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ESTWID_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ESTWID_MASK) + #define ENET_QOS_MAC_HW_FEAT_RAVSEL_MASK (0x200000U) #define ENET_QOS_MAC_HW_FEAT_RAVSEL_SHIFT (21U) /*! RAVSEL - Rx Side Only AV Feature Enable This bit is set to 1 when the Enable Audio Video @@ -32370,6 +39821,7 @@ typedef struct { * 0b0..Rx Side Only AV Feature is not selected */ #define ENET_QOS_MAC_HW_FEAT_RAVSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RAVSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RAVSEL_MASK) + #define ENET_QOS_MAC_HW_FEAT_MACADR32SEL_MASK (0x800000U) #define ENET_QOS_MAC_HW_FEAT_MACADR32SEL_SHIFT (23U) /*! MACADR32SEL - MAC Addresses 32-63 Selected This bit is set to 1 when the Enable Additional 32 @@ -32378,6 +39830,7 @@ typedef struct { * 0b0..MAC Addresses 32-63 Select option is not selected */ #define ENET_QOS_MAC_HW_FEAT_MACADR32SEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MACADR32SEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MACADR32SEL_MASK) + #define ENET_QOS_MAC_HW_FEAT_POUOST_MASK (0x800000U) #define ENET_QOS_MAC_HW_FEAT_POUOST_SHIFT (23U) /*! POUOST - One Step for PTP over UDP/IP Feature Enable This bit is set to 1 when the Enable One @@ -32386,6 +39839,7 @@ typedef struct { * 0b0..One Step for PTP over UDP/IP Feature is not selected */ #define ENET_QOS_MAC_HW_FEAT_POUOST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_POUOST_SHIFT)) & ENET_QOS_MAC_HW_FEAT_POUOST_MASK) + #define ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_MASK (0x3000000U) #define ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_SHIFT (24U) /*! HASHTBLSZ - Hash Table Size This field indicates the size of the hash table: @@ -32395,6 +39849,7 @@ typedef struct { * 0b00..No hash table */ #define ENET_QOS_MAC_HW_FEAT_HASHTBLSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_MASK) + #define ENET_QOS_MAC_HW_FEAT_MACADR64SEL_MASK (0x1000000U) #define ENET_QOS_MAC_HW_FEAT_MACADR64SEL_SHIFT (24U) /*! MACADR64SEL - MAC Addresses 64-127 Selected This bit is set to 1 when the Enable Additional 64 @@ -32403,6 +39858,7 @@ typedef struct { * 0b0..MAC Addresses 64-127 Select option is not selected */ #define ENET_QOS_MAC_HW_FEAT_MACADR64SEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MACADR64SEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MACADR64SEL_MASK) + #define ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_MASK (0x7000000U) #define ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_SHIFT (24U) /*! PPSOUTNUM - Number of PPS Outputs This field indicates the number of PPS outputs: @@ -32414,6 +39870,7 @@ typedef struct { * 0b101..Reserved */ #define ENET_QOS_MAC_HW_FEAT_PPSOUTNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_MASK) + #define ENET_QOS_MAC_HW_FEAT_TSSTSSEL_MASK (0x6000000U) #define ENET_QOS_MAC_HW_FEAT_TSSTSSEL_SHIFT (25U) /*! TSSTSSEL - Timestamp System Time Source This bit indicates the source of the Timestamp system @@ -32424,6 +39881,7 @@ typedef struct { * 0b11..Reserved */ #define ENET_QOS_MAC_HW_FEAT_TSSTSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TSSTSSEL_MASK) + #define ENET_QOS_MAC_HW_FEAT_FPESEL_MASK (0x4000000U) #define ENET_QOS_MAC_HW_FEAT_FPESEL_SHIFT (26U) /*! FPESEL - Frame Preemption Enable This bit is set to 1 when the Enable Frame preemption feature is selected. @@ -32431,6 +39889,7 @@ typedef struct { * 0b0..Frame Preemption Enable feature is not selected */ #define ENET_QOS_MAC_HW_FEAT_FPESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FPESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FPESEL_MASK) + #define ENET_QOS_MAC_HW_FEAT_L3L4FNUM_MASK (0x78000000U) #define ENET_QOS_MAC_HW_FEAT_L3L4FNUM_SHIFT (27U) /*! L3L4FNUM - Total number of L3 or L4 Filters This field indicates the total number of L3 or L4 filters: @@ -32445,6 +39904,7 @@ typedef struct { * 0b0000..No L3 or L4 Filter */ #define ENET_QOS_MAC_HW_FEAT_L3L4FNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_L3L4FNUM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_L3L4FNUM_MASK) + #define ENET_QOS_MAC_HW_FEAT_SAVLANINS_MASK (0x8000000U) #define ENET_QOS_MAC_HW_FEAT_SAVLANINS_SHIFT (27U) /*! SAVLANINS - Source Address or VLAN Insertion Enable This bit is set to 1 when the Enable SA and @@ -32453,6 +39913,7 @@ typedef struct { * 0b0..Source Address or VLAN Insertion Enable option is not selected */ #define ENET_QOS_MAC_HW_FEAT_SAVLANINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SAVLANINS_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SAVLANINS_MASK) + #define ENET_QOS_MAC_HW_FEAT_TBSSEL_MASK (0x8000000U) #define ENET_QOS_MAC_HW_FEAT_TBSSEL_SHIFT (27U) /*! TBSSEL - Time Based Scheduling Enable This bit is set to 1 when the Time Based Scheduling feature is selected. @@ -32460,6 +39921,7 @@ typedef struct { * 0b0..Time Based Scheduling Enable feature is not selected */ #define ENET_QOS_MAC_HW_FEAT_TBSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TBSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TBSSEL_MASK) + #define ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_MASK (0x70000000U) #define ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_SHIFT (28U) /*! ACTPHYSEL - Active PHY Selected When you have multiple PHY interfaces in your configuration, @@ -32474,6 +39936,7 @@ typedef struct { * 0b011..TBI */ #define ENET_QOS_MAC_HW_FEAT_ACTPHYSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_MASK) + #define ENET_QOS_MAC_HW_FEAT_ASP_MASK (0x30000000U) #define ENET_QOS_MAC_HW_FEAT_ASP_SHIFT (28U) /*! ASP - Automotive Safety Package Following are the encoding for the different Safety features @@ -32483,6 +39946,7 @@ typedef struct { * 0b00..No Safety features selected */ #define ENET_QOS_MAC_HW_FEAT_ASP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ASP_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ASP_MASK) + #define ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_MASK (0x70000000U) #define ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_SHIFT (28U) /*! AUXSNAPNUM - Number of Auxiliary Snapshot Inputs This field indicates the number of auxiliary snapshot inputs: @@ -32501,6 +39965,7 @@ typedef struct { /*! @name MAC_MDIO_ADDRESS - MDIO Address */ /*! @{ */ + #define ENET_QOS_MAC_MDIO_ADDRESS_GB_MASK (0x1U) #define ENET_QOS_MAC_MDIO_ADDRESS_GB_SHIFT (0U) /*! GB - GMII Busy The application sets this bit to instruct the SMA to initiate a Read or Write access to the MDIO slave. @@ -32508,6 +39973,7 @@ typedef struct { * 0b1..GMII Busy is enabled */ #define ENET_QOS_MAC_MDIO_ADDRESS_GB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_GB_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_GB_MASK) + #define ENET_QOS_MAC_MDIO_ADDRESS_C45E_MASK (0x2U) #define ENET_QOS_MAC_MDIO_ADDRESS_C45E_SHIFT (1U) /*! C45E - Clause 45 PHY Enable When this bit is set, Clause 45 capable PHY is connected to MDIO. @@ -32515,6 +39981,7 @@ typedef struct { * 0b1..Clause 45 PHY is enabled */ #define ENET_QOS_MAC_MDIO_ADDRESS_C45E(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_C45E_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_C45E_MASK) + #define ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_MASK (0x4U) #define ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_SHIFT (2U) /*! GOC_0 - GMII Operation Command 0 This is the lower bit of the operation command to the PHY or RevMII. @@ -32522,6 +39989,7 @@ typedef struct { * 0b1..GMII Operation Command 0 is enabled */ #define ENET_QOS_MAC_MDIO_ADDRESS_GOC_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_MASK) + #define ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_MASK (0x8U) #define ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_SHIFT (3U) /*! GOC_1 - GMII Operation Command 1 This bit is higher bit of the operation command to the PHY or @@ -32532,6 +40000,7 @@ typedef struct { * 0b1..GMII Operation Command 1 is enabled */ #define ENET_QOS_MAC_MDIO_ADDRESS_GOC_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_MASK) + #define ENET_QOS_MAC_MDIO_ADDRESS_SKAP_MASK (0x10U) #define ENET_QOS_MAC_MDIO_ADDRESS_SKAP_SHIFT (4U) /*! SKAP - Skip Address Packet When this bit is set, the SMA does not send the address packets @@ -32540,6 +40009,7 @@ typedef struct { * 0b1..Skip Address Packet is enabled */ #define ENET_QOS_MAC_MDIO_ADDRESS_SKAP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_SKAP_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_SKAP_MASK) + #define ENET_QOS_MAC_MDIO_ADDRESS_CR_MASK (0xF00U) #define ENET_QOS_MAC_MDIO_ADDRESS_CR_SHIFT (8U) /*! CR - CSR Clock Range The CSR Clock Range selection determines the frequency of the MDC clock @@ -32552,22 +40022,26 @@ typedef struct { * applicable for each value (when Bit 11 = 0) ensures that the MDC clock is approximately between 1. */ #define ENET_QOS_MAC_MDIO_ADDRESS_CR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_CR_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_CR_MASK) + #define ENET_QOS_MAC_MDIO_ADDRESS_NTC_MASK (0x7000U) #define ENET_QOS_MAC_MDIO_ADDRESS_NTC_SHIFT (12U) /*! NTC - Number of Trailing Clocks This field controls the number of trailing clock cycles * generated on gmii_mdc_o (MDC) after the end of transmission of MDIO frame. */ #define ENET_QOS_MAC_MDIO_ADDRESS_NTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_NTC_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_NTC_MASK) + #define ENET_QOS_MAC_MDIO_ADDRESS_RDA_MASK (0x1F0000U) #define ENET_QOS_MAC_MDIO_ADDRESS_RDA_SHIFT (16U) /*! RDA - Register/Device Address These bits select the PHY register in selected Clause 22 PHY device. */ #define ENET_QOS_MAC_MDIO_ADDRESS_RDA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_RDA_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_RDA_MASK) + #define ENET_QOS_MAC_MDIO_ADDRESS_PA_MASK (0x3E00000U) #define ENET_QOS_MAC_MDIO_ADDRESS_PA_SHIFT (21U) /*! PA - Physical Layer Address This field indicates which Clause 22 PHY devices (out of 32 devices) the MAC is accessing. */ #define ENET_QOS_MAC_MDIO_ADDRESS_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_PA_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_PA_MASK) + #define ENET_QOS_MAC_MDIO_ADDRESS_BTB_MASK (0x4000000U) #define ENET_QOS_MAC_MDIO_ADDRESS_BTB_SHIFT (26U) /*! BTB - Back to Back transactions When this bit is set and the NTC has value greater than 0, then @@ -32577,6 +40051,7 @@ typedef struct { * 0b1..Back to Back transactions enabled */ #define ENET_QOS_MAC_MDIO_ADDRESS_BTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_BTB_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_BTB_MASK) + #define ENET_QOS_MAC_MDIO_ADDRESS_PSE_MASK (0x8000000U) #define ENET_QOS_MAC_MDIO_ADDRESS_PSE_SHIFT (27U) /*! PSE - Preamble Suppression Enable When this bit is set, the SMA suppresses the 32-bit preamble @@ -32589,6 +40064,7 @@ typedef struct { /*! @name MAC_MDIO_DATA - MAC MDIO Data */ /*! @{ */ + #define ENET_QOS_MAC_MDIO_DATA_GD_MASK (0xFFFFU) #define ENET_QOS_MAC_MDIO_DATA_GD_SHIFT (0U) /*! GD - GMII Data This field contains the 16-bit data value read from the PHY or RevMII after a @@ -32596,6 +40072,7 @@ typedef struct { * Management Write operation. */ #define ENET_QOS_MAC_MDIO_DATA_GD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_DATA_GD_SHIFT)) & ENET_QOS_MAC_MDIO_DATA_GD_MASK) + #define ENET_QOS_MAC_MDIO_DATA_RA_MASK (0xFFFF0000U) #define ENET_QOS_MAC_MDIO_DATA_RA_SHIFT (16U) /*! RA - Register Address This field is valid only when C45E is set. @@ -32605,6 +40082,7 @@ typedef struct { /*! @name MAC_CSR_SW_CTRL - CSR Software Control */ /*! @{ */ + #define ENET_QOS_MAC_CSR_SW_CTRL_RCWE_MASK (0x1U) #define ENET_QOS_MAC_CSR_SW_CTRL_RCWE_SHIFT (0U) /*! RCWE - Register Clear on Write 1 Enable When this bit is set, the access mode of some register @@ -32618,6 +40096,7 @@ typedef struct { /*! @name MAC_FPE_CTRL_STS - Frame Preemption Control */ /*! @{ */ + #define ENET_QOS_MAC_FPE_CTRL_STS_EFPE_MASK (0x1U) #define ENET_QOS_MAC_FPE_CTRL_STS_EFPE_SHIFT (0U) /*! EFPE - Enable Tx Frame Preemption When set Frame Preemption Tx functionality is enabled. @@ -32625,6 +40104,7 @@ typedef struct { * 0b1..Tx Frame Preemption is enabled */ #define ENET_QOS_MAC_FPE_CTRL_STS_EFPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_EFPE_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_EFPE_MASK) + #define ENET_QOS_MAC_FPE_CTRL_STS_SVER_MASK (0x2U) #define ENET_QOS_MAC_FPE_CTRL_STS_SVER_SHIFT (1U) /*! SVER - Send Verify mPacket When set indicates hardware to send a verify mPacket. @@ -32632,6 +40112,7 @@ typedef struct { * 0b1..Send Verify mPacket is enabled */ #define ENET_QOS_MAC_FPE_CTRL_STS_SVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_SVER_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_SVER_MASK) + #define ENET_QOS_MAC_FPE_CTRL_STS_SRSP_MASK (0x4U) #define ENET_QOS_MAC_FPE_CTRL_STS_SRSP_SHIFT (2U) /*! SRSP - Send Respond mPacket When set indicates hardware to send a Respond mPacket. @@ -32639,11 +40120,13 @@ typedef struct { * 0b1..Send Respond mPacket is enabled */ #define ENET_QOS_MAC_FPE_CTRL_STS_SRSP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_SRSP_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_SRSP_MASK) + #define ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_MASK (0x8U) #define ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_SHIFT (3U) /*! S1_SET_0 - Synopsys Reserved, Must be set to "0". */ #define ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_MASK) + #define ENET_QOS_MAC_FPE_CTRL_STS_RVER_MASK (0x10000U) #define ENET_QOS_MAC_FPE_CTRL_STS_RVER_SHIFT (16U) /*! RVER - Received Verify Frame Set when a Verify mPacket is received. @@ -32651,6 +40134,7 @@ typedef struct { * 0b0..Not received Verify Frame */ #define ENET_QOS_MAC_FPE_CTRL_STS_RVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_RVER_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_RVER_MASK) + #define ENET_QOS_MAC_FPE_CTRL_STS_RRSP_MASK (0x20000U) #define ENET_QOS_MAC_FPE_CTRL_STS_RRSP_SHIFT (17U) /*! RRSP - Received Respond Frame Set when a Respond mPacket is received. @@ -32658,6 +40142,7 @@ typedef struct { * 0b0..Not received Respond Frame */ #define ENET_QOS_MAC_FPE_CTRL_STS_RRSP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_RRSP_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_RRSP_MASK) + #define ENET_QOS_MAC_FPE_CTRL_STS_TVER_MASK (0x40000U) #define ENET_QOS_MAC_FPE_CTRL_STS_TVER_SHIFT (18U) /*! TVER - Transmitted Verify Frame Set when a Verify mPacket is transmitted (triggered by setting SVER field). @@ -32665,6 +40150,7 @@ typedef struct { * 0b0..Not transmitted Verify Frame */ #define ENET_QOS_MAC_FPE_CTRL_STS_TVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_TVER_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_TVER_MASK) + #define ENET_QOS_MAC_FPE_CTRL_STS_TRSP_MASK (0x80000U) #define ENET_QOS_MAC_FPE_CTRL_STS_TRSP_SHIFT (19U) /*! TRSP - Transmitted Respond Frame Set when a Respond mPacket is transmitted (triggered by setting SRSP field). @@ -32676,6 +40162,7 @@ typedef struct { /*! @name MAC_PRESN_TIME_NS - 32-bit Binary Rollover Equivalent Time */ /*! @{ */ + #define ENET_QOS_MAC_PRESN_TIME_NS_MPTN_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_PRESN_TIME_NS_MPTN_SHIFT (0U) /*! MPTN - MAC 1722 Presentation Time in ns These bits indicate the value of the 32-bit binary @@ -32686,6 +40173,7 @@ typedef struct { /*! @name MAC_PRESN_TIME_UPDT - MAC 1722 Presentation Time */ /*! @{ */ + #define ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_SHIFT (0U) /*! MPTU - MAC 1722 Presentation Time Update This field holds the init value or the update value for the presentation time. @@ -32695,11 +40183,13 @@ typedef struct { /*! @name HIGH - MAC Address0 High..MAC Address63 High */ /*! @{ */ + #define ENET_QOS_HIGH_ADDRHI_MASK (0xFFFFU) #define ENET_QOS_HIGH_ADDRHI_SHIFT (0U) /*! ADDRHI - MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address. */ #define ENET_QOS_HIGH_ADDRHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_ADDRHI_SHIFT)) & ENET_QOS_HIGH_ADDRHI_MASK) + #define ENET_QOS_HIGH_DCS_MASK (0x1F0000U) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ #define ENET_QOS_HIGH_DCS_SHIFT (16U) /*! DCS - DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field @@ -32707,11 +40197,13 @@ typedef struct { * matches the MAC Address(#i) content is routed. */ #define ENET_QOS_HIGH_DCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_DCS_SHIFT)) & ENET_QOS_HIGH_DCS_MASK) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */ + #define ENET_QOS_HIGH_MBC_MASK (0x3F000000U) #define ENET_QOS_HIGH_MBC_SHIFT (24U) /*! MBC - Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. */ #define ENET_QOS_HIGH_MBC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_MBC_SHIFT)) & ENET_QOS_HIGH_MBC_MASK) + #define ENET_QOS_HIGH_SA_MASK (0x40000000U) #define ENET_QOS_HIGH_SA_SHIFT (30U) /*! SA - Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA @@ -32720,6 +40212,7 @@ typedef struct { * 0b1..Compare with Source Address */ #define ENET_QOS_HIGH_SA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_SA_SHIFT)) & ENET_QOS_HIGH_SA_MASK) + #define ENET_QOS_HIGH_AE_MASK (0x80000000U) #define ENET_QOS_HIGH_AE_SHIFT (31U) /*! AE - Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering. @@ -32734,6 +40227,7 @@ typedef struct { /*! @name LOW - MAC Address0 Low..MAC Address63 Low */ /*! @{ */ + #define ENET_QOS_LOW_ADDRLO_MASK (0xFFFFFFFFU) #define ENET_QOS_LOW_ADDRLO_SHIFT (0U) /*! ADDRLO - MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. @@ -32746,6 +40240,7 @@ typedef struct { /*! @name MAC_MMC_CONTROL - MMC Control */ /*! @{ */ + #define ENET_QOS_MAC_MMC_CONTROL_CNTRST_MASK (0x1U) #define ENET_QOS_MAC_MMC_CONTROL_CNTRST_SHIFT (0U) /*! CNTRST - Counters Reset When this bit is set, all counters are reset. @@ -32753,6 +40248,7 @@ typedef struct { * 0b1..All counters are reset */ #define ENET_QOS_MAC_MMC_CONTROL_CNTRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTRST_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTRST_MASK) + #define ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_MASK (0x2U) #define ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_SHIFT (1U) /*! CNTSTOPRO - Counter Stop Rollover When this bit is set, the counter does not roll over to zero after reaching the maximum value. @@ -32760,6 +40256,7 @@ typedef struct { * 0b1..Counter Stop Rollover is enabled */ #define ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_MASK) + #define ENET_QOS_MAC_MMC_CONTROL_RSTONRD_MASK (0x4U) #define ENET_QOS_MAC_MMC_CONTROL_RSTONRD_SHIFT (2U) /*! RSTONRD - Reset on Read When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset). @@ -32767,6 +40264,7 @@ typedef struct { * 0b1..Reset on Read is enabled */ #define ENET_QOS_MAC_MMC_CONTROL_RSTONRD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_RSTONRD_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_RSTONRD_MASK) + #define ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_MASK (0x8U) #define ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_SHIFT (3U) /*! CNTFREEZ - MMC Counter Freeze When this bit is set, it freezes all MMC counters to their current value. @@ -32774,6 +40272,7 @@ typedef struct { * 0b1..MMC Counter Freeze is enabled */ #define ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_MASK) + #define ENET_QOS_MAC_MMC_CONTROL_CNTPRST_MASK (0x10U) #define ENET_QOS_MAC_MMC_CONTROL_CNTPRST_SHIFT (4U) /*! CNTPRST - Counters Preset When this bit is set, all counters are initialized or preset to almost @@ -32782,6 +40281,7 @@ typedef struct { * 0b1..Counters Preset is enabled */ #define ENET_QOS_MAC_MMC_CONTROL_CNTPRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTPRST_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTPRST_MASK) + #define ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_MASK (0x20U) #define ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_SHIFT (5U) /*! CNTPRSTLVL - Full-Half Preset When this bit is low and the CNTPRST bit is set, all MMC counters get preset to almost-half value. @@ -32789,6 +40289,7 @@ typedef struct { * 0b1..Full-Half Preset is enabled */ #define ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_MASK) + #define ENET_QOS_MAC_MMC_CONTROL_UCDBC_MASK (0x100U) #define ENET_QOS_MAC_MMC_CONTROL_UCDBC_SHIFT (8U) /*! UCDBC - Update MMC Counters for Dropped Broadcast Packets Note: The CNTRST bit has a higher priority than the CNTPRST bit. @@ -32800,6 +40301,7 @@ typedef struct { /*! @name MAC_MMC_RX_INTERRUPT - MMC Rx Interrupt */ /*! @{ */ + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_MASK (0x1U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_SHIFT (0U) /*! RXGBPKTIS - MMC Receive Good Bad Packet Counter Interrupt Status This bit is set when the @@ -32808,6 +40310,7 @@ typedef struct { * 0b0..MMC Receive Good Bad Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_MASK (0x2U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_SHIFT (1U) /*! RXGBOCTIS - MMC Receive Good Bad Octet Counter Interrupt Status This bit is set when the @@ -32816,6 +40319,7 @@ typedef struct { * 0b0..MMC Receive Good Bad Octet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_MASK (0x4U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_SHIFT (2U) /*! RXGOCTIS - MMC Receive Good Octet Counter Interrupt Status This bit is set when the @@ -32824,6 +40328,7 @@ typedef struct { * 0b0..MMC Receive Good Octet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_MASK (0x8U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_SHIFT (3U) /*! RXBCGPIS - MMC Receive Broadcast Good Packet Counter Interrupt Status This bit is set when the @@ -32832,6 +40337,7 @@ typedef struct { * 0b0..MMC Receive Broadcast Good Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_MASK (0x10U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_SHIFT (4U) /*! RXMCGPIS - MMC Receive Multicast Good Packet Counter Interrupt Status This bit is set when the @@ -32840,6 +40346,7 @@ typedef struct { * 0b0..MMC Receive Multicast Good Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_MASK (0x20U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_SHIFT (5U) /*! RXCRCERPIS - MMC Receive CRC Error Packet Counter Interrupt Status This bit is set when the @@ -32848,6 +40355,7 @@ typedef struct { * 0b0..MMC Receive CRC Error Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_MASK (0x40U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_SHIFT (6U) /*! RXALGNERPIS - MMC Receive Alignment Error Packet Counter Interrupt Status This bit is set when @@ -32856,6 +40364,7 @@ typedef struct { * 0b0..MMC Receive Alignment Error Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_MASK (0x80U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_SHIFT (7U) /*! RXRUNTPIS - MMC Receive Runt Packet Counter Interrupt Status This bit is set when the @@ -32864,6 +40373,7 @@ typedef struct { * 0b0..MMC Receive Runt Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_MASK (0x100U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_SHIFT (8U) /*! RXJABERPIS - MMC Receive Jabber Error Packet Counter Interrupt Status This bit is set when the @@ -32872,6 +40382,7 @@ typedef struct { * 0b0..MMC Receive Jabber Error Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_MASK (0x200U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_SHIFT (9U) /*! RXUSIZEGPIS - MMC Receive Undersize Good Packet Counter Interrupt Status This bit is set when @@ -32880,6 +40391,7 @@ typedef struct { * 0b0..MMC Receive Undersize Good Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_MASK (0x400U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_SHIFT (10U) /*! RXOSIZEGPIS - MMC Receive Oversize Good Packet Counter Interrupt Status This bit is set when the @@ -32888,6 +40400,7 @@ typedef struct { * 0b0..MMC Receive Oversize Good Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_MASK (0x800U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_SHIFT (11U) /*! RX64OCTGBPIS - MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status This bit is set @@ -32896,6 +40409,7 @@ typedef struct { * 0b0..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_MASK (0x1000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_SHIFT (12U) /*! RX65T127OCTGBPIS - MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit @@ -32905,6 +40419,7 @@ typedef struct { * 0b0..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_MASK (0x2000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_SHIFT (13U) /*! RX128T255OCTGBPIS - MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status This @@ -32914,6 +40429,7 @@ typedef struct { * 0b0..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_MASK (0x4000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_SHIFT (14U) /*! RX256T511OCTGBPIS - MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status This @@ -32923,6 +40439,7 @@ typedef struct { * 0b0..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_MASK (0x8000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_SHIFT (15U) /*! RX512T1023OCTGBPIS - MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This @@ -32932,6 +40449,7 @@ typedef struct { * 0b0..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_MASK (0x10000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_SHIFT (16U) /*! RX1024TMAXOCTGBPIS - MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status @@ -32941,6 +40459,7 @@ typedef struct { * 0b0..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_MASK (0x20000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_SHIFT (17U) /*! RXUCGPIS - MMC Receive Unicast Good Packet Counter Interrupt Status This bit is set when the @@ -32949,6 +40468,7 @@ typedef struct { * 0b0..MMC Receive Unicast Good Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_MASK (0x40000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_SHIFT (18U) /*! RXLENERPIS - MMC Receive Length Error Packet Counter Interrupt Status This bit is set when the @@ -32957,6 +40477,7 @@ typedef struct { * 0b0..MMC Receive Length Error Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_MASK (0x80000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_SHIFT (19U) /*! RXORANGEPIS - MMC Receive Out Of Range Error Packet Counter Interrupt Status. @@ -32964,6 +40485,7 @@ typedef struct { * 0b0..MMC Receive Out Of Range Error Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_MASK (0x100000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_SHIFT (20U) /*! RXPAUSPIS - MMC Receive Pause Packet Counter Interrupt Status This bit is set when the @@ -32972,6 +40494,7 @@ typedef struct { * 0b0..MMC Receive Pause Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_MASK (0x200000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_SHIFT (21U) /*! RXFOVPIS - MMC Receive FIFO Overflow Packet Counter Interrupt Status This bit is set when the @@ -32980,6 +40503,7 @@ typedef struct { * 0b0..MMC Receive FIFO Overflow Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_MASK (0x400000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_SHIFT (22U) /*! RXVLANGBPIS - MMC Receive VLAN Good Bad Packet Counter Interrupt Status This bit is set when the @@ -32988,6 +40512,7 @@ typedef struct { * 0b0..MMC Receive VLAN Good Bad Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_MASK (0x800000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_SHIFT (23U) /*! RXWDOGPIS - MMC Receive Watchdog Error Packet Counter Interrupt Status This bit is set when the @@ -32996,6 +40521,7 @@ typedef struct { * 0b0..MMC Receive Watchdog Error Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_MASK (0x1000000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_SHIFT (24U) /*! RXRCVERRPIS - MMC Receive Error Packet Counter Interrupt Status This bit is set when the @@ -33004,6 +40530,7 @@ typedef struct { * 0b0..MMC Receive Error Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_MASK (0x2000000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_SHIFT (25U) /*! RXCTRLPIS - MMC Receive Control Packet Counter Interrupt Status This bit is set when the @@ -33012,6 +40539,7 @@ typedef struct { * 0b0..MMC Receive Control Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_MASK (0x4000000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_SHIFT (26U) /*! RXLPIUSCIS - MMC Receive LPI microsecond counter interrupt status This bit is set when the @@ -33020,6 +40548,7 @@ typedef struct { * 0b0..MMC Receive LPI microsecond Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_MASK (0x8000000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_SHIFT (27U) /*! RXLPITRCIS - MMC Receive LPI transition counter interrupt status This bit is set when the @@ -33032,6 +40561,7 @@ typedef struct { /*! @name MAC_MMC_TX_INTERRUPT - MMC Tx Interrupt */ /*! @{ */ + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_MASK (0x1U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_SHIFT (0U) /*! TXGBOCTIS - MMC Transmit Good Bad Octet Counter Interrupt Status This bit is set when the @@ -33040,6 +40570,7 @@ typedef struct { * 0b0..MMC Transmit Good Bad Octet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_MASK (0x2U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_SHIFT (1U) /*! TXGBPKTIS - MMC Transmit Good Bad Packet Counter Interrupt Status This bit is set when the @@ -33048,6 +40579,7 @@ typedef struct { * 0b0..MMC Transmit Good Bad Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_MASK (0x4U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_SHIFT (2U) /*! TXBCGPIS - MMC Transmit Broadcast Good Packet Counter Interrupt Status This bit is set when the @@ -33056,6 +40588,7 @@ typedef struct { * 0b0..MMC Transmit Broadcast Good Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_MASK (0x8U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_SHIFT (3U) /*! TXMCGPIS - MMC Transmit Multicast Good Packet Counter Interrupt Status This bit is set when the @@ -33064,6 +40597,7 @@ typedef struct { * 0b0..MMC Transmit Multicast Good Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_MASK (0x10U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_SHIFT (4U) /*! TX64OCTGBPIS - MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status This bit is set @@ -33072,6 +40606,7 @@ typedef struct { * 0b0..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_MASK (0x20U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_SHIFT (5U) /*! TX65T127OCTGBPIS - MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status This @@ -33081,6 +40616,7 @@ typedef struct { * 0b0..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_MASK (0x40U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_SHIFT (6U) /*! TX128T255OCTGBPIS - MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status This @@ -33090,6 +40626,7 @@ typedef struct { * 0b0..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_MASK (0x80U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_SHIFT (7U) /*! TX256T511OCTGBPIS - MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status This @@ -33099,6 +40636,7 @@ typedef struct { * 0b0..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_MASK (0x100U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_SHIFT (8U) /*! TX512T1023OCTGBPIS - MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status @@ -33108,6 +40646,7 @@ typedef struct { * 0b0..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_MASK (0x200U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_SHIFT (9U) /*! TX1024TMAXOCTGBPIS - MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status @@ -33117,6 +40656,7 @@ typedef struct { * 0b0..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_MASK (0x400U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_SHIFT (10U) /*! TXUCGBPIS - MMC Transmit Unicast Good Bad Packet Counter Interrupt Status This bit is set when @@ -33125,6 +40665,7 @@ typedef struct { * 0b0..MMC Transmit Unicast Good Bad Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_MASK (0x800U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_SHIFT (11U) /*! TXMCGBPIS - MMC Transmit Multicast Good Bad Packet Counter Interrupt Status The bit is set when @@ -33133,6 +40674,7 @@ typedef struct { * 0b0..MMC Transmit Multicast Good Bad Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_MASK (0x1000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_SHIFT (12U) /*! TXBCGBPIS - MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status This bit is set when @@ -33141,6 +40683,7 @@ typedef struct { * 0b0..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_MASK (0x2000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_SHIFT (13U) /*! TXUFLOWERPIS - MMC Transmit Underflow Error Packet Counter Interrupt Status This bit is set when @@ -33149,6 +40692,7 @@ typedef struct { * 0b0..MMC Transmit Underflow Error Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_MASK (0x4000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_SHIFT (14U) /*! TXSCOLGPIS - MMC Transmit Single Collision Good Packet Counter Interrupt Status This bit is set @@ -33157,6 +40701,7 @@ typedef struct { * 0b0..MMC Transmit Single Collision Good Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_MASK (0x8000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_SHIFT (15U) /*! TXMCOLGPIS - MMC Transmit Multiple Collision Good Packet Counter Interrupt Status This bit is @@ -33165,6 +40710,7 @@ typedef struct { * 0b0..MMC Transmit Multiple Collision Good Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_MASK (0x10000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_SHIFT (16U) /*! TXDEFPIS - MMC Transmit Deferred Packet Counter Interrupt Status This bit is set when the @@ -33173,6 +40719,7 @@ typedef struct { * 0b0..MMC Transmit Deferred Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_MASK (0x20000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_SHIFT (17U) /*! TXLATCOLPIS - MMC Transmit Late Collision Packet Counter Interrupt Status This bit is set when @@ -33181,6 +40728,7 @@ typedef struct { * 0b0..MMC Transmit Late Collision Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_MASK (0x40000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_SHIFT (18U) /*! TXEXCOLPIS - MMC Transmit Excessive Collision Packet Counter Interrupt Status This bit is set @@ -33189,6 +40737,7 @@ typedef struct { * 0b0..MMC Transmit Excessive Collision Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_MASK (0x80000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_SHIFT (19U) /*! TXCARERPIS - MMC Transmit Carrier Error Packet Counter Interrupt Status This bit is set when the @@ -33197,6 +40746,7 @@ typedef struct { * 0b0..MMC Transmit Carrier Error Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_MASK (0x100000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_SHIFT (20U) /*! TXGOCTIS - MMC Transmit Good Octet Counter Interrupt Status This bit is set when the @@ -33205,6 +40755,7 @@ typedef struct { * 0b0..MMC Transmit Good Octet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_MASK (0x200000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_SHIFT (21U) /*! TXGPKTIS - MMC Transmit Good Packet Counter Interrupt Status This bit is set when the @@ -33213,6 +40764,7 @@ typedef struct { * 0b0..MMC Transmit Good Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_MASK (0x400000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_SHIFT (22U) /*! TXEXDEFPIS - MMC Transmit Excessive Deferral Packet Counter Interrupt Status This bit is set @@ -33221,6 +40773,7 @@ typedef struct { * 0b0..MMC Transmit Excessive Deferral Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_MASK (0x800000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_SHIFT (23U) /*! TXPAUSPIS - MMC Transmit Pause Packet Counter Interrupt Status This bit is set when the @@ -33229,6 +40782,7 @@ typedef struct { * 0b0..MMC Transmit Pause Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_MASK (0x1000000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_SHIFT (24U) /*! TXVLANGPIS - MMC Transmit VLAN Good Packet Counter Interrupt Status This bit is set when the @@ -33237,6 +40791,7 @@ typedef struct { * 0b0..MMC Transmit VLAN Good Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_MASK (0x2000000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_SHIFT (25U) /*! TXOSIZEGPIS - MMC Transmit Oversize Good Packet Counter Interrupt Status This bit is set when @@ -33245,6 +40800,7 @@ typedef struct { * 0b0..MMC Transmit Oversize Good Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_MASK (0x4000000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_SHIFT (26U) /*! TXLPIUSCIS - MMC Transmit LPI microsecond counter interrupt status This bit is set when the @@ -33253,6 +40809,7 @@ typedef struct { * 0b0..MMC Transmit LPI microsecond Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_MASK (0x8000000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_SHIFT (27U) /*! TXLPITRCIS - MMC Transmit LPI transition counter interrupt status This bit is set when the @@ -33265,6 +40822,7 @@ typedef struct { /*! @name MAC_MMC_RX_INTERRUPT_MASK - MMC Rx Interrupt Mask */ /*! @{ */ + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_MASK (0x1U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_SHIFT (0U) /*! RXGBPKTIM - MMC Receive Good Bad Packet Counter Interrupt Mask Setting this bit masks the @@ -33273,6 +40831,7 @@ typedef struct { * 0b1..MMC Receive Good Bad Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_MASK (0x2U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_SHIFT (1U) /*! RXGBOCTIM - MMC Receive Good Bad Octet Counter Interrupt Mask Setting this bit masks the @@ -33281,6 +40840,7 @@ typedef struct { * 0b1..MMC Receive Good Bad Octet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_MASK (0x4U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_SHIFT (2U) /*! RXGOCTIM - MMC Receive Good Octet Counter Interrupt Mask Setting this bit masks the interrupt @@ -33289,6 +40849,7 @@ typedef struct { * 0b1..MMC Receive Good Octet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_MASK (0x8U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_SHIFT (3U) /*! RXBCGPIM - MMC Receive Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the @@ -33298,6 +40859,7 @@ typedef struct { * 0b1..MMC Receive Broadcast Good Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_MASK (0x10U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_SHIFT (4U) /*! RXMCGPIM - MMC Receive Multicast Good Packet Counter Interrupt Mask Setting this bit masks the @@ -33307,6 +40869,7 @@ typedef struct { * 0b1..MMC Receive Multicast Good Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_MASK (0x20U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_SHIFT (5U) /*! RXCRCERPIM - MMC Receive CRC Error Packet Counter Interrupt Mask Setting this bit masks the @@ -33315,6 +40878,7 @@ typedef struct { * 0b1..MMC Receive CRC Error Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_MASK (0x40U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_SHIFT (6U) /*! RXALGNERPIM - MMC Receive Alignment Error Packet Counter Interrupt Mask Setting this bit masks @@ -33324,6 +40888,7 @@ typedef struct { * 0b1..MMC Receive Alignment Error Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_MASK (0x80U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_SHIFT (7U) /*! RXRUNTPIM - MMC Receive Runt Packet Counter Interrupt Mask Setting this bit masks the interrupt @@ -33332,6 +40897,7 @@ typedef struct { * 0b1..MMC Receive Runt Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_MASK (0x100U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_SHIFT (8U) /*! RXJABERPIM - MMC Receive Jabber Error Packet Counter Interrupt Mask Setting this bit masks the @@ -33340,6 +40906,7 @@ typedef struct { * 0b1..MMC Receive Jabber Error Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_MASK (0x200U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_SHIFT (9U) /*! RXUSIZEGPIM - MMC Receive Undersize Good Packet Counter Interrupt Mask Setting this bit masks @@ -33349,6 +40916,7 @@ typedef struct { * 0b1..MMC Receive Undersize Good Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_MASK (0x400U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_SHIFT (10U) /*! RXOSIZEGPIM - MMC Receive Oversize Good Packet Counter Interrupt Mask Setting this bit masks the @@ -33358,6 +40926,7 @@ typedef struct { * 0b1..MMC Receive Oversize Good Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_MASK (0x800U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_SHIFT (11U) /*! RX64OCTGBPIM - MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit @@ -33367,6 +40936,7 @@ typedef struct { * 0b1..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_MASK (0x1000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_SHIFT (12U) /*! RX65T127OCTGBPIM - MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting @@ -33376,6 +40946,7 @@ typedef struct { * 0b1..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_MASK (0x2000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_SHIFT (13U) /*! RX128T255OCTGBPIM - MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting @@ -33385,6 +40956,7 @@ typedef struct { * 0b1..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_MASK (0x4000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_SHIFT (14U) /*! RX256T511OCTGBPIM - MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting @@ -33394,6 +40966,7 @@ typedef struct { * 0b1..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_MASK (0x8000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_SHIFT (15U) /*! RX512T1023OCTGBPIM - MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask @@ -33403,6 +40976,7 @@ typedef struct { * 0b1..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_MASK (0x10000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_SHIFT (16U) /*! RX1024TMAXOCTGBPIM - MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask. @@ -33410,6 +40984,7 @@ typedef struct { * 0b1..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_MASK (0x20000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_SHIFT (17U) /*! RXUCGPIM - MMC Receive Unicast Good Packet Counter Interrupt Mask Setting this bit masks the @@ -33419,6 +40994,7 @@ typedef struct { * 0b1..MMC Receive Unicast Good Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_MASK (0x40000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_SHIFT (18U) /*! RXLENERPIM - MMC Receive Length Error Packet Counter Interrupt Mask Setting this bit masks the @@ -33427,6 +41003,7 @@ typedef struct { * 0b1..MMC Receive Length Error Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_MASK (0x80000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_SHIFT (19U) /*! RXORANGEPIM - MMC Receive Out Of Range Error Packet Counter Interrupt Mask Setting this bit @@ -33436,6 +41013,7 @@ typedef struct { * 0b1..MMC Receive Out Of Range Error Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_MASK (0x100000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_SHIFT (20U) /*! RXPAUSPIM - MMC Receive Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt @@ -33444,6 +41022,7 @@ typedef struct { * 0b1..MMC Receive Pause Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_MASK (0x200000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_SHIFT (21U) /*! RXFOVPIM - MMC Receive FIFO Overflow Packet Counter Interrupt Mask Setting this bit masks the @@ -33452,6 +41031,7 @@ typedef struct { * 0b1..MMC Receive FIFO Overflow Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_MASK (0x400000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_SHIFT (22U) /*! RXVLANGBPIM - MMC Receive VLAN Good Bad Packet Counter Interrupt Mask Setting this bit masks the @@ -33461,6 +41041,7 @@ typedef struct { * 0b1..MMC Receive VLAN Good Bad Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_MASK (0x800000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_SHIFT (23U) /*! RXWDOGPIM - MMC Receive Watchdog Error Packet Counter Interrupt Mask Setting this bit masks the @@ -33469,6 +41050,7 @@ typedef struct { * 0b1..MMC Receive Watchdog Error Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_MASK (0x1000000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_SHIFT (24U) /*! RXRCVERRPIM - MMC Receive Error Packet Counter Interrupt Mask Setting this bit masks the @@ -33477,6 +41059,7 @@ typedef struct { * 0b1..MMC Receive Error Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_MASK (0x2000000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_SHIFT (25U) /*! RXCTRLPIM - MMC Receive Control Packet Counter Interrupt Mask Setting this bit masks the @@ -33485,6 +41068,7 @@ typedef struct { * 0b1..MMC Receive Control Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_MASK (0x4000000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_SHIFT (26U) /*! RXLPIUSCIM - MMC Receive LPI microsecond counter interrupt Mask Setting this bit masks the @@ -33493,6 +41077,7 @@ typedef struct { * 0b1..MMC Receive LPI microsecond counter interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_MASK) + #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_MASK (0x8000000U) #define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_SHIFT (27U) /*! RXLPITRCIM - MMC Receive LPI transition counter interrupt Mask Setting this bit masks the @@ -33505,6 +41090,7 @@ typedef struct { /*! @name MAC_MMC_TX_INTERRUPT_MASK - MMC Tx Interrupt Mask */ /*! @{ */ + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_MASK (0x1U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_SHIFT (0U) /*! TXGBOCTIM - MMC Transmit Good Bad Octet Counter Interrupt Mask Setting this bit masks the @@ -33513,6 +41099,7 @@ typedef struct { * 0b1..MMC Transmit Good Bad Octet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_MASK (0x2U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_SHIFT (1U) /*! TXGBPKTIM - MMC Transmit Good Bad Packet Counter Interrupt Mask Setting this bit masks the @@ -33521,6 +41108,7 @@ typedef struct { * 0b1..MMC Transmit Good Bad Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_MASK (0x4U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_SHIFT (2U) /*! TXBCGPIM - MMC Transmit Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the @@ -33530,6 +41118,7 @@ typedef struct { * 0b1..MMC Transmit Broadcast Good Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_MASK (0x8U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_SHIFT (3U) /*! TXMCGPIM - MMC Transmit Multicast Good Packet Counter Interrupt Mask Setting this bit masks the @@ -33539,6 +41128,7 @@ typedef struct { * 0b1..MMC Transmit Multicast Good Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_MASK (0x10U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_SHIFT (4U) /*! TX64OCTGBPIM - MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit @@ -33548,6 +41138,7 @@ typedef struct { * 0b1..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_MASK (0x20U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_SHIFT (5U) /*! TX65T127OCTGBPIM - MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting @@ -33557,6 +41148,7 @@ typedef struct { * 0b1..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_MASK (0x40U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_SHIFT (6U) /*! TX128T255OCTGBPIM - MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting @@ -33566,6 +41158,7 @@ typedef struct { * 0b1..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_MASK (0x80U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_SHIFT (7U) /*! TX256T511OCTGBPIM - MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting @@ -33575,6 +41168,7 @@ typedef struct { * 0b1..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_MASK (0x100U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_SHIFT (8U) /*! TX512T1023OCTGBPIM - MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask @@ -33584,6 +41178,7 @@ typedef struct { * 0b1..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_MASK (0x200U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_SHIFT (9U) /*! TX1024TMAXOCTGBPIM - MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask @@ -33593,6 +41188,7 @@ typedef struct { * 0b1..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_MASK (0x400U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_SHIFT (10U) /*! TXUCGBPIM - MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask Setting this bit masks @@ -33602,6 +41198,7 @@ typedef struct { * 0b1..MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_MASK (0x800U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_SHIFT (11U) /*! TXMCGBPIM - MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask Setting this bit masks @@ -33611,6 +41208,7 @@ typedef struct { * 0b1..MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_MASK (0x1000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_SHIFT (12U) /*! TXBCGBPIM - MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask Setting this bit masks @@ -33620,6 +41218,7 @@ typedef struct { * 0b1..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_MASK (0x2000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_SHIFT (13U) /*! TXUFLOWERPIM - MMC Transmit Underflow Error Packet Counter Interrupt Mask Setting this bit masks @@ -33629,6 +41228,7 @@ typedef struct { * 0b1..MMC Transmit Underflow Error Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_MASK (0x4000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_SHIFT (14U) /*! TXSCOLGPIM - MMC Transmit Single Collision Good Packet Counter Interrupt Mask Setting this bit @@ -33638,6 +41238,7 @@ typedef struct { * 0b1..MMC Transmit Single Collision Good Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_MASK (0x8000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_SHIFT (15U) /*! TXMCOLGPIM - MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask Setting this bit @@ -33647,6 +41248,7 @@ typedef struct { * 0b1..MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_MASK (0x10000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_SHIFT (16U) /*! TXDEFPIM - MMC Transmit Deferred Packet Counter Interrupt Mask Setting this bit masks the @@ -33655,6 +41257,7 @@ typedef struct { * 0b1..MMC Transmit Deferred Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_MASK (0x20000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_SHIFT (17U) /*! TXLATCOLPIM - MMC Transmit Late Collision Packet Counter Interrupt Mask Setting this bit masks @@ -33663,6 +41266,7 @@ typedef struct { * 0b1..MMC Transmit Late Collision Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_MASK (0x40000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_SHIFT (18U) /*! TXEXCOLPIM - MMC Transmit Excessive Collision Packet Counter Interrupt Mask Setting this bit @@ -33672,6 +41276,7 @@ typedef struct { * 0b1..MMC Transmit Excessive Collision Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_MASK (0x80000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_SHIFT (19U) /*! TXCARERPIM - MMC Transmit Carrier Error Packet Counter Interrupt Mask Setting this bit masks the @@ -33681,6 +41286,7 @@ typedef struct { * 0b1..MMC Transmit Carrier Error Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_MASK (0x100000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_SHIFT (20U) /*! TXGOCTIM - MMC Transmit Good Octet Counter Interrupt Mask Setting this bit masks the interrupt @@ -33689,6 +41295,7 @@ typedef struct { * 0b1..MMC Transmit Good Octet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_MASK (0x200000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_SHIFT (21U) /*! TXGPKTIM - MMC Transmit Good Packet Counter Interrupt Mask Setting this bit masks the interrupt @@ -33697,6 +41304,7 @@ typedef struct { * 0b1..MMC Transmit Good Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_MASK (0x400000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_SHIFT (22U) /*! TXEXDEFPIM - MMC Transmit Excessive Deferral Packet Counter Interrupt Mask Setting this bit @@ -33706,6 +41314,7 @@ typedef struct { * 0b1..MMC Transmit Excessive Deferral Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_MASK (0x800000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_SHIFT (23U) /*! TXPAUSPIM - MMC Transmit Pause Packet Counter Interrupt Mask Setting this bit masks the @@ -33714,6 +41323,7 @@ typedef struct { * 0b1..MMC Transmit Pause Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_MASK (0x1000000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_SHIFT (24U) /*! TXVLANGPIM - MMC Transmit VLAN Good Packet Counter Interrupt Mask Setting this bit masks the @@ -33722,6 +41332,7 @@ typedef struct { * 0b1..MMC Transmit VLAN Good Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_MASK (0x2000000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_SHIFT (25U) /*! TXOSIZEGPIM - MMC Transmit Oversize Good Packet Counter Interrupt Mask Setting this bit masks @@ -33731,6 +41342,7 @@ typedef struct { * 0b1..MMC Transmit Oversize Good Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_MASK (0x4000000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_SHIFT (26U) /*! TXLPIUSCIM - MMC Transmit LPI microsecond counter interrupt Mask Setting this bit masks the @@ -33739,6 +41351,7 @@ typedef struct { * 0b1..MMC Transmit LPI microsecond counter interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_MASK) + #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_MASK (0x8000000U) #define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_SHIFT (27U) /*! TXLPITRCIM - MMC Transmit LPI transition counter interrupt Mask Setting this bit masks the @@ -33751,6 +41364,7 @@ typedef struct { /*! @name MAC_TX_OCTET_COUNT_GOOD_BAD - Tx Octet Count Good and Bad */ /*! @{ */ + #define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT (0U) /*! TXOCTGB - Tx Octet Count Good Bad This field indicates the number of bytes transmitted, @@ -33761,6 +41375,7 @@ typedef struct { /*! @name MAC_TX_PACKET_COUNT_GOOD_BAD - Tx Packet Count Good and Bad */ /*! @{ */ + #define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT (0U) /*! TXPKTGB - Tx Packet Count Good Bad This field indicates the number of good and bad packets @@ -33771,6 +41386,7 @@ typedef struct { /*! @name MAC_TX_BROADCAST_PACKETS_GOOD - Tx Broadcast Packets Good */ /*! @{ */ + #define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT (0U) /*! TXBCASTG - Tx Broadcast Packets Good This field indicates the number of good broadcast packets transmitted. @@ -33780,6 +41396,7 @@ typedef struct { /*! @name MAC_TX_MULTICAST_PACKETS_GOOD - Tx Multicast Packets Good */ /*! @{ */ + #define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT (0U) /*! TXMCASTG - Tx Multicast Packets Good This field indicates the number of good multicast packets transmitted. @@ -33789,6 +41406,7 @@ typedef struct { /*! @name MAC_TX_64OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 64-Byte Packets */ /*! @{ */ + #define ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT (0U) /*! TX64OCTGB - Tx 64Octets Packets Good_Bad This field indicates the number of good and bad packets @@ -33799,6 +41417,7 @@ typedef struct { /*! @name MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 65 to 127-Byte Packets */ /*! @{ */ + #define ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT (0U) /*! TX65_127OCTGB - Tx 65To127Octets Packets Good Bad This field indicates the number of good and @@ -33810,6 +41429,7 @@ typedef struct { /*! @name MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 128 to 255-Byte Packets */ /*! @{ */ + #define ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT (0U) /*! TX128_255OCTGB - Tx 128To255Octets Packets Good Bad This field indicates the number of good and @@ -33821,6 +41441,7 @@ typedef struct { /*! @name MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 256 to 511-Byte Packets */ /*! @{ */ + #define ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT (0U) /*! TX256_511OCTGB - Tx 256To511Octets Packets Good Bad This field indicates the number of good and @@ -33832,6 +41453,7 @@ typedef struct { /*! @name MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 512 to 1023-Byte Packets */ /*! @{ */ + #define ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT (0U) /*! TX512_1023OCTGB - Tx 512To1023Octets Packets Good Bad This field indicates the number of good @@ -33843,6 +41465,7 @@ typedef struct { /*! @name MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 1024 to Max-Byte Packets */ /*! @{ */ + #define ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT (0U) /*! TX1024_MAXOCTGB - Tx 1024ToMaxOctets Packets Good Bad This field indicates the number of good @@ -33854,6 +41477,7 @@ typedef struct { /*! @name MAC_TX_UNICAST_PACKETS_GOOD_BAD - Good and Bad Unicast Packets Transmitted */ /*! @{ */ + #define ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT (0U) /*! TXUCASTGB - Tx Unicast Packets Good Bad This field indicates the number of good and bad unicast packets transmitted. @@ -33863,6 +41487,7 @@ typedef struct { /*! @name MAC_TX_MULTICAST_PACKETS_GOOD_BAD - Good and Bad Multicast Packets Transmitted */ /*! @{ */ + #define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT (0U) /*! TXMCASTGB - Tx Multicast Packets Good Bad This field indicates the number of good and bad multicast packets transmitted. @@ -33872,6 +41497,7 @@ typedef struct { /*! @name MAC_TX_BROADCAST_PACKETS_GOOD_BAD - Good and Bad Broadcast Packets Transmitted */ /*! @{ */ + #define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT (0U) /*! TXBCASTGB - Tx Broadcast Packets Good Bad This field indicates the number of good and bad broadcast packets transmitted. @@ -33881,6 +41507,7 @@ typedef struct { /*! @name MAC_TX_UNDERFLOW_ERROR_PACKETS - Tx Packets Aborted By Underflow Error */ /*! @{ */ + #define ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT (0U) /*! TXUNDRFLW - Tx Underflow Error Packets This field indicates the number of packets aborted because of packets underflow error. @@ -33890,6 +41517,7 @@ typedef struct { /*! @name MAC_TX_SINGLE_COLLISION_GOOD_PACKETS - Single Collision Good Packets Transmitted */ /*! @{ */ + #define ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT (0U) /*! TXSNGLCOLG - Tx Single Collision Good Packets This field indicates the number of successfully @@ -33900,6 +41528,7 @@ typedef struct { /*! @name MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS - Multiple Collision Good Packets Transmitted */ /*! @{ */ + #define ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT (0U) /*! TXMULTCOLG - Tx Multiple Collision Good Packets This field indicates the number of successfully @@ -33910,6 +41539,7 @@ typedef struct { /*! @name MAC_TX_DEFERRED_PACKETS - Deferred Packets Transmitted */ /*! @{ */ + #define ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT (0U) /*! TXDEFRD - Tx Deferred Packets This field indicates the number of successfully transmitted after @@ -33920,6 +41550,7 @@ typedef struct { /*! @name MAC_TX_LATE_COLLISION_PACKETS - Late Collision Packets Transmitted */ /*! @{ */ + #define ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT (0U) /*! TXLATECOL - Tx Late Collision Packets This field indicates the number of packets aborted because of late collision error. @@ -33929,6 +41560,7 @@ typedef struct { /*! @name MAC_TX_EXCESSIVE_COLLISION_PACKETS - Excessive Collision Packets Transmitted */ /*! @{ */ + #define ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT (0U) /*! TXEXSCOL - Tx Excessive Collision Packets This field indicates the number of packets aborted @@ -33939,6 +41571,7 @@ typedef struct { /*! @name MAC_TX_CARRIER_ERROR_PACKETS - Carrier Error Packets Transmitted */ /*! @{ */ + #define ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT (0U) /*! TXCARR - Tx Carrier Error Packets This field indicates the number of packets aborted because of @@ -33949,6 +41582,7 @@ typedef struct { /*! @name MAC_TX_OCTET_COUNT_GOOD - Bytes Transmitted in Good Packets */ /*! @{ */ + #define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT (0U) /*! TXOCTG - Tx Octet Count Good This field indicates the number of bytes transmitted, exclusive of preamble, only in good packets. @@ -33958,6 +41592,7 @@ typedef struct { /*! @name MAC_TX_PACKET_COUNT_GOOD - Good Packets Transmitted */ /*! @{ */ + #define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT (0U) /*! TXPKTG - Tx Packet Count Good This field indicates the number of good packets transmitted. @@ -33967,6 +41602,7 @@ typedef struct { /*! @name MAC_TX_EXCESSIVE_DEFERRAL_ERROR - Packets Aborted By Excessive Deferral Error */ /*! @{ */ + #define ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT (0U) /*! TXEXSDEF - Tx Excessive Deferral Error This field indicates the number of packets aborted @@ -33977,6 +41613,7 @@ typedef struct { /*! @name MAC_TX_PAUSE_PACKETS - Pause Packets Transmitted */ /*! @{ */ + #define ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT (0U) /*! TXPAUSE - Tx Pause Packets This field indicates the number of good Pause packets transmitted. @@ -33986,6 +41623,7 @@ typedef struct { /*! @name MAC_TX_VLAN_PACKETS_GOOD - Good VLAN Packets Transmitted */ /*! @{ */ + #define ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT (0U) /*! TXVLANG - Tx VLAN Packets Good This field provides the number of good VLAN packets transmitted. @@ -33995,6 +41633,7 @@ typedef struct { /*! @name MAC_TX_OSIZE_PACKETS_GOOD - Good Oversize Packets Transmitted */ /*! @{ */ + #define ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT (0U) /*! TXOSIZG - Tx OSize Packets Good This field indicates the number of packets transmitted without @@ -34006,6 +41645,7 @@ typedef struct { /*! @name MAC_RX_PACKETS_COUNT_GOOD_BAD - Good and Bad Packets Received */ /*! @{ */ + #define ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT (0U) /*! RXPKTGB - Rx Packets Count Good Bad This field indicates the number of good and bad packets received. @@ -34015,6 +41655,7 @@ typedef struct { /*! @name MAC_RX_OCTET_COUNT_GOOD_BAD - Bytes in Good and Bad Packets Received */ /*! @{ */ + #define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT (0U) /*! RXOCTGB - Rx Octet Count Good Bad This field indicates the number of bytes received, exclusive @@ -34025,6 +41666,7 @@ typedef struct { /*! @name MAC_RX_OCTET_COUNT_GOOD - Bytes in Good Packets Received */ /*! @{ */ + #define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT (0U) /*! RXOCTG - Rx Octet Count Good This field indicates the number of bytes received, exclusive of preamble, only in good packets. @@ -34034,6 +41676,7 @@ typedef struct { /*! @name MAC_RX_BROADCAST_PACKETS_GOOD - Good Broadcast Packets Received */ /*! @{ */ + #define ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT (0U) /*! RXBCASTG - Rx Broadcast Packets Good This field indicates the number of good broadcast packets received. @@ -34043,6 +41686,7 @@ typedef struct { /*! @name MAC_RX_MULTICAST_PACKETS_GOOD - Good Multicast Packets Received */ /*! @{ */ + #define ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT (0U) /*! RXMCASTG - Rx Multicast Packets Good This field indicates the number of good multicast packets received. @@ -34052,6 +41696,7 @@ typedef struct { /*! @name MAC_RX_CRC_ERROR_PACKETS - CRC Error Packets Received */ /*! @{ */ + #define ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT (0U) /*! RXCRCERR - Rx CRC Error Packets This field indicates the number of packets received with CRC error. @@ -34061,6 +41706,7 @@ typedef struct { /*! @name MAC_RX_ALIGNMENT_ERROR_PACKETS - Alignment Error Packets Received */ /*! @{ */ + #define ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT (0U) /*! RXALGNERR - Rx Alignment Error Packets This field indicates the number of packets received with alignment (dribble) error. @@ -34070,6 +41716,7 @@ typedef struct { /*! @name MAC_RX_RUNT_ERROR_PACKETS - Runt Error Packets Received */ /*! @{ */ + #define ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT (0U) /*! RXRUNTERR - Rx Runt Error Packets This field indicates the number of packets received with runt @@ -34080,6 +41727,7 @@ typedef struct { /*! @name MAC_RX_JABBER_ERROR_PACKETS - Jabber Error Packets Received */ /*! @{ */ + #define ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT (0U) /*! RXJABERR - Rx Jabber Error Packets This field indicates the number of giant packets received @@ -34091,6 +41739,7 @@ typedef struct { /*! @name MAC_RX_UNDERSIZE_PACKETS_GOOD - Good Undersize Packets Received */ /*! @{ */ + #define ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT (0U) /*! RXUNDERSZG - Rx Undersize Packets Good This field indicates the number of packets received with @@ -34101,6 +41750,7 @@ typedef struct { /*! @name MAC_RX_OVERSIZE_PACKETS_GOOD - Good Oversize Packets Received */ /*! @{ */ + #define ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT (0U) /*! RXOVERSZG - Rx Oversize Packets Good This field indicates the number of packets received without @@ -34112,6 +41762,7 @@ typedef struct { /*! @name MAC_RX_64OCTETS_PACKETS_GOOD_BAD - Good and Bad 64-Byte Packets Received */ /*! @{ */ + #define ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT (0U) /*! RX64OCTGB - Rx 64 Octets Packets Good Bad This field indicates the number of good and bad @@ -34122,6 +41773,7 @@ typedef struct { /*! @name MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD - Good and Bad 64-to-127 Byte Packets Received */ /*! @{ */ + #define ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT (0U) /*! RX65_127OCTGB - Rx 65-127 Octets Packets Good Bad This field indicates the number of good and @@ -34132,6 +41784,7 @@ typedef struct { /*! @name MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD - Good and Bad 128-to-255 Byte Packets Received */ /*! @{ */ + #define ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT (0U) /*! RX128_255OCTGB - Rx 128-255 Octets Packets Good Bad This field indicates the number of good and @@ -34143,6 +41796,7 @@ typedef struct { /*! @name MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD - Good and Bad 256-to-511 Byte Packets Received */ /*! @{ */ + #define ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT (0U) /*! RX256_511OCTGB - Rx 256-511 Octets Packets Good Bad This field indicates the number of good and @@ -34154,6 +41808,7 @@ typedef struct { /*! @name MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD - Good and Bad 512-to-1023 Byte Packets Received */ /*! @{ */ + #define ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT (0U) /*! RX512_1023OCTGB - RX 512-1023 Octets Packets Good Bad This field indicates the number of good @@ -34165,6 +41820,7 @@ typedef struct { /*! @name MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD - Good and Bad 1024-to-Max Byte Packets Received */ /*! @{ */ + #define ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT (0U) /*! RX1024_MAXOCTGB - Rx 1024-Max Octets Good Bad This field indicates the number of good and bad @@ -34176,6 +41832,7 @@ typedef struct { /*! @name MAC_RX_UNICAST_PACKETS_GOOD - Good Unicast Packets Received */ /*! @{ */ + #define ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT (0U) /*! RXUCASTG - Rx Unicast Packets Good This field indicates the number of good unicast packets received. @@ -34185,6 +41842,7 @@ typedef struct { /*! @name MAC_RX_LENGTH_ERROR_PACKETS - Length Error Packets Received */ /*! @{ */ + #define ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT (0U) /*! RXLENERR - Rx Length Error Packets This field indicates the number of packets received with @@ -34195,6 +41853,7 @@ typedef struct { /*! @name MAC_RX_OUT_OF_RANGE_TYPE_PACKETS - Out-of-range Type Packets Received */ /*! @{ */ + #define ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT (0U) /*! RXOUTOFRNG - Rx Out of Range Type Packet This field indicates the number of packets received @@ -34205,6 +41864,7 @@ typedef struct { /*! @name MAC_RX_PAUSE_PACKETS - Pause Packets Received */ /*! @{ */ + #define ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT (0U) /*! RXPAUSEPKT - Rx Pause Packets This field indicates the number of good and valid Pause packets received. @@ -34214,6 +41874,7 @@ typedef struct { /*! @name MAC_RX_FIFO_OVERFLOW_PACKETS - Missed Packets Due to FIFO Overflow */ /*! @{ */ + #define ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT (0U) /*! RXFIFOOVFL - Rx FIFO Overflow Packets This field indicates the number of missed received packets because of FIFO overflow. @@ -34223,6 +41884,7 @@ typedef struct { /*! @name MAC_RX_VLAN_PACKETS_GOOD_BAD - Good and Bad VLAN Packets Received */ /*! @{ */ + #define ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT (0U) /*! RXVLANPKTGB - Rx VLAN Packets Good Bad This field indicates the number of good and bad VLAN packets received. @@ -34232,6 +41894,7 @@ typedef struct { /*! @name MAC_RX_WATCHDOG_ERROR_PACKETS - Watchdog Error Packets Received */ /*! @{ */ + #define ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT (0U) /*! RXWDGERR - Rx Watchdog Error Packets This field indicates the number of packets received with @@ -34245,6 +41908,7 @@ typedef struct { /*! @name MAC_RX_RECEIVE_ERROR_PACKETS - Receive Error Packets Received */ /*! @{ */ + #define ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT (0U) /*! RXRCVERR - Rx Receive Error Packets This field indicates the number of packets received with @@ -34255,6 +41919,7 @@ typedef struct { /*! @name MAC_RX_CONTROL_PACKETS_GOOD - Good Control Packets Received */ /*! @{ */ + #define ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT (0U) /*! RXCTRLG - Rx Control Packets Good This field indicates the number of good control packets received. @@ -34264,6 +41929,7 @@ typedef struct { /*! @name MAC_TX_LPI_USEC_CNTR - Microseconds Tx LPI Asserted */ /*! @{ */ + #define ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_SHIFT (0U) /*! TXLPIUSC - Tx LPI Microseconds Counter This field indicates the number of microseconds Tx LPI is asserted. @@ -34273,6 +41939,7 @@ typedef struct { /*! @name MAC_TX_LPI_TRAN_CNTR - Number of Times Tx LPI Asserted */ /*! @{ */ + #define ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_SHIFT (0U) /*! TXLPITRC - Tx LPI Transition counter This field indicates the number of times Tx LPI Entry has occurred. @@ -34282,6 +41949,7 @@ typedef struct { /*! @name MAC_RX_LPI_USEC_CNTR - Microseconds Rx LPI Sampled */ /*! @{ */ + #define ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_SHIFT (0U) /*! RXLPIUSC - Rx LPI Microseconds Counter This field indicates the number of microseconds Rx LPI is asserted. @@ -34291,6 +41959,7 @@ typedef struct { /*! @name MAC_RX_LPI_TRAN_CNTR - Number of Times Rx LPI Entered */ /*! @{ */ + #define ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_SHIFT (0U) /*! RXLPITRC - Rx LPI Transition counter This field indicates the number of times Rx LPI Entry has occurred. @@ -34300,6 +41969,7 @@ typedef struct { /*! @name MAC_MMC_IPC_RX_INTERRUPT_MASK - MMC IPC Receive Interrupt Mask */ /*! @{ */ + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_MASK (0x1U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_SHIFT (0U) /*! RXIPV4GPIM - MMC Receive IPV4 Good Packet Counter Interrupt Mask Setting this bit masks the @@ -34308,6 +41978,7 @@ typedef struct { * 0b1..MMC Receive IPV4 Good Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_MASK (0x2U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_SHIFT (1U) /*! RXIPV4HERPIM - MMC Receive IPV4 Header Error Packet Counter Interrupt Mask Setting this bit @@ -34317,6 +41988,7 @@ typedef struct { * 0b1..MMC Receive IPV4 Header Error Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_MASK (0x4U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_SHIFT (2U) /*! RXIPV4NOPAYPIM - MMC Receive IPV4 No Payload Packet Counter Interrupt Mask Setting this bit @@ -34326,6 +41998,7 @@ typedef struct { * 0b1..MMC Receive IPV4 No Payload Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_MASK (0x8U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_SHIFT (3U) /*! RXIPV4FRAGPIM - MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask Setting this bit masks @@ -34335,6 +42008,7 @@ typedef struct { * 0b1..MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_MASK (0x10U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_SHIFT (4U) /*! RXIPV4UDSBLPIM - MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask Setting @@ -34344,6 +42018,7 @@ typedef struct { * 0b1..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_MASK (0x20U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_SHIFT (5U) /*! RXIPV6GPIM - MMC Receive IPV6 Good Packet Counter Interrupt Mask Setting this bit masks the @@ -34352,6 +42027,7 @@ typedef struct { * 0b1..MMC Receive IPV6 Good Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_MASK (0x40U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_SHIFT (6U) /*! RXIPV6HERPIM - MMC Receive IPV6 Header Error Packet Counter Interrupt Mask Setting this bit @@ -34361,6 +42037,7 @@ typedef struct { * 0b1..MMC Receive IPV6 Header Error Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_MASK (0x80U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_SHIFT (7U) /*! RXIPV6NOPAYPIM - MMC Receive IPV6 No Payload Packet Counter Interrupt Mask Setting this bit @@ -34370,6 +42047,7 @@ typedef struct { * 0b1..MMC Receive IPV6 No Payload Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_MASK (0x100U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_SHIFT (8U) /*! RXUDPGPIM - MMC Receive UDP Good Packet Counter Interrupt Mask Setting this bit masks the @@ -34378,6 +42056,7 @@ typedef struct { * 0b1..MMC Receive UDP Good Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_MASK (0x200U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_SHIFT (9U) /*! RXUDPERPIM - MMC Receive UDP Error Packet Counter Interrupt Mask Setting this bit masks the @@ -34386,6 +42065,7 @@ typedef struct { * 0b1..MMC Receive UDP Error Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_MASK (0x400U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_SHIFT (10U) /*! RXTCPGPIM - MMC Receive TCP Good Packet Counter Interrupt Mask Setting this bit masks the @@ -34394,6 +42074,7 @@ typedef struct { * 0b1..MMC Receive TCP Good Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_MASK (0x800U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_SHIFT (11U) /*! RXTCPERPIM - MMC Receive TCP Error Packet Counter Interrupt Mask Setting this bit masks the @@ -34402,6 +42083,7 @@ typedef struct { * 0b1..MMC Receive TCP Error Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_MASK (0x1000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_SHIFT (12U) /*! RXICMPGPIM - MMC Receive ICMP Good Packet Counter Interrupt Mask Setting this bit masks the @@ -34410,6 +42092,7 @@ typedef struct { * 0b1..MMC Receive ICMP Good Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_MASK (0x2000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_SHIFT (13U) /*! RXICMPERPIM - MMC Receive ICMP Error Packet Counter Interrupt Mask Setting this bit masks the @@ -34419,6 +42102,7 @@ typedef struct { * 0b1..MMC Receive ICMP Error Packet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_MASK (0x10000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_SHIFT (16U) /*! RXIPV4GOIM - MMC Receive IPV4 Good Octet Counter Interrupt Mask Setting this bit masks the @@ -34427,6 +42111,7 @@ typedef struct { * 0b1..MMC Receive IPV4 Good Octet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_MASK (0x20000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_SHIFT (17U) /*! RXIPV4HEROIM - MMC Receive IPV4 Header Error Octet Counter Interrupt Mask Setting this bit masks @@ -34436,6 +42121,7 @@ typedef struct { * 0b1..MMC Receive IPV4 Header Error Octet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_MASK (0x40000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_SHIFT (18U) /*! RXIPV4NOPAYOIM - MMC Receive IPV4 No Payload Octet Counter Interrupt Mask Setting this bit masks @@ -34445,6 +42131,7 @@ typedef struct { * 0b1..MMC Receive IPV4 No Payload Octet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_MASK (0x80000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_SHIFT (19U) /*! RXIPV4FRAGOIM - MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask Setting this bit masks @@ -34454,6 +42141,7 @@ typedef struct { * 0b1..MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_MASK (0x100000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_SHIFT (20U) /*! RXIPV4UDSBLOIM - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask Setting @@ -34463,6 +42151,7 @@ typedef struct { * 0b1..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_MASK (0x200000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_SHIFT (21U) /*! RXIPV6GOIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask Setting this bit masks the @@ -34471,6 +42160,7 @@ typedef struct { * 0b1..MMC Receive IPV6 Good Octet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_MASK (0x400000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_SHIFT (22U) /*! RXIPV6HEROIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask Setting this bit masks the @@ -34480,6 +42170,7 @@ typedef struct { * 0b1..MMC Receive IPV6 Good Octet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_MASK (0x800000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_SHIFT (23U) /*! RXIPV6NOPAYOIM - MMC Receive IPV6 Header Error Octet Counter Interrupt Mask Setting this bit @@ -34489,6 +42180,7 @@ typedef struct { * 0b1..MMC Receive IPV6 Header Error Octet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_MASK (0x1000000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_SHIFT (24U) /*! RXUDPGOIM - MMC Receive IPV6 No Payload Octet Counter Interrupt Mask Setting this bit masks the @@ -34498,6 +42190,7 @@ typedef struct { * 0b1..MMC Receive IPV6 No Payload Octet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_MASK (0x2000000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_SHIFT (25U) /*! RXUDPEROIM - MMC Receive UDP Good Octet Counter Interrupt Mask Setting this bit masks the @@ -34506,6 +42199,7 @@ typedef struct { * 0b1..MMC Receive UDP Good Octet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_MASK (0x4000000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_SHIFT (26U) /*! RXTCPGOIM - MMC Receive TCP Good Octet Counter Interrupt Mask Setting this bit masks the @@ -34514,6 +42208,7 @@ typedef struct { * 0b1..MMC Receive TCP Good Octet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_MASK (0x8000000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_SHIFT (27U) /*! RXTCPEROIM - MMC Receive TCP Error Octet Counter Interrupt Mask Setting this bit masks the @@ -34522,6 +42217,7 @@ typedef struct { * 0b1..MMC Receive TCP Error Octet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_MASK (0x10000000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_SHIFT (28U) /*! RXICMPGOIM - MMC Receive ICMP Good Octet Counter Interrupt Mask Setting this bit masks the @@ -34530,6 +42226,7 @@ typedef struct { * 0b1..MMC Receive ICMP Good Octet Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_MASK (0x20000000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_SHIFT (29U) /*! RXICMPEROIM - MMC Receive ICMP Error Octet Counter Interrupt Mask Setting this bit masks the @@ -34543,6 +42240,7 @@ typedef struct { /*! @name MAC_MMC_IPC_RX_INTERRUPT - MMC IPC Receive Interrupt */ /*! @{ */ + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_MASK (0x1U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_SHIFT (0U) /*! RXIPV4GPIS - MMC Receive IPV4 Good Packet Counter Interrupt Status This bit is set when the @@ -34551,6 +42249,7 @@ typedef struct { * 0b0..MMC Receive IPV4 Good Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_MASK (0x2U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_SHIFT (1U) /*! RXIPV4HERPIS - MMC Receive IPV4 Header Error Packet Counter Interrupt Status This bit is set @@ -34559,6 +42258,7 @@ typedef struct { * 0b0..MMC Receive IPV4 Header Error Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_MASK (0x4U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_SHIFT (2U) /*! RXIPV4NOPAYPIS - MMC Receive IPV4 No Payload Packet Counter Interrupt Status This bit is set @@ -34567,6 +42267,7 @@ typedef struct { * 0b0..MMC Receive IPV4 No Payload Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_MASK (0x8U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_SHIFT (3U) /*! RXIPV4FRAGPIS - MMC Receive IPV4 Fragmented Packet Counter Interrupt Status This bit is set when @@ -34575,6 +42276,7 @@ typedef struct { * 0b0..MMC Receive IPV4 Fragmented Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_MASK (0x10U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_SHIFT (4U) /*! RXIPV4UDSBLPIS - MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status This bit @@ -34584,6 +42286,7 @@ typedef struct { * 0b0..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_MASK (0x20U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_SHIFT (5U) /*! RXIPV6GPIS - MMC Receive IPV6 Good Packet Counter Interrupt Status This bit is set when the @@ -34592,6 +42295,7 @@ typedef struct { * 0b0..MMC Receive IPV6 Good Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_MASK (0x40U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_SHIFT (6U) /*! RXIPV6HERPIS - MMC Receive IPV6 Header Error Packet Counter Interrupt Status This bit is set @@ -34600,6 +42304,7 @@ typedef struct { * 0b0..MMC Receive IPV6 Header Error Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_MASK (0x80U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_SHIFT (7U) /*! RXIPV6NOPAYPIS - MMC Receive IPV6 No Payload Packet Counter Interrupt Status This bit is set @@ -34608,6 +42313,7 @@ typedef struct { * 0b0..MMC Receive IPV6 No Payload Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_MASK (0x100U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_SHIFT (8U) /*! RXUDPGPIS - MC Receive UDP Good Packet Counter Interrupt Status This bit is set when the @@ -34616,6 +42322,7 @@ typedef struct { * 0b0..MMC Receive UDP Good Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_MASK (0x200U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_SHIFT (9U) /*! RXUDPERPIS - MMC Receive UDP Error Packet Counter Interrupt Status This bit is set when the @@ -34624,6 +42331,7 @@ typedef struct { * 0b0..MMC Receive UDP Error Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_MASK (0x400U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_SHIFT (10U) /*! RXTCPGPIS - MMC Receive TCP Good Packet Counter Interrupt Status This bit is set when the @@ -34632,6 +42340,7 @@ typedef struct { * 0b0..MMC Receive TCP Good Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_MASK (0x800U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_SHIFT (11U) /*! RXTCPERPIS - MMC Receive TCP Error Packet Counter Interrupt Status This bit is set when the @@ -34640,6 +42349,7 @@ typedef struct { * 0b0..MMC Receive TCP Error Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_MASK (0x1000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_SHIFT (12U) /*! RXICMPGPIS - MMC Receive ICMP Good Packet Counter Interrupt Status This bit is set when the @@ -34648,6 +42358,7 @@ typedef struct { * 0b0..MMC Receive ICMP Good Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_MASK (0x2000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_SHIFT (13U) /*! RXICMPERPIS - MMC Receive ICMP Error Packet Counter Interrupt Status This bit is set when the @@ -34656,6 +42367,7 @@ typedef struct { * 0b0..MMC Receive ICMP Error Packet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_MASK (0x10000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_SHIFT (16U) /*! RXIPV4GOIS - MMC Receive IPV4 Good Octet Counter Interrupt Status This bit is set when the @@ -34664,6 +42376,7 @@ typedef struct { * 0b0..MMC Receive IPV4 Good Octet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_MASK (0x20000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_SHIFT (17U) /*! RXIPV4HEROIS - MMC Receive IPV4 Header Error Octet Counter Interrupt Status This bit is set when @@ -34672,6 +42385,7 @@ typedef struct { * 0b0..MMC Receive IPV4 Header Error Octet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_MASK (0x40000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_SHIFT (18U) /*! RXIPV4NOPAYOIS - MMC Receive IPV4 No Payload Octet Counter Interrupt Status This bit is set when @@ -34680,6 +42394,7 @@ typedef struct { * 0b0..MMC Receive IPV4 No Payload Octet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_MASK (0x80000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_SHIFT (19U) /*! RXIPV4FRAGOIS - MMC Receive IPV4 Fragmented Octet Counter Interrupt Status This bit is set when @@ -34688,6 +42403,7 @@ typedef struct { * 0b0..MMC Receive IPV4 Fragmented Octet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_MASK (0x100000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_SHIFT (20U) /*! RXIPV4UDSBLOIS - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status This bit @@ -34697,6 +42413,7 @@ typedef struct { * 0b0..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_MASK (0x200000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_SHIFT (21U) /*! RXIPV6GOIS - MMC Receive IPV6 Good Octet Counter Interrupt Status This bit is set when the @@ -34705,6 +42422,7 @@ typedef struct { * 0b0..MMC Receive IPV6 Good Octet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_MASK (0x400000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_SHIFT (22U) /*! RXIPV6HEROIS - MMC Receive IPV6 Header Error Octet Counter Interrupt Status This bit is set when @@ -34713,6 +42431,7 @@ typedef struct { * 0b0..MMC Receive IPV6 Header Error Octet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_MASK (0x800000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_SHIFT (23U) /*! RXIPV6NOPAYOIS - MMC Receive IPV6 No Payload Octet Counter Interrupt Status This bit is set when @@ -34721,6 +42440,7 @@ typedef struct { * 0b0..MMC Receive IPV6 No Payload Octet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_MASK (0x1000000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_SHIFT (24U) /*! RXUDPGOIS - MMC Receive UDP Good Octet Counter Interrupt Status This bit is set when the @@ -34729,6 +42449,7 @@ typedef struct { * 0b0..MMC Receive UDP Good Octet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_MASK (0x2000000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_SHIFT (25U) /*! RXUDPEROIS - MMC Receive UDP Error Octet Counter Interrupt Status This bit is set when the @@ -34737,6 +42458,7 @@ typedef struct { * 0b0..MMC Receive UDP Error Octet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_MASK (0x4000000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_SHIFT (26U) /*! RXTCPGOIS - MMC Receive TCP Good Octet Counter Interrupt Status This bit is set when the @@ -34745,6 +42467,7 @@ typedef struct { * 0b0..MMC Receive TCP Good Octet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_MASK (0x8000000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_SHIFT (27U) /*! RXTCPEROIS - MMC Receive TCP Error Octet Counter Interrupt Status This bit is set when the @@ -34753,6 +42476,7 @@ typedef struct { * 0b0..MMC Receive TCP Error Octet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_MASK (0x10000000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_SHIFT (28U) /*! RXICMPGOIS - MMC Receive ICMP Good Octet Counter Interrupt Status This bit is set when the @@ -34761,6 +42485,7 @@ typedef struct { * 0b0..MMC Receive ICMP Good Octet Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_MASK) + #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_MASK (0x20000000U) #define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_SHIFT (29U) /*! RXICMPEROIS - MMC Receive ICMP Error Octet Counter Interrupt Status This bit is set when the @@ -34773,6 +42498,7 @@ typedef struct { /*! @name MAC_RXIPV4_GOOD_PACKETS - Good IPv4 Datagrams Received */ /*! @{ */ + #define ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_SHIFT (0U) /*! RXIPV4GDPKT - RxIPv4 Good Packets This field indicates the number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload. @@ -34782,6 +42508,7 @@ typedef struct { /*! @name MAC_RXIPV4_HEADER_ERROR_PACKETS - IPv4 Datagrams Received with Header Errors */ /*! @{ */ + #define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_SHIFT (0U) /*! RXIPV4HDRERRPKT - RxIPv4 Header Error Packets This field indicates the number of IPv4 datagrams @@ -34792,6 +42519,7 @@ typedef struct { /*! @name MAC_RXIPV4_NO_PAYLOAD_PACKETS - IPv4 Datagrams Received with No Payload */ /*! @{ */ + #define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_SHIFT (0U) /*! RXIPV4NOPAYPKT - RxIPv4 Payload Packets This field indicates the number of IPv4 datagram packets @@ -34802,6 +42530,7 @@ typedef struct { /*! @name MAC_RXIPV4_FRAGMENTED_PACKETS - IPv4 Datagrams Received with Fragmentation */ /*! @{ */ + #define ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_SHIFT (0U) /*! RXIPV4FRAGPKT - RxIPv4 Fragmented Packets This field indicates the number of good IPv4 datagrams received with fragmentation. @@ -34811,6 +42540,7 @@ typedef struct { /*! @name MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS - IPv4 Datagrams Received with UDP Checksum Disabled */ /*! @{ */ + #define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_SHIFT (0U) /*! RXIPV4UDSBLPKT - RxIPv4 UDP Checksum Disabled Packets This field indicates the number of good @@ -34821,6 +42551,7 @@ typedef struct { /*! @name MAC_RXIPV6_GOOD_PACKETS - Good IPv6 Datagrams Received */ /*! @{ */ + #define ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_SHIFT (0U) /*! RXIPV6GDPKT - RxIPv6 Good Packets This field indicates the number of good IPv6 datagrams received with the TCP, UDP, or ICMP payload. @@ -34830,6 +42561,7 @@ typedef struct { /*! @name MAC_RXIPV6_HEADER_ERROR_PACKETS - IPv6 Datagrams Received with Header Errors */ /*! @{ */ + #define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_SHIFT (0U) /*! RXIPV6HDRERRPKT - RxIPv6 Header Error Packets This field indicates the number of IPv6 datagrams @@ -34840,6 +42572,7 @@ typedef struct { /*! @name MAC_RXIPV6_NO_PAYLOAD_PACKETS - IPv6 Datagrams Received with No Payload */ /*! @{ */ + #define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_SHIFT (0U) /*! RXIPV6NOPAYPKT - RxIPv6 Payload Packets This field indicates the number of IPv6 datagram packets @@ -34850,6 +42583,7 @@ typedef struct { /*! @name MAC_RXUDP_GOOD_PACKETS - IPv6 Datagrams Received with Good UDP */ /*! @{ */ + #define ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_SHIFT (0U) /*! RXUDPGDPKT - RxUDP Good Packets This field indicates the number of good IP datagrams received with a good UDP payload. @@ -34859,6 +42593,7 @@ typedef struct { /*! @name MAC_RXUDP_ERROR_PACKETS - IPv6 Datagrams Received with UDP Checksum Error */ /*! @{ */ + #define ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_SHIFT (0U) /*! RXUDPERRPKT - RxUDP Error Packets This field indicates the number of good IP datagrams received @@ -34869,6 +42604,7 @@ typedef struct { /*! @name MAC_RXTCP_GOOD_PACKETS - IPv6 Datagrams Received with Good TCP Payload */ /*! @{ */ + #define ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_SHIFT (0U) /*! RXTCPGDPKT - RxTCP Good Packets This field indicates the number of good IP datagrams received with a good TCP payload. @@ -34878,6 +42614,7 @@ typedef struct { /*! @name MAC_RXTCP_ERROR_PACKETS - IPv6 Datagrams Received with TCP Checksum Error */ /*! @{ */ + #define ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_SHIFT (0U) /*! RXTCPERRPKT - RxTCP Error Packets This field indicates the number of good IP datagrams received @@ -34888,6 +42625,7 @@ typedef struct { /*! @name MAC_RXICMP_GOOD_PACKETS - IPv6 Datagrams Received with Good ICMP Payload */ /*! @{ */ + #define ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_SHIFT (0U) /*! RXICMPGDPKT - RxICMP Good Packets This field indicates the number of good IP datagrams received with a good ICMP payload. @@ -34897,6 +42635,7 @@ typedef struct { /*! @name MAC_RXICMP_ERROR_PACKETS - IPv6 Datagrams Received with ICMP Checksum Error */ /*! @{ */ + #define ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_SHIFT (0U) /*! RXICMPERRPKT - RxICMP Error Packets This field indicates the number of good IP datagrams @@ -34907,6 +42646,7 @@ typedef struct { /*! @name MAC_RXIPV4_GOOD_OCTETS - Good Bytes Received in IPv4 Datagrams */ /*! @{ */ + #define ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_SHIFT (0U) /*! RXIPV4GDOCT - RxIPv4 Good Octets This field indicates the number of bytes received in good IPv4 @@ -34917,6 +42657,7 @@ typedef struct { /*! @name MAC_RXIPV4_HEADER_ERROR_OCTETS - Bytes Received in IPv4 Datagrams with Header Errors */ /*! @{ */ + #define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_SHIFT (0U) /*! RXIPV4HDRERROCT - RxIPv4 Header Error Octets This field indicates the number of bytes received @@ -34927,6 +42668,7 @@ typedef struct { /*! @name MAC_RXIPV4_NO_PAYLOAD_OCTETS - Bytes Received in IPv4 Datagrams with No Payload */ /*! @{ */ + #define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_SHIFT (0U) /*! RXIPV4NOPAYOCT - RxIPv4 Payload Octets This field indicates the number of bytes received in IPv4 @@ -34937,6 +42679,7 @@ typedef struct { /*! @name MAC_RXIPV4_FRAGMENTED_OCTETS - Bytes Received in Fragmented IPv4 Datagrams */ /*! @{ */ + #define ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_SHIFT (0U) /*! RXIPV4FRAGOCT - RxIPv4 Fragmented Octets This field indicates the number of bytes received in fragmented IPv4 datagrams. @@ -34946,6 +42689,7 @@ typedef struct { /*! @name MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS - Bytes Received with UDP Checksum Disabled */ /*! @{ */ + #define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_SHIFT (0U) /*! RXIPV4UDSBLOCT - RxIPv4 UDP Checksum Disable Octets This field indicates the number of bytes @@ -34956,6 +42700,7 @@ typedef struct { /*! @name MAC_RXIPV6_GOOD_OCTETS - Bytes Received in Good IPv6 Datagrams */ /*! @{ */ + #define ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_SHIFT (0U) /*! RXIPV6GDOCT - RxIPv6 Good Octets This field indicates the number of bytes received in good IPv6 @@ -34966,6 +42711,7 @@ typedef struct { /*! @name MAC_RXIPV6_HEADER_ERROR_OCTETS - Bytes Received in IPv6 Datagrams with Data Errors */ /*! @{ */ + #define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_SHIFT (0U) /*! RXIPV6HDRERROCT - RxIPv6 Header Error Octets This field indicates the number of bytes received @@ -34976,6 +42722,7 @@ typedef struct { /*! @name MAC_RXIPV6_NO_PAYLOAD_OCTETS - Bytes Received in IPv6 Datagrams with No Payload */ /*! @{ */ + #define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_SHIFT (0U) /*! RXIPV6NOPAYOCT - RxIPv6 Payload Octets This field indicates the number of bytes received in IPv6 @@ -34986,6 +42733,7 @@ typedef struct { /*! @name MAC_RXUDP_GOOD_OCTETS - Bytes Received in Good UDP Segment */ /*! @{ */ + #define ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_SHIFT (0U) /*! RXUDPGDOCT - RxUDP Good Octets This field indicates the number of bytes received in a good UDP segment. @@ -34995,6 +42743,7 @@ typedef struct { /*! @name MAC_RXUDP_ERROR_OCTETS - Bytes Received in UDP Segment with Checksum Errors */ /*! @{ */ + #define ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_SHIFT (0U) /*! RXUDPERROCT - RxUDP Error Octets This field indicates the number of bytes received in a UDP segment that had checksum errors. @@ -35004,6 +42753,7 @@ typedef struct { /*! @name MAC_RXTCP_GOOD_OCTETS - Bytes Received in Good TCP Segment */ /*! @{ */ + #define ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_SHIFT (0U) /*! RXTCPGDOCT - RxTCP Good Octets This field indicates the number of bytes received in a good TCP segment. @@ -35013,6 +42763,7 @@ typedef struct { /*! @name MAC_RXTCP_ERROR_OCTETS - Bytes Received in TCP Segment with Checksum Errors */ /*! @{ */ + #define ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_SHIFT (0U) /*! RXTCPERROCT - RxTCP Error Octets This field indicates the number of bytes received in a TCP segment that had checksum errors. @@ -35022,6 +42773,7 @@ typedef struct { /*! @name MAC_RXICMP_GOOD_OCTETS - Bytes Received in Good ICMP Segment */ /*! @{ */ + #define ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_SHIFT (0U) /*! RXICMPGDOCT - RxICMP Good Octets This field indicates the number of bytes received in a good ICMP segment. @@ -35031,6 +42783,7 @@ typedef struct { /*! @name MAC_RXICMP_ERROR_OCTETS - Bytes Received in ICMP Segment with Checksum Errors */ /*! @{ */ + #define ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_SHIFT (0U) /*! RXICMPERROCT - RxICMP Error Octets This field indicates the number of bytes received in a ICMP segment that had checksum errors. @@ -35040,6 +42793,7 @@ typedef struct { /*! @name MAC_MMC_FPE_TX_INTERRUPT - MMC FPE Transmit Interrupt */ /*! @{ */ + #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_MASK (0x1U) #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_SHIFT (0U) /*! FCIS - MMC Tx FPE Fragment Counter Interrupt status This bit is set when the @@ -35048,6 +42802,7 @@ typedef struct { * 0b0..MMC Tx FPE Fragment Counter Interrupt status not detected */ #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_MASK) + #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_MASK (0x2U) #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_SHIFT (1U) /*! HRCIS - MMC Tx Hold Request Counter Interrupt Status This bit is set when the Tx_Hold_Req_Cntr @@ -35060,6 +42815,7 @@ typedef struct { /*! @name MAC_MMC_FPE_TX_INTERRUPT_MASK - MMC FPE Transmit Mask Interrupt */ /*! @{ */ + #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_MASK (0x1U) #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_SHIFT (0U) /*! FCIM - MMC Transmit Fragment Counter Interrupt Mask Setting this bit masks the interrupt when @@ -35068,6 +42824,7 @@ typedef struct { * 0b1..MMC Transmit Fragment Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_MASK) + #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_MASK (0x2U) #define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_SHIFT (1U) /*! HRCIM - MMC Transmit Hold Request Counter Interrupt Mask Setting this bit masks the interrupt @@ -35080,6 +42837,7 @@ typedef struct { /*! @name MAC_MMC_TX_FPE_FRAGMENT_CNTR - MMC FPE Transmitted Fragment Counter */ /*! @{ */ + #define ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT (0U) /*! TXFFC - Tx FPE Fragment counter This field indicates the number of additional mPackets that has @@ -35091,6 +42849,7 @@ typedef struct { /*! @name MAC_MMC_TX_HOLD_REQ_CNTR - MMC FPE Transmitted Hold Request Counter */ /*! @{ */ + #define ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT (0U) /*! TXHRC - Tx Hold Request Counter This field indicates count of number of a hold request is given to MAC. @@ -35100,6 +42859,7 @@ typedef struct { /*! @name MAC_MMC_FPE_RX_INTERRUPT - MMC FPE Receive Interrupt */ /*! @{ */ + #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_MASK (0x1U) #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_SHIFT (0U) /*! PAECIS - MMC Rx Packet Assembly Error Counter Interrupt Status This bit is set when the @@ -35108,6 +42868,7 @@ typedef struct { * 0b0..MMC Rx Packet Assembly Error Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_MASK) + #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_MASK (0x2U) #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_SHIFT (1U) /*! PSECIS - MMC Rx Packet SMD Error Counter Interrupt Status This bit is set when the @@ -35116,6 +42877,7 @@ typedef struct { * 0b0..MMC Rx Packet SMD Error Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_MASK) + #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_MASK (0x4U) #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_SHIFT (2U) /*! PAOCIS - MMC Rx Packet Assembly OK Counter Interrupt Status This bit is set when the @@ -35124,6 +42886,7 @@ typedef struct { * 0b0..MMC Rx Packet Assembly OK Counter Interrupt Status not detected */ #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_MASK) + #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_MASK (0x8U) #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_SHIFT (3U) /*! FCIS - MMC Rx FPE Fragment Counter Interrupt Status This bit is set when the @@ -35136,6 +42899,7 @@ typedef struct { /*! @name MAC_MMC_FPE_RX_INTERRUPT_MASK - MMC FPE Receive Interrupt Mask */ /*! @{ */ + #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_MASK (0x1U) #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_SHIFT (0U) /*! PAECIM - MMC Rx Packet Assembly Error Counter Interrupt Mask Setting this bit masks the @@ -35145,6 +42909,7 @@ typedef struct { * 0b1..MMC Rx Packet Assembly Error Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_MASK) + #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_MASK (0x2U) #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_SHIFT (1U) /*! PSECIM - MMC Rx Packet SMD Error Counter Interrupt Mask Setting this bit masks the interrupt @@ -35153,6 +42918,7 @@ typedef struct { * 0b1..MMC Rx Packet SMD Error Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_MASK) + #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_MASK (0x4U) #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_SHIFT (2U) /*! PAOCIM - MMC Rx Packet Assembly OK Counter Interrupt Mask Setting this bit masks the interrupt @@ -35162,6 +42928,7 @@ typedef struct { * 0b1..MMC Rx Packet Assembly OK Counter Interrupt Mask is enabled */ #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_MASK) + #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_MASK (0x8U) #define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_SHIFT (3U) /*! FCIM - MMC Rx FPE Fragment Counter Interrupt Mask Setting this bit masks the interrupt when the @@ -35174,6 +42941,7 @@ typedef struct { /*! @name MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR - MMC Receive Packet Reassembly Error Counter */ /*! @{ */ + #define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT (0U) /*! PAEC - Rx Packet Assembly Error Counter This field indicates the number of MAC frames with @@ -35184,6 +42952,7 @@ typedef struct { /*! @name MAC_MMC_RX_PACKET_SMD_ERR_CNTR - MMC Receive Packet SMD Error Counter */ /*! @{ */ + #define ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT (0U) /*! PSEC - Rx Packet SMD Error Counter This field indicates the number of MAC frames rejected due to @@ -35195,6 +42964,7 @@ typedef struct { /*! @name MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR - MMC Receive Packet Successful Reassembly Counter */ /*! @{ */ + #define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT (0U) /*! PAOC - Rx Packet Assembly OK Counter This field indicates the number of MAC frames that were @@ -35205,6 +42975,7 @@ typedef struct { /*! @name MAC_MMC_RX_FPE_FRAGMENT_CNTR - MMC FPE Received Fragment Counter */ /*! @{ */ + #define ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT (0U) /*! FFC - Rx FPE Fragment Counter This field indicates the number of additional mPackets received @@ -35216,6 +42987,7 @@ typedef struct { /*! @name MAC_L3_L4_CONTROL0 - Layer 3 and Layer 4 Control of Filter 0 */ /*! @{ */ + #define ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_MASK (0x1U) #define ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_SHIFT (0U) /*! L3PEN0 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination @@ -35224,6 +42996,7 @@ typedef struct { * 0b1..Layer 3 Protocol is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_MASK (0x4U) #define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_SHIFT (2U) /*! L3SAM0 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. @@ -35231,6 +43004,7 @@ typedef struct { * 0b1..Layer 3 IP SA Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_MASK (0x8U) #define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_SHIFT (3U) /*! L3SAIM0 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address @@ -35239,6 +43013,7 @@ typedef struct { * 0b1..Layer 3 IP SA Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_MASK (0x10U) #define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_SHIFT (4U) /*! L3DAM0 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. @@ -35246,6 +43021,7 @@ typedef struct { * 0b1..Layer 3 IP DA Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_MASK (0x20U) #define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_SHIFT (5U) /*! L3DAIM0 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination @@ -35254,18 +43030,21 @@ typedef struct { * 0b1..Layer 3 IP DA Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_MASK (0x7C0U) #define ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT (6U) /*! L3HSBM0 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower * bits of IP Source Address that are masked for matching in the IPv4 packets. */ #define ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_MASK (0xF800U) #define ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT (11U) /*! L3HDBM0 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher * bits of IP Destination Address that are matched in the IPv4 packets. */ #define ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_MASK (0x10000U) #define ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_SHIFT (16U) /*! L4PEN0 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number @@ -35274,6 +43053,7 @@ typedef struct { * 0b1..Layer 4 Protocol is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_MASK (0x40000U) #define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_SHIFT (18U) /*! L4SPM0 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. @@ -35281,6 +43061,7 @@ typedef struct { * 0b1..Layer 4 Source Port Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_MASK (0x80000U) #define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_SHIFT (19U) /*! L4SPIM0 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port @@ -35289,6 +43070,7 @@ typedef struct { * 0b1..Layer 4 Source Port Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_MASK (0x100000U) #define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_SHIFT (20U) /*! L4DPM0 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination @@ -35297,6 +43079,7 @@ typedef struct { * 0b1..Layer 4 Destination Port Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_MASK (0x200000U) #define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_SHIFT (21U) /*! L4DPIM0 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 @@ -35305,12 +43088,14 @@ typedef struct { * 0b1..Layer 4 Destination Port Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_MASK (0x7000000U) #define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_SHIFT (24U) /*! DMCHN0 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number * to which the packet passed by this filter is routed. */ #define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_MASK (0x10000000U) #define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_SHIFT (28U) /*! DMCHEN0 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel @@ -35323,6 +43108,7 @@ typedef struct { /*! @name MAC_LAYER4_ADDRESS0 - Layer 4 Address 0 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_MASK (0xFFFFU) #define ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT (0U) /*! L4SP0 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set @@ -35330,6 +43116,7 @@ typedef struct { * Source Port Number field in the IPv4 or IPv6 packets. */ #define ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_MASK) + #define ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_MASK (0xFFFF0000U) #define ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT (16U) /*! L4DP0 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is @@ -35341,6 +43128,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR0_REG0 - Layer 3 Address 0 Register 0 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT (0U) /*! L3A00 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -35352,6 +43140,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR1_REG0 - Layer 3 Address 1 Register 0 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT (0U) /*! L3A10 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -35363,6 +43152,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR2_REG0 - Layer 3 Address 2 Register 0 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT (0U) /*! L3A20 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -35374,6 +43164,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR3_REG0 - Layer 3 Address 3 Register 0 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT (0U) /*! L3A30 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -35385,6 +43176,7 @@ typedef struct { /*! @name MAC_L3_L4_CONTROL1 - Layer 3 and Layer 4 Control of Filter 1 */ /*! @{ */ + #define ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_MASK (0x1U) #define ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_SHIFT (0U) /*! L3PEN1 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination @@ -35393,6 +43185,7 @@ typedef struct { * 0b1..Layer 3 Protocol is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_MASK (0x4U) #define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_SHIFT (2U) /*! L3SAM1 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. @@ -35400,6 +43193,7 @@ typedef struct { * 0b1..Layer 3 IP SA Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_MASK (0x8U) #define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_SHIFT (3U) /*! L3SAIM1 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address @@ -35408,6 +43202,7 @@ typedef struct { * 0b1..Layer 3 IP SA Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_MASK (0x10U) #define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_SHIFT (4U) /*! L3DAM1 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. @@ -35415,6 +43210,7 @@ typedef struct { * 0b1..Layer 3 IP DA Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_MASK (0x20U) #define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_SHIFT (5U) /*! L3DAIM1 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination @@ -35423,18 +43219,21 @@ typedef struct { * 0b1..Layer 3 IP DA Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_MASK (0x7C0U) #define ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT (6U) /*! L3HSBM1 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower * bits of IP Source Address that are masked for matching in the IPv4 packets. */ #define ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_MASK (0xF800U) #define ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT (11U) /*! L3HDBM1 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher * bits of IP Destination Address that are matched in the IPv4 packets. */ #define ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_MASK (0x10000U) #define ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_SHIFT (16U) /*! L4PEN1 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number @@ -35443,6 +43242,7 @@ typedef struct { * 0b1..Layer 4 Protocol is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_MASK (0x40000U) #define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_SHIFT (18U) /*! L4SPM1 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. @@ -35450,6 +43250,7 @@ typedef struct { * 0b1..Layer 4 Source Port Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_MASK (0x80000U) #define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_SHIFT (19U) /*! L4SPIM1 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port @@ -35458,6 +43259,7 @@ typedef struct { * 0b1..Layer 4 Source Port Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_MASK (0x100000U) #define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_SHIFT (20U) /*! L4DPM1 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination @@ -35466,6 +43268,7 @@ typedef struct { * 0b1..Layer 4 Destination Port Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_MASK (0x200000U) #define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_SHIFT (21U) /*! L4DPIM1 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 @@ -35474,12 +43277,14 @@ typedef struct { * 0b1..Layer 4 Destination Port Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_MASK (0x7000000U) #define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_SHIFT (24U) /*! DMCHN1 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number * to which the packet passed by this filter is routed. */ #define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_MASK (0x10000000U) #define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_SHIFT (28U) /*! DMCHEN1 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel @@ -35492,6 +43297,7 @@ typedef struct { /*! @name MAC_LAYER4_ADDRESS1 - Layer 4 Address 0 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_MASK (0xFFFFU) #define ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT (0U) /*! L4SP1 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set @@ -35499,6 +43305,7 @@ typedef struct { * Source Port Number field in the IPv4 or IPv6 packets. */ #define ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_MASK) + #define ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_MASK (0xFFFF0000U) #define ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT (16U) /*! L4DP1 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is @@ -35510,6 +43317,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR0_REG1 - Layer 3 Address 0 Register 1 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT (0U) /*! L3A01 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -35521,6 +43329,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR1_REG1 - Layer 3 Address 1 Register 1 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT (0U) /*! L3A11 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -35532,6 +43341,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR2_REG1 - Layer 3 Address 2 Register 1 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT (0U) /*! L3A21 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -35543,6 +43353,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR3_REG1 - Layer 3 Address 3 Register 1 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT (0U) /*! L3A31 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -35554,6 +43365,7 @@ typedef struct { /*! @name MAC_L3_L4_CONTROL2 - Layer 3 and Layer 4 Control of Filter 2 */ /*! @{ */ + #define ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_MASK (0x1U) #define ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_SHIFT (0U) /*! L3PEN2 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination @@ -35562,6 +43374,7 @@ typedef struct { * 0b1..Layer 3 Protocol is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_MASK (0x4U) #define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_SHIFT (2U) /*! L3SAM2 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. @@ -35569,6 +43382,7 @@ typedef struct { * 0b1..Layer 3 IP SA Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_MASK (0x8U) #define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_SHIFT (3U) /*! L3SAIM2 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address @@ -35577,6 +43391,7 @@ typedef struct { * 0b1..Layer 3 IP SA Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_MASK (0x10U) #define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_SHIFT (4U) /*! L3DAM2 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. @@ -35584,6 +43399,7 @@ typedef struct { * 0b1..Layer 3 IP DA Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_MASK (0x20U) #define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_SHIFT (5U) /*! L3DAIM2 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination @@ -35592,18 +43408,21 @@ typedef struct { * 0b1..Layer 3 IP DA Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_MASK (0x7C0U) #define ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT (6U) /*! L3HSBM2 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower * bits of IP Source Address that are masked for matching in the IPv4 packets. */ #define ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_MASK (0xF800U) #define ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT (11U) /*! L3HDBM2 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher * bits of IP Destination Address that are matched in the IPv4 packets. */ #define ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_MASK (0x10000U) #define ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_SHIFT (16U) /*! L4PEN2 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number @@ -35612,6 +43431,7 @@ typedef struct { * 0b1..Layer 4 Protocol is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_MASK (0x40000U) #define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_SHIFT (18U) /*! L4SPM2 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. @@ -35619,6 +43439,7 @@ typedef struct { * 0b1..Layer 4 Source Port Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_MASK (0x80000U) #define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_SHIFT (19U) /*! L4SPIM2 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port @@ -35627,6 +43448,7 @@ typedef struct { * 0b1..Layer 4 Source Port Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_MASK (0x100000U) #define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_SHIFT (20U) /*! L4DPM2 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination @@ -35635,6 +43457,7 @@ typedef struct { * 0b1..Layer 4 Destination Port Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_MASK (0x200000U) #define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_SHIFT (21U) /*! L4DPIM2 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 @@ -35643,12 +43466,14 @@ typedef struct { * 0b1..Layer 4 Destination Port Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_MASK (0x7000000U) #define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_SHIFT (24U) /*! DMCHN2 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number * to which the packet passed by this filter is routed. */ #define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_MASK (0x10000000U) #define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_SHIFT (28U) /*! DMCHEN2 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel @@ -35661,6 +43486,7 @@ typedef struct { /*! @name MAC_LAYER4_ADDRESS2 - Layer 4 Address 2 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_MASK (0xFFFFU) #define ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT (0U) /*! L4SP2 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set @@ -35668,6 +43494,7 @@ typedef struct { * Source Port Number field in the IPv4 or IPv6 packets. */ #define ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_MASK) + #define ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_MASK (0xFFFF0000U) #define ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT (16U) /*! L4DP2 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is @@ -35679,6 +43506,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR0_REG2 - Layer 3 Address 0 Register 2 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT (0U) /*! L3A02 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -35690,6 +43518,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR1_REG2 - Layer 3 Address 0 Register 2 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT (0U) /*! L3A12 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -35701,6 +43530,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR2_REG2 - Layer 3 Address 2 Register 2 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT (0U) /*! L3A22 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -35712,6 +43542,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR3_REG2 - Layer 3 Address 3 Register 2 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT (0U) /*! L3A32 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -35723,6 +43554,7 @@ typedef struct { /*! @name MAC_L3_L4_CONTROL3 - Layer 3 and Layer 4 Control of Filter 3 */ /*! @{ */ + #define ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_MASK (0x1U) #define ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_SHIFT (0U) /*! L3PEN3 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination @@ -35731,6 +43563,7 @@ typedef struct { * 0b1..Layer 3 Protocol is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_MASK (0x4U) #define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_SHIFT (2U) /*! L3SAM3 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. @@ -35738,6 +43571,7 @@ typedef struct { * 0b1..Layer 3 IP SA Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_MASK (0x8U) #define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_SHIFT (3U) /*! L3SAIM3 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address @@ -35746,6 +43580,7 @@ typedef struct { * 0b1..Layer 3 IP SA Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_MASK (0x10U) #define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_SHIFT (4U) /*! L3DAM3 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. @@ -35753,6 +43588,7 @@ typedef struct { * 0b1..Layer 3 IP DA Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_MASK (0x20U) #define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_SHIFT (5U) /*! L3DAIM3 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination @@ -35761,18 +43597,21 @@ typedef struct { * 0b1..Layer 3 IP DA Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_MASK (0x7C0U) #define ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT (6U) /*! L3HSBM3 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower * bits of IP Source Address that are masked for matching in the IPv4 packets. */ #define ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_MASK (0xF800U) #define ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT (11U) /*! L3HDBM3 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher * bits of IP Destination Address that are matched in the IPv4 packets. */ #define ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_MASK (0x10000U) #define ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_SHIFT (16U) /*! L4PEN3 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number @@ -35781,6 +43620,7 @@ typedef struct { * 0b1..Layer 4 Protocol is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_MASK (0x40000U) #define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_SHIFT (18U) /*! L4SPM3 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. @@ -35788,6 +43628,7 @@ typedef struct { * 0b1..Layer 4 Source Port Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_MASK (0x80000U) #define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_SHIFT (19U) /*! L4SPIM3 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port @@ -35796,6 +43637,7 @@ typedef struct { * 0b1..Layer 4 Source Port Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_MASK (0x100000U) #define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_SHIFT (20U) /*! L4DPM3 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination @@ -35804,6 +43646,7 @@ typedef struct { * 0b1..Layer 4 Destination Port Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_MASK (0x200000U) #define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_SHIFT (21U) /*! L4DPIM3 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 @@ -35812,12 +43655,14 @@ typedef struct { * 0b1..Layer 4 Destination Port Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_MASK (0x7000000U) #define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_SHIFT (24U) /*! DMCHN3 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number * to which the packet passed by this filter is routed. */ #define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_MASK (0x10000000U) #define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_SHIFT (28U) /*! DMCHEN3 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel @@ -35830,6 +43675,7 @@ typedef struct { /*! @name MAC_LAYER4_ADDRESS3 - Layer 4 Address 3 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_MASK (0xFFFFU) #define ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT (0U) /*! L4SP3 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set @@ -35837,6 +43683,7 @@ typedef struct { * Source Port Number field in the IPv4 or IPv6 packets. */ #define ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_MASK) + #define ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_MASK (0xFFFF0000U) #define ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT (16U) /*! L4DP3 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is @@ -35848,6 +43695,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR0_REG3 - Layer 3 Address 0 Register 3 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT (0U) /*! L3A03 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -35859,6 +43707,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR1_REG3 - Layer 3 Address 1 Register 3 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT (0U) /*! L3A13 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -35870,6 +43719,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR2_REG3 - Layer 3 Address 2 Register 3 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT (0U) /*! L3A23 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -35881,6 +43731,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR3_REG3 - Layer 3 Address 3 Register 3 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT (0U) /*! L3A33 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -35892,6 +43743,7 @@ typedef struct { /*! @name MAC_L3_L4_CONTROL4 - Layer 3 and Layer 4 Control of Filter 4 */ /*! @{ */ + #define ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_MASK (0x1U) #define ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_SHIFT (0U) /*! L3PEN4 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination @@ -35900,6 +43752,7 @@ typedef struct { * 0b1..Layer 3 Protocol is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_MASK (0x4U) #define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_SHIFT (2U) /*! L3SAM4 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. @@ -35907,6 +43760,7 @@ typedef struct { * 0b1..Layer 3 IP SA Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_MASK (0x8U) #define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_SHIFT (3U) /*! L3SAIM4 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address @@ -35915,6 +43769,7 @@ typedef struct { * 0b1..Layer 3 IP SA Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_MASK (0x10U) #define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_SHIFT (4U) /*! L3DAM4 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. @@ -35922,6 +43777,7 @@ typedef struct { * 0b1..Layer 3 IP DA Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_MASK (0x20U) #define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_SHIFT (5U) /*! L3DAIM4 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination @@ -35930,18 +43786,21 @@ typedef struct { * 0b1..Layer 3 IP DA Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_MASK (0x7C0U) #define ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_SHIFT (6U) /*! L3HSBM4 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower * bits of IP Source Address that are masked for matching in the IPv4 packets. */ #define ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_MASK (0xF800U) #define ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_SHIFT (11U) /*! L3HDBM4 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher * bits of IP Destination Address that are matched in the IPv4 packets. */ #define ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_MASK (0x10000U) #define ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_SHIFT (16U) /*! L4PEN4 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number @@ -35950,6 +43809,7 @@ typedef struct { * 0b1..Layer 4 Protocol is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_MASK (0x40000U) #define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_SHIFT (18U) /*! L4SPM4 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. @@ -35957,6 +43817,7 @@ typedef struct { * 0b1..Layer 4 Source Port Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_MASK (0x80000U) #define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_SHIFT (19U) /*! L4SPIM4 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port @@ -35965,6 +43826,7 @@ typedef struct { * 0b1..Layer 4 Source Port Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_MASK (0x100000U) #define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_SHIFT (20U) /*! L4DPM4 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination @@ -35973,6 +43835,7 @@ typedef struct { * 0b1..Layer 4 Destination Port Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_MASK (0x200000U) #define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_SHIFT (21U) /*! L4DPIM4 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 @@ -35981,12 +43844,14 @@ typedef struct { * 0b1..Layer 4 Destination Port Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_MASK (0x7000000U) #define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_SHIFT (24U) /*! DMCHN4 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number * to which the packet passed by this filter is routed. */ #define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_MASK (0x10000000U) #define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_SHIFT (28U) /*! DMCHEN4 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel @@ -35999,6 +43864,7 @@ typedef struct { /*! @name MAC_LAYER4_ADDRESS4 - Layer 4 Address 4 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_MASK (0xFFFFU) #define ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_SHIFT (0U) /*! L4SP4 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set @@ -36006,6 +43872,7 @@ typedef struct { * Source Port Number field in the IPv4 or IPv6 packets. */ #define ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_MASK) + #define ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_MASK (0xFFFF0000U) #define ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_SHIFT (16U) /*! L4DP4 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is @@ -36017,6 +43884,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR0_REG4 - Layer 3 Address 0 Register 4 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_SHIFT (0U) /*! L3A04 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -36028,6 +43896,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR1_REG4 - Layer 3 Address 1 Register 4 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_SHIFT (0U) /*! L3A14 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -36039,6 +43908,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR2_REG4 - Layer 3 Address 2 Register 4 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_SHIFT (0U) /*! L3A24 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -36050,6 +43920,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR3_REG4 - Layer 3 Address 3 Register 4 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_SHIFT (0U) /*! L3A34 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -36061,6 +43932,7 @@ typedef struct { /*! @name MAC_L3_L4_CONTROL5 - Layer 3 and Layer 4 Control of Filter 5 */ /*! @{ */ + #define ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_MASK (0x1U) #define ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_SHIFT (0U) /*! L3PEN5 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination @@ -36069,6 +43941,7 @@ typedef struct { * 0b1..Layer 3 Protocol is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_MASK (0x4U) #define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_SHIFT (2U) /*! L3SAM5 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. @@ -36076,6 +43949,7 @@ typedef struct { * 0b1..Layer 3 IP SA Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_MASK (0x8U) #define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_SHIFT (3U) /*! L3SAIM5 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address @@ -36084,6 +43958,7 @@ typedef struct { * 0b1..Layer 3 IP SA Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_MASK (0x10U) #define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_SHIFT (4U) /*! L3DAM5 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. @@ -36091,6 +43966,7 @@ typedef struct { * 0b1..Layer 3 IP DA Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_MASK (0x20U) #define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_SHIFT (5U) /*! L3DAIM5 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination @@ -36099,18 +43975,21 @@ typedef struct { * 0b1..Layer 3 IP DA Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_MASK (0x7C0U) #define ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_SHIFT (6U) /*! L3HSBM5 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower * bits of IP Source Address that are masked for matching in the IPv4 packets. */ #define ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_MASK (0xF800U) #define ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_SHIFT (11U) /*! L3HDBM5 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher * bits of IP Destination Address that are matched in the IPv4 packets. */ #define ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_MASK (0x10000U) #define ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_SHIFT (16U) /*! L4PEN5 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number @@ -36119,6 +43998,7 @@ typedef struct { * 0b1..Layer 4 Protocol is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_MASK (0x40000U) #define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_SHIFT (18U) /*! L4SPM5 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. @@ -36126,6 +44006,7 @@ typedef struct { * 0b1..Layer 4 Source Port Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_MASK (0x80000U) #define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_SHIFT (19U) /*! L4SPIM5 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port @@ -36134,6 +44015,7 @@ typedef struct { * 0b1..Layer 4 Source Port Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_MASK (0x100000U) #define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_SHIFT (20U) /*! L4DPM5 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination @@ -36142,6 +44024,7 @@ typedef struct { * 0b1..Layer 4 Destination Port Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_MASK (0x200000U) #define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_SHIFT (21U) /*! L4DPIM5 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 @@ -36150,12 +44033,14 @@ typedef struct { * 0b1..Layer 4 Destination Port Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_MASK (0x7000000U) #define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_SHIFT (24U) /*! DMCHN5 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number * to which the packet passed by this filter is routed. */ #define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_MASK (0x10000000U) #define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_SHIFT (28U) /*! DMCHEN5 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel @@ -36168,6 +44053,7 @@ typedef struct { /*! @name MAC_LAYER4_ADDRESS5 - Layer 4 Address 5 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_MASK (0xFFFFU) #define ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_SHIFT (0U) /*! L4SP5 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set @@ -36175,6 +44061,7 @@ typedef struct { * Source Port Number field in the IPv4 or IPv6 packets. */ #define ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_MASK) + #define ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_MASK (0xFFFF0000U) #define ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_SHIFT (16U) /*! L4DP5 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is @@ -36186,6 +44073,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR0_REG5 - Layer 3 Address 0 Register 5 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_SHIFT (0U) /*! L3A05 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -36197,6 +44085,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR1_REG5 - Layer 3 Address 1 Register 5 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_SHIFT (0U) /*! L3A15 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -36208,6 +44097,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR2_REG5 - Layer 3 Address 2 Register 5 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_SHIFT (0U) /*! L3A25 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -36219,6 +44109,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR3_REG5 - Layer 3 Address 3 Register 5 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_SHIFT (0U) /*! L3A35 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -36230,6 +44121,7 @@ typedef struct { /*! @name MAC_L3_L4_CONTROL6 - Layer 3 and Layer 4 Control of Filter 6 */ /*! @{ */ + #define ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_MASK (0x1U) #define ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_SHIFT (0U) /*! L3PEN6 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination @@ -36238,6 +44130,7 @@ typedef struct { * 0b1..Layer 3 Protocol is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_MASK (0x4U) #define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_SHIFT (2U) /*! L3SAM6 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. @@ -36245,6 +44138,7 @@ typedef struct { * 0b1..Layer 3 IP SA Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_MASK (0x8U) #define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_SHIFT (3U) /*! L3SAIM6 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address @@ -36253,6 +44147,7 @@ typedef struct { * 0b1..Layer 3 IP SA Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_MASK (0x10U) #define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_SHIFT (4U) /*! L3DAM6 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. @@ -36260,6 +44155,7 @@ typedef struct { * 0b1..Layer 3 IP DA Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_MASK (0x20U) #define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_SHIFT (5U) /*! L3DAIM6 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination @@ -36268,18 +44164,21 @@ typedef struct { * 0b1..Layer 3 IP DA Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_MASK (0x7C0U) #define ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_SHIFT (6U) /*! L3HSBM6 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower * bits of IP Source Address that are masked for matching in the IPv4 packets. */ #define ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_MASK (0xF800U) #define ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_SHIFT (11U) /*! L3HDBM6 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher * bits of IP Destination Address that are matched in the IPv4 packets. */ #define ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_MASK (0x10000U) #define ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_SHIFT (16U) /*! L4PEN6 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number @@ -36288,6 +44187,7 @@ typedef struct { * 0b1..Layer 4 Protocol is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_MASK (0x40000U) #define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_SHIFT (18U) /*! L4SPM6 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. @@ -36295,6 +44195,7 @@ typedef struct { * 0b1..Layer 4 Source Port Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_MASK (0x80000U) #define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_SHIFT (19U) /*! L4SPIM6 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port @@ -36303,6 +44204,7 @@ typedef struct { * 0b1..Layer 4 Source Port Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_MASK (0x100000U) #define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_SHIFT (20U) /*! L4DPM6 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination @@ -36311,6 +44213,7 @@ typedef struct { * 0b1..Layer 4 Destination Port Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_MASK (0x200000U) #define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_SHIFT (21U) /*! L4DPIM6 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 @@ -36319,12 +44222,14 @@ typedef struct { * 0b1..Layer 4 Destination Port Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_MASK (0x7000000U) #define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_SHIFT (24U) /*! DMCHN6 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number * to which the packet passed by this filter is routed. */ #define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_MASK (0x10000000U) #define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_SHIFT (28U) /*! DMCHEN6 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel @@ -36337,6 +44242,7 @@ typedef struct { /*! @name MAC_LAYER4_ADDRESS6 - Layer 4 Address 6 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_MASK (0xFFFFU) #define ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_SHIFT (0U) /*! L4SP6 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set @@ -36344,6 +44250,7 @@ typedef struct { * Source Port Number field in the IPv4 or IPv6 packets. */ #define ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_MASK) + #define ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_MASK (0xFFFF0000U) #define ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_SHIFT (16U) /*! L4DP6 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is @@ -36355,6 +44262,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR0_REG6 - Layer 3 Address 0 Register 6 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_SHIFT (0U) /*! L3A06 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -36366,6 +44274,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR1_REG6 - Layer 3 Address 1 Register 6 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_SHIFT (0U) /*! L3A16 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -36377,6 +44286,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR2_REG6 - Layer 3 Address 2 Register 6 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_SHIFT (0U) /*! L3A26 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -36388,6 +44298,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR3_REG6 - Layer 3 Address 3 Register 6 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_SHIFT (0U) /*! L3A36 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -36399,6 +44310,7 @@ typedef struct { /*! @name MAC_L3_L4_CONTROL7 - Layer 3 and Layer 4 Control of Filter 0 */ /*! @{ */ + #define ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_MASK (0x1U) #define ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_SHIFT (0U) /*! L3PEN7 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination @@ -36407,6 +44319,7 @@ typedef struct { * 0b1..Layer 3 Protocol is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_MASK (0x4U) #define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_SHIFT (2U) /*! L3SAM7 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching. @@ -36414,6 +44327,7 @@ typedef struct { * 0b1..Layer 3 IP SA Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_MASK (0x8U) #define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_SHIFT (3U) /*! L3SAIM7 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address @@ -36422,6 +44336,7 @@ typedef struct { * 0b1..Layer 3 IP SA Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_MASK (0x10U) #define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_SHIFT (4U) /*! L3DAM7 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching. @@ -36429,6 +44344,7 @@ typedef struct { * 0b1..Layer 3 IP DA Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_MASK (0x20U) #define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_SHIFT (5U) /*! L3DAIM7 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination @@ -36437,18 +44353,21 @@ typedef struct { * 0b1..Layer 3 IP DA Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_MASK (0x7C0U) #define ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_SHIFT (6U) /*! L3HSBM7 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower * bits of IP Source Address that are masked for matching in the IPv4 packets. */ #define ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_MASK (0xF800U) #define ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_SHIFT (11U) /*! L3HDBM7 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher * bits of IP Destination Address that are matched in the IPv4 packets. */ #define ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_MASK (0x10000U) #define ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_SHIFT (16U) /*! L4PEN7 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number @@ -36457,6 +44376,7 @@ typedef struct { * 0b1..Layer 4 Protocol is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_MASK (0x40000U) #define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_SHIFT (18U) /*! L4SPM7 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching. @@ -36464,6 +44384,7 @@ typedef struct { * 0b1..Layer 4 Source Port Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_MASK (0x80000U) #define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_SHIFT (19U) /*! L4SPIM7 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port @@ -36472,6 +44393,7 @@ typedef struct { * 0b1..Layer 4 Source Port Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_MASK (0x100000U) #define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_SHIFT (20U) /*! L4DPM7 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination @@ -36480,6 +44402,7 @@ typedef struct { * 0b1..Layer 4 Destination Port Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_MASK (0x200000U) #define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_SHIFT (21U) /*! L4DPIM7 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4 @@ -36488,12 +44411,14 @@ typedef struct { * 0b1..Layer 4 Destination Port Inverse Match is enabled */ #define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_MASK (0x7000000U) #define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_SHIFT (24U) /*! DMCHN7 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number * to which the packet passed by this filter is routed. */ #define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_MASK) + #define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_MASK (0x10000000U) #define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_SHIFT (28U) /*! DMCHEN7 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel @@ -36506,6 +44431,7 @@ typedef struct { /*! @name MAC_LAYER4_ADDRESS7 - Layer 4 Address 7 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_MASK (0xFFFFU) #define ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_SHIFT (0U) /*! L4SP7 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set @@ -36513,6 +44439,7 @@ typedef struct { * Source Port Number field in the IPv4 or IPv6 packets. */ #define ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_MASK) + #define ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_MASK (0xFFFF0000U) #define ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_SHIFT (16U) /*! L4DP7 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is @@ -36524,6 +44451,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR0_REG7 - Layer 3 Address 0 Register 7 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_SHIFT (0U) /*! L3A07 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -36535,6 +44463,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR1_REG7 - Layer 3 Address 1 Register 7 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_SHIFT (0U) /*! L3A17 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -36546,6 +44475,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR2_REG7 - Layer 3 Address 2 Register 7 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_SHIFT (0U) /*! L3A27 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -36557,6 +44487,7 @@ typedef struct { /*! @name MAC_LAYER3_ADDR3_REG7 - Layer 3 Address 3 Register 7 */ /*! @{ */ + #define ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_SHIFT (0U) /*! L3A37 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the @@ -36568,6 +44499,7 @@ typedef struct { /*! @name MAC_TIMESTAMP_CONTROL - Timestamp Control */ /*! @{ */ + #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_MASK (0x1U) #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT (0U) /*! TSENA - Enable Timestamp When this bit is set, the timestamp is added for Transmit and Receive packets. @@ -36575,6 +44507,7 @@ typedef struct { * 0b1..Timestamp is enabled */ #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_MASK) + #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK (0x2U) #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT (1U) /*! TSCFUPDT - Fine or Coarse Timestamp Update When this bit is set, the Fine method is used to update system timestamp. @@ -36582,6 +44515,7 @@ typedef struct { * 0b1..Fine method is used to update system timestamp */ #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK) + #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_MASK (0x4U) #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT (2U) /*! TSINIT - Initialize Timestamp When this bit is set, the system time is initialized (overwritten) @@ -36591,6 +44525,7 @@ typedef struct { * 0b1..Timestamp is initialized */ #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_MASK) + #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK (0x8U) #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT (3U) /*! TSUPDT - Update Timestamp When this bit is set, the system time is updated (added or subtracted) @@ -36600,6 +44535,7 @@ typedef struct { * 0b1..Timestamp is updated */ #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK) + #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK (0x20U) #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT (5U) /*! TSADDREG - Update Addend Register When this bit is set, the content of the Timestamp Addend @@ -36608,6 +44544,7 @@ typedef struct { * 0b1..Addend Register is updated */ #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK) + #define ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_MASK (0x40U) #define ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_SHIFT (6U) /*! PTGE - Presentation Time Generation Enable When this bit is set the Presentation Time generation will be enabled. @@ -36615,6 +44552,7 @@ typedef struct { * 0b1..Presentation Time Generation is enabled */ #define ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_MASK) + #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_MASK (0x100U) #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT (8U) /*! TSENALL - Enable Timestamp for All Packets When this bit is set, the timestamp snapshot is @@ -36623,6 +44561,7 @@ typedef struct { * 0b1..Timestamp for All Packets enabled */ #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_MASK) + #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK (0x200U) #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT (9U) /*! TSCTRLSSR - Timestamp Digital or Binary Rollover Control When this bit is set, the Timestamp Low @@ -36632,6 +44571,7 @@ typedef struct { * 0b1..Timestamp Digital or Binary Rollover Control is enabled */ #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK) + #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK (0x400U) #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT (10U) /*! TSVER2ENA - Enable PTP Packet Processing for Version 2 Format When this bit is set, the IEEE @@ -36640,6 +44580,7 @@ typedef struct { * 0b1..PTP Packet Processing for Version 2 Format is enabled */ #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK) + #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK (0x800U) #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT (11U) /*! TSIPENA - Enable Processing of PTP over Ethernet Packets When this bit is set, the MAC receiver @@ -36648,6 +44589,7 @@ typedef struct { * 0b1..Processing of PTP over Ethernet Packets is enabled */ #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK) + #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK (0x1000U) #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT (12U) /*! TSIPV6ENA - Enable Processing of PTP Packets Sent over IPv6-UDP When this bit is set, the MAC @@ -36656,6 +44598,7 @@ typedef struct { * 0b1..Processing of PTP Packets Sent over IPv6-UDP is enabled */ #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK) + #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK (0x2000U) #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT (13U) /*! TSIPV4ENA - Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set, the MAC @@ -36664,6 +44607,7 @@ typedef struct { * 0b1..Processing of PTP Packets Sent over IPv4-UDP is enabled */ #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK) + #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK (0x4000U) #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT (14U) /*! TSEVNTENA - Enable Timestamp Snapshot for Event Messages When this bit is set, the timestamp @@ -36672,6 +44616,7 @@ typedef struct { * 0b1..Timestamp Snapshot for Event Messages is enabled */ #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK) + #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK (0x8000U) #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT (15U) /*! TSMSTRENA - Enable Snapshot for Messages Relevant to Master When this bit is set, the snapshot @@ -36680,12 +44625,14 @@ typedef struct { * 0b1..Snapshot for Messages Relevant to Master is enabled */ #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK) + #define ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK (0x30000U) #define ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT (16U) /*! SNAPTYPSEL - Select PTP packets for Taking Snapshots These bits, along with Bits 15 and 14, * decide the set of PTP packet types for which snapshot needs to be taken. */ #define ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK) + #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK (0x40000U) #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT (18U) /*! TSENMACADDR - Enable MAC Address for PTP Packet Filtering When this bit is set, the DA MAC @@ -36695,6 +44642,7 @@ typedef struct { * 0b1..MAC Address for PTP Packet Filtering is enabled */ #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK) + #define ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_MASK (0x80000U) #define ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_SHIFT (19U) /*! CSC - Enable checksum correction during OST for PTP over UDP/IPv4 packets When this bit is set, @@ -36705,6 +44653,7 @@ typedef struct { * 0b1..checksum correction during OST for PTP over UDP/IPv4 packets is enabled */ #define ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_MASK) + #define ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_MASK (0x100000U) #define ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT (20U) /*! ESTI - External System Time Input When this bit is set, the MAC uses the external 64-bit @@ -36715,6 +44664,7 @@ typedef struct { * 0b1..External System Time Input is enabled */ #define ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_MASK) + #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK (0x1000000U) #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT (24U) /*! TXTSSTSM - Transmit Timestamp Status Mode When this bit is set, the MAC overwrites the earlier @@ -36723,6 +44673,7 @@ typedef struct { * 0b1..Transmit Timestamp Status Mode is enabled */ #define ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK) + #define ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK (0x10000000U) #define ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT (28U) /*! AV8021ASMEN - AV 802. @@ -36734,12 +44685,14 @@ typedef struct { /*! @name MAC_SUB_SECOND_INCREMENT - Subsecond Increment */ /*! @{ */ + #define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK (0xFF00U) #define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT (8U) /*! SNSINC - Sub-nanosecond Increment Value This field contains the sub-nanosecond increment value, * represented in nanoseconds multiplied by 2^8. */ #define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT)) & ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK) + #define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_MASK (0xFF0000U) #define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT (16U) /*! SSINC - Sub-second Increment Value The value programmed in this field is accumulated every clock @@ -36750,6 +44703,7 @@ typedef struct { /*! @name MAC_SYSTEM_TIME_SECONDS - System Time Seconds */ /*! @{ */ + #define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT (0U) /*! TSS - Timestamp Second The value in this field indicates the current value in seconds of the @@ -36760,6 +44714,7 @@ typedef struct { /*! @name MAC_SYSTEM_TIME_NANOSECONDS - System Time Nanoseconds */ /*! @{ */ + #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK (0x7FFFFFFFU) #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT (0U) /*! TSSS - Timestamp Sub Seconds The value in this field has the sub-second representation of time, with an accuracy of 0. @@ -36769,6 +44724,7 @@ typedef struct { /*! @name MAC_SYSTEM_TIME_SECONDS_UPDATE - System Time Seconds Update */ /*! @{ */ + #define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT (0U) /*! TSS - Timestamp Seconds The value in this field is the seconds part of the update. @@ -36778,11 +44734,13 @@ typedef struct { /*! @name MAC_SYSTEM_TIME_NANOSECONDS_UPDATE - System Time Nanoseconds Update */ /*! @{ */ + #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK (0x7FFFFFFFU) #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT (0U) /*! TSSS - Timestamp Sub Seconds The value in this field is the sub-seconds part of the update. */ #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK) + #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK (0x80000000U) #define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_SHIFT (31U) /*! ADDSUB - Add or Subtract Time When this bit is set, the time value is subtracted with the contents of the update register. @@ -36794,6 +44752,7 @@ typedef struct { /*! @name MAC_TIMESTAMP_ADDEND - Timestamp Addend */ /*! @{ */ + #define ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT (0U) /*! TSAR - Timestamp Addend Register This field indicates the 32-bit time value to be added to the @@ -36804,6 +44763,7 @@ typedef struct { /*! @name MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS - System Time - Higher Word Seconds */ /*! @{ */ + #define ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK (0xFFFFU) #define ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT (0U) /*! TSHWR - Timestamp Higher Word Register This field contains the most-significant 16-bits of timestamp seconds value. @@ -36813,6 +44773,7 @@ typedef struct { /*! @name MAC_TIMESTAMP_STATUS - Timestamp Status */ /*! @{ */ + #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_MASK (0x1U) #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT (0U) /*! TSSOVF - Timestamp Seconds Overflow When this bit is set, it indicates that the seconds value of @@ -36821,6 +44782,7 @@ typedef struct { * 0b0..Timestamp Seconds Overflow status not detected */ #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_MASK) + #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK (0x2U) #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT (1U) /*! TSTARGT0 - Timestamp Target Time Reached When set, this bit indicates that the value of system @@ -36830,6 +44792,7 @@ typedef struct { * 0b0..Timestamp Target Time Reached status not detected */ #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK) + #define ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_MASK (0x4U) #define ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_SHIFT (2U) /*! AUXTSTRIG - Auxiliary Timestamp Trigger Snapshot This bit is set high when the auxiliary snapshot is written to the FIFO. @@ -36837,6 +44800,7 @@ typedef struct { * 0b0..Auxiliary Timestamp Trigger Snapshot status not detected */ #define ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_MASK) + #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK (0x8U) #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT (3U) /*! TSTRGTERR0 - Timestamp Target Time Error This bit is set when the latest target time programmed @@ -36845,6 +44809,7 @@ typedef struct { * 0b0..Timestamp Target Time Error status not detected */ #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK) + #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_MASK (0x10U) #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_SHIFT (4U) /*! TSTARGT1 - Timestamp Target Time Reached for Target Time PPS1 When set, this bit indicates that @@ -36854,6 +44819,7 @@ typedef struct { * 0b0..Timestamp Target Time Reached for Target Time PPS1 status not detected */ #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_MASK) + #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_MASK (0x20U) #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_SHIFT (5U) /*! TSTRGTERR1 - Timestamp Target Time Error This bit is set when the latest target time programmed @@ -36862,6 +44828,7 @@ typedef struct { * 0b0..Timestamp Target Time Error status not detected */ #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_MASK) + #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_MASK (0x40U) #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_SHIFT (6U) /*! TSTARGT2 - Timestamp Target Time Reached for Target Time PPS2 When set, this bit indicates that @@ -36871,6 +44838,7 @@ typedef struct { * 0b0..Timestamp Target Time Reached for Target Time PPS2 status not detected */ #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_MASK) + #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_MASK (0x80U) #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_SHIFT (7U) /*! TSTRGTERR2 - Timestamp Target Time Error This bit is set when the latest target time programmed @@ -36879,6 +44847,7 @@ typedef struct { * 0b0..Timestamp Target Time Error status not detected */ #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_MASK) + #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_MASK (0x100U) #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_SHIFT (8U) /*! TSTARGT3 - Timestamp Target Time Reached for Target Time PPS3 When this bit is set, it indicates @@ -36888,6 +44857,7 @@ typedef struct { * 0b0..Timestamp Target Time Reached for Target Time PPS3 status not detected */ #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_MASK) + #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_MASK (0x200U) #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_SHIFT (9U) /*! TSTRGTERR3 - Timestamp Target Time Error This bit is set when the latest target time programmed @@ -36896,6 +44866,7 @@ typedef struct { * 0b0..Timestamp Target Time Error status not detected */ #define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_MASK) + #define ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK (0x8000U) #define ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT (15U) /*! TXTSSIS - Tx Timestamp Status Interrupt Status In non-EQOS_CORE configurations when drop @@ -36905,12 +44876,14 @@ typedef struct { * 0b0..Tx Timestamp Status Interrupt status not detected */ #define ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK) + #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_MASK (0xF0000U) #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_SHIFT (16U) /*! ATSSTN - Auxiliary Timestamp Snapshot Trigger Identifier These bits identify the Auxiliary * trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. */ #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_MASK) + #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_MASK (0x1000000U) #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_SHIFT (24U) /*! ATSSTM - Auxiliary Timestamp Snapshot Trigger Missed This bit is set when the Auxiliary @@ -36919,6 +44892,7 @@ typedef struct { * 0b0..Auxiliary Timestamp Snapshot Trigger Missed status not detected */ #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_MASK) + #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_MASK (0x3E000000U) #define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_SHIFT (25U) /*! ATSNS - Number of Auxiliary Timestamp Snapshots This field indicates the number of Snapshots available in the FIFO. @@ -36928,12 +44902,14 @@ typedef struct { /*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS - Transmit Timestamp Status Nanoseconds */ /*! @{ */ + #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK (0x7FFFFFFFU) #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT (0U) /*! TXTSSLO - Transmit Timestamp Status Low This field contains the 31 bits of the Nanoseconds field * of the Transmit packet's captured timestamp. */ #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT)) & ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK) + #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_MASK (0x80000000U) #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_SHIFT (31U) /*! TXTSSMIS - Transmit Timestamp Status Missed When this bit is set, it indicates one of the @@ -36948,6 +44924,7 @@ typedef struct { /*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS - Transmit Timestamp Status Seconds */ /*! @{ */ + #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT (0U) /*! TXTSSHI - Transmit Timestamp Status High This field contains the lower 32 bits of the Seconds @@ -36958,6 +44935,7 @@ typedef struct { /*! @name MAC_AUXILIARY_CONTROL - Auxiliary Timestamp Control */ /*! @{ */ + #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_MASK (0x1U) #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_SHIFT (0U) /*! ATSFC - Auxiliary Snapshot FIFO Clear When set, this bit resets the pointers of the Auxiliary Snapshot FIFO. @@ -36965,6 +44943,7 @@ typedef struct { * 0b1..Auxiliary Snapshot FIFO Clear is enabled */ #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_MASK) + #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_MASK (0x10U) #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_SHIFT (4U) /*! ATSEN0 - Auxiliary Snapshot 0 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 0. @@ -36972,6 +44951,7 @@ typedef struct { * 0b1..Auxiliary Snapshot $i is enabled */ #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_MASK) + #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_MASK (0x20U) #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_SHIFT (5U) /*! ATSEN1 - Auxiliary Snapshot 1 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 1. @@ -36979,6 +44959,7 @@ typedef struct { * 0b1..Auxiliary Snapshot $i is enabled */ #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_MASK) + #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_MASK (0x40U) #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_SHIFT (6U) /*! ATSEN2 - Auxiliary Snapshot 2 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 2. @@ -36986,6 +44967,7 @@ typedef struct { * 0b1..Auxiliary Snapshot $i is enabled */ #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_MASK) + #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_MASK (0x80U) #define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_SHIFT (7U) /*! ATSEN3 - Auxiliary Snapshot 3 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 3. @@ -36997,6 +44979,7 @@ typedef struct { /*! @name MAC_AUXILIARY_TIMESTAMP_NANOSECONDS - Auxiliary Timestamp Nanoseconds */ /*! @{ */ + #define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_MASK (0x7FFFFFFFU) #define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_SHIFT (0U) /*! AUXTSLO - Auxiliary Timestamp Contains the lower 31 bits (nanoseconds field) of the auxiliary timestamp. @@ -37006,6 +44989,7 @@ typedef struct { /*! @name MAC_AUXILIARY_TIMESTAMP_SECONDS - Auxiliary Timestamp Seconds */ /*! @{ */ + #define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_SHIFT (0U) /*! AUXTSHI - Auxiliary Timestamp Contains the lower 32 bits of the Seconds field of the auxiliary timestamp. @@ -37015,6 +44999,7 @@ typedef struct { /*! @name MAC_TIMESTAMP_INGRESS_ASYM_CORR - Timestamp Ingress Asymmetry Correction */ /*! @{ */ + #define ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT (0U) /*! OSTIAC - One-Step Timestamp Ingress Asymmetry Correction This field contains the ingress path @@ -37025,6 +45010,7 @@ typedef struct { /*! @name MAC_TIMESTAMP_EGRESS_ASYM_CORR - imestamp Egress Asymmetry Correction */ /*! @{ */ + #define ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT (0U) /*! OSTEAC - One-Step Timestamp Egress Asymmetry Correction This field contains the egress path @@ -37035,6 +45021,7 @@ typedef struct { /*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND - Timestamp Ingress Correction Nanosecond */ /*! @{ */ + #define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0U) /*! TSIC - Timestamp Ingress Correction This field contains the ingress path correction value as @@ -37045,6 +45032,7 @@ typedef struct { /*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND - Timestamp Egress Correction Nanosecond */ /*! @{ */ + #define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0U) /*! TSEC - Timestamp Egress Correction This field contains the nanoseconds part of the egress path @@ -37055,6 +45043,7 @@ typedef struct { /*! @name MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC - Timestamp Ingress Correction Subnanosecond */ /*! @{ */ + #define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK (0xFF00U) #define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT (8U) /*! TSICSNS - Timestamp Ingress Correction, sub-nanoseconds This field contains the sub-nanoseconds @@ -37065,6 +45054,7 @@ typedef struct { /*! @name MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC - Timestamp Egress Correction Subnanosecond */ /*! @{ */ + #define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK (0xFF00U) #define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT (8U) /*! TSECSNS - Timestamp Egress Correction, sub-nanoseconds This field contains the sub-nanoseconds @@ -37075,6 +45065,7 @@ typedef struct { /*! @name MAC_TIMESTAMP_INGRESS_LATENCY - Timestamp Ingress Latency */ /*! @{ */ + #define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK (0xFF00U) #define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT (8U) /*! ITLSNS - Ingress Timestamp Latency, in nanoseconds This register holds the average latency in @@ -37082,6 +45073,7 @@ typedef struct { * ingress timestamp is taken. */ #define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK) + #define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK (0xFFF0000U) #define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT (16U) /*! ITLNS - Ingress Timestamp Latency, in sub-nanoseconds This register holds the average latency in @@ -37093,6 +45085,7 @@ typedef struct { /*! @name MAC_TIMESTAMP_EGRESS_LATENCY - Timestamp Egress Latency */ /*! @{ */ + #define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK (0xFF00U) #define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT (8U) /*! ETLSNS - Egress Timestamp Latency, in sub-nanoseconds This register holds the average latency in @@ -37100,6 +45093,7 @@ typedef struct { * the output ports (phy_txd_o) of the MAC. */ #define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK) + #define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK (0xFFF0000U) #define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT (16U) /*! ETLNS - Egress Timestamp Latency, in nanoseconds This register holds the average latency in @@ -37111,11 +45105,13 @@ typedef struct { /*! @name MAC_PPS_CONTROL - PPS Control */ /*! @{ */ + #define ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK (0xFU) #define ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT (0U) /*! PPSCTRL_PPSCMD - PPS Output Frequency Control This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. */ #define ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK) + #define ENET_QOS_MAC_PPS_CONTROL_PPSEN0_MASK (0x10U) #define ENET_QOS_MAC_PPS_CONTROL_PPSEN0_SHIFT (4U) /*! PPSEN0 - Flexible PPS Output Mode Enable When this bit is set, Bits[3:0] function as PPSCMD. @@ -37123,6 +45119,7 @@ typedef struct { * 0b1..Flexible PPS Output Mode is enabled */ #define ENET_QOS_MAC_PPS_CONTROL_PPSEN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSEN0_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSEN0_MASK) + #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_MASK (0x60U) #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT (5U) /*! TRGTMODSEL0 - Target Time Register Mode for PPS0 Output This field indicates the Target Time @@ -37136,6 +45133,7 @@ typedef struct { * 0b01..Reserved */ #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_MASK) + #define ENET_QOS_MAC_PPS_CONTROL_MCGREN0_MASK (0x80U) #define ENET_QOS_MAC_PPS_CONTROL_MCGREN0_SHIFT (7U) /*! MCGREN0 - MCGR Mode Enable for PPS0 Output This field enables the 0th PPS instance to operate in PPS or MCGR mode. @@ -37143,11 +45141,13 @@ typedef struct { * 0b0..0th PPS instance is enabled to operate in PPS mode */ #define ENET_QOS_MAC_PPS_CONTROL_MCGREN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN0_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN0_MASK) + #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_MASK (0xF00U) #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_SHIFT (8U) /*! PPSCMD1 - Flexible PPS1 Output Control This field controls the flexible PPS1 output (ptp_pps_o[1]) signal. */ #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_MASK) + #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_MASK (0x6000U) #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT (13U) /*! TRGTMODSEL1 - Target Time Register Mode for PPS1 Output This field indicates the Target Time @@ -37161,6 +45161,7 @@ typedef struct { * 0b01..Reserved */ #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_MASK) + #define ENET_QOS_MAC_PPS_CONTROL_MCGREN1_MASK (0x8000U) #define ENET_QOS_MAC_PPS_CONTROL_MCGREN1_SHIFT (15U) /*! MCGREN1 - MCGR Mode Enable for PPS1 Output This field enables the 1st PPS instance to operate in PPS or MCGR mode. @@ -37168,11 +45169,13 @@ typedef struct { * 0b1..1st PPS instance is enabled to operate in PPS or MCGR mode */ #define ENET_QOS_MAC_PPS_CONTROL_MCGREN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN1_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN1_MASK) + #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_MASK (0xF0000U) #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_SHIFT (16U) /*! PPSCMD2 - Flexible PPS2 Output Control This field controls the flexible PPS2 output (ptp_pps_o[2]) signal. */ #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_MASK) + #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_MASK (0x600000U) #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT (21U) /*! TRGTMODSEL2 - Target Time Register Mode for PPS2 Output This field indicates the Target Time @@ -37186,6 +45189,7 @@ typedef struct { * 0b01..Reserved */ #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_MASK) + #define ENET_QOS_MAC_PPS_CONTROL_MCGREN2_MASK (0x800000U) #define ENET_QOS_MAC_PPS_CONTROL_MCGREN2_SHIFT (23U) /*! MCGREN2 - MCGR Mode Enable for PPS2 Output This field enables the 2nd PPS instance to operate in PPS or MCGR mode. @@ -37193,11 +45197,13 @@ typedef struct { * 0b1..2nd PPS instance is enabled to operate in PPS or MCGR mode */ #define ENET_QOS_MAC_PPS_CONTROL_MCGREN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN2_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN2_MASK) + #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_MASK (0xF000000U) #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_SHIFT (24U) /*! PPSCMD3 - Flexible PPS3 Output Control This field controls the flexible PPS3 output (ptp_pps_o[3]) signal. */ #define ENET_QOS_MAC_PPS_CONTROL_PPSCMD3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_MASK) + #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_MASK (0x60000000U) #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT (29U) /*! TRGTMODSEL3 - Target Time Register Mode for PPS3 Output This field indicates the Target Time @@ -37211,6 +45217,7 @@ typedef struct { * 0b01..Reserved */ #define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_MASK) + #define ENET_QOS_MAC_PPS_CONTROL_MCGREN3_MASK (0x80000000U) #define ENET_QOS_MAC_PPS_CONTROL_MCGREN3_SHIFT (31U) /*! MCGREN3 - MCGR Mode Enable for PPS3 Output This field enables the 3rd PPS instance to operate in PPS or MCGR mode. @@ -37220,6 +45227,7 @@ typedef struct { /*! @name MAC_PPS0_TARGET_TIME_SECONDS - PPS0 Target Time Seconds */ /*! @{ */ + #define ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT (0U) /*! TSTRH0 - PPS Target Time Seconds Register This field stores the time in seconds. @@ -37229,11 +45237,13 @@ typedef struct { /*! @name MAC_PPS0_TARGET_TIME_NANOSECONDS - PPS0 Target Time Nanoseconds */ /*! @{ */ + #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK (0x7FFFFFFFU) #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT (0U) /*! TTSL0 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. */ #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT)) & ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK) + #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_MASK (0x80000000U) #define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_SHIFT (31U) /*! TRGTBUSY0 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the @@ -37246,6 +45256,7 @@ typedef struct { /*! @name MAC_PPS0_INTERVAL - PPS0 Interval */ /*! @{ */ + #define ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_SHIFT (0U) /*! PPSINT0 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output. @@ -37255,6 +45266,7 @@ typedef struct { /*! @name MAC_PPS0_WIDTH - PPS0 Width */ /*! @{ */ + #define ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT (0U) /*! PPSWIDTH0 - PPS Output Signal Width These bits store the width between the rising edge and @@ -37265,6 +45277,7 @@ typedef struct { /*! @name MAC_PPS1_TARGET_TIME_SECONDS - PPS1 Target Time Seconds */ /*! @{ */ + #define ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT (0U) /*! TSTRH1 - PPS Target Time Seconds Register This field stores the time in seconds. @@ -37274,11 +45287,13 @@ typedef struct { /*! @name MAC_PPS1_TARGET_TIME_NANOSECONDS - PPS1 Target Time Nanoseconds */ /*! @{ */ + #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK (0x7FFFFFFFU) #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT (0U) /*! TTSL1 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. */ #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT)) & ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK) + #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_MASK (0x80000000U) #define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_SHIFT (31U) /*! TRGTBUSY1 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the @@ -37291,6 +45306,7 @@ typedef struct { /*! @name MAC_PPS1_INTERVAL - PPS1 Interval */ /*! @{ */ + #define ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_SHIFT (0U) /*! PPSINT1 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output. @@ -37300,6 +45316,7 @@ typedef struct { /*! @name MAC_PPS1_WIDTH - PPS1 Width */ /*! @{ */ + #define ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT (0U) /*! PPSWIDTH1 - PPS Output Signal Width These bits store the width between the rising edge and @@ -37310,6 +45327,7 @@ typedef struct { /*! @name MAC_PPS2_TARGET_TIME_SECONDS - PPS2 Target Time Seconds */ /*! @{ */ + #define ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT (0U) /*! TSTRH2 - PPS Target Time Seconds Register This field stores the time in seconds. @@ -37319,11 +45337,13 @@ typedef struct { /*! @name MAC_PPS2_TARGET_TIME_NANOSECONDS - PPS2 Target Time Nanoseconds */ /*! @{ */ + #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK (0x7FFFFFFFU) #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT (0U) /*! TTSL2 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. */ #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT)) & ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK) + #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_MASK (0x80000000U) #define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_SHIFT (31U) /*! TRGTBUSY2 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the @@ -37336,6 +45356,7 @@ typedef struct { /*! @name MAC_PPS2_INTERVAL - PPS2 Interval */ /*! @{ */ + #define ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_SHIFT (0U) /*! PPSINT2 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output. @@ -37345,6 +45366,7 @@ typedef struct { /*! @name MAC_PPS2_WIDTH - PPS2 Width */ /*! @{ */ + #define ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT (0U) /*! PPSWIDTH2 - PPS Output Signal Width These bits store the width between the rising edge and @@ -37355,6 +45377,7 @@ typedef struct { /*! @name MAC_PPS3_TARGET_TIME_SECONDS - PPS3 Target Time Seconds */ /*! @{ */ + #define ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT (0U) /*! TSTRH3 - PPS Target Time Seconds Register This field stores the time in seconds. @@ -37364,11 +45387,13 @@ typedef struct { /*! @name MAC_PPS3_TARGET_TIME_NANOSECONDS - PPS3 Target Time Nanoseconds */ /*! @{ */ + #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK (0x7FFFFFFFU) #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT (0U) /*! TTSL3 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. */ #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT)) & ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK) + #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_MASK (0x80000000U) #define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_SHIFT (31U) /*! TRGTBUSY3 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the @@ -37381,6 +45406,7 @@ typedef struct { /*! @name MAC_PPS3_INTERVAL - PPS3 Interval */ /*! @{ */ + #define ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_SHIFT (0U) /*! PPSINT3 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output. @@ -37390,6 +45416,7 @@ typedef struct { /*! @name MAC_PPS3_WIDTH - PPS3 Width */ /*! @{ */ + #define ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT (0U) /*! PPSWIDTH3 - PPS Output Signal Width These bits store the width between the rising edge and @@ -37400,6 +45427,7 @@ typedef struct { /*! @name MAC_PTO_CONTROL - PTP Offload Engine Control */ /*! @{ */ + #define ENET_QOS_MAC_PTO_CONTROL_PTOEN_MASK (0x1U) #define ENET_QOS_MAC_PTO_CONTROL_PTOEN_SHIFT (0U) /*! PTOEN - PTP Offload Enable When this bit is set, the PTP Offload feature is enabled. @@ -37407,6 +45435,7 @@ typedef struct { * 0b1..PTP Offload feature is enabled */ #define ENET_QOS_MAC_PTO_CONTROL_PTOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_PTOEN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_PTOEN_MASK) + #define ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_MASK (0x2U) #define ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_SHIFT (1U) /*! ASYNCEN - Automatic PTP SYNC message Enable When this bit is set, PTP SYNC message is generated @@ -37416,6 +45445,7 @@ typedef struct { * 0b1..Automatic PTP SYNC message is enabled */ #define ENET_QOS_MAC_PTO_CONTROL_ASYNCEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_MASK) + #define ENET_QOS_MAC_PTO_CONTROL_APDREQEN_MASK (0x4U) #define ENET_QOS_MAC_PTO_CONTROL_APDREQEN_SHIFT (2U) /*! APDREQEN - Automatic PTP Pdelay_Req message Enable When this bit is set, PTP Pdelay_Req message @@ -37425,6 +45455,7 @@ typedef struct { * 0b1..Automatic PTP Pdelay_Req message is enabled */ #define ENET_QOS_MAC_PTO_CONTROL_APDREQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_APDREQEN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_APDREQEN_MASK) + #define ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_MASK (0x10U) #define ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_SHIFT (4U) /*! ASYNCTRIG - Automatic PTP SYNC message Trigger When this bit is set, one PTP SYNC message is transmitted. @@ -37432,6 +45463,7 @@ typedef struct { * 0b1..Automatic PTP SYNC message Trigger is enabled */ #define ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_MASK) + #define ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_MASK (0x20U) #define ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_SHIFT (5U) /*! APDREQTRIG - Automatic PTP Pdelay_Req message Trigger When this bit is set, one PTP Pdelay_Req message is transmitted. @@ -37439,6 +45471,7 @@ typedef struct { * 0b1..Automatic PTP Pdelay_Req message Trigger is enabled */ #define ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_MASK) + #define ENET_QOS_MAC_PTO_CONTROL_DRRDIS_MASK (0x40U) #define ENET_QOS_MAC_PTO_CONTROL_DRRDIS_SHIFT (6U) /*! DRRDIS - Disable PTO Delay Request/Response response generation When this bit is set, the Delay @@ -37448,6 +45481,7 @@ typedef struct { * 0b0..PTO Delay Request/Response response generation is enabled */ #define ENET_QOS_MAC_PTO_CONTROL_DRRDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_DRRDIS_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_DRRDIS_MASK) + #define ENET_QOS_MAC_PTO_CONTROL_PDRDIS_MASK (0x80U) #define ENET_QOS_MAC_PTO_CONTROL_PDRDIS_SHIFT (7U) /*! PDRDIS - Disable Peer Delay Response response generation When this bit is set, the Peer Delay @@ -37457,6 +45491,7 @@ typedef struct { * 0b0..Peer Delay Response response generation is enabled */ #define ENET_QOS_MAC_PTO_CONTROL_PDRDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_PDRDIS_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_PDRDIS_MASK) + #define ENET_QOS_MAC_PTO_CONTROL_DN_MASK (0xFF00U) #define ENET_QOS_MAC_PTO_CONTROL_DN_SHIFT (8U) /*! DN - Domain Number This field indicates the domain Number in which the PTP node is operating. @@ -37466,6 +45501,7 @@ typedef struct { /*! @name MAC_SOURCE_PORT_IDENTITY0 - Source Port Identity 0 */ /*! @{ */ + #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_SHIFT (0U) /*! SPI0 - Source Port Identity 0 This field indicates bits [31:0] of sourcePortIdentity of PTP node. @@ -37475,6 +45511,7 @@ typedef struct { /*! @name MAC_SOURCE_PORT_IDENTITY1 - Source Port Identity 1 */ /*! @{ */ + #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_MASK (0xFFFFFFFFU) #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_SHIFT (0U) /*! SPI1 - Source Port Identity 1 This field indicates bits [63:32] of sourcePortIdentity of PTP node. @@ -37484,6 +45521,7 @@ typedef struct { /*! @name MAC_SOURCE_PORT_IDENTITY2 - Source Port Identity 2 */ /*! @{ */ + #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_MASK (0xFFFFU) #define ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_SHIFT (0U) /*! SPI2 - Source Port Identity 2 This field indicates bits [79:64] of sourcePortIdentity of PTP node. @@ -37493,12 +45531,14 @@ typedef struct { /*! @name MAC_LOG_MESSAGE_INTERVAL - Log Message Interval */ /*! @{ */ + #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_MASK (0xFFU) #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_SHIFT (0U) /*! LSI - Log Sync Interval This field indicates the periodicity of the automatically generated SYNC * message when the PTP node is Master. */ #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_SHIFT)) & ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_MASK) + #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_MASK (0x700U) #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_SHIFT (8U) /*! DRSYNCR - Delay_Req to SYNC Ratio In Slave mode, it is used for controlling frequency of Delay_Req messages transmitted. @@ -37511,6 +45551,7 @@ typedef struct { * 0b011..for every 8 SYNC messages */ #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_SHIFT)) & ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_MASK) + #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_MASK (0xFF000000U) #define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_SHIFT (24U) /*! LMPDRI - Log Min Pdelay_Req Interval This field indicates logMinPdelayReqInterval of PTP node. @@ -37520,6 +45561,7 @@ typedef struct { /*! @name MTL_OPERATION_MODE - MTL Operation Mode */ /*! @{ */ + #define ENET_QOS_MTL_OPERATION_MODE_DTXSTS_MASK (0x2U) #define ENET_QOS_MTL_OPERATION_MODE_DTXSTS_SHIFT (1U) /*! DTXSTS - Drop Transmit Status When this bit is set, the Tx packet status received from the MAC is dropped in the MTL. @@ -37527,6 +45569,7 @@ typedef struct { * 0b1..Drop Transmit Status is enabled */ #define ENET_QOS_MTL_OPERATION_MODE_DTXSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_DTXSTS_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_DTXSTS_MASK) + #define ENET_QOS_MTL_OPERATION_MODE_RAA_MASK (0x4U) #define ENET_QOS_MTL_OPERATION_MODE_RAA_SHIFT (2U) /*! RAA - Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side. @@ -37534,6 +45577,7 @@ typedef struct { * 0b1..Weighted Strict Priority (WSP) */ #define ENET_QOS_MTL_OPERATION_MODE_RAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_RAA_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_RAA_MASK) + #define ENET_QOS_MTL_OPERATION_MODE_SCHALG_MASK (0x60U) #define ENET_QOS_MTL_OPERATION_MODE_SCHALG_SHIFT (5U) /*! SCHALG - Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling: @@ -37543,6 +45587,7 @@ typedef struct { * 0b00..WRR algorithm */ #define ENET_QOS_MTL_OPERATION_MODE_SCHALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_SCHALG_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_SCHALG_MASK) + #define ENET_QOS_MTL_OPERATION_MODE_CNTPRST_MASK (0x100U) #define ENET_QOS_MTL_OPERATION_MODE_CNTPRST_SHIFT (8U) /*! CNTPRST - Counters Preset When this bit is set, - MTL_TxQ[0-7]_Underflow register is initialized/preset to 12'h7F0. @@ -37550,6 +45595,7 @@ typedef struct { * 0b1..Counters Preset is enabled */ #define ENET_QOS_MTL_OPERATION_MODE_CNTPRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_CNTPRST_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_CNTPRST_MASK) + #define ENET_QOS_MTL_OPERATION_MODE_CNTCLR_MASK (0x200U) #define ENET_QOS_MTL_OPERATION_MODE_CNTCLR_SHIFT (9U) /*! CNTCLR - Counters Reset When this bit is set, all counters are reset. @@ -37557,6 +45603,7 @@ typedef struct { * 0b1..All counters are reset */ #define ENET_QOS_MTL_OPERATION_MODE_CNTCLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_CNTCLR_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_CNTCLR_MASK) + #define ENET_QOS_MTL_OPERATION_MODE_FRPE_MASK (0x8000U) #define ENET_QOS_MTL_OPERATION_MODE_FRPE_SHIFT (15U) /*! FRPE - Flexible Rx parser Enable When this bit is set to 1, the Programmable Rx Parser functionality is enabled. @@ -37568,6 +45615,7 @@ typedef struct { /*! @name MTL_DBG_CTL - FIFO Debug Access Control and Status */ /*! @{ */ + #define ENET_QOS_MTL_DBG_CTL_FDBGEN_MASK (0x1U) #define ENET_QOS_MTL_DBG_CTL_FDBGEN_SHIFT (0U) /*! FDBGEN - FIFO Debug Access Enable When this bit is set, it indicates that the debug mode access to the FIFO is enabled. @@ -37575,6 +45623,7 @@ typedef struct { * 0b1..FIFO Debug Access is enabled */ #define ENET_QOS_MTL_DBG_CTL_FDBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FDBGEN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FDBGEN_MASK) + #define ENET_QOS_MTL_DBG_CTL_DBGMOD_MASK (0x2U) #define ENET_QOS_MTL_DBG_CTL_DBGMOD_SHIFT (1U) /*! DBGMOD - Debug Mode Access to FIFO When this bit is set, it indicates that the current access to @@ -37583,6 +45632,7 @@ typedef struct { * 0b1..Debug Mode Access to FIFO is enabled */ #define ENET_QOS_MTL_DBG_CTL_DBGMOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_DBGMOD_SHIFT)) & ENET_QOS_MTL_DBG_CTL_DBGMOD_MASK) + #define ENET_QOS_MTL_DBG_CTL_BYTEEN_MASK (0xCU) #define ENET_QOS_MTL_DBG_CTL_BYTEEN_SHIFT (2U) /*! BYTEEN - Byte Enables This field indicates the number of data bytes valid in the data register during Write operation. @@ -37592,6 +45642,7 @@ typedef struct { * 0b00..Byte 0 valid */ #define ENET_QOS_MTL_DBG_CTL_BYTEEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_BYTEEN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_BYTEEN_MASK) + #define ENET_QOS_MTL_DBG_CTL_PKTSTATE_MASK (0x60U) #define ENET_QOS_MTL_DBG_CTL_PKTSTATE_SHIFT (5U) /*! PKTSTATE - Encoded Packet State This field is used to write the control information to the Tx FIFO or Rx FIFO. @@ -37601,6 +45652,7 @@ typedef struct { * 0b10..SOP Data/Last Status */ #define ENET_QOS_MTL_DBG_CTL_PKTSTATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_PKTSTATE_SHIFT)) & ENET_QOS_MTL_DBG_CTL_PKTSTATE_MASK) + #define ENET_QOS_MTL_DBG_CTL_RSTALL_MASK (0x100U) #define ENET_QOS_MTL_DBG_CTL_RSTALL_SHIFT (8U) /*! RSTALL - Reset All Pointers When this bit is set, the pointers of all FIFOs are reset when FIFO Debug Access is enabled. @@ -37608,6 +45660,7 @@ typedef struct { * 0b1..Reset All Pointers is enabled */ #define ENET_QOS_MTL_DBG_CTL_RSTALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_RSTALL_SHIFT)) & ENET_QOS_MTL_DBG_CTL_RSTALL_MASK) + #define ENET_QOS_MTL_DBG_CTL_RSTSEL_MASK (0x200U) #define ENET_QOS_MTL_DBG_CTL_RSTSEL_SHIFT (9U) /*! RSTSEL - Reset Pointers of Selected FIFO When this bit is set, the pointers of the @@ -37616,6 +45669,7 @@ typedef struct { * 0b1..Reset Pointers of Selected FIFO is enabled */ #define ENET_QOS_MTL_DBG_CTL_RSTSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_RSTSEL_SHIFT)) & ENET_QOS_MTL_DBG_CTL_RSTSEL_MASK) + #define ENET_QOS_MTL_DBG_CTL_FIFORDEN_MASK (0x400U) #define ENET_QOS_MTL_DBG_CTL_FIFORDEN_SHIFT (10U) /*! FIFORDEN - FIFO Read Enable When this bit is set, it enables the Read operation on selected FIFO when FIFO Debug Access is enabled. @@ -37623,6 +45677,7 @@ typedef struct { * 0b1..FIFO Read is enabled */ #define ENET_QOS_MTL_DBG_CTL_FIFORDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FIFORDEN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FIFORDEN_MASK) + #define ENET_QOS_MTL_DBG_CTL_FIFOWREN_MASK (0x800U) #define ENET_QOS_MTL_DBG_CTL_FIFOWREN_SHIFT (11U) /*! FIFOWREN - FIFO Write Enable When this bit is set, it enables the Write operation on selected @@ -37631,6 +45686,7 @@ typedef struct { * 0b1..FIFO Write is enabled */ #define ENET_QOS_MTL_DBG_CTL_FIFOWREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FIFOWREN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FIFOWREN_MASK) + #define ENET_QOS_MTL_DBG_CTL_FIFOSEL_MASK (0x3000U) #define ENET_QOS_MTL_DBG_CTL_FIFOSEL_SHIFT (12U) /*! FIFOSEL - FIFO Selected for Access This field indicates the FIFO selected for debug access: @@ -37640,6 +45696,7 @@ typedef struct { * 0b01..Tx Status FIFO (only read access when SLVMOD is set) */ #define ENET_QOS_MTL_DBG_CTL_FIFOSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FIFOSEL_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FIFOSEL_MASK) + #define ENET_QOS_MTL_DBG_CTL_PKTIE_MASK (0x4000U) #define ENET_QOS_MTL_DBG_CTL_PKTIE_SHIFT (14U) /*! PKTIE - Receive Packet Available Interrupt Status Enable When this bit is set, an interrupt is @@ -37648,6 +45705,7 @@ typedef struct { * 0b1..Receive Packet Available Interrupt Status is enabled */ #define ENET_QOS_MTL_DBG_CTL_PKTIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_PKTIE_SHIFT)) & ENET_QOS_MTL_DBG_CTL_PKTIE_MASK) + #define ENET_QOS_MTL_DBG_CTL_STSIE_MASK (0x8000U) #define ENET_QOS_MTL_DBG_CTL_STSIE_SHIFT (15U) /*! STSIE - Transmit Status Available Interrupt Status Enable When this bit is set, an interrupt is @@ -37660,6 +45718,7 @@ typedef struct { /*! @name MTL_DBG_STS - FIFO Debug Status */ /*! @{ */ + #define ENET_QOS_MTL_DBG_STS_FIFOBUSY_MASK (0x1U) #define ENET_QOS_MTL_DBG_STS_FIFOBUSY_SHIFT (0U) /*! FIFOBUSY - FIFO Busy When set, this bit indicates that a FIFO operation is in progress in the @@ -37669,6 +45728,7 @@ typedef struct { * 0b0..FIFO Busy not detected */ #define ENET_QOS_MTL_DBG_STS_FIFOBUSY(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_FIFOBUSY_SHIFT)) & ENET_QOS_MTL_DBG_STS_FIFOBUSY_MASK) + #define ENET_QOS_MTL_DBG_STS_PKTSTATE_MASK (0x6U) #define ENET_QOS_MTL_DBG_STS_PKTSTATE_SHIFT (1U) /*! PKTSTATE - Encoded Packet State This field is used to get the control or status information of the selected FIFO. @@ -37678,6 +45738,7 @@ typedef struct { * 0b10..SOP Data/Last Status */ #define ENET_QOS_MTL_DBG_STS_PKTSTATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_PKTSTATE_SHIFT)) & ENET_QOS_MTL_DBG_STS_PKTSTATE_MASK) + #define ENET_QOS_MTL_DBG_STS_BYTEEN_MASK (0x18U) #define ENET_QOS_MTL_DBG_STS_BYTEEN_SHIFT (3U) /*! BYTEEN - Byte Enables This field indicates the number of data bytes valid in the data register during Read operation. @@ -37687,6 +45748,7 @@ typedef struct { * 0b00..Byte 0 valid */ #define ENET_QOS_MTL_DBG_STS_BYTEEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_BYTEEN_SHIFT)) & ENET_QOS_MTL_DBG_STS_BYTEEN_MASK) + #define ENET_QOS_MTL_DBG_STS_PKTI_MASK (0x100U) #define ENET_QOS_MTL_DBG_STS_PKTI_SHIFT (8U) /*! PKTI - Receive Packet Available Interrupt Status When set, this bit indicates that MAC layer has @@ -37695,6 +45757,7 @@ typedef struct { * 0b0..Receive Packet Available Interrupt Status not detected */ #define ENET_QOS_MTL_DBG_STS_PKTI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_PKTI_SHIFT)) & ENET_QOS_MTL_DBG_STS_PKTI_MASK) + #define ENET_QOS_MTL_DBG_STS_STSI_MASK (0x200U) #define ENET_QOS_MTL_DBG_STS_STSI_SHIFT (9U) /*! STSI - Transmit Status Available Interrupt Status When set, this bit indicates that the Slave @@ -37703,6 +45766,7 @@ typedef struct { * 0b0..Transmit Status Available Interrupt Status not detected */ #define ENET_QOS_MTL_DBG_STS_STSI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_STSI_SHIFT)) & ENET_QOS_MTL_DBG_STS_STSI_MASK) + #define ENET_QOS_MTL_DBG_STS_LOCR_MASK (0xFFFF8000U) #define ENET_QOS_MTL_DBG_STS_LOCR_SHIFT (15U) /*! LOCR - Remaining Locations in the FIFO Slave Access Mode: This field indicates the space available in selected FIFO. @@ -37712,6 +45776,7 @@ typedef struct { /*! @name MTL_FIFO_DEBUG_DATA - FIFO Debug Data */ /*! @{ */ + #define ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK (0xFFFFFFFFU) #define ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT (0U) /*! FDBGDATA - FIFO Debug Data During debug or slave access write operation, this field contains the @@ -37722,6 +45787,7 @@ typedef struct { /*! @name MTL_INTERRUPT_STATUS - MTL Interrupt Status */ /*! @{ */ + #define ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_MASK (0x1U) #define ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_SHIFT (0U) /*! Q0IS - Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0. @@ -37729,6 +45795,7 @@ typedef struct { * 0b0..Queue 0 Interrupt status not detected */ #define ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_MASK) + #define ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_MASK (0x2U) #define ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_SHIFT (1U) /*! Q1IS - Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1. @@ -37736,6 +45803,7 @@ typedef struct { * 0b0..Queue 1 Interrupt status not detected */ #define ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_MASK) + #define ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_MASK (0x4U) #define ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_SHIFT (2U) /*! Q2IS - Queue 2 Interrupt status This bit indicates that there is an interrupt from Queue 2. @@ -37743,6 +45811,7 @@ typedef struct { * 0b0..Queue 2 Interrupt status not detected */ #define ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_MASK) + #define ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_MASK (0x8U) #define ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_SHIFT (3U) /*! Q3IS - Queue 3 Interrupt status This bit indicates that there is an interrupt from Queue 3. @@ -37750,6 +45819,7 @@ typedef struct { * 0b0..Queue 3 Interrupt status not detected */ #define ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_MASK) + #define ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_MASK (0x10U) #define ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_SHIFT (4U) /*! Q4IS - Queue 4 Interrupt status This bit indicates that there is an interrupt from Queue 4. @@ -37757,6 +45827,7 @@ typedef struct { * 0b0..Queue 4 Interrupt status not detected */ #define ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_MASK) + #define ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_MASK (0x20000U) #define ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_SHIFT (17U) /*! DBGIS - Debug Interrupt status This bit indicates an interrupt event during the slave access. @@ -37764,6 +45835,7 @@ typedef struct { * 0b0..Debug Interrupt status not detected */ #define ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_MASK) + #define ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_MASK (0x40000U) #define ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_SHIFT (18U) /*! ESTIS - EST (TAS- 802. @@ -37771,6 +45843,7 @@ typedef struct { * 0b0..EST (TAS- 802.1Qbv) Interrupt status not detected */ #define ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_MASK) + #define ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_MASK (0x800000U) #define ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_SHIFT (23U) /*! MTLPIS - MTL Rx Parser Interrupt Status This bit indicates that there is an interrupt from Rx Parser Block. @@ -37782,14 +45855,16 @@ typedef struct { /*! @name MTL_RXQ_DMA_MAP0 - Receive Queue and DMA Channel Mapping 0 */ /*! @{ */ + #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK (0x7U) #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT (0U) /*! Q0MDMACH - Queue 0 Mapped to DMA Channel This field controls the routing of the packet received * in Queue 0 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - * - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: DMA Channel 5 - 110: DMA Channel 6 - 111: DMA - * Channel 7 This field is valid when the Q0DDMACH field is reset. + * - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This + * field is valid when the Q0DDMACH field is reset. */ #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK) + #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_MASK (0x10U) #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT (4U) /*! Q0DDMACH - Queue 0 Enabled for DA-based DMA Channel Selection When set, this bit indicates that @@ -37800,14 +45875,16 @@ typedef struct { * 0b1..Queue 0 enabled for DA-based DMA Channel Selection */ #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_MASK) + #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_MASK (0x700U) #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT (8U) /*! Q1MDMACH - Queue 1 Mapped to DMA Channel This field controls the routing of the received packet * in Queue 1 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - * - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: DMA Channel 5 - 110: DMA Channel 6 - 111: DMA - * Channel 7 This field is valid when the Q1DDMACH field is reset. + * - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This + * field is valid when the Q1DDMACH field is reset. */ #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_MASK) + #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_MASK (0x1000U) #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT (12U) /*! Q1DDMACH - Queue 1 Enabled for DA-based DMA Channel Selection When set, this bit indicates that @@ -37818,14 +45895,16 @@ typedef struct { * 0b1..Queue 1 enabled for DA-based DMA Channel Selection */ #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_MASK) + #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_MASK (0x70000U) #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_SHIFT (16U) /*! Q2MDMACH - Queue 2 Mapped to DMA Channel This field controls the routing of the received packet * in Queue 2 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - * - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: DMA Channel 5 - 110: DMA Channel 6 - 111: DMA - * Channel 7 This field is valid when the Q2DDMACH field is reset. + * - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This + * field is valid when the Q2DDMACH field is reset. */ #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_MASK) + #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_MASK (0x100000U) #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_SHIFT (20U) /*! Q2DDMACH - Queue 2 Enabled for DA-based DMA Channel Selection When set, this bit indicates that @@ -37836,14 +45915,16 @@ typedef struct { * 0b1..Queue 2 enabled for DA-based DMA Channel Selection */ #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_MASK) + #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_MASK (0x7000000U) #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_SHIFT (24U) /*! Q3MDMACH - Queue 3 Mapped to DMA Channel This field controls the routing of the received packet * in Queue 3 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - * - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: DMA Channel 5 - 110: DMA Channel 6 - 111: DMA - * Channel 7 This field is valid when the Q3DDMACH field is reset. + * - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This + * field is valid when the Q3DDMACH field is reset. */ #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_MASK) + #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_MASK (0x10000000U) #define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_SHIFT (28U) /*! Q3DDMACH - Queue 3 Enabled for Dynamic (per packet) DMA Channel Selection When set, this bit @@ -37858,14 +45939,16 @@ typedef struct { /*! @name MTL_RXQ_DMA_MAP1 - Receive Queue and DMA Channel Mapping 1 */ /*! @{ */ + #define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_MASK (0x7U) #define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_SHIFT (0U) /*! Q4MDMACH - Queue 4 Mapped to DMA Channel This field controls the routing of the packet received * in Queue 4 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - * - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: DMA Channel 5 - 110: DMA Channel 6 - 111: DMA - * Channel 7 This field is valid when the Q4DDMACH field is reset. + * - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This + * field is valid when the Q4DDMACH field is reset. */ #define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_MASK) + #define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_MASK (0x10U) #define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_SHIFT (4U) /*! Q4DDMACH - Queue 4 Enabled for DA-based DMA Channel Selection When set, this bit indicates that @@ -37880,6 +45963,7 @@ typedef struct { /*! @name MTL_TBS_CTRL - Time Based Scheduling Control */ /*! @{ */ + #define ENET_QOS_MTL_TBS_CTRL_ESTM_MASK (0x1U) #define ENET_QOS_MTL_TBS_CTRL_ESTM_SHIFT (0U) /*! ESTM - EST offset Mode When this bit is set, the Launch Time value used in Time Based Scheduling @@ -37889,6 +45973,7 @@ typedef struct { * 0b1..EST offset Mode is enabled */ #define ENET_QOS_MTL_TBS_CTRL_ESTM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_ESTM_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_ESTM_MASK) + #define ENET_QOS_MTL_TBS_CTRL_LEOV_MASK (0x2U) #define ENET_QOS_MTL_TBS_CTRL_LEOV_SHIFT (1U) /*! LEOV - Launch Expiry Offset Valid When set indicates the LEOS field is valid. @@ -37896,11 +45981,13 @@ typedef struct { * 0b1..LEOS field is valid */ #define ENET_QOS_MTL_TBS_CTRL_LEOV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_LEOV_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_LEOV_MASK) + #define ENET_QOS_MTL_TBS_CTRL_LEGOS_MASK (0x70U) #define ENET_QOS_MTL_TBS_CTRL_LEGOS_SHIFT (4U) /*! LEGOS - Launch Expiry GSN Offset The number GSN slots that has to be added to the Launch GSN to compute the Launch Expiry time. */ #define ENET_QOS_MTL_TBS_CTRL_LEGOS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_LEGOS_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_LEGOS_MASK) + #define ENET_QOS_MTL_TBS_CTRL_LEOS_MASK (0xFFFFFF00U) #define ENET_QOS_MTL_TBS_CTRL_LEOS_SHIFT (8U) /*! LEOS - Launch Expiry Offset The value in units of 256 nanoseconds that has to be added to the @@ -37911,6 +45998,7 @@ typedef struct { /*! @name MTL_EST_CONTROL - Enhancements to Scheduled Transmission Control */ /*! @{ */ + #define ENET_QOS_MTL_EST_CONTROL_EEST_MASK (0x1U) #define ENET_QOS_MTL_EST_CONTROL_EEST_SHIFT (0U) /*! EEST - Enable EST When reset, the gate control list processing is halted and all gates are assumed to be in Open state. @@ -37918,6 +46006,7 @@ typedef struct { * 0b1..EST is enabled */ #define ENET_QOS_MTL_EST_CONTROL_EEST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_EEST_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_EEST_MASK) + #define ENET_QOS_MTL_EST_CONTROL_SSWL_MASK (0x2U) #define ENET_QOS_MTL_EST_CONTROL_SSWL_SHIFT (1U) /*! SSWL - Switch to S/W owned list When set indicates that the software has programmed that list @@ -37927,6 +46016,7 @@ typedef struct { * 0b1..Switch to S/W owned list is enabled */ #define ENET_QOS_MTL_EST_CONTROL_SSWL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_SSWL_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_SSWL_MASK) + #define ENET_QOS_MTL_EST_CONTROL_DDBF_MASK (0x10U) #define ENET_QOS_MTL_EST_CONTROL_DDBF_SHIFT (4U) /*! DDBF - Do not Drop frames during Frame Size Error When set, frames are not be dropped during @@ -37935,6 +46025,7 @@ typedef struct { * 0b0..Drop frames during Frame Size Error */ #define ENET_QOS_MTL_EST_CONTROL_DDBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_DDBF_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_DDBF_MASK) + #define ENET_QOS_MTL_EST_CONTROL_DFBS_MASK (0x20U) #define ENET_QOS_MTL_EST_CONTROL_DFBS_SHIFT (5U) /*! DFBS - Drop Frames causing Scheduling Error When set frames reported to cause HOL Blocking due @@ -37944,6 +46035,7 @@ typedef struct { * 0b1..Drop Frames causing Scheduling Error */ #define ENET_QOS_MTL_EST_CONTROL_DFBS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_DFBS_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_DFBS_MASK) + #define ENET_QOS_MTL_EST_CONTROL_LCSE_MASK (0xC0U) #define ENET_QOS_MTL_EST_CONTROL_LCSE_SHIFT (6U) /*! LCSE - Loop Count to report Scheduling Error Programmable number of GCL list iterations before @@ -37954,12 +46046,14 @@ typedef struct { * 0b01..8 iterations */ #define ENET_QOS_MTL_EST_CONTROL_LCSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_LCSE_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_LCSE_MASK) + #define ENET_QOS_MTL_EST_CONTROL_TILS_MASK (0x700U) #define ENET_QOS_MTL_EST_CONTROL_TILS_SHIFT (8U) /*! TILS - Time Interval Left Shift Amount This field provides the left shift amount for the * programmed Time Interval values used in the Gate Control Lists. */ #define ENET_QOS_MTL_EST_CONTROL_TILS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_TILS_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_TILS_MASK) + #define ENET_QOS_MTL_EST_CONTROL_CTOV_MASK (0xFFF000U) #define ENET_QOS_MTL_EST_CONTROL_CTOV_SHIFT (12U) /*! CTOV - Current Time Offset Value Provides a 12 bit time offset value in nano second that is @@ -37967,6 +46061,7 @@ typedef struct { * sync delay, buffering delays, data path delays etc. */ #define ENET_QOS_MTL_EST_CONTROL_CTOV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_CTOV_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_CTOV_MASK) + #define ENET_QOS_MTL_EST_CONTROL_PTOV_MASK (0xFF000000U) #define ENET_QOS_MTL_EST_CONTROL_PTOV_SHIFT (24U) /*! PTOV - PTP Time Offset Value The value of PTP Clock period multiplied by 6 in nanoseconds. @@ -37976,6 +46071,7 @@ typedef struct { /*! @name MTL_EST_STATUS - Enhancements to Scheduled Transmission Status */ /*! @{ */ + #define ENET_QOS_MTL_EST_STATUS_SWLC_MASK (0x1U) #define ENET_QOS_MTL_EST_STATUS_SWLC_SHIFT (0U) /*! SWLC - Switch to S/W owned list Complete When "1" indicates the hardware has successfully @@ -37984,6 +46080,7 @@ typedef struct { * 0b0..Switch to S/W owned list Complete not detected */ #define ENET_QOS_MTL_EST_STATUS_SWLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_SWLC_SHIFT)) & ENET_QOS_MTL_EST_STATUS_SWLC_MASK) + #define ENET_QOS_MTL_EST_STATUS_BTRE_MASK (0x2U) #define ENET_QOS_MTL_EST_STATUS_BTRE_SHIFT (1U) /*! BTRE - BTR Error When "1" indicates a programming error in the BTR of SWOL where the programmed @@ -37992,6 +46089,7 @@ typedef struct { * 0b0..BTR Error not detected */ #define ENET_QOS_MTL_EST_STATUS_BTRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_BTRE_SHIFT)) & ENET_QOS_MTL_EST_STATUS_BTRE_MASK) + #define ENET_QOS_MTL_EST_STATUS_HLBF_MASK (0x4U) #define ENET_QOS_MTL_EST_STATUS_HLBF_SHIFT (2U) /*! HLBF - Head-Of-Line Blocking due to Frame Size Set when HOL Blocking is noticed on one or more @@ -38002,6 +46100,7 @@ typedef struct { * 0b0..Head-Of-Line Blocking due to Frame Size not detected */ #define ENET_QOS_MTL_EST_STATUS_HLBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_HLBF_SHIFT)) & ENET_QOS_MTL_EST_STATUS_HLBF_MASK) + #define ENET_QOS_MTL_EST_STATUS_HLBS_MASK (0x8U) #define ENET_QOS_MTL_EST_STATUS_HLBS_SHIFT (3U) /*! HLBS - Head-Of-Line Blocking due to Scheduling Set when the frame is not able to win arbitration @@ -38010,6 +46109,7 @@ typedef struct { * 0b0..Head-Of-Line Blocking due to Scheduling not detected */ #define ENET_QOS_MTL_EST_STATUS_HLBS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_HLBS_SHIFT)) & ENET_QOS_MTL_EST_STATUS_HLBS_MASK) + #define ENET_QOS_MTL_EST_STATUS_CGCE_MASK (0x10U) #define ENET_QOS_MTL_EST_STATUS_CGCE_SHIFT (4U) /*! CGCE - Constant Gate Control Error This error occurs when the list length (LLR) is 1 and the @@ -38019,6 +46119,7 @@ typedef struct { * 0b0..Constant Gate Control Error not detected */ #define ENET_QOS_MTL_EST_STATUS_CGCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_CGCE_SHIFT)) & ENET_QOS_MTL_EST_STATUS_CGCE_MASK) + #define ENET_QOS_MTL_EST_STATUS_SWOL_MASK (0x80U) #define ENET_QOS_MTL_EST_STATUS_SWOL_SHIFT (7U) /*! SWOL - S/W owned list When '0' indicates Gate control list number "0" is owned by software and @@ -38027,12 +46128,14 @@ typedef struct { * 0b0..Gate control list number "0" is owned by software */ #define ENET_QOS_MTL_EST_STATUS_SWOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_SWOL_SHIFT)) & ENET_QOS_MTL_EST_STATUS_SWOL_MASK) + #define ENET_QOS_MTL_EST_STATUS_BTRL_MASK (0xF00U) #define ENET_QOS_MTL_EST_STATUS_BTRL_SHIFT (8U) /*! BTRL - BTR Error Loop Count Provides the minimum count (N) for which the equation Current Time * =< New BTR + (N * New Cycle Time) becomes true. */ #define ENET_QOS_MTL_EST_STATUS_BTRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_BTRL_SHIFT)) & ENET_QOS_MTL_EST_STATUS_BTRL_MASK) + #define ENET_QOS_MTL_EST_STATUS_CGSN_MASK (0xF0000U) #define ENET_QOS_MTL_EST_STATUS_CGSN_SHIFT (16U) /*! CGSN - Current GCL Slot Number Indicates the slot number of the GCL list. @@ -38042,6 +46145,7 @@ typedef struct { /*! @name MTL_EST_SCH_ERROR - EST Scheduling Error */ /*! @{ */ + #define ENET_QOS_MTL_EST_SCH_ERROR_SEQN_MASK (0x1FU) #define ENET_QOS_MTL_EST_SCH_ERROR_SEQN_SHIFT (0U) /*! SEQN - Schedule Error Queue Number The One Hot Encoded Queue Numbers that have experienced @@ -38052,6 +46156,7 @@ typedef struct { /*! @name MTL_EST_FRM_SIZE_ERROR - EST Frame Size Error */ /*! @{ */ + #define ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK (0x1FU) #define ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT (0U) /*! FEQN - Frame Size Error Queue Number The One Hot Encoded Queue Numbers that have experienced @@ -38062,12 +46167,14 @@ typedef struct { /*! @name MTL_EST_FRM_SIZE_CAPTURE - EST Frame Size Capture */ /*! @{ */ + #define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK (0x7FFFU) #define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT (0U) /*! HBFS - Frame Size of HLBF Captures the Frame Size of the dropped frame related to queue number * indicated in HBFQ field of this register. */ #define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT)) & ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK) + #define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_MASK (0x70000U) #define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_SHIFT (16U) /*! HBFQ - Queue Number of HLBF Captures the binary value of the of the first Queue (number) @@ -38078,6 +46185,7 @@ typedef struct { /*! @name MTL_EST_INTR_ENABLE - EST Interrupt Enable */ /*! @{ */ + #define ENET_QOS_MTL_EST_INTR_ENABLE_IECC_MASK (0x1U) #define ENET_QOS_MTL_EST_INTR_ENABLE_IECC_SHIFT (0U) /*! IECC - Interrupt Enable for Switch List When set, generates interrupt when the configuration @@ -38086,6 +46194,7 @@ typedef struct { * 0b1..Interrupt for Switch List is enabled */ #define ENET_QOS_MTL_EST_INTR_ENABLE_IECC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IECC_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IECC_MASK) + #define ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_MASK (0x2U) #define ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_SHIFT (1U) /*! IEBE - Interrupt Enable for BTR Error When set, generates interrupt when the BTR Error occurs and is indicated in the status. @@ -38093,6 +46202,7 @@ typedef struct { * 0b1..Interrupt for BTR Error is enabled */ #define ENET_QOS_MTL_EST_INTR_ENABLE_IEBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_MASK) + #define ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_MASK (0x4U) #define ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_SHIFT (2U) /*! IEHF - Interrupt Enable for HLBF When set, generates interrupt when the Head-of-Line Blocking @@ -38101,6 +46211,7 @@ typedef struct { * 0b1..Interrupt for HLBF is enabled */ #define ENET_QOS_MTL_EST_INTR_ENABLE_IEHF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_MASK) + #define ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_MASK (0x8U) #define ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_SHIFT (3U) /*! IEHS - Interrupt Enable for HLBS When set, generates interrupt when the Head-of-Line Blocking @@ -38109,6 +46220,7 @@ typedef struct { * 0b1..Interrupt for HLBS is enabled */ #define ENET_QOS_MTL_EST_INTR_ENABLE_IEHS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_MASK) + #define ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_MASK (0x10U) #define ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_SHIFT (4U) /*! CGCE - Interrupt Enable for CGCE When set, generates interrupt when the Constant Gate Control @@ -38121,6 +46233,7 @@ typedef struct { /*! @name MTL_EST_GCL_CONTROL - EST GCL Control */ /*! @{ */ + #define ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_MASK (0x1U) #define ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_SHIFT (0U) /*! SRWO - Start Read/Write Op When set indicates a Read/Write Op has started and is in progress. @@ -38128,6 +46241,7 @@ typedef struct { * 0b1..Start Read/Write Op enabled */ #define ENET_QOS_MTL_EST_GCL_CONTROL_SRWO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_MASK) + #define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_MASK (0x2U) #define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_SHIFT (1U) /*! R1W0 - Read '1', Write '0': When set to '1': Read Operation When set to '0': Write Operation. @@ -38135,6 +46249,7 @@ typedef struct { * 0b0..Write Operation */ #define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_MASK) + #define ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_MASK (0x4U) #define ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_SHIFT (2U) /*! GCRR - Gate Control Related Registers When set to "1" indicates the R/W access is for the GCL @@ -38143,6 +46258,7 @@ typedef struct { * 0b1..Gate Control Related Registers are enabled */ #define ENET_QOS_MTL_EST_GCL_CONTROL_GCRR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_MASK) + #define ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_MASK (0x10U) #define ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_SHIFT (4U) /*! DBGM - Debug Mode When set to "1" indicates R/W in debug mode where the memory bank (for GCL and @@ -38152,6 +46268,7 @@ typedef struct { * 0b1..Debug Mode is enabled */ #define ENET_QOS_MTL_EST_GCL_CONTROL_DBGM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_MASK) + #define ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_MASK (0x20U) #define ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_SHIFT (5U) /*! DBGB - Debug Mode Bank Select When set to "0" indicates R/W in debug mode should be directed to @@ -38160,11 +46277,13 @@ typedef struct { * 0b1..R/W in debug mode should be directed to Bank 1 */ #define ENET_QOS_MTL_EST_GCL_CONTROL_DBGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_MASK) + #define ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_MASK (0x1FF00U) #define ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_SHIFT (8U) /*! ADDR - Gate Control List Address: (GCLA when GCRR is "0"). */ #define ENET_QOS_MTL_EST_GCL_CONTROL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_MASK) + #define ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_MASK (0x100000U) #define ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_SHIFT (20U) /*! ERR0 - When set indicates the last write operation was aborted as software writes to GCL and GCL @@ -38173,6 +46292,7 @@ typedef struct { * 0b1..ERR1 is enabled */ #define ENET_QOS_MTL_EST_GCL_CONTROL_ERR0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_MASK) + #define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_MASK (0x200000U) #define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_SHIFT (21U) /*! ESTEIEE - EST ECC Inject Error Enable When set along with EEST bit of MTL_EST_CONTROL register, @@ -38181,6 +46301,7 @@ typedef struct { * 0b1..EST ECC Inject Error is enabled */ #define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_MASK) + #define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_MASK (0xC00000U) #define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT (22U) /*! ESTEIEC - ECC Inject Error Control for EST Memory When EIEE bit of this register is set, @@ -38195,6 +46316,7 @@ typedef struct { /*! @name MTL_EST_GCL_DATA - EST GCL Data */ /*! @{ */ + #define ENET_QOS_MTL_EST_GCL_DATA_GCD_MASK (0xFFFFFFFFU) #define ENET_QOS_MTL_EST_GCL_DATA_GCD_SHIFT (0U) /*! GCD - Gate Control Data The data corresponding to the address selected in the MTL_GCL_CONTROL register. @@ -38204,18 +46326,21 @@ typedef struct { /*! @name MTL_FPE_CTRL_STS - Frame Preemption Control and Status */ /*! @{ */ + #define ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_MASK (0x3U) #define ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_SHIFT (0U) /*! AFSZ - Additional Fragment Size used to indicate, in units of 64 bytes, the minimum number of * bytes over 64 bytes required in non-final fragments of preempted frames. */ #define ENET_QOS_MTL_FPE_CTRL_STS_AFSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_SHIFT)) & ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_MASK) + #define ENET_QOS_MTL_FPE_CTRL_STS_PEC_MASK (0x1F00U) #define ENET_QOS_MTL_FPE_CTRL_STS_PEC_SHIFT (8U) /*! PEC - Preemption Classification When set indicates the corresponding Queue must be classified as * preemptable, when '0' Queue is classified as express. */ #define ENET_QOS_MTL_FPE_CTRL_STS_PEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_CTRL_STS_PEC_SHIFT)) & ENET_QOS_MTL_FPE_CTRL_STS_PEC_MASK) + #define ENET_QOS_MTL_FPE_CTRL_STS_HRS_MASK (0x10000000U) #define ENET_QOS_MTL_FPE_CTRL_STS_HRS_SHIFT (28U) /*! HRS - Hold/Release Status - 1: Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State. @@ -38227,6 +46352,7 @@ typedef struct { /*! @name MTL_FPE_ADVANCE - Frame Preemption Hold and Release Advance */ /*! @{ */ + #define ENET_QOS_MTL_FPE_ADVANCE_HADV_MASK (0xFFFFU) #define ENET_QOS_MTL_FPE_ADVANCE_HADV_SHIFT (0U) /*! HADV - Hold Advance The maximum time in nanoseconds that can elapse between issuing a HOLD to @@ -38234,6 +46360,7 @@ typedef struct { * transmission or any preemptable frames that are queued for transmission. */ #define ENET_QOS_MTL_FPE_ADVANCE_HADV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_ADVANCE_HADV_SHIFT)) & ENET_QOS_MTL_FPE_ADVANCE_HADV_MASK) + #define ENET_QOS_MTL_FPE_ADVANCE_RADV_MASK (0xFFFF0000U) #define ENET_QOS_MTL_FPE_ADVANCE_RADV_SHIFT (16U) /*! RADV - Release Advance The maximum time in nanoseconds that can elapse between issuing a RELEASE @@ -38245,18 +46372,21 @@ typedef struct { /*! @name MTL_RXP_CONTROL_STATUS - RXP Control Status */ /*! @{ */ + #define ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_MASK (0xFFU) #define ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_SHIFT (0U) /*! NVE - Number of valid entries in the Instruction table This control indicates the number of * valid entries in the Instruction Memory. */ #define ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_SHIFT)) & ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_MASK) + #define ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_MASK (0xFF0000U) #define ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_SHIFT (16U) /*! NPE - Number of parsable entries in the Instruction table This control indicates the number of * parsable entries in the Instruction Memory. */ #define ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_SHIFT)) & ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_MASK) + #define ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_MASK (0x80000000U) #define ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_SHIFT (31U) /*! RXPI - RX Parser in Idle state This status bit is set to 1 when the Rx parser is in Idle State @@ -38269,6 +46399,7 @@ typedef struct { /*! @name MTL_RXP_INTERRUPT_CONTROL_STATUS - RXP Interrupt Control Status */ /*! @{ */ + #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_MASK (0x1U) #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_SHIFT (0U) /*! NVEOVIS - Number of Valid Entries Overflow Interrupt Status While parsing if the Instruction @@ -38278,6 +46409,7 @@ typedef struct { * 0b0..Number of Valid Entries Overflow Interrupt Status not detected */ #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_MASK) + #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_MASK (0x2U) #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_SHIFT (1U) /*! NPEOVIS - Number of Parsable Entries Overflow Interrupt Status While parsing a packet if the @@ -38287,6 +46419,7 @@ typedef struct { * 0b0..Number of Parsable Entries Overflow Interrupt Status not detected */ #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_MASK) + #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_MASK (0x4U) #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_SHIFT (2U) /*! FOOVIS - Frame Offset Overflow Interrupt Status While parsing if the Instruction table entry's @@ -38295,6 +46428,7 @@ typedef struct { * 0b0..Frame Offset Overflow Interrupt Status not detected */ #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_MASK) + #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_MASK (0x8U) #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_SHIFT (3U) /*! PDRFIS - Packet Dropped due to RF Interrupt Status If the Rx Parser result says to drop the @@ -38303,6 +46437,7 @@ typedef struct { * 0b0..Packet Dropped due to RF Interrupt Status not detected */ #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_MASK) + #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_MASK (0x10000U) #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_SHIFT (16U) /*! NVEOVIE - Number of Valid Entries Overflow Interrupt Enable When this bit is set, the NVEOVIS interrupt is enabled. @@ -38310,6 +46445,7 @@ typedef struct { * 0b1..Number of Valid Entries Overflow Interrupt is enabled */ #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_MASK) + #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_MASK (0x20000U) #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_SHIFT (17U) /*! NPEOVIE - Number of Parsable Entries Overflow Interrupt Enable When this bit is set, the NPEOVIS interrupt is enabled. @@ -38317,6 +46453,7 @@ typedef struct { * 0b1..Number of Parsable Entries Overflow Interrupt is enabled */ #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_MASK) + #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_MASK (0x40000U) #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_SHIFT (18U) /*! FOOVIE - Frame Offset Overflow Interrupt Enable When this bit is set, the FOOVIS interrupt is enabled. @@ -38324,6 +46461,7 @@ typedef struct { * 0b1..Frame Offset Overflow Interrupt is enabled */ #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_MASK) + #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_MASK (0x80000U) #define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_SHIFT (19U) /*! PDRFIE - Packet Drop due to RF Interrupt Enable When this bit is set, the PDRFIS interrupt is enabled. @@ -38335,11 +46473,13 @@ typedef struct { /*! @name MTL_RXP_DROP_CNT - RXP Drop Count */ /*! @{ */ + #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_MASK (0x7FFFFFFFU) #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_SHIFT (0U) /*! RXPDC - Rx Parser Drop count This 31-bit counter is implemented whenever a Rx Parser Drops a packet due to RF =1. */ #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_SHIFT)) & ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_MASK) + #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_MASK (0x80000000U) #define ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_SHIFT (31U) /*! RXPDCOVF - Rx Parser Drop Counter Overflow Bit When set, this bit indicates that the @@ -38352,6 +46492,7 @@ typedef struct { /*! @name MTL_RXP_ERROR_CNT - RXP Error Count */ /*! @{ */ + #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_MASK (0x7FFFFFFFU) #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_SHIFT (0U) /*! RXPEC - Rx Parser Error count This 31-bit counter is implemented whenever a Rx Parser encounters @@ -38359,6 +46500,7 @@ typedef struct { * address > EOF data entry address The counter is cleared when the register is read. */ #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_SHIFT)) & ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_MASK) + #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_MASK (0x80000000U) #define ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_SHIFT (31U) /*! RXPECOVF - Rx Parser Error Counter Overflow Bit When set, this bit indicates that the @@ -38371,11 +46513,13 @@ typedef struct { /*! @name MTL_RXP_INDIRECT_ACC_CONTROL_STATUS - RXP Indirect Access Control and Status */ /*! @{ */ + #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK (0x3FFU) #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT (0U) /*! ADDR - FRP Instruction Table Offset Address This field indicates the ADDR of the 32-bit entry in Rx parser instruction table. */ #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK) + #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_MASK (0x10000U) #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_SHIFT (16U) /*! WRRDN - Read Write Control When this bit is set to 1 indicates the write operation to the Rx Parser Memory. @@ -38383,6 +46527,7 @@ typedef struct { * 0b1..Write operation to the Rx Parser Memory */ #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_MASK) + #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_MASK (0x80000000U) #define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_SHIFT (31U) /*! STARTBUSY - FRP Instruction Table Access Busy When this bit is set to 1 by the software then it @@ -38395,6 +46540,7 @@ typedef struct { /*! @name MTL_RXP_INDIRECT_ACC_DATA - RXP Indirect Access Data */ /*! @{ */ + #define ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK (0xFFFFFFFFU) #define ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT (0U) /*! DATA - FRP Instruction Table Write/Read Data Software should write this register before issuing any write command. @@ -38404,6 +46550,7 @@ typedef struct { /*! @name MTL_TXQX_OP_MODE - Queue 0 Transmit Operation Mode..Queue 4 Transmit Operation Mode */ /*! @{ */ + #define ENET_QOS_MTL_TXQX_OP_MODE_FTQ_MASK (0x1U) #define ENET_QOS_MTL_TXQX_OP_MODE_FTQ_SHIFT (0U) /*! FTQ - Flush Transmit Queue When this bit is set, the Tx queue controller logic is reset to its default values. @@ -38411,6 +46558,7 @@ typedef struct { * 0b1..Flush Transmit Queue is enabled */ #define ENET_QOS_MTL_TXQX_OP_MODE_FTQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_FTQ_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_FTQ_MASK) + #define ENET_QOS_MTL_TXQX_OP_MODE_TSF_MASK (0x2U) #define ENET_QOS_MTL_TXQX_OP_MODE_TSF_SHIFT (1U) /*! TSF - Transmit Store and Forward When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue. @@ -38418,6 +46566,7 @@ typedef struct { * 0b1..Transmit Store and Forward is enabled */ #define ENET_QOS_MTL_TXQX_OP_MODE_TSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TSF_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TSF_MASK) + #define ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_MASK (0xCU) #define ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_SHIFT (2U) /*! TXQEN - Transmit Queue Enable This field is used to enable/disable the transmit queue 0. @@ -38427,6 +46576,7 @@ typedef struct { * 0b11..Reserved */ #define ENET_QOS_MTL_TXQX_OP_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_MASK) + #define ENET_QOS_MTL_TXQX_OP_MODE_TTC_MASK (0x70U) #define ENET_QOS_MTL_TXQX_OP_MODE_TTC_SHIFT (4U) /*! TTC - Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue. @@ -38440,6 +46590,7 @@ typedef struct { * 0b010..96 */ #define ENET_QOS_MTL_TXQX_OP_MODE_TTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TTC_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TTC_MASK) + #define ENET_QOS_MTL_TXQX_OP_MODE_TQS_MASK (0x1F0000U) #define ENET_QOS_MTL_TXQX_OP_MODE_TQS_SHIFT (16U) /*! TQS - Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes. @@ -38452,12 +46603,14 @@ typedef struct { /*! @name MTL_TXQX_UNDRFLW - Queue 0 Underflow Counter..Queue 4 Underflow Counter */ /*! @{ */ + #define ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK (0x7FFU) #define ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT (0U) /*! UFFRMCNT - Underflow Packet Counter This field indicates the number of packets aborted by the * controller because of Tx Queue Underflow. */ #define ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT)) & ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK) + #define ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK (0x800U) #define ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U) /*! UFCNTOVF - Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue @@ -38473,6 +46626,7 @@ typedef struct { /*! @name MTL_TXQX_DBG - Queue 0 Transmit Debug..Queue 4 Transmit Debug */ /*! @{ */ + #define ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_MASK (0x1U) #define ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_SHIFT (0U) /*! TXQPAUSED - Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it @@ -38483,6 +46637,7 @@ typedef struct { * 0b0..Transmit Queue in Pause status is not detected */ #define ENET_QOS_MTL_TXQX_DBG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_MASK) + #define ENET_QOS_MTL_TXQX_DBG_TRCSTS_MASK (0x6U) #define ENET_QOS_MTL_TXQX_DBG_TRCSTS_SHIFT (1U) /*! TRCSTS - MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: @@ -38492,6 +46647,7 @@ typedef struct { * 0b10..Waiting for pending Tx Status from the MAC transmitter */ #define ENET_QOS_MTL_TXQX_DBG_TRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TRCSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TRCSTS_MASK) + #define ENET_QOS_MTL_TXQX_DBG_TWCSTS_MASK (0x8U) #define ENET_QOS_MTL_TXQX_DBG_TWCSTS_SHIFT (3U) /*! TWCSTS - MTL Tx Queue Write Controller Status When high, this bit indicates that the MTL Tx @@ -38500,6 +46656,7 @@ typedef struct { * 0b0..MTL Tx Queue Write Controller status is not detected */ #define ENET_QOS_MTL_TXQX_DBG_TWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TWCSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TWCSTS_MASK) + #define ENET_QOS_MTL_TXQX_DBG_TXQSTS_MASK (0x10U) #define ENET_QOS_MTL_TXQX_DBG_TXQSTS_SHIFT (4U) /*! TXQSTS - MTL Tx Queue Not Empty Status When this bit is high, it indicates that the MTL Tx Queue @@ -38508,6 +46665,7 @@ typedef struct { * 0b0..MTL Tx Queue Not Empty status is not detected */ #define ENET_QOS_MTL_TXQX_DBG_TXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TXQSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TXQSTS_MASK) + #define ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_MASK (0x20U) #define ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_SHIFT (5U) /*! TXSTSFSTS - MTL Tx Status FIFO Full Status When high, this bit indicates that the MTL Tx Status FIFO is full. @@ -38515,11 +46673,13 @@ typedef struct { * 0b0..MTL Tx Status FIFO Full status is not detected */ #define ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_MASK) + #define ENET_QOS_MTL_TXQX_DBG_PTXQ_MASK (0x70000U) #define ENET_QOS_MTL_TXQX_DBG_PTXQ_SHIFT (16U) /*! PTXQ - Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue. */ #define ENET_QOS_MTL_TXQX_DBG_PTXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_PTXQ_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_PTXQ_MASK) + #define ENET_QOS_MTL_TXQX_DBG_STXSTSF_MASK (0x700000U) #define ENET_QOS_MTL_TXQX_DBG_STXSTSF_SHIFT (20U) /*! STXSTSF - Number of Status Words in Tx Status FIFO of Queue This field indicates the current @@ -38533,6 +46693,7 @@ typedef struct { /*! @name MTL_TXQX_ETS_CTRL - Queue 1 ETS Control..Queue 4 ETS Control */ /*! @{ */ + #define ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_MASK (0x4U) #define ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_SHIFT (2U) /*! AVALG - AV Algorithm When Queue 1 is programmed for AV, this field configures the scheduling @@ -38542,6 +46703,7 @@ typedef struct { * 0b1..CBS Algorithm is enabled */ #define ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_MASK) + #define ENET_QOS_MTL_TXQX_ETS_CTRL_CC_MASK (0x8U) #define ENET_QOS_MTL_TXQX_ETS_CTRL_CC_SHIFT (3U) /*! CC - Credit Control When this bit is set, the accumulated credit parameter in the credit-based @@ -38551,6 +46713,7 @@ typedef struct { * 0b1..Credit Control is enabled */ #define ENET_QOS_MTL_TXQX_ETS_CTRL_CC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_CTRL_CC_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_CTRL_CC_MASK) + #define ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_MASK (0x70U) #define ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_SHIFT (4U) /*! SLC - Slot Count If the credit-based shaper algorithm is enabled, the software can program the @@ -38572,6 +46735,7 @@ typedef struct { /*! @name MTL_TXQX_ETS_STAT - Queue 0 ETS Status..Queue 4 ETS Status */ /*! @{ */ + #define ENET_QOS_MTL_TXQX_ETS_STAT_ABS_MASK (0xFFFFFFU) #define ENET_QOS_MTL_TXQX_ETS_STAT_ABS_SHIFT (0U) /*! ABS - Average Bits per Slot This field contains the average transmitted bits per slot. @@ -38584,6 +46748,7 @@ typedef struct { /*! @name MTL_TXQX_QNTM_WGHT - Queue 0 Quantum or Weights..Queue 4 idleSlopeCredit, Quantum or Weights */ /*! @{ */ + #define ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_MASK (0x1FFFFFU) #define ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT (0U) /*! ISCQW - Quantum or Weights When the DCB operation is enabled with DWRR algorithm for Queue 0 @@ -38598,6 +46763,7 @@ typedef struct { /*! @name MTL_TXQX_SNDSLP_CRDT - Queue 1 sendSlopeCredit..Queue 4 sendSlopeCredit */ /*! @{ */ + #define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_MASK (0x3FFFU) #define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT (0U) /*! SSC - sendSlopeCredit Value When AV operation is enabled, this field contains the @@ -38611,6 +46777,7 @@ typedef struct { /*! @name MTL_TXQX_HI_CRDT - Queue 1 hiCredit..Queue 4 hiCredit */ /*! @{ */ + #define ENET_QOS_MTL_TXQX_HI_CRDT_HC_MASK (0x1FFFFFFFU) #define ENET_QOS_MTL_TXQX_HI_CRDT_HC_SHIFT (0U) /*! HC - hiCredit Value When the AV feature is enabled, this field contains the hiCredit value @@ -38624,6 +46791,7 @@ typedef struct { /*! @name MTL_TXQX_LO_CRDT - Queue 1 loCredit..Queue 4 loCredit */ /*! @{ */ + #define ENET_QOS_MTL_TXQX_LO_CRDT_LC_MASK (0x1FFFFFFFU) #define ENET_QOS_MTL_TXQX_LO_CRDT_LC_SHIFT (0U) /*! LC - loCredit Value When AV operation is enabled, this field contains the loCredit value @@ -38637,6 +46805,7 @@ typedef struct { /*! @name MTL_TXQX_INTCTRL_STAT - Queue 0 Interrupt Control Status..Queue 4 Interrupt Control Status */ /*! @{ */ + #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK (0x1U) #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT (0U) /*! TXUNFIS - Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue @@ -38645,6 +46814,7 @@ typedef struct { * 0b0..Transmit Queue Underflow Interrupt Status not detected */ #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK) + #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK (0x2U) #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT (1U) /*! ABPSIS - Average Bits Per Slot Interrupt Status When set, this bit indicates that the MAC has updated the ABS value. @@ -38652,6 +46822,7 @@ typedef struct { * 0b0..Average Bits Per Slot Interrupt Status not detected */ #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK) + #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK (0x100U) #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT (8U) /*! TXUIE - Transmit Queue Underflow Interrupt Enable When this bit is set, the Transmit Queue Underflow interrupt is enabled. @@ -38659,6 +46830,7 @@ typedef struct { * 0b1..Transmit Queue Underflow Interrupt Status is enabled */ #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK) + #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK (0x200U) #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT (9U) /*! ABPSIE - Average Bits Per Slot Interrupt Enable When this bit is set, the MAC asserts the @@ -38667,6 +46839,7 @@ typedef struct { * 0b1..Average Bits Per Slot Interrupt is enabled */ #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK) + #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK (0x10000U) #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT (16U) /*! RXOVFIS - Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had @@ -38675,6 +46848,7 @@ typedef struct { * 0b0..Receive Queue Overflow Interrupt Status not detected */ #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK) + #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK (0x1000000U) #define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT (24U) /*! RXOIE - Receive Queue Overflow Interrupt Enable When this bit is set, the Receive Queue Overflow interrupt is enabled. @@ -38689,6 +46863,7 @@ typedef struct { /*! @name MTL_RXQX_OP_MODE - Queue 0 Receive Operation Mode..Queue 4 Receive Operation Mode */ /*! @{ */ + #define ENET_QOS_MTL_RXQX_OP_MODE_RTC_MASK (0x3U) #define ENET_QOS_MTL_RXQX_OP_MODE_RTC_SHIFT (0U) /*! RTC - Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue @@ -38700,6 +46875,7 @@ typedef struct { * 0b10..96 */ #define ENET_QOS_MTL_RXQX_OP_MODE_RTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RTC_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RTC_MASK) + #define ENET_QOS_MTL_RXQX_OP_MODE_FUP_MASK (0x8U) #define ENET_QOS_MTL_RXQX_OP_MODE_FUP_SHIFT (3U) /*! FUP - Forward Undersized Good Packets When this bit is set, the Rx queue forwards the undersized @@ -38709,6 +46885,7 @@ typedef struct { * 0b1..Forward Undersized Good Packets is enabled */ #define ENET_QOS_MTL_RXQX_OP_MODE_FUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_FUP_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_FUP_MASK) + #define ENET_QOS_MTL_RXQX_OP_MODE_FEP_MASK (0x10U) #define ENET_QOS_MTL_RXQX_OP_MODE_FEP_SHIFT (4U) /*! FEP - Forward Error Packets When this bit is reset, the Rx queue drops packets with error status @@ -38717,6 +46894,7 @@ typedef struct { * 0b1..Forward Error Packets is enabled */ #define ENET_QOS_MTL_RXQX_OP_MODE_FEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_FEP_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_FEP_MASK) + #define ENET_QOS_MTL_RXQX_OP_MODE_RSF_MASK (0x20U) #define ENET_QOS_MTL_RXQX_OP_MODE_RSF_SHIFT (5U) /*! RSF - Receive Queue Store and Forward When this bit is set, the DWC_ether_qos reads a packet @@ -38726,6 +46904,7 @@ typedef struct { * 0b1..Receive Queue Store and Forward is enabled */ #define ENET_QOS_MTL_RXQX_OP_MODE_RSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RSF_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RSF_MASK) + #define ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK (0x40U) #define ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT (6U) /*! DIS_TCP_EF - Disable Dropping of TCP/IP Checksum Error Packets When this bit is set, the MAC @@ -38735,6 +46914,7 @@ typedef struct { * 0b0..Dropping of TCP/IP Checksum Error Packets is enabled */ #define ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK) + #define ENET_QOS_MTL_RXQX_OP_MODE_EHFC_MASK (0x80U) #define ENET_QOS_MTL_RXQX_OP_MODE_EHFC_SHIFT (7U) /*! EHFC - Enable Hardware Flow Control When this bit is set, the flow control signal operation, @@ -38743,6 +46923,7 @@ typedef struct { * 0b1..Hardware Flow Control is enabled */ #define ENET_QOS_MTL_RXQX_OP_MODE_EHFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_EHFC_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_EHFC_MASK) + #define ENET_QOS_MTL_RXQX_OP_MODE_RFA_MASK (0xF00U) #define ENET_QOS_MTL_RXQX_OP_MODE_RFA_SHIFT (8U) /*! RFA - Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control @@ -38750,6 +46931,7 @@ typedef struct { * information on encoding for this field, see RFD. */ #define ENET_QOS_MTL_RXQX_OP_MODE_RFA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RFA_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RFA_MASK) + #define ENET_QOS_MTL_RXQX_OP_MODE_RFD_MASK (0x3C000U) #define ENET_QOS_MTL_RXQX_OP_MODE_RFD_SHIFT (14U) /*! RFD - Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits @@ -38757,6 +46939,7 @@ typedef struct { * activation: - 0: Full minus 1 KB, that is, FULL 1 KB - 1: Full minus 1. */ #define ENET_QOS_MTL_RXQX_OP_MODE_RFD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RFD_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RFD_MASK) + #define ENET_QOS_MTL_RXQX_OP_MODE_RQS_MASK (0x1F00000U) #define ENET_QOS_MTL_RXQX_OP_MODE_RQS_SHIFT (20U) /*! RQS - Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes. @@ -38769,12 +46952,14 @@ typedef struct { /*! @name MTL_RXQX_MISSPKT_OVRFLW_CNT - Queue 0 Missed Packet and Overflow Counter..Queue 4 Missed Packet and Overflow Counter */ /*! @{ */ + #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK (0x7FFU) #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT (0U) /*! OVFPKTCNT - Overflow Packet Counter This field indicates the number of packets discarded by the * DWC_ether_qos because of Receive queue overflow. */ #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK) + #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK (0x800U) #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT (11U) /*! OVFCNTOVF - Overflow Counter Overflow Bit When set, this bit indicates that the Rx Queue @@ -38783,12 +46968,14 @@ typedef struct { * 0b0..Overflow Counter overflow not detected */ #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK) + #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_MASK (0x7FF0000U) #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_SHIFT (16U) /*! MISPKTCNT - Missed Packet Counter This field indicates the number of packets missed by the * DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue. */ #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_MASK) + #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_MASK (0x8000000U) #define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_SHIFT (27U) /*! MISCNTOVF - Missed Packet Counter Overflow Bit When set, this bit indicates that the Rx Queue @@ -38804,6 +46991,7 @@ typedef struct { /*! @name MTL_RXQX_DBG - Queue 0 Receive Debug..Queue 4 Receive Debug */ /*! @{ */ + #define ENET_QOS_MTL_RXQX_DBG_RWCSTS_MASK (0x1U) #define ENET_QOS_MTL_RXQX_DBG_RWCSTS_SHIFT (0U) /*! RWCSTS - MTL Rx Queue Write Controller Active Status When high, this bit indicates that the MTL @@ -38812,6 +47000,7 @@ typedef struct { * 0b0..MTL Rx Queue Write Controller Active Status not detected */ #define ENET_QOS_MTL_RXQX_DBG_RWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_RWCSTS_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_RWCSTS_MASK) + #define ENET_QOS_MTL_RXQX_DBG_RRCSTS_MASK (0x6U) #define ENET_QOS_MTL_RXQX_DBG_RRCSTS_SHIFT (1U) /*! RRCSTS - MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller: @@ -38821,6 +47010,7 @@ typedef struct { * 0b10..Reading packet status (or timestamp) */ #define ENET_QOS_MTL_RXQX_DBG_RRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_RRCSTS_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_RRCSTS_MASK) + #define ENET_QOS_MTL_RXQX_DBG_RXQSTS_MASK (0x30U) #define ENET_QOS_MTL_RXQX_DBG_RXQSTS_SHIFT (4U) /*! RXQSTS - MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue: @@ -38830,6 +47020,7 @@ typedef struct { * 0b11..Rx Queue full */ #define ENET_QOS_MTL_RXQX_DBG_RXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_RXQSTS_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_RXQSTS_MASK) + #define ENET_QOS_MTL_RXQX_DBG_PRXQ_MASK (0x3FFF0000U) #define ENET_QOS_MTL_RXQX_DBG_PRXQ_SHIFT (16U) /*! PRXQ - Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue. @@ -38842,11 +47033,13 @@ typedef struct { /*! @name MTL_RXQX_CTRL - Queue 0 Receive Control..Queue 4 Receive Control */ /*! @{ */ + #define ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_MASK (0x7U) #define ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT (0U) /*! RXQ_WEGT - Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0. */ #define ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT)) & ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_MASK) + #define ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK (0x8U) #define ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT (3U) /*! RXQ_FRM_ARBIT - Receive Queue Packet Arbitration When this bit is set, the DWC_ether_qos drives @@ -38863,6 +47056,7 @@ typedef struct { /*! @name DMA_MODE - DMA Bus Mode */ /*! @{ */ + #define ENET_QOS_DMA_MODE_SWR_MASK (0x1U) #define ENET_QOS_DMA_MODE_SWR_SHIFT (0U) /*! SWR - Software Reset When this bit is set, the MAC and the DMA controller reset the logic and @@ -38871,6 +47065,7 @@ typedef struct { * 0b1..Software Reset is enabled */ #define ENET_QOS_DMA_MODE_SWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_MODE_SWR_SHIFT)) & ENET_QOS_DMA_MODE_SWR_MASK) + #define ENET_QOS_DMA_MODE_DSPW_MASK (0x100U) #define ENET_QOS_DMA_MODE_DSPW_SHIFT (8U) /*! DSPW - Descriptor Posted Write When this bit is set to 0, the descriptor writes are always non-posted. @@ -38878,6 +47073,7 @@ typedef struct { * 0b1..Descriptor Posted Write is enabled */ #define ENET_QOS_DMA_MODE_DSPW(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_MODE_DSPW_SHIFT)) & ENET_QOS_DMA_MODE_DSPW_MASK) + #define ENET_QOS_DMA_MODE_INTM_MASK (0x30000U) #define ENET_QOS_DMA_MODE_INTM_SHIFT (16U) /*! INTM - Interrupt Mode This field defines the interrupt mode of DWC_ether_qos. @@ -38891,6 +47087,7 @@ typedef struct { /*! @name DMA_SYSBUS_MODE - DMA System Bus Mode */ /*! @{ */ + #define ENET_QOS_DMA_SYSBUS_MODE_FB_MASK (0x1U) #define ENET_QOS_DMA_SYSBUS_MODE_FB_SHIFT (0U) /*! FB - Fixed Burst Length When this bit is set to 1, the EQOS-AXI master initiates burst transfers @@ -38899,6 +47096,7 @@ typedef struct { * 0b1..Fixed Burst Length is enabled */ #define ENET_QOS_DMA_SYSBUS_MODE_FB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_FB_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_FB_MASK) + #define ENET_QOS_DMA_SYSBUS_MODE_BLEN4_MASK (0x2U) #define ENET_QOS_DMA_SYSBUS_MODE_BLEN4_SHIFT (1U) /*! BLEN4 - AXI Burst Length 4 When this bit is set to 1 or the FB bit is set to 0, the EQOS-AXI @@ -38907,6 +47105,7 @@ typedef struct { * 0b1..AXI Burst Length 4 */ #define ENET_QOS_DMA_SYSBUS_MODE_BLEN4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_BLEN4_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_BLEN4_MASK) + #define ENET_QOS_DMA_SYSBUS_MODE_BLEN8_MASK (0x4U) #define ENET_QOS_DMA_SYSBUS_MODE_BLEN8_SHIFT (2U) /*! BLEN8 - AXI Burst Length 8 When this bit is set to 1 or the FB bit is set to 0, the EQOS-AXI @@ -38915,6 +47114,7 @@ typedef struct { * 0b1..AXI Burst Length 8 */ #define ENET_QOS_DMA_SYSBUS_MODE_BLEN8(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_BLEN8_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_BLEN8_MASK) + #define ENET_QOS_DMA_SYSBUS_MODE_BLEN16_MASK (0x8U) #define ENET_QOS_DMA_SYSBUS_MODE_BLEN16_SHIFT (3U) /*! BLEN16 - AXI Burst Length 16 When this bit is set to 1 or the FB bit is set to 0, the EQOS-AXI @@ -38923,6 +47123,7 @@ typedef struct { * 0b1..AXI Burst Length 16 */ #define ENET_QOS_DMA_SYSBUS_MODE_BLEN16(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_BLEN16_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_BLEN16_MASK) + #define ENET_QOS_DMA_SYSBUS_MODE_AALE_MASK (0x400U) #define ENET_QOS_DMA_SYSBUS_MODE_AALE_SHIFT (10U) /*! AALE - Automatic AXI LPI enable When set to 1, enables the AXI master to enter into LPI state @@ -38932,6 +47133,7 @@ typedef struct { * 0b1..Automatic AXI LPI is enabled */ #define ENET_QOS_DMA_SYSBUS_MODE_AALE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_AALE_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_AALE_MASK) + #define ENET_QOS_DMA_SYSBUS_MODE_AAL_MASK (0x1000U) #define ENET_QOS_DMA_SYSBUS_MODE_AAL_SHIFT (12U) /*! AAL - Address-Aligned Beats When this bit is set to 1, the EQOS-AXI or EQOS-AHB master performs @@ -38940,6 +47142,7 @@ typedef struct { * 0b1..Address-Aligned Beats is enabled */ #define ENET_QOS_DMA_SYSBUS_MODE_AAL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_AAL_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_AAL_MASK) + #define ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_MASK (0x2000U) #define ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_SHIFT (13U) /*! ONEKBBE - 1 KB Boundary Crossing Enable for the EQOS-AXI Master When set, the burst transfers @@ -38948,17 +47151,20 @@ typedef struct { * 0b1..1 KB Boundary Crossing for the EQOS-AXI Master Beats is enabled */ #define ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_MASK) + #define ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK (0xF0000U) #define ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT (16U) /*! RD_OSR_LMT - AXI Maximum Read Outstanding Request Limit This value limits the maximum outstanding request on the AXI read interface. */ #define ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK) + #define ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK (0xF000000U) #define ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT (24U) /*! WR_OSR_LMT - AXI Maximum Write Outstanding Request Limit This value limits the maximum * outstanding request on the AXI write interface. */ #define ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK) + #define ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_MASK (0x40000000U) #define ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_SHIFT (30U) /*! LPI_XIT_PKT - Unlock on Magic Packet or Remote Wake-Up Packet When set to 1, this bit enables @@ -38968,6 +47174,7 @@ typedef struct { * 0b1..Unlock on Magic Packet or Remote Wake-Up Packet is enabled */ #define ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_MASK) + #define ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_MASK (0x80000000U) #define ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_SHIFT (31U) /*! EN_LPI - Enable Low Power Interface (LPI) When set to 1, this bit enables the LPI mode supported @@ -38981,6 +47188,7 @@ typedef struct { /*! @name DMA_INTERRUPT_STATUS - DMA Interrupt Status */ /*! @{ */ + #define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_MASK (0x1U) #define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_SHIFT (0U) /*! DC0IS - DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0. @@ -38988,6 +47196,7 @@ typedef struct { * 0b0..DMA Channel 0 Interrupt Status not detected */ #define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_MASK) + #define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_MASK (0x2U) #define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_SHIFT (1U) /*! DC1IS - DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1. @@ -38995,6 +47204,7 @@ typedef struct { * 0b0..DMA Channel 1 Interrupt Status not detected */ #define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_MASK) + #define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK (0x4U) #define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_SHIFT (2U) /*! DC2IS - DMA Channel 2 Interrupt Status This bit indicates an interrupt event in DMA Channel 2. @@ -39002,6 +47212,7 @@ typedef struct { * 0b0..DMA Channel 2 Interrupt Status not detected */ #define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK) + #define ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_MASK (0x8U) #define ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_SHIFT (3U) /*! DC3IS - DMA Channel 3 Interrupt Status This bit indicates an interrupt event in DMA Channel 3. @@ -39009,6 +47220,7 @@ typedef struct { * 0b0..DMA Channel 3 Interrupt Status not detected */ #define ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_MASK) + #define ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_MASK (0x10U) #define ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_SHIFT (4U) /*! DC4IS - DMA Channel 4 Interrupt Status This bit indicates an interrupt event in DMA Channel 4. @@ -39016,6 +47228,7 @@ typedef struct { * 0b0..DMA Channel 4 Interrupt Status not detected */ #define ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_MASK) + #define ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_MASK (0x10000U) #define ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_SHIFT (16U) /*! MTLIS - MTL Interrupt Status This bit indicates an interrupt event in the MTL. @@ -39023,6 +47236,7 @@ typedef struct { * 0b0..MTL Interrupt Status not detected */ #define ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_MASK) + #define ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_MASK (0x20000U) #define ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_SHIFT (17U) /*! MACIS - MAC Interrupt Status This bit indicates an interrupt event in the MAC. @@ -39034,6 +47248,7 @@ typedef struct { /*! @name DMA_DEBUG_STATUS0 - DMA Debug Status 0 */ /*! @{ */ + #define ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_MASK (0x1U) #define ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT (0U) /*! AXWHSTS - AXI Master Write Channel When high, this bit indicates that the write channel of the @@ -39042,6 +47257,7 @@ typedef struct { * 0b0..AXI Master Write Channel or AHB Master Status not detected */ #define ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_MASK) + #define ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_MASK (0x2U) #define ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_SHIFT (1U) /*! AXRHSTS - AXI Master Read Channel Status When high, this bit indicates that the read channel of @@ -39050,6 +47266,7 @@ typedef struct { * 0b0..AXI Master Read Channel Status not detected */ #define ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_MASK) + #define ENET_QOS_DMA_DEBUG_STATUS0_RPS0_MASK (0xF00U) #define ENET_QOS_DMA_DEBUG_STATUS0_RPS0_SHIFT (8U) /*! RPS0 - DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel 0. @@ -39063,6 +47280,7 @@ typedef struct { * 0b0110..Timestamp write state */ #define ENET_QOS_DMA_DEBUG_STATUS0_RPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_RPS0_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_RPS0_MASK) + #define ENET_QOS_DMA_DEBUG_STATUS0_TPS0_MASK (0xF000U) #define ENET_QOS_DMA_DEBUG_STATUS0_TPS0_SHIFT (12U) /*! TPS0 - DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for Channel 0. @@ -39076,6 +47294,7 @@ typedef struct { * 0b0100..Timestamp write state */ #define ENET_QOS_DMA_DEBUG_STATUS0_TPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_TPS0_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_TPS0_MASK) + #define ENET_QOS_DMA_DEBUG_STATUS0_RPS1_MASK (0xF0000U) #define ENET_QOS_DMA_DEBUG_STATUS0_RPS1_SHIFT (16U) /*! RPS1 - DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1. @@ -39089,6 +47308,7 @@ typedef struct { * 0b0110..Timestamp write state */ #define ENET_QOS_DMA_DEBUG_STATUS0_RPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_RPS1_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_RPS1_MASK) + #define ENET_QOS_DMA_DEBUG_STATUS0_TPS1_MASK (0xF00000U) #define ENET_QOS_DMA_DEBUG_STATUS0_TPS1_SHIFT (20U) /*! TPS1 - DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1. @@ -39102,6 +47322,7 @@ typedef struct { * 0b0100..Timestamp write state */ #define ENET_QOS_DMA_DEBUG_STATUS0_TPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_TPS1_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_TPS1_MASK) + #define ENET_QOS_DMA_DEBUG_STATUS0_RPS2_MASK (0xF000000U) #define ENET_QOS_DMA_DEBUG_STATUS0_RPS2_SHIFT (24U) /*! RPS2 - DMA Channel 2 Receive Process State This field indicates the Rx DMA FSM state for Channel 2. @@ -39115,6 +47336,7 @@ typedef struct { * 0b0110..Timestamp write state */ #define ENET_QOS_DMA_DEBUG_STATUS0_RPS2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_RPS2_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_RPS2_MASK) + #define ENET_QOS_DMA_DEBUG_STATUS0_TPS2_MASK (0xF0000000U) #define ENET_QOS_DMA_DEBUG_STATUS0_TPS2_SHIFT (28U) /*! TPS2 - DMA Channel 2 Transmit Process State This field indicates the Tx DMA FSM state for Channel 2. @@ -39132,6 +47354,7 @@ typedef struct { /*! @name DMA_DEBUG_STATUS1 - DMA Debug Status 1 */ /*! @{ */ + #define ENET_QOS_DMA_DEBUG_STATUS1_RPS3_MASK (0xFU) #define ENET_QOS_DMA_DEBUG_STATUS1_RPS3_SHIFT (0U) /*! RPS3 - DMA Channel 3 Receive Process State This field indicates the Rx DMA FSM state for Channel 3. @@ -39145,6 +47368,7 @@ typedef struct { * 0b0110..Timestamp write state */ #define ENET_QOS_DMA_DEBUG_STATUS1_RPS3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_RPS3_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_RPS3_MASK) + #define ENET_QOS_DMA_DEBUG_STATUS1_TPS3_MASK (0xF0U) #define ENET_QOS_DMA_DEBUG_STATUS1_TPS3_SHIFT (4U) /*! TPS3 - DMA Channel 3 Transmit Process State This field indicates the Tx DMA FSM state for Channel 3. @@ -39158,6 +47382,7 @@ typedef struct { * 0b0100..Timestamp write state */ #define ENET_QOS_DMA_DEBUG_STATUS1_TPS3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_TPS3_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_TPS3_MASK) + #define ENET_QOS_DMA_DEBUG_STATUS1_RPS4_MASK (0xF00U) #define ENET_QOS_DMA_DEBUG_STATUS1_RPS4_SHIFT (8U) /*! RPS4 - DMA Channel 4 Receive Process State This field indicates the Rx DMA FSM state for Channel 4. @@ -39171,6 +47396,7 @@ typedef struct { * 0b0110..Timestamp write state */ #define ENET_QOS_DMA_DEBUG_STATUS1_RPS4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_RPS4_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_RPS4_MASK) + #define ENET_QOS_DMA_DEBUG_STATUS1_TPS4_MASK (0xF000U) #define ENET_QOS_DMA_DEBUG_STATUS1_TPS4_SHIFT (12U) /*! TPS4 - DMA Channel 4 Transmit Process State This field indicates the Tx DMA FSM state for Channel 4. @@ -39188,6 +47414,7 @@ typedef struct { /*! @name DMA_AXI_LPI_ENTRY_INTERVAL - AXI LPI Entry Interval Control */ /*! @{ */ + #define ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_MASK (0xFU) #define ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_SHIFT (0U) /*! LPIEI - LPI Entry Interval Contains the number of system clock cycles, multiplied by 64, to wait @@ -39199,6 +47426,7 @@ typedef struct { /*! @name DMA_TBS_CTRL - TBS Control */ /*! @{ */ + #define ENET_QOS_DMA_TBS_CTRL_FTOV_MASK (0x1U) #define ENET_QOS_DMA_TBS_CTRL_FTOV_SHIFT (0U) /*! FTOV - Fetch Time Offset Valid When set indicates the FTOS field is valid. @@ -39206,11 +47434,13 @@ typedef struct { * 0b1..Fetch Time Offset is valid */ #define ENET_QOS_DMA_TBS_CTRL_FTOV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL_FTOV_SHIFT)) & ENET_QOS_DMA_TBS_CTRL_FTOV_MASK) + #define ENET_QOS_DMA_TBS_CTRL_FGOS_MASK (0x70U) #define ENET_QOS_DMA_TBS_CTRL_FGOS_SHIFT (4U) /*! FGOS - Fetch GSN Offset The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN. */ #define ENET_QOS_DMA_TBS_CTRL_FGOS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL_FGOS_SHIFT)) & ENET_QOS_DMA_TBS_CTRL_FGOS_MASK) + #define ENET_QOS_DMA_TBS_CTRL_FTOS_MASK (0xFFFFFF00U) #define ENET_QOS_DMA_TBS_CTRL_FTOS_SHIFT (8U) /*! FTOS - Fetch Time Offset The value in units of 256 nanoseconds, that has to be deducted from the @@ -39221,6 +47451,7 @@ typedef struct { /*! @name DMA_CHX_CTRL - DMA Channel 0 Control..DMA Channel 4 Control */ /*! @{ */ + #define ENET_QOS_DMA_CHX_CTRL_PBLx8_MASK (0x10000U) #define ENET_QOS_DMA_CHX_CTRL_PBLx8_SHIFT (16U) /*! PBLx8 - 8xPBL mode When this bit is set, the PBL value programmed in Bits[21:16] in @@ -39229,6 +47460,7 @@ typedef struct { * 0b1..8xPBL mode is enabled */ #define ENET_QOS_DMA_CHX_CTRL_PBLx8(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CTRL_PBLx8_SHIFT)) & ENET_QOS_DMA_CHX_CTRL_PBLx8_MASK) + #define ENET_QOS_DMA_CHX_CTRL_DSL_MASK (0x1C0000U) #define ENET_QOS_DMA_CHX_CTRL_DSL_SHIFT (18U) /*! DSL - Descriptor Skip Length This bit specifies the Word, Dword, or Lword number (depending on @@ -39242,6 +47474,7 @@ typedef struct { /*! @name DMA_CHX_TX_CTRL - DMA Channel 0 Transmit Control..DMA Channel 4 Transmit Control */ /*! @{ */ + #define ENET_QOS_DMA_CHX_TX_CTRL_ST_MASK (0x1U) #define ENET_QOS_DMA_CHX_TX_CTRL_ST_SHIFT (0U) /*! ST - Start or Stop Transmission Command When this bit is set, transmission is placed in the Running state. @@ -39249,6 +47482,7 @@ typedef struct { * 0b0..Stop Transmission Command */ #define ENET_QOS_DMA_CHX_TX_CTRL_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_ST_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_ST_MASK) + #define ENET_QOS_DMA_CHX_TX_CTRL_OSF_MASK (0x10U) #define ENET_QOS_DMA_CHX_TX_CTRL_OSF_SHIFT (4U) /*! OSF - Operate on Second Packet When this bit is set, it instructs the DMA to process the second @@ -39257,6 +47491,7 @@ typedef struct { * 0b1..Operate on Second Packet enabled */ #define ENET_QOS_DMA_CHX_TX_CTRL_OSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_OSF_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_OSF_MASK) + #define ENET_QOS_DMA_CHX_TX_CTRL_IPBL_MASK (0x8000U) #define ENET_QOS_DMA_CHX_TX_CTRL_IPBL_SHIFT (15U) /*! IPBL - Ignore PBL Requirement When this bit is set, the DMA does not check for PBL number of @@ -39265,12 +47500,14 @@ typedef struct { * 0b1..Ignore PBL Requirement is enabled */ #define ENET_QOS_DMA_CHX_TX_CTRL_IPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_IPBL_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_IPBL_MASK) + #define ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_MASK (0x3F0000U) #define ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_SHIFT (16U) /*! TxPBL - Transmit Programmable Burst Length These bits indicate the maximum number of beats to be * transferred in one DMA block data transfer. */ #define ENET_QOS_DMA_CHX_TX_CTRL_TxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_MASK) + #define ENET_QOS_DMA_CHX_TX_CTRL_EDSE_MASK (0x10000000U) #define ENET_QOS_DMA_CHX_TX_CTRL_EDSE_SHIFT (28U) /*! EDSE - Enhanced Descriptor Enable When this bit is set, the corresponding channel uses Enhanced @@ -39286,6 +47523,7 @@ typedef struct { /*! @name DMA_CHX_RX_CTRL - DMA Channel 0 Receive Control..DMA Channel 4 Receive Control */ /*! @{ */ + #define ENET_QOS_DMA_CHX_RX_CTRL_SR_MASK (0x1U) #define ENET_QOS_DMA_CHX_RX_CTRL_SR_SHIFT (0U) /*! SR - Start or Stop Receive When this bit is set, the DMA tries to acquire the descriptor from @@ -39294,22 +47532,26 @@ typedef struct { * 0b0..Stop Receive */ #define ENET_QOS_DMA_CHX_RX_CTRL_SR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_SR_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_SR_MASK) + #define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_MASK (0xEU) #define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_SHIFT (1U) /*! RBSZ_x_0 - Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0. */ #define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_MASK) + #define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_MASK (0x7FF0U) #define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_SHIFT (4U) /*! RBSZ_13_y - Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0. */ #define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_MASK) + #define ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_MASK (0x3F0000U) #define ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_SHIFT (16U) /*! RxPBL - Receive Programmable Burst Length These bits indicate the maximum number of beats to be * transferred in one DMA block data transfer. */ #define ENET_QOS_DMA_CHX_RX_CTRL_RxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_MASK) + #define ENET_QOS_DMA_CHX_RX_CTRL_RPF_MASK (0x80000000U) #define ENET_QOS_DMA_CHX_RX_CTRL_RPF_SHIFT (31U) /*! RPF - Rx Packet Flush. @@ -39324,6 +47566,7 @@ typedef struct { /*! @name DMA_CHX_TXDESC_LIST_ADDR - Channel 0 Tx Descriptor List Address register..Channel 4 Tx Descriptor List Address */ /*! @{ */ + #define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_MASK (0xFFFFFFF8U) #define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_SHIFT (3U) /*! TDESLA - Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list. @@ -39336,6 +47579,7 @@ typedef struct { /*! @name DMA_CHX_RXDESC_LIST_ADDR - Channel 0 Rx Descriptor List Address register..Channel 4 Rx Descriptor List Address */ /*! @{ */ + #define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_MASK (0xFFFFFFF8U) #define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_SHIFT (3U) /*! RDESLA - Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list. @@ -39348,6 +47592,7 @@ typedef struct { /*! @name DMA_CHX_TXDESC_TAIL_PTR - Channel 0 Tx Descriptor Tail Pointer..Channel 4 Tx Descriptor Tail Pointer */ /*! @{ */ + #define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK (0xFFFFFFF8U) #define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT (3U) /*! TDTP - Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring. @@ -39360,6 +47605,7 @@ typedef struct { /*! @name DMA_CHX_RXDESC_TAIL_PTR - Channel 0 Rx Descriptor Tail Pointer..Channel 4 Rx Descriptor Tail Pointer */ /*! @{ */ + #define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK (0xFFFFFFF8U) #define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT (3U) /*! RDTP - Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring. @@ -39372,6 +47618,7 @@ typedef struct { /*! @name DMA_CHX_TXDESC_RING_LENGTH - Channel 0 Tx Descriptor Ring Length..Channel 4 Tx Descriptor Ring Length */ /*! @{ */ + #define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU) #define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT (0U) /*! TDRL - Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring. @@ -39384,6 +47631,7 @@ typedef struct { /*! @name DMA_CHX_RXDESC_RING_LENGTH - Channel 0 Rx Descriptor Ring Length..Channel 4 Rx Descriptor Ring Length */ /*! @{ */ + #define ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU) #define ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT (0U) /*! RDRL - Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring. @@ -39396,6 +47644,7 @@ typedef struct { /*! @name DMA_CHX_INT_EN - Channel 0 Interrupt Enable..Channel 4 Interrupt Enable */ /*! @{ */ + #define ENET_QOS_DMA_CHX_INT_EN_TIE_MASK (0x1U) #define ENET_QOS_DMA_CHX_INT_EN_TIE_SHIFT (0U) /*! TIE - Transmit Interrupt Enable When this bit is set along with the NIE bit, the Transmit Interrupt is enabled. @@ -39403,6 +47652,7 @@ typedef struct { * 0b1..Transmit Interrupt is enabled */ #define ENET_QOS_DMA_CHX_INT_EN_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_TIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_TIE_MASK) + #define ENET_QOS_DMA_CHX_INT_EN_TXSE_MASK (0x2U) #define ENET_QOS_DMA_CHX_INT_EN_TXSE_SHIFT (1U) /*! TXSE - Transmit Stopped Enable When this bit is set along with the AIE bit, the Transmission Stopped interrupt is enabled. @@ -39410,6 +47660,7 @@ typedef struct { * 0b1..Transmit Stopped is enabled */ #define ENET_QOS_DMA_CHX_INT_EN_TXSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_TXSE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_TXSE_MASK) + #define ENET_QOS_DMA_CHX_INT_EN_TBUE_MASK (0x4U) #define ENET_QOS_DMA_CHX_INT_EN_TBUE_SHIFT (2U) /*! TBUE - Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit, the @@ -39418,6 +47669,7 @@ typedef struct { * 0b1..Transmit Buffer Unavailable is enabled */ #define ENET_QOS_DMA_CHX_INT_EN_TBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_TBUE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_TBUE_MASK) + #define ENET_QOS_DMA_CHX_INT_EN_RIE_MASK (0x40U) #define ENET_QOS_DMA_CHX_INT_EN_RIE_SHIFT (6U) /*! RIE - Receive Interrupt Enable When this bit is set along with the NIE bit, the Receive Interrupt is enabled. @@ -39425,6 +47677,7 @@ typedef struct { * 0b1..Receive Interrupt is enabled */ #define ENET_QOS_DMA_CHX_INT_EN_RIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RIE_MASK) + #define ENET_QOS_DMA_CHX_INT_EN_RBUE_MASK (0x80U) #define ENET_QOS_DMA_CHX_INT_EN_RBUE_SHIFT (7U) /*! RBUE - Receive Buffer Unavailable Enable When this bit is set along with the AIE bit, the @@ -39433,6 +47686,7 @@ typedef struct { * 0b1..Receive Buffer Unavailable is enabled */ #define ENET_QOS_DMA_CHX_INT_EN_RBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RBUE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RBUE_MASK) + #define ENET_QOS_DMA_CHX_INT_EN_RSE_MASK (0x100U) #define ENET_QOS_DMA_CHX_INT_EN_RSE_SHIFT (8U) /*! RSE - Receive Stopped Enable When this bit is set along with the AIE bit, the Receive Stopped Interrupt is enabled. @@ -39440,6 +47694,7 @@ typedef struct { * 0b1..Receive Stopped is enabled */ #define ENET_QOS_DMA_CHX_INT_EN_RSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RSE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RSE_MASK) + #define ENET_QOS_DMA_CHX_INT_EN_RWTE_MASK (0x200U) #define ENET_QOS_DMA_CHX_INT_EN_RWTE_SHIFT (9U) /*! RWTE - Receive Watchdog Timeout Enable When this bit is set along with the AIE bit, the Receive @@ -39448,6 +47703,7 @@ typedef struct { * 0b1..Receive Watchdog Timeout is enabled */ #define ENET_QOS_DMA_CHX_INT_EN_RWTE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RWTE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RWTE_MASK) + #define ENET_QOS_DMA_CHX_INT_EN_ETIE_MASK (0x400U) #define ENET_QOS_DMA_CHX_INT_EN_ETIE_SHIFT (10U) /*! ETIE - Early Transmit Interrupt Enable When this bit is set along with the AIE bit, the Early Transmit interrupt is enabled. @@ -39455,6 +47711,7 @@ typedef struct { * 0b1..Early Transmit Interrupt is enabled */ #define ENET_QOS_DMA_CHX_INT_EN_ETIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_ETIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_ETIE_MASK) + #define ENET_QOS_DMA_CHX_INT_EN_ERIE_MASK (0x800U) #define ENET_QOS_DMA_CHX_INT_EN_ERIE_SHIFT (11U) /*! ERIE - Early Receive Interrupt Enable When this bit is set along with the NIE bit, the Early Receive interrupt is enabled. @@ -39462,6 +47719,7 @@ typedef struct { * 0b1..Early Receive Interrupt is enabled */ #define ENET_QOS_DMA_CHX_INT_EN_ERIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_ERIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_ERIE_MASK) + #define ENET_QOS_DMA_CHX_INT_EN_FBEE_MASK (0x1000U) #define ENET_QOS_DMA_CHX_INT_EN_FBEE_SHIFT (12U) /*! FBEE - Fatal Bus Error Enable When this bit is set along with the AIE bit, the Fatal Bus error interrupt is enabled. @@ -39469,6 +47727,7 @@ typedef struct { * 0b1..Fatal Bus Error is enabled */ #define ENET_QOS_DMA_CHX_INT_EN_FBEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_FBEE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_FBEE_MASK) + #define ENET_QOS_DMA_CHX_INT_EN_CDEE_MASK (0x2000U) #define ENET_QOS_DMA_CHX_INT_EN_CDEE_SHIFT (13U) /*! CDEE - Context Descriptor Error Enable When this bit is set along with the AIE bit, the Descriptor error interrupt is enabled. @@ -39476,6 +47735,7 @@ typedef struct { * 0b1..Context Descriptor Error is enabled */ #define ENET_QOS_DMA_CHX_INT_EN_CDEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_CDEE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_CDEE_MASK) + #define ENET_QOS_DMA_CHX_INT_EN_AIE_MASK (0x4000U) #define ENET_QOS_DMA_CHX_INT_EN_AIE_SHIFT (14U) /*! AIE - Abnormal Interrupt Summary Enable When this bit is set, the abnormal interrupt summary is enabled. @@ -39483,6 +47743,7 @@ typedef struct { * 0b1..Abnormal Interrupt Summary is enabled */ #define ENET_QOS_DMA_CHX_INT_EN_AIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_AIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_AIE_MASK) + #define ENET_QOS_DMA_CHX_INT_EN_NIE_MASK (0x8000U) #define ENET_QOS_DMA_CHX_INT_EN_NIE_SHIFT (15U) /*! NIE - Normal Interrupt Summary Enable When this bit is set, the normal interrupt summary is enabled. @@ -39497,12 +47758,14 @@ typedef struct { /*! @name DMA_CHX_RX_INT_WDTIMER - Channel 0 Receive Interrupt Watchdog Timer..Channel 4 Receive Interrupt Watchdog Timer */ /*! @{ */ + #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_MASK (0xFFU) #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_SHIFT (0U) /*! RWT - Receive Interrupt Watchdog Timer Count This field indicates the number of system clock * cycles, multiplied by factor indicated in RWTU field, for which the watchdog timer is set. */ #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_SHIFT)) & ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_MASK) + #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_MASK (0x30000U) #define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_SHIFT (16U) /*! RWTU - Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system @@ -39516,6 +47779,7 @@ typedef struct { /*! @name DMA_CHX_SLOT_FUNC_CTRL_STAT - Channel 0 Slot Function Control and Status..Channel 4 Slot Function Control and Status */ /*! @{ */ + #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK (0x1U) #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT (0U) /*! ESC - Enable Slot Comparison When set, this bit enables the checking of the slot numbers @@ -39524,6 +47788,7 @@ typedef struct { * 0b1..Slot Comparison is enabled */ #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK) + #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK (0x2U) #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT (1U) /*! ASC - Advance Slot Check When set, this bit enables the DMA to fetch the data from the buffer @@ -39534,12 +47799,14 @@ typedef struct { * 0b1..Advance Slot Check is enabled */ #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK) + #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_MASK (0xFFF0U) #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_SHIFT (4U) /*! SIV - Slot Interval Value This field controls the period of the slot interval in which the TxDMA * fetches the scheduled packets. */ #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_MASK) + #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK (0xF0000U) #define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT (16U) /*! RSN - Reference Slot Number This field gives the current value of the reference slot number in the DMA. @@ -39552,6 +47819,7 @@ typedef struct { /*! @name DMA_CHX_CUR_HST_TXDESC - Channel 0 Current Application Transmit Descriptor..Channel 4 Current Application Transmit Descriptor */ /*! @{ */ + #define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_MASK (0xFFFFFFFFU) #define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_SHIFT (0U) /*! CURTDESAPTR - Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation. @@ -39564,6 +47832,7 @@ typedef struct { /*! @name DMA_CHX_CUR_HST_RXDESC - Channel 0 Current Application Receive Descriptor..Channel 4 Current Application Receive Descriptor */ /*! @{ */ + #define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_MASK (0xFFFFFFFFU) #define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_SHIFT (0U) /*! CURRDESAPTR - Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation. @@ -39576,6 +47845,7 @@ typedef struct { /*! @name DMA_CHX_CUR_HST_TXBUF - Channel 0 Current Application Transmit Buffer Address..Channel 4 Current Application Transmit Buffer Address */ /*! @{ */ + #define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_MASK (0xFFFFFFFFU) #define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_SHIFT (0U) /*! CURTBUFAPTR - Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. @@ -39588,6 +47858,7 @@ typedef struct { /*! @name DMA_CHX_CUR_HST_RXBUF - Channel 0 Current Application Receive Buffer Address..Channel 4 Current Application Receive Buffer Address */ /*! @{ */ + #define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_MASK (0xFFFFFFFFU) #define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_SHIFT (0U) /*! CURRBUFAPTR - Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. @@ -39600,6 +47871,7 @@ typedef struct { /*! @name DMA_CHX_STAT - DMA Channel 0 Status..DMA Channel 4 Status */ /*! @{ */ + #define ENET_QOS_DMA_CHX_STAT_TI_MASK (0x1U) #define ENET_QOS_DMA_CHX_STAT_TI_SHIFT (0U) /*! TI - Transmit Interrupt This bit indicates that the packet transmission is complete. @@ -39607,6 +47879,7 @@ typedef struct { * 0b0..Transmit Interrupt status not detected */ #define ENET_QOS_DMA_CHX_STAT_TI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TI_MASK) + #define ENET_QOS_DMA_CHX_STAT_TPS_MASK (0x2U) #define ENET_QOS_DMA_CHX_STAT_TPS_SHIFT (1U) /*! TPS - Transmit Process Stopped This bit is set when the transmission is stopped. @@ -39614,6 +47887,7 @@ typedef struct { * 0b0..Transmit Process Stopped status not detected */ #define ENET_QOS_DMA_CHX_STAT_TPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TPS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TPS_MASK) + #define ENET_QOS_DMA_CHX_STAT_TBU_MASK (0x4U) #define ENET_QOS_DMA_CHX_STAT_TBU_SHIFT (2U) /*! TBU - Transmit Buffer Unavailable This bit indicates that the application owns the next @@ -39622,6 +47896,7 @@ typedef struct { * 0b0..Transmit Buffer Unavailable status not detected */ #define ENET_QOS_DMA_CHX_STAT_TBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TBU_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TBU_MASK) + #define ENET_QOS_DMA_CHX_STAT_RI_MASK (0x40U) #define ENET_QOS_DMA_CHX_STAT_RI_SHIFT (6U) /*! RI - Receive Interrupt This bit indicates that the packet reception is complete. @@ -39629,6 +47904,7 @@ typedef struct { * 0b0..Receive Interrupt status not detected */ #define ENET_QOS_DMA_CHX_STAT_RI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RI_MASK) + #define ENET_QOS_DMA_CHX_STAT_RBU_MASK (0x80U) #define ENET_QOS_DMA_CHX_STAT_RBU_SHIFT (7U) /*! RBU - Receive Buffer Unavailable This bit indicates that the application owns the next @@ -39637,6 +47913,7 @@ typedef struct { * 0b0..Receive Buffer Unavailable status not detected */ #define ENET_QOS_DMA_CHX_STAT_RBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RBU_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RBU_MASK) + #define ENET_QOS_DMA_CHX_STAT_RPS_MASK (0x100U) #define ENET_QOS_DMA_CHX_STAT_RPS_SHIFT (8U) /*! RPS - Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state. @@ -39644,6 +47921,7 @@ typedef struct { * 0b0..Receive Process Stopped status not detected */ #define ENET_QOS_DMA_CHX_STAT_RPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RPS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RPS_MASK) + #define ENET_QOS_DMA_CHX_STAT_RWT_MASK (0x200U) #define ENET_QOS_DMA_CHX_STAT_RWT_SHIFT (9U) /*! RWT - Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2,048 @@ -39652,6 +47930,7 @@ typedef struct { * 0b0..Receive Watchdog Timeout status not detected */ #define ENET_QOS_DMA_CHX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RWT_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RWT_MASK) + #define ENET_QOS_DMA_CHX_STAT_ETI_MASK (0x400U) #define ENET_QOS_DMA_CHX_STAT_ETI_SHIFT (10U) /*! ETI - Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the @@ -39660,6 +47939,7 @@ typedef struct { * 0b0..Early Transmit Interrupt status not detected */ #define ENET_QOS_DMA_CHX_STAT_ETI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_ETI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_ETI_MASK) + #define ENET_QOS_DMA_CHX_STAT_ERI_MASK (0x800U) #define ENET_QOS_DMA_CHX_STAT_ERI_SHIFT (11U) /*! ERI - Early Receive Interrupt This bit when set indicates that the RxDMA has completed the @@ -39668,6 +47948,7 @@ typedef struct { * 0b0..Early Receive Interrupt status not detected */ #define ENET_QOS_DMA_CHX_STAT_ERI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_ERI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_ERI_MASK) + #define ENET_QOS_DMA_CHX_STAT_FBE_MASK (0x1000U) #define ENET_QOS_DMA_CHX_STAT_FBE_SHIFT (12U) /*! FBE - Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field). @@ -39675,6 +47956,7 @@ typedef struct { * 0b0..Fatal Bus Error status not detected */ #define ENET_QOS_DMA_CHX_STAT_FBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_FBE_SHIFT)) & ENET_QOS_DMA_CHX_STAT_FBE_MASK) + #define ENET_QOS_DMA_CHX_STAT_CDE_MASK (0x2000U) #define ENET_QOS_DMA_CHX_STAT_CDE_SHIFT (13U) /*! CDE - Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a @@ -39685,6 +47967,7 @@ typedef struct { * 0b0..Context Descriptor Error status not detected */ #define ENET_QOS_DMA_CHX_STAT_CDE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_CDE_SHIFT)) & ENET_QOS_DMA_CHX_STAT_CDE_MASK) + #define ENET_QOS_DMA_CHX_STAT_AIS_MASK (0x4000U) #define ENET_QOS_DMA_CHX_STAT_AIS_SHIFT (14U) /*! AIS - Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the @@ -39696,6 +47979,7 @@ typedef struct { * 0b0..Abnormal Interrupt Summary status not detected */ #define ENET_QOS_DMA_CHX_STAT_AIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_AIS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_AIS_MASK) + #define ENET_QOS_DMA_CHX_STAT_NIS_MASK (0x8000U) #define ENET_QOS_DMA_CHX_STAT_NIS_SHIFT (15U) /*! NIS - Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the @@ -39707,11 +47991,13 @@ typedef struct { * 0b0..Normal Interrupt Summary status not detected */ #define ENET_QOS_DMA_CHX_STAT_NIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_NIS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_NIS_MASK) + #define ENET_QOS_DMA_CHX_STAT_TEB_MASK (0x70000U) #define ENET_QOS_DMA_CHX_STAT_TEB_SHIFT (16U) /*! TEB - Tx DMA Error Bits This field indicates the type of error that caused a Bus Error. */ #define ENET_QOS_DMA_CHX_STAT_TEB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TEB_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TEB_MASK) + #define ENET_QOS_DMA_CHX_STAT_REB_MASK (0x380000U) #define ENET_QOS_DMA_CHX_STAT_REB_SHIFT (19U) /*! REB - Rx DMA Error Bits This field indicates the type of error that caused a Bus Error. @@ -39724,6 +48010,7 @@ typedef struct { /*! @name DMA_CHX_MISS_FRAME_CNT - Channel 0 Missed Frame Counter..Channel 4 Missed Frame Counter */ /*! @{ */ + #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_MASK (0x7FFU) #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT (0U) /*! MFC - Dropped Packet Counters This counter indicates the number of packet counters that are @@ -39731,6 +48018,7 @@ typedef struct { * DMA_CH2_RX_CONTROL register. */ #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT)) & ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_MASK) + #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK (0x8000U) #define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT (15U) /*! MFCO - Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further. @@ -39745,11 +48033,13 @@ typedef struct { /*! @name DMA_CHX_RXP_ACCEPT_CNT - Channel 0 RXP Frames Accepted Counter..Channel 4 RXP Frames Accepted Counter */ /*! @{ */ + #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_MASK (0x7FFFFFFFU) #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_SHIFT (0U) /*! RXPAC - Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1. */ #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_SHIFT)) & ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_MASK) + #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_MASK (0x80000000U) #define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_SHIFT (31U) /*! RXPACOF - Rx Parser Accept Counter Overflow Bit When set, this bit indicates that the RXPAC @@ -39765,6 +48055,7 @@ typedef struct { /*! @name DMA_CHX_RX_ERI_CNT - Channel 0 Receive ERI Counter..Channel 4 Receive ERI Counter */ /*! @{ */ + #define ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT_MASK (0xFFFU) #define ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT_SHIFT (0U) /*! ECNT - ERI Counter When ERIC bit of DMA_CH4_RX_CONTROL register is set, this counter increments @@ -39835,30 +48126,6 @@ typedef struct { __IO uint32_t CLR; /**< Fractional PLL Denominator Control Register, offset: 0x38 */ __IO uint32_t TOG; /**< Fractional PLL Denominator Control Register, offset: 0x3C */ } DENOMINATOR; - struct { /* offset: 0x40 */ - uint32_t RW; /**< Fractional PLL Reserved Control Register, offset: 0x40 */ - uint32_t SET; /**< Fractional PLL Reserved Control Register, offset: 0x44 */ - uint32_t CLR; /**< Fractional PLL Reserved Control Register, offset: 0x48 */ - uint32_t TOG; /**< Fractional PLL Reserved Control Register, offset: 0x4C */ - } CTRL4; - struct { /* offset: 0x50 */ - __I uint32_t RW; /**< Analog Status Register STAT0, offset: 0x50 */ - __I uint32_t SET; /**< Analog Status Register STAT0, offset: 0x54 */ - __I uint32_t CLR; /**< Analog Status Register STAT0, offset: 0x58 */ - __I uint32_t TOG; /**< Analog Status Register STAT0, offset: 0x5C */ - } STAT0; - struct { /* offset: 0x60 */ - __I uint32_t RW; /**< Analog Status Register STAT1, offset: 0x60 */ - __I uint32_t SET; /**< Analog Status Register STAT1, offset: 0x64 */ - __I uint32_t CLR; /**< Analog Status Register STAT1, offset: 0x68 */ - __I uint32_t TOG; /**< Analog Status Register STAT1, offset: 0x6C */ - } STAT1; - struct { /* offset: 0x70 */ - __I uint32_t RW; /**< Analog Status Register STAT2, offset: 0x70 */ - __I uint32_t SET; /**< Analog Status Register STAT2, offset: 0x74 */ - __I uint32_t CLR; /**< Analog Status Register STAT2, offset: 0x78 */ - __I uint32_t TOG; /**< Analog Status Register STAT2, offset: 0x7C */ - } STAT2; } ETHERNET_PLL_Type; /* ---------------------------------------------------------------------------- @@ -39872,105 +48139,109 @@ typedef struct { /*! @name CTRL0 - Fractional PLL Control Register */ /*! @{ */ + #define ETHERNET_PLL_CTRL0_DIV_SELECT_MASK (0x7FU) #define ETHERNET_PLL_CTRL0_DIV_SELECT_SHIFT (0U) /*! DIV_SELECT - DIV_SELECT */ #define ETHERNET_PLL_CTRL0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_DIV_SELECT_SHIFT)) & ETHERNET_PLL_CTRL0_DIV_SELECT_MASK) -#define ETHERNET_PLL_CTRL0_HALF_LF_MASK (0x200U) -#define ETHERNET_PLL_CTRL0_HALF_LF_SHIFT (9U) -/*! HALF_LF - HALF_LF - */ -#define ETHERNET_PLL_CTRL0_HALF_LF(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_HALF_LF_SHIFT)) & ETHERNET_PLL_CTRL0_HALF_LF_MASK) -#define ETHERNET_PLL_CTRL0_DOUBLE_LF_MASK (0x400U) -#define ETHERNET_PLL_CTRL0_DOUBLE_LF_SHIFT (10U) -/*! DOUBLE_LF - DOUBLE_LF - */ -#define ETHERNET_PLL_CTRL0_DOUBLE_LF(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_DOUBLE_LF_SHIFT)) & ETHERNET_PLL_CTRL0_DOUBLE_LF_MASK) -#define ETHERNET_PLL_CTRL0_HALF_CP_MASK (0x800U) -#define ETHERNET_PLL_CTRL0_HALF_CP_SHIFT (11U) -/*! HALF_CP - HALF_CP - */ -#define ETHERNET_PLL_CTRL0_HALF_CP(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_HALF_CP_SHIFT)) & ETHERNET_PLL_CTRL0_HALF_CP_MASK) -#define ETHERNET_PLL_CTRL0_DOUBLE_CP_MASK (0x1000U) -#define ETHERNET_PLL_CTRL0_DOUBLE_CP_SHIFT (12U) -/*! DOUBLE_CP - DOUBLE_CP - */ -#define ETHERNET_PLL_CTRL0_DOUBLE_CP(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_DOUBLE_CP_SHIFT)) & ETHERNET_PLL_CTRL0_DOUBLE_CP_MASK) + +#define ETHERNET_PLL_CTRL0_ENABLE_ALT_MASK (0x100U) +#define ETHERNET_PLL_CTRL0_ENABLE_ALT_SHIFT (8U) +/*! ENABLE_ALT - ENABLE_ALT + * 0b0..Disable the alternate clock output + * 0b1..Enable the alternate clock output which is the output of the post_divider, and cannot be bypassed + */ +#define ETHERNET_PLL_CTRL0_ENABLE_ALT(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_ENABLE_ALT_SHIFT)) & ETHERNET_PLL_CTRL0_ENABLE_ALT_MASK) + #define ETHERNET_PLL_CTRL0_HOLD_RING_OFF_MASK (0x2000U) #define ETHERNET_PLL_CTRL0_HOLD_RING_OFF_SHIFT (13U) -/*! HOLD_RING_OFF - HOLD_RING_OFF +/*! HOLD_RING_OFF - PLL Start up initialization + * 0b0..Normal operation + * 0b1..Initialize PLL start up */ #define ETHERNET_PLL_CTRL0_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_HOLD_RING_OFF_SHIFT)) & ETHERNET_PLL_CTRL0_HOLD_RING_OFF_MASK) + #define ETHERNET_PLL_CTRL0_POWERUP_MASK (0x4000U) #define ETHERNET_PLL_CTRL0_POWERUP_SHIFT (14U) /*! POWERUP - POWERUP + * 0b1..Power Up the PLL + * 0b0..Power down the PLL */ #define ETHERNET_PLL_CTRL0_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_POWERUP_SHIFT)) & ETHERNET_PLL_CTRL0_POWERUP_MASK) + #define ETHERNET_PLL_CTRL0_ENABLE_MASK (0x8000U) #define ETHERNET_PLL_CTRL0_ENABLE_SHIFT (15U) /*! ENABLE - ENABLE + * 0b1..Enable the clock output + * 0b0..Disable the clock output */ #define ETHERNET_PLL_CTRL0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_ENABLE_SHIFT)) & ETHERNET_PLL_CTRL0_ENABLE_MASK) + #define ETHERNET_PLL_CTRL0_BYPASS_MASK (0x10000U) #define ETHERNET_PLL_CTRL0_BYPASS_SHIFT (16U) /*! BYPASS - BYPASS + * 0b1..Bypass the PLL + * 0b0..No Bypass */ #define ETHERNET_PLL_CTRL0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_BYPASS_SHIFT)) & ETHERNET_PLL_CTRL0_BYPASS_MASK) + #define ETHERNET_PLL_CTRL0_DITHER_EN_MASK (0x20000U) #define ETHERNET_PLL_CTRL0_DITHER_EN_SHIFT (17U) /*! DITHER_EN - DITHER_EN + * 0b0..Disable Dither + * 0b1..Enable Dither */ #define ETHERNET_PLL_CTRL0_DITHER_EN(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_DITHER_EN_SHIFT)) & ETHERNET_PLL_CTRL0_DITHER_EN_MASK) -#define ETHERNET_PLL_CTRL0_PFD_OFFSET_EN_MASK (0x40000U) -#define ETHERNET_PLL_CTRL0_PFD_OFFSET_EN_SHIFT (18U) -/*! PFD_OFFSET_EN - PFD_OFFSET_EN - */ -#define ETHERNET_PLL_CTRL0_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_PFD_OFFSET_EN_SHIFT)) & ETHERNET_PLL_CTRL0_PFD_OFFSET_EN_MASK) + #define ETHERNET_PLL_CTRL0_BIAS_TRIM_MASK (0x380000U) #define ETHERNET_PLL_CTRL0_BIAS_TRIM_SHIFT (19U) /*! BIAS_TRIM - BIAS_TRIM */ #define ETHERNET_PLL_CTRL0_BIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_BIAS_TRIM_SHIFT)) & ETHERNET_PLL_CTRL0_BIAS_TRIM_MASK) + #define ETHERNET_PLL_CTRL0_PLL_REG_EN_MASK (0x400000U) #define ETHERNET_PLL_CTRL0_PLL_REG_EN_SHIFT (22U) /*! PLL_REG_EN - PLL_REG_EN */ #define ETHERNET_PLL_CTRL0_PLL_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_PLL_REG_EN_SHIFT)) & ETHERNET_PLL_CTRL0_PLL_REG_EN_MASK) -#define ETHERNET_PLL_CTRL0_REGULATOR_VOLT_TRIM_MASK (0x1800000U) -#define ETHERNET_PLL_CTRL0_REGULATOR_VOLT_TRIM_SHIFT (23U) -/*! REGULATOR_VOLT_TRIM - Regulator trim - */ -#define ETHERNET_PLL_CTRL0_REGULATOR_VOLT_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_REGULATOR_VOLT_TRIM_SHIFT)) & ETHERNET_PLL_CTRL0_REGULATOR_VOLT_TRIM_MASK) + #define ETHERNET_PLL_CTRL0_POST_DIV_SEL_MASK (0xE000000U) #define ETHERNET_PLL_CTRL0_POST_DIV_SEL_SHIFT (25U) /*! POST_DIV_SEL - Post Divide Select + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 */ #define ETHERNET_PLL_CTRL0_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & ETHERNET_PLL_CTRL0_POST_DIV_SEL_MASK) -#define ETHERNET_PLL_CTRL0_TEST_MODE_MASK (0x40000000U) -#define ETHERNET_PLL_CTRL0_TEST_MODE_SHIFT (30U) -/*! TEST_MODE - TEST_MODE - */ -#define ETHERNET_PLL_CTRL0_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_TEST_MODE_SHIFT)) & ETHERNET_PLL_CTRL0_TEST_MODE_MASK) -#define ETHERNET_PLL_CTRL0_TEST_MUX_ENABLE_MASK (0x80000000U) -#define ETHERNET_PLL_CTRL0_TEST_MUX_ENABLE_SHIFT (31U) -/*! TEST_MUX_ENABLE - TEST_MUX_ENABLE + +#define ETHERNET_PLL_CTRL0_BIAS_SELECT_MASK (0x20000000U) +#define ETHERNET_PLL_CTRL0_BIAS_SELECT_SHIFT (29U) +/*! BIAS_SELECT - BIAS_SELECT + * 0b0..Used in SoCs with a bias current of 10uA + * 0b1..Used in SoCs with a bias current of 2uA */ -#define ETHERNET_PLL_CTRL0_TEST_MUX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_TEST_MUX_ENABLE_SHIFT)) & ETHERNET_PLL_CTRL0_TEST_MUX_ENABLE_MASK) +#define ETHERNET_PLL_CTRL0_BIAS_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_BIAS_SELECT_SHIFT)) & ETHERNET_PLL_CTRL0_BIAS_SELECT_MASK) /*! @} */ /*! @name SPREAD_SPECTRUM - Fractional PLL Spread Spectrum Control Register */ /*! @{ */ + #define ETHERNET_PLL_SPREAD_SPECTRUM_STEP_MASK (0x7FFFU) #define ETHERNET_PLL_SPREAD_SPECTRUM_STEP_SHIFT (0U) /*! STEP - Step */ #define ETHERNET_PLL_SPREAD_SPECTRUM_STEP(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_SPREAD_SPECTRUM_STEP_SHIFT)) & ETHERNET_PLL_SPREAD_SPECTRUM_STEP_MASK) + #define ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE_MASK (0x8000U) #define ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT (15U) /*! ENABLE - Enable */ #define ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT)) & ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE_MASK) + #define ETHERNET_PLL_SPREAD_SPECTRUM_STOP_MASK (0xFFFF0000U) #define ETHERNET_PLL_SPREAD_SPECTRUM_STOP_SHIFT (16U) /*! STOP - Stop @@ -39980,6 +48251,7 @@ typedef struct { /*! @name NUMERATOR - Fractional PLL Numerator Control Register */ /*! @{ */ + #define ETHERNET_PLL_NUMERATOR_NUM_MASK (0x3FFFFFFFU) #define ETHERNET_PLL_NUMERATOR_NUM_SHIFT (0U) /*! NUM - Numerator @@ -39989,6 +48261,7 @@ typedef struct { /*! @name DENOMINATOR - Fractional PLL Denominator Control Register */ /*! @{ */ + #define ETHERNET_PLL_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU) #define ETHERNET_PLL_DENOMINATOR_DENOM_SHIFT (0U) /*! DENOM - Denominator @@ -39996,33 +48269,6 @@ typedef struct { #define ETHERNET_PLL_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_DENOMINATOR_DENOM_SHIFT)) & ETHERNET_PLL_DENOMINATOR_DENOM_MASK) /*! @} */ -/*! @name STAT0 - Analog Status Register STAT0 */ -/*! @{ */ -#define ETHERNET_PLL_STAT0_REG_MASK (0xFFFFFFFFU) -#define ETHERNET_PLL_STAT0_REG_SHIFT (0U) -/*! REG - STAT0 Register - */ -#define ETHERNET_PLL_STAT0_REG(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_STAT0_REG_SHIFT)) & ETHERNET_PLL_STAT0_REG_MASK) -/*! @} */ - -/*! @name STAT1 - Analog Status Register STAT1 */ -/*! @{ */ -#define ETHERNET_PLL_STAT1_REG_MASK (0xFFFFFFFFU) -#define ETHERNET_PLL_STAT1_REG_SHIFT (0U) -/*! REG - STAT1 Register - */ -#define ETHERNET_PLL_STAT1_REG(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_STAT1_REG_SHIFT)) & ETHERNET_PLL_STAT1_REG_MASK) -/*! @} */ - -/*! @name STAT2 - Analog Status Register STAT2 */ -/*! @{ */ -#define ETHERNET_PLL_STAT2_REG_MASK (0xFFFFFFFFU) -#define ETHERNET_PLL_STAT2_REG_SHIFT (0U) -/*! REG - STAT2 Register - */ -#define ETHERNET_PLL_STAT2_REG(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_STAT2_REG_SHIFT)) & ETHERNET_PLL_STAT2_REG_MASK) -/*! @} */ - /*! * @} @@ -40074,30 +48320,43 @@ typedef struct { /*! @name CTRL - Control Register */ /*! @{ */ + #define EWM_CTRL_EWMEN_MASK (0x1U) #define EWM_CTRL_EWMEN_SHIFT (0U) /*! EWMEN - EWM enable. + * 0b0..EWM module is disabled. + * 0b1..EWM module is enabled. */ #define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) + #define EWM_CTRL_ASSIN_MASK (0x2U) #define EWM_CTRL_ASSIN_SHIFT (1U) /*! ASSIN - EWM_in's Assertion State Select. + * 0b0..Default assert state of the EWM_in signal. + * 0b1..Inverts the assert state of EWM_in signal. */ #define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK) + #define EWM_CTRL_INEN_MASK (0x4U) #define EWM_CTRL_INEN_SHIFT (2U) /*! INEN - Input Enable. + * 0b0..EWM_in port is disabled. + * 0b1..EWM_in port is enabled. */ #define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK) + #define EWM_CTRL_INTEN_MASK (0x8U) #define EWM_CTRL_INTEN_SHIFT (3U) /*! INTEN - Interrupt Enable. + * 0b1..Generates an interrupt request, when EWM_OUT_b is asserted. + * 0b0..Deasserts the interrupt request. */ #define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) /*! @} */ /*! @name SERV - Service Register */ /*! @{ */ + #define EWM_SERV_SERVICE_MASK (0xFFU) #define EWM_SERV_SERVICE_SHIFT (0U) /*! SERVICE - SERVICE @@ -40107,6 +48366,7 @@ typedef struct { /*! @name CMPL - Compare Low Register */ /*! @{ */ + #define EWM_CMPL_COMPAREL_MASK (0xFFU) #define EWM_CMPL_COMPAREL_SHIFT (0U) /*! COMPAREL - COMPAREL @@ -40116,6 +48376,7 @@ typedef struct { /*! @name CMPH - Compare High Register */ /*! @{ */ + #define EWM_CMPH_COMPAREH_MASK (0xFFU) #define EWM_CMPH_COMPAREH_SHIFT (0U) /*! COMPAREH - COMPAREH @@ -40125,6 +48386,7 @@ typedef struct { /*! @name CLKCTRL - Clock Control Register */ /*! @{ */ + #define EWM_CLKCTRL_CLKSEL_MASK (0x3U) #define EWM_CLKCTRL_CLKSEL_SHIFT (0U) /*! CLKSEL - CLKSEL @@ -40134,6 +48396,7 @@ typedef struct { /*! @name CLKPRESCALER - Clock Prescaler Register */ /*! @{ */ + #define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU) #define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U) /*! CLK_DIV - CLK_DIV @@ -40233,6 +48496,7 @@ typedef struct { /*! @name VERID - Version ID Register */ /*! @{ */ + #define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) #define FLEXIO_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number @@ -40242,11 +48506,13 @@ typedef struct { * 0b0000000000000011..Supports state, logic and parallel modes; plus pin control registers. */ #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) + #define FLEXIO_VERID_MINOR_MASK (0xFF0000U) #define FLEXIO_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK) + #define FLEXIO_VERID_MAJOR_MASK (0xFF000000U) #define FLEXIO_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number @@ -40256,21 +48522,25 @@ typedef struct { /*! @name PARAM - Parameter Register */ /*! @{ */ + #define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) #define FLEXIO_PARAM_SHIFTER_SHIFT (0U) /*! SHIFTER - Shifter Number */ #define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) + #define FLEXIO_PARAM_TIMER_MASK (0xFF00U) #define FLEXIO_PARAM_TIMER_SHIFT (8U) /*! TIMER - Timer Number */ #define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK) + #define FLEXIO_PARAM_PIN_MASK (0xFF0000U) #define FLEXIO_PARAM_PIN_SHIFT (16U) /*! PIN - Pin Number */ #define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK) + #define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) #define FLEXIO_PARAM_TRIGGER_SHIFT (24U) /*! TRIGGER - Trigger Number @@ -40280,6 +48550,7 @@ typedef struct { /*! @name CTRL - FlexIO Control Register */ /*! @{ */ + #define FLEXIO_CTRL_FLEXEN_MASK (0x1U) #define FLEXIO_CTRL_FLEXEN_SHIFT (0U) /*! FLEXEN - FlexIO Enable @@ -40287,6 +48558,7 @@ typedef struct { * 0b1..FlexIO module is enabled. */ #define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) + #define FLEXIO_CTRL_SWRST_MASK (0x2U) #define FLEXIO_CTRL_SWRST_SHIFT (1U) /*! SWRST - Software Reset @@ -40294,6 +48566,7 @@ typedef struct { * 0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset. */ #define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) + #define FLEXIO_CTRL_FASTACC_MASK (0x4U) #define FLEXIO_CTRL_FASTACC_SHIFT (2U) /*! FASTACC - Fast Access @@ -40301,6 +48574,7 @@ typedef struct { * 0b1..Configures for fast register accesses to FlexIO */ #define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) + #define FLEXIO_CTRL_DBGE_MASK (0x40000000U) #define FLEXIO_CTRL_DBGE_SHIFT (30U) /*! DBGE - Debug Enable @@ -40308,6 +48582,7 @@ typedef struct { * 0b1..FlexIO is enabled in debug modes */ #define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) + #define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) #define FLEXIO_CTRL_DOZEN_SHIFT (31U) /*! DOZEN - Doze Enable @@ -40319,6 +48594,7 @@ typedef struct { /*! @name PIN - Pin State Register */ /*! @{ */ + #define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) #define FLEXIO_PIN_PDI_SHIFT (0U) /*! PDI - Pin Data Input @@ -40328,6 +48604,7 @@ typedef struct { /*! @name SHIFTSTAT - Shifter Status Register */ /*! @{ */ + #define FLEXIO_SHIFTSTAT_SSF_MASK (0xFFU) #define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) /*! SSF - Shifter Status Flag @@ -40337,6 +48614,7 @@ typedef struct { /*! @name SHIFTERR - Shifter Error Register */ /*! @{ */ + #define FLEXIO_SHIFTERR_SEF_MASK (0xFFU) #define FLEXIO_SHIFTERR_SEF_SHIFT (0U) /*! SEF - Shifter Error Flags @@ -40346,6 +48624,7 @@ typedef struct { /*! @name TIMSTAT - Timer Status Register */ /*! @{ */ + #define FLEXIO_TIMSTAT_TSF_MASK (0xFFU) #define FLEXIO_TIMSTAT_TSF_SHIFT (0U) /*! TSF - Timer Status Flags @@ -40355,6 +48634,7 @@ typedef struct { /*! @name SHIFTSIEN - Shifter Status Interrupt Enable */ /*! @{ */ + #define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFFU) #define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) /*! SSIE - Shifter Status Interrupt Enable @@ -40364,6 +48644,7 @@ typedef struct { /*! @name SHIFTEIEN - Shifter Error Interrupt Enable */ /*! @{ */ + #define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFFU) #define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) /*! SEIE - Shifter Error Interrupt Enable @@ -40373,6 +48654,7 @@ typedef struct { /*! @name TIMIEN - Timer Interrupt Enable Register */ /*! @{ */ + #define FLEXIO_TIMIEN_TEIE_MASK (0xFFU) #define FLEXIO_TIMIEN_TEIE_SHIFT (0U) /*! TEIE - Timer Status Interrupt Enable @@ -40382,6 +48664,7 @@ typedef struct { /*! @name SHIFTSDEN - Shifter Status DMA Enable */ /*! @{ */ + #define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFFU) #define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) /*! SSDE - Shifter Status DMA Enable @@ -40391,6 +48674,7 @@ typedef struct { /*! @name TIMERSDEN - Timer Status DMA Enable */ /*! @{ */ + #define FLEXIO_TIMERSDEN_TSDE_MASK (0xFFU) #define FLEXIO_TIMERSDEN_TSDE_SHIFT (0U) /*! TSDE - Timer Status DMA Enable @@ -40400,6 +48684,7 @@ typedef struct { /*! @name SHIFTSTATE - Shifter State Register */ /*! @{ */ + #define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) #define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U) /*! STATE - Current State Pointer @@ -40409,6 +48694,7 @@ typedef struct { /*! @name SHIFTCTL - Shifter Control N Register */ /*! @{ */ + #define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) #define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) /*! SMOD - Shifter Mode @@ -40422,6 +48708,7 @@ typedef struct { * 0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table. */ #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) + #define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) #define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) /*! PINPOL - Shifter Pin Polarity @@ -40429,11 +48716,13 @@ typedef struct { * 0b1..Pin is active low */ #define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) + #define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) #define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) /*! PINSEL - Shifter Pin Select */ #define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) + #define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) #define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) /*! PINCFG - Shifter Pin Configuration @@ -40443,6 +48732,7 @@ typedef struct { * 0b11..Shifter pin output */ #define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK) + #define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) /*! TIMPOL - Timer Polarity @@ -40450,6 +48740,7 @@ typedef struct { * 0b1..Shift on negedge of Shift clock */ #define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) + #define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x7000000U) #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) /*! TIMSEL - Timer Select @@ -40462,6 +48753,7 @@ typedef struct { /*! @name SHIFTCFG - Shifter Configuration N Register */ /*! @{ */ + #define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) #define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) /*! SSTART - Shifter Start bit @@ -40471,6 +48763,7 @@ typedef struct { * 0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1 */ #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) + #define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) #define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) /*! SSTOP - Shifter Stop bit @@ -40480,6 +48773,7 @@ typedef struct { * 0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1 */ #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) + #define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) #define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) /*! INSRC - Input Source @@ -40487,13 +48781,15 @@ typedef struct { * 0b1..Shifter N+1 Output */ #define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) + #define FLEXIO_SHIFTCFG_LATST_MASK (0x200U) #define FLEXIO_SHIFTCFG_LATST_SHIFT (9U) /*! LATST - Late Store - * 0b0..Shift register will store the pre-shift register state. - * 0b1..Shift register will store the post-shift register state. + * 0b0..Shift register stores the pre-shift register state. + * 0b1..Shift register stores the post-shift register state. */ #define FLEXIO_SHIFTCFG_LATST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT)) & FLEXIO_SHIFTCFG_LATST_MASK) + #define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) #define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U) /*! PWIDTH - Parallel Width @@ -40506,6 +48802,7 @@ typedef struct { /*! @name SHIFTBUF - Shifter Buffer N Register */ /*! @{ */ + #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) /*! SHIFTBUF - Shift Buffer @@ -40518,6 +48815,7 @@ typedef struct { /*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */ /*! @{ */ + #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) /*! SHIFTBUFBIS - Shift Buffer @@ -40530,6 +48828,7 @@ typedef struct { /*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */ /*! @{ */ + #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) /*! SHIFTBUFBYS - Shift Buffer @@ -40542,6 +48841,7 @@ typedef struct { /*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */ /*! @{ */ + #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) /*! SHIFTBUFBBS - Shift Buffer @@ -40554,6 +48854,7 @@ typedef struct { /*! @name TIMCTL - Timer Control N Register */ /*! @{ */ + #define FLEXIO_TIMCTL_TIMOD_MASK (0x7U) #define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) /*! TIMOD - Timer Mode @@ -40567,6 +48868,7 @@ typedef struct { * 0b111..Single 16-bit input capture mode. */ #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) + #define FLEXIO_TIMCTL_ONETIM_MASK (0x20U) #define FLEXIO_TIMCTL_ONETIM_SHIFT (5U) /*! ONETIM - Timer One Time Operation @@ -40574,6 +48876,7 @@ typedef struct { * 0b1..The timer enable event is blocked unless timer status flag is clear. */ #define FLEXIO_TIMCTL_ONETIM(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_ONETIM_SHIFT)) & FLEXIO_TIMCTL_ONETIM_MASK) + #define FLEXIO_TIMCTL_PININS_MASK (0x40U) #define FLEXIO_TIMCTL_PININS_SHIFT (6U) /*! PININS - Timer Pin Input Select @@ -40581,6 +48884,7 @@ typedef struct { * 0b1..Timer pin input is selected by PINSEL+1, timer pin output remains selected by PINSEL. */ #define FLEXIO_TIMCTL_PININS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PININS_SHIFT)) & FLEXIO_TIMCTL_PININS_MASK) + #define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) #define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) /*! PINPOL - Timer Pin Polarity @@ -40588,11 +48892,13 @@ typedef struct { * 0b1..Pin is active low */ #define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) + #define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) #define FLEXIO_TIMCTL_PINSEL_SHIFT (8U) /*! PINSEL - Timer Pin Select */ #define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) + #define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) #define FLEXIO_TIMCTL_PINCFG_SHIFT (16U) /*! PINCFG - Timer Pin Configuration @@ -40602,6 +48908,7 @@ typedef struct { * 0b11..Timer pin output */ #define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK) + #define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) #define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) /*! TRGSRC - Trigger Source @@ -40609,6 +48916,7 @@ typedef struct { * 0b1..Internal trigger selected */ #define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) + #define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) #define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) /*! TRGPOL - Trigger Polarity @@ -40616,6 +48924,7 @@ typedef struct { * 0b1..Trigger active low */ #define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) + #define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) #define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) /*! TRGSEL - Trigger Select @@ -40628,6 +48937,7 @@ typedef struct { /*! @name TIMCFG - Timer Configuration N Register */ /*! @{ */ + #define FLEXIO_TIMCFG_TSTART_MASK (0x2U) #define FLEXIO_TIMCFG_TSTART_SHIFT (1U) /*! TSTART - Timer Start Bit @@ -40635,6 +48945,7 @@ typedef struct { * 0b1..Start bit enabled */ #define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) + #define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) #define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) /*! TSTOP - Timer Stop Bit @@ -40644,6 +48955,7 @@ typedef struct { * 0b11..Stop bit is enabled on timer compare and timer disable */ #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) + #define FLEXIO_TIMCFG_TIMENA_MASK (0x700U) #define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) /*! TIMENA - Timer Enable @@ -40657,6 +48969,7 @@ typedef struct { * 0b111..Timer enabled on Trigger rising or falling edge */ #define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) + #define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) #define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) /*! TIMDIS - Timer Disable @@ -40670,6 +48983,7 @@ typedef struct { * 0b111..Reserved */ #define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK) + #define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) #define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) /*! TIMRST - Timer Reset @@ -40683,6 +48997,7 @@ typedef struct { * 0b111..Timer reset on Trigger rising or falling edge */ #define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK) + #define FLEXIO_TIMCFG_TIMDEC_MASK (0x700000U) #define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) /*! TIMDEC - Timer Decrement @@ -40696,6 +49011,7 @@ typedef struct { * 0b111..Decrement counter on Trigger input (rising edge), Shift clock equals Trigger input. */ #define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) + #define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) #define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) /*! TIMOUT - Timer Output @@ -40712,6 +49028,7 @@ typedef struct { /*! @name TIMCMP - Timer Compare N Register */ /*! @{ */ + #define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) #define FLEXIO_TIMCMP_CMP_SHIFT (0U) /*! CMP - Timer Compare Value @@ -40724,6 +49041,7 @@ typedef struct { /*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */ /*! @{ */ + #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U) /*! SHIFTBUFNBS - Shift Buffer @@ -40736,6 +49054,7 @@ typedef struct { /*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */ /*! @{ */ + #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U) /*! SHIFTBUFHWS - Shift Buffer @@ -40748,6 +49067,7 @@ typedef struct { /*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */ /*! @{ */ + #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U) /*! SHIFTBUFNIS - Shift Buffer @@ -40760,6 +49080,7 @@ typedef struct { /*! @name SHIFTBUFOES - Shifter Buffer N Odd Even Swapped Register */ /*! @{ */ + #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT (0U) /*! SHIFTBUFOES - Shift Buffer @@ -40772,6 +49093,7 @@ typedef struct { /*! @name SHIFTBUFEOS - Shifter Buffer N Even Odd Swapped Register */ /*! @{ */ + #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK (0xFFFFFFFFU) #define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT (0U) /*! SHIFTBUFEOS - Shift Buffer @@ -40827,7 +49149,7 @@ typedef struct { __IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x10 */ __IO uint32_t INT_STAT_EN; /**< Interrupt Status Enable Register, offset: 0x14 */ __IO uint32_t INT_SIG_EN; /**< Interrupt Enable Register, offset: 0x18 */ - __I uint32_t OCRAM_ECC_SINGLE_ERROR_INFO; /**< OCRAM single bit ECC Error Information Register, offset: 0x1C */ + __I uint32_t OCRAM_ECC_SINGLE_ERROR_INFO; /**< OCRAM single-bit ECC Error Information Register, offset: 0x1C */ __I uint32_t OCRAM_ECC_SINGLE_ERROR_ADDR; /**< OCRAM single-bit ECC Error Address Register, offset: 0x20 */ __I uint32_t OCRAM_ECC_SINGLE_ERROR_DATA_LSB; /**< OCRAM single-bit ECC Error Data Register, offset: 0x24 */ __I uint32_t OCRAM_ECC_SINGLE_ERROR_DATA_MSB; /**< OCRAM single-bit ECC Error Data Register, offset: 0x28 */ @@ -40856,8 +49178,8 @@ typedef struct { __I uint32_t D1TCM_ECC_MULTI_ERROR_ADDR; /**< D1TCM multi-bit ECC Error Address Register, offset: 0x84 */ __I uint32_t D1TCM_ECC_MULTI_ERROR_DATA; /**< D1TCM multi-bit ECC Error Data Register, offset: 0x88 */ uint8_t RESERVED_0[124]; - __IO uint32_t FLEXRAM_CTRL; /**< Flexram feature ECC and ocram wait pipeline can be configured through this register, offset: 0x108 */ - __I uint32_t OCRAM_PIPELINE_STATUS; /**< Update pending signal for ocram wait and pipeline enable, offset: 0x10C */ + __IO uint32_t FLEXRAM_CTRL; /**< FlexRAM feature Control register, offset: 0x108 */ + __I uint32_t OCRAM_PIPELINE_STATUS; /**< OCRAM Pipeline Status register, offset: 0x10C */ } FLEXRAM_Type; /* ---------------------------------------------------------------------------- @@ -40871,6 +49193,7 @@ typedef struct { /*! @name TCM_CTRL - TCM CRTL Register */ /*! @{ */ + #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK (0x1U) #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT (0U) /*! TCM_WWAIT_EN - TCM Write Wait Mode Enable @@ -40878,6 +49201,7 @@ typedef struct { * 0b1..TCM write wait mode: Write RAM accesses are expected to be finished in 2-cycles. */ #define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK) + #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK (0x2U) #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT (1U) /*! TCM_RWAIT_EN - TCM Read Wait Mode Enable @@ -40885,11 +49209,13 @@ typedef struct { * 0b1..TCM read wait mode: Read RAM accesses are expected to be finished in 2-cycles. */ #define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK) + #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U) #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U) /*! FORCE_CLK_ON - Force RAM Clock Always On */ #define FLEXRAM_TCM_CTRL_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK) + #define FLEXRAM_TCM_CTRL_Reserved_MASK (0xFFFFFFF8U) #define FLEXRAM_TCM_CTRL_Reserved_SHIFT (3U) /*! Reserved - Reserved @@ -40899,6 +49225,7 @@ typedef struct { /*! @name OCRAM_MAGIC_ADDR - OCRAM Magic Address Register */ /*! @{ */ + #define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK (0x1U) #define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT (0U) /*! OCRAM_WR_RD_SEL - OCRAM Write Read Select @@ -40906,11 +49233,13 @@ typedef struct { * 0b1..When OCRAM write access hits magic address, it will generate interrupt. */ #define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK) + #define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK (0x3FFFEU) #define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT (1U) /*! OCRAM_MAGIC_ADDR - OCRAM Magic Address */ #define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK) + #define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK (0xFFFC0000U) #define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT (18U) /*! Reserved - Reserved @@ -40920,6 +49249,7 @@ typedef struct { /*! @name DTCM_MAGIC_ADDR - DTCM Magic Address Register */ /*! @{ */ + #define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK (0x1U) #define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT (0U) /*! DTCM_WR_RD_SEL - DTCM Write Read Select @@ -40927,11 +49257,13 @@ typedef struct { * 0b1..When DTCM write access hits magic address, it will generate interrupt. */ #define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK) + #define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK (0x1FFFEU) #define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT (1U) /*! DTCM_MAGIC_ADDR - DTCM Magic Address */ #define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK) + #define FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U) #define FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT (17U) /*! Reserved - Reserved @@ -40941,6 +49273,7 @@ typedef struct { /*! @name ITCM_MAGIC_ADDR - ITCM Magic Address Register */ /*! @{ */ + #define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK (0x1U) #define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT (0U) /*! ITCM_WR_RD_SEL - ITCM Write Read Select @@ -40948,11 +49281,13 @@ typedef struct { * 0b1..When ITCM write access hits magic address, it will generate interrupt. */ #define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK) + #define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK (0x1FFFEU) #define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT (1U) /*! ITCM_MAGIC_ADDR - ITCM Magic Address */ #define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK) + #define FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U) #define FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT (17U) /*! Reserved - Reserved @@ -40962,6 +49297,7 @@ typedef struct { /*! @name INT_STATUS - Interrupt Status Register */ /*! @{ */ + #define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK (0x1U) #define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT (0U) /*! ITCM_MAM_STATUS - ITCM Magic Address Match Status @@ -40969,6 +49305,7 @@ typedef struct { * 0b1..ITCM accessed magic address. */ #define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK) + #define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK (0x2U) #define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT (1U) /*! DTCM_MAM_STATUS - DTCM Magic Address Match Status @@ -40976,6 +49313,7 @@ typedef struct { * 0b1..DTCM accessed magic address. */ #define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK) + #define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK (0x4U) #define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT (2U) /*! OCRAM_MAM_STATUS - OCRAM Magic Address Match Status @@ -40983,6 +49321,7 @@ typedef struct { * 0b1..OCRAM accessed magic address. */ #define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK) + #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK (0x8U) #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U) /*! ITCM_ERR_STATUS - ITCM Access Error Status @@ -40990,6 +49329,7 @@ typedef struct { * 0b1..ITCM access error happens. */ #define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK) + #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK (0x10U) #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U) /*! DTCM_ERR_STATUS - DTCM Access Error Status @@ -40997,6 +49337,7 @@ typedef struct { * 0b1..DTCM access error happens. */ #define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK) + #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U) #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U) /*! OCRAM_ERR_STATUS - OCRAM Access Error Status @@ -41004,6 +49345,7 @@ typedef struct { * 0b1..OCRAM access error happens. */ #define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK) + #define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_MASK (0x40U) #define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_SHIFT (6U) /*! OCRAM_ECC_ERRM_INT - OCRAM access multi-bit ECC Error Interrupt Status @@ -41011,6 +49353,7 @@ typedef struct { * 0b1..OCRAM multi-bit ECC error happens. */ #define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_MASK) + #define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_MASK (0x80U) #define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_SHIFT (7U) /*! OCRAM_ECC_ERRS_INT - OCRAM access single-bit ECC Error Interrupt Status @@ -41018,6 +49361,7 @@ typedef struct { * 0b1..OCRAM single-bit ECC error happens. */ #define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_MASK) + #define FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_MASK (0x100U) #define FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_SHIFT (8U) /*! ITCM_ECC_ERRM_INT - ITCM Access multi-bit ECC Error Interrupt Status @@ -41025,6 +49369,7 @@ typedef struct { * 0b1..ITCM multi-bit ECC error happens. */ #define FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_MASK) + #define FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_MASK (0x200U) #define FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_SHIFT (9U) /*! ITCM_ECC_ERRS_INT - ITCM access single-bit ECC Error Interrupt Status @@ -41032,6 +49377,7 @@ typedef struct { * 0b1..ITCM single-bit ECC error happens. */ #define FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_MASK) + #define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_MASK (0x400U) #define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_SHIFT (10U) /*! D0TCM_ECC_ERRM_INT - D0TCM access multi-bit ECC Error Interrupt Status @@ -41039,6 +49385,7 @@ typedef struct { * 0b1..D0TCM multi-bit ECC error happens. */ #define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_SHIFT)) & FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_MASK) + #define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_MASK (0x800U) #define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_SHIFT (11U) /*! D0TCM_ECC_ERRS_INT - D0TCM access single-bit ECC Error Interrupt Status @@ -41046,6 +49393,7 @@ typedef struct { * 0b1..D0TCM single-bit ECC error happens. */ #define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_SHIFT)) & FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_MASK) + #define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_MASK (0x1000U) #define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_SHIFT (12U) /*! D1TCM_ECC_ERRM_INT - D1TCM access multi-bit ECC Error Interrupt Status @@ -41053,6 +49401,7 @@ typedef struct { * 0b1..D1TCM multi-bit ECC error happens. */ #define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_SHIFT)) & FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_MASK) + #define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_MASK (0x2000U) #define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_SHIFT (13U) /*! D1TCM_ECC_ERRS_INT - D1TCM access single-bit ECC Error Interrupt Status @@ -41060,6 +49409,7 @@ typedef struct { * 0b1..D1TCM single-bit ECC error happens. */ #define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_SHIFT)) & FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_MASK) + #define FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S_MASK (0x4000U) #define FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S_SHIFT (14U) /*! ITCM_PARTIAL_WR_INT_S - ITCM Partial Write Interrupt Status @@ -41067,6 +49417,7 @@ typedef struct { * 0b1..ITCM Partial Write happens. */ #define FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S_MASK) + #define FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S_MASK (0x8000U) #define FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S_SHIFT (15U) /*! D0TCM_PARTIAL_WR_INT_S - D0TCM Partial Write Interrupt Status @@ -41074,6 +49425,7 @@ typedef struct { * 0b1..D0TCM Partial Write happens. */ #define FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S_SHIFT)) & FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S_MASK) + #define FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S_MASK (0x10000U) #define FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S_SHIFT (16U) /*! D1TCM_PARTIAL_WR_INT_S - D1TCM Partial Write Interrupt Status @@ -41081,6 +49433,7 @@ typedef struct { * 0b1..D1TCM Partial Write happens. */ #define FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S_SHIFT)) & FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S_MASK) + #define FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S_MASK (0x20000U) #define FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S_SHIFT (17U) /*! OCRAM_PARTIAL_WR_INT_S - OCRAM Partial Write Interrupt Status @@ -41088,6 +49441,7 @@ typedef struct { * 0b1..OCRAM Partial Write happens. */ #define FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S_MASK) + #define FLEXRAM_INT_STATUS_Reserved_MASK (0xFFFC0000U) #define FLEXRAM_INT_STATUS_Reserved_SHIFT (18U) /*! Reserved - Reserved @@ -41097,6 +49451,7 @@ typedef struct { /*! @name INT_STAT_EN - Interrupt Status Enable Register */ /*! @{ */ + #define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK (0x1U) #define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT (0U) /*! ITCM_MAM_STAT_EN - ITCM Magic Address Match Status Enable @@ -41104,6 +49459,7 @@ typedef struct { * 0b1..Enabled */ #define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK) + #define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK (0x2U) #define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT (1U) /*! DTCM_MAM_STAT_EN - DTCM Magic Address Match Status Enable @@ -41111,6 +49467,7 @@ typedef struct { * 0b1..Enabled */ #define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK) + #define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK (0x4U) #define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT (2U) /*! OCRAM_MAM_STAT_EN - OCRAM Magic Address Match Status Enable @@ -41118,6 +49475,7 @@ typedef struct { * 0b1..Enabled */ #define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK) + #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U) #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U) /*! ITCM_ERR_STAT_EN - ITCM Access Error Status Enable @@ -41125,6 +49483,7 @@ typedef struct { * 0b1..Enabled */ #define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK) + #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U) #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U) /*! DTCM_ERR_STAT_EN - DTCM Access Error Status Enable @@ -41132,6 +49491,7 @@ typedef struct { * 0b1..Enabled */ #define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK) + #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U) #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U) /*! OCRAM_ERR_STAT_EN - OCRAM Access Error Status Enable @@ -41139,62 +49499,71 @@ typedef struct { * 0b1..Enabled */ #define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK) + #define FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN_MASK (0x40U) #define FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN_SHIFT (6U) -/*! OCRAM_ERRM_INT_EN - OCRAM Access multi bit ECC Error Interrupt Status Enable +/*! OCRAM_ERRM_INT_EN - OCRAM Access multi-bit ECC Error Interrupt Status Enable * 0b0..Masked * 0b1..Enabled */ #define FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN_MASK) + #define FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN_MASK (0x80U) #define FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN_SHIFT (7U) -/*! OCRAM_ERRS_INT_EN - OCRAM Access single bit ECC Error Interrupt Status Enable +/*! OCRAM_ERRS_INT_EN - OCRAM Access single-bit ECC Error Interrupt Status Enable * 0b0..Masked * 0b1..Enabled */ #define FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN_MASK) + #define FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN_MASK (0x100U) #define FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN_SHIFT (8U) -/*! ITCM_ERRM_INT_EN - ITCM Access multi bit ECC Error Interrupt Status Enable +/*! ITCM_ERRM_INT_EN - ITCM Access multi-bit ECC Error Interrupt Status Enable * 0b0..Masked * 0b1..Enabled */ #define FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN_MASK) + #define FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN_MASK (0x200U) #define FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN_SHIFT (9U) -/*! ITCM_ERRS_INT_EN - ITCM Access single bit ECC Error Interrupt Status Enable +/*! ITCM_ERRS_INT_EN - ITCM Access single-bit ECC Error Interrupt Status Enable * 0b0..Masked * 0b1..Enabled */ #define FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN_MASK) + #define FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN_MASK (0x400U) #define FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN_SHIFT (10U) -/*! D0TCM_ERRM_INT_EN - D0TCM Access multi bit ECC Error Interrupt Status Enable +/*! D0TCM_ERRM_INT_EN - D0TCM Access multi-bit ECC Error Interrupt Status Enable * 0b0..Masked * 0b1..Enabled */ #define FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN_MASK) + #define FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN_MASK (0x800U) #define FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN_SHIFT (11U) -/*! D0TCM_ERRS_INT_EN - D0TCM Access single bit ECC Error Interrupt Status Enable +/*! D0TCM_ERRS_INT_EN - D0TCM Access single-bit ECC Error Interrupt Status Enable * 0b0..Masked * 0b1..Enabled */ #define FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN_MASK) + #define FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN_MASK (0x1000U) #define FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN_SHIFT (12U) -/*! D1TCM_ERRM_INT_EN - D1TCM Access multi bit ECC Error Interrupt Status Enable +/*! D1TCM_ERRM_INT_EN - D1TCM Access multi-bit ECC Error Interrupt Status Enable * 0b0..Masked * 0b1..Enabled */ #define FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN_MASK) + #define FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN_MASK (0x2000U) #define FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN_SHIFT (13U) -/*! D1TCM_ERRS_INT_EN - D1TCM Access single bit ECC Error Interrupt Status Enable +/*! D1TCM_ERRS_INT_EN - D1TCM Access single-bit ECC Error Interrupt Status Enable * 0b0..Masked * 0b1..Enabled */ #define FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN_MASK) + #define FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN_MASK (0x4000U) #define FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN_SHIFT (14U) /*! ITCM_PARTIAL_WR_INT_S_EN - ITCM Partial Write Interrupt Status Enable @@ -41202,6 +49571,7 @@ typedef struct { * 0b1..Enabled */ #define FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN_MASK) + #define FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN_MASK (0x8000U) #define FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN_SHIFT (15U) /*! D0TCM_PARTIAL_WR_INT_S_EN - D0TCM Partial Write Interrupt Status Enable @@ -41209,6 +49579,7 @@ typedef struct { * 0b1..Enabled */ #define FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN_MASK) + #define FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN_MASK (0x10000U) #define FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN_SHIFT (16U) /*! D1TCM_PARTIAL_WR_INT_S_EN - D1TCM Partial Write Interrupt Status EN @@ -41216,6 +49587,7 @@ typedef struct { * 0b1..Enbaled */ #define FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN_MASK) + #define FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN_MASK (0x20000U) #define FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN_SHIFT (17U) /*! OCRAM_PARTIAL_WR_INT_S_EN - OCRAM Partial Write Interrupt Status @@ -41223,6 +49595,7 @@ typedef struct { * 0b1..Enabled */ #define FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN_MASK) + #define FLEXRAM_INT_STAT_EN_Reserved_MASK (0xFFFC0000U) #define FLEXRAM_INT_STAT_EN_Reserved_SHIFT (18U) /*! Reserved - Reserved @@ -41232,6 +49605,7 @@ typedef struct { /*! @name INT_SIG_EN - Interrupt Enable Register */ /*! @{ */ + #define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK (0x1U) #define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT (0U) /*! ITCM_MAM_SIG_EN - ITCM Magic Address Match Interrupt Enable @@ -41239,6 +49613,7 @@ typedef struct { * 0b1..Enabled */ #define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK) + #define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK (0x2U) #define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT (1U) /*! DTCM_MAM_SIG_EN - DTCM Magic Address Match Interrupt Enable @@ -41246,6 +49621,7 @@ typedef struct { * 0b1..Enabled */ #define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK) + #define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK (0x4U) #define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT (2U) /*! OCRAM_MAM_SIG_EN - OCRAM Magic Address Match Interrupt Enable @@ -41253,6 +49629,7 @@ typedef struct { * 0b1..Enabled */ #define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK) + #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U) #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U) /*! ITCM_ERR_SIG_EN - ITCM Access Error Interrupt Enable @@ -41260,6 +49637,7 @@ typedef struct { * 0b1..Enabled */ #define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK) + #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK (0x10U) #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U) /*! DTCM_ERR_SIG_EN - DTCM Access Error Interrupt Enable @@ -41267,6 +49645,7 @@ typedef struct { * 0b1..Enabled */ #define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK) + #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U) #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U) /*! OCRAM_ERR_SIG_EN - OCRAM Access Error Interrupt Enable @@ -41274,62 +49653,71 @@ typedef struct { * 0b1..Enabled */ #define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK) + #define FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN_MASK (0x40U) #define FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN_SHIFT (6U) -/*! OCRAM_ERRM_INT_SIG_EN - OCRAM Access multi bit ECC Error Interrupt Signal Enable +/*! OCRAM_ERRM_INT_SIG_EN - OCRAM Access multi-bit ECC Error Interrupt Signal Enable * 0b0..Masked * 0b1..Enabled */ #define FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN_MASK) + #define FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN_MASK (0x80U) #define FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN_SHIFT (7U) -/*! OCRAM_ERRS_INT_SIG_EN - OCRAM Access single bit ECC Error Interrupt Signal Enable +/*! OCRAM_ERRS_INT_SIG_EN - OCRAM Access single-bit ECC Error Interrupt Signal Enable * 0b0..Masked * 0b1..Enabled */ #define FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN_MASK) + #define FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN_MASK (0x100U) #define FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN_SHIFT (8U) -/*! ITCM_ERRM_INT_SIG_EN - ITCM Access multi bit ECC Error Interrupt Signal Enable +/*! ITCM_ERRM_INT_SIG_EN - ITCM Access multi-bit ECC Error Interrupt Signal Enable * 0b0..Masked * 0b1..Enabled */ #define FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN_MASK) + #define FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN_MASK (0x200U) #define FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN_SHIFT (9U) -/*! ITCM_ERRS_INT_SIG_EN - ITCM Access single bit ECC Error Interrupt Signal Enable +/*! ITCM_ERRS_INT_SIG_EN - ITCM Access single-bit ECC Error Interrupt Signal Enable * 0b0..Masked * 0b1..Enabled */ #define FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN_MASK) + #define FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN_MASK (0x400U) #define FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN_SHIFT (10U) -/*! D0TCM_ERRM_INT_SIG_EN - D0TCM Access multi bit ECC Error Interrupt Signal Enable +/*! D0TCM_ERRM_INT_SIG_EN - D0TCM Access multi-bit ECC Error Interrupt Signal Enable * 0b0..Masked * 0b1..Enabled */ #define FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN_MASK) + #define FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN_MASK (0x800U) #define FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN_SHIFT (11U) -/*! D0TCM_ERRS_INT_SIG_EN - D0TCM Access single bit ECC Error Interrupt Signal Enable +/*! D0TCM_ERRS_INT_SIG_EN - D0TCM Access single-bit ECC Error Interrupt Signal Enable * 0b0..Masked * 0b1..Enabled */ #define FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN_MASK) + #define FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN_MASK (0x1000U) #define FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN_SHIFT (12U) -/*! D1TCM_ERRM_INT_SIG_EN - D1TCM Access multi bit ECC Error Interrupt Signal Enable +/*! D1TCM_ERRM_INT_SIG_EN - D1TCM Access multi-bit ECC Error Interrupt Signal Enable * 0b0..Masked * 0b1..Enabled */ #define FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN_MASK) + #define FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN_MASK (0x2000U) #define FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN_SHIFT (13U) -/*! D1TCM_ERRS_INT_SIG_EN - D1TCM Access single bit ECC Error Interrupt Signal Enable +/*! D1TCM_ERRS_INT_SIG_EN - D1TCM Access single-bit ECC Error Interrupt Signal Enable * 0b0..Masked * 0b1..Enabled */ #define FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN_MASK) + #define FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN_MASK (0x4000U) #define FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN_SHIFT (14U) /*! ITCM_PARTIAL_WR_INT_SIG_EN - ITCM Partial Write Interrupt Signal Enable Enable @@ -41337,6 +49725,7 @@ typedef struct { * 0b1..Enabled */ #define FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN_MASK) + #define FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN_MASK (0x8000U) #define FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN_SHIFT (15U) /*! D0TCM_PARTIAL_WR_INT_SIG_EN - D0TCM Partial Write Interrupt Signal Enable Enable @@ -41344,6 +49733,7 @@ typedef struct { * 0b1..Enabled */ #define FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN_MASK) + #define FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN_MASK (0x10000U) #define FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN_SHIFT (16U) /*! D1TCM_PARTIAL_WR_INT_SIG_EN - D1TCM Partial Write Interrupt Signal Enable EN @@ -41351,6 +49741,7 @@ typedef struct { * 0b1..Enbaled */ #define FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN_MASK) + #define FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN_MASK (0x20000U) #define FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN_SHIFT (17U) /*! OCRAM_PARTIAL_WR_INT_SIG_EN - OCRAM Partial Write Interrupt Signal Enable @@ -41358,6 +49749,7 @@ typedef struct { * 0b1..Enabled */ #define FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN_MASK) + #define FLEXRAM_INT_SIG_EN_Reserved_MASK (0xFFFC0000U) #define FLEXRAM_INT_SIG_EN_Reserved_SHIFT (18U) /*! Reserved - Reserved @@ -41365,18 +49757,21 @@ typedef struct { #define FLEXRAM_INT_SIG_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_Reserved_SHIFT)) & FLEXRAM_INT_SIG_EN_Reserved_MASK) /*! @} */ -/*! @name OCRAM_ECC_SINGLE_ERROR_INFO - OCRAM single bit ECC Error Information Register */ +/*! @name OCRAM_ECC_SINGLE_ERROR_INFO - OCRAM single-bit ECC Error Information Register */ /*! @{ */ + #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_MASK (0xFFU) #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_SHIFT (0U) /*! OCRAM_ECCS_ERRED_ECC - corresponding ECC cipher of OCRAM single-bit ECC error */ #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_MASK) + #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_MASK (0xFF00U) #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_SHIFT (8U) /*! OCRAM_ECCS_ERRED_SYN - corresponding ECC syndrome of OCRAM single-bit ECC error */ #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_MASK) + #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFFF0000U) #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (16U) /*! Reserved - Reserved @@ -41386,6 +49781,7 @@ typedef struct { /*! @name OCRAM_ECC_SINGLE_ERROR_ADDR - OCRAM single-bit ECC Error Address Register */ /*! @{ */ + #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU) #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR_SHIFT (0U) /*! OCRAM_ECCS_ERRED_ADDR - OCRAM single-bit ECC error address @@ -41395,6 +49791,7 @@ typedef struct { /*! @name OCRAM_ECC_SINGLE_ERROR_DATA_LSB - OCRAM single-bit ECC Error Data Register */ /*! @{ */ + #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB_MASK (0xFFFFFFFFU) #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB_SHIFT (0U) /*! OCRAM_ECCS_ERRED_DATA_LSB - OCRAM single-bit ECC error data [31:0] @@ -41404,6 +49801,7 @@ typedef struct { /*! @name OCRAM_ECC_SINGLE_ERROR_DATA_MSB - OCRAM single-bit ECC Error Data Register */ /*! @{ */ + #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB_MASK (0xFFFFFFFFU) #define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB_SHIFT (0U) /*! OCRAM_ECCS_ERRED_DATA_MSB - OCRAM single-bit ECC error data [63:32] @@ -41413,11 +49811,13 @@ typedef struct { /*! @name OCRAM_ECC_MULTI_ERROR_INFO - OCRAM multi-bit ECC Error Information Register */ /*! @{ */ + #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_MASK (0xFFU) #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_SHIFT (0U) /*! OCRAM_ECCM_ERRED_ECC - OCRAM multi-bit ECC error corresponding ECC value */ #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_MASK) + #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFFFFF00U) #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (8U) /*! Reserved - Reserved @@ -41427,6 +49827,7 @@ typedef struct { /*! @name OCRAM_ECC_MULTI_ERROR_ADDR - OCRAM multi-bit ECC Error Address Register */ /*! @{ */ + #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU) #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR_SHIFT (0U) /*! OCRAM_ECCM_ERRED_ADDR - OCRAM multi-bit ECC error address @@ -41436,6 +49837,7 @@ typedef struct { /*! @name OCRAM_ECC_MULTI_ERROR_DATA_LSB - OCRAM multi-bit ECC Error Data Register */ /*! @{ */ + #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB_MASK (0xFFFFFFFFU) #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB_SHIFT (0U) /*! OCRAM_ECCM_ERRED_DATA_LSB - OCRAM multi-bit ECC error data [31:0] @@ -41445,6 +49847,7 @@ typedef struct { /*! @name OCRAM_ECC_MULTI_ERROR_DATA_MSB - OCRAM multi-bit ECC Error Data Register */ /*! @{ */ + #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB_MASK (0xFFFFFFFFU) #define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB_SHIFT (0U) /*! OCRAM_ECCM_ERRED_DATA_MSB - OCRAM multi-bit ECC error data [63:32] @@ -41454,31 +49857,37 @@ typedef struct { /*! @name ITCM_ECC_SINGLE_ERROR_INFO - ITCM single-bit ECC Error Information Register */ /*! @{ */ + #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_MASK (0x1U) #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_SHIFT (0U) -/*! ITCM_ECCS_EFW - ITCM single-bit ECC error corresponding tcm_wr value +/*! ITCM_ECCS_EFW - ITCM single-bit ECC error corresponding TCM_WR value. */ #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_MASK) + #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK (0xEU) #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_SHIFT (1U) -/*! ITCM_ECCS_EFSIZ - ITCM single-bit ECC error corresponding tcm access size +/*! ITCM_ECCS_EFSIZ - ITCM single-bit ECC error corresponding TCM size */ #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK) + #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_MASK (0xF0U) #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_SHIFT (4U) -/*! ITCM_ECCS_EFMST - ITCM single-bit ECC error corresponding tcm_master +/*! ITCM_ECCS_EFMST - ITCM single-bit ECC error corresponding TCM_MASTER. */ #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_MASK) + #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_MASK (0xF00U) #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_SHIFT (8U) -/*! ITCM_ECCS_EFPRT - ITCM single-bit ECC error corresponding tcm_priv +/*! ITCM_ECCS_EFPRT - ITCM single-bit ECC error corresponding TCM_PRIV. */ #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_MASK) + #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_MASK (0xFF000U) #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_SHIFT (12U) /*! ITCM_ECCS_EFSYN - ITCM single-bit ECC error corresponding syndrome */ #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_MASK) + #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFF00000U) #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (20U) /*! Reserved - Reserved @@ -41488,6 +49897,7 @@ typedef struct { /*! @name ITCM_ECC_SINGLE_ERROR_ADDR - ITCM single-bit ECC Error Address Register */ /*! @{ */ + #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU) #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_SHIFT (0U) /*! ITCM_ECCS_ERRED_ADDR - ITCM single-bit ECC error address @@ -41497,6 +49907,7 @@ typedef struct { /*! @name ITCM_ECC_SINGLE_ERROR_DATA_LSB - ITCM single-bit ECC Error Data Register */ /*! @{ */ + #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_MASK (0xFFFFFFFFU) #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_SHIFT (0U) /*! ITCM_ECCS_ERRED_DATA_LSB - ITCM single-bit ECC error data [31:0] @@ -41506,6 +49917,7 @@ typedef struct { /*! @name ITCM_ECC_SINGLE_ERROR_DATA_MSB - ITCM single-bit ECC Error Data Register */ /*! @{ */ + #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_MASK (0xFFFFFFFFU) #define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_SHIFT (0U) /*! ITCM_ECCS_ERRED_DATA_MSB - ITCM single-bit ECC error data [63:32] @@ -41515,31 +49927,37 @@ typedef struct { /*! @name ITCM_ECC_MULTI_ERROR_INFO - ITCM multi-bit ECC Error Information Register */ /*! @{ */ + #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_MASK (0x1U) #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_SHIFT (0U) -/*! ITCM_ECCM_EFW - ITCM multi-bit ECC error corresponding tcm_wr value +/*! ITCM_ECCM_EFW - ITCM multi-bit ECC error corresponding TCM_WR value */ #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_MASK) + #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_MASK (0xEU) #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_SHIFT (1U) /*! ITCM_ECCM_EFSIZ - ITCM multi-bit ECC error corresponding tcm access size */ #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_MASK) + #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_MASK (0xF0U) #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_SHIFT (4U) -/*! ITCM_ECCM_EFMST - ITCM multi-bit ECC error corresponding tcm_master +/*! ITCM_ECCM_EFMST - ITCM multi-bit ECC error corresponding TCM_MASTER */ #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_MASK) + #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_MASK (0xF00U) #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_SHIFT (8U) -/*! ITCM_ECCM_EFPRT - ITCM multi-bit ECC error corresponding tcm_priv +/*! ITCM_ECCM_EFPRT - ITCM multi-bit ECC error corresponding TCM_PRIV */ #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_MASK) + #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN_MASK (0xFF000U) #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN_SHIFT (12U) /*! ITCM_ECCM_EFSYN - ITCM multi-bit ECC error corresponding syndrome */ #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN_MASK) + #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFF00000U) #define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (20U) /*! Reserved - Reserved @@ -41549,6 +49967,7 @@ typedef struct { /*! @name ITCM_ECC_MULTI_ERROR_ADDR - ITCM multi-bit ECC Error Address Register */ /*! @{ */ + #define FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU) #define FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_SHIFT (0U) /*! ITCM_ECCM_ERRED_ADDR - ITCM multi-bit ECC error address @@ -41558,6 +49977,7 @@ typedef struct { /*! @name ITCM_ECC_MULTI_ERROR_DATA_LSB - ITCM multi-bit ECC Error Data Register */ /*! @{ */ + #define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_MASK (0xFFFFFFFFU) #define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_SHIFT (0U) /*! ITCM_ECCM_ERRED_DATA_LSB - ITCM multi-bit ECC error data [31:0] @@ -41567,6 +49987,7 @@ typedef struct { /*! @name ITCM_ECC_MULTI_ERROR_DATA_MSB - ITCM multi-bit ECC Error Data Register */ /*! @{ */ + #define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_MASK (0xFFFFFFFFU) #define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_SHIFT (0U) /*! ITCM_ECCM_ERRED_DATA_MSB - ITCM multi-bit ECC error data [63:32] @@ -41576,31 +49997,37 @@ typedef struct { /*! @name D0TCM_ECC_SINGLE_ERROR_INFO - D0TCM single-bit ECC Error Information Register */ /*! @{ */ + #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_MASK (0x1U) #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_SHIFT (0U) -/*! D0TCM_ECCS_EFW - D0TCM single-bit ECC error corresponding tcm_wr value +/*! D0TCM_ECCS_EFW - D0TCM single-bit ECC error corresponding TCM_WR value */ #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_MASK) + #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_MASK (0xEU) #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_SHIFT (1U) /*! D0TCM_ECCS_EFSIZ - D0TCM single-bit ECC error corresponding tcm access size */ #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_MASK) + #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_MASK (0xF0U) #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_SHIFT (4U) -/*! D0TCM_ECCS_EFMST - D0TCM single-bit ECC error corresponding tcm_master +/*! D0TCM_ECCS_EFMST - D0TCM single-bit ECC error corresponding TCM_MASTER */ #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_MASK) + #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_MASK (0xF00U) #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_SHIFT (8U) -/*! D0TCM_ECCS_EFPRT - D0TCM single-bit ECC error corresponding tcm_priv +/*! D0TCM_ECCS_EFPRT - D0TCM single-bit ECC error corresponding TCM_PRIV */ #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_MASK) + #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_MASK (0x7F000U) #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_SHIFT (12U) /*! D0TCM_ECCS_EFSYN - D0TCM single-bit ECC error corresponding syndrome */ #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_MASK) + #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFF80000U) #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (19U) /*! Reserved - Reserved @@ -41610,6 +50037,7 @@ typedef struct { /*! @name D0TCM_ECC_SINGLE_ERROR_ADDR - D0TCM single-bit ECC Error Address Register */ /*! @{ */ + #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU) #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_SHIFT (0U) /*! D0TCM_ECCS_ERRED_ADDR - D0TCM single-bit ECC error address @@ -41619,6 +50047,7 @@ typedef struct { /*! @name D0TCM_ECC_SINGLE_ERROR_DATA - D0TCM single-bit ECC Error Data Register */ /*! @{ */ + #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_MASK (0xFFFFFFFFU) #define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_SHIFT (0U) /*! D0TCM_ECCS_ERRED_DATA - D0TCM single-bit ECC error data @@ -41628,31 +50057,37 @@ typedef struct { /*! @name D0TCM_ECC_MULTI_ERROR_INFO - D0TCM multi-bit ECC Error Information Register */ /*! @{ */ + #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_MASK (0x1U) #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_SHIFT (0U) -/*! D0TCM_ECCM_EFW - D0TCM multi-bit ECC error corresponding tcm_wr value +/*! D0TCM_ECCM_EFW - D0TCM multi-bit ECC error corresponding TCM_WR value */ #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_MASK) + #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_MASK (0xEU) #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_SHIFT (1U) /*! D0TCM_ECCM_EFSIZ - D0TCM multi-bit ECC error corresponding tcm access size */ #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_MASK) + #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_MASK (0xF0U) #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_SHIFT (4U) -/*! D0TCM_ECCM_EFMST - D0TCM multi-bit ECC error corresponding tcm_master +/*! D0TCM_ECCM_EFMST - D0TCM multi-bit ECC error corresponding TCM_MASTER */ #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_MASK) + #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_MASK (0xF00U) #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_SHIFT (8U) -/*! D0TCM_ECCM_EFPRT - D0TCM multi-bit ECC error corresponding tcm_priv +/*! D0TCM_ECCM_EFPRT - D0TCM multi-bit ECC error corresponding TCM_PRIV */ #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_MASK) + #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN_MASK (0x7F000U) #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN_SHIFT (12U) /*! D0TCM_ECCM_EFSYN - D0TCM multi-bit ECC error corresponding syndrome */ #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN_MASK) + #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFF80000U) #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (19U) /*! Reserved - Reserved @@ -41662,6 +50097,7 @@ typedef struct { /*! @name D0TCM_ECC_MULTI_ERROR_ADDR - D0TCM multi-bit ECC Error Address Register */ /*! @{ */ + #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU) #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_SHIFT (0U) /*! D0TCM_ECCM_ERRED_ADDR - D0TCM multi-bit ECC error address @@ -41671,6 +50107,7 @@ typedef struct { /*! @name D0TCM_ECC_MULTI_ERROR_DATA - D0TCM multi-bit ECC Error Data Register */ /*! @{ */ + #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_MASK (0xFFFFFFFFU) #define FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_SHIFT (0U) /*! D0TCM_ECCM_ERRED_DATA - D0TCM multi-bit ECC error data @@ -41680,31 +50117,37 @@ typedef struct { /*! @name D1TCM_ECC_SINGLE_ERROR_INFO - D1TCM single-bit ECC Error Information Register */ /*! @{ */ + #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_MASK (0x1U) #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_SHIFT (0U) -/*! D1TCM_ECCS_EFW - D1TCM single-bit ECC error corresponding tcm_wr value +/*! D1TCM_ECCS_EFW - D1TCM single-bit ECC error corresponding TCM_WR value */ #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_MASK) + #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_MASK (0xEU) #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_SHIFT (1U) /*! D1TCM_ECCS_EFSIZ - D1TCM single-bit ECC error corresponding tcm access size */ #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_MASK) + #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_MASK (0xF0U) #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_SHIFT (4U) -/*! D1TCM_ECCS_EFMST - D1TCM single-bit ECC error corresponding tcm_master +/*! D1TCM_ECCS_EFMST - D1TCM single-bit ECC error corresponding TCM_MASTER */ #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_MASK) + #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_MASK (0xF00U) #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_SHIFT (8U) -/*! D1TCM_ECCS_EFPRT - D1TCM single-bit ECC error corresponding tcm_priv +/*! D1TCM_ECCS_EFPRT - D1TCM single-bit ECC error corresponding TCM_PRIV */ #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_MASK) + #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_MASK (0x7F000U) #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_SHIFT (12U) /*! D1TCM_ECCS_EFSYN - D1TCM single-bit ECC error corresponding syndrome */ #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_MASK) + #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFF80000U) #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (19U) /*! Reserved - Reserved @@ -41714,6 +50157,7 @@ typedef struct { /*! @name D1TCM_ECC_SINGLE_ERROR_ADDR - D1TCM single-bit ECC Error Address Register */ /*! @{ */ + #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU) #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_SHIFT (0U) /*! D1TCM_ECCS_ERRED_ADDR - D1TCM single-bit ECC error address @@ -41723,6 +50167,7 @@ typedef struct { /*! @name D1TCM_ECC_SINGLE_ERROR_DATA - D1TCM single-bit ECC Error Data Register */ /*! @{ */ + #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_MASK (0xFFFFFFFFU) #define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_SHIFT (0U) /*! D1TCM_ECCS_ERRED_DATA - D1TCM single-bit ECC error data @@ -41732,31 +50177,37 @@ typedef struct { /*! @name D1TCM_ECC_MULTI_ERROR_INFO - D1TCM multi-bit ECC Error Information Register */ /*! @{ */ + #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_MASK (0x1U) #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_SHIFT (0U) -/*! D1TCM_ECCM_EFW - D1TCM multi-bit ECC error corresponding tcm_wr value +/*! D1TCM_ECCM_EFW - D1TCM multi-bit ECC error corresponding TCM_WR value */ #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_MASK) + #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_MASK (0xEU) #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_SHIFT (1U) /*! D1TCM_ECCM_EFSIZ - D1TCM multi-bit ECC error corresponding tcm access size */ #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_MASK) + #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_MASK (0xF0U) #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_SHIFT (4U) -/*! D1TCM_ECCM_EFMST - D1TCM multi-bit ECC error corresponding tcm_master +/*! D1TCM_ECCM_EFMST - D1TCM multi-bit ECC error corresponding TCM_MASTER */ #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_MASK) + #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_MASK (0xF00U) #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_SHIFT (8U) -/*! D1TCM_ECCM_EFPRT - D1TCM multi-bit ECC error corresponding tcm_priv +/*! D1TCM_ECCM_EFPRT - D1TCM multi-bit ECC error corresponding TCM_PRIV */ #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_MASK) + #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN_MASK (0x7F000U) #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN_SHIFT (12U) /*! D1TCM_ECCM_EFSYN - D1TCM multi-bit ECC error corresponding syndrome */ #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN_MASK) + #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFF80000U) #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (19U) /*! Reserved - Reserved @@ -41766,6 +50217,7 @@ typedef struct { /*! @name D1TCM_ECC_MULTI_ERROR_ADDR - D1TCM multi-bit ECC Error Address Register */ /*! @{ */ + #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU) #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_SHIFT (0U) /*! D1TCM_ECCM_ERRED_ADDR - D1TCM multi-bit ECC error address @@ -41775,6 +50227,7 @@ typedef struct { /*! @name D1TCM_ECC_MULTI_ERROR_DATA - D1TCM multi-bit ECC Error Data Register */ /*! @{ */ + #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_MASK (0xFFFFFFFFU) #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_SHIFT (0U) /*! D1TCM_ECCM_ERRED_DATA - D1TCM multi-bit ECC error data @@ -41782,38 +50235,45 @@ typedef struct { #define FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_MASK) /*! @} */ -/*! @name FLEXRAM_CTRL - Flexram feature ECC and ocram wait pipeline can be configured through this register */ +/*! @name FLEXRAM_CTRL - FlexRAM feature Control register */ /*! @{ */ + #define FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN_MASK (0x1U) #define FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN_SHIFT (0U) /*! OCRAM_RDATA_WAIT_EN - Read Data Wait Enable */ #define FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN_MASK) + #define FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN_MASK (0x2U) #define FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN_SHIFT (1U) /*! OCRAM_RADDR_PIPELINE_EN - Read Address Pipeline Enable */ #define FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN_MASK) + #define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN_MASK (0x4U) #define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN_SHIFT (2U) /*! OCRAM_WRDATA_PIPELINE_EN - Write Data Pipeline Enable */ #define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN_MASK) + #define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN_MASK (0x8U) #define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN_SHIFT (3U) /*! OCRAM_WRADDR_PIPELINE_EN - Write Address Pipeline Enable */ #define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN_MASK) + #define FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_MASK (0x10U) #define FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_SHIFT (4U) /*! OCRAM_ECC_EN - OCRAM ECC enable */ #define FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_MASK) + #define FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_MASK (0x20U) #define FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_SHIFT (5U) /*! TCM_ECC_EN - TCM ECC enable */ #define FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_MASK) + #define FLEXRAM_FLEXRAM_CTRL_Reserved_MASK (0xFFFFFFC0U) #define FLEXRAM_FLEXRAM_CTRL_Reserved_SHIFT (6U) /*! Reserved - Reserved @@ -41821,28 +50281,33 @@ typedef struct { #define FLEXRAM_FLEXRAM_CTRL_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_Reserved_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_Reserved_MASK) /*! @} */ -/*! @name OCRAM_PIPELINE_STATUS - Update pending signal for ocram wait and pipeline enable */ +/*! @name OCRAM_PIPELINE_STATUS - OCRAM Pipeline Status register */ /*! @{ */ + #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING_MASK (0x1U) #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING_SHIFT (0U) /*! OCRAM_RDATA_WAIT_EN_UPDATA_PENDING - Read Data Wait Enable Pending */ #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING_MASK) + #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING_MASK (0x2U) #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING_SHIFT (1U) /*! OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING - Read Address Pipeline Enable Pending */ #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING_MASK) + #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING_MASK (0x4U) #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING_SHIFT (2U) /*! OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING - Write Data Pipeline Enable Pending */ #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING_MASK) + #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING_MASK (0x8U) #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING_SHIFT (3U) /*! OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING - Write Address Pipeline Enable Pending */ #define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING_MASK) + #define FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved_MASK (0xFFFFFFF0U) #define FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved_SHIFT (4U) /*! Reserved - Reserved @@ -41909,7 +50374,11 @@ typedef struct { __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */ __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */ __IO uint32_t DLLCR[2]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */ - uint8_t RESERVED_5[24]; + uint8_t RESERVED_5[8]; + __I uint32_t MISCCR4; /**< Misc Control Register 4, offset: 0xD0 */ + __I uint32_t MISCCR5; /**< Misc Control Register 5, offset: 0xD4 */ + __I uint32_t MISCCR6; /**< Misc Control Register 6, offset: 0xD8 */ + __I uint32_t MISCCR7; /**< Misc Control Register 7, offset: 0xDC */ __I uint32_t STS0; /**< Status Register 0, offset: 0xE0 */ __I uint32_t STS1; /**< Status Register 1, offset: 0xE4 */ __I uint32_t STS2; /**< Status Register 2, offset: 0xE8 */ @@ -41920,6 +50389,24 @@ typedef struct { __I uint32_t RFDR[32]; /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */ __O uint32_t TFDR[32]; /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */ __IO uint32_t LUT[64]; /**< LUT 0..LUT 63, array offset: 0x200, array step: 0x4 */ + uint8_t RESERVED_7[256]; + __IO uint32_t HMSTRCR[8]; /**< AHB Master ID 0 Control Register..AHB Master ID 7 Control Register, array offset: 0x400, array step: 0x4 */ + __IO uint32_t HADDRSTART; /**< HADDR REMAP START ADDR, offset: 0x420 */ + __IO uint32_t HADDREND; /**< HADDR REMAP END ADDR, offset: 0x424 */ + __IO uint32_t HADDROFFSET; /**< HADDR REMAP OFFSET, offset: 0x428 */ + uint8_t RESERVED_8[4]; + __IO uint32_t IPSNSZSTART0; /**< IPS nonsecure region Start address of region 0, offset: 0x430 */ + __IO uint32_t IPSNSZEND0; /**< IPS nonsecure region End address of region 0, offset: 0x434 */ + __IO uint32_t IPSNSZSTART1; /**< IPS nonsecure region Start address of region 1, offset: 0x438 */ + __IO uint32_t IPSNSZEND1; /**< IPS nonsecure region End address of region 1, offset: 0x43C */ + __IO uint32_t AHBBUFREGIONSTART0; /**< RX BUF Start address of region 0, offset: 0x440 */ + __IO uint32_t AHBBUFREGIONEND0; /**< RX BUF region End address of region 0, offset: 0x444 */ + __IO uint32_t AHBBUFREGIONSTART1; /**< RX BUF Start address of region 1, offset: 0x448 */ + __IO uint32_t AHBBUFREGIONEND1; /**< RX BUF region End address of region 1, offset: 0x44C */ + __IO uint32_t AHBBUFREGIONSTART2; /**< RX BUF Start address of region 2, offset: 0x450 */ + __IO uint32_t AHBBUFREGIONEND2; /**< RX BUF region End address of region 2, offset: 0x454 */ + __IO uint32_t AHBBUFREGIONSTART3; /**< RX BUF Start address of region 3, offset: 0x458 */ + __IO uint32_t AHBBUFREGIONEND3; /**< RX BUF region End address of region 3, offset: 0x45C */ } FLEXSPI_Type; /* ---------------------------------------------------------------------------- @@ -41933,16 +50420,19 @@ typedef struct { /*! @name MCR0 - Module Control Register 0 */ /*! @{ */ + #define FLEXSPI_MCR0_SWRESET_MASK (0x1U) #define FLEXSPI_MCR0_SWRESET_SHIFT (0U) /*! SWRESET - Software Reset */ #define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK) + #define FLEXSPI_MCR0_MDIS_MASK (0x2U) #define FLEXSPI_MCR0_MDIS_SHIFT (1U) /*! MDIS - Module Disable */ #define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK) + #define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U) #define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U) /*! RXCLKSRC - Sample Clock source selection for Flash Reading @@ -41952,6 +50442,7 @@ typedef struct { * 0b11..Flash provided Read strobe and input from DQS pad */ #define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK) + #define FLEXSPI_MCR0_ARDFEN_MASK (0x40U) #define FLEXSPI_MCR0_ARDFEN_SHIFT (6U) /*! ARDFEN - Enable AHB bus Read Access to IP RX FIFO. @@ -41959,6 +50450,7 @@ typedef struct { * 0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response. */ #define FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK) + #define FLEXSPI_MCR0_ATDFEN_MASK (0x80U) #define FLEXSPI_MCR0_ATDFEN_SHIFT (7U) /*! ATDFEN - Enable AHB bus Write Access to IP TX FIFO. @@ -41966,6 +50458,7 @@ typedef struct { * 0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response. */ #define FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK) + #define FLEXSPI_MCR0_SERCLKDIV_MASK (0x700U) #define FLEXSPI_MCR0_SERCLKDIV_SHIFT (8U) /*! SERCLKDIV - The serial root clock could be divided inside FlexSPI . Refer Clocks chapter for more details on clocking. @@ -41979,6 +50472,7 @@ typedef struct { * 0b111..Divided by 8 */ #define FLEXSPI_MCR0_SERCLKDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK) + #define FLEXSPI_MCR0_HSEN_MASK (0x800U) #define FLEXSPI_MCR0_HSEN_SHIFT (11U) /*! HSEN - Half Speed Serial Flash access Enable. @@ -41986,6 +50480,7 @@ typedef struct { * 0b1..Enable divide by 2 of serial flash clock for half speed commands. */ #define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK) + #define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U) #define FLEXSPI_MCR0_DOZEEN_SHIFT (12U) /*! DOZEEN - Doze mode enable bit @@ -41993,13 +50488,16 @@ typedef struct { * 0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system. */ #define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK) + #define FLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U) #define FLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U) -/*! COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and B_DATA[3:0]). +/*! COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data + * pins (A_DATA[3:0] and B_DATA[3:0]), when Port A and Port B are of 4 bit data width. * 0b0..Disable. * 0b1..Enable. */ #define FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK) + #define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U) #define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U) /*! SCKFREERUNEN - This bit is used to force SCLK output free-running. For FPGA applications, @@ -42009,11 +50507,13 @@ typedef struct { * 0b1..Enable. */ #define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK) + #define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U) #define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U) /*! IPGRANTWAIT - Time out wait cycle for IP command grant. */ #define FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK) + #define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U) #define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U) /*! AHBGRANTWAIT - Timeout wait cycle for AHB command grant. @@ -42023,9 +50523,11 @@ typedef struct { /*! @name MCR1 - Module Control Register 1 */ /*! @{ */ + #define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU) #define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U) #define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK) + #define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U) #define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U) #define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK) @@ -42033,6 +50535,7 @@ typedef struct { /*! @name MCR2 - Module Control Register 2 */ /*! @{ */ + #define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U) #define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U) /*! CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned @@ -42043,12 +50546,7 @@ typedef struct { * 0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK. */ #define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK) -#define FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U) -#define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U) -/*! CLRLEARNPHASE - The sampling clock phase selection will be reset to phase 0 when this bit is - * written with 0x1. This bit will be auto-cleared immediately. - */ -#define FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK) + #define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U) #define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U) /*! SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2. @@ -42059,6 +50557,7 @@ typedef struct { * 0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored. */ #define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK) + #define FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U) #define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U) /*! SCKBDIFFOPT - B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to @@ -42068,6 +50567,7 @@ typedef struct { * 0b0..B_SCLK pad is used as port B SCLK clock output. Port B flash access is available. */ #define FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK) + #define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U) #define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U) /*! RESUMEWAIT - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed. @@ -42077,6 +50577,7 @@ typedef struct { /*! @name AHBCR - AHB Bus Control Register */ /*! @{ */ + #define FLEXSPI_AHBCR_APAREN_MASK (0x1U) #define FLEXSPI_AHBCR_APAREN_SHIFT (0U) /*! APAREN - Parallel mode enabled for AHB triggered Command (both read and write) . @@ -42084,6 +50585,13 @@ typedef struct { * 0b1..Flash will be accessed in Parallel mode. */ #define FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK) + +#define FLEXSPI_AHBCR_CLRAHBRXBUF_MASK (0x2U) +#define FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT (1U) +/*! CLRAHBRXBUF - Clear the status/pointers of AHB RX Buffer. Auto-cleared. + */ +#define FLEXSPI_AHBCR_CLRAHBRXBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBRXBUF_MASK) + #define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U) #define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U) /*! CACHABLEEN - Enable AHB bus cachable read access support. @@ -42091,6 +50599,7 @@ typedef struct { * 0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first. */ #define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK) + #define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U) #define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U) /*! BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat @@ -42101,11 +50610,13 @@ typedef struct { * granted by arbitrator and will not wait for AHB command finished. */ #define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK) + #define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U) #define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U) /*! PREFETCHEN - AHB Read Prefetch Enable. */ #define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK) + #define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U) #define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U) /*! READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation. @@ -42114,6 +50625,7 @@ typedef struct { * burst required to meet the alignment requirement. */ #define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK) + #define FLEXSPI_AHBCR_READSZALIGN_MASK (0x400U) #define FLEXSPI_AHBCR_READSZALIGN_SHIFT (10U) /*! READSZALIGN - AHB Read Size Alignment @@ -42121,151 +50633,284 @@ typedef struct { * 0b1..AHB read size to up size to 8 bytes aligned, no prefetching */ #define FLEXSPI_AHBCR_READSZALIGN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READSZALIGN_SHIFT)) & FLEXSPI_AHBCR_READSZALIGN_MASK) + +#define FLEXSPI_AHBCR_ECCEN_MASK (0x800U) +#define FLEXSPI_AHBCR_ECCEN_SHIFT (11U) +/*! ECCEN - AHB Read ECC Enable + * 0b0..AHB read ECC check disabled + * 0b1..AHB read ECC check enabled + */ +#define FLEXSPI_AHBCR_ECCEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCEN_SHIFT)) & FLEXSPI_AHBCR_ECCEN_MASK) + +#define FLEXSPI_AHBCR_SPLITEN_MASK (0x1000U) +#define FLEXSPI_AHBCR_SPLITEN_SHIFT (12U) +/*! SPLITEN - AHB transaction SPLIT + * 0b0..AHB Split disabled + * 0b1..AHB Split enabled + */ +#define FLEXSPI_AHBCR_SPLITEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_SPLITEN_SHIFT)) & FLEXSPI_AHBCR_SPLITEN_MASK) + +#define FLEXSPI_AHBCR_SPLIT_LIMIT_MASK (0x6000U) +#define FLEXSPI_AHBCR_SPLIT_LIMIT_SHIFT (13U) +/*! SPLIT_LIMIT - AHB SPLIT SIZE + * 0b00..AHB Split Size=8bytes + * 0b01..AHB Split Size=16bytes + * 0b10..AHB Split Size=32bytes + * 0b11..AHB Split Size=64bytes + */ +#define FLEXSPI_AHBCR_SPLIT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_SPLIT_LIMIT_SHIFT)) & FLEXSPI_AHBCR_SPLIT_LIMIT_MASK) + +#define FLEXSPI_AHBCR_KEYECCEN_MASK (0x8000U) +#define FLEXSPI_AHBCR_KEYECCEN_SHIFT (15U) +/*! KEYECCEN - OTFAD KEY BLOC ECC Enable + * 0b0..AHB KEY ECC check disabled + * 0b1..AHB KEY ECC check enabled + */ +#define FLEXSPI_AHBCR_KEYECCEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_KEYECCEN_SHIFT)) & FLEXSPI_AHBCR_KEYECCEN_MASK) + +#define FLEXSPI_AHBCR_ECCSINGLEERRCLR_MASK (0x10000U) +#define FLEXSPI_AHBCR_ECCSINGLEERRCLR_SHIFT (16U) +/*! ECCSINGLEERRCLR - AHB ECC Single bit ERR CLR + */ +#define FLEXSPI_AHBCR_ECCSINGLEERRCLR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCSINGLEERRCLR_SHIFT)) & FLEXSPI_AHBCR_ECCSINGLEERRCLR_MASK) + +#define FLEXSPI_AHBCR_ECCMULTIERRCLR_MASK (0x20000U) +#define FLEXSPI_AHBCR_ECCMULTIERRCLR_SHIFT (17U) +/*! ECCMULTIERRCLR - AHB ECC Multi bits ERR CLR + */ +#define FLEXSPI_AHBCR_ECCMULTIERRCLR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCMULTIERRCLR_SHIFT)) & FLEXSPI_AHBCR_ECCMULTIERRCLR_MASK) + +#define FLEXSPI_AHBCR_HMSTRIDREMAP_MASK (0x40000U) +#define FLEXSPI_AHBCR_HMSTRIDREMAP_SHIFT (18U) +/*! HMSTRIDREMAP - AHB Master ID Remapping enable + */ +#define FLEXSPI_AHBCR_HMSTRIDREMAP(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_HMSTRIDREMAP_SHIFT)) & FLEXSPI_AHBCR_HMSTRIDREMAP_MASK) + +#define FLEXSPI_AHBCR_ECCSWAPEN_MASK (0x80000U) +#define FLEXSPI_AHBCR_ECCSWAPEN_SHIFT (19U) +/*! ECCSWAPEN - ECC Read data swap function + * 0b0..rdata send to ecc check without swap. + * 0b1..rdata send to ecc ehck with swap. + */ +#define FLEXSPI_AHBCR_ECCSWAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCSWAPEN_SHIFT)) & FLEXSPI_AHBCR_ECCSWAPEN_MASK) + +#define FLEXSPI_AHBCR_ALIGNMENT_MASK (0x300000U) +#define FLEXSPI_AHBCR_ALIGNMENT_SHIFT (20U) +/*! ALIGNMENT - Decides all AHB read/write boundary. All access cross the boundary will be divided into smaller sub accesses. + * 0b00..No limit + * 0b01..1 KBytes + * 0b10..512 Bytes + * 0b11..256 Bytes + */ +#define FLEXSPI_AHBCR_ALIGNMENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ALIGNMENT_SHIFT)) & FLEXSPI_AHBCR_ALIGNMENT_MASK) /*! @} */ /*! @name INTEN - Interrupt Enable Register */ /*! @{ */ + #define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U) #define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U) /*! IPCMDDONEEN - IP triggered Command Sequences Execution finished interrupt enable. */ #define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK) + #define FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U) #define FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U) /*! IPCMDGEEN - IP triggered Command Sequences Grant Timeout interrupt enable. */ #define FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK) + #define FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U) #define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U) /*! AHBCMDGEEN - AHB triggered Command Sequences Grant Timeout interrupt enable. */ #define FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK) + #define FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U) #define FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U) /*! IPCMDERREN - IP triggered Command Sequences Error Detected interrupt enable. */ #define FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK) + #define FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U) #define FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U) /*! AHBCMDERREN - AHB triggered Command Sequences Error Detected interrupt enable. */ #define FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK) + #define FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U) #define FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U) /*! IPRXWAEN - IP RX FIFO WaterMark available interrupt enable. */ #define FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK) + #define FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U) #define FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U) /*! IPTXWEEN - IP TX FIFO WaterMark empty interrupt enable. */ #define FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK) + #define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U) #define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U) /*! SCKSTOPBYRDEN - SCLK is stopped during command sequence because Async RX FIFO full interrupt enable. */ #define FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK) + #define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U) #define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U) /*! SCKSTOPBYWREN - SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable. */ #define FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK) + #define FLEXSPI_INTEN_AHBBUSERROREN_MASK (0x400U) #define FLEXSPI_INTEN_AHBBUSERROREN_SHIFT (10U) /*! AHBBUSERROREN - AHB Bus error interrupt enable.Refer Interrupts chapter for more details. */ #define FLEXSPI_INTEN_AHBBUSERROREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSERROREN_SHIFT)) & FLEXSPI_INTEN_AHBBUSERROREN_MASK) + #define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U) #define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U) /*! SEQTIMEOUTEN - Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details. */ #define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK) + #define FLEXSPI_INTEN_KEYDONEEN_MASK (0x1000U) #define FLEXSPI_INTEN_KEYDONEEN_SHIFT (12U) /*! KEYDONEEN - OTFAD key blob processing done interrupt enable.Refer Interrupts chapter for more details. */ #define FLEXSPI_INTEN_KEYDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYDONEEN_SHIFT)) & FLEXSPI_INTEN_KEYDONEEN_MASK) + #define FLEXSPI_INTEN_KEYERROREN_MASK (0x2000U) #define FLEXSPI_INTEN_KEYERROREN_SHIFT (13U) /*! KEYERROREN - OTFAD key blob processing error interrupt enable.Refer Interrupts chapter for more details. */ #define FLEXSPI_INTEN_KEYERROREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYERROREN_SHIFT)) & FLEXSPI_INTEN_KEYERROREN_MASK) + +#define FLEXSPI_INTEN_ECCMULTIERREN_MASK (0x4000U) +#define FLEXSPI_INTEN_ECCMULTIERREN_SHIFT (14U) +/*! ECCMULTIERREN - ECC multi bits error interrupt enable.Refer Interrupts chapter for more details. + */ +#define FLEXSPI_INTEN_ECCMULTIERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_ECCMULTIERREN_SHIFT)) & FLEXSPI_INTEN_ECCMULTIERREN_MASK) + +#define FLEXSPI_INTEN_ECCSINGLEERREN_MASK (0x8000U) +#define FLEXSPI_INTEN_ECCSINGLEERREN_SHIFT (15U) +/*! ECCSINGLEERREN - ECC single bit error interrupt enable.Refer Interrupts chapter for more details. + */ +#define FLEXSPI_INTEN_ECCSINGLEERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_ECCSINGLEERREN_SHIFT)) & FLEXSPI_INTEN_ECCSINGLEERREN_MASK) + +#define FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK (0x10000U) +#define FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT (16U) +/*! IPCMDSECUREVIOEN - IP command security violation interrupt enable. + */ +#define FLEXSPI_INTEN_IPCMDSECUREVIOEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT)) & FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK) /*! @} */ /*! @name INTR - Interrupt Register */ /*! @{ */ + #define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U) #define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U) /*! IPCMDDONE - IP triggered Command Sequences Execution finished interrupt. This interrupt is also * generated when there is IPCMDGE or IPCMDERR interrupt generated. */ #define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK) + #define FLEXSPI_INTR_IPCMDGE_MASK (0x2U) #define FLEXSPI_INTR_IPCMDGE_SHIFT (1U) /*! IPCMDGE - IP triggered Command Sequences Grant Timeout interrupt. */ #define FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK) + #define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) #define FLEXSPI_INTR_AHBCMDGE_SHIFT (2U) /*! AHBCMDGE - AHB triggered Command Sequences Grant Timeout interrupt. */ #define FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK) + #define FLEXSPI_INTR_IPCMDERR_MASK (0x8U) #define FLEXSPI_INTR_IPCMDERR_SHIFT (3U) /*! IPCMDERR - IP triggered Command Sequences Error Detected interrupt. When an error detected for * IP command, this command will be ignored and not executed at all. */ #define FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK) + #define FLEXSPI_INTR_AHBCMDERR_MASK (0x10U) #define FLEXSPI_INTR_AHBCMDERR_SHIFT (4U) /*! AHBCMDERR - AHB triggered Command Sequences Error Detected interrupt. When an error detected for * AHB command, this command will be ignored and not executed at all. */ #define FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK) + #define FLEXSPI_INTR_IPRXWA_MASK (0x20U) #define FLEXSPI_INTR_IPRXWA_SHIFT (5U) /*! IPRXWA - IP RX FIFO watermark available interrupt. */ #define FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK) + #define FLEXSPI_INTR_IPTXWE_MASK (0x40U) #define FLEXSPI_INTR_IPTXWE_SHIFT (6U) /*! IPTXWE - IP TX FIFO watermark empty interrupt. */ #define FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK) + #define FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U) #define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U) /*! SCKSTOPBYRD - SCLK is stopped during command sequence because Async RX FIFO full interrupt. */ #define FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK) + #define FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U) #define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U) /*! SCKSTOPBYWR - SCLK is stopped during command sequence because Async TX FIFO empty interrupt. */ #define FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK) + #define FLEXSPI_INTR_AHBBUSERROR_MASK (0x400U) #define FLEXSPI_INTR_AHBBUSERROR_SHIFT (10U) /*! AHBBUSERROR - AHB Bus timeout or AHB bus illegal access Flash during OTFAD key blob processing interrupt. */ #define FLEXSPI_INTR_AHBBUSERROR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSERROR_SHIFT)) & FLEXSPI_INTR_AHBBUSERROR_MASK) + #define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U) #define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U) /*! SEQTIMEOUT - Sequence execution timeout interrupt. */ #define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK) + #define FLEXSPI_INTR_KEYDONE_MASK (0x1000U) #define FLEXSPI_INTR_KEYDONE_SHIFT (12U) /*! KEYDONE - OTFAD key blob processing done interrupt. */ #define FLEXSPI_INTR_KEYDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYDONE_SHIFT)) & FLEXSPI_INTR_KEYDONE_MASK) + #define FLEXSPI_INTR_KEYERROR_MASK (0x2000U) #define FLEXSPI_INTR_KEYERROR_SHIFT (13U) /*! KEYERROR - OTFAD key blob processing error interrupt. */ #define FLEXSPI_INTR_KEYERROR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYERROR_SHIFT)) & FLEXSPI_INTR_KEYERROR_MASK) + +#define FLEXSPI_INTR_ECCMULTIERR_MASK (0x4000U) +#define FLEXSPI_INTR_ECCMULTIERR_SHIFT (14U) +/*! ECCMULTIERR - ECC multi bits error interrupt. + */ +#define FLEXSPI_INTR_ECCMULTIERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_ECCMULTIERR_SHIFT)) & FLEXSPI_INTR_ECCMULTIERR_MASK) + +#define FLEXSPI_INTR_ECCSINGLEERR_MASK (0x8000U) +#define FLEXSPI_INTR_ECCSINGLEERR_SHIFT (15U) +/*! ECCSINGLEERR - ECC single bit error interrupt. + */ +#define FLEXSPI_INTR_ECCSINGLEERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_ECCSINGLEERR_SHIFT)) & FLEXSPI_INTR_ECCSINGLEERR_MASK) + +#define FLEXSPI_INTR_IPCMDSECUREVIO_MASK (0x10000U) +#define FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT (16U) +/*! IPCMDSECUREVIO - IP command security violation interrupt. + */ +#define FLEXSPI_INTR_IPCMDSECUREVIO(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT)) & FLEXSPI_INTR_IPCMDSECUREVIO_MASK) /*! @} */ /*! @name LUTKEY - LUT Key Register */ /*! @{ */ + #define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) #define FLEXSPI_LUTKEY_KEY_SHIFT (0U) /*! KEY - The Key to lock or unlock LUT. @@ -42275,35 +50920,53 @@ typedef struct { /*! @name LUTCR - LUT Control Register */ /*! @{ */ + #define FLEXSPI_LUTCR_LOCK_MASK (0x1U) #define FLEXSPI_LUTCR_LOCK_SHIFT (0U) /*! LOCK - Lock LUT */ #define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK) + #define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U) #define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U) /*! UNLOCK - Unlock LUT */ #define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK) + +#define FLEXSPI_LUTCR_PROTECT_MASK (0x4U) +#define FLEXSPI_LUTCR_PROTECT_SHIFT (2U) +/*! PROTECT - LUT protection + */ +#define FLEXSPI_LUTCR_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_PROTECT_SHIFT)) & FLEXSPI_LUTCR_PROTECT_MASK) /*! @} */ /*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0 */ /*! @{ */ + #define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0x3FFU) #define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U) /*! BUFSZ - AHB RX Buffer Size in 64 bits. */ #define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK) + #define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U) #define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U) /*! MSTRID - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID). */ #define FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK) + #define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x7000000U) #define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U) /*! PRIORITY - This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest. */ #define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK) + +#define FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK (0x40000000U) +#define FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT (30U) +/*! REGIONEN - AHB RX Buffer address region funciton enable + */ +#define FLEXSPI_AHBRXBUFCR0_REGIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK) + #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U) #define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U) /*! PREFETCHEN - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master. @@ -42316,11 +50979,24 @@ typedef struct { /*! @name FLSHCR0 - Flash Control Register 0 */ /*! @{ */ + #define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU) #define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U) /*! FLSHSZ - Flash Size in KByte. */ #define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) + +#define FLEXSPI_FLSHCR0_SPLITWREN_MASK (0x40000000U) +#define FLEXSPI_FLSHCR0_SPLITWREN_SHIFT (30U) +/*! SPLITWREN - AHB write access split function control. + */ +#define FLEXSPI_FLSHCR0_SPLITWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITWREN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITWREN_MASK) + +#define FLEXSPI_FLSHCR0_SPLITRDEN_MASK (0x80000000U) +#define FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT (31U) +/*! SPLITRDEN - AHB read access split function control. + */ +#define FLEXSPI_FLSHCR0_SPLITRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITRDEN_MASK) /*! @} */ /* The count of FLEXSPI_FLSHCR0 */ @@ -42328,26 +51004,31 @@ typedef struct { /*! @name FLSHCR1 - Flash Control Register 1 */ /*! @{ */ + #define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU) #define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U) /*! TCSS - Serial Flash CS setup time. */ #define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK) + #define FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U) #define FLEXSPI_FLSHCR1_TCSH_SHIFT (5U) /*! TCSH - Serial Flash CS Hold time. */ #define FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK) + #define FLEXSPI_FLSHCR1_WA_MASK (0x400U) #define FLEXSPI_FLSHCR1_WA_SHIFT (10U) /*! WA - Word Addressable. */ #define FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK) + #define FLEXSPI_FLSHCR1_CAS_MASK (0x7800U) #define FLEXSPI_FLSHCR1_CAS_SHIFT (11U) /*! CAS - Column Address Size. */ #define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK) + #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U) #define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U) /*! CSINTERVALUNIT - CS interval unit @@ -42355,6 +51036,7 @@ typedef struct { * 0b1..The CS interval unit is 256 serial clock cycle */ #define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK) + #define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U) #define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U) /*! CSINTERVAL - This field is used to set the minimum interval between flash device Chip selection @@ -42370,29 +51052,35 @@ typedef struct { /*! @name FLSHCR2 - Flash Control Register 2 */ /*! @{ */ + #define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU) #define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U) /*! ARDSEQID - Sequence Index for AHB Read triggered Command in LUT. */ #define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK) + #define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) #define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U) /*! ARDSEQNUM - Sequence Number for AHB Read triggered Command in LUT. */ #define FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK) + #define FLEXSPI_FLSHCR2_AWRSEQID_MASK (0xF00U) #define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U) /*! AWRSEQID - Sequence Index for AHB Write triggered Command. */ #define FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK) + #define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U) #define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U) /*! AWRSEQNUM - Sequence Number for AHB Write triggered Command. */ #define FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK) + #define FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U) #define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U) #define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK) + #define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U) #define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U) /*! AWRWAITUNIT - AWRWAIT unit @@ -42406,6 +51094,7 @@ typedef struct { * 0b111..The AWRWAIT unit is 32768 ahb clock cycle */ #define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK) + #define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U) #define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U) /*! CLRINSTRPTR - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. @@ -42419,6 +51108,7 @@ typedef struct { /*! @name FLSHCR4 - Flash Control Register 4 */ /*! @{ */ + #define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U) #define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U) /*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation. @@ -42428,6 +51118,18 @@ typedef struct { * burst start address alignment when flash is accessed in individual mode. */ #define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK) + +#define FLEXSPI_FLSHCR4_WMOPT2_MASK (0x2U) +#define FLEXSPI_FLSHCR4_WMOPT2_SHIFT (1U) +/*! WMOPT2 - Write mask option bit 2. When using AP memory, This option bit could be used to remove + * AHB write burst minimal length limitation. When using this bit, WMOPT1 should also be set. + * 0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write + * burst length when flash is accessed in individual mode. + * 0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write + * burst length when flash is accessed in individual mode, the minimal write burst length should be 4. + */ +#define FLEXSPI_FLSHCR4_WMOPT2(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT2_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT2_MASK) + #define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U) #define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U) /*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for @@ -42436,6 +51138,7 @@ typedef struct { * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. */ #define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK) + #define FLEXSPI_FLSHCR4_WMENB_MASK (0x8U) #define FLEXSPI_FLSHCR4_WMENB_SHIFT (3U) /*! WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for @@ -42444,10 +51147,23 @@ typedef struct { * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device. */ #define FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK) + +#define FLEXSPI_FLSHCR4_PAR_WM_MASK (0x600U) +#define FLEXSPI_FLSHCR4_PAR_WM_SHIFT (9U) +/*! PAR_WM - Enable APMEM 16 bit write mask function, bit 9 for A1-B1 pair, bit 10 for A2-B2 pair. + */ +#define FLEXSPI_FLSHCR4_PAR_WM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_PAR_WM_SHIFT)) & FLEXSPI_FLSHCR4_PAR_WM_MASK) + +#define FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_MASK (0x800U) +#define FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_SHIFT (11U) +/*! PAR_ADDR_ADJ_DIS - Disable the address shift logic for lower density of 16 bit PSRAM. + */ +#define FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_SHIFT)) & FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_MASK) /*! @} */ /*! @name IPCR0 - IP Control Register 0 */ /*! @{ */ + #define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU) #define FLEXSPI_IPCR0_SFAR_SHIFT (0U) /*! SFAR - Serial Flash Address for IP command. @@ -42457,21 +51173,25 @@ typedef struct { /*! @name IPCR1 - IP Control Register 1 */ /*! @{ */ + #define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU) #define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U) /*! IDATSZ - Flash Read/Program Data Size (in Bytes) for IP command. */ #define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK) + #define FLEXSPI_IPCR1_ISEQID_MASK (0xF0000U) #define FLEXSPI_IPCR1_ISEQID_SHIFT (16U) /*! ISEQID - Sequence Index in LUT for IP command. */ #define FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK) + #define FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U) #define FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U) /*! ISEQNUM - Sequence Number for IP command: ISEQNUM+1. */ #define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK) + #define FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U) #define FLEXSPI_IPCR1_IPAREN_SHIFT (31U) /*! IPAREN - Parallel mode Enabled for IP command. @@ -42483,6 +51203,7 @@ typedef struct { /*! @name IPCMD - IP Command Register */ /*! @{ */ + #define FLEXSPI_IPCMD_TRG_MASK (0x1U) #define FLEXSPI_IPCMD_TRG_SHIFT (0U) /*! TRG - Setting this bit will trigger an IP Command. @@ -42492,11 +51213,13 @@ typedef struct { /*! @name IPRXFCR - IP RX FIFO Control Register */ /*! @{ */ + #define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U) #define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U) /*! CLRIPRXF - Clear all valid data entries in IP RX FIFO. */ #define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK) + #define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U) #define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U) /*! RXDMAEN - IP RX FIFO reading by DMA enabled. @@ -42504,6 +51227,7 @@ typedef struct { * 0b1..IP RX FIFO would be read by DMA. */ #define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK) + #define FLEXSPI_IPRXFCR_RXWMRK_MASK (0x7CU) #define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U) /*! RXWMRK - Watermark level is (RXWMRK+1)*64 Bits. @@ -42513,11 +51237,13 @@ typedef struct { /*! @name IPTXFCR - IP TX FIFO Control Register */ /*! @{ */ + #define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U) #define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U) /*! CLRIPTXF - Clear all valid data entries in IP TX FIFO. */ #define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK) + #define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U) #define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U) /*! TXDMAEN - IP TX FIFO filling by DMA enabled. @@ -42525,6 +51251,7 @@ typedef struct { * 0b1..IP TX FIFO would be filled by DMA. */ #define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK) + #define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x7CU) #define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U) /*! TXWMRK - Watermark level is (TXWMRK+1)*64 Bits. @@ -42534,11 +51261,13 @@ typedef struct { /*! @name DLLCR - DLL Control Register 0 */ /*! @{ */ + #define FLEXSPI_DLLCR_DLLEN_MASK (0x1U) #define FLEXSPI_DLLCR_DLLEN_SHIFT (0U) /*! DLLEN - DLL calibration enable. */ #define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK) + #define FLEXSPI_DLLCR_DLLRESET_MASK (0x2U) #define FLEXSPI_DLLCR_DLLRESET_SHIFT (1U) /*! DLLRESET - Software could force a reset on DLL by setting this field to 0x1. This will cause the @@ -42547,6 +51276,7 @@ typedef struct { * limitation). */ #define FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK) + #define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U) #define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U) /*! SLVDLYTARGET - The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle @@ -42554,11 +51284,13 @@ typedef struct { * OVRDEN set to =0x0, then SLVDLYTARGET setting of 0xF is recommended. */ #define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK) + #define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U) #define FLEXSPI_DLLCR_OVRDEN_SHIFT (8U) /*! OVRDEN - Slave clock delay line delay cell number selection override enable. */ #define FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK) + #define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U) #define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U) /*! OVRDVAL - Slave clock delay line delay cell number selection override value. @@ -42569,14 +51301,80 @@ typedef struct { /* The count of FLEXSPI_DLLCR */ #define FLEXSPI_DLLCR_COUNT (2U) +/*! @name MISCCR4 - Misc Control Register 4 */ +/*! @{ */ + +#define FLEXSPI_MISCCR4_AHBADDRESS_MASK (0xFFFFFFFFU) +#define FLEXSPI_MISCCR4_AHBADDRESS_SHIFT (0U) +/*! AHBADDRESS - AHB bus address that trigger the current ECC multi bits error interrupt. + */ +#define FLEXSPI_MISCCR4_AHBADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR4_AHBADDRESS_SHIFT)) & FLEXSPI_MISCCR4_AHBADDRESS_MASK) +/*! @} */ + +/*! @name MISCCR5 - Misc Control Register 5 */ +/*! @{ */ + +#define FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_MASK (0xFFFFFFFFU) +#define FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_SHIFT (0U) +/*! ECCSINGLEERRORCORR - ECC single bit error correction indication. + */ +#define FLEXSPI_MISCCR5_ECCSINGLEERRORCORR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_SHIFT)) & FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_MASK) +/*! @} */ + +/*! @name MISCCR6 - Misc Control Register 6 */ +/*! @{ */ + +#define FLEXSPI_MISCCR6_VALID_MASK (0x1U) +#define FLEXSPI_MISCCR6_VALID_SHIFT (0U) +/*! VALID - ECC single error information Valid + */ +#define FLEXSPI_MISCCR6_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_VALID_SHIFT)) & FLEXSPI_MISCCR6_VALID_MASK) + +#define FLEXSPI_MISCCR6_HIT_MASK (0x2U) +#define FLEXSPI_MISCCR6_HIT_SHIFT (1U) +/*! HIT - ECC single error information Hit + */ +#define FLEXSPI_MISCCR6_HIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_HIT_SHIFT)) & FLEXSPI_MISCCR6_HIT_MASK) + +#define FLEXSPI_MISCCR6_ADDRESS_MASK (0xFFFFFFFCU) +#define FLEXSPI_MISCCR6_ADDRESS_SHIFT (2U) +/*! ADDRESS - ECC single error address + */ +#define FLEXSPI_MISCCR6_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_ADDRESS_SHIFT)) & FLEXSPI_MISCCR6_ADDRESS_MASK) +/*! @} */ + +/*! @name MISCCR7 - Misc Control Register 7 */ +/*! @{ */ + +#define FLEXSPI_MISCCR7_VALID_MASK (0x1U) +#define FLEXSPI_MISCCR7_VALID_SHIFT (0U) +/*! VALID - ECC multi error information Valid + */ +#define FLEXSPI_MISCCR7_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_VALID_SHIFT)) & FLEXSPI_MISCCR7_VALID_MASK) + +#define FLEXSPI_MISCCR7_HIT_MASK (0x2U) +#define FLEXSPI_MISCCR7_HIT_SHIFT (1U) +/*! HIT - ECC multi error information Hit + */ +#define FLEXSPI_MISCCR7_HIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_HIT_SHIFT)) & FLEXSPI_MISCCR7_HIT_MASK) + +#define FLEXSPI_MISCCR7_ADDRESS_MASK (0xFFFFFFFCU) +#define FLEXSPI_MISCCR7_ADDRESS_SHIFT (2U) +/*! ADDRESS - ECC multi error address + */ +#define FLEXSPI_MISCCR7_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_ADDRESS_SHIFT)) & FLEXSPI_MISCCR7_ADDRESS_MASK) +/*! @} */ + /*! @name STS0 - Status Register 0 */ /*! @{ */ + #define FLEXSPI_STS0_SEQIDLE_MASK (0x1U) #define FLEXSPI_STS0_SEQIDLE_SHIFT (0U) /*! SEQIDLE - This status bit indicates the state machine in SEQ_CTL is idle and there is command * sequence executing on FlexSPI interface. */ #define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK) + #define FLEXSPI_STS0_ARBIDLE_MASK (0x2U) #define FLEXSPI_STS0_ARBIDLE_SHIFT (1U) /*! ARBIDLE - This status bit indicates the state machine in ARB_CTL is busy and there is command @@ -42585,6 +51383,7 @@ typedef struct { * this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE. */ #define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK) + #define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU) #define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U) /*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted @@ -42599,12 +51398,14 @@ typedef struct { /*! @name STS1 - Status Register 1 */ /*! @{ */ + #define FLEXSPI_STS1_AHBCMDERRID_MASK (0xFU) #define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U) /*! AHBCMDERRID - Indicates the sequence index when an AHB command error is detected. This field * will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c). */ #define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK) + #define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U) #define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U) /*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be @@ -42617,12 +51418,14 @@ typedef struct { * 0b1110..Sequence execution timeout. */ #define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK) + #define FLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U) #define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U) /*! IPCMDERRID - Indicates the sequence Index when IP command error detected. This field will be * cleared when INTR[IPCMDERR] is write-1-clear(w1c). */ #define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK) + #define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U) #define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U) /*! IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be @@ -42641,41 +51444,49 @@ typedef struct { /*! @name STS2 - Status Register 2 */ /*! @{ */ + #define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U) #define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U) /*! ASLVLOCK - Flash A sample clock slave delay line locked. */ #define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK) + #define FLEXSPI_STS2_AREFLOCK_MASK (0x2U) #define FLEXSPI_STS2_AREFLOCK_SHIFT (1U) /*! AREFLOCK - Flash A sample clock reference delay line locked. */ #define FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK) + #define FLEXSPI_STS2_ASLVSEL_MASK (0xFCU) #define FLEXSPI_STS2_ASLVSEL_SHIFT (2U) /*! ASLVSEL - Flash A sample clock slave delay line delay cell number selection . */ #define FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK) + #define FLEXSPI_STS2_AREFSEL_MASK (0x3F00U) #define FLEXSPI_STS2_AREFSEL_SHIFT (8U) /*! AREFSEL - Flash A sample clock reference delay line delay cell number selection. */ #define FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK) + #define FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U) #define FLEXSPI_STS2_BSLVLOCK_SHIFT (16U) /*! BSLVLOCK - Flash B sample clock slave delay line locked. */ #define FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK) + #define FLEXSPI_STS2_BREFLOCK_MASK (0x20000U) #define FLEXSPI_STS2_BREFLOCK_SHIFT (17U) /*! BREFLOCK - Flash B sample clock reference delay line locked. */ #define FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK) + #define FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U) #define FLEXSPI_STS2_BSLVSEL_SHIFT (18U) /*! BSLVSEL - Flash B sample clock slave delay line delay cell number selection. */ #define FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK) + #define FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U) #define FLEXSPI_STS2_BREFSEL_SHIFT (24U) /*! BREFSEL - Flash B sample clock reference delay line delay cell number selection. @@ -42685,16 +51496,19 @@ typedef struct { /*! @name AHBSPNDSTS - AHB Suspend Status Register */ /*! @{ */ + #define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U) #define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U) /*! ACTIVE - Indicates if an AHB read prefetch command sequence has been suspended. */ #define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK) + #define FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU) #define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U) /*! BUFID - AHB RX BUF ID for suspended command sequence. */ #define FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK) + #define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U) #define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U) /*! DATLFT - Left Data size for suspended command sequence (in byte). @@ -42704,11 +51518,13 @@ typedef struct { /*! @name IPRXFSTS - IP RX FIFO Status Register */ /*! @{ */ + #define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU) #define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U) /*! FILL - Fill level of IP RX FIFO. */ #define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK) + #define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U) #define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U) /*! RDCNTR - Total Read Data Counter: RDCNTR * 64 Bits. @@ -42718,11 +51534,13 @@ typedef struct { /*! @name IPTXFSTS - IP TX FIFO Status Register */ /*! @{ */ + #define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU) #define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U) /*! FILL - Fill level of IP TX FIFO. */ #define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK) + #define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U) #define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U) /*! WRCNTR - Total Write Data Counter: WRCNTR * 64 Bits. @@ -42732,6 +51550,7 @@ typedef struct { /*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */ /*! @{ */ + #define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU) #define FLEXSPI_RFDR_RXDATA_SHIFT (0U) /*! RXDATA - RX Data @@ -42744,6 +51563,7 @@ typedef struct { /*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */ /*! @{ */ + #define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU) #define FLEXSPI_TFDR_TXDATA_SHIFT (0U) /*! TXDATA - TX Data @@ -42756,31 +51576,37 @@ typedef struct { /*! @name LUT - LUT 0..LUT 63 */ /*! @{ */ + #define FLEXSPI_LUT_OPERAND0_MASK (0xFFU) #define FLEXSPI_LUT_OPERAND0_SHIFT (0U) /*! OPERAND0 - OPERAND0 */ #define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK) + #define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U) #define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U) /*! NUM_PADS0 - NUM_PADS0 */ #define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK) + #define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U) #define FLEXSPI_LUT_OPCODE0_SHIFT (10U) /*! OPCODE0 - OPCODE */ #define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK) + #define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U) #define FLEXSPI_LUT_OPERAND1_SHIFT (16U) /*! OPERAND1 - OPERAND1 */ #define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK) + #define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U) #define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U) /*! NUM_PADS1 - NUM_PADS1 */ #define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK) + #define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U) #define FLEXSPI_LUT_OPCODE1_SHIFT (26U) /*! OPCODE1 - OPCODE1 @@ -42791,6 +51617,187 @@ typedef struct { /* The count of FLEXSPI_LUT */ #define FLEXSPI_LUT_COUNT (64U) +/*! @name HMSTRCR - AHB Master ID 0 Control Register..AHB Master ID 7 Control Register */ +/*! @{ */ + +#define FLEXSPI_HMSTRCR_MASK_MASK (0xFFFFU) +#define FLEXSPI_HMSTRCR_MASK_SHIFT (0U) +/*! MASK - Mask bits for AHB master ID. + * 0b0000000000000000..Mask + * 0b0000000000000001..Unmask + */ +#define FLEXSPI_HMSTRCR_MASK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HMSTRCR_MASK_SHIFT)) & FLEXSPI_HMSTRCR_MASK_MASK) + +#define FLEXSPI_HMSTRCR_MSTRID_MASK (0xFFFF0000U) +#define FLEXSPI_HMSTRCR_MSTRID_SHIFT (16U) +/*! MSTRID - This is expected Master ID. + */ +#define FLEXSPI_HMSTRCR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HMSTRCR_MSTRID_SHIFT)) & FLEXSPI_HMSTRCR_MSTRID_MASK) +/*! @} */ + +/* The count of FLEXSPI_HMSTRCR */ +#define FLEXSPI_HMSTRCR_COUNT (8U) + +/*! @name HADDRSTART - HADDR REMAP START ADDR */ +/*! @{ */ + +#define FLEXSPI_HADDRSTART_REMAPEN_MASK (0x1U) +#define FLEXSPI_HADDRSTART_REMAPEN_SHIFT (0U) +/*! REMAPEN + * 0b0..HADDR REMAP Disabled + * 0b1..HADDR REMAP Enabled + */ +#define FLEXSPI_HADDRSTART_REMAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_REMAPEN_SHIFT)) & FLEXSPI_HADDRSTART_REMAPEN_MASK) + +#define FLEXSPI_HADDRSTART_KBINECC_MASK (0x2U) +#define FLEXSPI_HADDRSTART_KBINECC_SHIFT (1U) +/*! KBINECC + * 0b0..If key blob is in remap region, FlexSPI will fetch keyblob at base address + offset + * 0b1..If key blob is in remap region, FlexSPI will fetch keyblob at base address + offset*2 + */ +#define FLEXSPI_HADDRSTART_KBINECC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_KBINECC_SHIFT)) & FLEXSPI_HADDRSTART_KBINECC_MASK) + +#define FLEXSPI_HADDRSTART_ADDRSTART_MASK (0xFFFFF000U) +#define FLEXSPI_HADDRSTART_ADDRSTART_SHIFT (12U) +#define FLEXSPI_HADDRSTART_ADDRSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_ADDRSTART_SHIFT)) & FLEXSPI_HADDRSTART_ADDRSTART_MASK) +/*! @} */ + +/*! @name HADDREND - HADDR REMAP END ADDR */ +/*! @{ */ + +#define FLEXSPI_HADDREND_ENDSTART_MASK (0xFFFFF000U) +#define FLEXSPI_HADDREND_ENDSTART_SHIFT (12U) +#define FLEXSPI_HADDREND_ENDSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDREND_ENDSTART_SHIFT)) & FLEXSPI_HADDREND_ENDSTART_MASK) +/*! @} */ + +/*! @name HADDROFFSET - HADDR REMAP OFFSET */ +/*! @{ */ + +#define FLEXSPI_HADDROFFSET_ADDROFFSET_MASK (0xFFFFF000U) +#define FLEXSPI_HADDROFFSET_ADDROFFSET_SHIFT (12U) +#define FLEXSPI_HADDROFFSET_ADDROFFSET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDROFFSET_ADDROFFSET_SHIFT)) & FLEXSPI_HADDROFFSET_ADDROFFSET_MASK) +/*! @} */ + +/*! @name IPSNSZSTART0 - IPS nonsecure region Start address of region 0 */ +/*! @{ */ + +#define FLEXSPI_IPSNSZSTART0_start_address_MASK (0xFFFFF000U) +#define FLEXSPI_IPSNSZSTART0_start_address_SHIFT (12U) +/*! start_address - Start address of region 0. Minimal 4K Bytes aligned. It is flash address. + */ +#define FLEXSPI_IPSNSZSTART0_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZSTART0_start_address_SHIFT)) & FLEXSPI_IPSNSZSTART0_start_address_MASK) +/*! @} */ + +/*! @name IPSNSZEND0 - IPS nonsecure region End address of region 0 */ +/*! @{ */ + +#define FLEXSPI_IPSNSZEND0_end_address_MASK (0xFFFFF000U) +#define FLEXSPI_IPSNSZEND0_end_address_SHIFT (12U) +/*! end_address - End address of region 0. Minimal 4K Bytes aligned. It is flash address. + */ +#define FLEXSPI_IPSNSZEND0_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZEND0_end_address_SHIFT)) & FLEXSPI_IPSNSZEND0_end_address_MASK) +/*! @} */ + +/*! @name IPSNSZSTART1 - IPS nonsecure region Start address of region 1 */ +/*! @{ */ + +#define FLEXSPI_IPSNSZSTART1_start_address_MASK (0xFFFFF000U) +#define FLEXSPI_IPSNSZSTART1_start_address_SHIFT (12U) +/*! start_address - Start address of region 1. Minimal 4K Bytes aligned. It is flash address. + */ +#define FLEXSPI_IPSNSZSTART1_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZSTART1_start_address_SHIFT)) & FLEXSPI_IPSNSZSTART1_start_address_MASK) +/*! @} */ + +/*! @name IPSNSZEND1 - IPS nonsecure region End address of region 1 */ +/*! @{ */ + +#define FLEXSPI_IPSNSZEND1_end_address_MASK (0xFFFFF000U) +#define FLEXSPI_IPSNSZEND1_end_address_SHIFT (12U) +/*! end_address - End address of region 1. Minimal 4K Bytes aligned. It is flash address. + */ +#define FLEXSPI_IPSNSZEND1_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZEND1_end_address_SHIFT)) & FLEXSPI_IPSNSZEND1_end_address_MASK) +/*! @} */ + +/*! @name AHBBUFREGIONSTART0 - RX BUF Start address of region 0 */ +/*! @{ */ + +#define FLEXSPI_AHBBUFREGIONSTART0_start_address_MASK (0xFFFFF000U) +#define FLEXSPI_AHBBUFREGIONSTART0_start_address_SHIFT (12U) +/*! start_address - Start address of region 0. Minimal 4K Bytes aligned. It is system address. + */ +#define FLEXSPI_AHBBUFREGIONSTART0_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART0_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART0_start_address_MASK) +/*! @} */ + +/*! @name AHBBUFREGIONEND0 - RX BUF region End address of region 0 */ +/*! @{ */ + +#define FLEXSPI_AHBBUFREGIONEND0_end_address_MASK (0xFFFFF000U) +#define FLEXSPI_AHBBUFREGIONEND0_end_address_SHIFT (12U) +/*! end_address - End address of region 0. Minimal 4K Bytes aligned. It is system address. + */ +#define FLEXSPI_AHBBUFREGIONEND0_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND0_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND0_end_address_MASK) +/*! @} */ + +/*! @name AHBBUFREGIONSTART1 - RX BUF Start address of region 1 */ +/*! @{ */ + +#define FLEXSPI_AHBBUFREGIONSTART1_start_address_MASK (0xFFFFF000U) +#define FLEXSPI_AHBBUFREGIONSTART1_start_address_SHIFT (12U) +/*! start_address - Start address of region 1. Minimal 4K Bytes aligned. It is system address. + */ +#define FLEXSPI_AHBBUFREGIONSTART1_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART1_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART1_start_address_MASK) +/*! @} */ + +/*! @name AHBBUFREGIONEND1 - RX BUF region End address of region 1 */ +/*! @{ */ + +#define FLEXSPI_AHBBUFREGIONEND1_end_address_MASK (0xFFFFF000U) +#define FLEXSPI_AHBBUFREGIONEND1_end_address_SHIFT (12U) +/*! end_address - End address of region 1. Minimal 4K Bytes aligned. It is system address. + */ +#define FLEXSPI_AHBBUFREGIONEND1_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND1_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND1_end_address_MASK) +/*! @} */ + +/*! @name AHBBUFREGIONSTART2 - RX BUF Start address of region 2 */ +/*! @{ */ + +#define FLEXSPI_AHBBUFREGIONSTART2_start_address_MASK (0xFFFFF000U) +#define FLEXSPI_AHBBUFREGIONSTART2_start_address_SHIFT (12U) +/*! start_address - Start address of region 2. Minimal 4K Bytes aligned. It is system address. + */ +#define FLEXSPI_AHBBUFREGIONSTART2_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART2_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART2_start_address_MASK) +/*! @} */ + +/*! @name AHBBUFREGIONEND2 - RX BUF region End address of region 2 */ +/*! @{ */ + +#define FLEXSPI_AHBBUFREGIONEND2_end_address_MASK (0xFFFFF000U) +#define FLEXSPI_AHBBUFREGIONEND2_end_address_SHIFT (12U) +/*! end_address - End address of region 2. Minimal 4K Bytes aligned. It is system address. + */ +#define FLEXSPI_AHBBUFREGIONEND2_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND2_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND2_end_address_MASK) +/*! @} */ + +/*! @name AHBBUFREGIONSTART3 - RX BUF Start address of region 3 */ +/*! @{ */ + +#define FLEXSPI_AHBBUFREGIONSTART3_start_address_MASK (0xFFFFF000U) +#define FLEXSPI_AHBBUFREGIONSTART3_start_address_SHIFT (12U) +/*! start_address - Start address of region 3. Minimal 4K Bytes aligned. It is system address. + */ +#define FLEXSPI_AHBBUFREGIONSTART3_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART3_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART3_start_address_MASK) +/*! @} */ + +/*! @name AHBBUFREGIONEND3 - RX BUF region End address of region 3 */ +/*! @{ */ + +#define FLEXSPI_AHBBUFREGIONEND3_end_address_MASK (0xFFFFF000U) +#define FLEXSPI_AHBBUFREGIONEND3_end_address_SHIFT (12U) +/*! end_address - End address of region 3. Minimal 4K Bytes aligned. It is system address. + */ +#define FLEXSPI_AHBBUFREGIONEND3_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND3_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND3_end_address_MASK) +/*! @} */ + /*! * @} @@ -42820,8 +51827,10 @@ typedef struct { #define FlexSPI1_ARDF_BASE (0x2FC00000U) /* Base Address of AHB address space mapped to IP TX FIFO. */ #define FlexSPI1_ATDF_BASE (0x2F800000U) +/* FlexSPI1 alias base address. */ +#define FlexSPI1_ALIAS_BASE (0x8000000U) /* FlexSPI2 AMBA address. */ -#define FlexSPI2_AMBA_BASE (0x60000000U) +#define FlexSPI2_AMBA_BASE (0x60000000U) /* FlexSPI ASFM address. */ #define FlexSPI2_ASFM_BASE (0x60000000U) /* Base Address of AHB address space mapped to IP RX FIFO. */ @@ -42852,8 +51861,7 @@ typedef struct { __IO uint32_t CM_MISC; /**< Miscellaneous, offset: 0xC */ __IO uint32_t CM_MODE_CTRL; /**< CPU mode control, offset: 0x10 */ __I uint32_t CM_MODE_STAT; /**< CM CPU mode Status, offset: 0x14 */ - __I uint32_t CM_PIN_STAT; /**< CM pin Status, offset: 0x18 */ - uint8_t RESERVED_1[228]; + uint8_t RESERVED_1[232]; __IO uint32_t CM_IRQ_WAKEUP_MASK[8]; /**< CM IRQ0~31 wakeup mask..CM IRQ224~255 wakeup mask, array offset: 0x100, array step: 0x4 */ uint8_t RESERVED_2[32]; __IO uint32_t CM_NON_IRQ_WAKEUP_MASK; /**< CM non-irq wakeup mask, offset: 0x140 */ @@ -42863,51 +51871,39 @@ typedef struct { __I uint32_t CM_NON_IRQ_WAKEUP_STAT; /**< CM non-irq wakeup status, offset: 0x190 */ uint8_t RESERVED_5[108]; __IO uint32_t CM_SLEEP_SSAR_CTRL; /**< CM sleep SSAR control, offset: 0x200 */ - __I uint32_t CM_SLEEP_SSAR_STAT; /**< CM sleep SSAR status, offset: 0x204 */ + uint8_t RESERVED_6[4]; __IO uint32_t CM_SLEEP_LPCG_CTRL; /**< CM sleep LPCG control, offset: 0x208 */ - __I uint32_t CM_SLEEP_LPCG_STAT; /**< CM sleep LPCG status, offset: 0x20C */ + uint8_t RESERVED_7[4]; __IO uint32_t CM_SLEEP_PLL_CTRL; /**< CM sleep PLL control, offset: 0x210 */ - __I uint32_t CM_SLEEP_PLL_STAT; /**< CM sleep PLL status, offset: 0x214 */ + uint8_t RESERVED_8[4]; __IO uint32_t CM_SLEEP_ISO_CTRL; /**< CM sleep isolation control, offset: 0x218 */ - __I uint32_t CM_SLEEP_ISO_STAT; /**< CM sleep isolation status, offset: 0x21C */ + uint8_t RESERVED_9[4]; __IO uint32_t CM_SLEEP_RESET_CTRL; /**< CM sleep reset control, offset: 0x220 */ - __I uint32_t CM_SLEEP_RESET_STAT; /**< CM sleep reset status, offset: 0x224 */ + uint8_t RESERVED_10[4]; __IO uint32_t CM_SLEEP_POWER_CTRL; /**< CM sleep power control, offset: 0x228 */ - __I uint32_t CM_SLEEP_POWER_STAT; /**< CM sleep power status, offset: 0x22C */ - uint8_t RESERVED_6[4]; - __I uint32_t CM_SLEEP_SP_STAT; /**< CM sleep set point status, offset: 0x234 */ - uint8_t RESERVED_7[4]; - __I uint32_t CM_SLEEP_STBY_STAT; /**< CM sleep standby status, offset: 0x23C */ - uint8_t RESERVED_8[68]; - __I uint32_t CM_WAKEUP_STBY_STAT; /**< CM wakeup standby status, offset: 0x284 */ - uint8_t RESERVED_9[4]; - __I uint32_t CM_WAKEUP_SP_STAT; /**< CM wakeup set point status, offset: 0x28C */ + uint8_t RESERVED_11[100]; __IO uint32_t CM_WAKEUP_POWER_CTRL; /**< CM wakeup power control, offset: 0x290 */ - __I uint32_t CM_WAKEUP_POWER_STAT; /**< CM wakeup power status, offset: 0x294 */ + uint8_t RESERVED_12[4]; __IO uint32_t CM_WAKEUP_RESET_CTRL; /**< CM wakeup reset control, offset: 0x298 */ - __I uint32_t CM_WAKEUP_RESET_STAT; /**< CM sleep ssar status, offset: 0x29C */ + uint8_t RESERVED_13[4]; __IO uint32_t CM_WAKEUP_ISO_CTRL; /**< CM wakeup isolation control, offset: 0x2A0 */ - __I uint32_t CM_WAKEUP_ISO_STAT; /**< CM wakeup isolation status, offset: 0x2A4 */ + uint8_t RESERVED_14[4]; __IO uint32_t CM_WAKEUP_PLL_CTRL; /**< CM wakeup PLL control, offset: 0x2A8 */ - __I uint32_t CM_WAKEUP_PLL_STAT; /**< CM wakeup PLL status, offset: 0x2AC */ + uint8_t RESERVED_15[4]; __IO uint32_t CM_WAKEUP_LPCG_CTRL; /**< CM wakeup LPCG control, offset: 0x2B0 */ - __I uint32_t CM_WAKEUP_LPCG_STAT; /**< CM wakeup LPCG status, offset: 0x2B4 */ + uint8_t RESERVED_16[4]; __IO uint32_t CM_WAKEUP_SSAR_CTRL; /**< CM wakeup SSAR control, offset: 0x2B8 */ - __I uint32_t CM_WAKEUP_SSAR_STAT; /**< CM wakeup SSAR status, offset: 0x2BC */ - uint8_t RESERVED_10[60]; - __I uint32_t CM_SOFT_SP_STAT; /**< CM software set point status, offset: 0x2FC */ - __IO uint32_t CM_SP_CTRL; /**< CM Set Point Control, offset: 0x300 */ - __I uint32_t CM_SP_STAT; /**< CM Set Point Status, offset: 0x304 */ - uint8_t RESERVED_11[8]; - __IO uint32_t CM_RUN_MODE_MAPPING; /**< CM Run Mode Set Point Allowed, offset: 0x310 */ - __IO uint32_t CM_WAIT_MODE_MAPPING; /**< CM Wait Mode Set Point Allowed, offset: 0x314 */ - __IO uint32_t CM_STOP_MODE_MAPPING; /**< CM Stop Mode Set Point Allowed, offset: 0x318 */ - __IO uint32_t CM_SUSPEND_MODE_MAPPING; /**< CM Suspend Mode Set Point Allowed, offset: 0x31C */ - __IO uint32_t CM_SP_MAPPING[16]; /**< CM Set Point 0 Mapping..CM Set Point 15 Mapping, array offset: 0x320, array step: 0x4 */ - uint8_t RESERVED_12[32]; + uint8_t RESERVED_17[68]; + __IO uint32_t CM_SP_CTRL; /**< CM Setpoint Control, offset: 0x300 */ + __I uint32_t CM_SP_STAT; /**< CM Setpoint Status, offset: 0x304 */ + uint8_t RESERVED_18[8]; + __IO uint32_t CM_RUN_MODE_MAPPING; /**< CM Run Mode Setpoint Allowed, offset: 0x310 */ + __IO uint32_t CM_WAIT_MODE_MAPPING; /**< CM Wait Mode Setpoint Allowed, offset: 0x314 */ + __IO uint32_t CM_STOP_MODE_MAPPING; /**< CM Stop Mode Setpoint Allowed, offset: 0x318 */ + __IO uint32_t CM_SUSPEND_MODE_MAPPING; /**< CM Suspend Mode Setpoint Allowed, offset: 0x31C */ + __IO uint32_t CM_SP_MAPPING[16]; /**< CM Setpoint 0 Mapping..CM Setpoint 15 Mapping, array offset: 0x320, array step: 0x4 */ + uint8_t RESERVED_19[32]; __IO uint32_t CM_STBY_CTRL; /**< CM standby control, offset: 0x380 */ - uint8_t RESERVED_13[12]; - __IO uint32_t CM_DEBUG; /**< CM debug, offset: 0x390 */ } GPC_CPU_MODE_CTRL_Type; /* ---------------------------------------------------------------------------- @@ -42921,31 +51917,41 @@ typedef struct { /*! @name CM_AUTHEN_CTRL - CM Authentication Control */ /*! @{ */ + #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER_MASK (0x1U) #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER_SHIFT (0U) /*! USER - Allow user mode access + * 0b0..Allow only privilege mode to access CPU mode control registers + * 0b1..Allow both privilege and user mode to access CPU mode control registers */ #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER_MASK) + #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE_MASK (0x2U) #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE_SHIFT (1U) /*! NONSECURE - Allow non-secure mode access + * 0b0..Allow only secure mode to access CPU mode control registers + * 0b1..Allow both secure and non-secure mode to access CPU mode control registers */ #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE_MASK) + #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U) #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U) /*! LOCK_SETTING - Lock NONSECURE and USER */ #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_MASK) + #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U) #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U) /*! WHITE_LIST - Domain ID white list */ #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_MASK) + #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_MASK (0x1000U) #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U) /*! LOCK_LIST - White list lock */ #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_MASK) + #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U) #define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U) /*! LOCK_CFG - Configuration lock @@ -42955,31 +51961,43 @@ typedef struct { /*! @name CM_INT_CTRL - CM Interrupt Control */ /*! @{ */ + #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN_MASK (0x1U) #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN_SHIFT (0U) /*! SP_REQ_NOT_ALLOWED_SLEEP_INT_EN - sp_req_not_allowed_for_sleep interrupt enable + * 0b0..Interrupt disable + * 0b1..Interrupt enable */ #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN_MASK) + #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN_MASK (0x2U) #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN_SHIFT (1U) /*! SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN - sp_req_not_allowed_for_wakeup interrupt enable + * 0b0..Interrupt disable + * 0b1..Interrupt enable */ #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN_MASK) + #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN_MASK (0x4U) #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN_SHIFT (2U) /*! SP_REQ_NOT_ALLOWED_SOFT_INT_EN - sp_req_not_allowed_for_soft interrupt enable + * 0b0..Interrupt disable + * 0b1..Interrupt enable */ #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN_MASK) + #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_MASK (0x10000U) #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_SHIFT (16U) /*! SP_REQ_NOT_ALLOWED_SLEEP_INT - sp_req_not_allowed_for_sleep interrupt status and clear register */ #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_MASK) + #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_MASK (0x20000U) #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_SHIFT (17U) /*! SP_REQ_NOT_ALLOWED_WAKEUP_INT - sp_req_not_allowed_for_wakeup interrupt status and clear register */ #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_MASK) + #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_MASK (0x40000U) #define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_SHIFT (18U) /*! SP_REQ_NOT_ALLOWED_SOFT_INT - sp_req_not_allowed_for_soft interrupt status and clear register @@ -42989,21 +52007,29 @@ typedef struct { /*! @name CM_MISC - Miscellaneous */ /*! @{ */ + #define GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT_MASK (0x1U) #define GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT_SHIFT (0U) /*! NMI_STAT - Non-masked interrupt status + * 0b0..NMI is not asserting + * 0b1..NMI is asserting */ #define GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT_MASK) + #define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_MASK (0x2U) #define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_SHIFT (1U) /*! SLEEP_HOLD_EN - Allow cpu_sleep_hold_req assert during CPU low power status + * 0b0..Disable cpu_sleep_hold_req + * 0b1..Allow cpu_sleep_hold_req assert during CPU low power status */ #define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_MASK) + #define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT_MASK (0x4U) #define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT_SHIFT (2U) /*! SLEEP_HOLD_STAT - Status of cpu_sleep_hold_ack_b */ #define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT_MASK) + #define GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU_MASK (0x10U) #define GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU_SHIFT (4U) /*! MASTER_CPU - Master CPU @@ -43013,6 +52039,7 @@ typedef struct { /*! @name CM_MODE_CTRL - CPU mode control */ /*! @{ */ + #define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_MASK (0x3U) #define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_SHIFT (0U) /*! CPU_MODE_TARGET - The CPU mode the CPU platform should transit to on next sleep event @@ -43022,203 +52049,85 @@ typedef struct { * 0b11..Transit to SUSPEND mode */ #define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_MASK) + #define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN_MASK (0x10U) #define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN_SHIFT (4U) /*! WFE_EN - WFE assertion can be sleep event + * 0b0..WFE assertion can not trigger low power + * 0b1..WFE assertion can trigger low power */ #define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN_MASK) /*! @} */ /*! @name CM_MODE_STAT - CM CPU mode Status */ /*! @{ */ + #define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_MASK (0x3U) #define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_SHIFT (0U) /*! CPU_MODE_CURRENT - Current CPU mode + * 0b00..CPU is currently in RUN mode + * 0b01..CPU is currently in WAIT mode + * 0b10..CPU is currently in STOP mode + * 0b11..CPU is currently in SUSPEND mode */ #define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_MASK) + #define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_MASK (0xCU) #define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_SHIFT (2U) /*! CPU_MODE_PREVIOUS - Previous CPU mode + * 0b00..CPU was previously in RUN mode + * 0b01..CPU was previously in WAIT mode + * 0b10..CPU was previously in STOP mode + * 0b11..CPU was previously in SUSPEND mode */ #define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_MASK) -#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_SLEEP_TRANS_BUSY_MASK (0x100U) -#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_SLEEP_TRANS_BUSY_SHIFT (8U) -/*! SLEEP_TRANS_BUSY - Busy on CPU mode transition of sleep, not include set point trans busy. - */ -#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_SLEEP_TRANS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_STAT_SLEEP_TRANS_BUSY_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_STAT_SLEEP_TRANS_BUSY_MASK) -#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_WAKEUP_TRANS_BUSY_MASK (0x200U) -#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_WAKEUP_TRANS_BUSY_SHIFT (9U) -/*! WAKEUP_TRANS_BUSY - Busy on CPU mode transition of wakeup, not include set point trans busy. - */ -#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_WAKEUP_TRANS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_STAT_WAKEUP_TRANS_BUSY_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_STAT_WAKEUP_TRANS_BUSY_MASK) -#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_SLEEPING_IDLE_MASK (0x400U) -#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_SLEEPING_IDLE_SHIFT (10U) -/*! SLEEPING_IDLE - Completed CPU mode and set point transition of sleep sequence, in a sleeping_idle state. - */ -#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_SLEEPING_IDLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_STAT_SLEEPING_IDLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_STAT_SLEEPING_IDLE_MASK) -#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_SLEEP_REQUEST_MASK (0x10000U) -#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_SLEEP_REQUEST_SHIFT (16U) -/*! SLEEP_REQUEST - Status of sleep_request input port - */ -#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_SLEEP_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_STAT_SLEEP_REQUEST_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_STAT_SLEEP_REQUEST_MASK) -#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_WFE_REQUEST_MASK (0x20000U) -#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_WFE_REQUEST_SHIFT (17U) -/*! WFE_REQUEST - Status of standby_wfe input port - */ -#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_WFE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_STAT_WFE_REQUEST_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_STAT_WFE_REQUEST_MASK) -#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_WAKEUP_REQUEST_MASK (0x40000U) -#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_WAKEUP_REQUEST_SHIFT (18U) -/*! WAKEUP_REQUEST - "ORed" of all unmasked IRQ in. - */ -#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_WAKEUP_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_STAT_WAKEUP_REQUEST_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_STAT_WAKEUP_REQUEST_MASK) -#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_FSM_STATE_MASK (0x1F000000U) -#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_FSM_STATE_SHIFT (24U) -/*! FSM_STATE - CPU mode trans FSM state. - */ -#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_FSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_STAT_FSM_STATE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_STAT_FSM_STATE_MASK) -/*! @} */ - -/*! @name CM_PIN_STAT - CM pin Status */ -/*! @{ */ -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_SSAR_REQUEST_STAT_MASK (0x1U) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_SSAR_REQUEST_STAT_SHIFT (0U) -/*! SSAR_REQUEST_STAT - cpu_mode_trans_ssar_request pin status - */ -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_SSAR_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_PIN_STAT_SSAR_REQUEST_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_PIN_STAT_SSAR_REQUEST_STAT_MASK) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_LPCG_REQUEST_STAT_MASK (0x2U) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_LPCG_REQUEST_STAT_SHIFT (1U) -/*! LPCG_REQUEST_STAT - cpu_mode_trans_lpcg_request pin status - */ -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_LPCG_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_PIN_STAT_LPCG_REQUEST_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_PIN_STAT_LPCG_REQUEST_STAT_MASK) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_PLL_REQUEST_STAT_MASK (0x4U) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_PLL_REQUEST_STAT_SHIFT (2U) -/*! PLL_REQUEST_STAT - cpu_mode_trans_pll_request pin status - */ -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_PLL_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_PIN_STAT_PLL_REQUEST_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_PIN_STAT_PLL_REQUEST_STAT_MASK) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_ISO_REQUEST_STAT_MASK (0x8U) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_ISO_REQUEST_STAT_SHIFT (3U) -/*! ISO_REQUEST_STAT - cpu_mode_trans_iso_request pin status - */ -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_ISO_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_PIN_STAT_ISO_REQUEST_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_PIN_STAT_ISO_REQUEST_STAT_MASK) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_RESET_REQUEST_STAT_MASK (0x10U) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_RESET_REQUEST_STAT_SHIFT (4U) -/*! RESET_REQUEST_STAT - cpu_mode_trans_reset_request pin status - */ -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_RESET_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_PIN_STAT_RESET_REQUEST_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_PIN_STAT_RESET_REQUEST_STAT_MASK) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_POWER_REQUEST_STAT_MASK (0x20U) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_POWER_REQUEST_STAT_SHIFT (5U) -/*! POWER_REQUEST_STAT - cpu_mode_trans_power_request pin status - */ -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_POWER_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_PIN_STAT_POWER_REQUEST_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_PIN_STAT_POWER_REQUEST_STAT_MASK) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_SP_REQUEST_STAT_MASK (0x40U) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_SP_REQUEST_STAT_SHIFT (6U) -/*! SP_REQUEST_STAT - cpu_mode_trans_sp_request pin status - */ -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_SP_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_PIN_STAT_SP_REQUEST_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_PIN_STAT_SP_REQUEST_STAT_MASK) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_STBY_IN_REQUEST_STAT_MASK (0x80U) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_STBY_IN_REQUEST_STAT_SHIFT (7U) -/*! STBY_IN_REQUEST_STAT - cpu_mode_trans_stby_in_request pin status - */ -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_STBY_IN_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_PIN_STAT_STBY_IN_REQUEST_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_PIN_STAT_STBY_IN_REQUEST_STAT_MASK) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_STBY_OUT_REQUEST_STAT_MASK (0x100U) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_STBY_OUT_REQUEST_STAT_SHIFT (8U) -/*! STBY_OUT_REQUEST_STAT - cpu_mode_trans_stby_out_request pin status - */ -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_STBY_OUT_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_PIN_STAT_STBY_OUT_REQUEST_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_PIN_STAT_STBY_OUT_REQUEST_STAT_MASK) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_SSAR_DONE_STAT_MASK (0x200U) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_SSAR_DONE_STAT_SHIFT (9U) -/*! SSAR_DONE_STAT - cpu_mode_trans_ssar_done pin status - */ -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_SSAR_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_PIN_STAT_SSAR_DONE_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_PIN_STAT_SSAR_DONE_STAT_MASK) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_LPCG_DONE_STAT_MASK (0x400U) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_LPCG_DONE_STAT_SHIFT (10U) -/*! LPCG_DONE_STAT - cpu_mode_trans_lpcg_done pin status - */ -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_LPCG_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_PIN_STAT_LPCG_DONE_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_PIN_STAT_LPCG_DONE_STAT_MASK) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_PLL_DONE_STAT_MASK (0x800U) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_PLL_DONE_STAT_SHIFT (11U) -/*! PLL_DONE_STAT - cpu_mode_trans_pll_done pin status - */ -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_PLL_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_PIN_STAT_PLL_DONE_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_PIN_STAT_PLL_DONE_STAT_MASK) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_ISO_DONE_STAT_MASK (0x1000U) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_ISO_DONE_STAT_SHIFT (12U) -/*! ISO_DONE_STAT - cpu_mode_trans_iso_done pin status - */ -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_ISO_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_PIN_STAT_ISO_DONE_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_PIN_STAT_ISO_DONE_STAT_MASK) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_RESET_DONE_STAT_MASK (0x2000U) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_RESET_DONE_STAT_SHIFT (13U) -/*! RESET_DONE_STAT - cpu_mode_trans_reset_done pin status - */ -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_RESET_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_PIN_STAT_RESET_DONE_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_PIN_STAT_RESET_DONE_STAT_MASK) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_POWER_DONE_STAT_MASK (0x4000U) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_POWER_DONE_STAT_SHIFT (14U) -/*! POWER_DONE_STAT - cpu_mode_trans_power_done pin status - */ -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_POWER_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_PIN_STAT_POWER_DONE_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_PIN_STAT_POWER_DONE_STAT_MASK) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_SP_DONE_STAT_MASK (0x8000U) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_SP_DONE_STAT_SHIFT (15U) -/*! SP_DONE_STAT - cpu_mode_trans_sp_done pin status - */ -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_SP_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_PIN_STAT_SP_DONE_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_PIN_STAT_SP_DONE_STAT_MASK) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_STBY_IN_DONE_STAT_MASK (0x10000U) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_STBY_IN_DONE_STAT_SHIFT (16U) -/*! STBY_IN_DONE_STAT - cpu_mode_trans_stby_in_done pin status - */ -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_STBY_IN_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_PIN_STAT_STBY_IN_DONE_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_PIN_STAT_STBY_IN_DONE_STAT_MASK) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_STBY_OUT_DONE_STAT_MASK (0x20000U) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_STBY_OUT_DONE_STAT_SHIFT (17U) -/*! STBY_OUT_DONE_STAT - cpu_mode_trans_stby_out_done pin status - */ -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_STBY_OUT_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_PIN_STAT_STBY_OUT_DONE_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_PIN_STAT_STBY_OUT_DONE_STAT_MASK) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_CPU_MODE_STAT_MASK (0xC0000U) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_CPU_MODE_STAT_SHIFT (18U) -/*! CPU_MODE_STAT - cpu_power_mode pin status - */ -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_CPU_MODE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_PIN_STAT_CPU_MODE_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_PIN_STAT_CPU_MODE_STAT_MASK) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_DEBUG_WAKEUP_ACK_STAT_MASK (0x100000U) -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_DEBUG_WAKEUP_ACK_STAT_SHIFT (20U) -/*! DEBUG_WAKEUP_ACK_STAT - debug wakeup acknowledge pin status - */ -#define GPC_CPU_MODE_CTRL_CM_PIN_STAT_DEBUG_WAKEUP_ACK_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_PIN_STAT_DEBUG_WAKEUP_ACK_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_PIN_STAT_DEBUG_WAKEUP_ACK_STAT_MASK) /*! @} */ /*! @name CM_IRQ_WAKEUP_MASK - CM IRQ0~31 wakeup mask..CM IRQ224~255 wakeup mask */ /*! @{ */ + #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31_MASK (0xFFFFFFFFU) #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31_SHIFT (0U) /*! IRQ_WAKEUP_MASK_0_31 - "1" means the IRQ cannot wakeup CPU platform */ #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31_MASK) + #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63_MASK (0xFFFFFFFFU) #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63_SHIFT (0U) /*! IRQ_WAKEUP_MASK_32_63 - "1" means the IRQ cannot wakeup CPU platform */ #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63_MASK) + #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95_MASK (0xFFFFFFFFU) #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95_SHIFT (0U) /*! IRQ_WAKEUP_MASK_64_95 - "1" means the IRQ cannot wakeup CPU platform */ #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95_MASK) + #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127_MASK (0xFFFFFFFFU) #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127_SHIFT (0U) /*! IRQ_WAKEUP_MASK_96_127 - "1" means the IRQ cannot wakeup CPU platform */ #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127_MASK) + #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159_MASK (0xFFFFFFFFU) #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159_SHIFT (0U) /*! IRQ_WAKEUP_MASK_128_159 - "1" means the IRQ cannot wakeup CPU platform */ #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159_MASK) + #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191_MASK (0xFFFFFFFFU) #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191_SHIFT (0U) /*! IRQ_WAKEUP_MASK_160_191 - "1" means the IRQ cannot wakeup CPU platform */ #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191_MASK) + #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223_MASK (0xFFFFFFFFU) #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223_SHIFT (0U) /*! IRQ_WAKEUP_MASK_192_223 - "1" means the IRQ cannot wakeup CPU platform */ #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223_MASK) + #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255_MASK (0xFFFFFFFFU) #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255_SHIFT (0U) /*! IRQ_WAKEUP_MASK_224_255 - "1" means the IRQ cannot wakeup CPU platform @@ -43231,11 +52140,14 @@ typedef struct { /*! @name CM_NON_IRQ_WAKEUP_MASK - CM non-irq wakeup mask */ /*! @{ */ + #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_MASK (0x1U) #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_SHIFT (0U) -/*! EVENT_WAKEUP_MASK - "1" means the event cannot wakeup CPU platform +/*! EVENT_WAKEUP_MASK - There are 256 interrupts and 1 event as a wakeup source for GPC. This field masks the 1 event wakeup source. + * 0b1..The event cannot wakeup CPU platform */ #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_SHIFT)) & GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_MASK) + #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_MASK (0x2U) #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_SHIFT (1U) /*! DEBUG_WAKEUP_MASK - "1" means the debug_wakeup_request cannot wakeup CPU platform @@ -43245,44 +52157,68 @@ typedef struct { /*! @name CM_IRQ_WAKEUP_STAT - CM IRQ0~31 wakeup status..CM IRQ224~255 wakeup status */ /*! @{ */ + #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255_MASK (0xFFFFFFFFU) #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255_SHIFT (0U) /*! IRQ_WAKEUP_MASK_224_255 - IRQ status + * 0b00000000000000000000000000000000..None + * 0b00000000000000000000000000000001..Valid */ #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255_MASK) + #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31_MASK (0xFFFFFFFFU) #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31_SHIFT (0U) /*! IRQ_WAKEUP_STAT_0_31 - IRQ status + * 0b00000000000000000000000000000000..None + * 0b00000000000000000000000000000001..Valid */ #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31_MASK) + #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63_MASK (0xFFFFFFFFU) #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63_SHIFT (0U) /*! IRQ_WAKEUP_STAT_32_63 - IRQ status + * 0b00000000000000000000000000000000..None + * 0b00000000000000000000000000000001..Valid */ #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63_MASK) + #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95_MASK (0xFFFFFFFFU) #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95_SHIFT (0U) /*! IRQ_WAKEUP_STAT_64_95 - IRQ status + * 0b00000000000000000000000000000000..None + * 0b00000000000000000000000000000001..Valid */ #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95_MASK) + #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127_MASK (0xFFFFFFFFU) #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127_SHIFT (0U) /*! IRQ_WAKEUP_STAT_96_127 - IRQ status + * 0b00000000000000000000000000000000..None + * 0b00000000000000000000000000000001..Valid */ #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127_MASK) + #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159_MASK (0xFFFFFFFFU) #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159_SHIFT (0U) /*! IRQ_WAKEUP_STAT_128_159 - IRQ status + * 0b00000000000000000000000000000000..None + * 0b00000000000000000000000000000001..Valid */ #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159_MASK) + #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191_MASK (0xFFFFFFFFU) #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191_SHIFT (0U) /*! IRQ_WAKEUP_STAT_160_191 - IRQ status + * 0b00000000000000000000000000000000..None + * 0b00000000000000000000000000000001..Valid */ #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191_MASK) + #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223_MASK (0xFFFFFFFFU) #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223_SHIFT (0U) /*! IRQ_WAKEUP_STAT_192_223 - IRQ status + * 0b00000000000000000000000000000000..None + * 0b00000000000000000000000000000001..Valid */ #define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223_MASK) /*! @} */ @@ -43292,11 +52228,14 @@ typedef struct { /*! @name CM_NON_IRQ_WAKEUP_STAT - CM non-irq wakeup status */ /*! @{ */ + #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_MASK (0x1U) #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_SHIFT (0U) /*! EVENT_WAKEUP_STAT - Event wakeup status + * 0b1..Interrupt is asserting (pending) */ #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_MASK) + #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_MASK (0x2U) #define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_SHIFT (1U) /*! DEBUG_WAKEUP_STAT - Debug wakeup status @@ -43306,11 +52245,13 @@ typedef struct { /*! @name CM_SLEEP_SSAR_CTRL - CM sleep SSAR control */ /*! @{ */ + #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE. */ #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_MASK) + #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -43320,6 +52261,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_MASK) + #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_MASK (0x80000000U) #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -43327,22 +52269,15 @@ typedef struct { #define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_MASK) /*! @} */ -/*! @name CM_SLEEP_SSAR_STAT - CM sleep SSAR status */ -/*! @{ */ -#define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_STAT_RSP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name CM_SLEEP_LPCG_CTRL - CM sleep LPCG control */ /*! @{ */ + #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_MASK) + #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -43352,6 +52287,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_MASK) + #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_MASK (0x80000000U) #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -43359,22 +52295,15 @@ typedef struct { #define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_MASK) /*! @} */ -/*! @name CM_SLEEP_LPCG_STAT - CM sleep LPCG status */ -/*! @{ */ -#define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_STAT_RSP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name CM_SLEEP_PLL_CTRL - CM sleep PLL control */ /*! @{ */ + #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_MASK) + #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -43384,6 +52313,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_MASK) + #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_MASK (0x80000000U) #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -43391,22 +52321,15 @@ typedef struct { #define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_MASK) /*! @} */ -/*! @name CM_SLEEP_PLL_STAT - CM sleep PLL status */ -/*! @{ */ -#define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_STAT_RSP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name CM_SLEEP_ISO_CTRL - CM sleep isolation control */ /*! @{ */ + #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_MASK) + #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -43416,6 +52339,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_MASK) + #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_MASK (0x80000000U) #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -43423,22 +52347,15 @@ typedef struct { #define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_MASK) /*! @} */ -/*! @name CM_SLEEP_ISO_STAT - CM sleep isolation status */ -/*! @{ */ -#define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_STAT_RSP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name CM_SLEEP_RESET_CTRL - CM sleep reset control */ /*! @{ */ + #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_MASK) + #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -43448,6 +52365,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_MASK) + #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_MASK (0x80000000U) #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -43455,22 +52373,15 @@ typedef struct { #define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_MASK) /*! @} */ -/*! @name CM_SLEEP_RESET_STAT - CM sleep reset status */ -/*! @{ */ -#define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_STAT_RSP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name CM_SLEEP_POWER_CTRL - CM sleep power control */ /*! @{ */ + #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_MASK) + #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -43480,6 +52391,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_MASK) + #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_MASK (0x80000000U) #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -43487,58 +52399,15 @@ typedef struct { #define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_MASK) /*! @} */ -/*! @name CM_SLEEP_POWER_STAT - CM sleep power status */ -/*! @{ */ -#define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_STAT_RSP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_STAT_RSP_CNT_MASK) -/*! @} */ - -/*! @name CM_SLEEP_SP_STAT - CM sleep set point status */ -/*! @{ */ -#define GPC_CPU_MODE_CTRL_CM_SLEEP_SP_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_CPU_MODE_CTRL_CM_SLEEP_SP_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_CPU_MODE_CTRL_CM_SLEEP_SP_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_SP_STAT_RSP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_SP_STAT_RSP_CNT_MASK) -/*! @} */ - -/*! @name CM_SLEEP_STBY_STAT - CM sleep standby status */ -/*! @{ */ -#define GPC_CPU_MODE_CTRL_CM_SLEEP_STBY_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_CPU_MODE_CTRL_CM_SLEEP_STBY_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_CPU_MODE_CTRL_CM_SLEEP_STBY_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_STBY_STAT_RSP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_STBY_STAT_RSP_CNT_MASK) -/*! @} */ - -/*! @name CM_WAKEUP_STBY_STAT - CM wakeup standby status */ -/*! @{ */ -#define GPC_CPU_MODE_CTRL_CM_WAKEUP_STBY_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_CPU_MODE_CTRL_CM_WAKEUP_STBY_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_CPU_MODE_CTRL_CM_WAKEUP_STBY_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_STBY_STAT_RSP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_STBY_STAT_RSP_CNT_MASK) -/*! @} */ - -/*! @name CM_WAKEUP_SP_STAT - CM wakeup set point status */ -/*! @{ */ -#define GPC_CPU_MODE_CTRL_CM_WAKEUP_SP_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_CPU_MODE_CTRL_CM_WAKEUP_SP_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_CPU_MODE_CTRL_CM_WAKEUP_SP_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_SP_STAT_RSP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_SP_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name CM_WAKEUP_POWER_CTRL - CM wakeup power control */ /*! @{ */ + #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_MASK) + #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -43548,6 +52417,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_MASK) + #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_MASK (0x80000000U) #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -43555,22 +52425,15 @@ typedef struct { #define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_MASK) /*! @} */ -/*! @name CM_WAKEUP_POWER_STAT - CM wakeup power status */ -/*! @{ */ -#define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_STAT_RSP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name CM_WAKEUP_RESET_CTRL - CM wakeup reset control */ /*! @{ */ + #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_MASK) + #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -43580,6 +52443,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_MASK) + #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_MASK (0x80000000U) #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -43587,22 +52451,15 @@ typedef struct { #define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_MASK) /*! @} */ -/*! @name CM_WAKEUP_RESET_STAT - CM sleep ssar status */ -/*! @{ */ -#define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_STAT_RSP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name CM_WAKEUP_ISO_CTRL - CM wakeup isolation control */ /*! @{ */ + #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_MASK) + #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -43612,6 +52469,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_MASK) + #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_MASK (0x80000000U) #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -43619,22 +52477,15 @@ typedef struct { #define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_MASK) /*! @} */ -/*! @name CM_WAKEUP_ISO_STAT - CM wakeup isolation status */ -/*! @{ */ -#define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_STAT_RSP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name CM_WAKEUP_PLL_CTRL - CM wakeup PLL control */ /*! @{ */ + #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_MASK) + #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -43644,6 +52495,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_MASK) + #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_MASK (0x80000000U) #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -43651,22 +52503,15 @@ typedef struct { #define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_MASK) /*! @} */ -/*! @name CM_WAKEUP_PLL_STAT - CM wakeup PLL status */ -/*! @{ */ -#define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_STAT_RSP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name CM_WAKEUP_LPCG_CTRL - CM wakeup LPCG control */ /*! @{ */ + #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_MASK) + #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -43676,6 +52521,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_MASK) + #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_MASK (0x80000000U) #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -43683,22 +52529,15 @@ typedef struct { #define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_MASK) /*! @} */ -/*! @name CM_WAKEUP_LPCG_STAT - CM wakeup LPCG status */ -/*! @{ */ -#define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_STAT_RSP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name CM_WAKEUP_SSAR_CTRL - CM wakeup SSAR control */ /*! @{ */ + #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_MASK) + #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -43708,6 +52547,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_MASK) + #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_MASK (0x80000000U) #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -43715,218 +52555,209 @@ typedef struct { #define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_MASK) /*! @} */ -/*! @name CM_WAKEUP_SSAR_STAT - CM wakeup SSAR status */ -/*! @{ */ -#define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_STAT_RSP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_STAT_RSP_CNT_MASK) -/*! @} */ - -/*! @name CM_SOFT_SP_STAT - CM software set point status */ +/*! @name CM_SP_CTRL - CM Setpoint Control */ /*! @{ */ -#define GPC_CPU_MODE_CTRL_CM_SOFT_SP_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_CPU_MODE_CTRL_CM_SOFT_SP_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_CPU_MODE_CTRL_CM_SOFT_SP_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SOFT_SP_STAT_RSP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SOFT_SP_STAT_RSP_CNT_MASK) -/*! @} */ -/*! @name CM_SP_CTRL - CM Set Point Control */ -/*! @{ */ #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_MASK (0x1U) #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_SHIFT (0U) -/*! CPU_SP_RUN_EN - Request a set point transition when this bit is set +/*! CPU_SP_RUN_EN - Request a Setpoint transition when this bit is set */ #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_MASK) + #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_MASK (0x1EU) #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_SHIFT (1U) -/*! CPU_SP_RUN - The set point CPU want the system to transit to when CPU_SP_RUN_EN is set +/*! CPU_SP_RUN - The Setpoint that CPU want the system to transit to when CPU_SP_RUN_EN is set */ #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_MASK) + #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_MASK (0x20U) #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_SHIFT (5U) -/*! CPU_SP_SLEEP_EN - Enable set point transition on next CPU platform sleep sequence +/*! CPU_SP_SLEEP_EN - 1 means enable Setpoint transition on next CPU platform sleep sequence */ #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_MASK) + #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_MASK (0x3C0U) #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_SHIFT (6U) -/*! CPU_SP_SLEEP - The set point CPU want the system to transit to on next CPU platform sleep sequence +/*! CPU_SP_SLEEP - The Setpoint that CPU want the system to transit to on next CPU platform sleep sequence */ #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_MASK) + #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_MASK (0x400U) #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_SHIFT (10U) -/*! CPU_SP_WAKEUP_EN - Enable set point transition on next CPU platform wakeup sequence +/*! CPU_SP_WAKEUP_EN - 1 means enable Setpoint transition on next CPU platform wakeup sequence */ #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_MASK) + #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_MASK (0x7800U) #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SHIFT (11U) -/*! CPU_SP_WAKEUP - The set point CPU want the system to transit to on next CPU platform wakeup sequence +/*! CPU_SP_WAKEUP - The Setpoint that CPU want the system to transit to on next CPU platform wakeup sequence */ #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_MASK) + #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_MASK (0x8000U) #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_SHIFT (15U) -/*! CPU_SP_WAKEUP_SEL - Select the set point transiton on the next CPU platform wakeup sequence +/*! CPU_SP_WAKEUP_SEL - Select the Setpoint transiton on the next CPU platform wakeup sequence * 0b0..Request SP transition to CPU_SP_WAKEUP - * 0b1..Request SP transition to the set point when the sleep event happens, which is captured in CPU_SP_PREVIOUS + * 0b1..Request SP transition to the Setpoint when the sleep event happens, which is captured in CPU_SP_PREVIOUS */ #define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_MASK) /*! @} */ -/*! @name CM_SP_STAT - CM Set Point Status */ +/*! @name CM_SP_STAT - CM Setpoint Status */ /*! @{ */ + #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_MASK (0xFU) #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_SHIFT (0U) -/*! CPU_SP_CURRENT - The current set point of the system +/*! CPU_SP_CURRENT - The current Setpoint of the system */ #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_MASK) + #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS_MASK (0xF0U) #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS_SHIFT (4U) -/*! CPU_SP_PREVIOUS - The previous set point of the system +/*! CPU_SP_PREVIOUS - The previous Setpoint of the system */ #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS_MASK) + #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET_MASK (0xF00U) #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET_SHIFT (8U) -/*! CPU_SP_TARGET - The requested set point from the CPU platform +/*! CPU_SP_TARGET - The requested Setpoint from the CPU platform */ #define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET_MASK) -#define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CHANGE_REQ_MASK (0x1000U) -#define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CHANGE_REQ_SHIFT (12U) -/*! CPU_SP_CHANGE_REQ - The set point change request from the CPU platform - */ -#define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CHANGE_REQ(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CHANGE_REQ_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CHANGE_REQ_MASK) -#define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_SLEEP_BUSY_MASK (0x2000U) -#define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_SLEEP_BUSY_SHIFT (13U) -/*! CPU_SP_SLEEP_BUSY - Indicate busy on set point transition of sleep sequence - */ -#define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_SLEEP_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_SLEEP_BUSY_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_SLEEP_BUSY_MASK) -#define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_WAKEUP_BUSY_MASK (0x4000U) -#define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_WAKEUP_BUSY_SHIFT (14U) -/*! CPU_SP_WAKEUP_BUSY - Indicate busy on set point transition of wakeup sequence - */ -#define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_WAKEUP_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_WAKEUP_BUSY_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_WAKEUP_BUSY_MASK) -#define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_SOFT_BUSY_MASK (0x8000U) -#define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_SOFT_BUSY_SHIFT (15U) -/*! CPU_SP_SOFT_BUSY - Indicate busy on set point transition of software trigger - */ -#define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_SOFT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_SOFT_BUSY_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_SOFT_BUSY_MASK) /*! @} */ -/*! @name CM_RUN_MODE_MAPPING - CM Run Mode Set Point Allowed */ +/*! @name CM_RUN_MODE_MAPPING - CM Run Mode Setpoint Allowed */ /*! @{ */ + #define GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING_SHIFT (0U) -/*! CPU_RUN_MODE_MAPPING - Defines which set point is allowed when CPU enters RUN mode. Each bit - * standards for 1 set point, locked by LOCK_CFG field +/*! CPU_RUN_MODE_MAPPING - Defines which Setpoint is allowed when CPU enters RUN mode. Each bit stands for 1 Setpoint, locked by LOCK_CFG field */ #define GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING_MASK) /*! @} */ -/*! @name CM_WAIT_MODE_MAPPING - CM Wait Mode Set Point Allowed */ +/*! @name CM_WAIT_MODE_MAPPING - CM Wait Mode Setpoint Allowed */ /*! @{ */ + #define GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING_SHIFT (0U) -/*! CPU_WAIT_MODE_MAPPING - Defines which set point is allowed when CPU enters WAIT mode. Each bit standards for 1 set point, locked by LOCK_CFG +/*! CPU_WAIT_MODE_MAPPING - Defines which Setpoint is allowed when CPU enters WAIT mode. Each bit stands for 1 Setpoint, locked by LOCK_CFG */ #define GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING_MASK) /*! @} */ -/*! @name CM_STOP_MODE_MAPPING - CM Stop Mode Set Point Allowed */ +/*! @name CM_STOP_MODE_MAPPING - CM Stop Mode Setpoint Allowed */ /*! @{ */ + #define GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING_SHIFT (0U) -/*! CPU_STOP_MODE_MAPPING - Defines which set point is allowed when CPU enters STOP mode. Each bit standards for 1 set point, locked by LOCK_CFG +/*! CPU_STOP_MODE_MAPPING - Defines which Setpoint is allowed when CPU enters STOP mode. Each bit stands for 1 Setpoint, locked by LOCK_CFG */ #define GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING_MASK) /*! @} */ -/*! @name CM_SUSPEND_MODE_MAPPING - CM Suspend Mode Set Point Allowed */ +/*! @name CM_SUSPEND_MODE_MAPPING - CM Suspend Mode Setpoint Allowed */ /*! @{ */ + #define GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING_SHIFT (0U) -/*! CPU_SUSPEND_MODE_MAPPING - Defines which set point is allowed when CPU enters SUSPEND mode. Each bit standards for 1 set point, locked by LOCK_CFG +/*! CPU_SUSPEND_MODE_MAPPING - Defines which Setpoint is allowed when CPU enters SUSPEND mode. Each bit stands for 1 Setpoint, locked by LOCK_CFG */ #define GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING_MASK) /*! @} */ -/*! @name CM_SP_MAPPING - CM Set Point 0 Mapping..CM Set Point 15 Mapping */ +/*! @name CM_SP_MAPPING - CM Setpoint 0 Mapping..CM Setpoint 15 Mapping */ /*! @{ */ + #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING_SHIFT (0U) /*! CPU_SP0_MAPPING - Defines when SP0 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */ #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING_MASK) + #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING_SHIFT (0U) /*! CPU_SP1_MAPPING - Defines when SP1 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */ #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING_MASK) + #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING_SHIFT (0U) /*! CPU_SP2_MAPPING - Defines when SP2 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */ #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING_MASK) + #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING_SHIFT (0U) /*! CPU_SP3_MAPPING - Defines when SP3 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */ #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING_MASK) + #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING_SHIFT (0U) /*! CPU_SP4_MAPPING - Defines when SP4 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */ #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING_MASK) + #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING_SHIFT (0U) /*! CPU_SP5_MAPPING - Defines when SP5 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */ #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING_MASK) + #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING_SHIFT (0U) /*! CPU_SP6_MAPPING - Defines when SP6 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */ #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING_MASK) + #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING_SHIFT (0U) /*! CPU_SP7_MAPPING - Defines when SP7 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */ #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING_MASK) + #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING_SHIFT (0U) /*! CPU_SP8_MAPPING - Defines when SP8 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */ #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING_MASK) + #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING_SHIFT (0U) /*! CPU_SP9_MAPPING - Defines when SP9 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */ #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING_MASK) + #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING_SHIFT (0U) /*! CPU_SP10_MAPPING - Defines when SP10 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */ #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING_MASK) + #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING_SHIFT (0U) /*! CPU_SP11_MAPPING - Defines when SP11 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */ #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING_MASK) + #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING_SHIFT (0U) /*! CPU_SP12_MAPPING - Defines when SP12 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */ #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING_MASK) + #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING_SHIFT (0U) /*! CPU_SP13_MAPPING - Defines when SP13 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */ #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING_MASK) + #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING_SHIFT (0U) /*! CPU_SP14_MAPPING - Defines when SP14 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field */ #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING_MASK) + #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING_MASK (0xFFFFU) #define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING_SHIFT (0U) /*! CPU_SP15_MAPPING - Defines when SP15 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field @@ -43939,26 +52770,31 @@ typedef struct { /*! @name CM_STBY_CTRL - CM standby control */ /*! @{ */ + #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_MASK (0x1U) #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_SHIFT (0U) -/*! STBY_WAIT - Request the chip into standby mode when CPU entering WAIT mode, locked by LOCK_CFG field. +/*! STBY_WAIT - 0x1: Request the chip into standby mode when CPU entering WAIT mode, locked by LOCK_CFG field. */ #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_MASK) + #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_MASK (0x2U) #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_SHIFT (1U) -/*! STBY_STOP - Request the chip into standby mode when CPU entering STOP mode, locked by LOCK_CFG field. +/*! STBY_STOP - 0x1: Request the chip into standby mode when CPU entering STOP mode, locked by LOCK_CFG field. */ #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_MASK) + #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_MASK (0x4U) #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_SHIFT (2U) -/*! STBY_SUSPEND - Request the chip into standby mode when CPU entering SUSPEND mode, locked by LOCK_CFG field. +/*! STBY_SUSPEND - 0x1: Request the chip into standby mode when CPU entering SUSPEND mode, locked by LOCK_CFG field. */ #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_MASK) + #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_MASK (0x10000U) #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_SHIFT (16U) /*! STBY_SLEEP_BUSY - Indicate the CPU is busy entering standby mode. */ #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_MASK) + #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_MASK (0x20000U) #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_SHIFT (17U) /*! STBY_WAKEUP_BUSY - Indicate the CPU is busy exiting standby mode. @@ -43966,15 +52802,6 @@ typedef struct { #define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_MASK) /*! @} */ -/*! @name CM_DEBUG - CM debug */ -/*! @{ */ -#define GPC_CPU_MODE_CTRL_CM_DEBUG_PRETEND_SLEEP_MASK (0x1U) -#define GPC_CPU_MODE_CTRL_CM_DEBUG_PRETEND_SLEEP_SHIFT (0U) -/*! PRETEND_SLEEP - Write 1 to force CMC into sleep, used to debug GPC status, locked by LOCK_CFG field. - */ -#define GPC_CPU_MODE_CTRL_CM_DEBUG_PRETEND_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_DEBUG_PRETEND_SLEEP_SHIFT)) & GPC_CPU_MODE_CTRL_CM_DEBUG_PRETEND_SLEEP_MASK) -/*! @} */ - /*! * @} @@ -44014,88 +52841,62 @@ typedef struct { uint8_t RESERVED_0[4]; __IO uint32_t SP_AUTHEN_CTRL; /**< SP Authentication Control, offset: 0x4 */ __IO uint32_t SP_INT_CTRL; /**< SP Interrupt Control, offset: 0x8 */ - uint32_t SP_MISC; /**< SP Misc, offset: 0xC */ + uint8_t RESERVED_1[4]; __I uint32_t SP_CPU_REQ; /**< CPU SP Request, offset: 0x10 */ __I uint32_t SP_SYS_STAT; /**< SP System Status, offset: 0x14 */ - __I uint32_t SP_TRANS_STAT; /**< SP Transition Status, offset: 0x18 */ + uint8_t RESERVED_2[4]; __IO uint32_t SP_ROSC_CTRL; /**< SP ROSC Control, offset: 0x1C */ - __I uint32_t SP_REQ_PIN_STAT; /**< SP Request Pin Status, offset: 0x20 */ - __I uint32_t SP_RSP_PIN_STAT; /**< SP Response Pin Status, offset: 0x24 */ - uint8_t RESERVED_1[24]; + uint8_t RESERVED_3[32]; __IO uint32_t SP_PRIORITY_0_7; /**< SP0~7 Priority, offset: 0x40 */ __IO uint32_t SP_PRIORITY_8_15; /**< SP8~15 Priority, offset: 0x44 */ - uint8_t RESERVED_2[184]; + uint8_t RESERVED_4[184]; __IO uint32_t SP_SSAR_SAVE_CTRL; /**< SP SSAR save control, offset: 0x100 */ - __I uint32_t SP_SSAR_SAVE_STAT; /**< SP SSAR save status, offset: 0x104 */ - uint8_t RESERVED_3[8]; + uint8_t RESERVED_5[12]; __IO uint32_t SP_LPCG_OFF_CTRL; /**< SP LPCG off control, offset: 0x110 */ - __I uint32_t SP_LPCG_OFF_STAT; /**< SP LPCG off status, offset: 0x114 */ - uint8_t RESERVED_4[8]; + uint8_t RESERVED_6[12]; __IO uint32_t SP_GROUP_DOWN_CTRL; /**< SP group down control, offset: 0x120 */ - __I uint32_t SP_GROUP_DOWN_STAT; /**< SP group down status, offset: 0x124 */ - uint8_t RESERVED_5[8]; + uint8_t RESERVED_7[12]; __IO uint32_t SP_ROOT_DOWN_CTRL; /**< SP root down control, offset: 0x130 */ - __I uint32_t SP_ROOT_DOWN_STAT; /**< SP root down status, offset: 0x134 */ - uint8_t RESERVED_6[8]; + uint8_t RESERVED_8[12]; __IO uint32_t SP_PLL_OFF_CTRL; /**< SP PLL off control, offset: 0x140 */ - __I uint32_t SP_PLL_OFF_STAT; /**< SP PLL off status, offset: 0x144 */ - uint8_t RESERVED_7[8]; + uint8_t RESERVED_9[12]; __IO uint32_t SP_ISO_ON_CTRL; /**< SP ISO on control, offset: 0x150 */ - __I uint32_t SP_ISO_ON_STAT; /**< SP ISO on status, offset: 0x154 */ - uint8_t RESERVED_8[8]; + uint8_t RESERVED_10[12]; __IO uint32_t SP_RESET_EARLY_CTRL; /**< SP reset early control, offset: 0x160 */ - __I uint32_t SP_RESET_EARLY_STAT; /**< SP reset early status, offset: 0x164 */ - uint8_t RESERVED_9[8]; + uint8_t RESERVED_11[12]; __IO uint32_t SP_POWER_OFF_CTRL; /**< SP power off control, offset: 0x170 */ - __I uint32_t SP_POWER_OFF_STAT; /**< SP power off status, offset: 0x174 */ - uint8_t RESERVED_10[8]; + uint8_t RESERVED_12[12]; __IO uint32_t SP_BIAS_OFF_CTRL; /**< SP bias off control, offset: 0x180 */ - __I uint32_t SP_BIAS_OFF_STAT; /**< SP bias off status, offset: 0x184 */ - uint8_t RESERVED_11[8]; + uint8_t RESERVED_13[12]; __IO uint32_t SP_BG_PLDO_OFF_CTRL; /**< SP bandgap and PLL_LDO off control, offset: 0x190 */ - __I uint32_t SP_BG_PLDO_OFF_STAT; /**< SP bandgap and PLL_LDO off status, offset: 0x194 */ - uint8_t RESERVED_12[8]; + uint8_t RESERVED_14[12]; __IO uint32_t SP_LDO_PRE_CTRL; /**< SP LDO pre control, offset: 0x1A0 */ - __I uint32_t SP_LDO_PRE_STAT; /**< SP LDO pre status, offset: 0x1A4 */ - uint8_t RESERVED_13[8]; + uint8_t RESERVED_15[12]; __IO uint32_t SP_DCDC_DOWN_CTRL; /**< SP DCDC down control, offset: 0x1B0 */ - __I uint32_t SP_DCDC_DOWN_STAT; /**< SP DCDC down status, offset: 0x1B4 */ - uint8_t RESERVED_14[72]; + uint8_t RESERVED_16[76]; __IO uint32_t SP_DCDC_UP_CTRL; /**< SP DCDC up control, offset: 0x200 */ - __I uint32_t SP_DCDC_UP_STAT; /**< SP DCDC up status, offset: 0x204 */ - uint8_t RESERVED_15[8]; + uint8_t RESERVED_17[12]; __IO uint32_t SP_LDO_POST_CTRL; /**< SP LDO post control, offset: 0x210 */ - __I uint32_t SP_LDO_POST_STAT; /**< SP LDO post status, offset: 0x214 */ - uint8_t RESERVED_16[8]; + uint8_t RESERVED_18[12]; __IO uint32_t SP_BG_PLDO_ON_CTRL; /**< SP bandgap and PLL_LDO on control, offset: 0x220 */ - __I uint32_t SP_BG_PLDO_ON_STAT; /**< SP bandgap and PLL_LDO on status, offset: 0x224 */ - uint8_t RESERVED_17[8]; + uint8_t RESERVED_19[12]; __IO uint32_t SP_BIAS_ON_CTRL; /**< SP bias on control, offset: 0x230 */ - __I uint32_t SP_BIAS_ON_STAT; /**< SP bias on status, offset: 0x234 */ - uint8_t RESERVED_18[8]; + uint8_t RESERVED_20[12]; __IO uint32_t SP_POWER_ON_CTRL; /**< SP power on control, offset: 0x240 */ - __I uint32_t SP_POWER_ON_STAT; /**< SP power on status, offset: 0x244 */ - uint8_t RESERVED_19[8]; + uint8_t RESERVED_21[12]; __IO uint32_t SP_RESET_LATE_CTRL; /**< SP reset late control, offset: 0x250 */ - __I uint32_t SP_RESET_LATE_STAT; /**< SP reset late status, offset: 0x254 */ - uint8_t RESERVED_20[8]; + uint8_t RESERVED_22[12]; __IO uint32_t SP_ISO_OFF_CTRL; /**< SP ISO off control, offset: 0x260 */ - __I uint32_t SP_ISO_OFF_STAT; /**< SP ISO off status, offset: 0x264 */ - uint8_t RESERVED_21[8]; + uint8_t RESERVED_23[12]; __IO uint32_t SP_PLL_ON_CTRL; /**< SP PLL on control, offset: 0x270 */ - __I uint32_t SP_PLL_ON_STAT; /**< SP PLL on status, offset: 0x274 */ - uint8_t RESERVED_22[8]; + uint8_t RESERVED_24[12]; __IO uint32_t SP_ROOT_UP_CTRL; /**< SP root up control, offset: 0x280 */ - __I uint32_t SP_ROOT_UP_STAT; /**< SP root up status, offset: 0x284 */ - uint8_t RESERVED_23[8]; + uint8_t RESERVED_25[12]; __IO uint32_t SP_GROUP_UP_CTRL; /**< SP group up control, offset: 0x290 */ - __I uint32_t SP_GROUP_UP_STAT; /**< SP group up status, offset: 0x294 */ - uint8_t RESERVED_24[8]; + uint8_t RESERVED_26[12]; __IO uint32_t SP_LPCG_ON_CTRL; /**< SP LPCG on control, offset: 0x2A0 */ - __I uint32_t SP_LPCG_ON_STAT; /**< SP LPCG on status, offset: 0x2A4 */ - uint8_t RESERVED_25[8]; + uint8_t RESERVED_27[12]; __IO uint32_t SP_SSAR_RESTORE_CTRL; /**< SP SSAR restore control, offset: 0x2B0 */ - __I uint32_t SP_SSAR_RESTORE_STAT; /**< SP SSAR restore status, offset: 0x2B4 */ } GPC_SET_POINT_CTRL_Type; /* ---------------------------------------------------------------------------- @@ -44109,31 +52910,41 @@ typedef struct { /*! @name SP_AUTHEN_CTRL - SP Authentication Control */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER_MASK (0x1U) #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER_SHIFT (0U) /*! USER - Allow user mode access + * 0b0..Allow only privilege mode to access setpoint control registers + * 0b1..Allow both privilege and user mode to access setpoint control registers */ #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER_MASK) + #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE_MASK (0x2U) #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE_SHIFT (1U) /*! NONSECURE - Allow non-secure mode access + * 0b0..Allow only secure mode to access setpoint control registers + * 0b1..Allow both secure and non-secure mode to access setpoint control registers */ #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE_MASK) + #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U) #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U) /*! LOCK_SETTING - Lock NONSECURE and USER */ #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING_MASK) + #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U) #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U) /*! WHITE_LIST - Domain ID white list */ #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST_MASK) + #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST_MASK (0x1000U) #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U) /*! LOCK_LIST - White list lock */ #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST_MASK) + #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U) #define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U) /*! LOCK_CFG - Configuration lock @@ -44143,11 +52954,13 @@ typedef struct { /*! @name SP_INT_CTRL - SP Interrupt Control */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN_MASK (0x1U) #define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN_SHIFT (0U) /*! NO_ALLOWED_SP_INT_EN - no_allowed_set_point interrupt enable */ #define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN_SHIFT)) & GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN_MASK) + #define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_MASK (0x2U) #define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_SHIFT (1U) /*! NO_ALLOWED_SP_INT - no_allowed_set_point interrupt @@ -44157,449 +52970,207 @@ typedef struct { /*! @name SP_CPU_REQ - CPU SP Request */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0_MASK (0xFU) #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0_SHIFT (0U) -/*! SP_REQ_CPU0 - set point requested by CPU0 +/*! SP_REQ_CPU0 - Setpoint requested by CPU0 */ #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0_MASK) + #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1_MASK (0xF0U) #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1_SHIFT (4U) -/*! SP_REQ_CPU1 - set point requested by CPU1 +/*! SP_REQ_CPU1 - Setpoint requested by CPU1 */ #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1_MASK) + #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2_MASK (0xF00U) #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2_SHIFT (8U) -/*! SP_REQ_CPU2 - set point requested by CPU2 +/*! SP_REQ_CPU2 - Setpoint requested by CPU2 */ #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2_MASK) + #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3_MASK (0xF000U) #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3_SHIFT (12U) -/*! SP_REQ_CPU3 - set point requested by CPU3 +/*! SP_REQ_CPU3 - Setpoint requested by CPU3 */ #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3_MASK) + #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0_MASK (0xF0000U) #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0_SHIFT (16U) -/*! SP_ACCEPTED_CPU0 - CPU0 set point accepted by SP controller +/*! SP_ACCEPTED_CPU0 - CPU0 Setpoint accepted by SP controller */ #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0_MASK) + #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1_MASK (0xF00000U) #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1_SHIFT (20U) -/*! SP_ACCEPTED_CPU1 - CPU1 set point accepted by SP controller +/*! SP_ACCEPTED_CPU1 - CPU1 Setpoint accepted by SP controller */ #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1_MASK) + #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2_MASK (0xF000000U) #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2_SHIFT (24U) -/*! SP_ACCEPTED_CPU2 - CPU2 set point accepted by SP controller +/*! SP_ACCEPTED_CPU2 - CPU2 Setpoint accepted by SP controller */ #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2_MASK) + #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3_MASK (0xF0000000U) #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3_SHIFT (28U) -/*! SP_ACCEPTED_CPU3 - CPU3 set point accepted by SP controller +/*! SP_ACCEPTED_CPU3 - CPU3 Setpoint accepted by SP controller */ #define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3_MASK) /*! @} */ /*! @name SP_SYS_STAT - SP System Status */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED_MASK (0xFFFFU) #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED_SHIFT (0U) -/*! SYS_SP_ALLOWED - allowed set points by all current CPU set point requests +/*! SYS_SP_ALLOWED - Allowed Setpoints by all current CPU Setpoint requests */ #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED_SHIFT)) & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED_MASK) + #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_MASK (0xF0000U) #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_SHIFT (16U) -/*! SYS_SP_TARGET - the set point chosen as target set point +/*! SYS_SP_TARGET - The Setpoint chosen as the target setpoint */ #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_SHIFT)) & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_MASK) + #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_MASK (0xF00000U) #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_SHIFT (20U) -/*! SYS_SP_CURRENT - Current set point, only valid when not SP trans busy +/*! SYS_SP_CURRENT - Current Setpoint, only valid when not SP trans busy */ #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_SHIFT)) & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_MASK) + #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_MASK (0xF000000U) #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_SHIFT (24U) -/*! SYS_SP_PREVIOUS - Previous set point, only valid when not SP trans busy +/*! SYS_SP_PREVIOUS - Previous Setpoint, only valid when not SP trans busy */ #define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_SHIFT)) & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_MASK) /*! @} */ -/*! @name SP_TRANS_STAT - SP Transition Status */ -/*! @{ */ -#define GPC_SET_POINT_CTRL_SP_TRANS_STAT_SEVERING_CPU_MASK (0xFU) -#define GPC_SET_POINT_CTRL_SP_TRANS_STAT_SEVERING_CPU_SHIFT (0U) -/*! SEVERING_CPU - Indicate the CPU which the SP controller is severing for its SP transfer request, each bit stands for a CPU. - */ -#define GPC_SET_POINT_CTRL_SP_TRANS_STAT_SEVERING_CPU(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_TRANS_STAT_SEVERING_CPU_SHIFT)) & GPC_SET_POINT_CTRL_SP_TRANS_STAT_SEVERING_CPU_MASK) -#define GPC_SET_POINT_CTRL_SP_TRANS_STAT_PENDING_CPU_MASK (0xF0U) -#define GPC_SET_POINT_CTRL_SP_TRANS_STAT_PENDING_CPU_SHIFT (4U) -/*! PENDING_CPU - Indicate which CPUs are requesting SP transition and is not completly served, each bit stands for a CPU. - */ -#define GPC_SET_POINT_CTRL_SP_TRANS_STAT_PENDING_CPU(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_TRANS_STAT_PENDING_CPU_SHIFT)) & GPC_SET_POINT_CTRL_SP_TRANS_STAT_PENDING_CPU_MASK) -#define GPC_SET_POINT_CTRL_SP_TRANS_STAT_TRANS_BUSY_MASK (0x10000U) -#define GPC_SET_POINT_CTRL_SP_TRANS_STAT_TRANS_BUSY_SHIFT (16U) -/*! TRANS_BUSY - SP controller is busy on SP transition - */ -#define GPC_SET_POINT_CTRL_SP_TRANS_STAT_TRANS_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_TRANS_STAT_TRANS_BUSY_SHIFT)) & GPC_SET_POINT_CTRL_SP_TRANS_STAT_TRANS_BUSY_MASK) -#define GPC_SET_POINT_CTRL_SP_TRANS_STAT_TRANS_FSM_STATE_MASK (0x1F000000U) -#define GPC_SET_POINT_CTRL_SP_TRANS_STAT_TRANS_FSM_STATE_SHIFT (24U) -/*! TRANS_FSM_STATE - SP transition FSM status - */ -#define GPC_SET_POINT_CTRL_SP_TRANS_STAT_TRANS_FSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_TRANS_STAT_TRANS_FSM_STATE_SHIFT)) & GPC_SET_POINT_CTRL_SP_TRANS_STAT_TRANS_FSM_STATE_MASK) -/*! @} */ - /*! @name SP_ROSC_CTRL - SP ROSC Control */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF_MASK (0xFFFFU) #define GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF_SHIFT (0U) -/*! SP_ALLOW_ROSC_OFF - Allow shutting off the ROSC which is main clock source of GPC when system is - * in selected set point. Each bit represents a set point index.Locked by LOCK_CFG field. +/*! SP_ALLOW_ROSC_OFF - Allow shutting off the ROSC */ #define GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF_MASK) /*! @} */ -/*! @name SP_REQ_PIN_STAT - SP Request Pin Status */ -/*! @{ */ -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_SSAR_SAVE_REQUEST_STAT_MASK (0x1U) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_SSAR_SAVE_REQUEST_STAT_SHIFT (0U) -/*! SSAR_SAVE_REQUEST_STAT - Status of pin set_point_trans_ssar_save_request - */ -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_SSAR_SAVE_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_SSAR_SAVE_REQUEST_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_SSAR_SAVE_REQUEST_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_LPCG_OFF_REQUEST_STAT_MASK (0x2U) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_LPCG_OFF_REQUEST_STAT_SHIFT (1U) -/*! LPCG_OFF_REQUEST_STAT - Status of pin set_point_trans_lpcg_off_request - */ -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_LPCG_OFF_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_LPCG_OFF_REQUEST_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_LPCG_OFF_REQUEST_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_GROUP_DN_REQUEST_STAT_MASK (0x4U) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_GROUP_DN_REQUEST_STAT_SHIFT (2U) -/*! GROUP_DN_REQUEST_STAT - Status of pin set_point_trans_group_down_request - */ -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_GROUP_DN_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_GROUP_DN_REQUEST_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_GROUP_DN_REQUEST_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_ROOT_DN_REQUEST_STAT_MASK (0x8U) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_ROOT_DN_REQUEST_STAT_SHIFT (3U) -/*! ROOT_DN_REQUEST_STAT - Status of pin set_point_trans_root_down_request - */ -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_ROOT_DN_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_ROOT_DN_REQUEST_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_ROOT_DN_REQUEST_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_PLL_OFF_REQUEST_STAT_MASK (0x10U) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_PLL_OFF_REQUEST_STAT_SHIFT (4U) -/*! PLL_OFF_REQUEST_STAT - Status of pin set_point_trans_oscpll_off_request - */ -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_PLL_OFF_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_PLL_OFF_REQUEST_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_PLL_OFF_REQUEST_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_ISO_ON_REQUEST_STAT_MASK (0x20U) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_ISO_ON_REQUEST_STAT_SHIFT (5U) -/*! ISO_ON_REQUEST_STAT - Status of pin set_point_trans_iso_on_request - */ -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_ISO_ON_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_ISO_ON_REQUEST_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_ISO_ON_REQUEST_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_RST_EARLY_REQUEST_STAT_MASK (0x40U) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_RST_EARLY_REQUEST_STAT_SHIFT (6U) -/*! RST_EARLY_REQUEST_STAT - Status of pin set_point_trans_reset_early_request - */ -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_RST_EARLY_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_RST_EARLY_REQUEST_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_RST_EARLY_REQUEST_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_PWR_OFF_REQUEST_STAT_MASK (0x80U) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_PWR_OFF_REQUEST_STAT_SHIFT (7U) -/*! PWR_OFF_REQUEST_STAT - Status of pin set_point_trans_power_off_request - */ -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_PWR_OFF_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_PWR_OFF_REQUEST_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_PWR_OFF_REQUEST_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_BIAS_OFF_REQUEST_STAT_MASK (0x100U) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_BIAS_OFF_REQUEST_STAT_SHIFT (8U) -/*! BIAS_OFF_REQUEST_STAT - Status of pin set_point_trans_bias_off_request - */ -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_BIAS_OFF_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_BIAS_OFF_REQUEST_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_BIAS_OFF_REQUEST_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_BG_PLDO_OFF_REQUEST_STAT_MASK (0x200U) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_BG_PLDO_OFF_REQUEST_STAT_SHIFT (9U) -/*! BG_PLDO_OFF_REQUEST_STAT - Status of pin set_point_trans_bg_pldo_off_request - */ -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_BG_PLDO_OFF_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_BG_PLDO_OFF_REQUEST_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_BG_PLDO_OFF_REQUEST_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_LDO_PRE_REQUEST_STAT_MASK (0x400U) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_LDO_PRE_REQUEST_STAT_SHIFT (10U) -/*! LDO_PRE_REQUEST_STAT - Status of pin set_point_trans_ldo_pre_request - */ -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_LDO_PRE_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_LDO_PRE_REQUEST_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_LDO_PRE_REQUEST_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_DCDC_DN_REQUEST_STAT_MASK (0x800U) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_DCDC_DN_REQUEST_STAT_SHIFT (11U) -/*! DCDC_DN_REQUEST_STAT - Status of pin set_point_trans_dcdc_down_request - */ -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_DCDC_DN_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_DCDC_DN_REQUEST_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_DCDC_DN_REQUEST_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_DCDC_UP_REQUEST_STAT_MASK (0x10000U) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_DCDC_UP_REQUEST_STAT_SHIFT (16U) -/*! DCDC_UP_REQUEST_STAT - Status of pin set_point_trans_dcdc_up_request - */ -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_DCDC_UP_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_DCDC_UP_REQUEST_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_DCDC_UP_REQUEST_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_LDO_POST_REQUEST_STAT_MASK (0x20000U) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_LDO_POST_REQUEST_STAT_SHIFT (17U) -/*! LDO_POST_REQUEST_STAT - Status of pin set_point_trans_ldo_post_request - */ -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_LDO_POST_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_LDO_POST_REQUEST_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_LDO_POST_REQUEST_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_BG_PLDO_ON_REQUEST_STAT_MASK (0x40000U) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_BG_PLDO_ON_REQUEST_STAT_SHIFT (18U) -/*! BG_PLDO_ON_REQUEST_STAT - Status of pin set_point_trans_bg_pldo_on_request - */ -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_BG_PLDO_ON_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_BG_PLDO_ON_REQUEST_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_BG_PLDO_ON_REQUEST_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_BIAS_ON_REQUEST_STAT_MASK (0x80000U) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_BIAS_ON_REQUEST_STAT_SHIFT (19U) -/*! BIAS_ON_REQUEST_STAT - Status of pin set_point_trans_bias_on_request - */ -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_BIAS_ON_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_BIAS_ON_REQUEST_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_BIAS_ON_REQUEST_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_PWR_ON_REQUEST_STAT_MASK (0x100000U) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_PWR_ON_REQUEST_STAT_SHIFT (20U) -/*! PWR_ON_REQUEST_STAT - Status of pin set_point_trans_power_on_request - */ -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_PWR_ON_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_PWR_ON_REQUEST_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_PWR_ON_REQUEST_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_RST_LATE_REQUEST_STAT_MASK (0x200000U) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_RST_LATE_REQUEST_STAT_SHIFT (21U) -/*! RST_LATE_REQUEST_STAT - Status of pin set_point_trans_reset_late_request - */ -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_RST_LATE_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_RST_LATE_REQUEST_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_RST_LATE_REQUEST_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_ISO_OFF_REQUEST_STAT_MASK (0x400000U) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_ISO_OFF_REQUEST_STAT_SHIFT (22U) -/*! ISO_OFF_REQUEST_STAT - Status of pin set_point_trans_iso_off_request - */ -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_ISO_OFF_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_ISO_OFF_REQUEST_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_ISO_OFF_REQUEST_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_PLL_ON_REQUEST_STAT_MASK (0x800000U) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_PLL_ON_REQUEST_STAT_SHIFT (23U) -/*! PLL_ON_REQUEST_STAT - Status of pin set_point_trans_oscpll_on_request - */ -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_PLL_ON_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_PLL_ON_REQUEST_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_PLL_ON_REQUEST_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_ROOT_UP_REQUEST_STAT_MASK (0x1000000U) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_ROOT_UP_REQUEST_STAT_SHIFT (24U) -/*! ROOT_UP_REQUEST_STAT - Status of pin set_point_trans_root_up_request - */ -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_ROOT_UP_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_ROOT_UP_REQUEST_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_ROOT_UP_REQUEST_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_GROUP_UP_REQUEST_STAT_MASK (0x2000000U) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_GROUP_UP_REQUEST_STAT_SHIFT (25U) -/*! GROUP_UP_REQUEST_STAT - Status of pin set_point_trans_group_up_request - */ -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_GROUP_UP_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_GROUP_UP_REQUEST_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_GROUP_UP_REQUEST_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_LPCG_ON_REQUEST_STAT_MASK (0x4000000U) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_LPCG_ON_REQUEST_STAT_SHIFT (26U) -/*! LPCG_ON_REQUEST_STAT - Status of pin set_point_trans_lpcg_on_request - */ -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_LPCG_ON_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_LPCG_ON_REQUEST_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_LPCG_ON_REQUEST_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_SSAR_RSTR_REQUEST_STAT_MASK (0x8000000U) -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_SSAR_RSTR_REQUEST_STAT_SHIFT (27U) -/*! SSAR_RSTR_REQUEST_STAT - Status of pin set_point_trans_ssar_restore_request - */ -#define GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_SSAR_RSTR_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_SSAR_RSTR_REQUEST_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_REQ_PIN_STAT_SSAR_RSTR_REQUEST_STAT_MASK) -/*! @} */ - -/*! @name SP_RSP_PIN_STAT - SP Response Pin Status */ -/*! @{ */ -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_SSAR_SAVE_DONE_STAT_MASK (0x1U) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_SSAR_SAVE_DONE_STAT_SHIFT (0U) -/*! SSAR_SAVE_DONE_STAT - Status of pin set_point_trans_ssar_save_done - */ -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_SSAR_SAVE_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_SSAR_SAVE_DONE_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_SSAR_SAVE_DONE_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_LPCG_OFF_DONE_STAT_MASK (0x2U) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_LPCG_OFF_DONE_STAT_SHIFT (1U) -/*! LPCG_OFF_DONE_STAT - Status of pin set_point_trans_lpcg_off_done - */ -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_LPCG_OFF_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_LPCG_OFF_DONE_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_LPCG_OFF_DONE_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_GROUP_DN_DONE_STAT_MASK (0x4U) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_GROUP_DN_DONE_STAT_SHIFT (2U) -/*! GROUP_DN_DONE_STAT - Status of pin set_point_trans_group_down_done - */ -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_GROUP_DN_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_GROUP_DN_DONE_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_GROUP_DN_DONE_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_ROOT_DN_DONE_STAT_MASK (0x8U) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_ROOT_DN_DONE_STAT_SHIFT (3U) -/*! ROOT_DN_DONE_STAT - Status of pin set_point_trans_root_down_done - */ -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_ROOT_DN_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_ROOT_DN_DONE_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_ROOT_DN_DONE_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_PLL_OFF_DONE_STAT_MASK (0x10U) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_PLL_OFF_DONE_STAT_SHIFT (4U) -/*! PLL_OFF_DONE_STAT - Status of pin set_point_trans_oscpll_off_done - */ -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_PLL_OFF_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_PLL_OFF_DONE_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_PLL_OFF_DONE_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_ISO_ON_DONE_STAT_MASK (0x20U) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_ISO_ON_DONE_STAT_SHIFT (5U) -/*! ISO_ON_DONE_STAT - Status of pin set_point_trans_iso_on_done - */ -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_ISO_ON_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_ISO_ON_DONE_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_ISO_ON_DONE_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_RST_EARLY_DONE_STAT_MASK (0x40U) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_RST_EARLY_DONE_STAT_SHIFT (6U) -/*! RST_EARLY_DONE_STAT - Status of pin set_point_trans_reset_early_done - */ -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_RST_EARLY_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_RST_EARLY_DONE_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_RST_EARLY_DONE_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_PWR_OFF_DONE_STAT_MASK (0x80U) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_PWR_OFF_DONE_STAT_SHIFT (7U) -/*! PWR_OFF_DONE_STAT - Status of pin set_point_trans_power_off_done - */ -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_PWR_OFF_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_PWR_OFF_DONE_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_PWR_OFF_DONE_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_BIAS_OFF_DONE_STAT_MASK (0x100U) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_BIAS_OFF_DONE_STAT_SHIFT (8U) -/*! BIAS_OFF_DONE_STAT - Status of pin set_point_trans_bias_off_done - */ -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_BIAS_OFF_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_BIAS_OFF_DONE_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_BIAS_OFF_DONE_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_BG_PLDO_OFF_DONE_STAT_MASK (0x200U) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_BG_PLDO_OFF_DONE_STAT_SHIFT (9U) -/*! BG_PLDO_OFF_DONE_STAT - Status of pin set_point_trans_bg_pldo_off_done - */ -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_BG_PLDO_OFF_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_BG_PLDO_OFF_DONE_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_BG_PLDO_OFF_DONE_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_LDO_PRE_DONE_STAT_MASK (0x400U) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_LDO_PRE_DONE_STAT_SHIFT (10U) -/*! LDO_PRE_DONE_STAT - Status of pin set_point_trans_ldo_pre_done - */ -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_LDO_PRE_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_LDO_PRE_DONE_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_LDO_PRE_DONE_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_DCDC_DN_DONE_STAT_MASK (0x800U) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_DCDC_DN_DONE_STAT_SHIFT (11U) -/*! DCDC_DN_DONE_STAT - Status of pin set_point_trans_dcdc_down_done - */ -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_DCDC_DN_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_DCDC_DN_DONE_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_DCDC_DN_DONE_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_DCDC_UP_DONE_STAT_MASK (0x10000U) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_DCDC_UP_DONE_STAT_SHIFT (16U) -/*! DCDC_UP_DONE_STAT - Status of pin set_point_trans_dcdc_up_done - */ -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_DCDC_UP_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_DCDC_UP_DONE_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_DCDC_UP_DONE_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_LDO_POST_DONE_STAT_MASK (0x20000U) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_LDO_POST_DONE_STAT_SHIFT (17U) -/*! LDO_POST_DONE_STAT - Status of pin set_point_trans_ldo_post_done - */ -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_LDO_POST_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_LDO_POST_DONE_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_LDO_POST_DONE_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_BG_PLDO_ON_DONE_STAT_MASK (0x40000U) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_BG_PLDO_ON_DONE_STAT_SHIFT (18U) -/*! BG_PLDO_ON_DONE_STAT - Status of pin set_point_trans_bg_pldo_on_done - */ -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_BG_PLDO_ON_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_BG_PLDO_ON_DONE_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_BG_PLDO_ON_DONE_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_BIAS_ON_DONE_STAT_MASK (0x80000U) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_BIAS_ON_DONE_STAT_SHIFT (19U) -/*! BIAS_ON_DONE_STAT - Status of pin set_point_trans_bias_on_done - */ -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_BIAS_ON_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_BIAS_ON_DONE_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_BIAS_ON_DONE_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_PWR_ON_DONE_STAT_MASK (0x100000U) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_PWR_ON_DONE_STAT_SHIFT (20U) -/*! PWR_ON_DONE_STAT - Status of pin set_point_trans_power_on_done - */ -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_PWR_ON_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_PWR_ON_DONE_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_PWR_ON_DONE_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_RST_LATE_DONE_STAT_MASK (0x200000U) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_RST_LATE_DONE_STAT_SHIFT (21U) -/*! RST_LATE_DONE_STAT - Status of pin set_point_trans_reset_late_done - */ -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_RST_LATE_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_RST_LATE_DONE_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_RST_LATE_DONE_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_ISO_OFF_DONE_STAT_MASK (0x400000U) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_ISO_OFF_DONE_STAT_SHIFT (22U) -/*! ISO_OFF_DONE_STAT - Status of pin set_point_trans_iso_off_done - */ -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_ISO_OFF_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_ISO_OFF_DONE_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_ISO_OFF_DONE_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_PLL_ON_DONE_STAT_MASK (0x800000U) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_PLL_ON_DONE_STAT_SHIFT (23U) -/*! PLL_ON_DONE_STAT - Status of pin set_point_trans_oscpll_on_done - */ -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_PLL_ON_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_PLL_ON_DONE_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_PLL_ON_DONE_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_ROOT_UP_DONE_STAT_MASK (0x1000000U) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_ROOT_UP_DONE_STAT_SHIFT (24U) -/*! ROOT_UP_DONE_STAT - Status of pin set_point_trans_root_up_done - */ -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_ROOT_UP_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_ROOT_UP_DONE_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_ROOT_UP_DONE_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_GROUP_UP_DONE_STAT_MASK (0x2000000U) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_GROUP_UP_DONE_STAT_SHIFT (25U) -/*! GROUP_UP_DONE_STAT - Status of pin set_point_trans_group_up_done - */ -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_GROUP_UP_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_GROUP_UP_DONE_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_GROUP_UP_DONE_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_LPCG_ON_DONE_STAT_MASK (0x4000000U) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_LPCG_ON_DONE_STAT_SHIFT (26U) -/*! LPCG_ON_DONE_STAT - Status of pin set_point_trans_lpcg_on_done - */ -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_LPCG_ON_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_LPCG_ON_DONE_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_LPCG_ON_DONE_STAT_MASK) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_SSAR_RSTR_DONE_STAT_MASK (0x8000000U) -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_SSAR_RSTR_DONE_STAT_SHIFT (27U) -/*! SSAR_RSTR_DONE_STAT - Status of pin set_point_trans_ssar_restore_done - */ -#define GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_SSAR_RSTR_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_SSAR_RSTR_DONE_STAT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RSP_PIN_STAT_SSAR_RSTR_DONE_STAT_MASK) -/*! @} */ - /*! @name SP_PRIORITY_0_7 - SP0~7 Priority */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY_MASK (0xFU) #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY_SHIFT (0U) -/*! SYS_SP0_PRIORITY - priority of set point 0 +/*! SYS_SP0_PRIORITY - priority of Setpoint 0 */ #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY_MASK) + #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY_MASK (0xF0U) #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY_SHIFT (4U) -/*! SYS_SP1_PRIORITY - priority of set point 1 +/*! SYS_SP1_PRIORITY - priority of Setpoint 1 */ #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY_MASK) + #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY_MASK (0xF00U) #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY_SHIFT (8U) -/*! SYS_SP2_PRIORITY - priority of set point 2 +/*! SYS_SP2_PRIORITY - priority of Setpoint 2 */ #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY_MASK) + #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY_MASK (0xF000U) #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY_SHIFT (12U) -/*! SYS_SP3_PRIORITY - priority of set point 3 +/*! SYS_SP3_PRIORITY - priority of Setpoint 3 */ #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY_MASK) + #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY_MASK (0xF0000U) #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY_SHIFT (16U) -/*! SYS_SP4_PRIORITY - priority of set point 4 +/*! SYS_SP4_PRIORITY - priority of Setpoint 4 */ #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY_MASK) + #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY_MASK (0xF00000U) #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY_SHIFT (20U) -/*! SYS_SP5_PRIORITY - priority of set point 5 +/*! SYS_SP5_PRIORITY - priority of Setpoint 5 */ #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY_MASK) + #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY_MASK (0xF000000U) #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY_SHIFT (24U) -/*! SYS_SP6_PRIORITY - priority of set point 6 +/*! SYS_SP6_PRIORITY - priority of Setpoint 6 */ #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY_MASK) + #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY_MASK (0xF0000000U) #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY_SHIFT (28U) -/*! SYS_SP7_PRIORITY - priority of set point 7 +/*! SYS_SP7_PRIORITY - priority of Setpoint 7 */ #define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY_MASK) /*! @} */ /*! @name SP_PRIORITY_8_15 - SP8~15 Priority */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY_MASK (0xFU) #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY_SHIFT (0U) -/*! SYS_SP8_PRIORITY - priority of set point 8 +/*! SYS_SP8_PRIORITY - priority of Setpoint 8 */ #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY_MASK) + #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY_MASK (0xF0U) #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY_SHIFT (4U) -/*! SYS_SP9_PRIORITY - priority of set point 9 +/*! SYS_SP9_PRIORITY - priority of Setpoint 9 */ #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY_MASK) + #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY_MASK (0xF00U) #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY_SHIFT (8U) -/*! SYS_SP10_PRIORITY - priority of set point 10 +/*! SYS_SP10_PRIORITY - priority of Setpoint 10 */ #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY_MASK) + #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY_MASK (0xF000U) #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY_SHIFT (12U) -/*! SYS_SP11_PRIORITY - priority of set point 11 +/*! SYS_SP11_PRIORITY - priority of Setpoint 11 */ #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY_MASK) + #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY_MASK (0xF0000U) #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY_SHIFT (16U) -/*! SYS_SP12_PRIORITY - priority of set point 12 +/*! SYS_SP12_PRIORITY - priority of Setpoint 12 */ #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY_MASK) + #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY_MASK (0xF00000U) #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY_SHIFT (20U) -/*! SYS_SP13_PRIORITY - priority of set point 13 +/*! SYS_SP13_PRIORITY - priority of Setpoint 13 */ #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY_MASK) + #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY_MASK (0xF000000U) #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY_SHIFT (24U) -/*! SYS_SP14_PRIORITY - priority of set point 14 +/*! SYS_SP14_PRIORITY - priority of Setpoint 14 */ #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY_MASK) + #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_MASK (0xF0000000U) #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_SHIFT (28U) -/*! SYS_SP15_PRIORITY - priority of set point 15 +/*! SYS_SP15_PRIORITY - priority of Setpoint 15 */ #define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_MASK) /*! @} */ /*! @name SP_SSAR_SAVE_CTRL - SP SSAR save control */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_MASK) + #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -44609,6 +53180,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_MASK) + #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_MASK (0x80000000U) #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -44616,22 +53188,15 @@ typedef struct { #define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_MASK) /*! @} */ -/*! @name SP_SSAR_SAVE_STAT - SP SSAR save status */ -/*! @{ */ -#define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_SAVE_STAT_RSP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_SAVE_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name SP_LPCG_OFF_CTRL - SP LPCG off control */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_MASK) + #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -44641,6 +53206,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_MASK) + #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE_MASK (0x80000000U) #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -44648,22 +53214,15 @@ typedef struct { #define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE_MASK) /*! @} */ -/*! @name SP_LPCG_OFF_STAT - SP LPCG off status */ -/*! @{ */ -#define GPC_SET_POINT_CTRL_SP_LPCG_OFF_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_SET_POINT_CTRL_SP_LPCG_OFF_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_SET_POINT_CTRL_SP_LPCG_OFF_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_OFF_STAT_RSP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_OFF_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name SP_GROUP_DOWN_CTRL - SP group down control */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_MASK) + #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -44673,6 +53232,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_MASK) + #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE_MASK (0x80000000U) #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -44680,22 +53240,15 @@ typedef struct { #define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE_MASK) /*! @} */ -/*! @name SP_GROUP_DOWN_STAT - SP group down status */ -/*! @{ */ -#define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_DOWN_STAT_RSP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_DOWN_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name SP_ROOT_DOWN_CTRL - SP root down control */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_MASK) + #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -44705,6 +53258,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_MASK) + #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE_MASK (0x80000000U) #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -44712,22 +53266,15 @@ typedef struct { #define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE_MASK) /*! @} */ -/*! @name SP_ROOT_DOWN_STAT - SP root down status */ -/*! @{ */ -#define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_DOWN_STAT_RSP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_DOWN_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name SP_PLL_OFF_CTRL - SP PLL off control */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_MASK) + #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -44737,6 +53284,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_MASK) + #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE_MASK (0x80000000U) #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -44744,22 +53292,15 @@ typedef struct { #define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE_MASK) /*! @} */ -/*! @name SP_PLL_OFF_STAT - SP PLL off status */ -/*! @{ */ -#define GPC_SET_POINT_CTRL_SP_PLL_OFF_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_SET_POINT_CTRL_SP_PLL_OFF_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_SET_POINT_CTRL_SP_PLL_OFF_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_OFF_STAT_RSP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_OFF_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name SP_ISO_ON_CTRL - SP ISO on control */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_MASK) + #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -44769,6 +53310,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_MASK) + #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE_MASK (0x80000000U) #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -44776,22 +53318,15 @@ typedef struct { #define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE_MASK) /*! @} */ -/*! @name SP_ISO_ON_STAT - SP ISO on status */ -/*! @{ */ -#define GPC_SET_POINT_CTRL_SP_ISO_ON_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_SET_POINT_CTRL_SP_ISO_ON_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_SET_POINT_CTRL_SP_ISO_ON_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_ON_STAT_RSP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_ON_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name SP_RESET_EARLY_CTRL - SP reset early control */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_MASK) + #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -44801,6 +53336,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_MASK) + #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE_MASK (0x80000000U) #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -44808,22 +53344,15 @@ typedef struct { #define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE_MASK) /*! @} */ -/*! @name SP_RESET_EARLY_STAT - SP reset early status */ -/*! @{ */ -#define GPC_SET_POINT_CTRL_SP_RESET_EARLY_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_SET_POINT_CTRL_SP_RESET_EARLY_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_SET_POINT_CTRL_SP_RESET_EARLY_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_EARLY_STAT_RSP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_EARLY_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name SP_POWER_OFF_CTRL - SP power off control */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_MASK) + #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -44833,6 +53362,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_MASK) + #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE_MASK (0x80000000U) #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -44840,22 +53370,15 @@ typedef struct { #define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE_MASK) /*! @} */ -/*! @name SP_POWER_OFF_STAT - SP power off status */ -/*! @{ */ -#define GPC_SET_POINT_CTRL_SP_POWER_OFF_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_SET_POINT_CTRL_SP_POWER_OFF_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_SET_POINT_CTRL_SP_POWER_OFF_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_OFF_STAT_RSP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_OFF_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name SP_BIAS_OFF_CTRL - SP bias off control */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_MASK) + #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -44865,6 +53388,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_MASK) + #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE_MASK (0x80000000U) #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -44872,22 +53396,15 @@ typedef struct { #define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE_MASK) /*! @} */ -/*! @name SP_BIAS_OFF_STAT - SP bias off status */ -/*! @{ */ -#define GPC_SET_POINT_CTRL_SP_BIAS_OFF_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_SET_POINT_CTRL_SP_BIAS_OFF_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_SET_POINT_CTRL_SP_BIAS_OFF_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_OFF_STAT_RSP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_OFF_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name SP_BG_PLDO_OFF_CTRL - SP bandgap and PLL_LDO off control */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_MASK) + #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -44897,6 +53414,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_MASK) + #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE_MASK (0x80000000U) #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -44904,22 +53422,15 @@ typedef struct { #define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE_MASK) /*! @} */ -/*! @name SP_BG_PLDO_OFF_STAT - SP bandgap and PLL_LDO off status */ -/*! @{ */ -#define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_STAT_RSP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name SP_LDO_PRE_CTRL - SP LDO pre control */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_MASK) + #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -44929,6 +53440,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_MASK) + #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE_MASK (0x80000000U) #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -44936,22 +53448,15 @@ typedef struct { #define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE_MASK) /*! @} */ -/*! @name SP_LDO_PRE_STAT - SP LDO pre status */ -/*! @{ */ -#define GPC_SET_POINT_CTRL_SP_LDO_PRE_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_SET_POINT_CTRL_SP_LDO_PRE_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_SET_POINT_CTRL_SP_LDO_PRE_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_PRE_STAT_RSP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_PRE_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name SP_DCDC_DOWN_CTRL - SP DCDC down control */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_MASK) + #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -44961,6 +53466,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_MASK) + #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE_MASK (0x80000000U) #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -44968,22 +53474,15 @@ typedef struct { #define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE_MASK) /*! @} */ -/*! @name SP_DCDC_DOWN_STAT - SP DCDC down status */ -/*! @{ */ -#define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_DOWN_STAT_RSP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_DOWN_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name SP_DCDC_UP_CTRL - SP DCDC up control */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_MASK) + #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -44993,6 +53492,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_MASK) + #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE_MASK (0x80000000U) #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -45000,22 +53500,15 @@ typedef struct { #define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE_MASK) /*! @} */ -/*! @name SP_DCDC_UP_STAT - SP DCDC up status */ -/*! @{ */ -#define GPC_SET_POINT_CTRL_SP_DCDC_UP_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_SET_POINT_CTRL_SP_DCDC_UP_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_SET_POINT_CTRL_SP_DCDC_UP_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_UP_STAT_RSP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_UP_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name SP_LDO_POST_CTRL - SP LDO post control */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_MASK) + #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -45025,6 +53518,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_MASK) + #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE_MASK (0x80000000U) #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -45032,22 +53526,15 @@ typedef struct { #define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE_MASK) /*! @} */ -/*! @name SP_LDO_POST_STAT - SP LDO post status */ -/*! @{ */ -#define GPC_SET_POINT_CTRL_SP_LDO_POST_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_SET_POINT_CTRL_SP_LDO_POST_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_SET_POINT_CTRL_SP_LDO_POST_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_POST_STAT_RSP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_POST_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name SP_BG_PLDO_ON_CTRL - SP bandgap and PLL_LDO on control */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_MASK) + #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -45057,6 +53544,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_MASK) + #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE_MASK (0x80000000U) #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -45064,22 +53552,15 @@ typedef struct { #define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE_MASK) /*! @} */ -/*! @name SP_BG_PLDO_ON_STAT - SP bandgap and PLL_LDO on status */ -/*! @{ */ -#define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_STAT_RSP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name SP_BIAS_ON_CTRL - SP bias on control */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_MASK) + #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -45089,6 +53570,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_MASK) + #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE_MASK (0x80000000U) #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -45096,22 +53578,15 @@ typedef struct { #define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE_MASK) /*! @} */ -/*! @name SP_BIAS_ON_STAT - SP bias on status */ -/*! @{ */ -#define GPC_SET_POINT_CTRL_SP_BIAS_ON_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_SET_POINT_CTRL_SP_BIAS_ON_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_SET_POINT_CTRL_SP_BIAS_ON_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_ON_STAT_RSP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_ON_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name SP_POWER_ON_CTRL - SP power on control */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_MASK) + #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -45121,6 +53596,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_MASK) + #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE_MASK (0x80000000U) #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -45128,22 +53604,15 @@ typedef struct { #define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE_MASK) /*! @} */ -/*! @name SP_POWER_ON_STAT - SP power on status */ -/*! @{ */ -#define GPC_SET_POINT_CTRL_SP_POWER_ON_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_SET_POINT_CTRL_SP_POWER_ON_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_SET_POINT_CTRL_SP_POWER_ON_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_ON_STAT_RSP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_ON_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name SP_RESET_LATE_CTRL - SP reset late control */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_MASK) + #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -45153,6 +53622,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_MASK) + #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE_MASK (0x80000000U) #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -45160,22 +53630,15 @@ typedef struct { #define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE_MASK) /*! @} */ -/*! @name SP_RESET_LATE_STAT - SP reset late status */ -/*! @{ */ -#define GPC_SET_POINT_CTRL_SP_RESET_LATE_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_SET_POINT_CTRL_SP_RESET_LATE_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_SET_POINT_CTRL_SP_RESET_LATE_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_LATE_STAT_RSP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_LATE_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name SP_ISO_OFF_CTRL - SP ISO off control */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_MASK) + #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -45185,6 +53648,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_MASK) + #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE_MASK (0x80000000U) #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -45192,22 +53656,15 @@ typedef struct { #define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE_MASK) /*! @} */ -/*! @name SP_ISO_OFF_STAT - SP ISO off status */ -/*! @{ */ -#define GPC_SET_POINT_CTRL_SP_ISO_OFF_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_SET_POINT_CTRL_SP_ISO_OFF_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_SET_POINT_CTRL_SP_ISO_OFF_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_OFF_STAT_RSP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_OFF_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name SP_PLL_ON_CTRL - SP PLL on control */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_MASK) + #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -45217,6 +53674,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_MASK) + #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE_MASK (0x80000000U) #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -45224,22 +53682,15 @@ typedef struct { #define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE_MASK) /*! @} */ -/*! @name SP_PLL_ON_STAT - SP PLL on status */ -/*! @{ */ -#define GPC_SET_POINT_CTRL_SP_PLL_ON_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_SET_POINT_CTRL_SP_PLL_ON_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_SET_POINT_CTRL_SP_PLL_ON_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_ON_STAT_RSP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_ON_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name SP_ROOT_UP_CTRL - SP root up control */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_MASK) + #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -45249,6 +53700,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_MASK) + #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE_MASK (0x80000000U) #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -45256,22 +53708,15 @@ typedef struct { #define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE_MASK) /*! @} */ -/*! @name SP_ROOT_UP_STAT - SP root up status */ -/*! @{ */ -#define GPC_SET_POINT_CTRL_SP_ROOT_UP_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_SET_POINT_CTRL_SP_ROOT_UP_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_SET_POINT_CTRL_SP_ROOT_UP_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_UP_STAT_RSP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_UP_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name SP_GROUP_UP_CTRL - SP group up control */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_MASK) + #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -45281,6 +53726,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_MASK) + #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE_MASK (0x80000000U) #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -45288,22 +53734,15 @@ typedef struct { #define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE_MASK) /*! @} */ -/*! @name SP_GROUP_UP_STAT - SP group up status */ -/*! @{ */ -#define GPC_SET_POINT_CTRL_SP_GROUP_UP_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_SET_POINT_CTRL_SP_GROUP_UP_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_SET_POINT_CTRL_SP_GROUP_UP_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_UP_STAT_RSP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_UP_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name SP_LPCG_ON_CTRL - SP LPCG on control */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_MASK) + #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -45313,6 +53752,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_MASK) + #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE_MASK (0x80000000U) #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -45320,22 +53760,15 @@ typedef struct { #define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE_MASK) /*! @} */ -/*! @name SP_LPCG_ON_STAT - SP LPCG on status */ -/*! @{ */ -#define GPC_SET_POINT_CTRL_SP_LPCG_ON_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_SET_POINT_CTRL_SP_LPCG_ON_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_SET_POINT_CTRL_SP_LPCG_ON_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_ON_STAT_RSP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_ON_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name SP_SSAR_RESTORE_CTRL - SP SSAR restore control */ /*! @{ */ + #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_MASK) + #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -45345,6 +53778,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_MASK) + #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE_MASK (0x80000000U) #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -45352,15 +53786,6 @@ typedef struct { #define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE_MASK) /*! @} */ -/*! @name SP_SSAR_RESTORE_STAT - SP SSAR restore status */ -/*! @{ */ -#define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_STAT_RSP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_STAT_RSP_CNT_MASK) -/*! @} */ - /*! * @} @@ -45397,53 +53822,38 @@ typedef struct { __IO uint32_t STBY_AUTHEN_CTRL; /**< Standby Authentication Control, offset: 0x4 */ uint8_t RESERVED_1[4]; __IO uint32_t STBY_MISC; /**< STBY Misc, offset: 0xC */ - uint8_t RESERVED_2[8]; - __I uint32_t STBY_TRANS_STAT; /**< Standby Transition Status, offset: 0x18 */ - __I uint32_t STBY_PIN_STAT; /**< Standby Pin Status, offset: 0x1C */ - uint8_t RESERVED_3[208]; + uint8_t RESERVED_2[224]; __IO uint32_t STBY_LPCG_IN_CTRL; /**< STBY lpcg_in control, offset: 0xF0 */ - __I uint32_t STBY_LPCG_IN_STAT; /**< STBY pll_in status, offset: 0xF4 */ - uint8_t RESERVED_4[8]; + uint8_t RESERVED_3[12]; __IO uint32_t STBY_PLL_IN_CTRL; /**< STBY pll_in control, offset: 0x100 */ - __I uint32_t STBY_PLL_IN_STAT; /**< STBY pll_in status, offset: 0x104 */ - uint8_t RESERVED_5[8]; + uint8_t RESERVED_4[12]; __IO uint32_t STBY_BIAS_IN_CTRL; /**< STBY bias_in control, offset: 0x110 */ - __I uint32_t STBY_BIAS_IN_STAT; /**< STBY bias_in status, offset: 0x114 */ - uint8_t RESERVED_6[8]; + uint8_t RESERVED_5[12]; __IO uint32_t STBY_PLDO_IN_CTRL; /**< STBY pldo_in control, offset: 0x120 */ - __I uint32_t STBY_PLDO_IN_STAT; /**< STBY pldo_in status, offset: 0x124 */ + uint8_t RESERVED_6[4]; __IO uint32_t STBY_BANDGAP_IN_CTRL; /**< STBY bandgap_in control, offset: 0x128 */ - __I uint32_t STBY_BANDGAP_IN_STAT; /**< STBY bandgap_in status, offset: 0x12C */ + uint8_t RESERVED_7[4]; __IO uint32_t STBY_LDO_IN_CTRL; /**< STBY ldo_in control, offset: 0x130 */ - __I uint32_t STBY_LDO_IN_STAT; /**< STBY ldo_in status, offset: 0x134 */ - uint8_t RESERVED_7[8]; + uint8_t RESERVED_8[12]; __IO uint32_t STBY_DCDC_IN_CTRL; /**< STBY dcdc_in control, offset: 0x140 */ - __I uint32_t STBY_DCDC_IN_STAT; /**< STBY dcdc_in status, offset: 0x144 */ - uint8_t RESERVED_8[8]; + uint8_t RESERVED_9[12]; __IO uint32_t STBY_PMIC_IN_CTRL; /**< STBY PMIC in control, offset: 0x150 */ - __I uint32_t STBY_PMIC_IN_STAT; /**< STBY PMIC in status, offset: 0x154 */ - uint8_t RESERVED_9[168]; + uint8_t RESERVED_10[172]; __IO uint32_t STBY_PMIC_OUT_CTRL; /**< STBY PMIC out control, offset: 0x200 */ - __I uint32_t STBY_PMIC_OUT_STAT; /**< STBY PMIC out status, offset: 0x204 */ - uint8_t RESERVED_10[8]; + uint8_t RESERVED_11[12]; __IO uint32_t STBY_DCDC_OUT_CTRL; /**< STBY DCDC out control, offset: 0x210 */ - __I uint32_t STBY_DCDC_OUT_STAT; /**< STBY DCDC out status, offset: 0x214 */ - uint8_t RESERVED_11[8]; + uint8_t RESERVED_12[12]; __IO uint32_t STBY_LDO_OUT_CTRL; /**< STBY LDO out control, offset: 0x220 */ - __I uint32_t STBY_LDO_OUT_STAT; /**< STBY LDO out status, offset: 0x224 */ - uint8_t RESERVED_12[8]; + uint8_t RESERVED_13[12]; __IO uint32_t STBY_BANDGAP_OUT_CTRL; /**< STBY bandgap out control, offset: 0x230 */ - __I uint32_t STBY_BANDGAP_OUT_STAT; /**< STBY BANDGAP out status, offset: 0x234 */ + uint8_t RESERVED_14[4]; __IO uint32_t STBY_PLDO_OUT_CTRL; /**< STBY pldo out control, offset: 0x238 */ - __I uint32_t STBY_PLDO_OUT_STAT; /**< STBY PLDO out status, offset: 0x23C */ + uint8_t RESERVED_15[4]; __IO uint32_t STBY_BIAS_OUT_CTRL; /**< STBY bias out control, offset: 0x240 */ - __I uint32_t STBY_BIAS_OUT_STAT; /**< STBY bias out status, offset: 0x244 */ - uint8_t RESERVED_13[8]; + uint8_t RESERVED_16[12]; __IO uint32_t STBY_PLL_OUT_CTRL; /**< STBY PLL out control, offset: 0x250 */ - __I uint32_t STBY_PLL_OUT_STAT; /**< STBY PLL out status, offset: 0x254 */ - uint8_t RESERVED_14[8]; + uint8_t RESERVED_17[12]; __IO uint32_t STBY_LPCG_OUT_CTRL; /**< STBY LPCG out control, offset: 0x260 */ - __I uint32_t STBY_LPCG_OUT_STAT; /**< STBY LPCG out status, offset: 0x264 */ } GPC_STBY_CTRL_Type; /* ---------------------------------------------------------------------------- @@ -45457,6 +53867,7 @@ typedef struct { /*! @name STBY_AUTHEN_CTRL - Standby Authentication Control */ /*! @{ */ + #define GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U) #define GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U) /*! LOCK_CFG - Configuration lock @@ -45466,21 +53877,25 @@ typedef struct { /*! @name STBY_MISC - STBY Misc */ /*! @{ */ + #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY_MASK (0x1U) #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY_SHIFT (0U) /*! FORCE_CPU0_STBY - Force CPU0 requesting standby mode */ #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY_SHIFT)) & GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY_MASK) + #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY_MASK (0x2U) #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY_SHIFT (1U) /*! FORCE_CPU1_STBY - Force CPU0 requesting standby mode */ #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY_SHIFT)) & GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY_MASK) + #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY_MASK (0x4U) #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY_SHIFT (2U) /*! FORCE_CPU2_STBY - Force CPU2 requesting standby mode */ #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY_SHIFT)) & GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY_MASK) + #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY_MASK (0x8U) #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY_SHIFT (3U) /*! FORCE_CPU3_STBY - Force CPU3 requesting standby mode @@ -45488,191 +53903,15 @@ typedef struct { #define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY_SHIFT)) & GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY_MASK) /*! @} */ -/*! @name STBY_TRANS_STAT - Standby Transition Status */ -/*! @{ */ -#define GPC_STBY_CTRL_STBY_TRANS_STAT_RESUME_FSM_STATE_MASK (0x1F0000U) -#define GPC_STBY_CTRL_STBY_TRANS_STAT_RESUME_FSM_STATE_SHIFT (16U) -/*! RESUME_FSM_STATE - Last FSM status before resume - */ -#define GPC_STBY_CTRL_STBY_TRANS_STAT_RESUME_FSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_TRANS_STAT_RESUME_FSM_STATE_SHIFT)) & GPC_STBY_CTRL_STBY_TRANS_STAT_RESUME_FSM_STATE_MASK) -#define GPC_STBY_CTRL_STBY_TRANS_STAT_TRANS_FSM_STATE_MASK (0x1F000000U) -#define GPC_STBY_CTRL_STBY_TRANS_STAT_TRANS_FSM_STATE_SHIFT (24U) -/*! TRANS_FSM_STATE - Standby transition FSM status - */ -#define GPC_STBY_CTRL_STBY_TRANS_STAT_TRANS_FSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_TRANS_STAT_TRANS_FSM_STATE_SHIFT)) & GPC_STBY_CTRL_STBY_TRANS_STAT_TRANS_FSM_STATE_MASK) -/*! @} */ - -/*! @name STBY_PIN_STAT - Standby Pin Status */ -/*! @{ */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_LPCG_IN_REQUEST_STAT_MASK (0x1U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_LPCG_IN_REQUEST_STAT_SHIFT (0U) -/*! LPCG_IN_REQUEST_STAT - Status of pin standby_pll_in_request - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_LPCG_IN_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_LPCG_IN_REQUEST_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_LPCG_IN_REQUEST_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_PLL_IN_REQUEST_STAT_MASK (0x2U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_PLL_IN_REQUEST_STAT_SHIFT (1U) -/*! PLL_IN_REQUEST_STAT - Status of pin standby_pll_in_request - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_PLL_IN_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_PLL_IN_REQUEST_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_PLL_IN_REQUEST_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_BIAS_IN_REQUEST_STAT_MASK (0x4U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_BIAS_IN_REQUEST_STAT_SHIFT (2U) -/*! BIAS_IN_REQUEST_STAT - Status of pin standby_bias_in_request - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_BIAS_IN_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_BIAS_IN_REQUEST_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_BIAS_IN_REQUEST_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_PLDO_IN_REQUEST_STAT_MASK (0x8U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_PLDO_IN_REQUEST_STAT_SHIFT (3U) -/*! PLDO_IN_REQUEST_STAT - Status of pin standby_pldo_in_request - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_PLDO_IN_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_PLDO_IN_REQUEST_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_PLDO_IN_REQUEST_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_BANDGAP_IN_REQUEST_STAT_MASK (0x10U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_BANDGAP_IN_REQUEST_STAT_SHIFT (4U) -/*! BANDGAP_IN_REQUEST_STAT - Status of pin standby_bandgap_in_request - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_BANDGAP_IN_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_BANDGAP_IN_REQUEST_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_BANDGAP_IN_REQUEST_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_LDO_IN_REQUEST_STAT_MASK (0x20U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_LDO_IN_REQUEST_STAT_SHIFT (5U) -/*! LDO_IN_REQUEST_STAT - Status of pin standby_ldo_in_request - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_LDO_IN_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_LDO_IN_REQUEST_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_LDO_IN_REQUEST_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_DCDC_IN_REQUEST_STAT_MASK (0x40U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_DCDC_IN_REQUEST_STAT_SHIFT (6U) -/*! DCDC_IN_REQUEST_STAT - Status of pin standby_dcdc_in_request - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_DCDC_IN_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_DCDC_IN_REQUEST_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_DCDC_IN_REQUEST_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_PMIC_IN_REQUEST_STAT_MASK (0x80U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_PMIC_IN_REQUEST_STAT_SHIFT (7U) -/*! PMIC_IN_REQUEST_STAT - Status of pin standby_pmic_in_request - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_PMIC_IN_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_PMIC_IN_REQUEST_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_PMIC_IN_REQUEST_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_PMIC_OUT_REQUEST_STAT_MASK (0x100U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_PMIC_OUT_REQUEST_STAT_SHIFT (8U) -/*! PMIC_OUT_REQUEST_STAT - Status of pin standby_pmic_out_request - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_PMIC_OUT_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_PMIC_OUT_REQUEST_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_PMIC_OUT_REQUEST_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_DCDC_OUT_REQUEST_STAT_MASK (0x200U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_DCDC_OUT_REQUEST_STAT_SHIFT (9U) -/*! DCDC_OUT_REQUEST_STAT - Status of pin standby_dcdc_out_request - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_DCDC_OUT_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_DCDC_OUT_REQUEST_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_DCDC_OUT_REQUEST_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_LDO_OUT_REQUEST_STAT_MASK (0x400U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_LDO_OUT_REQUEST_STAT_SHIFT (10U) -/*! LDO_OUT_REQUEST_STAT - Status of pin standby_ldo_out_request - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_LDO_OUT_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_LDO_OUT_REQUEST_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_LDO_OUT_REQUEST_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_BANDGAP_OUT_REQUEST_STAT_MASK (0x800U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_BANDGAP_OUT_REQUEST_STAT_SHIFT (11U) -/*! BANDGAP_OUT_REQUEST_STAT - Status of pin standby_bandgap_out_request - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_BANDGAP_OUT_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_BANDGAP_OUT_REQUEST_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_BANDGAP_OUT_REQUEST_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_PLDO_OUT_REQUEST_STAT_MASK (0x1000U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_PLDO_OUT_REQUEST_STAT_SHIFT (12U) -/*! PLDO_OUT_REQUEST_STAT - Status of pin standby_pldo_out_request - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_PLDO_OUT_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_PLDO_OUT_REQUEST_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_PLDO_OUT_REQUEST_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_BIAS_OUT_REQUEST_STAT_MASK (0x2000U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_BIAS_OUT_REQUEST_STAT_SHIFT (13U) -/*! BIAS_OUT_REQUEST_STAT - Status of pin standby_bias_out_request - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_BIAS_OUT_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_BIAS_OUT_REQUEST_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_BIAS_OUT_REQUEST_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_PLL_OUT_REQUEST_STAT_MASK (0x4000U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_PLL_OUT_REQUEST_STAT_SHIFT (14U) -/*! PLL_OUT_REQUEST_STAT - Status of pin standby_pll_out_request - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_PLL_OUT_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_PLL_OUT_REQUEST_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_PLL_OUT_REQUEST_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_LPCG_OUT_REQUEST_STAT_MASK (0x8000U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_LPCG_OUT_REQUEST_STAT_SHIFT (15U) -/*! LPCG_OUT_REQUEST_STAT - Status of pin standby_lpcg_out_request - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_LPCG_OUT_REQUEST_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_LPCG_OUT_REQUEST_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_LPCG_OUT_REQUEST_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_LPCG_IN_DONE_STAT_MASK (0x10000U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_LPCG_IN_DONE_STAT_SHIFT (16U) -/*! LPCG_IN_DONE_STAT - Status of pin standby_pll_in_done - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_LPCG_IN_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_LPCG_IN_DONE_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_LPCG_IN_DONE_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_PLL_IN_DONE_STAT_MASK (0x20000U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_PLL_IN_DONE_STAT_SHIFT (17U) -/*! PLL_IN_DONE_STAT - Status of pin standby_pll_in_done - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_PLL_IN_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_PLL_IN_DONE_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_PLL_IN_DONE_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_BIAS_IN_DONE_STAT_MASK (0x40000U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_BIAS_IN_DONE_STAT_SHIFT (18U) -/*! BIAS_IN_DONE_STAT - Status of pin standby_bias_in_done - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_BIAS_IN_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_BIAS_IN_DONE_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_BIAS_IN_DONE_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_PLDO_IN_DONE_STAT_MASK (0x80000U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_PLDO_IN_DONE_STAT_SHIFT (19U) -/*! PLDO_IN_DONE_STAT - Status of pin standby_pldo_in_done - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_PLDO_IN_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_PLDO_IN_DONE_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_PLDO_IN_DONE_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_BANDGAP_IN_DONE_STAT_MASK (0x100000U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_BANDGAP_IN_DONE_STAT_SHIFT (20U) -/*! BANDGAP_IN_DONE_STAT - Status of pin standby_bandgap_in_done - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_BANDGAP_IN_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_BANDGAP_IN_DONE_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_BANDGAP_IN_DONE_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_LDO_IN_DONE_STAT_MASK (0x200000U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_LDO_IN_DONE_STAT_SHIFT (21U) -/*! LDO_IN_DONE_STAT - Status of pin standby_ldo_in_done - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_LDO_IN_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_LDO_IN_DONE_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_LDO_IN_DONE_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_DCDC_IN_DONE_STAT_MASK (0x400000U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_DCDC_IN_DONE_STAT_SHIFT (22U) -/*! DCDC_IN_DONE_STAT - Status of pin standby_dcdc_in_done - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_DCDC_IN_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_DCDC_IN_DONE_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_DCDC_IN_DONE_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_PMIC_IN_DONE_STAT_MASK (0x800000U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_PMIC_IN_DONE_STAT_SHIFT (23U) -/*! PMIC_IN_DONE_STAT - Status of pin standby_pmic_in_done - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_PMIC_IN_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_PMIC_IN_DONE_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_PMIC_IN_DONE_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_PMIC_OUT_DONE_STAT_MASK (0x1000000U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_PMIC_OUT_DONE_STAT_SHIFT (24U) -/*! PMIC_OUT_DONE_STAT - Status of pin standby_pmic_out_done - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_PMIC_OUT_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_PMIC_OUT_DONE_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_PMIC_OUT_DONE_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_DCDC_OUT_DONE_STAT_MASK (0x2000000U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_DCDC_OUT_DONE_STAT_SHIFT (25U) -/*! DCDC_OUT_DONE_STAT - Status of pin standby_dcdc_out_done - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_DCDC_OUT_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_DCDC_OUT_DONE_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_DCDC_OUT_DONE_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_LDO_OUT_DONE_STAT_MASK (0x4000000U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_LDO_OUT_DONE_STAT_SHIFT (26U) -/*! LDO_OUT_DONE_STAT - Status of pin standby_ldo_out_done - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_LDO_OUT_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_LDO_OUT_DONE_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_LDO_OUT_DONE_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_BANDGAP_OUT_DONE_STAT_MASK (0x8000000U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_BANDGAP_OUT_DONE_STAT_SHIFT (27U) -/*! BANDGAP_OUT_DONE_STAT - Status of pin standby_bandgap_out_done - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_BANDGAP_OUT_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_BANDGAP_OUT_DONE_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_BANDGAP_OUT_DONE_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_PLDO_OUT_DONE_STAT_MASK (0x10000000U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_PLDO_OUT_DONE_STAT_SHIFT (28U) -/*! PLDO_OUT_DONE_STAT - Status of pin standby_pldo_out_done - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_PLDO_OUT_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_PLDO_OUT_DONE_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_PLDO_OUT_DONE_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_BIAS_OUT_DONE_STAT_MASK (0x20000000U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_BIAS_OUT_DONE_STAT_SHIFT (29U) -/*! BIAS_OUT_DONE_STAT - Status of pin standby_bias_out_done - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_BIAS_OUT_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_BIAS_OUT_DONE_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_BIAS_OUT_DONE_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_PLL_OUT_DONE_STAT_MASK (0x40000000U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_PLL_OUT_DONE_STAT_SHIFT (30U) -/*! PLL_OUT_DONE_STAT - Status of pin standby_pll_out_done - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_PLL_OUT_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_PLL_OUT_DONE_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_PLL_OUT_DONE_STAT_MASK) -#define GPC_STBY_CTRL_STBY_PIN_STAT_LPCG_OUT_DONE_STAT_MASK (0x80000000U) -#define GPC_STBY_CTRL_STBY_PIN_STAT_LPCG_OUT_DONE_STAT_SHIFT (31U) -/*! LPCG_OUT_DONE_STAT - Status of pin standby_lpcg_out_done - */ -#define GPC_STBY_CTRL_STBY_PIN_STAT_LPCG_OUT_DONE_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PIN_STAT_LPCG_OUT_DONE_STAT_SHIFT)) & GPC_STBY_CTRL_STBY_PIN_STAT_LPCG_OUT_DONE_STAT_MASK) -/*! @} */ - /*! @name STBY_LPCG_IN_CTRL - STBY lpcg_in control */ /*! @{ */ + #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_MASK) + #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -45682,6 +53921,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_MASK) + #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_MASK (0x80000000U) #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -45689,22 +53929,15 @@ typedef struct { #define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_MASK) /*! @} */ -/*! @name STBY_LPCG_IN_STAT - STBY pll_in status */ -/*! @{ */ -#define GPC_STBY_CTRL_STBY_LPCG_IN_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_STBY_CTRL_STBY_LPCG_IN_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_STBY_CTRL_STBY_LPCG_IN_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_IN_STAT_RSP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_IN_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name STBY_PLL_IN_CTRL - STBY pll_in control */ /*! @{ */ + #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_MASK) + #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -45714,6 +53947,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_MASK) + #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE_MASK (0x80000000U) #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -45721,22 +53955,15 @@ typedef struct { #define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE_MASK) /*! @} */ -/*! @name STBY_PLL_IN_STAT - STBY pll_in status */ -/*! @{ */ -#define GPC_STBY_CTRL_STBY_PLL_IN_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_STBY_CTRL_STBY_PLL_IN_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_STBY_CTRL_STBY_PLL_IN_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_IN_STAT_RSP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_IN_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name STBY_BIAS_IN_CTRL - STBY bias_in control */ /*! @{ */ + #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_MASK) + #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -45746,6 +53973,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_MASK) + #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE_MASK (0x80000000U) #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -45753,22 +53981,15 @@ typedef struct { #define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE_MASK) /*! @} */ -/*! @name STBY_BIAS_IN_STAT - STBY bias_in status */ -/*! @{ */ -#define GPC_STBY_CTRL_STBY_BIAS_IN_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_STBY_CTRL_STBY_BIAS_IN_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_STBY_CTRL_STBY_BIAS_IN_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_IN_STAT_RSP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_IN_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name STBY_PLDO_IN_CTRL - STBY pldo_in control */ /*! @{ */ + #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_MASK) + #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -45778,6 +53999,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_MASK) + #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE_MASK (0x80000000U) #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -45785,22 +54007,15 @@ typedef struct { #define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE_MASK) /*! @} */ -/*! @name STBY_PLDO_IN_STAT - STBY pldo_in status */ -/*! @{ */ -#define GPC_STBY_CTRL_STBY_PLDO_IN_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_STBY_CTRL_STBY_PLDO_IN_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_STBY_CTRL_STBY_PLDO_IN_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_IN_STAT_RSP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_IN_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name STBY_BANDGAP_IN_CTRL - STBY bandgap_in control */ /*! @{ */ + #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_MASK) + #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -45810,6 +54025,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_MASK) + #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE_MASK (0x80000000U) #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -45817,22 +54033,15 @@ typedef struct { #define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE_MASK) /*! @} */ -/*! @name STBY_BANDGAP_IN_STAT - STBY bandgap_in status */ -/*! @{ */ -#define GPC_STBY_CTRL_STBY_BANDGAP_IN_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_STBY_CTRL_STBY_BANDGAP_IN_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_STBY_CTRL_STBY_BANDGAP_IN_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_IN_STAT_RSP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_IN_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name STBY_LDO_IN_CTRL - STBY ldo_in control */ /*! @{ */ + #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_MASK) + #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -45842,6 +54051,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_MASK) + #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE_MASK (0x80000000U) #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -45849,22 +54059,15 @@ typedef struct { #define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE_MASK) /*! @} */ -/*! @name STBY_LDO_IN_STAT - STBY ldo_in status */ -/*! @{ */ -#define GPC_STBY_CTRL_STBY_LDO_IN_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_STBY_CTRL_STBY_LDO_IN_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_STBY_CTRL_STBY_LDO_IN_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_IN_STAT_RSP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_IN_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name STBY_DCDC_IN_CTRL - STBY dcdc_in control */ /*! @{ */ + #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_MASK) + #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -45874,6 +54077,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_MASK) + #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE_MASK (0x80000000U) #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -45881,22 +54085,15 @@ typedef struct { #define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE_MASK) /*! @} */ -/*! @name STBY_DCDC_IN_STAT - STBY dcdc_in status */ -/*! @{ */ -#define GPC_STBY_CTRL_STBY_DCDC_IN_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_STBY_CTRL_STBY_DCDC_IN_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_STBY_CTRL_STBY_DCDC_IN_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_IN_STAT_RSP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_IN_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name STBY_PMIC_IN_CTRL - STBY PMIC in control */ /*! @{ */ + #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_MASK) + #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -45906,6 +54103,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_MASK) + #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE_MASK (0x80000000U) #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -45913,22 +54111,15 @@ typedef struct { #define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE_MASK) /*! @} */ -/*! @name STBY_PMIC_IN_STAT - STBY PMIC in status */ -/*! @{ */ -#define GPC_STBY_CTRL_STBY_PMIC_IN_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_STBY_CTRL_STBY_PMIC_IN_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_STBY_CTRL_STBY_PMIC_IN_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_IN_STAT_RSP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_IN_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name STBY_PMIC_OUT_CTRL - STBY PMIC out control */ /*! @{ */ + #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_MASK) + #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -45938,6 +54129,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_MASK) + #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE_MASK (0x80000000U) #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -45945,22 +54137,15 @@ typedef struct { #define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE_MASK) /*! @} */ -/*! @name STBY_PMIC_OUT_STAT - STBY PMIC out status */ -/*! @{ */ -#define GPC_STBY_CTRL_STBY_PMIC_OUT_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_STBY_CTRL_STBY_PMIC_OUT_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_STBY_CTRL_STBY_PMIC_OUT_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_OUT_STAT_RSP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_OUT_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name STBY_DCDC_OUT_CTRL - STBY DCDC out control */ /*! @{ */ + #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_MASK) + #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -45970,6 +54155,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_MASK) + #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE_MASK (0x80000000U) #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -45977,22 +54163,15 @@ typedef struct { #define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE_MASK) /*! @} */ -/*! @name STBY_DCDC_OUT_STAT - STBY DCDC out status */ -/*! @{ */ -#define GPC_STBY_CTRL_STBY_DCDC_OUT_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_STBY_CTRL_STBY_DCDC_OUT_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_STBY_CTRL_STBY_DCDC_OUT_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_OUT_STAT_RSP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_OUT_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name STBY_LDO_OUT_CTRL - STBY LDO out control */ /*! @{ */ + #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_MASK) + #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -46002,6 +54181,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_MASK) + #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE_MASK (0x80000000U) #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -46009,22 +54189,15 @@ typedef struct { #define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE_MASK) /*! @} */ -/*! @name STBY_LDO_OUT_STAT - STBY LDO out status */ -/*! @{ */ -#define GPC_STBY_CTRL_STBY_LDO_OUT_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_STBY_CTRL_STBY_LDO_OUT_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_STBY_CTRL_STBY_LDO_OUT_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_OUT_STAT_RSP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_OUT_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name STBY_BANDGAP_OUT_CTRL - STBY bandgap out control */ /*! @{ */ + #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_MASK) + #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -46034,6 +54207,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_MASK) + #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE_MASK (0x80000000U) #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -46041,22 +54215,15 @@ typedef struct { #define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE_MASK) /*! @} */ -/*! @name STBY_BANDGAP_OUT_STAT - STBY BANDGAP out status */ -/*! @{ */ -#define GPC_STBY_CTRL_STBY_BANDGAP_OUT_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_STBY_CTRL_STBY_BANDGAP_OUT_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_STBY_CTRL_STBY_BANDGAP_OUT_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_OUT_STAT_RSP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_OUT_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name STBY_PLDO_OUT_CTRL - STBY pldo out control */ /*! @{ */ + #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_MASK) + #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -46066,6 +54233,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_MASK) + #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE_MASK (0x80000000U) #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -46073,22 +54241,15 @@ typedef struct { #define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE_MASK) /*! @} */ -/*! @name STBY_PLDO_OUT_STAT - STBY PLDO out status */ -/*! @{ */ -#define GPC_STBY_CTRL_STBY_PLDO_OUT_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_STBY_CTRL_STBY_PLDO_OUT_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_STBY_CTRL_STBY_PLDO_OUT_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_OUT_STAT_RSP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_OUT_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name STBY_BIAS_OUT_CTRL - STBY bias out control */ /*! @{ */ + #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_MASK) + #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -46098,6 +54259,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_MASK) + #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE_MASK (0x80000000U) #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -46105,22 +54267,15 @@ typedef struct { #define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE_MASK) /*! @} */ -/*! @name STBY_BIAS_OUT_STAT - STBY bias out status */ -/*! @{ */ -#define GPC_STBY_CTRL_STBY_BIAS_OUT_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_STBY_CTRL_STBY_BIAS_OUT_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_STBY_CTRL_STBY_BIAS_OUT_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_OUT_STAT_RSP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_OUT_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name STBY_PLL_OUT_CTRL - STBY PLL out control */ /*! @{ */ + #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_MASK) + #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -46130,6 +54285,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_MASK) + #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE_MASK (0x80000000U) #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -46137,22 +54293,15 @@ typedef struct { #define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE_MASK) /*! @} */ -/*! @name STBY_PLL_OUT_STAT - STBY PLL out status */ -/*! @{ */ -#define GPC_STBY_CTRL_STBY_PLL_OUT_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_STBY_CTRL_STBY_PLL_OUT_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_STBY_CTRL_STBY_PLL_OUT_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_OUT_STAT_RSP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_OUT_STAT_RSP_CNT_MASK) -/*! @} */ - /*! @name STBY_LPCG_OUT_CTRL - STBY LPCG out control */ /*! @{ */ + #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_MASK (0xFFFFU) #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_SHIFT (0U) /*! STEP_CNT - Step count, useage is depending on CNT_MODE */ #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_MASK) + #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_MASK (0x30000000U) #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_SHIFT (28U) /*! CNT_MODE - Count mode @@ -46162,6 +54311,7 @@ typedef struct { * 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value */ #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_MASK) + #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE_MASK (0x80000000U) #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE_SHIFT (31U) /*! DISABLE - Disable this step @@ -46169,15 +54319,6 @@ typedef struct { #define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE_MASK) /*! @} */ -/*! @name STBY_LPCG_OUT_STAT - STBY LPCG out status */ -/*! @{ */ -#define GPC_STBY_CTRL_STBY_LPCG_OUT_STAT_RSP_CNT_MASK (0xFFFFU) -#define GPC_STBY_CTRL_STBY_LPCG_OUT_STAT_RSP_CNT_SHIFT (0U) -/*! RSP_CNT - Response count, record the delay from step start to step_done received - */ -#define GPC_STBY_CTRL_STBY_LPCG_OUT_STAT_RSP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_OUT_STAT_RSP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_OUT_STAT_RSP_CNT_MASK) -/*! @} */ - /*! * @} @@ -46235,377 +54376,418 @@ typedef struct { /*! @name DR - GPIO data register */ /*! @{ */ + #define GPIO_DR_DR_MASK (0xFFFFFFFFU) #define GPIO_DR_DR_SHIFT (0U) -/*! DR - DR +/*! DR - DR data bits */ #define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK) /*! @} */ /*! @name GDIR - GPIO direction register */ /*! @{ */ + #define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU) #define GPIO_GDIR_GDIR_SHIFT (0U) -/*! GDIR - GDIR +/*! GDIR - GPIO direction bits */ #define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK) /*! @} */ /*! @name PSR - GPIO pad status register */ /*! @{ */ + #define GPIO_PSR_PSR_MASK (0xFFFFFFFFU) #define GPIO_PSR_PSR_SHIFT (0U) -/*! PSR - PSR +/*! PSR - GPIO pad status bits */ #define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK) /*! @} */ /*! @name ICR1 - GPIO interrupt configuration register1 */ /*! @{ */ + #define GPIO_ICR1_ICR0_MASK (0x3U) #define GPIO_ICR1_ICR0_SHIFT (0U) -/*! ICR0 - ICR0 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR0 - Interrupt configuration field for GPIO interrupt 0 + * 0b00..Interrupt 0 is low-level sensitive. + * 0b01..Interrupt 0 is high-level sensitive. + * 0b10..Interrupt 0 is rising-edge sensitive. + * 0b11..Interrupt 0 is falling-edge sensitive. */ #define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK) + #define GPIO_ICR1_ICR1_MASK (0xCU) #define GPIO_ICR1_ICR1_SHIFT (2U) -/*! ICR1 - ICR1 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR1 - Interrupt configuration field for GPIO interrupt 1 + * 0b00..Interrupt 1 is low-level sensitive. + * 0b01..Interrupt 1 is high-level sensitive. + * 0b10..Interrupt 1 is rising-edge sensitive. + * 0b11..Interrupt 1 is falling-edge sensitive. */ #define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK) + #define GPIO_ICR1_ICR2_MASK (0x30U) #define GPIO_ICR1_ICR2_SHIFT (4U) -/*! ICR2 - ICR2 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR2 - Interrupt configuration field for GPIO interrupt 2 + * 0b00..Interrupt 2 is low-level sensitive. + * 0b01..Interrupt 2 is high-level sensitive. + * 0b10..Interrupt 2 is rising-edge sensitive. + * 0b11..Interrupt 2 is falling-edge sensitive. */ #define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK) + #define GPIO_ICR1_ICR3_MASK (0xC0U) #define GPIO_ICR1_ICR3_SHIFT (6U) -/*! ICR3 - ICR3 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR3 - Interrupt configuration field for GPIO interrupt 3 + * 0b00..Interrupt 3 is low-level sensitive. + * 0b01..Interrupt 3 is high-level sensitive. + * 0b10..Interrupt 3 is rising-edge sensitive. + * 0b11..Interrupt 3 is falling-edge sensitive. */ #define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK) + #define GPIO_ICR1_ICR4_MASK (0x300U) #define GPIO_ICR1_ICR4_SHIFT (8U) -/*! ICR4 - ICR4 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR4 - Interrupt configuration field for GPIO interrupt 4 + * 0b00..Interrupt 4 is low-level sensitive. + * 0b01..Interrupt 4 is high-level sensitive. + * 0b10..Interrupt 4 is rising-edge sensitive. + * 0b11..Interrupt 4 is falling-edge sensitive. */ #define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK) + #define GPIO_ICR1_ICR5_MASK (0xC00U) #define GPIO_ICR1_ICR5_SHIFT (10U) -/*! ICR5 - ICR5 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR5 - Interrupt configuration field for GPIO interrupt 5 + * 0b00..Interrupt 5 is low-level sensitive. + * 0b01..Interrupt 5 is high-level sensitive. + * 0b10..Interrupt 5 is rising-edge sensitive. + * 0b11..Interrupt 5 is falling-edge sensitive. */ #define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK) + #define GPIO_ICR1_ICR6_MASK (0x3000U) #define GPIO_ICR1_ICR6_SHIFT (12U) -/*! ICR6 - ICR6 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR6 - Interrupt configuration field for GPIO interrupt 6 + * 0b00..Interrupt 6 is low-level sensitive. + * 0b01..Interrupt 6 is high-level sensitive. + * 0b10..Interrupt 6 is rising-edge sensitive. + * 0b11..Interrupt 6 is falling-edge sensitive. */ #define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK) + #define GPIO_ICR1_ICR7_MASK (0xC000U) #define GPIO_ICR1_ICR7_SHIFT (14U) -/*! ICR7 - ICR7 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR7 - Interrupt configuration field for GPIO interrupt 7 + * 0b00..Interrupt 7 is low-level sensitive. + * 0b01..Interrupt 7 is high-level sensitive. + * 0b10..Interrupt 7 is rising-edge sensitive. + * 0b11..Interrupt 7 is falling-edge sensitive. */ #define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK) + #define GPIO_ICR1_ICR8_MASK (0x30000U) #define GPIO_ICR1_ICR8_SHIFT (16U) -/*! ICR8 - ICR8 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR8 - Interrupt configuration field for GPIO interrupt 8 + * 0b00..Interrupt 8 is low-level sensitive. + * 0b01..Interrupt 8 is high-level sensitive. + * 0b10..Interrupt 8 is rising-edge sensitive. + * 0b11..Interrupt 8 is falling-edge sensitive. */ #define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK) + #define GPIO_ICR1_ICR9_MASK (0xC0000U) #define GPIO_ICR1_ICR9_SHIFT (18U) -/*! ICR9 - ICR9 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR9 - Interrupt configuration field for GPIO interrupt 9 + * 0b00..Interrupt 9 is low-level sensitive. + * 0b01..Interrupt 9 is high-level sensitive. + * 0b10..Interrupt 9 is rising-edge sensitive. + * 0b11..Interrupt 9 is falling-edge sensitive. */ #define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK) + #define GPIO_ICR1_ICR10_MASK (0x300000U) #define GPIO_ICR1_ICR10_SHIFT (20U) -/*! ICR10 - ICR10 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR10 - Interrupt configuration field for GPIO interrupt 10 + * 0b00..Interrupt 10 is low-level sensitive. + * 0b01..Interrupt 10 is high-level sensitive. + * 0b10..Interrupt 10 is rising-edge sensitive. + * 0b11..Interrupt 10 is falling-edge sensitive. */ #define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK) + #define GPIO_ICR1_ICR11_MASK (0xC00000U) #define GPIO_ICR1_ICR11_SHIFT (22U) -/*! ICR11 - ICR11 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR11 - Interrupt configuration field for GPIO interrupt 11 + * 0b00..Interrupt 11 is low-level sensitive. + * 0b01..Interrupt 11 is high-level sensitive. + * 0b10..Interrupt 11 is rising-edge sensitive. + * 0b11..Interrupt 11 is falling-edge sensitive. */ #define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK) + #define GPIO_ICR1_ICR12_MASK (0x3000000U) #define GPIO_ICR1_ICR12_SHIFT (24U) -/*! ICR12 - ICR12 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR12 - Interrupt configuration field for GPIO interrupt 12 + * 0b00..Interrupt 12 is low-level sensitive. + * 0b01..Interrupt 12 is high-level sensitive. + * 0b10..Interrupt 12 is rising-edge sensitive. + * 0b11..Interrupt 12 is falling-edge sensitive. */ #define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK) + #define GPIO_ICR1_ICR13_MASK (0xC000000U) #define GPIO_ICR1_ICR13_SHIFT (26U) -/*! ICR13 - ICR13 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR13 - Interrupt configuration field for GPIO interrupt 13 + * 0b00..Interrupt 13 is low-level sensitive. + * 0b01..Interrupt 13 is high-level sensitive. + * 0b10..Interrupt 13 is rising-edge sensitive. + * 0b11..Interrupt 13 is falling-edge sensitive. */ #define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK) + #define GPIO_ICR1_ICR14_MASK (0x30000000U) #define GPIO_ICR1_ICR14_SHIFT (28U) -/*! ICR14 - ICR14 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR14 - Interrupt configuration field for GPIO interrupt 14 + * 0b00..Interrupt 14 is low-level sensitive. + * 0b01..Interrupt 14 is high-level sensitive. + * 0b10..Interrupt 14 is rising-edge sensitive. + * 0b11..Interrupt 14 is falling-edge sensitive. */ #define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK) + #define GPIO_ICR1_ICR15_MASK (0xC0000000U) #define GPIO_ICR1_ICR15_SHIFT (30U) -/*! ICR15 - ICR15 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR15 - Interrupt configuration field for GPIO interrupt 15 + * 0b00..Interrupt 15 is low-level sensitive. + * 0b01..Interrupt 15 is high-level sensitive. + * 0b10..Interrupt 15 is rising-edge sensitive. + * 0b11..Interrupt 15 is falling-edge sensitive. */ #define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK) /*! @} */ /*! @name ICR2 - GPIO interrupt configuration register2 */ /*! @{ */ + #define GPIO_ICR2_ICR16_MASK (0x3U) #define GPIO_ICR2_ICR16_SHIFT (0U) -/*! ICR16 - ICR16 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR16 - Interrupt configuration field for GPIO interrupt 16 + * 0b00..Interrupt 16 is low-level sensitive. + * 0b01..Interrupt 16 is high-level sensitive. + * 0b10..Interrupt 16 is rising-edge sensitive. + * 0b11..Interrupt 16 is falling-edge sensitive. */ #define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK) + #define GPIO_ICR2_ICR17_MASK (0xCU) #define GPIO_ICR2_ICR17_SHIFT (2U) -/*! ICR17 - ICR17 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR17 - Interrupt configuration field for GPIO interrupt 17 + * 0b00..Interrupt 17 is low-level sensitive. + * 0b01..Interrupt 17 is high-level sensitive. + * 0b10..Interrupt 17 is rising-edge sensitive. + * 0b11..Interrupt 17 is falling-edge sensitive. */ #define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK) + #define GPIO_ICR2_ICR18_MASK (0x30U) #define GPIO_ICR2_ICR18_SHIFT (4U) -/*! ICR18 - ICR18 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR18 - Interrupt configuration field for GPIO interrupt 18 + * 0b00..Interrupt 18 is low-level sensitive. + * 0b01..Interrupt 18 is high-level sensitive. + * 0b10..Interrupt 18 is rising-edge sensitive. + * 0b11..Interrupt 18 is falling-edge sensitive. */ #define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK) + #define GPIO_ICR2_ICR19_MASK (0xC0U) #define GPIO_ICR2_ICR19_SHIFT (6U) -/*! ICR19 - ICR19 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR19 - Interrupt configuration field for GPIO interrupt 19 + * 0b00..Interrupt 19 is low-level sensitive. + * 0b01..Interrupt 19 is high-level sensitive. + * 0b10..Interrupt 19 is rising-edge sensitive. + * 0b11..Interrupt 19 is falling-edge sensitive. */ #define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK) + #define GPIO_ICR2_ICR20_MASK (0x300U) #define GPIO_ICR2_ICR20_SHIFT (8U) -/*! ICR20 - ICR20 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR20 - Interrupt configuration field for GPIO interrupt 20 + * 0b00..Interrupt 20 is low-level sensitive. + * 0b01..Interrupt 20 is high-level sensitive. + * 0b10..Interrupt 20 is rising-edge sensitive. + * 0b11..Interrupt 20 is falling-edge sensitive. */ #define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK) + #define GPIO_ICR2_ICR21_MASK (0xC00U) #define GPIO_ICR2_ICR21_SHIFT (10U) -/*! ICR21 - ICR21 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR21 - Interrupt configuration field for GPIO interrupt 21 + * 0b00..Interrupt 21 is low-level sensitive. + * 0b01..Interrupt 21 is high-level sensitive. + * 0b10..Interrupt 21 is rising-edge sensitive. + * 0b11..Interrupt 21 is falling-edge sensitive. */ #define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK) + #define GPIO_ICR2_ICR22_MASK (0x3000U) #define GPIO_ICR2_ICR22_SHIFT (12U) -/*! ICR22 - ICR22 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR22 - Interrupt configuration field for GPIO interrupt 22 + * 0b00..Interrupt 22 is low-level sensitive. + * 0b01..Interrupt 22 is high-level sensitive. + * 0b10..Interrupt 22 is rising-edge sensitive. + * 0b11..Interrupt 22 is falling-edge sensitive. */ #define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK) + #define GPIO_ICR2_ICR23_MASK (0xC000U) #define GPIO_ICR2_ICR23_SHIFT (14U) -/*! ICR23 - ICR23 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR23 - Interrupt configuration field for GPIO interrupt 23 + * 0b00..Interrupt 23 is low-level sensitive. + * 0b01..Interrupt 23 is high-level sensitive. + * 0b10..Interrupt 23 is rising-edge sensitive. + * 0b11..Interrupt 23 is falling-edge sensitive. */ #define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK) + #define GPIO_ICR2_ICR24_MASK (0x30000U) #define GPIO_ICR2_ICR24_SHIFT (16U) -/*! ICR24 - ICR24 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR24 - Interrupt configuration field for GPIO interrupt 24 + * 0b00..Interrupt 24 is low-level sensitive. + * 0b01..Interrupt 24 is high-level sensitive. + * 0b10..Interrupt 24 is rising-edge sensitive. + * 0b11..Interrupt 24 is falling-edge sensitive. */ #define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK) + #define GPIO_ICR2_ICR25_MASK (0xC0000U) #define GPIO_ICR2_ICR25_SHIFT (18U) -/*! ICR25 - ICR25 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR25 - Interrupt configuration field for GPIO interrupt 25 + * 0b00..Interrupt 25 is low-level sensitive. + * 0b01..Interrupt 25 is high-level sensitive. + * 0b10..Interrupt 25 is rising-edge sensitive. + * 0b11..Interrupt 25 is falling-edge sensitive. */ #define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK) + #define GPIO_ICR2_ICR26_MASK (0x300000U) #define GPIO_ICR2_ICR26_SHIFT (20U) -/*! ICR26 - ICR26 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR26 - Interrupt configuration field for GPIO interrupt 26 + * 0b00..Interrupt 26 is low-level sensitive. + * 0b01..Interrupt 26 is high-level sensitive. + * 0b10..Interrupt 26 is rising-edge sensitive. + * 0b11..Interrupt 26 is falling-edge sensitive. */ #define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK) + #define GPIO_ICR2_ICR27_MASK (0xC00000U) #define GPIO_ICR2_ICR27_SHIFT (22U) -/*! ICR27 - ICR27 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR27 - Interrupt configuration field for GPIO interrupt 27 + * 0b00..Interrupt 27 is low-level sensitive. + * 0b01..Interrupt 27 is high-level sensitive. + * 0b10..Interrupt 27 is rising-edge sensitive. + * 0b11..Interrupt 27 is falling-edge sensitive. */ #define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK) + #define GPIO_ICR2_ICR28_MASK (0x3000000U) #define GPIO_ICR2_ICR28_SHIFT (24U) -/*! ICR28 - ICR28 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR28 - Interrupt configuration field for GPIO interrupt 28 + * 0b00..Interrupt 28 is low-level sensitive. + * 0b01..Interrupt 28 is high-level sensitive. + * 0b10..Interrupt 28 is rising-edge sensitive. + * 0b11..Interrupt 28 is falling-edge sensitive. */ #define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK) + #define GPIO_ICR2_ICR29_MASK (0xC000000U) #define GPIO_ICR2_ICR29_SHIFT (26U) -/*! ICR29 - ICR29 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR29 - Interrupt configuration field for GPIO interrupt 29 + * 0b00..Interrupt 29 is low-level sensitive. + * 0b01..Interrupt 29 is high-level sensitive. + * 0b10..Interrupt 29 is rising-edge sensitive. + * 0b11..Interrupt 29 is falling-edge sensitive. */ #define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK) + #define GPIO_ICR2_ICR30_MASK (0x30000000U) #define GPIO_ICR2_ICR30_SHIFT (28U) -/*! ICR30 - ICR30 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR30 - Interrupt configuration field for GPIO interrupt 30 + * 0b00..Interrupt 30 is low-level sensitive. + * 0b01..Interrupt 30 is high-level sensitive. + * 0b10..Interrupt 30 is rising-edge sensitive. + * 0b11..Interrupt 30 is falling-edge sensitive. */ #define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK) + #define GPIO_ICR2_ICR31_MASK (0xC0000000U) #define GPIO_ICR2_ICR31_SHIFT (30U) -/*! ICR31 - ICR31 - * 0b00..Interrupt n is low-level sensitive. - * 0b01..Interrupt n is high-level sensitive. - * 0b10..Interrupt n is rising-edge sensitive. - * 0b11..Interrupt n is falling-edge sensitive. +/*! ICR31 - Interrupt configuration field for GPIO interrupt 31 + * 0b00..Interrupt 31 is low-level sensitive. + * 0b01..Interrupt 31 is high-level sensitive. + * 0b10..Interrupt 31 is rising-edge sensitive. + * 0b11..Interrupt 31 is falling-edge sensitive. */ #define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK) /*! @} */ /*! @name IMR - GPIO interrupt mask register */ /*! @{ */ + #define GPIO_IMR_IMR_MASK (0xFFFFFFFFU) #define GPIO_IMR_IMR_SHIFT (0U) -/*! IMR - IMR +/*! IMR - Interrupt Mask bits */ #define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK) /*! @} */ /*! @name ISR - GPIO interrupt status register */ /*! @{ */ + #define GPIO_ISR_ISR_MASK (0xFFFFFFFFU) #define GPIO_ISR_ISR_SHIFT (0U) -/*! ISR - ISR +/*! ISR - Interrupt status bits */ #define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK) /*! @} */ /*! @name EDGE_SEL - GPIO edge select register */ /*! @{ */ + #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU) #define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U) -/*! GPIO_EDGE_SEL - GPIO_EDGE_SEL +/*! GPIO_EDGE_SEL - Edge select */ #define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK) /*! @} */ /*! @name DR_SET - GPIO data register SET */ /*! @{ */ + #define GPIO_DR_SET_DR_SET_MASK (0xFFFFFFFFU) #define GPIO_DR_SET_DR_SET_SHIFT (0U) -/*! DR_SET - DR_SET +/*! DR_SET - Set */ #define GPIO_DR_SET_DR_SET(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK) /*! @} */ /*! @name DR_CLEAR - GPIO data register CLEAR */ /*! @{ */ + #define GPIO_DR_CLEAR_DR_CLEAR_MASK (0xFFFFFFFFU) #define GPIO_DR_CLEAR_DR_CLEAR_SHIFT (0U) -/*! DR_CLEAR - DR_CLEAR +/*! DR_CLEAR - Clear */ #define GPIO_DR_CLEAR_DR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK) /*! @} */ /*! @name DR_TOGGLE - GPIO data register TOGGLE */ /*! @{ */ + #define GPIO_DR_TOGGLE_DR_TOGGLE_MASK (0xFFFFFFFFU) #define GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT (0U) -/*! DR_TOGGLE - DR_TOGGLE +/*! DR_TOGGLE - Toggle */ #define GPIO_DR_TOGGLE_DR_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK) /*! @} */ @@ -46721,48 +54903,55 @@ typedef struct { /*! @name CR - GPT Control Register */ /*! @{ */ + #define GPT_CR_EN_MASK (0x1U) #define GPT_CR_EN_SHIFT (0U) /*! EN - GPT Enable - * 0b0..GPT is disabled. - * 0b1..GPT is enabled. + * 0b0..Disable + * 0b1..Enable */ #define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK) + #define GPT_CR_ENMOD_MASK (0x2U) #define GPT_CR_ENMOD_SHIFT (1U) /*! ENMOD - GPT Enable Mode - * 0b0..The Main Counter and Prescaler Counter restart counting from their frozen values after GPT is enabled (EN=1). - * 0b1..The Main Counter and Prescaler Counter values are reset to 0 after GPT is enabled (EN=1). + * 0b0..Restart counting from their frozen values after GPT is enabled (EN=1). + * 0b1..Reset counting from 0 after GPT is enabled (EN=1). */ #define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK) + #define GPT_CR_DBGEN_MASK (0x4U) #define GPT_CR_DBGEN_SHIFT (2U) /*! DBGEN - GPT Debug Mode Enable - * 0b0..GPT is disabled in Debug mode. - * 0b1..GPT is enabled in Debug mode. + * 0b0..Disable in Debug mode + * 0b1..Enable in Debug mode */ #define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK) + #define GPT_CR_WAITEN_MASK (0x8U) #define GPT_CR_WAITEN_SHIFT (3U) /*! WAITEN - GPT Wait Mode Enable - * 0b0..GPT is disabled in Wait mode. - * 0b1..GPT is enabled in Wait mode. + * 0b0..Disable in Wait mode + * 0b1..Enable in Wait mode */ #define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK) + #define GPT_CR_DOZEEN_MASK (0x10U) #define GPT_CR_DOZEEN_SHIFT (4U) /*! DOZEEN - GPT Doze Mode Enable - * 0b0..GPT is disabled in Doze mode. - * 0b1..GPT is enabled in Doze mode. + * 0b0..Disable in Doze mode + * 0b1..Enable in Doze mode */ #define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK) + #define GPT_CR_STOPEN_MASK (0x20U) #define GPT_CR_STOPEN_SHIFT (5U) /*! STOPEN - GPT Stop Mode Enable - * 0b0..GPT is disabled in Stop mode. - * 0b1..GPT is enabled in Stop mode. + * 0b0..Disable in Stop mode + * 0b1..Enable in Stop mode */ #define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK) + #define GPT_CR_CLKSRC_MASK (0x1C0U) #define GPT_CR_CLKSRC_SHIFT (6U) /*! CLKSRC - Clock Source Select @@ -46771,9 +54960,10 @@ typedef struct { * 0b010..High Frequency Reference Clock (ipg_clk_highfreq) * 0b011..External Clock * 0b100..Low Frequency Reference Clock (ipg_clk_32k) - * 0b101..Crystal oscillator as Reference Clock (ipg_clk_24M) + * 0b101..Oscillator as Reference Clock (ipg_clk_16M) */ #define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK) + #define GPT_CR_FRR_MASK (0x200U) #define GPT_CR_FRR_SHIFT (9U) /*! FRR - Free-Run or Restart Mode @@ -46781,13 +54971,15 @@ typedef struct { * 0b1..Free-Run mode. After a compare event, the counter continues counting until 0xFFFF_FFFF and then rolls over to 0. */ #define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK) + #define GPT_CR_EN_24M_MASK (0x400U) #define GPT_CR_EN_24M_SHIFT (10U) -/*! EN_24M - Enable 24 MHz Clock Input - * 0b0..24-MHz clock disabled - * 0b1..24-MHz clock enabled +/*! EN_24M - Enable Oscillator Clock Input + * 0b0..Disable + * 0b1..Enable */ #define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK) + #define GPT_CR_SWR_MASK (0x8000U) #define GPT_CR_SWR_SHIFT (15U) /*! SWR - Software Reset @@ -46795,6 +54987,7 @@ typedef struct { * 0b1..GPT is in software reset state */ #define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK) + #define GPT_CR_IM1_MASK (0x30000U) #define GPT_CR_IM1_SHIFT (16U) /*! IM1 - Input Capture Operating Mode for Channel 1 @@ -46804,6 +54997,7 @@ typedef struct { * 0b11..Capture on both edges */ #define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK) + #define GPT_CR_IM2_MASK (0xC0000U) #define GPT_CR_IM2_SHIFT (18U) /*! IM2 - Input Capture Operating Mode for Channel 2 @@ -46813,6 +55007,7 @@ typedef struct { * 0b11..Capture on both edges */ #define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK) + #define GPT_CR_OM1_MASK (0x700000U) #define GPT_CR_OM1_SHIFT (20U) /*! OM1 - Output Compare Operating Mode for Channel 1 @@ -46825,6 +55020,7 @@ typedef struct { * "Input clock" here refers to the clock selected by the CLKSRC field of this register. */ #define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK) + #define GPT_CR_OM2_MASK (0x3800000U) #define GPT_CR_OM2_SHIFT (23U) /*! OM2 - Output Compare Operating Mode for Channel 2 @@ -46837,6 +55033,7 @@ typedef struct { * "Input clock" here refers to the clock selected by the CLKSRC field of this register. */ #define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK) + #define GPT_CR_OM3_MASK (0x1C000000U) #define GPT_CR_OM3_SHIFT (26U) /*! OM3 - Output Compare Operating Mode for Channel 3 @@ -46849,31 +55046,35 @@ typedef struct { * "Input clock" here refers to the clock selected by the CLKSRC field of this register. */ #define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK) + #define GPT_CR_FO1_MASK (0x20000000U) #define GPT_CR_FO1_SHIFT (29U) /*! FO1 - Force Output Compare for Channel 1 * 0b0..No effect - * 0b1..Trigger the programmed response on the pin. + * 0b1..Trigger the programmed response on the pin */ #define GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK) + #define GPT_CR_FO2_MASK (0x40000000U) #define GPT_CR_FO2_SHIFT (30U) /*! FO2 - Force Output Compare for Channel 2 * 0b0..No effect - * 0b1..Trigger the programmed response on the pin. + * 0b1..Trigger the programmed response on the pin */ #define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK) + #define GPT_CR_FO3_MASK (0x80000000U) #define GPT_CR_FO3_SHIFT (31U) /*! FO3 - Force Output Compare for Channel 3 * 0b0..No effect - * 0b1..Trigger the programmed response on the pin. + * 0b1..Trigger the programmed response on the pin */ #define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK) /*! @} */ /*! @name PR - GPT Prescaler Register */ /*! @{ */ + #define GPT_PR_PRESCALER_MASK (0xFFFU) #define GPT_PR_PRESCALER_SHIFT (0U) /*! PRESCALER - Prescaler divide value @@ -46882,9 +55083,10 @@ typedef struct { * 0b111111111111..Divide by 4096 */ #define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK) + #define GPT_PR_PRESCALER24M_MASK (0xF000U) #define GPT_PR_PRESCALER24M_SHIFT (12U) -/*! PRESCALER24M - Prescaler divide value for the 24 MHz crystal clock +/*! PRESCALER24M - Prescaler divide value for the oscillator clock * 0b0000..Divide by 1 * 0b0001..Divide by 2 * 0b1111..Divide by 16 @@ -46894,6 +55096,7 @@ typedef struct { /*! @name SR - GPT Status Register */ /*! @{ */ + #define GPT_SR_OF1_MASK (0x1U) #define GPT_SR_OF1_SHIFT (0U) /*! OF1 - Output Compare Flag for Channel 1 @@ -46901,6 +55104,7 @@ typedef struct { * 0b1..Compare event has occurred. */ #define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK) + #define GPT_SR_OF2_MASK (0x2U) #define GPT_SR_OF2_SHIFT (1U) /*! OF2 - Output Compare Flag for Channel 2 @@ -46908,6 +55112,7 @@ typedef struct { * 0b1..Compare event has occurred. */ #define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK) + #define GPT_SR_OF3_MASK (0x4U) #define GPT_SR_OF3_SHIFT (2U) /*! OF3 - Output Compare Flag for Channel 3 @@ -46915,6 +55120,7 @@ typedef struct { * 0b1..Compare event has occurred. */ #define GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK) + #define GPT_SR_IF1_MASK (0x8U) #define GPT_SR_IF1_SHIFT (3U) /*! IF1 - Input Capture Flag for Channel 1 @@ -46922,6 +55128,7 @@ typedef struct { * 0b1..Capture event has occurred. */ #define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK) + #define GPT_SR_IF2_MASK (0x10U) #define GPT_SR_IF2_SHIFT (4U) /*! IF2 - Input Capture Flag for Channel 2 @@ -46929,6 +55136,7 @@ typedef struct { * 0b1..Capture event has occurred. */ #define GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK) + #define GPT_SR_ROV_MASK (0x20U) #define GPT_SR_ROV_SHIFT (5U) /*! ROV - Rollover Flag @@ -46940,52 +55148,59 @@ typedef struct { /*! @name IR - GPT Interrupt Register */ /*! @{ */ + #define GPT_IR_OF1IE_MASK (0x1U) #define GPT_IR_OF1IE_SHIFT (0U) -/*! OF1IE - Output Compare for Channel 1 Interrupt Enable - * 0b0..Disable interrupt - * 0b1..Enable interrupt +/*! OF1IE - Output Compare Flag for Channel 1 Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK) + #define GPT_IR_OF2IE_MASK (0x2U) #define GPT_IR_OF2IE_SHIFT (1U) -/*! OF2IE - Output Compare for Channel 2 Interrupt Enable - * 0b0..Disable interrupt - * 0b1..Enable interrupt +/*! OF2IE - Output Compare Flag for Channel 2 Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK) + #define GPT_IR_OF3IE_MASK (0x4U) #define GPT_IR_OF3IE_SHIFT (2U) -/*! OF3IE - Output Compare for Channel 3 Interrupt Enable - * 0b0..Disable interrupt - * 0b1..Enable interrupt +/*! OF3IE - Output Compare Flag for Channel 3 Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK) + #define GPT_IR_IF1IE_MASK (0x8U) #define GPT_IR_IF1IE_SHIFT (3U) -/*! IF1IE - Input Capture for Channel 1 Interrupt Enable - * 0b0..Disable interrupt - * 0b1..Enable interrupt +/*! IF1IE - Input Capture Flag for Channel 1 Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK) + #define GPT_IR_IF2IE_MASK (0x10U) #define GPT_IR_IF2IE_SHIFT (4U) -/*! IF2IE - Input Capture for Channel 2 Interrupt Enable - * 0b0..Disable interrupt - * 0b1..Enable interrupt +/*! IF2IE - Input Capture Flag for Channel 2 Interrupt Enable + * 0b0..Disable + * 0b1..Enable */ #define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK) + #define GPT_IR_ROVIE_MASK (0x20U) #define GPT_IR_ROVIE_SHIFT (5U) /*! ROVIE - Rollover Interrupt Enable - * 0b0..Disable interrupt - * 0b1..Enable interrupt + * 0b0..Disable + * 0b1..Enable */ #define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK) /*! @} */ /*! @name OCR - GPT Output Compare Register */ /*! @{ */ + #define GPT_OCR_COMP_MASK (0xFFFFFFFFU) #define GPT_OCR_COMP_SHIFT (0U) /*! COMP - Compare Value @@ -46998,6 +55213,7 @@ typedef struct { /*! @name ICR - GPT Input Capture Register */ /*! @{ */ + #define GPT_ICR_CAPT_MASK (0xFFFFFFFFU) #define GPT_ICR_CAPT_SHIFT (0U) /*! CAPT - Capture Value @@ -47010,6 +55226,7 @@ typedef struct { /*! @name CNT - GPT Counter Register */ /*! @{ */ + #define GPT_CNT_COUNT_MASK (0xFFFFFFFFU) #define GPT_CNT_COUNT_SHIFT (0U) /*! COUNT - Counter Value @@ -47071,31 +55288,31 @@ typedef struct { /** I2S - Register Layout Typedef */ typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ - __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x8 */ - __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0xC */ - __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x10 */ - __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0x14 */ - __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x18 */ - __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x1C */ - __O uint32_t TDR[4]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */ + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ + __IO uint32_t TCSR; /**< Transmit Control, offset: 0x8 */ + __IO uint32_t TCR1; /**< Transmit Configuration 1, offset: 0xC */ + __IO uint32_t TCR2; /**< Transmit Configuration 2, offset: 0x10 */ + __IO uint32_t TCR3; /**< Transmit Configuration 3, offset: 0x14 */ + __IO uint32_t TCR4; /**< Transmit Configuration 4, offset: 0x18 */ + __IO uint32_t TCR5; /**< Transmit Configuration 5, offset: 0x1C */ + __O uint32_t TDR[4]; /**< Transmit Data, array offset: 0x20, array step: 0x4 */ uint8_t RESERVED_0[16]; - __I uint32_t TFR[4]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */ + __I uint32_t TFR[4]; /**< Transmit FIFO, array offset: 0x40, array step: 0x4 */ uint8_t RESERVED_1[16]; - __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */ + __IO uint32_t TMR; /**< Transmit Mask, offset: 0x60 */ uint8_t RESERVED_2[36]; - __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x88 */ - __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x8C */ - __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x90 */ - __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x94 */ - __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x98 */ - __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x9C */ - __I uint32_t RDR[4]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */ + __IO uint32_t RCSR; /**< Receive Control, offset: 0x88 */ + __IO uint32_t RCR1; /**< Receive Configuration 1, offset: 0x8C */ + __IO uint32_t RCR2; /**< Receive Configuration 2, offset: 0x90 */ + __IO uint32_t RCR3; /**< Receive Configuration 3, offset: 0x94 */ + __IO uint32_t RCR4; /**< Receive Configuration 4, offset: 0x98 */ + __IO uint32_t RCR5; /**< Receive Configuration 5, offset: 0x9C */ + __I uint32_t RDR[4]; /**< Receive Data, array offset: 0xA0, array step: 0x4 */ uint8_t RESERVED_3[16]; - __I uint32_t RFR[4]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */ + __I uint32_t RFR[4]; /**< Receive FIFO, array offset: 0xC0, array step: 0x4 */ uint8_t RESERVED_4[16]; - __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */ + __IO uint32_t RMR; /**< Receive Mask, offset: 0xE0 */ } I2S_Type; /* ---------------------------------------------------------------------------- @@ -47107,19 +55324,22 @@ typedef struct { * @{ */ -/*! @name VERID - Version ID Register */ +/*! @name VERID - Version ID */ /*! @{ */ + #define I2S_VERID_FEATURE_MASK (0xFFFFU) #define I2S_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number * 0b0000000000000000..Standard feature set. */ #define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK) + #define I2S_VERID_MINOR_MASK (0xFF0000U) #define I2S_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK) + #define I2S_VERID_MAJOR_MASK (0xFF000000U) #define I2S_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number @@ -47127,18 +55347,21 @@ typedef struct { #define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK) /*! @} */ -/*! @name PARAM - Parameter Register */ +/*! @name PARAM - Parameter */ /*! @{ */ + #define I2S_PARAM_DATALINE_MASK (0xFU) #define I2S_PARAM_DATALINE_SHIFT (0U) /*! DATALINE - Number of Datalines */ #define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK) + #define I2S_PARAM_FIFO_MASK (0xF00U) #define I2S_PARAM_FIFO_SHIFT (8U) /*! FIFO - FIFO Size */ #define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK) + #define I2S_PARAM_FRAME_MASK (0xF0000U) #define I2S_PARAM_FRAME_SHIFT (16U) /*! FRAME - Frame Size @@ -47146,8 +55369,9 @@ typedef struct { #define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK) /*! @} */ -/*! @name TCSR - SAI Transmit Control Register */ +/*! @name TCSR - Transmit Control */ /*! @{ */ + #define I2S_TCSR_FRDE_MASK (0x1U) #define I2S_TCSR_FRDE_SHIFT (0U) /*! FRDE - FIFO Request DMA Enable @@ -47155,6 +55379,7 @@ typedef struct { * 0b1..Enables the DMA request. */ #define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK) + #define I2S_TCSR_FWDE_MASK (0x2U) #define I2S_TCSR_FWDE_SHIFT (1U) /*! FWDE - FIFO Warning DMA Enable @@ -47162,6 +55387,7 @@ typedef struct { * 0b1..Enables the DMA request. */ #define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK) + #define I2S_TCSR_FRIE_MASK (0x100U) #define I2S_TCSR_FRIE_SHIFT (8U) /*! FRIE - FIFO Request Interrupt Enable @@ -47169,6 +55395,7 @@ typedef struct { * 0b1..Enables the interrupt. */ #define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK) + #define I2S_TCSR_FWIE_MASK (0x200U) #define I2S_TCSR_FWIE_SHIFT (9U) /*! FWIE - FIFO Warning Interrupt Enable @@ -47176,6 +55403,7 @@ typedef struct { * 0b1..Enables the interrupt. */ #define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK) + #define I2S_TCSR_FEIE_MASK (0x400U) #define I2S_TCSR_FEIE_SHIFT (10U) /*! FEIE - FIFO Error Interrupt Enable @@ -47183,6 +55411,7 @@ typedef struct { * 0b1..Enables the interrupt. */ #define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK) + #define I2S_TCSR_SEIE_MASK (0x800U) #define I2S_TCSR_SEIE_SHIFT (11U) /*! SEIE - Sync Error Interrupt Enable @@ -47190,6 +55419,7 @@ typedef struct { * 0b1..Enables interrupt. */ #define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK) + #define I2S_TCSR_WSIE_MASK (0x1000U) #define I2S_TCSR_WSIE_SHIFT (12U) /*! WSIE - Word Start Interrupt Enable @@ -47197,6 +55427,7 @@ typedef struct { * 0b1..Enables interrupt. */ #define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK) + #define I2S_TCSR_FRF_MASK (0x10000U) #define I2S_TCSR_FRF_SHIFT (16U) /*! FRF - FIFO Request Flag @@ -47204,6 +55435,7 @@ typedef struct { * 0b1..Transmit FIFO watermark has been reached. */ #define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK) + #define I2S_TCSR_FWF_MASK (0x20000U) #define I2S_TCSR_FWF_SHIFT (17U) /*! FWF - FIFO Warning Flag @@ -47211,6 +55443,7 @@ typedef struct { * 0b1..Enabled transmit FIFO is empty. */ #define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK) + #define I2S_TCSR_FEF_MASK (0x40000U) #define I2S_TCSR_FEF_SHIFT (18U) /*! FEF - FIFO Error Flag @@ -47218,6 +55451,7 @@ typedef struct { * 0b1..Transmit underrun detected. */ #define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK) + #define I2S_TCSR_SEF_MASK (0x80000U) #define I2S_TCSR_SEF_SHIFT (19U) /*! SEF - Sync Error Flag @@ -47225,6 +55459,7 @@ typedef struct { * 0b1..Frame sync error detected. */ #define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK) + #define I2S_TCSR_WSF_MASK (0x100000U) #define I2S_TCSR_WSF_SHIFT (20U) /*! WSF - Word Start Flag @@ -47232,6 +55467,7 @@ typedef struct { * 0b1..Start of word detected. */ #define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK) + #define I2S_TCSR_SR_MASK (0x1000000U) #define I2S_TCSR_SR_SHIFT (24U) /*! SR - Software Reset @@ -47239,6 +55475,7 @@ typedef struct { * 0b1..Software reset. */ #define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK) + #define I2S_TCSR_FR_MASK (0x2000000U) #define I2S_TCSR_FR_SHIFT (25U) /*! FR - FIFO Reset @@ -47246,6 +55483,7 @@ typedef struct { * 0b1..FIFO reset. */ #define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK) + #define I2S_TCSR_BCE_MASK (0x10000000U) #define I2S_TCSR_BCE_SHIFT (28U) /*! BCE - Bit Clock Enable @@ -47253,6 +55491,7 @@ typedef struct { * 0b1..Transmit bit clock is enabled. */ #define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK) + #define I2S_TCSR_DBGE_MASK (0x20000000U) #define I2S_TCSR_DBGE_SHIFT (29U) /*! DBGE - Debug Enable @@ -47260,6 +55499,7 @@ typedef struct { * 0b1..Transmitter is enabled in Debug mode. */ #define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK) + #define I2S_TCSR_STOPE_MASK (0x40000000U) #define I2S_TCSR_STOPE_SHIFT (30U) /*! STOPE - Stop Enable @@ -47267,6 +55507,7 @@ typedef struct { * 0b1..Transmitter enabled in Stop mode. */ #define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK) + #define I2S_TCSR_TE_MASK (0x80000000U) #define I2S_TCSR_TE_SHIFT (31U) /*! TE - Transmitter Enable @@ -47276,8 +55517,9 @@ typedef struct { #define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK) /*! @} */ -/*! @name TCR1 - SAI Transmit Configuration 1 Register */ +/*! @name TCR1 - Transmit Configuration 1 */ /*! @{ */ + #define I2S_TCR1_TFW_MASK (0x1FU) #define I2S_TCR1_TFW_SHIFT (0U) /*! TFW - Transmit FIFO Watermark @@ -47285,13 +55527,23 @@ typedef struct { #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK) /*! @} */ -/*! @name TCR2 - SAI Transmit Configuration 2 Register */ +/*! @name TCR2 - Transmit Configuration 2 */ /*! @{ */ + #define I2S_TCR2_DIV_MASK (0xFFU) #define I2S_TCR2_DIV_SHIFT (0U) /*! DIV - Bit Clock Divide */ #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK) + +#define I2S_TCR2_BYP_MASK (0x800000U) +#define I2S_TCR2_BYP_SHIFT (23U) +/*! BYP - Bit Clock Bypass + * 0b0..Internal bit clock is generated from bit clock divider. + * 0b1..Internal bit clock is divide by one of the audio master clock. + */ +#define I2S_TCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BYP_SHIFT)) & I2S_TCR2_BYP_MASK) + #define I2S_TCR2_BCD_MASK (0x1000000U) #define I2S_TCR2_BCD_SHIFT (24U) /*! BCD - Bit Clock Direction @@ -47299,6 +55551,7 @@ typedef struct { * 0b1..Bit clock is generated internally in Master mode. */ #define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK) + #define I2S_TCR2_BCP_MASK (0x2000000U) #define I2S_TCR2_BCP_SHIFT (25U) /*! BCP - Bit Clock Polarity @@ -47306,6 +55559,7 @@ typedef struct { * 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. */ #define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK) + #define I2S_TCR2_MSEL_MASK (0xC000000U) #define I2S_TCR2_MSEL_SHIFT (26U) /*! MSEL - MCLK Select @@ -47315,6 +55569,7 @@ typedef struct { * 0b11..Master Clock (MCLK) 3 option selected. */ #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK) + #define I2S_TCR2_BCI_MASK (0x10000000U) #define I2S_TCR2_BCI_SHIFT (28U) /*! BCI - Bit Clock Input @@ -47322,6 +55577,7 @@ typedef struct { * 0b1..Internal logic is clocked as if bit clock was externally generated. */ #define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK) + #define I2S_TCR2_BCS_MASK (0x20000000U) #define I2S_TCR2_BCS_SHIFT (29U) /*! BCS - Bit Clock Swap @@ -47329,6 +55585,7 @@ typedef struct { * 0b1..Swap the bit clock source. */ #define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK) + #define I2S_TCR2_SYNC_MASK (0x40000000U) #define I2S_TCR2_SYNC_SHIFT (30U) /*! SYNC - Synchronous Mode @@ -47338,18 +55595,21 @@ typedef struct { #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK) /*! @} */ -/*! @name TCR3 - SAI Transmit Configuration 3 Register */ +/*! @name TCR3 - Transmit Configuration 3 */ /*! @{ */ + #define I2S_TCR3_WDFL_MASK (0x1FU) #define I2S_TCR3_WDFL_SHIFT (0U) /*! WDFL - Word Flag Configuration */ #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) + #define I2S_TCR3_TCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ #define I2S_TCR3_TCE_SHIFT (16U) /*! TCE - Transmit Channel Enable */ #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ + #define I2S_TCR3_CFR_MASK (0xF000000U) #define I2S_TCR3_CFR_SHIFT (24U) /*! CFR - Channel FIFO Reset @@ -47357,8 +55617,9 @@ typedef struct { #define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK) /*! @} */ -/*! @name TCR4 - SAI Transmit Configuration 4 Register */ +/*! @name TCR4 - Transmit Configuration 4 */ /*! @{ */ + #define I2S_TCR4_FSD_MASK (0x1U) #define I2S_TCR4_FSD_SHIFT (0U) /*! FSD - Frame Sync Direction @@ -47366,6 +55627,7 @@ typedef struct { * 0b1..Frame sync is generated internally in Master mode. */ #define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK) + #define I2S_TCR4_FSP_MASK (0x2U) #define I2S_TCR4_FSP_SHIFT (1U) /*! FSP - Frame Sync Polarity @@ -47373,6 +55635,7 @@ typedef struct { * 0b1..Frame sync is active low. */ #define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK) + #define I2S_TCR4_ONDEM_MASK (0x4U) #define I2S_TCR4_ONDEM_SHIFT (2U) /*! ONDEM - On Demand Mode @@ -47380,6 +55643,7 @@ typedef struct { * 0b1..Internal frame sync is generated when the FIFO warning flag is clear. */ #define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK) + #define I2S_TCR4_FSE_MASK (0x8U) #define I2S_TCR4_FSE_SHIFT (3U) /*! FSE - Frame Sync Early @@ -47387,6 +55651,7 @@ typedef struct { * 0b1..Frame sync asserts one bit before the first bit of the frame. */ #define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK) + #define I2S_TCR4_MF_MASK (0x10U) #define I2S_TCR4_MF_SHIFT (4U) /*! MF - MSB First @@ -47394,6 +55659,7 @@ typedef struct { * 0b1..MSB is transmitted first. */ #define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK) + #define I2S_TCR4_CHMOD_MASK (0x20U) #define I2S_TCR4_CHMOD_SHIFT (5U) /*! CHMOD - Channel Mode @@ -47401,16 +55667,19 @@ typedef struct { * 0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled. */ #define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK) + #define I2S_TCR4_SYWD_MASK (0x1F00U) #define I2S_TCR4_SYWD_SHIFT (8U) /*! SYWD - Sync Width */ #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK) + #define I2S_TCR4_FRSZ_MASK (0x1F0000U) #define I2S_TCR4_FRSZ_SHIFT (16U) /*! FRSZ - Frame size */ #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) + #define I2S_TCR4_FPACK_MASK (0x3000000U) #define I2S_TCR4_FPACK_SHIFT (24U) /*! FPACK - FIFO Packing Mode @@ -47420,6 +55689,7 @@ typedef struct { * 0b11..16-bit FIFO packing is enabled. */ #define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK) + #define I2S_TCR4_FCOMB_MASK (0xC000000U) #define I2S_TCR4_FCOMB_SHIFT (26U) /*! FCOMB - FIFO Combine Mode @@ -47429,6 +55699,7 @@ typedef struct { * 0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software). */ #define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK) + #define I2S_TCR4_FCONT_MASK (0x10000000U) #define I2S_TCR4_FCONT_SHIFT (28U) /*! FCONT - FIFO Continue on Error @@ -47438,18 +55709,21 @@ typedef struct { #define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK) /*! @} */ -/*! @name TCR5 - SAI Transmit Configuration 5 Register */ +/*! @name TCR5 - Transmit Configuration 5 */ /*! @{ */ + #define I2S_TCR5_FBT_MASK (0x1F00U) #define I2S_TCR5_FBT_SHIFT (8U) /*! FBT - First Bit Shifted */ #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK) + #define I2S_TCR5_W0W_MASK (0x1F0000U) #define I2S_TCR5_W0W_SHIFT (16U) /*! W0W - Word 0 Width */ #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK) + #define I2S_TCR5_WNW_MASK (0x1F000000U) #define I2S_TCR5_WNW_SHIFT (24U) /*! WNW - Word N Width @@ -47457,8 +55731,9 @@ typedef struct { #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK) /*! @} */ -/*! @name TDR - SAI Transmit Data Register */ +/*! @name TDR - Transmit Data */ /*! @{ */ + #define I2S_TDR_TDR_MASK (0xFFFFFFFFU) #define I2S_TDR_TDR_SHIFT (0U) /*! TDR - Transmit Data Register @@ -47469,18 +55744,21 @@ typedef struct { /* The count of I2S_TDR */ #define I2S_TDR_COUNT (4U) -/*! @name TFR - SAI Transmit FIFO Register */ +/*! @name TFR - Transmit FIFO */ /*! @{ */ + #define I2S_TFR_RFP_MASK (0x3FU) #define I2S_TFR_RFP_SHIFT (0U) /*! RFP - Read FIFO Pointer */ #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK) + #define I2S_TFR_WFP_MASK (0x3F0000U) #define I2S_TFR_WFP_SHIFT (16U) /*! WFP - Write FIFO Pointer */ #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK) + #define I2S_TFR_WCP_MASK (0x80000000U) #define I2S_TFR_WCP_SHIFT (31U) /*! WCP - Write Channel Pointer @@ -47493,8 +55771,9 @@ typedef struct { /* The count of I2S_TFR */ #define I2S_TFR_COUNT (4U) -/*! @name TMR - SAI Transmit Mask Register */ +/*! @name TMR - Transmit Mask */ /*! @{ */ + #define I2S_TMR_TWM_MASK (0xFFFFFFFFU) #define I2S_TMR_TWM_SHIFT (0U) /*! TWM - Transmit Word Mask @@ -47504,8 +55783,9 @@ typedef struct { #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) /*! @} */ -/*! @name RCSR - SAI Receive Control Register */ +/*! @name RCSR - Receive Control */ /*! @{ */ + #define I2S_RCSR_FRDE_MASK (0x1U) #define I2S_RCSR_FRDE_SHIFT (0U) /*! FRDE - FIFO Request DMA Enable @@ -47513,6 +55793,7 @@ typedef struct { * 0b1..Enables the DMA request. */ #define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK) + #define I2S_RCSR_FWDE_MASK (0x2U) #define I2S_RCSR_FWDE_SHIFT (1U) /*! FWDE - FIFO Warning DMA Enable @@ -47520,6 +55801,7 @@ typedef struct { * 0b1..Enables the DMA request. */ #define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK) + #define I2S_RCSR_FRIE_MASK (0x100U) #define I2S_RCSR_FRIE_SHIFT (8U) /*! FRIE - FIFO Request Interrupt Enable @@ -47527,6 +55809,7 @@ typedef struct { * 0b1..Enables the interrupt. */ #define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK) + #define I2S_RCSR_FWIE_MASK (0x200U) #define I2S_RCSR_FWIE_SHIFT (9U) /*! FWIE - FIFO Warning Interrupt Enable @@ -47534,6 +55817,7 @@ typedef struct { * 0b1..Enables the interrupt. */ #define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK) + #define I2S_RCSR_FEIE_MASK (0x400U) #define I2S_RCSR_FEIE_SHIFT (10U) /*! FEIE - FIFO Error Interrupt Enable @@ -47541,6 +55825,7 @@ typedef struct { * 0b1..Enables the interrupt. */ #define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK) + #define I2S_RCSR_SEIE_MASK (0x800U) #define I2S_RCSR_SEIE_SHIFT (11U) /*! SEIE - Sync Error Interrupt Enable @@ -47548,6 +55833,7 @@ typedef struct { * 0b1..Enables interrupt. */ #define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK) + #define I2S_RCSR_WSIE_MASK (0x1000U) #define I2S_RCSR_WSIE_SHIFT (12U) /*! WSIE - Word Start Interrupt Enable @@ -47555,6 +55841,7 @@ typedef struct { * 0b1..Enables interrupt. */ #define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK) + #define I2S_RCSR_FRF_MASK (0x10000U) #define I2S_RCSR_FRF_SHIFT (16U) /*! FRF - FIFO Request Flag @@ -47562,6 +55849,7 @@ typedef struct { * 0b1..Receive FIFO watermark has been reached. */ #define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK) + #define I2S_RCSR_FWF_MASK (0x20000U) #define I2S_RCSR_FWF_SHIFT (17U) /*! FWF - FIFO Warning Flag @@ -47569,6 +55857,7 @@ typedef struct { * 0b1..Enabled receive FIFO is full. */ #define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK) + #define I2S_RCSR_FEF_MASK (0x40000U) #define I2S_RCSR_FEF_SHIFT (18U) /*! FEF - FIFO Error Flag @@ -47576,6 +55865,7 @@ typedef struct { * 0b1..Receive overflow detected. */ #define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK) + #define I2S_RCSR_SEF_MASK (0x80000U) #define I2S_RCSR_SEF_SHIFT (19U) /*! SEF - Sync Error Flag @@ -47583,6 +55873,7 @@ typedef struct { * 0b1..Frame sync error detected. */ #define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK) + #define I2S_RCSR_WSF_MASK (0x100000U) #define I2S_RCSR_WSF_SHIFT (20U) /*! WSF - Word Start Flag @@ -47590,6 +55881,7 @@ typedef struct { * 0b1..Start of word detected. */ #define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK) + #define I2S_RCSR_SR_MASK (0x1000000U) #define I2S_RCSR_SR_SHIFT (24U) /*! SR - Software Reset @@ -47597,6 +55889,7 @@ typedef struct { * 0b1..Software reset. */ #define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK) + #define I2S_RCSR_FR_MASK (0x2000000U) #define I2S_RCSR_FR_SHIFT (25U) /*! FR - FIFO Reset @@ -47604,6 +55897,7 @@ typedef struct { * 0b1..FIFO reset. */ #define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK) + #define I2S_RCSR_BCE_MASK (0x10000000U) #define I2S_RCSR_BCE_SHIFT (28U) /*! BCE - Bit Clock Enable @@ -47611,6 +55905,7 @@ typedef struct { * 0b1..Receive bit clock is enabled. */ #define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK) + #define I2S_RCSR_DBGE_MASK (0x20000000U) #define I2S_RCSR_DBGE_SHIFT (29U) /*! DBGE - Debug Enable @@ -47618,6 +55913,7 @@ typedef struct { * 0b1..Receiver is enabled in Debug mode. */ #define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK) + #define I2S_RCSR_STOPE_MASK (0x40000000U) #define I2S_RCSR_STOPE_SHIFT (30U) /*! STOPE - Stop Enable @@ -47625,6 +55921,7 @@ typedef struct { * 0b1..Receiver enabled in Stop mode. */ #define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK) + #define I2S_RCSR_RE_MASK (0x80000000U) #define I2S_RCSR_RE_SHIFT (31U) /*! RE - Receiver Enable @@ -47634,8 +55931,9 @@ typedef struct { #define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK) /*! @} */ -/*! @name RCR1 - SAI Receive Configuration 1 Register */ +/*! @name RCR1 - Receive Configuration 1 */ /*! @{ */ + #define I2S_RCR1_RFW_MASK (0x1FU) #define I2S_RCR1_RFW_SHIFT (0U) /*! RFW - Receive FIFO Watermark @@ -47643,13 +55941,23 @@ typedef struct { #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK) /*! @} */ -/*! @name RCR2 - SAI Receive Configuration 2 Register */ +/*! @name RCR2 - Receive Configuration 2 */ /*! @{ */ + #define I2S_RCR2_DIV_MASK (0xFFU) #define I2S_RCR2_DIV_SHIFT (0U) /*! DIV - Bit Clock Divide */ #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK) + +#define I2S_RCR2_BYP_MASK (0x800000U) +#define I2S_RCR2_BYP_SHIFT (23U) +/*! BYP - Bit Clock Bypass + * 0b0..Internal bit clock is generated from bit clock divider. + * 0b1..Internal bit clock is divide by one of the audio master clock. + */ +#define I2S_RCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BYP_SHIFT)) & I2S_RCR2_BYP_MASK) + #define I2S_RCR2_BCD_MASK (0x1000000U) #define I2S_RCR2_BCD_SHIFT (24U) /*! BCD - Bit Clock Direction @@ -47657,6 +55965,7 @@ typedef struct { * 0b1..Bit clock is generated internally in Master mode. */ #define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK) + #define I2S_RCR2_BCP_MASK (0x2000000U) #define I2S_RCR2_BCP_SHIFT (25U) /*! BCP - Bit Clock Polarity @@ -47664,6 +55973,7 @@ typedef struct { * 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge. */ #define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK) + #define I2S_RCR2_MSEL_MASK (0xC000000U) #define I2S_RCR2_MSEL_SHIFT (26U) /*! MSEL - MCLK Select @@ -47673,6 +55983,7 @@ typedef struct { * 0b11..Master Clock (MCLK) 3 option selected. */ #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK) + #define I2S_RCR2_BCI_MASK (0x10000000U) #define I2S_RCR2_BCI_SHIFT (28U) /*! BCI - Bit Clock Input @@ -47680,6 +55991,7 @@ typedef struct { * 0b1..Internal logic is clocked as if bit clock was externally generated. */ #define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK) + #define I2S_RCR2_BCS_MASK (0x20000000U) #define I2S_RCR2_BCS_SHIFT (29U) /*! BCS - Bit Clock Swap @@ -47687,6 +55999,7 @@ typedef struct { * 0b1..Swap the bit clock source. */ #define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK) + #define I2S_RCR2_SYNC_MASK (0x40000000U) #define I2S_RCR2_SYNC_SHIFT (30U) /*! SYNC - Synchronous Mode @@ -47696,18 +56009,21 @@ typedef struct { #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK) /*! @} */ -/*! @name RCR3 - SAI Receive Configuration 3 Register */ +/*! @name RCR3 - Receive Configuration 3 */ /*! @{ */ + #define I2S_RCR3_WDFL_MASK (0x1FU) #define I2S_RCR3_WDFL_SHIFT (0U) /*! WDFL - Word Flag Configuration */ #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) + #define I2S_RCR3_RCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ #define I2S_RCR3_RCE_SHIFT (16U) /*! RCE - Receive Channel Enable */ #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */ + #define I2S_RCR3_CFR_MASK (0xF000000U) #define I2S_RCR3_CFR_SHIFT (24U) /*! CFR - Channel FIFO Reset @@ -47715,8 +56031,9 @@ typedef struct { #define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK) /*! @} */ -/*! @name RCR4 - SAI Receive Configuration 4 Register */ +/*! @name RCR4 - Receive Configuration 4 */ /*! @{ */ + #define I2S_RCR4_FSD_MASK (0x1U) #define I2S_RCR4_FSD_SHIFT (0U) /*! FSD - Frame Sync Direction @@ -47724,6 +56041,7 @@ typedef struct { * 0b1..Frame Sync is generated internally in Master mode. */ #define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK) + #define I2S_RCR4_FSP_MASK (0x2U) #define I2S_RCR4_FSP_SHIFT (1U) /*! FSP - Frame Sync Polarity @@ -47731,6 +56049,7 @@ typedef struct { * 0b1..Frame sync is active low. */ #define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK) + #define I2S_RCR4_ONDEM_MASK (0x4U) #define I2S_RCR4_ONDEM_SHIFT (2U) /*! ONDEM - On Demand Mode @@ -47738,6 +56057,7 @@ typedef struct { * 0b1..Internal frame sync is generated when the FIFO warning flag is clear. */ #define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK) + #define I2S_RCR4_FSE_MASK (0x8U) #define I2S_RCR4_FSE_SHIFT (3U) /*! FSE - Frame Sync Early @@ -47745,6 +56065,7 @@ typedef struct { * 0b1..Frame sync asserts one bit before the first bit of the frame. */ #define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK) + #define I2S_RCR4_MF_MASK (0x10U) #define I2S_RCR4_MF_SHIFT (4U) /*! MF - MSB First @@ -47752,16 +56073,19 @@ typedef struct { * 0b1..MSB is received first. */ #define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK) + #define I2S_RCR4_SYWD_MASK (0x1F00U) #define I2S_RCR4_SYWD_SHIFT (8U) /*! SYWD - Sync Width */ #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK) + #define I2S_RCR4_FRSZ_MASK (0x1F0000U) #define I2S_RCR4_FRSZ_SHIFT (16U) /*! FRSZ - Frame Size */ #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) + #define I2S_RCR4_FPACK_MASK (0x3000000U) #define I2S_RCR4_FPACK_SHIFT (24U) /*! FPACK - FIFO Packing Mode @@ -47771,6 +56095,7 @@ typedef struct { * 0b11..16-bit FIFO packing is enabled */ #define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK) + #define I2S_RCR4_FCOMB_MASK (0xC000000U) #define I2S_RCR4_FCOMB_SHIFT (26U) /*! FCOMB - FIFO Combine Mode @@ -47780,6 +56105,7 @@ typedef struct { * 0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software). */ #define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK) + #define I2S_RCR4_FCONT_MASK (0x10000000U) #define I2S_RCR4_FCONT_SHIFT (28U) /*! FCONT - FIFO Continue on Error @@ -47789,18 +56115,21 @@ typedef struct { #define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK) /*! @} */ -/*! @name RCR5 - SAI Receive Configuration 5 Register */ +/*! @name RCR5 - Receive Configuration 5 */ /*! @{ */ + #define I2S_RCR5_FBT_MASK (0x1F00U) #define I2S_RCR5_FBT_SHIFT (8U) /*! FBT - First Bit Shifted */ #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK) + #define I2S_RCR5_W0W_MASK (0x1F0000U) #define I2S_RCR5_W0W_SHIFT (16U) /*! W0W - Word 0 Width */ #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK) + #define I2S_RCR5_WNW_MASK (0x1F000000U) #define I2S_RCR5_WNW_SHIFT (24U) /*! WNW - Word N Width @@ -47808,8 +56137,9 @@ typedef struct { #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK) /*! @} */ -/*! @name RDR - SAI Receive Data Register */ +/*! @name RDR - Receive Data */ /*! @{ */ + #define I2S_RDR_RDR_MASK (0xFFFFFFFFU) #define I2S_RDR_RDR_SHIFT (0U) /*! RDR - Receive Data Register @@ -47820,13 +56150,15 @@ typedef struct { /* The count of I2S_RDR */ #define I2S_RDR_COUNT (4U) -/*! @name RFR - SAI Receive FIFO Register */ +/*! @name RFR - Receive FIFO */ /*! @{ */ + #define I2S_RFR_RFP_MASK (0x3FU) #define I2S_RFR_RFP_SHIFT (0U) /*! RFP - Read FIFO Pointer */ #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK) + #define I2S_RFR_RCP_MASK (0x8000U) #define I2S_RFR_RCP_SHIFT (15U) /*! RCP - Receive Channel Pointer @@ -47834,6 +56166,7 @@ typedef struct { * 0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read. */ #define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK) + #define I2S_RFR_WFP_MASK (0x3F0000U) #define I2S_RFR_WFP_SHIFT (16U) /*! WFP - Write FIFO Pointer @@ -47844,8 +56177,9 @@ typedef struct { /* The count of I2S_RFR */ #define I2S_RFR_COUNT (4U) -/*! @name RMR - SAI Receive Mask Register */ +/*! @name RMR - Receive Mask */ /*! @{ */ + #define I2S_RMR_RWM_MASK (0xFFFFFFFFU) #define I2S_RMR_RWM_SHIFT (0U) /*! RWM - Receive Word Mask @@ -47906,8 +56240,7 @@ typedef struct { __I uint32_t STA; /**< IEE Status, offset: 0x4 */ __IO uint32_t TSTMD; /**< IEE Test Mode Register, offset: 0x8 */ __O uint32_t DPAMS; /**< AES Mask Generation Seed, offset: 0xC */ - __IO uint32_t KBCR; /**< IEE Keystream Buffer Configuration Register, offset: 0x10 */ - uint8_t RESERVED_0[12]; + uint8_t RESERVED_0[16]; __IO uint32_t PC_S_LT; /**< Performance Counter, AES Slave Latency Threshold Value, offset: 0x20 */ __IO uint32_t PC_M_LT; /**< Performance Counter, AES Master Latency Threshold, offset: 0x24 */ uint8_t RESERVED_1[24]; @@ -47921,20 +56254,30 @@ typedef struct { uint8_t RESERVED_3[4]; __IO uint32_t PC_M_MBR; /**< Performance Counter, Number of AXI Master Merge Buffer Read Transactions, offset: 0x64 */ uint8_t RESERVED_4[8]; - __IO uint64_t PC_SR_TBC; /**< Performance Counter, Slave Read Transactions Byte Count, offset: 0x70 */ - __IO uint64_t PC_SW_TBC; /**< Performance Counter, Slave Write Transactions Byte Count, offset: 0x78 */ - __IO uint64_t PC_MR_TBC; /**< Performance Counter, Master Read Transactions Byte Count, offset: 0x80 */ - __IO uint64_t PC_MW_TBC; /**< Performance Counter, Master Write Transactions Byte Count, offset: 0x88 */ + __IO uint32_t PC_SR_TBC_U; /**< Performance Counter, Upper Slave Read Transactions Byte Count, offset: 0x70 */ + __IO uint32_t PC_SR_TBC_L; /**< Performance Counter, Lower Slave Read Transactions Byte Count, offset: 0x74 */ + __IO uint32_t PC_SW_TBC_U; /**< Performance Counter, Upper Slave Write Transactions Byte Count, offset: 0x78 */ + __IO uint32_t PC_SW_TBC_L; /**< Performance Counter, Lower Slave Write Transactions Byte Count, offset: 0x7C */ + __IO uint32_t PC_MR_TBC_U; /**< Performance Counter, Upper Master Read Transactions Byte Count, offset: 0x80 */ + __IO uint32_t PC_MR_TBC_L; /**< Performance Counter, Lower Master Read Transactions Byte Count, offset: 0x84 */ + __IO uint32_t PC_MW_TBC_U; /**< Performance Counter, Upper Master Write Transactions Byte Count, offset: 0x88 */ + __IO uint32_t PC_MW_TBC_L; /**< Performance Counter, Lower Master Write Transactions Byte Count, offset: 0x8C */ __IO uint32_t PC_SR_TLGTT; /**< Performance Counter, Number of AXI Slave Read Transactions with Latency Greater than the Threshold, offset: 0x90 */ __IO uint32_t PC_SW_TLGTT; /**< Performance Counter, Number of AXI Slave Write Transactions with Latency Greater than the Threshold, offset: 0x94 */ __IO uint32_t PC_MR_TLGTT; /**< Performance Counter, Number of AXI Master Read Transactions with Latency Greater than the Threshold, offset: 0x98 */ __IO uint32_t PC_MW_TLGTT; /**< Performance Counter, Number of AXI Master Write Transactions with Latency Greater than the Threshold, offset: 0x9C */ - __IO uint64_t PC_SR_TLAT; /**< Performance Counter, Slave Read Latency Count, offset: 0xA0 */ - __IO uint64_t PC_SW_TLAT; /**< Performance Counter, Slave Write Latency Count, offset: 0xA8 */ - __IO uint64_t PC_MR_TLAT; /**< Performance Counter, Master Read Latency Count, offset: 0xB0 */ - __IO uint64_t PC_MW_TLAT; /**< Performance Counter, Master Write Latency Count, offset: 0xB8 */ - __IO uint64_t PC_SR_TNRT; /**< Performance Counter, Slave Read Total Non-Responding Time, offset: 0xC0 */ - __IO uint64_t PC_SW_TNRT; /**< Performance Counter, Slave Write Total Non-Responding Time, offset: 0xC8 */ + __IO uint32_t PC_SR_TLAT_U; /**< Performance Counter, Upper Slave Read Latency Count, offset: 0xA0 */ + __IO uint32_t PC_SR_TLAT_L; /**< Performance Counter, Lower Slave Read Latency Count, offset: 0xA4 */ + __IO uint32_t PC_SW_TLAT_U; /**< Performance Counter, Upper Slave Write Latency Count, offset: 0xA8 */ + __IO uint32_t PC_SW_TLAT_L; /**< Performance Counter, Lower Slave Write Latency Count, offset: 0xAC */ + __IO uint32_t PC_MR_TLAT_U; /**< Performance Counter, Upper Master Read Latency Count, offset: 0xB0 */ + __IO uint32_t PC_MR_TLAT_L; /**< Performance Counter, Lower Master Read Latency Count, offset: 0xB4 */ + __IO uint32_t PC_MW_TLAT_U; /**< Performance Counter, Upper Master Write Latency Count, offset: 0xB8 */ + __IO uint32_t PC_MW_TLAT_L; /**< Performance Counter, Lower Master Write Latency Count, offset: 0xBC */ + __IO uint32_t PC_SR_TNRT_U; /**< Performance Counter, Upper Slave Read Total Non-Responding Time, offset: 0xC0 */ + __IO uint32_t PC_SR_TNRT_L; /**< Performance Counter, Lower Slave Read Total Non-Responding Time, offset: 0xC4 */ + __IO uint32_t PC_SW_TNRT_U; /**< Performance Counter, Upper Slave Write Total Non-Responding Time, offset: 0xC8 */ + __IO uint32_t PC_SW_TNRT_L; /**< Performance Counter, Lower Slave Write Total Non-Responding Time, offset: 0xCC */ uint8_t RESERVED_5[32]; __I uint32_t VIDR1; /**< IEE Version ID Register 1, offset: 0xF0 */ uint8_t RESERVED_6[4]; @@ -47965,6 +56308,7 @@ typedef struct { /*! @name GCFG - IEE Global Configuration */ /*! @{ */ + #define IEE_GCFG_RL0_MASK (0x1U) #define IEE_GCFG_RL0_SHIFT (0U) /*! RL0 @@ -47972,6 +56316,7 @@ typedef struct { * 0b1..Key, Offset and Attribute registers are locked. */ #define IEE_GCFG_RL0(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL0_SHIFT)) & IEE_GCFG_RL0_MASK) + #define IEE_GCFG_RL1_MASK (0x2U) #define IEE_GCFG_RL1_SHIFT (1U) /*! RL1 @@ -47979,6 +56324,7 @@ typedef struct { * 0b1..Key, Offset and Attribute registers are locked. */ #define IEE_GCFG_RL1(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL1_SHIFT)) & IEE_GCFG_RL1_MASK) + #define IEE_GCFG_RL2_MASK (0x4U) #define IEE_GCFG_RL2_SHIFT (2U) /*! RL2 @@ -47986,6 +56332,7 @@ typedef struct { * 0b1..Key, Offset and Attribute registers are locked. */ #define IEE_GCFG_RL2(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL2_SHIFT)) & IEE_GCFG_RL2_MASK) + #define IEE_GCFG_RL3_MASK (0x8U) #define IEE_GCFG_RL3_SHIFT (3U) /*! RL3 @@ -47993,6 +56340,7 @@ typedef struct { * 0b1..Key, Offset and Attribute registers are locked. */ #define IEE_GCFG_RL3(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL3_SHIFT)) & IEE_GCFG_RL3_MASK) + #define IEE_GCFG_RL4_MASK (0x10U) #define IEE_GCFG_RL4_SHIFT (4U) /*! RL4 @@ -48000,6 +56348,7 @@ typedef struct { * 0b1..Key, Offset and Attribute registers are locked. */ #define IEE_GCFG_RL4(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL4_SHIFT)) & IEE_GCFG_RL4_MASK) + #define IEE_GCFG_RL5_MASK (0x20U) #define IEE_GCFG_RL5_SHIFT (5U) /*! RL5 @@ -48007,6 +56356,7 @@ typedef struct { * 0b1..Key, Offset and Attribute registers are locked. */ #define IEE_GCFG_RL5(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL5_SHIFT)) & IEE_GCFG_RL5_MASK) + #define IEE_GCFG_RL6_MASK (0x40U) #define IEE_GCFG_RL6_SHIFT (6U) /*! RL6 @@ -48014,6 +56364,7 @@ typedef struct { * 0b1..Key, Offset and Attribute registers are locked. */ #define IEE_GCFG_RL6(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL6_SHIFT)) & IEE_GCFG_RL6_MASK) + #define IEE_GCFG_RL7_MASK (0x80U) #define IEE_GCFG_RL7_SHIFT (7U) /*! RL7 @@ -48021,6 +56372,7 @@ typedef struct { * 0b1..Key, Offset and Attribute registers are locked. */ #define IEE_GCFG_RL7(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL7_SHIFT)) & IEE_GCFG_RL7_MASK) + #define IEE_GCFG_TME_MASK (0x10000U) #define IEE_GCFG_TME_SHIFT (16U) /*! TME @@ -48028,6 +56380,7 @@ typedef struct { * 0b1..Enabled. */ #define IEE_GCFG_TME(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_TME_SHIFT)) & IEE_GCFG_TME_MASK) + #define IEE_GCFG_TMD_MASK (0x20000U) #define IEE_GCFG_TMD_SHIFT (17U) /*! TMD @@ -48035,13 +56388,7 @@ typedef struct { * 0b1..Test mode is disabled. */ #define IEE_GCFG_TMD(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_TMD_SHIFT)) & IEE_GCFG_TMD_MASK) -#define IEE_GCFG_DPA_DIS_MASK (0x1000000U) -#define IEE_GCFG_DPA_DIS_SHIFT (24U) -/*! DPA_DIS - * 0b0..DPA enabled. - * 0b1..DPA disabled. AES DPA is disabled for testing. - */ -#define IEE_GCFG_DPA_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_DPA_DIS_SHIFT)) & IEE_GCFG_DPA_DIS_MASK) + #define IEE_GCFG_KEY_RD_DIS_MASK (0x2000000U) #define IEE_GCFG_KEY_RD_DIS_SHIFT (25U) /*! KEY_RD_DIS @@ -48049,6 +56396,7 @@ typedef struct { * 0b1..Key read disabled. Reading the key registers is disabled. */ #define IEE_GCFG_KEY_RD_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_KEY_RD_DIS_SHIFT)) & IEE_GCFG_KEY_RD_DIS_MASK) + #define IEE_GCFG_MON_EN_MASK (0x10000000U) #define IEE_GCFG_MON_EN_SHIFT (28U) /*! MON_EN @@ -48056,6 +56404,7 @@ typedef struct { * 0b1..Performance monitoring enabled. Writing of the performance counter registers is disabled. */ #define IEE_GCFG_MON_EN(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_MON_EN_SHIFT)) & IEE_GCFG_MON_EN_MASK) + #define IEE_GCFG_CLR_MON_MASK (0x20000000U) #define IEE_GCFG_CLR_MON_SHIFT (29U) /*! CLR_MON @@ -48063,6 +56412,7 @@ typedef struct { * 0b1..Reset performance counters. */ #define IEE_GCFG_CLR_MON(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_CLR_MON_SHIFT)) & IEE_GCFG_CLR_MON_MASK) + #define IEE_GCFG_RST_MASK (0x80000000U) #define IEE_GCFG_RST_SHIFT (31U) /*! RST @@ -48074,16 +56424,27 @@ typedef struct { /*! @name STA - IEE Status */ /*! @{ */ + #define IEE_STA_DSR_MASK (0x1U) #define IEE_STA_DSR_SHIFT (0U) +/*! DSR + * 0b0..No seed request present + * 0b1..Seed request present + */ #define IEE_STA_DSR(x) (((uint32_t)(((uint32_t)(x)) << IEE_STA_DSR_SHIFT)) & IEE_STA_DSR_MASK) + #define IEE_STA_AFD_MASK (0x10U) #define IEE_STA_AFD_SHIFT (4U) +/*! AFD + * 0b0..No fault detected + * 0b1..Fault detected + */ #define IEE_STA_AFD(x) (((uint32_t)(((uint32_t)(x)) << IEE_STA_AFD_SHIFT)) & IEE_STA_AFD_MASK) /*! @} */ /*! @name TSTMD - IEE Test Mode Register */ /*! @{ */ + #define IEE_TSTMD_TMRDY_MASK (0x1U) #define IEE_TSTMD_TMRDY_SHIFT (0U) /*! TMRDY @@ -48091,13 +56452,15 @@ typedef struct { * 0b1..Ready. */ #define IEE_TSTMD_TMRDY(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMRDY_SHIFT)) & IEE_TSTMD_TMRDY_MASK) + #define IEE_TSTMD_TMR_MASK (0x2U) #define IEE_TSTMD_TMR_SHIFT (1U) /*! TMR - * 0b0..Not running. may be written if IEE_GCFG[TME] = 1 + * 0b0..Not running. May be written if IEE_GCFG[TME] = 1 * 0b1..Run AES Test until TMDONE is indicated. */ #define IEE_TSTMD_TMR(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMR_SHIFT)) & IEE_TSTMD_TMR_MASK) + #define IEE_TSTMD_TMENCR_MASK (0x4U) #define IEE_TSTMD_TMENCR_SHIFT (2U) /*! TMENCR @@ -48105,13 +56468,15 @@ typedef struct { * 0b1..AES Test mode will do encryption. */ #define IEE_TSTMD_TMENCR(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMENCR_SHIFT)) & IEE_TSTMD_TMENCR_MASK) + #define IEE_TSTMD_TMCONT_MASK (0x8U) #define IEE_TSTMD_TMCONT_SHIFT (3U) /*! TMCONT - * 0b0..Not continue. This is the last block of data for AES. - * 0b1..Continue. Don't initialize AES after this block. + * 0b0..Do not continue. This is the last block of data for AES. + * 0b1..Continue. Do not initialize AES after this block. */ #define IEE_TSTMD_TMCONT(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMCONT_SHIFT)) & IEE_TSTMD_TMCONT_MASK) + #define IEE_TSTMD_TMDONE_MASK (0x10U) #define IEE_TSTMD_TMDONE_SHIFT (4U) /*! TMDONE @@ -48119,6 +56484,7 @@ typedef struct { * 0b1..Test Done. */ #define IEE_TSTMD_TMDONE(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMDONE_SHIFT)) & IEE_TSTMD_TMDONE_MASK) + #define IEE_TSTMD_TMLEN_MASK (0xF00U) #define IEE_TSTMD_TMLEN_SHIFT (8U) #define IEE_TSTMD_TMLEN(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMLEN_SHIFT)) & IEE_TSTMD_TMLEN_MASK) @@ -48126,42 +56492,19 @@ typedef struct { /*! @name DPAMS - AES Mask Generation Seed */ /*! @{ */ + #define IEE_DPAMS_DPAMS_MASK (0xFFFFFFFFU) #define IEE_DPAMS_DPAMS_SHIFT (0U) #define IEE_DPAMS_DPAMS(x) (((uint32_t)(((uint32_t)(x)) << IEE_DPAMS_DPAMS_SHIFT)) & IEE_DPAMS_DPAMS_MASK) /*! @} */ -/*! @name KBCR - IEE Keystream Buffer Configuration Register */ -/*! @{ */ -#define IEE_KBCR_BUF_CNT_MASK (0x7U) -#define IEE_KBCR_BUF_CNT_SHIFT (0U) -/*! BUF_CNT - * 0b000..0 buffers enabled. - * 0b001..1 buffer enabled. Entire buffer will be used for 1 region. - * 0b010..2 buffers enabled. Buffer is split into 2 regions. - * 0b011..3 buffers enabled. Buffer is split into 4 regions; 4th region is unused - * 0b100..4 buffers enabled. Buffer is split into 4 regions. - * 0b101..4 buffers enabled. Buffer is split into 4 regions. - * 0b110..4 buffers enabled. Buffer is split into 4 regions. - * 0b111..4 buffers enabled. Buffer is split into 4 regions. - */ -#define IEE_KBCR_BUF_CNT(x) (((uint32_t)(((uint32_t)(x)) << IEE_KBCR_BUF_CNT_SHIFT)) & IEE_KBCR_BUF_CNT_MASK) -#define IEE_KBCR_BLK_LD_SIZE_MASK (0x300U) -#define IEE_KBCR_BLK_LD_SIZE_SHIFT (8U) -/*! BLK_LD_SIZE - * 0b00..2 blocks. - * 0b01..4 blocks. - * 0b10..8 blocks. - * 0b11..16 blocks. - */ -#define IEE_KBCR_BLK_LD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << IEE_KBCR_BLK_LD_SIZE_SHIFT)) & IEE_KBCR_BLK_LD_SIZE_MASK) -/*! @} */ - /*! @name PC_S_LT - Performance Counter, AES Slave Latency Threshold Value */ /*! @{ */ + #define IEE_PC_S_LT_SW_LT_MASK (0xFFFFU) #define IEE_PC_S_LT_SW_LT_SHIFT (0U) #define IEE_PC_S_LT_SW_LT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_S_LT_SW_LT_SHIFT)) & IEE_PC_S_LT_SW_LT_MASK) + #define IEE_PC_S_LT_SR_LT_MASK (0xFFFF0000U) #define IEE_PC_S_LT_SR_LT_SHIFT (16U) #define IEE_PC_S_LT_SR_LT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_S_LT_SR_LT_SHIFT)) & IEE_PC_S_LT_SR_LT_MASK) @@ -48169,9 +56512,11 @@ typedef struct { /*! @name PC_M_LT - Performance Counter, AES Master Latency Threshold */ /*! @{ */ + #define IEE_PC_M_LT_MW_LT_MASK (0xFFFU) #define IEE_PC_M_LT_MW_LT_SHIFT (0U) #define IEE_PC_M_LT_MW_LT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_M_LT_MW_LT_SHIFT)) & IEE_PC_M_LT_MW_LT_MASK) + #define IEE_PC_M_LT_MR_LT_MASK (0xFFF0000U) #define IEE_PC_M_LT_MR_LT_SHIFT (16U) #define IEE_PC_M_LT_MR_LT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_M_LT_MR_LT_SHIFT)) & IEE_PC_M_LT_MR_LT_MASK) @@ -48179,6 +56524,7 @@ typedef struct { /*! @name PC_BLK_ENC - Performance Counter, Number of AES Block Encryptions */ /*! @{ */ + #define IEE_PC_BLK_ENC_BLK_ENC_MASK (0xFFFFFFFFU) #define IEE_PC_BLK_ENC_BLK_ENC_SHIFT (0U) #define IEE_PC_BLK_ENC_BLK_ENC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_BLK_ENC_BLK_ENC_SHIFT)) & IEE_PC_BLK_ENC_BLK_ENC_MASK) @@ -48186,6 +56532,7 @@ typedef struct { /*! @name PC_BLK_DEC - Performance Counter, Number of AES Block Decryptions */ /*! @{ */ + #define IEE_PC_BLK_DEC_BLK_DEC_MASK (0xFFFFFFFFU) #define IEE_PC_BLK_DEC_BLK_DEC_SHIFT (0U) #define IEE_PC_BLK_DEC_BLK_DEC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_BLK_DEC_BLK_DEC_SHIFT)) & IEE_PC_BLK_DEC_BLK_DEC_MASK) @@ -48193,6 +56540,7 @@ typedef struct { /*! @name PC_SR_TRANS - Performance Counter, Number of AXI Slave Read Transactions */ /*! @{ */ + #define IEE_PC_SR_TRANS_SR_TRANS_MASK (0xFFFFFFFFU) #define IEE_PC_SR_TRANS_SR_TRANS_SHIFT (0U) #define IEE_PC_SR_TRANS_SR_TRANS(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TRANS_SR_TRANS_SHIFT)) & IEE_PC_SR_TRANS_SR_TRANS_MASK) @@ -48200,6 +56548,7 @@ typedef struct { /*! @name PC_SW_TRANS - Performance Counter, Number of AXI Slave Write Transactions */ /*! @{ */ + #define IEE_PC_SW_TRANS_SW_TRANS_MASK (0xFFFFFFFFU) #define IEE_PC_SW_TRANS_SW_TRANS_SHIFT (0U) #define IEE_PC_SW_TRANS_SW_TRANS(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TRANS_SW_TRANS_SHIFT)) & IEE_PC_SW_TRANS_SW_TRANS_MASK) @@ -48207,6 +56556,7 @@ typedef struct { /*! @name PC_MR_TRANS - Performance Counter, Number of AXI Master Read Transactions */ /*! @{ */ + #define IEE_PC_MR_TRANS_MR_TRANS_MASK (0xFFFFFFFFU) #define IEE_PC_MR_TRANS_MR_TRANS_SHIFT (0U) #define IEE_PC_MR_TRANS_MR_TRANS(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TRANS_MR_TRANS_SHIFT)) & IEE_PC_MR_TRANS_MR_TRANS_MASK) @@ -48214,6 +56564,7 @@ typedef struct { /*! @name PC_MW_TRANS - Performance Counter, Number of AXI Master Write Transactions */ /*! @{ */ + #define IEE_PC_MW_TRANS_MW_TRANS_MASK (0xFFFFFFFFU) #define IEE_PC_MW_TRANS_MW_TRANS_SHIFT (0U) #define IEE_PC_MW_TRANS_MW_TRANS(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TRANS_MW_TRANS_SHIFT)) & IEE_PC_MW_TRANS_MW_TRANS_MASK) @@ -48221,47 +56572,87 @@ typedef struct { /*! @name PC_M_MBR - Performance Counter, Number of AXI Master Merge Buffer Read Transactions */ /*! @{ */ + #define IEE_PC_M_MBR_M_MBR_MASK (0xFFFFFFFFU) #define IEE_PC_M_MBR_M_MBR_SHIFT (0U) #define IEE_PC_M_MBR_M_MBR(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_M_MBR_M_MBR_SHIFT)) & IEE_PC_M_MBR_M_MBR_MASK) /*! @} */ -/*! @name PC_SR_TBC - Performance Counter, Slave Read Transactions Byte Count */ +/*! @name PC_SR_TBC_U - Performance Counter, Upper Slave Read Transactions Byte Count */ /*! @{ */ -#define IEE_PC_SR_TBC_SR_TBC_MASK (0xFFFFFFFFFFFFU) -#define IEE_PC_SR_TBC_SR_TBC_SHIFT (0U) -#define IEE_PC_SR_TBC_SR_TBC(x) (((uint64_t)(((uint64_t)(x)) << IEE_PC_SR_TBC_SR_TBC_SHIFT)) & IEE_PC_SR_TBC_SR_TBC_MASK) + +#define IEE_PC_SR_TBC_U_SR_TBC_MASK (0xFFFFU) +#define IEE_PC_SR_TBC_U_SR_TBC_SHIFT (0U) +#define IEE_PC_SR_TBC_U_SR_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TBC_U_SR_TBC_SHIFT)) & IEE_PC_SR_TBC_U_SR_TBC_MASK) /*! @} */ -/*! @name PC_SW_TBC - Performance Counter, Slave Write Transactions Byte Count */ +/*! @name PC_SR_TBC_L - Performance Counter, Lower Slave Read Transactions Byte Count */ /*! @{ */ -#define IEE_PC_SW_TBC_SW_TBC_MASK (0xFFFFFFFFFFFFU) -#define IEE_PC_SW_TBC_SW_TBC_SHIFT (0U) -#define IEE_PC_SW_TBC_SW_TBC(x) (((uint64_t)(((uint64_t)(x)) << IEE_PC_SW_TBC_SW_TBC_SHIFT)) & IEE_PC_SW_TBC_SW_TBC_MASK) + +#define IEE_PC_SR_TBC_L_SR_TBC_MASK (0xFFFFFFFFU) +#define IEE_PC_SR_TBC_L_SR_TBC_SHIFT (0U) +#define IEE_PC_SR_TBC_L_SR_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TBC_L_SR_TBC_SHIFT)) & IEE_PC_SR_TBC_L_SR_TBC_MASK) +/*! @} */ + +/*! @name PC_SW_TBC_U - Performance Counter, Upper Slave Write Transactions Byte Count */ +/*! @{ */ + +#define IEE_PC_SW_TBC_U_SW_TBC_MASK (0xFFFFU) +#define IEE_PC_SW_TBC_U_SW_TBC_SHIFT (0U) +#define IEE_PC_SW_TBC_U_SW_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TBC_U_SW_TBC_SHIFT)) & IEE_PC_SW_TBC_U_SW_TBC_MASK) +/*! @} */ + +/*! @name PC_SW_TBC_L - Performance Counter, Lower Slave Write Transactions Byte Count */ +/*! @{ */ + +#define IEE_PC_SW_TBC_L_SW_TBC_MASK (0xFFFFFFFFU) +#define IEE_PC_SW_TBC_L_SW_TBC_SHIFT (0U) +#define IEE_PC_SW_TBC_L_SW_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TBC_L_SW_TBC_SHIFT)) & IEE_PC_SW_TBC_L_SW_TBC_MASK) +/*! @} */ + +/*! @name PC_MR_TBC_U - Performance Counter, Upper Master Read Transactions Byte Count */ +/*! @{ */ + +#define IEE_PC_MR_TBC_U_MR_TBC_MASK (0xFFFFU) +#define IEE_PC_MR_TBC_U_MR_TBC_SHIFT (0U) +#define IEE_PC_MR_TBC_U_MR_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TBC_U_MR_TBC_SHIFT)) & IEE_PC_MR_TBC_U_MR_TBC_MASK) +/*! @} */ + +/*! @name PC_MR_TBC_L - Performance Counter, Lower Master Read Transactions Byte Count */ +/*! @{ */ + +#define IEE_PC_MR_TBC_L_MR_TBC_LSB_MASK (0xFU) +#define IEE_PC_MR_TBC_L_MR_TBC_LSB_SHIFT (0U) +#define IEE_PC_MR_TBC_L_MR_TBC_LSB(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TBC_L_MR_TBC_LSB_SHIFT)) & IEE_PC_MR_TBC_L_MR_TBC_LSB_MASK) + +#define IEE_PC_MR_TBC_L_MR_TBC_MASK (0xFFFFFFF0U) +#define IEE_PC_MR_TBC_L_MR_TBC_SHIFT (4U) +#define IEE_PC_MR_TBC_L_MR_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TBC_L_MR_TBC_SHIFT)) & IEE_PC_MR_TBC_L_MR_TBC_MASK) /*! @} */ -/*! @name PC_MR_TBC - Performance Counter, Master Read Transactions Byte Count */ +/*! @name PC_MW_TBC_U - Performance Counter, Upper Master Write Transactions Byte Count */ /*! @{ */ -#define IEE_PC_MR_TBC_MR_TBC_LSB_MASK (0xFU) -#define IEE_PC_MR_TBC_MR_TBC_LSB_SHIFT (0U) -#define IEE_PC_MR_TBC_MR_TBC_LSB(x) (((uint64_t)(((uint64_t)(x)) << IEE_PC_MR_TBC_MR_TBC_LSB_SHIFT)) & IEE_PC_MR_TBC_MR_TBC_LSB_MASK) -#define IEE_PC_MR_TBC_MR_TBC_MASK (0xFFFFFFFFFFF0U) -#define IEE_PC_MR_TBC_MR_TBC_SHIFT (4U) -#define IEE_PC_MR_TBC_MR_TBC(x) (((uint64_t)(((uint64_t)(x)) << IEE_PC_MR_TBC_MR_TBC_SHIFT)) & IEE_PC_MR_TBC_MR_TBC_MASK) + +#define IEE_PC_MW_TBC_U_MW_TBC_MASK (0xFFFFU) +#define IEE_PC_MW_TBC_U_MW_TBC_SHIFT (0U) +#define IEE_PC_MW_TBC_U_MW_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TBC_U_MW_TBC_SHIFT)) & IEE_PC_MW_TBC_U_MW_TBC_MASK) /*! @} */ -/*! @name PC_MW_TBC - Performance Counter, Master Write Transactions Byte Count */ +/*! @name PC_MW_TBC_L - Performance Counter, Lower Master Write Transactions Byte Count */ /*! @{ */ -#define IEE_PC_MW_TBC_MW_TBC_LSB_MASK (0xFU) -#define IEE_PC_MW_TBC_MW_TBC_LSB_SHIFT (0U) -#define IEE_PC_MW_TBC_MW_TBC_LSB(x) (((uint64_t)(((uint64_t)(x)) << IEE_PC_MW_TBC_MW_TBC_LSB_SHIFT)) & IEE_PC_MW_TBC_MW_TBC_LSB_MASK) -#define IEE_PC_MW_TBC_MW_TBC_MASK (0xFFFFFFFFFFF0U) -#define IEE_PC_MW_TBC_MW_TBC_SHIFT (4U) -#define IEE_PC_MW_TBC_MW_TBC(x) (((uint64_t)(((uint64_t)(x)) << IEE_PC_MW_TBC_MW_TBC_SHIFT)) & IEE_PC_MW_TBC_MW_TBC_MASK) + +#define IEE_PC_MW_TBC_L_MW_TBC_LSB_MASK (0xFU) +#define IEE_PC_MW_TBC_L_MW_TBC_LSB_SHIFT (0U) +#define IEE_PC_MW_TBC_L_MW_TBC_LSB(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TBC_L_MW_TBC_LSB_SHIFT)) & IEE_PC_MW_TBC_L_MW_TBC_LSB_MASK) + +#define IEE_PC_MW_TBC_L_MW_TBC_MASK (0xFFFFFFF0U) +#define IEE_PC_MW_TBC_L_MW_TBC_SHIFT (4U) +#define IEE_PC_MW_TBC_L_MW_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TBC_L_MW_TBC_SHIFT)) & IEE_PC_MW_TBC_L_MW_TBC_MASK) /*! @} */ /*! @name PC_SR_TLGTT - Performance Counter, Number of AXI Slave Read Transactions with Latency Greater than the Threshold */ /*! @{ */ + #define IEE_PC_SR_TLGTT_SR_TLGTT_MASK (0xFFFFFFFFU) #define IEE_PC_SR_TLGTT_SR_TLGTT_SHIFT (0U) #define IEE_PC_SR_TLGTT_SR_TLGTT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TLGTT_SR_TLGTT_SHIFT)) & IEE_PC_SR_TLGTT_SR_TLGTT_MASK) @@ -48269,6 +56660,7 @@ typedef struct { /*! @name PC_SW_TLGTT - Performance Counter, Number of AXI Slave Write Transactions with Latency Greater than the Threshold */ /*! @{ */ + #define IEE_PC_SW_TLGTT_SW_TLGTT_MASK (0xFFFFFFFFU) #define IEE_PC_SW_TLGTT_SW_TLGTT_SHIFT (0U) #define IEE_PC_SW_TLGTT_SW_TLGTT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TLGTT_SW_TLGTT_SHIFT)) & IEE_PC_SW_TLGTT_SW_TLGTT_MASK) @@ -48276,6 +56668,7 @@ typedef struct { /*! @name PC_MR_TLGTT - Performance Counter, Number of AXI Master Read Transactions with Latency Greater than the Threshold */ /*! @{ */ + #define IEE_PC_MR_TLGTT_MR_TLGTT_MASK (0xFFFFFFFFU) #define IEE_PC_MR_TLGTT_MR_TLGTT_SHIFT (0U) #define IEE_PC_MR_TLGTT_MR_TLGTT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TLGTT_MR_TLGTT_SHIFT)) & IEE_PC_MR_TLGTT_MR_TLGTT_MASK) @@ -48283,61 +56676,119 @@ typedef struct { /*! @name PC_MW_TLGTT - Performance Counter, Number of AXI Master Write Transactions with Latency Greater than the Threshold */ /*! @{ */ + #define IEE_PC_MW_TLGTT_MW_TGTT_MASK (0xFFFFFFFFU) #define IEE_PC_MW_TLGTT_MW_TGTT_SHIFT (0U) #define IEE_PC_MW_TLGTT_MW_TGTT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TLGTT_MW_TGTT_SHIFT)) & IEE_PC_MW_TLGTT_MW_TGTT_MASK) /*! @} */ -/*! @name PC_SR_TLAT - Performance Counter, Slave Read Latency Count */ +/*! @name PC_SR_TLAT_U - Performance Counter, Upper Slave Read Latency Count */ +/*! @{ */ + +#define IEE_PC_SR_TLAT_U_SR_TLAT_MASK (0xFFFFU) +#define IEE_PC_SR_TLAT_U_SR_TLAT_SHIFT (0U) +#define IEE_PC_SR_TLAT_U_SR_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TLAT_U_SR_TLAT_SHIFT)) & IEE_PC_SR_TLAT_U_SR_TLAT_MASK) +/*! @} */ + +/*! @name PC_SR_TLAT_L - Performance Counter, Lower Slave Read Latency Count */ /*! @{ */ -#define IEE_PC_SR_TLAT_SR_TLAT_MASK (0xFFFFFFFFFFFFU) -#define IEE_PC_SR_TLAT_SR_TLAT_SHIFT (0U) -#define IEE_PC_SR_TLAT_SR_TLAT(x) (((uint64_t)(((uint64_t)(x)) << IEE_PC_SR_TLAT_SR_TLAT_SHIFT)) & IEE_PC_SR_TLAT_SR_TLAT_MASK) + +#define IEE_PC_SR_TLAT_L_SR_TLAT_MASK (0xFFFFFFFFU) +#define IEE_PC_SR_TLAT_L_SR_TLAT_SHIFT (0U) +#define IEE_PC_SR_TLAT_L_SR_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TLAT_L_SR_TLAT_SHIFT)) & IEE_PC_SR_TLAT_L_SR_TLAT_MASK) /*! @} */ -/*! @name PC_SW_TLAT - Performance Counter, Slave Write Latency Count */ +/*! @name PC_SW_TLAT_U - Performance Counter, Upper Slave Write Latency Count */ /*! @{ */ -#define IEE_PC_SW_TLAT_SW_TLAT_MASK (0xFFFFFFFFFFFFU) -#define IEE_PC_SW_TLAT_SW_TLAT_SHIFT (0U) -#define IEE_PC_SW_TLAT_SW_TLAT(x) (((uint64_t)(((uint64_t)(x)) << IEE_PC_SW_TLAT_SW_TLAT_SHIFT)) & IEE_PC_SW_TLAT_SW_TLAT_MASK) + +#define IEE_PC_SW_TLAT_U_SW_TLAT_MASK (0xFFFFU) +#define IEE_PC_SW_TLAT_U_SW_TLAT_SHIFT (0U) +#define IEE_PC_SW_TLAT_U_SW_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TLAT_U_SW_TLAT_SHIFT)) & IEE_PC_SW_TLAT_U_SW_TLAT_MASK) /*! @} */ -/*! @name PC_MR_TLAT - Performance Counter, Master Read Latency Count */ +/*! @name PC_SW_TLAT_L - Performance Counter, Lower Slave Write Latency Count */ /*! @{ */ -#define IEE_PC_MR_TLAT_MR_TLAT_MASK (0xFFFFFFFFFFFFU) -#define IEE_PC_MR_TLAT_MR_TLAT_SHIFT (0U) -#define IEE_PC_MR_TLAT_MR_TLAT(x) (((uint64_t)(((uint64_t)(x)) << IEE_PC_MR_TLAT_MR_TLAT_SHIFT)) & IEE_PC_MR_TLAT_MR_TLAT_MASK) + +#define IEE_PC_SW_TLAT_L_SW_TLAT_MASK (0xFFFFFFFFU) +#define IEE_PC_SW_TLAT_L_SW_TLAT_SHIFT (0U) +#define IEE_PC_SW_TLAT_L_SW_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TLAT_L_SW_TLAT_SHIFT)) & IEE_PC_SW_TLAT_L_SW_TLAT_MASK) /*! @} */ -/*! @name PC_MW_TLAT - Performance Counter, Master Write Latency Count */ +/*! @name PC_MR_TLAT_U - Performance Counter, Upper Master Read Latency Count */ /*! @{ */ -#define IEE_PC_MW_TLAT_MW_TLAT_MASK (0xFFFFFFFFFFFFU) -#define IEE_PC_MW_TLAT_MW_TLAT_SHIFT (0U) -#define IEE_PC_MW_TLAT_MW_TLAT(x) (((uint64_t)(((uint64_t)(x)) << IEE_PC_MW_TLAT_MW_TLAT_SHIFT)) & IEE_PC_MW_TLAT_MW_TLAT_MASK) + +#define IEE_PC_MR_TLAT_U_MR_TLAT_MASK (0xFFFFU) +#define IEE_PC_MR_TLAT_U_MR_TLAT_SHIFT (0U) +#define IEE_PC_MR_TLAT_U_MR_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TLAT_U_MR_TLAT_SHIFT)) & IEE_PC_MR_TLAT_U_MR_TLAT_MASK) /*! @} */ -/*! @name PC_SR_TNRT - Performance Counter, Slave Read Total Non-Responding Time */ +/*! @name PC_MR_TLAT_L - Performance Counter, Lower Master Read Latency Count */ /*! @{ */ -#define IEE_PC_SR_TNRT_SR_TNRT_MASK (0xFFFFFFFFFFFFU) -#define IEE_PC_SR_TNRT_SR_TNRT_SHIFT (0U) -#define IEE_PC_SR_TNRT_SR_TNRT(x) (((uint64_t)(((uint64_t)(x)) << IEE_PC_SR_TNRT_SR_TNRT_SHIFT)) & IEE_PC_SR_TNRT_SR_TNRT_MASK) + +#define IEE_PC_MR_TLAT_L_MR_TLAT_MASK (0xFFFFFFFFU) +#define IEE_PC_MR_TLAT_L_MR_TLAT_SHIFT (0U) +#define IEE_PC_MR_TLAT_L_MR_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TLAT_L_MR_TLAT_SHIFT)) & IEE_PC_MR_TLAT_L_MR_TLAT_MASK) /*! @} */ -/*! @name PC_SW_TNRT - Performance Counter, Slave Write Total Non-Responding Time */ +/*! @name PC_MW_TLAT_U - Performance Counter, Upper Master Write Latency Count */ /*! @{ */ -#define IEE_PC_SW_TNRT_SW_TNRT_MASK (0xFFFFFFFFFFFFU) -#define IEE_PC_SW_TNRT_SW_TNRT_SHIFT (0U) -#define IEE_PC_SW_TNRT_SW_TNRT(x) (((uint64_t)(((uint64_t)(x)) << IEE_PC_SW_TNRT_SW_TNRT_SHIFT)) & IEE_PC_SW_TNRT_SW_TNRT_MASK) + +#define IEE_PC_MW_TLAT_U_MW_TLAT_MASK (0xFFFFU) +#define IEE_PC_MW_TLAT_U_MW_TLAT_SHIFT (0U) +#define IEE_PC_MW_TLAT_U_MW_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TLAT_U_MW_TLAT_SHIFT)) & IEE_PC_MW_TLAT_U_MW_TLAT_MASK) +/*! @} */ + +/*! @name PC_MW_TLAT_L - Performance Counter, Lower Master Write Latency Count */ +/*! @{ */ + +#define IEE_PC_MW_TLAT_L_MW_TLAT_MASK (0xFFFFFFFFU) +#define IEE_PC_MW_TLAT_L_MW_TLAT_SHIFT (0U) +#define IEE_PC_MW_TLAT_L_MW_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TLAT_L_MW_TLAT_SHIFT)) & IEE_PC_MW_TLAT_L_MW_TLAT_MASK) +/*! @} */ + +/*! @name PC_SR_TNRT_U - Performance Counter, Upper Slave Read Total Non-Responding Time */ +/*! @{ */ + +#define IEE_PC_SR_TNRT_U_SR_TNRT_MASK (0xFFFFU) +#define IEE_PC_SR_TNRT_U_SR_TNRT_SHIFT (0U) +#define IEE_PC_SR_TNRT_U_SR_TNRT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TNRT_U_SR_TNRT_SHIFT)) & IEE_PC_SR_TNRT_U_SR_TNRT_MASK) +/*! @} */ + +/*! @name PC_SR_TNRT_L - Performance Counter, Lower Slave Read Total Non-Responding Time */ +/*! @{ */ + +#define IEE_PC_SR_TNRT_L_SR_TNRT_MASK (0xFFFFFFFFU) +#define IEE_PC_SR_TNRT_L_SR_TNRT_SHIFT (0U) +#define IEE_PC_SR_TNRT_L_SR_TNRT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TNRT_L_SR_TNRT_SHIFT)) & IEE_PC_SR_TNRT_L_SR_TNRT_MASK) +/*! @} */ + +/*! @name PC_SW_TNRT_U - Performance Counter, Upper Slave Write Total Non-Responding Time */ +/*! @{ */ + +#define IEE_PC_SW_TNRT_U_SW_TNRT_MASK (0xFFFFU) +#define IEE_PC_SW_TNRT_U_SW_TNRT_SHIFT (0U) +#define IEE_PC_SW_TNRT_U_SW_TNRT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TNRT_U_SW_TNRT_SHIFT)) & IEE_PC_SW_TNRT_U_SW_TNRT_MASK) +/*! @} */ + +/*! @name PC_SW_TNRT_L - Performance Counter, Lower Slave Write Total Non-Responding Time */ +/*! @{ */ + +#define IEE_PC_SW_TNRT_L_SW_TNRT_MASK (0xFFFFFFFFU) +#define IEE_PC_SW_TNRT_L_SW_TNRT_SHIFT (0U) +#define IEE_PC_SW_TNRT_L_SW_TNRT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TNRT_L_SW_TNRT_SHIFT)) & IEE_PC_SW_TNRT_L_SW_TNRT_MASK) /*! @} */ /*! @name VIDR1 - IEE Version ID Register 1 */ /*! @{ */ + #define IEE_VIDR1_MIN_REV_MASK (0xFFU) #define IEE_VIDR1_MIN_REV_SHIFT (0U) #define IEE_VIDR1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << IEE_VIDR1_MIN_REV_SHIFT)) & IEE_VIDR1_MIN_REV_MASK) + #define IEE_VIDR1_MAJ_REV_MASK (0xFF00U) #define IEE_VIDR1_MAJ_REV_SHIFT (8U) #define IEE_VIDR1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << IEE_VIDR1_MAJ_REV_SHIFT)) & IEE_VIDR1_MAJ_REV_MASK) + #define IEE_VIDR1_IP_ID_MASK (0xFFFF0000U) #define IEE_VIDR1_IP_ID_SHIFT (16U) #define IEE_VIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << IEE_VIDR1_IP_ID_SHIFT)) & IEE_VIDR1_IP_ID_MASK) @@ -48345,9 +56796,11 @@ typedef struct { /*! @name AESVID - IEE AES Version ID Register */ /*! @{ */ + #define IEE_AESVID_AESRN_MASK (0xFU) #define IEE_AESVID_AESRN_SHIFT (0U) #define IEE_AESVID_AESRN(x) (((uint32_t)(((uint32_t)(x)) << IEE_AESVID_AESRN_SHIFT)) & IEE_AESVID_AESRN_MASK) + #define IEE_AESVID_AESVID_MASK (0xF0U) #define IEE_AESVID_AESVID_SHIFT (4U) #define IEE_AESVID_AESVID(x) (((uint32_t)(((uint32_t)(x)) << IEE_AESVID_AESVID_SHIFT)) & IEE_AESVID_AESVID_MASK) @@ -48355,6 +56808,7 @@ typedef struct { /*! @name REGATTR - IEE Region 0 Attribute Register...IEE Region 7 Attribute Register. */ /*! @{ */ + #define IEE_REGATTR_KS_MASK (0x1U) #define IEE_REGATTR_KS_SHIFT (0U) /*! KS @@ -48362,6 +56816,7 @@ typedef struct { * 0b1..256 bits (CTR), 512 bits (XTS). */ #define IEE_REGATTR_KS(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_KS_SHIFT)) & IEE_REGATTR_KS_MASK) + #define IEE_REGATTR_MD_MASK (0x70U) #define IEE_REGATTR_MD_SHIFT (4U) /*! MD @@ -48375,6 +56830,7 @@ typedef struct { * 0b111..Undefined, AXI error if used */ #define IEE_REGATTR_MD(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_MD_SHIFT)) & IEE_REGATTR_MD_MASK) + #define IEE_REGATTR_BYP_MASK (0x80U) #define IEE_REGATTR_BYP_SHIFT (7U) /*! BYP @@ -48389,6 +56845,7 @@ typedef struct { /*! @name REGPO - IEE Region 0 Page Offset Register..IEE Region 7 Page Offset Register */ /*! @{ */ + #define IEE_REGPO_PGOFF_MASK (0xFFFFFFU) #define IEE_REGPO_PGOFF_SHIFT (0U) #define IEE_REGPO_PGOFF(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGPO_PGOFF_SHIFT)) & IEE_REGPO_PGOFF_MASK) @@ -48399,6 +56856,7 @@ typedef struct { /*! @name REGKEY1 - IEE Region 0 Key 1 Register..IEE Region 7 Key 1 Register */ /*! @{ */ + #define IEE_REGKEY1_KEY1_MASK (0xFFFFFFFFU) #define IEE_REGKEY1_KEY1_SHIFT (0U) #define IEE_REGKEY1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGKEY1_KEY1_SHIFT)) & IEE_REGKEY1_KEY1_MASK) @@ -48412,6 +56870,7 @@ typedef struct { /*! @name REGKEY2 - IEE Region 0 Key 2 Register..IEE Region 7 Key 2 Register */ /*! @{ */ + #define IEE_REGKEY2_KEY2_MASK (0xFFFFFFFFU) #define IEE_REGKEY2_KEY2_SHIFT (0U) #define IEE_REGKEY2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGKEY2_KEY2_SHIFT)) & IEE_REGKEY2_KEY2_MASK) @@ -48425,99 +56884,131 @@ typedef struct { /*! @name AES_TST_DB - IEE AES Test Mode Data Buffer */ /*! @{ */ + #define IEE_AES_TST_DB_AES_TST_DB0_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB0_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB0(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB0_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB0_MASK) + #define IEE_AES_TST_DB_AES_TST_DB1_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB1_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB1(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB1_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB1_MASK) + #define IEE_AES_TST_DB_AES_TST_DB2_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB2_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB2(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB2_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB2_MASK) + #define IEE_AES_TST_DB_AES_TST_DB3_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB3_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB3(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB3_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB3_MASK) + #define IEE_AES_TST_DB_AES_TST_DB4_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB4_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB4(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB4_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB4_MASK) + #define IEE_AES_TST_DB_AES_TST_DB5_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB5_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB5(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB5_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB5_MASK) + #define IEE_AES_TST_DB_AES_TST_DB6_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB6_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB6(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB6_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB6_MASK) + #define IEE_AES_TST_DB_AES_TST_DB7_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB7_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB7(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB7_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB7_MASK) + #define IEE_AES_TST_DB_AES_TST_DB8_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB8_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB8(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB8_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB8_MASK) + #define IEE_AES_TST_DB_AES_TST_DB9_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB9_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB9(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB9_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB9_MASK) + #define IEE_AES_TST_DB_AES_TST_DB10_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB10_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB10(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB10_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB10_MASK) + #define IEE_AES_TST_DB_AES_TST_DB11_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB11_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB11(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB11_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB11_MASK) + #define IEE_AES_TST_DB_AES_TST_DB12_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB12_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB12(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB12_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB12_MASK) + #define IEE_AES_TST_DB_AES_TST_DB13_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB13_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB13(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB13_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB13_MASK) + #define IEE_AES_TST_DB_AES_TST_DB14_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB14_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB14(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB14_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB14_MASK) + #define IEE_AES_TST_DB_AES_TST_DB15_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB15_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB15(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB15_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB15_MASK) + #define IEE_AES_TST_DB_AES_TST_DB16_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB16_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB16(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB16_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB16_MASK) + #define IEE_AES_TST_DB_AES_TST_DB17_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB17_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB17(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB17_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB17_MASK) + #define IEE_AES_TST_DB_AES_TST_DB18_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB18_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB18(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB18_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB18_MASK) + #define IEE_AES_TST_DB_AES_TST_DB19_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB19_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB19(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB19_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB19_MASK) + #define IEE_AES_TST_DB_AES_TST_DB20_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB20_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB20(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB20_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB20_MASK) + #define IEE_AES_TST_DB_AES_TST_DB21_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB21_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB21(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB21_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB21_MASK) + #define IEE_AES_TST_DB_AES_TST_DB22_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB22_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB22(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB22_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB22_MASK) + #define IEE_AES_TST_DB_AES_TST_DB23_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB23_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB23(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB23_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB23_MASK) + #define IEE_AES_TST_DB_AES_TST_DB24_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB24_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB24(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB24_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB24_MASK) + #define IEE_AES_TST_DB_AES_TST_DB25_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB25_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB25(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB25_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB25_MASK) + #define IEE_AES_TST_DB_AES_TST_DB26_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB26_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB26(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB26_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB26_MASK) + #define IEE_AES_TST_DB_AES_TST_DB27_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB27_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB27(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB27_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB27_MASK) + #define IEE_AES_TST_DB_AES_TST_DB28_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB28_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB28(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB28_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB28_MASK) + #define IEE_AES_TST_DB_AES_TST_DB29_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB29_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB29(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB29_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB29_MASK) + #define IEE_AES_TST_DB_AES_TST_DB30_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB30_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB30(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB30_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB30_MASK) + #define IEE_AES_TST_DB_AES_TST_DB31_MASK (0xFFFFFFFFU) #define IEE_AES_TST_DB_AES_TST_DB31_SHIFT (0U) #define IEE_AES_TST_DB_AES_TST_DB31(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB31_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB31_MASK) @@ -48533,14 +57024,14 @@ typedef struct { /* IEE - Peripheral instance base addresses */ -/** Peripheral IEE__RT1170 base address */ -#define IEE__RT1170_BASE (0u) -/** Peripheral IEE__RT1170 base pointer */ -#define IEE__RT1170 ((IEE_Type *)IEE__RT1170_BASE) +/** Peripheral IEE__IEE_RT1170 base address */ +#define IEE__IEE_RT1170_BASE (0x4006C000u) +/** Peripheral IEE__IEE_RT1170 base pointer */ +#define IEE__IEE_RT1170 ((IEE_Type *)IEE__IEE_RT1170_BASE) /** Array initializer of IEE peripheral base addresses */ -#define IEE_BASE_ADDRS { IEE__RT1170_BASE } +#define IEE_BASE_ADDRS { IEE__IEE_RT1170_BASE } /** Array initializer of IEE peripheral base pointers */ -#define IEE_BASE_PTRS { IEE__RT1170 } +#define IEE_BASE_PTRS { IEE__IEE_RT1170 } /*! * @} @@ -48603,6 +57094,7 @@ typedef struct { /*! @name REGION0_TOP_ADDR - End address of IEE region (n) */ /*! @{ */ + #define IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU) #define IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_SHIFT (0U) /*! TOP_ADDR - End address of IEE region @@ -48612,6 +57104,7 @@ typedef struct { /*! @name REGION0_BOT_ADDR - Start address of IEE region (n) */ /*! @{ */ + #define IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU) #define IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_SHIFT (0U) /*! BOT_ADDR - Start address of IEE region @@ -48621,6 +57114,7 @@ typedef struct { /*! @name REGION0_RDC_D0 - Region control of core domain 0 for region (n) */ /*! @{ */ + #define IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U) #define IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U) /*! RDC_D0_WRITE_DIS - Write disable of core domain 1 @@ -48628,6 +57122,7 @@ typedef struct { * 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled */ #define IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_MASK) + #define IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_MASK (0x2U) #define IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_SHIFT (1U) /*! RDC_D0_LOCK - Lock bit for bit 0 @@ -48639,6 +57134,7 @@ typedef struct { /*! @name REGION0_RDC_D1 - Region control of core domain 1 for region (n) */ /*! @{ */ + #define IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U) #define IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U) /*! RDC_D1_WRITE_DIS - Write disable of core domain 1 @@ -48646,6 +57142,7 @@ typedef struct { * 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled */ #define IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_MASK) + #define IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_MASK (0x2U) #define IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_SHIFT (1U) /*! RDC_D1_LOCK - Lock bit for bit 0 @@ -48657,6 +57154,7 @@ typedef struct { /*! @name REGION1_TOP_ADDR - End address of IEE region (n) */ /*! @{ */ + #define IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU) #define IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_SHIFT (0U) /*! TOP_ADDR - End address of IEE region @@ -48666,6 +57164,7 @@ typedef struct { /*! @name REGION1_BOT_ADDR - Start address of IEE region (n) */ /*! @{ */ + #define IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU) #define IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_SHIFT (0U) /*! BOT_ADDR - Start address of IEE region @@ -48675,6 +57174,7 @@ typedef struct { /*! @name REGION1_RDC_D0 - Region control of core domain 0 for region (n) */ /*! @{ */ + #define IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U) #define IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U) /*! RDC_D0_WRITE_DIS - Write disable of core domain 1 @@ -48682,6 +57182,7 @@ typedef struct { * 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled */ #define IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_MASK) + #define IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_MASK (0x2U) #define IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_SHIFT (1U) /*! RDC_D0_LOCK - Lock bit for bit 0 @@ -48693,6 +57194,7 @@ typedef struct { /*! @name REGION1_RDC_D1 - Region control of core domain 1 for region (n) */ /*! @{ */ + #define IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U) #define IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U) /*! RDC_D1_WRITE_DIS - Write disable of core domain 1 @@ -48700,6 +57202,7 @@ typedef struct { * 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled */ #define IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_MASK) + #define IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_MASK (0x2U) #define IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_SHIFT (1U) /*! RDC_D1_LOCK - Lock bit for bit 0 @@ -48711,6 +57214,7 @@ typedef struct { /*! @name REGION2_TOP_ADDR - End address of IEE region (n) */ /*! @{ */ + #define IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU) #define IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_SHIFT (0U) /*! TOP_ADDR - End address of IEE region @@ -48720,6 +57224,7 @@ typedef struct { /*! @name REGION2_BOT_ADDR - Start address of IEE region (n) */ /*! @{ */ + #define IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU) #define IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_SHIFT (0U) /*! BOT_ADDR - Start address of IEE region @@ -48729,6 +57234,7 @@ typedef struct { /*! @name REGION2_RDC_D0 - Region control of core domain 0 for region (n) */ /*! @{ */ + #define IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U) #define IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U) /*! RDC_D0_WRITE_DIS - Write disable of core domain 1 @@ -48736,6 +57242,7 @@ typedef struct { * 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled */ #define IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_MASK) + #define IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_MASK (0x2U) #define IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_SHIFT (1U) /*! RDC_D0_LOCK - Lock bit for bit 0 @@ -48747,6 +57254,7 @@ typedef struct { /*! @name REGION2_RDC_D1 - Region control of core domain 1 for region (n) */ /*! @{ */ + #define IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U) #define IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U) /*! RDC_D1_WRITE_DIS - Write disable of core domain 1 @@ -48754,6 +57262,7 @@ typedef struct { * 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled */ #define IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_MASK) + #define IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_MASK (0x2U) #define IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_SHIFT (1U) /*! RDC_D1_LOCK - Lock bit for bit 0 @@ -48765,6 +57274,7 @@ typedef struct { /*! @name REGION3_TOP_ADDR - End address of IEE region (n) */ /*! @{ */ + #define IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU) #define IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_SHIFT (0U) /*! TOP_ADDR - End address of IEE region @@ -48774,6 +57284,7 @@ typedef struct { /*! @name REGION3_BOT_ADDR - Start address of IEE region (n) */ /*! @{ */ + #define IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU) #define IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_SHIFT (0U) /*! BOT_ADDR - Start address of IEE region @@ -48783,6 +57294,7 @@ typedef struct { /*! @name REGION3_RDC_D0 - Region control of core domain 0 for region (n) */ /*! @{ */ + #define IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U) #define IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U) /*! RDC_D0_WRITE_DIS - Write disable of core domain 1 @@ -48790,6 +57302,7 @@ typedef struct { * 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled */ #define IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_MASK) + #define IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_MASK (0x2U) #define IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_SHIFT (1U) /*! RDC_D0_LOCK - Lock bit for bit 0 @@ -48801,6 +57314,7 @@ typedef struct { /*! @name REGION3_RDC_D1 - Region control of core domain 1 for region (n) */ /*! @{ */ + #define IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U) #define IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U) /*! RDC_D1_WRITE_DIS - Write disable of core domain 1 @@ -48808,6 +57322,7 @@ typedef struct { * 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled */ #define IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_MASK) + #define IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_MASK (0x2U) #define IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_SHIFT (1U) /*! RDC_D1_LOCK - Lock bit for bit 0 @@ -48819,6 +57334,7 @@ typedef struct { /*! @name REGION4_TOP_ADDR - End address of IEE region (n) */ /*! @{ */ + #define IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU) #define IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_SHIFT (0U) /*! TOP_ADDR - End address of IEE region @@ -48828,6 +57344,7 @@ typedef struct { /*! @name REGION4_BOT_ADDR - Start address of IEE region (n) */ /*! @{ */ + #define IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU) #define IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_SHIFT (0U) /*! BOT_ADDR - Start address of IEE region @@ -48837,6 +57354,7 @@ typedef struct { /*! @name REGION4_RDC_D0 - Region control of core domain 0 for region (n) */ /*! @{ */ + #define IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U) #define IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U) /*! RDC_D0_WRITE_DIS - Write disable of core domain 1 @@ -48844,6 +57362,7 @@ typedef struct { * 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled */ #define IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_MASK) + #define IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_MASK (0x2U) #define IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_SHIFT (1U) /*! RDC_D0_LOCK - Lock bit for bit 0 @@ -48855,6 +57374,7 @@ typedef struct { /*! @name REGION4_RDC_D1 - Region control of core domain 1 for region (n) */ /*! @{ */ + #define IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U) #define IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U) /*! RDC_D1_WRITE_DIS - Write disable of core domain 1 @@ -48862,6 +57382,7 @@ typedef struct { * 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled */ #define IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_MASK) + #define IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_MASK (0x2U) #define IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_SHIFT (1U) /*! RDC_D1_LOCK - Lock bit for bit 0 @@ -48873,6 +57394,7 @@ typedef struct { /*! @name REGION5_TOP_ADDR - End address of IEE region (n) */ /*! @{ */ + #define IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU) #define IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_SHIFT (0U) /*! TOP_ADDR - End address of IEE region @@ -48882,6 +57404,7 @@ typedef struct { /*! @name REGION5_BOT_ADDR - Start address of IEE region (n) */ /*! @{ */ + #define IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU) #define IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_SHIFT (0U) /*! BOT_ADDR - Start address of IEE region @@ -48891,6 +57414,7 @@ typedef struct { /*! @name REGION5_RDC_D0 - Region control of core domain 0 for region (n) */ /*! @{ */ + #define IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U) #define IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U) /*! RDC_D0_WRITE_DIS - Write disable of core domain 1 @@ -48898,6 +57422,7 @@ typedef struct { * 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled */ #define IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_MASK) + #define IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_MASK (0x2U) #define IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_SHIFT (1U) /*! RDC_D0_LOCK - Lock bit for bit 0 @@ -48909,6 +57434,7 @@ typedef struct { /*! @name REGION5_RDC_D1 - Region control of core domain 1 for region (n) */ /*! @{ */ + #define IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U) #define IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U) /*! RDC_D1_WRITE_DIS - Write disable of core domain 1 @@ -48916,6 +57442,7 @@ typedef struct { * 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled */ #define IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_MASK) + #define IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_MASK (0x2U) #define IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_SHIFT (1U) /*! RDC_D1_LOCK - Lock bit for bit 0 @@ -48927,6 +57454,7 @@ typedef struct { /*! @name REGION6_TOP_ADDR - End address of IEE region (n) */ /*! @{ */ + #define IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU) #define IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_SHIFT (0U) /*! TOP_ADDR - End address of IEE region @@ -48936,6 +57464,7 @@ typedef struct { /*! @name REGION6_BOT_ADDR - Start address of IEE region (n) */ /*! @{ */ + #define IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU) #define IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_SHIFT (0U) /*! BOT_ADDR - Start address of IEE region @@ -48945,6 +57474,7 @@ typedef struct { /*! @name REGION6_RDC_D0 - Region control of core domain 0 for region (n) */ /*! @{ */ + #define IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U) #define IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U) /*! RDC_D0_WRITE_DIS - Write disable of core domain 1 @@ -48952,6 +57482,7 @@ typedef struct { * 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled */ #define IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_MASK) + #define IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_MASK (0x2U) #define IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_SHIFT (1U) /*! RDC_D0_LOCK - Lock bit for bit 0 @@ -48963,6 +57494,7 @@ typedef struct { /*! @name REGION6_RDC_D1 - Region control of core domain 1 for region (n) */ /*! @{ */ + #define IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U) #define IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U) /*! RDC_D1_WRITE_DIS - Write disable of core domain 1 @@ -48970,6 +57502,7 @@ typedef struct { * 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled */ #define IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_MASK) + #define IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_MASK (0x2U) #define IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_SHIFT (1U) /*! RDC_D1_LOCK - Lock bit for bit 0 @@ -48981,6 +57514,7 @@ typedef struct { /*! @name REGION7_TOP_ADDR - End address of IEE region (n) */ /*! @{ */ + #define IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU) #define IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_SHIFT (0U) /*! TOP_ADDR - End address of IEE region @@ -48990,6 +57524,7 @@ typedef struct { /*! @name REGION7_BOT_ADDR - Start address of IEE region (n) */ /*! @{ */ + #define IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU) #define IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_SHIFT (0U) /*! BOT_ADDR - Start address of IEE region @@ -48999,6 +57534,7 @@ typedef struct { /*! @name REGION7_RDC_D0 - Region control of core domain 0 for region (n) */ /*! @{ */ + #define IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U) #define IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U) /*! RDC_D0_WRITE_DIS - Write disable of core domain 1 @@ -49006,6 +57542,7 @@ typedef struct { * 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled */ #define IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_MASK) + #define IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_MASK (0x2U) #define IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_SHIFT (1U) /*! RDC_D0_LOCK - Lock bit for bit 0 @@ -49017,6 +57554,7 @@ typedef struct { /*! @name REGION7_RDC_D1 - Region control of core domain 1 for region (n) */ /*! @{ */ + #define IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U) #define IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U) /*! RDC_D1_WRITE_DIS - Write disable of core domain 1 @@ -49024,6 +57562,7 @@ typedef struct { * 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled */ #define IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_MASK) + #define IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_MASK (0x2U) #define IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_SHIFT (1U) /*! RDC_D1_LOCK - Lock bit for bit 0 @@ -49082,6 +57621,7 @@ typedef struct { /*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_EMC_B1_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_DISP_B2_15 SW MUX Control Register */ /*! @{ */ + #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xFU) #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) /*! MUX_MODE - MUX Mode Select Field. @@ -49092,6 +57632,7 @@ typedef struct { * 0b1010..Select mux mode: ALT10 mux port: GPIO7_IO00 of instance: GPIO7 */ #define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK) + #define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U) #define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U) /*! SION - Software Input On Field. @@ -49106,6 +57647,7 @@ typedef struct { /*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_EMC_B1_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_DISP_B2_15 SW PAD Control Register */ /*! @{ */ + #define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x1U) #define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (0U) /*! SRE - Slew Rate Field @@ -49113,20 +57655,23 @@ typedef struct { * 0b1..Fast Slew Rate */ #define IOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK) + #define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x2U) #define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (1U) /*! DSE - Drive Strength Field - * 0b0..normal driver - * 0b1..high driver + * 0b0..normal drive strength + * 0b1..high drive strength */ #define IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK) + #define IOMUXC_SW_PAD_CTL_PAD_PDRV_MASK (0x2U) #define IOMUXC_SW_PAD_CTL_PAD_PDRV_SHIFT (1U) /*! PDRV - PDRV Field - * 0b0..high driver - * 0b1..normal driver + * 0b0..high drive strength + * 0b1..normal drive strength */ #define IOMUXC_SW_PAD_CTL_PAD_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PDRV_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PDRV_MASK) + #define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x4U) #define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (2U) /*! PUE - Pull / Keep Select Field @@ -49134,15 +57679,17 @@ typedef struct { * 0b1..Pull Enable */ #define IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK) + #define IOMUXC_SW_PAD_CTL_PAD_PULL_MASK (0xCU) #define IOMUXC_SW_PAD_CTL_PAD_PULL_SHIFT (2U) /*! PULL - Pull Down Pull Up Field * 0b00..Forbidden - * 0b01..PU - * 0b10..PD + * 0b01..Internal pullup resistor enabled + * 0b10..Internal pulldown resistor enabled * 0b11..No Pull */ #define IOMUXC_SW_PAD_CTL_PAD_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PULL_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PULL_MASK) + #define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK (0x8U) #define IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT (3U) /*! PUS - Pull Up / Down Config. Field @@ -49150,6 +57697,7 @@ typedef struct { * 0b1..Weak pull up */ #define IOMUXC_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK) + #define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x10U) #define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (4U) /*! ODE - Open Drain Field @@ -49157,6 +57705,7 @@ typedef struct { * 0b1..Enabled */ #define IOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK) + #define IOMUXC_SW_PAD_CTL_PAD_DWP_MASK (0x30000000U) #define IOMUXC_SW_PAD_CTL_PAD_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -49166,6 +57715,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_SW_PAD_CTL_PAD_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DWP_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DWP_MASK) + #define IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -49182,6 +57732,7 @@ typedef struct { /*! @name SELECT_INPUT - FLEXCAN1_RX_SELECT_INPUT DAISY Register..XBAR1_IN_SELECT_INPUT_35 DAISY Register */ /*! @{ */ + #define IOMUXC_SELECT_INPUT_DAISY_MASK (0x3U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ #define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U) /*! DAISY - Selecting Pads Involved in Daisy Chain. @@ -49314,26 +57865,31 @@ typedef struct { /*! @name GPR0 - GPR0 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK (0x7U) #define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT (0U) /*! SAI1_MCLK1_SEL - SAI1 MCLK1 source select */ #define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK) + #define IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_MASK (0x38U) #define IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_SHIFT (3U) /*! SAI1_MCLK2_SEL - SAI1 MCLK2 source select */ #define IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_MASK) + #define IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_MASK (0xC0U) #define IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_SHIFT (6U) /*! SAI1_MCLK3_SEL - SAI1 MCLK3 source select */ #define IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_MASK) + #define IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_MASK (0x100U) #define IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_SHIFT (8U) -/*! SAI1_MCLK_DIR - sai1.MCLK signal direction control +/*! SAI1_MCLK_DIR - SAI1_MCLK signal direction control */ #define IOMUXC_GPR_GPR0_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_MASK) + #define IOMUXC_GPR_GPR0_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR0_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -49343,6 +57899,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR0_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DWP_SHIFT)) & IOMUXC_GPR_GPR0_DWP_MASK) + #define IOMUXC_GPR_GPR0_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR0_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -49356,16 +57913,19 @@ typedef struct { /*! @name GPR1 - GPR1 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK (0x3U) #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (0U) /*! SAI2_MCLK3_SEL - SAI2 MCLK3 source select */ #define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK) + #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100U) #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (8U) -/*! SAI2_MCLK_DIR - sai2.MCLK signal direction control +/*! SAI2_MCLK_DIR - SAI2_MCLK signal direction control */ #define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK) + #define IOMUXC_GPR_GPR1_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR1_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -49375,6 +57935,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR1_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_DWP_SHIFT)) & IOMUXC_GPR_GPR1_DWP_MASK) + #define IOMUXC_GPR_GPR1_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR1_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -49388,21 +57949,25 @@ typedef struct { /*! @name GPR2 - GPR2 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_MASK (0x3U) #define IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_SHIFT (0U) /*! SAI3_MCLK3_SEL - SAI3 MCLK3 source select */ #define IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_MASK) + #define IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_MASK (0x100U) #define IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_SHIFT (8U) -/*! SAI3_MCLK_DIR - sai3.MCLK signal direction control +/*! SAI3_MCLK_DIR - SAI3_MCLK signal direction control */ #define IOMUXC_GPR_GPR2_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_MASK) + #define IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_MASK (0x200U) #define IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_SHIFT (9U) -/*! SAI4_MCLK_DIR - sai4.MCLK signal direction control +/*! SAI4_MCLK_DIR - SAI4_MCLK signal direction control */ #define IOMUXC_GPR_GPR2_SAI4_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_MASK) + #define IOMUXC_GPR_GPR2_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR2_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -49412,6 +57977,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR2_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DWP_SHIFT)) & IOMUXC_GPR_GPR2_DWP_MASK) + #define IOMUXC_GPR_GPR2_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR2_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -49425,26 +57991,31 @@ typedef struct { /*! @name GPR3 - GPR3 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR3_MQS_CLK_DIV_MASK (0xFFU) #define IOMUXC_GPR_GPR3_MQS_CLK_DIV_SHIFT (0U) -/*! MQS_CLK_DIV - Divider ratio control for mclk from hmclk. mclk frequency = 1/(n+1) * hmclk frequency. +/*! MQS_CLK_DIV - Divider ratio control for mclk from hmclk. */ #define IOMUXC_GPR_GPR3_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR3_MQS_CLK_DIV_MASK) + #define IOMUXC_GPR_GPR3_MQS_SW_RST_MASK (0x100U) #define IOMUXC_GPR_GPR3_MQS_SW_RST_SHIFT (8U) /*! MQS_SW_RST - MQS software reset */ #define IOMUXC_GPR_GPR3_MQS_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR3_MQS_SW_RST_MASK) + #define IOMUXC_GPR_GPR3_MQS_EN_MASK (0x200U) #define IOMUXC_GPR_GPR3_MQS_EN_SHIFT (9U) /*! MQS_EN - MQS enable */ #define IOMUXC_GPR_GPR3_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR3_MQS_EN_MASK) + #define IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_MASK (0x400U) #define IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_SHIFT (10U) /*! MQS_OVERSAMPLE - Medium Quality Sound (MQS) Oversample */ #define IOMUXC_GPR_GPR3_MQS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_MASK) + #define IOMUXC_GPR_GPR3_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR3_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -49454,6 +58025,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR3_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DWP_SHIFT)) & IOMUXC_GPR_GPR3_DWP_MASK) + #define IOMUXC_GPR_GPR3_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR3_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -49467,26 +58039,31 @@ typedef struct { /*! @name GPR4 - GPR4 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_MASK (0x1U) #define IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_SHIFT (0U) /*! ENET_TX_CLK_SEL - ENET TX_CLK select */ #define IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_MASK) + #define IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK (0x2U) #define IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_SHIFT (1U) /*! ENET_REF_CLK_DIR - ENET_REF_CLK direction control */ #define IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK) + #define IOMUXC_GPR_GPR4_ENET_TIME_SEL_MASK (0x4U) #define IOMUXC_GPR_GPR4_ENET_TIME_SEL_SHIFT (2U) /*! ENET_TIME_SEL - ENET master timer source select */ #define IOMUXC_GPR_GPR4_ENET_TIME_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_TIME_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_TIME_SEL_MASK) + #define IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_MASK (0x8U) #define IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_SHIFT (3U) /*! ENET_EVENT0IN_SEL - ENET ENET_1588_EVENT0_IN source select */ #define IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_MASK) + #define IOMUXC_GPR_GPR4_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR4_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -49496,6 +58073,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR4_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_DWP_SHIFT)) & IOMUXC_GPR_GPR4_DWP_MASK) + #define IOMUXC_GPR_GPR4_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR4_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -49509,31 +58087,37 @@ typedef struct { /*! @name GPR5 - GPR5 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK (0x1U) #define IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_SHIFT (0U) /*! ENET1G_TX_CLK_SEL - ENET1G TX_CLK select */ #define IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK) + #define IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK (0x2U) #define IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_SHIFT (1U) /*! ENET1G_REF_CLK_DIR - ENET1G_REF_CLK direction control */ #define IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK) + #define IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK (0x4U) #define IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_SHIFT (2U) /*! ENET1G_RGMII_EN - ENET1G RGMII TX clock output enable */ #define IOMUXC_GPR_GPR5_ENET1G_RGMII_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK) + #define IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_MASK (0x8U) #define IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_SHIFT (3U) /*! ENET1G_TIME_SEL - ENET1G master timer source select */ #define IOMUXC_GPR_GPR5_ENET1G_TIME_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_MASK) + #define IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_MASK (0x10U) #define IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_SHIFT (4U) /*! ENET1G_EVENT0IN_SEL - ENET1G ENET_1588_EVENT0_IN source select */ #define IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_MASK) + #define IOMUXC_GPR_GPR5_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR5_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -49543,6 +58127,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR5_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_DWP_SHIFT)) & IOMUXC_GPR_GPR5_DWP_MASK) + #define IOMUXC_GPR_GPR5_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR5_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -49556,36 +58141,43 @@ typedef struct { /*! @name GPR6 - GPR6 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_MASK (0x1U) #define IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_SHIFT (0U) /*! ENET_QOS_REF_CLK_DIR - ENET_QOS_REF_CLK direction control */ #define IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_MASK) + #define IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_MASK (0x2U) #define IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_SHIFT (1U) /*! ENET_QOS_RGMII_EN - ENET_QOS RGMII TX clock output enable */ #define IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_SHIFT)) & IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_MASK) + #define IOMUXC_GPR_GPR6_ENET_QOS_TIME_SEL_MASK (0x4U) #define IOMUXC_GPR_GPR6_ENET_QOS_TIME_SEL_SHIFT (2U) /*! ENET_QOS_TIME_SEL - ENET_QOS master timer source select */ #define IOMUXC_GPR_GPR6_ENET_QOS_TIME_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_ENET_QOS_TIME_SEL_SHIFT)) & IOMUXC_GPR_GPR6_ENET_QOS_TIME_SEL_MASK) + #define IOMUXC_GPR_GPR6_ENET_QOS_INTF_SEL_MASK (0x38U) #define IOMUXC_GPR_GPR6_ENET_QOS_INTF_SEL_SHIFT (3U) /*! ENET_QOS_INTF_SEL - ENET_QOS PHY Interface Select */ #define IOMUXC_GPR_GPR6_ENET_QOS_INTF_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_ENET_QOS_INTF_SEL_SHIFT)) & IOMUXC_GPR_GPR6_ENET_QOS_INTF_SEL_MASK) + #define IOMUXC_GPR_GPR6_ENET_QOS_CLKGEN_EN_MASK (0x40U) #define IOMUXC_GPR_GPR6_ENET_QOS_CLKGEN_EN_SHIFT (6U) /*! ENET_QOS_CLKGEN_EN - ENET_QOS clock generator enable */ #define IOMUXC_GPR_GPR6_ENET_QOS_CLKGEN_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_ENET_QOS_CLKGEN_EN_SHIFT)) & IOMUXC_GPR_GPR6_ENET_QOS_CLKGEN_EN_MASK) + #define IOMUXC_GPR_GPR6_ENET_QOS_EVENT0IN_SEL_MASK (0x80U) #define IOMUXC_GPR_GPR6_ENET_QOS_EVENT0IN_SEL_SHIFT (7U) /*! ENET_QOS_EVENT0IN_SEL - ENET_QOS ENET_1588_EVENT0_IN source select */ #define IOMUXC_GPR_GPR6_ENET_QOS_EVENT0IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_ENET_QOS_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR6_ENET_QOS_EVENT0IN_SEL_MASK) + #define IOMUXC_GPR_GPR6_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR6_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -49595,6 +58187,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR6_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_DWP_SHIFT)) & IOMUXC_GPR_GPR6_DWP_MASK) + #define IOMUXC_GPR_GPR6_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR6_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -49608,11 +58201,13 @@ typedef struct { /*! @name GPR7 - GPR7 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR7_GINT_MASK (0x1U) #define IOMUXC_GPR_GPR7_GINT_SHIFT (0U) /*! GINT - Global interrupt */ #define IOMUXC_GPR_GPR7_GINT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_GINT_SHIFT)) & IOMUXC_GPR_GPR7_GINT_MASK) + #define IOMUXC_GPR_GPR7_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR7_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -49622,6 +58217,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR7_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_DWP_SHIFT)) & IOMUXC_GPR_GPR7_DWP_MASK) + #define IOMUXC_GPR_GPR7_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR7_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -49635,11 +58231,13 @@ typedef struct { /*! @name GPR8 - GPR8 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR8_WDOG1_MASK_MASK (0x1U) #define IOMUXC_GPR_GPR8_WDOG1_MASK_SHIFT (0U) /*! WDOG1_MASK - WDOG1 timeout mask for WDOG_ANY */ #define IOMUXC_GPR_GPR8_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR8_WDOG1_MASK_MASK) + #define IOMUXC_GPR_GPR8_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR8_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -49649,6 +58247,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR8_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_DWP_SHIFT)) & IOMUXC_GPR_GPR8_DWP_MASK) + #define IOMUXC_GPR_GPR8_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR8_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -49662,11 +58261,13 @@ typedef struct { /*! @name GPR9 - GPR9 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR9_WDOG2_MASK_MASK (0x1U) #define IOMUXC_GPR_GPR9_WDOG2_MASK_SHIFT (0U) /*! WDOG2_MASK - WDOG2 timeout mask for WDOG_ANY */ #define IOMUXC_GPR_GPR9_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR9_WDOG2_MASK_MASK) + #define IOMUXC_GPR_GPR9_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR9_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -49676,6 +58277,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR9_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_DWP_SHIFT)) & IOMUXC_GPR_GPR9_DWP_MASK) + #define IOMUXC_GPR_GPR9_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR9_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -49689,6 +58291,7 @@ typedef struct { /*! @name GPR10 - GPR10 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR10_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR10_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -49698,6 +58301,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR10_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DWP_SHIFT)) & IOMUXC_GPR_GPR10_DWP_MASK) + #define IOMUXC_GPR_GPR10_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR10_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -49711,6 +58315,7 @@ typedef struct { /*! @name GPR11 - GPR11 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR11_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR11_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -49720,6 +58325,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR11_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_DWP_SHIFT)) & IOMUXC_GPR_GPR11_DWP_MASK) + #define IOMUXC_GPR_GPR11_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR11_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -49733,31 +58339,37 @@ typedef struct { /*! @name GPR12 - GPR12 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_MASK (0x1U) #define IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_SHIFT (0U) /*! QTIMER1_TMR_CNTS_FREEZE - QTIMER1 timer counter freeze */ #define IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_MASK) + #define IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_MASK (0x100U) #define IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_SHIFT (8U) /*! QTIMER1_TRM0_INPUT_SEL - QTIMER1 TMR0 input select */ #define IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_MASK) + #define IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_MASK (0x200U) #define IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_SHIFT (9U) /*! QTIMER1_TRM1_INPUT_SEL - QTIMER1 TMR1 input select */ #define IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_MASK) + #define IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_MASK (0x400U) #define IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_SHIFT (10U) /*! QTIMER1_TRM2_INPUT_SEL - QTIMER1 TMR2 input select */ #define IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_MASK) + #define IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_MASK (0x800U) #define IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_SHIFT (11U) /*! QTIMER1_TRM3_INPUT_SEL - QTIMER1 TMR3 input select */ #define IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_MASK) + #define IOMUXC_GPR_GPR12_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR12_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -49767,6 +58379,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR12_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_DWP_SHIFT)) & IOMUXC_GPR_GPR12_DWP_MASK) + #define IOMUXC_GPR_GPR12_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR12_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -49780,31 +58393,37 @@ typedef struct { /*! @name GPR13 - GPR13 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_MASK (0x1U) #define IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_SHIFT (0U) /*! QTIMER2_TMR_CNTS_FREEZE - QTIMER2 timer counter freeze */ #define IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_MASK) + #define IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_MASK (0x100U) #define IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_SHIFT (8U) /*! QTIMER2_TRM0_INPUT_SEL - QTIMER2 TMR0 input select */ #define IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_MASK) + #define IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_MASK (0x200U) #define IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_SHIFT (9U) /*! QTIMER2_TRM1_INPUT_SEL - QTIMER2 TMR1 input select */ #define IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_MASK) + #define IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_MASK (0x400U) #define IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_SHIFT (10U) /*! QTIMER2_TRM2_INPUT_SEL - QTIMER2 TMR2 input select */ #define IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_MASK) + #define IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_MASK (0x800U) #define IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_SHIFT (11U) /*! QTIMER2_TRM3_INPUT_SEL - QTIMER2 TMR3 input select */ #define IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_MASK) + #define IOMUXC_GPR_GPR13_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR13_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -49814,6 +58433,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR13_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_DWP_SHIFT)) & IOMUXC_GPR_GPR13_DWP_MASK) + #define IOMUXC_GPR_GPR13_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR13_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -49827,31 +58447,37 @@ typedef struct { /*! @name GPR14 - GPR14 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_MASK (0x1U) #define IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_SHIFT (0U) /*! QTIMER3_TMR_CNTS_FREEZE - QTIMER3 timer counter freeze */ #define IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_MASK) + #define IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_MASK (0x100U) #define IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_SHIFT (8U) /*! QTIMER3_TRM0_INPUT_SEL - QTIMER3 TMR0 input select */ #define IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_MASK) + #define IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_MASK (0x200U) #define IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_SHIFT (9U) /*! QTIMER3_TRM1_INPUT_SEL - QTIMER3 TMR1 input select */ #define IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_MASK) + #define IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_MASK (0x400U) #define IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_SHIFT (10U) /*! QTIMER3_TRM2_INPUT_SEL - QTIMER3 TMR2 input select */ #define IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_MASK) + #define IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_MASK (0x800U) #define IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_SHIFT (11U) /*! QTIMER3_TRM3_INPUT_SEL - QTIMER3 TMR3 input select */ #define IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_MASK) + #define IOMUXC_GPR_GPR14_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR14_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -49861,6 +58487,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR14_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_DWP_SHIFT)) & IOMUXC_GPR_GPR14_DWP_MASK) + #define IOMUXC_GPR_GPR14_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR14_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -49874,31 +58501,37 @@ typedef struct { /*! @name GPR15 - GPR15 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_MASK (0x1U) #define IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_SHIFT (0U) /*! QTIMER4_TMR_CNTS_FREEZE - QTIMER4 timer counter freeze */ #define IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_MASK) + #define IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_MASK (0x100U) #define IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_SHIFT (8U) /*! QTIMER4_TRM0_INPUT_SEL - QTIMER4 TMR0 input select */ #define IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_MASK) + #define IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_MASK (0x200U) #define IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_SHIFT (9U) /*! QTIMER4_TRM1_INPUT_SEL - QTIMER4 TMR1 input select */ #define IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_MASK) + #define IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_MASK (0x400U) #define IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_SHIFT (10U) /*! QTIMER4_TRM2_INPUT_SEL - QTIMER4 TMR2 input select */ #define IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_MASK) + #define IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_MASK (0x800U) #define IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_SHIFT (11U) /*! QTIMER4_TRM3_INPUT_SEL - QTIMER4 TMR3 input select */ #define IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_MASK) + #define IOMUXC_GPR_GPR15_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR15_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -49908,6 +58541,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR15_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_DWP_SHIFT)) & IOMUXC_GPR_GPR15_DWP_MASK) + #define IOMUXC_GPR_GPR15_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR15_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -49921,59 +58555,25 @@ typedef struct { /*! @name GPR16 - GPR16 General Purpose Register */ /*! @{ */ -#define IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK (0x1U) -#define IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT (0U) -/*! INIT_ITCM_EN - * 0b0..ITCM is disabled - * 0b1..ITCM is enabled - */ -#define IOMUXC_GPR_GPR16_INIT_ITCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_ITCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK) -#define IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK (0x2U) -#define IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT (1U) -/*! INIT_DTCM_EN - * 0b0..DTCM is disabled - * 0b1..DTCM is enabled - */ -#define IOMUXC_GPR_GPR16_INIT_DTCM_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_INIT_DTCM_EN_SHIFT)) & IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK) + #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U) #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U) /*! FLEXRAM_BANK_CFG_SEL - FlexRAM bank config source select */ #define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK) + #define IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_MASK (0x8U) #define IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_SHIFT (3U) /*! CM7_FORCE_HCLK_EN - CM7 platform AHB clock enable */ #define IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_MASK) + #define IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_MASK (0x20U) #define IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_SHIFT (5U) /*! M7_GPC_SLEEP_SEL - CM7 sleep request selection */ #define IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_SHIFT)) & IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_MASK) -#define IOMUXC_GPR_GPR16_CM7_CFGITCMSZ_MASK (0xF0000U) -#define IOMUXC_GPR_GPR16_CM7_CFGITCMSZ_SHIFT (8U) -/*! CM7_CFGITCMSZ - * 0b0000..0 KB (No ITCM) - * 0b0011..4 KB - * 0b0100..8 KB - * 0b0101..16 KB - * 0b0110..32 KB - * 0b0111..64 KB - * 0b1000..128 KB - */ -#define IOMUXC_GPR_GPR16_CM7_CFGITCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_CM7_CFGITCMSZ_SHIFT)) & IOMUXC_GPR_GPR16_CM7_CFGITCMSZ_MASK) -#define IOMUXC_GPR_GPR16_CM7_CFGDTCMSZ_MASK (0xF00000U) -#define IOMUXC_GPR_GPR16_CM7_CFGDTCMSZ_SHIFT (12U) -/*! CM7_CFGDTCMSZ - * 0b0000..0 KB (No DTCM) - * 0b0011..4 KB - * 0b0100..8 KB - * 0b0101..16 KB - * 0b0110..32 KB - * 0b0111..64 KB - * 0b1000..128 KB - */ -#define IOMUXC_GPR_GPR16_CM7_CFGDTCMSZ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_CM7_CFGDTCMSZ_SHIFT)) & IOMUXC_GPR_GPR16_CM7_CFGDTCMSZ_MASK) + #define IOMUXC_GPR_GPR16_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR16_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -49983,6 +58583,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR16_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_DWP_SHIFT)) & IOMUXC_GPR_GPR16_DWP_MASK) + #define IOMUXC_GPR_GPR16_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR16_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -49996,11 +58597,13 @@ typedef struct { /*! @name GPR17 - GPR17 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK (0xFFFFU) #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_SHIFT (0U) /*! FLEXRAM_BANK_CFG_LOW - FlexRAM bank config value */ #define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK) + #define IOMUXC_GPR_GPR17_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR17_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -50010,6 +58613,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR17_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_DWP_SHIFT)) & IOMUXC_GPR_GPR17_DWP_MASK) + #define IOMUXC_GPR_GPR17_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR17_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -50023,11 +58627,13 @@ typedef struct { /*! @name GPR18 - GPR18 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_MASK (0xFFFFU) #define IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_SHIFT (0U) /*! FLEXRAM_BANK_CFG_HIGH - FlexRAM bank config value */ #define IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_SHIFT)) & IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_MASK) + #define IOMUXC_GPR_GPR18_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR18_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -50037,6 +58643,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR18_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_DWP_SHIFT)) & IOMUXC_GPR_GPR18_DWP_MASK) + #define IOMUXC_GPR_GPR18_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR18_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -50050,146 +58657,175 @@ typedef struct { /*! @name GPR20 - GPR20 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_MASK (0x1U) #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_SHIFT (0U) /*! IOMUXC_XBAR_DIR_SEL_4 - IOMUXC XBAR_INOUT4 function direction select */ #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_MASK) + #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_MASK (0x2U) #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_SHIFT (1U) /*! IOMUXC_XBAR_DIR_SEL_5 - IOMUXC XBAR_INOUT5 function direction select */ #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_MASK) + #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_MASK (0x4U) #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_SHIFT (2U) /*! IOMUXC_XBAR_DIR_SEL_6 - IOMUXC XBAR_INOUT6 function direction select */ #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_MASK) + #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_MASK (0x8U) #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_SHIFT (3U) /*! IOMUXC_XBAR_DIR_SEL_7 - IOMUXC XBAR_INOUT7 function direction select */ #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_MASK) + #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_MASK (0x10U) #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_SHIFT (4U) /*! IOMUXC_XBAR_DIR_SEL_8 - IOMUXC XBAR_INOUT8 function direction select */ #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_MASK) + #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_MASK (0x20U) #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_SHIFT (5U) /*! IOMUXC_XBAR_DIR_SEL_9 - IOMUXC XBAR_INOUT9 function direction select */ #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_MASK) + #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_MASK (0x40U) #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_SHIFT (6U) /*! IOMUXC_XBAR_DIR_SEL_10 - IOMUXC XBAR_INOUT10 function direction select */ #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_MASK) + #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_MASK (0x80U) #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_SHIFT (7U) /*! IOMUXC_XBAR_DIR_SEL_11 - IOMUXC XBAR_INOUT11 function direction select */ #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_MASK) + #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_MASK (0x100U) #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_SHIFT (8U) /*! IOMUXC_XBAR_DIR_SEL_12 - IOMUXC XBAR_INOUT12 function direction select */ #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_MASK) + #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_MASK (0x200U) #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_SHIFT (9U) /*! IOMUXC_XBAR_DIR_SEL_13 - IOMUXC XBAR_INOUT13 function direction select */ #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_MASK) + #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_MASK (0x400U) #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_SHIFT (10U) /*! IOMUXC_XBAR_DIR_SEL_14 - IOMUXC XBAR_INOUT14 function direction select */ #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_MASK) + #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_MASK (0x800U) #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_SHIFT (11U) /*! IOMUXC_XBAR_DIR_SEL_15 - IOMUXC XBAR_INOUT15 function direction select */ #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_MASK) + #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_MASK (0x1000U) #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_SHIFT (12U) /*! IOMUXC_XBAR_DIR_SEL_16 - IOMUXC XBAR_INOUT16 function direction select */ #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_MASK) + #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_MASK (0x2000U) #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_SHIFT (13U) /*! IOMUXC_XBAR_DIR_SEL_17 - IOMUXC XBAR_INOUT17 function direction select */ #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_MASK) + #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_MASK (0x4000U) #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_SHIFT (14U) /*! IOMUXC_XBAR_DIR_SEL_18 - IOMUXC XBAR_INOUT18 function direction select */ #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_MASK) + #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_MASK (0x8000U) #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_SHIFT (15U) /*! IOMUXC_XBAR_DIR_SEL_19 - IOMUXC XBAR_INOUT19 function direction select */ #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_MASK) + #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_MASK (0x10000U) #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_SHIFT (16U) /*! IOMUXC_XBAR_DIR_SEL_20 - IOMUXC XBAR_INOUT20 function direction select */ #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_MASK) + #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_MASK (0x20000U) #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_SHIFT (17U) /*! IOMUXC_XBAR_DIR_SEL_21 - IOMUXC XBAR_INOUT21 function direction select */ #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_MASK) + #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_MASK (0x40000U) #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_SHIFT (18U) /*! IOMUXC_XBAR_DIR_SEL_22 - IOMUXC XBAR_INOUT22 function direction select */ #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_MASK) + #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_MASK (0x80000U) #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_SHIFT (19U) /*! IOMUXC_XBAR_DIR_SEL_23 - IOMUXC XBAR_INOUT23 function direction select */ #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_MASK) + #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_MASK (0x100000U) #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_SHIFT (20U) /*! IOMUXC_XBAR_DIR_SEL_24 - IOMUXC XBAR_INOUT24 function direction select */ #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_MASK) + #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_MASK (0x200000U) #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_SHIFT (21U) /*! IOMUXC_XBAR_DIR_SEL_25 - IOMUXC XBAR_INOUT25 function direction select */ #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_MASK) + #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_MASK (0x400000U) #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_SHIFT (22U) /*! IOMUXC_XBAR_DIR_SEL_26 - IOMUXC XBAR_INOUT26 function direction select */ #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_MASK) + #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_MASK (0x800000U) #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_SHIFT (23U) /*! IOMUXC_XBAR_DIR_SEL_27 - IOMUXC XBAR_INOUT27 function direction select */ #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_MASK) + #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_MASK (0x1000000U) #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_SHIFT (24U) /*! IOMUXC_XBAR_DIR_SEL_28 - IOMUXC XBAR_INOUT28 function direction select */ #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_MASK) + #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_MASK (0x2000000U) #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_SHIFT (25U) /*! IOMUXC_XBAR_DIR_SEL_29 - IOMUXC XBAR_INOUT29 function direction select */ #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_MASK) + #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_MASK (0x4000000U) #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_SHIFT (26U) /*! IOMUXC_XBAR_DIR_SEL_30 - IOMUXC XBAR_INOUT30 function direction select */ #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_MASK) + #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_MASK (0x8000000U) #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_SHIFT (27U) /*! IOMUXC_XBAR_DIR_SEL_31 - IOMUXC XBAR_INOUT31 function direction select */ #define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_MASK) + #define IOMUXC_GPR_GPR20_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR20_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -50199,6 +58835,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR20_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_DWP_SHIFT)) & IOMUXC_GPR_GPR20_DWP_MASK) + #define IOMUXC_GPR_GPR20_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR20_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -50212,61 +58849,73 @@ typedef struct { /*! @name GPR21 - GPR21 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_MASK (0x1U) #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_SHIFT (0U) /*! IOMUXC_XBAR_DIR_SEL_32 - IOMUXC XBAR_INOUT32 function direction select */ #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_MASK) + #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_MASK (0x2U) #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_SHIFT (1U) /*! IOMUXC_XBAR_DIR_SEL_33 - IOMUXC XBAR_INOUT33 function direction select */ #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_MASK) + #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_MASK (0x4U) #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_SHIFT (2U) /*! IOMUXC_XBAR_DIR_SEL_34 - IOMUXC XBAR_INOUT34 function direction select */ #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_MASK) + #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_MASK (0x8U) #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_SHIFT (3U) /*! IOMUXC_XBAR_DIR_SEL_35 - IOMUXC XBAR_INOUT35 function direction select */ #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_MASK) + #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_MASK (0x10U) #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_SHIFT (4U) /*! IOMUXC_XBAR_DIR_SEL_36 - IOMUXC XBAR_INOUT36 function direction select */ #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_MASK) + #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_MASK (0x20U) #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_SHIFT (5U) /*! IOMUXC_XBAR_DIR_SEL_37 - IOMUXC XBAR_INOUT37 function direction select */ #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_MASK) + #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_MASK (0x40U) #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_SHIFT (6U) /*! IOMUXC_XBAR_DIR_SEL_38 - IOMUXC XBAR_INOUT38 function direction select */ #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_MASK) + #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_MASK (0x80U) #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_SHIFT (7U) /*! IOMUXC_XBAR_DIR_SEL_39 - IOMUXC XBAR_INOUT39 function direction select */ #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_MASK) + #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_MASK (0x100U) #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_SHIFT (8U) /*! IOMUXC_XBAR_DIR_SEL_40 - IOMUXC XBAR_INOUT40 function direction select */ #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_MASK) + #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_MASK (0x200U) #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_SHIFT (9U) /*! IOMUXC_XBAR_DIR_SEL_41 - IOMUXC XBAR_INOUT41 function direction select */ #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_MASK) + #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_MASK (0x400U) #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_SHIFT (10U) /*! IOMUXC_XBAR_DIR_SEL_42 - IOMUXC XBAR_INOUT42 function direction select */ #define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_MASK) + #define IOMUXC_GPR_GPR21_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR21_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -50276,6 +58925,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR21_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_DWP_SHIFT)) & IOMUXC_GPR_GPR21_DWP_MASK) + #define IOMUXC_GPR_GPR21_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR21_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -50289,11 +58939,13 @@ typedef struct { /*! @name GPR22 - GPR22 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK (0x1U) #define IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_SHIFT (0U) /*! REF_1M_CLK_GPT1 - GPT1 1 MHz clock source select */ #define IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK) + #define IOMUXC_GPR_GPR22_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR22_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -50303,6 +58955,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR22_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_DWP_SHIFT)) & IOMUXC_GPR_GPR22_DWP_MASK) + #define IOMUXC_GPR_GPR22_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR22_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -50316,21 +58969,25 @@ typedef struct { /*! @name GPR23 - GPR23 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK (0x1U) #define IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_SHIFT (0U) /*! REF_1M_CLK_GPT2 - GPT2 1 MHz clock source select */ #define IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK) + #define IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_MASK (0x2U) #define IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_SHIFT (1U) /*! GPT2_CAPIN1_SEL - GPT2 input capture channel 1 source select */ #define IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_MASK) + #define IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_MASK (0x4U) #define IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_SHIFT (2U) /*! GPT2_CAPIN2_SEL - GPT2 input capture channel 2 source select */ #define IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_SHIFT)) & IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_MASK) + #define IOMUXC_GPR_GPR23_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR23_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -50340,6 +58997,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR23_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_DWP_SHIFT)) & IOMUXC_GPR_GPR23_DWP_MASK) + #define IOMUXC_GPR_GPR23_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR23_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -50353,16 +59011,19 @@ typedef struct { /*! @name GPR24 - GPR24 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK (0x1U) #define IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_SHIFT (0U) /*! REF_1M_CLK_GPT3 - GPT3 1 MHz clock source select */ #define IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_SHIFT)) & IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK) + #define IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_MASK (0x2U) #define IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_SHIFT (1U) /*! GPT3_CAPIN1_SEL - GPT3 input capture channel 1 source select */ #define IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_MASK) + #define IOMUXC_GPR_GPR24_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR24_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -50372,6 +59033,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR24_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_DWP_SHIFT)) & IOMUXC_GPR_GPR24_DWP_MASK) + #define IOMUXC_GPR_GPR24_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR24_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -50385,11 +59047,13 @@ typedef struct { /*! @name GPR25 - GPR25 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK (0x1U) #define IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_SHIFT (0U) /*! REF_1M_CLK_GPT4 - GPT4 1 MHz clock source select */ #define IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_SHIFT)) & IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK) + #define IOMUXC_GPR_GPR25_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR25_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -50399,6 +59063,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR25_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_DWP_SHIFT)) & IOMUXC_GPR_GPR25_DWP_MASK) + #define IOMUXC_GPR_GPR25_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR25_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -50412,11 +59077,13 @@ typedef struct { /*! @name GPR26 - GPR26 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK (0x1U) #define IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_SHIFT (0U) /*! REF_1M_CLK_GPT5 - GPT5 1 MHz clock source select */ #define IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_SHIFT)) & IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK) + #define IOMUXC_GPR_GPR26_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR26_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -50426,6 +59093,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR26_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_DWP_SHIFT)) & IOMUXC_GPR_GPR26_DWP_MASK) + #define IOMUXC_GPR_GPR26_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR26_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -50439,11 +59107,13 @@ typedef struct { /*! @name GPR27 - GPR27 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK (0x1U) #define IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_SHIFT (0U) /*! REF_1M_CLK_GPT6 - GPT6 1 MHz clock source select */ #define IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_SHIFT)) & IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK) + #define IOMUXC_GPR_GPR27_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR27_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -50453,6 +59123,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR27_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_DWP_SHIFT)) & IOMUXC_GPR_GPR27_DWP_MASK) + #define IOMUXC_GPR_GPR27_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR27_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -50466,29 +59137,35 @@ typedef struct { /*! @name GPR28 - GPR28 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR28_ARCACHE_USDHC_MASK (0x1U) #define IOMUXC_GPR_GPR28_ARCACHE_USDHC_SHIFT (0U) /*! ARCACHE_USDHC - uSDHC block cacheable attribute value of AXI read transactions */ #define IOMUXC_GPR_GPR28_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR28_ARCACHE_USDHC_MASK) + #define IOMUXC_GPR_GPR28_AWCACHE_USDHC_MASK (0x2U) #define IOMUXC_GPR_GPR28_AWCACHE_USDHC_SHIFT (1U) /*! AWCACHE_USDHC - uSDHC block cacheable attribute value of AXI write transactions */ #define IOMUXC_GPR_GPR28_AWCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR28_AWCACHE_USDHC_MASK) + #define IOMUXC_GPR_GPR28_CACHE_ENET1G_MASK (0x20U) #define IOMUXC_GPR_GPR28_CACHE_ENET1G_SHIFT (5U) #define IOMUXC_GPR_GPR28_CACHE_ENET1G(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_ENET1G_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_ENET1G_MASK) + #define IOMUXC_GPR_GPR28_CACHE_ENET_MASK (0x80U) #define IOMUXC_GPR_GPR28_CACHE_ENET_SHIFT (7U) /*! CACHE_ENET - ENET block cacheable attribute value of AXI transactions */ #define IOMUXC_GPR_GPR28_CACHE_ENET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_ENET_MASK) + #define IOMUXC_GPR_GPR28_CACHE_USB_MASK (0x2000U) #define IOMUXC_GPR_GPR28_CACHE_USB_SHIFT (13U) /*! CACHE_USB - USB block cacheable attribute value of AXI transactions */ #define IOMUXC_GPR_GPR28_CACHE_USB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_USB_MASK) + #define IOMUXC_GPR_GPR28_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR28_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -50498,6 +59175,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR28_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_DWP_SHIFT)) & IOMUXC_GPR_GPR28_DWP_MASK) + #define IOMUXC_GPR_GPR28_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR28_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -50511,11 +59189,13 @@ typedef struct { /*! @name GPR29 - GPR29 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_MASK (0x1U) #define IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_SHIFT (0U) /*! USBPHY1_IPG_CLK_ACTIVE - USBPHY1 register access clock enable */ #define IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_MASK) + #define IOMUXC_GPR_GPR29_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR29_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -50525,6 +59205,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR29_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_DWP_SHIFT)) & IOMUXC_GPR_GPR29_DWP_MASK) + #define IOMUXC_GPR_GPR29_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR29_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -50538,11 +59219,13 @@ typedef struct { /*! @name GPR30 - GPR30 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_MASK (0x1U) #define IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_SHIFT (0U) /*! USBPHY2_IPG_CLK_ACTIVE - USBPHY2 register access clock enable */ #define IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_MASK) + #define IOMUXC_GPR_GPR30_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR30_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -50552,6 +59235,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR30_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_DWP_SHIFT)) & IOMUXC_GPR_GPR30_DWP_MASK) + #define IOMUXC_GPR_GPR30_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR30_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -50565,16 +59249,19 @@ typedef struct { /*! @name GPR31 - GPR31 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_MASK (0x1U) #define IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_SHIFT (0U) /*! RMW2_WAIT_BVALID_CPL - OCRAM M7 RMW wait enable */ #define IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_MASK) + #define IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_MASK (0x4U) #define IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_SHIFT (2U) /*! OCRAM_M7_CLK_GATING - OCRAM M7 clock gating enable */ #define IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_SHIFT)) & IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_MASK) + #define IOMUXC_GPR_GPR31_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR31_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -50584,6 +59271,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR31_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_DWP_SHIFT)) & IOMUXC_GPR_GPR31_DWP_MASK) + #define IOMUXC_GPR_GPR31_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR31_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -50597,11 +59285,13 @@ typedef struct { /*! @name GPR32 - GPR32 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_MASK (0x1U) #define IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_SHIFT (0U) /*! RMW1_WAIT_BVALID_CPL - OCRAM1 RMW wait enable */ #define IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_MASK) + #define IOMUXC_GPR_GPR32_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR32_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -50611,6 +59301,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR32_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_DWP_SHIFT)) & IOMUXC_GPR_GPR32_DWP_MASK) + #define IOMUXC_GPR_GPR32_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR32_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -50624,11 +59315,13 @@ typedef struct { /*! @name GPR33 - GPR33 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_MASK (0x1U) #define IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_SHIFT (0U) /*! RMW2_WAIT_BVALID_CPL - OCRAM2 RMW wait enable */ #define IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_MASK) + #define IOMUXC_GPR_GPR33_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR33_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -50638,6 +59331,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR33_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_DWP_SHIFT)) & IOMUXC_GPR_GPR33_DWP_MASK) + #define IOMUXC_GPR_GPR33_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR33_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -50651,16 +59345,19 @@ typedef struct { /*! @name GPR34 - GPR34 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_MASK (0x1U) #define IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_SHIFT (0U) /*! XECC_FLEXSPI1_WAIT_BVALID_CPL - XECC_FLEXSPI1 RMW wait enable */ #define IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_MASK) + #define IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_MASK (0x2U) #define IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_SHIFT (1U) /*! FLEXSPI1_OTFAD_EN - FlexSPI1 OTFAD enable */ #define IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_SHIFT)) & IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_MASK) + #define IOMUXC_GPR_GPR34_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR34_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -50670,6 +59367,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR34_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_DWP_SHIFT)) & IOMUXC_GPR_GPR34_DWP_MASK) + #define IOMUXC_GPR_GPR34_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR34_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -50683,16 +59381,19 @@ typedef struct { /*! @name GPR35 - GPR35 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_MASK (0x1U) #define IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_SHIFT (0U) /*! XECC_FLEXSPI2_WAIT_BVALID_CPL - XECC_FLEXSPI2 RMW wait enable */ #define IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_MASK) + #define IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_MASK (0x2U) #define IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_SHIFT (1U) /*! FLEXSPI2_OTFAD_EN - FlexSPI2 OTFAD enable */ #define IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_SHIFT)) & IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_MASK) + #define IOMUXC_GPR_GPR35_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR35_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -50702,6 +59403,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR35_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_DWP_SHIFT)) & IOMUXC_GPR_GPR35_DWP_MASK) + #define IOMUXC_GPR_GPR35_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR35_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -50715,11 +59417,13 @@ typedef struct { /*! @name GPR36 - GPR36 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_MASK (0x1U) #define IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_SHIFT (0U) /*! XECC_SEMC_WAIT_BVALID_CPL - XECC_SEMC RMW wait enable */ #define IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_MASK) + #define IOMUXC_GPR_GPR36_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR36_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -50729,6 +59433,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR36_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_DWP_SHIFT)) & IOMUXC_GPR_GPR36_DWP_MASK) + #define IOMUXC_GPR_GPR36_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR36_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -50742,31 +59447,37 @@ typedef struct { /*! @name GPR37 - GPR37 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR37_NIDEN_MASK (0x1U) #define IOMUXC_GPR_GPR37_NIDEN_SHIFT (0U) /*! NIDEN - ARM non-secure (non-invasive) debug enable */ #define IOMUXC_GPR_GPR37_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_NIDEN_SHIFT)) & IOMUXC_GPR_GPR37_NIDEN_MASK) + #define IOMUXC_GPR_GPR37_DBG_EN_MASK (0x2U) #define IOMUXC_GPR_GPR37_DBG_EN_SHIFT (1U) /*! DBG_EN - ARM invasive debug enable */ #define IOMUXC_GPR_GPR37_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR37_DBG_EN_MASK) + #define IOMUXC_GPR_GPR37_EXC_MON_MASK (0x8U) #define IOMUXC_GPR_GPR37_EXC_MON_SHIFT (3U) /*! EXC_MON - Exclusive monitor response select of illegal command */ #define IOMUXC_GPR_GPR37_EXC_MON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR37_EXC_MON_MASK) + #define IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_MASK (0x20U) #define IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_SHIFT (5U) /*! M7_DBG_ACK_MASK - CM7 debug halt mask */ #define IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_SHIFT)) & IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_MASK) + #define IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_MASK (0x40U) #define IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_SHIFT (6U) /*! M4_DBG_ACK_MASK - CM4 debug halt mask */ #define IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_SHIFT)) & IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_MASK) + #define IOMUXC_GPR_GPR37_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR37_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -50776,6 +59487,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR37_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DWP_SHIFT)) & IOMUXC_GPR_GPR37_DWP_MASK) + #define IOMUXC_GPR_GPR37_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR37_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -50789,6 +59501,7 @@ typedef struct { /*! @name GPR38 - GPR38 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR38_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR38_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -50798,6 +59511,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR38_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR38_DWP_SHIFT)) & IOMUXC_GPR_GPR38_DWP_MASK) + #define IOMUXC_GPR_GPR38_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR38_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -50811,6 +59525,7 @@ typedef struct { /*! @name GPR39 - GPR39 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR39_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR39_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -50820,6 +59535,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR39_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR39_DWP_SHIFT)) & IOMUXC_GPR_GPR39_DWP_MASK) + #define IOMUXC_GPR_GPR39_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR39_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -50833,11 +59549,13 @@ typedef struct { /*! @name GPR40 - GPR40 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_MASK (0xFFFFU) #define IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_SHIFT (0U) -/*! GPIO_MUX2_GPIO_SEL_LOW - GPIO2 and GPIO_M7_2 share same IO MUX function, GPIO_MUX2 selects one GPIO function. +/*! GPIO_MUX2_GPIO_SEL_LOW - GPIO2 and CM7_GPIO2 share same IO MUX function, GPIO_MUX2 selects one GPIO function. */ #define IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_SHIFT)) & IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_MASK) + #define IOMUXC_GPR_GPR40_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR40_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -50847,6 +59565,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR40_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_DWP_SHIFT)) & IOMUXC_GPR_GPR40_DWP_MASK) + #define IOMUXC_GPR_GPR40_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR40_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -50860,11 +59579,13 @@ typedef struct { /*! @name GPR41 - GPR41 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_MASK (0xFFFFU) #define IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_SHIFT (0U) -/*! GPIO_MUX2_GPIO_SEL_HIGH - GPIO2 and GPIO_M7_2 share same IO MUX function, GPIO_MUX2 selects one GPIO function. +/*! GPIO_MUX2_GPIO_SEL_HIGH - GPIO2 and CM7_GPIO2 share same IO MUX function, GPIO_MUX2 selects one GPIO function. */ #define IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_SHIFT)) & IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_MASK) + #define IOMUXC_GPR_GPR41_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR41_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -50874,6 +59595,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR41_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_DWP_SHIFT)) & IOMUXC_GPR_GPR41_DWP_MASK) + #define IOMUXC_GPR_GPR41_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR41_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -50887,11 +59609,13 @@ typedef struct { /*! @name GPR42 - GPR42 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_MASK (0xFFFFU) #define IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_SHIFT (0U) -/*! GPIO_MUX3_GPIO_SEL_LOW - GPIO3 and GPIO_M7_3 share same IO MUX function, GPIO_MUX3 selects one GPIO function. +/*! GPIO_MUX3_GPIO_SEL_LOW - GPIO3 and CM7_GPIO3 share same IO MUX function, GPIO_MUX3 selects one GPIO function. */ #define IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_SHIFT)) & IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_MASK) + #define IOMUXC_GPR_GPR42_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR42_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -50901,6 +59625,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR42_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_DWP_SHIFT)) & IOMUXC_GPR_GPR42_DWP_MASK) + #define IOMUXC_GPR_GPR42_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR42_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -50914,11 +59639,13 @@ typedef struct { /*! @name GPR43 - GPR43 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_MASK (0xFFFFU) #define IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_SHIFT (0U) -/*! GPIO_MUX3_GPIO_SEL_HIGH - GPIO3 and GPIO_M7_3 share same IO MUX function, GPIO_MUX3 selects one GPIO function. +/*! GPIO_MUX3_GPIO_SEL_HIGH - GPIO3 and CM7_GPIO3 share same IO MUX function, GPIO_MUX3 selects one GPIO function. */ #define IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_SHIFT)) & IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_MASK) + #define IOMUXC_GPR_GPR43_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR43_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -50928,6 +59655,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR43_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_DWP_SHIFT)) & IOMUXC_GPR_GPR43_DWP_MASK) + #define IOMUXC_GPR_GPR43_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR43_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -50941,6 +59669,7 @@ typedef struct { /*! @name GPR44 - GPR44 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR44_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR44_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -50950,6 +59679,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR44_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR44_DWP_SHIFT)) & IOMUXC_GPR_GPR44_DWP_MASK) + #define IOMUXC_GPR_GPR44_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR44_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -50963,6 +59693,7 @@ typedef struct { /*! @name GPR45 - GPR45 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR45_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR45_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -50972,6 +59703,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR45_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR45_DWP_SHIFT)) & IOMUXC_GPR_GPR45_DWP_MASK) + #define IOMUXC_GPR_GPR45_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR45_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -50985,6 +59717,7 @@ typedef struct { /*! @name GPR46 - GPR46 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR46_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR46_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -50994,6 +59727,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR46_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR46_DWP_SHIFT)) & IOMUXC_GPR_GPR46_DWP_MASK) + #define IOMUXC_GPR_GPR46_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR46_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -51007,6 +59741,7 @@ typedef struct { /*! @name GPR47 - GPR47 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR47_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR47_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -51016,6 +59751,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR47_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR47_DWP_SHIFT)) & IOMUXC_GPR_GPR47_DWP_MASK) + #define IOMUXC_GPR_GPR47_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR47_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -51029,6 +59765,7 @@ typedef struct { /*! @name GPR48 - GPR48 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR48_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR48_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -51038,6 +59775,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR48_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR48_DWP_SHIFT)) & IOMUXC_GPR_GPR48_DWP_MASK) + #define IOMUXC_GPR_GPR48_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR48_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -51051,6 +59789,7 @@ typedef struct { /*! @name GPR49 - GPR49 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR49_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR49_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -51060,6 +59799,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR49_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR49_DWP_SHIFT)) & IOMUXC_GPR_GPR49_DWP_MASK) + #define IOMUXC_GPR_GPR49_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR49_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -51073,11 +59813,13 @@ typedef struct { /*! @name GPR50 - GPR50 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR50_CAAM_IPS_MGR_MASK (0x1FU) #define IOMUXC_GPR_GPR50_CAAM_IPS_MGR_SHIFT (0U) /*! CAAM_IPS_MGR - CAAM manager processor identifier */ #define IOMUXC_GPR_GPR50_CAAM_IPS_MGR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_CAAM_IPS_MGR_SHIFT)) & IOMUXC_GPR_GPR50_CAAM_IPS_MGR_MASK) + #define IOMUXC_GPR_GPR50_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR50_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -51087,6 +59829,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR50_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_DWP_SHIFT)) & IOMUXC_GPR_GPR50_DWP_MASK) + #define IOMUXC_GPR_GPR50_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR50_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -51100,11 +59843,13 @@ typedef struct { /*! @name GPR51 - GPR51 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR51_M7_NMI_CLEAR_MASK (0x1U) #define IOMUXC_GPR_GPR51_M7_NMI_CLEAR_SHIFT (0U) /*! M7_NMI_CLEAR - Clear CM7 NMI holding register */ #define IOMUXC_GPR_GPR51_M7_NMI_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_M7_NMI_CLEAR_SHIFT)) & IOMUXC_GPR_GPR51_M7_NMI_CLEAR_MASK) + #define IOMUXC_GPR_GPR51_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR51_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -51114,6 +59859,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR51_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_DWP_SHIFT)) & IOMUXC_GPR_GPR51_DWP_MASK) + #define IOMUXC_GPR_GPR51_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR51_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -51127,6 +59873,7 @@ typedef struct { /*! @name GPR52 - GPR52 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR52_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR52_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -51136,6 +59883,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR52_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR52_DWP_SHIFT)) & IOMUXC_GPR_GPR52_DWP_MASK) + #define IOMUXC_GPR_GPR52_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR52_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -51149,6 +59897,7 @@ typedef struct { /*! @name GPR53 - GPR53 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR53_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR53_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -51158,6 +59907,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR53_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR53_DWP_SHIFT)) & IOMUXC_GPR_GPR53_DWP_MASK) + #define IOMUXC_GPR_GPR53_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR53_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -51171,6 +59921,7 @@ typedef struct { /*! @name GPR54 - GPR54 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR54_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR54_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -51180,6 +59931,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR54_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR54_DWP_SHIFT)) & IOMUXC_GPR_GPR54_DWP_MASK) + #define IOMUXC_GPR_GPR54_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR54_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -51193,6 +59945,7 @@ typedef struct { /*! @name GPR55 - GPR55 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR55_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR55_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -51202,6 +59955,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR55_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR55_DWP_SHIFT)) & IOMUXC_GPR_GPR55_DWP_MASK) + #define IOMUXC_GPR_GPR55_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR55_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -51215,57 +59969,74 @@ typedef struct { /*! @name GPR59 - GPR59 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_MASK (0x1U) #define IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_SHIFT (0U) /*! MIPI_CSI_AUTO_PD_EN - Powers down inactive lanes reported by CSI2X_CFG_NUM_LANES. */ #define IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_MASK) + #define IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK (0x2U) #define IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_SHIFT (1U) /*! MIPI_CSI_SOFT_RST_N - MIPI CSI APB clock domain and User interface clock domain software reset bit + * 0b0..Assert reset + * 0b1..De-assert reset */ #define IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK) + #define IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_MASK (0x4U) #define IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_SHIFT (2U) /*! MIPI_CSI_CONT_CLK_MODE - Enables the slave clock lane feature to maintain HS reception state * during continuous clock mode operation, despite line glitches. */ #define IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_MASK) + #define IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_MASK (0x8U) #define IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_SHIFT (3U) /*! MIPI_CSI_DDRCLK_EN - When high, enables received DDR clock on CLK_DRXHS */ #define IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_MASK) + #define IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK (0x10U) #define IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_SHIFT (4U) /*! MIPI_CSI_PD_RX - Power Down input for MIPI CSI PHY. */ #define IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK) + #define IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK (0x20U) #define IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_SHIFT (5U) /*! MIPI_CSI_RX_ENABLE - Assert to enable MIPI CSI Receive Enable */ #define IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK) + #define IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_MASK (0xC0U) #define IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_SHIFT (6U) /*! MIPI_CSI_RX_RCAL - MIPI CSI PHY on-chip termination control bits */ #define IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_MASK) + #define IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_MASK (0x300U) #define IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_SHIFT (8U) /*! MIPI_CSI_RXCDRP - Programming bits that adjust the threshold voltage of LP-CD, default setting 2'b01 + * 0b00..344mV + * 0b01..325mV (Default) + * 0b10..307mV + * 0b11..Invalid */ #define IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_MASK) + #define IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_MASK (0xC00U) #define IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT (10U) /*! MIPI_CSI_RXLPRP - Programming bits that adjust the threshold voltage of LP-RX, default setting 2'b01 */ #define IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_MASK) + #define IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK (0x3F000U) #define IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_SHIFT (12U) /*! MIPI_CSI_S_PRG_RXHS_SETTLE - Bits used to program T_HS_SETTLE. */ #define IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK) + #define IOMUXC_GPR_GPR59_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR59_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -51275,6 +60046,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR59_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_DWP_SHIFT)) & IOMUXC_GPR_GPR59_DWP_MASK) + #define IOMUXC_GPR_GPR59_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR59_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -51288,51 +60060,69 @@ typedef struct { /*! @name GPR62 - GPR62 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_MASK (0x7U) #define IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_SHIFT (0U) /*! MIPI_DSI_CLK_TM - MIPI DSI Clock Lane triming bits */ #define IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_MASK) + #define IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_MASK (0x38U) #define IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_SHIFT (3U) /*! MIPI_DSI_D0_TM - MIPI DSI Data Lane 0 triming bits */ #define IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_MASK) + #define IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_MASK (0x1C0U) #define IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_SHIFT (6U) /*! MIPI_DSI_D1_TM - MIPI DSI Data Lane 1 triming bits */ #define IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_MASK) + #define IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_MASK (0x600U) #define IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_SHIFT (9U) /*! MIPI_DSI_TX_RCAL - MIPI DSI PHY on-chip termination control bits */ #define IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_MASK) + #define IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_MASK (0x3800U) #define IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_SHIFT (11U) /*! MIPI_DSI_TX_ULPS_ENABLE - DSI transmit ULPS mode enable */ #define IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_MASK) + #define IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK (0x10000U) #define IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_SHIFT (16U) /*! MIPI_DSI_PCLK_SOFT_RESET_N - MIPI DSI APB clock domain software reset bit + * 0b0..Assert reset + * 0b1..De-assert reset */ #define IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK) + #define IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK (0x20000U) #define IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_SHIFT (17U) /*! MIPI_DSI_BYTE_SOFT_RESET_N - MIPI DSI Byte clock domain software reset bit + * 0b0..Assert reset + * 0b1..De-assert reset */ #define IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK) + #define IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK (0x40000U) #define IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_SHIFT (18U) /*! MIPI_DSI_DPI_SOFT_RESET_N - MIPI DSI Pixel clock domain software reset bit + * 0b0..Assert reset + * 0b1..De-assert reset */ #define IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK) + #define IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK (0x80000U) #define IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_SHIFT (19U) /*! MIPI_DSI_ESC_SOFT_RESET_N - MIPI DSI Escape clock domain software reset bit + * 0b0..Assert reset + * 0b1..De-assert reset */ #define IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK) + #define IOMUXC_GPR_GPR62_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR62_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -51342,6 +60132,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR62_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_DWP_SHIFT)) & IOMUXC_GPR_GPR62_DWP_MASK) + #define IOMUXC_GPR_GPR62_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR62_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -51355,70 +60146,83 @@ typedef struct { /*! @name GPR63 - GPR63 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_MASK (0x7U) #define IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_SHIFT (0U) -/*! MIPI_DSI_TX_ULPS_ACTIVE - DSI transmit ULPS mode acitve flag +/*! MIPI_DSI_TX_ULPS_ACTIVE - DSI transmit ULPS mode active flag */ #define IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_MASK) /*! @} */ /*! @name GPR64 - GPR64 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_MASK (0x1U) #define IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_SHIFT (0U) /*! GPIO_DISP1_FREEZE - Compensation code freeze */ #define IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_MASK) + #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_MASK (0x2U) #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_SHIFT (1U) /*! GPIO_DISP1_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell */ #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_MASK) + #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_MASK (0x4U) #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_SHIFT (2U) /*! GPIO_DISP1_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell */ #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_MASK) + #define IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_MASK (0x8U) #define IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_SHIFT (3U) /*! GPIO_DISP1_FASTFRZ_EN - Compensation code fast freeze */ #define IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_MASK) + #define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_MASK (0xF0U) #define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_SHIFT (4U) /*! GPIO_DISP1_RASRCP - GPIO_DISP_B1 IO bank's 4-bit PMOS compensation codes from core */ #define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_MASK) + #define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_MASK (0xF00U) #define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_SHIFT (8U) /*! GPIO_DISP1_RASRCN - GPIO_DISP_B1 IO bank's 4-bit NMOS compensation codes from core */ #define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_MASK) + #define IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_MASK (0x1000U) #define IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_SHIFT (12U) /*! GPIO_DISP1_SELECT_NASRC - GPIO_DISP1_NASRC selection */ #define IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_MASK) + #define IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_MASK (0x2000U) #define IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_SHIFT (13U) /*! GPIO_DISP1_REFGEN_SLEEP - GPIO_DISP_B1 IO bank reference voltage generator cell sleep enable */ #define IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_MASK) + #define IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_MASK (0x4000U) #define IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_SHIFT (14U) /*! GPIO_DISP1_SUPLYDET_LATCH - GPIO_DISP_B1 IO bank power supply mode latch enable */ #define IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_MASK) + #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_MASK (0x100000U) #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_SHIFT (20U) /*! GPIO_DISP1_COMPOK - GPIO_DISP_B1 IO bank compensation OK flag */ #define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_MASK) + #define IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_MASK (0x1E00000U) #define IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_SHIFT (21U) /*! GPIO_DISP1_NASRC - GPIO_DISP_B1 IO bank compensation codes */ #define IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_MASK) + #define IOMUXC_GPR_GPR64_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR64_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -51428,6 +60232,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR64_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_DWP_SHIFT)) & IOMUXC_GPR_GPR64_DWP_MASK) + #define IOMUXC_GPR_GPR64_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR64_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -51441,61 +60246,73 @@ typedef struct { /*! @name GPR65 - GPR65 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_MASK (0x1U) #define IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_SHIFT (0U) /*! GPIO_EMC1_FREEZE - Compensation code freeze */ #define IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_MASK) + #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_MASK (0x2U) #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_SHIFT (1U) /*! GPIO_EMC1_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell */ #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_MASK) + #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_MASK (0x4U) #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_SHIFT (2U) /*! GPIO_EMC1_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell */ #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_MASK) + #define IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_MASK (0x8U) #define IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_SHIFT (3U) /*! GPIO_EMC1_FASTFRZ_EN - Compensation code fast freeze */ #define IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_MASK) + #define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_MASK (0xF0U) #define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_SHIFT (4U) /*! GPIO_EMC1_RASRCP - GPIO_EMC_B1 IO bank's 4-bit PMOS compensation codes from core */ #define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_MASK) + #define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_MASK (0xF00U) #define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_SHIFT (8U) /*! GPIO_EMC1_RASRCN - GPIO_EMC_B1 IO bank's 4-bit NMOS compensation codes from core */ #define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_MASK) + #define IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_MASK (0x1000U) #define IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_SHIFT (12U) /*! GPIO_EMC1_SELECT_NASRC - GPIO_EMC1_NASRC selection */ #define IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_MASK) + #define IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_MASK (0x2000U) #define IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_SHIFT (13U) /*! GPIO_EMC1_REFGEN_SLEEP - GPIO_EMC_B1 IO bank reference voltage generator cell sleep enable */ #define IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_MASK) + #define IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_MASK (0x4000U) #define IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_SHIFT (14U) /*! GPIO_EMC1_SUPLYDET_LATCH - GPIO_EMC_B1 IO bank power supply mode latch enable */ #define IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_MASK) + #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_MASK (0x100000U) #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_SHIFT (20U) /*! GPIO_EMC1_COMPOK - GPIO_EMC_B1 IO bank compensation OK flag */ #define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_MASK) + #define IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_MASK (0x1E00000U) #define IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_SHIFT (21U) /*! GPIO_EMC1_NASRC - GPIO_EMC_B1 IO bank compensation codes */ #define IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_MASK) + #define IOMUXC_GPR_GPR65_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR65_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -51505,6 +60322,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR65_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_DWP_SHIFT)) & IOMUXC_GPR_GPR65_DWP_MASK) + #define IOMUXC_GPR_GPR65_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR65_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -51518,61 +60336,73 @@ typedef struct { /*! @name GPR66 - GPR66 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_MASK (0x1U) #define IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_SHIFT (0U) /*! GPIO_EMC2_FREEZE - Compensation code freeze */ #define IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_MASK) + #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_MASK (0x2U) #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_SHIFT (1U) /*! GPIO_EMC2_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell */ #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_MASK) + #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_MASK (0x4U) #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_SHIFT (2U) /*! GPIO_EMC2_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell */ #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_MASK) + #define IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_MASK (0x8U) #define IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_SHIFT (3U) /*! GPIO_EMC2_FASTFRZ_EN - Compensation code fast freeze */ #define IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_MASK) + #define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_MASK (0xF0U) #define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_SHIFT (4U) /*! GPIO_EMC2_RASRCP - GPIO_EMC_B2 IO bank's 4-bit PMOS compensation codes from core */ #define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_MASK) + #define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_MASK (0xF00U) #define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_SHIFT (8U) /*! GPIO_EMC2_RASRCN - GPIO_EMC_B2 IO bank's 4-bit NMOS compensation codes from core */ #define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_MASK) + #define IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_MASK (0x1000U) #define IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_SHIFT (12U) /*! GPIO_EMC2_SELECT_NASRC - GPIO_EMC2_NASRC selection */ #define IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_MASK) + #define IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_MASK (0x2000U) #define IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_SHIFT (13U) /*! GPIO_EMC2_REFGEN_SLEEP - GPIO_EMC_B2 IO bank reference voltage generator cell sleep enable */ #define IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_MASK) + #define IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_MASK (0x4000U) #define IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_SHIFT (14U) /*! GPIO_EMC2_SUPLYDET_LATCH - GPIO_EMC_B2 IO bank power supply mode latch enable */ #define IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_MASK) + #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_MASK (0x100000U) #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_SHIFT (20U) /*! GPIO_EMC2_COMPOK - GPIO_EMC_B2 IO bank compensation OK flag */ #define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_MASK) + #define IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_MASK (0x1E00000U) #define IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_SHIFT (21U) /*! GPIO_EMC2_NASRC - GPIO_EMC_B2 IO bank compensation codes */ #define IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_MASK) + #define IOMUXC_GPR_GPR66_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR66_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -51582,6 +60412,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR66_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_DWP_SHIFT)) & IOMUXC_GPR_GPR66_DWP_MASK) + #define IOMUXC_GPR_GPR66_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR66_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -51595,61 +60426,73 @@ typedef struct { /*! @name GPR67 - GPR67 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_MASK (0x1U) #define IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_SHIFT (0U) /*! GPIO_SD1_FREEZE - Compensation code freeze */ #define IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_MASK) + #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_MASK (0x2U) #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_SHIFT (1U) /*! GPIO_SD1_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell */ #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_MASK) + #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_MASK (0x4U) #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_SHIFT (2U) /*! GPIO_SD1_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell */ #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_MASK) + #define IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_MASK (0x8U) #define IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_SHIFT (3U) /*! GPIO_SD1_FASTFRZ_EN - Compensation code fast freeze */ #define IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_MASK) + #define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_MASK (0xF0U) #define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_SHIFT (4U) /*! GPIO_SD1_RASRCP - GPIO_SD_B1 IO bank's 4-bit PMOS compensation codes from core */ #define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_MASK) + #define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_MASK (0xF00U) #define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_SHIFT (8U) /*! GPIO_SD1_RASRCN - GPIO_SD_B1 IO bank's 4-bit NMOS compensation codes from core */ #define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_MASK) + #define IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_MASK (0x1000U) #define IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_SHIFT (12U) /*! GPIO_SD1_SELECT_NASRC - GPIO_SD1_NASRC selection */ #define IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_MASK) + #define IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_MASK (0x2000U) #define IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_SHIFT (13U) /*! GPIO_SD1_REFGEN_SLEEP - GPIO_SD_B1 IO bank reference voltage generator cell sleep enable */ #define IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_MASK) + #define IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_MASK (0x4000U) #define IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_SHIFT (14U) /*! GPIO_SD1_SUPLYDET_LATCH - GPIO_SD_B1 IO bank power supply mode latch enable */ #define IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_MASK) + #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_MASK (0x100000U) #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_SHIFT (20U) /*! GPIO_SD1_COMPOK - GPIO_SD_B1 IO bank compensation OK flag */ #define IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_MASK) + #define IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_MASK (0x1E00000U) #define IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_SHIFT (21U) /*! GPIO_SD1_NASRC - GPIO_SD_B1 IO bank compensation codes */ #define IOMUXC_GPR_GPR67_GPIO_SD1_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_MASK) + #define IOMUXC_GPR_GPR67_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR67_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -51659,6 +60502,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR67_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_DWP_SHIFT)) & IOMUXC_GPR_GPR67_DWP_MASK) + #define IOMUXC_GPR_GPR67_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR67_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -51672,61 +60516,73 @@ typedef struct { /*! @name GPR68 - GPR68 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_MASK (0x1U) #define IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_SHIFT (0U) /*! GPIO_SD2_FREEZE - Compensation code freeze */ #define IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_MASK) + #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_MASK (0x2U) #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_SHIFT (1U) /*! GPIO_SD2_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell */ #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_MASK) + #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_MASK (0x4U) #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_SHIFT (2U) /*! GPIO_SD2_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell */ #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_MASK) + #define IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_MASK (0x8U) #define IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_SHIFT (3U) /*! GPIO_SD2_FASTFRZ_EN - Compensation code fast freeze */ #define IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_MASK) + #define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_MASK (0xF0U) #define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_SHIFT (4U) /*! GPIO_SD2_RASRCP - GPIO_SD_B2 IO bank's 4-bit PMOS compensation codes from core */ #define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_MASK) + #define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_MASK (0xF00U) #define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_SHIFT (8U) /*! GPIO_SD2_RASRCN - GPIO_SD_B2 IO bank's 4-bit NMOS compensation codes from core */ #define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_MASK) + #define IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_MASK (0x1000U) #define IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_SHIFT (12U) /*! GPIO_SD2_SELECT_NASRC - GPIO_SD2_NASRC selection */ #define IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_MASK) + #define IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_MASK (0x2000U) #define IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_SHIFT (13U) /*! GPIO_SD2_REFGEN_SLEEP - GPIO_SD_B2 IO bank reference voltage generator cell sleep enable */ #define IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_MASK) + #define IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_MASK (0x4000U) #define IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_SHIFT (14U) /*! GPIO_SD2_SUPLYDET_LATCH - GPIO_SD_B2 IO bank power supply mode latch enable */ #define IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_MASK) + #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_MASK (0x100000U) #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_SHIFT (20U) /*! GPIO_SD2_COMPOK - GPIO_SD_B2 IO bank compensation OK flag */ #define IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_MASK) + #define IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_MASK (0x1E00000U) #define IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_SHIFT (21U) /*! GPIO_SD2_NASRC - GPIO_SD_B2 IO bank compensation codes */ #define IOMUXC_GPR_GPR68_GPIO_SD2_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_MASK) + #define IOMUXC_GPR_GPR68_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR68_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -51736,6 +60592,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR68_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_DWP_SHIFT)) & IOMUXC_GPR_GPR68_DWP_MASK) + #define IOMUXC_GPR_GPR68_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR68_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -51749,61 +60606,73 @@ typedef struct { /*! @name GPR69 - GPR69 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_MASK (0x2U) #define IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_SHIFT (1U) /*! GPIO_DISP2_HIGH_RANGE - GPIO_DISP_B2 IO bank supply voltage range selection */ #define IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_MASK) + #define IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_MASK (0x4U) #define IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_SHIFT (2U) /*! GPIO_DISP2_LOW_RANGE - GPIO_DISP_B2 IO bank supply voltage range selection */ #define IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_MASK) + #define IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_MASK (0x10U) #define IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_SHIFT (4U) /*! GPIO_AD0_HIGH_RANGE - GPIO_AD IO bank supply voltage range selection for GPIO_AD_00 to GPIO_AD_17 */ #define IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_MASK) + #define IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_MASK (0x20U) #define IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_SHIFT (5U) /*! GPIO_AD0_LOW_RANGE - GPIO_AD IO bank supply voltage range selection for GPIO_AD_00 to GPIO_AD_17 */ #define IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_MASK) + #define IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_MASK (0x80U) #define IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_SHIFT (7U) /*! GPIO_AD1_HIGH_RANGE - GPIO_LPSR IO bank supply voltage range selection for GPIO_AD_18 to GPIO_AD_35 */ #define IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_MASK) + #define IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_MASK (0x100U) #define IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_SHIFT (8U) /*! GPIO_AD1_LOW_RANGE - GPIO_LPSR IO bank supply voltage range selection for GPIO_AD_18 to GPIO_AD_35 */ #define IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_MASK) + #define IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_MASK (0x200U) #define IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_SHIFT (9U) /*! SUPLYDET_DISP1_SLEEP - GPIO_DISP_B1 IO bank supply voltage detector sleep mode enable */ #define IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_MASK) + #define IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_MASK (0x400U) #define IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_SHIFT (10U) /*! SUPLYDET_EMC1_SLEEP - GPIO_EMC_B1 IO bank supply voltage detector sleep mode enable */ #define IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_MASK) + #define IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_MASK (0x800U) #define IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_SHIFT (11U) /*! SUPLYDET_EMC2_SLEEP - GPIO_EMC_B2 IO bank supply voltage detector sleep mode enable */ #define IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_MASK) + #define IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_MASK (0x1000U) #define IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_SHIFT (12U) /*! SUPLYDET_SD1_SLEEP - GPIO_SD_B1 IO bank supply voltage detector sleep mode enable */ #define IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_MASK) + #define IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_MASK (0x2000U) #define IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_SHIFT (13U) /*! SUPLYDET_SD2_SLEEP - GPIO_SD_B2 IO bank supply voltage detector sleep mode enable */ #define IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_MASK) + #define IOMUXC_GPR_GPR69_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR69_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -51813,6 +60682,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR69_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_DWP_SHIFT)) & IOMUXC_GPR_GPR69_DWP_MASK) + #define IOMUXC_GPR_GPR69_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR69_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -51826,136 +60696,167 @@ typedef struct { /*! @name GPR70 - GPR70 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_MASK (0x1U) #define IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_SHIFT (0U) -/*! ADC1_IPG_DOZE - ADC2 doze mode +/*! ADC1_IPG_DOZE - ADC1 doze mode */ #define IOMUXC_GPR_GPR70_ADC1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR70_ADC1_STOP_REQ_MASK (0x2U) #define IOMUXC_GPR_GPR70_ADC1_STOP_REQ_SHIFT (1U) -/*! ADC1_STOP_REQ - ADC2 stop request +/*! ADC1_STOP_REQ - ADC1 stop request */ #define IOMUXC_GPR_GPR70_ADC1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_MASK (0x4U) #define IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_SHIFT (2U) -/*! ADC1_IPG_STOP_MODE - ADC2 stop mode selection, cannot change when ADC2_STOP_REQ is asserted. +/*! ADC1_IPG_STOP_MODE - ADC1 stop mode selection, cannot change when ADC1_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_MASK) + #define IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_MASK (0x8U) #define IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_SHIFT (3U) /*! ADC2_IPG_DOZE - ADC2 doze mode */ #define IOMUXC_GPR_GPR70_ADC2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR70_ADC2_STOP_REQ_MASK (0x10U) #define IOMUXC_GPR_GPR70_ADC2_STOP_REQ_SHIFT (4U) /*! ADC2_STOP_REQ - ADC2 stop request */ #define IOMUXC_GPR_GPR70_ADC2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_MASK (0x20U) #define IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_SHIFT (5U) /*! ADC2_IPG_STOP_MODE - ADC2 stop mode selection, cannot change when ADC2_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_MASK) + #define IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_MASK (0x40U) #define IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_SHIFT (6U) /*! CAAM_IPG_DOZE - CAN3 doze mode */ #define IOMUXC_GPR_GPR70_CAAM_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR70_CAAM_STOP_REQ_MASK (0x80U) #define IOMUXC_GPR_GPR70_CAAM_STOP_REQ_SHIFT (7U) /*! CAAM_STOP_REQ - CAAM stop request */ #define IOMUXC_GPR_GPR70_CAAM_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAAM_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAAM_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_MASK (0x100U) #define IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_SHIFT (8U) /*! CAN1_IPG_DOZE - CAN1 doze mode */ #define IOMUXC_GPR_GPR70_CAN1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR70_CAN1_STOP_REQ_MASK (0x200U) #define IOMUXC_GPR_GPR70_CAN1_STOP_REQ_SHIFT (9U) /*! CAN1_STOP_REQ - CAN1 stop request */ #define IOMUXC_GPR_GPR70_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN1_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_MASK (0x400U) #define IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_SHIFT (10U) /*! CAN2_IPG_DOZE - CAN2 doze mode */ #define IOMUXC_GPR_GPR70_CAN2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR70_CAN2_STOP_REQ_MASK (0x800U) #define IOMUXC_GPR_GPR70_CAN2_STOP_REQ_SHIFT (11U) /*! CAN2_STOP_REQ - CAN2 stop request */ #define IOMUXC_GPR_GPR70_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN2_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_MASK (0x1000U) #define IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_SHIFT (12U) /*! CAN3_IPG_DOZE - CAN3 doze mode */ #define IOMUXC_GPR_GPR70_CAN3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR70_CAN3_STOP_REQ_MASK (0x2000U) #define IOMUXC_GPR_GPR70_CAN3_STOP_REQ_SHIFT (13U) /*! CAN3_STOP_REQ - CAN3 stop request */ #define IOMUXC_GPR_GPR70_CAN3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN3_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR70_EDMA_STOP_REQ_MASK (0x8000U) #define IOMUXC_GPR_GPR70_EDMA_STOP_REQ_SHIFT (15U) /*! EDMA_STOP_REQ - EDMA stop request */ #define IOMUXC_GPR_GPR70_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_EDMA_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_MASK (0x10000U) #define IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_SHIFT (16U) /*! EDMA_LPSR_STOP_REQ - EDMA_LPSR stop request */ #define IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR70_ENET_IPG_DOZE_MASK (0x20000U) #define IOMUXC_GPR_GPR70_ENET_IPG_DOZE_SHIFT (17U) /*! ENET_IPG_DOZE - ENET doze mode */ #define IOMUXC_GPR_GPR70_ENET_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ENET_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR70_ENET_STOP_REQ_MASK (0x40000U) #define IOMUXC_GPR_GPR70_ENET_STOP_REQ_SHIFT (18U) /*! ENET_STOP_REQ - ENET stop request */ #define IOMUXC_GPR_GPR70_ENET_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ENET_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_MASK (0x80000U) #define IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_SHIFT (19U) /*! ENET1G_IPG_DOZE - ENET1G doze mode */ #define IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_MASK (0x100000U) #define IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_SHIFT (20U) /*! ENET1G_STOP_REQ - ENET1G stop request */ #define IOMUXC_GPR_GPR70_ENET1G_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_MASK (0x200000U) #define IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_SHIFT (21U) /*! FLEXIO1_IPG_DOZE - FLEXIO2 doze mode */ #define IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_MASK (0x400000U) #define IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_SHIFT (22U) /*! FLEXIO2_IPG_DOZE - FLEXIO2 doze mode */ #define IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_MASK (0x800000U) #define IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_SHIFT (23U) /*! FLEXSPI1_IPG_DOZE - FLEXSPI1 doze mode */ #define IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_MASK (0x1000000U) #define IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_SHIFT (24U) /*! FLEXSPI1_STOP_REQ - FLEXSPI1 stop request */ #define IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_MASK (0x2000000U) #define IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_SHIFT (25U) /*! FLEXSPI2_IPG_DOZE - FLEXSPI2 doze mode */ #define IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_MASK (0x4000000U) #define IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_SHIFT (26U) /*! FLEXSPI2_STOP_REQ - FLEXSPI2 stop request */ #define IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR70_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR70_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -51965,6 +60866,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR70_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_DWP_SHIFT)) & IOMUXC_GPR_GPR70_DWP_MASK) + #define IOMUXC_GPR_GPR70_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR70_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -51978,141 +60880,183 @@ typedef struct { /*! @name GPR71 - GPR71 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_MASK (0x1U) #define IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_SHIFT (0U) /*! GPT1_IPG_DOZE - GPT1 doze mode */ #define IOMUXC_GPR_GPR71_GPT1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_MASK (0x2U) #define IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_SHIFT (1U) /*! GPT2_IPG_DOZE - GPT2 doze mode */ #define IOMUXC_GPR_GPR71_GPT2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_MASK (0x4U) #define IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_SHIFT (2U) /*! GPT3_IPG_DOZE - GPT3 doze mode */ #define IOMUXC_GPR_GPR71_GPT3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_MASK (0x8U) #define IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_SHIFT (3U) /*! GPT4_IPG_DOZE - GPT4 doze mode */ #define IOMUXC_GPR_GPR71_GPT4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_MASK (0x10U) #define IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_SHIFT (4U) /*! GPT5_IPG_DOZE - GPT5 doze mode */ #define IOMUXC_GPR_GPR71_GPT5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_MASK (0x20U) #define IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_SHIFT (5U) /*! GPT6_IPG_DOZE - GPT6 doze mode */ #define IOMUXC_GPR_GPR71_GPT6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_MASK (0x40U) #define IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_SHIFT (6U) /*! LPI2C1_IPG_DOZE - LPI2C1 doze mode */ #define IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_MASK (0x80U) #define IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_SHIFT (7U) /*! LPI2C1_STOP_REQ - LPI2C1 stop request */ #define IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_MASK (0x100U) #define IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_SHIFT (8U) /*! LPI2C1_IPG_STOP_MODE - LPI2C1 stop mode selection, cannot change when LPI2C1_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_MASK) + #define IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_MASK (0x200U) #define IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_SHIFT (9U) /*! LPI2C2_IPG_DOZE - LPI2C2 doze mode */ #define IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_MASK (0x400U) #define IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_SHIFT (10U) /*! LPI2C2_STOP_REQ - LPI2C2 stop request */ #define IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_MASK (0x800U) #define IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_SHIFT (11U) /*! LPI2C2_IPG_STOP_MODE - LPI2C2 stop mode selection, cannot change when LPI2C2_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_MASK) + #define IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_MASK (0x1000U) #define IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_SHIFT (12U) /*! LPI2C3_IPG_DOZE - LPI2C3 doze mode */ #define IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_MASK (0x2000U) #define IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_SHIFT (13U) /*! LPI2C3_STOP_REQ - LPI2C3 stop request */ #define IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_MASK (0x4000U) #define IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_SHIFT (14U) /*! LPI2C3_IPG_STOP_MODE - LPI2C3 stop mode selection, cannot change when LPI2C3_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_MASK) + #define IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_MASK (0x8000U) #define IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_SHIFT (15U) /*! LPI2C4_IPG_DOZE - LPI2C4 doze mode */ #define IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_MASK (0x10000U) #define IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_SHIFT (16U) /*! LPI2C4_STOP_REQ - LPI2C4 stop request */ #define IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_MASK (0x20000U) #define IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_SHIFT (17U) /*! LPI2C4_IPG_STOP_MODE - LPI2C4 stop mode selection, cannot change when LPI2C4_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_MASK) + #define IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_MASK (0x40000U) #define IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_SHIFT (18U) /*! LPI2C5_IPG_DOZE - LPI2C5 doze mode */ #define IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_MASK (0x80000U) #define IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_SHIFT (19U) /*! LPI2C5_STOP_REQ - LPI2C5 stop request */ #define IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_MASK (0x100000U) #define IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_SHIFT (20U) /*! LPI2C5_IPG_STOP_MODE - LPI2C5 stop mode selection, cannot change when LPI2C5_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_MASK) + #define IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_MASK (0x200000U) #define IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_SHIFT (21U) /*! LPI2C6_IPG_DOZE - LPI2C6 doze mode */ #define IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_MASK (0x400000U) #define IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_SHIFT (22U) /*! LPI2C6_STOP_REQ - LPI2C6 stop request */ #define IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_MASK (0x800000U) #define IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_SHIFT (23U) /*! LPI2C6_IPG_STOP_MODE - LPI2C6 stop mode selection, cannot change when LPI2C6_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_MASK) + #define IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_MASK (0x1000000U) #define IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_SHIFT (24U) /*! LPSPI1_IPG_DOZE - LPSPI1 doze mode */ #define IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_MASK (0x2000000U) #define IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_SHIFT (25U) /*! LPSPI1_STOP_REQ - LPSPI1 stop request */ #define IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_MASK (0x4000000U) #define IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_SHIFT (26U) /*! LPSPI1_IPG_STOP_MODE - LPSPI1 stop mode selection, cannot change when LPSPI1_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_MASK) + #define IOMUXC_GPR_GPR71_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR71_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -52122,6 +61066,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR71_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_DWP_SHIFT)) & IOMUXC_GPR_GPR71_DWP_MASK) + #define IOMUXC_GPR_GPR71_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR71_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -52135,141 +61080,187 @@ typedef struct { /*! @name GPR72 - GPR72 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_MASK (0x1U) #define IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_SHIFT (0U) /*! LPSPI2_IPG_DOZE - LPSPI2 doze mode */ #define IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_MASK (0x2U) #define IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_SHIFT (1U) /*! LPSPI2_STOP_REQ - LPSPI2 stop request */ #define IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_MASK (0x4U) #define IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_SHIFT (2U) /*! LPSPI2_IPG_STOP_MODE - LPSPI2 stop mode selection, cannot change when LPSPI2_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_MASK) + #define IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_MASK (0x8U) #define IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_SHIFT (3U) /*! LPSPI3_IPG_DOZE - LPSPI3 doze mode */ #define IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_MASK (0x10U) #define IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_SHIFT (4U) /*! LPSPI3_STOP_REQ - LPSPI3 stop request */ #define IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_MASK (0x20U) #define IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_SHIFT (5U) /*! LPSPI3_IPG_STOP_MODE - LPSPI3 stop mode selection, cannot change when LPSPI3_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_MASK) + #define IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_MASK (0x40U) #define IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_SHIFT (6U) /*! LPSPI4_IPG_DOZE - LPSPI4 doze mode */ #define IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_MASK (0x80U) #define IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_SHIFT (7U) /*! LPSPI4_STOP_REQ - LPSPI4 stop request */ #define IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_MASK (0x100U) #define IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_SHIFT (8U) /*! LPSPI4_IPG_STOP_MODE - LPSPI4 stop mode selection, cannot change when LPSPI4_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_MASK) + #define IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_MASK (0x200U) #define IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_SHIFT (9U) /*! LPSPI5_IPG_DOZE - LPSPI5 doze mode */ #define IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_MASK (0x400U) #define IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_SHIFT (10U) /*! LPSPI5_STOP_REQ - LPSPI5 stop request */ #define IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_MASK (0x800U) #define IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_SHIFT (11U) /*! LPSPI5_IPG_STOP_MODE - LPSPI5 stop mode selection, cannot change when LPSPI5_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_MASK) + #define IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_MASK (0x1000U) #define IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_SHIFT (12U) /*! LPSPI6_IPG_DOZE - LPSPI6 doze mode */ #define IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_MASK (0x2000U) #define IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_SHIFT (13U) /*! LPSPI6_STOP_REQ - LPSPI6 stop request */ #define IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_MASK (0x4000U) #define IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_SHIFT (14U) /*! LPSPI6_IPG_STOP_MODE - LPSPI6 stop mode selection, cannot change when LPSPI6_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_MASK) + #define IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_MASK (0x8000U) #define IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_SHIFT (15U) /*! LPUART1_IPG_DOZE - LPUART1 doze mode */ #define IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_MASK (0x10000U) #define IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_SHIFT (16U) /*! LPUART1_STOP_REQ - LPUART1 stop request */ #define IOMUXC_GPR_GPR72_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_MASK (0x20000U) #define IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_SHIFT (17U) /*! LPUART1_IPG_STOP_MODE - LPUART1 stop mode selection, cannot change when LPUART1_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_MASK) + #define IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_MASK (0x40000U) #define IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_SHIFT (18U) /*! LPUART2_IPG_DOZE - LPUART2 doze mode */ #define IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_MASK (0x80000U) #define IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_SHIFT (19U) /*! LPUART2_STOP_REQ - LPUART2 stop request */ #define IOMUXC_GPR_GPR72_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_MASK (0x100000U) #define IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_SHIFT (20U) /*! LPUART2_IPG_STOP_MODE - LPUART2 stop mode selection, cannot change when LPUART2_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_MASK) + #define IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_MASK (0x200000U) #define IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_SHIFT (21U) /*! LPUART3_IPG_DOZE - LPUART3 doze mode */ #define IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_MASK (0x400000U) #define IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_SHIFT (22U) /*! LPUART3_STOP_REQ - LPUART3 stop request */ #define IOMUXC_GPR_GPR72_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_MASK (0x800000U) #define IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_SHIFT (23U) /*! LPUART3_IPG_STOP_MODE - LPUART3 stop mode selection, cannot change when LPUART3_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_MASK) + #define IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_MASK (0x1000000U) #define IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_SHIFT (24U) /*! LPUART4_IPG_DOZE - LPUART4 doze mode */ #define IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_MASK (0x2000000U) #define IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_SHIFT (25U) /*! LPUART4_STOP_REQ - LPUART4 stop request */ #define IOMUXC_GPR_GPR72_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_MASK (0x4000000U) #define IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_SHIFT (26U) /*! LPUART4_IPG_STOP_MODE - LPUART4 stop mode selection, cannot change when LPUART4_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_MASK) + #define IOMUXC_GPR_GPR72_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR72_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -52279,6 +61270,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR72_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_DWP_SHIFT)) & IOMUXC_GPR_GPR72_DWP_MASK) + #define IOMUXC_GPR_GPR72_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR72_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -52292,141 +61284,187 @@ typedef struct { /*! @name GPR73 - GPR73 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_MASK (0x1U) #define IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_SHIFT (0U) /*! LPUART5_IPG_DOZE - LPUART5 doze mode */ #define IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_MASK (0x2U) #define IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_SHIFT (1U) /*! LPUART5_STOP_REQ - LPUART5 stop request */ #define IOMUXC_GPR_GPR73_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_MASK (0x4U) #define IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_SHIFT (2U) /*! LPUART5_IPG_STOP_MODE - LPUART5 stop mode selection, cannot change when LPUART5_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_MASK) + #define IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_MASK (0x8U) #define IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_SHIFT (3U) /*! LPUART6_IPG_DOZE - LPUART6 doze mode */ #define IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_MASK (0x10U) #define IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_SHIFT (4U) /*! LPUART6_STOP_REQ - LPUART6 stop request */ #define IOMUXC_GPR_GPR73_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_MASK (0x20U) #define IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_SHIFT (5U) /*! LPUART6_IPG_STOP_MODE - LPUART6 stop mode selection, cannot change when LPUART6_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_MASK) + #define IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_MASK (0x40U) #define IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_SHIFT (6U) /*! LPUART7_IPG_DOZE - LPUART7 doze mode */ #define IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_MASK (0x80U) #define IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_SHIFT (7U) /*! LPUART7_STOP_REQ - LPUART7 stop request */ #define IOMUXC_GPR_GPR73_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_MASK (0x100U) #define IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_SHIFT (8U) /*! LPUART7_IPG_STOP_MODE - LPUART7 stop mode selection, cannot change when LPUART7_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_MASK) + #define IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_MASK (0x200U) #define IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_SHIFT (9U) /*! LPUART8_IPG_DOZE - LPUART8 doze mode */ #define IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_MASK (0x400U) #define IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_SHIFT (10U) /*! LPUART8_STOP_REQ - LPUART8 stop request */ #define IOMUXC_GPR_GPR73_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_MASK (0x800U) #define IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_SHIFT (11U) /*! LPUART8_IPG_STOP_MODE - LPUART8 stop mode selection, cannot change when LPUART8_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_MASK) + #define IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_MASK (0x1000U) #define IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_SHIFT (12U) /*! LPUART9_IPG_DOZE - LPUART9 doze mode */ #define IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_MASK (0x2000U) #define IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_SHIFT (13U) /*! LPUART9_STOP_REQ - LPUART9 stop request */ #define IOMUXC_GPR_GPR73_LPUART9_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_MASK (0x4000U) #define IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_SHIFT (14U) /*! LPUART9_IPG_STOP_MODE - LPUART9 stop mode selection, cannot change when LPUART9_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_MASK) + #define IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_MASK (0x8000U) #define IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_SHIFT (15U) /*! LPUART10_IPG_DOZE - LPUART10 doze mode */ #define IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_MASK (0x10000U) #define IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_SHIFT (16U) /*! LPUART10_STOP_REQ - LPUART10 stop request */ #define IOMUXC_GPR_GPR73_LPUART10_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_MASK (0x20000U) #define IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_SHIFT (17U) /*! LPUART10_IPG_STOP_MODE - LPUART10 stop mode selection, cannot change when LPUART10_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_MASK) + #define IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_MASK (0x40000U) #define IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_SHIFT (18U) /*! LPUART11_IPG_DOZE - LPUART11 doze mode */ #define IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_MASK (0x80000U) #define IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_SHIFT (19U) /*! LPUART11_STOP_REQ - LPUART11 stop request */ #define IOMUXC_GPR_GPR73_LPUART11_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_MASK (0x100000U) #define IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_SHIFT (20U) /*! LPUART11_IPG_STOP_MODE - LPUART11 stop mode selection, cannot change when LPUART11_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_MASK) + #define IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_MASK (0x200000U) #define IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_SHIFT (21U) /*! LPUART12_IPG_DOZE - LPUART12 doze mode */ #define IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_MASK (0x400000U) #define IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_SHIFT (22U) /*! LPUART12_STOP_REQ - LPUART12 stop request */ #define IOMUXC_GPR_GPR73_LPUART12_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_MASK (0x800000U) #define IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_SHIFT (23U) /*! LPUART12_IPG_STOP_MODE - LPUART12 stop mode selection, cannot change when LPUART12_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_MASK) + #define IOMUXC_GPR_GPR73_MIC_IPG_DOZE_MASK (0x1000000U) #define IOMUXC_GPR_GPR73_MIC_IPG_DOZE_SHIFT (24U) /*! MIC_IPG_DOZE - MIC doze mode */ #define IOMUXC_GPR_GPR73_MIC_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_MIC_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR73_MIC_STOP_REQ_MASK (0x2000000U) #define IOMUXC_GPR_GPR73_MIC_STOP_REQ_SHIFT (25U) /*! MIC_STOP_REQ - MIC stop request */ #define IOMUXC_GPR_GPR73_MIC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_MIC_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_MASK (0x4000000U) #define IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_SHIFT (26U) /*! MIC_IPG_STOP_MODE - MIC stop mode selection, cannot change when MIC_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_MASK) + #define IOMUXC_GPR_GPR73_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR73_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -52436,6 +61474,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR73_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_DWP_SHIFT)) & IOMUXC_GPR_GPR73_DWP_MASK) + #define IOMUXC_GPR_GPR73_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR73_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -52449,91 +61488,109 @@ typedef struct { /*! @name GPR74 - GPR74 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR74_PIT1_STOP_REQ_MASK (0x2U) #define IOMUXC_GPR_GPR74_PIT1_STOP_REQ_SHIFT (1U) /*! PIT1_STOP_REQ - PIT1 stop request */ #define IOMUXC_GPR_GPR74_PIT1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_PIT1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_PIT1_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR74_PIT2_STOP_REQ_MASK (0x4U) #define IOMUXC_GPR_GPR74_PIT2_STOP_REQ_SHIFT (2U) /*! PIT2_STOP_REQ - PIT2 stop request */ #define IOMUXC_GPR_GPR74_PIT2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_PIT2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_PIT2_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR74_SEMC_STOP_REQ_MASK (0x8U) #define IOMUXC_GPR_GPR74_SEMC_STOP_REQ_SHIFT (3U) /*! SEMC_STOP_REQ - SEMC stop request */ #define IOMUXC_GPR_GPR74_SEMC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SEMC_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_MASK (0x10U) #define IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_SHIFT (4U) /*! SIM1_IPG_DOZE - SIM1 doze mode */ #define IOMUXC_GPR_GPR74_SIM1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_MASK (0x20U) #define IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_SHIFT (5U) /*! SIM2_IPG_DOZE - SIM2 doze mode */ #define IOMUXC_GPR_GPR74_SIM2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_MASK (0x40U) #define IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_SHIFT (6U) /*! SNVS_HP_IPG_DOZE - SNVS_HP doze mode */ #define IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_MASK (0x80U) #define IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_SHIFT (7U) /*! SNVS_HP_STOP_REQ - SNVS_HP stop request */ #define IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_MASK (0x100U) #define IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_SHIFT (8U) /*! WDOG1_IPG_DOZE - WDOG1 doze mode */ #define IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_MASK (0x200U) #define IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_SHIFT (9U) /*! WDOG2_IPG_DOZE - WDOG2 doze mode */ #define IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_MASK) + #define IOMUXC_GPR_GPR74_SAI1_STOP_REQ_MASK (0x400U) #define IOMUXC_GPR_GPR74_SAI1_STOP_REQ_SHIFT (10U) /*! SAI1_STOP_REQ - SAI1 stop request */ #define IOMUXC_GPR_GPR74_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI1_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR74_SAI2_STOP_REQ_MASK (0x800U) #define IOMUXC_GPR_GPR74_SAI2_STOP_REQ_SHIFT (11U) /*! SAI2_STOP_REQ - SAI2 stop request */ #define IOMUXC_GPR_GPR74_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI2_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR74_SAI3_STOP_REQ_MASK (0x1000U) #define IOMUXC_GPR_GPR74_SAI3_STOP_REQ_SHIFT (12U) /*! SAI3_STOP_REQ - SAI3 stop request */ #define IOMUXC_GPR_GPR74_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI3_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR74_SAI4_STOP_REQ_MASK (0x2000U) #define IOMUXC_GPR_GPR74_SAI4_STOP_REQ_SHIFT (13U) /*! SAI4_STOP_REQ - SAI4 stop request */ #define IOMUXC_GPR_GPR74_SAI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI4_STOP_REQ_MASK) + #define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_MASK (0x4000U) #define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_SHIFT (14U) /*! FLEXIO1_STOP_REQ_BUS - FLEXIO1 bus clock domain stop request */ #define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_MASK) + #define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_MASK (0x8000U) #define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_SHIFT (15U) /*! FLEXIO1_STOP_REQ_PER - FLEXIO1 peripheral clock domain stop request */ #define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_MASK) + #define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_MASK (0x10000U) #define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_SHIFT (16U) /*! FLEXIO2_STOP_REQ_BUS - FLEXIO2 bus clock domain stop request */ #define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_MASK) + #define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_MASK (0x20000U) #define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_SHIFT (17U) /*! FLEXIO2_STOP_REQ_PER - FLEXIO2 peripheral clock domain stop request */ #define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_MASK) + #define IOMUXC_GPR_GPR74_DWP_MASK (0x30000000U) #define IOMUXC_GPR_GPR74_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -52543,6 +61600,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_GPR_GPR74_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_DWP_SHIFT)) & IOMUXC_GPR_GPR74_DWP_MASK) + #define IOMUXC_GPR_GPR74_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_GPR_GPR74_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -52556,161 +61614,193 @@ typedef struct { /*! @name GPR75 - GPR75 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR75_ADC1_STOP_ACK_MASK (0x1U) #define IOMUXC_GPR_GPR75_ADC1_STOP_ACK_SHIFT (0U) /*! ADC1_STOP_ACK - ADC1 stop acknowledge */ #define IOMUXC_GPR_GPR75_ADC1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ADC1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ADC1_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_ADC2_STOP_ACK_MASK (0x2U) #define IOMUXC_GPR_GPR75_ADC2_STOP_ACK_SHIFT (1U) /*! ADC2_STOP_ACK - ADC2 stop acknowledge */ #define IOMUXC_GPR_GPR75_ADC2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ADC2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ADC2_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_CAAM_STOP_ACK_MASK (0x4U) #define IOMUXC_GPR_GPR75_CAAM_STOP_ACK_SHIFT (2U) /*! CAAM_STOP_ACK - CAAM stop acknowledge */ #define IOMUXC_GPR_GPR75_CAAM_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAAM_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAAM_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_CAN1_STOP_ACK_MASK (0x8U) #define IOMUXC_GPR_GPR75_CAN1_STOP_ACK_SHIFT (3U) /*! CAN1_STOP_ACK - CAN1 stop acknowledge */ #define IOMUXC_GPR_GPR75_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN1_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_CAN2_STOP_ACK_MASK (0x10U) #define IOMUXC_GPR_GPR75_CAN2_STOP_ACK_SHIFT (4U) /*! CAN2_STOP_ACK - CAN2 stop acknowledge */ #define IOMUXC_GPR_GPR75_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN2_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_CAN3_STOP_ACK_MASK (0x20U) #define IOMUXC_GPR_GPR75_CAN3_STOP_ACK_SHIFT (5U) /*! CAN3_STOP_ACK - CAN3 stop acknowledge */ #define IOMUXC_GPR_GPR75_CAN3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN3_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_EDMA_STOP_ACK_MASK (0x40U) #define IOMUXC_GPR_GPR75_EDMA_STOP_ACK_SHIFT (6U) /*! EDMA_STOP_ACK - EDMA stop acknowledge */ #define IOMUXC_GPR_GPR75_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_EDMA_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_MASK (0x80U) #define IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_SHIFT (7U) /*! EDMA_LPSR_STOP_ACK - EDMA_LPSR stop acknowledge */ #define IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_ENET_STOP_ACK_MASK (0x100U) #define IOMUXC_GPR_GPR75_ENET_STOP_ACK_SHIFT (8U) /*! ENET_STOP_ACK - ENET stop acknowledge */ #define IOMUXC_GPR_GPR75_ENET_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ENET_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_MASK (0x200U) #define IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_SHIFT (9U) /*! ENET1G_STOP_ACK - ENET1G stop acknowledge */ #define IOMUXC_GPR_GPR75_ENET1G_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_MASK (0x400U) #define IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_SHIFT (10U) /*! FLEXSPI1_STOP_ACK - FLEXSPI1 stop acknowledge */ #define IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_MASK (0x800U) #define IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_SHIFT (11U) /*! FLEXSPI2_STOP_ACK - FLEXSPI2 stop acknowledge */ #define IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_MASK (0x1000U) #define IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_SHIFT (12U) /*! LPI2C1_STOP_ACK - LPI2C1 stop acknowledge */ #define IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_MASK (0x2000U) #define IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_SHIFT (13U) /*! LPI2C2_STOP_ACK - LPI2C2 stop acknowledge */ #define IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_MASK (0x4000U) #define IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_SHIFT (14U) /*! LPI2C3_STOP_ACK - LPI2C3 stop acknowledge */ #define IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_MASK (0x8000U) #define IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_SHIFT (15U) /*! LPI2C4_STOP_ACK - LPI2C4 stop acknowledge */ #define IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_MASK (0x10000U) #define IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_SHIFT (16U) /*! LPI2C5_STOP_ACK - LPI2C5 stop acknowledge */ #define IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_MASK (0x20000U) #define IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_SHIFT (17U) /*! LPI2C6_STOP_ACK - LPI2C6 stop acknowledge */ #define IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_MASK (0x40000U) #define IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_SHIFT (18U) /*! LPSPI1_STOP_ACK - LPSPI1 stop acknowledge */ #define IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_MASK (0x80000U) #define IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_SHIFT (19U) /*! LPSPI2_STOP_ACK - LPSPI2 stop acknowledge */ #define IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_MASK (0x100000U) #define IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_SHIFT (20U) /*! LPSPI3_STOP_ACK - LPSPI3 stop acknowledge */ #define IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_MASK (0x200000U) #define IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_SHIFT (21U) /*! LPSPI4_STOP_ACK - LPSPI4 stop acknowledge */ #define IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_MASK (0x400000U) #define IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_SHIFT (22U) /*! LPSPI5_STOP_ACK - LPSPI5 stop acknowledge */ #define IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_MASK (0x800000U) #define IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_SHIFT (23U) /*! LPSPI6_STOP_ACK - LPSPI6 stop acknowledge */ #define IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_MASK (0x1000000U) #define IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_SHIFT (24U) /*! LPUART1_STOP_ACK - LPUART1 stop acknowledge */ #define IOMUXC_GPR_GPR75_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_MASK (0x2000000U) #define IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_SHIFT (25U) /*! LPUART2_STOP_ACK - LPUART2 stop acknowledge */ #define IOMUXC_GPR_GPR75_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_MASK (0x4000000U) #define IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_SHIFT (26U) /*! LPUART3_STOP_ACK - LPUART3 stop acknowledge */ #define IOMUXC_GPR_GPR75_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_MASK (0x8000000U) #define IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_SHIFT (27U) /*! LPUART4_STOP_ACK - LPUART4 stop acknowledge */ #define IOMUXC_GPR_GPR75_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_MASK (0x10000000U) #define IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_SHIFT (28U) /*! LPUART5_STOP_ACK - LPUART5 stop acknowledge */ #define IOMUXC_GPR_GPR75_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_MASK (0x20000000U) #define IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_SHIFT (29U) /*! LPUART6_STOP_ACK - LPUART6 stop acknowledge */ #define IOMUXC_GPR_GPR75_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_MASK (0x40000000U) #define IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_SHIFT (30U) /*! LPUART7_STOP_ACK - LPUART7 stop acknowledge */ #define IOMUXC_GPR_GPR75_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_MASK (0x80000000U) #define IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_SHIFT (31U) /*! LPUART8_STOP_ACK - LPUART8 stop acknowledge @@ -52720,86 +61810,103 @@ typedef struct { /*! @name GPR76 - GPR76 General Purpose Register */ /*! @{ */ + #define IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_MASK (0x1U) #define IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_SHIFT (0U) /*! LPUART9_STOP_ACK - LPUART9 stop acknowledge */ #define IOMUXC_GPR_GPR76_LPUART9_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_MASK (0x2U) #define IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_SHIFT (1U) /*! LPUART10_STOP_ACK - LPUART10 stop acknowledge */ #define IOMUXC_GPR_GPR76_LPUART10_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_MASK (0x4U) #define IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_SHIFT (2U) /*! LPUART11_STOP_ACK - LPUART11 stop acknowledge */ #define IOMUXC_GPR_GPR76_LPUART11_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_MASK (0x8U) #define IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_SHIFT (3U) /*! LPUART12_STOP_ACK - LPUART12 stop acknowledge */ #define IOMUXC_GPR_GPR76_LPUART12_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR76_MIC_STOP_ACK_MASK (0x10U) #define IOMUXC_GPR_GPR76_MIC_STOP_ACK_SHIFT (4U) /*! MIC_STOP_ACK - MIC stop acknowledge */ #define IOMUXC_GPR_GPR76_MIC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_MIC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_MIC_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR76_PIT1_STOP_ACK_MASK (0x20U) #define IOMUXC_GPR_GPR76_PIT1_STOP_ACK_SHIFT (5U) /*! PIT1_STOP_ACK - PIT1 stop acknowledge */ #define IOMUXC_GPR_GPR76_PIT1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_PIT1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_PIT1_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR76_PIT2_STOP_ACK_MASK (0x40U) #define IOMUXC_GPR_GPR76_PIT2_STOP_ACK_SHIFT (6U) /*! PIT2_STOP_ACK - PIT2 stop acknowledge */ #define IOMUXC_GPR_GPR76_PIT2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_PIT2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_PIT2_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR76_SEMC_STOP_ACK_MASK (0x80U) #define IOMUXC_GPR_GPR76_SEMC_STOP_ACK_SHIFT (7U) /*! SEMC_STOP_ACK - SEMC stop acknowledge */ #define IOMUXC_GPR_GPR76_SEMC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SEMC_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_MASK (0x100U) #define IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_SHIFT (8U) /*! SNVS_HP_STOP_ACK - SNVS_HP stop acknowledge */ #define IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR76_SAI1_STOP_ACK_MASK (0x200U) #define IOMUXC_GPR_GPR76_SAI1_STOP_ACK_SHIFT (9U) /*! SAI1_STOP_ACK - SAI1 stop acknowledge */ #define IOMUXC_GPR_GPR76_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI1_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR76_SAI2_STOP_ACK_MASK (0x400U) #define IOMUXC_GPR_GPR76_SAI2_STOP_ACK_SHIFT (10U) /*! SAI2_STOP_ACK - SAI2 stop acknowledge */ #define IOMUXC_GPR_GPR76_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI2_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR76_SAI3_STOP_ACK_MASK (0x800U) #define IOMUXC_GPR_GPR76_SAI3_STOP_ACK_SHIFT (11U) /*! SAI3_STOP_ACK - SAI3 stop acknowledge */ #define IOMUXC_GPR_GPR76_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI3_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR76_SAI4_STOP_ACK_MASK (0x1000U) #define IOMUXC_GPR_GPR76_SAI4_STOP_ACK_SHIFT (12U) /*! SAI4_STOP_ACK - SAI4 stop acknowledge */ #define IOMUXC_GPR_GPR76_SAI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI4_STOP_ACK_MASK) + #define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_MASK (0x2000U) #define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_SHIFT (13U) /*! FLEXIO1_STOP_ACK_BUS - FLEXIO1 stop acknowledge of bus clock domain */ #define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_MASK) + #define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_MASK (0x4000U) #define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_SHIFT (14U) /*! FLEXIO1_STOP_ACK_PER - FLEXIO1 stop acknowledge of peripheral clock domain */ #define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_MASK) + #define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_MASK (0x8000U) #define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_SHIFT (15U) /*! FLEXIO2_STOP_ACK_BUS - FLEXIO2 stop acknowledge of bus clock domain */ #define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_MASK) + #define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_MASK (0x10000U) #define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_SHIFT (16U) /*! FLEXIO2_STOP_ACK_PER - FLEXIO2 stop acknowledge of peripheral clock domain @@ -52855,6 +61962,7 @@ typedef struct { /*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_LPSR_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_LPSR_15 SW MUX Control Register */ /*! @{ */ + #define IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xFU) #define IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U) /*! MUX_MODE - MUX Mode Select Field. @@ -52868,6 +61976,7 @@ typedef struct { * 0b1010..Select mux mode: ALT10 mux port: GPIO12_IO00 of instance: GPIO12 */ #define IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_MASK) + #define IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_MASK (0x10U) #define IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_SHIFT (4U) /*! SION - Software Input On Field. @@ -52882,6 +61991,7 @@ typedef struct { /*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_LPSR_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_LPSR_15 SW PAD Control Register */ /*! @{ */ + #define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_MASK (0x1U) #define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_SHIFT (0U) /*! SRE - Slew Rate Field @@ -52889,6 +61999,7 @@ typedef struct { * 0b1..Fast Slew Rate */ #define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_MASK) + #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_MASK (0x2U) #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_SHIFT (1U) /*! DSE - Drive Strength Field @@ -52896,13 +62007,15 @@ typedef struct { * 0b1..high driver */ #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_MASK) + #define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_MASK (0x4U) #define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_SHIFT (2U) /*! PUE - Pull / Keep Select Field - * 0b0..Keeper - * 0b1..Pull + * 0b0..Pull Disable + * 0b1..Pull Enable */ #define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_MASK) + #define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_MASK (0x8U) #define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_SHIFT (3U) /*! PUS - Pull Up / Down Config. Field @@ -52910,6 +62023,7 @@ typedef struct { * 0b1..Weak pull up */ #define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_MASK) + #define IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_MASK (0x20U) #define IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_SHIFT (5U) /*! ODE_LPSR - Open Drain LPSR Field @@ -52917,6 +62031,7 @@ typedef struct { * 0b1..Enabled */ #define IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_MASK) + #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_MASK (0x30000000U) #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -52926,6 +62041,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_MASK) + #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -52942,6 +62058,7 @@ typedef struct { /*! @name SELECT_INPUT - CAN3_IPP_IND_CANRX_SELECT_INPUT DAISY Register..SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY Register */ /*! @{ */ + #define IOMUXC_LPSR_SELECT_INPUT_DAISY_MASK (0x3U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */ #define IOMUXC_LPSR_SELECT_INPUT_DAISY_SHIFT (0U) /*! DAISY - Selecting Pads Involved in Daisy Chain. @@ -53014,7 +62131,8 @@ typedef struct { __IO uint32_t GPR24; /**< GPR24 General Purpose Register, offset: 0x60 */ __IO uint32_t GPR25; /**< GPR25 General Purpose Register, offset: 0x64 */ __IO uint32_t GPR26; /**< GPR26 General Purpose Register, offset: 0x68 */ - uint8_t RESERVED_0[28]; + uint8_t RESERVED_0[24]; + __IO uint32_t GPR33; /**< GPR33 General Purpose Register, offset: 0x84 */ __IO uint32_t GPR34; /**< GPR34 General Purpose Register, offset: 0x88 */ __IO uint32_t GPR35; /**< GPR35 General Purpose Register, offset: 0x8C */ __IO uint32_t GPR36; /**< GPR36 General Purpose Register, offset: 0x90 */ @@ -53036,11 +62154,13 @@ typedef struct { /*! @name GPR0 - GPR0 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_MASK (0xFFF8U) #define IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_SHIFT (3U) /*! CM4_INIT_VTOR_LOW - CM4 Vector table offset value lower bits out of reset */ #define IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_MASK) + #define IOMUXC_LPSR_GPR_GPR0_DWP_MASK (0x30000000U) #define IOMUXC_LPSR_GPR_GPR0_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -53050,6 +62170,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_LPSR_GPR_GPR0_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_DWP_MASK) + #define IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -53063,11 +62184,13 @@ typedef struct { /*! @name GPR1 - GPR1 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_MASK (0xFFFFU) #define IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_SHIFT (0U) /*! CM4_INIT_VTOR_HIGH - CM4 Vector table offset value higher bits out of reset */ #define IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_MASK) + #define IOMUXC_LPSR_GPR_GPR1_DWP_MASK (0x30000000U) #define IOMUXC_LPSR_GPR_GPR1_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -53077,6 +62200,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_LPSR_GPR_GPR1_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_DWP_MASK) + #define IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -53090,11 +62214,15 @@ typedef struct { /*! @name GPR2 - GPR2 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR2_LOCK_MASK (0x1U) #define IOMUXC_LPSR_GPR_GPR2_LOCK_SHIFT (0U) /*! LOCK - Lock the write to bit 31:1 + * 0b1..Write access to bit 31:1 is blocked + * 0b0..Write access to bit 31:1 is not blocked */ #define IOMUXC_LPSR_GPR_GPR2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR2_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR2_LOCK_MASK) + #define IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_MASK (0xFFFFFFF8U) #define IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_SHIFT (3U) /*! APC_AC_R0_BOT - APC start address of memory region-0 @@ -53104,11 +62232,15 @@ typedef struct { /*! @name GPR3 - GPR3 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR3_LOCK_MASK (0x1U) #define IOMUXC_LPSR_GPR_GPR3_LOCK_SHIFT (0U) /*! LOCK - Lock the write to bit 31:1 + * 0b1..Write access to bit 31:1 is blocked + * 0b0..Write access to bit 31:1 is not blocked */ #define IOMUXC_LPSR_GPR_GPR3_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR3_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR3_LOCK_MASK) + #define IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_MASK (0xFFFFFFF8U) #define IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_SHIFT (3U) /*! APC_AC_R0_TOP - APC end address of memory region-0 @@ -53118,11 +62250,15 @@ typedef struct { /*! @name GPR4 - GPR4 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR4_LOCK_MASK (0x1U) #define IOMUXC_LPSR_GPR_GPR4_LOCK_SHIFT (0U) /*! LOCK - Lock the write to bit 31:1 + * 0b1..Write access to bit 31:1 is blocked + * 0b0..Write access to bit 31:1 is not blocked */ #define IOMUXC_LPSR_GPR_GPR4_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR4_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR4_LOCK_MASK) + #define IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_MASK (0xFFFFFFF8U) #define IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_SHIFT (3U) /*! APC_AC_R1_BOT - APC start address of memory region-1 @@ -53132,11 +62268,15 @@ typedef struct { /*! @name GPR5 - GPR5 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR5_LOCK_MASK (0x1U) #define IOMUXC_LPSR_GPR_GPR5_LOCK_SHIFT (0U) /*! LOCK - Lock the write to bit 31:1 + * 0b1..Write access to bit 31:1 is blocked + * 0b0..Write access to bit 31:1 is not blocked */ #define IOMUXC_LPSR_GPR_GPR5_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR5_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR5_LOCK_MASK) + #define IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_MASK (0xFFFFFFF8U) #define IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_SHIFT (3U) /*! APC_AC_R1_TOP - APC end address of memory region-1 @@ -53146,11 +62286,15 @@ typedef struct { /*! @name GPR6 - GPR6 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR6_LOCK_MASK (0x1U) #define IOMUXC_LPSR_GPR_GPR6_LOCK_SHIFT (0U) /*! LOCK - Lock the write to bit 31:1 + * 0b1..Write access to bit 31:1 is blocked + * 0b0..Write access to bit 31:1 is not blocked */ #define IOMUXC_LPSR_GPR_GPR6_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR6_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR6_LOCK_MASK) + #define IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_MASK (0xFFFFFFF8U) #define IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_SHIFT (3U) /*! APC_AC_R2_BOT - APC start address of memory region-2 @@ -53160,11 +62304,15 @@ typedef struct { /*! @name GPR7 - GPR7 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR7_LOCK_MASK (0x1U) #define IOMUXC_LPSR_GPR_GPR7_LOCK_SHIFT (0U) /*! LOCK - Lock the write to bit 31:1 + * 0b1..Write access to bit 31:1 is blocked + * 0b0..Write access to bit 31:1 is not blocked */ #define IOMUXC_LPSR_GPR_GPR7_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR7_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR7_LOCK_MASK) + #define IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_MASK (0xFFFFFFF8U) #define IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_SHIFT (3U) /*! APC_AC_R2_TOP - APC end address of memory region-2 @@ -53174,11 +62322,15 @@ typedef struct { /*! @name GPR8 - GPR8 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR8_LOCK_MASK (0x1U) #define IOMUXC_LPSR_GPR_GPR8_LOCK_SHIFT (0U) /*! LOCK - Lock the write to bit 31:1 + * 0b1..Write access to bit 31:1 is blocked + * 0b0..Write access to bit 31:1 is not blocked */ #define IOMUXC_LPSR_GPR_GPR8_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR8_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR8_LOCK_MASK) + #define IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_MASK (0xFFFFFFF8U) #define IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_SHIFT (3U) /*! APC_AC_R3_BOT - APC start address of memory region-3 @@ -53188,11 +62340,15 @@ typedef struct { /*! @name GPR9 - GPR9 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR9_LOCK_MASK (0x1U) #define IOMUXC_LPSR_GPR_GPR9_LOCK_SHIFT (0U) /*! LOCK - Lock the write to bit 31:1 + * 0b1..Write access to bit 31:1 is blocked + * 0b0..Write access to bit 31:1 is not blocked */ #define IOMUXC_LPSR_GPR_GPR9_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR9_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR9_LOCK_MASK) + #define IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_MASK (0xFFFFFFF8U) #define IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_SHIFT (3U) /*! APC_AC_R3_TOP - APC end address of memory region-3 @@ -53202,11 +62358,15 @@ typedef struct { /*! @name GPR10 - GPR10 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR10_LOCK_MASK (0x1U) #define IOMUXC_LPSR_GPR_GPR10_LOCK_SHIFT (0U) /*! LOCK - Lock the write to bit 31:1 + * 0b1..Write access to bit 31:1 is blocked + * 0b0..Write access to bit 31:1 is not blocked */ #define IOMUXC_LPSR_GPR_GPR10_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR10_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR10_LOCK_MASK) + #define IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_MASK (0xFFFFFFF8U) #define IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_SHIFT (3U) /*! APC_AC_R4_BOT - APC start address of memory region-4 @@ -53216,11 +62376,15 @@ typedef struct { /*! @name GPR11 - GPR11 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR11_LOCK_MASK (0x1U) #define IOMUXC_LPSR_GPR_GPR11_LOCK_SHIFT (0U) /*! LOCK - Lock the write to bit 31:1 + * 0b1..Write access to bit 31:1 is blocked + * 0b0..Write access to bit 31:1 is not blocked */ #define IOMUXC_LPSR_GPR_GPR11_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR11_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR11_LOCK_MASK) + #define IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_MASK (0xFFFFFFF8U) #define IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_SHIFT (3U) /*! APC_AC_R4_TOP - APC end address of memory region-4 @@ -53230,11 +62394,15 @@ typedef struct { /*! @name GPR12 - GPR12 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR12_LOCK_MASK (0x1U) #define IOMUXC_LPSR_GPR_GPR12_LOCK_SHIFT (0U) /*! LOCK - Lock the write to bit 31:1 + * 0b1..Write access to bit 31:1 is blocked + * 0b0..Write access to bit 31:1 is not blocked */ #define IOMUXC_LPSR_GPR_GPR12_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR12_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR12_LOCK_MASK) + #define IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_MASK (0xFFFFFFF8U) #define IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_SHIFT (3U) /*! APC_AC_R5_BOT - APC start address of memory region-5 @@ -53244,11 +62412,15 @@ typedef struct { /*! @name GPR13 - GPR13 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR13_LOCK_MASK (0x1U) #define IOMUXC_LPSR_GPR_GPR13_LOCK_SHIFT (0U) /*! LOCK - Lock the write to bit 31:1 + * 0b1..Write access to bit 31:1 is blocked + * 0b0..Write access to bit 31:1 is not blocked */ #define IOMUXC_LPSR_GPR_GPR13_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR13_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR13_LOCK_MASK) + #define IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_MASK (0xFFFFFFF8U) #define IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_SHIFT (3U) /*! APC_AC_R5_TOP - APC end address of memory region-5 @@ -53258,11 +62430,15 @@ typedef struct { /*! @name GPR14 - GPR14 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR14_LOCK_MASK (0x1U) #define IOMUXC_LPSR_GPR_GPR14_LOCK_SHIFT (0U) /*! LOCK - Lock the write to bit 31:1 + * 0b1..Write access to bit 31:1 is blocked + * 0b0..Write access to bit 31:1 is not blocked */ #define IOMUXC_LPSR_GPR_GPR14_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR14_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR14_LOCK_MASK) + #define IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_MASK (0xFFFFFFF8U) #define IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_SHIFT (3U) /*! APC_AC_R6_BOT - APC start address of memory region-6 @@ -53272,11 +62448,15 @@ typedef struct { /*! @name GPR15 - GPR15 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR15_LOCK_MASK (0x1U) #define IOMUXC_LPSR_GPR_GPR15_LOCK_SHIFT (0U) /*! LOCK - Lock the write to bit 31:1 + * 0b1..Write access to bit 31:1 is blocked + * 0b0..Write access to bit 31:1 is not blocked */ #define IOMUXC_LPSR_GPR_GPR15_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR15_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR15_LOCK_MASK) + #define IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_MASK (0xFFFFFFF8U) #define IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_SHIFT (3U) /*! APC_AC_R6_TOP - APC end address of memory region-6 @@ -53286,11 +62466,15 @@ typedef struct { /*! @name GPR16 - GPR16 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR16_LOCK_MASK (0x1U) #define IOMUXC_LPSR_GPR_GPR16_LOCK_SHIFT (0U) /*! LOCK - Lock the write to bit 31:1 + * 0b1..Write access to bit 31:1 is blocked + * 0b0..Write access to bit 31:1 is not blocked */ #define IOMUXC_LPSR_GPR_GPR16_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR16_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR16_LOCK_MASK) + #define IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_MASK (0xFFFFFFF8U) #define IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_SHIFT (3U) /*! APC_AC_R7_BOT - APC start address of memory region-7 @@ -53300,11 +62484,15 @@ typedef struct { /*! @name GPR17 - GPR17 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR17_LOCK_MASK (0x1U) #define IOMUXC_LPSR_GPR_GPR17_LOCK_SHIFT (0U) /*! LOCK - Lock the write to bit 31:1 + * 0b1..Write access to bit 31:1 is blocked + * 0b0..Write access to bit 31:1 is not blocked */ #define IOMUXC_LPSR_GPR_GPR17_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR17_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR17_LOCK_MASK) + #define IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_MASK (0xFFFFFFF8U) #define IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_SHIFT (3U) /*! APC_AC_R7_TOP - APC end address of memory region-7 @@ -53314,11 +62502,15 @@ typedef struct { /*! @name GPR18 - GPR18 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_MASK (0x10U) #define IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_SHIFT (4U) /*! APC_R0_ENCRYPT_ENABLE - APC memory region-0 encryption enable + * 0b1..Encryption enabled + * 0b0..No effect */ #define IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_MASK) + #define IOMUXC_LPSR_GPR_GPR18_LOCK_MASK (0xFFFF0000U) #define IOMUXC_LPSR_GPR_GPR18_LOCK_SHIFT (16U) /*! LOCK - Lock the write to bit 15:0 @@ -53328,11 +62520,15 @@ typedef struct { /*! @name GPR19 - GPR19 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_MASK (0x10U) #define IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_SHIFT (4U) /*! APC_R1_ENCRYPT_ENABLE - APC memory region-1 encryption enable + * 0b1..Encryption enabled + * 0b0..No effect */ #define IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_MASK) + #define IOMUXC_LPSR_GPR_GPR19_LOCK_MASK (0xFFFF0000U) #define IOMUXC_LPSR_GPR_GPR19_LOCK_SHIFT (16U) /*! LOCK - Lock the write to bit 15:0 @@ -53342,11 +62538,15 @@ typedef struct { /*! @name GPR20 - GPR20 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_MASK (0x10U) #define IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_SHIFT (4U) /*! APC_R2_ENCRYPT_ENABLE - APC memory region-2 encryption enable + * 0b1..Encryption enabled + * 0b0..No effect */ #define IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_MASK) + #define IOMUXC_LPSR_GPR_GPR20_LOCK_MASK (0xFFFF0000U) #define IOMUXC_LPSR_GPR_GPR20_LOCK_SHIFT (16U) /*! LOCK - Lock the write to bit 15:0 @@ -53356,11 +62556,15 @@ typedef struct { /*! @name GPR21 - GPR21 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_MASK (0x10U) #define IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_SHIFT (4U) /*! APC_R3_ENCRYPT_ENABLE - APC memory region-3 encryption enable + * 0b1..Encryption enabled + * 0b0..No effect */ #define IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_MASK) + #define IOMUXC_LPSR_GPR_GPR21_LOCK_MASK (0xFFFF0000U) #define IOMUXC_LPSR_GPR_GPR21_LOCK_SHIFT (16U) /*! LOCK - Lock the write to bit 15:0 @@ -53370,11 +62574,15 @@ typedef struct { /*! @name GPR22 - GPR22 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_MASK (0x10U) #define IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_SHIFT (4U) /*! APC_R4_ENCRYPT_ENABLE - APC memory region-4 encryption enable + * 0b1..Encryption enabled + * 0b0..No effect */ #define IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_MASK) + #define IOMUXC_LPSR_GPR_GPR22_LOCK_MASK (0xFFFF0000U) #define IOMUXC_LPSR_GPR_GPR22_LOCK_SHIFT (16U) /*! LOCK - Lock the write to bit 15:0 @@ -53384,11 +62592,15 @@ typedef struct { /*! @name GPR23 - GPR23 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_MASK (0x10U) #define IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_SHIFT (4U) /*! APC_R5_ENCRYPT_ENABLE - APC memory region-5 encryption enable + * 0b1..Encryption enabled + * 0b0..No effect */ #define IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_MASK) + #define IOMUXC_LPSR_GPR_GPR23_LOCK_MASK (0xFFFF0000U) #define IOMUXC_LPSR_GPR_GPR23_LOCK_SHIFT (16U) /*! LOCK - Lock the write to bit 15:0 @@ -53398,11 +62610,15 @@ typedef struct { /*! @name GPR24 - GPR24 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_MASK (0x10U) #define IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_SHIFT (4U) /*! APC_R6_ENCRYPT_ENABLE - APC memory region-6 encryption enable + * 0b1..Encryption enabled + * 0b0..No effect */ #define IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_MASK) + #define IOMUXC_LPSR_GPR_GPR24_LOCK_MASK (0xFFFF0000U) #define IOMUXC_LPSR_GPR_GPR24_LOCK_SHIFT (16U) /*! LOCK - Lock the write to bit 15:0 @@ -53412,16 +62628,23 @@ typedef struct { /*! @name GPR25 - GPR25 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_MASK (0x10U) #define IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_SHIFT (4U) /*! APC_R7_ENCRYPT_ENABLE - APC memory region-7 encryption enable + * 0b1..Encryption enabled + * 0b0..No effect */ #define IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_MASK) + #define IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK (0x20U) #define IOMUXC_LPSR_GPR_GPR25_APC_VALID_SHIFT (5U) /*! APC_VALID - APC global enable bit + * 0b1..Enable encryption for GPRx[APC_x_ENCRYPT_ENABLE] (valid for GPR2-GPR25) + * 0b0..No effect */ #define IOMUXC_LPSR_GPR_GPR25_APC_VALID(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_APC_VALID_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK) + #define IOMUXC_LPSR_GPR_GPR25_LOCK_MASK (0xFFFF0000U) #define IOMUXC_LPSR_GPR_GPR25_LOCK_SHIFT (16U) /*! LOCK - Lock the write to bit 15:0 @@ -53431,17 +62654,20 @@ typedef struct { /*! @name GPR26 - GPR26 General Purpose Register */ /*! @{ */ -#define IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK (0xFFFFFFU) + +#define IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK (0x1FFFFFFU) #define IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_SHIFT (0U) /*! CM7_INIT_VTOR - Vector table offset register out of reset. See the ARM v7-M Architecture * Reference Manual for more information about the vector table offset register (VTOR). */ #define IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK) -#define IOMUXC_LPSR_GPR_GPR26_FIELD_0_MASK (0xF000000U) -#define IOMUXC_LPSR_GPR_GPR26_FIELD_0_SHIFT (24U) + +#define IOMUXC_LPSR_GPR_GPR26_FIELD_0_MASK (0xE000000U) +#define IOMUXC_LPSR_GPR_GPR26_FIELD_0_SHIFT (25U) /*! FIELD_0 - General purpose bits */ #define IOMUXC_LPSR_GPR_GPR26_FIELD_0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_FIELD_0_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_FIELD_0_MASK) + #define IOMUXC_LPSR_GPR_GPR26_DWP_MASK (0x30000000U) #define IOMUXC_LPSR_GPR_GPR26_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -53451,6 +62677,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_LPSR_GPR_GPR26_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_DWP_MASK) + #define IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -53462,53 +62689,95 @@ typedef struct { #define IOMUXC_LPSR_GPR_GPR26_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_MASK) /*! @} */ +/*! @name GPR33 - GPR33 General Purpose Register */ +/*! @{ */ + +#define IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_MASK (0x1U) +#define IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_SHIFT (0U) +/*! M4_NMI_CLEAR - Clear CM4 NMI holding register + */ +#define IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_MASK) + +#define IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_MASK (0x100U) +#define IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT (8U) +/*! USBPHY1_WAKEUP_IRQ_CLEAR - Clear USBPHY1 wakeup interrupt holding register + */ +#define IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_MASK) + +#define IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_MASK (0x200U) +#define IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT (9U) +/*! USBPHY2_WAKEUP_IRQ_CLEAR - Clear USBPHY1 wakeup interrupt holding register + */ +#define IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_MASK) + +#define IOMUXC_LPSR_GPR_GPR33_DWP_MASK (0x30000000U) +#define IOMUXC_LPSR_GPR_GPR33_DWP_SHIFT (28U) +/*! DWP - Domain write protection + * 0b00..Both cores are allowed + * 0b01..CM7 is forbidden + * 0b10..CM4 is forbidden + * 0b11..Both cores are forbidden + */ +#define IOMUXC_LPSR_GPR_GPR33_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_DWP_MASK) + +#define IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_MASK (0xC0000000U) +#define IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_SHIFT (30U) +/*! DWP_LOCK - Domain write protection lock + * 0b00..Neither of DWP bits is locked + * 0b01..The lower DWP bit is locked + * 0b10..The higher DWP bit is locked + * 0b11..Both DWP bits are locked + */ +#define IOMUXC_LPSR_GPR_GPR33_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_MASK) +/*! @} */ + /*! @name GPR34 - GPR34 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_MASK (0x2U) #define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_SHIFT (1U) /*! GPIO_LPSR_HIGH_RANGE - GPIO_LPSR IO bank supply voltage range selection */ #define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_MASK) + #define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_MASK (0x4U) #define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_SHIFT (2U) /*! GPIO_LPSR_LOW_RANGE - GPIO_LPSR IO bank supply voltage range selection */ #define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_MASK) + #define IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_MASK (0x8U) #define IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_SHIFT (3U) /*! M7_NMI_MASK - Mask CM7 NMI pin input + * 0b0..NMI input from IO to CM7 is not blocked + * 0b1..NMI input from IO to CM7 is blocked */ #define IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_MASK) + #define IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_MASK (0x10U) #define IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_SHIFT (4U) /*! M4_NMI_MASK - Mask CM4 NMI pin input + * 0b0..NMI input from IO to CM4 is not blocked + * 0b1..NMI input from IO to CM4 is blocked */ #define IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_MASK) + #define IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK (0x20U) #define IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_SHIFT (5U) /*! M4_GPC_SLEEP_SEL - CM4 sleep request selection + * 0b0..CM4 SLEEPDEEP is sent to GPC + * 0b1..CM4 SLEEPING is sent to GPC */ #define IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK) -#define IOMUXC_LPSR_GPR_GPR34_M4_NMI_CLEAR_MASK (0x40U) -#define IOMUXC_LPSR_GPR_GPR34_M4_NMI_CLEAR_SHIFT (6U) -/*! M4_NMI_CLEAR - Clear CM4 NMI holding register - */ -#define IOMUXC_LPSR_GPR_GPR34_M4_NMI_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_NMI_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_NMI_CLEAR_MASK) -#define IOMUXC_LPSR_GPR_GPR34_USBPHY1_WAKEUP_IRQ_CLEAR_MASK (0x80U) -#define IOMUXC_LPSR_GPR_GPR34_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT (7U) -/*! USBPHY1_WAKEUP_IRQ_CLEAR - Clear USBPHY1 wakeup interrupt holding register - */ -#define IOMUXC_LPSR_GPR_GPR34_USBPHY1_WAKEUP_IRQ_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_USBPHY1_WAKEUP_IRQ_CLEAR_MASK) -#define IOMUXC_LPSR_GPR_GPR34_USBPHY2_WAKEUP_IRQ_CLEAR_MASK (0x100U) -#define IOMUXC_LPSR_GPR_GPR34_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT (8U) -/*! USBPHY2_WAKEUP_IRQ_CLEAR - Clear USBPHY1 wakeup interrupt holding register - */ -#define IOMUXC_LPSR_GPR_GPR34_USBPHY2_WAKEUP_IRQ_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_USBPHY2_WAKEUP_IRQ_CLEAR_MASK) + #define IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_MASK (0x800U) #define IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_SHIFT (11U) /*! SEC_ERR_RESP - Security error response enable + * 0b0..OKEY response + * 0b1..SLVError (default) */ #define IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_MASK) + #define IOMUXC_LPSR_GPR_GPR34_DWP_MASK (0x30000000U) #define IOMUXC_LPSR_GPR_GPR34_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -53518,6 +62787,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_LPSR_GPR_GPR34_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_DWP_MASK) + #define IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -53531,136 +62801,215 @@ typedef struct { /*! @name GPR35 - GPR35 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_MASK (0x1U) #define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_SHIFT (0U) -/*! ADC1_IPG_DOZE - ADC2 doze mode +/*! ADC1_IPG_DOZE - ADC1 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_MASK (0x2U) #define IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_SHIFT (1U) -/*! ADC1_STOP_REQ - ADC2 stop request +/*! ADC1_STOP_REQ - ADC1 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_MASK (0x4U) #define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_SHIFT (2U) -/*! ADC1_IPG_STOP_MODE - ADC2 stop mode selection, cannot change when ADC2_STOP_REQ is asserted. +/*! ADC1_IPG_STOP_MODE - ADC1 stop mode selection. This bitfield cannot change when ADC1_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_MASK) + #define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_MASK (0x8U) #define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_SHIFT (3U) /*! ADC2_IPG_DOZE - ADC2 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_MASK (0x10U) #define IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_SHIFT (4U) /*! ADC2_STOP_REQ - ADC2 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_MASK (0x20U) #define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_SHIFT (5U) -/*! ADC2_IPG_STOP_MODE - ADC2 stop mode selection, cannot change when ADC2_STOP_REQ is asserted. +/*! ADC2_IPG_STOP_MODE - ADC2 stop mode selection. This bitfield cannot change when ADC2_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_MASK) + #define IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_MASK (0x40U) #define IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_SHIFT (6U) /*! CAAM_IPG_DOZE - CAN3 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_MASK (0x80U) #define IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_SHIFT (7U) /*! CAAM_STOP_REQ - CAAM stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_MASK (0x100U) #define IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_SHIFT (8U) /*! CAN1_IPG_DOZE - CAN1 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_MASK (0x200U) #define IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_SHIFT (9U) /*! CAN1_STOP_REQ - CAN1 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_MASK (0x400U) #define IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_SHIFT (10U) /*! CAN2_IPG_DOZE - CAN2 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_MASK (0x800U) #define IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_SHIFT (11U) /*! CAN2_STOP_REQ - CAN2 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_MASK (0x1000U) #define IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_SHIFT (12U) /*! CAN3_IPG_DOZE - CAN3 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_MASK (0x2000U) #define IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_SHIFT (13U) /*! CAN3_STOP_REQ - CAN3 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_MASK (0x8000U) #define IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_SHIFT (15U) /*! EDMA_STOP_REQ - EDMA stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_MASK (0x10000U) #define IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_SHIFT (16U) /*! EDMA_LPSR_STOP_REQ - EDMA_LPSR stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_MASK (0x20000U) #define IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_SHIFT (17U) /*! ENET_IPG_DOZE - ENET doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_MASK (0x40000U) #define IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_SHIFT (18U) /*! ENET_STOP_REQ - ENET stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_MASK (0x80000U) #define IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_SHIFT (19U) /*! ENET1G_IPG_DOZE - ENET1G doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_MASK (0x100000U) #define IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_SHIFT (20U) /*! ENET1G_STOP_REQ - ENET1G stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_MASK (0x200000U) #define IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_SHIFT (21U) /*! FLEXIO1_IPG_DOZE - FLEXIO2 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_MASK (0x400000U) #define IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_SHIFT (22U) /*! FLEXIO2_IPG_DOZE - FLEXIO2 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_MASK (0x800000U) #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_SHIFT (23U) /*! FLEXSPI1_IPG_DOZE - FLEXSPI1 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_MASK (0x1000000U) #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_SHIFT (24U) /*! FLEXSPI1_STOP_REQ - FLEXSPI1 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_MASK (0x2000000U) #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_SHIFT (25U) /*! FLEXSPI2_IPG_DOZE - FLEXSPI2 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_MASK (0x4000000U) #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_SHIFT (26U) /*! FLEXSPI2_STOP_REQ - FLEXSPI2 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR35_DWP_MASK (0x30000000U) #define IOMUXC_LPSR_GPR_GPR35_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -53670,6 +63019,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_LPSR_GPR_GPR35_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_DWP_MASK) + #define IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -53683,141 +63033,223 @@ typedef struct { /*! @name GPR36 - GPR36 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_MASK (0x1U) #define IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_SHIFT (0U) /*! GPT1_IPG_DOZE - GPT1 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_MASK (0x2U) #define IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_SHIFT (1U) /*! GPT2_IPG_DOZE - GPT2 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_MASK (0x4U) #define IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_SHIFT (2U) /*! GPT3_IPG_DOZE - GPT3 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_MASK (0x8U) #define IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_SHIFT (3U) /*! GPT4_IPG_DOZE - GPT4 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_MASK (0x10U) #define IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_SHIFT (4U) /*! GPT5_IPG_DOZE - GPT5 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_MASK (0x20U) #define IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_SHIFT (5U) /*! GPT6_IPG_DOZE - GPT6 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_MASK (0x40U) #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_SHIFT (6U) /*! LPI2C1_IPG_DOZE - LPI2C1 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_MASK (0x80U) #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_SHIFT (7U) /*! LPI2C1_STOP_REQ - LPI2C1 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_MASK (0x100U) #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_SHIFT (8U) -/*! LPI2C1_IPG_STOP_MODE - LPI2C1 stop mode selection, cannot change when LPI2C1_STOP_REQ is asserted. +/*! LPI2C1_IPG_STOP_MODE - LPI2C1 stop mode selection. This bitfield cannot change when LPI2C1_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_MASK) + #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_MASK (0x200U) #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_SHIFT (9U) /*! LPI2C2_IPG_DOZE - LPI2C2 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_MASK (0x400U) #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_SHIFT (10U) /*! LPI2C2_STOP_REQ - LPI2C2 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_MASK (0x800U) #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_SHIFT (11U) -/*! LPI2C2_IPG_STOP_MODE - LPI2C2 stop mode selection, cannot change when LPI2C2_STOP_REQ is asserted. +/*! LPI2C2_IPG_STOP_MODE - LPI2C2 stop mode selection. This bitfield cannot change when LPI2C2_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_MASK) + #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_MASK (0x1000U) #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_SHIFT (12U) /*! LPI2C3_IPG_DOZE - LPI2C3 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_MASK (0x2000U) #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_SHIFT (13U) /*! LPI2C3_STOP_REQ - LPI2C3 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_MASK (0x4000U) #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_SHIFT (14U) -/*! LPI2C3_IPG_STOP_MODE - LPI2C3 stop mode selection, cannot change when LPI2C3_STOP_REQ is asserted. +/*! LPI2C3_IPG_STOP_MODE - LPI2C3 stop mode selection. This bitfield cannot change when LPI2C3_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_MASK) + #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_MASK (0x8000U) #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_SHIFT (15U) /*! LPI2C4_IPG_DOZE - LPI2C4 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_MASK (0x10000U) #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_SHIFT (16U) /*! LPI2C4_STOP_REQ - LPI2C4 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_MASK (0x20000U) #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_SHIFT (17U) -/*! LPI2C4_IPG_STOP_MODE - LPI2C4 stop mode selection, cannot change when LPI2C4_STOP_REQ is asserted. +/*! LPI2C4_IPG_STOP_MODE - LPI2C4 stop mode selection. This bitfield cannot change when LPI2C4_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_MASK) + #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_MASK (0x40000U) #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_SHIFT (18U) /*! LPI2C5_IPG_DOZE - LPI2C5 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_MASK (0x80000U) #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_SHIFT (19U) /*! LPI2C5_STOP_REQ - LPI2C5 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_MASK (0x100000U) #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_SHIFT (20U) -/*! LPI2C5_IPG_STOP_MODE - LPI2C5 stop mode selection, cannot change when LPI2C5_STOP_REQ is asserted. +/*! LPI2C5_IPG_STOP_MODE - LPI2C5 stop mode selection. This bitfield cannot change when LPI2C5_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_MASK) + #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_MASK (0x200000U) #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_SHIFT (21U) /*! LPI2C6_IPG_DOZE - LPI2C6 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_MASK (0x400000U) #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_SHIFT (22U) /*! LPI2C6_STOP_REQ - LPI2C6 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_MASK (0x800000U) #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_SHIFT (23U) -/*! LPI2C6_IPG_STOP_MODE - LPI2C6 stop mode selection, cannot change when LPI2C6_STOP_REQ is asserted. +/*! LPI2C6_IPG_STOP_MODE - LPI2C6 stop mode selection. This bitfield cannot change when LPI2C6_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_MASK) + #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_MASK (0x1000000U) #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_SHIFT (24U) /*! LPSPI1_IPG_DOZE - LPSPI1 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_MASK (0x2000000U) #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_SHIFT (25U) /*! LPSPI1_STOP_REQ - LPSPI1 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_MASK (0x4000000U) #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_SHIFT (26U) -/*! LPSPI1_IPG_STOP_MODE - LPSPI1 stop mode selection, cannot change when LPSPI1_STOP_REQ is asserted. +/*! LPSPI1_IPG_STOP_MODE - LPSPI1 stop mode selection. This bitfield cannot change when LPSPI1_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_MASK) + #define IOMUXC_LPSR_GPR_GPR36_DWP_MASK (0x30000000U) #define IOMUXC_LPSR_GPR_GPR36_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -53827,6 +63259,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_LPSR_GPR_GPR36_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_DWP_MASK) + #define IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -53840,141 +63273,223 @@ typedef struct { /*! @name GPR37 - GPR37 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_MASK (0x1U) #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_SHIFT (0U) /*! LPSPI2_IPG_DOZE - LPSPI2 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_MASK (0x2U) #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_SHIFT (1U) /*! LPSPI2_STOP_REQ - LPSPI2 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_MASK (0x4U) #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_SHIFT (2U) -/*! LPSPI2_IPG_STOP_MODE - LPSPI2 stop mode selection, cannot change when LPSPI2_STOP_REQ is asserted. +/*! LPSPI2_IPG_STOP_MODE - LPSPI2 stop mode selection. This bitfield cannot change when LPSPI2_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_MASK) + #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_MASK (0x8U) #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_SHIFT (3U) /*! LPSPI3_IPG_DOZE - LPSPI3 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_MASK (0x10U) #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_SHIFT (4U) /*! LPSPI3_STOP_REQ - LPSPI3 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_MASK (0x20U) #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_SHIFT (5U) -/*! LPSPI3_IPG_STOP_MODE - LPSPI3 stop mode selection, cannot change when LPSPI3_STOP_REQ is asserted. +/*! LPSPI3_IPG_STOP_MODE - LPSPI3 stop mode selection. This bitfield cannot change when LPSPI3_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_MASK) + #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_MASK (0x40U) #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_SHIFT (6U) /*! LPSPI4_IPG_DOZE - LPSPI4 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_MASK (0x80U) #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_SHIFT (7U) /*! LPSPI4_STOP_REQ - LPSPI4 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_MASK (0x100U) #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_SHIFT (8U) -/*! LPSPI4_IPG_STOP_MODE - LPSPI4 stop mode selection, cannot change when LPSPI4_STOP_REQ is asserted. +/*! LPSPI4_IPG_STOP_MODE - LPSPI4 stop mode selection. This bitfield cannot change when LPSPI4_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_MASK) + #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_MASK (0x200U) #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_SHIFT (9U) /*! LPSPI5_IPG_DOZE - LPSPI5 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_MASK (0x400U) #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_SHIFT (10U) /*! LPSPI5_STOP_REQ - LPSPI5 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_MASK (0x800U) #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_SHIFT (11U) -/*! LPSPI5_IPG_STOP_MODE - LPSPI5 stop mode selection, cannot change when LPSPI5_STOP_REQ is asserted. +/*! LPSPI5_IPG_STOP_MODE - LPSPI5 stop mode selection. This bitfield cannot change when LPSPI5_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_MASK) + #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_MASK (0x1000U) #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_SHIFT (12U) /*! LPSPI6_IPG_DOZE - LPSPI6 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_MASK (0x2000U) #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_SHIFT (13U) /*! LPSPI6_STOP_REQ - LPSPI6 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_MASK (0x4000U) #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_SHIFT (14U) -/*! LPSPI6_IPG_STOP_MODE - LPSPI6 stop mode selection, cannot change when LPSPI6_STOP_REQ is asserted. +/*! LPSPI6_IPG_STOP_MODE - LPSPI6 stop mode selection. This bitfield cannot change when LPSPI6_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_MASK) + #define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_MASK (0x8000U) #define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_SHIFT (15U) /*! LPUART1_IPG_DOZE - LPUART1 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_MASK (0x10000U) #define IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_SHIFT (16U) /*! LPUART1_STOP_REQ - LPUART1 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_MASK (0x20000U) #define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_SHIFT (17U) -/*! LPUART1_IPG_STOP_MODE - LPUART1 stop mode selection, cannot change when LPUART1_STOP_REQ is asserted. +/*! LPUART1_IPG_STOP_MODE - LPUART1 stop mode selection. This bitfield cannot change when LPUART1_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_MASK) + #define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_MASK (0x40000U) #define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_SHIFT (18U) /*! LPUART2_IPG_DOZE - LPUART2 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_MASK (0x80000U) #define IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_SHIFT (19U) /*! LPUART2_STOP_REQ - LPUART2 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_MASK (0x100000U) #define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_SHIFT (20U) -/*! LPUART2_IPG_STOP_MODE - LPUART2 stop mode selection, cannot change when LPUART2_STOP_REQ is asserted. +/*! LPUART2_IPG_STOP_MODE - LPUART2 stop mode selection. This bitfield cannot change when LPUART2_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_MASK) + #define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_MASK (0x200000U) #define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_SHIFT (21U) /*! LPUART3_IPG_DOZE - LPUART3 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_MASK (0x400000U) #define IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_SHIFT (22U) /*! LPUART3_STOP_REQ - LPUART3 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_MASK (0x800000U) #define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_SHIFT (23U) -/*! LPUART3_IPG_STOP_MODE - LPUART3 stop mode selection, cannot change when LPUART3_STOP_REQ is asserted. +/*! LPUART3_IPG_STOP_MODE - LPUART3 stop mode selection. This bitfield cannot change when LPUART3_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_MASK) + #define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_MASK (0x1000000U) #define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_SHIFT (24U) /*! LPUART4_IPG_DOZE - LPUART4 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_MASK (0x2000000U) #define IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_SHIFT (25U) /*! LPUART4_STOP_REQ - LPUART4 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_MASK (0x4000000U) #define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_SHIFT (26U) -/*! LPUART4_IPG_STOP_MODE - LPUART4 stop mode selection, cannot change when LPUART4_STOP_REQ is asserted. +/*! LPUART4_IPG_STOP_MODE - LPUART4 stop mode selection. This bitfield cannot change when LPUART4_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_MASK) + #define IOMUXC_LPSR_GPR_GPR37_DWP_MASK (0x30000000U) #define IOMUXC_LPSR_GPR_GPR37_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -53984,6 +63499,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_LPSR_GPR_GPR37_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_DWP_MASK) + #define IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -53997,141 +63513,223 @@ typedef struct { /*! @name GPR38 - GPR38 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_MASK (0x1U) #define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_SHIFT (0U) /*! LPUART5_IPG_DOZE - LPUART5 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_MASK (0x2U) #define IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_SHIFT (1U) /*! LPUART5_STOP_REQ - LPUART5 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_MASK (0x4U) #define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_SHIFT (2U) -/*! LPUART5_IPG_STOP_MODE - LPUART5 stop mode selection, cannot change when LPUART5_STOP_REQ is asserted. +/*! LPUART5_IPG_STOP_MODE - LPUART5 stop mode selection. This bitfield cannot change when LPUART5_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_MASK) + #define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_MASK (0x8U) #define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_SHIFT (3U) /*! LPUART6_IPG_DOZE - LPUART6 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_MASK (0x10U) #define IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_SHIFT (4U) /*! LPUART6_STOP_REQ - LPUART6 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_MASK (0x20U) #define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_SHIFT (5U) -/*! LPUART6_IPG_STOP_MODE - LPUART6 stop mode selection, cannot change when LPUART6_STOP_REQ is asserted. +/*! LPUART6_IPG_STOP_MODE - LPUART6 stop mode selection. This bitfield cannot change when LPUART6_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_MASK) + #define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_MASK (0x40U) #define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_SHIFT (6U) /*! LPUART7_IPG_DOZE - LPUART7 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_MASK (0x80U) #define IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_SHIFT (7U) /*! LPUART7_STOP_REQ - LPUART7 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_MASK (0x100U) #define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_SHIFT (8U) -/*! LPUART7_IPG_STOP_MODE - LPUART7 stop mode selection, cannot change when LPUART7_STOP_REQ is asserted. +/*! LPUART7_IPG_STOP_MODE - LPUART7 stop mode selection. This bitfield cannot change when LPUART7_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_MASK) + #define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_MASK (0x200U) #define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_SHIFT (9U) /*! LPUART8_IPG_DOZE - LPUART8 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_MASK (0x400U) #define IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_SHIFT (10U) /*! LPUART8_STOP_REQ - LPUART8 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_MASK (0x800U) #define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_SHIFT (11U) -/*! LPUART8_IPG_STOP_MODE - LPUART8 stop mode selection, cannot change when LPUART8_STOP_REQ is asserted. +/*! LPUART8_IPG_STOP_MODE - LPUART8 stop mode selection. This bitfield cannot change when LPUART8_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_MASK) + #define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_MASK (0x1000U) #define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_SHIFT (12U) /*! LPUART9_IPG_DOZE - LPUART9 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_MASK (0x2000U) #define IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_SHIFT (13U) /*! LPUART9_STOP_REQ - LPUART9 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_MASK (0x4000U) #define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_SHIFT (14U) -/*! LPUART9_IPG_STOP_MODE - LPUART9 stop mode selection, cannot change when LPUART9_STOP_REQ is asserted. +/*! LPUART9_IPG_STOP_MODE - LPUART9 stop mode selection. This bitfield cannot change when LPUART9_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_MASK) + #define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_MASK (0x8000U) #define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_SHIFT (15U) /*! LPUART10_IPG_DOZE - LPUART10 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_MASK (0x10000U) #define IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_SHIFT (16U) /*! LPUART10_STOP_REQ - LPUART10 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_MASK (0x20000U) #define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_SHIFT (17U) -/*! LPUART10_IPG_STOP_MODE - LPUART10 stop mode selection, cannot change when LPUART10_STOP_REQ is asserted. +/*! LPUART10_IPG_STOP_MODE - LPUART10 stop mode selection. This bitfield cannot change when LPUART10_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_MASK) + #define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_MASK (0x40000U) #define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_SHIFT (18U) /*! LPUART11_IPG_DOZE - LPUART11 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_MASK (0x80000U) #define IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_SHIFT (19U) /*! LPUART11_STOP_REQ - LPUART11 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_MASK (0x100000U) #define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_SHIFT (20U) -/*! LPUART11_IPG_STOP_MODE - LPUART11 stop mode selection, cannot change when LPUART11_STOP_REQ is asserted. +/*! LPUART11_IPG_STOP_MODE - LPUART11 stop mode selection. This bitfield cannot change when LPUART11_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_MASK) + #define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_MASK (0x200000U) #define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_SHIFT (21U) /*! LPUART12_IPG_DOZE - LPUART12 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_MASK (0x400000U) #define IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_SHIFT (22U) /*! LPUART12_STOP_REQ - LPUART12 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_MASK (0x800000U) #define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_SHIFT (23U) -/*! LPUART12_IPG_STOP_MODE - LPUART12 stop mode selection, cannot change when LPUART12_STOP_REQ is asserted. +/*! LPUART12_IPG_STOP_MODE - LPUART12 stop mode selection. This bitfield cannot change when LPUART12_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_MASK) + #define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_MASK (0x1000000U) #define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_SHIFT (24U) /*! MIC_IPG_DOZE - MIC doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_MASK (0x2000000U) #define IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_SHIFT (25U) /*! MIC_STOP_REQ - MIC stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_MASK (0x4000000U) #define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_SHIFT (26U) -/*! MIC_IPG_STOP_MODE - MIC stop mode selection, cannot change when MIC_STOP_REQ is asserted. +/*! MIC_IPG_STOP_MODE - MIC stop mode selection. This bitfield cannot change when MIC_STOP_REQ is asserted. + * 0b0..This module is functional in Stop Mode + * 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'. */ #define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_MASK) + #define IOMUXC_LPSR_GPR_GPR38_DWP_MASK (0x30000000U) #define IOMUXC_LPSR_GPR_GPR38_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -54141,6 +63739,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_LPSR_GPR_GPR38_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_DWP_MASK) + #define IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -54154,91 +63753,143 @@ typedef struct { /*! @name GPR39 - GPR39 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_MASK (0x2U) #define IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_SHIFT (1U) /*! PIT1_STOP_REQ - PIT1 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_MASK (0x4U) #define IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_SHIFT (2U) /*! PIT2_STOP_REQ - PIT2 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_MASK (0x8U) #define IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_SHIFT (3U) /*! SEMC_STOP_REQ - SEMC stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_MASK (0x10U) #define IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_SHIFT (4U) /*! SIM1_IPG_DOZE - SIM1 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_MASK (0x20U) #define IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_SHIFT (5U) /*! SIM2_IPG_DOZE - SIM2 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_MASK (0x40U) #define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_SHIFT (6U) /*! SNVS_HP_IPG_DOZE - SNVS_HP doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_MASK (0x80U) #define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_SHIFT (7U) /*! SNVS_HP_STOP_REQ - SNVS_HP stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_MASK (0x100U) #define IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_SHIFT (8U) /*! WDOG1_IPG_DOZE - WDOG1 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_MASK (0x200U) #define IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_SHIFT (9U) /*! WDOG2_IPG_DOZE - WDOG2 doze mode + * 0b0..Not in doze mode + * 0b1..In doze mode */ #define IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_MASK) + #define IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_MASK (0x400U) #define IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_SHIFT (10U) /*! SAI1_STOP_REQ - SAI1 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_MASK (0x800U) #define IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_SHIFT (11U) /*! SAI2_STOP_REQ - SAI2 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_MASK (0x1000U) #define IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_SHIFT (12U) /*! SAI3_STOP_REQ - SAI3 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_MASK (0x2000U) #define IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_SHIFT (13U) /*! SAI4_STOP_REQ - SAI4 stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_MASK) + #define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_MASK (0x4000U) #define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_SHIFT (14U) /*! FLEXIO1_STOP_REQ_BUS - FLEXIO1 bus clock domain stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_MASK) + #define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_MASK (0x8000U) #define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_SHIFT (15U) /*! FLEXIO1_STOP_REQ_PER - FLEXIO1 peripheral clock domain stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_MASK) + #define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_MASK (0x10000U) #define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_SHIFT (16U) /*! FLEXIO2_STOP_REQ_BUS - FLEXIO2 bus clock domain stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_MASK) + #define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_MASK (0x20000U) #define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_SHIFT (17U) /*! FLEXIO2_STOP_REQ_PER - FLEXIO2 peripheral clock domain stop request + * 0b0..Stop request off + * 0b1..Stop request on */ #define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_MASK) + #define IOMUXC_LPSR_GPR_GPR39_DWP_MASK (0x30000000U) #define IOMUXC_LPSR_GPR_GPR39_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -54248,6 +63899,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_LPSR_GPR_GPR39_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_DWP_MASK) + #define IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -54261,161 +63913,193 @@ typedef struct { /*! @name GPR40 - GPR40 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_MASK (0x1U) #define IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_SHIFT (0U) /*! ADC1_STOP_ACK - ADC1 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_MASK (0x2U) #define IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_SHIFT (1U) /*! ADC2_STOP_ACK - ADC2 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_MASK (0x4U) #define IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_SHIFT (2U) /*! CAAM_STOP_ACK - CAAM stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_MASK (0x8U) #define IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_SHIFT (3U) /*! CAN1_STOP_ACK - CAN1 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_MASK (0x10U) #define IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_SHIFT (4U) /*! CAN2_STOP_ACK - CAN2 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_MASK (0x20U) #define IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_SHIFT (5U) /*! CAN3_STOP_ACK - CAN3 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_MASK (0x40U) #define IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_SHIFT (6U) /*! EDMA_STOP_ACK - EDMA stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_MASK (0x80U) #define IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_SHIFT (7U) /*! EDMA_LPSR_STOP_ACK - EDMA_LPSR stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_MASK (0x100U) #define IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_SHIFT (8U) /*! ENET_STOP_ACK - ENET stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_MASK (0x200U) #define IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_SHIFT (9U) /*! ENET1G_STOP_ACK - ENET1G stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_MASK (0x400U) #define IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_SHIFT (10U) /*! FLEXSPI1_STOP_ACK - FLEXSPI1 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_MASK (0x800U) #define IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_SHIFT (11U) /*! FLEXSPI2_STOP_ACK - FLEXSPI2 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_MASK (0x1000U) #define IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_SHIFT (12U) /*! LPI2C1_STOP_ACK - LPI2C1 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_MASK (0x2000U) #define IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_SHIFT (13U) /*! LPI2C2_STOP_ACK - LPI2C2 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_MASK (0x4000U) #define IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_SHIFT (14U) /*! LPI2C3_STOP_ACK - LPI2C3 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_MASK (0x8000U) #define IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_SHIFT (15U) /*! LPI2C4_STOP_ACK - LPI2C4 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_MASK (0x10000U) #define IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_SHIFT (16U) /*! LPI2C5_STOP_ACK - LPI2C5 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_MASK (0x20000U) #define IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_SHIFT (17U) /*! LPI2C6_STOP_ACK - LPI2C6 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_MASK (0x40000U) #define IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_SHIFT (18U) /*! LPSPI1_STOP_ACK - LPSPI1 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_MASK (0x80000U) #define IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_SHIFT (19U) /*! LPSPI2_STOP_ACK - LPSPI2 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_MASK (0x100000U) #define IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_SHIFT (20U) /*! LPSPI3_STOP_ACK - LPSPI3 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_MASK (0x200000U) #define IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_SHIFT (21U) /*! LPSPI4_STOP_ACK - LPSPI4 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_MASK (0x400000U) #define IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_SHIFT (22U) /*! LPSPI5_STOP_ACK - LPSPI5 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_MASK (0x800000U) #define IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_SHIFT (23U) /*! LPSPI6_STOP_ACK - LPSPI6 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_MASK (0x1000000U) #define IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_SHIFT (24U) /*! LPUART1_STOP_ACK - LPUART1 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_MASK (0x2000000U) #define IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_SHIFT (25U) /*! LPUART2_STOP_ACK - LPUART2 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_MASK (0x4000000U) #define IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_SHIFT (26U) /*! LPUART3_STOP_ACK - LPUART3 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_MASK (0x8000000U) #define IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_SHIFT (27U) /*! LPUART4_STOP_ACK - LPUART4 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_MASK (0x10000000U) #define IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_SHIFT (28U) /*! LPUART5_STOP_ACK - LPUART5 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_MASK (0x20000000U) #define IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_SHIFT (29U) /*! LPUART6_STOP_ACK - LPUART6 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_MASK (0x40000000U) #define IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_SHIFT (30U) /*! LPUART7_STOP_ACK - LPUART7 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_MASK (0x80000000U) #define IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_SHIFT (31U) /*! LPUART8_STOP_ACK - LPUART8 stop acknowledge @@ -54425,91 +64109,109 @@ typedef struct { /*! @name GPR41 - GPR41 General Purpose Register */ /*! @{ */ + #define IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_MASK (0x1U) #define IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_SHIFT (0U) /*! LPUART9_STOP_ACK - LPUART9 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_MASK (0x2U) #define IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_SHIFT (1U) /*! LPUART10_STOP_ACK - LPUART10 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_MASK (0x4U) #define IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_SHIFT (2U) /*! LPUART11_STOP_ACK - LPUART11 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_MASK (0x8U) #define IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_SHIFT (3U) /*! LPUART12_STOP_ACK - LPUART12 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_MASK (0x10U) #define IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_SHIFT (4U) /*! MIC_STOP_ACK - MIC stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_MASK (0x20U) #define IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_SHIFT (5U) /*! PIT1_STOP_ACK - PIT1 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_MASK (0x40U) #define IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_SHIFT (6U) /*! PIT2_STOP_ACK - PIT2 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_MASK (0x80U) #define IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_SHIFT (7U) /*! SEMC_STOP_ACK - SEMC stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_MASK (0x100U) #define IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_SHIFT (8U) /*! SNVS_HP_STOP_ACK - SNVS_HP stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_MASK (0x200U) #define IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_SHIFT (9U) /*! SAI1_STOP_ACK - SAI1 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_MASK (0x400U) #define IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_SHIFT (10U) /*! SAI2_STOP_ACK - SAI2 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_MASK (0x800U) #define IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_SHIFT (11U) /*! SAI3_STOP_ACK - SAI3 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_MASK (0x1000U) #define IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_SHIFT (12U) /*! SAI4_STOP_ACK - SAI4 stop acknowledge */ #define IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_MASK) + #define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_MASK (0x2000U) #define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_SHIFT (13U) /*! FLEXIO1_STOP_ACK_BUS - FLEXIO1 stop acknowledge of bus clock domain */ #define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_MASK) + #define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_MASK (0x4000U) #define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_SHIFT (14U) /*! FLEXIO1_STOP_ACK_PER - FLEXIO1 stop acknowledge of peripheral clock domain */ #define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_MASK) + #define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_MASK (0x8000U) #define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_SHIFT (15U) /*! FLEXIO2_STOP_ACK_BUS - FLEXIO2 stop acknowledge of bus clock domain */ #define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_MASK) + #define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_MASK (0x10000U) #define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_SHIFT (16U) /*! FLEXIO2_STOP_ACK_PER - FLEXIO2 stop acknowledge of peripheral clock domain */ #define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_MASK) + #define IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_MASK (0x1000000U) #define IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_SHIFT (24U) /*! ROM_READ_LOCKED - ROM read lock status bit @@ -54591,6 +64293,7 @@ typedef struct { /*! @name SW_MUX_CTL_PAD_WAKEUP_DIG - SW_MUX_CTL_PAD_WAKEUP_DIG SW MUX Control Register */ /*! @{ */ + #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_MASK (0x7U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_SHIFT (0U) /*! MUX_MODE - MUX Mode Select Field. @@ -54598,6 +64301,7 @@ typedef struct { * 0b111..Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: NMI_GLUE */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_MASK) + #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_MASK (0x10U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_SHIFT (4U) /*! SION - Software Input On Field. @@ -54609,6 +64313,7 @@ typedef struct { /*! @name SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG - SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG SW MUX Control Register */ /*! @{ */ + #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_MASK (0x7U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_SHIFT (0U) /*! MUX_MODE - MUX Mode Select Field. @@ -54616,6 +64321,7 @@ typedef struct { * 0b101..Select mux mode: ALT5 mux port: GPIO13_IO01 of instance: GPIO13 */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_MASK) + #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_MASK (0x10U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_SHIFT (4U) /*! SION - Software Input On Field. @@ -54627,6 +64333,7 @@ typedef struct { /*! @name SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG - SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG SW MUX Control Register */ /*! @{ */ + #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_MASK (0x7U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_SHIFT (0U) /*! MUX_MODE - MUX Mode Select Field. @@ -54634,6 +64341,7 @@ typedef struct { * 0b101..Select mux mode: ALT5 mux port: GPIO13_IO02 of instance: GPIO13 */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_MASK) + #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_MASK (0x10U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_SHIFT (4U) /*! SION - Software Input On Field. @@ -54645,6 +64353,7 @@ typedef struct { /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG SW MUX Control Register */ /*! @{ */ + #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_MASK (0x7U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_SHIFT (0U) /*! MUX_MODE - MUX Mode Select Field. @@ -54652,6 +64361,7 @@ typedef struct { * 0b101..Select mux mode: ALT5 mux port: GPIO13_IO03 of instance: GPIO13 */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_MASK) + #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_MASK (0x10U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_SHIFT (4U) /*! SION - Software Input On Field. @@ -54663,6 +64373,7 @@ typedef struct { /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG SW MUX Control Register */ /*! @{ */ + #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_MASK (0x7U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_SHIFT (0U) /*! MUX_MODE - MUX Mode Select Field. @@ -54670,6 +64381,7 @@ typedef struct { * 0b101..Select mux mode: ALT5 mux port: GPIO13_IO04 of instance: GPIO13 */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_MASK) + #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_MASK (0x10U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_SHIFT (4U) /*! SION - Software Input On Field. @@ -54681,6 +64393,7 @@ typedef struct { /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG SW MUX Control Register */ /*! @{ */ + #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_MASK (0x7U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_SHIFT (0U) /*! MUX_MODE - MUX Mode Select Field. @@ -54688,6 +64401,7 @@ typedef struct { * 0b101..Select mux mode: ALT5 mux port: GPIO13_IO05 of instance: GPIO13 */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_MASK) + #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_MASK (0x10U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_SHIFT (4U) /*! SION - Software Input On Field. @@ -54699,6 +64413,7 @@ typedef struct { /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG SW MUX Control Register */ /*! @{ */ + #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_MASK (0x7U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_SHIFT (0U) /*! MUX_MODE - MUX Mode Select Field. @@ -54706,6 +64421,7 @@ typedef struct { * 0b101..Select mux mode: ALT5 mux port: GPIO13_IO06 of instance: GPIO13 */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_MASK) + #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_MASK (0x10U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_SHIFT (4U) /*! SION - Software Input On Field. @@ -54717,6 +64433,7 @@ typedef struct { /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG SW MUX Control Register */ /*! @{ */ + #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_MASK (0x7U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_SHIFT (0U) /*! MUX_MODE - MUX Mode Select Field. @@ -54724,6 +64441,7 @@ typedef struct { * 0b101..Select mux mode: ALT5 mux port: GPIO13_IO07 of instance: GPIO13 */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_MASK) + #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_MASK (0x10U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_SHIFT (4U) /*! SION - Software Input On Field. @@ -54735,6 +64453,7 @@ typedef struct { /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG SW MUX Control Register */ /*! @{ */ + #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_MASK (0x7U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_SHIFT (0U) /*! MUX_MODE - MUX Mode Select Field. @@ -54742,6 +64461,7 @@ typedef struct { * 0b101..Select mux mode: ALT5 mux port: GPIO13_IO08 of instance: GPIO13 */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_MASK) + #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_MASK (0x10U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_SHIFT (4U) /*! SION - Software Input On Field. @@ -54753,6 +64473,7 @@ typedef struct { /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG SW MUX Control Register */ /*! @{ */ + #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_MASK (0x7U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_SHIFT (0U) /*! MUX_MODE - MUX Mode Select Field. @@ -54760,6 +64481,7 @@ typedef struct { * 0b101..Select mux mode: ALT5 mux port: GPIO13_IO09 of instance: GPIO13 */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_MASK) + #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_MASK (0x10U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_SHIFT (4U) /*! SION - Software Input On Field. @@ -54771,6 +64493,7 @@ typedef struct { /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG SW MUX Control Register */ /*! @{ */ + #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_MASK (0x7U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_SHIFT (0U) /*! MUX_MODE - MUX Mode Select Field. @@ -54778,6 +64501,7 @@ typedef struct { * 0b101..Select mux mode: ALT5 mux port: GPIO13_IO10 of instance: GPIO13 */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_MASK) + #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_MASK (0x10U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_SHIFT (4U) /*! SION - Software Input On Field. @@ -54789,6 +64513,7 @@ typedef struct { /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG SW MUX Control Register */ /*! @{ */ + #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_MASK (0x7U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_SHIFT (0U) /*! MUX_MODE - MUX Mode Select Field. @@ -54796,6 +64521,7 @@ typedef struct { * 0b101..Select mux mode: ALT5 mux port: GPIO13_IO11 of instance: GPIO13 */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_MASK) + #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_MASK (0x10U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_SHIFT (4U) /*! SION - Software Input On Field. @@ -54807,6 +64533,7 @@ typedef struct { /*! @name SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG SW MUX Control Register */ /*! @{ */ + #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_MASK (0x7U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_SHIFT (0U) /*! MUX_MODE - MUX Mode Select Field. @@ -54814,6 +64541,7 @@ typedef struct { * 0b101..Select mux mode: ALT5 mux port: GPIO13_IO12 of instance: GPIO13 */ #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_MASK) + #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_MASK (0x10U) #define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_SHIFT (4U) /*! SION - Software Input On Field. @@ -54825,6 +64553,7 @@ typedef struct { /*! @name SW_PAD_CTL_PAD_TEST_MODE_DIG - SW_PAD_CTL_PAD_TEST_MODE_DIG SW PAD Control Register */ /*! @{ */ + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_SHIFT (0U) /*! SRE - Slew Rate Field @@ -54832,6 +64561,7 @@ typedef struct { * 0b1..Fast Slew Rate */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_MASK (0x2U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_SHIFT (1U) /*! DSE - Drive Strength Field @@ -54839,13 +64569,15 @@ typedef struct { * 0b1..high driver */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_MASK (0x4U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_SHIFT (2U) /*! PUE - Pull / Keep Select Field - * 0b0..Keeper - * 0b1..Pull + * 0b0..Pull Disable + * 0b1..Pull Enable */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_MASK (0x8U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_SHIFT (3U) /*! PUS - Pull Up / Down Config. Field @@ -54853,6 +64585,7 @@ typedef struct { * 0b1..Weak pull up */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_MASK (0x30000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -54862,6 +64595,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -54875,6 +64609,7 @@ typedef struct { /*! @name SW_PAD_CTL_PAD_POR_B_DIG - SW_PAD_CTL_PAD_POR_B_DIG SW PAD Control Register */ /*! @{ */ + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_SHIFT (0U) /*! SRE - Slew Rate Field @@ -54882,6 +64617,7 @@ typedef struct { * 0b1..Fast Slew Rate */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_MASK (0x2U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_SHIFT (1U) /*! DSE - Drive Strength Field @@ -54889,13 +64625,15 @@ typedef struct { * 0b1..high driver */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_MASK (0x4U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_SHIFT (2U) /*! PUE - Pull / Keep Select Field - * 0b0..Keeper - * 0b1..Pull + * 0b0..Pull Disable + * 0b1..Pull Enable */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_MASK (0x8U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_SHIFT (3U) /*! PUS - Pull Up / Down Config. Field @@ -54903,6 +64641,7 @@ typedef struct { * 0b1..Weak pull up */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_MASK (0x30000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -54912,6 +64651,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -54925,6 +64665,7 @@ typedef struct { /*! @name SW_PAD_CTL_PAD_ONOFF_DIG - SW_PAD_CTL_PAD_ONOFF_DIG SW PAD Control Register */ /*! @{ */ + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_SHIFT (0U) /*! SRE - Slew Rate Field @@ -54932,6 +64673,7 @@ typedef struct { * 0b1..Fast Slew Rate */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_MASK (0x2U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_SHIFT (1U) /*! DSE - Drive Strength Field @@ -54939,13 +64681,15 @@ typedef struct { * 0b1..high driver */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_MASK (0x4U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_SHIFT (2U) /*! PUE - Pull / Keep Select Field - * 0b0..Keeper - * 0b1..Pull + * 0b0..Pull Disable + * 0b1..Pull Enable */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_MASK (0x8U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_SHIFT (3U) /*! PUS - Pull Up / Down Config. Field @@ -54953,6 +64697,7 @@ typedef struct { * 0b1..Weak pull up */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_MASK (0x30000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -54962,6 +64707,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -54975,6 +64721,7 @@ typedef struct { /*! @name SW_PAD_CTL_PAD_WAKEUP_DIG - SW_PAD_CTL_PAD_WAKEUP_DIG SW PAD Control Register */ /*! @{ */ + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_SHIFT (0U) /*! SRE - Slew Rate Field @@ -54982,6 +64729,7 @@ typedef struct { * 0b1..Fast Slew Rate */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_MASK (0x2U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_SHIFT (1U) /*! DSE - Drive Strength Field @@ -54989,13 +64737,15 @@ typedef struct { * 0b1..high driver */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_MASK (0x4U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_SHIFT (2U) /*! PUE - Pull / Keep Select Field - * 0b0..Keeper - * 0b1..Pull + * 0b0..Pull Disable + * 0b1..Pull Enable */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_MASK (0x8U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_SHIFT (3U) /*! PUS - Pull Up / Down Config. Field @@ -55003,6 +64753,7 @@ typedef struct { * 0b1..Weak pull up */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_MASK (0x40U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_SHIFT (6U) /*! ODE_SNVS - Open Drain SNVS Field @@ -55010,6 +64761,7 @@ typedef struct { * 0b1..Enabled */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_MASK (0x30000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -55019,6 +64771,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -55032,6 +64785,7 @@ typedef struct { /*! @name SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG - SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG SW PAD Control Register */ /*! @{ */ + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_SHIFT (0U) /*! SRE - Slew Rate Field @@ -55039,6 +64793,7 @@ typedef struct { * 0b1..Fast Slew Rate */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_MASK (0x2U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_SHIFT (1U) /*! DSE - Drive Strength Field @@ -55046,13 +64801,15 @@ typedef struct { * 0b1..high driver */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_MASK (0x4U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_SHIFT (2U) /*! PUE - Pull / Keep Select Field - * 0b0..Keeper - * 0b1..Pull + * 0b0..Pull Disable + * 0b1..Pull Enable */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_MASK (0x8U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_SHIFT (3U) /*! PUS - Pull Up / Down Config. Field @@ -55060,6 +64817,7 @@ typedef struct { * 0b1..Weak pull up */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_MASK (0x40U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_SHIFT (6U) /*! ODE_SNVS - Open Drain SNVS Field @@ -55067,6 +64825,7 @@ typedef struct { * 0b1..Enabled */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_MASK (0x30000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -55076,6 +64835,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -55089,6 +64849,7 @@ typedef struct { /*! @name SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG - SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG SW PAD Control Register */ /*! @{ */ + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_SHIFT (0U) /*! SRE - Slew Rate Field @@ -55096,6 +64857,7 @@ typedef struct { * 0b1..Fast Slew Rate */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_MASK (0x2U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_SHIFT (1U) /*! DSE - Drive Strength Field @@ -55103,13 +64865,15 @@ typedef struct { * 0b1..high driver */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_MASK (0x4U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_SHIFT (2U) /*! PUE - Pull / Keep Select Field - * 0b0..Keeper - * 0b1..Pull + * 0b0..Pull Disable + * 0b1..Pull Enable */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_MASK (0x8U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_SHIFT (3U) /*! PUS - Pull Up / Down Config. Field @@ -55117,6 +64881,7 @@ typedef struct { * 0b1..Weak pull up */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_MASK (0x40U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_SHIFT (6U) /*! ODE_SNVS - Open Drain SNVS Field @@ -55124,6 +64889,7 @@ typedef struct { * 0b1..Enabled */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_MASK (0x30000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -55133,6 +64899,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -55146,6 +64913,7 @@ typedef struct { /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG SW PAD Control Register */ /*! @{ */ + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_SHIFT (0U) /*! SRE - Slew Rate Field @@ -55153,6 +64921,7 @@ typedef struct { * 0b1..Fast Slew Rate */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_MASK (0x2U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_SHIFT (1U) /*! DSE - Drive Strength Field @@ -55160,13 +64929,15 @@ typedef struct { * 0b1..high driver */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_MASK (0x4U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_SHIFT (2U) /*! PUE - Pull / Keep Select Field - * 0b0..Keeper - * 0b1..Pull + * 0b0..Pull Disable + * 0b1..Pull Enable */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_MASK (0x8U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_SHIFT (3U) /*! PUS - Pull Up / Down Config. Field @@ -55174,6 +64945,7 @@ typedef struct { * 0b1..Weak pull up */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_MASK (0x40U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_SHIFT (6U) /*! ODE_SNVS - Open Drain SNVS Field @@ -55181,6 +64953,7 @@ typedef struct { * 0b1..Enabled */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_MASK (0x30000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -55190,6 +64963,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -55203,6 +64977,7 @@ typedef struct { /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG SW PAD Control Register */ /*! @{ */ + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_SHIFT (0U) /*! SRE - Slew Rate Field @@ -55210,6 +64985,7 @@ typedef struct { * 0b1..Fast Slew Rate */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_MASK (0x2U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_SHIFT (1U) /*! DSE - Drive Strength Field @@ -55217,13 +64993,15 @@ typedef struct { * 0b1..high driver */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_MASK (0x4U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_SHIFT (2U) /*! PUE - Pull / Keep Select Field - * 0b0..Keeper - * 0b1..Pull + * 0b0..Pull Disable + * 0b1..Pull Enable */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_MASK (0x8U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_SHIFT (3U) /*! PUS - Pull Up / Down Config. Field @@ -55231,6 +65009,7 @@ typedef struct { * 0b1..Weak pull up */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_MASK (0x40U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_SHIFT (6U) /*! ODE_SNVS - Open Drain SNVS Field @@ -55238,6 +65017,7 @@ typedef struct { * 0b1..Enabled */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_MASK (0x30000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -55247,6 +65027,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -55260,6 +65041,7 @@ typedef struct { /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG SW PAD Control Register */ /*! @{ */ + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_SHIFT (0U) /*! SRE - Slew Rate Field @@ -55267,6 +65049,7 @@ typedef struct { * 0b1..Fast Slew Rate */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_MASK (0x2U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_SHIFT (1U) /*! DSE - Drive Strength Field @@ -55274,13 +65057,15 @@ typedef struct { * 0b1..high driver */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_MASK (0x4U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_SHIFT (2U) /*! PUE - Pull / Keep Select Field - * 0b0..Keeper - * 0b1..Pull + * 0b0..Pull Disable + * 0b1..Pull Enable */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_MASK (0x8U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_SHIFT (3U) /*! PUS - Pull Up / Down Config. Field @@ -55288,6 +65073,7 @@ typedef struct { * 0b1..Weak pull up */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_MASK (0x40U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_SHIFT (6U) /*! ODE_SNVS - Open Drain SNVS Field @@ -55295,6 +65081,7 @@ typedef struct { * 0b1..Enabled */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_MASK (0x30000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -55304,6 +65091,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -55317,6 +65105,7 @@ typedef struct { /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG SW PAD Control Register */ /*! @{ */ + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_SHIFT (0U) /*! SRE - Slew Rate Field @@ -55324,6 +65113,7 @@ typedef struct { * 0b1..Fast Slew Rate */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_MASK (0x2U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_SHIFT (1U) /*! DSE - Drive Strength Field @@ -55331,13 +65121,15 @@ typedef struct { * 0b1..high driver */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_MASK (0x4U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_SHIFT (2U) /*! PUE - Pull / Keep Select Field - * 0b0..Keeper - * 0b1..Pull + * 0b0..Pull Disable + * 0b1..Pull Enable */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_MASK (0x8U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_SHIFT (3U) /*! PUS - Pull Up / Down Config. Field @@ -55345,6 +65137,7 @@ typedef struct { * 0b1..Weak pull up */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_MASK (0x40U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_SHIFT (6U) /*! ODE_SNVS - Open Drain SNVS Field @@ -55352,6 +65145,7 @@ typedef struct { * 0b1..Enabled */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_MASK (0x30000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -55361,6 +65155,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -55374,6 +65169,7 @@ typedef struct { /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG SW PAD Control Register */ /*! @{ */ + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_SHIFT (0U) /*! SRE - Slew Rate Field @@ -55381,6 +65177,7 @@ typedef struct { * 0b1..Fast Slew Rate */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_MASK (0x2U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_SHIFT (1U) /*! DSE - Drive Strength Field @@ -55388,13 +65185,15 @@ typedef struct { * 0b1..high driver */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_MASK (0x4U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_SHIFT (2U) /*! PUE - Pull / Keep Select Field - * 0b0..Keeper - * 0b1..Pull + * 0b0..Pull Disable + * 0b1..Pull Enable */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_MASK (0x8U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_SHIFT (3U) /*! PUS - Pull Up / Down Config. Field @@ -55402,6 +65201,7 @@ typedef struct { * 0b1..Weak pull up */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_MASK (0x40U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_SHIFT (6U) /*! ODE_SNVS - Open Drain SNVS Field @@ -55409,6 +65209,7 @@ typedef struct { * 0b1..Enabled */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_MASK (0x30000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -55418,6 +65219,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -55431,6 +65233,7 @@ typedef struct { /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG SW PAD Control Register */ /*! @{ */ + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_SHIFT (0U) /*! SRE - Slew Rate Field @@ -55438,6 +65241,7 @@ typedef struct { * 0b1..Fast Slew Rate */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_MASK (0x2U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_SHIFT (1U) /*! DSE - Drive Strength Field @@ -55445,13 +65249,15 @@ typedef struct { * 0b1..high driver */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_MASK (0x4U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_SHIFT (2U) /*! PUE - Pull / Keep Select Field - * 0b0..Keeper - * 0b1..Pull + * 0b0..Pull Disable + * 0b1..Pull Enable */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_MASK (0x8U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_SHIFT (3U) /*! PUS - Pull Up / Down Config. Field @@ -55459,6 +65265,7 @@ typedef struct { * 0b1..Weak pull up */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_MASK (0x40U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_SHIFT (6U) /*! ODE_SNVS - Open Drain SNVS Field @@ -55466,6 +65273,7 @@ typedef struct { * 0b1..Enabled */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_MASK (0x30000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -55475,6 +65283,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -55488,6 +65297,7 @@ typedef struct { /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG SW PAD Control Register */ /*! @{ */ + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_SHIFT (0U) /*! SRE - Slew Rate Field @@ -55495,6 +65305,7 @@ typedef struct { * 0b1..Fast Slew Rate */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_MASK (0x2U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_SHIFT (1U) /*! DSE - Drive Strength Field @@ -55502,13 +65313,15 @@ typedef struct { * 0b1..high driver */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_MASK (0x4U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_SHIFT (2U) /*! PUE - Pull / Keep Select Field - * 0b0..Keeper - * 0b1..Pull + * 0b0..Pull Disable + * 0b1..Pull Enable */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_MASK (0x8U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_SHIFT (3U) /*! PUS - Pull Up / Down Config. Field @@ -55516,6 +65329,7 @@ typedef struct { * 0b1..Weak pull up */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_MASK (0x40U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_SHIFT (6U) /*! ODE_SNVS - Open Drain SNVS Field @@ -55523,6 +65337,7 @@ typedef struct { * 0b1..Enabled */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_MASK (0x30000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -55532,6 +65347,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -55545,6 +65361,7 @@ typedef struct { /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG SW PAD Control Register */ /*! @{ */ + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_SHIFT (0U) /*! SRE - Slew Rate Field @@ -55552,6 +65369,7 @@ typedef struct { * 0b1..Fast Slew Rate */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_MASK (0x2U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_SHIFT (1U) /*! DSE - Drive Strength Field @@ -55559,13 +65377,15 @@ typedef struct { * 0b1..high driver */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_MASK (0x4U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_SHIFT (2U) /*! PUE - Pull / Keep Select Field - * 0b0..Keeper - * 0b1..Pull + * 0b0..Pull Disable + * 0b1..Pull Enable */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_MASK (0x8U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_SHIFT (3U) /*! PUS - Pull Up / Down Config. Field @@ -55573,6 +65393,7 @@ typedef struct { * 0b1..Weak pull up */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_MASK (0x40U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_SHIFT (6U) /*! ODE_SNVS - Open Drain SNVS Field @@ -55580,6 +65401,7 @@ typedef struct { * 0b1..Enabled */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_MASK (0x30000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -55589,6 +65411,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -55602,6 +65425,7 @@ typedef struct { /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG SW PAD Control Register */ /*! @{ */ + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_SHIFT (0U) /*! SRE - Slew Rate Field @@ -55609,6 +65433,7 @@ typedef struct { * 0b1..Fast Slew Rate */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_MASK (0x2U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_SHIFT (1U) /*! DSE - Drive Strength Field @@ -55616,13 +65441,15 @@ typedef struct { * 0b1..high driver */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_MASK (0x4U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_SHIFT (2U) /*! PUE - Pull / Keep Select Field - * 0b0..Keeper - * 0b1..Pull + * 0b0..Pull Disable + * 0b1..Pull Enable */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_MASK (0x8U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_SHIFT (3U) /*! PUS - Pull Up / Down Config. Field @@ -55630,6 +65457,7 @@ typedef struct { * 0b1..Weak pull up */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_MASK (0x40U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_SHIFT (6U) /*! ODE_SNVS - Open Drain SNVS Field @@ -55637,6 +65465,7 @@ typedef struct { * 0b1..Enabled */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_MASK (0x30000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -55646,6 +65475,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -55659,6 +65489,7 @@ typedef struct { /*! @name SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG SW PAD Control Register */ /*! @{ */ + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_MASK (0x1U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_SHIFT (0U) /*! SRE - Slew Rate Field @@ -55666,6 +65497,7 @@ typedef struct { * 0b1..Fast Slew Rate */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_MASK (0x2U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_SHIFT (1U) /*! DSE - Drive Strength Field @@ -55673,13 +65505,15 @@ typedef struct { * 0b1..high driver */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_MASK (0x4U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_SHIFT (2U) /*! PUE - Pull / Keep Select Field - * 0b0..Keeper - * 0b1..Pull + * 0b0..Pull Disable + * 0b1..Pull Enable */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_MASK (0x8U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_SHIFT (3U) /*! PUS - Pull Up / Down Config. Field @@ -55687,6 +65521,7 @@ typedef struct { * 0b1..Weak pull up */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_MASK (0x40U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_SHIFT (6U) /*! ODE_SNVS - Open Drain SNVS Field @@ -55694,6 +65529,7 @@ typedef struct { * 0b1..Enabled */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_MASK (0x30000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_SHIFT (28U) /*! DWP - Domain write protection @@ -55703,6 +65539,7 @@ typedef struct { * 0b11..Both cores are forbidden */ #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_MASK) + #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_MASK (0xC0000000U) #define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_SHIFT (30U) /*! DWP_LOCK - Domain write protection lock @@ -55746,38 +65583,7 @@ typedef struct { /** IOMUXC_SNVS_GPR - Register Layout Typedef */ typedef struct { - __IO uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */ - __IO uint32_t GPR1; /**< GPR1 General Purpose Register, offset: 0x4 */ - __IO uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */ - __IO uint32_t GPR3; /**< GPR3 General Purpose Register, offset: 0xC */ - __IO uint32_t GPR4; /**< GPR4 General Purpose Register, offset: 0x10 */ - __IO uint32_t GPR5; /**< GPR5 General Purpose Register, offset: 0x14 */ - __IO uint32_t GPR6; /**< GPR6 General Purpose Register, offset: 0x18 */ - __IO uint32_t GPR7; /**< GPR7 General Purpose Register, offset: 0x1C */ - __IO uint32_t GPR8; /**< GPR8 General Purpose Register, offset: 0x20 */ - __IO uint32_t GPR9; /**< GPR9 General Purpose Register, offset: 0x24 */ - __IO uint32_t GPR10; /**< GPR10 General Purpose Register, offset: 0x28 */ - __IO uint32_t GPR11; /**< GPR11 General Purpose Register, offset: 0x2C */ - __IO uint32_t GPR12; /**< GPR12 General Purpose Register, offset: 0x30 */ - __IO uint32_t GPR13; /**< GPR13 General Purpose Register, offset: 0x34 */ - __IO uint32_t GPR14; /**< GPR14 General Purpose Register, offset: 0x38 */ - __IO uint32_t GPR15; /**< GPR15 General Purpose Register, offset: 0x3C */ - __IO uint32_t GPR16; /**< GPR16 General Purpose Register, offset: 0x40 */ - __IO uint32_t GPR17; /**< GPR17 General Purpose Register, offset: 0x44 */ - __IO uint32_t GPR18; /**< GPR18 General Purpose Register, offset: 0x48 */ - __IO uint32_t GPR19; /**< GPR19 General Purpose Register, offset: 0x4C */ - __IO uint32_t GPR20; /**< GPR20 General Purpose Register, offset: 0x50 */ - __IO uint32_t GPR21; /**< GPR21 General Purpose Register, offset: 0x54 */ - __IO uint32_t GPR22; /**< GPR22 General Purpose Register, offset: 0x58 */ - __IO uint32_t GPR23; /**< GPR23 General Purpose Register, offset: 0x5C */ - __IO uint32_t GPR24; /**< GPR24 General Purpose Register, offset: 0x60 */ - __IO uint32_t GPR25; /**< GPR25 General Purpose Register, offset: 0x64 */ - __IO uint32_t GPR26; /**< GPR26 General Purpose Register, offset: 0x68 */ - __IO uint32_t GPR27; /**< GPR27 General Purpose Register, offset: 0x6C */ - __IO uint32_t GPR28; /**< GPR28 General Purpose Register, offset: 0x70 */ - __IO uint32_t GPR29; /**< GPR29 General Purpose Register, offset: 0x74 */ - __IO uint32_t GPR30; /**< GPR30 General Purpose Register, offset: 0x78 */ - __IO uint32_t GPR31; /**< GPR31 General Purpose Register, offset: 0x7C */ + __IO uint32_t GPR[32]; /**< GPR0 General Purpose Register, array offset: 0x0, array step: 0x4 */ __IO uint32_t GPR32; /**< GPR32 General Purpose Register, offset: 0x80 */ __IO uint32_t GPR33; /**< GPR33 General Purpose Register, offset: 0x84 */ __IO uint32_t GPR34; /**< GPR34 General Purpose Register, offset: 0x88 */ @@ -55795,301 +65601,28 @@ typedef struct { * @{ */ -/*! @name GPR0 - GPR0 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR0_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR0_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR0_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR0_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR0_GPR_MASK) -/*! @} */ - -/*! @name GPR1 - GPR1 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR1_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR1_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR1_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR1_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR1_GPR_MASK) -/*! @} */ - -/*! @name GPR2 - GPR2 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR2_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR2_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR2_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR2_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR2_GPR_MASK) -/*! @} */ - -/*! @name GPR3 - GPR3 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR3_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR3_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR3_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR3_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR3_GPR_MASK) -/*! @} */ - -/*! @name GPR4 - GPR4 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR4_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR4_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR4_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR4_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR4_GPR_MASK) -/*! @} */ - -/*! @name GPR5 - GPR5 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR5_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR5_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR5_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR5_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR5_GPR_MASK) -/*! @} */ - -/*! @name GPR6 - GPR6 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR6_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR6_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR6_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR6_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR6_GPR_MASK) -/*! @} */ - -/*! @name GPR7 - GPR7 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR7_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR7_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR7_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR7_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR7_GPR_MASK) -/*! @} */ - -/*! @name GPR8 - GPR8 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR8_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR8_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR8_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR8_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR8_GPR_MASK) -/*! @} */ - -/*! @name GPR9 - GPR9 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR9_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR9_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR9_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR9_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR9_GPR_MASK) -/*! @} */ - -/*! @name GPR10 - GPR10 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR10_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR10_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR10_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR10_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR10_GPR_MASK) -/*! @} */ - -/*! @name GPR11 - GPR11 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR11_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR11_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR11_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR11_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR11_GPR_MASK) -/*! @} */ - -/*! @name GPR12 - GPR12 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR12_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR12_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR12_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR12_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR12_GPR_MASK) -/*! @} */ - -/*! @name GPR13 - GPR13 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR13_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR13_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR13_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR13_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR13_GPR_MASK) -/*! @} */ - -/*! @name GPR14 - GPR14 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR14_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR14_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR14_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR14_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR14_GPR_MASK) -/*! @} */ - -/*! @name GPR15 - GPR15 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR15_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR15_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR15_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR15_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR15_GPR_MASK) -/*! @} */ - -/*! @name GPR16 - GPR16 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR16_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR16_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR16_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR16_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR16_GPR_MASK) -/*! @} */ - -/*! @name GPR17 - GPR17 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR17_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR17_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR17_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR17_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR17_GPR_MASK) -/*! @} */ - -/*! @name GPR18 - GPR18 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR18_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR18_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR18_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR18_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR18_GPR_MASK) -/*! @} */ - -/*! @name GPR19 - GPR19 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR19_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR19_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR19_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR19_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR19_GPR_MASK) -/*! @} */ - -/*! @name GPR20 - GPR20 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR20_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR20_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR20_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR20_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR20_GPR_MASK) -/*! @} */ - -/*! @name GPR21 - GPR21 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR21_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR21_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR21_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR21_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR21_GPR_MASK) -/*! @} */ - -/*! @name GPR22 - GPR22 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR22_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR22_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR22_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR22_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR22_GPR_MASK) -/*! @} */ - -/*! @name GPR23 - GPR23 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR23_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR23_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR23_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR23_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR23_GPR_MASK) -/*! @} */ - -/*! @name GPR24 - GPR24 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR24_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR24_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR24_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR24_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR24_GPR_MASK) -/*! @} */ - -/*! @name GPR25 - GPR25 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR25_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR25_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR25_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR25_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR25_GPR_MASK) -/*! @} */ - -/*! @name GPR26 - GPR26 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR26_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR26_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR26_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR26_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR26_GPR_MASK) -/*! @} */ - -/*! @name GPR27 - GPR27 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR27_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR27_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR27_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR27_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR27_GPR_MASK) -/*! @} */ - -/*! @name GPR28 - GPR28 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR28_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR28_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR28_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR28_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR28_GPR_MASK) -/*! @} */ - -/*! @name GPR29 - GPR29 General Purpose Register */ +/*! @name GPR - GPR0 General Purpose Register */ /*! @{ */ -#define IOMUXC_SNVS_GPR_GPR29_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR29_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR29_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR29_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR29_GPR_MASK) -/*! @} */ -/*! @name GPR30 - GPR30 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR30_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR30_GPR_SHIFT (0U) +#define IOMUXC_SNVS_GPR_GPR_GPR_MASK (0xFFFFFFFFU) +#define IOMUXC_SNVS_GPR_GPR_GPR_SHIFT (0U) /*! GPR - General purpose bits */ -#define IOMUXC_SNVS_GPR_GPR30_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR30_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR30_GPR_MASK) +#define IOMUXC_SNVS_GPR_GPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR_GPR_MASK) /*! @} */ -/*! @name GPR31 - GPR31 General Purpose Register */ -/*! @{ */ -#define IOMUXC_SNVS_GPR_GPR31_GPR_MASK (0xFFFFFFFFU) -#define IOMUXC_SNVS_GPR_GPR31_GPR_SHIFT (0U) -/*! GPR - General purpose bits - */ -#define IOMUXC_SNVS_GPR_GPR31_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR31_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR31_GPR_MASK) -/*! @} */ +/* The count of IOMUXC_SNVS_GPR_GPR */ +#define IOMUXC_SNVS_GPR_GPR_COUNT (32U) /*! @name GPR32 - GPR32 General Purpose Register */ /*! @{ */ -#define IOMUXC_SNVS_GPR_GPR32_GPR_MASK (0xFFFFU) -#define IOMUXC_SNVS_GPR_GPR32_GPR_SHIFT (0U) + +#define IOMUXC_SNVS_GPR_GPR32_GPR_MASK (0xFFFEU) +#define IOMUXC_SNVS_GPR_GPR32_GPR_SHIFT (1U) /*! GPR - General purpose bits */ #define IOMUXC_SNVS_GPR_GPR32_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_GPR_MASK) + #define IOMUXC_SNVS_GPR_GPR32_LOCK_MASK (0xFFFF0000U) #define IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT (16U) /*! LOCK - Lock the write to bit 15:0 @@ -56099,31 +65632,47 @@ typedef struct { /*! @name GPR33 - GPR33 General Purpose Register */ /*! @{ */ + #define IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_MASK (0x2U) #define IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_SHIFT (1U) /*! DCDC_STATUS_CAPT_CLR - DCDC captured status clear + * 0b0..No change + * 0b1..Clear the 3 bits of DCDC captured status: DCDC_OVER_VOL, DCDC_OVER_CUR, and DCDC_IN_LOW_VOL */ #define IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_MASK) + #define IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_MASK (0x4U) #define IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_SHIFT (2U) /*! SNVS_BYPASS_EN - SNVS LDO_SNVS_ANA bypass enable + * 0b1..Enable bypass + * 0b0..Disable bypass */ #define IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_MASK) + #define IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_MASK (0x10000U) #define IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_SHIFT (16U) /*! DCDC_IN_LOW_VOL - DCDC_IN low voltage detect + * 0b1..Voltage on DCDC_IN is lower than 2.6V + * 0b0..Voltage on DCDC_IN is higher than 2.6V */ #define IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_MASK) + #define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_MASK (0x20000U) #define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_SHIFT (17U) /*! DCDC_OVER_CUR - DCDC output over current alert + * 0b1..Overcurrent on DCDC output + * 0b0..No Overcurrent on DCDC output */ #define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_MASK) + #define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_MASK (0x40000U) #define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_SHIFT (18U) /*! DCDC_OVER_VOL - DCDC output over voltage alert + * 0b1..Overvoltage on DCDC VDDLP0 or VDDLP8 output + * 0b0..No Overvoltage on DCDC VDDLP0 or VDDLP8 output */ #define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_MASK) + #define IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_MASK (0x80000U) #define IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_SHIFT (19U) /*! DCDC_STS_DC_OK - DCDC status OK @@ -56131,55 +65680,83 @@ typedef struct { * 0b1..DCDC already settled */ #define IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_MASK) + #define IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_MASK (0x100000U) #define IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_SHIFT (20U) /*! SNVS_XTAL_CLK_OK - 32K OSC ok flag + * 0b1..32K oscillator is stable into normal operation + * 0b0..32K oscillator is NOT stable into normal operation */ #define IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_MASK) /*! @} */ /*! @name GPR34 - GPR34 General Purpose Register */ /*! @{ */ + #define IOMUXC_SNVS_GPR_GPR34_LOCK_MASK (0x1U) #define IOMUXC_SNVS_GPR_GPR34_LOCK_SHIFT (0U) /*! LOCK - Lock the write to bit 31:1 + * 0b0..Write access is not blocked + * 0b1..Write access is blocked */ #define IOMUXC_SNVS_GPR_GPR34_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_LOCK_MASK) + #define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_MASK (0x2U) #define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_SHIFT (1U) /*! SNVS_CORE_VOLT_DET_TRIM_SEL - SNVS core voltage detect trim select + * 0b0..The trimming codes are selected from eFuse + * 0b1..The trimming codes of core voltage detectors used to change the voltage falling trip point are selected from SNVS_CORE_VOLT_DET_TRIM */ #define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_MASK) + #define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_MASK (0xCU) #define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SHIFT (2U) /*! SNVS_CORE_VOLT_DET_TRIM - SNVS core voltage detect trim */ #define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_MASK) + #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_MASK (0x80U) #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_SHIFT (7U) /*! SNVS_CLK_DET_TRIM_SEL - SNVS clock detect trim select + * 0b0..The trimming codes are selected from eFuse + * 0b1..The trimming codes of clock detector used to change the boundary frequencies are selected from SNVS_CLK_DET_TRIM */ #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_MASK) + #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_MASK (0xFF00U) #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SHIFT (8U) /*! SNVS_CLK_DET_TRIM - SNVS clock detect trim bits */ #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_MASK) + #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_MASK (0x30000U) #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_SHIFT (16U) /*! SNVS_CLK_DET_OFFSET_HIGH - SNVS clock detect offset of high boundary frequency + * 0b00..No change (Default) + * 0b01..Add +5 to the Trim + * 0b10..Add +10 to the trim + * 0b11..Add -5 to the Trim */ #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_MASK) + #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_MASK (0xC0000U) #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_SHIFT (18U) /*! SNVS_CLK_DET_OFFSET_LOW - SNVS clock detect offset of low boundary frequency + * 0b00..No change (Default) + * 0b01..Add +5 to the Trim + * 0b10..Add +10 to the trim + * 0b11..Add -5 to the Trim */ #define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_MASK) + #define IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_MASK (0x800000U) #define IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_SHIFT (23U) /*! SNVS_CAP_TRIM_SEL - SNVS OSC load capacitor trim select + * 0b0..The trimming codes are selected from eFuse + * 0b1..The trimming codes are used from SNVS_OSC_CAP_TRIM (osc32k's load capacitor) */ #define IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_MASK) + #define IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_MASK (0xF000000U) #define IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_SHIFT (24U) /*! SNVS_OSC_CAP_TRIM - SNVS OSC load capacitor trim @@ -56189,94 +65766,143 @@ typedef struct { /*! @name GPR35 - GPR35 General Purpose Register */ /*! @{ */ + #define IOMUXC_SNVS_GPR_GPR35_LOCK_MASK (0x1U) #define IOMUXC_SNVS_GPR_GPR35_LOCK_SHIFT (0U) /*! LOCK - Lock the write to bit 31:1 + * 0b0..Write access is not blocked + * 0b1..Write access is blocked */ #define IOMUXC_SNVS_GPR_GPR35_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_LOCK_MASK) + #define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_MASK (0x8U) #define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_SHIFT (3U) /*! SNVS_VOLT_DET_TRIM_SEL - SNVS voltage detect trim select + * 0b0..The trimming codes are selected from eFuse + * 0b1..The trimming codes of voltage detectors to change the voltage boundaries in battery voltage detecting are selected from SNVS_VOLT_DET_TRIM */ #define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_MASK) + #define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_MASK (0xFF0U) #define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SHIFT (4U) /*! SNVS_VOLT_DET_TRIM - SNVS voltage detect trim */ #define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_MASK) + #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_MASK (0x8000U) #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_SHIFT (15U) /*! SNVS_TEMP_DET_TRIM_SEL - SNVS temperature detect trim select + * 0b0..The trimming codes are selected from eFuse + * 0b1..The trimming codes to define the temperature boundaries of temperature detector are selected from SNVS_TEMP_DET_TRIM */ #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_MASK) + #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_MASK (0xFFF0000U) #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SHIFT (16U) /*! SNVS_TEMP_DET_TRIM - SNVS temperature detect trim */ #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_MASK) + #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_MASK (0x30000000U) #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_SHIFT (28U) /*! SNVS_TEMP_DET_OFFSET_HIGH - SNVS temperature detect offset of high temperature boundary + * 0b00..No change (Default) + * 0b01..Add +5 to the Trim + * 0b10..Add +10 to the trim + * 0b11..Add -5 to the Trim */ #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_MASK) + #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_MASK (0xC0000000U) #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_SHIFT (30U) /*! SNVS_TEMP_DET_OFFSET_LOW - SNVS temperature detect offset of low temperature boundary + * 0b00..No change (Default) + * 0b01..Add +5 to the Trim + * 0b10..Add +10 to the trim + * 0b11..Add -5 to the Trim */ #define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_MASK) /*! @} */ /*! @name GPR36 - GPR36 General Purpose Register */ /*! @{ */ + #define IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_MASK (0x800000U) #define IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_SHIFT (23U) /*! SNVSDIG_SNVS1P8_ISO_EN - SNVS RAM isolation enable bit + * 0b1..Enable the isolation to avoid extra leakage power before SNVS SRAM peripheral power or LDO_SNVS_DIG is switched off + * 0b0..Enable SRAM access (It should be cleared after LDO_SNVS_DIG and SNVS SRAM peripheral power is back) */ #define IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_MASK) + #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_MASK (0x4000000U) #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_SHIFT (26U) /*! SNVS_SRAM_SLEEP - SNVS SRAM power-down enable bit + * 0b0..Enable SRAM access (It should be cleared after LDO_SNVS_DIG is enabled) + * 0b1..SNVS SRAM can go in Shutdown/ Periphery Off Array On/ Periphery On Array Off mode. In addition, this bit + * ensures power-up without stuck-at /high DC current states and hence must be held to 1 during wake-up, so + * this bit is default high. */ #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_MASK) + #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_MASK (0x8000000U) #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_SHIFT (27U) /*! SNVS_SRAM_STDBY - SNVS SRAM standby enable bit + * 0b1..SNVS SRAM enters low leakage state and large drivers are switched OFF + * 0b0..SNVS SRAM does not enter low leakage state */ #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_MASK) + #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_MASK (0x10000000U) #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_SHIFT (28U) /*! SNVS_SRAM_PSWLARGEMP_FORCE - SNVS SRAM large switch control bit for peripheral + * 0b1..Switch off SNVS SRAM power for peripheral (SRAM array power is not impacted, and data can be retained) + * 0b0..Switch on SNVS SRAM power for peripheral */ #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_MASK) + #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_MASK (0x20000000U) #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_SHIFT (29U) /*! SNVS_SRAM_PSWLARGE - SNVS SRAM large switch control bit + * 0b1..Switch off SNVS SRAM power for peripheral and array + * 0b0..Switch on SNVS SRAM power for peripheral and array */ #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_MASK) + #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_MASK (0x40000000U) #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_SHIFT (30U) /*! SNVS_SRAM_PSWSMALLMP_FORCE - SNVS SRAM small switch control bit for peripheral + * 0b1..Switch off SNVS SRAM power for peripheral (SRAM array power is not impacted, and data can be retained) + * 0b0..Switch on SNVS SRAM power for peripheral */ #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_MASK) + #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_MASK (0x80000000U) #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_SHIFT (31U) /*! SNVS_SRAM_PSWSMALL - SNVS SRAM small switch control bit + * 0b1..Switch off SNVS SRAM power for peripheral and array + * 0b0..Switch on SNVS SRAM power for peripheral and array */ #define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_MASK) /*! @} */ /*! @name GPR37 - GPR37 General Purpose Register */ /*! @{ */ + #define IOMUXC_SNVS_GPR_GPR37_LOCK_MASK (0x1U) #define IOMUXC_SNVS_GPR_GPR37_LOCK_SHIFT (0U) /*! LOCK - Lock the write to bit 31:1 + * 0b0..Write access is not blocked + * 0b1..Write access is blocked */ #define IOMUXC_SNVS_GPR_GPR37_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_LOCK_MASK) + #define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_MASK (0x7FEU) #define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_SHIFT (1U) /*! SNVS_TAMPER_PUE - SNVS tamper detect pin pull enable bit */ #define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_MASK) + #define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_MASK (0x1FF800U) #define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_SHIFT (11U) /*! SNVS_TAMPER_PUS - SNVS tamper detect pin pull selection bit @@ -56305,6 +65931,98 @@ typedef struct { */ /* end of group IOMUXC_SNVS_GPR_Peripheral_Access_Layer */ +/* ---------------------------------------------------------------------------- + -- IPS_DOMAIN Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IPS_DOMAIN_Peripheral_Access_Layer IPS_DOMAIN Peripheral Access Layer + * @{ + */ + +/** IPS_DOMAIN - Register Layout Typedef */ +typedef struct { + struct { /* offset: 0x0, array step: 0x10 */ + __IO uint32_t SLOT_CTRL; /**< Slot Control Register, array offset: 0x0, array step: 0x10 */ + uint8_t RESERVED_0[12]; + } SLOT_CTRL[38]; +} IPS_DOMAIN_Type; + +/* ---------------------------------------------------------------------------- + -- IPS_DOMAIN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IPS_DOMAIN_Register_Masks IPS_DOMAIN Register Masks + * @{ + */ + +/*! @name SLOT_CTRL - Slot Control Register */ +/*! @{ */ + +#define IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_MASK (0xFU) +#define IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_SHIFT (0U) +/*! LOCKED_DOMAIN_ID - Domain ID of the slot to be locked + */ +#define IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_MASK) + +#define IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_MASK (0x8000U) +#define IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_SHIFT (15U) +/*! DOMAIN_LOCK - Lock domain ID of this slot + * 0b0..Do not lock the domain ID + * 0b1..Lock the domain ID + */ +#define IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_MASK) + +#define IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_MASK (0x10000U) +#define IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_SHIFT (16U) +/*! ALLOW_NONSECURE - Allow non-secure write access to this domain control register or domain register + * 0b0..Do not allow non-secure write access + * 0b1..Allow non-secure write access + */ +#define IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_MASK) + +#define IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_MASK (0x20000U) +#define IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_SHIFT (17U) +/*! ALLOW_USER - Allow user write access to this domain control register or domain register + * 0b0..Do not allow user write access + * 0b1..Allow user write access + */ +#define IPS_DOMAIN_SLOT_CTRL_ALLOW_USER(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_MASK) + +#define IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_MASK (0x80000000U) +#define IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_SHIFT (31U) +/*! LOCK_CONTROL - Lock control of this slot + * 0b0..Do not lock the control register of this slot + * 0b1..Lock the control register of this slot + */ +#define IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_MASK) +/*! @} */ + +/* The count of IPS_DOMAIN_SLOT_CTRL */ +#define IPS_DOMAIN_SLOT_CTRL_COUNT (38U) + + +/*! + * @} + */ /* end of group IPS_DOMAIN_Register_Masks */ + + +/* IPS_DOMAIN - Peripheral instance base addresses */ +/** Peripheral IPS_DOMAIN base address */ +#define IPS_DOMAIN_BASE (0x40C87C00u) +/** Peripheral IPS_DOMAIN base pointer */ +#define IPS_DOMAIN ((IPS_DOMAIN_Type *)IPS_DOMAIN_BASE) +/** Array initializer of IPS_DOMAIN peripheral base addresses */ +#define IPS_DOMAIN_BASE_ADDRS { IPS_DOMAIN_BASE } +/** Array initializer of IPS_DOMAIN peripheral base pointers */ +#define IPS_DOMAIN_BASE_PTRS { IPS_DOMAIN } + +/*! + * @} + */ /* end of group IPS_DOMAIN_Peripheral_Access_Layer */ + + /* ---------------------------------------------------------------------------- -- KEY_MANAGER Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -56316,15 +66034,15 @@ typedef struct { /** KEY_MANAGER - Register Layout Typedef */ typedef struct { - __IO uint32_t CSR_MASTER_KEY_CTRL; /**< CSR Master Key Control Register, offset: 0x0 */ + __IO uint32_t MASTER_KEY_CTRL; /**< CSR Master Key Control Register, offset: 0x0 */ uint8_t RESERVED_0[12]; - __IO uint32_t CSR_OTFAD1_KEY_CTRL; /**< CSR OTFAD-1 Key Control, offset: 0x10 */ + __IO uint32_t OTFAD1_KEY_CTRL; /**< CSR OTFAD-1 Key Control, offset: 0x10 */ uint8_t RESERVED_1[4]; - __IO uint32_t CSR_OTFAD2_KEY_CTRL; /**< CSR OTFAD-2 Key Control, offset: 0x18 */ + __IO uint32_t OTFAD2_KEY_CTRL; /**< CSR OTFAD-2 Key Control, offset: 0x18 */ uint8_t RESERVED_2[4]; - __IO uint32_t CSR_IEE_KEY_CTRL; /**< CSR IEE Key Control, offset: 0x20 */ + __IO uint32_t IEE_KEY_CTRL; /**< CSR IEE Key Control, offset: 0x20 */ uint8_t RESERVED_3[12]; - __IO uint32_t CSR_PUF_KEY_CTRL; /**< CSR PUF Key Control, offset: 0x30 */ + __IO uint32_t PUF_KEY_CTRL; /**< CSR PUF Key Control, offset: 0x30 */ uint8_t RESERVED_4[972]; __IO uint32_t SLOT0_CTRL; /**< Slot 0 Control, offset: 0x400 */ __IO uint32_t SLOT1_CTRL; /**< Slot1 Control, offset: 0x404 */ @@ -56342,111 +66060,124 @@ typedef struct { * @{ */ -/*! @name CSR_MASTER_KEY_CTRL - CSR Master Key Control Register */ +/*! @name MASTER_KEY_CTRL - CSR Master Key Control Register */ /*! @{ */ -#define KEY_MANAGER_CSR_MASTER_KEY_CTRL_KEY_SELECT_MASK (0x1U) -#define KEY_MANAGER_CSR_MASTER_KEY_CTRL_KEY_SELECT_SHIFT (0U) -/*! KEY_SELECT - Key select for SNVS OTPMK + +#define KEY_MANAGER_MASTER_KEY_CTRL_SELECT_MASK (0x1U) +#define KEY_MANAGER_MASTER_KEY_CTRL_SELECT_SHIFT (0U) +/*! SELECT - Key select for SNVS OTPMK. Default value comes from FUSE_MASTER_KEY_SEL. * 0b0..select key from UDF - * 0b1..If PUF_KEY_LOCK signal is equal to 1, select key from PUF, otherwise select key from OCOTP + * 0b1..If LOCK = 1, select key from PUF, otherwise select key from fuse (bypass the fuse OTPMK to SNVS) */ -#define KEY_MANAGER_CSR_MASTER_KEY_CTRL_KEY_SELECT(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_CSR_MASTER_KEY_CTRL_KEY_SELECT_SHIFT)) & KEY_MANAGER_CSR_MASTER_KEY_CTRL_KEY_SELECT_MASK) -#define KEY_MANAGER_CSR_MASTER_KEY_CTRL_KEY_LOCK_MASK (0x10000U) -#define KEY_MANAGER_CSR_MASTER_KEY_CTRL_KEY_LOCK_SHIFT (16U) -/*! KEY_LOCK - lock this register, prevent from writing +#define KEY_MANAGER_MASTER_KEY_CTRL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_MASTER_KEY_CTRL_SELECT_SHIFT)) & KEY_MANAGER_MASTER_KEY_CTRL_SELECT_MASK) + +#define KEY_MANAGER_MASTER_KEY_CTRL_LOCK_MASK (0x10000U) +#define KEY_MANAGER_MASTER_KEY_CTRL_LOCK_SHIFT (16U) +/*! LOCK - lock this register, prevent from writing. Default value comes from FUSE_MASTER_KEY_SEL_LOCK. * 0b0..not locked * 0b1..locked */ -#define KEY_MANAGER_CSR_MASTER_KEY_CTRL_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_CSR_MASTER_KEY_CTRL_KEY_LOCK_SHIFT)) & KEY_MANAGER_CSR_MASTER_KEY_CTRL_KEY_LOCK_MASK) +#define KEY_MANAGER_MASTER_KEY_CTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_MASTER_KEY_CTRL_LOCK_SHIFT)) & KEY_MANAGER_MASTER_KEY_CTRL_LOCK_MASK) /*! @} */ -/*! @name CSR_OTFAD1_KEY_CTRL - CSR OTFAD-1 Key Control */ +/*! @name OTFAD1_KEY_CTRL - CSR OTFAD-1 Key Control */ /*! @{ */ -#define KEY_MANAGER_CSR_OTFAD1_KEY_CTRL_KEY_SELECT_MASK (0x1U) -#define KEY_MANAGER_CSR_OTFAD1_KEY_CTRL_KEY_SELECT_SHIFT (0U) -/*! KEY_SELECT - key select for OTFAD-1 + +#define KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT_MASK (0x1U) +#define KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT_SHIFT (0U) +/*! SELECT - key select for OTFAD-1. Default value comes from FUSE_OTFAD1_KEY_SEL. * 0b0..Select key from OCOTP USER_KEY5 - * 0b1..If CSR_PUF_KEY_CTRL[PUF_KEY_LOCK] is 1, select key from PUF, otherwise select key from OCOTP USER_KEY5 + * 0b1..If PUF_KEY_CTRL[LOCK] is 1, select key from PUF, otherwise select key from OCOTP USER_KEY5 */ -#define KEY_MANAGER_CSR_OTFAD1_KEY_CTRL_KEY_SELECT(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_CSR_OTFAD1_KEY_CTRL_KEY_SELECT_SHIFT)) & KEY_MANAGER_CSR_OTFAD1_KEY_CTRL_KEY_SELECT_MASK) -#define KEY_MANAGER_CSR_OTFAD1_KEY_CTRL_KEY_LOCK_MASK (0x10000U) -#define KEY_MANAGER_CSR_OTFAD1_KEY_CTRL_KEY_LOCK_SHIFT (16U) -/*! KEY_LOCK - lock this register, prevent from writing +#define KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT_SHIFT)) & KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT_MASK) + +#define KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK_MASK (0x10000U) +#define KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK_SHIFT (16U) +/*! LOCK - lock this register, prevent from writing. Default value comes from FUSE_OTFAD1_KEY_SEL_LOCK. * 0b0..not locked * 0b1..locked */ -#define KEY_MANAGER_CSR_OTFAD1_KEY_CTRL_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_CSR_OTFAD1_KEY_CTRL_KEY_LOCK_SHIFT)) & KEY_MANAGER_CSR_OTFAD1_KEY_CTRL_KEY_LOCK_MASK) +#define KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK_SHIFT)) & KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK_MASK) /*! @} */ -/*! @name CSR_OTFAD2_KEY_CTRL - CSR OTFAD-2 Key Control */ +/*! @name OTFAD2_KEY_CTRL - CSR OTFAD-2 Key Control */ /*! @{ */ -#define KEY_MANAGER_CSR_OTFAD2_KEY_CTRL_key_select_MASK (0x1U) -#define KEY_MANAGER_CSR_OTFAD2_KEY_CTRL_key_select_SHIFT (0U) -/*! key_select - key select for OTFAD-2 + +#define KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT_MASK (0x1U) +#define KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT_SHIFT (0U) +/*! SELECT - key select for OTFAD-2. Default value comes from FUSE_OTFAD1_KEY_SEL. * 0b0..select key from OCOTP USER_KEY5 - * 0b1..If CSR_PUF_KEY_CTRL[PUF_KEY_LOCK] is 1, select key from PUF, otherwise select key from OCOTP USER_KEY5 + * 0b1..If PUF_KEY_CTRL[LOCK] is 1, select key from PUF, otherwise select key from OCOTP USER_KEY5 */ -#define KEY_MANAGER_CSR_OTFAD2_KEY_CTRL_key_select(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_CSR_OTFAD2_KEY_CTRL_key_select_SHIFT)) & KEY_MANAGER_CSR_OTFAD2_KEY_CTRL_key_select_MASK) -#define KEY_MANAGER_CSR_OTFAD2_KEY_CTRL_KEY_LOCK_MASK (0x10000U) -#define KEY_MANAGER_CSR_OTFAD2_KEY_CTRL_KEY_LOCK_SHIFT (16U) -/*! KEY_LOCK - lock this register, prevent from writing +#define KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT_SHIFT)) & KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT_MASK) + +#define KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK_MASK (0x10000U) +#define KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK_SHIFT (16U) +/*! LOCK - lock this register, prevent from writing. Default value comes from FUSE_OTFAD2_KEY_SEL_LOCK. * 0b0..not locked * 0b1..locked */ -#define KEY_MANAGER_CSR_OTFAD2_KEY_CTRL_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_CSR_OTFAD2_KEY_CTRL_KEY_LOCK_SHIFT)) & KEY_MANAGER_CSR_OTFAD2_KEY_CTRL_KEY_LOCK_MASK) +#define KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK_SHIFT)) & KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK_MASK) /*! @} */ -/*! @name CSR_IEE_KEY_CTRL - CSR IEE Key Control */ +/*! @name IEE_KEY_CTRL - CSR IEE Key Control */ /*! @{ */ -#define KEY_MANAGER_CSR_IEE_KEY_CTRL_IEE_KEY_RELOAD_MASK (0x1U) -#define KEY_MANAGER_CSR_IEE_KEY_CTRL_IEE_KEY_RELOAD_SHIFT (0U) -/*! IEE_KEY_RELOAD - Restart load key signal for IEE + +#define KEY_MANAGER_IEE_KEY_CTRL_RELOAD_MASK (0x1U) +#define KEY_MANAGER_IEE_KEY_CTRL_RELOAD_SHIFT (0U) +/*! RELOAD - Restart load key signal for IEE * 0b0..Do nothing * 0b1..Restart IEE key load flow */ -#define KEY_MANAGER_CSR_IEE_KEY_CTRL_IEE_KEY_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_CSR_IEE_KEY_CTRL_IEE_KEY_RELOAD_SHIFT)) & KEY_MANAGER_CSR_IEE_KEY_CTRL_IEE_KEY_RELOAD_MASK) +#define KEY_MANAGER_IEE_KEY_CTRL_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_IEE_KEY_CTRL_RELOAD_SHIFT)) & KEY_MANAGER_IEE_KEY_CTRL_RELOAD_MASK) /*! @} */ -/*! @name CSR_PUF_KEY_CTRL - CSR PUF Key Control */ +/*! @name PUF_KEY_CTRL - CSR PUF Key Control */ /*! @{ */ -#define KEY_MANAGER_CSR_PUF_KEY_CTRL_PUF_KEY_LOCK_MASK (0x1U) -#define KEY_MANAGER_CSR_PUF_KEY_CTRL_PUF_KEY_LOCK_SHIFT (0U) -/*! PUF_KEY_LOCK - lock signal for key select + +#define KEY_MANAGER_PUF_KEY_CTRL_LOCK_MASK (0x1U) +#define KEY_MANAGER_PUF_KEY_CTRL_LOCK_SHIFT (0U) +/*! LOCK - Lock signal for key select * 0b0..Do not lock the key select - * 0b1..Lock the key select to select key from PUF, ohterwise bypass key from OCOPT and do not lock. Once it has + * 0b1..Lock the key select to select key from PUF, otherwise bypass key from OCOPT and do not lock. Once it has * been set to 1, it cannot be reset manually. It will be set to 0 when the IEE key reload operation is done. */ -#define KEY_MANAGER_CSR_PUF_KEY_CTRL_PUF_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_CSR_PUF_KEY_CTRL_PUF_KEY_LOCK_SHIFT)) & KEY_MANAGER_CSR_PUF_KEY_CTRL_PUF_KEY_LOCK_MASK) +#define KEY_MANAGER_PUF_KEY_CTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_PUF_KEY_CTRL_LOCK_SHIFT)) & KEY_MANAGER_PUF_KEY_CTRL_LOCK_MASK) /*! @} */ /*! @name SLOT0_CTRL - Slot 0 Control */ /*! @{ */ -#define KEY_MANAGER_SLOT0_CTRL_LOCKED_DOMAIN_ID_MASK (0xFU) -#define KEY_MANAGER_SLOT0_CTRL_LOCKED_DOMAIN_ID_SHIFT (0U) -/*! LOCKED_DOMAIN_ID - Domain ID of the slot to be locked + +#define KEY_MANAGER_SLOT0_CTRL_WHITE_LIST_MASK (0xFU) +#define KEY_MANAGER_SLOT0_CTRL_WHITE_LIST_SHIFT (0U) +/*! WHITE_LIST - Whitelist */ -#define KEY_MANAGER_SLOT0_CTRL_LOCKED_DOMAIN_ID(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_LOCKED_DOMAIN_ID_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_LOCKED_DOMAIN_ID_MASK) -#define KEY_MANAGER_SLOT0_CTRL_DOMAIN_LOCK_MASK (0x8000U) -#define KEY_MANAGER_SLOT0_CTRL_DOMAIN_LOCK_SHIFT (15U) -/*! DOMAIN_LOCK - Lock domain ID of this slot - * 0b0..Do not lock the domain ID - * 0b1..Lock the domain ID +#define KEY_MANAGER_SLOT0_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_WHITE_LIST_MASK) + +#define KEY_MANAGER_SLOT0_CTRL_LOCK_LIST_MASK (0x8000U) +#define KEY_MANAGER_SLOT0_CTRL_LOCK_LIST_SHIFT (15U) +/*! LOCK_LIST - Lock whitelist + * 0b0..Whitelist is not locked + * 0b1..Whitelist is locked */ -#define KEY_MANAGER_SLOT0_CTRL_DOMAIN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_DOMAIN_LOCK_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_DOMAIN_LOCK_MASK) -#define KEY_MANAGER_SLOT0_CTRL_ALLOW_NONSECURE_MASK (0x10000U) -#define KEY_MANAGER_SLOT0_CTRL_ALLOW_NONSECURE_SHIFT (16U) -/*! ALLOW_NONSECURE - Allow non-secure write access to this domain control register or domain register +#define KEY_MANAGER_SLOT0_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_LOCK_LIST_MASK) + +#define KEY_MANAGER_SLOT0_CTRL_TZ_NS_MASK (0x10000U) +#define KEY_MANAGER_SLOT0_CTRL_TZ_NS_SHIFT (16U) +/*! TZ_NS - Allow non-secure write access to this register and the slot it controls * 0b0..Do not allow non-secure write access * 0b1..Allow non-secure write access */ -#define KEY_MANAGER_SLOT0_CTRL_ALLOW_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_ALLOW_NONSECURE_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_ALLOW_NONSECURE_MASK) -#define KEY_MANAGER_SLOT0_CTRL_ALLOW_USER_MASK (0x20000U) -#define KEY_MANAGER_SLOT0_CTRL_ALLOW_USER_SHIFT (17U) -/*! ALLOW_USER - Allow user write access to this domain control register or domain register +#define KEY_MANAGER_SLOT0_CTRL_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_TZ_NS_MASK) + +#define KEY_MANAGER_SLOT0_CTRL_TZ_USER_MASK (0x20000U) +#define KEY_MANAGER_SLOT0_CTRL_TZ_USER_SHIFT (17U) +/*! TZ_USER - Allow user write access to this register and the slot it controls * 0b0..Do not allow user write access * 0b1..Allow user write access */ -#define KEY_MANAGER_SLOT0_CTRL_ALLOW_USER(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_ALLOW_USER_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_ALLOW_USER_MASK) +#define KEY_MANAGER_SLOT0_CTRL_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_TZ_USER_MASK) + #define KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL_MASK (0x80000000U) #define KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL_SHIFT (31U) /*! LOCK_CONTROL - Lock control of this slot @@ -56458,32 +66189,37 @@ typedef struct { /*! @name SLOT1_CTRL - Slot1 Control */ /*! @{ */ -#define KEY_MANAGER_SLOT1_CTRL_LOCKED_DOMAIN_ID_MASK (0xFU) -#define KEY_MANAGER_SLOT1_CTRL_LOCKED_DOMAIN_ID_SHIFT (0U) -/*! LOCKED_DOMAIN_ID - Domain ID of the slot to be locked + +#define KEY_MANAGER_SLOT1_CTRL_WHITE_LIST_MASK (0xFU) +#define KEY_MANAGER_SLOT1_CTRL_WHITE_LIST_SHIFT (0U) +/*! WHITE_LIST - Whitelist */ -#define KEY_MANAGER_SLOT1_CTRL_LOCKED_DOMAIN_ID(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_LOCKED_DOMAIN_ID_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_LOCKED_DOMAIN_ID_MASK) -#define KEY_MANAGER_SLOT1_CTRL_DOMAIN_LOCK_MASK (0x8000U) -#define KEY_MANAGER_SLOT1_CTRL_DOMAIN_LOCK_SHIFT (15U) -/*! DOMAIN_LOCK - Lock domain ID of this slot - * 0b0..Do not lock the domain ID - * 0b1..Lock the domain ID +#define KEY_MANAGER_SLOT1_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_WHITE_LIST_MASK) + +#define KEY_MANAGER_SLOT1_CTRL_LOCK_LIST_MASK (0x8000U) +#define KEY_MANAGER_SLOT1_CTRL_LOCK_LIST_SHIFT (15U) +/*! LOCK_LIST - Lock whitelist + * 0b0..Whitelist is not locked + * 0b1..Whitelist is locked */ -#define KEY_MANAGER_SLOT1_CTRL_DOMAIN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_DOMAIN_LOCK_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_DOMAIN_LOCK_MASK) -#define KEY_MANAGER_SLOT1_CTRL_ALLOW_NONSECURE_MASK (0x10000U) -#define KEY_MANAGER_SLOT1_CTRL_ALLOW_NONSECURE_SHIFT (16U) -/*! ALLOW_NONSECURE - Allow non-secure write access to this domain control register or domain register +#define KEY_MANAGER_SLOT1_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_LOCK_LIST_MASK) + +#define KEY_MANAGER_SLOT1_CTRL_TZ_NS_MASK (0x10000U) +#define KEY_MANAGER_SLOT1_CTRL_TZ_NS_SHIFT (16U) +/*! TZ_NS - Allow non-secure write access to this register and the slot it controls * 0b0..Do not allow non-secure write access * 0b1..Allow non-secure write access */ -#define KEY_MANAGER_SLOT1_CTRL_ALLOW_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_ALLOW_NONSECURE_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_ALLOW_NONSECURE_MASK) -#define KEY_MANAGER_SLOT1_CTRL_ALLOW_USER_MASK (0x20000U) -#define KEY_MANAGER_SLOT1_CTRL_ALLOW_USER_SHIFT (17U) -/*! ALLOW_USER - Allow user write access to this domain control register or domain register +#define KEY_MANAGER_SLOT1_CTRL_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_TZ_NS_MASK) + +#define KEY_MANAGER_SLOT1_CTRL_TZ_USER_MASK (0x20000U) +#define KEY_MANAGER_SLOT1_CTRL_TZ_USER_SHIFT (17U) +/*! TZ_USER - Allow user write access to this register and the slot it controls * 0b0..Do not allow user write access * 0b1..Allow user write access */ -#define KEY_MANAGER_SLOT1_CTRL_ALLOW_USER(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_ALLOW_USER_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_ALLOW_USER_MASK) +#define KEY_MANAGER_SLOT1_CTRL_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_TZ_USER_MASK) + #define KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL_MASK (0x80000000U) #define KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL_SHIFT (31U) /*! LOCK_CONTROL - Lock control of this slot @@ -56495,32 +66231,37 @@ typedef struct { /*! @name SLOT2_CTRL - Slot2 Control */ /*! @{ */ -#define KEY_MANAGER_SLOT2_CTRL_LOCKED_DOMAIN_ID_MASK (0xFU) -#define KEY_MANAGER_SLOT2_CTRL_LOCKED_DOMAIN_ID_SHIFT (0U) -/*! LOCKED_DOMAIN_ID - Domain ID of the slot to be locked + +#define KEY_MANAGER_SLOT2_CTRL_WHITE_LIST_MASK (0xFU) +#define KEY_MANAGER_SLOT2_CTRL_WHITE_LIST_SHIFT (0U) +/*! WHITE_LIST - Whitelist */ -#define KEY_MANAGER_SLOT2_CTRL_LOCKED_DOMAIN_ID(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_LOCKED_DOMAIN_ID_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_LOCKED_DOMAIN_ID_MASK) -#define KEY_MANAGER_SLOT2_CTRL_DOMAIN_LOCK_MASK (0x8000U) -#define KEY_MANAGER_SLOT2_CTRL_DOMAIN_LOCK_SHIFT (15U) -/*! DOMAIN_LOCK - Lock domain ID of this slot - * 0b0..Do not lock the domain ID - * 0b1..Lock the domain ID +#define KEY_MANAGER_SLOT2_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_WHITE_LIST_MASK) + +#define KEY_MANAGER_SLOT2_CTRL_LOCK_LIST_MASK (0x8000U) +#define KEY_MANAGER_SLOT2_CTRL_LOCK_LIST_SHIFT (15U) +/*! LOCK_LIST - Lock whitelist + * 0b0..Whitelist is not locked + * 0b1..Whitelist is locked */ -#define KEY_MANAGER_SLOT2_CTRL_DOMAIN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_DOMAIN_LOCK_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_DOMAIN_LOCK_MASK) -#define KEY_MANAGER_SLOT2_CTRL_ALLOW_NONSECURE_MASK (0x10000U) -#define KEY_MANAGER_SLOT2_CTRL_ALLOW_NONSECURE_SHIFT (16U) -/*! ALLOW_NONSECURE - Allow non-secure write access to this domain control register or domain register +#define KEY_MANAGER_SLOT2_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_LOCK_LIST_MASK) + +#define KEY_MANAGER_SLOT2_CTRL_TZ_NS_MASK (0x10000U) +#define KEY_MANAGER_SLOT2_CTRL_TZ_NS_SHIFT (16U) +/*! TZ_NS - Allow non-secure write access to this register and the slot it controls * 0b0..Do not allow non-secure write access * 0b1..Allow non-secure write access */ -#define KEY_MANAGER_SLOT2_CTRL_ALLOW_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_ALLOW_NONSECURE_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_ALLOW_NONSECURE_MASK) -#define KEY_MANAGER_SLOT2_CTRL_ALLOW_USER_MASK (0x20000U) -#define KEY_MANAGER_SLOT2_CTRL_ALLOW_USER_SHIFT (17U) -/*! ALLOW_USER - Allow user write access to this domain control register or domain register +#define KEY_MANAGER_SLOT2_CTRL_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_TZ_NS_MASK) + +#define KEY_MANAGER_SLOT2_CTRL_TZ_USER_MASK (0x20000U) +#define KEY_MANAGER_SLOT2_CTRL_TZ_USER_SHIFT (17U) +/*! TZ_USER - Allow user write access to this register and the slot it controls * 0b0..Do not allow user write access * 0b1..Allow user write access */ -#define KEY_MANAGER_SLOT2_CTRL_ALLOW_USER(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_ALLOW_USER_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_ALLOW_USER_MASK) +#define KEY_MANAGER_SLOT2_CTRL_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_TZ_USER_MASK) + #define KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL_MASK (0x80000000U) #define KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL_SHIFT (31U) /*! LOCK_CONTROL - Lock control of this slot @@ -56532,32 +66273,37 @@ typedef struct { /*! @name SLOT3_CTRL - Slot3 Control */ /*! @{ */ -#define KEY_MANAGER_SLOT3_CTRL_LOCKED_DOMAIN_ID_MASK (0xFU) -#define KEY_MANAGER_SLOT3_CTRL_LOCKED_DOMAIN_ID_SHIFT (0U) -/*! LOCKED_DOMAIN_ID - Domain ID of the slot to be locked + +#define KEY_MANAGER_SLOT3_CTRL_WHITE_LIST_MASK (0xFU) +#define KEY_MANAGER_SLOT3_CTRL_WHITE_LIST_SHIFT (0U) +/*! WHITE_LIST - Whitelist */ -#define KEY_MANAGER_SLOT3_CTRL_LOCKED_DOMAIN_ID(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_LOCKED_DOMAIN_ID_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_LOCKED_DOMAIN_ID_MASK) -#define KEY_MANAGER_SLOT3_CTRL_DOMAIN_LOCK_MASK (0x8000U) -#define KEY_MANAGER_SLOT3_CTRL_DOMAIN_LOCK_SHIFT (15U) -/*! DOMAIN_LOCK - Lock domain ID of this slot - * 0b0..Do not lock the domain ID - * 0b1..Lock the domain ID +#define KEY_MANAGER_SLOT3_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_WHITE_LIST_MASK) + +#define KEY_MANAGER_SLOT3_CTRL_LOCK_LIST_MASK (0x8000U) +#define KEY_MANAGER_SLOT3_CTRL_LOCK_LIST_SHIFT (15U) +/*! LOCK_LIST - Lock whitelist + * 0b0..Whitelist is not locked + * 0b1..Whitelist is locked */ -#define KEY_MANAGER_SLOT3_CTRL_DOMAIN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_DOMAIN_LOCK_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_DOMAIN_LOCK_MASK) -#define KEY_MANAGER_SLOT3_CTRL_ALLOW_NONSECURE_MASK (0x10000U) -#define KEY_MANAGER_SLOT3_CTRL_ALLOW_NONSECURE_SHIFT (16U) -/*! ALLOW_NONSECURE - Allow non-secure write access to this domain control register or domain register +#define KEY_MANAGER_SLOT3_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_LOCK_LIST_MASK) + +#define KEY_MANAGER_SLOT3_CTRL_TZ_NS_MASK (0x10000U) +#define KEY_MANAGER_SLOT3_CTRL_TZ_NS_SHIFT (16U) +/*! TZ_NS - Allow non-secure write access to this register and the slot it controls * 0b0..Do not allow non-secure write access * 0b1..Allow non-secure write access */ -#define KEY_MANAGER_SLOT3_CTRL_ALLOW_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_ALLOW_NONSECURE_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_ALLOW_NONSECURE_MASK) -#define KEY_MANAGER_SLOT3_CTRL_ALLOW_USER_MASK (0x20000U) -#define KEY_MANAGER_SLOT3_CTRL_ALLOW_USER_SHIFT (17U) -/*! ALLOW_USER - Allow user write access to this domain control register or domain register +#define KEY_MANAGER_SLOT3_CTRL_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_TZ_NS_MASK) + +#define KEY_MANAGER_SLOT3_CTRL_TZ_USER_MASK (0x20000U) +#define KEY_MANAGER_SLOT3_CTRL_TZ_USER_SHIFT (17U) +/*! TZ_USER - Allow user write access to this register and the slot it controls * 0b0..Do not allow user write access * 0b1..Allow user write access */ -#define KEY_MANAGER_SLOT3_CTRL_ALLOW_USER(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_ALLOW_USER_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_ALLOW_USER_MASK) +#define KEY_MANAGER_SLOT3_CTRL_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_TZ_USER_MASK) + #define KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL_MASK (0x80000000U) #define KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL_SHIFT (31U) /*! LOCK_CONTROL - Lock control of this slot @@ -56569,32 +66315,37 @@ typedef struct { /*! @name SLOT4_CTRL - Slot 4 Control */ /*! @{ */ -#define KEY_MANAGER_SLOT4_CTRL_LOCKED_DOMAIN_ID_MASK (0xFU) -#define KEY_MANAGER_SLOT4_CTRL_LOCKED_DOMAIN_ID_SHIFT (0U) -/*! LOCKED_DOMAIN_ID - the domain id locked of this slot + +#define KEY_MANAGER_SLOT4_CTRL_WHITE_LIST_MASK (0xFU) +#define KEY_MANAGER_SLOT4_CTRL_WHITE_LIST_SHIFT (0U) +/*! WHITE_LIST - Whitelist */ -#define KEY_MANAGER_SLOT4_CTRL_LOCKED_DOMAIN_ID(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_LOCKED_DOMAIN_ID_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_LOCKED_DOMAIN_ID_MASK) -#define KEY_MANAGER_SLOT4_CTRL_DOMAIN_LOCK_MASK (0x8000U) -#define KEY_MANAGER_SLOT4_CTRL_DOMAIN_LOCK_SHIFT (15U) -/*! DOMAIN_LOCK - Lock domain ID of this slot - * 0b0..Do not lock the domain ID - * 0b1..Lock the domain ID +#define KEY_MANAGER_SLOT4_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_WHITE_LIST_MASK) + +#define KEY_MANAGER_SLOT4_CTRL_LOCK_LIST_MASK (0x8000U) +#define KEY_MANAGER_SLOT4_CTRL_LOCK_LIST_SHIFT (15U) +/*! LOCK_LIST - Lock whitelist + * 0b0..Whitelist is not locked + * 0b1..Whitelist is locked */ -#define KEY_MANAGER_SLOT4_CTRL_DOMAIN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_DOMAIN_LOCK_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_DOMAIN_LOCK_MASK) -#define KEY_MANAGER_SLOT4_CTRL_ALLOW_NONSECURE_MASK (0x10000U) -#define KEY_MANAGER_SLOT4_CTRL_ALLOW_NONSECURE_SHIFT (16U) -/*! ALLOW_NONSECURE - Allow non-secure write access to this domain control register or domain register +#define KEY_MANAGER_SLOT4_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_LOCK_LIST_MASK) + +#define KEY_MANAGER_SLOT4_CTRL_TZ_NS_MASK (0x10000U) +#define KEY_MANAGER_SLOT4_CTRL_TZ_NS_SHIFT (16U) +/*! TZ_NS - Allow non-secure write access to this register and the slot it controls * 0b0..Do not allow non-secure write access * 0b1..Allow non-secure write access */ -#define KEY_MANAGER_SLOT4_CTRL_ALLOW_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_ALLOW_NONSECURE_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_ALLOW_NONSECURE_MASK) -#define KEY_MANAGER_SLOT4_CTRL_ALLOW_USER_MASK (0x20000U) -#define KEY_MANAGER_SLOT4_CTRL_ALLOW_USER_SHIFT (17U) -/*! ALLOW_USER - Allow user write access to this domain control register or domain register +#define KEY_MANAGER_SLOT4_CTRL_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_TZ_NS_MASK) + +#define KEY_MANAGER_SLOT4_CTRL_TZ_USER_MASK (0x20000U) +#define KEY_MANAGER_SLOT4_CTRL_TZ_USER_SHIFT (17U) +/*! TZ_USER - Allow user write access to this register and the slot it controls * 0b0..Do not allow user write access * 0b1..Allow user write access */ -#define KEY_MANAGER_SLOT4_CTRL_ALLOW_USER(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_ALLOW_USER_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_ALLOW_USER_MASK) +#define KEY_MANAGER_SLOT4_CTRL_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_TZ_USER_MASK) + #define KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL_MASK (0x80000000U) #define KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL_SHIFT (31U) /*! LOCK_CONTROL - Lock control of this slot @@ -56653,16 +66404,18 @@ typedef struct { /*! @name KPCR - Keypad Control Register */ /*! @{ */ + #define KPP_KPCR_KRE_MASK (0xFFU) #define KPP_KPCR_KRE_SHIFT (0U) -/*! KRE +/*! KRE - KRE * 0b00000000..Row is not included in the keypad key press detect. * 0b00000001..Row is included in the keypad key press detect. */ #define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK) + #define KPP_KPCR_KCO_MASK (0xFF00U) #define KPP_KPCR_KCO_SHIFT (8U) -/*! KCO +/*! KCO - KCO * 0b00000000..Column strobe output is totem pole drive. * 0b00000001..Column strobe output is open drain. */ @@ -56671,44 +66424,50 @@ typedef struct { /*! @name KPSR - Keypad Status Register */ /*! @{ */ + #define KPP_KPSR_KPKD_MASK (0x1U) #define KPP_KPSR_KPKD_SHIFT (0U) -/*! KPKD +/*! KPKD - KPKD * 0b0..No key presses detected * 0b1..A key has been depressed */ #define KPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK) + #define KPP_KPSR_KPKR_MASK (0x2U) #define KPP_KPSR_KPKR_SHIFT (1U) -/*! KPKR +/*! KPKR - KPKR * 0b0..No key release detected * 0b1..All keys have been released */ #define KPP_KPSR_KPKR(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK) + #define KPP_KPSR_KDSC_MASK (0x4U) #define KPP_KPSR_KDSC_SHIFT (2U) -/*! KDSC +/*! KDSC - KDSC * 0b0..No effect * 0b1..Set bits that clear the keypad depress synchronizer chain */ #define KPP_KPSR_KDSC(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK) + #define KPP_KPSR_KRSS_MASK (0x8U) #define KPP_KPSR_KRSS_SHIFT (3U) -/*! KRSS +/*! KRSS - KRSS * 0b0..No effect * 0b1..Set bits which sets keypad release synchronizer chain */ #define KPP_KPSR_KRSS(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK) + #define KPP_KPSR_KDIE_MASK (0x100U) #define KPP_KPSR_KDIE_SHIFT (8U) -/*! KDIE +/*! KDIE - KDIE * 0b0..No interrupt request is generated when KPKD is set. * 0b1..An interrupt request is generated when KPKD is set. */ #define KPP_KPSR_KDIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK) + #define KPP_KPSR_KRIE_MASK (0x200U) #define KPP_KPSR_KRIE_SHIFT (9U) -/*! KRIE +/*! KRIE - KRIE * 0b0..No interrupt request is generated when KPKR is set. * 0b1..An interrupt request is generated when KPKR is set. */ @@ -56717,16 +66476,18 @@ typedef struct { /*! @name KDDR - Keypad Data Direction Register */ /*! @{ */ + #define KPP_KDDR_KRDD_MASK (0xFFU) #define KPP_KDDR_KRDD_SHIFT (0U) -/*! KRDD +/*! KRDD - KRDD * 0b00000000..ROWn pin configured as an input. * 0b00000001..ROWn pin configured as an output. */ #define KPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK) + #define KPP_KDDR_KCDD_MASK (0xFF00U) #define KPP_KDDR_KCDD_SHIFT (8U) -/*! KCDD +/*! KCDD - KCDD * 0b00000000..COLn pin is configured as an input. * 0b00000001..COLn pin is configured as an output. */ @@ -56735,11 +66496,17 @@ typedef struct { /*! @name KPDR - Keypad Data Register */ /*! @{ */ + #define KPP_KPDR_KRD_MASK (0xFFU) #define KPP_KPDR_KRD_SHIFT (0U) +/*! KRD - KRD + */ #define KPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK) + #define KPP_KPDR_KCD_MASK (0xFF00U) #define KPP_KPDR_KCD_SHIFT (8U) +/*! KCD - KCD + */ #define KPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK) /*! @} */ @@ -56794,31 +66561,27 @@ typedef struct { __IO uint32_t CUR_BUF; /**< LCD Interface Current Buffer Address Register, offset: 0x40 */ uint8_t RESERVED_1[12]; __IO uint32_t NEXT_BUF; /**< LCD Interface Next Buffer Address Register, offset: 0x50 */ - uint8_t RESERVED_2[12]; - __IO uint32_t TIMING; /**< LCD Interface Timing Register, offset: 0x60 */ - uint8_t RESERVED_3[12]; + uint8_t RESERVED_2[28]; __IO uint32_t VDCTRL0; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */ __IO uint32_t VDCTRL0_SET; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */ __IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */ __IO uint32_t VDCTRL0_TOG; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */ __IO uint32_t VDCTRL1; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */ - uint8_t RESERVED_4[12]; + uint8_t RESERVED_3[12]; __IO uint32_t VDCTRL2; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90 */ - uint8_t RESERVED_5[12]; + uint8_t RESERVED_4[12]; __IO uint32_t VDCTRL3; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */ - uint8_t RESERVED_6[12]; + uint8_t RESERVED_5[12]; __IO uint32_t VDCTRL4; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */ - uint8_t RESERVED_7[220]; + uint8_t RESERVED_6[220]; __IO uint32_t BM_ERROR_STAT; /**< Bus Master Error Status Register, offset: 0x190 */ - uint8_t RESERVED_8[12]; + uint8_t RESERVED_7[12]; __IO uint32_t CRC_STAT; /**< CRC Status Register, offset: 0x1A0 */ - uint8_t RESERVED_9[12]; + uint8_t RESERVED_8[12]; __I uint32_t STAT; /**< LCD Interface Status Register, offset: 0x1B0 */ - uint8_t RESERVED_10[76]; + uint8_t RESERVED_9[76]; __IO uint32_t THRES; /**< LCDIF Threshold Register, offset: 0x200 */ - uint8_t RESERVED_11[92]; - __IO uint32_t SYNC_DELAY; /**< LCD working insync mode with CSI for VSYNC delay, offset: 0x260 */ - uint8_t RESERVED_12[284]; + uint8_t RESERVED_10[380]; __IO uint32_t PIGEONCTRL0; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x380 */ __IO uint32_t PIGEONCTRL0_SET; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x384 */ __IO uint32_t PIGEONCTRL0_CLR; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x388 */ @@ -56831,7 +66594,7 @@ typedef struct { __IO uint32_t PIGEONCTRL2_SET; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A4 */ __IO uint32_t PIGEONCTRL2_CLR; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A8 */ __IO uint32_t PIGEONCTRL2_TOG; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3AC */ - uint8_t RESERVED_13[1104]; + uint8_t RESERVED_11[1104]; struct { /* offset: 0x800, array step: 0x40 */ __IO uint32_t PIGEON_0; /**< Panel Interface Signal Generator Register, array offset: 0x800, array step: 0x40 */ uint8_t RESERVED_0[12]; @@ -56840,15 +66603,15 @@ typedef struct { __IO uint32_t PIGEON_2; /**< Panel Interface Signal Generator Register, array offset: 0x820, array step: 0x40 */ uint8_t RESERVED_2[28]; } PIGEON[12]; - __IO uint32_t LUT_CTRL; /**< Lookup Table Data Register., offset: 0xB00 */ + __IO uint32_t LUT_CTRL; /**< Look Up Table Control Register, offset: 0xB00 */ + uint8_t RESERVED_12[12]; + __IO uint32_t LUT0_ADDR; /**< Lookup Table 0 Index Register, offset: 0xB10 */ + uint8_t RESERVED_13[12]; + __IO uint32_t LUT0_DATA; /**< Lookup Table 0 Data Register, offset: 0xB20 */ uint8_t RESERVED_14[12]; - __IO uint32_t LUT0_ADDR; /**< Lookup Table Control Register., offset: 0xB10 */ + __IO uint32_t LUT1_ADDR; /**< Lookup Table 1 Index Register, offset: 0xB30 */ uint8_t RESERVED_15[12]; - __IO uint32_t LUT0_DATA; /**< Lookup Table Data Register., offset: 0xB20 */ - uint8_t RESERVED_16[12]; - __IO uint32_t LUT1_ADDR; /**< Lookup Table Control Register., offset: 0xB30 */ - uint8_t RESERVED_17[12]; - __IO uint32_t LUT1_DATA; /**< Lookup Table Data Register., offset: 0xB40 */ + __IO uint32_t LUT1_DATA; /**< Lookup Table 1 Data Register, offset: 0xB40 */ } LCDIF_Type; /* ---------------------------------------------------------------------------- @@ -56862,9 +66625,11 @@ typedef struct { /*! @name CTRL - LCDIF General Control Register */ /*! @{ */ + #define LCDIF_CTRL_RUN_MASK (0x1U) #define LCDIF_CTRL_RUN_SHIFT (0U) #define LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK) + #define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U) #define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U) /*! DATA_FORMAT_24_BIT @@ -56873,6 +66638,7 @@ typedef struct { * each byte do not contain any useful data, and should be dropped. */ #define LCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK) + #define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U) #define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U) /*! DATA_FORMAT_18_BIT @@ -56880,18 +66646,23 @@ typedef struct { * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. */ #define LCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK) + #define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U) #define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U) #define LCDIF_CTRL_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK) + #define LCDIF_CTRL_RSRVD0_MASK (0x10U) #define LCDIF_CTRL_RSRVD0_SHIFT (4U) #define LCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK) + #define LCDIF_CTRL_MASTER_MASK (0x20U) #define LCDIF_CTRL_MASTER_SHIFT (5U) #define LCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK) + #define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK (0x40U) #define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT (6U) #define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK) + #define LCDIF_CTRL_WORD_LENGTH_MASK (0x300U) #define LCDIF_CTRL_WORD_LENGTH_SHIFT (8U) /*! WORD_LENGTH @@ -56901,6 +66672,7 @@ typedef struct { * 0b11..Input data is 24 bits per pixel. */ #define LCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK) + #define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U) #define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U) /*! LCD_DATABUS_WIDTH @@ -56910,6 +66682,7 @@ typedef struct { * 0b11..24-bit data bus mode. */ #define LCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK) + #define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U) #define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U) /*! CSC_DATA_SWIZZLE @@ -56921,6 +66694,7 @@ typedef struct { * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK) + #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U) #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U) /*! INPUT_DATA_SWIZZLE @@ -56932,18 +66706,19 @@ typedef struct { * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK) + #define LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U) #define LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U) #define LCDIF_CTRL_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK) -#define LCDIF_CTRL_VSYNC_MODE_MASK (0x40000U) -#define LCDIF_CTRL_VSYNC_MODE_SHIFT (18U) -#define LCDIF_CTRL_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_VSYNC_MODE_MASK) + #define LCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U) #define LCDIF_CTRL_BYPASS_COUNT_SHIFT (19U) #define LCDIF_CTRL_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK) + #define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3E00000U) #define LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U) #define LCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK) + #define LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U) #define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U) /*! DATA_SHIFT_DIR @@ -56951,12 +66726,11 @@ typedef struct { * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. */ #define LCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK) -#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) -#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) -#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_MASK) + #define LCDIF_CTRL_CLKGATE_MASK (0x40000000U) #define LCDIF_CTRL_CLKGATE_SHIFT (30U) #define LCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK) + #define LCDIF_CTRL_SFTRST_MASK (0x80000000U) #define LCDIF_CTRL_SFTRST_SHIFT (31U) #define LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK) @@ -56964,9 +66738,11 @@ typedef struct { /*! @name CTRL_SET - LCDIF General Control Register */ /*! @{ */ + #define LCDIF_CTRL_SET_RUN_MASK (0x1U) #define LCDIF_CTRL_SET_RUN_SHIFT (0U) #define LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK) + #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U) #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U) /*! DATA_FORMAT_24_BIT @@ -56975,6 +66751,7 @@ typedef struct { * each byte do not contain any useful data, and should be dropped. */ #define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK) + #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U) #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U) /*! DATA_FORMAT_18_BIT @@ -56982,18 +66759,23 @@ typedef struct { * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. */ #define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK) + #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U) #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U) #define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK) + #define LCDIF_CTRL_SET_RSRVD0_MASK (0x10U) #define LCDIF_CTRL_SET_RSRVD0_SHIFT (4U) #define LCDIF_CTRL_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK) + #define LCDIF_CTRL_SET_MASTER_MASK (0x20U) #define LCDIF_CTRL_SET_MASTER_SHIFT (5U) #define LCDIF_CTRL_SET_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK) + #define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U) #define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U) #define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK) + #define LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U) #define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U) /*! WORD_LENGTH @@ -57003,6 +66785,7 @@ typedef struct { * 0b11..Input data is 24 bits per pixel. */ #define LCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK) + #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U) #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U) /*! LCD_DATABUS_WIDTH @@ -57012,6 +66795,7 @@ typedef struct { * 0b11..24-bit data bus mode. */ #define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK) + #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U) #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U) /*! CSC_DATA_SWIZZLE @@ -57023,6 +66807,7 @@ typedef struct { * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK) + #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U) #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U) /*! INPUT_DATA_SWIZZLE @@ -57034,18 +66819,19 @@ typedef struct { * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK) + #define LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U) #define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U) #define LCDIF_CTRL_SET_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK) -#define LCDIF_CTRL_SET_VSYNC_MODE_MASK (0x40000U) -#define LCDIF_CTRL_SET_VSYNC_MODE_SHIFT (18U) -#define LCDIF_CTRL_SET_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_SET_VSYNC_MODE_MASK) + #define LCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U) #define LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U) #define LCDIF_CTRL_SET_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK) + #define LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3E00000U) #define LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U) #define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK) + #define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U) #define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U) /*! DATA_SHIFT_DIR @@ -57053,12 +66839,11 @@ typedef struct { * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. */ #define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK) -#define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) -#define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) -#define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_MASK) + #define LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U) #define LCDIF_CTRL_SET_CLKGATE_SHIFT (30U) #define LCDIF_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK) + #define LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U) #define LCDIF_CTRL_SET_SFTRST_SHIFT (31U) #define LCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK) @@ -57066,9 +66851,11 @@ typedef struct { /*! @name CTRL_CLR - LCDIF General Control Register */ /*! @{ */ + #define LCDIF_CTRL_CLR_RUN_MASK (0x1U) #define LCDIF_CTRL_CLR_RUN_SHIFT (0U) #define LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK) + #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U) #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U) /*! DATA_FORMAT_24_BIT @@ -57077,6 +66864,7 @@ typedef struct { * each byte do not contain any useful data, and should be dropped. */ #define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK) + #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U) #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U) /*! DATA_FORMAT_18_BIT @@ -57084,18 +66872,23 @@ typedef struct { * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. */ #define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK) + #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U) #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U) #define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK) + #define LCDIF_CTRL_CLR_RSRVD0_MASK (0x10U) #define LCDIF_CTRL_CLR_RSRVD0_SHIFT (4U) #define LCDIF_CTRL_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK) + #define LCDIF_CTRL_CLR_MASTER_MASK (0x20U) #define LCDIF_CTRL_CLR_MASTER_SHIFT (5U) #define LCDIF_CTRL_CLR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK) + #define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U) #define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U) #define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK) + #define LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U) #define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U) /*! WORD_LENGTH @@ -57105,6 +66898,7 @@ typedef struct { * 0b11..Input data is 24 bits per pixel. */ #define LCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK) + #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U) #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U) /*! LCD_DATABUS_WIDTH @@ -57114,6 +66908,7 @@ typedef struct { * 0b11..24-bit data bus mode. */ #define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK) + #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U) #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U) /*! CSC_DATA_SWIZZLE @@ -57125,6 +66920,7 @@ typedef struct { * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK) + #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U) #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U) /*! INPUT_DATA_SWIZZLE @@ -57136,18 +66932,19 @@ typedef struct { * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK) + #define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U) #define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U) #define LCDIF_CTRL_CLR_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK) -#define LCDIF_CTRL_CLR_VSYNC_MODE_MASK (0x40000U) -#define LCDIF_CTRL_CLR_VSYNC_MODE_SHIFT (18U) -#define LCDIF_CTRL_CLR_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_CLR_VSYNC_MODE_MASK) + #define LCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U) #define LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U) #define LCDIF_CTRL_CLR_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK) + #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3E00000U) #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U) #define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK) + #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U) #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U) /*! DATA_SHIFT_DIR @@ -57155,12 +66952,11 @@ typedef struct { * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. */ #define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK) -#define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) -#define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) -#define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_MASK) + #define LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U) #define LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U) #define LCDIF_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK) + #define LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U) #define LCDIF_CTRL_CLR_SFTRST_SHIFT (31U) #define LCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK) @@ -57168,9 +66964,11 @@ typedef struct { /*! @name CTRL_TOG - LCDIF General Control Register */ /*! @{ */ + #define LCDIF_CTRL_TOG_RUN_MASK (0x1U) #define LCDIF_CTRL_TOG_RUN_SHIFT (0U) #define LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK) + #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U) #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U) /*! DATA_FORMAT_24_BIT @@ -57179,6 +66977,7 @@ typedef struct { * each byte do not contain any useful data, and should be dropped. */ #define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK) + #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U) #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U) /*! DATA_FORMAT_18_BIT @@ -57186,18 +66985,23 @@ typedef struct { * 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data. */ #define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK) + #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U) #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U) #define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK) + #define LCDIF_CTRL_TOG_RSRVD0_MASK (0x10U) #define LCDIF_CTRL_TOG_RSRVD0_SHIFT (4U) #define LCDIF_CTRL_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK) + #define LCDIF_CTRL_TOG_MASTER_MASK (0x20U) #define LCDIF_CTRL_TOG_MASTER_SHIFT (5U) #define LCDIF_CTRL_TOG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK) + #define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U) #define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U) #define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK) + #define LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U) #define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U) /*! WORD_LENGTH @@ -57207,6 +67011,7 @@ typedef struct { * 0b11..Input data is 24 bits per pixel. */ #define LCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK) + #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U) #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U) /*! LCD_DATABUS_WIDTH @@ -57216,6 +67021,7 @@ typedef struct { * 0b11..24-bit data bus mode. */ #define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK) + #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U) #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U) /*! CSC_DATA_SWIZZLE @@ -57227,6 +67033,7 @@ typedef struct { * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK) + #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U) #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U) /*! INPUT_DATA_SWIZZLE @@ -57238,18 +67045,19 @@ typedef struct { * 0b11..Swap bytes within each half-word. */ #define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK) + #define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U) #define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U) #define LCDIF_CTRL_TOG_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK) -#define LCDIF_CTRL_TOG_VSYNC_MODE_MASK (0x40000U) -#define LCDIF_CTRL_TOG_VSYNC_MODE_SHIFT (18U) -#define LCDIF_CTRL_TOG_VSYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_TOG_VSYNC_MODE_MASK) + #define LCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U) #define LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U) #define LCDIF_CTRL_TOG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK) + #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3E00000U) #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U) #define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK) + #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U) #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U) /*! DATA_SHIFT_DIR @@ -57257,12 +67065,11 @@ typedef struct { * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits. */ #define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK) -#define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U) -#define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_SHIFT (27U) -#define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_MASK) + #define LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U) #define LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U) #define LCDIF_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK) + #define LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U) #define LCDIF_CTRL_TOG_SFTRST_SHIFT (31U) #define LCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK) @@ -57270,9 +67077,11 @@ typedef struct { /*! @name CTRL1 - LCDIF General Control1 Register */ /*! @{ */ + #define LCDIF_CTRL1_RSRVD0_MASK (0xF8U) #define LCDIF_CTRL1_RSRVD0_SHIFT (3U) #define LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK) + #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U) #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U) /*! VSYNC_EDGE_IRQ @@ -57280,6 +67089,7 @@ typedef struct { * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK) + #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U) #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U) /*! CUR_FRAME_DONE_IRQ @@ -57287,6 +67097,7 @@ typedef struct { * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK) + #define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U) #define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U) /*! UNDERFLOW_IRQ @@ -57294,6 +67105,7 @@ typedef struct { * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK) + #define LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U) #define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U) /*! OVERFLOW_IRQ @@ -57301,36 +67113,47 @@ typedef struct { * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK) + #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U) #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK) + #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK) + #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U) #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U) #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK) + #define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U) #define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U) #define LCDIF_CTRL1_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK) + #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xF0000U) #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U) #define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK) + #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK) + #define LCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U) #define LCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U) #define LCDIF_CTRL1_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK) + #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK) + #define LCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U) #define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U) #define LCDIF_CTRL1_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK) + #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U) #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK) + #define LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U) #define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U) /*! BM_ERROR_IRQ @@ -57338,12 +67161,15 @@ typedef struct { * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK) + #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U) #define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U) #define LCDIF_CTRL1_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK) + #define LCDIF_CTRL1_CS_OUT_SELECT_MASK (0x40000000U) #define LCDIF_CTRL1_CS_OUT_SELECT_SHIFT (30U) #define LCDIF_CTRL1_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CS_OUT_SELECT_MASK) + #define LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK (0x80000000U) #define LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT (31U) #define LCDIF_CTRL1_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK) @@ -57351,9 +67177,11 @@ typedef struct { /*! @name CTRL1_SET - LCDIF General Control1 Register */ /*! @{ */ + #define LCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U) #define LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U) #define LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK) + #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U) #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U) /*! VSYNC_EDGE_IRQ @@ -57361,6 +67189,7 @@ typedef struct { * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK) + #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U) #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U) /*! CUR_FRAME_DONE_IRQ @@ -57368,6 +67197,7 @@ typedef struct { * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK) + #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U) #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U) /*! UNDERFLOW_IRQ @@ -57375,6 +67205,7 @@ typedef struct { * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK) + #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U) #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U) /*! OVERFLOW_IRQ @@ -57382,36 +67213,47 @@ typedef struct { * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK) + #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U) #define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK) + #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) #define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK) + #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U) #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U) #define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK) + #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U) #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U) #define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK) + #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U) #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U) #define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK) + #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) #define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK) + #define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U) #define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U) #define LCDIF_CTRL1_SET_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK) + #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) #define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK) + #define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U) #define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U) #define LCDIF_CTRL1_SET_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK) + #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U) #define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK) + #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U) #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U) /*! BM_ERROR_IRQ @@ -57419,12 +67261,15 @@ typedef struct { * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK) + #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U) #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U) #define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK) + #define LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK (0x40000000U) #define LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT (30U) #define LCDIF_CTRL1_SET_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK) + #define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK (0x80000000U) #define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT (31U) #define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK) @@ -57432,9 +67277,11 @@ typedef struct { /*! @name CTRL1_CLR - LCDIF General Control1 Register */ /*! @{ */ + #define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U) #define LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U) #define LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK) + #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U) #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U) /*! VSYNC_EDGE_IRQ @@ -57442,6 +67289,7 @@ typedef struct { * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK) + #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U) #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U) /*! CUR_FRAME_DONE_IRQ @@ -57449,6 +67297,7 @@ typedef struct { * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK) + #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U) #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U) /*! UNDERFLOW_IRQ @@ -57456,6 +67305,7 @@ typedef struct { * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK) + #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U) #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U) /*! OVERFLOW_IRQ @@ -57463,36 +67313,47 @@ typedef struct { * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK) + #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U) #define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK) + #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) #define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK) + #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U) #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U) #define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK) + #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U) #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U) #define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK) + #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U) #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U) #define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK) + #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) #define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK) + #define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U) #define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U) #define LCDIF_CTRL1_CLR_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK) + #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) #define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK) + #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U) #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U) #define LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK) + #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U) #define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK) + #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U) #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U) /*! BM_ERROR_IRQ @@ -57500,12 +67361,15 @@ typedef struct { * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK) + #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U) #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U) #define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK) + #define LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK (0x40000000U) #define LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT (30U) #define LCDIF_CTRL1_CLR_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK) + #define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK (0x80000000U) #define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT (31U) #define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK) @@ -57513,9 +67377,11 @@ typedef struct { /*! @name CTRL1_TOG - LCDIF General Control1 Register */ /*! @{ */ + #define LCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U) #define LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U) #define LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK) + #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U) #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U) /*! VSYNC_EDGE_IRQ @@ -57523,6 +67389,7 @@ typedef struct { * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK) + #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U) #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U) /*! CUR_FRAME_DONE_IRQ @@ -57530,6 +67397,7 @@ typedef struct { * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK) + #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U) #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U) /*! UNDERFLOW_IRQ @@ -57537,6 +67405,7 @@ typedef struct { * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK) + #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U) #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U) /*! OVERFLOW_IRQ @@ -57544,36 +67413,47 @@ typedef struct { * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK) + #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U) #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U) #define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK) + #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U) #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U) #define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK) + #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U) #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U) #define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK) + #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U) #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U) #define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK) + #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U) #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U) #define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK) + #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U) #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U) #define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK) + #define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U) #define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U) #define LCDIF_CTRL1_TOG_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK) + #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U) #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U) #define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK) + #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U) #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U) #define LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK) + #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U) #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U) #define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK) + #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U) #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U) /*! BM_ERROR_IRQ @@ -57581,12 +67461,15 @@ typedef struct { * 0b1..Interrupt Request Pending. */ #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK) + #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U) #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U) #define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK) + #define LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK (0x40000000U) #define LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT (30U) #define LCDIF_CTRL1_TOG_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK) + #define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK (0x80000000U) #define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT (31U) #define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK) @@ -57594,9 +67477,11 @@ typedef struct { /*! @name CTRL2 - LCDIF General Control2 Register */ /*! @{ */ + #define LCDIF_CTRL2_RSRVD0_MASK (0xFFFU) #define LCDIF_CTRL2_RSRVD0_SHIFT (0U) #define LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK) + #define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U) #define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U) /*! EVEN_LINE_PATTERN @@ -57608,9 +67493,11 @@ typedef struct { * 0b101..BGR */ #define LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK) + #define LCDIF_CTRL2_RSRVD3_MASK (0x8000U) #define LCDIF_CTRL2_RSRVD3_SHIFT (15U) #define LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK) + #define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U) #define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U) /*! ODD_LINE_PATTERN @@ -57622,12 +67509,15 @@ typedef struct { * 0b101..BGR */ #define LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK) + #define LCDIF_CTRL2_RSRVD4_MASK (0x80000U) #define LCDIF_CTRL2_RSRVD4_SHIFT (19U) #define LCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK) + #define LCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U) #define LCDIF_CTRL2_BURST_LEN_8_SHIFT (20U) #define LCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK) + #define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U) #define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U) /*! OUTSTANDING_REQS @@ -57638,6 +67528,7 @@ typedef struct { * 0b100..REQ_16 */ #define LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK) + #define LCDIF_CTRL2_RSRVD5_MASK (0xFF000000U) #define LCDIF_CTRL2_RSRVD5_SHIFT (24U) #define LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK) @@ -57645,9 +67536,11 @@ typedef struct { /*! @name CTRL2_SET - LCDIF General Control2 Register */ /*! @{ */ + #define LCDIF_CTRL2_SET_RSRVD0_MASK (0xFFFU) #define LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U) #define LCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK) + #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U) #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U) /*! EVEN_LINE_PATTERN @@ -57659,9 +67552,11 @@ typedef struct { * 0b101..BGR */ #define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK) + #define LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U) #define LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U) #define LCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK) + #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U) #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U) /*! ODD_LINE_PATTERN @@ -57673,12 +67568,15 @@ typedef struct { * 0b101..BGR */ #define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK) + #define LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U) #define LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U) #define LCDIF_CTRL2_SET_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK) + #define LCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U) #define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U) #define LCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK) + #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U) #define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U) /*! OUTSTANDING_REQS @@ -57689,6 +67587,7 @@ typedef struct { * 0b100..REQ_16 */ #define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK) + #define LCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U) #define LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U) #define LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK) @@ -57696,9 +67595,11 @@ typedef struct { /*! @name CTRL2_CLR - LCDIF General Control2 Register */ /*! @{ */ + #define LCDIF_CTRL2_CLR_RSRVD0_MASK (0xFFFU) #define LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U) #define LCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK) + #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U) #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U) /*! EVEN_LINE_PATTERN @@ -57710,9 +67611,11 @@ typedef struct { * 0b101..BGR */ #define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK) + #define LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U) #define LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U) #define LCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK) + #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U) #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U) /*! ODD_LINE_PATTERN @@ -57724,12 +67627,15 @@ typedef struct { * 0b101..BGR */ #define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK) + #define LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U) #define LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U) #define LCDIF_CTRL2_CLR_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK) + #define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U) #define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U) #define LCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK) + #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U) #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U) /*! OUTSTANDING_REQS @@ -57740,6 +67646,7 @@ typedef struct { * 0b100..REQ_16 */ #define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK) + #define LCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U) #define LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U) #define LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK) @@ -57747,9 +67654,11 @@ typedef struct { /*! @name CTRL2_TOG - LCDIF General Control2 Register */ /*! @{ */ + #define LCDIF_CTRL2_TOG_RSRVD0_MASK (0xFFFU) #define LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U) #define LCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK) + #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U) #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U) /*! EVEN_LINE_PATTERN @@ -57761,9 +67670,11 @@ typedef struct { * 0b101..BGR */ #define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK) + #define LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U) #define LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U) #define LCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK) + #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U) #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U) /*! ODD_LINE_PATTERN @@ -57775,12 +67686,15 @@ typedef struct { * 0b101..BGR */ #define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK) + #define LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U) #define LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U) #define LCDIF_CTRL2_TOG_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK) + #define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U) #define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U) #define LCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK) + #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U) #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U) /*! OUTSTANDING_REQS @@ -57791,6 +67705,7 @@ typedef struct { * 0b100..REQ_16 */ #define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK) + #define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U) #define LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U) #define LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK) @@ -57798,9 +67713,11 @@ typedef struct { /*! @name TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register */ /*! @{ */ + #define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU) #define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U) #define LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK) + #define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U) #define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U) #define LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK) @@ -57808,6 +67725,7 @@ typedef struct { /*! @name CUR_BUF - LCD Interface Current Buffer Address Register */ /*! @{ */ + #define LCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU) #define LCDIF_CUR_BUF_ADDR_SHIFT (0U) #define LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK) @@ -57815,62 +67733,59 @@ typedef struct { /*! @name NEXT_BUF - LCD Interface Next Buffer Address Register */ /*! @{ */ + #define LCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU) #define LCDIF_NEXT_BUF_ADDR_SHIFT (0U) #define LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK) /*! @} */ -/*! @name TIMING - LCD Interface Timing Register */ -/*! @{ */ -#define LCDIF_TIMING_DATA_SETUP_MASK (0xFFU) -#define LCDIF_TIMING_DATA_SETUP_SHIFT (0U) -#define LCDIF_TIMING_DATA_SETUP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_DATA_SETUP_SHIFT)) & LCDIF_TIMING_DATA_SETUP_MASK) -#define LCDIF_TIMING_DATA_HOLD_MASK (0xFF00U) -#define LCDIF_TIMING_DATA_HOLD_SHIFT (8U) -#define LCDIF_TIMING_DATA_HOLD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_DATA_HOLD_SHIFT)) & LCDIF_TIMING_DATA_HOLD_MASK) -#define LCDIF_TIMING_CMD_SETUP_MASK (0xFF0000U) -#define LCDIF_TIMING_CMD_SETUP_SHIFT (16U) -#define LCDIF_TIMING_CMD_SETUP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_CMD_SETUP_SHIFT)) & LCDIF_TIMING_CMD_SETUP_MASK) -#define LCDIF_TIMING_CMD_HOLD_MASK (0xFF000000U) -#define LCDIF_TIMING_CMD_HOLD_SHIFT (24U) -#define LCDIF_TIMING_CMD_HOLD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_CMD_HOLD_SHIFT)) & LCDIF_TIMING_CMD_HOLD_MASK) -/*! @} */ - /*! @name VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ /*! @{ */ + #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U) #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK) + #define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U) #define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U) #define LCDIF_VDCTRL0_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK) + #define LCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U) #define LCDIF_VDCTRL0_HALF_LINE_SHIFT (19U) #define LCDIF_VDCTRL0_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK) + #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK) + #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U) #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U) #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK) + #define LCDIF_VDCTRL0_RSRVD1_MASK (0xC00000U) #define LCDIF_VDCTRL0_RSRVD1_SHIFT (22U) #define LCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK) + #define LCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U) #define LCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U) #define LCDIF_VDCTRL0_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK) + #define LCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U) #define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U) #define LCDIF_VDCTRL0_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK) + #define LCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U) #define LCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U) #define LCDIF_VDCTRL0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK) + #define LCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U) #define LCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U) #define LCDIF_VDCTRL0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK) + #define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U) #define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U) #define LCDIF_VDCTRL0_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK) + #define LCDIF_VDCTRL0_VSYNC_OEB_MASK (0x20000000U) #define LCDIF_VDCTRL0_VSYNC_OEB_SHIFT (29U) /*! VSYNC_OEB @@ -57878,6 +67793,7 @@ typedef struct { * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. */ #define LCDIF_VDCTRL0_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_VSYNC_OEB_MASK) + #define LCDIF_VDCTRL0_RSRVD2_MASK (0xC0000000U) #define LCDIF_VDCTRL0_RSRVD2_SHIFT (30U) #define LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK) @@ -57885,39 +67801,51 @@ typedef struct { /*! @name VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ /*! @{ */ + #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U) #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK) + #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U) #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U) #define LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK) + #define LCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U) #define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U) #define LCDIF_VDCTRL0_SET_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK) + #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) #define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK) + #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U) #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U) #define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK) + #define LCDIF_VDCTRL0_SET_RSRVD1_MASK (0xC00000U) #define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U) #define LCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK) + #define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U) #define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U) #define LCDIF_VDCTRL0_SET_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK) + #define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U) #define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U) #define LCDIF_VDCTRL0_SET_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK) + #define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U) #define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U) #define LCDIF_VDCTRL0_SET_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK) + #define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U) #define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U) #define LCDIF_VDCTRL0_SET_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK) + #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U) #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U) #define LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK) + #define LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK (0x20000000U) #define LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT (29U) /*! VSYNC_OEB @@ -57925,6 +67853,7 @@ typedef struct { * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. */ #define LCDIF_VDCTRL0_SET_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK) + #define LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xC0000000U) #define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (30U) #define LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK) @@ -57932,39 +67861,51 @@ typedef struct { /*! @name VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ /*! @{ */ + #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U) #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK) + #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U) #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U) #define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK) + #define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U) #define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U) #define LCDIF_VDCTRL0_CLR_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK) + #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) #define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK) + #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U) #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U) #define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK) + #define LCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xC00000U) #define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U) #define LCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK) + #define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U) #define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U) #define LCDIF_VDCTRL0_CLR_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK) + #define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U) #define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U) #define LCDIF_VDCTRL0_CLR_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK) + #define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U) #define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U) #define LCDIF_VDCTRL0_CLR_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK) + #define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U) #define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U) #define LCDIF_VDCTRL0_CLR_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK) + #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U) #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U) #define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK) + #define LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK (0x20000000U) #define LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT (29U) /*! VSYNC_OEB @@ -57972,6 +67913,7 @@ typedef struct { * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. */ #define LCDIF_VDCTRL0_CLR_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK) + #define LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xC0000000U) #define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (30U) #define LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK) @@ -57979,39 +67921,51 @@ typedef struct { /*! @name VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */ /*! @{ */ + #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU) #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U) #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK) + #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U) #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U) #define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK) + #define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U) #define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U) #define LCDIF_VDCTRL0_TOG_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK) + #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U) #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U) #define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK) + #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U) #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U) #define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK) + #define LCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xC00000U) #define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U) #define LCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK) + #define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U) #define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U) #define LCDIF_VDCTRL0_TOG_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK) + #define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U) #define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U) #define LCDIF_VDCTRL0_TOG_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK) + #define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U) #define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U) #define LCDIF_VDCTRL0_TOG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK) + #define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U) #define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U) #define LCDIF_VDCTRL0_TOG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK) + #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U) #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U) #define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK) + #define LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK (0x20000000U) #define LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT (29U) /*! VSYNC_OEB @@ -58019,6 +67973,7 @@ typedef struct { * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block. */ #define LCDIF_VDCTRL0_TOG_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK) + #define LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xC0000000U) #define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (30U) #define LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK) @@ -58026,6 +67981,7 @@ typedef struct { /*! @name VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1 */ /*! @{ */ + #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU) #define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U) #define LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK) @@ -58033,9 +67989,11 @@ typedef struct { /*! @name VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2 */ /*! @{ */ + #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU) #define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U) #define LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK) + #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U) #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U) #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK) @@ -58043,18 +68001,23 @@ typedef struct { /*! @name VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3 */ /*! @{ */ + #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU) #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U) #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK) + #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xFFF0000U) #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U) #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK) + #define LCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U) #define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U) #define LCDIF_VDCTRL3_VSYNC_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK) + #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U) #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U) #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK) + #define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U) #define LCDIF_VDCTRL3_RSRVD0_SHIFT (30U) #define LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK) @@ -58062,15 +68025,19 @@ typedef struct { /*! @name VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4 */ /*! @{ */ + #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU) #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U) #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK) + #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U) #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U) #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK) + #define LCDIF_VDCTRL4_RSRVD0_MASK (0x1FF80000U) #define LCDIF_VDCTRL4_RSRVD0_SHIFT (19U) #define LCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK) + #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U) #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U) #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK) @@ -58078,6 +68045,7 @@ typedef struct { /*! @name BM_ERROR_STAT - Bus Master Error Status Register */ /*! @{ */ + #define LCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU) #define LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U) #define LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK) @@ -58085,6 +68053,7 @@ typedef struct { /*! @name CRC_STAT - CRC Status Register */ /*! @{ */ + #define LCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU) #define LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U) #define LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK) @@ -58092,27 +68061,35 @@ typedef struct { /*! @name STAT - LCD Interface Status Register */ /*! @{ */ + #define LCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU) #define LCDIF_STAT_LFIFO_COUNT_SHIFT (0U) #define LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK) + #define LCDIF_STAT_RSRVD0_MASK (0x1FFFE00U) #define LCDIF_STAT_RSRVD0_SHIFT (9U) #define LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK) + #define LCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U) #define LCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U) #define LCDIF_STAT_TXFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK) + #define LCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U) #define LCDIF_STAT_TXFIFO_FULL_SHIFT (27U) #define LCDIF_STAT_TXFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK) + #define LCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U) #define LCDIF_STAT_LFIFO_EMPTY_SHIFT (28U) #define LCDIF_STAT_LFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK) + #define LCDIF_STAT_LFIFO_FULL_MASK (0x20000000U) #define LCDIF_STAT_LFIFO_FULL_SHIFT (29U) #define LCDIF_STAT_LFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK) + #define LCDIF_STAT_DMA_REQ_MASK (0x40000000U) #define LCDIF_STAT_DMA_REQ_SHIFT (30U) #define LCDIF_STAT_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DMA_REQ_SHIFT)) & LCDIF_STAT_DMA_REQ_MASK) + #define LCDIF_STAT_PRESENT_MASK (0x80000000U) #define LCDIF_STAT_PRESENT_SHIFT (31U) #define LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK) @@ -58120,35 +68097,31 @@ typedef struct { /*! @name THRES - LCDIF Threshold Register */ /*! @{ */ + #define LCDIF_THRES_RSRVD_MASK (0x1FFU) #define LCDIF_THRES_RSRVD_SHIFT (0U) #define LCDIF_THRES_RSRVD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD_SHIFT)) & LCDIF_THRES_RSRVD_MASK) + #define LCDIF_THRES_RSRVD1_MASK (0xFE00U) #define LCDIF_THRES_RSRVD1_SHIFT (9U) #define LCDIF_THRES_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK) + #define LCDIF_THRES_FASTCLOCK_MASK (0x1FF0000U) #define LCDIF_THRES_FASTCLOCK_SHIFT (16U) #define LCDIF_THRES_FASTCLOCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK) + #define LCDIF_THRES_RSRVD2_MASK (0xFE000000U) #define LCDIF_THRES_RSRVD2_SHIFT (25U) #define LCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK) /*! @} */ -/*! @name SYNC_DELAY - LCD working insync mode with CSI for VSYNC delay */ -/*! @{ */ -#define LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK (0xFFFFU) -#define LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT (0U) -#define LCDIF_SYNC_DELAY_H_COUNT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT)) & LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK) -#define LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK (0xFFFF0000U) -#define LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT (16U) -#define LCDIF_SYNC_DELAY_V_COUNT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT)) & LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK) -/*! @} */ - /*! @name PIGEONCTRL0 - LCDIF Pigeon Mode Control0 Register */ /*! @{ */ + #define LCDIF_PIGEONCTRL0_FD_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL0_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_FD_PERIOD_MASK) + #define LCDIF_PIGEONCTRL0_LD_PERIOD_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT (16U) #define LCDIF_PIGEONCTRL0_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_LD_PERIOD_MASK) @@ -58156,9 +68129,11 @@ typedef struct { /*! @name PIGEONCTRL0_SET - LCDIF Pigeon Mode Control0 Register */ /*! @{ */ + #define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL0_SET_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK) + #define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT (16U) #define LCDIF_PIGEONCTRL0_SET_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK) @@ -58166,9 +68141,11 @@ typedef struct { /*! @name PIGEONCTRL0_CLR - LCDIF Pigeon Mode Control0 Register */ /*! @{ */ + #define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK) + #define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT (16U) #define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK) @@ -58176,9 +68153,11 @@ typedef struct { /*! @name PIGEONCTRL0_TOG - LCDIF Pigeon Mode Control0 Register */ /*! @{ */ + #define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK) + #define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT (16U) #define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK) @@ -58186,9 +68165,11 @@ typedef struct { /*! @name PIGEONCTRL1 - LCDIF Pigeon Mode Control1 Register */ /*! @{ */ + #define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK) + #define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT (16U) #define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK) @@ -58196,9 +68177,11 @@ typedef struct { /*! @name PIGEONCTRL1_SET - LCDIF Pigeon Mode Control1 Register */ /*! @{ */ + #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK) + #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT (16U) #define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK) @@ -58206,9 +68189,11 @@ typedef struct { /*! @name PIGEONCTRL1_CLR - LCDIF Pigeon Mode Control1 Register */ /*! @{ */ + #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK) + #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT (16U) #define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK) @@ -58216,9 +68201,11 @@ typedef struct { /*! @name PIGEONCTRL1_TOG - LCDIF Pigeon Mode Control1 Register */ /*! @{ */ + #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK (0xFFFU) #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT (0U) #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK) + #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK (0xFFF0000U) #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT (16U) #define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK) @@ -58226,9 +68213,11 @@ typedef struct { /*! @name PIGEONCTRL2 - LCDIF Pigeon Mode Control2 Register */ /*! @{ */ + #define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK (0x1U) #define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT (0U) #define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK) + #define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK (0x2U) #define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT (1U) #define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK) @@ -58236,9 +68225,11 @@ typedef struct { /*! @name PIGEONCTRL2_SET - LCDIF Pigeon Mode Control2 Register */ /*! @{ */ + #define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK (0x1U) #define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT (0U) #define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK) + #define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK (0x2U) #define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT (1U) #define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK) @@ -58246,9 +68237,11 @@ typedef struct { /*! @name PIGEONCTRL2_CLR - LCDIF Pigeon Mode Control2 Register */ /*! @{ */ + #define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK (0x1U) #define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT (0U) #define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK) + #define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK (0x2U) #define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT (1U) #define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK) @@ -58256,9 +68249,11 @@ typedef struct { /*! @name PIGEONCTRL2_TOG - LCDIF Pigeon Mode Control2 Register */ /*! @{ */ + #define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK (0x1U) #define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT (0U) #define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK) + #define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK (0x2U) #define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT (1U) #define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK) @@ -58266,9 +68261,11 @@ typedef struct { /*! @name PIGEON_0 - Panel Interface Signal Generator Register */ /*! @{ */ + #define LCDIF_PIGEON_0_EN_MASK (0x1U) #define LCDIF_PIGEON_0_EN_SHIFT (0U) #define LCDIF_PIGEON_0_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_EN_SHIFT)) & LCDIF_PIGEON_0_EN_MASK) + #define LCDIF_PIGEON_0_POL_MASK (0x2U) #define LCDIF_PIGEON_0_POL_SHIFT (1U) /*! POL @@ -58276,6 +68273,7 @@ typedef struct { * 0b1..Inverted signal (Active low) */ #define LCDIF_PIGEON_0_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_POL_SHIFT)) & LCDIF_PIGEON_0_POL_MASK) + #define LCDIF_PIGEON_0_INC_SEL_MASK (0xCU) #define LCDIF_PIGEON_0_INC_SEL_SHIFT (2U) /*! INC_SEL @@ -58285,9 +68283,11 @@ typedef struct { * 0b11..Use another signal as tick event */ #define LCDIF_PIGEON_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_0_INC_SEL_MASK) + #define LCDIF_PIGEON_0_OFFSET_MASK (0xF0U) #define LCDIF_PIGEON_0_OFFSET_SHIFT (4U) #define LCDIF_PIGEON_0_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_OFFSET_SHIFT)) & LCDIF_PIGEON_0_OFFSET_MASK) + #define LCDIF_PIGEON_0_MASK_CNT_SEL_MASK (0xF00U) #define LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT (8U) /*! MASK_CNT_SEL @@ -58301,9 +68301,11 @@ typedef struct { * 0b0111..vertical counter (line counter within one frame) */ #define LCDIF_PIGEON_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_SEL_MASK) + #define LCDIF_PIGEON_0_MASK_CNT_MASK (0xFFF000U) #define LCDIF_PIGEON_0_MASK_CNT_SHIFT (12U) #define LCDIF_PIGEON_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_MASK) + #define LCDIF_PIGEON_0_STATE_MASK_MASK (0xFF000000U) #define LCDIF_PIGEON_0_STATE_MASK_SHIFT (24U) /*! STATE_MASK @@ -58324,12 +68326,14 @@ typedef struct { /*! @name PIGEON_1 - Panel Interface Signal Generator Register */ /*! @{ */ + #define LCDIF_PIGEON_1_SET_CNT_MASK (0xFFFFU) #define LCDIF_PIGEON_1_SET_CNT_SHIFT (0U) /*! SET_CNT * 0b0000000000000000..Start as active */ #define LCDIF_PIGEON_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK) + #define LCDIF_PIGEON_1_CLR_CNT_MASK (0xFFFF0000U) #define LCDIF_PIGEON_1_CLR_CNT_SHIFT (16U) /*! CLR_CNT @@ -58343,6 +68347,7 @@ typedef struct { /*! @name PIGEON_2 - Panel Interface Signal Generator Register */ /*! @{ */ + #define LCDIF_PIGEON_2_SIG_LOGIC_MASK (0xFU) #define LCDIF_PIGEON_2_SIG_LOGIC_SHIFT (0U) /*! SIG_LOGIC @@ -58352,12 +68357,14 @@ typedef struct { * 0b0011..mask = sig_another AND other_masks */ #define LCDIF_PIGEON_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK) + #define LCDIF_PIGEON_2_SIG_ANOTHER_MASK (0x1F0U) #define LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT (4U) /*! SIG_ANOTHER * 0b00000..Keep active until mask off */ #define LCDIF_PIGEON_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_2_SIG_ANOTHER_MASK) + #define LCDIF_PIGEON_2_RSVD_MASK (0xFFFFFE00U) #define LCDIF_PIGEON_2_RSVD_SHIFT (9U) #define LCDIF_PIGEON_2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_RSVD_SHIFT)) & LCDIF_PIGEON_2_RSVD_MASK) @@ -58366,36 +68373,41 @@ typedef struct { /* The count of LCDIF_PIGEON_2 */ #define LCDIF_PIGEON_2_COUNT (12U) -/*! @name LUT_CTRL - Lookup Table Data Register. */ +/*! @name LUT_CTRL - Look Up Table Control Register */ /*! @{ */ + #define LCDIF_LUT_CTRL_LUT_BYPASS_MASK (0x1U) #define LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT (0U) #define LCDIF_LUT_CTRL_LUT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT)) & LCDIF_LUT_CTRL_LUT_BYPASS_MASK) /*! @} */ -/*! @name LUT0_ADDR - Lookup Table Control Register. */ +/*! @name LUT0_ADDR - Lookup Table 0 Index Register */ /*! @{ */ + #define LCDIF_LUT0_ADDR_ADDR_MASK (0xFFU) #define LCDIF_LUT0_ADDR_ADDR_SHIFT (0U) #define LCDIF_LUT0_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_ADDR_ADDR_SHIFT)) & LCDIF_LUT0_ADDR_ADDR_MASK) /*! @} */ -/*! @name LUT0_DATA - Lookup Table Data Register. */ +/*! @name LUT0_DATA - Lookup Table 0 Data Register */ /*! @{ */ + #define LCDIF_LUT0_DATA_DATA_MASK (0xFFFFFFFFU) #define LCDIF_LUT0_DATA_DATA_SHIFT (0U) #define LCDIF_LUT0_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_DATA_DATA_SHIFT)) & LCDIF_LUT0_DATA_DATA_MASK) /*! @} */ -/*! @name LUT1_ADDR - Lookup Table Control Register. */ +/*! @name LUT1_ADDR - Lookup Table 1 Index Register */ /*! @{ */ + #define LCDIF_LUT1_ADDR_ADDR_MASK (0xFFU) #define LCDIF_LUT1_ADDR_ADDR_SHIFT (0U) #define LCDIF_LUT1_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_ADDR_ADDR_SHIFT)) & LCDIF_LUT1_ADDR_ADDR_MASK) /*! @} */ -/*! @name LUT1_DATA - Lookup Table Data Register. */ +/*! @name LUT1_DATA - Lookup Table 1 Data Register */ /*! @{ */ + #define LCDIF_LUT1_DATA_DATA_MASK (0xFFFFFFFFU) #define LCDIF_LUT1_DATA_DATA_SHIFT (0U) #define LCDIF_LUT1_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_DATA_DATA_SHIFT)) & LCDIF_LUT1_DATA_DATA_MASK) @@ -58416,6 +68428,8 @@ typedef struct { #define LCDIF_BASE_ADDRS { LCDIF_BASE } /** Array initializer of LCDIF peripheral base pointers */ #define LCDIF_BASE_PTRS { LCDIF } +/** Interrupt vectors for the LCDIF peripheral type */ +#define LCDIF_IRQ0_IRQS { eLCDIF_IRQn } /*! * @} @@ -58433,10 +68447,10 @@ typedef struct { /** LCDIFV2 - Register Layout Typedef */ typedef struct { - __IO uint32_t CTRL; /**< LCDIF display control Register, offset: 0x0 */ - __IO uint32_t CTRL_SET; /**< LCDIF display control Register, offset: 0x4 */ - __IO uint32_t CTRL_CLR; /**< LCDIF display control Register, offset: 0x8 */ - __IO uint32_t CTRL_TOG; /**< LCDIF display control Register, offset: 0xC */ + __IO uint32_t CTRL; /**< LCDIFv2 display control Register, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< LCDIFv2 display control Register, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< LCDIFv2 display control Register, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< LCDIFv2 display control Register, offset: 0xC */ __IO uint32_t DISP_PARA; /**< Display Parameter Register, offset: 0x10 */ __IO uint32_t DISP_SIZE; /**< Display Size Register, offset: 0x14 */ __IO uint32_t HSYN_PARA; /**< Horizontal Sync Parameter Register, offset: 0x18 */ @@ -58447,14 +68461,7 @@ typedef struct { uint8_t RESERVED_0[8]; } INT[2]; __IO uint32_t PDI_PARA; /**< Parallel Data Interface Parameter Register, offset: 0x40 */ - uint8_t RESERVED_0[12]; - __IO uint32_t WR_CTRL; /**< Write Control Register, offset: 0x50 */ - __IO uint32_t WR_CTRL_SET; /**< Write Control Register, offset: 0x54 */ - __IO uint32_t WR_CTRL_CLR; /**< Write Control Register, offset: 0x58 */ - __IO uint32_t WR_CTRL_TOG; /**< Write Control Register, offset: 0x5C */ - __IO uint32_t BASE_ADDR; /**< Write Address Register, offset: 0x60 */ - __IO uint32_t PITCH; /**< Write Pitch Register, offset: 0x64 */ - uint8_t RESERVED_1[408]; + uint8_t RESERVED_0[444]; struct { /* offset: 0x200, array step: 0x40 */ __IO uint32_t CTRLDESCL1; /**< Control Descriptor Layer 1 Register, array offset: 0x200, array step: 0x40 */ __IO uint32_t CTRLDESCL2; /**< Control Descriptor Layer 2 Register, array offset: 0x204, array step: 0x40 */ @@ -58467,15 +68474,9 @@ typedef struct { __IO uint32_t CSC_COEF2; /**< Color Space Conversion Coefficient Register 2, array offset: 0x220, array step: 0x40, this item is not available for all array instances */ uint8_t RESERVED_0[28]; } LAYER[8]; - __IO uint32_t CLUT_LOAD; /**< LCDIF CLUT load Register, offset: 0x400 */ - uint8_t RESERVED_5[7164]; - __IO uint32_t CLUT_RAM[2048]; + __IO uint32_t CLUT_LOAD; /**< LCDIFv2 CLUT load Register, offset: 0x400 */ } LCDIFV2_Type; -#define LCDIFV2_LAYER_COUNT 8 -#define LCDIFV2_CSC_COUNT 2 -#define LCDIFV2_INT_DOMAIN_COUNT 2 - /* ---------------------------------------------------------------------------- -- LCDIFV2 Register Masks ---------------------------------------------------------------------------- */ @@ -58485,22 +68486,25 @@ typedef struct { * @{ */ -/*! @name CTRL - LCDIF display control Register */ +/*! @name CTRL - LCDIFv2 display control Register */ /*! @{ */ + #define LCDIFV2_CTRL_INV_HS_MASK (0x1U) #define LCDIFV2_CTRL_INV_HS_SHIFT (0U) -/*! INV_HS - Invert Horizontal synchronization signal. - * 0b0..HSYNC signal not inverted (active HIGH). - * 0b1..Invert HSYNC signal (active LOW). +/*! INV_HS - Invert Horizontal synchronization signal + * 0b0..HSYNC signal not inverted (active HIGH) + * 0b1..Invert HSYNC signal (active LOW) */ #define LCDIFV2_CTRL_INV_HS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_HS_SHIFT)) & LCDIFV2_CTRL_INV_HS_MASK) + #define LCDIFV2_CTRL_INV_VS_MASK (0x2U) #define LCDIFV2_CTRL_INV_VS_SHIFT (1U) -/*! INV_VS - Invert Vertical synchronization signal. - * 0b0..VSYNC signal not inverted (active HIGH). - * 0b1..Invert VSYNC signal (active LOW). +/*! INV_VS - Invert Vertical synchronization signal + * 0b0..VSYNC signal not inverted (active HIGH) + * 0b1..Invert VSYNC signal (active LOW) */ #define LCDIFV2_CTRL_INV_VS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_VS_SHIFT)) & LCDIFV2_CTRL_INV_VS_MASK) + #define LCDIFV2_CTRL_INV_DE_MASK (0x4U) #define LCDIFV2_CTRL_INV_DE_SHIFT (2U) /*! INV_DE - Invert Data Enable polarity @@ -58508,269 +68512,306 @@ typedef struct { * 0b1..Data enable is active low */ #define LCDIFV2_CTRL_INV_DE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_DE_SHIFT)) & LCDIFV2_CTRL_INV_DE_MASK) + #define LCDIFV2_CTRL_INV_PXCK_MASK (0x8U) #define LCDIFV2_CTRL_INV_PXCK_SHIFT (3U) -/*! INV_PXCK - Polarity change of Pixel Clock. +/*! INV_PXCK - Polarity change of Pixel Clock * 0b0..Display samples data on the falling edge * 0b1..Display samples data on the rising edge */ #define LCDIFV2_CTRL_INV_PXCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_INV_PXCK_MASK) + #define LCDIFV2_CTRL_NEG_MASK (0x10U) #define LCDIFV2_CTRL_NEG_SHIFT (4U) -/*! NEG - Indicates if value at the output (pixel data output) needs to be negated. +/*! NEG - Indicates if value at the output (pixel data output) needs to be negated * 0b0..Output is to remain same * 0b1..Output to be negated */ #define LCDIFV2_CTRL_NEG(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_NEG_SHIFT)) & LCDIFV2_CTRL_NEG_MASK) + #define LCDIFV2_CTRL_SW_RESET_MASK (0x80000000U) #define LCDIFV2_CTRL_SW_RESET_SHIFT (31U) -/*! SW_RESET - SW_RESET +/*! SW_RESET - Software Reset * 0b0..No action - * 0b1..All LCDIF internal registers are forced into their reset state. User registers are not affected. + * 0b1..All LCDIFv2 internal registers are forced into their reset state. User registers are not affected */ #define LCDIFV2_CTRL_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SW_RESET_SHIFT)) & LCDIFV2_CTRL_SW_RESET_MASK) /*! @} */ -/*! @name CTRL_SET - LCDIF display control Register */ +/*! @name CTRL_SET - LCDIFv2 display control Register */ /*! @{ */ + #define LCDIFV2_CTRL_SET_INV_HS_MASK (0x1U) #define LCDIFV2_CTRL_SET_INV_HS_SHIFT (0U) -/*! INV_HS - Invert Horizontal synchronization signal. +/*! INV_HS - Invert Horizontal synchronization signal */ #define LCDIFV2_CTRL_SET_INV_HS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_HS_SHIFT)) & LCDIFV2_CTRL_SET_INV_HS_MASK) + #define LCDIFV2_CTRL_SET_INV_VS_MASK (0x2U) #define LCDIFV2_CTRL_SET_INV_VS_SHIFT (1U) -/*! INV_VS - Invert Vertical synchronization signal. +/*! INV_VS - Invert Vertical synchronization signal */ #define LCDIFV2_CTRL_SET_INV_VS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_VS_SHIFT)) & LCDIFV2_CTRL_SET_INV_VS_MASK) + #define LCDIFV2_CTRL_SET_INV_DE_MASK (0x4U) #define LCDIFV2_CTRL_SET_INV_DE_SHIFT (2U) /*! INV_DE - Invert Data Enable polarity */ #define LCDIFV2_CTRL_SET_INV_DE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_DE_SHIFT)) & LCDIFV2_CTRL_SET_INV_DE_MASK) + #define LCDIFV2_CTRL_SET_INV_PXCK_MASK (0x8U) #define LCDIFV2_CTRL_SET_INV_PXCK_SHIFT (3U) -/*! INV_PXCK - Polarity change of Pixel Clock. +/*! INV_PXCK - Polarity change of Pixel Clock */ #define LCDIFV2_CTRL_SET_INV_PXCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_SET_INV_PXCK_MASK) + #define LCDIFV2_CTRL_SET_NEG_MASK (0x10U) #define LCDIFV2_CTRL_SET_NEG_SHIFT (4U) -/*! NEG - Indicates if value at the output (pixel data output) needs to be negated. +/*! NEG - Indicates if value at the output (pixel data output) needs to be negated */ #define LCDIFV2_CTRL_SET_NEG(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_NEG_SHIFT)) & LCDIFV2_CTRL_SET_NEG_MASK) + #define LCDIFV2_CTRL_SET_SW_RESET_MASK (0x80000000U) #define LCDIFV2_CTRL_SET_SW_RESET_SHIFT (31U) -/*! SW_RESET - SW_RESET +/*! SW_RESET - Software Reset */ #define LCDIFV2_CTRL_SET_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_SW_RESET_SHIFT)) & LCDIFV2_CTRL_SET_SW_RESET_MASK) /*! @} */ -/*! @name CTRL_CLR - LCDIF display control Register */ +/*! @name CTRL_CLR - LCDIFv2 display control Register */ /*! @{ */ + #define LCDIFV2_CTRL_CLR_INV_HS_MASK (0x1U) #define LCDIFV2_CTRL_CLR_INV_HS_SHIFT (0U) -/*! INV_HS - Invert Horizontal synchronization signal. +/*! INV_HS - Invert Horizontal synchronization signal */ #define LCDIFV2_CTRL_CLR_INV_HS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_HS_SHIFT)) & LCDIFV2_CTRL_CLR_INV_HS_MASK) + #define LCDIFV2_CTRL_CLR_INV_VS_MASK (0x2U) #define LCDIFV2_CTRL_CLR_INV_VS_SHIFT (1U) -/*! INV_VS - Invert Vertical synchronization signal. +/*! INV_VS - Invert Vertical synchronization signal */ #define LCDIFV2_CTRL_CLR_INV_VS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_VS_SHIFT)) & LCDIFV2_CTRL_CLR_INV_VS_MASK) + #define LCDIFV2_CTRL_CLR_INV_DE_MASK (0x4U) #define LCDIFV2_CTRL_CLR_INV_DE_SHIFT (2U) /*! INV_DE - Invert Data Enable polarity */ #define LCDIFV2_CTRL_CLR_INV_DE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_DE_SHIFT)) & LCDIFV2_CTRL_CLR_INV_DE_MASK) + #define LCDIFV2_CTRL_CLR_INV_PXCK_MASK (0x8U) #define LCDIFV2_CTRL_CLR_INV_PXCK_SHIFT (3U) -/*! INV_PXCK - Polarity change of Pixel Clock. +/*! INV_PXCK - Polarity change of Pixel Clock */ #define LCDIFV2_CTRL_CLR_INV_PXCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_CLR_INV_PXCK_MASK) + #define LCDIFV2_CTRL_CLR_NEG_MASK (0x10U) #define LCDIFV2_CTRL_CLR_NEG_SHIFT (4U) -/*! NEG - Indicates if value at the output (pixel data output) needs to be negated. +/*! NEG - Indicates if value at the output (pixel data output) needs to be negated */ #define LCDIFV2_CTRL_CLR_NEG(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_NEG_SHIFT)) & LCDIFV2_CTRL_CLR_NEG_MASK) + #define LCDIFV2_CTRL_CLR_SW_RESET_MASK (0x80000000U) #define LCDIFV2_CTRL_CLR_SW_RESET_SHIFT (31U) -/*! SW_RESET - SW_RESET +/*! SW_RESET - Software Reset */ #define LCDIFV2_CTRL_CLR_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_SW_RESET_SHIFT)) & LCDIFV2_CTRL_CLR_SW_RESET_MASK) /*! @} */ -/*! @name CTRL_TOG - LCDIF display control Register */ +/*! @name CTRL_TOG - LCDIFv2 display control Register */ /*! @{ */ + #define LCDIFV2_CTRL_TOG_INV_HS_MASK (0x1U) #define LCDIFV2_CTRL_TOG_INV_HS_SHIFT (0U) -/*! INV_HS - Invert Horizontal synchronization signal. +/*! INV_HS - Invert Horizontal synchronization signal */ #define LCDIFV2_CTRL_TOG_INV_HS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_HS_SHIFT)) & LCDIFV2_CTRL_TOG_INV_HS_MASK) + #define LCDIFV2_CTRL_TOG_INV_VS_MASK (0x2U) #define LCDIFV2_CTRL_TOG_INV_VS_SHIFT (1U) -/*! INV_VS - Invert Vertical synchronization signal. +/*! INV_VS - Invert Vertical synchronization signal */ #define LCDIFV2_CTRL_TOG_INV_VS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_VS_SHIFT)) & LCDIFV2_CTRL_TOG_INV_VS_MASK) + #define LCDIFV2_CTRL_TOG_INV_DE_MASK (0x4U) #define LCDIFV2_CTRL_TOG_INV_DE_SHIFT (2U) /*! INV_DE - Invert Data Enable polarity */ #define LCDIFV2_CTRL_TOG_INV_DE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_DE_SHIFT)) & LCDIFV2_CTRL_TOG_INV_DE_MASK) + #define LCDIFV2_CTRL_TOG_INV_PXCK_MASK (0x8U) #define LCDIFV2_CTRL_TOG_INV_PXCK_SHIFT (3U) -/*! INV_PXCK - Polarity change of Pixel Clock. +/*! INV_PXCK - Polarity change of Pixel Clock */ #define LCDIFV2_CTRL_TOG_INV_PXCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_TOG_INV_PXCK_MASK) + #define LCDIFV2_CTRL_TOG_NEG_MASK (0x10U) #define LCDIFV2_CTRL_TOG_NEG_SHIFT (4U) -/*! NEG - Indicates if value at the output (pixel data output) needs to be negated. +/*! NEG - Indicates if value at the output (pixel data output) needs to be negated */ #define LCDIFV2_CTRL_TOG_NEG(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_NEG_SHIFT)) & LCDIFV2_CTRL_TOG_NEG_MASK) + #define LCDIFV2_CTRL_TOG_SW_RESET_MASK (0x80000000U) #define LCDIFV2_CTRL_TOG_SW_RESET_SHIFT (31U) -/*! SW_RESET - SW_RESET +/*! SW_RESET - Software Reset */ #define LCDIFV2_CTRL_TOG_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_SW_RESET_SHIFT)) & LCDIFV2_CTRL_TOG_SW_RESET_MASK) /*! @} */ /*! @name DISP_PARA - Display Parameter Register */ /*! @{ */ + #define LCDIFV2_DISP_PARA_BGND_B_MASK (0xFFU) #define LCDIFV2_DISP_PARA_BGND_B_SHIFT (0U) -/*! BGND_B - Blue component of the default color displayed in the sectors where no layer is active. +/*! BGND_B - Blue component of the default color displayed in the sectors where no layer is active */ #define LCDIFV2_DISP_PARA_BGND_B(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_B_SHIFT)) & LCDIFV2_DISP_PARA_BGND_B_MASK) + #define LCDIFV2_DISP_PARA_BGND_G_MASK (0xFF00U) #define LCDIFV2_DISP_PARA_BGND_G_SHIFT (8U) -/*! BGND_G - Green component of the default color displayed in the sectors where no layer is active. +/*! BGND_G - Green component of the default color displayed in the sectors where no layer is active */ #define LCDIFV2_DISP_PARA_BGND_G(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_G_SHIFT)) & LCDIFV2_DISP_PARA_BGND_G_MASK) + #define LCDIFV2_DISP_PARA_BGND_R_MASK (0xFF0000U) #define LCDIFV2_DISP_PARA_BGND_R_SHIFT (16U) -/*! BGND_R - Red component of the default color displayed in the sectors where no layer is active. +/*! BGND_R - Red component of the default color displayed in the sectors where no layer is active */ #define LCDIFV2_DISP_PARA_BGND_R(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_R_SHIFT)) & LCDIFV2_DISP_PARA_BGND_R_MASK) + #define LCDIFV2_DISP_PARA_DISP_MODE_MASK (0x3000000U) #define LCDIFV2_DISP_PARA_DISP_MODE_SHIFT (24U) -/*! DISP_MODE - LCDIF operating mode. - * 0b00..Normal mode. Panel content controlled by layer configuration. - * 0b01..Test Mode1.(BGND Color Display) - * 0b10..Test Mode2.(Column Color Bar) - * 0b11..Test Mode3.(Row Color Bar) +/*! DISP_MODE - LCDIFv2 operating mode + * 0b00..Normal mode. Panel content controlled by layer configuration + * 0b01..Test Mode1(BGND Color Display) + * 0b10..Test Mode2(Column Color Bar) + * 0b11..Test Mode3(Row Color Bar) */ #define LCDIFV2_DISP_PARA_DISP_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_DISP_MODE_SHIFT)) & LCDIFV2_DISP_PARA_DISP_MODE_MASK) + #define LCDIFV2_DISP_PARA_LINE_PATTERN_MASK (0x1C000000U) #define LCDIFV2_DISP_PARA_LINE_PATTERN_SHIFT (26U) -/*! LINE_PATTERN - LCDIF line output order. - * 0b000..RGB. - * 0b001..RBG. - * 0b010..GBR. - * 0b011..GRB. - * 0b100..BRG. - * 0b101..BGR. +/*! LINE_PATTERN - LCDIFv2 line output order + * 0b000..RGB + * 0b001..RBG + * 0b010..GBR + * 0b011..GRB + * 0b100..BRG + * 0b101..BGR */ #define LCDIFV2_DISP_PARA_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_LINE_PATTERN_SHIFT)) & LCDIFV2_DISP_PARA_LINE_PATTERN_MASK) + #define LCDIFV2_DISP_PARA_DISP_ON_MASK (0x80000000U) #define LCDIFV2_DISP_PARA_DISP_ON_SHIFT (31U) -/*! DISP_ON - Display panel On/Off mode. - * 0b0..Display Off. - * 0b1..Display On. +/*! DISP_ON - Display panel On/Off mode + * 0b0..Display Off + * 0b1..Display On */ #define LCDIFV2_DISP_PARA_DISP_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_DISP_ON_SHIFT)) & LCDIFV2_DISP_PARA_DISP_ON_MASK) /*! @} */ /*! @name DISP_SIZE - Display Size Register */ /*! @{ */ + #define LCDIFV2_DISP_SIZE_DELTA_X_MASK (0xFFFU) #define LCDIFV2_DISP_SIZE_DELTA_X_SHIFT (0U) -/*! DELTA_X - Sets the display size horizontal resolution in pixels. +/*! DELTA_X - Sets the display size horizontal resolution in pixels */ #define LCDIFV2_DISP_SIZE_DELTA_X(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_SIZE_DELTA_X_SHIFT)) & LCDIFV2_DISP_SIZE_DELTA_X_MASK) + #define LCDIFV2_DISP_SIZE_DELTA_Y_MASK (0xFFF0000U) #define LCDIFV2_DISP_SIZE_DELTA_Y_SHIFT (16U) -/*! DELTA_Y - Sets the display size vertical resolution in pixels. +/*! DELTA_Y - Sets the display size vertical resolution in pixels */ #define LCDIFV2_DISP_SIZE_DELTA_Y(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_SIZE_DELTA_Y_SHIFT)) & LCDIFV2_DISP_SIZE_DELTA_Y_MASK) /*! @} */ /*! @name HSYN_PARA - Horizontal Sync Parameter Register */ /*! @{ */ + #define LCDIFV2_HSYN_PARA_FP_H_MASK (0x1FFU) #define LCDIFV2_HSYN_PARA_FP_H_SHIFT (0U) -/*! FP_H - HSYNC front-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1. +/*! FP_H - HSYNC front-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1 */ #define LCDIFV2_HSYN_PARA_FP_H(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_FP_H_SHIFT)) & LCDIFV2_HSYN_PARA_FP_H_MASK) + #define LCDIFV2_HSYN_PARA_PW_H_MASK (0xFF800U) #define LCDIFV2_HSYN_PARA_PW_H_SHIFT (11U) -/*! PW_H - HSYNC active pulse width (in pixel clock cycles). Pulse width has a minimum value of 1. +/*! PW_H - HSYNC active pulse width (in pixel clock cycles). Pulse width has a minimum value of 1 */ #define LCDIFV2_HSYN_PARA_PW_H(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_PW_H_SHIFT)) & LCDIFV2_HSYN_PARA_PW_H_MASK) + #define LCDIFV2_HSYN_PARA_BP_H_MASK (0x7FC00000U) #define LCDIFV2_HSYN_PARA_BP_H_SHIFT (22U) -/*! BP_H - HSYNC back-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1. +/*! BP_H - HSYNC back-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1 */ #define LCDIFV2_HSYN_PARA_BP_H(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_BP_H_SHIFT)) & LCDIFV2_HSYN_PARA_BP_H_MASK) /*! @} */ /*! @name VSYN_PARA - Vertical Sync Parameter Register */ /*! @{ */ + #define LCDIFV2_VSYN_PARA_FP_V_MASK (0x1FFU) #define LCDIFV2_VSYN_PARA_FP_V_SHIFT (0U) -/*! FP_V - VSYNC front-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of 1. +/*! FP_V - VSYNC front-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of 1 */ #define LCDIFV2_VSYN_PARA_FP_V(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_FP_V_SHIFT)) & LCDIFV2_VSYN_PARA_FP_V_MASK) + #define LCDIFV2_VSYN_PARA_PW_V_MASK (0xFF800U) #define LCDIFV2_VSYN_PARA_PW_V_SHIFT (11U) -/*! PW_V - VSYNC active pulse width (in horizontal line cycles). Pulse width has a minimum value of 1. +/*! PW_V - VSYNC active pulse width (in horizontal line cycles). Pulse width has a minimum value of 1 */ #define LCDIFV2_VSYN_PARA_PW_V(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_PW_V_SHIFT)) & LCDIFV2_VSYN_PARA_PW_V_MASK) + #define LCDIFV2_VSYN_PARA_BP_V_MASK (0x7FC00000U) #define LCDIFV2_VSYN_PARA_BP_V_SHIFT (22U) -/*! BP_V - VSYNC back-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of 1. +/*! BP_V - VSYNC back-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of 1 */ #define LCDIFV2_VSYN_PARA_BP_V(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_BP_V_SHIFT)) & LCDIFV2_VSYN_PARA_BP_V_MASK) /*! @} */ /*! @name INT_STATUS - Interrupt Status Register for domain 0..Interrupt Status Register for domain 1 */ /*! @{ */ + #define LCDIFV2_INT_STATUS_VSYNC_MASK (0x1U) #define LCDIFV2_INT_STATUS_VSYNC_SHIFT (0U) -/*! VSYNC - Interrupt flag to indicate that the vertical synchronization phase(The beginning of a frame). +/*! VSYNC - Interrupt flag to indicate that the vertical synchronization phase(The beginning of a frame) + * 0b0..VSYNC has not started + * 0b1..VSYNC has started */ #define LCDIFV2_INT_STATUS_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_VSYNC_SHIFT)) & LCDIFV2_INT_STATUS_VSYNC_MASK) + #define LCDIFV2_INT_STATUS_UNDERRUN_MASK (0x2U) #define LCDIFV2_INT_STATUS_UNDERRUN_SHIFT (1U) -/*! UNDERRUN - Interrupt flag to indicate the output buffer underrun condition. +/*! UNDERRUN - Interrupt flag to indicate the output buffer underrun condition + * 0b0..Output buffer not underrun + * 0b1..Output buffer underrun */ #define LCDIFV2_INT_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_UNDERRUN_SHIFT)) & LCDIFV2_INT_STATUS_UNDERRUN_MASK) + #define LCDIFV2_INT_STATUS_VS_BLANK_MASK (0x4U) #define LCDIFV2_INT_STATUS_VS_BLANK_SHIFT (2U) -/*! VS_BLANK - Interrupt flag to indicate vertical blanking period. +/*! VS_BLANK - Interrupt flag to indicate vertical blanking period + * 0b0..Vertical blanking period has not started + * 0b1..Vertical blanking period has started */ #define LCDIFV2_INT_STATUS_VS_BLANK(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_VS_BLANK_SHIFT)) & LCDIFV2_INT_STATUS_VS_BLANK_MASK) -#define LCDIFV2_INT_STATUS_FRAME_COMP_MASK (0x10U) -#define LCDIFV2_INT_STATUS_FRAME_COMP_SHIFT (4U) -/*! FRAME_COMP - Indicates the current frame being processed has finished. - */ -#define LCDIFV2_INT_STATUS_FRAME_COMP(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_FRAME_COMP_SHIFT)) & LCDIFV2_INT_STATUS_FRAME_COMP_MASK) -#define LCDIFV2_INT_STATUS_WR_ERR_MASK (0x20U) -#define LCDIFV2_INT_STATUS_WR_ERR_SHIFT (5U) -/*! WR_ERR - Indicates a write error on the axi interface. - */ -#define LCDIFV2_INT_STATUS_WR_ERR(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_WR_ERR_SHIFT)) & LCDIFV2_INT_STATUS_WR_ERR_MASK) + #define LCDIFV2_INT_STATUS_DMA_ERR_MASK (0xFF00U) #define LCDIFV2_INT_STATUS_DMA_ERR_SHIFT (8U) -/*! DMA_ERR - Interrupt flag to indicate that which PLANE has Read Error on the AXI interface. +/*! DMA_ERR - Interrupt flag to indicate that which PLANE has Read Error on the AXI interface */ #define LCDIFV2_INT_STATUS_DMA_ERR(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_DMA_ERR_SHIFT)) & LCDIFV2_INT_STATUS_DMA_ERR_MASK) + #define LCDIFV2_INT_STATUS_DMA_DONE_MASK (0xFF0000U) #define LCDIFV2_INT_STATUS_DMA_DONE_SHIFT (16U) -/*! DMA_DONE - Interrupt flag to indicate that which PLANE has fetched the last pixel from memory. +/*! DMA_DONE - Interrupt flag to indicate that which PLANE has fetched the last pixel from memory */ #define LCDIFV2_INT_STATUS_DMA_DONE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_DMA_DONE_SHIFT)) & LCDIFV2_INT_STATUS_DMA_DONE_MASK) + #define LCDIFV2_INT_STATUS_FIFO_EMPTY_MASK (0xFF000000U) #define LCDIFV2_INT_STATUS_FIFO_EMPTY_SHIFT (24U) -/*! FIFO_EMPTY - Interrupt flag to indicate that which FIFO in the pixel blending underflowed. +/*! FIFO_EMPTY - Interrupt flag to indicate that which FIFO in the pixel blending underflowed */ #define LCDIFV2_INT_STATUS_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_FIFO_EMPTY_SHIFT)) & LCDIFV2_INT_STATUS_FIFO_EMPTY_MASK) /*! @} */ @@ -58780,44 +68821,46 @@ typedef struct { /*! @name INT_ENABLE - Interrupt Enable Register for domain 0..Interrupt Enable Register for domain 1 */ /*! @{ */ + #define LCDIFV2_INT_ENABLE_VSYNC_EN_MASK (0x1U) #define LCDIFV2_INT_ENABLE_VSYNC_EN_SHIFT (0U) -/*! VSYNC_EN - Enable Interrupt flag to indicate that the vertical synchronization phase(The beginning of a frame). +/*! VSYNC_EN - Enable Interrupt flag to indicate that the vertical synchronization phase(The beginning of a frame) + * 0b0..VSYNC interrupt disable + * 0b1..VSYNC interrupt enable */ #define LCDIFV2_INT_ENABLE_VSYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_VSYNC_EN_SHIFT)) & LCDIFV2_INT_ENABLE_VSYNC_EN_MASK) + #define LCDIFV2_INT_ENABLE_UNDERRUN_EN_MASK (0x2U) #define LCDIFV2_INT_ENABLE_UNDERRUN_EN_SHIFT (1U) -/*! UNDERRUN_EN - Enable Interrupt flag to indicate the output buffer underrun condition. +/*! UNDERRUN_EN - Enable Interrupt flag to indicate the output buffer underrun condition + * 0b0..Output buffer underrun disable + * 0b1..Output buffer underrun enable */ #define LCDIFV2_INT_ENABLE_UNDERRUN_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_UNDERRUN_EN_SHIFT)) & LCDIFV2_INT_ENABLE_UNDERRUN_EN_MASK) + #define LCDIFV2_INT_ENABLE_VS_BLANK_EN_MASK (0x4U) #define LCDIFV2_INT_ENABLE_VS_BLANK_EN_SHIFT (2U) -/*! VS_BLANK_EN - Enable Interrupt flag to indicate vertical blanking period. +/*! VS_BLANK_EN - Enable Interrupt flag to indicate vertical blanking period + * 0b0..Vertical blanking start interrupt disable + * 0b1..Vertical blanking start interrupt enable */ #define LCDIFV2_INT_ENABLE_VS_BLANK_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_VS_BLANK_EN_SHIFT)) & LCDIFV2_INT_ENABLE_VS_BLANK_EN_MASK) -#define LCDIFV2_INT_ENABLE_FRAME_COMP_EN_MASK (0x10U) -#define LCDIFV2_INT_ENABLE_FRAME_COMP_EN_SHIFT (4U) -/*! FRAME_COMP_EN - Write error IRQ enable - */ -#define LCDIFV2_INT_ENABLE_FRAME_COMP_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_FRAME_COMP_EN_SHIFT)) & LCDIFV2_INT_ENABLE_FRAME_COMP_EN_MASK) -#define LCDIFV2_INT_ENABLE_WR_ERR_EN_MASK (0x20U) -#define LCDIFV2_INT_ENABLE_WR_ERR_EN_SHIFT (5U) -/*! WR_ERR_EN - Write error IRQ enable - */ -#define LCDIFV2_INT_ENABLE_WR_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_WR_ERR_EN_SHIFT)) & LCDIFV2_INT_ENABLE_WR_ERR_EN_MASK) + #define LCDIFV2_INT_ENABLE_DMA_ERR_EN_MASK (0xFF00U) #define LCDIFV2_INT_ENABLE_DMA_ERR_EN_SHIFT (8U) -/*! DMA_ERR_EN - Enable Interrupt flag to indicate that which PLANE has Read Error on the AXI interface. +/*! DMA_ERR_EN - Enable Interrupt flag to indicate that which PLANE has Read Error on the AXI interface */ #define LCDIFV2_INT_ENABLE_DMA_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_DMA_ERR_EN_SHIFT)) & LCDIFV2_INT_ENABLE_DMA_ERR_EN_MASK) + #define LCDIFV2_INT_ENABLE_DMA_DONE_EN_MASK (0xFF0000U) #define LCDIFV2_INT_ENABLE_DMA_DONE_EN_SHIFT (16U) -/*! DMA_DONE_EN - Enable Interrupt flag to indicate that which PLANE has fetched the last pixel from memory. +/*! DMA_DONE_EN - Enable Interrupt flag to indicate that which PLANE has fetched the last pixel from memory */ #define LCDIFV2_INT_ENABLE_DMA_DONE_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_DMA_DONE_EN_SHIFT)) & LCDIFV2_INT_ENABLE_DMA_DONE_EN_MASK) + #define LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_MASK (0xFF000000U) #define LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_SHIFT (24U) -/*! FIFO_EMPTY_EN - Enable Interrupt flag to indicate that which FIFO in the pixel blending underflowed. +/*! FIFO_EMPTY_EN - Enable Interrupt flag to indicate that which FIFO in the pixel blending underflowed */ #define LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_SHIFT)) & LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_MASK) /*! @} */ @@ -58827,34 +68870,39 @@ typedef struct { /*! @name PDI_PARA - Parallel Data Interface Parameter Register */ /*! @{ */ + #define LCDIFV2_PDI_PARA_INV_PDI_HS_MASK (0x1U) #define LCDIFV2_PDI_PARA_INV_PDI_HS_SHIFT (0U) -/*! INV_PDI_HS - Polarity of PDI input HSYNC. +/*! INV_PDI_HS - Polarity of PDI input HSYNC * 0b0..HSYNC is active HIGH * 0b1..HSYNC is active LOW */ #define LCDIFV2_PDI_PARA_INV_PDI_HS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_HS_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_HS_MASK) + #define LCDIFV2_PDI_PARA_INV_PDI_VS_MASK (0x2U) #define LCDIFV2_PDI_PARA_INV_PDI_VS_SHIFT (1U) -/*! INV_PDI_VS - Polarity of PDI input VSYNC. +/*! INV_PDI_VS - Polarity of PDI input VSYNC * 0b0..VSYNC is active HIGH * 0b1..VSYNC is active LOW */ #define LCDIFV2_PDI_PARA_INV_PDI_VS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_VS_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_VS_MASK) + #define LCDIFV2_PDI_PARA_INV_PDI_DE_MASK (0x4U) #define LCDIFV2_PDI_PARA_INV_PDI_DE_SHIFT (2U) -/*! INV_PDI_DE - Polarity of PDI input Data Enable. +/*! INV_PDI_DE - Polarity of PDI input Data Enable * 0b0..Data enable is active HIGH * 0b1..Data enable is active LOW */ #define LCDIFV2_PDI_PARA_INV_PDI_DE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_DE_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_DE_MASK) + #define LCDIFV2_PDI_PARA_INV_PDI_PXCK_MASK (0x8U) #define LCDIFV2_PDI_PARA_INV_PDI_PXCK_SHIFT (3U) -/*! INV_PDI_PXCK - Polarity of PDI input Pixel Clock. +/*! INV_PDI_PXCK - Polarity of PDI input Pixel Clock * 0b0..Samples data on the falling edge * 0b1..Samples data on the rising edge */ #define LCDIFV2_PDI_PARA_INV_PDI_PXCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_PXCK_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_PXCK_MASK) + #define LCDIFV2_PDI_PARA_MODE_MASK (0xF0U) #define LCDIFV2_PDI_PARA_MODE_SHIFT (4U) /*! MODE - The PDI mode for input data format @@ -58867,167 +68915,36 @@ typedef struct { * 0b0110..16 bpp (YCbCr422) */ #define LCDIFV2_PDI_PARA_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_MODE_SHIFT)) & LCDIFV2_PDI_PARA_MODE_MASK) -#define LCDIFV2_PDI_PARA_PXL_CNT_MASK (0xFFF00U) -#define LCDIFV2_PDI_PARA_PXL_CNT_SHIFT (8U) -/*! PXL_CNT - Pixels count of LCD Hsync output for the Pass_Through MODE. - */ -#define LCDIFV2_PDI_PARA_PXL_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_PXL_CNT_SHIFT)) & LCDIFV2_PDI_PARA_PXL_CNT_MASK) + #define LCDIFV2_PDI_PARA_PDI_SEL_MASK (0x40000000U) #define LCDIFV2_PDI_PARA_PDI_SEL_SHIFT (30U) -/*! PDI_SEL - PDI selected on LCDIF plane number. - * 0b0..PDI selected on LCDIF plane 0 - * 0b1..PDI selected on LCDIF plane 1 +/*! PDI_SEL - PDI selected on LCDIFv2 plane number + * 0b0..PDI selected on LCDIFv2 plane 0 + * 0b1..PDI selected on LCDIFv2 plane 1 */ #define LCDIFV2_PDI_PARA_PDI_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_PDI_SEL_SHIFT)) & LCDIFV2_PDI_PARA_PDI_SEL_MASK) + #define LCDIFV2_PDI_PARA_PDI_EN_MASK (0x80000000U) #define LCDIFV2_PDI_PARA_PDI_EN_SHIFT (31U) -/*! PDI_EN - Enable PDI input data to LCDIF display. +/*! PDI_EN - Enable PDI input data to LCDIFv2 display * 0b0..Disable PDI input data * 0b1..Enable PDI input data */ #define LCDIFV2_PDI_PARA_PDI_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_PDI_EN_SHIFT)) & LCDIFV2_PDI_PARA_PDI_EN_MASK) /*! @} */ -/*! @name WR_CTRL - Write Control Register */ -/*! @{ */ -#define LCDIFV2_WR_CTRL_ENABLE_MASK (0x1U) -#define LCDIFV2_WR_CTRL_ENABLE_SHIFT (0U) -/*! ENABLE - Enable / Busy - */ -#define LCDIFV2_WR_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_WR_CTRL_ENABLE_SHIFT)) & LCDIFV2_WR_CTRL_ENABLE_MASK) -#define LCDIFV2_WR_CTRL_REPEAT_MASK (0x2U) -#define LCDIFV2_WR_CTRL_REPEAT_SHIFT (1U) -/*! REPEAT - Repeat feature - */ -#define LCDIFV2_WR_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_WR_CTRL_REPEAT_SHIFT)) & LCDIFV2_WR_CTRL_REPEAT_MASK) -#define LCDIFV2_WR_CTRL_BPP_MASK (0x4U) -#define LCDIFV2_WR_CTRL_BPP_SHIFT (2U) -/*! BPP - Bits per pixel - */ -#define LCDIFV2_WR_CTRL_BPP(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_WR_CTRL_BPP_SHIFT)) & LCDIFV2_WR_CTRL_BPP_MASK) -#define LCDIFV2_WR_CTRL_P_FREQ_MASK (0x3FC00U) -#define LCDIFV2_WR_CTRL_P_FREQ_SHIFT (10U) -/*! P_FREQ - Payload frequency - */ -#define LCDIFV2_WR_CTRL_P_FREQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_WR_CTRL_P_FREQ_SHIFT)) & LCDIFV2_WR_CTRL_P_FREQ_MASK) -#define LCDIFV2_WR_CTRL_FIFO_SIZE_MASK (0x1FC0000U) -#define LCDIFV2_WR_CTRL_FIFO_SIZE_SHIFT (18U) -/*! FIFO_SIZE - Size of FIFO in design - */ -#define LCDIFV2_WR_CTRL_FIFO_SIZE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_WR_CTRL_FIFO_SIZE_SHIFT)) & LCDIFV2_WR_CTRL_FIFO_SIZE_MASK) -/*! @} */ - -/*! @name WR_CTRL_SET - Write Control Register */ -/*! @{ */ -#define LCDIFV2_WR_CTRL_SET_ENABLE_MASK (0x1U) -#define LCDIFV2_WR_CTRL_SET_ENABLE_SHIFT (0U) -/*! ENABLE - Enable / Busy - */ -#define LCDIFV2_WR_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_WR_CTRL_SET_ENABLE_SHIFT)) & LCDIFV2_WR_CTRL_SET_ENABLE_MASK) -#define LCDIFV2_WR_CTRL_SET_REPEAT_MASK (0x2U) -#define LCDIFV2_WR_CTRL_SET_REPEAT_SHIFT (1U) -/*! REPEAT - Repeat feature - */ -#define LCDIFV2_WR_CTRL_SET_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_WR_CTRL_SET_REPEAT_SHIFT)) & LCDIFV2_WR_CTRL_SET_REPEAT_MASK) -#define LCDIFV2_WR_CTRL_SET_BPP_MASK (0x4U) -#define LCDIFV2_WR_CTRL_SET_BPP_SHIFT (2U) -/*! BPP - Bits per pixel - */ -#define LCDIFV2_WR_CTRL_SET_BPP(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_WR_CTRL_SET_BPP_SHIFT)) & LCDIFV2_WR_CTRL_SET_BPP_MASK) -#define LCDIFV2_WR_CTRL_SET_P_FREQ_MASK (0x3FC00U) -#define LCDIFV2_WR_CTRL_SET_P_FREQ_SHIFT (10U) -/*! P_FREQ - Payload frequency - */ -#define LCDIFV2_WR_CTRL_SET_P_FREQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_WR_CTRL_SET_P_FREQ_SHIFT)) & LCDIFV2_WR_CTRL_SET_P_FREQ_MASK) -#define LCDIFV2_WR_CTRL_SET_FIFO_SIZE_MASK (0x1FC0000U) -#define LCDIFV2_WR_CTRL_SET_FIFO_SIZE_SHIFT (18U) -/*! FIFO_SIZE - Size of FIFO in design - */ -#define LCDIFV2_WR_CTRL_SET_FIFO_SIZE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_WR_CTRL_SET_FIFO_SIZE_SHIFT)) & LCDIFV2_WR_CTRL_SET_FIFO_SIZE_MASK) -/*! @} */ - -/*! @name WR_CTRL_CLR - Write Control Register */ -/*! @{ */ -#define LCDIFV2_WR_CTRL_CLR_ENABLE_MASK (0x1U) -#define LCDIFV2_WR_CTRL_CLR_ENABLE_SHIFT (0U) -/*! ENABLE - Enable / Busy - */ -#define LCDIFV2_WR_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_WR_CTRL_CLR_ENABLE_SHIFT)) & LCDIFV2_WR_CTRL_CLR_ENABLE_MASK) -#define LCDIFV2_WR_CTRL_CLR_REPEAT_MASK (0x2U) -#define LCDIFV2_WR_CTRL_CLR_REPEAT_SHIFT (1U) -/*! REPEAT - Repeat feature - */ -#define LCDIFV2_WR_CTRL_CLR_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_WR_CTRL_CLR_REPEAT_SHIFT)) & LCDIFV2_WR_CTRL_CLR_REPEAT_MASK) -#define LCDIFV2_WR_CTRL_CLR_BPP_MASK (0x4U) -#define LCDIFV2_WR_CTRL_CLR_BPP_SHIFT (2U) -/*! BPP - Bits per pixel - */ -#define LCDIFV2_WR_CTRL_CLR_BPP(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_WR_CTRL_CLR_BPP_SHIFT)) & LCDIFV2_WR_CTRL_CLR_BPP_MASK) -#define LCDIFV2_WR_CTRL_CLR_P_FREQ_MASK (0x3FC00U) -#define LCDIFV2_WR_CTRL_CLR_P_FREQ_SHIFT (10U) -/*! P_FREQ - Payload frequency - */ -#define LCDIFV2_WR_CTRL_CLR_P_FREQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_WR_CTRL_CLR_P_FREQ_SHIFT)) & LCDIFV2_WR_CTRL_CLR_P_FREQ_MASK) -#define LCDIFV2_WR_CTRL_CLR_FIFO_SIZE_MASK (0x1FC0000U) -#define LCDIFV2_WR_CTRL_CLR_FIFO_SIZE_SHIFT (18U) -/*! FIFO_SIZE - Size of FIFO in design - */ -#define LCDIFV2_WR_CTRL_CLR_FIFO_SIZE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_WR_CTRL_CLR_FIFO_SIZE_SHIFT)) & LCDIFV2_WR_CTRL_CLR_FIFO_SIZE_MASK) -/*! @} */ - -/*! @name WR_CTRL_TOG - Write Control Register */ -/*! @{ */ -#define LCDIFV2_WR_CTRL_TOG_ENABLE_MASK (0x1U) -#define LCDIFV2_WR_CTRL_TOG_ENABLE_SHIFT (0U) -/*! ENABLE - Enable / Busy - */ -#define LCDIFV2_WR_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_WR_CTRL_TOG_ENABLE_SHIFT)) & LCDIFV2_WR_CTRL_TOG_ENABLE_MASK) -#define LCDIFV2_WR_CTRL_TOG_REPEAT_MASK (0x2U) -#define LCDIFV2_WR_CTRL_TOG_REPEAT_SHIFT (1U) -/*! REPEAT - Repeat feature - */ -#define LCDIFV2_WR_CTRL_TOG_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_WR_CTRL_TOG_REPEAT_SHIFT)) & LCDIFV2_WR_CTRL_TOG_REPEAT_MASK) -#define LCDIFV2_WR_CTRL_TOG_BPP_MASK (0x4U) -#define LCDIFV2_WR_CTRL_TOG_BPP_SHIFT (2U) -/*! BPP - Bits per pixel - */ -#define LCDIFV2_WR_CTRL_TOG_BPP(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_WR_CTRL_TOG_BPP_SHIFT)) & LCDIFV2_WR_CTRL_TOG_BPP_MASK) -#define LCDIFV2_WR_CTRL_TOG_P_FREQ_MASK (0x3FC00U) -#define LCDIFV2_WR_CTRL_TOG_P_FREQ_SHIFT (10U) -/*! P_FREQ - Payload frequency - */ -#define LCDIFV2_WR_CTRL_TOG_P_FREQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_WR_CTRL_TOG_P_FREQ_SHIFT)) & LCDIFV2_WR_CTRL_TOG_P_FREQ_MASK) -#define LCDIFV2_WR_CTRL_TOG_FIFO_SIZE_MASK (0x1FC0000U) -#define LCDIFV2_WR_CTRL_TOG_FIFO_SIZE_SHIFT (18U) -/*! FIFO_SIZE - Size of FIFO in design - */ -#define LCDIFV2_WR_CTRL_TOG_FIFO_SIZE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_WR_CTRL_TOG_FIFO_SIZE_SHIFT)) & LCDIFV2_WR_CTRL_TOG_FIFO_SIZE_MASK) -/*! @} */ - -/*! @name BASE_ADDR - Write Address Register */ -/*! @{ */ -#define LCDIFV2_BASE_ADDR_BASE_ADDR_MASK (0xFFFFFFFFU) -#define LCDIFV2_BASE_ADDR_BASE_ADDR_SHIFT (0U) -#define LCDIFV2_BASE_ADDR_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_BASE_ADDR_BASE_ADDR_SHIFT)) & LCDIFV2_BASE_ADDR_BASE_ADDR_MASK) -/*! @} */ - -/*! @name PITCH - Write Pitch Register */ -/*! @{ */ -#define LCDIFV2_PITCH_PITCH_MASK (0xFFFFU) -#define LCDIFV2_PITCH_PITCH_SHIFT (0U) -#define LCDIFV2_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PITCH_PITCH_SHIFT)) & LCDIFV2_PITCH_PITCH_MASK) -/*! @} */ - /*! @name CTRLDESCL1 - Control Descriptor Layer 1 Register */ /*! @{ */ + #define LCDIFV2_CTRLDESCL1_WIDTH_MASK (0xFFFU) #define LCDIFV2_CTRLDESCL1_WIDTH_SHIFT (0U) -/*! WIDTH - Width of the layer in pixels. +/*! WIDTH - Width of the layer in pixels */ #define LCDIFV2_CTRLDESCL1_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL1_WIDTH_SHIFT)) & LCDIFV2_CTRLDESCL1_WIDTH_MASK) + #define LCDIFV2_CTRLDESCL1_HEIGHT_MASK (0xFFF0000U) #define LCDIFV2_CTRLDESCL1_HEIGHT_SHIFT (16U) -/*! HEIGHT - Height of the layer in pixels. +/*! HEIGHT - Height of the layer in pixels */ #define LCDIFV2_CTRLDESCL1_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL1_HEIGHT_SHIFT)) & LCDIFV2_CTRLDESCL1_HEIGHT_MASK) /*! @} */ @@ -59037,16 +68954,18 @@ typedef struct { /*! @name CTRLDESCL2 - Control Descriptor Layer 2 Register */ /*! @{ */ + #define LCDIFV2_CTRLDESCL2_POSX_MASK (0xFFFU) #define LCDIFV2_CTRLDESCL2_POSX_SHIFT (0U) /*! POSX - The horizontal position of left-hand column of the layer, where 0 is the left-hand column - * of the panel, only positive values are to the right the left-hand column of the panel. + * of the panel, only positive values are to the right the left-hand column of the panel */ #define LCDIFV2_CTRLDESCL2_POSX(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL2_POSX_SHIFT)) & LCDIFV2_CTRLDESCL2_POSX_MASK) + #define LCDIFV2_CTRLDESCL2_POSY_MASK (0xFFF0000U) #define LCDIFV2_CTRLDESCL2_POSY_SHIFT (16U) /*! POSY - The vertical position of top row of the layer, where 0 is the top row of the panel, only - * positive values are below the top row of the panel. + * positive values are below the top row of the panel */ #define LCDIFV2_CTRLDESCL2_POSY(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL2_POSY_SHIFT)) & LCDIFV2_CTRLDESCL2_POSY_MASK) /*! @} */ @@ -59056,10 +68975,11 @@ typedef struct { /*! @name CTRLDESCL3 - Control Descriptor Layer 3 Register */ /*! @{ */ + #define LCDIFV2_CTRLDESCL3_PITCH_MASK (0xFFFFU) #define LCDIFV2_CTRLDESCL3_PITCH_SHIFT (0U) /*! PITCH - Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity - * is supported, but SW should align to 64B boundry. + * is supported, but SW should align to 64B boundry */ #define LCDIFV2_CTRLDESCL3_PITCH(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL3_PITCH_SHIFT)) & LCDIFV2_CTRLDESCL3_PITCH_MASK) /*! @} */ @@ -59069,9 +68989,10 @@ typedef struct { /*! @name CTRLDESCL4 - Control Descriptor Layer 4 Register */ /*! @{ */ + #define LCDIFV2_CTRLDESCL4_ADDR_MASK (0xFFFFFFFFU) #define LCDIFV2_CTRLDESCL4_ADDR_SHIFT (0U) -/*! ADDR - Address of layer data in the memory. The address programmed should be 64-bit aligned. +/*! ADDR - Address of layer data in the memory. The address programmed should be 64-bit aligned */ #define LCDIFV2_CTRLDESCL4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL4_ADDR_SHIFT)) & LCDIFV2_CTRLDESCL4_ADDR_MASK) /*! @} */ @@ -59081,61 +69002,69 @@ typedef struct { /*! @name CTRLDESCL5 - Control Descriptor Layer 5 Register */ /*! @{ */ + #define LCDIFV2_CTRLDESCL5_AB_MODE_MASK (0x3U) #define LCDIFV2_CTRLDESCL5_AB_MODE_SHIFT (0U) -/*! AB_MODE - Alpha Blending Mode. +/*! AB_MODE - Alpha Blending Mode * 0b00..No alpha Blending (The SAFETY_EN bit need set to 1) * 0b01..Blend with global ALPHA * 0b10..Blend with embedded ALPHA * 0b11..Blend with PoterDuff enable */ #define LCDIFV2_CTRLDESCL5_AB_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_AB_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_AB_MODE_MASK) + #define LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_MASK (0x30U) #define LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_SHIFT (4U) -/*! PD_FACTOR_MODE - PoterDuff factor mode. - * 0b00..Using 1. - * 0b01..Using 0. - * 0b10..Using straight alpha. - * 0b11..Using inverse alpha. +/*! PD_FACTOR_MODE - PoterDuff factor mode + * 0b00..Using 1 + * 0b01..Using 0 + * 0b10..Using straight alpha + * 0b11..Using inverse alpha */ #define LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_MASK) + #define LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_MASK (0xC0U) #define LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_SHIFT (6U) -/*! PD_GLOBAL_ALPHA_MODE - PoterDuff global alpha mode. - * 0b00..Using global alpha. - * 0b01..Using local alpha. - * 0b10..Using scaled alpha. - * 0b11..Using scaled alpha. +/*! PD_GLOBAL_ALPHA_MODE - PoterDuff global alpha mode + * 0b00..Using global alpha + * 0b01..Using local alpha + * 0b10..Using scaled alpha + * 0b11..Using scaled alpha */ #define LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_MASK) + #define LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_MASK (0x100U) #define LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_SHIFT (8U) -/*! PD_ALPHA_MODE - PoterDuff alpha mode. - * 0b0..Straight mode for PorterDuff alpha. - * 0b1..Inversed mode for PorterDuff alpha. +/*! PD_ALPHA_MODE - PoterDuff alpha mode + * 0b0..Straight mode for Porter Duff alpha + * 0b1..Inversed mode for Porter Duff alpha */ #define LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_MASK) + #define LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_MASK (0x200U) #define LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_SHIFT (9U) -/*! PD_COLOR_MODE - PoterDuff alpha mode. - * 0b0..Straight mode for PorterDuff color. - * 0b1..Inversed mode for PorterDuff color. +/*! PD_COLOR_MODE - PoterDuff alpha mode + * 0b0..Straight mode for Porter Duff color + * 0b1..Inversed mode for Porter Duff color */ #define LCDIFV2_CTRLDESCL5_PD_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_MASK) + #define LCDIFV2_CTRLDESCL5_YUV_FORMAT_MASK (0xC000U) #define LCDIFV2_CTRLDESCL5_YUV_FORMAT_SHIFT (14U) -/*! YUV_FORMAT - The YUV422 input format selection. +/*! YUV_FORMAT - The YUV422 input format selection * 0b00..The YVYU422 8bit sequence is U1,Y1,V1,Y2 * 0b01..The YVYU422 8bit sequence is V1,Y1,U1,Y2 * 0b10..The YVYU422 8bit sequence is Y1,U1,Y2,V1 * 0b11..The YVYU422 8bit sequence is Y1,V1,Y2,U1 */ #define LCDIFV2_CTRLDESCL5_YUV_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_YUV_FORMAT_SHIFT)) & LCDIFV2_CTRLDESCL5_YUV_FORMAT_MASK) + #define LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_MASK (0xFF0000U) #define LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_SHIFT (16U) -/*! GLOBAL_ALPHA - Global Alpha. +/*! GLOBAL_ALPHA - Global Alpha */ #define LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_SHIFT)) & LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_MASK) + #define LCDIFV2_CTRLDESCL5_BPP_MASK (0xF000000U) #define LCDIFV2_CTRLDESCL5_BPP_SHIFT (24U) /*! BPP - Layer encoding format (bit per pixel) @@ -59152,21 +69081,24 @@ typedef struct { * 0b1010..32 bpp (ABGR8888) */ #define LCDIFV2_CTRLDESCL5_BPP(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_BPP_SHIFT)) & LCDIFV2_CTRLDESCL5_BPP_MASK) + #define LCDIFV2_CTRLDESCL5_SAFETY_EN_MASK (0x10000000U) #define LCDIFV2_CTRLDESCL5_SAFETY_EN_SHIFT (28U) -/*! SAFETY_EN - Safety Mode Enable Bit. +/*! SAFETY_EN - Safety Mode Enable Bit * 0b0..Safety Mode is disabled * 0b1..Safety Mode is enabled for this layer */ #define LCDIFV2_CTRLDESCL5_SAFETY_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_SAFETY_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_SAFETY_EN_MASK) + #define LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_MASK (0x40000000U) #define LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_SHIFT (30U) /*! SHADOW_LOAD_EN - Shadow Load Enable */ #define LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_MASK) + #define LCDIFV2_CTRLDESCL5_EN_MASK (0x80000000U) #define LCDIFV2_CTRLDESCL5_EN_SHIFT (31U) -/*! EN - Enable the layer for DMA. +/*! EN - Enable the layer for DMA * 0b0..OFF * 0b1..ON */ @@ -59178,11 +69110,24 @@ typedef struct { /*! @name CTRLDESCL6 - Control Descriptor Layer 6 Register */ /*! @{ */ -#define LCDIFV2_CTRLDESCL6_FGn_BCOLOR_MASK (0xFFFFFFFFU) -#define LCDIFV2_CTRLDESCL6_FGn_BCOLOR_SHIFT (0U) -/*! FGn_BCOLOR - Background color to use when this layer is not active. + +#define LCDIFV2_CTRLDESCL6_BCLR_B_MASK (0xFFU) +#define LCDIFV2_CTRLDESCL6_BCLR_B_SHIFT (0U) +/*! BCLR_B - Background B component value + */ +#define LCDIFV2_CTRLDESCL6_BCLR_B(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_B_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_B_MASK) + +#define LCDIFV2_CTRLDESCL6_BCLR_G_MASK (0xFF00U) +#define LCDIFV2_CTRLDESCL6_BCLR_G_SHIFT (8U) +/*! BCLR_G - Background G component value */ -#define LCDIFV2_CTRLDESCL6_FGn_BCOLOR(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_FGn_BCOLOR_SHIFT)) & LCDIFV2_CTRLDESCL6_FGn_BCOLOR_MASK) +#define LCDIFV2_CTRLDESCL6_BCLR_G(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_G_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_G_MASK) + +#define LCDIFV2_CTRLDESCL6_BCLR_R_MASK (0xFF0000U) +#define LCDIFV2_CTRLDESCL6_BCLR_R_SHIFT (16U) +/*! BCLR_R - Background R component value + */ +#define LCDIFV2_CTRLDESCL6_BCLR_R(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_R_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_R_MASK) /*! @} */ /* The count of LCDIFV2_CTRLDESCL6 */ @@ -59190,34 +69135,39 @@ typedef struct { /*! @name CSC_COEF0 - Color Space Conversion Coefficient Register 0 */ /*! @{ */ + #define LCDIFV2_CSC_COEF0_Y_OFFSET_MASK (0x1FFU) #define LCDIFV2_CSC_COEF0_Y_OFFSET_SHIFT (0U) /*! Y_OFFSET - Two's compliment amplitude offset implicit in the Y data. For YUV, this is typically - * 0 and for YCbCr, this is typically -16 (0x1F0). + * 0 and for YCbCr, this is typically -16 (0x1F0) */ #define LCDIFV2_CSC_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_Y_OFFSET_SHIFT)) & LCDIFV2_CSC_COEF0_Y_OFFSET_MASK) + #define LCDIFV2_CSC_COEF0_UV_OFFSET_MASK (0x3FE00U) #define LCDIFV2_CSC_COEF0_UV_OFFSET_SHIFT (9U) /*! UV_OFFSET - Two's compliment phase offset implicit for CbCr data. Generally used for YCbCr to * RGB conversion. YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to - * 0.5 range). + * 0.5 range) */ #define LCDIFV2_CSC_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_UV_OFFSET_SHIFT)) & LCDIFV2_CSC_COEF0_UV_OFFSET_MASK) + #define LCDIFV2_CSC_COEF0_C0_MASK (0x1FFC0000U) #define LCDIFV2_CSC_COEF0_C0_SHIFT (18U) -/*! C0 - Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164). +/*! C0 - Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164) */ #define LCDIFV2_CSC_COEF0_C0(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_C0_SHIFT)) & LCDIFV2_CSC_COEF0_C0_MASK) + #define LCDIFV2_CSC_COEF0_ENABLE_MASK (0x40000000U) #define LCDIFV2_CSC_COEF0_ENABLE_SHIFT (30U) -/*! ENABLE - Enable the CSC unit in the LCDIF plane data path. +/*! ENABLE - Enable the CSC unit in the LCDIFv2 plane data path * 0b0..The CSC is bypassed and the input pixels are RGB data already * 0b1..The CSC is enabled and the pixels will be converted to RGB data */ #define LCDIFV2_CSC_COEF0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_ENABLE_SHIFT)) & LCDIFV2_CSC_COEF0_ENABLE_MASK) + #define LCDIFV2_CSC_COEF0_YCBCR_MODE_MASK (0x80000000U) #define LCDIFV2_CSC_COEF0_YCBCR_MODE_SHIFT (31U) -/*! YCBCR_MODE - This bit changes the behavior when performing U/V converting. +/*! YCBCR_MODE - This bit changes the behavior when performing U/V converting * 0b0..Converting YUV to RGB data * 0b1..Converting YCbCr to RGB data */ @@ -59229,14 +69179,16 @@ typedef struct { /*! @name CSC_COEF1 - Color Space Conversion Coefficient Register 1 */ /*! @{ */ + #define LCDIFV2_CSC_COEF1_C4_MASK (0x7FFU) #define LCDIFV2_CSC_COEF1_C4_SHIFT (0U) -/*! C4 - Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017). +/*! C4 - Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017) */ #define LCDIFV2_CSC_COEF1_C4(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF1_C4_SHIFT)) & LCDIFV2_CSC_COEF1_C4_MASK) + #define LCDIFV2_CSC_COEF1_C1_MASK (0x7FF0000U) #define LCDIFV2_CSC_COEF1_C1_SHIFT (16U) -/*! C1 - Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596). +/*! C1 - Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596) */ #define LCDIFV2_CSC_COEF1_C1(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF1_C1_SHIFT)) & LCDIFV2_CSC_COEF1_C1_MASK) /*! @} */ @@ -59246,14 +69198,16 @@ typedef struct { /*! @name CSC_COEF2 - Color Space Conversion Coefficient Register 2 */ /*! @{ */ + #define LCDIFV2_CSC_COEF2_C3_MASK (0x7FFU) #define LCDIFV2_CSC_COEF2_C3_SHIFT (0U) -/*! C3 - Two's compliment Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392). +/*! C3 - Two's compliment Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392) */ #define LCDIFV2_CSC_COEF2_C3(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF2_C3_SHIFT)) & LCDIFV2_CSC_COEF2_C3_MASK) + #define LCDIFV2_CSC_COEF2_C2_MASK (0x7FF0000U) #define LCDIFV2_CSC_COEF2_C2_SHIFT (16U) -/*! C2 - Two's compliment Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813). +/*! C2 - Two's compliment Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813) */ #define LCDIFV2_CSC_COEF2_C2(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF2_C2_SHIFT)) & LCDIFV2_CSC_COEF2_C2_MASK) /*! @} */ @@ -59261,13 +69215,15 @@ typedef struct { /* The count of LCDIFV2_CSC_COEF2 */ #define LCDIFV2_CSC_COEF2_COUNT (8U) -/*! @name CLUT_LOAD - LCDIF CLUT load Register */ +/*! @name CLUT_LOAD - LCDIFv2 CLUT load Register */ /*! @{ */ + #define LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_MASK (0x1U) #define LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_SHIFT (0U) /*! CLUT_UPDATE_EN - CLUT Update Enable */ #define LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_SHIFT)) & LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_MASK) + #define LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_MASK (0x70U) #define LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_SHIFT (4U) /*! SEL_CLUT_NUM - Selected CLUT Number @@ -59307,46 +69263,46 @@ typedef struct { /** LPI2C - Register Layout Typedef */ typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ uint8_t RESERVED_0[8]; - __IO uint32_t MCR; /**< Master Control Register, offset: 0x10 */ - __IO uint32_t MSR; /**< Master Status Register, offset: 0x14 */ - __IO uint32_t MIER; /**< Master Interrupt Enable Register, offset: 0x18 */ - __IO uint32_t MDER; /**< Master DMA Enable Register, offset: 0x1C */ - __IO uint32_t MCFGR0; /**< Master Configuration Register 0, offset: 0x20 */ - __IO uint32_t MCFGR1; /**< Master Configuration Register 1, offset: 0x24 */ - __IO uint32_t MCFGR2; /**< Master Configuration Register 2, offset: 0x28 */ - __IO uint32_t MCFGR3; /**< Master Configuration Register 3, offset: 0x2C */ + __IO uint32_t MCR; /**< Master Control, offset: 0x10 */ + __IO uint32_t MSR; /**< Master Status, offset: 0x14 */ + __IO uint32_t MIER; /**< Master Interrupt Enable, offset: 0x18 */ + __IO uint32_t MDER; /**< Master DMA Enable, offset: 0x1C */ + __IO uint32_t MCFGR0; /**< Master Configuration 0, offset: 0x20 */ + __IO uint32_t MCFGR1; /**< Master Configuration 1, offset: 0x24 */ + __IO uint32_t MCFGR2; /**< Master Configuration 2, offset: 0x28 */ + __IO uint32_t MCFGR3; /**< Master Configuration 3, offset: 0x2C */ uint8_t RESERVED_1[16]; - __IO uint32_t MDMR; /**< Master Data Match Register, offset: 0x40 */ + __IO uint32_t MDMR; /**< Master Data Match, offset: 0x40 */ uint8_t RESERVED_2[4]; - __IO uint32_t MCCR0; /**< Master Clock Configuration Register 0, offset: 0x48 */ + __IO uint32_t MCCR0; /**< Master Clock Configuration 0, offset: 0x48 */ uint8_t RESERVED_3[4]; - __IO uint32_t MCCR1; /**< Master Clock Configuration Register 1, offset: 0x50 */ + __IO uint32_t MCCR1; /**< Master Clock Configuration 1, offset: 0x50 */ uint8_t RESERVED_4[4]; - __IO uint32_t MFCR; /**< Master FIFO Control Register, offset: 0x58 */ - __I uint32_t MFSR; /**< Master FIFO Status Register, offset: 0x5C */ - __O uint32_t MTDR; /**< Master Transmit Data Register, offset: 0x60 */ + __IO uint32_t MFCR; /**< Master FIFO Control, offset: 0x58 */ + __I uint32_t MFSR; /**< Master FIFO Status, offset: 0x5C */ + __O uint32_t MTDR; /**< Master Transmit Data, offset: 0x60 */ uint8_t RESERVED_5[12]; - __I uint32_t MRDR; /**< Master Receive Data Register, offset: 0x70 */ + __I uint32_t MRDR; /**< Master Receive Data, offset: 0x70 */ uint8_t RESERVED_6[156]; - __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */ - __IO uint32_t SSR; /**< Slave Status Register, offset: 0x114 */ - __IO uint32_t SIER; /**< Slave Interrupt Enable Register, offset: 0x118 */ - __IO uint32_t SDER; /**< Slave DMA Enable Register, offset: 0x11C */ + __IO uint32_t SCR; /**< Slave Control, offset: 0x110 */ + __IO uint32_t SSR; /**< Slave Status, offset: 0x114 */ + __IO uint32_t SIER; /**< Slave Interrupt Enable, offset: 0x118 */ + __IO uint32_t SDER; /**< Slave DMA Enable, offset: 0x11C */ uint8_t RESERVED_7[4]; - __IO uint32_t SCFGR1; /**< Slave Configuration Register 1, offset: 0x124 */ - __IO uint32_t SCFGR2; /**< Slave Configuration Register 2, offset: 0x128 */ + __IO uint32_t SCFGR1; /**< Slave Configuration 1, offset: 0x124 */ + __IO uint32_t SCFGR2; /**< Slave Configuration 2, offset: 0x128 */ uint8_t RESERVED_8[20]; - __IO uint32_t SAMR; /**< Slave Address Match Register, offset: 0x140 */ + __IO uint32_t SAMR; /**< Slave Address Match, offset: 0x140 */ uint8_t RESERVED_9[12]; - __I uint32_t SASR; /**< Slave Address Status Register, offset: 0x150 */ - __IO uint32_t STAR; /**< Slave Transmit ACK Register, offset: 0x154 */ + __I uint32_t SASR; /**< Slave Address Status, offset: 0x150 */ + __IO uint32_t STAR; /**< Slave Transmit ACK, offset: 0x154 */ uint8_t RESERVED_10[8]; - __O uint32_t STDR; /**< Slave Transmit Data Register, offset: 0x160 */ + __O uint32_t STDR; /**< Slave Transmit Data, offset: 0x160 */ uint8_t RESERVED_11[12]; - __I uint32_t SRDR; /**< Slave Receive Data Register, offset: 0x170 */ + __I uint32_t SRDR; /**< Slave Receive Data, offset: 0x170 */ } LPI2C_Type; /* ---------------------------------------------------------------------------- @@ -59358,8 +69314,9 @@ typedef struct { * @{ */ -/*! @name VERID - Version ID Register */ +/*! @name VERID - Version ID */ /*! @{ */ + #define LPI2C_VERID_FEATURE_MASK (0xFFFFU) #define LPI2C_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Specification Number @@ -59367,11 +69324,13 @@ typedef struct { * 0b0000000000000011..Master and slave, with standard feature set */ #define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK) + #define LPI2C_VERID_MINOR_MASK (0xFF0000U) #define LPI2C_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK) + #define LPI2C_VERID_MAJOR_MASK (0xFF000000U) #define LPI2C_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number @@ -59379,13 +69338,15 @@ typedef struct { #define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK) /*! @} */ -/*! @name PARAM - Parameter Register */ +/*! @name PARAM - Parameter */ /*! @{ */ + #define LPI2C_PARAM_MTXFIFO_MASK (0xFU) #define LPI2C_PARAM_MTXFIFO_SHIFT (0U) /*! MTXFIFO - Master Transmit FIFO Size */ #define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK) + #define LPI2C_PARAM_MRXFIFO_MASK (0xF00U) #define LPI2C_PARAM_MRXFIFO_SHIFT (8U) /*! MRXFIFO - Master Receive FIFO Size @@ -59393,8 +69354,9 @@ typedef struct { #define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK) /*! @} */ -/*! @name MCR - Master Control Register */ +/*! @name MCR - Master Control */ /*! @{ */ + #define LPI2C_MCR_MEN_MASK (0x1U) #define LPI2C_MCR_MEN_SHIFT (0U) /*! MEN - Master Enable @@ -59402,6 +69364,7 @@ typedef struct { * 0b1..Master logic is enabled */ #define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK) + #define LPI2C_MCR_RST_MASK (0x2U) #define LPI2C_MCR_RST_SHIFT (1U) /*! RST - Software Reset @@ -59409,6 +69372,7 @@ typedef struct { * 0b1..Master logic is reset */ #define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK) + #define LPI2C_MCR_DOZEN_MASK (0x4U) #define LPI2C_MCR_DOZEN_SHIFT (2U) /*! DOZEN - Doze mode enable @@ -59416,6 +69380,7 @@ typedef struct { * 0b1..Master is disabled in Doze mode */ #define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK) + #define LPI2C_MCR_DBGEN_MASK (0x8U) #define LPI2C_MCR_DBGEN_SHIFT (3U) /*! DBGEN - Debug Enable @@ -59423,6 +69388,7 @@ typedef struct { * 0b1..Master is enabled in debug mode */ #define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK) + #define LPI2C_MCR_RTF_MASK (0x100U) #define LPI2C_MCR_RTF_SHIFT (8U) /*! RTF - Reset Transmit FIFO @@ -59430,6 +69396,7 @@ typedef struct { * 0b1..Transmit FIFO is reset */ #define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK) + #define LPI2C_MCR_RRF_MASK (0x200U) #define LPI2C_MCR_RRF_SHIFT (9U) /*! RRF - Reset Receive FIFO @@ -59439,8 +69406,9 @@ typedef struct { #define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK) /*! @} */ -/*! @name MSR - Master Status Register */ +/*! @name MSR - Master Status */ /*! @{ */ + #define LPI2C_MSR_TDF_MASK (0x1U) #define LPI2C_MSR_TDF_SHIFT (0U) /*! TDF - Transmit Data Flag @@ -59448,6 +69416,7 @@ typedef struct { * 0b1..Transmit data is requested */ #define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK) + #define LPI2C_MSR_RDF_MASK (0x2U) #define LPI2C_MSR_RDF_SHIFT (1U) /*! RDF - Receive Data Flag @@ -59455,6 +69424,7 @@ typedef struct { * 0b1..Receive data is ready */ #define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK) + #define LPI2C_MSR_EPF_MASK (0x100U) #define LPI2C_MSR_EPF_SHIFT (8U) /*! EPF - End Packet Flag @@ -59462,6 +69432,7 @@ typedef struct { * 0b1..Master has generated a STOP or Repeated START condition */ #define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK) + #define LPI2C_MSR_SDF_MASK (0x200U) #define LPI2C_MSR_SDF_SHIFT (9U) /*! SDF - STOP Detect Flag @@ -59469,6 +69440,7 @@ typedef struct { * 0b1..Master has generated a STOP condition */ #define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK) + #define LPI2C_MSR_NDF_MASK (0x400U) #define LPI2C_MSR_NDF_SHIFT (10U) /*! NDF - NACK Detect Flag @@ -59476,6 +69448,7 @@ typedef struct { * 0b1..Unexpected NACK was detected */ #define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK) + #define LPI2C_MSR_ALF_MASK (0x800U) #define LPI2C_MSR_ALF_SHIFT (11U) /*! ALF - Arbitration Lost Flag @@ -59483,6 +69456,7 @@ typedef struct { * 0b1..Master has lost arbitration */ #define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK) + #define LPI2C_MSR_FEF_MASK (0x1000U) #define LPI2C_MSR_FEF_SHIFT (12U) /*! FEF - FIFO Error Flag @@ -59490,6 +69464,7 @@ typedef struct { * 0b1..Master sending or receiving data without a START condition */ #define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK) + #define LPI2C_MSR_PLTF_MASK (0x2000U) #define LPI2C_MSR_PLTF_SHIFT (13U) /*! PLTF - Pin Low Timeout Flag @@ -59497,6 +69472,7 @@ typedef struct { * 0b1..Pin low timeout has occurred */ #define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK) + #define LPI2C_MSR_DMF_MASK (0x4000U) #define LPI2C_MSR_DMF_SHIFT (14U) /*! DMF - Data Match Flag @@ -59504,6 +69480,7 @@ typedef struct { * 0b1..Have received matching data */ #define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK) + #define LPI2C_MSR_MBF_MASK (0x1000000U) #define LPI2C_MSR_MBF_SHIFT (24U) /*! MBF - Master Busy Flag @@ -59511,6 +69488,7 @@ typedef struct { * 0b1..I2C Master is busy */ #define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK) + #define LPI2C_MSR_BBF_MASK (0x2000000U) #define LPI2C_MSR_BBF_SHIFT (25U) /*! BBF - Bus Busy Flag @@ -59520,8 +69498,9 @@ typedef struct { #define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK) /*! @} */ -/*! @name MIER - Master Interrupt Enable Register */ +/*! @name MIER - Master Interrupt Enable */ /*! @{ */ + #define LPI2C_MIER_TDIE_MASK (0x1U) #define LPI2C_MIER_TDIE_SHIFT (0U) /*! TDIE - Transmit Data Interrupt Enable @@ -59529,6 +69508,7 @@ typedef struct { * 0b1..Enabled */ #define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK) + #define LPI2C_MIER_RDIE_MASK (0x2U) #define LPI2C_MIER_RDIE_SHIFT (1U) /*! RDIE - Receive Data Interrupt Enable @@ -59536,6 +69516,7 @@ typedef struct { * 0b1..Enabled */ #define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK) + #define LPI2C_MIER_EPIE_MASK (0x100U) #define LPI2C_MIER_EPIE_SHIFT (8U) /*! EPIE - End Packet Interrupt Enable @@ -59543,6 +69524,7 @@ typedef struct { * 0b1..Enabled */ #define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK) + #define LPI2C_MIER_SDIE_MASK (0x200U) #define LPI2C_MIER_SDIE_SHIFT (9U) /*! SDIE - STOP Detect Interrupt Enable @@ -59550,6 +69532,7 @@ typedef struct { * 0b1..Enabled */ #define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK) + #define LPI2C_MIER_NDIE_MASK (0x400U) #define LPI2C_MIER_NDIE_SHIFT (10U) /*! NDIE - NACK Detect Interrupt Enable @@ -59557,6 +69540,7 @@ typedef struct { * 0b1..Enabled */ #define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK) + #define LPI2C_MIER_ALIE_MASK (0x800U) #define LPI2C_MIER_ALIE_SHIFT (11U) /*! ALIE - Arbitration Lost Interrupt Enable @@ -59564,6 +69548,7 @@ typedef struct { * 0b1..Enabled */ #define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK) + #define LPI2C_MIER_FEIE_MASK (0x1000U) #define LPI2C_MIER_FEIE_SHIFT (12U) /*! FEIE - FIFO Error Interrupt Enable @@ -59571,6 +69556,7 @@ typedef struct { * 0b1..Disabled */ #define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK) + #define LPI2C_MIER_PLTIE_MASK (0x2000U) #define LPI2C_MIER_PLTIE_SHIFT (13U) /*! PLTIE - Pin Low Timeout Interrupt Enable @@ -59578,6 +69564,7 @@ typedef struct { * 0b1..Enabled */ #define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK) + #define LPI2C_MIER_DMIE_MASK (0x4000U) #define LPI2C_MIER_DMIE_SHIFT (14U) /*! DMIE - Data Match Interrupt Enable @@ -59587,8 +69574,9 @@ typedef struct { #define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK) /*! @} */ -/*! @name MDER - Master DMA Enable Register */ +/*! @name MDER - Master DMA Enable */ /*! @{ */ + #define LPI2C_MDER_TDDE_MASK (0x1U) #define LPI2C_MDER_TDDE_SHIFT (0U) /*! TDDE - Transmit Data DMA Enable @@ -59596,6 +69584,7 @@ typedef struct { * 0b1..DMA request is enabled */ #define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK) + #define LPI2C_MDER_RDDE_MASK (0x2U) #define LPI2C_MDER_RDDE_SHIFT (1U) /*! RDDE - Receive Data DMA Enable @@ -59605,8 +69594,9 @@ typedef struct { #define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK) /*! @} */ -/*! @name MCFGR0 - Master Configuration Register 0 */ +/*! @name MCFGR0 - Master Configuration 0 */ /*! @{ */ + #define LPI2C_MCFGR0_HREN_MASK (0x1U) #define LPI2C_MCFGR0_HREN_SHIFT (0U) /*! HREN - Host Request Enable @@ -59614,6 +69604,7 @@ typedef struct { * 0b1..Host request input is enabled */ #define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK) + #define LPI2C_MCFGR0_HRPOL_MASK (0x2U) #define LPI2C_MCFGR0_HRPOL_SHIFT (1U) /*! HRPOL - Host Request Polarity @@ -59621,6 +69612,7 @@ typedef struct { * 0b1..Active high */ #define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK) + #define LPI2C_MCFGR0_HRSEL_MASK (0x4U) #define LPI2C_MCFGR0_HRSEL_SHIFT (2U) /*! HRSEL - Host Request Select @@ -59628,6 +69620,7 @@ typedef struct { * 0b1..Host request input is input trigger */ #define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK) + #define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U) #define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U) /*! CIRFIFO - Circular FIFO Enable @@ -59635,6 +69628,7 @@ typedef struct { * 0b1..Circular FIFO is enabled */ #define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK) + #define LPI2C_MCFGR0_RDMO_MASK (0x200U) #define LPI2C_MCFGR0_RDMO_SHIFT (9U) /*! RDMO - Receive Data Match Only @@ -59644,8 +69638,9 @@ typedef struct { #define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK) /*! @} */ -/*! @name MCFGR1 - Master Configuration Register 1 */ +/*! @name MCFGR1 - Master Configuration 1 */ /*! @{ */ + #define LPI2C_MCFGR1_PRESCALE_MASK (0x7U) #define LPI2C_MCFGR1_PRESCALE_SHIFT (0U) /*! PRESCALE - Prescaler @@ -59659,6 +69654,7 @@ typedef struct { * 0b111..Divide by 128 */ #define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK) + #define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U) #define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U) /*! AUTOSTOP - Automatic STOP Generation @@ -59666,33 +69662,37 @@ typedef struct { * 0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy */ #define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK) + #define LPI2C_MCFGR1_IGNACK_MASK (0x200U) #define LPI2C_MCFGR1_IGNACK_SHIFT (9U) /*! IGNACK - IGNACK - * 0b0..LPI2C Master will receive ACK and NACK normally - * 0b1..LPI2C Master will treat a received NACK as if it (NACK) was an ACK + * 0b0..LPI2C Master receives ACK and NACK normally + * 0b1..LPI2C Master treats a received NACK as if it (NACK) was an ACK */ #define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK) + #define LPI2C_MCFGR1_TIMECFG_MASK (0x400U) #define LPI2C_MCFGR1_TIMECFG_SHIFT (10U) /*! TIMECFG - Timeout Configuration - * 0b0..Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout - * 0b1..Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout + * 0b0..MSR[PLTF] sets if SCL is low for longer than the configured timeout + * 0b1..MSR[PLTF] sets if either SCL or SDA is low for longer than the configured timeout */ #define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK) + #define LPI2C_MCFGR1_MATCFG_MASK (0x70000U) #define LPI2C_MCFGR1_MATCFG_SHIFT (16U) /*! MATCFG - Match Configuration * 0b000..Match is disabled * 0b001..Reserved - * 0b010..Match is enabled (1st data word equals MATCH0 OR MATCH1) - * 0b011..Match is enabled (any data word equals MATCH0 OR MATCH1) - * 0b100..Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1) - * 0b101..Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1) - * 0b110..Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1) - * 0b111..Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1) + * 0b010..Match is enabled (1st data word equals MDMR[MATCH0] OR MDMR[MATCH1]) + * 0b011..Match is enabled (any data word equals MDMR[MATCH0] OR MDMR[MATCH1]) + * 0b100..Match is enabled (1st data word equals MDMR[MATCH0] AND 2nd data word equals MDMR[MATCH1) + * 0b101..Match is enabled (any data word equals MDMR[MATCH0] AND next data word equals MDMR[MATCH1) + * 0b110..Match is enabled (1st data word AND MDMR[MATCH1] equals MDMR[MATCH0] AND MDMR[MATCH1]) + * 0b111..Match is enabled (any data word AND MDMR[MATCH1] equals MDMR[MATCH0] AND MDMR[MATCH1]) */ #define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK) + #define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U) #define LPI2C_MCFGR1_PINCFG_SHIFT (24U) /*! PINCFG - Pin Configuration @@ -59708,18 +69708,21 @@ typedef struct { #define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK) /*! @} */ -/*! @name MCFGR2 - Master Configuration Register 2 */ +/*! @name MCFGR2 - Master Configuration 2 */ /*! @{ */ + #define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU) #define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U) /*! BUSIDLE - Bus Idle Timeout */ #define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK) + #define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U) #define LPI2C_MCFGR2_FILTSCL_SHIFT (16U) /*! FILTSCL - Glitch Filter SCL */ #define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK) + #define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U) #define LPI2C_MCFGR2_FILTSDA_SHIFT (24U) /*! FILTSDA - Glitch Filter SDA @@ -59727,8 +69730,9 @@ typedef struct { #define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK) /*! @} */ -/*! @name MCFGR3 - Master Configuration Register 3 */ +/*! @name MCFGR3 - Master Configuration 3 */ /*! @{ */ + #define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U) #define LPI2C_MCFGR3_PINLOW_SHIFT (8U) /*! PINLOW - Pin Low Timeout @@ -59736,13 +69740,15 @@ typedef struct { #define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK) /*! @} */ -/*! @name MDMR - Master Data Match Register */ +/*! @name MDMR - Master Data Match */ /*! @{ */ + #define LPI2C_MDMR_MATCH0_MASK (0xFFU) #define LPI2C_MDMR_MATCH0_SHIFT (0U) /*! MATCH0 - Match 0 Value */ #define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK) + #define LPI2C_MDMR_MATCH1_MASK (0xFF0000U) #define LPI2C_MDMR_MATCH1_SHIFT (16U) /*! MATCH1 - Match 1 Value @@ -59750,23 +69756,27 @@ typedef struct { #define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK) /*! @} */ -/*! @name MCCR0 - Master Clock Configuration Register 0 */ +/*! @name MCCR0 - Master Clock Configuration 0 */ /*! @{ */ + #define LPI2C_MCCR0_CLKLO_MASK (0x3FU) #define LPI2C_MCCR0_CLKLO_SHIFT (0U) /*! CLKLO - Clock Low Period */ #define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK) + #define LPI2C_MCCR0_CLKHI_MASK (0x3F00U) #define LPI2C_MCCR0_CLKHI_SHIFT (8U) /*! CLKHI - Clock High Period */ #define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK) + #define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U) #define LPI2C_MCCR0_SETHOLD_SHIFT (16U) /*! SETHOLD - Setup Hold Delay */ #define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK) + #define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U) #define LPI2C_MCCR0_DATAVD_SHIFT (24U) /*! DATAVD - Data Valid Delay @@ -59774,23 +69784,27 @@ typedef struct { #define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK) /*! @} */ -/*! @name MCCR1 - Master Clock Configuration Register 1 */ +/*! @name MCCR1 - Master Clock Configuration 1 */ /*! @{ */ + #define LPI2C_MCCR1_CLKLO_MASK (0x3FU) #define LPI2C_MCCR1_CLKLO_SHIFT (0U) /*! CLKLO - Clock Low Period */ #define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK) + #define LPI2C_MCCR1_CLKHI_MASK (0x3F00U) #define LPI2C_MCCR1_CLKHI_SHIFT (8U) /*! CLKHI - Clock High Period */ #define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK) + #define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U) #define LPI2C_MCCR1_SETHOLD_SHIFT (16U) /*! SETHOLD - Setup Hold Delay */ #define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK) + #define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U) #define LPI2C_MCCR1_DATAVD_SHIFT (24U) /*! DATAVD - Data Valid Delay @@ -59798,13 +69812,15 @@ typedef struct { #define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK) /*! @} */ -/*! @name MFCR - Master FIFO Control Register */ +/*! @name MFCR - Master FIFO Control */ /*! @{ */ + #define LPI2C_MFCR_TXWATER_MASK (0x3U) #define LPI2C_MFCR_TXWATER_SHIFT (0U) /*! TXWATER - Transmit FIFO Watermark */ #define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK) + #define LPI2C_MFCR_RXWATER_MASK (0x30000U) #define LPI2C_MFCR_RXWATER_SHIFT (16U) /*! RXWATER - Receive FIFO Watermark @@ -59812,13 +69828,15 @@ typedef struct { #define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK) /*! @} */ -/*! @name MFSR - Master FIFO Status Register */ +/*! @name MFSR - Master FIFO Status */ /*! @{ */ + #define LPI2C_MFSR_TXCOUNT_MASK (0x7U) #define LPI2C_MFSR_TXCOUNT_SHIFT (0U) /*! TXCOUNT - Transmit FIFO Count */ #define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK) + #define LPI2C_MFSR_RXCOUNT_MASK (0x70000U) #define LPI2C_MFSR_RXCOUNT_SHIFT (16U) /*! RXCOUNT - Receive FIFO Count @@ -59826,13 +69844,15 @@ typedef struct { #define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK) /*! @} */ -/*! @name MTDR - Master Transmit Data Register */ +/*! @name MTDR - Master Transmit Data */ /*! @{ */ + #define LPI2C_MTDR_DATA_MASK (0xFFU) #define LPI2C_MTDR_DATA_SHIFT (0U) /*! DATA - Transmit Data */ #define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK) + #define LPI2C_MTDR_CMD_MASK (0x700U) #define LPI2C_MTDR_CMD_SHIFT (8U) /*! CMD - Command Data @@ -59848,13 +69868,15 @@ typedef struct { #define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK) /*! @} */ -/*! @name MRDR - Master Receive Data Register */ +/*! @name MRDR - Master Receive Data */ /*! @{ */ + #define LPI2C_MRDR_DATA_MASK (0xFFU) #define LPI2C_MRDR_DATA_SHIFT (0U) /*! DATA - Receive Data */ #define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK) + #define LPI2C_MRDR_RXEMPTY_MASK (0x4000U) #define LPI2C_MRDR_RXEMPTY_SHIFT (14U) /*! RXEMPTY - RX Empty @@ -59864,8 +69886,9 @@ typedef struct { #define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK) /*! @} */ -/*! @name SCR - Slave Control Register */ +/*! @name SCR - Slave Control */ /*! @{ */ + #define LPI2C_SCR_SEN_MASK (0x1U) #define LPI2C_SCR_SEN_SHIFT (0U) /*! SEN - Slave Enable @@ -59873,6 +69896,7 @@ typedef struct { * 0b1..I2C Slave mode is enabled */ #define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK) + #define LPI2C_SCR_RST_MASK (0x2U) #define LPI2C_SCR_RST_SHIFT (1U) /*! RST - Software Reset @@ -59880,6 +69904,7 @@ typedef struct { * 0b1..Slave mode logic is reset */ #define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK) + #define LPI2C_SCR_FILTEN_MASK (0x10U) #define LPI2C_SCR_FILTEN_SHIFT (4U) /*! FILTEN - Filter Enable @@ -59887,6 +69912,7 @@ typedef struct { * 0b1..Enable digital filter and output delay counter for slave mode */ #define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK) + #define LPI2C_SCR_FILTDZ_MASK (0x20U) #define LPI2C_SCR_FILTDZ_SHIFT (5U) /*! FILTDZ - Filter Doze Enable @@ -59894,6 +69920,7 @@ typedef struct { * 0b1..Filter is disabled in Doze mode */ #define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK) + #define LPI2C_SCR_RTF_MASK (0x100U) #define LPI2C_SCR_RTF_SHIFT (8U) /*! RTF - Reset Transmit FIFO @@ -59901,6 +69928,7 @@ typedef struct { * 0b1..Transmit Data Register is now empty */ #define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK) + #define LPI2C_SCR_RRF_MASK (0x200U) #define LPI2C_SCR_RRF_SHIFT (9U) /*! RRF - Reset Receive FIFO @@ -59910,8 +69938,9 @@ typedef struct { #define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK) /*! @} */ -/*! @name SSR - Slave Status Register */ +/*! @name SSR - Slave Status */ /*! @{ */ + #define LPI2C_SSR_TDF_MASK (0x1U) #define LPI2C_SSR_TDF_SHIFT (0U) /*! TDF - Transmit Data Flag @@ -59919,6 +69948,7 @@ typedef struct { * 0b1..Transmit data is requested */ #define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK) + #define LPI2C_SSR_RDF_MASK (0x2U) #define LPI2C_SSR_RDF_SHIFT (1U) /*! RDF - Receive Data Flag @@ -59926,6 +69956,7 @@ typedef struct { * 0b1..Receive data is ready */ #define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK) + #define LPI2C_SSR_AVF_MASK (0x4U) #define LPI2C_SSR_AVF_SHIFT (2U) /*! AVF - Address Valid Flag @@ -59933,6 +69964,7 @@ typedef struct { * 0b1..Address Status Register is valid */ #define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK) + #define LPI2C_SSR_TAF_MASK (0x8U) #define LPI2C_SSR_TAF_SHIFT (3U) /*! TAF - Transmit ACK Flag @@ -59940,6 +69972,7 @@ typedef struct { * 0b1..Transmit ACK/NACK is required */ #define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK) + #define LPI2C_SSR_RSF_MASK (0x100U) #define LPI2C_SSR_RSF_SHIFT (8U) /*! RSF - Repeated Start Flag @@ -59947,6 +69980,7 @@ typedef struct { * 0b1..Slave has detected a Repeated START condition */ #define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK) + #define LPI2C_SSR_SDF_MASK (0x200U) #define LPI2C_SSR_SDF_SHIFT (9U) /*! SDF - STOP Detect Flag @@ -59954,6 +69988,7 @@ typedef struct { * 0b1..Slave has detected a STOP condition */ #define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK) + #define LPI2C_SSR_BEF_MASK (0x400U) #define LPI2C_SSR_BEF_SHIFT (10U) /*! BEF - Bit Error Flag @@ -59961,6 +69996,7 @@ typedef struct { * 0b1..Slave has detected a bit error */ #define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK) + #define LPI2C_SSR_FEF_MASK (0x800U) #define LPI2C_SSR_FEF_SHIFT (11U) /*! FEF - FIFO Error Flag @@ -59968,6 +70004,7 @@ typedef struct { * 0b1..FIFO underflow or overflow was detected */ #define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK) + #define LPI2C_SSR_AM0F_MASK (0x1000U) #define LPI2C_SSR_AM0F_SHIFT (12U) /*! AM0F - Address Match 0 Flag @@ -59975,6 +70012,7 @@ typedef struct { * 0b1..Have received an ADDR0 matching address */ #define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK) + #define LPI2C_SSR_AM1F_MASK (0x2000U) #define LPI2C_SSR_AM1F_SHIFT (13U) /*! AM1F - Address Match 1 Flag @@ -59982,6 +70020,7 @@ typedef struct { * 0b1..Have received an ADDR1 or ADDR0/ADDR1 range matching address */ #define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK) + #define LPI2C_SSR_GCF_MASK (0x4000U) #define LPI2C_SSR_GCF_SHIFT (14U) /*! GCF - General Call Flag @@ -59989,6 +70028,7 @@ typedef struct { * 0b1..Slave has detected the General Call Address */ #define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK) + #define LPI2C_SSR_SARF_MASK (0x8000U) #define LPI2C_SSR_SARF_SHIFT (15U) /*! SARF - SMBus Alert Response Flag @@ -59996,6 +70036,7 @@ typedef struct { * 0b1..SMBus Alert Response is enabled and detected */ #define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK) + #define LPI2C_SSR_SBF_MASK (0x1000000U) #define LPI2C_SSR_SBF_SHIFT (24U) /*! SBF - Slave Busy Flag @@ -60003,6 +70044,7 @@ typedef struct { * 0b1..I2C Slave is busy */ #define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK) + #define LPI2C_SSR_BBF_MASK (0x2000000U) #define LPI2C_SSR_BBF_SHIFT (25U) /*! BBF - Bus Busy Flag @@ -60012,8 +70054,9 @@ typedef struct { #define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK) /*! @} */ -/*! @name SIER - Slave Interrupt Enable Register */ +/*! @name SIER - Slave Interrupt Enable */ /*! @{ */ + #define LPI2C_SIER_TDIE_MASK (0x1U) #define LPI2C_SIER_TDIE_SHIFT (0U) /*! TDIE - Transmit Data Interrupt Enable @@ -60021,6 +70064,7 @@ typedef struct { * 0b1..Enabled */ #define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK) + #define LPI2C_SIER_RDIE_MASK (0x2U) #define LPI2C_SIER_RDIE_SHIFT (1U) /*! RDIE - Receive Data Interrupt Enable @@ -60028,6 +70072,7 @@ typedef struct { * 0b1..Enabled */ #define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK) + #define LPI2C_SIER_AVIE_MASK (0x4U) #define LPI2C_SIER_AVIE_SHIFT (2U) /*! AVIE - Address Valid Interrupt Enable @@ -60035,6 +70080,7 @@ typedef struct { * 0b1..Enabled */ #define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK) + #define LPI2C_SIER_TAIE_MASK (0x8U) #define LPI2C_SIER_TAIE_SHIFT (3U) /*! TAIE - Transmit ACK Interrupt Enable @@ -60042,6 +70088,7 @@ typedef struct { * 0b1..Enabled */ #define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK) + #define LPI2C_SIER_RSIE_MASK (0x100U) #define LPI2C_SIER_RSIE_SHIFT (8U) /*! RSIE - Repeated Start Interrupt Enable @@ -60049,6 +70096,7 @@ typedef struct { * 0b1..Enabled */ #define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK) + #define LPI2C_SIER_SDIE_MASK (0x200U) #define LPI2C_SIER_SDIE_SHIFT (9U) /*! SDIE - STOP Detect Interrupt Enable @@ -60056,6 +70104,7 @@ typedef struct { * 0b1..Enabled */ #define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK) + #define LPI2C_SIER_BEIE_MASK (0x400U) #define LPI2C_SIER_BEIE_SHIFT (10U) /*! BEIE - Bit Error Interrupt Enable @@ -60063,6 +70112,7 @@ typedef struct { * 0b1..Enabled */ #define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK) + #define LPI2C_SIER_FEIE_MASK (0x800U) #define LPI2C_SIER_FEIE_SHIFT (11U) /*! FEIE - FIFO Error Interrupt Enable @@ -60070,20 +70120,23 @@ typedef struct { * 0b1..Enabled */ #define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK) + #define LPI2C_SIER_AM0IE_MASK (0x1000U) #define LPI2C_SIER_AM0IE_SHIFT (12U) /*! AM0IE - Address Match 0 Interrupt Enable - * 0b0..Enabled - * 0b1..Disabled + * 0b0..Disabled + * 0b1..Enabled */ #define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK) -#define LPI2C_SIER_AM1F_MASK (0x2000U) -#define LPI2C_SIER_AM1F_SHIFT (13U) -/*! AM1F - Address Match 1 Interrupt Enable + +#define LPI2C_SIER_AM1IE_MASK (0x2000U) +#define LPI2C_SIER_AM1IE_SHIFT (13U) +/*! AM1IE - Address Match 1 Interrupt Enable * 0b0..Disabled * 0b1..Enabled */ -#define LPI2C_SIER_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1F_SHIFT)) & LPI2C_SIER_AM1F_MASK) +#define LPI2C_SIER_AM1IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK) + #define LPI2C_SIER_GCIE_MASK (0x4000U) #define LPI2C_SIER_GCIE_SHIFT (14U) /*! GCIE - General Call Interrupt Enable @@ -60091,6 +70144,7 @@ typedef struct { * 0b1..Enabled */ #define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK) + #define LPI2C_SIER_SARIE_MASK (0x8000U) #define LPI2C_SIER_SARIE_SHIFT (15U) /*! SARIE - SMBus Alert Response Interrupt Enable @@ -60100,8 +70154,9 @@ typedef struct { #define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK) /*! @} */ -/*! @name SDER - Slave DMA Enable Register */ +/*! @name SDER - Slave DMA Enable */ /*! @{ */ + #define LPI2C_SDER_TDDE_MASK (0x1U) #define LPI2C_SDER_TDDE_SHIFT (0U) /*! TDDE - Transmit Data DMA Enable @@ -60109,6 +70164,7 @@ typedef struct { * 0b1..DMA request is enabled */ #define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK) + #define LPI2C_SDER_RDDE_MASK (0x2U) #define LPI2C_SDER_RDDE_SHIFT (1U) /*! RDDE - Receive Data DMA Enable @@ -60116,6 +70172,7 @@ typedef struct { * 0b1..DMA request is enabled */ #define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK) + #define LPI2C_SDER_AVDE_MASK (0x4U) #define LPI2C_SDER_AVDE_SHIFT (2U) /*! AVDE - Address Valid DMA Enable @@ -60125,8 +70182,9 @@ typedef struct { #define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK) /*! @} */ -/*! @name SCFGR1 - Slave Configuration Register 1 */ +/*! @name SCFGR1 - Slave Configuration 1 */ /*! @{ */ + #define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U) #define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U) /*! ADRSTALL - Address SCL Stall @@ -60134,6 +70192,7 @@ typedef struct { * 0b1..Clock stretching is enabled */ #define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK) + #define LPI2C_SCFGR1_RXSTALL_MASK (0x2U) #define LPI2C_SCFGR1_RXSTALL_SHIFT (1U) /*! RXSTALL - RX SCL Stall @@ -60141,6 +70200,7 @@ typedef struct { * 0b1..Clock stretching is enabled */ #define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK) + #define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U) #define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U) /*! TXDSTALL - TX Data SCL Stall @@ -60148,6 +70208,7 @@ typedef struct { * 0b1..Clock stretching is enabled */ #define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK) + #define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U) #define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U) /*! ACKSTALL - ACK SCL Stall @@ -60155,6 +70216,7 @@ typedef struct { * 0b1..Clock stretching is enabled */ #define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK) + #define LPI2C_SCFGR1_GCEN_MASK (0x100U) #define LPI2C_SCFGR1_GCEN_SHIFT (8U) /*! GCEN - General Call Enable @@ -60162,6 +70224,7 @@ typedef struct { * 0b1..General Call address is enabled */ #define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK) + #define LPI2C_SCFGR1_SAEN_MASK (0x200U) #define LPI2C_SCFGR1_SAEN_SHIFT (9U) /*! SAEN - SMBus Alert Enable @@ -60169,29 +70232,33 @@ typedef struct { * 0b1..Enables match on SMBus Alert */ #define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK) + #define LPI2C_SCFGR1_TXCFG_MASK (0x400U) #define LPI2C_SCFGR1_TXCFG_SHIFT (10U) /*! TXCFG - Transmit Flag Configuration - * 0b0..Transmit Data Flag will only assert during a slave-transmit transfer when the Transmit Data register is empty - * 0b1..Transmit Data Flag will assert whenever the Transmit Data register is empty + * 0b0..Transmit Data Flag only asserts during a slave-transmit transfer when the Transmit Data register is empty + * 0b1..Transmit Data Flag asserts whenever the Transmit Data register is empty */ #define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK) + #define LPI2C_SCFGR1_RXCFG_MASK (0x800U) #define LPI2C_SCFGR1_RXCFG_SHIFT (11U) /*! RXCFG - Receive Data Configuration - * 0b0..Reading the Receive Data register will return received data and clear the Receive Data flag (MSR[RDF]). - * 0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, will return the Address - * Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid - * flag is clear, will return received data and clear the Receive Data flag (MSR[RDF]). + * 0b0..Reading the Receive Data register returns received data and clears the Receive Data flag (MSR[RDF]). + * 0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, returns the Address + * Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag + * is clear, returns received data and clears the Receive Data flag (MSR[RDF]). */ #define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK) + #define LPI2C_SCFGR1_IGNACK_MASK (0x1000U) #define LPI2C_SCFGR1_IGNACK_SHIFT (12U) /*! IGNACK - Ignore NACK - * 0b0..Slave will end transfer when NACK is detected - * 0b1..Slave will not end transfer when NACK detected + * 0b0..Slave ends transfer when NACK is detected + * 0b1..Slave does not end transfer when NACK detected */ #define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK) + #define LPI2C_SCFGR1_HSMEN_MASK (0x2000U) #define LPI2C_SCFGR1_HSMEN_SHIFT (13U) /*! HSMEN - High Speed Mode Enable @@ -60199,6 +70266,7 @@ typedef struct { * 0b1..Enables detection of HS-mode master code */ #define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK) + #define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U) #define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U) /*! ADDRCFG - Address Configuration @@ -60214,23 +70282,27 @@ typedef struct { #define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK) /*! @} */ -/*! @name SCFGR2 - Slave Configuration Register 2 */ +/*! @name SCFGR2 - Slave Configuration 2 */ /*! @{ */ + #define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU) #define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U) /*! CLKHOLD - Clock Hold Time */ #define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK) + #define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U) #define LPI2C_SCFGR2_DATAVD_SHIFT (8U) /*! DATAVD - Data Valid Delay */ #define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK) + #define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U) #define LPI2C_SCFGR2_FILTSCL_SHIFT (16U) /*! FILTSCL - Glitch Filter SCL */ #define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK) + #define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U) #define LPI2C_SCFGR2_FILTSDA_SHIFT (24U) /*! FILTSDA - Glitch Filter SDA @@ -60238,13 +70310,15 @@ typedef struct { #define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK) /*! @} */ -/*! @name SAMR - Slave Address Match Register */ +/*! @name SAMR - Slave Address Match */ /*! @{ */ + #define LPI2C_SAMR_ADDR0_MASK (0x7FEU) #define LPI2C_SAMR_ADDR0_SHIFT (1U) /*! ADDR0 - Address 0 Value */ #define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK) + #define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U) #define LPI2C_SAMR_ADDR1_SHIFT (17U) /*! ADDR1 - Address 1 Value @@ -60252,13 +70326,15 @@ typedef struct { #define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK) /*! @} */ -/*! @name SASR - Slave Address Status Register */ +/*! @name SASR - Slave Address Status */ /*! @{ */ + #define LPI2C_SASR_RADDR_MASK (0x7FFU) #define LPI2C_SASR_RADDR_SHIFT (0U) /*! RADDR - Received Address */ #define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK) + #define LPI2C_SASR_ANV_MASK (0x4000U) #define LPI2C_SASR_ANV_SHIFT (14U) /*! ANV - Address Not Valid @@ -60268,8 +70344,9 @@ typedef struct { #define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK) /*! @} */ -/*! @name STAR - Slave Transmit ACK Register */ +/*! @name STAR - Slave Transmit ACK */ /*! @{ */ + #define LPI2C_STAR_TXNACK_MASK (0x1U) #define LPI2C_STAR_TXNACK_SHIFT (0U) /*! TXNACK - Transmit NACK @@ -60279,8 +70356,9 @@ typedef struct { #define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK) /*! @} */ -/*! @name STDR - Slave Transmit Data Register */ +/*! @name STDR - Slave Transmit Data */ /*! @{ */ + #define LPI2C_STDR_DATA_MASK (0xFFU) #define LPI2C_STDR_DATA_SHIFT (0U) /*! DATA - Transmit Data @@ -60288,13 +70366,15 @@ typedef struct { #define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK) /*! @} */ -/*! @name SRDR - Slave Receive Data Register */ +/*! @name SRDR - Slave Receive Data */ /*! @{ */ + #define LPI2C_SRDR_DATA_MASK (0xFFU) #define LPI2C_SRDR_DATA_SHIFT (0U) /*! DATA - Receive Data */ #define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK) + #define LPI2C_SRDR_RXEMPTY_MASK (0x4000U) #define LPI2C_SRDR_RXEMPTY_SHIFT (14U) /*! RXEMPTY - RX Empty @@ -60302,6 +70382,7 @@ typedef struct { * 0b1..The Receive Data Register is empty */ #define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK) + #define LPI2C_SRDR_SOF_MASK (0x8000U) #define LPI2C_SRDR_SOF_SHIFT (15U) /*! SOF - Start Of Frame @@ -60365,28 +70446,28 @@ typedef struct { /** LPSPI - Register Layout Typedef */ typedef struct { - __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ - __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ + __I uint32_t VERID; /**< Version ID, offset: 0x0 */ + __I uint32_t PARAM; /**< Parameter, offset: 0x4 */ uint8_t RESERVED_0[8]; - __IO uint32_t CR; /**< Control Register, offset: 0x10 */ - __IO uint32_t SR; /**< Status Register, offset: 0x14 */ - __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x18 */ - __IO uint32_t DER; /**< DMA Enable Register, offset: 0x1C */ - __IO uint32_t CFGR0; /**< Configuration Register 0, offset: 0x20 */ - __IO uint32_t CFGR1; /**< Configuration Register 1, offset: 0x24 */ + __IO uint32_t CR; /**< Control, offset: 0x10 */ + __IO uint32_t SR; /**< Status, offset: 0x14 */ + __IO uint32_t IER; /**< Interrupt Enable, offset: 0x18 */ + __IO uint32_t DER; /**< DMA Enable, offset: 0x1C */ + __IO uint32_t CFGR0; /**< Configuration 0, offset: 0x20 */ + __IO uint32_t CFGR1; /**< Configuration 1, offset: 0x24 */ uint8_t RESERVED_1[8]; - __IO uint32_t DMR0; /**< Data Match Register 0, offset: 0x30 */ - __IO uint32_t DMR1; /**< Data Match Register 1, offset: 0x34 */ + __IO uint32_t DMR0; /**< Data Match 0, offset: 0x30 */ + __IO uint32_t DMR1; /**< Data Match 1, offset: 0x34 */ uint8_t RESERVED_2[8]; - __IO uint32_t CCR; /**< Clock Configuration Register, offset: 0x40 */ + __IO uint32_t CCR; /**< Clock Configuration, offset: 0x40 */ uint8_t RESERVED_3[20]; - __IO uint32_t FCR; /**< The FIFO Control register contains the RXWATER and TXWATER control fields., offset: 0x58 */ - __I uint32_t FSR; /**< FIFO Status Register, offset: 0x5C */ - __IO uint32_t TCR; /**< Transmit Command Register, offset: 0x60 */ - __O uint32_t TDR; /**< Transmit Data Register, offset: 0x64 */ + __IO uint32_t FCR; /**< FIFO Control, offset: 0x58 */ + __I uint32_t FSR; /**< FIFO Status, offset: 0x5C */ + __IO uint32_t TCR; /**< Transmit Command, offset: 0x60 */ + __O uint32_t TDR; /**< Transmit Data, offset: 0x64 */ uint8_t RESERVED_4[8]; - __I uint32_t RSR; /**< Receive Status Register, offset: 0x70 */ - __I uint32_t RDR; /**< Receive Data Register, offset: 0x74 */ + __I uint32_t RSR; /**< Receive Status, offset: 0x70 */ + __I uint32_t RDR; /**< Receive Data, offset: 0x74 */ } LPSPI_Type; /* ---------------------------------------------------------------------------- @@ -60398,19 +70479,22 @@ typedef struct { * @{ */ -/*! @name VERID - Version ID Register */ +/*! @name VERID - Version ID */ /*! @{ */ + #define LPSPI_VERID_FEATURE_MASK (0xFFFFU) #define LPSPI_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Module Identification Number * 0b0000000000000100..Standard feature set supporting a 32-bit shift register. */ #define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK) + #define LPSPI_VERID_MINOR_MASK (0xFF0000U) #define LPSPI_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK) + #define LPSPI_VERID_MAJOR_MASK (0xFF000000U) #define LPSPI_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number @@ -60418,18 +70502,21 @@ typedef struct { #define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK) /*! @} */ -/*! @name PARAM - Parameter Register */ +/*! @name PARAM - Parameter */ /*! @{ */ + #define LPSPI_PARAM_TXFIFO_MASK (0xFFU) #define LPSPI_PARAM_TXFIFO_SHIFT (0U) /*! TXFIFO - Transmit FIFO Size */ #define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK) + #define LPSPI_PARAM_RXFIFO_MASK (0xFF00U) #define LPSPI_PARAM_RXFIFO_SHIFT (8U) /*! RXFIFO - Receive FIFO Size */ #define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK) + #define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U) #define LPSPI_PARAM_PCSNUM_SHIFT (16U) /*! PCSNUM - PCS Number @@ -60437,8 +70524,9 @@ typedef struct { #define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK) /*! @} */ -/*! @name CR - Control Register */ +/*! @name CR - Control */ /*! @{ */ + #define LPSPI_CR_MEN_MASK (0x1U) #define LPSPI_CR_MEN_SHIFT (0U) /*! MEN - Module Enable @@ -60446,6 +70534,7 @@ typedef struct { * 0b1..Module is enabled */ #define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK) + #define LPSPI_CR_RST_MASK (0x2U) #define LPSPI_CR_RST_SHIFT (1U) /*! RST - Software Reset @@ -60453,6 +70542,7 @@ typedef struct { * 0b1..Module is reset */ #define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK) + #define LPSPI_CR_DOZEN_MASK (0x4U) #define LPSPI_CR_DOZEN_SHIFT (2U) /*! DOZEN - Doze Mode Enable @@ -60460,6 +70550,7 @@ typedef struct { * 0b1..LPSPI module is disabled in Doze mode */ #define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK) + #define LPSPI_CR_DBGEN_MASK (0x8U) #define LPSPI_CR_DBGEN_SHIFT (3U) /*! DBGEN - Debug Enable @@ -60467,24 +70558,27 @@ typedef struct { * 0b1..LPSPI module is enabled in debug mode */ #define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK) + #define LPSPI_CR_RTF_MASK (0x100U) #define LPSPI_CR_RTF_SHIFT (8U) /*! RTF - Reset Transmit FIFO * 0b0..No effect - * 0b1..Transmit FIFO is reset + * 0b1..Reset the Transmit FIFO. The register bit always reads zero. */ #define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK) + #define LPSPI_CR_RRF_MASK (0x200U) #define LPSPI_CR_RRF_SHIFT (9U) /*! RRF - Reset Receive FIFO * 0b0..No effect - * 0b1..Receive FIFO is reset + * 0b1..Reset the Receive FIFO. The register bit always reads zero. */ #define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK) /*! @} */ -/*! @name SR - Status Register */ +/*! @name SR - Status */ /*! @{ */ + #define LPSPI_SR_TDF_MASK (0x1U) #define LPSPI_SR_TDF_SHIFT (0U) /*! TDF - Transmit Data Flag @@ -60492,6 +70586,7 @@ typedef struct { * 0b1..Transmit data is requested */ #define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK) + #define LPSPI_SR_RDF_MASK (0x2U) #define LPSPI_SR_RDF_SHIFT (1U) /*! RDF - Receive Data Flag @@ -60499,6 +70594,7 @@ typedef struct { * 0b1..Receive data is ready */ #define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK) + #define LPSPI_SR_WCF_MASK (0x100U) #define LPSPI_SR_WCF_SHIFT (8U) /*! WCF - Word Complete Flag @@ -60506,6 +70602,7 @@ typedef struct { * 0b1..Transfer of a received word has completed */ #define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK) + #define LPSPI_SR_FCF_MASK (0x200U) #define LPSPI_SR_FCF_SHIFT (9U) /*! FCF - Frame Complete Flag @@ -60513,6 +70610,7 @@ typedef struct { * 0b1..Frame transfer has completed */ #define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK) + #define LPSPI_SR_TCF_MASK (0x400U) #define LPSPI_SR_TCF_SHIFT (10U) /*! TCF - Transfer Complete Flag @@ -60520,6 +70618,7 @@ typedef struct { * 0b1..All transfers have completed */ #define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK) + #define LPSPI_SR_TEF_MASK (0x800U) #define LPSPI_SR_TEF_SHIFT (11U) /*! TEF - Transmit Error Flag @@ -60527,6 +70626,7 @@ typedef struct { * 0b1..Transmit FIFO underrun has occurred */ #define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK) + #define LPSPI_SR_REF_MASK (0x1000U) #define LPSPI_SR_REF_SHIFT (12U) /*! REF - Receive Error Flag @@ -60534,6 +70634,7 @@ typedef struct { * 0b1..Receive FIFO has overflowed */ #define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK) + #define LPSPI_SR_DMF_MASK (0x2000U) #define LPSPI_SR_DMF_SHIFT (13U) /*! DMF - Data Match Flag @@ -60541,6 +70642,7 @@ typedef struct { * 0b1..Have received matching data */ #define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK) + #define LPSPI_SR_MBF_MASK (0x1000000U) #define LPSPI_SR_MBF_SHIFT (24U) /*! MBF - Module Busy Flag @@ -60550,8 +70652,9 @@ typedef struct { #define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK) /*! @} */ -/*! @name IER - Interrupt Enable Register */ +/*! @name IER - Interrupt Enable */ /*! @{ */ + #define LPSPI_IER_TDIE_MASK (0x1U) #define LPSPI_IER_TDIE_SHIFT (0U) /*! TDIE - Transmit Data Interrupt Enable @@ -60559,6 +70662,7 @@ typedef struct { * 0b1..Enabled */ #define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK) + #define LPSPI_IER_RDIE_MASK (0x2U) #define LPSPI_IER_RDIE_SHIFT (1U) /*! RDIE - Receive Data Interrupt Enable @@ -60566,6 +70670,7 @@ typedef struct { * 0b1..Enabled */ #define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK) + #define LPSPI_IER_WCIE_MASK (0x100U) #define LPSPI_IER_WCIE_SHIFT (8U) /*! WCIE - Word Complete Interrupt Enable @@ -60573,6 +70678,7 @@ typedef struct { * 0b1..Enabled */ #define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK) + #define LPSPI_IER_FCIE_MASK (0x200U) #define LPSPI_IER_FCIE_SHIFT (9U) /*! FCIE - Frame Complete Interrupt Enable @@ -60580,6 +70686,7 @@ typedef struct { * 0b1..Enabled */ #define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK) + #define LPSPI_IER_TCIE_MASK (0x400U) #define LPSPI_IER_TCIE_SHIFT (10U) /*! TCIE - Transfer Complete Interrupt Enable @@ -60587,6 +70694,7 @@ typedef struct { * 0b1..Enabled */ #define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK) + #define LPSPI_IER_TEIE_MASK (0x800U) #define LPSPI_IER_TEIE_SHIFT (11U) /*! TEIE - Transmit Error Interrupt Enable @@ -60594,6 +70702,7 @@ typedef struct { * 0b1..Enabled */ #define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK) + #define LPSPI_IER_REIE_MASK (0x1000U) #define LPSPI_IER_REIE_SHIFT (12U) /*! REIE - Receive Error Interrupt Enable @@ -60601,6 +70710,7 @@ typedef struct { * 0b1..Enabled */ #define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK) + #define LPSPI_IER_DMIE_MASK (0x2000U) #define LPSPI_IER_DMIE_SHIFT (13U) /*! DMIE - Data Match Interrupt Enable @@ -60610,8 +70720,9 @@ typedef struct { #define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK) /*! @} */ -/*! @name DER - DMA Enable Register */ +/*! @name DER - DMA Enable */ /*! @{ */ + #define LPSPI_DER_TDDE_MASK (0x1U) #define LPSPI_DER_TDDE_SHIFT (0U) /*! TDDE - Transmit Data DMA Enable @@ -60619,6 +70730,7 @@ typedef struct { * 0b1..DMA request is enabled */ #define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK) + #define LPSPI_DER_RDDE_MASK (0x2U) #define LPSPI_DER_RDDE_SHIFT (1U) /*! RDDE - Receive Data DMA Enable @@ -60628,29 +70740,9 @@ typedef struct { #define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK) /*! @} */ -/*! @name CFGR0 - Configuration Register 0 */ +/*! @name CFGR0 - Configuration 0 */ /*! @{ */ -#define LPSPI_CFGR0_HREN_MASK (0x1U) -#define LPSPI_CFGR0_HREN_SHIFT (0U) -/*! HREN - Host Request Enable - * 0b0..Host request is disabled - * 0b1..Host request is enabled - */ -#define LPSPI_CFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HREN_SHIFT)) & LPSPI_CFGR0_HREN_MASK) -#define LPSPI_CFGR0_HRPOL_MASK (0x2U) -#define LPSPI_CFGR0_HRPOL_SHIFT (1U) -/*! HRPOL - Host Request Polarity - * 0b0..LPSPI_HREQ pin is active high provided PCSPOL[1] is clear - * 0b1..LPSPI_HREQ pin is active low provided PCSPOL[1] is clear - */ -#define LPSPI_CFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRPOL_SHIFT)) & LPSPI_CFGR0_HRPOL_MASK) -#define LPSPI_CFGR0_HRSEL_MASK (0x4U) -#define LPSPI_CFGR0_HRSEL_SHIFT (2U) -/*! HRSEL - Host Request Select - * 0b0..Host request input is the LPSPI_HREQ pin - * 0b1..Host request input is the input trigger - */ -#define LPSPI_CFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_HRSEL_SHIFT)) & LPSPI_CFGR0_HRSEL_MASK) + #define LPSPI_CFGR0_CIRFIFO_MASK (0x100U) #define LPSPI_CFGR0_CIRFIFO_SHIFT (8U) /*! CIRFIFO - Circular FIFO Enable @@ -60658,17 +70750,19 @@ typedef struct { * 0b1..Circular FIFO is enabled */ #define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK) + #define LPSPI_CFGR0_RDMO_MASK (0x200U) #define LPSPI_CFGR0_RDMO_SHIFT (9U) /*! RDMO - Receive Data Match Only * 0b0..Received data is stored in the receive FIFO as in normal operations - * 0b1..Received data is discarded unless the Data Match Flag (DMF) is set + * 0b1..Received data is discarded unless the SR[DMF] = 1 */ #define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK) /*! @} */ -/*! @name CFGR1 - Configuration Register 1 */ +/*! @name CFGR1 - Configuration 1 */ /*! @{ */ + #define LPSPI_CFGR1_MASTER_MASK (0x1U) #define LPSPI_CFGR1_MASTER_SHIFT (0U) /*! MASTER - Master Mode @@ -60676,6 +70770,7 @@ typedef struct { * 0b1..Master mode */ #define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK) + #define LPSPI_CFGR1_SAMPLE_MASK (0x2U) #define LPSPI_CFGR1_SAMPLE_SHIFT (1U) /*! SAMPLE - Sample Point @@ -60683,6 +70778,7 @@ typedef struct { * 0b1..Input data is sampled on delayed SCK edge */ #define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK) + #define LPSPI_CFGR1_AUTOPCS_MASK (0x4U) #define LPSPI_CFGR1_AUTOPCS_SHIFT (2U) /*! AUTOPCS - Automatic PCS @@ -60690,33 +70786,35 @@ typedef struct { * 0b1..Automatic PCS generation is enabled */ #define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK) + #define LPSPI_CFGR1_NOSTALL_MASK (0x8U) #define LPSPI_CFGR1_NOSTALL_SHIFT (3U) /*! NOSTALL - No Stall - * 0b0..Transfers will stall when the transmit FIFO is empty - * 0b1..Transfers will not stall, allowing transmit FIFO underruns to occur + * 0b0..Transfers stall when the transmit FIFO is empty + * 0b1..Transfers do not stall, allowing transmit FIFO underruns to occur */ #define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK) + #define LPSPI_CFGR1_PCSPOL_MASK (0xF00U) #define LPSPI_CFGR1_PCSPOL_SHIFT (8U) /*! PCSPOL - Peripheral Chip Select Polarity */ #define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK) + #define LPSPI_CFGR1_MATCFG_MASK (0x70000U) #define LPSPI_CFGR1_MATCFG_SHIFT (16U) /*! MATCFG - Match Configuration * 0b000..Match is disabled * 0b001..Reserved - * 0b010..010b - Match is enabled, if 1st data word equals MATCH0 OR MATCH1, i.e., (1st data word = MATCH0 + MATCH1) - * 0b011..011b - Match is enabled, if any data word equals MATCH0 OR MATCH1, i.e., (any data word = MATCH0 + MATCH1) - * 0b100..100b - Match is enabled, if 1st data word equals MATCH0 AND 2nd data word equals MATCH1, i.e., [(1st - * data word = MATCH0) * (2nd data word = MATCH1)] - * 0b101..101b - Match is enabled, if any data word equals MATCH0 AND the next data word equals MATCH1, i.e., - * [(any data word = MATCH0) * (next data word = MATCH1)] - * 0b110..110b - Match is enabled, if (1st data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(1st data word * MATCH1) = (MATCH0 * MATCH1)] - * 0b111..111b - Match is enabled, if (any data word AND MATCH1) equals (MATCH0 AND MATCH1), i.e., [(any data word * MATCH1) = (MATCH0 * MATCH1)] + * 0b010..Match is enabled is 1st data word is MATCH0 or MATCH1 + * 0b011..Match is enabled on any data word equal MATCH0 or MATCH1 + * 0b100..Match is enabled on data match sequence + * 0b101..Match is enabled on data match sequence + * 0b110..Match is enabled + * 0b111..Match is enabled */ #define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK) + #define LPSPI_CFGR1_PINCFG_MASK (0x3000000U) #define LPSPI_CFGR1_PINCFG_SHIFT (24U) /*! PINCFG - Pin Configuration @@ -60726,6 +70824,7 @@ typedef struct { * 0b11..SOUT is used for input data and SIN is used for output data */ #define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK) + #define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U) #define LPSPI_CFGR1_OUTCFG_SHIFT (26U) /*! OUTCFG - Output Configuration @@ -60733,6 +70832,7 @@ typedef struct { * 0b1..Output data is tristated when chip select is negated */ #define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK) + #define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U) #define LPSPI_CFGR1_PCSCFG_SHIFT (27U) /*! PCSCFG - Peripheral Chip Select Configuration @@ -60742,8 +70842,9 @@ typedef struct { #define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK) /*! @} */ -/*! @name DMR0 - Data Match Register 0 */ +/*! @name DMR0 - Data Match 0 */ /*! @{ */ + #define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU) #define LPSPI_DMR0_MATCH0_SHIFT (0U) /*! MATCH0 - Match 0 Value @@ -60751,8 +70852,9 @@ typedef struct { #define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK) /*! @} */ -/*! @name DMR1 - Data Match Register 1 */ +/*! @name DMR1 - Data Match 1 */ /*! @{ */ + #define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU) #define LPSPI_DMR1_MATCH1_SHIFT (0U) /*! MATCH1 - Match 1 Value @@ -60760,23 +70862,27 @@ typedef struct { #define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK) /*! @} */ -/*! @name CCR - Clock Configuration Register */ +/*! @name CCR - Clock Configuration */ /*! @{ */ + #define LPSPI_CCR_SCKDIV_MASK (0xFFU) #define LPSPI_CCR_SCKDIV_SHIFT (0U) /*! SCKDIV - SCK Divider */ #define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK) + #define LPSPI_CCR_DBT_MASK (0xFF00U) #define LPSPI_CCR_DBT_SHIFT (8U) /*! DBT - Delay Between Transfers */ #define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK) + #define LPSPI_CCR_PCSSCK_MASK (0xFF0000U) #define LPSPI_CCR_PCSSCK_SHIFT (16U) /*! PCSSCK - PCS-to-SCK Delay */ #define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK) + #define LPSPI_CCR_SCKPCS_MASK (0xFF000000U) #define LPSPI_CCR_SCKPCS_SHIFT (24U) /*! SCKPCS - SCK-to-PCS Delay @@ -60784,13 +70890,15 @@ typedef struct { #define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK) /*! @} */ -/*! @name FCR - The FIFO Control register contains the RXWATER and TXWATER control fields. */ +/*! @name FCR - FIFO Control */ /*! @{ */ + #define LPSPI_FCR_TXWATER_MASK (0xFU) #define LPSPI_FCR_TXWATER_SHIFT (0U) /*! TXWATER - Transmit FIFO Watermark */ #define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK) + #define LPSPI_FCR_RXWATER_MASK (0xF0000U) #define LPSPI_FCR_RXWATER_SHIFT (16U) /*! RXWATER - Receive FIFO Watermark @@ -60798,13 +70906,15 @@ typedef struct { #define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK) /*! @} */ -/*! @name FSR - FIFO Status Register */ +/*! @name FSR - FIFO Status */ /*! @{ */ + #define LPSPI_FSR_TXCOUNT_MASK (0x1FU) #define LPSPI_FSR_TXCOUNT_SHIFT (0U) /*! TXCOUNT - Transmit FIFO Count */ #define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK) + #define LPSPI_FSR_RXCOUNT_MASK (0x1F0000U) #define LPSPI_FSR_RXCOUNT_SHIFT (16U) /*! RXCOUNT - Receive FIFO Count @@ -60812,13 +70922,15 @@ typedef struct { #define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK) /*! @} */ -/*! @name TCR - Transmit Command Register */ +/*! @name TCR - Transmit Command */ /*! @{ */ + #define LPSPI_TCR_FRAMESZ_MASK (0xFFFU) #define LPSPI_TCR_FRAMESZ_SHIFT (0U) /*! FRAMESZ - Frame Size */ #define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK) + #define LPSPI_TCR_WIDTH_MASK (0x30000U) #define LPSPI_TCR_WIDTH_SHIFT (16U) /*! WIDTH - Transfer Width @@ -60828,6 +70940,7 @@ typedef struct { * 0b11..Reserved */ #define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK) + #define LPSPI_TCR_TXMSK_MASK (0x40000U) #define LPSPI_TCR_TXMSK_SHIFT (18U) /*! TXMSK - Transmit Data Mask @@ -60835,6 +70948,7 @@ typedef struct { * 0b1..Mask transmit data */ #define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK) + #define LPSPI_TCR_RXMSK_MASK (0x80000U) #define LPSPI_TCR_RXMSK_SHIFT (19U) /*! RXMSK - Receive Data Mask @@ -60842,6 +70956,7 @@ typedef struct { * 0b1..Receive data is masked */ #define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK) + #define LPSPI_TCR_CONTC_MASK (0x100000U) #define LPSPI_TCR_CONTC_SHIFT (20U) /*! CONTC - Continuing Command @@ -60849,6 +70964,7 @@ typedef struct { * 0b1..Command word for continuing transfer */ #define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK) + #define LPSPI_TCR_CONT_MASK (0x200000U) #define LPSPI_TCR_CONT_SHIFT (21U) /*! CONT - Continuous Transfer @@ -60856,6 +70972,7 @@ typedef struct { * 0b1..Continuous transfer is enabled */ #define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK) + #define LPSPI_TCR_BYSW_MASK (0x400000U) #define LPSPI_TCR_BYSW_SHIFT (22U) /*! BYSW - Byte Swap @@ -60863,6 +70980,7 @@ typedef struct { * 0b1..Byte swap is enabled */ #define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK) + #define LPSPI_TCR_LSBF_MASK (0x800000U) #define LPSPI_TCR_LSBF_SHIFT (23U) /*! LSBF - LSB First @@ -60870,15 +70988,17 @@ typedef struct { * 0b1..Data is transferred LSB first */ #define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK) + #define LPSPI_TCR_PCS_MASK (0x3000000U) #define LPSPI_TCR_PCS_SHIFT (24U) /*! PCS - Peripheral Chip Select - * 0b00..Transfer using LPSPI_PCS[0] - * 0b01..Transfer using LPSPI_PCS[1] - * 0b10..Transfer using LPSPI_PCS[2] - * 0b11..Transfer using LPSPI_PCS[3] + * 0b00..Transfer using PCS[0] + * 0b01..Transfer using PCS[1] + * 0b10..Transfer using PCS[2] + * 0b11..Transfer using PCS[3] */ #define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK) + #define LPSPI_TCR_PRESCALE_MASK (0x38000000U) #define LPSPI_TCR_PRESCALE_SHIFT (27U) /*! PRESCALE - Prescaler Value @@ -60892,13 +71012,15 @@ typedef struct { * 0b111..Divide by 128 */ #define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK) + #define LPSPI_TCR_CPHA_MASK (0x40000000U) #define LPSPI_TCR_CPHA_SHIFT (30U) /*! CPHA - Clock Phase - * 0b0..Data is captured on the leading edge of SCK and changed on the following edge of SCK - * 0b1..Data is changed on the leading edge of SCK and captured on the following edge of SCK + * 0b0..Captured + * 0b1..Changed */ #define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK) + #define LPSPI_TCR_CPOL_MASK (0x80000000U) #define LPSPI_TCR_CPOL_SHIFT (31U) /*! CPOL - Clock Polarity @@ -60908,8 +71030,9 @@ typedef struct { #define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK) /*! @} */ -/*! @name TDR - Transmit Data Register */ +/*! @name TDR - Transmit Data */ /*! @{ */ + #define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU) #define LPSPI_TDR_DATA_SHIFT (0U) /*! DATA - Transmit Data @@ -60917,15 +71040,17 @@ typedef struct { #define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK) /*! @} */ -/*! @name RSR - Receive Status Register */ +/*! @name RSR - Receive Status */ /*! @{ */ + #define LPSPI_RSR_SOF_MASK (0x1U) #define LPSPI_RSR_SOF_SHIFT (0U) /*! SOF - Start Of Frame - * 0b0..Subsequent data word received after LPSPI_PCS assertion - * 0b1..First data word received after LPSPI_PCS assertion + * 0b0..Subsequent data word received after PCS assertion + * 0b1..First data word received after PCS assertion */ #define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK) + #define LPSPI_RSR_RXEMPTY_MASK (0x2U) #define LPSPI_RSR_RXEMPTY_SHIFT (1U) /*! RXEMPTY - RX FIFO Empty @@ -60935,8 +71060,9 @@ typedef struct { #define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK) /*! @} */ -/*! @name RDR - Receive Data Register */ +/*! @name RDR - Receive Data */ /*! @{ */ + #define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU) #define LPSPI_RDR_DATA_SHIFT (0U) /*! DATA - Receive Data @@ -61023,6 +71149,7 @@ typedef struct { /*! @name VERID - Version ID Register */ /*! @{ */ + #define LPUART_VERID_FEATURE_MASK (0xFFFFU) #define LPUART_VERID_FEATURE_SHIFT (0U) /*! FEATURE - Feature Identification Number @@ -61030,11 +71157,13 @@ typedef struct { * 0b0000000000000011..Standard feature set with MODEM/IrDA support. */ #define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK) + #define LPUART_VERID_MINOR_MASK (0xFF0000U) #define LPUART_VERID_MINOR_SHIFT (16U) /*! MINOR - Minor Version Number */ #define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK) + #define LPUART_VERID_MAJOR_MASK (0xFF000000U) #define LPUART_VERID_MAJOR_SHIFT (24U) /*! MAJOR - Major Version Number @@ -61044,11 +71173,13 @@ typedef struct { /*! @name PARAM - Parameter Register */ /*! @{ */ + #define LPUART_PARAM_TXFIFO_MASK (0xFFU) #define LPUART_PARAM_TXFIFO_SHIFT (0U) /*! TXFIFO - Transmit FIFO Size */ #define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK) + #define LPUART_PARAM_RXFIFO_MASK (0xFF00U) #define LPUART_PARAM_RXFIFO_SHIFT (8U) /*! RXFIFO - Receive FIFO Size @@ -61058,6 +71189,7 @@ typedef struct { /*! @name GLOBAL - LPUART Global Register */ /*! @{ */ + #define LPUART_GLOBAL_RST_MASK (0x2U) #define LPUART_GLOBAL_RST_SHIFT (1U) /*! RST - Software Reset @@ -61069,24 +71201,28 @@ typedef struct { /*! @name PINCFG - LPUART Pin Configuration Register */ /*! @{ */ + #define LPUART_PINCFG_TRGSEL_MASK (0x3U) #define LPUART_PINCFG_TRGSEL_SHIFT (0U) /*! TRGSEL - Trigger Select * 0b00..Input trigger is disabled. * 0b01..Input trigger is used instead of RXD pin input. * 0b10..Input trigger is used instead of CTS_B pin input. - * 0b11..Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger. + * 0b11..Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is + * internally ANDed with the input trigger. */ #define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK) /*! @} */ /*! @name BAUD - LPUART Baud Rate Register */ /*! @{ */ + #define LPUART_BAUD_SBR_MASK (0x1FFFU) #define LPUART_BAUD_SBR_SHIFT (0U) /*! SBR - Baud Rate Modulo Divisor. */ #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) + #define LPUART_BAUD_SBNS_MASK (0x2000U) #define LPUART_BAUD_SBNS_SHIFT (13U) /*! SBNS - Stop Bit Number Select @@ -61094,6 +71230,7 @@ typedef struct { * 0b1..Two stop bits. */ #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) + #define LPUART_BAUD_RXEDGIE_MASK (0x4000U) #define LPUART_BAUD_RXEDGIE_SHIFT (14U) /*! RXEDGIE - RX Input Active Edge Interrupt Enable @@ -61101,20 +71238,23 @@ typedef struct { * 0b1..Hardware interrupt is requested when STAT[RXEDGIF] flag is 1. */ #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) + #define LPUART_BAUD_LBKDIE_MASK (0x8000U) #define LPUART_BAUD_LBKDIE_SHIFT (15U) /*! LBKDIE - LIN Break Detect Interrupt Enable * 0b0..Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling). - * 0b1..Hardware interrupt requested when STAT[LBKDIF] flag is 1. + * 0b1..Hardware interrupt is requested when STAT[LBKDIF] flag is 1. */ #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) + #define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) #define LPUART_BAUD_RESYNCDIS_SHIFT (16U) /*! RESYNCDIS - Resynchronization Disable - * 0b0..Resynchronization during received data word is supported - * 0b1..Resynchronization during received data word is disabled + * 0b0..Resynchronization during received data word is supported. + * 0b1..Resynchronization during received data word is disabled. */ #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) + #define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) #define LPUART_BAUD_BOTHEDGE_SHIFT (17U) /*! BOTHEDGE - Both Edge Sampling @@ -61122,6 +71262,7 @@ typedef struct { * 0b1..Receiver samples input data using the rising and falling edge of the baud rate clock. */ #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) + #define LPUART_BAUD_MATCFG_MASK (0xC0000U) #define LPUART_BAUD_MATCFG_SHIFT (18U) /*! MATCFG - Match Configuration @@ -61131,13 +71272,7 @@ typedef struct { * 0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input */ #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) -#define LPUART_BAUD_RIDMAE_MASK (0x100000U) -#define LPUART_BAUD_RIDMAE_SHIFT (20U) -/*! RIDMAE - Receiver Idle DMA Enable - * 0b0..DMA request disabled. - * 0b1..DMA request enabled. - */ -#define LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK) + #define LPUART_BAUD_RDMAE_MASK (0x200000U) #define LPUART_BAUD_RDMAE_SHIFT (21U) /*! RDMAE - Receiver Full DMA Enable @@ -61145,6 +71280,7 @@ typedef struct { * 0b1..DMA request enabled. */ #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) + #define LPUART_BAUD_TDMAE_MASK (0x800000U) #define LPUART_BAUD_TDMAE_SHIFT (23U) /*! TDMAE - Transmitter DMA Enable @@ -61152,6 +71288,7 @@ typedef struct { * 0b1..DMA request enabled. */ #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) + #define LPUART_BAUD_OSR_MASK (0x1F000000U) #define LPUART_BAUD_OSR_SHIFT (24U) /*! OSR - Oversampling Ratio @@ -61189,6 +71326,7 @@ typedef struct { * 0b11111..Oversampling ratio of 32. */ #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) + #define LPUART_BAUD_M10_MASK (0x20000000U) #define LPUART_BAUD_M10_SHIFT (29U) /*! M10 - 10-bit Mode select @@ -61196,6 +71334,7 @@ typedef struct { * 0b1..Receiver and transmitter use 10-bit data characters. */ #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) + #define LPUART_BAUD_MAEN2_MASK (0x40000000U) #define LPUART_BAUD_MAEN2_SHIFT (30U) /*! MAEN2 - Match Address Mode Enable 2 @@ -61203,6 +71342,7 @@ typedef struct { * 0b1..Enables automatic address matching or data matching mode for MATCH[MA2]. */ #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) + #define LPUART_BAUD_MAEN1_MASK (0x80000000U) #define LPUART_BAUD_MAEN1_SHIFT (31U) /*! MAEN1 - Match Address Mode Enable 1 @@ -61214,6 +71354,7 @@ typedef struct { /*! @name STAT - LPUART Status Register */ /*! @{ */ + #define LPUART_STAT_MA2F_MASK (0x4000U) #define LPUART_STAT_MA2F_SHIFT (14U) /*! MA2F - Match 2 Flag @@ -61221,6 +71362,7 @@ typedef struct { * 0b1..Received data is equal to MA2 */ #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) + #define LPUART_STAT_MA1F_MASK (0x8000U) #define LPUART_STAT_MA1F_SHIFT (15U) /*! MA1F - Match 1 Flag @@ -61228,6 +71370,7 @@ typedef struct { * 0b1..Received data is equal to MA1 */ #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) + #define LPUART_STAT_PF_MASK (0x10000U) #define LPUART_STAT_PF_SHIFT (16U) /*! PF - Parity Error Flag @@ -61235,6 +71378,7 @@ typedef struct { * 0b1..Parity error. */ #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) + #define LPUART_STAT_FE_MASK (0x20000U) #define LPUART_STAT_FE_SHIFT (17U) /*! FE - Framing Error Flag @@ -61242,6 +71386,7 @@ typedef struct { * 0b1..Framing error. */ #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) + #define LPUART_STAT_NF_MASK (0x40000U) #define LPUART_STAT_NF_SHIFT (18U) /*! NF - Noise Flag @@ -61249,6 +71394,7 @@ typedef struct { * 0b1..Noise detected in the received character in the DATA register. */ #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) + #define LPUART_STAT_OR_MASK (0x80000U) #define LPUART_STAT_OR_SHIFT (19U) /*! OR - Receiver Overrun Flag @@ -61256,20 +71402,23 @@ typedef struct { * 0b1..Receive overrun (new LPUART data lost). */ #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) + #define LPUART_STAT_IDLE_MASK (0x100000U) #define LPUART_STAT_IDLE_SHIFT (20U) /*! IDLE - Idle Line Flag * 0b0..No idle line detected. - * 0b1..Idle line was detected. + * 0b1..Idle line is detected. */ #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) + #define LPUART_STAT_RDRF_MASK (0x200000U) #define LPUART_STAT_RDRF_SHIFT (21U) /*! RDRF - Receive Data Register Full Flag - * 0b0..Receive data buffer empty. - * 0b1..Receive data buffer full. + * 0b0..Receive FIFO level is less than watermark. + * 0b1..Receive FIFO level is equal or greater than watermark. */ #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) + #define LPUART_STAT_TC_MASK (0x400000U) #define LPUART_STAT_TC_SHIFT (22U) /*! TC - Transmission Complete Flag @@ -61277,13 +71426,15 @@ typedef struct { * 0b1..Transmitter idle (transmission activity complete). */ #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) + #define LPUART_STAT_TDRE_MASK (0x800000U) #define LPUART_STAT_TDRE_SHIFT (23U) /*! TDRE - Transmit Data Register Empty Flag - * 0b0..Transmit data buffer full. - * 0b1..Transmit data buffer empty. + * 0b0..Transmit FIFO level is greater than watermark. + * 0b1..Transmit FIFO level is equal or less than watermark. */ #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) + #define LPUART_STAT_RAF_MASK (0x1000000U) #define LPUART_STAT_RAF_SHIFT (24U) /*! RAF - Receiver Active Flag @@ -61291,6 +71442,7 @@ typedef struct { * 0b1..LPUART receiver active (RXD input not idle). */ #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) + #define LPUART_STAT_LBKDE_MASK (0x2000000U) #define LPUART_STAT_LBKDE_SHIFT (25U) /*! LBKDE - LIN Break Detection Enable @@ -61298,6 +71450,7 @@ typedef struct { * 0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1). */ #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) + #define LPUART_STAT_BRK13_MASK (0x4000000U) #define LPUART_STAT_BRK13_SHIFT (26U) /*! BRK13 - Break Character Generation Length @@ -61305,6 +71458,7 @@ typedef struct { * 0b1..Break character is transmitted with length of 12 to 15 bit times. */ #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) + #define LPUART_STAT_RWUID_MASK (0x8000000U) #define LPUART_STAT_RWUID_SHIFT (27U) /*! RWUID - Receive Wake Up Idle Detect @@ -61314,6 +71468,7 @@ typedef struct { * address match wakeup, the IDLE bit does set when an address does not match. */ #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) + #define LPUART_STAT_RXINV_MASK (0x10000000U) #define LPUART_STAT_RXINV_SHIFT (28U) /*! RXINV - Receive Data Inversion @@ -61321,16 +71476,17 @@ typedef struct { * 0b1..Receive data inverted. */ #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) + #define LPUART_STAT_MSBF_MASK (0x20000000U) #define LPUART_STAT_MSBF_SHIFT (29U) /*! MSBF - MSB First * 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received * after the start bit is identified as bit0. - * 0b1..MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on - * the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is - * identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE]. + * 0b1..MSB (identified as bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit + * depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. . */ #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) + #define LPUART_STAT_RXEDGIF_MASK (0x40000000U) #define LPUART_STAT_RXEDGIF_SHIFT (30U) /*! RXEDGIF - RXD Pin Active Edge Interrupt Flag @@ -61338,6 +71494,7 @@ typedef struct { * 0b1..An active edge on the receive pin has occurred. */ #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) + #define LPUART_STAT_LBKDIF_MASK (0x80000000U) #define LPUART_STAT_LBKDIF_SHIFT (31U) /*! LBKDIF - LIN Break Detect Interrupt Flag @@ -61349,6 +71506,7 @@ typedef struct { /*! @name CTRL - LPUART Control Register */ /*! @{ */ + #define LPUART_CTRL_PT_MASK (0x1U) #define LPUART_CTRL_PT_SHIFT (0U) /*! PT - Parity Type @@ -61356,6 +71514,7 @@ typedef struct { * 0b1..Odd parity. */ #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) + #define LPUART_CTRL_PE_MASK (0x2U) #define LPUART_CTRL_PE_SHIFT (1U) /*! PE - Parity Enable @@ -61363,6 +71522,7 @@ typedef struct { * 0b1..Parity enabled. */ #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) + #define LPUART_CTRL_ILT_MASK (0x4U) #define LPUART_CTRL_ILT_SHIFT (2U) /*! ILT - Idle Line Type Select @@ -61370,6 +71530,7 @@ typedef struct { * 0b1..Idle character bit count starts after stop bit. */ #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) + #define LPUART_CTRL_WAKE_MASK (0x8U) #define LPUART_CTRL_WAKE_SHIFT (3U) /*! WAKE - Receiver Wakeup Method Select @@ -61377,6 +71538,7 @@ typedef struct { * 0b1..Configures RWU with address-mark wakeup. */ #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) + #define LPUART_CTRL_M_MASK (0x10U) #define LPUART_CTRL_M_SHIFT (4U) /*! M - 9-Bit or 8-Bit Mode Select @@ -61384,6 +71546,7 @@ typedef struct { * 0b1..Receiver and transmitter use 9-bit data characters. */ #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) + #define LPUART_CTRL_RSRC_MASK (0x20U) #define LPUART_CTRL_RSRC_SHIFT (5U) /*! RSRC - Receiver Source Select @@ -61391,13 +71554,15 @@ typedef struct { * 0b1..Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input. */ #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) + #define LPUART_CTRL_DOZEEN_MASK (0x40U) #define LPUART_CTRL_DOZEEN_SHIFT (6U) /*! DOZEEN - Doze Enable * 0b0..LPUART is enabled in Doze mode. - * 0b1..LPUART is disabled in Doze mode. + * 0b1..LPUART is disabled in Doze mode . */ #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) + #define LPUART_CTRL_LOOPS_MASK (0x80U) #define LPUART_CTRL_LOOPS_SHIFT (7U) /*! LOOPS - Loop Mode Select @@ -61405,6 +71570,7 @@ typedef struct { * 0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit). */ #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) + #define LPUART_CTRL_IDLECFG_MASK (0x700U) #define LPUART_CTRL_IDLECFG_SHIFT (8U) /*! IDLECFG - Idle Configuration @@ -61418,6 +71584,7 @@ typedef struct { * 0b111..128 idle characters */ #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) + #define LPUART_CTRL_M7_MASK (0x800U) #define LPUART_CTRL_M7_SHIFT (11U) /*! M7 - 7-Bit Mode Select @@ -61425,6 +71592,7 @@ typedef struct { * 0b1..Receiver and transmitter use 7-bit data characters. */ #define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK) + #define LPUART_CTRL_MA2IE_MASK (0x4000U) #define LPUART_CTRL_MA2IE_SHIFT (14U) /*! MA2IE - Match 2 Interrupt Enable @@ -61432,6 +71600,7 @@ typedef struct { * 0b1..MA2F interrupt enabled */ #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) + #define LPUART_CTRL_MA1IE_MASK (0x8000U) #define LPUART_CTRL_MA1IE_SHIFT (15U) /*! MA1IE - Match 1 Interrupt Enable @@ -61439,6 +71608,7 @@ typedef struct { * 0b1..MA1F interrupt enabled */ #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) + #define LPUART_CTRL_SBK_MASK (0x10000U) #define LPUART_CTRL_SBK_SHIFT (16U) /*! SBK - Send Break @@ -61446,6 +71616,7 @@ typedef struct { * 0b1..Queue break character(s) to be sent. */ #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) + #define LPUART_CTRL_RWU_MASK (0x20000U) #define LPUART_CTRL_RWU_SHIFT (17U) /*! RWU - Receiver Wakeup Control @@ -61453,6 +71624,7 @@ typedef struct { * 0b1..LPUART receiver in standby waiting for wakeup condition. */ #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) + #define LPUART_CTRL_RE_MASK (0x40000U) #define LPUART_CTRL_RE_SHIFT (18U) /*! RE - Receiver Enable @@ -61460,6 +71632,7 @@ typedef struct { * 0b1..Receiver enabled. */ #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) + #define LPUART_CTRL_TE_MASK (0x80000U) #define LPUART_CTRL_TE_SHIFT (19U) /*! TE - Transmitter Enable @@ -61467,62 +71640,71 @@ typedef struct { * 0b1..Transmitter enabled. */ #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) + #define LPUART_CTRL_ILIE_MASK (0x100000U) #define LPUART_CTRL_ILIE_SHIFT (20U) /*! ILIE - Idle Line Interrupt Enable * 0b0..Hardware interrupts from IDLE disabled; use polling. - * 0b1..Hardware interrupt requested when IDLE flag is 1. + * 0b1..Hardware interrupt is requested when IDLE flag is 1. */ #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) + #define LPUART_CTRL_RIE_MASK (0x200000U) #define LPUART_CTRL_RIE_SHIFT (21U) /*! RIE - Receiver Interrupt Enable - * 0b0..Hardware interrupts from RDRF disabled; use polling. - * 0b1..Hardware interrupt requested when RDRF flag is 1. + * 0b0..Hardware interrupts from RDRF disabled. + * 0b1..Hardware interrupt is requested when RDRF flag is 1. */ #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) + #define LPUART_CTRL_TCIE_MASK (0x400000U) #define LPUART_CTRL_TCIE_SHIFT (22U) /*! TCIE - Transmission Complete Interrupt Enable for - * 0b0..Hardware interrupts from TC disabled; use polling. - * 0b1..Hardware interrupt requested when TC flag is 1. + * 0b0..Hardware interrupts from TC disabled. + * 0b1..Hardware interrupt is requested when TC flag is 1. */ #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) + #define LPUART_CTRL_TIE_MASK (0x800000U) #define LPUART_CTRL_TIE_SHIFT (23U) /*! TIE - Transmit Interrupt Enable - * 0b0..Hardware interrupts from TDRE disabled; use polling. - * 0b1..Hardware interrupt requested when TDRE flag is 1. + * 0b0..Hardware interrupts from TDRE disabled. + * 0b1..Hardware interrupt is requested when TDRE flag is 1. */ #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) + #define LPUART_CTRL_PEIE_MASK (0x1000000U) #define LPUART_CTRL_PEIE_SHIFT (24U) /*! PEIE - Parity Error Interrupt Enable * 0b0..PF interrupts disabled; use polling). - * 0b1..Hardware interrupt requested when PF is set. + * 0b1..Hardware interrupt is requested when PF is set. */ #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) + #define LPUART_CTRL_FEIE_MASK (0x2000000U) #define LPUART_CTRL_FEIE_SHIFT (25U) /*! FEIE - Framing Error Interrupt Enable * 0b0..FE interrupts disabled; use polling. - * 0b1..Hardware interrupt requested when FE is set. + * 0b1..Hardware interrupt is requested when FE is set. */ #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) + #define LPUART_CTRL_NEIE_MASK (0x4000000U) #define LPUART_CTRL_NEIE_SHIFT (26U) /*! NEIE - Noise Error Interrupt Enable * 0b0..NF interrupts disabled; use polling. - * 0b1..Hardware interrupt requested when NF is set. + * 0b1..Hardware interrupt is requested when NF is set. */ #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) + #define LPUART_CTRL_ORIE_MASK (0x8000000U) #define LPUART_CTRL_ORIE_SHIFT (27U) /*! ORIE - Overrun Interrupt Enable * 0b0..OR interrupts disabled; use polling. - * 0b1..Hardware interrupt requested when OR is set. + * 0b1..Hardware interrupt is requested when OR is set. */ #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) + #define LPUART_CTRL_TXINV_MASK (0x10000000U) #define LPUART_CTRL_TXINV_SHIFT (28U) /*! TXINV - Transmit Data Inversion @@ -61530,6 +71712,7 @@ typedef struct { * 0b1..Transmit data inverted. */ #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) + #define LPUART_CTRL_TXDIR_MASK (0x20000000U) #define LPUART_CTRL_TXDIR_SHIFT (29U) /*! TXDIR - TXD Pin Direction in Single-Wire Mode @@ -61537,11 +71720,13 @@ typedef struct { * 0b1..TXD pin is an output in single-wire mode. */ #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) + #define LPUART_CTRL_R9T8_MASK (0x40000000U) #define LPUART_CTRL_R9T8_SHIFT (30U) /*! R9T8 - Receive Bit 9 / Transmit Bit 8 */ #define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) + #define LPUART_CTRL_R8T9_MASK (0x80000000U) #define LPUART_CTRL_R8T9_SHIFT (31U) /*! R8T9 - Receive Bit 8 / Transmit Bit 9 @@ -61551,56 +71736,67 @@ typedef struct { /*! @name DATA - LPUART Data Register */ /*! @{ */ + #define LPUART_DATA_R0T0_MASK (0x1U) #define LPUART_DATA_R0T0_SHIFT (0U) /*! R0T0 - R0T0 */ #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) + #define LPUART_DATA_R1T1_MASK (0x2U) #define LPUART_DATA_R1T1_SHIFT (1U) /*! R1T1 - R1T1 */ #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) + #define LPUART_DATA_R2T2_MASK (0x4U) #define LPUART_DATA_R2T2_SHIFT (2U) /*! R2T2 - R2T2 */ #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) + #define LPUART_DATA_R3T3_MASK (0x8U) #define LPUART_DATA_R3T3_SHIFT (3U) /*! R3T3 - R3T3 */ #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) + #define LPUART_DATA_R4T4_MASK (0x10U) #define LPUART_DATA_R4T4_SHIFT (4U) /*! R4T4 - R4T4 */ #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) + #define LPUART_DATA_R5T5_MASK (0x20U) #define LPUART_DATA_R5T5_SHIFT (5U) /*! R5T5 - R5T5 */ #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) + #define LPUART_DATA_R6T6_MASK (0x40U) #define LPUART_DATA_R6T6_SHIFT (6U) /*! R6T6 - R6T6 */ #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) + #define LPUART_DATA_R7T7_MASK (0x80U) #define LPUART_DATA_R7T7_SHIFT (7U) /*! R7T7 - R7T7 */ #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) + #define LPUART_DATA_R8T8_MASK (0x100U) #define LPUART_DATA_R8T8_SHIFT (8U) /*! R8T8 - R8T8 */ #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) + #define LPUART_DATA_R9T9_MASK (0x200U) #define LPUART_DATA_R9T9_SHIFT (9U) /*! R9T9 - R9T9 */ #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) + #define LPUART_DATA_IDLINE_MASK (0x800U) #define LPUART_DATA_IDLINE_SHIFT (11U) /*! IDLINE - Idle Line @@ -61608,6 +71804,7 @@ typedef struct { * 0b1..Receiver was idle before receiving this character. */ #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) + #define LPUART_DATA_RXEMPT_MASK (0x1000U) #define LPUART_DATA_RXEMPT_SHIFT (12U) /*! RXEMPT - Receive Buffer Empty @@ -61615,36 +71812,41 @@ typedef struct { * 0b1..Receive buffer is empty, data returned on read is not valid. */ #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) + #define LPUART_DATA_FRETSC_MASK (0x2000U) #define LPUART_DATA_FRETSC_SHIFT (13U) /*! FRETSC - Frame Error / Transmit Special Character - * 0b0..The dataword was received without a frame error on read, or transmit a normal character on write. - * 0b1..The dataword was received with a frame error, or transmit an idle or break character on transmit. + * 0b0..The dataword is received without a frame error on read, or transmit a normal character on write. + * 0b1..The dataword is received with a frame error, or transmit an idle or break character on transmit. */ #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) + #define LPUART_DATA_PARITYE_MASK (0x4000U) #define LPUART_DATA_PARITYE_SHIFT (14U) -/*! PARITYE - PARITYE - * 0b0..The dataword was received without a parity error. - * 0b1..The dataword was received with a parity error. +/*! PARITYE - Parity Error + * 0b0..The dataword is received without a parity error. + * 0b1..The dataword is received with a parity error. */ #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) + #define LPUART_DATA_NOISY_MASK (0x8000U) #define LPUART_DATA_NOISY_SHIFT (15U) -/*! NOISY - NOISY - * 0b0..The dataword was received without noise. - * 0b1..The data was received with noise. +/*! NOISY - Noisy Data Received + * 0b0..The dataword is received without noise. + * 0b1..The data is received with noise. */ #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) /*! @} */ /*! @name MATCH - LPUART Match Address Register */ /*! @{ */ + #define LPUART_MATCH_MA1_MASK (0x3FFU) #define LPUART_MATCH_MA1_SHIFT (0U) /*! MA1 - Match Address 1 */ #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) + #define LPUART_MATCH_MA2_MASK (0x3FF0000U) #define LPUART_MATCH_MA2_SHIFT (16U) /*! MA2 - Match Address 2 @@ -61654,6 +71856,7 @@ typedef struct { /*! @name MODIR - LPUART Modem IrDA Register */ /*! @{ */ + #define LPUART_MODIR_TXCTSE_MASK (0x1U) #define LPUART_MODIR_TXCTSE_SHIFT (0U) /*! TXCTSE - Transmitter clear-to-send enable @@ -61664,15 +71867,17 @@ typedef struct { * do not affect its transmission. */ #define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) + #define LPUART_MODIR_TXRTSE_MASK (0x2U) #define LPUART_MODIR_TXRTSE_SHIFT (1U) /*! TXRTSE - Transmitter request-to-send enable * 0b0..The transmitter has no effect on RTS. - * 0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the - * start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and - * shift register are completely sent, including the last stop bit. + * 0b1..When a character is placed into an empty transmit shift register, RTS asserts one bit time before the + * start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter FIFO and shift + * register are completely sent, including the last stop bit. */ #define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) + #define LPUART_MODIR_TXRTSPOL_MASK (0x4U) #define LPUART_MODIR_TXRTSPOL_SHIFT (2U) /*! TXRTSPOL - Transmitter request-to-send polarity @@ -61680,6 +71885,7 @@ typedef struct { * 0b1..Transmitter RTS is active high. */ #define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) + #define LPUART_MODIR_RXRTSE_MASK (0x8U) #define LPUART_MODIR_RXRTSE_SHIFT (3U) /*! RXRTSE - Receiver request-to-send enable @@ -61689,6 +71895,7 @@ typedef struct { * has not detected a start bit that would cause the receiver data register to become full. */ #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) + #define LPUART_MODIR_TXCTSC_MASK (0x10U) #define LPUART_MODIR_TXCTSC_SHIFT (4U) /*! TXCTSC - Transmit CTS Configuration @@ -61696,18 +71903,21 @@ typedef struct { * 0b1..CTS input is sampled when the transmitter is idle. */ #define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) + #define LPUART_MODIR_TXCTSSRC_MASK (0x20U) #define LPUART_MODIR_TXCTSSRC_SHIFT (5U) /*! TXCTSSRC - Transmit CTS Source * 0b0..CTS input is the CTS_B pin. - * 0b1..CTS input is the inverted Receiver Match result. + * 0b1..CTS input is an internal connection to the receiver address match result. */ #define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) + #define LPUART_MODIR_RTSWATER_MASK (0x300U) #define LPUART_MODIR_RTSWATER_SHIFT (8U) /*! RTSWATER - Receive RTS Configuration */ #define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) + #define LPUART_MODIR_TNP_MASK (0x30000U) #define LPUART_MODIR_TNP_SHIFT (16U) /*! TNP - Transmitter narrow pulse @@ -61717,6 +71927,7 @@ typedef struct { * 0b11..4/OSR. */ #define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) + #define LPUART_MODIR_IREN_MASK (0x40000U) #define LPUART_MODIR_IREN_SHIFT (18U) /*! IREN - Infrared enable @@ -61728,6 +71939,7 @@ typedef struct { /*! @name FIFO - LPUART FIFO Register */ /*! @{ */ + #define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) #define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) /*! RXFIFOSIZE - Receive FIFO Buffer Depth @@ -61741,13 +71953,15 @@ typedef struct { * 0b111..Receive FIFO/Buffer depth = 256 datawords. */ #define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) + #define LPUART_FIFO_RXFE_MASK (0x8U) #define LPUART_FIFO_RXFE_SHIFT (3U) /*! RXFE - Receive FIFO Enable - * 0b0..Receive FIFO is not enabled. Buffer is depth 1. - * 0b1..Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. + * 0b0..Receive FIFO is not enabled. Buffer depth is 1. + * 0b1..Receive FIFO is enabled. Buffer depth is indicted by RXFIFOSIZE. */ #define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) + #define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) #define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) /*! TXFIFOSIZE - Transmit FIFO Buffer Depth @@ -61761,13 +71975,15 @@ typedef struct { * 0b111..Transmit FIFO/Buffer depth = 256 datawords */ #define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) + #define LPUART_FIFO_TXFE_MASK (0x80U) #define LPUART_FIFO_TXFE_SHIFT (7U) /*! TXFE - Transmit FIFO Enable - * 0b0..Transmit FIFO is not enabled. Buffer is depth 1. - * 0b1..Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. + * 0b0..Transmit FIFO is not enabled. Buffer depth is 1. + * 0b1..Transmit FIFO is enabled. Buffer depth is indicated by TXFIFOSIZE. */ #define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) + #define LPUART_FIFO_RXUFE_MASK (0x100U) #define LPUART_FIFO_RXUFE_SHIFT (8U) /*! RXUFE - Receive FIFO Underflow Interrupt Enable @@ -61775,6 +71991,7 @@ typedef struct { * 0b1..RXUF flag generates an interrupt to the host. */ #define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) + #define LPUART_FIFO_TXOFE_MASK (0x200U) #define LPUART_FIFO_TXOFE_SHIFT (9U) /*! TXOFE - Transmit FIFO Overflow Interrupt Enable @@ -61782,6 +71999,7 @@ typedef struct { * 0b1..TXOF flag generates an interrupt to the host. */ #define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) + #define LPUART_FIFO_RXIDEN_MASK (0x1C00U) #define LPUART_FIFO_RXIDEN_SHIFT (10U) /*! RXIDEN - Receiver Idle Empty Enable @@ -61795,44 +72013,50 @@ typedef struct { * 0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters. */ #define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) + #define LPUART_FIFO_RXFLUSH_MASK (0x4000U) #define LPUART_FIFO_RXFLUSH_SHIFT (14U) -/*! RXFLUSH - Receive FIFO/Buffer Flush +/*! RXFLUSH - Receive FIFO Flush * 0b0..No flush operation occurs. * 0b1..All data in the receive FIFO/buffer is cleared out. */ #define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) + #define LPUART_FIFO_TXFLUSH_MASK (0x8000U) #define LPUART_FIFO_TXFLUSH_SHIFT (15U) -/*! TXFLUSH - Transmit FIFO/Buffer Flush +/*! TXFLUSH - Transmit FIFO Flush * 0b0..No flush operation occurs. - * 0b1..All data in the transmit FIFO/Buffer is cleared out. + * 0b1..All data in the transmit FIFO is cleared out. */ #define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) + #define LPUART_FIFO_RXUF_MASK (0x10000U) #define LPUART_FIFO_RXUF_SHIFT (16U) -/*! RXUF - Receiver Buffer Underflow Flag - * 0b0..No receive buffer underflow has occurred since the last time the flag was cleared. - * 0b1..At least one receive buffer underflow has occurred since the last time the flag was cleared. +/*! RXUF - Receiver FIFO Underflow Flag + * 0b0..No receive FIFO underflow has occurred since the last time the flag was cleared. + * 0b1..At least one receive FIFO underflow has occurred since the last time the flag was cleared. */ #define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) + #define LPUART_FIFO_TXOF_MASK (0x20000U) #define LPUART_FIFO_TXOF_SHIFT (17U) -/*! TXOF - Transmitter Buffer Overflow Flag - * 0b0..No transmit buffer overflow has occurred since the last time the flag was cleared. - * 0b1..At least one transmit buffer overflow has occurred since the last time the flag was cleared. +/*! TXOF - Transmitter FIFO Overflow Flag + * 0b0..No transmit FIFO overflow has occurred since the last time the flag was cleared. + * 0b1..At least one transmit FIFO overflow has occurred since the last time the flag was cleared. */ #define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) + #define LPUART_FIFO_RXEMPT_MASK (0x400000U) #define LPUART_FIFO_RXEMPT_SHIFT (22U) -/*! RXEMPT - Receive Buffer/FIFO Empty +/*! RXEMPT - Receive FIFO/Buffer Empty * 0b0..Receive buffer is not empty. * 0b1..Receive buffer is empty. */ #define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) + #define LPUART_FIFO_TXEMPT_MASK (0x800000U) #define LPUART_FIFO_TXEMPT_SHIFT (23U) -/*! TXEMPT - Transmit Buffer/FIFO Empty +/*! TXEMPT - Transmit FIFO/Buffer Empty * 0b0..Transmit buffer is not empty. * 0b1..Transmit buffer is empty. */ @@ -61841,21 +72065,25 @@ typedef struct { /*! @name WATER - LPUART Watermark Register */ /*! @{ */ + #define LPUART_WATER_TXWATER_MASK (0x3U) #define LPUART_WATER_TXWATER_SHIFT (0U) /*! TXWATER - Transmit Watermark */ #define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) + #define LPUART_WATER_TXCOUNT_MASK (0x700U) #define LPUART_WATER_TXCOUNT_SHIFT (8U) /*! TXCOUNT - Transmit Counter */ #define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK) + #define LPUART_WATER_RXWATER_MASK (0x30000U) #define LPUART_WATER_RXWATER_SHIFT (16U) /*! RXWATER - Receive Watermark */ #define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK) + #define LPUART_WATER_RXCOUNT_MASK (0x7000000U) #define LPUART_WATER_RXCOUNT_SHIFT (24U) /*! RXCOUNT - Receive Counter @@ -61941,14 +72169,8 @@ typedef struct { /** MCM - Register Layout Typedef */ typedef struct { - uint8_t RESERVED_0[8]; - __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ - __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ - __IO uint32_t PLACR; /**< Crossbar Switch (AXBS) Control Register, offset: 0xC */ - uint8_t RESERVED_1[16]; - __I uint32_t FADR; /**< Fault address register, offset: 0x20 */ - __I uint32_t FATR; /**< Fault attributes register, offset: 0x24 */ - __I uint32_t FDR; /**< Fault data register, offset: 0x28 */ + uint8_t RESERVED_0[16]; + __IO uint32_t ISCR; /**< Interrupt Status and Control Register, offset: 0x10 */ } MCM_Type; /* ---------------------------------------------------------------------------- @@ -61960,102 +72182,128 @@ typedef struct { * @{ */ -/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ +/*! @name ISCR - Interrupt Status and Control Register */ /*! @{ */ -#define MCM_PLASC_ASC_MASK (0xFFU) -#define MCM_PLASC_ASC_SHIFT (0U) -/*! ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the - * crossbar switch's slave input port. - * 0b00000000..A bus slave connection to AXBS input port n is absent - * 0b00000001..A bus slave connection to AXBS input port n is present + +#define MCM_ISCR_WABS_MASK (0x20U) +#define MCM_ISCR_WABS_SHIFT (5U) +/*! WABS - Write Abort on Slave + * 0b0..No abort + * 0b1..Abort */ -#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) -/*! @} */ +#define MCM_ISCR_WABS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_WABS_SHIFT)) & MCM_ISCR_WABS_MASK) -/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ -/*! @{ */ -#define MCM_PLAMC_AMC_MASK (0xFFU) -#define MCM_PLAMC_AMC_SHIFT (0U) -/*! AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. - * 0b00000000..A bus master connection to AXBS input port n is absent - * 0b00000001..A bus master connection to AXBS input port n is present +#define MCM_ISCR_WABSO_MASK (0x40U) +#define MCM_ISCR_WABSO_SHIFT (6U) +/*! WABSO - Write Abort on Slave Overrun + * 0b0..No write abort overrun + * 0b1..Write abort overrun occurred */ -#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) -/*! @} */ +#define MCM_ISCR_WABSO(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_WABSO_SHIFT)) & MCM_ISCR_WABSO_MASK) -/*! @name PLACR - Crossbar Switch (AXBS) Control Register */ -/*! @{ */ -#define MCM_PLACR_ARB_MASK (0x200U) -#define MCM_PLACR_ARB_SHIFT (9U) -/*! ARB - Arbitration select - * 0b0..Fixed-priority arbitration for the crossbar masters - * 0b1..Round-robin arbitration for the crossbar masters +#define MCM_ISCR_FIOC_MASK (0x100U) +#define MCM_ISCR_FIOC_SHIFT (8U) +/*! FIOC - FPU Invalid Operation interrupt Status + * 0b0..No interrupt + * 0b1..Interrupt occured */ -#define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK) -/*! @} */ +#define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK) -/*! @name FADR - Fault address register */ -/*! @{ */ -#define MCM_FADR_ADDRESS_MASK (0xFFFFFFFFU) -#define MCM_FADR_ADDRESS_SHIFT (0U) -/*! ADDRESS - Fault address +#define MCM_ISCR_FDZC_MASK (0x200U) +#define MCM_ISCR_FDZC_SHIFT (9U) +/*! FDZC - FPU Divide-by-Zero Interrupt Status + * 0b0..No interrupt + * 0b1..Interrupt occured */ -#define MCM_FADR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << MCM_FADR_ADDRESS_SHIFT)) & MCM_FADR_ADDRESS_MASK) -/*! @} */ +#define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK) -/*! @name FATR - Fault attributes register */ -/*! @{ */ -#define MCM_FATR_BEDA_MASK (0x1U) -#define MCM_FATR_BEDA_SHIFT (0U) -/*! BEDA - Bus error access type - * 0b0..Instruction - * 0b1..Data +#define MCM_ISCR_FOFC_MASK (0x400U) +#define MCM_ISCR_FOFC_SHIFT (10U) +/*! FOFC - FPU Overflow interrupt status + * 0b0..No interrupt + * 0b1..Interrupt occured */ -#define MCM_FATR_BEDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEDA_SHIFT)) & MCM_FATR_BEDA_MASK) -#define MCM_FATR_BEMD_MASK (0x2U) -#define MCM_FATR_BEMD_SHIFT (1U) -/*! BEMD - Bus error privilege level - * 0b0..User mode - * 0b1..Supervisor/privileged mode +#define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK) + +#define MCM_ISCR_FUFC_MASK (0x800U) +#define MCM_ISCR_FUFC_SHIFT (11U) +/*! FUFC - FPU Underflow Interrupt Status + * 0b0..No interrupt + * 0b1..Interrupt occured */ -#define MCM_FATR_BEMD(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMD_SHIFT)) & MCM_FATR_BEMD_MASK) -#define MCM_FATR_BESZ_MASK (0x30U) -#define MCM_FATR_BESZ_SHIFT (4U) -/*! BESZ - Bus error size - * 0b00..8-bit access - * 0b01..16-bit access - * 0b10..32-bit access - * 0b11..Reserved +#define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK) + +#define MCM_ISCR_FIXC_MASK (0x1000U) +#define MCM_ISCR_FIXC_SHIFT (12U) +/*! FIXC - FPU Inexact Interrupt Status + * 0b0..No interrupt + * 0b1..Interrupt occured */ -#define MCM_FATR_BESZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BESZ_SHIFT)) & MCM_FATR_BESZ_MASK) -#define MCM_FATR_BEWT_MASK (0x80U) -#define MCM_FATR_BEWT_SHIFT (7U) -/*! BEWT - Bus error write - * 0b0..Read access - * 0b1..Write access +#define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK) + +#define MCM_ISCR_FIDC_MASK (0x8000U) +#define MCM_ISCR_FIDC_SHIFT (15U) +/*! FIDC - FPU Input Denormal Interrupt Status + * 0b0..No interrupt + * 0b1..Interrupt occured */ -#define MCM_FATR_BEWT(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEWT_SHIFT)) & MCM_FATR_BEWT_MASK) -#define MCM_FATR_BEMN_MASK (0xF00U) -#define MCM_FATR_BEMN_SHIFT (8U) -/*! BEMN - Bus error master number +#define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK) + +#define MCM_ISCR_WABE_MASK (0x200000U) +#define MCM_ISCR_WABE_SHIFT (21U) +/*! WABE - TCM Write Abort Interrupt enable + * 0b0..Disable interrupt + * 0b1..Enable interrupt */ -#define MCM_FATR_BEMN(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMN_SHIFT)) & MCM_FATR_BEMN_MASK) -#define MCM_FATR_BEOVR_MASK (0x80000000U) -#define MCM_FATR_BEOVR_SHIFT (31U) -/*! BEOVR - Bus error overrun - * 0b0..No bus error overrun - * 0b1..Bus error overrun occurred. The FADR and FDR registers and the other FATR bits are not updated to reflect this new bus error. +#define MCM_ISCR_WABE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_WABE_SHIFT)) & MCM_ISCR_WABE_MASK) + +#define MCM_ISCR_FIOCE_MASK (0x1000000U) +#define MCM_ISCR_FIOCE_SHIFT (24U) +/*! FIOCE - FPU Invalid Operation Interrupt Enable + * 0b0..Disable interrupt + * 0b1..Enable interrupt */ -#define MCM_FATR_BEOVR(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEOVR_SHIFT)) & MCM_FATR_BEOVR_MASK) -/*! @} */ +#define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK) -/*! @name FDR - Fault data register */ -/*! @{ */ -#define MCM_FDR_DATA_MASK (0xFFFFFFFFU) -#define MCM_FDR_DATA_SHIFT (0U) -/*! DATA - Fault data +#define MCM_ISCR_FDZCE_MASK (0x2000000U) +#define MCM_ISCR_FDZCE_SHIFT (25U) +/*! FDZCE - FPU Divide-by-Zero Interrupt Enable + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK) + +#define MCM_ISCR_FOFCE_MASK (0x4000000U) +#define MCM_ISCR_FOFCE_SHIFT (26U) +/*! FOFCE - FPU Overflow Interrupt Enable + * 0b0..Disable interrupt + * 0b1..Enable interrupt */ -#define MCM_FDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FDR_DATA_SHIFT)) & MCM_FDR_DATA_MASK) +#define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK) + +#define MCM_ISCR_FUFCE_MASK (0x8000000U) +#define MCM_ISCR_FUFCE_SHIFT (27U) +/*! FUFCE - FPU Underflow Interrupt Enable + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK) + +#define MCM_ISCR_FIXCE_MASK (0x10000000U) +#define MCM_ISCR_FIXCE_SHIFT (28U) +/*! FIXCE - FPU Inexact Interrupt Enable + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK) + +#define MCM_ISCR_FIDCE_MASK (0x80000000U) +#define MCM_ISCR_FIDCE_SHIFT (31U) +/*! FIDCE - FPU Input Denormal Interrupt Enable + * 0b0..Disable interrupt + * 0b1..Enable interrupt + */ +#define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK) /*! @} */ @@ -62065,14 +72313,14 @@ typedef struct { /* MCM - Peripheral instance base addresses */ -/** Peripheral MCM base address */ -#define MCM_BASE (0xE0080000u) -/** Peripheral MCM base pointer */ -#define MCM ((MCM_Type *)MCM_BASE) +/** Peripheral CM7_MCM base address */ +#define CM7_MCM_BASE (0xE0080000u) +/** Peripheral CM7_MCM base pointer */ +#define CM7_MCM ((MCM_Type *)CM7_MCM_BASE) /** Array initializer of MCM peripheral base addresses */ -#define MCM_BASE_ADDRS { MCM_BASE } +#define MCM_BASE_ADDRS { CM7_MCM_BASE } /** Array initializer of MCM peripheral base pointers */ -#define MCM_BASE_PTRS { MCM } +#define MCM_BASE_PTRS { CM7_MCM } /*! * @} @@ -62093,52 +72341,52 @@ typedef struct { __IO uint32_t ERR_STATUS; /**< Error Interrupt Status Register, offset: 0x0 */ __IO uint32_t ERR_STAT_EN; /**< Error Interrupt Status Enable Register, offset: 0x4 */ __IO uint32_t ERR_SIG_EN; /**< Error Interrupt Enable Register, offset: 0x8 */ - __IO uint32_t ERR_DATA_INJ_LOW0; /**< Error Injection On Low 32 bits Of Ocram Bank0 Write Data, offset: 0xC */ - __IO uint32_t ERR_DATA_INJ_HIGH0; /**< Error Injection On High 32 bits Of Ocram Bank0 Write Data, offset: 0x10 */ - __IO uint32_t ERR_ECC_INJ0; /**< Error Injection On 8 bits ECC code Of Ocram Bank0 Write Data, offset: 0x14 */ - __IO uint32_t ERR_DATA_INJ_LOW1; /**< Error Injection On Low 32 bits Of Ocram Bank1 Write Data, offset: 0x18 */ - __IO uint32_t ERR_DATA_INJ_HIGH1; /**< Error Injection On High 32 bits Of Ocram Bank1 Write Data, offset: 0x1C */ - __IO uint32_t ERR_ECC_INJ1; /**< Error Injection On 8 bits ECC code Of Ocram Bank1 Write Data, offset: 0x20 */ - __IO uint32_t ERR_DATA_INJ_LOW2; /**< Error Injection On Low 32 bits Of Ocram Bank2 Write Data, offset: 0x24 */ - __IO uint32_t ERR_DATA_INJ_HIGH2; /**< Error Injection On High 32 bits Of Ocram Bank2 Write Data, offset: 0x28 */ - __IO uint32_t ERR_ECC_INJ2; /**< Error Injection On 8 bits ECC code Of Ocram Bank2 Write Data, offset: 0x2C */ - __IO uint32_t ERR_DATA_INJ_LOW3; /**< Error Injection On Low 32 bits Of Ocram Bank3 Write Data, offset: 0x30 */ - __IO uint32_t ERR_DATA_INJ_HIGH3; /**< Error Injection On High 32 bits Of Ocram Bank3 Write Data, offset: 0x34 */ - __IO uint32_t ERR_ECC_INJ3; /**< Error Injection On 8 bits ECC code Of Ocram Bank3 Write Data, offset: 0x38 */ - __I uint32_t SINGLE_ERR_ADDR_ECC0; /**< Single Error Address And ECC Code On Ocram Bank0, offset: 0x3C */ - __I uint32_t SINGLE_ERR_DATA_LOW0; /**< Low 32 Bits Single Error Read Data On Ocram Bank0, offset: 0x40 */ - __I uint32_t SINGLE_ERR_DATA_HIGH0; /**< High 32 Bits Single Error Read Data On Ocram Bank0, offset: 0x44 */ - __I uint32_t SINGLE_ERR_POS_LOW0; /**< Low Single Error Bit Position On Ocram Bank0, offset: 0x48 */ - __I uint32_t SINGLE_ERR_POS_HIGH0; /**< High Single Error Bit Position On Ocram Bank0, offset: 0x4C */ - __I uint32_t SINGLE_ERR_ADDR_ECC1; /**< Single Error Address And ECC Code On Ocram Bank1, offset: 0x50 */ - __I uint32_t SINGLE_ERR_DATA_LOW1; /**< Low 32 Bits Single Error Read Data On Ocram Bank1, offset: 0x54 */ - __I uint32_t SINGLE_ERR_DATA_HIGH1; /**< High 32 Bits Single Error Read Data On Ocram Bank1, offset: 0x58 */ - __I uint32_t SINGLE_ERR_POS_LOW1; /**< Low Single Error Bit Position On Ocram Bank1, offset: 0x5C */ - __I uint32_t SINGLE_ERR_POS_HIGH1; /**< High Single Error Bit Position On Ocram Bank1, offset: 0x60 */ - __I uint32_t SINGLE_ERR_ADDR_ECC2; /**< Single Error Address And ECC Code On Ocram Bank2, offset: 0x64 */ - __I uint32_t SINGLE_ERR_DATA_LOW2; /**< Low 32 Bits Single Error Read Data On Ocram Bank2, offset: 0x68 */ - __I uint32_t SINGLE_ERR_DATA_HIGH2; /**< High 32 Bits Single Error Read Data On Ocram Bank2, offset: 0x6C */ - __I uint32_t SINGLE_ERR_POS_LOW2; /**< Low Single Error Bit Position On Ocram Bank2, offset: 0x70 */ - __I uint32_t SINGLE_ERR_POS_HIGH2; /**< High Single Error Bit Position On Ocram Bank2, offset: 0x74 */ - __I uint32_t SINGLE_ERR_ADDR_ECC3; /**< Single Error Address And ECC Code On Ocram Bank3, offset: 0x78 */ - __I uint32_t SINGLE_ERR_DATA_LOW3; /**< Low 32 Bits Single Error Read Data On Ocram Bank3, offset: 0x7C */ - __I uint32_t SINGLE_ERR_DATA_HIGH3; /**< High 32 Bits Single Error Read Data On Ocram Bank3, offset: 0x80 */ - __I uint32_t SINGLE_ERR_POS_LOW3; /**< Low Single Error Bit Position On Ocram Bank3, offset: 0x84 */ - __I uint32_t SINGLE_ERR_POS_HIGH3; /**< High Single Error Bit Position On Ocram Bank3, offset: 0x88 */ - __I uint32_t MULTI_ERR_ADDR_ECC0; /**< Multiple Error Address And ECC Code On Ocram Bank0, offset: 0x8C */ - __I uint32_t MULTI_ERR_DATA_LOW0; /**< Low 32 Bits Multiple Error Read Data On Ocram Bank0, offset: 0x90 */ - __I uint32_t MULTI_ERR_DATA_HIGH0; /**< High 32 Bits Multiple Error Read Data On Ocram Bank0, offset: 0x94 */ - __I uint32_t MULTI_ERR_ADDR_ECC1; /**< Multiple Error Address And ECC Code On Ocram Bank1, offset: 0x98 */ - __I uint32_t MULTI_ERR_DATA_LOW1; /**< Low 32 Bits Multiple Error Read Data On Ocram Bank1, offset: 0x9C */ - __I uint32_t MULTI_ERR_DATA_HIGH1; /**< High 32 Bits Multiple Error Read Data On Ocram Bank1, offset: 0xA0 */ - __I uint32_t MULTI_ERR_ADDR_ECC2; /**< Multiple Error Address And ECC Code On Ocram Bank2, offset: 0xA4 */ - __I uint32_t MULTI_ERR_DATA_LOW2; /**< Low 32 Bits Multiple Error Read Data On Ocram Bank2, offset: 0xA8 */ - __I uint32_t MULTI_ERR_DATA_HIGH2; /**< High 32 Bits Multiple Error Read Data On Ocram Bank2, offset: 0xAC */ - __I uint32_t MULTI_ERR_ADDR_ECC3; /**< Multiple Error Address And ECC Code On Ocram Bank3, offset: 0xB0 */ - __I uint32_t MULTI_ERR_DATA_LOW3; /**< Low 32 Bits Multiple Error Read Data On Ocram Bank3, offset: 0xB4 */ - __I uint32_t MULTI_ERR_DATA_HIGH3; /**< High 32 Bits Multiple Error Read Data On Ocram Bank3, offset: 0xB8 */ + __IO uint32_t ERR_DATA_INJ_LOW0; /**< Error Injection On LOW 32 bits Of OCRAM Bank0 Write Data, offset: 0xC */ + __IO uint32_t ERR_DATA_INJ_HIGH0; /**< Error Injection On HIGH 32 bits Of OCRAM Bank0 Write Data, offset: 0x10 */ + __IO uint32_t ERR_ECC_INJ0; /**< Error Injection On 8 bits ECC code Of OCRAM Bank0 Write Data, offset: 0x14 */ + __IO uint32_t ERR_DATA_INJ_LOW1; /**< Error Injection On LOW 32 bits Of OCRAM Bank1 Write Data, offset: 0x18 */ + __IO uint32_t ERR_DATA_INJ_HIGH1; /**< Error Injection On HIGH 32 bits Of OCRAM Bank1 Write Data, offset: 0x1C */ + __IO uint32_t ERR_ECC_INJ1; /**< Error Injection On 8 bits ECC code Of OCRAM Bank1 Write Data, offset: 0x20 */ + __IO uint32_t ERR_DATA_INJ_LOW2; /**< Error Injection On LOW 32 bits Of OCRAM Bank2 Write Data, offset: 0x24 */ + __IO uint32_t ERR_DATA_INJ_HIGH2; /**< Error Injection On HIGH 32 bits Of OCRAM Bank2 Write Data, offset: 0x28 */ + __IO uint32_t ERR_ECC_INJ2; /**< Error Injection On 8 bits ECC code Of OCRAM Bank2 Write Data, offset: 0x2C */ + __IO uint32_t ERR_DATA_INJ_LOW3; /**< Error Injection On LOW 32 bits Of OCRAM Bank3 Write Data, offset: 0x30 */ + __IO uint32_t ERR_DATA_INJ_HIGH3; /**< Error Injection On HIGH 32 bits Of OCRAM Bank3 Write Data, offset: 0x34 */ + __IO uint32_t ERR_ECC_INJ3; /**< Error Injection On 8 bits ECC code Of OCRAM Bank3 Write Data, offset: 0x38 */ + __I uint32_t SINGLE_ERR_ADDR_ECC0; /**< Single Error Address And ECC code On OCRAM Bank0, offset: 0x3C */ + __I uint32_t SINGLE_ERR_DATA_LOW0; /**< LOW 32 Bits Single Error Read Data On OCRAM Bank0, offset: 0x40 */ + __I uint32_t SINGLE_ERR_DATA_HIGH0; /**< HIGH 32 Bits Single Error Read Data On OCRAM Bank0, offset: 0x44 */ + __I uint32_t SINGLE_ERR_POS_LOW0; /**< LOW Single Error Bit Position On OCRAM Bank0, offset: 0x48 */ + __I uint32_t SINGLE_ERR_POS_HIGH0; /**< HIGH Single Error Bit Position On OCRAM Bank0, offset: 0x4C */ + __I uint32_t SINGLE_ERR_ADDR_ECC1; /**< Single Error Address And ECC code On OCRAM Bank1, offset: 0x50 */ + __I uint32_t SINGLE_ERR_DATA_LOW1; /**< LOW 32 Bits Single Error Read Data On OCRAM Bank1, offset: 0x54 */ + __I uint32_t SINGLE_ERR_DATA_HIGH1; /**< HIGH 32 Bits Single Error Read Data On OCRAM Bank1, offset: 0x58 */ + __I uint32_t SINGLE_ERR_POS_LOW1; /**< LOW Single Error Bit Position On OCRAM Bank1, offset: 0x5C */ + __I uint32_t SINGLE_ERR_POS_HIGH1; /**< HIGH Single Error Bit Position On OCRAM Bank1, offset: 0x60 */ + __I uint32_t SINGLE_ERR_ADDR_ECC2; /**< Single Error Address And ECC code On OCRAM Bank2, offset: 0x64 */ + __I uint32_t SINGLE_ERR_DATA_LOW2; /**< LOW 32 Bits Single Error Read Data On OCRAM Bank2, offset: 0x68 */ + __I uint32_t SINGLE_ERR_DATA_HIGH2; /**< HIGH 32 Bits Single Error Read Data On OCRAM Bank2, offset: 0x6C */ + __I uint32_t SINGLE_ERR_POS_LOW2; /**< LOW Single Error Bit Position On OCRAM Bank2, offset: 0x70 */ + __I uint32_t SINGLE_ERR_POS_HIGH2; /**< HIGH Single Error Bit Position On OCRAM Bank2, offset: 0x74 */ + __I uint32_t SINGLE_ERR_ADDR_ECC3; /**< Single Error Address And ECC code On OCRAM Bank3, offset: 0x78 */ + __I uint32_t SINGLE_ERR_DATA_LOW3; /**< LOW 32 Bits Single Error Read Data On OCRAM Bank3, offset: 0x7C */ + __I uint32_t SINGLE_ERR_DATA_HIGH3; /**< HIGH 32 Bits Single Error Read Data On OCRAM Bank3, offset: 0x80 */ + __I uint32_t SINGLE_ERR_POS_LOW3; /**< LOW Single Error Bit Position On OCRAM Bank3, offset: 0x84 */ + __I uint32_t SINGLE_ERR_POS_HIGH3; /**< HIGH Single Error Bit Position On OCRAM Bank3, offset: 0x88 */ + __I uint32_t MULTI_ERR_ADDR_ECC0; /**< Multiple Error Address And ECC code On OCRAM Bank0, offset: 0x8C */ + __I uint32_t MULTI_ERR_DATA_LOW0; /**< LOW 32 Bits Multiple Error Read Data On OCRAM Bank0, offset: 0x90 */ + __I uint32_t MULTI_ERR_DATA_HIGH0; /**< HIGH 32 Bits Multiple Error Read Data On OCRAM Bank0, offset: 0x94 */ + __I uint32_t MULTI_ERR_ADDR_ECC1; /**< Multiple Error Address And ECC code On OCRAM Bank1, offset: 0x98 */ + __I uint32_t MULTI_ERR_DATA_LOW1; /**< LOW 32 Bits Multiple Error Read Data On OCRAM Bank1, offset: 0x9C */ + __I uint32_t MULTI_ERR_DATA_HIGH1; /**< HIGH 32 Bits Multiple Error Read Data On OCRAM Bank1, offset: 0xA0 */ + __I uint32_t MULTI_ERR_ADDR_ECC2; /**< Multiple Error Address And ECC code On OCRAM Bank2, offset: 0xA4 */ + __I uint32_t MULTI_ERR_DATA_LOW2; /**< LOW 32 Bits Multiple Error Read Data On OCRAM Bank2, offset: 0xA8 */ + __I uint32_t MULTI_ERR_DATA_HIGH2; /**< HIGH 32 Bits Multiple Error Read Data On OCRAM Bank2, offset: 0xAC */ + __I uint32_t MULTI_ERR_ADDR_ECC3; /**< Multiple Error Address And ECC code On OCRAM Bank3, offset: 0xB0 */ + __I uint32_t MULTI_ERR_DATA_LOW3; /**< LOW 32 Bits Multiple Error Read Data On OCRAM Bank3, offset: 0xB4 */ + __I uint32_t MULTI_ERR_DATA_HIGH3; /**< HIGH 32 Bits Multiple Error Read Data On OCRAM Bank3, offset: 0xB8 */ uint8_t RESERVED_0[68]; - __IO uint32_t PIPE_ECC_EN; /**< Ocram Pipeline And ECC Enable, offset: 0x100 */ + __IO uint32_t PIPE_ECC_EN; /**< OCRAM Pipeline And ECC Enable, offset: 0x100 */ __I uint32_t PENDING_STAT; /**< Pending Status, offset: 0x104 */ } MECC_Type; @@ -62153,865 +72401,891 @@ typedef struct { /*! @name ERR_STATUS - Error Interrupt Status Register */ /*! @{ */ + #define MECC_ERR_STATUS_SINGLE_ERR0_MASK (0x1U) #define MECC_ERR_STATUS_SINGLE_ERR0_SHIFT (0U) -/*! SINGLE_ERR0 - Single Bit Error On Ocram Bank0 - * 0b0..Single bit error does not happen on ocram bank0. - * 0b1..Single bit error happens on ocram bank0. +/*! SINGLE_ERR0 - Single Bit Error On OCRAM Bank0 + * 0b0..Single bit error does not happen on OCRAM bank0. + * 0b1..Single bit error happens on OCRAM bank0. */ #define MECC_ERR_STATUS_SINGLE_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR0_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR0_MASK) + #define MECC_ERR_STATUS_SINGLE_ERR1_MASK (0x2U) #define MECC_ERR_STATUS_SINGLE_ERR1_SHIFT (1U) -/*! SINGLE_ERR1 - Single Bit Error On Ocram Bank1 - * 0b0..Single bit error does not happen on ocram bank1. - * 0b1..Single bit error happens on ocram bank1. +/*! SINGLE_ERR1 - Single Bit Error On OCRAM Bank1 + * 0b0..Single bit error does not happen on OCRAM bank1. + * 0b1..Single bit error happens on OCRAM bank1. */ #define MECC_ERR_STATUS_SINGLE_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR1_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR1_MASK) + #define MECC_ERR_STATUS_SINGLE_ERR2_MASK (0x4U) #define MECC_ERR_STATUS_SINGLE_ERR2_SHIFT (2U) -/*! SINGLE_ERR2 - Single Bit Error On Ocram Bank2 - * 0b0..Single bit error does not happen on ocram bank2. - * 0b1..Single bit error happens on ocram bank2. +/*! SINGLE_ERR2 - Single Bit Error On OCRAM Bank2 + * 0b0..Single bit error does not happen on OCRAM bank2. + * 0b1..Single bit error happens on OCRAM bank2. */ #define MECC_ERR_STATUS_SINGLE_ERR2(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR2_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR2_MASK) + #define MECC_ERR_STATUS_SINGLE_ERR3_MASK (0x8U) #define MECC_ERR_STATUS_SINGLE_ERR3_SHIFT (3U) -/*! SINGLE_ERR3 - Single Bit Error On Ocram Bank3 - * 0b0..Single bit error does not happen on ocram bank3. - * 0b1..Single bit error happens on ocram bank3. +/*! SINGLE_ERR3 - Single Bit Error On OCRAM Bank3 + * 0b0..Single bit error does not happen on OCRAM bank3. + * 0b1..Single bit error happens on OCRAM bank3. */ #define MECC_ERR_STATUS_SINGLE_ERR3(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR3_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR3_MASK) + #define MECC_ERR_STATUS_MULTI_ERR0_MASK (0x10U) #define MECC_ERR_STATUS_MULTI_ERR0_SHIFT (4U) -/*! MULTI_ERR0 - Multiple Bits Error On Ocram Bank0 - * 0b0..Multiple bits error does not happen on ocram bank0. - * 0b1..Multiple bits error happens on ocram bank0. +/*! MULTI_ERR0 - Multiple Bits Error On OCRAM Bank0 + * 0b0..Multiple bits error does not happen on OCRAM bank0. + * 0b1..Multiple bits error happens on OCRAM bank0. */ #define MECC_ERR_STATUS_MULTI_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR0_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR0_MASK) + #define MECC_ERR_STATUS_MULTI_ERR1_MASK (0x20U) #define MECC_ERR_STATUS_MULTI_ERR1_SHIFT (5U) -/*! MULTI_ERR1 - Multiple Bits Error On Ocram Bank1 - * 0b0..Multiple bits error does not happen on ocram bank1. - * 0b1..Multiple bits error happens on ocram bank1. +/*! MULTI_ERR1 - Multiple Bits Error On OCRAM Bank1 + * 0b0..Multiple bits error does not happen on OCRAM bank1. + * 0b1..Multiple bits error happens on OCRAM bank1. */ #define MECC_ERR_STATUS_MULTI_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR1_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR1_MASK) + #define MECC_ERR_STATUS_MULTI_ERR2_MASK (0x40U) #define MECC_ERR_STATUS_MULTI_ERR2_SHIFT (6U) -/*! MULTI_ERR2 - Multiple Bits Error On Ocram Bank2 - * 0b0..Multiple bits error does not happen on ocram bank2. - * 0b1..Multiple bits error happens on ocram bank2. +/*! MULTI_ERR2 - Multiple Bits Error On OCRAM Bank2 + * 0b0..Multiple bits error does not happen on OCRAM bank2. + * 0b1..Multiple bits error happens on OCRAM bank2. */ #define MECC_ERR_STATUS_MULTI_ERR2(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR2_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR2_MASK) + #define MECC_ERR_STATUS_MULTI_ERR3_MASK (0x80U) #define MECC_ERR_STATUS_MULTI_ERR3_SHIFT (7U) -/*! MULTI_ERR3 - Multiple Bits Error On Ocram Bank3 - * 0b0..Multiple bits error does not happen on ocram bank3. - * 0b1..Multiple bits error happens on ocram bank3. +/*! MULTI_ERR3 - Multiple Bits Error On OCRAM Bank3 + * 0b0..Multiple bits error does not happen on OCRAM bank3. + * 0b1..Multiple bits error happens on OCRAM bank3. */ #define MECC_ERR_STATUS_MULTI_ERR3(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR3_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR3_MASK) + #define MECC_ERR_STATUS_STRB_ERR0_MASK (0x100U) #define MECC_ERR_STATUS_STRB_ERR0_SHIFT (8U) -/*! STRB_ERR0 - AXI Strobe Error On Ocram Bank0 - * 0b0..AXI strobe error does not happen on ocram bank0. - * 0b1..AXI strobe error happens on ocram bank0. +/*! STRB_ERR0 - AXI Strobe Error On OCRAM Bank0 + * 0b0..AXI strobe error does not happen on OCRAM bank0. + * 0b1..AXI strobe error happens on OCRAM bank0. */ #define MECC_ERR_STATUS_STRB_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR0_SHIFT)) & MECC_ERR_STATUS_STRB_ERR0_MASK) + #define MECC_ERR_STATUS_STRB_ERR1_MASK (0x200U) #define MECC_ERR_STATUS_STRB_ERR1_SHIFT (9U) -/*! STRB_ERR1 - AXI Strobe Error On Ocram Bank1 - * 0b0..AXI strobe error does not happen on ocram bank1. - * 0b1..AXI strobe error happens on ocram bank1. +/*! STRB_ERR1 - AXI Strobe Error On OCRAM Bank1 + * 0b0..AXI strobe error does not happen on OCRAM bank1. + * 0b1..AXI strobe error happens on OCRAM bank1. */ #define MECC_ERR_STATUS_STRB_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR1_SHIFT)) & MECC_ERR_STATUS_STRB_ERR1_MASK) + #define MECC_ERR_STATUS_STRB_ERR2_MASK (0x400U) #define MECC_ERR_STATUS_STRB_ERR2_SHIFT (10U) -/*! STRB_ERR2 - AXI Strobe Error On Ocram Bank2 - * 0b0..AXI strobe error does not happen on ocram bank2. - * 0b1..AXI strobe error happens on ocram bank2. +/*! STRB_ERR2 - AXI Strobe Error On OCRAM Bank2 + * 0b0..AXI strobe error does not happen on OCRAM bank2. + * 0b1..AXI strobe error happens on OCRAM bank2. */ #define MECC_ERR_STATUS_STRB_ERR2(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR2_SHIFT)) & MECC_ERR_STATUS_STRB_ERR2_MASK) + #define MECC_ERR_STATUS_STRB_ERR3_MASK (0x800U) #define MECC_ERR_STATUS_STRB_ERR3_SHIFT (11U) -/*! STRB_ERR3 - AXI Strobe Error On Ocram Bank3 - * 0b0..AXI strobe error does not happen on ocram bank3. - * 0b1..AXI strobe error happens on ocram bank3. +/*! STRB_ERR3 - AXI Strobe Error On OCRAM Bank3 + * 0b0..AXI strobe error does not happen on OCRAM bank3. + * 0b1..AXI strobe error happens on OCRAM bank3. */ #define MECC_ERR_STATUS_STRB_ERR3(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR3_SHIFT)) & MECC_ERR_STATUS_STRB_ERR3_MASK) + #define MECC_ERR_STATUS_ADDR_ERR0_MASK (0x1000U) #define MECC_ERR_STATUS_ADDR_ERR0_SHIFT (12U) -/*! ADDR_ERR0 - Ocram Access Error On Bank0 - * 0b0..Ocram access error does not happen on ocram bank0. - * 0b1..Ocram access error happens on ocram bank0. +/*! ADDR_ERR0 - OCRAM Access Error On Bank0 + * 0b0..OCRAM access error does not happen on OCRAM bank0. + * 0b1..OCRAM access error happens on OCRAM bank0. */ #define MECC_ERR_STATUS_ADDR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR0_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR0_MASK) + #define MECC_ERR_STATUS_ADDR_ERR1_MASK (0x2000U) #define MECC_ERR_STATUS_ADDR_ERR1_SHIFT (13U) -/*! ADDR_ERR1 - Ocram Access Error On Bank1 - * 0b0..Ocram access error does not happen on ocram bank1. - * 0b1..Ocram access error happens on ocram bank1. +/*! ADDR_ERR1 - OCRAM Access Error On Bank1 + * 0b0..OCRAM access error does not happen on OCRAM bank1. + * 0b1..OCRAM access error happens on OCRAM bank1. */ #define MECC_ERR_STATUS_ADDR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR1_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR1_MASK) + #define MECC_ERR_STATUS_ADDR_ERR2_MASK (0x4000U) #define MECC_ERR_STATUS_ADDR_ERR2_SHIFT (14U) -/*! ADDR_ERR2 - Ocram Access Error On Bank2 - * 0b0..Ocram access error does not happen on ocram bank2. - * 0b1..Ocram access error happens on ocram bank2. +/*! ADDR_ERR2 - OCRAM Access Error On Bank2 + * 0b0..OCRAM access error does not happen on OCRAM bank2. + * 0b1..OCRAM access error happens on OCRAM bank2. */ #define MECC_ERR_STATUS_ADDR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR2_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR2_MASK) + #define MECC_ERR_STATUS_ADDR_ERR3_MASK (0x8000U) #define MECC_ERR_STATUS_ADDR_ERR3_SHIFT (15U) -/*! ADDR_ERR3 - Ocram Access Error On Bank3 - * 0b0..Ocram access error does not happen on ocram bank3. - * 0b1..Ocram access error happens on ocram bank3. +/*! ADDR_ERR3 - OCRAM Access Error On Bank3 + * 0b0..OCRAM access error does not happen on OCRAM bank3. + * 0b1..OCRAM access error happens on OCRAM bank3. */ #define MECC_ERR_STATUS_ADDR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR3_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR3_MASK) -#define MECC_ERR_STATUS_Reserved1_MASK (0xFFFF0000U) -#define MECC_ERR_STATUS_Reserved1_SHIFT (16U) -/*! Reserved1 - Reserved - */ -#define MECC_ERR_STATUS_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_Reserved1_SHIFT)) & MECC_ERR_STATUS_Reserved1_MASK) /*! @} */ /*! @name ERR_STAT_EN - Error Interrupt Status Enable Register */ /*! @{ */ + #define MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_MASK (0x1U) #define MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_SHIFT (0U) -/*! SINGLE_ERR0_STAT_EN - Single Bit Error Status Enable On Ocram Bank0 - * 0b0..Masked +/*! SINGLE_ERR0_STAT_EN - Single Bit Error Status Enable On OCRAM Bank0 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_MASK) + #define MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_MASK (0x2U) #define MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_SHIFT (1U) -/*! SINGLE_ERR1_STAT_EN - Single Bit Error Status Enable On Ocram Bank1 - * 0b0..Masked +/*! SINGLE_ERR1_STAT_EN - Single Bit Error Status Enable On OCRAM Bank1 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_MASK) + #define MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_MASK (0x4U) #define MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_SHIFT (2U) -/*! SINGLE_ERR2_STAT_EN - Single Bit Error Status Enable On Ocram Bank2 - * 0b0..Masked +/*! SINGLE_ERR2_STAT_EN - Single Bit Error Status Enable On OCRAM Bank2 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_MASK) + #define MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_MASK (0x8U) #define MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_SHIFT (3U) -/*! SINGLE_ERR3_STAT_EN - Single Bit Error Status Enable On Ocram Bank3 - * 0b0..Masked +/*! SINGLE_ERR3_STAT_EN - Single Bit Error Status Enable On OCRAM Bank3 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_MASK) + #define MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_MASK (0x10U) #define MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_SHIFT (4U) -/*! MULTI_ERR0_STAT_EN - Multiple Bits Error Status Enable On Ocram Bank0 - * 0b0..Masked +/*! MULTI_ERR0_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank0 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_MASK) + #define MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_MASK (0x20U) #define MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_SHIFT (5U) -/*! MULTI_ERR1_STAT_EN - Multiple Bits Error Status Enable On Ocram Bank1 - * 0b0..Masked +/*! MULTI_ERR1_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank1 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_MASK) + #define MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_MASK (0x40U) #define MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_SHIFT (6U) -/*! MULTI_ERR2_STAT_EN - Multiple Bits Error Status Enable On Ocram Bank2 - * 0b0..Masked +/*! MULTI_ERR2_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank2 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_MASK) + #define MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_MASK (0x80U) #define MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_SHIFT (7U) -/*! MULTI_ERR3_STAT_EN - Multiple Bits Error Status Enable On Ocram Bank3 - * 0b0..Masked +/*! MULTI_ERR3_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank3 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_MASK) + #define MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_MASK (0x100U) #define MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_SHIFT (8U) -/*! STRB_ERR0_STAT_EN - AXI Strobe Error Status Enable On Ocram Bank0 - * 0b0..Masked +/*! STRB_ERR0_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank0 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_MASK) + #define MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_MASK (0x200U) #define MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_SHIFT (9U) -/*! STRB_ERR1_STAT_EN - AXI Strobe Error Status Enable On Ocram Bank1 - * 0b0..Masked +/*! STRB_ERR1_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank1 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_MASK) + #define MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_MASK (0x400U) #define MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_SHIFT (10U) -/*! STRB_ERR2_STAT_EN - AXI Strobe Error Status Enable On Ocram Bank2 - * 0b0..Masked +/*! STRB_ERR2_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank2 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_MASK) + #define MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_MASK (0x800U) #define MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_SHIFT (11U) -/*! STRB_ERR3_STAT_EN - AXI Strobe Error Status Enable On Ocram Bank3 - * 0b0..Masked +/*! STRB_ERR3_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank3 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_MASK) + #define MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_MASK (0x1000U) #define MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_SHIFT (12U) -/*! ADDR_ERR0_STAT_EN - Ocram Access Error Status Enable On Bank0 - * 0b0..Masked +/*! ADDR_ERR0_STAT_EN - OCRAM Access Error Status Enable On Bank0 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_MASK) + #define MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_MASK (0x2000U) #define MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_SHIFT (13U) -/*! ADDR_ERR1_STAT_EN - Ocram Access Error Status Enable On Bank1 - * 0b0..Masked +/*! ADDR_ERR1_STAT_EN - OCRAM Access Error Status Enable On Bank1 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_MASK) + #define MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_MASK (0x4000U) #define MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_SHIFT (14U) -/*! ADDR_ERR2_STAT_EN - Ocram Access Error Status Enable On Bank2 - * 0b0..Masked +/*! ADDR_ERR2_STAT_EN - OCRAM Access Error Status Enable On Bank2 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_MASK) + #define MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_MASK (0x8000U) #define MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_SHIFT (15U) -/*! ADDR_ERR3_STAT_EN - Ocram Access Error Status Enable On Bank3 - * 0b0..Masked +/*! ADDR_ERR3_STAT_EN - OCRAM Access Error Status Enable On Bank3 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_MASK) -#define MECC_ERR_STAT_EN_Reserved1_MASK (0xFFFF0000U) -#define MECC_ERR_STAT_EN_Reserved1_SHIFT (16U) -/*! Reserved1 - Reserved - */ -#define MECC_ERR_STAT_EN_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_Reserved1_SHIFT)) & MECC_ERR_STAT_EN_Reserved1_MASK) /*! @} */ /*! @name ERR_SIG_EN - Error Interrupt Enable Register */ /*! @{ */ + #define MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_MASK (0x1U) #define MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_SHIFT (0U) -/*! SINGLE_ERR0_SIG_EN - Single Bit Error Interrupt Enable On Ocram Bank0 - * 0b0..Masked +/*! SINGLE_ERR0_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank0 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_MASK) + #define MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_MASK (0x2U) #define MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_SHIFT (1U) -/*! SINGLE_ERR1_SIG_EN - Single Bit Error Interrupt Enable On Ocram Bank1 - * 0b0..Masked +/*! SINGLE_ERR1_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank1 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_MASK) + #define MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_MASK (0x4U) #define MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_SHIFT (2U) -/*! SINGLE_ERR2_SIG_EN - Single Bit Error Interrupt Enable On Ocram Bank2 - * 0b0..Masked +/*! SINGLE_ERR2_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank2 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_MASK) + #define MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_MASK (0x8U) #define MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_SHIFT (3U) -/*! SINGLE_ERR3_SIG_EN - Single Bit Error Interrupt Enable On Ocram Bank3 - * 0b0..Masked +/*! SINGLE_ERR3_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank3 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_MASK) + #define MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_MASK (0x10U) #define MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_SHIFT (4U) -/*! MULTI_ERR0_SIG_EN - Multiple Bits Error Interrupt Enable On Ocram Bank0 - * 0b0..Masked +/*! MULTI_ERR0_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank0 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_MASK) + #define MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_MASK (0x20U) #define MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_SHIFT (5U) -/*! MULTI_ERR1_SIG_EN - Multiple Bits Error Interrupt Enable On Ocram Bank1 - * 0b0..Masked +/*! MULTI_ERR1_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank1 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_MASK) + #define MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_MASK (0x40U) #define MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_SHIFT (6U) -/*! MULTI_ERR2_SIG_EN - Multiple Bits Error Interrupt Enable On Ocram Bank2 - * 0b0..Masked +/*! MULTI_ERR2_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank2 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_MASK) + #define MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_MASK (0x80U) #define MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_SHIFT (7U) -/*! MULTI_ERR3_SIG_EN - Multiple Bits Error Interrupt Enable On Ocram Bank3 - * 0b0..Masked +/*! MULTI_ERR3_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank3 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_MASK) + #define MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_MASK (0x100U) #define MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_SHIFT (8U) -/*! STRB_ERR0_SIG_EN - AXI Strobe Error Interrupt Enable On Ocram Bank0 - * 0b0..Masked +/*! STRB_ERR0_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank0 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_MASK) + #define MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_MASK (0x200U) #define MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_SHIFT (9U) -/*! STRB_ERR1_SIG_EN - AXI Strobe Error Interrupt Enable On Ocram Bank1 - * 0b0..Masked +/*! STRB_ERR1_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank1 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_MASK) + #define MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_MASK (0x400U) #define MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_SHIFT (10U) -/*! STRB_ERR2_SIG_EN - AXI Strobe Error Interrupt Enable On Ocram Bank2 - * 0b0..Masked +/*! STRB_ERR2_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank2 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_MASK) + #define MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_MASK (0x800U) #define MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_SHIFT (11U) -/*! STRB_ERR3_SIG_EN - AXI Strobe Error Interrupt Enable On Ocram Bank3 - * 0b0..Masked +/*! STRB_ERR3_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank3 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_MASK) + #define MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_MASK (0x1000U) #define MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_SHIFT (12U) -/*! ADDR_ERR0_SIG_EN - Ocram Access Error Interrupt Enable On Bank0 - * 0b0..Masked +/*! ADDR_ERR0_SIG_EN - OCRAM Access Error Interrupt Enable On Bank0 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_MASK) + #define MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_MASK (0x2000U) #define MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_SHIFT (13U) -/*! ADDR_ERR1_SIG_EN - Ocram Access Error Interrupt Enable On Bank1 - * 0b0..Masked +/*! ADDR_ERR1_SIG_EN - OCRAM Access Error Interrupt Enable On Bank1 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_MASK) + #define MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_MASK (0x4000U) #define MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_SHIFT (14U) -/*! ADDR_ERR2_SIG_EN - Ocram Access Error Interrupt Enable On Bank2 - * 0b0..Masked +/*! ADDR_ERR2_SIG_EN - OCRAM Access Error Interrupt Enable On Bank2 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_MASK) + #define MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_MASK (0x8000U) #define MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_SHIFT (15U) -/*! ADDR_ERR3_SIG_EN - Ocram Access Error Interrupt Enable On Bank3 - * 0b0..Masked +/*! ADDR_ERR3_SIG_EN - OCRAM Access Error Interrupt Enable On Bank3 + * 0b0..Disabled * 0b1..Enabled */ #define MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_MASK) -#define MECC_ERR_SIG_EN_Reserved1_MASK (0xFFFF0000U) -#define MECC_ERR_SIG_EN_Reserved1_SHIFT (16U) -/*! Reserved1 - Reserved - */ -#define MECC_ERR_SIG_EN_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_Reserved1_SHIFT)) & MECC_ERR_SIG_EN_Reserved1_MASK) /*! @} */ -/*! @name ERR_DATA_INJ_LOW0 - Error Injection On Low 32 bits Of Ocram Bank0 Write Data */ +/*! @name ERR_DATA_INJ_LOW0 - Error Injection On LOW 32 bits Of OCRAM Bank0 Write Data */ /*! @{ */ -#define MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_LOW0_MASK (0xFFFFFFFFU) -#define MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_LOW0_SHIFT (0U) -/*! ERR_DATA_INJ_LOW0 - Error Injection On Low 32 bits Of Ocram Bank0 Write Data + +#define MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_MASK (0xFFFFFFFFU) +#define MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_SHIFT (0U) +/*! ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank0 Write Data */ -#define MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_LOW0(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_LOW0_SHIFT)) & MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_LOW0_MASK) +#define MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_MASK) /*! @} */ -/*! @name ERR_DATA_INJ_HIGH0 - Error Injection On High 32 bits Of Ocram Bank0 Write Data */ +/*! @name ERR_DATA_INJ_HIGH0 - Error Injection On HIGH 32 bits Of OCRAM Bank0 Write Data */ /*! @{ */ -#define MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_HIGH0_MASK (0xFFFFFFFFU) -#define MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_HIGH0_SHIFT (0U) -/*! ERR_DATA_INJ_HIGH0 - Error Injection On High 32 bits Of Ocram Bank0 Write Data + +#define MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_MASK (0xFFFFFFFFU) +#define MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_SHIFT (0U) +/*! ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank0 Write Data */ -#define MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_HIGH0(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_HIGH0_SHIFT)) & MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_HIGH0_MASK) +#define MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_MASK) /*! @} */ -/*! @name ERR_ECC_INJ0 - Error Injection On 8 bits ECC code Of Ocram Bank0 Write Data */ +/*! @name ERR_ECC_INJ0 - Error Injection On 8 bits ECC code Of OCRAM Bank0 Write Data */ /*! @{ */ -#define MECC_ERR_ECC_INJ0_ERR_ECC_INJ0_MASK (0xFFU) -#define MECC_ERR_ECC_INJ0_ERR_ECC_INJ0_SHIFT (0U) -/*! ERR_ECC_INJ0 - Error Injection On 8 bits ECC code Of Ocram Bank0 Write Data - */ -#define MECC_ERR_ECC_INJ0_ERR_ECC_INJ0(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ0_ERR_ECC_INJ0_SHIFT)) & MECC_ERR_ECC_INJ0_ERR_ECC_INJ0_MASK) -#define MECC_ERR_ECC_INJ0_Reserved1_MASK (0xFFFFFF00U) -#define MECC_ERR_ECC_INJ0_Reserved1_SHIFT (8U) -/*! Reserved1 - Reserved + +#define MECC_ERR_ECC_INJ0_ERR_ECC_INJ_MASK (0xFFU) +#define MECC_ERR_ECC_INJ0_ERR_ECC_INJ_SHIFT (0U) +/*! ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank0 Write Data */ -#define MECC_ERR_ECC_INJ0_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ0_Reserved1_SHIFT)) & MECC_ERR_ECC_INJ0_Reserved1_MASK) +#define MECC_ERR_ECC_INJ0_ERR_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ0_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ0_ERR_ECC_INJ_MASK) /*! @} */ -/*! @name ERR_DATA_INJ_LOW1 - Error Injection On Low 32 bits Of Ocram Bank1 Write Data */ +/*! @name ERR_DATA_INJ_LOW1 - Error Injection On LOW 32 bits Of OCRAM Bank1 Write Data */ /*! @{ */ -#define MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_LOW1_MASK (0xFFFFFFFFU) -#define MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_LOW1_SHIFT (0U) -/*! ERR_DATA_INJ_LOW1 - Error Injection On Low 32 bits Of Ocram Bank1 Write Data + +#define MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_MASK (0xFFFFFFFFU) +#define MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_SHIFT (0U) +/*! ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank1 Write Data */ -#define MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_LOW1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_LOW1_SHIFT)) & MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_LOW1_MASK) +#define MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_MASK) /*! @} */ -/*! @name ERR_DATA_INJ_HIGH1 - Error Injection On High 32 bits Of Ocram Bank1 Write Data */ +/*! @name ERR_DATA_INJ_HIGH1 - Error Injection On HIGH 32 bits Of OCRAM Bank1 Write Data */ /*! @{ */ -#define MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_HIGH1_MASK (0xFFFFFFFFU) -#define MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_HIGH1_SHIFT (0U) -/*! ERR_DATA_INJ_HIGH1 - Error Injection On High 32 bits Of Ocram Bank1 Write Data + +#define MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_MASK (0xFFFFFFFFU) +#define MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_SHIFT (0U) +/*! ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank1 Write Data */ -#define MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_HIGH1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_HIGH1_SHIFT)) & MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_HIGH1_MASK) +#define MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_MASK) /*! @} */ -/*! @name ERR_ECC_INJ1 - Error Injection On 8 bits ECC code Of Ocram Bank1 Write Data */ +/*! @name ERR_ECC_INJ1 - Error Injection On 8 bits ECC code Of OCRAM Bank1 Write Data */ /*! @{ */ -#define MECC_ERR_ECC_INJ1_ERR_ECC_INJ1_MASK (0xFFU) -#define MECC_ERR_ECC_INJ1_ERR_ECC_INJ1_SHIFT (0U) -/*! ERR_ECC_INJ1 - Error Injection On 8 bits ECC code Of Ocram Bank1 Write Data - */ -#define MECC_ERR_ECC_INJ1_ERR_ECC_INJ1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ1_ERR_ECC_INJ1_SHIFT)) & MECC_ERR_ECC_INJ1_ERR_ECC_INJ1_MASK) -#define MECC_ERR_ECC_INJ1_Reserved1_MASK (0xFFFFFF00U) -#define MECC_ERR_ECC_INJ1_Reserved1_SHIFT (8U) -/*! Reserved1 - Reserved + +#define MECC_ERR_ECC_INJ1_ERR_ECC_INJ_MASK (0xFFU) +#define MECC_ERR_ECC_INJ1_ERR_ECC_INJ_SHIFT (0U) +/*! ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank1 Write Data */ -#define MECC_ERR_ECC_INJ1_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ1_Reserved1_SHIFT)) & MECC_ERR_ECC_INJ1_Reserved1_MASK) +#define MECC_ERR_ECC_INJ1_ERR_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ1_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ1_ERR_ECC_INJ_MASK) /*! @} */ -/*! @name ERR_DATA_INJ_LOW2 - Error Injection On Low 32 bits Of Ocram Bank2 Write Data */ +/*! @name ERR_DATA_INJ_LOW2 - Error Injection On LOW 32 bits Of OCRAM Bank2 Write Data */ /*! @{ */ -#define MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_LOW2_MASK (0xFFFFFFFFU) -#define MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_LOW2_SHIFT (0U) -/*! ERR_DATA_INJ_LOW2 - Error Injection On Low 32 bits Of Ocram Bank2 Write Data + +#define MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_MASK (0xFFFFFFFFU) +#define MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_SHIFT (0U) +/*! ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank2 Write Data */ -#define MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_LOW2(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_LOW2_SHIFT)) & MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_LOW2_MASK) +#define MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_MASK) /*! @} */ -/*! @name ERR_DATA_INJ_HIGH2 - Error Injection On High 32 bits Of Ocram Bank2 Write Data */ +/*! @name ERR_DATA_INJ_HIGH2 - Error Injection On HIGH 32 bits Of OCRAM Bank2 Write Data */ /*! @{ */ -#define MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_HIGH2_MASK (0xFFFFFFFFU) -#define MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_HIGH2_SHIFT (0U) -/*! ERR_DATA_INJ_HIGH2 - Error Injection On High 32 bits Of Ocram Bank2 Write Data + +#define MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_MASK (0xFFFFFFFFU) +#define MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_SHIFT (0U) +/*! ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank2 Write Data */ -#define MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_HIGH2(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_HIGH2_SHIFT)) & MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_HIGH2_MASK) +#define MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_MASK) /*! @} */ -/*! @name ERR_ECC_INJ2 - Error Injection On 8 bits ECC code Of Ocram Bank2 Write Data */ +/*! @name ERR_ECC_INJ2 - Error Injection On 8 bits ECC code Of OCRAM Bank2 Write Data */ /*! @{ */ -#define MECC_ERR_ECC_INJ2_ERR_ECC_INJ2_MASK (0xFFU) -#define MECC_ERR_ECC_INJ2_ERR_ECC_INJ2_SHIFT (0U) -/*! ERR_ECC_INJ2 - Error Injection On 8 bits ECC code Of Ocram Bank2 Write Data - */ -#define MECC_ERR_ECC_INJ2_ERR_ECC_INJ2(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ2_ERR_ECC_INJ2_SHIFT)) & MECC_ERR_ECC_INJ2_ERR_ECC_INJ2_MASK) -#define MECC_ERR_ECC_INJ2_Reserved1_MASK (0xFFFFFF00U) -#define MECC_ERR_ECC_INJ2_Reserved1_SHIFT (8U) -/*! Reserved1 - Reserved + +#define MECC_ERR_ECC_INJ2_ERR_ECC_INJ_MASK (0xFFU) +#define MECC_ERR_ECC_INJ2_ERR_ECC_INJ_SHIFT (0U) +/*! ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank2 Write Data */ -#define MECC_ERR_ECC_INJ2_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ2_Reserved1_SHIFT)) & MECC_ERR_ECC_INJ2_Reserved1_MASK) +#define MECC_ERR_ECC_INJ2_ERR_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ2_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ2_ERR_ECC_INJ_MASK) /*! @} */ -/*! @name ERR_DATA_INJ_LOW3 - Error Injection On Low 32 bits Of Ocram Bank3 Write Data */ +/*! @name ERR_DATA_INJ_LOW3 - Error Injection On LOW 32 bits Of OCRAM Bank3 Write Data */ /*! @{ */ -#define MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_LOW3_MASK (0xFFFFFFFFU) -#define MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_LOW3_SHIFT (0U) -/*! ERR_DATA_INJ_LOW3 - Error Injection On Low 32 bits Of Ocram Bank3 Write Data + +#define MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_MASK (0xFFFFFFFFU) +#define MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_SHIFT (0U) +/*! ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank3 Write Data */ -#define MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_LOW3(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_LOW3_SHIFT)) & MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_LOW3_MASK) +#define MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_MASK) /*! @} */ -/*! @name ERR_DATA_INJ_HIGH3 - Error Injection On High 32 bits Of Ocram Bank3 Write Data */ +/*! @name ERR_DATA_INJ_HIGH3 - Error Injection On HIGH 32 bits Of OCRAM Bank3 Write Data */ /*! @{ */ -#define MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_HIGH2_MASK (0xFFFFFFFFU) -#define MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_HIGH2_SHIFT (0U) -/*! ERR_DATA_INJ_HIGH2 - Error Injection On High 32 bits Of Ocram Bank2 Write Data + +#define MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_MASK (0xFFFFFFFFU) +#define MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_SHIFT (0U) +/*! ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank3 Write Data */ -#define MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_HIGH2(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_HIGH2_SHIFT)) & MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_HIGH2_MASK) +#define MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_MASK) /*! @} */ -/*! @name ERR_ECC_INJ3 - Error Injection On 8 bits ECC code Of Ocram Bank3 Write Data */ +/*! @name ERR_ECC_INJ3 - Error Injection On 8 bits ECC code Of OCRAM Bank3 Write Data */ /*! @{ */ -#define MECC_ERR_ECC_INJ3_ERR_ECC_INJ3_MASK (0xFFU) -#define MECC_ERR_ECC_INJ3_ERR_ECC_INJ3_SHIFT (0U) -/*! ERR_ECC_INJ3 - Error Injection On 8 bits ECC code Of Ocram Bank3 Write Data - */ -#define MECC_ERR_ECC_INJ3_ERR_ECC_INJ3(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ3_ERR_ECC_INJ3_SHIFT)) & MECC_ERR_ECC_INJ3_ERR_ECC_INJ3_MASK) -#define MECC_ERR_ECC_INJ3_Reserved1_MASK (0xFFFFFF00U) -#define MECC_ERR_ECC_INJ3_Reserved1_SHIFT (8U) -/*! Reserved1 - Reserved + +#define MECC_ERR_ECC_INJ3_ERR_ECC_INJ_MASK (0xFFU) +#define MECC_ERR_ECC_INJ3_ERR_ECC_INJ_SHIFT (0U) +/*! ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank3 Write Data */ -#define MECC_ERR_ECC_INJ3_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ3_Reserved1_SHIFT)) & MECC_ERR_ECC_INJ3_Reserved1_MASK) +#define MECC_ERR_ECC_INJ3_ERR_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ3_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ3_ERR_ECC_INJ_MASK) /*! @} */ -/*! @name SINGLE_ERR_ADDR_ECC0 - Single Error Address And ECC Code On Ocram Bank0 */ +/*! @name SINGLE_ERR_ADDR_ECC0 - Single Error Address And ECC code On OCRAM Bank0 */ /*! @{ */ -#define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC0_MASK (0xFFU) -#define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC0_SHIFT (0U) -/*! SINGLE_ERR_ECC0 - Single Error ECC Code On Ocram Bank0 - */ -#define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC0(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC0_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC0_MASK) -#define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR0_MASK (0x7FFFF00U) -#define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR0_SHIFT (8U) -/*! SINGLE_ERR_ADDR0 - Single Error Address On Ocram Bank0 + +#define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_MASK (0xFFU) +#define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_SHIFT (0U) +/*! SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank0 */ -#define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR0_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR0_MASK) -#define MECC_SINGLE_ERR_ADDR_ECC0_Reserved1_MASK (0xF8000000U) -#define MECC_SINGLE_ERR_ADDR_ECC0_Reserved1_SHIFT (27U) -/*! Reserved1 - Reserved +#define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_MASK) + +#define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_MASK (0x7FFFF00U) +#define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_SHIFT (8U) +/*! SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank0 */ -#define MECC_SINGLE_ERR_ADDR_ECC0_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC0_Reserved1_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC0_Reserved1_MASK) +#define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_MASK) /*! @} */ -/*! @name SINGLE_ERR_DATA_LOW0 - Low 32 Bits Single Error Read Data On Ocram Bank0 */ +/*! @name SINGLE_ERR_DATA_LOW0 - LOW 32 Bits Single Error Read Data On OCRAM Bank0 */ /*! @{ */ -#define MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_LOW0_MASK (0xFFFFFFFFU) -#define MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_LOW0_SHIFT (0U) -/*! SINGLE_ERR_DATA_LOW0 - Low 32 Bits Single Error Read Data On Ocram Bank0 + +#define MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU) +#define MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_SHIFT (0U) +/*! SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank0 */ -#define MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_LOW0(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_LOW0_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_LOW0_MASK) +#define MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_MASK) /*! @} */ -/*! @name SINGLE_ERR_DATA_HIGH0 - High 32 Bits Single Error Read Data On Ocram Bank0 */ +/*! @name SINGLE_ERR_DATA_HIGH0 - HIGH 32 Bits Single Error Read Data On OCRAM Bank0 */ /*! @{ */ -#define MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_HIGH0_MASK (0xFFFFFFFFU) -#define MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_HIGH0_SHIFT (0U) -/*! SINGLE_ERR_DATA_HIGH0 - High 32 Bits Single Error Read Data On Ocram Bank0 + +#define MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU) +#define MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_SHIFT (0U) +/*! SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank0 */ -#define MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_HIGH0(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_HIGH0_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_HIGH0_MASK) +#define MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_MASK) /*! @} */ -/*! @name SINGLE_ERR_POS_LOW0 - Low Single Error Bit Position On Ocram Bank0 */ +/*! @name SINGLE_ERR_POS_LOW0 - LOW Single Error Bit Position On OCRAM Bank0 */ /*! @{ */ -#define MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_LOW0_MASK (0xFFFFFFFFU) -#define MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_LOW0_SHIFT (0U) -/*! SINGLE_ERR_POS_LOW0 - Low Single Error Bit Position On Ocram Bank0 + +#define MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_MASK (0xFFFFFFFFU) +#define MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_SHIFT (0U) +/*! SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank0 */ -#define MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_LOW0(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_LOW0_SHIFT)) & MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_LOW0_MASK) +#define MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_MASK) /*! @} */ -/*! @name SINGLE_ERR_POS_HIGH0 - High Single Error Bit Position On Ocram Bank0 */ +/*! @name SINGLE_ERR_POS_HIGH0 - HIGH Single Error Bit Position On OCRAM Bank0 */ /*! @{ */ -#define MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_HIGH0_MASK (0xFFFFFFFFU) -#define MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_HIGH0_SHIFT (0U) -/*! SINGLE_ERR_POS_HIGH0 - High Single Error Bit Position On Ocram Bank0 + +#define MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_MASK (0xFFFFFFFFU) +#define MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_SHIFT (0U) +/*! SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank0 */ -#define MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_HIGH0(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_HIGH0_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_HIGH0_MASK) +#define MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_MASK) /*! @} */ -/*! @name SINGLE_ERR_ADDR_ECC1 - Single Error Address And ECC Code On Ocram Bank1 */ +/*! @name SINGLE_ERR_ADDR_ECC1 - Single Error Address And ECC code On OCRAM Bank1 */ /*! @{ */ -#define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC1_MASK (0xFFU) -#define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC1_SHIFT (0U) -/*! SINGLE_ERR_ECC1 - Single Error ECC Code On Ocram Bank1 - */ -#define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC1(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC1_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC1_MASK) -#define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR1_MASK (0x7FFFF00U) -#define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR1_SHIFT (8U) -/*! SINGLE_ERR_ADDR1 - Single Error Address On Ocram Bank1 + +#define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_MASK (0xFFU) +#define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_SHIFT (0U) +/*! SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank1 */ -#define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR1_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR1_MASK) -#define MECC_SINGLE_ERR_ADDR_ECC1_Reserved1_MASK (0xF8000000U) -#define MECC_SINGLE_ERR_ADDR_ECC1_Reserved1_SHIFT (27U) -/*! Reserved1 - Reserved +#define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_MASK) + +#define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_MASK (0x7FFFF00U) +#define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_SHIFT (8U) +/*! SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank1 */ -#define MECC_SINGLE_ERR_ADDR_ECC1_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC1_Reserved1_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC1_Reserved1_MASK) +#define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_MASK) /*! @} */ -/*! @name SINGLE_ERR_DATA_LOW1 - Low 32 Bits Single Error Read Data On Ocram Bank1 */ +/*! @name SINGLE_ERR_DATA_LOW1 - LOW 32 Bits Single Error Read Data On OCRAM Bank1 */ /*! @{ */ -#define MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_LOW1_MASK (0xFFFFFFFFU) -#define MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_LOW1_SHIFT (0U) -/*! SINGLE_ERR_DATA_LOW1 - Low 32 Bits Single Error Read Data On Ocram Bank1 + +#define MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU) +#define MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_SHIFT (0U) +/*! SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank1 */ -#define MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_LOW1(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_LOW1_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_LOW1_MASK) +#define MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_MASK) /*! @} */ -/*! @name SINGLE_ERR_DATA_HIGH1 - High 32 Bits Single Error Read Data On Ocram Bank1 */ +/*! @name SINGLE_ERR_DATA_HIGH1 - HIGH 32 Bits Single Error Read Data On OCRAM Bank1 */ /*! @{ */ -#define MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_HIGH1_MASK (0xFFFFFFFFU) -#define MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_HIGH1_SHIFT (0U) -/*! SINGLE_ERR_DATA_HIGH1 - High 32 Bits Single Error Read Data On Ocram Bank1 + +#define MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU) +#define MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_SHIFT (0U) +/*! SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank1 */ -#define MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_HIGH1(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_HIGH1_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_HIGH1_MASK) +#define MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_MASK) /*! @} */ -/*! @name SINGLE_ERR_POS_LOW1 - Low Single Error Bit Position On Ocram Bank1 */ +/*! @name SINGLE_ERR_POS_LOW1 - LOW Single Error Bit Position On OCRAM Bank1 */ /*! @{ */ -#define MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_LOW1_MASK (0xFFFFFFFFU) -#define MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_LOW1_SHIFT (0U) -/*! SINGLE_ERR_POS_LOW1 - Low Single Error Bit Position On Ocram Bank1 + +#define MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_MASK (0xFFFFFFFFU) +#define MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_SHIFT (0U) +/*! SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank1 */ -#define MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_LOW1(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_LOW1_SHIFT)) & MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_LOW1_MASK) +#define MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_MASK) /*! @} */ -/*! @name SINGLE_ERR_POS_HIGH1 - High Single Error Bit Position On Ocram Bank1 */ +/*! @name SINGLE_ERR_POS_HIGH1 - HIGH Single Error Bit Position On OCRAM Bank1 */ /*! @{ */ -#define MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_HIGH1_MASK (0xFFFFFFFFU) -#define MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_HIGH1_SHIFT (0U) -/*! SINGLE_ERR_POS_HIGH1 - High Single Error Bit Position On Ocram Bank1 + +#define MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_MASK (0xFFFFFFFFU) +#define MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_SHIFT (0U) +/*! SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank1 */ -#define MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_HIGH1(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_HIGH1_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_HIGH1_MASK) +#define MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_MASK) /*! @} */ -/*! @name SINGLE_ERR_ADDR_ECC2 - Single Error Address And ECC Code On Ocram Bank2 */ +/*! @name SINGLE_ERR_ADDR_ECC2 - Single Error Address And ECC code On OCRAM Bank2 */ /*! @{ */ -#define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC2_MASK (0xFFU) -#define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC2_SHIFT (0U) -/*! SINGLE_ERR_ECC2 - Single Error ECC Code On Ocram Bank2 - */ -#define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC2(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC2_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC2_MASK) -#define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR2_MASK (0x7FFFF00U) -#define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR2_SHIFT (8U) -/*! SINGLE_ERR_ADDR2 - Single Error Address On Ocram Bank2 + +#define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_MASK (0xFFU) +#define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_SHIFT (0U) +/*! SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank2 */ -#define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR2(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR2_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR2_MASK) -#define MECC_SINGLE_ERR_ADDR_ECC2_Reserved1_MASK (0xF8000000U) -#define MECC_SINGLE_ERR_ADDR_ECC2_Reserved1_SHIFT (27U) -/*! Reserved1 - Reserved +#define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_MASK) + +#define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_MASK (0x7FFFF00U) +#define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_SHIFT (8U) +/*! SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank2 */ -#define MECC_SINGLE_ERR_ADDR_ECC2_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC2_Reserved1_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC2_Reserved1_MASK) +#define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_MASK) /*! @} */ -/*! @name SINGLE_ERR_DATA_LOW2 - Low 32 Bits Single Error Read Data On Ocram Bank2 */ +/*! @name SINGLE_ERR_DATA_LOW2 - LOW 32 Bits Single Error Read Data On OCRAM Bank2 */ /*! @{ */ -#define MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_LOW2_MASK (0xFFFFFFFFU) -#define MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_LOW2_SHIFT (0U) -/*! SINGLE_ERR_DATA_LOW2 - Low 32 Bits Single Error Read Data On Ocram Bank2 + +#define MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU) +#define MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_SHIFT (0U) +/*! SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank2 */ -#define MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_LOW2(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_LOW2_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_LOW2_MASK) +#define MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_MASK) /*! @} */ -/*! @name SINGLE_ERR_DATA_HIGH2 - High 32 Bits Single Error Read Data On Ocram Bank2 */ +/*! @name SINGLE_ERR_DATA_HIGH2 - HIGH 32 Bits Single Error Read Data On OCRAM Bank2 */ /*! @{ */ -#define MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_HIGH2_MASK (0xFFFFFFFFU) -#define MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_HIGH2_SHIFT (0U) -/*! SINGLE_ERR_DATA_HIGH2 - High 32 Bits Single Error Read Data On Ocram Bank2 + +#define MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU) +#define MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_SHIFT (0U) +/*! SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank2 */ -#define MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_HIGH2(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_HIGH2_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_HIGH2_MASK) +#define MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_MASK) /*! @} */ -/*! @name SINGLE_ERR_POS_LOW2 - Low Single Error Bit Position On Ocram Bank2 */ +/*! @name SINGLE_ERR_POS_LOW2 - LOW Single Error Bit Position On OCRAM Bank2 */ /*! @{ */ -#define MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_LOW2_MASK (0xFFFFFFFFU) -#define MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_LOW2_SHIFT (0U) -/*! SINGLE_ERR_POS_LOW2 - Low Single Error Bit Position On Ocram Bank2 + +#define MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_MASK (0xFFFFFFFFU) +#define MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_SHIFT (0U) +/*! SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank2 */ -#define MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_LOW2(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_LOW2_SHIFT)) & MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_LOW2_MASK) +#define MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_MASK) /*! @} */ -/*! @name SINGLE_ERR_POS_HIGH2 - High Single Error Bit Position On Ocram Bank2 */ +/*! @name SINGLE_ERR_POS_HIGH2 - HIGH Single Error Bit Position On OCRAM Bank2 */ /*! @{ */ -#define MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_HIGH2_MASK (0xFFFFFFFFU) -#define MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_HIGH2_SHIFT (0U) -/*! SINGLE_ERR_POS_HIGH2 - High Single Error Bit Position On Ocram Bank2 + +#define MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_MASK (0xFFFFFFFFU) +#define MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_SHIFT (0U) +/*! SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank2 */ -#define MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_HIGH2(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_HIGH2_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_HIGH2_MASK) +#define MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_MASK) /*! @} */ -/*! @name SINGLE_ERR_ADDR_ECC3 - Single Error Address And ECC Code On Ocram Bank3 */ +/*! @name SINGLE_ERR_ADDR_ECC3 - Single Error Address And ECC code On OCRAM Bank3 */ /*! @{ */ -#define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC3_MASK (0xFFU) -#define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC3_SHIFT (0U) -/*! SINGLE_ERR_ECC3 - Single Error ECC Code On Ocram Bank3 - */ -#define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC3(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC3_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC3_MASK) -#define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR3_MASK (0x7FFFF00U) -#define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR3_SHIFT (8U) -/*! SINGLE_ERR_ADDR3 - Single Error Address On Ocram Bank3 + +#define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_MASK (0xFFU) +#define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_SHIFT (0U) +/*! SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank3 */ -#define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR3(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR3_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR3_MASK) -#define MECC_SINGLE_ERR_ADDR_ECC3_Reserved1_MASK (0xF8000000U) -#define MECC_SINGLE_ERR_ADDR_ECC3_Reserved1_SHIFT (27U) -/*! Reserved1 - Reserved +#define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_MASK) + +#define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_MASK (0x7FFFF00U) +#define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_SHIFT (8U) +/*! SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank3 */ -#define MECC_SINGLE_ERR_ADDR_ECC3_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC3_Reserved1_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC3_Reserved1_MASK) +#define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_MASK) /*! @} */ -/*! @name SINGLE_ERR_DATA_LOW3 - Low 32 Bits Single Error Read Data On Ocram Bank3 */ +/*! @name SINGLE_ERR_DATA_LOW3 - LOW 32 Bits Single Error Read Data On OCRAM Bank3 */ /*! @{ */ -#define MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_LOW3_MASK (0xFFFFFFFFU) -#define MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_LOW3_SHIFT (0U) -/*! SINGLE_ERR_DATA_LOW3 - Low 32 Bits Single Error Read Data On Ocram Bank3 + +#define MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU) +#define MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_SHIFT (0U) +/*! SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank3 */ -#define MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_LOW3(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_LOW3_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_LOW3_MASK) +#define MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_MASK) /*! @} */ -/*! @name SINGLE_ERR_DATA_HIGH3 - High 32 Bits Single Error Read Data On Ocram Bank3 */ +/*! @name SINGLE_ERR_DATA_HIGH3 - HIGH 32 Bits Single Error Read Data On OCRAM Bank3 */ /*! @{ */ -#define MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_HIGH3_MASK (0xFFFFFFFFU) -#define MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_HIGH3_SHIFT (0U) -/*! SINGLE_ERR_DATA_HIGH3 - High 32 Bits Single Error Read Data On Ocram Bank3 + +#define MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU) +#define MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_SHIFT (0U) +/*! SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank3 */ -#define MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_HIGH3(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_HIGH3_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_HIGH3_MASK) +#define MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_MASK) /*! @} */ -/*! @name SINGLE_ERR_POS_LOW3 - Low Single Error Bit Position On Ocram Bank3 */ +/*! @name SINGLE_ERR_POS_LOW3 - LOW Single Error Bit Position On OCRAM Bank3 */ /*! @{ */ -#define MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_LOW3_MASK (0xFFFFFFFFU) -#define MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_LOW3_SHIFT (0U) -/*! SINGLE_ERR_POS_LOW3 - Low Single Error Bit Position On Ocram Bank3 + +#define MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_MASK (0xFFFFFFFFU) +#define MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_SHIFT (0U) +/*! SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank3 */ -#define MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_LOW3(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_LOW3_SHIFT)) & MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_LOW3_MASK) +#define MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_MASK) /*! @} */ -/*! @name SINGLE_ERR_POS_HIGH3 - High Single Error Bit Position On Ocram Bank3 */ +/*! @name SINGLE_ERR_POS_HIGH3 - HIGH Single Error Bit Position On OCRAM Bank3 */ /*! @{ */ -#define MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_HIGH3_MASK (0xFFFFFFFFU) -#define MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_HIGH3_SHIFT (0U) -/*! SINGLE_ERR_POS_HIGH3 - High Single Error Bit Position On Ocram Bank3 + +#define MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_MASK (0xFFFFFFFFU) +#define MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_SHIFT (0U) +/*! SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank3 */ -#define MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_HIGH3(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_HIGH3_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_HIGH3_MASK) +#define MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_MASK) /*! @} */ -/*! @name MULTI_ERR_ADDR_ECC0 - Multiple Error Address And ECC Code On Ocram Bank0 */ +/*! @name MULTI_ERR_ADDR_ECC0 - Multiple Error Address And ECC code On OCRAM Bank0 */ /*! @{ */ -#define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC0_MASK (0xFFU) -#define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC0_SHIFT (0U) -/*! MULTI_ERR_ECC0 - Multiple Error ECC Code On Ocram Bank0 - */ -#define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC0(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC0_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC0_MASK) -#define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR0_MASK (0x7FFFF00U) -#define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR0_SHIFT (8U) -/*! MULTI_ERR_ADDR0 - Multiple Error Address On Ocram Bank0 + +#define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_MASK (0xFFU) +#define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_SHIFT (0U) +/*! MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank0 */ -#define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR0_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR0_MASK) -#define MECC_MULTI_ERR_ADDR_ECC0_Reserved1_MASK (0xF8000000U) -#define MECC_MULTI_ERR_ADDR_ECC0_Reserved1_SHIFT (27U) -/*! Reserved1 - Reserved +#define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_MASK) + +#define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_MASK (0x7FFFF00U) +#define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_SHIFT (8U) +/*! MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank0 */ -#define MECC_MULTI_ERR_ADDR_ECC0_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC0_Reserved1_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC0_Reserved1_MASK) +#define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_MASK) /*! @} */ -/*! @name MULTI_ERR_DATA_LOW0 - Low 32 Bits Multiple Error Read Data On Ocram Bank0 */ +/*! @name MULTI_ERR_DATA_LOW0 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank0 */ /*! @{ */ -#define MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_LOW0_MASK (0xFFFFFFFFU) -#define MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_LOW0_SHIFT (0U) -/*! MULTI_ERR_DATA_LOW0 - Low 32 Bits Multiple Error Read Data On Ocram Bank0 + +#define MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_MASK (0xFFFFFFFFU) +#define MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_SHIFT (0U) +/*! MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank0 */ -#define MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_LOW0(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_LOW0_SHIFT)) & MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_LOW0_MASK) +#define MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_MASK) /*! @} */ -/*! @name MULTI_ERR_DATA_HIGH0 - High 32 Bits Multiple Error Read Data On Ocram Bank0 */ +/*! @name MULTI_ERR_DATA_HIGH0 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank0 */ /*! @{ */ -#define MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_HIGH0_MASK (0xFFFFFFFFU) -#define MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_HIGH0_SHIFT (0U) -/*! MULTI_ERR_DATA_HIGH0 - High 32 Bits Multiple Error Read Data On Ocram Bank0 + +#define MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_MASK (0xFFFFFFFFU) +#define MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_SHIFT (0U) +/*! MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank0 */ -#define MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_HIGH0(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_HIGH0_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_HIGH0_MASK) +#define MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_MASK) /*! @} */ -/*! @name MULTI_ERR_ADDR_ECC1 - Multiple Error Address And ECC Code On Ocram Bank1 */ +/*! @name MULTI_ERR_ADDR_ECC1 - Multiple Error Address And ECC code On OCRAM Bank1 */ /*! @{ */ -#define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC1_MASK (0xFFU) -#define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC1_SHIFT (0U) -/*! MULTI_ERR_ECC1 - Multiple Error ECC Code On Ocram Bank1 - */ -#define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC1(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC1_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC1_MASK) -#define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR1_MASK (0x7FFFF00U) -#define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR1_SHIFT (8U) -/*! MULTI_ERR_ADDR1 - Multiple Error Address On Ocram Bank1 + +#define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_MASK (0xFFU) +#define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_SHIFT (0U) +/*! MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank1 */ -#define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR1_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR1_MASK) -#define MECC_MULTI_ERR_ADDR_ECC1_Reserved1_MASK (0xF8000000U) -#define MECC_MULTI_ERR_ADDR_ECC1_Reserved1_SHIFT (27U) -/*! Reserved1 - Reserved +#define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_MASK) + +#define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_MASK (0x7FFFF00U) +#define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_SHIFT (8U) +/*! MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank1 */ -#define MECC_MULTI_ERR_ADDR_ECC1_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC1_Reserved1_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC1_Reserved1_MASK) +#define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_MASK) /*! @} */ -/*! @name MULTI_ERR_DATA_LOW1 - Low 32 Bits Multiple Error Read Data On Ocram Bank1 */ +/*! @name MULTI_ERR_DATA_LOW1 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank1 */ /*! @{ */ -#define MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_LOW1_MASK (0xFFFFFFFFU) -#define MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_LOW1_SHIFT (0U) -/*! MULTI_ERR_DATA_LOW1 - Low 32 Bits Multiple Error Read Data On Ocram Bank1 + +#define MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_MASK (0xFFFFFFFFU) +#define MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_SHIFT (0U) +/*! MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank1 */ -#define MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_LOW1(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_LOW1_SHIFT)) & MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_LOW1_MASK) +#define MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_MASK) /*! @} */ -/*! @name MULTI_ERR_DATA_HIGH1 - High 32 Bits Multiple Error Read Data On Ocram Bank1 */ +/*! @name MULTI_ERR_DATA_HIGH1 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank1 */ /*! @{ */ -#define MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_HIGH1_MASK (0xFFFFFFFFU) -#define MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_HIGH1_SHIFT (0U) -/*! MULTI_ERR_DATA_HIGH1 - High 32 Bits Multiple Error Read Data On Ocram Bank1 + +#define MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_MASK (0xFFFFFFFFU) +#define MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_SHIFT (0U) +/*! MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank1 */ -#define MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_HIGH1(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_HIGH1_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_HIGH1_MASK) +#define MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_MASK) /*! @} */ -/*! @name MULTI_ERR_ADDR_ECC2 - Multiple Error Address And ECC Code On Ocram Bank2 */ +/*! @name MULTI_ERR_ADDR_ECC2 - Multiple Error Address And ECC code On OCRAM Bank2 */ /*! @{ */ -#define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC2_MASK (0xFFU) -#define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC2_SHIFT (0U) -/*! MULTI_ERR_ECC2 - Multiple Error ECC Code On Ocram Bank2 - */ -#define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC2(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC2_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC2_MASK) -#define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR2_MASK (0x7FFFF00U) -#define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR2_SHIFT (8U) -/*! MULTI_ERR_ADDR2 - Multiple Error Address On Ocram Bank2 + +#define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_MASK (0xFFU) +#define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_SHIFT (0U) +/*! MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank2 */ -#define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR2(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR2_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR2_MASK) -#define MECC_MULTI_ERR_ADDR_ECC2_Reserved1_MASK (0xF8000000U) -#define MECC_MULTI_ERR_ADDR_ECC2_Reserved1_SHIFT (27U) -/*! Reserved1 - Reserved +#define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_MASK) + +#define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_MASK (0x7FFFF00U) +#define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_SHIFT (8U) +/*! MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank2 */ -#define MECC_MULTI_ERR_ADDR_ECC2_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC2_Reserved1_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC2_Reserved1_MASK) +#define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_MASK) /*! @} */ -/*! @name MULTI_ERR_DATA_LOW2 - Low 32 Bits Multiple Error Read Data On Ocram Bank2 */ +/*! @name MULTI_ERR_DATA_LOW2 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank2 */ /*! @{ */ -#define MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_LOW2_MASK (0xFFFFFFFFU) -#define MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_LOW2_SHIFT (0U) -/*! MULTI_ERR_DATA_LOW2 - Low 32 Bits Multiple Error Read Data On Ocram Bank2 + +#define MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_MASK (0xFFFFFFFFU) +#define MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_SHIFT (0U) +/*! MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank2 */ -#define MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_LOW2(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_LOW2_SHIFT)) & MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_LOW2_MASK) +#define MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_MASK) /*! @} */ -/*! @name MULTI_ERR_DATA_HIGH2 - High 32 Bits Multiple Error Read Data On Ocram Bank2 */ +/*! @name MULTI_ERR_DATA_HIGH2 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank2 */ /*! @{ */ -#define MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_HIGH2_MASK (0xFFFFFFFFU) -#define MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_HIGH2_SHIFT (0U) -/*! MULTI_ERR_DATA_HIGH2 - High 32 Bits Multiple Error Read Data On Ocram Bank2 + +#define MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_MASK (0xFFFFFFFFU) +#define MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_SHIFT (0U) +/*! MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank2 */ -#define MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_HIGH2(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_HIGH2_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_HIGH2_MASK) +#define MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_MASK) /*! @} */ -/*! @name MULTI_ERR_ADDR_ECC3 - Multiple Error Address And ECC Code On Ocram Bank3 */ +/*! @name MULTI_ERR_ADDR_ECC3 - Multiple Error Address And ECC code On OCRAM Bank3 */ /*! @{ */ -#define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC3_MASK (0xFFU) -#define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC3_SHIFT (0U) -/*! MULTI_ERR_ECC3 - Multiple Error ECC Code On Ocram Bank3 - */ -#define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC3(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC3_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC3_MASK) -#define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR3_MASK (0x7FFFF00U) -#define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR3_SHIFT (8U) -/*! MULTI_ERR_ADDR3 - Multiple Error Address On Ocram Bank3 + +#define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_MASK (0xFFU) +#define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_SHIFT (0U) +/*! MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank3 */ -#define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR3(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR3_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR3_MASK) -#define MECC_MULTI_ERR_ADDR_ECC3_Reserved1_MASK (0xF8000000U) -#define MECC_MULTI_ERR_ADDR_ECC3_Reserved1_SHIFT (27U) -/*! Reserved1 - Reserved +#define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_MASK) + +#define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_MASK (0x7FFFF00U) +#define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_SHIFT (8U) +/*! MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank3 */ -#define MECC_MULTI_ERR_ADDR_ECC3_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC3_Reserved1_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC3_Reserved1_MASK) +#define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_MASK) /*! @} */ -/*! @name MULTI_ERR_DATA_LOW3 - Low 32 Bits Multiple Error Read Data On Ocram Bank3 */ +/*! @name MULTI_ERR_DATA_LOW3 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank3 */ /*! @{ */ -#define MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_LOW3_MASK (0xFFFFFFFFU) -#define MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_LOW3_SHIFT (0U) -/*! MULTI_ERR_DATA_LOW3 - Low 32 Bits Multiple Error Read Data On Ocram Bank3 + +#define MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_MASK (0xFFFFFFFFU) +#define MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_SHIFT (0U) +/*! MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank3 */ -#define MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_LOW3(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_LOW3_SHIFT)) & MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_LOW3_MASK) +#define MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_MASK) /*! @} */ -/*! @name MULTI_ERR_DATA_HIGH3 - High 32 Bits Multiple Error Read Data On Ocram Bank3 */ +/*! @name MULTI_ERR_DATA_HIGH3 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank3 */ /*! @{ */ -#define MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_HIGH3_MASK (0xFFFFFFFFU) -#define MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_HIGH3_SHIFT (0U) -/*! MULTI_ERR_DATA_HIGH3 - High 32 Bits Multiple Error Read Data On Ocram Bank3 + +#define MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_MASK (0xFFFFFFFFU) +#define MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_SHIFT (0U) +/*! MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank3 */ -#define MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_HIGH3(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_HIGH3_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_HIGH3_MASK) +#define MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_MASK) /*! @} */ -/*! @name PIPE_ECC_EN - Ocram Pipeline And ECC Enable */ +/*! @name PIPE_ECC_EN - OCRAM Pipeline And ECC Enable */ /*! @{ */ + #define MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_MASK (0x1U) #define MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_SHIFT (0U) /*! READ_DATA_WAIT_EN - Read Data Wait Enable @@ -63019,6 +73293,7 @@ typedef struct { * 0b1..Enable. */ #define MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_SHIFT)) & MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_MASK) + #define MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_MASK (0x2U) #define MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_SHIFT (1U) /*! READ_ADDR_PIPE_EN - Read Address Pipeline Enable @@ -63026,6 +73301,7 @@ typedef struct { * 0b1..Enable. */ #define MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_MASK) + #define MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_MASK (0x4U) #define MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_SHIFT (2U) /*! WRITE_DATA_PIPE_EN - Write Data Pipeline Enable @@ -63033,6 +73309,7 @@ typedef struct { * 0b1..Enable. */ #define MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_MASK) + #define MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_MASK (0x8U) #define MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_SHIFT (3U) /*! WRITE_ADDR_PIPE_EN - Write Address Pipeline Enable @@ -63040,6 +73317,7 @@ typedef struct { * 0b1..Enable. */ #define MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_MASK) + #define MECC_PIPE_ECC_EN_ECC_EN_MASK (0x10U) #define MECC_PIPE_ECC_EN_ECC_EN_SHIFT (4U) /*! ECC_EN - ECC Function Enable @@ -63047,40 +73325,42 @@ typedef struct { * 0b1..Enable. */ #define MECC_PIPE_ECC_EN_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_ECC_EN_SHIFT)) & MECC_PIPE_ECC_EN_ECC_EN_MASK) -#define MECC_PIPE_ECC_EN_Reserved1_MASK (0xFFFFFFE0U) -#define MECC_PIPE_ECC_EN_Reserved1_SHIFT (5U) -/*! Reserved1 - Reserved - */ -#define MECC_PIPE_ECC_EN_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_Reserved1_SHIFT)) & MECC_PIPE_ECC_EN_Reserved1_MASK) /*! @} */ /*! @name PENDING_STAT - Pending Status */ /*! @{ */ + #define MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_MASK (0x1U) #define MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_SHIFT (0U) /*! READ_DATA_WAIT_PENDING - Read Data Wait Pending + * 0b0..No update pending status for READ_DATA_WAIT_EN. + * 0b1..When READ_DATA_WAIT_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller. */ #define MECC_PENDING_STAT_READ_DATA_WAIT_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_SHIFT)) & MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_MASK) + #define MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_MASK (0x2U) #define MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_SHIFT (1U) /*! READ_ADDR_PIPE_PENDING - Read Address Pipeline Pending + * 0b0..No update pending status for READ_ADDR_PIPE_EN. + * 0b1..When READ_ADDR_PIPE_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller. */ #define MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_MASK) + #define MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_MASK (0x4U) #define MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_SHIFT (2U) /*! WRITE_DATA_PIPE_PENDING - Write Data Pipeline Pending + * 0b0..No update pending status for WRITE_DATA_PIPE_EN. + * 0b1..When WRITE_DATA_PIPE_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller. */ #define MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_MASK) + #define MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_MASK (0x8U) #define MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_SHIFT (3U) /*! WRITE_ADDR_PIPE_PENDING - Write Address Pipeline Pending + * 0b0..No update pending status for WRITE_ADDR_PIPE_EN. + * 0b1..When WRITE_ADDR_PIPE_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller. */ #define MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_MASK) -#define MECC_PENDING_STAT_Reserved1_MASK (0xFFFFFFF0U) -#define MECC_PENDING_STAT_Reserved1_SHIFT (4U) -/*! Reserved1 - Reserved - */ -#define MECC_PENDING_STAT_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_Reserved1_SHIFT)) & MECC_PENDING_STAT_Reserved1_MASK) /*! @} */ @@ -63119,20 +73399,28 @@ typedef struct { /** MIPI_CSI2RX - Register Layout Typedef */ typedef struct { - uint8_t reserved0[0x100]; - __IO uint32_t CSI2RX_CFG_NUM_LANES; /**< , offset: 0x0 */ - __IO uint32_t CSI2RX_CFG_DISABLE_DATA_LANES; /**< , offset: 0x4 */ - __I uint32_t CSI2RX_BIT_ERR; /**< , offset: 0x8 */ - __I uint32_t CSI2RX_IRQ_STATUS; /**< , offset: 0xC */ - __IO uint32_t CSI2RX_IRQ_MASK; /**< , offset: 0x10 */ - __I uint32_t CSI2RX_ULPS_STATUS; /**< , offset: 0x14 */ - __I uint32_t CSI2RX_PPI_ERRSOT_HS; /**< , offset: 0x18 */ - __I uint32_t CSI2RX_PPI_ERRSOTSYNC_HS; /**< , offset: 0x1C */ - __I uint32_t CSI2RX_PPI_ERRESC; /**< , offset: 0x20 */ - __I uint32_t CSI2RX_PPI_ERRSYNCESC; /**< , offset: 0x24 */ - __I uint32_t CSI2RX_PPI_ERRCONTROL; /**< , offset: 0x28 */ - __IO uint32_t CSI2RX_CFG_DISABLE_PAYLOAD_0; /**< , offset: 0x2C */ - __IO uint32_t CSI2RX_CFG_DISABLE_PAYLOAD_1; /**< , offset: 0x30 */ + uint8_t RESERVED_0[256]; + __IO uint32_t CFG_NUM_LANES; /**< Lane Configuration Register, offset: 0x100 */ + __IO uint32_t CFG_DISABLE_DATA_LANES; /**< Disable Data Lane Register, offset: 0x104 */ + __I uint32_t BIT_ERR; /**< ECC and CRC Error Status Register, offset: 0x108 */ + __I uint32_t IRQ_STATUS; /**< IRQ Status Register, offset: 0x10C */ + __IO uint32_t IRQ_MASK; /**< IRQ Mask Setting Register, offset: 0x110 */ + __I uint32_t ULPS_STATUS; /**< Ultra Low Power State (ULPS) Status Register, offset: 0x114 */ + __I uint32_t PPI_ERRSOT_HS; /**< ERRSot HS Status Register, offset: 0x118 */ + __I uint32_t PPI_ERRSOTSYNC_HS; /**< ErrSotSync HS Status Register, offset: 0x11C */ + __I uint32_t PPI_ERRESC; /**< ErrEsc Status Register, offset: 0x120 */ + __I uint32_t PPI_ERRSYNCESC; /**< ErrSyncEsc Status Register, offset: 0x124 */ + __I uint32_t PPI_ERRCONTROL; /**< ErrControl Status Register, offset: 0x128 */ + __IO uint32_t CFG_DISABLE_PAYLOAD_0; /**< Disable Payload 0 Register, offset: 0x12C */ + __IO uint32_t CFG_DISABLE_PAYLOAD_1; /**< Disable Payload 1 Register, offset: 0x130 */ + uint8_t RESERVED_1[76]; + __IO uint32_t CFG_IGNORE_VC; /**< Ignore Virtual Channel Register, offset: 0x180 */ + __IO uint32_t CFG_VID_VC; /**< Virtual Channel value Register, offset: 0x184 */ + __IO uint32_t CFG_VID_P_FIFO_SEND_LEVEL; /**< FIFO Send Level Configuration Register, offset: 0x188 */ + __IO uint32_t CFG_VID_VSYNC; /**< VSYNC Configuration Register, offset: 0x18C */ + __IO uint32_t CFG_VID_HSYNC_FP; /**< Start of HSYNC Delay control Register, offset: 0x190 */ + __IO uint32_t CFG_VID_HSYNC; /**< HSYNC Configuration Register, offset: 0x194 */ + __IO uint32_t CFG_VID_HSYNC_BP; /**< End of HSYNC Delay Control Register, offset: 0x198 */ } MIPI_CSI2RX_Type; /* ---------------------------------------------------------------------------- @@ -63144,192 +73432,305 @@ typedef struct { * @{ */ -/*! @name CSI2RX_CFG_NUM_LANES - */ +/*! @name CFG_NUM_LANES - Lane Configuration Register */ /*! @{ */ -#define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_MASK (0x3U) -#define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_SHIFT (0U) -/*! csi2rx_cfg_num_lanes - Sets the number of active lanes that are to be used for receiving data. - * 2'b00 - 1 Lane 2'b01 - 2 Lanes 2'b10 - 3 Lanes 2'b11 - 4 Lanes - */ -#define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_MASK) -#define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_reserved_MASK (0xFFFFFFFCU) -#define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_reserved_SHIFT (2U) -/*! reserved - reserved + +#define MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_MASK (0x3U) +#define MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_SHIFT (0U) +/*! CFG_NUM_LANES - This field is used to set the number of active lanes for receiving data. + * 0b00..1 Lane + * 0b01..2 Lane + * 0b10-0b11..Reserved */ -#define MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_reserved_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_reserved_MASK) +#define MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_SHIFT)) & MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_MASK) /*! @} */ -/*! @name CSI2RX_CFG_DISABLE_DATA_LANES - */ +/*! @name CFG_DISABLE_DATA_LANES - Disable Data Lane Register */ /*! @{ */ -#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes_MASK (0xFU) -#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes_SHIFT (0U) -/*! csi2rx_cfg_disable_data_lanes - Forces DPHY Enable_n signals to 1'b0 when register is set to 1. - * See the CSI-2 Controller User Guide description of the input port cfg_disable_data_lanes for - * additional information. - */ -#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_csi2rx_cfg_disable_data_lanes_MASK) -#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_reserved_MASK (0xFFFFFFF0U) -#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_reserved_SHIFT (4U) -/*! reserved - reserved + +#define MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_MASK (0xFU) +#define MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_SHIFT (0U) +/*! CFG_DISABLE_DATA_LANES - This field is used to disable data lanes. */ -#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_reserved_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_DATA_LANES_reserved_MASK) +#define MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_MASK) /*! @} */ -/*! @name CSI2RX_BIT_ERR - */ +/*! @name BIT_ERR - ECC and CRC Error Status Register */ /*! @{ */ -#define MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err_MASK (0x3FFU) -#define MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err_SHIFT (0U) -/*! csi2rx_bit_err - Captures the first Status event when either a one or two bit error occurs, with - * only the one bit error providing position information. 7'b000_0000 - No Error event captured - * 7'bxxx_xxx1 - Two Bit Error event captured 7'bxxx_xx10 - One Bit Error event captured with the - * bit position contained in the upper bits - */ -#define MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err_SHIFT)) & MIPI_CSI2RX_CSI2RX_BIT_ERR_csi2rx_bit_err_MASK) -#define MIPI_CSI2RX_CSI2RX_BIT_ERR_reserved_MASK (0xFFFFFC00U) -#define MIPI_CSI2RX_CSI2RX_BIT_ERR_reserved_SHIFT (10U) -/*! reserved - reserved + +#define MIPI_CSI2RX_BIT_ERR_BIT_ERR_MASK (0x3FFU) +#define MIPI_CSI2RX_BIT_ERR_BIT_ERR_SHIFT (0U) +/*! BIT_ERR - This field shows the error status of ECC and CRC */ -#define MIPI_CSI2RX_CSI2RX_BIT_ERR_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_BIT_ERR_reserved_SHIFT)) & MIPI_CSI2RX_CSI2RX_BIT_ERR_reserved_MASK) +#define MIPI_CSI2RX_BIT_ERR_BIT_ERR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_BIT_ERR_BIT_ERR_SHIFT)) & MIPI_CSI2RX_BIT_ERR_BIT_ERR_MASK) /*! @} */ -/*! @name CSI2RX_IRQ_STATUS - */ +/*! @name IRQ_STATUS - IRQ Status Register */ /*! @{ */ -#define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status_MASK (0x1FFU) -#define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status_SHIFT (0U) -/*! csi2rx_irq_status - CSI2 RX IRQ status. See CSI-2 Controller User Guice description for additional information. - */ -#define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status_SHIFT)) & MIPI_CSI2RX_CSI2RX_IRQ_STATUS_csi2rx_irq_status_MASK) -#define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_reserved_MASK (0xFFFFFE00U) -#define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_reserved_SHIFT (9U) -/*! reserved - reserved + +#define MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS_MASK (0x1FFU) +#define MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS_SHIFT (0U) +/*! IRQ_STATUS - This field shows the IRQ status */ -#define MIPI_CSI2RX_CSI2RX_IRQ_STATUS_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_IRQ_STATUS_reserved_SHIFT)) & MIPI_CSI2RX_CSI2RX_IRQ_STATUS_reserved_MASK) +#define MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS_SHIFT)) & MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS_MASK) /*! @} */ -/*! @name CSI2RX_IRQ_MASK - */ +/*! @name IRQ_MASK - IRQ Mask Setting Register */ /*! @{ */ -#define MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_MASK (0x1FFU) -#define MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_SHIFT (0U) -/*! csi2rx_irq_mask - CSI2 RX IRQ Mask. See CSI-2 Controller User Guice description for additional information. - */ -#define MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_SHIFT)) & MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_MASK) -#define MIPI_CSI2RX_CSI2RX_IRQ_MASK_reserved_MASK (0xFFFFFE00U) -#define MIPI_CSI2RX_CSI2RX_IRQ_MASK_reserved_SHIFT (9U) -/*! reserved - reserved + +#define MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_MASK (0x1FFU) +#define MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_SHIFT (0U) +/*! IRQ_MASK - This field shows the IRQ Mask setting */ -#define MIPI_CSI2RX_CSI2RX_IRQ_MASK_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_IRQ_MASK_reserved_SHIFT)) & MIPI_CSI2RX_CSI2RX_IRQ_MASK_reserved_MASK) +#define MIPI_CSI2RX_IRQ_MASK_IRQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_SHIFT)) & MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_MASK) /*! @} */ -/*! @name CSI2RX_ULPS_STATUS - */ +/*! @name ULPS_STATUS - Ultra Low Power State (ULPS) Status Register */ /*! @{ */ -#define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status_MASK (0x3FFU) -#define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status_SHIFT (0U) -/*! csi2rx_ulps_status - CSI2 RX ULPS status. See CSI-2 Controller User Guice description for additional information. + +#define MIPI_CSI2RX_ULPS_STATUS_STATUS_MASK (0x3FFU) +#define MIPI_CSI2RX_ULPS_STATUS_STATUS_SHIFT (0U) +/*! STATUS - This field shows the status of Rx D-PHY ULPS state */ -#define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status_SHIFT)) & MIPI_CSI2RX_CSI2RX_ULPS_STATUS_csi2rx_ulps_status_MASK) -#define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_reserved_MASK (0xFFFFFC00U) -#define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_reserved_SHIFT (10U) -/*! reserved - reserved +#define MIPI_CSI2RX_ULPS_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_ULPS_STATUS_STATUS_SHIFT)) & MIPI_CSI2RX_ULPS_STATUS_STATUS_MASK) +/*! @} */ + +/*! @name PPI_ERRSOT_HS - ERRSot HS Status Register */ +/*! @{ */ + +#define MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS_MASK (0xFU) +#define MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS_SHIFT (0U) +/*! STATUS - This field indicates PPI ErrSotHS captured status from D-PHY */ -#define MIPI_CSI2RX_CSI2RX_ULPS_STATUS_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_ULPS_STATUS_reserved_SHIFT)) & MIPI_CSI2RX_CSI2RX_ULPS_STATUS_reserved_MASK) +#define MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS_MASK) /*! @} */ -/*! @name CSI2RX_PPI_ERRSOT_HS - */ +/*! @name PPI_ERRSOTSYNC_HS - ErrSotSync HS Status Register */ /*! @{ */ -#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs_MASK (0xFU) -#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs_SHIFT (0U) -/*! csi2rx_ppi_errsot_hs - CSI2 RX DPHY PPI ErrSotHS captured status from the DPHY. See CSI-2 - * Controller User Guice description for additional information. + +#define MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_MASK (0xFU) +#define MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_SHIFT (0U) +/*! STATUS - This field indicates PPI ErrSotSync_HS captured status from D-PHY */ -#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_csi2rx_ppi_errsot_hs_MASK) -#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_reserved_MASK (0xFFFFFFF0U) -#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_reserved_SHIFT (4U) -/*! reserved - reserved +#define MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_MASK) +/*! @} */ + +/*! @name PPI_ERRESC - ErrEsc Status Register */ +/*! @{ */ + +#define MIPI_CSI2RX_PPI_ERRESC_STATUS_MASK (0xFU) +#define MIPI_CSI2RX_PPI_ERRESC_STATUS_SHIFT (0U) +/*! STATUS - This field indicates PPI ErrEsc captured status from D-PHY */ -#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_reserved_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRSOT_HS_reserved_MASK) +#define MIPI_CSI2RX_PPI_ERRESC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRESC_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRESC_STATUS_MASK) /*! @} */ -/*! @name CSI2RX_PPI_ERRSOTSYNC_HS - */ +/*! @name PPI_ERRSYNCESC - ErrSyncEsc Status Register */ /*! @{ */ -#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs_MASK (0xFU) -#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs_SHIFT (0U) -/*! csi2rx_ppi_errsotsync_hs - CSI2 RX DPHY PPI ErrSotSync_HS captured status from the DPHY. See - * CSI-2 Controller User Guice description for additional information. + +#define MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS_MASK (0xFU) +#define MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS_SHIFT (0U) +/*! STATUS - This field indicates PPI ErrSyncEsc captured status from D-PHY */ -#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_csi2rx_ppi_errsotsync_hs_MASK) -#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_reserved_MASK (0xFFFFFFF0U) -#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_reserved_SHIFT (4U) -/*! reserved - reserved +#define MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS_MASK) +/*! @} */ + +/*! @name PPI_ERRCONTROL - ErrControl Status Register */ +/*! @{ */ + +#define MIPI_CSI2RX_PPI_ERRCONTROL_STATUS_MASK (0xFU) +#define MIPI_CSI2RX_PPI_ERRCONTROL_STATUS_SHIFT (0U) +/*! STATUS - This field indicates PPI ErrControl captured status from D-PHY */ -#define MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_reserved_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRSOTSYNC_HS_reserved_MASK) +#define MIPI_CSI2RX_PPI_ERRCONTROL_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRCONTROL_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRCONTROL_STATUS_MASK) /*! @} */ -/*! @name CSI2RX_PPI_ERRESC - */ +/*! @name CFG_DISABLE_PAYLOAD_0 - Disable Payload 0 Register */ /*! @{ */ -#define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc_MASK (0xFU) -#define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc_SHIFT (0U) -/*! csi2rx_ppi_erresc - CSI2 RX DPHY PPI ErrEsc captured status from the DPHY. See CSI-2 Controller - * User Guice description for additional information. + +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_MASK (0x1U) +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_SHIFT (0U) +/*! DIS_PAYLOAD_NULL - Null + */ +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_MASK) + +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_MASK (0x2U) +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_SHIFT (1U) +/*! DIS_PAYLOAD_BLANK - Blank + */ +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_MASK) + +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_MASK (0x4U) +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_SHIFT (2U) +/*! DIS_PAYLOAD_EMBEDDED - Embedded + */ +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_MASK) + +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_MASK (0x400U) +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_SHIFT (10U) +/*! DIS_PAYLOAD_YUV420 - Legacy YUV 420 8 bit + */ +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_MASK) + +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_MASK (0x4000U) +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_SHIFT (14U) +/*! DIS_PAYLOAD_YUV422_8BIT - YUV422 8 bit + */ +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_MASK) + +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_MASK (0x10000U) +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_SHIFT (16U) +/*! DIS_PAYLOAD_RGB444 - RGB444 + */ +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_MASK) + +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_MASK (0x20000U) +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_SHIFT (17U) +/*! DIS_PAYLOAD_RGB555 - RGB555 + */ +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_MASK) + +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_MASK (0x40000U) +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_SHIFT (18U) +/*! DIS_PAYLOAD_RGB565 - RGB565 + */ +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_MASK) + +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_MASK (0x80000U) +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_SHIFT (19U) +/*! DIS_PAYLOAD_RGB666 - RGB666 */ -#define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRESC_csi2rx_ppi_erresc_MASK) -#define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_reserved_MASK (0xFFFFFFF0U) -#define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_reserved_SHIFT (4U) -/*! reserved - reserved +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_MASK) + +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_MASK (0x100000U) +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_SHIFT (20U) +/*! DIS_PAYLOAD_RGB888 - RGB888 */ -#define MIPI_CSI2RX_CSI2RX_PPI_ERRESC_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRESC_reserved_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRESC_reserved_MASK) +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_MASK) /*! @} */ -/*! @name CSI2RX_PPI_ERRSYNCESC - */ +/*! @name CFG_DISABLE_PAYLOAD_1 - Disable Payload 1 Register */ /*! @{ */ -#define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc_MASK (0xFU) -#define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc_SHIFT (0U) -/*! csi2rx_ppi_errsyncesc - CSI2 RX DPHY PPI ErrSyncEsc captured status from the DPHY. See CSI-2 - * Controller User Guice description for additional information. + +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_MASK (0x1U) +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_SHIFT (0U) +/*! DIS_PAYLOAD_UDEF_30 - User defined type 0x31 + */ +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_MASK) + +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_MASK (0x2U) +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_SHIFT (1U) +/*! DIS_PAYLOAD_UDEF_31 - User defined type 0x32 + */ +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_MASK) + +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_MASK (0x4U) +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_SHIFT (2U) +/*! DIS_PAYLOAD_UDEF_32 - User defined type 0x33 + */ +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_MASK) + +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_MASK (0x8U) +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_SHIFT (3U) +/*! DIS_PAYLOAD_UDEF_33 - User defined type 0x34 + */ +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_MASK) + +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_MASK (0x10U) +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_SHIFT (4U) +/*! DIS_PAYLOAD_UDEF_34 - User defined type 0x35 + */ +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_MASK) + +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_MASK (0x20U) +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_SHIFT (5U) +/*! DIS_PAYLOAD_UDEF_35 - User defined type 0x35 + */ +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_MASK) + +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_MASK (0x40U) +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_SHIFT (6U) +/*! DIS_PAYLOAD_UDEF_36 - User defined type 0x36 + */ +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_MASK) + +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_MASK (0x80U) +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_SHIFT (7U) +/*! DIS_PAYLOAD_UDEF_37 - User defined type 0x37 */ -#define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_csi2rx_ppi_errsyncesc_MASK) -#define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_reserved_MASK (0xFFFFFFF0U) -#define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_reserved_SHIFT (4U) -/*! reserved - reserved +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_MASK) + +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_MASK (0x10000U) +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_SHIFT (16U) +/*! DIS_PAYLOAD_UNSUPPORTED - Unsupported Data Types */ -#define MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_reserved_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRSYNCESC_reserved_MASK) +#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_MASK) +/*! @} */ + +/*! @name CFG_IGNORE_VC - Ignore Virtual Channel Register */ +/*! @{ */ + +#define MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_MASK (0x1U) +#define MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_SHIFT (0U) +#define MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_SHIFT)) & MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_MASK) +/*! @} */ + +/*! @name CFG_VID_VC - Virtual Channel value Register */ +/*! @{ */ + +#define MIPI_CSI2RX_CFG_VID_VC_VID_VC_MASK (0x3U) +#define MIPI_CSI2RX_CFG_VID_VC_VID_VC_SHIFT (0U) +#define MIPI_CSI2RX_CFG_VID_VC_VID_VC(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_VC_VID_VC_SHIFT)) & MIPI_CSI2RX_CFG_VID_VC_VID_VC_MASK) /*! @} */ -/*! @name CSI2RX_PPI_ERRCONTROL - */ +/*! @name CFG_VID_P_FIFO_SEND_LEVEL - FIFO Send Level Configuration Register */ /*! @{ */ -#define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol_MASK (0xFU) -#define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol_SHIFT (0U) -/*! csi2rx_ppi_errcontrol - CSI2 RX DPHY PPI ErrControl captured status from the DPHY. See CSI-2 - * Controller User Guice description for additional information. + +#define MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_MASK (0xFFFFU) +#define MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_SHIFT (0U) +/*! SEND_LEVEL - FIFO Send Level field */ -#define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_csi2rx_ppi_errcontrol_MASK) -#define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_reserved_MASK (0xFFFFFFF0U) -#define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_reserved_SHIFT (4U) -/*! reserved - reserved +#define MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_SHIFT)) & MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_MASK) +/*! @} */ + +/*! @name CFG_VID_VSYNC - VSYNC Configuration Register */ +/*! @{ */ + +#define MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH_MASK (0xFFU) +#define MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH_SHIFT (0U) +/*! WIDTH - Width of VSYNC */ -#define MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_reserved_SHIFT)) & MIPI_CSI2RX_CSI2RX_PPI_ERRCONTROL_reserved_MASK) +#define MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH_SHIFT)) & MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH_MASK) /*! @} */ -/*! @name CSI2RX_CFG_DISABLE_PAYLOAD_0 - */ +/*! @name CFG_VID_HSYNC_FP - Start of HSYNC Delay control Register */ /*! @{ */ -#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_0_MASK (0xFFFFFFFFU) -#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_0_SHIFT (0U) -/*! csi2rx_cfg_disable_payload_0 - CSI2 RX Controller cfg_diable_payload. See CSI-2 Controller User Guice description for additional information. + +#define MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_MASK (0xFFU) +#define MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_SHIFT (0U) +/*! DELAY_CTL - Delay control for beginning of HSYNC pulse */ -#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_0(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_0_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_0_csi2rx_cfg_disable_payload_0_MASK) +#define MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_SHIFT)) & MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_MASK) /*! @} */ -/*! @name CSI2RX_CFG_DISABLE_PAYLOAD_1 - */ +/*! @name CFG_VID_HSYNC - HSYNC Configuration Register */ /*! @{ */ -#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_1_MASK (0x1FFFFU) -#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_1_SHIFT (0U) -/*! csi2rx_cfg_disable_payload_1 - CSI2 RX Controller cfg_diable_payload. See CSI-2 Controller User Guice description for additional information. + +#define MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH_MASK (0xFFU) +#define MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH_SHIFT (0U) +/*! WIDTH - Width of HSYNC */ -#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_1(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_1_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_csi2rx_cfg_disable_payload_1_MASK) -#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_reserved_MASK (0xFFFE0000U) -#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_reserved_SHIFT (17U) -/*! reserved - reserved +#define MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH_SHIFT)) & MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH_MASK) +/*! @} */ + +/*! @name CFG_VID_HSYNC_BP - End of HSYNC Delay Control Register */ +/*! @{ */ + +#define MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_MASK (0xFFU) +#define MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_SHIFT (0U) +/*! DELAY_CTL - Delay Control for end of HSYNC pulse */ -#define MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_reserved(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_reserved_SHIFT)) & MIPI_CSI2RX_CSI2RX_CFG_DISABLE_PAYLOAD_1_reserved_MASK) +#define MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_SHIFT)) & MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_MASK) /*! @} */ @@ -63381,6 +73782,7 @@ typedef struct { /*! @name TR - Processor A Transmit Register 0..Processor A Transmit Register 3 */ /*! @{ */ + #define MU_TR_DATA_MASK (0xFFFFFFFFU) #define MU_TR_DATA_SHIFT (0U) /*! DATA - TR3 @@ -63393,6 +73795,7 @@ typedef struct { /*! @name RR - Processor A Receive Register 0..Processor A Receive Register 3 */ /*! @{ */ + #define MU_RR_DATA_MASK (0xFFFFFFFFU) #define MU_RR_DATA_SHIFT (0U) /*! DATA - RR3 @@ -63405,6 +73808,7 @@ typedef struct { /*! @name SR - Processor A Status Register */ /*! @{ */ + #define MU_SR_Fn_MASK (0x7U) #define MU_SR_Fn_SHIFT (0U) /*! Fn - Fn @@ -63412,6 +73816,7 @@ typedef struct { * 0b001..BAFn bit in MUB.CR register is written 1. */ #define MU_SR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_Fn_SHIFT)) & MU_SR_Fn_MASK) + #define MU_SR_EP_MASK (0x10U) #define MU_SR_EP_SHIFT (4U) /*! EP - EP @@ -63419,6 +73824,7 @@ typedef struct { * 0b1..The Processor A-side event is pending. */ #define MU_SR_EP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK) + #define MU_SR_RS_MASK (0x80U) #define MU_SR_RS_SHIFT (7U) /*! RS - RS @@ -63426,6 +73832,7 @@ typedef struct { * 0b1..The Processor B-side of the MU is in reset. */ #define MU_SR_RS(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RS_SHIFT)) & MU_SR_RS_MASK) + #define MU_SR_FUP_MASK (0x100U) #define MU_SR_FUP_SHIFT (8U) /*! FUP - FUP @@ -63433,13 +73840,7 @@ typedef struct { * 0b1..Processor A initiated flags update, processing */ #define MU_SR_FUP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK) -#define MU_SR_RDIP_MASK (0x200U) -#define MU_SR_RDIP_SHIFT (9U) -/*! RDIP - RDIP - * 0b0..The Processor A general purpose interrupt 3, because of a Processor B-side reset de-assertion, is cleared (default). - * 0b1..The Processor B-side is out of reset. - */ -#define MU_SR_RDIP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RDIP_SHIFT)) & MU_SR_RDIP_MASK) + #define MU_SR_TEn_MASK (0xF00000U) #define MU_SR_TEn_SHIFT (20U) /*! TEn - TEn @@ -63447,6 +73848,7 @@ typedef struct { * 0b0001..MUA.TRn register is empty (default). */ #define MU_SR_TEn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_TEn_SHIFT)) & MU_SR_TEn_MASK) + #define MU_SR_RFn_MASK (0xF000000U) #define MU_SR_RFn_SHIFT (24U) /*! RFn - RFn @@ -63454,6 +73856,7 @@ typedef struct { * 0b0001..MUA.RRn register has received data from MUB.TRn register and is ready to be read by the Processor A. */ #define MU_SR_RFn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK) + #define MU_SR_GIPn_MASK (0xF0000000U) #define MU_SR_GIPn_SHIFT (28U) /*! GIPn - GIPn @@ -63465,6 +73868,7 @@ typedef struct { /*! @name CR - Processor A Control Register */ /*! @{ */ + #define MU_CR_Fn_MASK (0x7U) #define MU_CR_Fn_SHIFT (0U) /*! Fn - Fn @@ -63472,13 +73876,7 @@ typedef struct { * 0b001..Asserts the Processor A MU reset. */ #define MU_CR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_Fn_SHIFT)) & MU_CR_Fn_MASK) -#define MU_CR_HR_MASK (0x10U) -#define MU_CR_HR_SHIFT (4U) -/*! HR - HR - * 0b0..De-assert Hardware reset to the Processor B. (default) - * 0b1..Assert Hardware reset to the Processor B. - */ -#define MU_CR_HR(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_HR_SHIFT)) & MU_CR_HR_MASK) + #define MU_CR_MUR_MASK (0x20U) #define MU_CR_MUR_SHIFT (5U) /*! MUR - MUR @@ -63486,15 +73884,7 @@ typedef struct { * 0b1..Asserts the Processor A MU reset. */ #define MU_CR_MUR(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK) -#define MU_CR_RDIE_MASK (0x40U) -#define MU_CR_RDIE_SHIFT (6U) -/*! RDIE - RDIE - * 0b0..Disables the Processor A General Purpose Interrupt 3 request due to the Processor B reset de-assertion to - * the Processor A. Processor B reset deassertion causes Processor B and MU-Processor B side to come out of - * reset thus setting RDIP bit to "1". - * 0b1..Enables Processor A General Purpose Interrupt 3 request due to the Processor B reset de-assertion to the Processor A. - */ -#define MU_CR_RDIE(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_RDIE_SHIFT)) & MU_CR_RDIE_MASK) + #define MU_CR_GIRn_MASK (0xF0000U) #define MU_CR_GIRn_SHIFT (16U) /*! GIRn - GIRn @@ -63502,6 +73892,7 @@ typedef struct { * 0b0001..Processor A General Interrupt n is requested to the Processor B. */ #define MU_CR_GIRn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK) + #define MU_CR_TIEn_MASK (0xF00000U) #define MU_CR_TIEn_SHIFT (20U) /*! TIEn - TIEn @@ -63509,6 +73900,7 @@ typedef struct { * 0b0001..Enables Processor A Transmit Interrupt n. */ #define MU_CR_TIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_TIEn_SHIFT)) & MU_CR_TIEn_MASK) + #define MU_CR_RIEn_MASK (0xF000000U) #define MU_CR_RIEn_SHIFT (24U) /*! RIEn - RIEn @@ -63516,6 +73908,7 @@ typedef struct { * 0b0001..Enables Processor A Receive Interrupt n. */ #define MU_CR_RIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_RIEn_SHIFT)) & MU_CR_RIEn_MASK) + #define MU_CR_GIEn_MASK (0xF0000000U) #define MU_CR_GIEn_SHIFT (28U) /*! GIEn - GIEn @@ -63559,334 +73952,45 @@ typedef struct { /** OCOTP - Register Layout Typedef */ typedef struct { - __IO uint32_t CTRL; /**< OTP Controller Control Register, offset: 0x0 */ - __IO uint32_t CTRL_SET; /**< OTP Controller Control Register, offset: 0x4 */ - __IO uint32_t CTRL_CLR; /**< OTP Controller Control Register, offset: 0x8 */ - __IO uint32_t CTRL_TOG; /**< OTP Controller Control Register, offset: 0xC */ + __IO uint32_t CTRL; /**< OTP Controller Control and Status Register, offset: 0x0 */ + __IO uint32_t CTRL_SET; /**< OTP Controller Control and Status Register, offset: 0x4 */ + __IO uint32_t CTRL_CLR; /**< OTP Controller Control and Status Register, offset: 0x8 */ + __IO uint32_t CTRL_TOG; /**< OTP Controller Control and Status Register, offset: 0xC */ __IO uint32_t PDN; /**< OTP Controller PDN Register, offset: 0x10 */ uint8_t RESERVED_0[12]; __IO uint32_t DATA; /**< OTP Controller Write Data Register, offset: 0x20 */ uint8_t RESERVED_1[12]; - __IO uint32_t READ_CTRL; /**< OTP Controller Write Data Register, offset: 0x30 */ - uint8_t RESERVED_2[44]; - __IO uint32_t SCS; /**< Software Controllable Signals Register, offset: 0x60 */ - __IO uint32_t SCS_SET; /**< Software Controllable Signals Register, offset: 0x64 */ - __IO uint32_t SCS_CLR; /**< Software Controllable Signals Register, offset: 0x68 */ - __IO uint32_t SCS_TOG; /**< Software Controllable Signals Register, offset: 0x6C */ - uint8_t RESERVED_3[32]; - __IO uint32_t OUT_STATUS0; /**< 8K OTP Memory STATUS Register, offset: 0x90 */ - __IO uint32_t OUT_STATUS0_SET; /**< 8K OTP Memory STATUS Register, offset: 0x94 */ - __IO uint32_t OUT_STATUS0_CLR; /**< 8K OTP Memory STATUS Register, offset: 0x98 */ - __IO uint32_t OUT_STATUS0_TOG; /**< 8K OTP Memory STATUS Register, offset: 0x9C */ - __I uint32_t STARTWORD0; /**< 8K OTP memory Startword Register, offset: 0xA0 */ - uint8_t RESERVED_4[12]; + __IO uint32_t READ_CTRL; /**< OTP Controller Read Control Register, offset: 0x30 */ + uint8_t RESERVED_2[92]; + __IO uint32_t OUT_STATUS; /**< 8K OTP Memory STATUS Register, offset: 0x90 */ + __IO uint32_t OUT_STATUS_SET; /**< 8K OTP Memory STATUS Register, offset: 0x94 */ + __IO uint32_t OUT_STATUS_CLR; /**< 8K OTP Memory STATUS Register, offset: 0x98 */ + __IO uint32_t OUT_STATUS_TOG; /**< 8K OTP Memory STATUS Register, offset: 0x9C */ + uint8_t RESERVED_3[16]; __I uint32_t VERSION; /**< OTP Controller Version Register, offset: 0xB0 */ - uint8_t RESERVED_5[76]; + uint8_t RESERVED_4[76]; struct { /* offset: 0x100, array step: 0x10 */ - __IO uint32_t READ_FUSE_DATA; /**< , array offset: 0x100, array step: 0x10 */ + __IO uint32_t READ_FUSE_DATA; /**< OTP Controller Read Data 0 Register..OTP Controller Read Data 3 Register, array offset: 0x100, array step: 0x10 */ uint8_t RESERVED_0[12]; } READ_FUSE_DATAS[4]; - __IO uint32_t SW_LOCK; /**< , offset: 0x140 */ - uint8_t RESERVED_6[12]; - __IO uint32_t BIT_LOCK; /**< , offset: 0x150 */ - uint8_t RESERVED_7[1196]; - __I uint32_t LOCKED0; /**< OTP Controller Program Locked Status Register, offset: 0x600 */ + __IO uint32_t SW_LOCK; /**< SW_LOCK Register, offset: 0x140 */ + uint8_t RESERVED_5[12]; + __IO uint32_t BIT_LOCK; /**< BIT_LOCK Register, offset: 0x150 */ + uint8_t RESERVED_6[1196]; + __I uint32_t LOCKED0; /**< OTP Controller Program Locked Status 0 Register, offset: 0x600 */ + uint8_t RESERVED_7[12]; + __I uint32_t LOCKED1; /**< OTP Controller Program Locked Status 1 Register, offset: 0x610 */ uint8_t RESERVED_8[12]; - __I uint32_t LOCKED1; /**< OTP Controller Program Locked Status Register, offset: 0x610 */ + __I uint32_t LOCKED2; /**< OTP Controller Program Locked Status 2 Register, offset: 0x620 */ uint8_t RESERVED_9[12]; - __I uint32_t LOCKED2; /**< OTP Controller Program Locked Status Register, offset: 0x620 */ + __I uint32_t LOCKED3; /**< OTP Controller Program Locked Status 3 Register, offset: 0x630 */ uint8_t RESERVED_10[12]; - __I uint32_t LOCKED3; /**< OTP Controller Program Locked Status Register, offset: 0x630 */ - uint8_t RESERVED_11[12]; - __I uint32_t LOCKED4; /**< OTP Controller Program Locked Status Register, offset: 0x640 */ - uint8_t RESERVED_12[444]; - __IO uint32_t FUSE000; /**< Value of fuse word 0, offset: 0x800 */ - uint8_t RESERVED_13[12]; - __IO uint32_t FUSE001; /**< Value of fuse word 1, offset: 0x810 */ - uint8_t RESERVED_14[12]; - __IO uint32_t FUSE002; /**< Value of fuse word 2, offset: 0x820 */ - uint8_t RESERVED_15[12]; - __IO uint32_t FUSE003; /**< Value of fuse word 3, offset: 0x830 */ - uint8_t RESERVED_16[12]; - __IO uint32_t FUSE004; /**< Value of fuse word 4, offset: 0x840 */ - uint8_t RESERVED_17[12]; - __IO uint32_t FUSE005; /**< Value of fuse word 5, offset: 0x850 */ - uint8_t RESERVED_18[12]; - __IO uint32_t FUSE006; /**< Value of fuse word 6, offset: 0x860 */ - uint8_t RESERVED_19[12]; - __IO uint32_t FUSE007; /**< Value of fuse word 7, offset: 0x870 */ - uint8_t RESERVED_20[12]; - __IO uint32_t FUSE008; /**< Value of fuse word 8, offset: 0x880 */ - uint8_t RESERVED_21[12]; - __IO uint32_t FUSE009; /**< Value of fuse word 9, offset: 0x890 */ - uint8_t RESERVED_22[12]; - __IO uint32_t FUSE010; /**< Value of fuse word 10, offset: 0x8A0 */ - uint8_t RESERVED_23[12]; - __IO uint32_t FUSE011; /**< Value of fuse word 11, offset: 0x8B0 */ - uint8_t RESERVED_24[12]; - __IO uint32_t FUSE012; /**< Value of fuse word 12, offset: 0x8C0 */ - uint8_t RESERVED_25[12]; - __IO uint32_t FUSE013; /**< Value of fuse word 13, offset: 0x8D0 */ - uint8_t RESERVED_26[12]; - __IO uint32_t FUSE014; /**< Value of fuse word 14, offset: 0x8E0 */ - uint8_t RESERVED_27[12]; - __IO uint32_t FUSE015; /**< Value of fuse word 15, offset: 0x8F0 */ - uint8_t RESERVED_28[12]; - __IO uint32_t FUSE016; /**< Value of fuse word 16, offset: 0x900 */ - uint8_t RESERVED_29[12]; - __IO uint32_t FUSE017; /**< Value of fuse word 17, offset: 0x910 */ - uint8_t RESERVED_30[12]; - __IO uint32_t FUSE018; /**< Value of fuse word 18, offset: 0x920 */ - uint8_t RESERVED_31[12]; - __IO uint32_t FUSE019; /**< Value of fuse word 19, offset: 0x930 */ - uint8_t RESERVED_32[12]; - __IO uint32_t FUSE020; /**< Value of fuse word 20, offset: 0x940 */ - uint8_t RESERVED_33[12]; - __IO uint32_t FUSE021; /**< Value of fuse word 21, offset: 0x950 */ - uint8_t RESERVED_34[12]; - __IO uint32_t FUSE022; /**< Value of fuse word 22, offset: 0x960 */ - uint8_t RESERVED_35[12]; - __IO uint32_t FUSE023; /**< Value of fuse word 23, offset: 0x970 */ - uint8_t RESERVED_36[12]; - __IO uint32_t FUSE024; /**< Value of fuse word 24, offset: 0x980 */ - uint8_t RESERVED_37[12]; - __IO uint32_t FUSE025; /**< Value of fuse word 25, offset: 0x990 */ - uint8_t RESERVED_38[12]; - __IO uint32_t FUSE026; /**< Value of fuse word 26, offset: 0x9A0 */ - uint8_t RESERVED_39[12]; - __IO uint32_t FUSE027; /**< Value of fuse word 27, offset: 0x9B0 */ - uint8_t RESERVED_40[12]; - __IO uint32_t FUSE028; /**< Value of fuse word 28, offset: 0x9C0 */ - uint8_t RESERVED_41[12]; - __IO uint32_t FUSE029; /**< Value of fuse word 29, offset: 0x9D0 */ - uint8_t RESERVED_42[12]; - __IO uint32_t FUSE030; /**< Value of fuse word 30, offset: 0x9E0 */ - uint8_t RESERVED_43[12]; - __IO uint32_t FUSE031; /**< Value of fuse word 31, offset: 0x9F0 */ - uint8_t RESERVED_44[12]; - __IO uint32_t FUSE032; /**< Value of fuse word 32, offset: 0xA00 */ - uint8_t RESERVED_45[12]; - __IO uint32_t FUSE033; /**< Value of fuse word 33, offset: 0xA10 */ - uint8_t RESERVED_46[12]; - __IO uint32_t FUSE034; /**< Value of fuse word 34, offset: 0xA20 */ - uint8_t RESERVED_47[12]; - __IO uint32_t FUSE035; /**< Value of fuse word 35, offset: 0xA30 */ - uint8_t RESERVED_48[12]; - __IO uint32_t FUSE036; /**< Value of fuse word 36, offset: 0xA40 */ - uint8_t RESERVED_49[12]; - __IO uint32_t FUSE037; /**< Value of fuse word 37, offset: 0xA50 */ - uint8_t RESERVED_50[12]; - __IO uint32_t FUSE038; /**< Value of fuse word 38, offset: 0xA60 */ - uint8_t RESERVED_51[12]; - __IO uint32_t FUSE039; /**< Value of fuse word 39, offset: 0xA70 */ - uint8_t RESERVED_52[12]; - __IO uint32_t FUSE040; /**< Value of fuse word 40, offset: 0xA80 */ - uint8_t RESERVED_53[12]; - __IO uint32_t FUSE041; /**< Value of fuse word 41, offset: 0xA90 */ - uint8_t RESERVED_54[12]; - __IO uint32_t FUSE042; /**< Value of fuse word 42, offset: 0xAA0 */ - uint8_t RESERVED_55[12]; - __IO uint32_t FUSE043; /**< Value of fuse word 43, offset: 0xAB0 */ - uint8_t RESERVED_56[12]; - __IO uint32_t FUSE044; /**< Value of fuse word 44, offset: 0xAC0 */ - uint8_t RESERVED_57[12]; - __IO uint32_t FUSE045; /**< Value of fuse word 45, offset: 0xAD0 */ - uint8_t RESERVED_58[12]; - __IO uint32_t FUSE046; /**< Value of fuse word 46, offset: 0xAE0 */ - uint8_t RESERVED_59[12]; - __IO uint32_t FUSE047; /**< Value of fuse word 47, offset: 0xAF0 */ - uint8_t RESERVED_60[12]; - __IO uint32_t FUSE048; /**< Value of fuse word 47, offset: 0xB00 */ - uint8_t RESERVED_61[12]; - __IO uint32_t FUSE049; /**< Value of fuse word 49, offset: 0xB10 */ - uint8_t RESERVED_62[12]; - __IO uint32_t FUSE050; /**< Value of fuse word 50, offset: 0xB20 */ - uint8_t RESERVED_63[12]; - __IO uint32_t FUSE051; /**< Value of fuse word 51, offset: 0xB30 */ - uint8_t RESERVED_64[12]; - __IO uint32_t FUSE052; /**< Value of fuse word 52, offset: 0xB40 */ - uint8_t RESERVED_65[12]; - __IO uint32_t FUSE053; /**< Value of fuse word 53, offset: 0xB50 */ - uint8_t RESERVED_66[12]; - __IO uint32_t FUSE054; /**< Value of fuse word 54, offset: 0xB60 */ - uint8_t RESERVED_67[12]; - __IO uint32_t FUSE055; /**< Value of fuse word 55, offset: 0xB70 */ - uint8_t RESERVED_68[12]; - __IO uint32_t FUSE056; /**< Value of fuse word 56, offset: 0xB80 */ - uint8_t RESERVED_69[12]; - __IO uint32_t FUSE057; /**< Value of fuse word 57, offset: 0xB90 */ - uint8_t RESERVED_70[12]; - __IO uint32_t FUSE058; /**< Value of fuse word 58, offset: 0xBA0 */ - uint8_t RESERVED_71[12]; - __IO uint32_t FUSE059; /**< Value of fuse word 59, offset: 0xBB0 */ - uint8_t RESERVED_72[12]; - __IO uint32_t FUSE060; /**< Value of fuse word 60, offset: 0xBC0 */ - uint8_t RESERVED_73[12]; - __IO uint32_t FUSE061; /**< Value of fuse word 61, offset: 0xBD0 */ - uint8_t RESERVED_74[12]; - __IO uint32_t FUSE062; /**< Value of fuse word 62, offset: 0xBE0 */ - uint8_t RESERVED_75[12]; - __IO uint32_t FUSE063; /**< Value of fuse word 63, offset: 0xBF0 */ - uint8_t RESERVED_76[12]; - __IO uint32_t FUSE064; /**< Value of fuse word 64, offset: 0xC00 */ - uint8_t RESERVED_77[12]; - __IO uint32_t FUSE065; /**< Value of fuse word 65, offset: 0xC10 */ - uint8_t RESERVED_78[12]; - __IO uint32_t FUSE066; /**< Value of fuse word 66, offset: 0xC20 */ - uint8_t RESERVED_79[12]; - __IO uint32_t FUSE067; /**< Value of fuse word 67, offset: 0xC30 */ - uint8_t RESERVED_80[12]; - __IO uint32_t FUSE068; /**< Value of fuse word 68, offset: 0xC40 */ - uint8_t RESERVED_81[12]; - __IO uint32_t FUSE069; /**< Value of fuse word 69, offset: 0xC50 */ - uint8_t RESERVED_82[12]; - __IO uint32_t FUSE070; /**< Value of fuse word 70, offset: 0xC60 */ - uint8_t RESERVED_83[12]; - __IO uint32_t FUSE071; /**< Value of fuse word 71, offset: 0xC70 */ - uint8_t RESERVED_84[12]; - __IO uint32_t FUSE072; /**< Value of fuse word 72, offset: 0xC80 */ - uint8_t RESERVED_85[12]; - __IO uint32_t FUSE073; /**< Value of fuse word 73, offset: 0xC90 */ - uint8_t RESERVED_86[12]; - __IO uint32_t FUSE074; /**< Value of fuse word 74, offset: 0xCA0 */ - uint8_t RESERVED_87[12]; - __IO uint32_t FUSE075; /**< Value of fuse word 75, offset: 0xCB0 */ - uint8_t RESERVED_88[12]; - __IO uint32_t FUSE076; /**< Value of fuse word 76, offset: 0xCC0 */ - uint8_t RESERVED_89[12]; - __IO uint32_t FUSE077; /**< Value of fuse word 77, offset: 0xCD0 */ - uint8_t RESERVED_90[12]; - __IO uint32_t FUSE078; /**< Value of fuse word 78, offset: 0xCE0 */ - uint8_t RESERVED_91[12]; - __IO uint32_t FUSE079; /**< Value of fuse word 79, offset: 0xCF0 */ - uint8_t RESERVED_92[12]; - __IO uint32_t FUSE080; /**< Value of fuse word 80, offset: 0xD00 */ - uint8_t RESERVED_93[12]; - __IO uint32_t FUSE081; /**< Value of fuse word 81, offset: 0xD10 */ - uint8_t RESERVED_94[12]; - __IO uint32_t FUSE082; /**< Value of fuse word 82, offset: 0xD20 */ - uint8_t RESERVED_95[12]; - __IO uint32_t FUSE083; /**< Value of fuse word 83, offset: 0xD30 */ - uint8_t RESERVED_96[12]; - __IO uint32_t FUSE084; /**< Value of fuse word 84, offset: 0xD40 */ - uint8_t RESERVED_97[12]; - __IO uint32_t FUSE085; /**< Value of fuse word 85, offset: 0xD50 */ - uint8_t RESERVED_98[12]; - __IO uint32_t FUSE086; /**< Value of fuse word 86, offset: 0xD60 */ - uint8_t RESERVED_99[12]; - __IO uint32_t FUSE087; /**< Value of fuse word 87, offset: 0xD70 */ - uint8_t RESERVED_100[12]; - __IO uint32_t FUSE088; /**< Value of fuse word 88, offset: 0xD80 */ - uint8_t RESERVED_101[12]; - __IO uint32_t FUSE089; /**< Value of fuse word 89, offset: 0xD90 */ - uint8_t RESERVED_102[12]; - __IO uint32_t FUSE090; /**< Value of fuse word 90, offset: 0xDA0 */ - uint8_t RESERVED_103[12]; - __IO uint32_t FUSE091; /**< Value of fuse word 91, offset: 0xDB0 */ - uint8_t RESERVED_104[12]; - __IO uint32_t FUSE092; /**< Value of fuse word 92, offset: 0xDC0 */ - uint8_t RESERVED_105[12]; - __IO uint32_t FUSE093; /**< Value of fuse word 93, offset: 0xDD0 */ - uint8_t RESERVED_106[12]; - __IO uint32_t FUSE094; /**< Value of fuse word 94, offset: 0xDE0 */ - uint8_t RESERVED_107[12]; - __IO uint32_t FUSE095; /**< Value of fuse word 95, offset: 0xDF0 */ - uint8_t RESERVED_108[12]; - __IO uint32_t FUSE096; /**< Value of fuse word 96, offset: 0xE00 */ - uint8_t RESERVED_109[12]; - __IO uint32_t FUSE097; /**< Value of fuse word 97, offset: 0xE10 */ - uint8_t RESERVED_110[12]; - __IO uint32_t FUSE098; /**< Value of fuse word 98, offset: 0xE20 */ - uint8_t RESERVED_111[12]; - __IO uint32_t FUSE099; /**< Value of fuse word 99, offset: 0xE30 */ - uint8_t RESERVED_112[12]; - __IO uint32_t FUSE100; /**< Value of fuse word 100, offset: 0xE40 */ - uint8_t RESERVED_113[12]; - __IO uint32_t FUSE101; /**< Value of fuse word 101, offset: 0xE50 */ - uint8_t RESERVED_114[12]; - __IO uint32_t FUSE102; /**< Value of fuse word 102, offset: 0xE60 */ - uint8_t RESERVED_115[12]; - __IO uint32_t FUSE103; /**< Value of fuse word 103, offset: 0xE70 */ - uint8_t RESERVED_116[12]; - __IO uint32_t FUSE104; /**< Value of fuse word 104, offset: 0xE80 */ - uint8_t RESERVED_117[12]; - __IO uint32_t FUSE105; /**< Value of fuse word 105, offset: 0xE90 */ - uint8_t RESERVED_118[12]; - __IO uint32_t FUSE106; /**< Value of fuse word 106, offset: 0xEA0 */ - uint8_t RESERVED_119[12]; - __IO uint32_t FUSE107; /**< Value of fuse word 107, offset: 0xEB0 */ - uint8_t RESERVED_120[12]; - __IO uint32_t FUSE108; /**< Value of fuse word 108, offset: 0xEC0 */ - uint8_t RESERVED_121[12]; - __IO uint32_t FUSE109; /**< Value of fuse word 109, offset: 0xED0 */ - uint8_t RESERVED_122[12]; - __IO uint32_t FUSE110; /**< Value of fuse word 110, offset: 0xEE0 */ - uint8_t RESERVED_123[12]; - __IO uint32_t FUSE111; /**< Value of fuse word 111, offset: 0xEF0 */ - uint8_t RESERVED_124[12]; - __IO uint32_t FUSE112; /**< Value of fuse word 112, offset: 0xF00 */ - uint8_t RESERVED_125[12]; - __IO uint32_t FUSE113; /**< Value of fuse word 113, offset: 0xF10 */ - uint8_t RESERVED_126[12]; - __IO uint32_t FUSE114; /**< Value of fuse word 114, offset: 0xF20 */ - uint8_t RESERVED_127[12]; - __IO uint32_t FUSE115; /**< Value of fuse word 115, offset: 0xF30 */ - uint8_t RESERVED_128[12]; - __IO uint32_t FUSE116; /**< Value of fuse word 116, offset: 0xF40 */ - uint8_t RESERVED_129[12]; - __IO uint32_t FUSE117; /**< Value of fuse word 117, offset: 0xF50 */ - uint8_t RESERVED_130[12]; - __IO uint32_t FUSE118; /**< Value of fuse word 118, offset: 0xF60 */ - uint8_t RESERVED_131[12]; - __IO uint32_t FUSE119; /**< Value of fuse word 119, offset: 0xF70 */ - uint8_t RESERVED_132[12]; - __IO uint32_t FUSE120; /**< Value of fuse word 120, offset: 0xF80 */ - uint8_t RESERVED_133[12]; - __IO uint32_t FUSE121; /**< Value of fuse word 121, offset: 0xF90 */ - uint8_t RESERVED_134[12]; - __IO uint32_t FUSE122; /**< Value of fuse word 122, offset: 0xFA0 */ - uint8_t RESERVED_135[12]; - __IO uint32_t FUSE123; /**< Value of fuse word 123, offset: 0xFB0 */ - uint8_t RESERVED_136[12]; - __IO uint32_t FUSE124; /**< Value of fuse word 124, offset: 0xFC0 */ - uint8_t RESERVED_137[12]; - __IO uint32_t FUSE125; /**< Value of fuse word 125, offset: 0xFD0 */ - uint8_t RESERVED_138[12]; - __IO uint32_t FUSE126; /**< Value of fuse word 126, offset: 0xFE0 */ - uint8_t RESERVED_139[12]; - __IO uint32_t FUSE127; /**< Value of fuse word 127, offset: 0xFF0 */ - uint8_t RESERVED_140[12]; - __IO uint32_t FUSE128; /**< Value of fuse word 128, offset: 0x1000 */ - uint8_t RESERVED_141[12]; - __IO uint32_t FUSE129; /**< Value of fuse word 129, offset: 0x1010 */ - uint8_t RESERVED_142[12]; - __IO uint32_t FUSE130; /**< Value of fuse word 130, offset: 0x1020 */ - uint8_t RESERVED_143[12]; - __IO uint32_t FUSE131; /**< Value of fuse word 131, offset: 0x1030 */ - uint8_t RESERVED_144[12]; - __IO uint32_t FUSE132; /**< Value of fuse word 132, offset: 0x1040 */ - uint8_t RESERVED_145[12]; - __IO uint32_t FUSE133; /**< Value of fuse word 133, offset: 0x1050 */ - uint8_t RESERVED_146[12]; - __IO uint32_t FUSE134; /**< Value of fuse word 134, offset: 0x1060 */ - uint8_t RESERVED_147[12]; - __IO uint32_t FUSE135; /**< Value of fuse word 135, offset: 0x1070 */ - uint8_t RESERVED_148[12]; - __IO uint32_t FUSE136; /**< Value of fuse word 136, offset: 0x1080 */ - uint8_t RESERVED_149[12]; - __IO uint32_t FUSE137; /**< Value of fuse word 137, offset: 0x1090 */ - uint8_t RESERVED_150[12]; - __IO uint32_t FUSE138; /**< Value of fuse word 138, offset: 0x10A0 */ - uint8_t RESERVED_151[12]; - __IO uint32_t FUSE139; /**< Value of fuse word 139, offset: 0x10B0 */ - uint8_t RESERVED_152[12]; - __IO uint32_t FUSE140; /**< Value of fuse word 140, offset: 0x10C0 */ - uint8_t RESERVED_153[12]; - __IO uint32_t FUSE141; /**< Value of fuse word 141, offset: 0x10D0 */ - uint8_t RESERVED_154[12]; - __IO uint32_t FUSE142; /**< Value of fuse word 142, offset: 0x10E0 */ - uint8_t RESERVED_155[12]; - __IO uint32_t FUSE143; /**< Value of fuse word 143, offset: 0x10F0 */ + __I uint32_t LOCKED4; /**< OTP Controller Program Locked Status 4 Register, offset: 0x640 */ + uint8_t RESERVED_11[444]; + struct { /* offset: 0x800, array step: 0x10 */ + __I uint32_t FUSE; /**< Value of fuse word 0..Value of fuse word 143, array offset: 0x800, array step: 0x10 */ + uint8_t RESERVED_0[12]; + } FUSEN[144]; } OCOTP_Type; /* ---------------------------------------------------------------------------- @@ -63896,1487 +74000,745 @@ typedef struct { /*! * @addtogroup OCOTP_Register_Masks OCOTP Register Masks * @{ - */ - -/*! @name CTRL - OTP Controller Control Register */ -/*! @{ */ -#define OCOTP_CTRL_ADDR_MASK (0x3FFU) -#define OCOTP_CTRL_ADDR_SHIFT (0U) -#define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK) -#define OCOTP_CTRL_BUSY_MASK (0x400U) -#define OCOTP_CTRL_BUSY_SHIFT (10U) -#define OCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK) -#define OCOTP_CTRL_ERROR_MASK (0x800U) -#define OCOTP_CTRL_ERROR_SHIFT (11U) -#define OCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK) -#define OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x1000U) -#define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (12U) -#define OCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK) -#define OCOTP_CTRL_WORDLOCK_MASK (0x8000U) -#define OCOTP_CTRL_WORDLOCK_SHIFT (15U) -#define OCOTP_CTRL_WORDLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WORDLOCK_SHIFT)) & OCOTP_CTRL_WORDLOCK_MASK) -#define OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U) -#define OCOTP_CTRL_WR_UNLOCK_SHIFT (16U) -#define OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK) -/*! @} */ - -/*! @name CTRL_SET - OTP Controller Control Register */ -/*! @{ */ -#define OCOTP_CTRL_SET_ADDR_MASK (0x3FFU) -#define OCOTP_CTRL_SET_ADDR_SHIFT (0U) -#define OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK) -#define OCOTP_CTRL_SET_BUSY_MASK (0x400U) -#define OCOTP_CTRL_SET_BUSY_SHIFT (10U) -#define OCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK) -#define OCOTP_CTRL_SET_ERROR_MASK (0x800U) -#define OCOTP_CTRL_SET_ERROR_SHIFT (11U) -#define OCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK) -#define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x1000U) -#define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (12U) -#define OCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK) -#define OCOTP_CTRL_SET_WORDLOCK_MASK (0x8000U) -#define OCOTP_CTRL_SET_WORDLOCK_SHIFT (15U) -#define OCOTP_CTRL_SET_WORDLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WORDLOCK_SHIFT)) & OCOTP_CTRL_SET_WORDLOCK_MASK) -#define OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U) -#define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U) -#define OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK) -/*! @} */ - -/*! @name CTRL_CLR - OTP Controller Control Register */ -/*! @{ */ -#define OCOTP_CTRL_CLR_ADDR_MASK (0x3FFU) -#define OCOTP_CTRL_CLR_ADDR_SHIFT (0U) -#define OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK) -#define OCOTP_CTRL_CLR_BUSY_MASK (0x400U) -#define OCOTP_CTRL_CLR_BUSY_SHIFT (10U) -#define OCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK) -#define OCOTP_CTRL_CLR_ERROR_MASK (0x800U) -#define OCOTP_CTRL_CLR_ERROR_SHIFT (11U) -#define OCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK) -#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x1000U) -#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (12U) -#define OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK) -#define OCOTP_CTRL_CLR_WORDLOCK_MASK (0x8000U) -#define OCOTP_CTRL_CLR_WORDLOCK_SHIFT (15U) -#define OCOTP_CTRL_CLR_WORDLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WORDLOCK_SHIFT)) & OCOTP_CTRL_CLR_WORDLOCK_MASK) -#define OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U) -#define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U) -#define OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK) -/*! @} */ - -/*! @name CTRL_TOG - OTP Controller Control Register */ -/*! @{ */ -#define OCOTP_CTRL_TOG_ADDR_MASK (0x3FFU) -#define OCOTP_CTRL_TOG_ADDR_SHIFT (0U) -#define OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK) -#define OCOTP_CTRL_TOG_BUSY_MASK (0x400U) -#define OCOTP_CTRL_TOG_BUSY_SHIFT (10U) -#define OCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK) -#define OCOTP_CTRL_TOG_ERROR_MASK (0x800U) -#define OCOTP_CTRL_TOG_ERROR_SHIFT (11U) -#define OCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK) -#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x1000U) -#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (12U) -#define OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK) -#define OCOTP_CTRL_TOG_WORDLOCK_MASK (0x8000U) -#define OCOTP_CTRL_TOG_WORDLOCK_SHIFT (15U) -#define OCOTP_CTRL_TOG_WORDLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WORDLOCK_SHIFT)) & OCOTP_CTRL_TOG_WORDLOCK_MASK) -#define OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U) -#define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U) -#define OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK) -/*! @} */ - -/*! @name PDN - OTP Controller PDN Register */ -/*! @{ */ -#define OCOTP_PDN_PDN0_MASK (0x1U) -#define OCOTP_PDN_PDN0_SHIFT (0U) -#define OCOTP_PDN_PDN0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_PDN_PDN0_SHIFT)) & OCOTP_PDN_PDN0_MASK) -/*! @} */ - -/*! @name DATA - OTP Controller Write Data Register */ -/*! @{ */ -#define OCOTP_DATA_DATA_MASK (0xFFFFFFFFU) -#define OCOTP_DATA_DATA_SHIFT (0U) -#define OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK) -/*! @} */ - -/*! @name READ_CTRL - OTP Controller Write Data Register */ -/*! @{ */ -#define OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U) -#define OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U) -#define OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK) -#define OCOTP_READ_CTRL_READ_NUM_MASK (0x6U) -#define OCOTP_READ_CTRL_READ_NUM_SHIFT (1U) -#define OCOTP_READ_CTRL_READ_NUM(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_NUM_SHIFT)) & OCOTP_READ_CTRL_READ_NUM_MASK) -#define OCOTP_READ_CTRL_READ_DONE_INTR_ENA_MASK (0x8U) -#define OCOTP_READ_CTRL_READ_DONE_INTR_ENA_SHIFT (3U) -#define OCOTP_READ_CTRL_READ_DONE_INTR_ENA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_DONE_INTR_ENA_SHIFT)) & OCOTP_READ_CTRL_READ_DONE_INTR_ENA_MASK) -#define OCOTP_READ_CTRL_READ_ERROR_INTR_ENA_MASK (0x10U) -#define OCOTP_READ_CTRL_READ_ERROR_INTR_ENA_SHIFT (4U) -#define OCOTP_READ_CTRL_READ_ERROR_INTR_ENA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_ERROR_INTR_ENA_SHIFT)) & OCOTP_READ_CTRL_READ_ERROR_INTR_ENA_MASK) -/*! @} */ - -/*! @name SCS - Software Controllable Signals Register */ -/*! @{ */ -#define OCOTP_SCS_HAB_JDE_MASK (0x1U) -#define OCOTP_SCS_HAB_JDE_SHIFT (0U) -#define OCOTP_SCS_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_SCS_HAB_JDE_MASK) -#define OCOTP_SCS_SPARE_MASK (0x7FFFFFFEU) -#define OCOTP_SCS_SPARE_SHIFT (1U) -#define OCOTP_SCS_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SPARE_SHIFT)) & OCOTP_SCS_SPARE_MASK) -#define OCOTP_SCS_LOCK_MASK (0x80000000U) -#define OCOTP_SCS_LOCK_SHIFT (31U) -#define OCOTP_SCS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_LOCK_SHIFT)) & OCOTP_SCS_LOCK_MASK) -/*! @} */ - -/*! @name SCS_SET - Software Controllable Signals Register */ -/*! @{ */ -#define OCOTP_SCS_SET_HAB_JDE_MASK (0x1U) -#define OCOTP_SCS_SET_HAB_JDE_SHIFT (0U) -#define OCOTP_SCS_SET_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_SCS_SET_HAB_JDE_MASK) -#define OCOTP_SCS_SET_SPARE_MASK (0x7FFFFFFEU) -#define OCOTP_SCS_SET_SPARE_SHIFT (1U) -#define OCOTP_SCS_SET_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_SCS_SET_SPARE_MASK) -#define OCOTP_SCS_SET_LOCK_MASK (0x80000000U) -#define OCOTP_SCS_SET_LOCK_SHIFT (31U) -#define OCOTP_SCS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_SCS_SET_LOCK_MASK) -/*! @} */ - -/*! @name SCS_CLR - Software Controllable Signals Register */ -/*! @{ */ -#define OCOTP_SCS_CLR_HAB_JDE_MASK (0x1U) -#define OCOTP_SCS_CLR_HAB_JDE_SHIFT (0U) -#define OCOTP_SCS_CLR_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_SCS_CLR_HAB_JDE_MASK) -#define OCOTP_SCS_CLR_SPARE_MASK (0x7FFFFFFEU) -#define OCOTP_SCS_CLR_SPARE_SHIFT (1U) -#define OCOTP_SCS_CLR_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_SCS_CLR_SPARE_MASK) -#define OCOTP_SCS_CLR_LOCK_MASK (0x80000000U) -#define OCOTP_SCS_CLR_LOCK_SHIFT (31U) -#define OCOTP_SCS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_SCS_CLR_LOCK_MASK) -/*! @} */ - -/*! @name SCS_TOG - Software Controllable Signals Register */ -/*! @{ */ -#define OCOTP_SCS_TOG_HAB_JDE_MASK (0x1U) -#define OCOTP_SCS_TOG_HAB_JDE_SHIFT (0U) -#define OCOTP_SCS_TOG_HAB_JDE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_SCS_TOG_HAB_JDE_MASK) -#define OCOTP_SCS_TOG_SPARE_MASK (0x7FFFFFFEU) -#define OCOTP_SCS_TOG_SPARE_SHIFT (1U) -#define OCOTP_SCS_TOG_SPARE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_SCS_TOG_SPARE_MASK) -#define OCOTP_SCS_TOG_LOCK_MASK (0x80000000U) -#define OCOTP_SCS_TOG_LOCK_SHIFT (31U) -#define OCOTP_SCS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_SCS_TOG_LOCK_MASK) -/*! @} */ - -/*! @name OUT_STATUS0 - 8K OTP Memory STATUS Register */ -/*! @{ */ -#define OCOTP_OUT_STATUS0_DOUT_40_32_MASK (0x1FFU) -#define OCOTP_OUT_STATUS0_DOUT_40_32_SHIFT (0U) -#define OCOTP_OUT_STATUS0_DOUT_40_32(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_DOUT_40_32_SHIFT)) & OCOTP_OUT_STATUS0_DOUT_40_32_MASK) -#define OCOTP_OUT_STATUS0_SEC_MASK (0x200U) -#define OCOTP_OUT_STATUS0_SEC_SHIFT (9U) -#define OCOTP_OUT_STATUS0_SEC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_SEC_SHIFT)) & OCOTP_OUT_STATUS0_SEC_MASK) -#define OCOTP_OUT_STATUS0_RESERVED_MASK (0x400U) -#define OCOTP_OUT_STATUS0_RESERVED_SHIFT (10U) -#define OCOTP_OUT_STATUS0_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_RESERVED_SHIFT)) & OCOTP_OUT_STATUS0_RESERVED_MASK) -#define OCOTP_OUT_STATUS0_LOCKED_MASK (0x800U) -#define OCOTP_OUT_STATUS0_LOCKED_SHIFT (11U) -#define OCOTP_OUT_STATUS0_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_LOCKED_SHIFT)) & OCOTP_OUT_STATUS0_LOCKED_MASK) -#define OCOTP_OUT_STATUS0_PROGFAIL_MASK (0x1000U) -#define OCOTP_OUT_STATUS0_PROGFAIL_SHIFT (12U) -#define OCOTP_OUT_STATUS0_PROGFAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS0_PROGFAIL_MASK) -#define OCOTP_OUT_STATUS0_ACK_MASK (0x2000U) -#define OCOTP_OUT_STATUS0_ACK_SHIFT (13U) -#define OCOTP_OUT_STATUS0_ACK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_ACK_SHIFT)) & OCOTP_OUT_STATUS0_ACK_MASK) -#define OCOTP_OUT_STATUS0_PWOK_MASK (0x4000U) -#define OCOTP_OUT_STATUS0_PWOK_SHIFT (14U) -#define OCOTP_OUT_STATUS0_PWOK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_PWOK_SHIFT)) & OCOTP_OUT_STATUS0_PWOK_MASK) -#define OCOTP_OUT_STATUS0_FLAGSTATE_MASK (0x78000U) -#define OCOTP_OUT_STATUS0_FLAGSTATE_SHIFT (15U) -#define OCOTP_OUT_STATUS0_FLAGSTATE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS0_FLAGSTATE_MASK) -#define OCOTP_OUT_STATUS0_SEC_RELOAD_MASK (0x80000U) -#define OCOTP_OUT_STATUS0_SEC_RELOAD_SHIFT (19U) -#define OCOTP_OUT_STATUS0_SEC_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS0_SEC_RELOAD_MASK) -#define OCOTP_OUT_STATUS0_DED_RELOAD_MASK (0x100000U) -#define OCOTP_OUT_STATUS0_DED_RELOAD_SHIFT (20U) -#define OCOTP_OUT_STATUS0_DED_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS0_DED_RELOAD_MASK) -#define OCOTP_OUT_STATUS0_CALIBRATED_MASK (0x200000U) -#define OCOTP_OUT_STATUS0_CALIBRATED_SHIFT (21U) -#define OCOTP_OUT_STATUS0_CALIBRATED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS0_CALIBRATED_MASK) -#define OCOTP_OUT_STATUS0_READ_DONE_INTR_MASK (0x400000U) -#define OCOTP_OUT_STATUS0_READ_DONE_INTR_SHIFT (22U) -#define OCOTP_OUT_STATUS0_READ_DONE_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS0_READ_DONE_INTR_MASK) -#define OCOTP_OUT_STATUS0_READ_ERROR_INTR_MASK (0x800000U) -#define OCOTP_OUT_STATUS0_READ_ERROR_INTR_SHIFT (23U) -#define OCOTP_OUT_STATUS0_READ_ERROR_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS0_READ_ERROR_INTR_MASK) -#define OCOTP_OUT_STATUS0_DED0_MASK (0x1000000U) -#define OCOTP_OUT_STATUS0_DED0_SHIFT (24U) -#define OCOTP_OUT_STATUS0_DED0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_DED0_SHIFT)) & OCOTP_OUT_STATUS0_DED0_MASK) -#define OCOTP_OUT_STATUS0_DED1_MASK (0x2000000U) -#define OCOTP_OUT_STATUS0_DED1_SHIFT (25U) -#define OCOTP_OUT_STATUS0_DED1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_DED1_SHIFT)) & OCOTP_OUT_STATUS0_DED1_MASK) -#define OCOTP_OUT_STATUS0_DED2_MASK (0x4000000U) -#define OCOTP_OUT_STATUS0_DED2_SHIFT (26U) -#define OCOTP_OUT_STATUS0_DED2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_DED2_SHIFT)) & OCOTP_OUT_STATUS0_DED2_MASK) -#define OCOTP_OUT_STATUS0_DED3_MASK (0x8000000U) -#define OCOTP_OUT_STATUS0_DED3_SHIFT (27U) -#define OCOTP_OUT_STATUS0_DED3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_DED3_SHIFT)) & OCOTP_OUT_STATUS0_DED3_MASK) -/*! @} */ - -/*! @name OUT_STATUS0_SET - 8K OTP Memory STATUS Register */ -/*! @{ */ -#define OCOTP_OUT_STATUS0_SET_DOUT_40_32_MASK (0x1FFU) -#define OCOTP_OUT_STATUS0_SET_DOUT_40_32_SHIFT (0U) -#define OCOTP_OUT_STATUS0_SET_DOUT_40_32(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_SET_DOUT_40_32_SHIFT)) & OCOTP_OUT_STATUS0_SET_DOUT_40_32_MASK) -#define OCOTP_OUT_STATUS0_SET_SEC_MASK (0x200U) -#define OCOTP_OUT_STATUS0_SET_SEC_SHIFT (9U) -#define OCOTP_OUT_STATUS0_SET_SEC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_SET_SEC_SHIFT)) & OCOTP_OUT_STATUS0_SET_SEC_MASK) -#define OCOTP_OUT_STATUS0_SET_RESERVED_MASK (0x400U) -#define OCOTP_OUT_STATUS0_SET_RESERVED_SHIFT (10U) -#define OCOTP_OUT_STATUS0_SET_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_SET_RESERVED_SHIFT)) & OCOTP_OUT_STATUS0_SET_RESERVED_MASK) -#define OCOTP_OUT_STATUS0_SET_LOCKED_MASK (0x800U) -#define OCOTP_OUT_STATUS0_SET_LOCKED_SHIFT (11U) -#define OCOTP_OUT_STATUS0_SET_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_SET_LOCKED_SHIFT)) & OCOTP_OUT_STATUS0_SET_LOCKED_MASK) -#define OCOTP_OUT_STATUS0_SET_PROGFAIL_MASK (0x1000U) -#define OCOTP_OUT_STATUS0_SET_PROGFAIL_SHIFT (12U) -#define OCOTP_OUT_STATUS0_SET_PROGFAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_SET_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS0_SET_PROGFAIL_MASK) -#define OCOTP_OUT_STATUS0_SET_ACK_MASK (0x2000U) -#define OCOTP_OUT_STATUS0_SET_ACK_SHIFT (13U) -#define OCOTP_OUT_STATUS0_SET_ACK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_SET_ACK_SHIFT)) & OCOTP_OUT_STATUS0_SET_ACK_MASK) -#define OCOTP_OUT_STATUS0_SET_PWOK_MASK (0x4000U) -#define OCOTP_OUT_STATUS0_SET_PWOK_SHIFT (14U) -#define OCOTP_OUT_STATUS0_SET_PWOK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_SET_PWOK_SHIFT)) & OCOTP_OUT_STATUS0_SET_PWOK_MASK) -#define OCOTP_OUT_STATUS0_SET_FLAGSTATE_MASK (0x78000U) -#define OCOTP_OUT_STATUS0_SET_FLAGSTATE_SHIFT (15U) -#define OCOTP_OUT_STATUS0_SET_FLAGSTATE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_SET_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS0_SET_FLAGSTATE_MASK) -#define OCOTP_OUT_STATUS0_SET_SEC_RELOAD_MASK (0x80000U) -#define OCOTP_OUT_STATUS0_SET_SEC_RELOAD_SHIFT (19U) -#define OCOTP_OUT_STATUS0_SET_SEC_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_SET_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS0_SET_SEC_RELOAD_MASK) -#define OCOTP_OUT_STATUS0_SET_DED_RELOAD_MASK (0x100000U) -#define OCOTP_OUT_STATUS0_SET_DED_RELOAD_SHIFT (20U) -#define OCOTP_OUT_STATUS0_SET_DED_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_SET_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS0_SET_DED_RELOAD_MASK) -#define OCOTP_OUT_STATUS0_SET_CALIBRATED_MASK (0x200000U) -#define OCOTP_OUT_STATUS0_SET_CALIBRATED_SHIFT (21U) -#define OCOTP_OUT_STATUS0_SET_CALIBRATED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_SET_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS0_SET_CALIBRATED_MASK) -#define OCOTP_OUT_STATUS0_SET_READ_DONE_INTR_MASK (0x400000U) -#define OCOTP_OUT_STATUS0_SET_READ_DONE_INTR_SHIFT (22U) -#define OCOTP_OUT_STATUS0_SET_READ_DONE_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_SET_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS0_SET_READ_DONE_INTR_MASK) -#define OCOTP_OUT_STATUS0_SET_READ_ERROR_INTR_MASK (0x800000U) -#define OCOTP_OUT_STATUS0_SET_READ_ERROR_INTR_SHIFT (23U) -#define OCOTP_OUT_STATUS0_SET_READ_ERROR_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_SET_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS0_SET_READ_ERROR_INTR_MASK) -#define OCOTP_OUT_STATUS0_SET_DED0_MASK (0x1000000U) -#define OCOTP_OUT_STATUS0_SET_DED0_SHIFT (24U) -#define OCOTP_OUT_STATUS0_SET_DED0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_SET_DED0_SHIFT)) & OCOTP_OUT_STATUS0_SET_DED0_MASK) -#define OCOTP_OUT_STATUS0_SET_DED1_MASK (0x2000000U) -#define OCOTP_OUT_STATUS0_SET_DED1_SHIFT (25U) -#define OCOTP_OUT_STATUS0_SET_DED1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_SET_DED1_SHIFT)) & OCOTP_OUT_STATUS0_SET_DED1_MASK) -#define OCOTP_OUT_STATUS0_SET_DED2_MASK (0x4000000U) -#define OCOTP_OUT_STATUS0_SET_DED2_SHIFT (26U) -#define OCOTP_OUT_STATUS0_SET_DED2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_SET_DED2_SHIFT)) & OCOTP_OUT_STATUS0_SET_DED2_MASK) -#define OCOTP_OUT_STATUS0_SET_DED3_MASK (0x8000000U) -#define OCOTP_OUT_STATUS0_SET_DED3_SHIFT (27U) -#define OCOTP_OUT_STATUS0_SET_DED3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_SET_DED3_SHIFT)) & OCOTP_OUT_STATUS0_SET_DED3_MASK) -/*! @} */ - -/*! @name OUT_STATUS0_CLR - 8K OTP Memory STATUS Register */ -/*! @{ */ -#define OCOTP_OUT_STATUS0_CLR_DOUT_40_32_MASK (0x1FFU) -#define OCOTP_OUT_STATUS0_CLR_DOUT_40_32_SHIFT (0U) -#define OCOTP_OUT_STATUS0_CLR_DOUT_40_32(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_CLR_DOUT_40_32_SHIFT)) & OCOTP_OUT_STATUS0_CLR_DOUT_40_32_MASK) -#define OCOTP_OUT_STATUS0_CLR_SEC_MASK (0x200U) -#define OCOTP_OUT_STATUS0_CLR_SEC_SHIFT (9U) -#define OCOTP_OUT_STATUS0_CLR_SEC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_CLR_SEC_SHIFT)) & OCOTP_OUT_STATUS0_CLR_SEC_MASK) -#define OCOTP_OUT_STATUS0_CLR_RESERVED_MASK (0x400U) -#define OCOTP_OUT_STATUS0_CLR_RESERVED_SHIFT (10U) -#define OCOTP_OUT_STATUS0_CLR_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_CLR_RESERVED_SHIFT)) & OCOTP_OUT_STATUS0_CLR_RESERVED_MASK) -#define OCOTP_OUT_STATUS0_CLR_LOCKED_MASK (0x800U) -#define OCOTP_OUT_STATUS0_CLR_LOCKED_SHIFT (11U) -#define OCOTP_OUT_STATUS0_CLR_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_CLR_LOCKED_SHIFT)) & OCOTP_OUT_STATUS0_CLR_LOCKED_MASK) -#define OCOTP_OUT_STATUS0_CLR_PROGFAIL_MASK (0x1000U) -#define OCOTP_OUT_STATUS0_CLR_PROGFAIL_SHIFT (12U) -#define OCOTP_OUT_STATUS0_CLR_PROGFAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_CLR_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS0_CLR_PROGFAIL_MASK) -#define OCOTP_OUT_STATUS0_CLR_ACK_MASK (0x2000U) -#define OCOTP_OUT_STATUS0_CLR_ACK_SHIFT (13U) -#define OCOTP_OUT_STATUS0_CLR_ACK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_CLR_ACK_SHIFT)) & OCOTP_OUT_STATUS0_CLR_ACK_MASK) -#define OCOTP_OUT_STATUS0_CLR_PWOK_MASK (0x4000U) -#define OCOTP_OUT_STATUS0_CLR_PWOK_SHIFT (14U) -#define OCOTP_OUT_STATUS0_CLR_PWOK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_CLR_PWOK_SHIFT)) & OCOTP_OUT_STATUS0_CLR_PWOK_MASK) -#define OCOTP_OUT_STATUS0_CLR_FLAGSTATE_MASK (0x78000U) -#define OCOTP_OUT_STATUS0_CLR_FLAGSTATE_SHIFT (15U) -#define OCOTP_OUT_STATUS0_CLR_FLAGSTATE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_CLR_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS0_CLR_FLAGSTATE_MASK) -#define OCOTP_OUT_STATUS0_CLR_SEC_RELOAD_MASK (0x80000U) -#define OCOTP_OUT_STATUS0_CLR_SEC_RELOAD_SHIFT (19U) -#define OCOTP_OUT_STATUS0_CLR_SEC_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_CLR_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS0_CLR_SEC_RELOAD_MASK) -#define OCOTP_OUT_STATUS0_CLR_DED_RELOAD_MASK (0x100000U) -#define OCOTP_OUT_STATUS0_CLR_DED_RELOAD_SHIFT (20U) -#define OCOTP_OUT_STATUS0_CLR_DED_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_CLR_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS0_CLR_DED_RELOAD_MASK) -#define OCOTP_OUT_STATUS0_CLR_CALIBRATED_MASK (0x200000U) -#define OCOTP_OUT_STATUS0_CLR_CALIBRATED_SHIFT (21U) -#define OCOTP_OUT_STATUS0_CLR_CALIBRATED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_CLR_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS0_CLR_CALIBRATED_MASK) -#define OCOTP_OUT_STATUS0_CLR_READ_DONE_INTR_MASK (0x400000U) -#define OCOTP_OUT_STATUS0_CLR_READ_DONE_INTR_SHIFT (22U) -#define OCOTP_OUT_STATUS0_CLR_READ_DONE_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_CLR_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS0_CLR_READ_DONE_INTR_MASK) -#define OCOTP_OUT_STATUS0_CLR_READ_ERROR_INTR_MASK (0x800000U) -#define OCOTP_OUT_STATUS0_CLR_READ_ERROR_INTR_SHIFT (23U) -#define OCOTP_OUT_STATUS0_CLR_READ_ERROR_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_CLR_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS0_CLR_READ_ERROR_INTR_MASK) -#define OCOTP_OUT_STATUS0_CLR_DED0_MASK (0x1000000U) -#define OCOTP_OUT_STATUS0_CLR_DED0_SHIFT (24U) -#define OCOTP_OUT_STATUS0_CLR_DED0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_CLR_DED0_SHIFT)) & OCOTP_OUT_STATUS0_CLR_DED0_MASK) -#define OCOTP_OUT_STATUS0_CLR_DED1_MASK (0x2000000U) -#define OCOTP_OUT_STATUS0_CLR_DED1_SHIFT (25U) -#define OCOTP_OUT_STATUS0_CLR_DED1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_CLR_DED1_SHIFT)) & OCOTP_OUT_STATUS0_CLR_DED1_MASK) -#define OCOTP_OUT_STATUS0_CLR_DED2_MASK (0x4000000U) -#define OCOTP_OUT_STATUS0_CLR_DED2_SHIFT (26U) -#define OCOTP_OUT_STATUS0_CLR_DED2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_CLR_DED2_SHIFT)) & OCOTP_OUT_STATUS0_CLR_DED2_MASK) -#define OCOTP_OUT_STATUS0_CLR_DED3_MASK (0x8000000U) -#define OCOTP_OUT_STATUS0_CLR_DED3_SHIFT (27U) -#define OCOTP_OUT_STATUS0_CLR_DED3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_CLR_DED3_SHIFT)) & OCOTP_OUT_STATUS0_CLR_DED3_MASK) -/*! @} */ - -/*! @name OUT_STATUS0_TOG - 8K OTP Memory STATUS Register */ -/*! @{ */ -#define OCOTP_OUT_STATUS0_TOG_DOUT_40_32_MASK (0x1FFU) -#define OCOTP_OUT_STATUS0_TOG_DOUT_40_32_SHIFT (0U) -#define OCOTP_OUT_STATUS0_TOG_DOUT_40_32(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_TOG_DOUT_40_32_SHIFT)) & OCOTP_OUT_STATUS0_TOG_DOUT_40_32_MASK) -#define OCOTP_OUT_STATUS0_TOG_SEC_MASK (0x200U) -#define OCOTP_OUT_STATUS0_TOG_SEC_SHIFT (9U) -#define OCOTP_OUT_STATUS0_TOG_SEC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_TOG_SEC_SHIFT)) & OCOTP_OUT_STATUS0_TOG_SEC_MASK) -#define OCOTP_OUT_STATUS0_TOG_RESERVED_MASK (0x400U) -#define OCOTP_OUT_STATUS0_TOG_RESERVED_SHIFT (10U) -#define OCOTP_OUT_STATUS0_TOG_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_TOG_RESERVED_SHIFT)) & OCOTP_OUT_STATUS0_TOG_RESERVED_MASK) -#define OCOTP_OUT_STATUS0_TOG_LOCKED_MASK (0x800U) -#define OCOTP_OUT_STATUS0_TOG_LOCKED_SHIFT (11U) -#define OCOTP_OUT_STATUS0_TOG_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_TOG_LOCKED_SHIFT)) & OCOTP_OUT_STATUS0_TOG_LOCKED_MASK) -#define OCOTP_OUT_STATUS0_TOG_PROGFAIL_MASK (0x1000U) -#define OCOTP_OUT_STATUS0_TOG_PROGFAIL_SHIFT (12U) -#define OCOTP_OUT_STATUS0_TOG_PROGFAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_TOG_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS0_TOG_PROGFAIL_MASK) -#define OCOTP_OUT_STATUS0_TOG_ACK_MASK (0x2000U) -#define OCOTP_OUT_STATUS0_TOG_ACK_SHIFT (13U) -#define OCOTP_OUT_STATUS0_TOG_ACK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_TOG_ACK_SHIFT)) & OCOTP_OUT_STATUS0_TOG_ACK_MASK) -#define OCOTP_OUT_STATUS0_TOG_PWOK_MASK (0x4000U) -#define OCOTP_OUT_STATUS0_TOG_PWOK_SHIFT (14U) -#define OCOTP_OUT_STATUS0_TOG_PWOK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_TOG_PWOK_SHIFT)) & OCOTP_OUT_STATUS0_TOG_PWOK_MASK) -#define OCOTP_OUT_STATUS0_TOG_FLAGSTATE_MASK (0x78000U) -#define OCOTP_OUT_STATUS0_TOG_FLAGSTATE_SHIFT (15U) -#define OCOTP_OUT_STATUS0_TOG_FLAGSTATE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_TOG_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS0_TOG_FLAGSTATE_MASK) -#define OCOTP_OUT_STATUS0_TOG_SEC_RELOAD_MASK (0x80000U) -#define OCOTP_OUT_STATUS0_TOG_SEC_RELOAD_SHIFT (19U) -#define OCOTP_OUT_STATUS0_TOG_SEC_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_TOG_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS0_TOG_SEC_RELOAD_MASK) -#define OCOTP_OUT_STATUS0_TOG_DED_RELOAD_MASK (0x100000U) -#define OCOTP_OUT_STATUS0_TOG_DED_RELOAD_SHIFT (20U) -#define OCOTP_OUT_STATUS0_TOG_DED_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_TOG_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS0_TOG_DED_RELOAD_MASK) -#define OCOTP_OUT_STATUS0_TOG_CALIBRATED_MASK (0x200000U) -#define OCOTP_OUT_STATUS0_TOG_CALIBRATED_SHIFT (21U) -#define OCOTP_OUT_STATUS0_TOG_CALIBRATED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_TOG_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS0_TOG_CALIBRATED_MASK) -#define OCOTP_OUT_STATUS0_TOG_READ_DONE_INTR_MASK (0x400000U) -#define OCOTP_OUT_STATUS0_TOG_READ_DONE_INTR_SHIFT (22U) -#define OCOTP_OUT_STATUS0_TOG_READ_DONE_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_TOG_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS0_TOG_READ_DONE_INTR_MASK) -#define OCOTP_OUT_STATUS0_TOG_READ_ERROR_INTR_MASK (0x800000U) -#define OCOTP_OUT_STATUS0_TOG_READ_ERROR_INTR_SHIFT (23U) -#define OCOTP_OUT_STATUS0_TOG_READ_ERROR_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_TOG_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS0_TOG_READ_ERROR_INTR_MASK) -#define OCOTP_OUT_STATUS0_TOG_DED0_MASK (0x1000000U) -#define OCOTP_OUT_STATUS0_TOG_DED0_SHIFT (24U) -#define OCOTP_OUT_STATUS0_TOG_DED0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_TOG_DED0_SHIFT)) & OCOTP_OUT_STATUS0_TOG_DED0_MASK) -#define OCOTP_OUT_STATUS0_TOG_DED1_MASK (0x2000000U) -#define OCOTP_OUT_STATUS0_TOG_DED1_SHIFT (25U) -#define OCOTP_OUT_STATUS0_TOG_DED1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_TOG_DED1_SHIFT)) & OCOTP_OUT_STATUS0_TOG_DED1_MASK) -#define OCOTP_OUT_STATUS0_TOG_DED2_MASK (0x4000000U) -#define OCOTP_OUT_STATUS0_TOG_DED2_SHIFT (26U) -#define OCOTP_OUT_STATUS0_TOG_DED2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_TOG_DED2_SHIFT)) & OCOTP_OUT_STATUS0_TOG_DED2_MASK) -#define OCOTP_OUT_STATUS0_TOG_DED3_MASK (0x8000000U) -#define OCOTP_OUT_STATUS0_TOG_DED3_SHIFT (27U) -#define OCOTP_OUT_STATUS0_TOG_DED3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS0_TOG_DED3_SHIFT)) & OCOTP_OUT_STATUS0_TOG_DED3_MASK) -/*! @} */ - -/*! @name STARTWORD0 - 8K OTP memory Startword Register */ -/*! @{ */ -#define OCOTP_STARTWORD0_STARTWORD_MASK (0xFFFFU) -#define OCOTP_STARTWORD0_STARTWORD_SHIFT (0U) -#define OCOTP_STARTWORD0_STARTWORD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_STARTWORD0_STARTWORD_SHIFT)) & OCOTP_STARTWORD0_STARTWORD_MASK) -/*! @} */ - -/*! @name VERSION - OTP Controller Version Register */ -/*! @{ */ -#define OCOTP_VERSION_STEP_MASK (0xFFFFU) -#define OCOTP_VERSION_STEP_SHIFT (0U) -#define OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK) -#define OCOTP_VERSION_MINOR_MASK (0xFF0000U) -#define OCOTP_VERSION_MINOR_SHIFT (16U) -#define OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK) -#define OCOTP_VERSION_MAJOR_MASK (0xFF000000U) -#define OCOTP_VERSION_MAJOR_SHIFT (24U) -#define OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK) -/*! @} */ - -/*! @name READ_FUSE_DATA - */ -/*! @{ */ -#define OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU) -#define OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U) -#define OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK) -/*! @} */ - -/* The count of OCOTP_READ_FUSE_DATA */ -#define OCOTP_READ_FUSE_DATA_COUNT (4U) - -/*! @name SW_LOCK - */ -/*! @{ */ -#define OCOTP_SW_LOCK_SW_LOCK_MASK (0xFFFFFFFFU) -#define OCOTP_SW_LOCK_SW_LOCK_SHIFT (0U) -#define OCOTP_SW_LOCK_SW_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_LOCK_SW_LOCK_SHIFT)) & OCOTP_SW_LOCK_SW_LOCK_MASK) -/*! @} */ - -/*! @name BIT_LOCK - */ -/*! @{ */ -#define OCOTP_BIT_LOCK_BIT_LOCK_MASK (0xFFFFU) -#define OCOTP_BIT_LOCK_BIT_LOCK_SHIFT (0U) -#define OCOTP_BIT_LOCK_BIT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_BIT_LOCK_BIT_LOCK_SHIFT)) & OCOTP_BIT_LOCK_BIT_LOCK_MASK) -#define OCOTP_BIT_LOCK_RESERVED_MASK (0xFFFF0000U) -#define OCOTP_BIT_LOCK_RESERVED_SHIFT (16U) -#define OCOTP_BIT_LOCK_RESERVED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_BIT_LOCK_RESERVED_SHIFT)) & OCOTP_BIT_LOCK_RESERVED_MASK) -/*! @} */ - -/*! @name LOCKED0 - OTP Controller Program Locked Status Register */ -/*! @{ */ -#define OCOTP_LOCKED0_LOCKED_MASK (0xFFFFFFFFU) -#define OCOTP_LOCKED0_LOCKED_SHIFT (0U) -#define OCOTP_LOCKED0_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED0_LOCKED_SHIFT)) & OCOTP_LOCKED0_LOCKED_MASK) -/*! @} */ - -/*! @name LOCKED1 - OTP Controller Program Locked Status Register */ -/*! @{ */ -#define OCOTP_LOCKED1_LOCKED_MASK (0xFFFFFFFFU) -#define OCOTP_LOCKED1_LOCKED_SHIFT (0U) -#define OCOTP_LOCKED1_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED1_LOCKED_SHIFT)) & OCOTP_LOCKED1_LOCKED_MASK) -/*! @} */ - -/*! @name LOCKED2 - OTP Controller Program Locked Status Register */ -/*! @{ */ -#define OCOTP_LOCKED2_LOCKED_MASK (0xFFFFFFFFU) -#define OCOTP_LOCKED2_LOCKED_SHIFT (0U) -#define OCOTP_LOCKED2_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED2_LOCKED_SHIFT)) & OCOTP_LOCKED2_LOCKED_MASK) -/*! @} */ - -/*! @name LOCKED3 - OTP Controller Program Locked Status Register */ -/*! @{ */ -#define OCOTP_LOCKED3_LOCKED_MASK (0xFFFFFFFFU) -#define OCOTP_LOCKED3_LOCKED_SHIFT (0U) -#define OCOTP_LOCKED3_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED3_LOCKED_SHIFT)) & OCOTP_LOCKED3_LOCKED_MASK) -/*! @} */ - -/*! @name LOCKED4 - OTP Controller Program Locked Status Register */ -/*! @{ */ -#define OCOTP_LOCKED4_LOCKED_MASK (0xFFFFFFFFU) -#define OCOTP_LOCKED4_LOCKED_SHIFT (0U) -#define OCOTP_LOCKED4_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED4_LOCKED_SHIFT)) & OCOTP_LOCKED4_LOCKED_MASK) -/*! @} */ - -/*! @name FUSE000 - Value of fuse word 0 */ -/*! @{ */ -#define OCOTP_FUSE000_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE000_BITS_SHIFT (0U) -#define OCOTP_FUSE000_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE000_BITS_SHIFT)) & OCOTP_FUSE000_BITS_MASK) -/*! @} */ - -/*! @name FUSE001 - Value of fuse word 1 */ -/*! @{ */ -#define OCOTP_FUSE001_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE001_BITS_SHIFT (0U) -#define OCOTP_FUSE001_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE001_BITS_SHIFT)) & OCOTP_FUSE001_BITS_MASK) -/*! @} */ - -/*! @name FUSE002 - Value of fuse word 2 */ -/*! @{ */ -#define OCOTP_FUSE002_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE002_BITS_SHIFT (0U) -#define OCOTP_FUSE002_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE002_BITS_SHIFT)) & OCOTP_FUSE002_BITS_MASK) -/*! @} */ - -/*! @name FUSE003 - Value of fuse word 3 */ -/*! @{ */ -#define OCOTP_FUSE003_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE003_BITS_SHIFT (0U) -#define OCOTP_FUSE003_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE003_BITS_SHIFT)) & OCOTP_FUSE003_BITS_MASK) -/*! @} */ - -/*! @name FUSE004 - Value of fuse word 4 */ -/*! @{ */ -#define OCOTP_FUSE004_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE004_BITS_SHIFT (0U) -#define OCOTP_FUSE004_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE004_BITS_SHIFT)) & OCOTP_FUSE004_BITS_MASK) -/*! @} */ - -/*! @name FUSE005 - Value of fuse word 5 */ -/*! @{ */ -#define OCOTP_FUSE005_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE005_BITS_SHIFT (0U) -#define OCOTP_FUSE005_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE005_BITS_SHIFT)) & OCOTP_FUSE005_BITS_MASK) -/*! @} */ - -/*! @name FUSE006 - Value of fuse word 6 */ -/*! @{ */ -#define OCOTP_FUSE006_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE006_BITS_SHIFT (0U) -#define OCOTP_FUSE006_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE006_BITS_SHIFT)) & OCOTP_FUSE006_BITS_MASK) -/*! @} */ - -/*! @name FUSE007 - Value of fuse word 7 */ -/*! @{ */ -#define OCOTP_FUSE007_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE007_BITS_SHIFT (0U) -#define OCOTP_FUSE007_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE007_BITS_SHIFT)) & OCOTP_FUSE007_BITS_MASK) -/*! @} */ - -/*! @name FUSE008 - Value of fuse word 8 */ -/*! @{ */ -#define OCOTP_FUSE008_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE008_BITS_SHIFT (0U) -#define OCOTP_FUSE008_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE008_BITS_SHIFT)) & OCOTP_FUSE008_BITS_MASK) -/*! @} */ - -/*! @name FUSE009 - Value of fuse word 9 */ -/*! @{ */ -#define OCOTP_FUSE009_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE009_BITS_SHIFT (0U) -#define OCOTP_FUSE009_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE009_BITS_SHIFT)) & OCOTP_FUSE009_BITS_MASK) -/*! @} */ - -/*! @name FUSE010 - Value of fuse word 10 */ -/*! @{ */ -#define OCOTP_FUSE010_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE010_BITS_SHIFT (0U) -#define OCOTP_FUSE010_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE010_BITS_SHIFT)) & OCOTP_FUSE010_BITS_MASK) -/*! @} */ - -/*! @name FUSE011 - Value of fuse word 11 */ -/*! @{ */ -#define OCOTP_FUSE011_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE011_BITS_SHIFT (0U) -#define OCOTP_FUSE011_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE011_BITS_SHIFT)) & OCOTP_FUSE011_BITS_MASK) -/*! @} */ - -/*! @name FUSE012 - Value of fuse word 12 */ -/*! @{ */ -#define OCOTP_FUSE012_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE012_BITS_SHIFT (0U) -#define OCOTP_FUSE012_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE012_BITS_SHIFT)) & OCOTP_FUSE012_BITS_MASK) -/*! @} */ - -/*! @name FUSE013 - Value of fuse word 13 */ -/*! @{ */ -#define OCOTP_FUSE013_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE013_BITS_SHIFT (0U) -#define OCOTP_FUSE013_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE013_BITS_SHIFT)) & OCOTP_FUSE013_BITS_MASK) -/*! @} */ - -/*! @name FUSE014 - Value of fuse word 14 */ -/*! @{ */ -#define OCOTP_FUSE014_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE014_BITS_SHIFT (0U) -#define OCOTP_FUSE014_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE014_BITS_SHIFT)) & OCOTP_FUSE014_BITS_MASK) -/*! @} */ + */ -/*! @name FUSE015 - Value of fuse word 15 */ +/*! @name CTRL - OTP Controller Control and Status Register */ /*! @{ */ -#define OCOTP_FUSE015_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE015_BITS_SHIFT (0U) -#define OCOTP_FUSE015_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE015_BITS_SHIFT)) & OCOTP_FUSE015_BITS_MASK) -/*! @} */ -/*! @name FUSE016 - Value of fuse word 16 */ -/*! @{ */ -#define OCOTP_FUSE016_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE016_BITS_SHIFT (0U) -#define OCOTP_FUSE016_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE016_BITS_SHIFT)) & OCOTP_FUSE016_BITS_MASK) -/*! @} */ +#define OCOTP_CTRL_ADDR_MASK (0x3FFU) +#define OCOTP_CTRL_ADDR_SHIFT (0U) +/*! ADDR - OTP write and read access address register + * 0b0000000000-0b0000001111..Address of one of the 16 supplementary fuse words in OTP memory. + * 0b0000010000-0b0100001111..Address of one of the 256 user fuse words in OTP memory. + */ +#define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK) -/*! @name FUSE017 - Value of fuse word 17 */ -/*! @{ */ -#define OCOTP_FUSE017_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE017_BITS_SHIFT (0U) -#define OCOTP_FUSE017_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE017_BITS_SHIFT)) & OCOTP_FUSE017_BITS_MASK) -/*! @} */ +#define OCOTP_CTRL_BUSY_MASK (0x400U) +#define OCOTP_CTRL_BUSY_SHIFT (10U) +/*! BUSY - OTP controller status bit + * 0b0..No write or read access to OTP started. + * 0b1..Write or read access to OTP started. + */ +#define OCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK) -/*! @name FUSE018 - Value of fuse word 18 */ -/*! @{ */ -#define OCOTP_FUSE018_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE018_BITS_SHIFT (0U) -#define OCOTP_FUSE018_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE018_BITS_SHIFT)) & OCOTP_FUSE018_BITS_MASK) -/*! @} */ +#define OCOTP_CTRL_ERROR_MASK (0x800U) +#define OCOTP_CTRL_ERROR_SHIFT (11U) +/*! ERROR - Locked Region Access Error + * 0b0..No error. + * 0b1..Error - access to a locked region requested. + */ +#define OCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK) -/*! @name FUSE019 - Value of fuse word 19 */ -/*! @{ */ -#define OCOTP_FUSE019_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE019_BITS_SHIFT (0U) -#define OCOTP_FUSE019_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE019_BITS_SHIFT)) & OCOTP_FUSE019_BITS_MASK) -/*! @} */ +#define OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x1000U) +#define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (12U) +/*! RELOAD_SHADOWS - Reload Shadow Registers + * 0b0..Do not force shadow register re-load. + * 0b1..Force shadow register re-load. This bit is cleared automatically after shadow registers are re-loaded. + */ +#define OCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK) -/*! @name FUSE020 - Value of fuse word 20 */ -/*! @{ */ -#define OCOTP_FUSE020_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE020_BITS_SHIFT (0U) -#define OCOTP_FUSE020_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE020_BITS_SHIFT)) & OCOTP_FUSE020_BITS_MASK) -/*! @} */ +#define OCOTP_CTRL_WORDLOCK_MASK (0x8000U) +#define OCOTP_CTRL_WORDLOCK_SHIFT (15U) +/*! WORDLOCK - Lock fuse word + * 0b0..No change to LOCK bit when programming a word using redundancy + * 0b1..LOCK bit for fuse word will be set after successfully programming a word using redundancy + */ +#define OCOTP_CTRL_WORDLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WORDLOCK_SHIFT)) & OCOTP_CTRL_WORDLOCK_MASK) -/*! @name FUSE021 - Value of fuse word 21 */ -/*! @{ */ -#define OCOTP_FUSE021_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE021_BITS_SHIFT (0U) -#define OCOTP_FUSE021_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE021_BITS_SHIFT)) & OCOTP_FUSE021_BITS_MASK) +#define OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_WR_UNLOCK_SHIFT (16U) +/*! WR_UNLOCK - Write unlock + * 0b0000000000000000..OTP write access is locked. + * 0b0011111001110111..OTP write access is unlocked. + */ +#define OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK) /*! @} */ -/*! @name FUSE022 - Value of fuse word 22 */ +/*! @name CTRL_SET - OTP Controller Control and Status Register */ /*! @{ */ -#define OCOTP_FUSE022_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE022_BITS_SHIFT (0U) -#define OCOTP_FUSE022_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE022_BITS_SHIFT)) & OCOTP_FUSE022_BITS_MASK) -/*! @} */ -/*! @name FUSE023 - Value of fuse word 23 */ -/*! @{ */ -#define OCOTP_FUSE023_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE023_BITS_SHIFT (0U) -#define OCOTP_FUSE023_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE023_BITS_SHIFT)) & OCOTP_FUSE023_BITS_MASK) -/*! @} */ +#define OCOTP_CTRL_SET_ADDR_MASK (0x3FFU) +#define OCOTP_CTRL_SET_ADDR_SHIFT (0U) +/*! ADDR - OTP write and read access address register + */ +#define OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK) -/*! @name FUSE024 - Value of fuse word 24 */ -/*! @{ */ -#define OCOTP_FUSE024_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE024_BITS_SHIFT (0U) -#define OCOTP_FUSE024_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE024_BITS_SHIFT)) & OCOTP_FUSE024_BITS_MASK) -/*! @} */ +#define OCOTP_CTRL_SET_BUSY_MASK (0x400U) +#define OCOTP_CTRL_SET_BUSY_SHIFT (10U) +/*! BUSY - OTP controller status bit + */ +#define OCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK) -/*! @name FUSE025 - Value of fuse word 25 */ -/*! @{ */ -#define OCOTP_FUSE025_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE025_BITS_SHIFT (0U) -#define OCOTP_FUSE025_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE025_BITS_SHIFT)) & OCOTP_FUSE025_BITS_MASK) -/*! @} */ +#define OCOTP_CTRL_SET_ERROR_MASK (0x800U) +#define OCOTP_CTRL_SET_ERROR_SHIFT (11U) +/*! ERROR - Locked Region Access Error + */ +#define OCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK) -/*! @name FUSE026 - Value of fuse word 26 */ -/*! @{ */ -#define OCOTP_FUSE026_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE026_BITS_SHIFT (0U) -#define OCOTP_FUSE026_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE026_BITS_SHIFT)) & OCOTP_FUSE026_BITS_MASK) -/*! @} */ +#define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x1000U) +#define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (12U) +/*! RELOAD_SHADOWS - Reload Shadow Registers + */ +#define OCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK) -/*! @name FUSE027 - Value of fuse word 27 */ -/*! @{ */ -#define OCOTP_FUSE027_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE027_BITS_SHIFT (0U) -#define OCOTP_FUSE027_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE027_BITS_SHIFT)) & OCOTP_FUSE027_BITS_MASK) -/*! @} */ +#define OCOTP_CTRL_SET_WORDLOCK_MASK (0x8000U) +#define OCOTP_CTRL_SET_WORDLOCK_SHIFT (15U) +/*! WORDLOCK - Lock fuse word + */ +#define OCOTP_CTRL_SET_WORDLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WORDLOCK_SHIFT)) & OCOTP_CTRL_SET_WORDLOCK_MASK) -/*! @name FUSE028 - Value of fuse word 28 */ -/*! @{ */ -#define OCOTP_FUSE028_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE028_BITS_SHIFT (0U) -#define OCOTP_FUSE028_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE028_BITS_SHIFT)) & OCOTP_FUSE028_BITS_MASK) +#define OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U) +/*! WR_UNLOCK - Write unlock + */ +#define OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK) /*! @} */ -/*! @name FUSE029 - Value of fuse word 29 */ +/*! @name CTRL_CLR - OTP Controller Control and Status Register */ /*! @{ */ -#define OCOTP_FUSE029_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE029_BITS_SHIFT (0U) -#define OCOTP_FUSE029_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE029_BITS_SHIFT)) & OCOTP_FUSE029_BITS_MASK) -/*! @} */ -/*! @name FUSE030 - Value of fuse word 30 */ -/*! @{ */ -#define OCOTP_FUSE030_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE030_BITS_SHIFT (0U) -#define OCOTP_FUSE030_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE030_BITS_SHIFT)) & OCOTP_FUSE030_BITS_MASK) -/*! @} */ +#define OCOTP_CTRL_CLR_ADDR_MASK (0x3FFU) +#define OCOTP_CTRL_CLR_ADDR_SHIFT (0U) +/*! ADDR - OTP write and read access address register + */ +#define OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK) -/*! @name FUSE031 - Value of fuse word 31 */ -/*! @{ */ -#define OCOTP_FUSE031_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE031_BITS_SHIFT (0U) -#define OCOTP_FUSE031_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE031_BITS_SHIFT)) & OCOTP_FUSE031_BITS_MASK) -/*! @} */ +#define OCOTP_CTRL_CLR_BUSY_MASK (0x400U) +#define OCOTP_CTRL_CLR_BUSY_SHIFT (10U) +/*! BUSY - OTP controller status bit + */ +#define OCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK) -/*! @name FUSE032 - Value of fuse word 32 */ -/*! @{ */ -#define OCOTP_FUSE032_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE032_BITS_SHIFT (0U) -#define OCOTP_FUSE032_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE032_BITS_SHIFT)) & OCOTP_FUSE032_BITS_MASK) -/*! @} */ +#define OCOTP_CTRL_CLR_ERROR_MASK (0x800U) +#define OCOTP_CTRL_CLR_ERROR_SHIFT (11U) +/*! ERROR - Locked Region Access Error + */ +#define OCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK) -/*! @name FUSE033 - Value of fuse word 33 */ -/*! @{ */ -#define OCOTP_FUSE033_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE033_BITS_SHIFT (0U) -#define OCOTP_FUSE033_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE033_BITS_SHIFT)) & OCOTP_FUSE033_BITS_MASK) -/*! @} */ +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x1000U) +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (12U) +/*! RELOAD_SHADOWS - Reload Shadow Registers + */ +#define OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK) -/*! @name FUSE034 - Value of fuse word 34 */ -/*! @{ */ -#define OCOTP_FUSE034_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE034_BITS_SHIFT (0U) -#define OCOTP_FUSE034_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE034_BITS_SHIFT)) & OCOTP_FUSE034_BITS_MASK) -/*! @} */ +#define OCOTP_CTRL_CLR_WORDLOCK_MASK (0x8000U) +#define OCOTP_CTRL_CLR_WORDLOCK_SHIFT (15U) +/*! WORDLOCK - Lock fuse word + */ +#define OCOTP_CTRL_CLR_WORDLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WORDLOCK_SHIFT)) & OCOTP_CTRL_CLR_WORDLOCK_MASK) -/*! @name FUSE035 - Value of fuse word 35 */ -/*! @{ */ -#define OCOTP_FUSE035_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE035_BITS_SHIFT (0U) -#define OCOTP_FUSE035_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE035_BITS_SHIFT)) & OCOTP_FUSE035_BITS_MASK) +#define OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U) +/*! WR_UNLOCK - Write unlock + */ +#define OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK) /*! @} */ -/*! @name FUSE036 - Value of fuse word 36 */ +/*! @name CTRL_TOG - OTP Controller Control and Status Register */ /*! @{ */ -#define OCOTP_FUSE036_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE036_BITS_SHIFT (0U) -#define OCOTP_FUSE036_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE036_BITS_SHIFT)) & OCOTP_FUSE036_BITS_MASK) -/*! @} */ -/*! @name FUSE037 - Value of fuse word 37 */ -/*! @{ */ -#define OCOTP_FUSE037_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE037_BITS_SHIFT (0U) -#define OCOTP_FUSE037_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE037_BITS_SHIFT)) & OCOTP_FUSE037_BITS_MASK) -/*! @} */ +#define OCOTP_CTRL_TOG_ADDR_MASK (0x3FFU) +#define OCOTP_CTRL_TOG_ADDR_SHIFT (0U) +/*! ADDR - OTP write and read access address register + */ +#define OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK) -/*! @name FUSE038 - Value of fuse word 38 */ -/*! @{ */ -#define OCOTP_FUSE038_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE038_BITS_SHIFT (0U) -#define OCOTP_FUSE038_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE038_BITS_SHIFT)) & OCOTP_FUSE038_BITS_MASK) -/*! @} */ +#define OCOTP_CTRL_TOG_BUSY_MASK (0x400U) +#define OCOTP_CTRL_TOG_BUSY_SHIFT (10U) +/*! BUSY - OTP controller status bit + */ +#define OCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK) -/*! @name FUSE039 - Value of fuse word 39 */ -/*! @{ */ -#define OCOTP_FUSE039_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE039_BITS_SHIFT (0U) -#define OCOTP_FUSE039_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE039_BITS_SHIFT)) & OCOTP_FUSE039_BITS_MASK) -/*! @} */ +#define OCOTP_CTRL_TOG_ERROR_MASK (0x800U) +#define OCOTP_CTRL_TOG_ERROR_SHIFT (11U) +/*! ERROR - Locked Region Access Error + */ +#define OCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK) -/*! @name FUSE040 - Value of fuse word 40 */ -/*! @{ */ -#define OCOTP_FUSE040_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE040_BITS_SHIFT (0U) -#define OCOTP_FUSE040_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE040_BITS_SHIFT)) & OCOTP_FUSE040_BITS_MASK) -/*! @} */ +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x1000U) +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (12U) +/*! RELOAD_SHADOWS - Reload Shadow Registers + */ +#define OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK) -/*! @name FUSE041 - Value of fuse word 41 */ -/*! @{ */ -#define OCOTP_FUSE041_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE041_BITS_SHIFT (0U) -#define OCOTP_FUSE041_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE041_BITS_SHIFT)) & OCOTP_FUSE041_BITS_MASK) -/*! @} */ +#define OCOTP_CTRL_TOG_WORDLOCK_MASK (0x8000U) +#define OCOTP_CTRL_TOG_WORDLOCK_SHIFT (15U) +/*! WORDLOCK - Lock fuse word + */ +#define OCOTP_CTRL_TOG_WORDLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WORDLOCK_SHIFT)) & OCOTP_CTRL_TOG_WORDLOCK_MASK) -/*! @name FUSE042 - Value of fuse word 42 */ -/*! @{ */ -#define OCOTP_FUSE042_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE042_BITS_SHIFT (0U) -#define OCOTP_FUSE042_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE042_BITS_SHIFT)) & OCOTP_FUSE042_BITS_MASK) +#define OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U) +#define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U) +/*! WR_UNLOCK - Write unlock + */ +#define OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK) /*! @} */ -/*! @name FUSE043 - Value of fuse word 43 */ +/*! @name PDN - OTP Controller PDN Register */ /*! @{ */ -#define OCOTP_FUSE043_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE043_BITS_SHIFT (0U) -#define OCOTP_FUSE043_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE043_BITS_SHIFT)) & OCOTP_FUSE043_BITS_MASK) -/*! @} */ -/*! @name FUSE044 - Value of fuse word 44 */ -/*! @{ */ -#define OCOTP_FUSE044_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE044_BITS_SHIFT (0U) -#define OCOTP_FUSE044_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE044_BITS_SHIFT)) & OCOTP_FUSE044_BITS_MASK) +#define OCOTP_PDN_PDN_MASK (0x1U) +#define OCOTP_PDN_PDN_SHIFT (0U) +/*! PDN - PDN value + * 0b0..OTP memory is not powered + * 0b1..OTP memory is powered + */ +#define OCOTP_PDN_PDN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_PDN_PDN_SHIFT)) & OCOTP_PDN_PDN_MASK) /*! @} */ -/*! @name FUSE045 - Value of fuse word 45 */ +/*! @name DATA - OTP Controller Write Data Register */ /*! @{ */ -#define OCOTP_FUSE045_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE045_BITS_SHIFT (0U) -#define OCOTP_FUSE045_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE045_BITS_SHIFT)) & OCOTP_FUSE045_BITS_MASK) -/*! @} */ -/*! @name FUSE046 - Value of fuse word 46 */ -/*! @{ */ -#define OCOTP_FUSE046_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE046_BITS_SHIFT (0U) -#define OCOTP_FUSE046_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE046_BITS_SHIFT)) & OCOTP_FUSE046_BITS_MASK) +#define OCOTP_DATA_DATA_MASK (0xFFFFFFFFU) +#define OCOTP_DATA_DATA_SHIFT (0U) +/*! DATA - Data + */ +#define OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK) /*! @} */ -/*! @name FUSE047 - Value of fuse word 47 */ +/*! @name READ_CTRL - OTP Controller Read Control Register */ /*! @{ */ -#define OCOTP_FUSE047_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE047_BITS_SHIFT (0U) -#define OCOTP_FUSE047_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE047_BITS_SHIFT)) & OCOTP_FUSE047_BITS_MASK) -/*! @} */ -/*! @name FUSE048 - Value of fuse word 47 */ -/*! @{ */ -#define OCOTP_FUSE048_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE048_BITS_SHIFT (0U) -#define OCOTP_FUSE048_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE048_BITS_SHIFT)) & OCOTP_FUSE048_BITS_MASK) -/*! @} */ +#define OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U) +#define OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U) +/*! READ_FUSE - Read Fuse + * 0b0..Do not initiate a read from OTP + * 0b1..Initiate a read from OTP + */ +#define OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK) -/*! @name FUSE049 - Value of fuse word 49 */ -/*! @{ */ -#define OCOTP_FUSE049_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE049_BITS_SHIFT (0U) -#define OCOTP_FUSE049_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE049_BITS_SHIFT)) & OCOTP_FUSE049_BITS_MASK) -/*! @} */ +#define OCOTP_READ_CTRL_READ_FUSE_CNTR_MASK (0x6U) +#define OCOTP_READ_CTRL_READ_FUSE_CNTR_SHIFT (1U) +/*! READ_FUSE_CNTR - Number of words to read. + * 0b00..1 word + * 0b01..2 words + * 0b10..3 words + * 0b11..4 words + */ +#define OCOTP_READ_CTRL_READ_FUSE_CNTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_CNTR_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_CNTR_MASK) -/*! @name FUSE050 - Value of fuse word 50 */ -/*! @{ */ -#define OCOTP_FUSE050_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE050_BITS_SHIFT (0U) -#define OCOTP_FUSE050_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE050_BITS_SHIFT)) & OCOTP_FUSE050_BITS_MASK) -/*! @} */ +#define OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA_MASK (0x8U) +#define OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA_SHIFT (3U) +/*! READ_FUSE_DONE_INTR_ENA - Enable read-done interrupt + * 0b0..Disable + * 0b1..Enable + */ +#define OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA_MASK) -/*! @name FUSE051 - Value of fuse word 51 */ -/*! @{ */ -#define OCOTP_FUSE051_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE051_BITS_SHIFT (0U) -#define OCOTP_FUSE051_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE051_BITS_SHIFT)) & OCOTP_FUSE051_BITS_MASK) +#define OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA_MASK (0x10U) +#define OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA_SHIFT (4U) +/*! READ_FUSE_ERROR_INTR_ENA - Enable read-error interrupt + * 0b0..Disable + * 0b1..Enable + */ +#define OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA_MASK) /*! @} */ -/*! @name FUSE052 - Value of fuse word 52 */ +/*! @name OUT_STATUS - 8K OTP Memory STATUS Register */ /*! @{ */ -#define OCOTP_FUSE052_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE052_BITS_SHIFT (0U) -#define OCOTP_FUSE052_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE052_BITS_SHIFT)) & OCOTP_FUSE052_BITS_MASK) -/*! @} */ -/*! @name FUSE053 - Value of fuse word 53 */ -/*! @{ */ -#define OCOTP_FUSE053_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE053_BITS_SHIFT (0U) -#define OCOTP_FUSE053_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE053_BITS_SHIFT)) & OCOTP_FUSE053_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_SEC_MASK (0x200U) +#define OCOTP_OUT_STATUS_SEC_SHIFT (9U) +/*! SEC - Single Error Correct + */ +#define OCOTP_OUT_STATUS_SEC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SEC_SHIFT)) & OCOTP_OUT_STATUS_SEC_MASK) -/*! @name FUSE054 - Value of fuse word 54 */ -/*! @{ */ -#define OCOTP_FUSE054_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE054_BITS_SHIFT (0U) -#define OCOTP_FUSE054_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE054_BITS_SHIFT)) & OCOTP_FUSE054_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_DED_MASK (0x400U) +#define OCOTP_OUT_STATUS_DED_SHIFT (10U) +/*! DED - Double error detect + */ +#define OCOTP_OUT_STATUS_DED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED_SHIFT)) & OCOTP_OUT_STATUS_DED_MASK) -/*! @name FUSE055 - Value of fuse word 55 */ -/*! @{ */ -#define OCOTP_FUSE055_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE055_BITS_SHIFT (0U) -#define OCOTP_FUSE055_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE055_BITS_SHIFT)) & OCOTP_FUSE055_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_LOCKED_MASK (0x800U) +#define OCOTP_OUT_STATUS_LOCKED_SHIFT (11U) +/*! LOCKED - Word Locked + */ +#define OCOTP_OUT_STATUS_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_LOCKED_SHIFT)) & OCOTP_OUT_STATUS_LOCKED_MASK) -/*! @name FUSE056 - Value of fuse word 56 */ -/*! @{ */ -#define OCOTP_FUSE056_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE056_BITS_SHIFT (0U) -#define OCOTP_FUSE056_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE056_BITS_SHIFT)) & OCOTP_FUSE056_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_PROGFAIL_MASK (0x1000U) +#define OCOTP_OUT_STATUS_PROGFAIL_SHIFT (12U) +/*! PROGFAIL - Programming failed + */ +#define OCOTP_OUT_STATUS_PROGFAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS_PROGFAIL_MASK) -/*! @name FUSE057 - Value of fuse word 57 */ -/*! @{ */ -#define OCOTP_FUSE057_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE057_BITS_SHIFT (0U) -#define OCOTP_FUSE057_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE057_BITS_SHIFT)) & OCOTP_FUSE057_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_ACK_MASK (0x2000U) +#define OCOTP_OUT_STATUS_ACK_SHIFT (13U) +/*! ACK - Acknowledge + */ +#define OCOTP_OUT_STATUS_ACK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_ACK_SHIFT)) & OCOTP_OUT_STATUS_ACK_MASK) -/*! @name FUSE058 - Value of fuse word 58 */ -/*! @{ */ -#define OCOTP_FUSE058_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE058_BITS_SHIFT (0U) -#define OCOTP_FUSE058_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE058_BITS_SHIFT)) & OCOTP_FUSE058_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_PWOK_MASK (0x4000U) +#define OCOTP_OUT_STATUS_PWOK_SHIFT (14U) +/*! PWOK - Power OK + */ +#define OCOTP_OUT_STATUS_PWOK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_PWOK_SHIFT)) & OCOTP_OUT_STATUS_PWOK_MASK) -/*! @name FUSE059 - Value of fuse word 59 */ -/*! @{ */ -#define OCOTP_FUSE059_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE059_BITS_SHIFT (0U) -#define OCOTP_FUSE059_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE059_BITS_SHIFT)) & OCOTP_FUSE059_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_FLAGSTATE_MASK (0x78000U) +#define OCOTP_OUT_STATUS_FLAGSTATE_SHIFT (15U) +/*! FLAGSTATE - Flag state + */ +#define OCOTP_OUT_STATUS_FLAGSTATE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS_FLAGSTATE_MASK) -/*! @name FUSE060 - Value of fuse word 60 */ -/*! @{ */ -#define OCOTP_FUSE060_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE060_BITS_SHIFT (0U) -#define OCOTP_FUSE060_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE060_BITS_SHIFT)) & OCOTP_FUSE060_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_SEC_RELOAD_MASK (0x80000U) +#define OCOTP_OUT_STATUS_SEC_RELOAD_SHIFT (19U) +/*! SEC_RELOAD - Indicates single error correction occured on reload + */ +#define OCOTP_OUT_STATUS_SEC_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_SEC_RELOAD_MASK) -/*! @name FUSE061 - Value of fuse word 61 */ -/*! @{ */ -#define OCOTP_FUSE061_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE061_BITS_SHIFT (0U) -#define OCOTP_FUSE061_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE061_BITS_SHIFT)) & OCOTP_FUSE061_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_DED_RELOAD_MASK (0x100000U) +#define OCOTP_OUT_STATUS_DED_RELOAD_SHIFT (20U) +/*! DED_RELOAD - Indicates double error detection occured on reload + */ +#define OCOTP_OUT_STATUS_DED_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_DED_RELOAD_MASK) -/*! @name FUSE062 - Value of fuse word 62 */ -/*! @{ */ -#define OCOTP_FUSE062_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE062_BITS_SHIFT (0U) -#define OCOTP_FUSE062_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE062_BITS_SHIFT)) & OCOTP_FUSE062_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_CALIBRATED_MASK (0x200000U) +#define OCOTP_OUT_STATUS_CALIBRATED_SHIFT (21U) +/*! CALIBRATED - Calibrated status + */ +#define OCOTP_OUT_STATUS_CALIBRATED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS_CALIBRATED_MASK) -/*! @name FUSE063 - Value of fuse word 63 */ -/*! @{ */ -#define OCOTP_FUSE063_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE063_BITS_SHIFT (0U) -#define OCOTP_FUSE063_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE063_BITS_SHIFT)) & OCOTP_FUSE063_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_READ_DONE_INTR_MASK (0x400000U) +#define OCOTP_OUT_STATUS_READ_DONE_INTR_SHIFT (22U) +/*! READ_DONE_INTR - Read fuse done + */ +#define OCOTP_OUT_STATUS_READ_DONE_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS_READ_DONE_INTR_MASK) -/*! @name FUSE064 - Value of fuse word 64 */ -/*! @{ */ -#define OCOTP_FUSE064_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE064_BITS_SHIFT (0U) -#define OCOTP_FUSE064_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE064_BITS_SHIFT)) & OCOTP_FUSE064_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_READ_ERROR_INTR_MASK (0x800000U) +#define OCOTP_OUT_STATUS_READ_ERROR_INTR_SHIFT (23U) +/*! READ_ERROR_INTR - Fuse read error + * 0b0..Read operation finished with out any error + * 0b1..Read operation finished with an error + */ +#define OCOTP_OUT_STATUS_READ_ERROR_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS_READ_ERROR_INTR_MASK) -/*! @name FUSE065 - Value of fuse word 65 */ -/*! @{ */ -#define OCOTP_FUSE065_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE065_BITS_SHIFT (0U) -#define OCOTP_FUSE065_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE065_BITS_SHIFT)) & OCOTP_FUSE065_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_DED0_MASK (0x1000000U) +#define OCOTP_OUT_STATUS_DED0_SHIFT (24U) +/*! DED0 - Double error detect + */ +#define OCOTP_OUT_STATUS_DED0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED0_SHIFT)) & OCOTP_OUT_STATUS_DED0_MASK) -/*! @name FUSE066 - Value of fuse word 66 */ -/*! @{ */ -#define OCOTP_FUSE066_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE066_BITS_SHIFT (0U) -#define OCOTP_FUSE066_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE066_BITS_SHIFT)) & OCOTP_FUSE066_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_DED1_MASK (0x2000000U) +#define OCOTP_OUT_STATUS_DED1_SHIFT (25U) +/*! DED1 - Double error detect + */ +#define OCOTP_OUT_STATUS_DED1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED1_SHIFT)) & OCOTP_OUT_STATUS_DED1_MASK) -/*! @name FUSE067 - Value of fuse word 67 */ -/*! @{ */ -#define OCOTP_FUSE067_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE067_BITS_SHIFT (0U) -#define OCOTP_FUSE067_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE067_BITS_SHIFT)) & OCOTP_FUSE067_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_DED2_MASK (0x4000000U) +#define OCOTP_OUT_STATUS_DED2_SHIFT (26U) +/*! DED2 - Double error detect + */ +#define OCOTP_OUT_STATUS_DED2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED2_SHIFT)) & OCOTP_OUT_STATUS_DED2_MASK) -/*! @name FUSE068 - Value of fuse word 68 */ -/*! @{ */ -#define OCOTP_FUSE068_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE068_BITS_SHIFT (0U) -#define OCOTP_FUSE068_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE068_BITS_SHIFT)) & OCOTP_FUSE068_BITS_MASK) +#define OCOTP_OUT_STATUS_DED3_MASK (0x8000000U) +#define OCOTP_OUT_STATUS_DED3_SHIFT (27U) +/*! DED3 - Double error detect + */ +#define OCOTP_OUT_STATUS_DED3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED3_SHIFT)) & OCOTP_OUT_STATUS_DED3_MASK) /*! @} */ -/*! @name FUSE069 - Value of fuse word 69 */ +/*! @name OUT_STATUS_SET - 8K OTP Memory STATUS Register */ /*! @{ */ -#define OCOTP_FUSE069_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE069_BITS_SHIFT (0U) -#define OCOTP_FUSE069_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE069_BITS_SHIFT)) & OCOTP_FUSE069_BITS_MASK) -/*! @} */ -/*! @name FUSE070 - Value of fuse word 70 */ -/*! @{ */ -#define OCOTP_FUSE070_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE070_BITS_SHIFT (0U) -#define OCOTP_FUSE070_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE070_BITS_SHIFT)) & OCOTP_FUSE070_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_SET_SEC_MASK (0x200U) +#define OCOTP_OUT_STATUS_SET_SEC_SHIFT (9U) +/*! SEC - Single Error Correct + */ +#define OCOTP_OUT_STATUS_SET_SEC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_SEC_SHIFT)) & OCOTP_OUT_STATUS_SET_SEC_MASK) -/*! @name FUSE071 - Value of fuse word 71 */ -/*! @{ */ -#define OCOTP_FUSE071_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE071_BITS_SHIFT (0U) -#define OCOTP_FUSE071_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE071_BITS_SHIFT)) & OCOTP_FUSE071_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_SET_DED_MASK (0x400U) +#define OCOTP_OUT_STATUS_SET_DED_SHIFT (10U) +/*! DED - Double error detect + */ +#define OCOTP_OUT_STATUS_SET_DED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED_SHIFT)) & OCOTP_OUT_STATUS_SET_DED_MASK) -/*! @name FUSE072 - Value of fuse word 72 */ -/*! @{ */ -#define OCOTP_FUSE072_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE072_BITS_SHIFT (0U) -#define OCOTP_FUSE072_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE072_BITS_SHIFT)) & OCOTP_FUSE072_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_SET_LOCKED_MASK (0x800U) +#define OCOTP_OUT_STATUS_SET_LOCKED_SHIFT (11U) +/*! LOCKED - Word Locked + */ +#define OCOTP_OUT_STATUS_SET_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_LOCKED_SHIFT)) & OCOTP_OUT_STATUS_SET_LOCKED_MASK) -/*! @name FUSE073 - Value of fuse word 73 */ -/*! @{ */ -#define OCOTP_FUSE073_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE073_BITS_SHIFT (0U) -#define OCOTP_FUSE073_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE073_BITS_SHIFT)) & OCOTP_FUSE073_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_SET_PROGFAIL_MASK (0x1000U) +#define OCOTP_OUT_STATUS_SET_PROGFAIL_SHIFT (12U) +/*! PROGFAIL - Programming failed + */ +#define OCOTP_OUT_STATUS_SET_PROGFAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS_SET_PROGFAIL_MASK) -/*! @name FUSE074 - Value of fuse word 74 */ -/*! @{ */ -#define OCOTP_FUSE074_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE074_BITS_SHIFT (0U) -#define OCOTP_FUSE074_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE074_BITS_SHIFT)) & OCOTP_FUSE074_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_SET_ACK_MASK (0x2000U) +#define OCOTP_OUT_STATUS_SET_ACK_SHIFT (13U) +/*! ACK - Acknowledge + */ +#define OCOTP_OUT_STATUS_SET_ACK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_ACK_SHIFT)) & OCOTP_OUT_STATUS_SET_ACK_MASK) -/*! @name FUSE075 - Value of fuse word 75 */ -/*! @{ */ -#define OCOTP_FUSE075_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE075_BITS_SHIFT (0U) -#define OCOTP_FUSE075_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE075_BITS_SHIFT)) & OCOTP_FUSE075_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_SET_PWOK_MASK (0x4000U) +#define OCOTP_OUT_STATUS_SET_PWOK_SHIFT (14U) +/*! PWOK - Power OK + */ +#define OCOTP_OUT_STATUS_SET_PWOK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_PWOK_SHIFT)) & OCOTP_OUT_STATUS_SET_PWOK_MASK) -/*! @name FUSE076 - Value of fuse word 76 */ -/*! @{ */ -#define OCOTP_FUSE076_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE076_BITS_SHIFT (0U) -#define OCOTP_FUSE076_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE076_BITS_SHIFT)) & OCOTP_FUSE076_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_SET_FLAGSTATE_MASK (0x78000U) +#define OCOTP_OUT_STATUS_SET_FLAGSTATE_SHIFT (15U) +/*! FLAGSTATE - Flag state + */ +#define OCOTP_OUT_STATUS_SET_FLAGSTATE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS_SET_FLAGSTATE_MASK) -/*! @name FUSE077 - Value of fuse word 77 */ -/*! @{ */ -#define OCOTP_FUSE077_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE077_BITS_SHIFT (0U) -#define OCOTP_FUSE077_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE077_BITS_SHIFT)) & OCOTP_FUSE077_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_SET_SEC_RELOAD_MASK (0x80000U) +#define OCOTP_OUT_STATUS_SET_SEC_RELOAD_SHIFT (19U) +/*! SEC_RELOAD - Indicates single error correction occured on reload + */ +#define OCOTP_OUT_STATUS_SET_SEC_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_SET_SEC_RELOAD_MASK) -/*! @name FUSE078 - Value of fuse word 78 */ -/*! @{ */ -#define OCOTP_FUSE078_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE078_BITS_SHIFT (0U) -#define OCOTP_FUSE078_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE078_BITS_SHIFT)) & OCOTP_FUSE078_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_SET_DED_RELOAD_MASK (0x100000U) +#define OCOTP_OUT_STATUS_SET_DED_RELOAD_SHIFT (20U) +/*! DED_RELOAD - Indicates double error detection occured on reload + */ +#define OCOTP_OUT_STATUS_SET_DED_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_SET_DED_RELOAD_MASK) -/*! @name FUSE079 - Value of fuse word 79 */ -/*! @{ */ -#define OCOTP_FUSE079_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE079_BITS_SHIFT (0U) -#define OCOTP_FUSE079_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE079_BITS_SHIFT)) & OCOTP_FUSE079_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_SET_CALIBRATED_MASK (0x200000U) +#define OCOTP_OUT_STATUS_SET_CALIBRATED_SHIFT (21U) +/*! CALIBRATED - Calibrated status + */ +#define OCOTP_OUT_STATUS_SET_CALIBRATED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS_SET_CALIBRATED_MASK) -/*! @name FUSE080 - Value of fuse word 80 */ -/*! @{ */ -#define OCOTP_FUSE080_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE080_BITS_SHIFT (0U) -#define OCOTP_FUSE080_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE080_BITS_SHIFT)) & OCOTP_FUSE080_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_SET_READ_DONE_INTR_MASK (0x400000U) +#define OCOTP_OUT_STATUS_SET_READ_DONE_INTR_SHIFT (22U) +/*! READ_DONE_INTR - Read fuse done + */ +#define OCOTP_OUT_STATUS_SET_READ_DONE_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS_SET_READ_DONE_INTR_MASK) -/*! @name FUSE081 - Value of fuse word 81 */ -/*! @{ */ -#define OCOTP_FUSE081_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE081_BITS_SHIFT (0U) -#define OCOTP_FUSE081_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE081_BITS_SHIFT)) & OCOTP_FUSE081_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_SET_READ_ERROR_INTR_MASK (0x800000U) +#define OCOTP_OUT_STATUS_SET_READ_ERROR_INTR_SHIFT (23U) +/*! READ_ERROR_INTR - Fuse read error + */ +#define OCOTP_OUT_STATUS_SET_READ_ERROR_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS_SET_READ_ERROR_INTR_MASK) -/*! @name FUSE082 - Value of fuse word 82 */ -/*! @{ */ -#define OCOTP_FUSE082_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE082_BITS_SHIFT (0U) -#define OCOTP_FUSE082_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE082_BITS_SHIFT)) & OCOTP_FUSE082_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_SET_DED0_MASK (0x1000000U) +#define OCOTP_OUT_STATUS_SET_DED0_SHIFT (24U) +/*! DED0 - Double error detect + */ +#define OCOTP_OUT_STATUS_SET_DED0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED0_SHIFT)) & OCOTP_OUT_STATUS_SET_DED0_MASK) -/*! @name FUSE083 - Value of fuse word 83 */ -/*! @{ */ -#define OCOTP_FUSE083_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE083_BITS_SHIFT (0U) -#define OCOTP_FUSE083_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE083_BITS_SHIFT)) & OCOTP_FUSE083_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_SET_DED1_MASK (0x2000000U) +#define OCOTP_OUT_STATUS_SET_DED1_SHIFT (25U) +/*! DED1 - Double error detect + */ +#define OCOTP_OUT_STATUS_SET_DED1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED1_SHIFT)) & OCOTP_OUT_STATUS_SET_DED1_MASK) -/*! @name FUSE084 - Value of fuse word 84 */ -/*! @{ */ -#define OCOTP_FUSE084_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE084_BITS_SHIFT (0U) -#define OCOTP_FUSE084_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE084_BITS_SHIFT)) & OCOTP_FUSE084_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_SET_DED2_MASK (0x4000000U) +#define OCOTP_OUT_STATUS_SET_DED2_SHIFT (26U) +/*! DED2 - Double error detect + */ +#define OCOTP_OUT_STATUS_SET_DED2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED2_SHIFT)) & OCOTP_OUT_STATUS_SET_DED2_MASK) -/*! @name FUSE085 - Value of fuse word 85 */ -/*! @{ */ -#define OCOTP_FUSE085_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE085_BITS_SHIFT (0U) -#define OCOTP_FUSE085_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE085_BITS_SHIFT)) & OCOTP_FUSE085_BITS_MASK) +#define OCOTP_OUT_STATUS_SET_DED3_MASK (0x8000000U) +#define OCOTP_OUT_STATUS_SET_DED3_SHIFT (27U) +/*! DED3 - Double error detect + */ +#define OCOTP_OUT_STATUS_SET_DED3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED3_SHIFT)) & OCOTP_OUT_STATUS_SET_DED3_MASK) /*! @} */ -/*! @name FUSE086 - Value of fuse word 86 */ +/*! @name OUT_STATUS_CLR - 8K OTP Memory STATUS Register */ /*! @{ */ -#define OCOTP_FUSE086_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE086_BITS_SHIFT (0U) -#define OCOTP_FUSE086_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE086_BITS_SHIFT)) & OCOTP_FUSE086_BITS_MASK) -/*! @} */ -/*! @name FUSE087 - Value of fuse word 87 */ -/*! @{ */ -#define OCOTP_FUSE087_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE087_BITS_SHIFT (0U) -#define OCOTP_FUSE087_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE087_BITS_SHIFT)) & OCOTP_FUSE087_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_CLR_SEC_MASK (0x200U) +#define OCOTP_OUT_STATUS_CLR_SEC_SHIFT (9U) +/*! SEC - Single Error Correct + */ +#define OCOTP_OUT_STATUS_CLR_SEC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_SEC_SHIFT)) & OCOTP_OUT_STATUS_CLR_SEC_MASK) -/*! @name FUSE088 - Value of fuse word 88 */ -/*! @{ */ -#define OCOTP_FUSE088_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE088_BITS_SHIFT (0U) -#define OCOTP_FUSE088_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE088_BITS_SHIFT)) & OCOTP_FUSE088_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_CLR_DED_MASK (0x400U) +#define OCOTP_OUT_STATUS_CLR_DED_SHIFT (10U) +/*! DED - Double error detect + */ +#define OCOTP_OUT_STATUS_CLR_DED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED_MASK) -/*! @name FUSE089 - Value of fuse word 89 */ -/*! @{ */ -#define OCOTP_FUSE089_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE089_BITS_SHIFT (0U) -#define OCOTP_FUSE089_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE089_BITS_SHIFT)) & OCOTP_FUSE089_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_CLR_LOCKED_MASK (0x800U) +#define OCOTP_OUT_STATUS_CLR_LOCKED_SHIFT (11U) +/*! LOCKED - Word Locked + */ +#define OCOTP_OUT_STATUS_CLR_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_LOCKED_SHIFT)) & OCOTP_OUT_STATUS_CLR_LOCKED_MASK) -/*! @name FUSE090 - Value of fuse word 90 */ -/*! @{ */ -#define OCOTP_FUSE090_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE090_BITS_SHIFT (0U) -#define OCOTP_FUSE090_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE090_BITS_SHIFT)) & OCOTP_FUSE090_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_CLR_PROGFAIL_MASK (0x1000U) +#define OCOTP_OUT_STATUS_CLR_PROGFAIL_SHIFT (12U) +/*! PROGFAIL - Programming failed + */ +#define OCOTP_OUT_STATUS_CLR_PROGFAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS_CLR_PROGFAIL_MASK) -/*! @name FUSE091 - Value of fuse word 91 */ -/*! @{ */ -#define OCOTP_FUSE091_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE091_BITS_SHIFT (0U) -#define OCOTP_FUSE091_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE091_BITS_SHIFT)) & OCOTP_FUSE091_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_CLR_ACK_MASK (0x2000U) +#define OCOTP_OUT_STATUS_CLR_ACK_SHIFT (13U) +/*! ACK - Acknowledge + */ +#define OCOTP_OUT_STATUS_CLR_ACK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_ACK_SHIFT)) & OCOTP_OUT_STATUS_CLR_ACK_MASK) -/*! @name FUSE092 - Value of fuse word 92 */ -/*! @{ */ -#define OCOTP_FUSE092_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE092_BITS_SHIFT (0U) -#define OCOTP_FUSE092_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE092_BITS_SHIFT)) & OCOTP_FUSE092_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_CLR_PWOK_MASK (0x4000U) +#define OCOTP_OUT_STATUS_CLR_PWOK_SHIFT (14U) +/*! PWOK - Power OK + */ +#define OCOTP_OUT_STATUS_CLR_PWOK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_PWOK_SHIFT)) & OCOTP_OUT_STATUS_CLR_PWOK_MASK) -/*! @name FUSE093 - Value of fuse word 93 */ -/*! @{ */ -#define OCOTP_FUSE093_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE093_BITS_SHIFT (0U) -#define OCOTP_FUSE093_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE093_BITS_SHIFT)) & OCOTP_FUSE093_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_CLR_FLAGSTATE_MASK (0x78000U) +#define OCOTP_OUT_STATUS_CLR_FLAGSTATE_SHIFT (15U) +/*! FLAGSTATE - Flag state + */ +#define OCOTP_OUT_STATUS_CLR_FLAGSTATE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS_CLR_FLAGSTATE_MASK) -/*! @name FUSE094 - Value of fuse word 94 */ -/*! @{ */ -#define OCOTP_FUSE094_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE094_BITS_SHIFT (0U) -#define OCOTP_FUSE094_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE094_BITS_SHIFT)) & OCOTP_FUSE094_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_CLR_SEC_RELOAD_MASK (0x80000U) +#define OCOTP_OUT_STATUS_CLR_SEC_RELOAD_SHIFT (19U) +/*! SEC_RELOAD - Indicates single error correction occured on reload + */ +#define OCOTP_OUT_STATUS_CLR_SEC_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_CLR_SEC_RELOAD_MASK) -/*! @name FUSE095 - Value of fuse word 95 */ -/*! @{ */ -#define OCOTP_FUSE095_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE095_BITS_SHIFT (0U) -#define OCOTP_FUSE095_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE095_BITS_SHIFT)) & OCOTP_FUSE095_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_CLR_DED_RELOAD_MASK (0x100000U) +#define OCOTP_OUT_STATUS_CLR_DED_RELOAD_SHIFT (20U) +/*! DED_RELOAD - Indicates double error detection occured on reload + */ +#define OCOTP_OUT_STATUS_CLR_DED_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED_RELOAD_MASK) -/*! @name FUSE096 - Value of fuse word 96 */ -/*! @{ */ -#define OCOTP_FUSE096_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE096_BITS_SHIFT (0U) -#define OCOTP_FUSE096_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE096_BITS_SHIFT)) & OCOTP_FUSE096_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_CLR_CALIBRATED_MASK (0x200000U) +#define OCOTP_OUT_STATUS_CLR_CALIBRATED_SHIFT (21U) +/*! CALIBRATED - Calibrated status + */ +#define OCOTP_OUT_STATUS_CLR_CALIBRATED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS_CLR_CALIBRATED_MASK) -/*! @name FUSE097 - Value of fuse word 97 */ -/*! @{ */ -#define OCOTP_FUSE097_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE097_BITS_SHIFT (0U) -#define OCOTP_FUSE097_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE097_BITS_SHIFT)) & OCOTP_FUSE097_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_CLR_READ_DONE_INTR_MASK (0x400000U) +#define OCOTP_OUT_STATUS_CLR_READ_DONE_INTR_SHIFT (22U) +/*! READ_DONE_INTR - Read fuse done + */ +#define OCOTP_OUT_STATUS_CLR_READ_DONE_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS_CLR_READ_DONE_INTR_MASK) -/*! @name FUSE098 - Value of fuse word 98 */ -/*! @{ */ -#define OCOTP_FUSE098_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE098_BITS_SHIFT (0U) -#define OCOTP_FUSE098_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE098_BITS_SHIFT)) & OCOTP_FUSE098_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR_MASK (0x800000U) +#define OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR_SHIFT (23U) +/*! READ_ERROR_INTR - Fuse read error + */ +#define OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR_MASK) -/*! @name FUSE099 - Value of fuse word 99 */ -/*! @{ */ -#define OCOTP_FUSE099_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE099_BITS_SHIFT (0U) -#define OCOTP_FUSE099_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE099_BITS_SHIFT)) & OCOTP_FUSE099_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_CLR_DED0_MASK (0x1000000U) +#define OCOTP_OUT_STATUS_CLR_DED0_SHIFT (24U) +/*! DED0 - Double error detect + */ +#define OCOTP_OUT_STATUS_CLR_DED0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED0_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED0_MASK) -/*! @name FUSE100 - Value of fuse word 100 */ -/*! @{ */ -#define OCOTP_FUSE100_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE100_BITS_SHIFT (0U) -#define OCOTP_FUSE100_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE100_BITS_SHIFT)) & OCOTP_FUSE100_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_CLR_DED1_MASK (0x2000000U) +#define OCOTP_OUT_STATUS_CLR_DED1_SHIFT (25U) +/*! DED1 - Double error detect + */ +#define OCOTP_OUT_STATUS_CLR_DED1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED1_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED1_MASK) -/*! @name FUSE101 - Value of fuse word 101 */ -/*! @{ */ -#define OCOTP_FUSE101_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE101_BITS_SHIFT (0U) -#define OCOTP_FUSE101_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE101_BITS_SHIFT)) & OCOTP_FUSE101_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_CLR_DED2_MASK (0x4000000U) +#define OCOTP_OUT_STATUS_CLR_DED2_SHIFT (26U) +/*! DED2 - Double error detect + */ +#define OCOTP_OUT_STATUS_CLR_DED2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED2_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED2_MASK) -/*! @name FUSE102 - Value of fuse word 102 */ -/*! @{ */ -#define OCOTP_FUSE102_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE102_BITS_SHIFT (0U) -#define OCOTP_FUSE102_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE102_BITS_SHIFT)) & OCOTP_FUSE102_BITS_MASK) +#define OCOTP_OUT_STATUS_CLR_DED3_MASK (0x8000000U) +#define OCOTP_OUT_STATUS_CLR_DED3_SHIFT (27U) +/*! DED3 - Double error detect + */ +#define OCOTP_OUT_STATUS_CLR_DED3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED3_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED3_MASK) /*! @} */ -/*! @name FUSE103 - Value of fuse word 103 */ +/*! @name OUT_STATUS_TOG - 8K OTP Memory STATUS Register */ /*! @{ */ -#define OCOTP_FUSE103_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE103_BITS_SHIFT (0U) -#define OCOTP_FUSE103_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE103_BITS_SHIFT)) & OCOTP_FUSE103_BITS_MASK) -/*! @} */ -/*! @name FUSE104 - Value of fuse word 104 */ -/*! @{ */ -#define OCOTP_FUSE104_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE104_BITS_SHIFT (0U) -#define OCOTP_FUSE104_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE104_BITS_SHIFT)) & OCOTP_FUSE104_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_TOG_SEC_MASK (0x200U) +#define OCOTP_OUT_STATUS_TOG_SEC_SHIFT (9U) +/*! SEC - Single Error Correct + */ +#define OCOTP_OUT_STATUS_TOG_SEC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_SEC_SHIFT)) & OCOTP_OUT_STATUS_TOG_SEC_MASK) -/*! @name FUSE105 - Value of fuse word 105 */ -/*! @{ */ -#define OCOTP_FUSE105_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE105_BITS_SHIFT (0U) -#define OCOTP_FUSE105_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE105_BITS_SHIFT)) & OCOTP_FUSE105_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_TOG_DED_MASK (0x400U) +#define OCOTP_OUT_STATUS_TOG_DED_SHIFT (10U) +/*! DED - Double error detect + */ +#define OCOTP_OUT_STATUS_TOG_DED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED_MASK) -/*! @name FUSE106 - Value of fuse word 106 */ -/*! @{ */ -#define OCOTP_FUSE106_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE106_BITS_SHIFT (0U) -#define OCOTP_FUSE106_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE106_BITS_SHIFT)) & OCOTP_FUSE106_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_TOG_LOCKED_MASK (0x800U) +#define OCOTP_OUT_STATUS_TOG_LOCKED_SHIFT (11U) +/*! LOCKED - Word Locked + */ +#define OCOTP_OUT_STATUS_TOG_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_LOCKED_SHIFT)) & OCOTP_OUT_STATUS_TOG_LOCKED_MASK) -/*! @name FUSE107 - Value of fuse word 107 */ -/*! @{ */ -#define OCOTP_FUSE107_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE107_BITS_SHIFT (0U) -#define OCOTP_FUSE107_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE107_BITS_SHIFT)) & OCOTP_FUSE107_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_TOG_PROGFAIL_MASK (0x1000U) +#define OCOTP_OUT_STATUS_TOG_PROGFAIL_SHIFT (12U) +/*! PROGFAIL - Programming failed + */ +#define OCOTP_OUT_STATUS_TOG_PROGFAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS_TOG_PROGFAIL_MASK) -/*! @name FUSE108 - Value of fuse word 108 */ -/*! @{ */ -#define OCOTP_FUSE108_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE108_BITS_SHIFT (0U) -#define OCOTP_FUSE108_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE108_BITS_SHIFT)) & OCOTP_FUSE108_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_TOG_ACK_MASK (0x2000U) +#define OCOTP_OUT_STATUS_TOG_ACK_SHIFT (13U) +/*! ACK - Acknowledge + */ +#define OCOTP_OUT_STATUS_TOG_ACK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_ACK_SHIFT)) & OCOTP_OUT_STATUS_TOG_ACK_MASK) -/*! @name FUSE109 - Value of fuse word 109 */ -/*! @{ */ -#define OCOTP_FUSE109_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE109_BITS_SHIFT (0U) -#define OCOTP_FUSE109_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE109_BITS_SHIFT)) & OCOTP_FUSE109_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_TOG_PWOK_MASK (0x4000U) +#define OCOTP_OUT_STATUS_TOG_PWOK_SHIFT (14U) +/*! PWOK - Power OK + */ +#define OCOTP_OUT_STATUS_TOG_PWOK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_PWOK_SHIFT)) & OCOTP_OUT_STATUS_TOG_PWOK_MASK) -/*! @name FUSE110 - Value of fuse word 110 */ -/*! @{ */ -#define OCOTP_FUSE110_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE110_BITS_SHIFT (0U) -#define OCOTP_FUSE110_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE110_BITS_SHIFT)) & OCOTP_FUSE110_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_TOG_FLAGSTATE_MASK (0x78000U) +#define OCOTP_OUT_STATUS_TOG_FLAGSTATE_SHIFT (15U) +/*! FLAGSTATE - Flag state + */ +#define OCOTP_OUT_STATUS_TOG_FLAGSTATE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS_TOG_FLAGSTATE_MASK) -/*! @name FUSE111 - Value of fuse word 111 */ -/*! @{ */ -#define OCOTP_FUSE111_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE111_BITS_SHIFT (0U) -#define OCOTP_FUSE111_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE111_BITS_SHIFT)) & OCOTP_FUSE111_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_TOG_SEC_RELOAD_MASK (0x80000U) +#define OCOTP_OUT_STATUS_TOG_SEC_RELOAD_SHIFT (19U) +/*! SEC_RELOAD - Indicates single error correction occured on reload + */ +#define OCOTP_OUT_STATUS_TOG_SEC_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_TOG_SEC_RELOAD_MASK) -/*! @name FUSE112 - Value of fuse word 112 */ -/*! @{ */ -#define OCOTP_FUSE112_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE112_BITS_SHIFT (0U) -#define OCOTP_FUSE112_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE112_BITS_SHIFT)) & OCOTP_FUSE112_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_TOG_DED_RELOAD_MASK (0x100000U) +#define OCOTP_OUT_STATUS_TOG_DED_RELOAD_SHIFT (20U) +/*! DED_RELOAD - Indicates double error detection occured on reload + */ +#define OCOTP_OUT_STATUS_TOG_DED_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED_RELOAD_MASK) -/*! @name FUSE113 - Value of fuse word 113 */ -/*! @{ */ -#define OCOTP_FUSE113_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE113_BITS_SHIFT (0U) -#define OCOTP_FUSE113_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE113_BITS_SHIFT)) & OCOTP_FUSE113_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_TOG_CALIBRATED_MASK (0x200000U) +#define OCOTP_OUT_STATUS_TOG_CALIBRATED_SHIFT (21U) +/*! CALIBRATED - Calibrated status + */ +#define OCOTP_OUT_STATUS_TOG_CALIBRATED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS_TOG_CALIBRATED_MASK) -/*! @name FUSE114 - Value of fuse word 114 */ -/*! @{ */ -#define OCOTP_FUSE114_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE114_BITS_SHIFT (0U) -#define OCOTP_FUSE114_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE114_BITS_SHIFT)) & OCOTP_FUSE114_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_TOG_READ_DONE_INTR_MASK (0x400000U) +#define OCOTP_OUT_STATUS_TOG_READ_DONE_INTR_SHIFT (22U) +/*! READ_DONE_INTR - Read fuse done + */ +#define OCOTP_OUT_STATUS_TOG_READ_DONE_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS_TOG_READ_DONE_INTR_MASK) -/*! @name FUSE115 - Value of fuse word 115 */ -/*! @{ */ -#define OCOTP_FUSE115_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE115_BITS_SHIFT (0U) -#define OCOTP_FUSE115_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE115_BITS_SHIFT)) & OCOTP_FUSE115_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR_MASK (0x800000U) +#define OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR_SHIFT (23U) +/*! READ_ERROR_INTR - Fuse read error + */ +#define OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR_MASK) -/*! @name FUSE116 - Value of fuse word 116 */ -/*! @{ */ -#define OCOTP_FUSE116_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE116_BITS_SHIFT (0U) -#define OCOTP_FUSE116_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE116_BITS_SHIFT)) & OCOTP_FUSE116_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_TOG_DED0_MASK (0x1000000U) +#define OCOTP_OUT_STATUS_TOG_DED0_SHIFT (24U) +/*! DED0 - Double error detect + */ +#define OCOTP_OUT_STATUS_TOG_DED0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED0_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED0_MASK) -/*! @name FUSE117 - Value of fuse word 117 */ -/*! @{ */ -#define OCOTP_FUSE117_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE117_BITS_SHIFT (0U) -#define OCOTP_FUSE117_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE117_BITS_SHIFT)) & OCOTP_FUSE117_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_TOG_DED1_MASK (0x2000000U) +#define OCOTP_OUT_STATUS_TOG_DED1_SHIFT (25U) +/*! DED1 - Double error detect + */ +#define OCOTP_OUT_STATUS_TOG_DED1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED1_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED1_MASK) -/*! @name FUSE118 - Value of fuse word 118 */ -/*! @{ */ -#define OCOTP_FUSE118_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE118_BITS_SHIFT (0U) -#define OCOTP_FUSE118_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE118_BITS_SHIFT)) & OCOTP_FUSE118_BITS_MASK) -/*! @} */ +#define OCOTP_OUT_STATUS_TOG_DED2_MASK (0x4000000U) +#define OCOTP_OUT_STATUS_TOG_DED2_SHIFT (26U) +/*! DED2 - Double error detect + */ +#define OCOTP_OUT_STATUS_TOG_DED2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED2_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED2_MASK) -/*! @name FUSE119 - Value of fuse word 119 */ -/*! @{ */ -#define OCOTP_FUSE119_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE119_BITS_SHIFT (0U) -#define OCOTP_FUSE119_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE119_BITS_SHIFT)) & OCOTP_FUSE119_BITS_MASK) +#define OCOTP_OUT_STATUS_TOG_DED3_MASK (0x8000000U) +#define OCOTP_OUT_STATUS_TOG_DED3_SHIFT (27U) +/*! DED3 - Double error detect + */ +#define OCOTP_OUT_STATUS_TOG_DED3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED3_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED3_MASK) /*! @} */ -/*! @name FUSE120 - Value of fuse word 120 */ +/*! @name VERSION - OTP Controller Version Register */ /*! @{ */ -#define OCOTP_FUSE120_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE120_BITS_SHIFT (0U) -#define OCOTP_FUSE120_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE120_BITS_SHIFT)) & OCOTP_FUSE120_BITS_MASK) -/*! @} */ -/*! @name FUSE121 - Value of fuse word 121 */ -/*! @{ */ -#define OCOTP_FUSE121_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE121_BITS_SHIFT (0U) -#define OCOTP_FUSE121_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE121_BITS_SHIFT)) & OCOTP_FUSE121_BITS_MASK) -/*! @} */ +#define OCOTP_VERSION_STEP_MASK (0xFFFFU) +#define OCOTP_VERSION_STEP_SHIFT (0U) +/*! STEP - RTL Version Stepping + */ +#define OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK) -/*! @name FUSE122 - Value of fuse word 122 */ -/*! @{ */ -#define OCOTP_FUSE122_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE122_BITS_SHIFT (0U) -#define OCOTP_FUSE122_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE122_BITS_SHIFT)) & OCOTP_FUSE122_BITS_MASK) -/*! @} */ +#define OCOTP_VERSION_MINOR_MASK (0xFF0000U) +#define OCOTP_VERSION_MINOR_SHIFT (16U) +/*! MINOR - Minor RTL Version + */ +#define OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK) -/*! @name FUSE123 - Value of fuse word 123 */ -/*! @{ */ -#define OCOTP_FUSE123_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE123_BITS_SHIFT (0U) -#define OCOTP_FUSE123_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE123_BITS_SHIFT)) & OCOTP_FUSE123_BITS_MASK) +#define OCOTP_VERSION_MAJOR_MASK (0xFF000000U) +#define OCOTP_VERSION_MAJOR_SHIFT (24U) +/*! MAJOR - Major RTL Version + */ +#define OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK) /*! @} */ -/*! @name FUSE124 - Value of fuse word 124 */ +/*! @name READ_FUSE_DATA - OTP Controller Read Data 0 Register..OTP Controller Read Data 3 Register */ /*! @{ */ -#define OCOTP_FUSE124_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE124_BITS_SHIFT (0U) -#define OCOTP_FUSE124_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE124_BITS_SHIFT)) & OCOTP_FUSE124_BITS_MASK) -/*! @} */ -/*! @name FUSE125 - Value of fuse word 125 */ -/*! @{ */ -#define OCOTP_FUSE125_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE125_BITS_SHIFT (0U) -#define OCOTP_FUSE125_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE125_BITS_SHIFT)) & OCOTP_FUSE125_BITS_MASK) +#define OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU) +#define OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U) +/*! DATA - Data + */ +#define OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK) /*! @} */ -/*! @name FUSE126 - Value of fuse word 126 */ -/*! @{ */ -#define OCOTP_FUSE126_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE126_BITS_SHIFT (0U) -#define OCOTP_FUSE126_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE126_BITS_SHIFT)) & OCOTP_FUSE126_BITS_MASK) -/*! @} */ +/* The count of OCOTP_READ_FUSE_DATA */ +#define OCOTP_READ_FUSE_DATA_COUNT (4U) -/*! @name FUSE127 - Value of fuse word 127 */ +/*! @name SW_LOCK - SW_LOCK Register */ /*! @{ */ -#define OCOTP_FUSE127_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE127_BITS_SHIFT (0U) -#define OCOTP_FUSE127_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE127_BITS_SHIFT)) & OCOTP_FUSE127_BITS_MASK) -/*! @} */ -/*! @name FUSE128 - Value of fuse word 128 */ -/*! @{ */ -#define OCOTP_FUSE128_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE128_BITS_SHIFT (0U) -#define OCOTP_FUSE128_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE128_BITS_SHIFT)) & OCOTP_FUSE128_BITS_MASK) +#define OCOTP_SW_LOCK_SW_LOCK_MASK (0xFFFFFFFFU) +#define OCOTP_SW_LOCK_SW_LOCK_SHIFT (0U) +#define OCOTP_SW_LOCK_SW_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_LOCK_SW_LOCK_SHIFT)) & OCOTP_SW_LOCK_SW_LOCK_MASK) /*! @} */ -/*! @name FUSE129 - Value of fuse word 129 */ +/*! @name BIT_LOCK - BIT_LOCK Register */ /*! @{ */ -#define OCOTP_FUSE129_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE129_BITS_SHIFT (0U) -#define OCOTP_FUSE129_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE129_BITS_SHIFT)) & OCOTP_FUSE129_BITS_MASK) -/*! @} */ -/*! @name FUSE130 - Value of fuse word 130 */ -/*! @{ */ -#define OCOTP_FUSE130_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE130_BITS_SHIFT (0U) -#define OCOTP_FUSE130_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE130_BITS_SHIFT)) & OCOTP_FUSE130_BITS_MASK) +#define OCOTP_BIT_LOCK_BIT_LOCK_MASK (0xFFFFFFFFU) +#define OCOTP_BIT_LOCK_BIT_LOCK_SHIFT (0U) +#define OCOTP_BIT_LOCK_BIT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_BIT_LOCK_BIT_LOCK_SHIFT)) & OCOTP_BIT_LOCK_BIT_LOCK_MASK) /*! @} */ -/*! @name FUSE131 - Value of fuse word 131 */ +/*! @name LOCKED0 - OTP Controller Program Locked Status 0 Register */ /*! @{ */ -#define OCOTP_FUSE131_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE131_BITS_SHIFT (0U) -#define OCOTP_FUSE131_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE131_BITS_SHIFT)) & OCOTP_FUSE131_BITS_MASK) -/*! @} */ -/*! @name FUSE132 - Value of fuse word 132 */ -/*! @{ */ -#define OCOTP_FUSE132_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE132_BITS_SHIFT (0U) -#define OCOTP_FUSE132_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE132_BITS_SHIFT)) & OCOTP_FUSE132_BITS_MASK) +#define OCOTP_LOCKED0_LOCKED_MASK (0xFFFFU) +#define OCOTP_LOCKED0_LOCKED_SHIFT (0U) +#define OCOTP_LOCKED0_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED0_LOCKED_SHIFT)) & OCOTP_LOCKED0_LOCKED_MASK) /*! @} */ -/*! @name FUSE133 - Value of fuse word 133 */ +/*! @name LOCKED1 - OTP Controller Program Locked Status 1 Register */ /*! @{ */ -#define OCOTP_FUSE133_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE133_BITS_SHIFT (0U) -#define OCOTP_FUSE133_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE133_BITS_SHIFT)) & OCOTP_FUSE133_BITS_MASK) -/*! @} */ -/*! @name FUSE134 - Value of fuse word 134 */ -/*! @{ */ -#define OCOTP_FUSE134_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE134_BITS_SHIFT (0U) -#define OCOTP_FUSE134_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE134_BITS_SHIFT)) & OCOTP_FUSE134_BITS_MASK) +#define OCOTP_LOCKED1_LOCKED_MASK (0xFFFFFFFFU) +#define OCOTP_LOCKED1_LOCKED_SHIFT (0U) +#define OCOTP_LOCKED1_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED1_LOCKED_SHIFT)) & OCOTP_LOCKED1_LOCKED_MASK) /*! @} */ -/*! @name FUSE135 - Value of fuse word 135 */ +/*! @name LOCKED2 - OTP Controller Program Locked Status 2 Register */ /*! @{ */ -#define OCOTP_FUSE135_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE135_BITS_SHIFT (0U) -#define OCOTP_FUSE135_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE135_BITS_SHIFT)) & OCOTP_FUSE135_BITS_MASK) -/*! @} */ -/*! @name FUSE136 - Value of fuse word 136 */ -/*! @{ */ -#define OCOTP_FUSE136_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE136_BITS_SHIFT (0U) -#define OCOTP_FUSE136_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE136_BITS_SHIFT)) & OCOTP_FUSE136_BITS_MASK) +#define OCOTP_LOCKED2_LOCKED_MASK (0xFFFFFFFFU) +#define OCOTP_LOCKED2_LOCKED_SHIFT (0U) +#define OCOTP_LOCKED2_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED2_LOCKED_SHIFT)) & OCOTP_LOCKED2_LOCKED_MASK) /*! @} */ -/*! @name FUSE137 - Value of fuse word 137 */ +/*! @name LOCKED3 - OTP Controller Program Locked Status 3 Register */ /*! @{ */ -#define OCOTP_FUSE137_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE137_BITS_SHIFT (0U) -#define OCOTP_FUSE137_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE137_BITS_SHIFT)) & OCOTP_FUSE137_BITS_MASK) -/*! @} */ -/*! @name FUSE138 - Value of fuse word 138 */ -/*! @{ */ -#define OCOTP_FUSE138_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE138_BITS_SHIFT (0U) -#define OCOTP_FUSE138_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE138_BITS_SHIFT)) & OCOTP_FUSE138_BITS_MASK) +#define OCOTP_LOCKED3_LOCKED_MASK (0xFFFFFFFFU) +#define OCOTP_LOCKED3_LOCKED_SHIFT (0U) +#define OCOTP_LOCKED3_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED3_LOCKED_SHIFT)) & OCOTP_LOCKED3_LOCKED_MASK) /*! @} */ -/*! @name FUSE139 - Value of fuse word 139 */ +/*! @name LOCKED4 - OTP Controller Program Locked Status 4 Register */ /*! @{ */ -#define OCOTP_FUSE139_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE139_BITS_SHIFT (0U) -#define OCOTP_FUSE139_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE139_BITS_SHIFT)) & OCOTP_FUSE139_BITS_MASK) -/*! @} */ -/*! @name FUSE140 - Value of fuse word 140 */ -/*! @{ */ -#define OCOTP_FUSE140_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE140_BITS_SHIFT (0U) -#define OCOTP_FUSE140_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE140_BITS_SHIFT)) & OCOTP_FUSE140_BITS_MASK) +#define OCOTP_LOCKED4_LOCKED_MASK (0xFFFFFFFFU) +#define OCOTP_LOCKED4_LOCKED_SHIFT (0U) +#define OCOTP_LOCKED4_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED4_LOCKED_SHIFT)) & OCOTP_LOCKED4_LOCKED_MASK) /*! @} */ -/*! @name FUSE141 - Value of fuse word 141 */ +/*! @name FUSE - Value of fuse word 0..Value of fuse word 143 */ /*! @{ */ -#define OCOTP_FUSE141_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE141_BITS_SHIFT (0U) -#define OCOTP_FUSE141_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE141_BITS_SHIFT)) & OCOTP_FUSE141_BITS_MASK) -/*! @} */ -/*! @name FUSE142 - Value of fuse word 142 */ -/*! @{ */ -#define OCOTP_FUSE142_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE142_BITS_SHIFT (0U) -#define OCOTP_FUSE142_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE142_BITS_SHIFT)) & OCOTP_FUSE142_BITS_MASK) +#define OCOTP_FUSE_BITS_MASK (0xFFFFFFFFU) +#define OCOTP_FUSE_BITS_SHIFT (0U) +/*! BITS - Reflects value of the fuse word + */ +#define OCOTP_FUSE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE_BITS_SHIFT)) & OCOTP_FUSE_BITS_MASK) /*! @} */ -/*! @name FUSE143 - Value of fuse word 143 */ -/*! @{ */ -#define OCOTP_FUSE143_BITS_MASK (0xFFFFFFFFU) -#define OCOTP_FUSE143_BITS_SHIFT (0U) -#define OCOTP_FUSE143_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE143_BITS_SHIFT)) & OCOTP_FUSE143_BITS_MASK) -/*! @} */ +/* The count of OCOTP_FUSE */ +#define OCOTP_FUSE_COUNT (144U) /*! @@ -65411,52 +74773,47 @@ typedef struct { /** OSC_RC_400M - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0 */ - __IO uint32_t RW; /**< Analog Control Register CTRL0, offset: 0x0 */ - __IO uint32_t SET; /**< Analog Control Register CTRL0, offset: 0x4 */ - __IO uint32_t CLR; /**< Analog Control Register CTRL0, offset: 0x8 */ - __IO uint32_t TOG; /**< Analog Control Register CTRL0, offset: 0xC */ + __IO uint32_t RW; /**< Control Register 0, offset: 0x0 */ + __IO uint32_t SET; /**< Control Register 0, offset: 0x4 */ + __IO uint32_t CLR; /**< Control Register 0, offset: 0x8 */ + __IO uint32_t TOG; /**< Control Register 0, offset: 0xC */ } CTRL0; struct { /* offset: 0x10 */ - __IO uint32_t RW; /**< Analog Control Register CTRL0, offset: 0x10 */ - __IO uint32_t SET; /**< Analog Control Register CTRL0, offset: 0x14 */ - __IO uint32_t CLR; /**< Analog Control Register CTRL0, offset: 0x18 */ - __IO uint32_t TOG; /**< Analog Control Register CTRL0, offset: 0x1C */ + __IO uint32_t RW; /**< Control Register 1, offset: 0x10 */ + __IO uint32_t SET; /**< Control Register 1, offset: 0x14 */ + __IO uint32_t CLR; /**< Control Register 1, offset: 0x18 */ + __IO uint32_t TOG; /**< Control Register 1, offset: 0x1C */ } CTRL1; struct { /* offset: 0x20 */ - __IO uint32_t RW; /**< Analog Control Register CTRL0, offset: 0x20 */ - __IO uint32_t SET; /**< Analog Control Register CTRL0, offset: 0x24 */ - __IO uint32_t CLR; /**< Analog Control Register CTRL0, offset: 0x28 */ - __IO uint32_t TOG; /**< Analog Control Register CTRL0, offset: 0x2C */ + __IO uint32_t RW; /**< Control Register 2, offset: 0x20 */ + __IO uint32_t SET; /**< Control Register 2, offset: 0x24 */ + __IO uint32_t CLR; /**< Control Register 2, offset: 0x28 */ + __IO uint32_t TOG; /**< Control Register 2, offset: 0x2C */ } CTRL2; struct { /* offset: 0x30 */ - __IO uint32_t RW; /**< Analog Control Register CTRL0, offset: 0x30 */ - __IO uint32_t SET; /**< Analog Control Register CTRL0, offset: 0x34 */ - __IO uint32_t CLR; /**< Analog Control Register CTRL0, offset: 0x38 */ - __IO uint32_t TOG; /**< Analog Control Register CTRL0, offset: 0x3C */ + __IO uint32_t RW; /**< Control Register 3, offset: 0x30 */ + __IO uint32_t SET; /**< Control Register 3, offset: 0x34 */ + __IO uint32_t CLR; /**< Control Register 3, offset: 0x38 */ + __IO uint32_t TOG; /**< Control Register 3, offset: 0x3C */ } CTRL3; - struct { /* offset: 0x40 */ - __IO uint32_t RW; /**< Analog Control Register CTRL0, offset: 0x40 */ - __IO uint32_t SET; /**< Analog Control Register CTRL0, offset: 0x44 */ - __IO uint32_t CLR; /**< Analog Control Register CTRL0, offset: 0x48 */ - __IO uint32_t TOG; /**< Analog Control Register CTRL0, offset: 0x4C */ - } CTRL4; + uint8_t RESERVED_0[16]; struct { /* offset: 0x50 */ - __I uint32_t RW; /**< Analog Status Register STAT0, offset: 0x50 */ - __I uint32_t SET; /**< Analog Status Register STAT0, offset: 0x54 */ - __I uint32_t CLR; /**< Analog Status Register STAT0, offset: 0x58 */ - __I uint32_t TOG; /**< Analog Status Register STAT0, offset: 0x5C */ + __I uint32_t RW; /**< Status Register 0, offset: 0x50 */ + __I uint32_t SET; /**< Status Register 0, offset: 0x54 */ + __I uint32_t CLR; /**< Status Register 0, offset: 0x58 */ + __I uint32_t TOG; /**< Status Register 0, offset: 0x5C */ } STAT0; struct { /* offset: 0x60 */ - __I uint32_t RW; /**< Analog Status Register STAT0, offset: 0x60 */ - __I uint32_t SET; /**< Analog Status Register STAT0, offset: 0x64 */ - __I uint32_t CLR; /**< Analog Status Register STAT0, offset: 0x68 */ - __I uint32_t TOG; /**< Analog Status Register STAT0, offset: 0x6C */ + __I uint32_t RW; /**< Status Register 1, offset: 0x60 */ + __I uint32_t SET; /**< Status Register 1, offset: 0x64 */ + __I uint32_t CLR; /**< Status Register 1, offset: 0x68 */ + __I uint32_t TOG; /**< Status Register 1, offset: 0x6C */ } STAT1; struct { /* offset: 0x70 */ - __I uint32_t RW; /**< Analog Status Register STAT0, offset: 0x70 */ - __I uint32_t SET; /**< Analog Status Register STAT0, offset: 0x74 */ - __I uint32_t CLR; /**< Analog Status Register STAT0, offset: 0x78 */ - __I uint32_t TOG; /**< Analog Status Register STAT0, offset: 0x7C */ + __I uint32_t RW; /**< Status Register 2, offset: 0x70 */ + __I uint32_t SET; /**< Status Register 2, offset: 0x74 */ + __I uint32_t CLR; /**< Status Register 2, offset: 0x78 */ + __I uint32_t TOG; /**< Status Register 2, offset: 0x7C */ } STAT2; } OSC_RC_400M_Type; @@ -65469,124 +74826,134 @@ typedef struct { * @{ */ -/*! @name CTRL0 - Analog Control Register CTRL0 */ +/*! @name CTRL0 - Control Register 0 */ /*! @{ */ + #define OSC_RC_400M_CTRL0_REF_CLK_DIV_MASK (0x3F000000U) #define OSC_RC_400M_CTRL0_REF_CLK_DIV_SHIFT (24U) -/*! REF_CLK_DIV - Divide value for ref_clk to generate slow_clk. +/*! REF_CLK_DIV - Divide value for ref_clk to generate slow_clk (used inside this IP) */ #define OSC_RC_400M_CTRL0_REF_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL0_REF_CLK_DIV_SHIFT)) & OSC_RC_400M_CTRL0_REF_CLK_DIV_MASK) /*! @} */ -/*! @name CTRL1 - Analog Control Register CTRL0 */ +/*! @name CTRL1 - Control Register 1 */ /*! @{ */ + #define OSC_RC_400M_CTRL1_HYST_MINUS_MASK (0xFU) #define OSC_RC_400M_CTRL1_HYST_MINUS_SHIFT (0U) -/*! HYST_MINUS - Negative hysteresis value for the tuned clock. +/*! HYST_MINUS - Negative hysteresis value for the tuned clock */ #define OSC_RC_400M_CTRL1_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL1_HYST_MINUS_SHIFT)) & OSC_RC_400M_CTRL1_HYST_MINUS_MASK) + #define OSC_RC_400M_CTRL1_HYST_PLUS_MASK (0xF00U) #define OSC_RC_400M_CTRL1_HYST_PLUS_SHIFT (8U) -/*! HYST_PLUS - Positive hysteresis value for the tuned clock. +/*! HYST_PLUS - Positive hysteresis value for the tuned clock */ #define OSC_RC_400M_CTRL1_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL1_HYST_PLUS_SHIFT)) & OSC_RC_400M_CTRL1_HYST_PLUS_MASK) + #define OSC_RC_400M_CTRL1_TARGET_COUNT_MASK (0xFFFF0000U) #define OSC_RC_400M_CTRL1_TARGET_COUNT_SHIFT (16U) -/*! TARGET_COUNT - Target count for the fast clock. +/*! TARGET_COUNT - Target count for the fast clock */ #define OSC_RC_400M_CTRL1_TARGET_COUNT(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL1_TARGET_COUNT_SHIFT)) & OSC_RC_400M_CTRL1_TARGET_COUNT_MASK) /*! @} */ -/*! @name CTRL2 - Analog Control Register CTRL0 */ +/*! @name CTRL2 - Control Register 2 */ /*! @{ */ -#define OSC_RC_400M_CTRL2_TUNE_INV_MASK (0x100U) -#define OSC_RC_400M_CTRL2_TUNE_INV_SHIFT (8U) -/*! TUNE_INV - Inverse tuning direction. - */ -#define OSC_RC_400M_CTRL2_TUNE_INV(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_INV_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_INV_MASK) + #define OSC_RC_400M_CTRL2_TUNE_BYP_MASK (0x400U) #define OSC_RC_400M_CTRL2_TUNE_BYP_SHIFT (10U) /*! TUNE_BYP - Bypass the tuning logic + * 0b0..Use the output of tuning logic to run the oscillator + * 0b1..Bypass the tuning logic and use the programmed OSC_TUNE_VAL to run the oscillator */ #define OSC_RC_400M_CTRL2_TUNE_BYP(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_BYP_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_BYP_MASK) + #define OSC_RC_400M_CTRL2_TUNE_EN_MASK (0x1000U) #define OSC_RC_400M_CTRL2_TUNE_EN_SHIFT (12U) -/*! TUNE_EN - Freeze/Unfreeze the tuning value. +/*! TUNE_EN - Freeze/Unfreeze the tuning value + * 0b0..Freezes the tuning at the current tuned value. Oscillator runs at the frozen tuning value + * 0b1..Unfreezes and continues the tuning operation */ #define OSC_RC_400M_CTRL2_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_EN_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_EN_MASK) + #define OSC_RC_400M_CTRL2_TUNE_START_MASK (0x4000U) #define OSC_RC_400M_CTRL2_TUNE_START_SHIFT (14U) -/*! TUNE_START - Start/Stop tuning. +/*! TUNE_START - Start/Stop tuning + * 0b0..Stop tuning and reset the tuning logic. Oscillator runs using programmed OSC_TUNE_VAL + * 0b1..Start tuning */ #define OSC_RC_400M_CTRL2_TUNE_START(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_START_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_START_MASK) + #define OSC_RC_400M_CTRL2_OSC_TUNE_VAL_MASK (0xFF000000U) #define OSC_RC_400M_CTRL2_OSC_TUNE_VAL_SHIFT (24U) -/*! OSC_TUNE_VAL - Program the oscillator frequency. +/*! OSC_TUNE_VAL - Program the oscillator frequency */ #define OSC_RC_400M_CTRL2_OSC_TUNE_VAL(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & OSC_RC_400M_CTRL2_OSC_TUNE_VAL_MASK) /*! @} */ -/*! @name CTRL3 - Analog Control Register CTRL0 */ +/*! @name CTRL3 - Control Register 3 */ /*! @{ */ + #define OSC_RC_400M_CTRL3_CLR_ERR_MASK (0x1U) #define OSC_RC_400M_CTRL3_CLR_ERR_SHIFT (0U) /*! CLR_ERR - Clear the error flag CLK1M_ERR + * 0b0..No effect + * 0b1..Clears the error flag CLK1M_ERR in status register STAT0 */ #define OSC_RC_400M_CTRL3_CLR_ERR(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_CLR_ERR_SHIFT)) & OSC_RC_400M_CTRL3_CLR_ERR_MASK) + #define OSC_RC_400M_CTRL3_EN_1M_CLK_MASK (0x100U) #define OSC_RC_400M_CTRL3_EN_1M_CLK_SHIFT (8U) -/*! EN_1M_CLK - 1: Disable clk_1m_out. +/*! EN_1M_CLK - Enable 1MHz output Clock + * 0b0..Enable the output (clk_1m_out) + * 0b1..Disable the output (clk_1m_out) */ #define OSC_RC_400M_CTRL3_EN_1M_CLK(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_EN_1M_CLK_SHIFT)) & OSC_RC_400M_CTRL3_EN_1M_CLK_MASK) + #define OSC_RC_400M_CTRL3_MUX_1M_CLK_MASK (0x400U) #define OSC_RC_400M_CTRL3_MUX_1M_CLK_SHIFT (10U) /*! MUX_1M_CLK - Select free/locked 1MHz output + * 0b0..Select free-running 1MHz to be put out on clk_1m_out + * 0b1..Select locked 1MHz to be put out on clk_1m_out */ #define OSC_RC_400M_CTRL3_MUX_1M_CLK(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_MUX_1M_CLK_SHIFT)) & OSC_RC_400M_CTRL3_MUX_1M_CLK_MASK) + #define OSC_RC_400M_CTRL3_COUNT_1M_CLK_MASK (0xFFFF0000U) #define OSC_RC_400M_CTRL3_COUNT_1M_CLK_SHIFT (16U) -/*! COUNT_1M_CLK - Count for the locked clk_1m_out. +/*! COUNT_1M_CLK - Count for the locked clk_1m_out */ #define OSC_RC_400M_CTRL3_COUNT_1M_CLK(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_COUNT_1M_CLK_SHIFT)) & OSC_RC_400M_CTRL3_COUNT_1M_CLK_MASK) /*! @} */ -/*! @name CTRL4 - Analog Control Register CTRL0 */ +/*! @name STAT0 - Status Register 0 */ /*! @{ */ -#define OSC_RC_400M_CTRL4_PWD_MASK (0x20000000U) -#define OSC_RC_400M_CTRL4_PWD_SHIFT (29U) -/*! PWD - Not used. - */ -#define OSC_RC_400M_CTRL4_PWD(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL4_PWD_SHIFT)) & OSC_RC_400M_CTRL4_PWD_MASK) -#define OSC_RC_400M_CTRL4_OSC_EN_MASK (0x80000000U) -#define OSC_RC_400M_CTRL4_OSC_EN_SHIFT (31U) -/*! OSC_EN - Not used. - */ -#define OSC_RC_400M_CTRL4_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL4_OSC_EN_SHIFT)) & OSC_RC_400M_CTRL4_OSC_EN_MASK) -/*! @} */ -/*! @name STAT0 - Analog Status Register STAT0 */ -/*! @{ */ #define OSC_RC_400M_STAT0_CLK1M_ERR_MASK (0x1U) #define OSC_RC_400M_STAT0_CLK1M_ERR_SHIFT (0U) -/*! CLK1M_ERR - Error flag for clk_1m_locked. +/*! CLK1M_ERR - Error flag for clk_1m_locked + * 0b0..No effect + * 0b1..The count value has been reached within one divided ref_clk period */ #define OSC_RC_400M_STAT0_CLK1M_ERR(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_STAT0_CLK1M_ERR_SHIFT)) & OSC_RC_400M_STAT0_CLK1M_ERR_MASK) /*! @} */ -/*! @name STAT1 - Analog Status Register STAT0 */ +/*! @name STAT1 - Status Register 1 */ /*! @{ */ + #define OSC_RC_400M_STAT1_CURR_COUNT_VAL_MASK (0xFFFF0000U) #define OSC_RC_400M_STAT1_CURR_COUNT_VAL_SHIFT (16U) -/*! CURR_COUNT_VAL - Current count for the fast clock. +/*! CURR_COUNT_VAL - Current count for the fast clock */ #define OSC_RC_400M_STAT1_CURR_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_STAT1_CURR_COUNT_VAL_SHIFT)) & OSC_RC_400M_STAT1_CURR_COUNT_VAL_MASK) /*! @} */ -/*! @name STAT2 - Analog Status Register STAT0 */ +/*! @name STAT2 - Status Register 2 */ /*! @{ */ + #define OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_MASK (0xFF000000U) #define OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT (24U) -/*! CURR_OSC_TUNE_VAL - Current tuning value used by oscillator. +/*! CURR_OSC_TUNE_VAL - Current tuning value used by oscillator */ #define OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT)) & OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_MASK) /*! @} */ @@ -65625,9 +74992,8 @@ typedef struct { typedef struct { uint8_t RESERVED_0[3072]; __IO uint32_t CR; /**< Control Register, offset: 0xC00 */ - __I uint32_t SR; /**< Status Register, offset: 0xC04 */ - __IO uint32_t CRC; /**< Cyclic Redundancy Check Register, offset: 0xC08 */ - uint8_t RESERVED_1[244]; + __IO uint32_t SR; /**< Status Register, offset: 0xC04 */ + uint8_t RESERVED_1[248]; struct { /* offset: 0xD00, array step: 0x40 */ __IO uint32_t KEY[4]; /**< AES Key Word, array offset: 0xD00, array step: index*0x40, index2*0x4 */ __IO uint32_t CTR[2]; /**< AES Counter Word, array offset: 0xD10, array step: index*0x40, index2*0x4 */ @@ -65648,6 +75014,15 @@ typedef struct { /*! @name CR - Control Register */ /*! @{ */ + +#define OTFAD_CR_FERR_MASK (0x2U) +#define OTFAD_CR_FERR_SHIFT (1U) +/*! FERR - Force Error + * 0b0..No effect on the SR[KBERE] indicator. + * 0b1..SR[KBERR] is immediately set after a write with this data bit set. + */ +#define OTFAD_CR_FERR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FERR_SHIFT)) & OTFAD_CR_FERR_MASK) + #define OTFAD_CR_FLDM_MASK (0x8U) #define OTFAD_CR_FLDM_SHIFT (3U) /*! FLDM - Force Logically Disabled Mode @@ -65655,52 +75030,65 @@ typedef struct { * 0b1..Force entry into LDM after a write with this data bit set. SR[MODE] signals the operating mode. */ #define OTFAD_CR_FLDM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FLDM_SHIFT)) & OTFAD_CR_FLDM_MASK) + +#define OTFAD_CR_KBSE_MASK (0x10U) +#define OTFAD_CR_KBSE_SHIFT (4U) +/*! KBSE - Key Blob Scramble Enable + * 0b0..Key blob KEK scrambling is disabled. + * 0b1..Key blob KEK scrambling is enabled. + */ +#define OTFAD_CR_KBSE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBSE_SHIFT)) & OTFAD_CR_KBSE_MASK) + +#define OTFAD_CR_KBPE_MASK (0x20U) +#define OTFAD_CR_KBPE_SHIFT (5U) +/*! KBPE - Key Blob Processing Enable + * 0b0..Key blob processing is disabled. + * 0b1..Key blob processing is enabled. + */ +#define OTFAD_CR_KBPE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBPE_SHIFT)) & OTFAD_CR_KBPE_MASK) + #define OTFAD_CR_RRAE_MASK (0x80U) #define OTFAD_CR_RRAE_SHIFT (7U) /*! RRAE - Restricted Register Access Enable * 0b0..Register access is fully enabled. The OTFAD programming model registers can be accessed "normally". - * 0b1..Register access is restricted and only the CR, SR, CRC and optional MDPC registers can be accessed; others are treated as RAZ/WI. + * 0b1..Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI. */ #define OTFAD_CR_RRAE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_RRAE_SHIFT)) & OTFAD_CR_RRAE_MASK) -#define OTFAD_CR_CCTX_MASK (0x30000U) -#define OTFAD_CR_CCTX_SHIFT (16U) -/*! CCTX - CRC Context - * 0b00..Enable CTX0 CRC check. - * 0b01..Enable CTX1 CRC check. - * 0b10..Enable CTX2 CRC check. - * 0b11..Enable CTX3 CRC check. - */ -#define OTFAD_CR_CCTX(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_CCTX_SHIFT)) & OTFAD_CR_CCTX_MASK) -#define OTFAD_CR_CRCE_MASK (0x100000U) -#define OTFAD_CR_CRCE_SHIFT (20U) -/*! CRCE - CRC Enable - * 0b0..CRC-32 is disabled. - * 0b1..CRC-32 for the context defined by CR[CCTRX] is enabled. - */ -#define OTFAD_CR_CRCE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_CRCE_SHIFT)) & OTFAD_CR_CRCE_MASK) -#define OTFAD_CR_CRCI_MASK (0x200000U) -#define OTFAD_CR_CRCI_SHIFT (21U) -/*! CRCI - CRC Initialization - * 0b0..CRC data register is unaffected. - * 0b1..CRC data register is immediately initialized after a write with this data bit set. - */ -#define OTFAD_CR_CRCI(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_CRCI_SHIFT)) & OTFAD_CR_CRCI_MASK) + +#define OTFAD_CR_SKBP_MASK (0x40000000U) +#define OTFAD_CR_SKBP_SHIFT (30U) +/*! SKBP - Start key blob processing + * 0b0..Key blob processing is not initiated. + * 0b1..Properly-enabled key blob processing is initiated. + */ +#define OTFAD_CR_SKBP(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_SKBP_SHIFT)) & OTFAD_CR_SKBP_MASK) + #define OTFAD_CR_GE_MASK (0x80000000U) #define OTFAD_CR_GE_SHIFT (31U) /*! GE - Global OTFAD Enable - * 0b0..OTFAD has decryption disabled. All data fetched by the QuadSPI bypasses OTFAD processing. - * 0b1..OTFAD has decryption enabled, and processes data fetched by the QuadSPI as defined by the hardware configuration. + * 0b0..OTFAD has decryption disabled. All data fetched by the FlexSPI bypasses OTFAD processing. + * 0b1..OTFAD has decryption enabled, and processes data fetched by the FlexSPI as defined by the hardware configuration. */ #define OTFAD_CR_GE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_GE_SHIFT)) & OTFAD_CR_GE_MASK) /*! @} */ /*! @name SR - Status Register */ /*! @{ */ + +#define OTFAD_SR_KBERR_MASK (0x1U) +#define OTFAD_SR_KBERR_SHIFT (0U) +/*! KBERR - Key Blob Error + * 0b0..No key blob error detected. + * 0b1..One or more key blob errors has been detected. + */ +#define OTFAD_SR_KBERR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBERR_SHIFT)) & OTFAD_SR_KBERR_MASK) + #define OTFAD_SR_MDPCP_MASK (0x2U) #define OTFAD_SR_MDPCP_SHIFT (1U) /*! MDPCP - MDPC Present */ #define OTFAD_SR_MDPCP(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MDPCP_SHIFT)) & OTFAD_SR_MDPCP_MASK) + #define OTFAD_SR_MODE_MASK (0xCU) #define OTFAD_SR_MODE_SHIFT (2U) /*! MODE - Operating Mode @@ -65710,43 +75098,119 @@ typedef struct { * 0b11..Operating in Logically Disabled Mode (LDM) */ #define OTFAD_SR_MODE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MODE_SHIFT)) & OTFAD_SR_MODE_MASK) + #define OTFAD_SR_NCTX_MASK (0xF0U) #define OTFAD_SR_NCTX_SHIFT (4U) /*! NCTX - Number of Contexts */ #define OTFAD_SR_NCTX(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_NCTX_SHIFT)) & OTFAD_SR_NCTX_MASK) + +#define OTFAD_SR_CTXER0_MASK (0x100U) +#define OTFAD_SR_CTXER0_SHIFT (8U) +/*! CTXER0 - Context Error + * 0b0..No key blob error was detected for context "n". + * 0b1..A key blob integrity error might have been detected in context "n". + */ +#define OTFAD_SR_CTXER0(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER0_SHIFT)) & OTFAD_SR_CTXER0_MASK) + +#define OTFAD_SR_CTXER1_MASK (0x200U) +#define OTFAD_SR_CTXER1_SHIFT (9U) +/*! CTXER1 - Context Error + * 0b0..No key blob error was detected for context "n". + * 0b1..A key blob integrity error might have been detected in context "n". + */ +#define OTFAD_SR_CTXER1(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER1_SHIFT)) & OTFAD_SR_CTXER1_MASK) + +#define OTFAD_SR_CTXER2_MASK (0x400U) +#define OTFAD_SR_CTXER2_SHIFT (10U) +/*! CTXER2 - Context Error + * 0b0..No key blob error was detected for context "n". + * 0b1..A key blob integrity error might have been detected in context "n". + */ +#define OTFAD_SR_CTXER2(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER2_SHIFT)) & OTFAD_SR_CTXER2_MASK) + +#define OTFAD_SR_CTXER3_MASK (0x800U) +#define OTFAD_SR_CTXER3_SHIFT (11U) +/*! CTXER3 - Context Error + * 0b0..No key blob error was detected for context "n". + * 0b1..A key blob integrity error might have been detected in context "n". + */ +#define OTFAD_SR_CTXER3(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER3_SHIFT)) & OTFAD_SR_CTXER3_MASK) + +#define OTFAD_SR_CTXIE0_MASK (0x10000U) +#define OTFAD_SR_CTXIE0_SHIFT (16U) +/*! CTXIE0 - Context Integrity Error + * 0b0..No key blob integrity error was detected for context "n". + * 0b1..A key blob integrity error was detected in context "n". + */ +#define OTFAD_SR_CTXIE0(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE0_SHIFT)) & OTFAD_SR_CTXIE0_MASK) + +#define OTFAD_SR_CTXIE1_MASK (0x20000U) +#define OTFAD_SR_CTXIE1_SHIFT (17U) +/*! CTXIE1 - Context Integrity Error + * 0b0..No key blob integrity error was detected for context "n". + * 0b1..A key blob integrity error was detected in context "n". + */ +#define OTFAD_SR_CTXIE1(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE1_SHIFT)) & OTFAD_SR_CTXIE1_MASK) + +#define OTFAD_SR_CTXIE2_MASK (0x40000U) +#define OTFAD_SR_CTXIE2_SHIFT (18U) +/*! CTXIE2 - Context Integrity Error + * 0b0..No key blob integrity error was detected for context "n". + * 0b1..A key blob integrity error was detected in context "n". + */ +#define OTFAD_SR_CTXIE2(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE2_SHIFT)) & OTFAD_SR_CTXIE2_MASK) + +#define OTFAD_SR_CTXIE3_MASK (0x80000U) +#define OTFAD_SR_CTXIE3_SHIFT (19U) +/*! CTXIE3 - Context Integrity Error + * 0b0..No key blob integrity error was detected for context "n". + * 0b1..A key blob integrity error was detected in context "n". + */ +#define OTFAD_SR_CTXIE3(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE3_SHIFT)) & OTFAD_SR_CTXIE3_MASK) + #define OTFAD_SR_HRL_MASK (0xF000000U) #define OTFAD_SR_HRL_SHIFT (24U) /*! HRL - Hardware Revision Level */ #define OTFAD_SR_HRL(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_HRL_SHIFT)) & OTFAD_SR_HRL_MASK) + #define OTFAD_SR_RRAM_MASK (0x10000000U) #define OTFAD_SR_RRAM_SHIFT (28U) /*! RRAM - Restricted Register Access Mode * 0b0..Register access is fully enabled. The OTFAD programming model registers can be accessed "normally". - * 0b1..Register access is restricted and only the CR, SR, CRC and optional MDPC registers can be accessed; others are treated as RAZ/WI. + * 0b1..Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI. */ #define OTFAD_SR_RRAM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK) + #define OTFAD_SR_GEM_MASK (0x20000000U) #define OTFAD_SR_GEM_SHIFT (29U) /*! GEM - Global Enable Mode - * 0b0..OTFAD is disabled. All data fetched by the QuadSPI bypasses OTFAD processing. - * 0b1..OTFAD is enabled, and processes data fetched by the QuadSPI as defined by the hardware configuration. + * 0b0..OTFAD is disabled. All data fetched by the FlexSPI bypasses OTFAD processing. + * 0b1..OTFAD is enabled, and processes data fetched by the FlexSPI as defined by the hardware configuration. */ #define OTFAD_SR_GEM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_GEM_SHIFT)) & OTFAD_SR_GEM_MASK) -/*! @} */ -/*! @name CRC - Cyclic Redundancy Check Register */ -/*! @{ */ -#define OTFAD_CRC_CRCD_MASK (0xFFFFFFFFU) -#define OTFAD_CRC_CRCD_SHIFT (0U) -/*! CRCD - CRC Data. +#define OTFAD_SR_KBPE_MASK (0x40000000U) +#define OTFAD_SR_KBPE_SHIFT (30U) +/*! KBPE - Key Blob Processing Enable + * 0b0..Key blob processing is not enabled. + * 0b1..Key blob processing is enabled. + */ +#define OTFAD_SR_KBPE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBPE_SHIFT)) & OTFAD_SR_KBPE_MASK) + +#define OTFAD_SR_KBD_MASK (0x80000000U) +#define OTFAD_SR_KBD_SHIFT (31U) +/*! KBD - Key Blob Processing Done + * 0b0..Key blob processing was not enabled, or is not complete. + * 0b1..Key blob processing was enabled and is complete. */ -#define OTFAD_CRC_CRCD(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CRC_CRCD_SHIFT)) & OTFAD_CRC_CRCD_MASK) +#define OTFAD_SR_KBD(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBD_SHIFT)) & OTFAD_SR_KBD_MASK) /*! @} */ /*! @name KEY - AES Key Word */ /*! @{ */ + #define OTFAD_KEY_KEY_MASK (0xFFFFFFFFU) #define OTFAD_KEY_KEY_SHIFT (0U) /*! KEY - AES Key @@ -65762,6 +75226,7 @@ typedef struct { /*! @name CTR - AES Counter Word */ /*! @{ */ + #define OTFAD_CTR_CTR_MASK (0xFFFFFFFFU) #define OTFAD_CTR_CTR_SHIFT (0U) /*! CTR - AES Counter @@ -65777,6 +75242,7 @@ typedef struct { /*! @name RGD_W0 - AES Region Descriptor Word0 */ /*! @{ */ + #define OTFAD_RGD_W0_SRTADDR_MASK (0xFFFFFC00U) #define OTFAD_RGD_W0_SRTADDR_SHIFT (10U) /*! SRTADDR - Start Address @@ -65789,6 +75255,7 @@ typedef struct { /*! @name RGD_W1 - AES Region Descriptor Word1 */ /*! @{ */ + #define OTFAD_RGD_W1_VLD_MASK (0x1U) #define OTFAD_RGD_W1_VLD_SHIFT (0U) /*! VLD - Valid @@ -65796,6 +75263,7 @@ typedef struct { * 0b1..Context is valid. */ #define OTFAD_RGD_W1_VLD(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_VLD_SHIFT)) & OTFAD_RGD_W1_VLD_MASK) + #define OTFAD_RGD_W1_ADE_MASK (0x2U) #define OTFAD_RGD_W1_ADE_SHIFT (1U) /*! ADE - AES Decryption Enable. @@ -65803,6 +75271,7 @@ typedef struct { * 0b1..Perform the CTR-AES128 mode decryption on the fetched data. */ #define OTFAD_RGD_W1_ADE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_ADE_SHIFT)) & OTFAD_RGD_W1_ADE_MASK) + #define OTFAD_RGD_W1_RO_MASK (0x4U) #define OTFAD_RGD_W1_RO_SHIFT (2U) /*! RO - Read-Only @@ -65810,6 +75279,7 @@ typedef struct { * 0b1..The context registers are read-only and accesses may be further restricted based on SR[RRAM]. */ #define OTFAD_RGD_W1_RO(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_RO_SHIFT)) & OTFAD_RGD_W1_RO_MASK) + #define OTFAD_RGD_W1_ENDADDR_MASK (0xFFFFFC00U) #define OTFAD_RGD_W1_ENDADDR_SHIFT (10U) /*! ENDADDR - End Address @@ -65891,46 +75361,55 @@ typedef struct { /*! @name CTRL_1 - PDM Control register 1 */ /*! @{ */ + #define PDM_CTRL_1_CH0EN_MASK (0x1U) #define PDM_CTRL_1_CH0EN_SHIFT (0U) /*! CH0EN - Channel 0 Enable */ #define PDM_CTRL_1_CH0EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH0EN_SHIFT)) & PDM_CTRL_1_CH0EN_MASK) + #define PDM_CTRL_1_CH1EN_MASK (0x2U) #define PDM_CTRL_1_CH1EN_SHIFT (1U) /*! CH1EN - Channel 1 Enable */ #define PDM_CTRL_1_CH1EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH1EN_SHIFT)) & PDM_CTRL_1_CH1EN_MASK) + #define PDM_CTRL_1_CH2EN_MASK (0x4U) #define PDM_CTRL_1_CH2EN_SHIFT (2U) /*! CH2EN - Channel 2 Enable */ #define PDM_CTRL_1_CH2EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH2EN_SHIFT)) & PDM_CTRL_1_CH2EN_MASK) + #define PDM_CTRL_1_CH3EN_MASK (0x8U) #define PDM_CTRL_1_CH3EN_SHIFT (3U) /*! CH3EN - Channel 3 Enable */ #define PDM_CTRL_1_CH3EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH3EN_SHIFT)) & PDM_CTRL_1_CH3EN_MASK) + #define PDM_CTRL_1_CH4EN_MASK (0x10U) #define PDM_CTRL_1_CH4EN_SHIFT (4U) /*! CH4EN - Channel 4 Enable */ #define PDM_CTRL_1_CH4EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH4EN_SHIFT)) & PDM_CTRL_1_CH4EN_MASK) + #define PDM_CTRL_1_CH5EN_MASK (0x20U) #define PDM_CTRL_1_CH5EN_SHIFT (5U) /*! CH5EN - Channel 5 Enable */ #define PDM_CTRL_1_CH5EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH5EN_SHIFT)) & PDM_CTRL_1_CH5EN_MASK) + #define PDM_CTRL_1_CH6EN_MASK (0x40U) #define PDM_CTRL_1_CH6EN_SHIFT (6U) /*! CH6EN - Channel 6 Enable */ #define PDM_CTRL_1_CH6EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH6EN_SHIFT)) & PDM_CTRL_1_CH6EN_MASK) + #define PDM_CTRL_1_CH7EN_MASK (0x80U) #define PDM_CTRL_1_CH7EN_SHIFT (7U) /*! CH7EN - Channel 7 Enable */ #define PDM_CTRL_1_CH7EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH7EN_SHIFT)) & PDM_CTRL_1_CH7EN_MASK) + #define PDM_CTRL_1_ERREN_MASK (0x800000U) #define PDM_CTRL_1_ERREN_SHIFT (23U) /*! ERREN - Error Interruption Enable @@ -65938,6 +75417,7 @@ typedef struct { * 0b1..Error Interrupts enabled */ #define PDM_CTRL_1_ERREN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_ERREN_SHIFT)) & PDM_CTRL_1_ERREN_MASK) + #define PDM_CTRL_1_DISEL_MASK (0x3000000U) #define PDM_CTRL_1_DISEL_SHIFT (24U) /*! DISEL - DMA Interrupt Selection @@ -65947,13 +75427,15 @@ typedef struct { * 0b11..Reserved */ #define PDM_CTRL_1_DISEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DISEL_SHIFT)) & PDM_CTRL_1_DISEL_MASK) + #define PDM_CTRL_1_DBGE_MASK (0x4000000U) #define PDM_CTRL_1_DBGE_SHIFT (26U) /*! DBGE - Module Enable in Debug - * 0b0..PDM is disabled in debug mode, after completing the current frame. - * 0b1..PDM is enabled in debug mode. + * 0b0..Disabled after completing the current frame + * 0b1..Enabled */ #define PDM_CTRL_1_DBGE(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBGE_SHIFT)) & PDM_CTRL_1_DBGE_MASK) + #define PDM_CTRL_1_SRES_MASK (0x8000000U) #define PDM_CTRL_1_SRES_SHIFT (27U) /*! SRES - Software-reset bit @@ -65961,25 +75443,29 @@ typedef struct { * 0b1..Software reset */ #define PDM_CTRL_1_SRES(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_SRES_SHIFT)) & PDM_CTRL_1_SRES_MASK) + #define PDM_CTRL_1_DBG_MASK (0x10000000U) #define PDM_CTRL_1_DBG_SHIFT (28U) /*! DBG - Debug Mode - * 0b0..Normal Mode. - * 0b1..Debug Mode. + * 0b0..Normal Mode + * 0b1..Debug Mode */ #define PDM_CTRL_1_DBG(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBG_SHIFT)) & PDM_CTRL_1_DBG_MASK) + #define PDM_CTRL_1_PDMIEN_MASK (0x20000000U) #define PDM_CTRL_1_PDMIEN_SHIFT (29U) /*! PDMIEN - PDM Enable * 0b0..PDM stopped - * 0b1..PDM operation started. + * 0b1..PDM operation started */ #define PDM_CTRL_1_PDMIEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_PDMIEN_SHIFT)) & PDM_CTRL_1_PDMIEN_MASK) + #define PDM_CTRL_1_DOZEN_MASK (0x40000000U) #define PDM_CTRL_1_DOZEN_SHIFT (30U) /*! DOZEN - DOZE enable */ #define PDM_CTRL_1_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DOZEN_SHIFT)) & PDM_CTRL_1_DOZEN_MASK) + #define PDM_CTRL_1_MDIS_MASK (0x80000000U) #define PDM_CTRL_1_MDIS_SHIFT (31U) /*! MDIS - Module Disable @@ -65991,112 +75477,127 @@ typedef struct { /*! @name CTRL_2 - PDM Control register 2 */ /*! @{ */ + #define PDM_CTRL_2_CLKDIV_MASK (0xFFU) #define PDM_CTRL_2_CLKDIV_SHIFT (0U) /*! CLKDIV - Clock Divider */ #define PDM_CTRL_2_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIV_SHIFT)) & PDM_CTRL_2_CLKDIV_MASK) + #define PDM_CTRL_2_CICOSR_MASK (0xF0000U) #define PDM_CTRL_2_CICOSR_SHIFT (16U) -/*! CICOSR - CIC Oversampling Rate +/*! CICOSR - CIC Decimation Rate */ #define PDM_CTRL_2_CICOSR(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CICOSR_SHIFT)) & PDM_CTRL_2_CICOSR_MASK) + #define PDM_CTRL_2_QSEL_MASK (0xE000000U) #define PDM_CTRL_2_QSEL_SHIFT (25U) -/*! QSEL - Quality Select - * 0b001..High quality mode. - * 0b000..Medium quality mode. - * 0b111..Low quality mode. - * 0b110..Very low quality 0 mode. - * 0b101..Very low quality 1 mode. - * 0b100..Very low quality 2 mode. +/*! QSEL - Quality Mode + * 0b001..High quality mode + * 0b000..Medium quality mode + * 0b111..Low quality mode + * 0b110..Very low quality 0 mode + * 0b101..Very low quality 1 mode + * 0b100..Very low quality 2 mode */ #define PDM_CTRL_2_QSEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_QSEL_SHIFT)) & PDM_CTRL_2_QSEL_MASK) /*! @} */ /*! @name STAT - PDM Status register */ /*! @{ */ + #define PDM_STAT_CH0F_MASK (0x1U) #define PDM_STAT_CH0F_SHIFT (0U) /*! CH0F - Channel 0 Output Data Flag - * 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field. - * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field. + * 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field + * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field */ #define PDM_STAT_CH0F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH0F_SHIFT)) & PDM_STAT_CH0F_MASK) + #define PDM_STAT_CH1F_MASK (0x2U) #define PDM_STAT_CH1F_SHIFT (1U) /*! CH1F - Channel 1 Output Data Flag - * 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field. - * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field. + * 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field + * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field */ #define PDM_STAT_CH1F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH1F_SHIFT)) & PDM_STAT_CH1F_MASK) + #define PDM_STAT_CH2F_MASK (0x4U) #define PDM_STAT_CH2F_SHIFT (2U) /*! CH2F - Channel 2 Output Data Flag - * 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field. - * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field. + * 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field + * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field */ #define PDM_STAT_CH2F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH2F_SHIFT)) & PDM_STAT_CH2F_MASK) + #define PDM_STAT_CH3F_MASK (0x8U) #define PDM_STAT_CH3F_SHIFT (3U) /*! CH3F - Channel 3 Output Data Flag - * 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field. - * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field. + * 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field + * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field */ #define PDM_STAT_CH3F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH3F_SHIFT)) & PDM_STAT_CH3F_MASK) + #define PDM_STAT_CH4F_MASK (0x10U) #define PDM_STAT_CH4F_SHIFT (4U) /*! CH4F - Channel 4 Output Data Flag - * 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field. - * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field. + * 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field + * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field */ #define PDM_STAT_CH4F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH4F_SHIFT)) & PDM_STAT_CH4F_MASK) + #define PDM_STAT_CH5F_MASK (0x20U) #define PDM_STAT_CH5F_SHIFT (5U) /*! CH5F - Channel 5 Output Data Flag - * 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field. - * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field. + * 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field + * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field */ #define PDM_STAT_CH5F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH5F_SHIFT)) & PDM_STAT_CH5F_MASK) + #define PDM_STAT_CH6F_MASK (0x40U) #define PDM_STAT_CH6F_SHIFT (6U) /*! CH6F - Channel 6 Output Data Flag - * 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field. - * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field. + * 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field + * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field */ #define PDM_STAT_CH6F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH6F_SHIFT)) & PDM_STAT_CH6F_MASK) + #define PDM_STAT_CH7F_MASK (0x80U) #define PDM_STAT_CH7F_SHIFT (7U) /*! CH7F - Channel 7 Output Data Flag - * 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field. - * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field. + * 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field + * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field */ #define PDM_STAT_CH7F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH7F_SHIFT)) & PDM_STAT_CH7F_MASK) + #define PDM_STAT_LOWFREQF_MASK (0x20000000U) #define PDM_STAT_LOWFREQF_SHIFT (29U) /*! LOWFREQF - Low Frequency Flag - * 0b0..CLKDIV value is OK. - * 0b1..CLKDIV value is too low. + * 0b0..CLKDIV value is OK + * 0b1..CLKDIV value is too low */ #define PDM_STAT_LOWFREQF(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_LOWFREQF_SHIFT)) & PDM_STAT_LOWFREQF_MASK) + #define PDM_STAT_FIR_RDY_MASK (0x40000000U) #define PDM_STAT_FIR_RDY_SHIFT (30U) /*! FIR_RDY - Filter Data Ready - * 0b0..Filter data is not reliable. - * 0b1..Filter data is reliable. + * 0b0..Filter data is not reliable + * 0b1..Filter data is reliable */ #define PDM_STAT_FIR_RDY(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_FIR_RDY_SHIFT)) & PDM_STAT_FIR_RDY_MASK) + #define PDM_STAT_BSY_FIL_MASK (0x80000000U) #define PDM_STAT_BSY_FIL_SHIFT (31U) /*! BSY_FIL - Busy Flag - * 0b1..PDM is running. - * 0b0..PDM is stopped. + * 0b1..PDM is running + * 0b0..PDM is stopped */ #define PDM_STAT_BSY_FIL(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_BSY_FIL_SHIFT)) & PDM_STAT_BSY_FIL_MASK) /*! @} */ /*! @name FIFO_CTRL - PDM FIFO Control register */ /*! @{ */ + #define PDM_FIFO_CTRL_FIFOWMK_MASK (0x7U) #define PDM_FIFO_CTRL_FIFOWMK_SHIFT (0U) /*! FIFOWMK - FIFO Watermark Control @@ -66106,6 +75607,7 @@ typedef struct { /*! @name FIFO_STAT - PDM FIFO Status register */ /*! @{ */ + #define PDM_FIFO_STAT_FIFOOVF0_MASK (0x1U) #define PDM_FIFO_STAT_FIFOOVF0_SHIFT (0U) /*! FIFOOVF0 - FIFO Overflow Exception flag for Channel 0 @@ -66113,6 +75615,7 @@ typedef struct { * 0b1..Exception by FIFO overflow */ #define PDM_FIFO_STAT_FIFOOVF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF0_SHIFT)) & PDM_FIFO_STAT_FIFOOVF0_MASK) + #define PDM_FIFO_STAT_FIFOOVF1_MASK (0x2U) #define PDM_FIFO_STAT_FIFOOVF1_SHIFT (1U) /*! FIFOOVF1 - FIFO Overflow Exception flag for Channel 1 @@ -66120,6 +75623,7 @@ typedef struct { * 0b1..Exception by FIFO overflow */ #define PDM_FIFO_STAT_FIFOOVF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF1_SHIFT)) & PDM_FIFO_STAT_FIFOOVF1_MASK) + #define PDM_FIFO_STAT_FIFOOVF2_MASK (0x4U) #define PDM_FIFO_STAT_FIFOOVF2_SHIFT (2U) /*! FIFOOVF2 - FIFO Overflow Exception flag for Channel 2 @@ -66127,6 +75631,7 @@ typedef struct { * 0b1..Exception by FIFO overflow */ #define PDM_FIFO_STAT_FIFOOVF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF2_SHIFT)) & PDM_FIFO_STAT_FIFOOVF2_MASK) + #define PDM_FIFO_STAT_FIFOOVF3_MASK (0x8U) #define PDM_FIFO_STAT_FIFOOVF3_SHIFT (3U) /*! FIFOOVF3 - FIFO Overflow Exception flag for Channel 3 @@ -66134,6 +75639,7 @@ typedef struct { * 0b1..Exception by FIFO overflow */ #define PDM_FIFO_STAT_FIFOOVF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF3_SHIFT)) & PDM_FIFO_STAT_FIFOOVF3_MASK) + #define PDM_FIFO_STAT_FIFOOVF4_MASK (0x10U) #define PDM_FIFO_STAT_FIFOOVF4_SHIFT (4U) /*! FIFOOVF4 - FIFO Overflow Exception flag for Channel 4 @@ -66141,6 +75647,7 @@ typedef struct { * 0b1..Exception by FIFO overflow */ #define PDM_FIFO_STAT_FIFOOVF4(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF4_SHIFT)) & PDM_FIFO_STAT_FIFOOVF4_MASK) + #define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U) #define PDM_FIFO_STAT_FIFOOVF5_SHIFT (5U) /*! FIFOOVF5 - FIFO Overflow Exception flag for Channel 5 @@ -66148,6 +75655,7 @@ typedef struct { * 0b1..Exception by FIFO overflow */ #define PDM_FIFO_STAT_FIFOOVF5(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK) + #define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U) #define PDM_FIFO_STAT_FIFOOVF6_SHIFT (6U) /*! FIFOOVF6 - FIFO Overflow Exception flag for Channel 6 @@ -66155,6 +75663,7 @@ typedef struct { * 0b1..Exception by FIFO overflow */ #define PDM_FIFO_STAT_FIFOOVF6(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK) + #define PDM_FIFO_STAT_FIFOOVF7_MASK (0x80U) #define PDM_FIFO_STAT_FIFOOVF7_SHIFT (7U) /*! FIFOOVF7 - FIFO Overflow Exception flag for Channel 7 @@ -66162,6 +75671,7 @@ typedef struct { * 0b1..Exception by FIFO overflow */ #define PDM_FIFO_STAT_FIFOOVF7(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF7_SHIFT)) & PDM_FIFO_STAT_FIFOOVF7_MASK) + #define PDM_FIFO_STAT_FIFOUND0_MASK (0x100U) #define PDM_FIFO_STAT_FIFOUND0_SHIFT (8U) /*! FIFOUND0 - FIFO Underflow Exception flag for Channel 0 @@ -66169,6 +75679,7 @@ typedef struct { * 0b1..Exception by FIFO underflow */ #define PDM_FIFO_STAT_FIFOUND0(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND0_SHIFT)) & PDM_FIFO_STAT_FIFOUND0_MASK) + #define PDM_FIFO_STAT_FIFOUND1_MASK (0x200U) #define PDM_FIFO_STAT_FIFOUND1_SHIFT (9U) /*! FIFOUND1 - FIFO Underflow Exception flag for Channel 1 @@ -66176,6 +75687,7 @@ typedef struct { * 0b1..Exception by FIFO underflow */ #define PDM_FIFO_STAT_FIFOUND1(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND1_SHIFT)) & PDM_FIFO_STAT_FIFOUND1_MASK) + #define PDM_FIFO_STAT_FIFOUND2_MASK (0x400U) #define PDM_FIFO_STAT_FIFOUND2_SHIFT (10U) /*! FIFOUND2 - FIFO Underflow Exception flag for Channel 2 @@ -66183,6 +75695,7 @@ typedef struct { * 0b1..Exception by FIFO underflow */ #define PDM_FIFO_STAT_FIFOUND2(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND2_SHIFT)) & PDM_FIFO_STAT_FIFOUND2_MASK) + #define PDM_FIFO_STAT_FIFOUND3_MASK (0x800U) #define PDM_FIFO_STAT_FIFOUND3_SHIFT (11U) /*! FIFOUND3 - FIFO Underflow Exception flag for Channel 3 @@ -66190,6 +75703,7 @@ typedef struct { * 0b1..Exception by FIFO underflow */ #define PDM_FIFO_STAT_FIFOUND3(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND3_SHIFT)) & PDM_FIFO_STAT_FIFOUND3_MASK) + #define PDM_FIFO_STAT_FIFOUND4_MASK (0x1000U) #define PDM_FIFO_STAT_FIFOUND4_SHIFT (12U) /*! FIFOUND4 - FIFO Underflow Exception flag for Channel 4 @@ -66197,6 +75711,7 @@ typedef struct { * 0b1..Exception by FIFO underflow */ #define PDM_FIFO_STAT_FIFOUND4(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND4_SHIFT)) & PDM_FIFO_STAT_FIFOUND4_MASK) + #define PDM_FIFO_STAT_FIFOUND5_MASK (0x2000U) #define PDM_FIFO_STAT_FIFOUND5_SHIFT (13U) /*! FIFOUND5 - FIFO Underflow Exception flag for Channel 5 @@ -66204,6 +75719,7 @@ typedef struct { * 0b1..Exception by FIFO underflow */ #define PDM_FIFO_STAT_FIFOUND5(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND5_SHIFT)) & PDM_FIFO_STAT_FIFOUND5_MASK) + #define PDM_FIFO_STAT_FIFOUND6_MASK (0x4000U) #define PDM_FIFO_STAT_FIFOUND6_SHIFT (14U) /*! FIFOUND6 - FIFO Underflow Exception flag for Channel 6 @@ -66211,6 +75727,7 @@ typedef struct { * 0b1..Exception by FIFO underflow */ #define PDM_FIFO_STAT_FIFOUND6(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND6_SHIFT)) & PDM_FIFO_STAT_FIFOUND6_MASK) + #define PDM_FIFO_STAT_FIFOUND7_MASK (0x8000U) #define PDM_FIFO_STAT_FIFOUND7_SHIFT (15U) /*! FIFOUND7 - FIFO Underflow Exception flag for Channel 7 @@ -66222,6 +75739,7 @@ typedef struct { /*! @name DATACH - PDM Output Result Register */ /*! @{ */ + #define PDM_DATACH_DATA_MASK (0xFFFFFFFFU) #define PDM_DATACH_DATA_SHIFT (0U) /*! DATA - Channel n Data @@ -66234,117 +75752,133 @@ typedef struct { /*! @name DC_CTRL - PDM DC Remover Control register */ /*! @{ */ + #define PDM_DC_CTRL_DCCONFIG0_MASK (0x3U) #define PDM_DC_CTRL_DCCONFIG0_SHIFT (0U) /*! DCCONFIG0 - Channel 0 DC Remover Configuration - * 0b11..DC Remover is bypassed. - * 0b00..DC Remover cut-off at 21Hz. - * 0b01..DC Remover cut-off at 83Hz. - * 0b10..DC Remover cut-off at 152Hz. + * 0b11..DC Remover is bypassed + * 0b00..DC Remover cut-off at 21Hz + * 0b01..DC Remover cut-off at 83Hz + * 0b10..DC Remover cut-off at 152Hz */ #define PDM_DC_CTRL_DCCONFIG0(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_CTRL_DCCONFIG0_MASK) + #define PDM_DC_CTRL_DCCONFIG1_MASK (0xCU) #define PDM_DC_CTRL_DCCONFIG1_SHIFT (2U) /*! DCCONFIG1 - Channel 1 DC Remover Configuration - * 0b11..DC Remover is bypassed. - * 0b00..DC Remover cut-off at 21Hz. - * 0b01..DC Remover cut-off at 83Hz. - * 0b10..DC Remover cut-off at 152Hz. + * 0b11..DC Remover is bypassed + * 0b00..DC Remover cut-off at 21Hz + * 0b01..DC Remover cut-off at 83Hz + * 0b10..DC Remover cut-off at 152Hz */ #define PDM_DC_CTRL_DCCONFIG1(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_CTRL_DCCONFIG1_MASK) + #define PDM_DC_CTRL_DCCONFIG2_MASK (0x30U) #define PDM_DC_CTRL_DCCONFIG2_SHIFT (4U) /*! DCCONFIG2 - Channel 2 DC Remover Configuration - * 0b11..DC Remover is bypassed. - * 0b00..DC Remover cut-off at 21Hz. - * 0b01..DC Remover cut-off at 83Hz. - * 0b10..DC Remover cut-off at 152Hz. + * 0b11..DC Remover is bypassed + * 0b00..DC Remover cut-off at 21Hz + * 0b01..DC Remover cut-off at 83Hz + * 0b10..DC Remover cut-off at 152Hz */ #define PDM_DC_CTRL_DCCONFIG2(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_CTRL_DCCONFIG2_MASK) + #define PDM_DC_CTRL_DCCONFIG3_MASK (0xC0U) #define PDM_DC_CTRL_DCCONFIG3_SHIFT (6U) /*! DCCONFIG3 - Channel 3 DC Remover Configuration - * 0b11..DC Remover is bypassed. - * 0b00..DC Remover cut-off at 21Hz. - * 0b01..DC Remover cut-off at 83Hz. - * 0b10..DC Remover cut-off at 152Hz. + * 0b11..DC Remover is bypassed + * 0b00..DC Remover cut-off at 21Hz + * 0b01..DC Remover cut-off at 83Hz + * 0b10..DC Remover cut-off at 152Hz */ #define PDM_DC_CTRL_DCCONFIG3(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_CTRL_DCCONFIG3_MASK) + #define PDM_DC_CTRL_DCCONFIG4_MASK (0x300U) #define PDM_DC_CTRL_DCCONFIG4_SHIFT (8U) /*! DCCONFIG4 - Channel 4 DC Remover Configuration - * 0b11..DC Remover is bypassed. - * 0b00..DC Remover cut-off at 21Hz. - * 0b01..DC Remover cut-off at 83Hz. - * 0b10..DC Remover cut-off at 152Hz. + * 0b11..DC Remover is bypassed + * 0b00..DC Remover cut-off at 21Hz + * 0b01..DC Remover cut-off at 83Hz + * 0b10..DC Remover cut-off at 152Hz */ #define PDM_DC_CTRL_DCCONFIG4(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG4_SHIFT)) & PDM_DC_CTRL_DCCONFIG4_MASK) + #define PDM_DC_CTRL_DCCONFIG5_MASK (0xC00U) #define PDM_DC_CTRL_DCCONFIG5_SHIFT (10U) /*! DCCONFIG5 - Channel 5 DC Remover Configuration - * 0b11..DC Remover is bypassed. - * 0b00..DC Remover cut-off at 21Hz. - * 0b01..DC Remover cut-off at 83Hz. - * 0b10..DC Remover cut-off at 152Hz. + * 0b11..DC Remover is bypassed + * 0b00..DC Remover cut-off at 21Hz + * 0b01..DC Remover cut-off at 83Hz + * 0b10..DC Remover cut-off at 152Hz */ #define PDM_DC_CTRL_DCCONFIG5(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG5_SHIFT)) & PDM_DC_CTRL_DCCONFIG5_MASK) + #define PDM_DC_CTRL_DCCONFIG6_MASK (0x3000U) #define PDM_DC_CTRL_DCCONFIG6_SHIFT (12U) /*! DCCONFIG6 - Channel 6 DC Remover Configuration - * 0b11..DC Remover is bypassed. - * 0b00..DC Remover cut-off at 21Hz. - * 0b01..DC Remover cut-off at 83Hz. - * 0b10..DC Remover cut-off at 152Hz. + * 0b11..DC Remover is bypassed + * 0b00..DC Remover cut-off at 21Hz + * 0b01..DC Remover cut-off at 83Hz + * 0b10..DC Remover cut-off at 152Hz */ #define PDM_DC_CTRL_DCCONFIG6(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG6_SHIFT)) & PDM_DC_CTRL_DCCONFIG6_MASK) + #define PDM_DC_CTRL_DCCONFIG7_MASK (0xC000U) #define PDM_DC_CTRL_DCCONFIG7_SHIFT (14U) /*! DCCONFIG7 - Channel 7 DC Remover Configuration - * 0b11..DC Remover is bypassed. - * 0b00..DC Remover cut-off at 21Hz. - * 0b01..DC Remover cut-off at 83Hz. - * 0b10..DC Remover cut-off at 152Hz. + * 0b11..DC Remover is bypassed + * 0b00..DC Remover cut-off at 21Hz + * 0b01..DC Remover cut-off at 83Hz + * 0b10..DC Remover cut-off at 152Hz */ #define PDM_DC_CTRL_DCCONFIG7(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG7_SHIFT)) & PDM_DC_CTRL_DCCONFIG7_MASK) /*! @} */ /*! @name RANGE_CTRL - PDM Range Control register */ /*! @{ */ + #define PDM_RANGE_CTRL_RANGEADJ0_MASK (0xFU) #define PDM_RANGE_CTRL_RANGEADJ0_SHIFT (0U) /*! RANGEADJ0 - Channel 0 Range Adjustment */ #define PDM_RANGE_CTRL_RANGEADJ0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ0_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ0_MASK) + #define PDM_RANGE_CTRL_RANGEADJ1_MASK (0xF0U) #define PDM_RANGE_CTRL_RANGEADJ1_SHIFT (4U) /*! RANGEADJ1 - Channel 1 Range Adjustment */ #define PDM_RANGE_CTRL_RANGEADJ1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ1_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ1_MASK) + #define PDM_RANGE_CTRL_RANGEADJ2_MASK (0xF00U) #define PDM_RANGE_CTRL_RANGEADJ2_SHIFT (8U) /*! RANGEADJ2 - Channel 2 Range Adjustment */ #define PDM_RANGE_CTRL_RANGEADJ2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ2_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ2_MASK) + #define PDM_RANGE_CTRL_RANGEADJ3_MASK (0xF000U) #define PDM_RANGE_CTRL_RANGEADJ3_SHIFT (12U) /*! RANGEADJ3 - Channel 3 Range Adjustment */ #define PDM_RANGE_CTRL_RANGEADJ3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ3_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ3_MASK) + #define PDM_RANGE_CTRL_RANGEADJ4_MASK (0xF0000U) #define PDM_RANGE_CTRL_RANGEADJ4_SHIFT (16U) /*! RANGEADJ4 - Channel 4 Range Adjustment */ #define PDM_RANGE_CTRL_RANGEADJ4(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ4_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ4_MASK) + #define PDM_RANGE_CTRL_RANGEADJ5_MASK (0xF00000U) #define PDM_RANGE_CTRL_RANGEADJ5_SHIFT (20U) /*! RANGEADJ5 - Channel 5 Range Adjustment */ #define PDM_RANGE_CTRL_RANGEADJ5(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ5_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ5_MASK) + #define PDM_RANGE_CTRL_RANGEADJ6_MASK (0xF000000U) #define PDM_RANGE_CTRL_RANGEADJ6_SHIFT (24U) /*! RANGEADJ6 - Channel 6 Range Adjustment */ #define PDM_RANGE_CTRL_RANGEADJ6(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ6_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ6_MASK) + #define PDM_RANGE_CTRL_RANGEADJ7_MASK (0xF0000000U) #define PDM_RANGE_CTRL_RANGEADJ7_SHIFT (28U) /*! RANGEADJ7 - Channel 7 Range Adjustment @@ -66354,134 +75888,153 @@ typedef struct { /*! @name RANGE_STAT - PDM Range Status register */ /*! @{ */ + #define PDM_RANGE_STAT_RANGEOVF0_MASK (0x1U) #define PDM_RANGE_STAT_RANGEOVF0_SHIFT (0U) /*! RANGEOVF0 - Channel 0 Range Overflow Error Flag - * 0b0..No exception by range overflow. - * 0b1..Exception by range overflow. + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow */ #define PDM_RANGE_STAT_RANGEOVF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF0_SHIFT)) & PDM_RANGE_STAT_RANGEOVF0_MASK) + #define PDM_RANGE_STAT_RANGEOVF1_MASK (0x2U) #define PDM_RANGE_STAT_RANGEOVF1_SHIFT (1U) /*! RANGEOVF1 - Channel 1 Range Overflow Error Flag - * 0b0..No exception by range overflow. - * 0b1..Exception by range overflow. + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow */ #define PDM_RANGE_STAT_RANGEOVF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF1_SHIFT)) & PDM_RANGE_STAT_RANGEOVF1_MASK) + #define PDM_RANGE_STAT_RANGEOVF2_MASK (0x4U) #define PDM_RANGE_STAT_RANGEOVF2_SHIFT (2U) /*! RANGEOVF2 - Channel 2 Range Overflow Error Flag - * 0b0..No exception by range overflow. - * 0b1..Exception by range overflow. + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow */ #define PDM_RANGE_STAT_RANGEOVF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF2_SHIFT)) & PDM_RANGE_STAT_RANGEOVF2_MASK) + #define PDM_RANGE_STAT_RANGEOVF3_MASK (0x8U) #define PDM_RANGE_STAT_RANGEOVF3_SHIFT (3U) /*! RANGEOVF3 - Channel 3 Range Overflow Error Flag - * 0b0..No exception by range overflow. - * 0b1..Exception by range overflow. + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow */ #define PDM_RANGE_STAT_RANGEOVF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF3_SHIFT)) & PDM_RANGE_STAT_RANGEOVF3_MASK) + #define PDM_RANGE_STAT_RANGEOVF4_MASK (0x10U) #define PDM_RANGE_STAT_RANGEOVF4_SHIFT (4U) /*! RANGEOVF4 - Channel 4 Range Overflow Error Flag - * 0b0..No exception by range overflow. - * 0b1..Exception by range overflow. + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow */ #define PDM_RANGE_STAT_RANGEOVF4(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF4_SHIFT)) & PDM_RANGE_STAT_RANGEOVF4_MASK) + #define PDM_RANGE_STAT_RANGEOVF5_MASK (0x20U) #define PDM_RANGE_STAT_RANGEOVF5_SHIFT (5U) /*! RANGEOVF5 - Channel 5 Range Overflow Error Flag - * 0b0..No exception by range overflow. - * 0b1..Exception by range overflow. + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow */ #define PDM_RANGE_STAT_RANGEOVF5(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF5_SHIFT)) & PDM_RANGE_STAT_RANGEOVF5_MASK) + #define PDM_RANGE_STAT_RANGEOVF6_MASK (0x40U) #define PDM_RANGE_STAT_RANGEOVF6_SHIFT (6U) /*! RANGEOVF6 - Channel 6 Range Overflow Error Flag - * 0b0..No exception by range overflow. - * 0b1..Exception by range overflow. + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow */ #define PDM_RANGE_STAT_RANGEOVF6(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF6_SHIFT)) & PDM_RANGE_STAT_RANGEOVF6_MASK) + #define PDM_RANGE_STAT_RANGEOVF7_MASK (0x80U) #define PDM_RANGE_STAT_RANGEOVF7_SHIFT (7U) /*! RANGEOVF7 - Channel 7 Range Overflow Error Flag - * 0b0..No exception by range overflow. - * 0b1..Exception by range overflow. + * 0b0..No exception by range overflow + * 0b1..Exception by range overflow */ #define PDM_RANGE_STAT_RANGEOVF7(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF7_SHIFT)) & PDM_RANGE_STAT_RANGEOVF7_MASK) + #define PDM_RANGE_STAT_RANGEUNF0_MASK (0x10000U) #define PDM_RANGE_STAT_RANGEUNF0_SHIFT (16U) /*! RANGEUNF0 - Channel 0 Range Underflow Error Flag - * 0b0..No exception by range underflow. - * 0b1..Exception by range underflow. + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow */ #define PDM_RANGE_STAT_RANGEUNF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF0_SHIFT)) & PDM_RANGE_STAT_RANGEUNF0_MASK) + #define PDM_RANGE_STAT_RANGEUNF1_MASK (0x20000U) #define PDM_RANGE_STAT_RANGEUNF1_SHIFT (17U) /*! RANGEUNF1 - Channel 1 Range Underflow Error Flag - * 0b0..No exception by range underflow. - * 0b1..Exception by range underflow. + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow */ #define PDM_RANGE_STAT_RANGEUNF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF1_SHIFT)) & PDM_RANGE_STAT_RANGEUNF1_MASK) + #define PDM_RANGE_STAT_RANGEUNF2_MASK (0x40000U) #define PDM_RANGE_STAT_RANGEUNF2_SHIFT (18U) /*! RANGEUNF2 - Channel 2 Range Underflow Error Flag - * 0b0..No exception by range underflow. - * 0b1..Exception by range underflow. + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow */ #define PDM_RANGE_STAT_RANGEUNF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF2_SHIFT)) & PDM_RANGE_STAT_RANGEUNF2_MASK) + #define PDM_RANGE_STAT_RANGEUNF3_MASK (0x80000U) #define PDM_RANGE_STAT_RANGEUNF3_SHIFT (19U) /*! RANGEUNF3 - Channel 3 Range Underflow Error Flag - * 0b0..No exception by range underflow. - * 0b1..Exception by range underflow. + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow */ #define PDM_RANGE_STAT_RANGEUNF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF3_SHIFT)) & PDM_RANGE_STAT_RANGEUNF3_MASK) + #define PDM_RANGE_STAT_RANGEUNF4_MASK (0x100000U) #define PDM_RANGE_STAT_RANGEUNF4_SHIFT (20U) /*! RANGEUNF4 - Channel 4 Range Underflow Error Flag - * 0b0..No exception by range underflow. - * 0b1..Exception by range underflow. + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow */ #define PDM_RANGE_STAT_RANGEUNF4(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF4_SHIFT)) & PDM_RANGE_STAT_RANGEUNF4_MASK) + #define PDM_RANGE_STAT_RANGEUNF5_MASK (0x200000U) #define PDM_RANGE_STAT_RANGEUNF5_SHIFT (21U) /*! RANGEUNF5 - Channel 5 Range Underflow Error Flag - * 0b0..No exception by range underflow. - * 0b1..Exception by range underflow. + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow */ #define PDM_RANGE_STAT_RANGEUNF5(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF5_SHIFT)) & PDM_RANGE_STAT_RANGEUNF5_MASK) + #define PDM_RANGE_STAT_RANGEUNF6_MASK (0x400000U) #define PDM_RANGE_STAT_RANGEUNF6_SHIFT (22U) /*! RANGEUNF6 - Channel 6 Range Underflow Error Flag - * 0b0..No exception by range underflow. - * 0b1..Exception by range underflow. + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow */ #define PDM_RANGE_STAT_RANGEUNF6(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF6_SHIFT)) & PDM_RANGE_STAT_RANGEUNF6_MASK) + #define PDM_RANGE_STAT_RANGEUNF7_MASK (0x800000U) #define PDM_RANGE_STAT_RANGEUNF7_SHIFT (23U) /*! RANGEUNF7 - Channel 7 Range Underflow Error Flag - * 0b0..No exception by range underflow. - * 0b1..Exception by range underflow. + * 0b0..No exception by range underflow + * 0b1..Exception by range underflow */ #define PDM_RANGE_STAT_RANGEUNF7(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF7_SHIFT)) & PDM_RANGE_STAT_RANGEUNF7_MASK) /*! @} */ /*! @name VAD0_CTRL_1 - Voice Activity Detector 0 Control register */ /*! @{ */ + #define PDM_VAD0_CTRL_1_VADEN_MASK (0x1U) #define PDM_VAD0_CTRL_1_VADEN_SHIFT (0U) /*! VADEN - Voice Activity Detector Enable - * 0b0..The HWVAD is disabled. - * 0b1..The HWVAD is enabled. + * 0b0..The HWVAD is disabled + * 0b1..The HWVAD is enabled */ #define PDM_VAD0_CTRL_1_VADEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADEN_SHIFT)) & PDM_VAD0_CTRL_1_VADEN_MASK) + #define PDM_VAD0_CTRL_1_VADRST_MASK (0x2U) #define PDM_VAD0_CTRL_1_VADRST_SHIFT (1U) /*! VADRST - Voice Activity Detector Reset */ #define PDM_VAD0_CTRL_1_VADRST(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADRST_SHIFT)) & PDM_VAD0_CTRL_1_VADRST_MASK) + #define PDM_VAD0_CTRL_1_VADIE_MASK (0x4U) #define PDM_VAD0_CTRL_1_VADIE_SHIFT (2U) /*! VADIE - Voice Activity Detector Interruption Enable @@ -66489,6 +76042,7 @@ typedef struct { * 0b1..HWVAD Interrupts enabled */ #define PDM_VAD0_CTRL_1_VADIE(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADIE_SHIFT)) & PDM_VAD0_CTRL_1_VADIE_MASK) + #define PDM_VAD0_CTRL_1_VADERIE_MASK (0x8U) #define PDM_VAD0_CTRL_1_VADERIE_SHIFT (3U) /*! VADERIE - Voice Activity Detector Error Interruption Enable @@ -66496,6 +76050,7 @@ typedef struct { * 0b1..HWVAD Error Interrupts enabled */ #define PDM_VAD0_CTRL_1_VADERIE(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADERIE_SHIFT)) & PDM_VAD0_CTRL_1_VADERIE_MASK) + #define PDM_VAD0_CTRL_1_VADST10_MASK (0x10U) #define PDM_VAD0_CTRL_1_VADST10_SHIFT (4U) /*! VADST10 - Voice Activity Detector Internal Filters Initialization @@ -66503,16 +76058,19 @@ typedef struct { * 0b1..Filters are initialized. */ #define PDM_VAD0_CTRL_1_VADST10(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADST10_SHIFT)) & PDM_VAD0_CTRL_1_VADST10_MASK) + #define PDM_VAD0_CTRL_1_VADINITT_MASK (0x1F00U) #define PDM_VAD0_CTRL_1_VADINITT_SHIFT (8U) /*! VADINITT - Voice Activity Detector Initialization Time */ #define PDM_VAD0_CTRL_1_VADINITT(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADINITT_SHIFT)) & PDM_VAD0_CTRL_1_VADINITT_MASK) + #define PDM_VAD0_CTRL_1_VADCICOSR_MASK (0xF0000U) #define PDM_VAD0_CTRL_1_VADCICOSR_SHIFT (16U) /*! VADCICOSR - Voice Activity Detector CIC Oversampling Rate */ #define PDM_VAD0_CTRL_1_VADCICOSR(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCICOSR_SHIFT)) & PDM_VAD0_CTRL_1_VADCICOSR_MASK) + #define PDM_VAD0_CTRL_1_VADCHSEL_MASK (0x7000000U) #define PDM_VAD0_CTRL_1_VADCHSEL_SHIFT (24U) /*! VADCHSEL - Voice Activity Detector Channel Selector @@ -66522,6 +76080,7 @@ typedef struct { /*! @name VAD0_CTRL_2 - Voice Activity Detector 0 Control register */ /*! @{ */ + #define PDM_VAD0_CTRL_2_VADHPF_MASK (0x3U) #define PDM_VAD0_CTRL_2_VADHPF_SHIFT (0U) /*! VADHPF - Voice Activity Detector High-Pass Filter @@ -66531,16 +76090,19 @@ typedef struct { * 0b11..Cut-off frequency at 102Hz. */ #define PDM_VAD0_CTRL_2_VADHPF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADHPF_SHIFT)) & PDM_VAD0_CTRL_2_VADHPF_MASK) + #define PDM_VAD0_CTRL_2_VADINPGAIN_MASK (0xF00U) #define PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT (8U) /*! VADINPGAIN - Voice Activity Detector Input Gain */ #define PDM_VAD0_CTRL_2_VADINPGAIN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT)) & PDM_VAD0_CTRL_2_VADINPGAIN_MASK) + #define PDM_VAD0_CTRL_2_VADFRAMET_MASK (0x3F0000U) #define PDM_VAD0_CTRL_2_VADFRAMET_SHIFT (16U) /*! VADFRAMET - Voice Activity Detector Frame Time */ #define PDM_VAD0_CTRL_2_VADFRAMET(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRAMET_SHIFT)) & PDM_VAD0_CTRL_2_VADFRAMET_MASK) + #define PDM_VAD0_CTRL_2_VADFOUTDIS_MASK (0x10000000U) #define PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT (28U) /*! VADFOUTDIS - Voice Activity Detector Force Output Disable @@ -66548,6 +76110,7 @@ typedef struct { * 0b1..Output is disabled. */ #define PDM_VAD0_CTRL_2_VADFOUTDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFOUTDIS_MASK) + #define PDM_VAD0_CTRL_2_VADPREFEN_MASK (0x40000000U) #define PDM_VAD0_CTRL_2_VADPREFEN_SHIFT (30U) /*! VADPREFEN - Voice Activity Detector Pre Filter Enable @@ -66555,6 +76118,7 @@ typedef struct { * 0b1..Pre-filter is enabled. */ #define PDM_VAD0_CTRL_2_VADPREFEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADPREFEN_SHIFT)) & PDM_VAD0_CTRL_2_VADPREFEN_MASK) + #define PDM_VAD0_CTRL_2_VADFRENDIS_MASK (0x80000000U) #define PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT (31U) /*! VADFRENDIS - Voice Activity Detector Frame Energy Disable @@ -66566,27 +76130,31 @@ typedef struct { /*! @name VAD0_STAT - Voice Activity Detector 0 Status register */ /*! @{ */ + #define PDM_VAD0_STAT_VADIF_MASK (0x1U) #define PDM_VAD0_STAT_VADIF_SHIFT (0U) /*! VADIF - Voice Activity Detector Interrupt Flag - * 0b0..Voice activity has not been detected by the HWVAD. - * 0b1..Voice activity has been detected by the HWVAD. + * 0b0..Voice activity not detected + * 0b1..Voice activity detected */ #define PDM_VAD0_STAT_VADIF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADIF_SHIFT)) & PDM_VAD0_STAT_VADIF_MASK) + #define PDM_VAD0_STAT_VADEF_MASK (0x8000U) #define PDM_VAD0_STAT_VADEF_SHIFT (15U) /*! VADEF - Voice Activity Detector Event Flag - * 0b0..Voice activity has not been detected by the HWVAD. - * 0b1..Voice activity has been detected by the HWVAD. + * 0b0..Voice activity not detected + * 0b1..Voice activity detected */ #define PDM_VAD0_STAT_VADEF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADEF_SHIFT)) & PDM_VAD0_STAT_VADEF_MASK) + #define PDM_VAD0_STAT_VADINSATF_MASK (0x10000U) #define PDM_VAD0_STAT_VADINSATF_SHIFT (16U) /*! VADINSATF - Voice Activity Detector Input Saturation Flag - * 0b0..No exception by HWVAD input saturation. - * 0b1..Exception by HWVAD input saturation. + * 0b0..No exception + * 0b1..Exception */ #define PDM_VAD0_STAT_VADINSATF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINSATF_SHIFT)) & PDM_VAD0_STAT_VADINSATF_MASK) + #define PDM_VAD0_STAT_VADINITF_MASK (0x80000000U) #define PDM_VAD0_STAT_VADINITF_SHIFT (31U) /*! VADINITF - Voice Activity Detector Initialization Flag @@ -66598,11 +76166,13 @@ typedef struct { /*! @name VAD0_SCONFIG - Voice Activity Detector 0 Signal Configuration */ /*! @{ */ + #define PDM_VAD0_SCONFIG_VADSGAIN_MASK (0xFU) #define PDM_VAD0_SCONFIG_VADSGAIN_SHIFT (0U) /*! VADSGAIN - Voice Activity Detector Signal Gain */ #define PDM_VAD0_SCONFIG_VADSGAIN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSGAIN_SHIFT)) & PDM_VAD0_SCONFIG_VADSGAIN_MASK) + #define PDM_VAD0_SCONFIG_VADSMAXEN_MASK (0x40000000U) #define PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT (30U) /*! VADSMAXEN - Voice Activity Detector Signal Maximum Enable @@ -66610,6 +76180,7 @@ typedef struct { * 0b1..Maximum block is enabled. */ #define PDM_VAD0_SCONFIG_VADSMAXEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSMAXEN_MASK) + #define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U) #define PDM_VAD0_SCONFIG_VADSFILEN_SHIFT (31U) /*! VADSFILEN - Voice Activity Detector Signal Filter Enable @@ -66621,16 +76192,19 @@ typedef struct { /*! @name VAD0_NCONFIG - Voice Activity Detector 0 Noise Configuration */ /*! @{ */ + #define PDM_VAD0_NCONFIG_VADNGAIN_MASK (0xFU) #define PDM_VAD0_NCONFIG_VADNGAIN_SHIFT (0U) /*! VADNGAIN - Voice Activity Detector Noise Gain */ #define PDM_VAD0_NCONFIG_VADNGAIN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNGAIN_SHIFT)) & PDM_VAD0_NCONFIG_VADNGAIN_MASK) + #define PDM_VAD0_NCONFIG_VADNFILADJ_MASK (0x1F00U) #define PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT (8U) /*! VADNFILADJ - Voice Activity Detector Noise Filter Adjustment */ #define PDM_VAD0_NCONFIG_VADNFILADJ(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILADJ_MASK) + #define PDM_VAD0_NCONFIG_VADNOREN_MASK (0x10000000U) #define PDM_VAD0_NCONFIG_VADNOREN_SHIFT (28U) /*! VADNOREN - Voice Activity Detector Noise OR Enable @@ -66638,6 +76212,7 @@ typedef struct { * 0b1..Noise input is decimated. */ #define PDM_VAD0_NCONFIG_VADNOREN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNOREN_SHIFT)) & PDM_VAD0_NCONFIG_VADNOREN_MASK) + #define PDM_VAD0_NCONFIG_VADNDECEN_MASK (0x20000000U) #define PDM_VAD0_NCONFIG_VADNDECEN_SHIFT (29U) /*! VADNDECEN - Voice Activity Detector Noise Decimation Enable @@ -66645,6 +76220,7 @@ typedef struct { * 0b1..Noise input is decimated. */ #define PDM_VAD0_NCONFIG_VADNDECEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNDECEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNDECEN_MASK) + #define PDM_VAD0_NCONFIG_VADNMINEN_MASK (0x40000000U) #define PDM_VAD0_NCONFIG_VADNMINEN_SHIFT (30U) /*! VADNMINEN - Voice Activity Detector Noise Minimum Enable @@ -66652,6 +76228,7 @@ typedef struct { * 0b1..Minimum block is enabled. */ #define PDM_VAD0_NCONFIG_VADNMINEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNMINEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNMINEN_MASK) + #define PDM_VAD0_NCONFIG_VADNFILAUTO_MASK (0x80000000U) #define PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT (31U) /*! VADNFILAUTO - Voice Activity Detector Noise Filter Auto @@ -66663,6 +76240,7 @@ typedef struct { /*! @name VAD0_NDATA - Voice Activity Detector 0 Noise Data */ /*! @{ */ + #define PDM_VAD0_NDATA_VADNDATA_MASK (0xFFFFU) #define PDM_VAD0_NDATA_VADNDATA_SHIFT (0U) /*! VADNDATA - Voice Activity Detector Noise Data @@ -66672,20 +76250,23 @@ typedef struct { /*! @name VAD0_ZCD - Voice Activity Detector 0 Zero-Crossing Detector */ /*! @{ */ + #define PDM_VAD0_ZCD_VADZCDEN_MASK (0x1U) #define PDM_VAD0_ZCD_VADZCDEN_SHIFT (0U) /*! VADZCDEN - Zero-Crossing Detector Enable - * 0b0..The ZCD is disabled. - * 0b1..The ZCD is enabled. + * 0b0..The ZCD is disabled + * 0b1..The ZCD is enabled */ #define PDM_VAD0_ZCD_VADZCDEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDEN_SHIFT)) & PDM_VAD0_ZCD_VADZCDEN_MASK) + #define PDM_VAD0_ZCD_VADZCDAUTO_MASK (0x4U) #define PDM_VAD0_ZCD_VADZCDAUTO_SHIFT (2U) /*! VADZCDAUTO - Zero-Crossing Detector Automatic Threshold - * 0b0..The ZCD threshold is not estimated automatically, - * 0b1..The ZCD threshold is estimated automatically. + * 0b0..The ZCD threshold is not estimated automatically + * 0b1..The ZCD threshold is estimated automatically */ #define PDM_VAD0_ZCD_VADZCDAUTO(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAUTO_SHIFT)) & PDM_VAD0_ZCD_VADZCDAUTO_MASK) + #define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U) #define PDM_VAD0_ZCD_VADZCDAND_SHIFT (4U) /*! VADZCDAND - Zero-Crossing Detector AND Behavior @@ -66693,11 +76274,13 @@ typedef struct { * 0b1..The ZCD result is AND'ed with the energy-based detection. */ #define PDM_VAD0_ZCD_VADZCDAND(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK) + #define PDM_VAD0_ZCD_VADZCDADJ_MASK (0xF00U) #define PDM_VAD0_ZCD_VADZCDADJ_SHIFT (8U) /*! VADZCDADJ - Zero-Crossing Detector Adjustment */ #define PDM_VAD0_ZCD_VADZCDADJ(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDADJ_SHIFT)) & PDM_VAD0_ZCD_VADZCDADJ_MASK) + #define PDM_VAD0_ZCD_VADZCDTH_MASK (0x3FF0000U) #define PDM_VAD0_ZCD_VADZCDTH_SHIFT (16U) /*! VADZCDTH - Zero-Crossing Detector Threshold @@ -66739,28 +76322,14 @@ typedef struct { typedef struct { uint8_t RESERVED_0[4]; __IO uint32_t BPC_AUTHEN_CTRL; /**< BPC Authentication Control, offset: 0x4 */ - uint8_t RESERVED_1[4]; - uint32_t BPC_MISC; /**< BPC Miscellaneous, offset: 0xC */ + uint8_t RESERVED_1[8]; __IO uint32_t BPC_MODE; /**< BPC Mode, offset: 0x10 */ __IO uint32_t BPC_POWER_CTRL; /**< BPC power control, offset: 0x14 */ - __IO uint32_t BPC_PDN_CTRL; /**< BPC power down control, offset: 0x18 */ - __IO uint32_t BPC_PUP_CTRL; /**< BPC power up control, offset: 0x1C */ - __I uint32_t BPC_POWER_STAT; /**< BPC power status, offset: 0x20 */ - __IO uint32_t BPC_PSW_ACK_CTRL; /**< BPC PSW acknowledge control, offset: 0x24 */ - __I uint32_t BPC_PSW_ACK_STAT; /**< BPC PSW acknowledge status, offset: 0x28 */ + uint8_t RESERVED_2[20]; __IO uint32_t BPC_FLAG; /**< BPC flag, offset: 0x2C */ - uint8_t RESERVED_2[16]; + uint8_t RESERVED_3[16]; __IO uint32_t BPC_SSAR_SAVE_CTRL; /**< BPC SSAR save control, offset: 0x40 */ __IO uint32_t BPC_SSAR_RESTORE_CTRL; /**< BPC SSAR restore control, offset: 0x44 */ - __I uint32_t BPC_SSAR_STAT; /**< BPC SSAR status, offset: 0x48 */ - __IO uint32_t BPC_SSAR_ACK_CTRL; /**< BPC SSAR acknowledge control, offset: 0x4C */ - __I uint32_t BPC_SSAR_ACK_STAT; /**< BPC SSAR acknowledge status, offset: 0x50 */ - __IO uint32_t BPC_MEM_CM_CTRL; /**< BPC memory CPU mode control, offset: 0x54 */ - __IO uint32_t BPC_MEM_SP_CTRL_0; /**< BPC memory set point control 0, offset: 0x58 */ - __IO uint32_t BPC_MEM_SP_CTRL_1; /**< BPC memory set point control 1, offset: 0x5C */ - __I uint32_t BPC_MEM_STAT; /**< BPC memory status, offset: 0x60 */ - uint8_t RESERVED_3[28]; - __I uint32_t BPC_FSM_STAT; /**< BPC FSM status, offset: 0x80 */ } PGMC_BPC_Type; /* ---------------------------------------------------------------------------- @@ -66774,31 +76343,41 @@ typedef struct { /*! @name BPC_AUTHEN_CTRL - BPC Authentication Control */ /*! @{ */ + #define PGMC_BPC_BPC_AUTHEN_CTRL_USER_MASK (0x1U) #define PGMC_BPC_BPC_AUTHEN_CTRL_USER_SHIFT (0U) /*! USER - Allow user mode access + * 0b0..Allow only privilege mode to access basic power control registers + * 0b1..Allow both privilege and user mode to access basic power control registers */ #define PGMC_BPC_BPC_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_USER_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_USER_MASK) + #define PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_MASK (0x2U) #define PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_SHIFT (1U) /*! NONSECURE - Allow non-secure mode access + * 0b0..Allow only secure mode to access basic power control registers + * 0b1..Allow both secure and non-secure mode to access basic power control registers */ #define PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_MASK) + #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U) #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U) /*! LOCK_SETTING - Lock NONSECURE and USER */ #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_MASK) + #define PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U) #define PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U) /*! WHITE_LIST - Domain ID white list */ #define PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_MASK) + #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_MASK (0x1000U) #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U) /*! LOCK_LIST - White list lock */ #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_MASK) + #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U) #define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U) /*! LOCK_CFG - Configuration lock @@ -66808,228 +76387,83 @@ typedef struct { /*! @name BPC_MODE - BPC Mode */ /*! @{ */ + #define PGMC_BPC_BPC_MODE_CTRL_MODE_MASK (0x3U) #define PGMC_BPC_BPC_MODE_CTRL_MODE_SHIFT (0U) -/*! CTRL_MODE - Control mode, locked by LOCK_CFG field +/*! CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. * 0b00..Not affected by any low power mode * 0b01..Controlled by CPU power mode of the domain - * 0b10..Controlled by set point + * 0b10..Controlled by Setpoint * 0b11..Reserved */ #define PGMC_BPC_BPC_MODE_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MODE_CTRL_MODE_SHIFT)) & PGMC_BPC_BPC_MODE_CTRL_MODE_MASK) + #define PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_MASK (0x30U) #define PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_SHIFT (4U) /*! DOMAIN_ASSIGN - Domain assignment of the BPC + * 0b00..Domain 0 + * 0b01..Domain 1 + * 0b10..Domain 2 + * 0b11..Domain 3 */ #define PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_SHIFT)) & PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_MASK) /*! @} */ /*! @name BPC_POWER_CTRL - BPC power control */ /*! @{ */ + #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_MASK (0x2U) #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT (1U) -/*! PWR_OFF_AT_WAIT - Power off when domain enters WAIT mode +/*! PWR_OFF_AT_WAIT - 0x1: Power off when domain enters WAIT mode */ #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_MASK) + #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_MASK (0x4U) #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT (2U) -/*! PWR_OFF_AT_STOP - Power off when domain enters STOP mode +/*! PWR_OFF_AT_STOP - 0x1: Power off when domain enters STOP mode */ #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_MASK) + #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK (0x8U) #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT (3U) -/*! PWR_OFF_AT_SUSPEND - Power off when domain enters SUSPEND mode +/*! PWR_OFF_AT_SUSPEND - 0x1: Power off when domain enters SUSPEND mode */ #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK) + #define PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_MASK (0x100U) #define PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_SHIFT (8U) /*! ISO_ON_SOFT - Software isolation on trigger */ #define PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_MASK) + #define PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_MASK (0x200U) #define PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_SHIFT (9U) /*! PSW_OFF_SOFT - Software power off trigger */ #define PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_MASK) + #define PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK (0x400U) #define PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_SHIFT (10U) /*! PSW_ON_SOFT - Software power on trigger */ #define PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK) + #define PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_MASK (0x800U) #define PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_SHIFT (11U) /*! ISO_OFF_SOFT - Software isolation off trigger */ #define PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_MASK) + #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_MASK (0xFFFF0000U) #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_SHIFT (16U) -/*! PWR_OFF_AT_SP - Power off when system enters set point number +/*! PWR_OFF_AT_SP - Power off when system enters Setpoint number */ #define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_MASK) /*! @} */ -/*! @name BPC_PDN_CTRL - BPC power down control */ -/*! @{ */ -#define PGMC_BPC_BPC_PDN_CTRL_DLY_PRE_PSW_LF_OFF_MASK (0x3FFU) -#define PGMC_BPC_BPC_PDN_CTRL_DLY_PRE_PSW_LF_OFF_SHIFT (0U) -/*! DLY_PRE_PSW_LF_OFF - Delay from receiving power off request to low fanout power switch shut off, locked by LOCK_CFG field - */ -#define PGMC_BPC_BPC_PDN_CTRL_DLY_PRE_PSW_LF_OFF(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_PDN_CTRL_DLY_PRE_PSW_LF_OFF_SHIFT)) & PGMC_BPC_BPC_PDN_CTRL_DLY_PRE_PSW_LF_OFF_MASK) -#define PGMC_BPC_BPC_PDN_CTRL_DLY_PRE_PSW_HF_OFF_MASK (0xFFC00U) -#define PGMC_BPC_BPC_PDN_CTRL_DLY_PRE_PSW_HF_OFF_SHIFT (10U) -/*! DLY_PRE_PSW_HF_OFF - Delay from receiving power off request to high fanout power switch shut off, locked by LOCK_CFG field - */ -#define PGMC_BPC_BPC_PDN_CTRL_DLY_PRE_PSW_HF_OFF(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_PDN_CTRL_DLY_PRE_PSW_HF_OFF_SHIFT)) & PGMC_BPC_BPC_PDN_CTRL_DLY_PRE_PSW_HF_OFF_MASK) -#define PGMC_BPC_BPC_PDN_CTRL_DLY_PRE_ISO_ON_MASK (0x3FF00000U) -#define PGMC_BPC_BPC_PDN_CTRL_DLY_PRE_ISO_ON_SHIFT (20U) -/*! DLY_PRE_ISO_ON - Delay from receiving iso_on request to isolation enable, locked by LOCK_CFG field - */ -#define PGMC_BPC_BPC_PDN_CTRL_DLY_PRE_ISO_ON(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_PDN_CTRL_DLY_PRE_ISO_ON_SHIFT)) & PGMC_BPC_BPC_PDN_CTRL_DLY_PRE_ISO_ON_MASK) -/*! @} */ - -/*! @name BPC_PUP_CTRL - BPC power up control */ -/*! @{ */ -#define PGMC_BPC_BPC_PUP_CTRL_DLY_PRE_PSW_LF_ON_MASK (0x3FFU) -#define PGMC_BPC_BPC_PUP_CTRL_DLY_PRE_PSW_LF_ON_SHIFT (0U) -/*! DLY_PRE_PSW_LF_ON - Delay from receiving power on request to low fanout power switch truns on, locked by LOCK_CFG field - */ -#define PGMC_BPC_BPC_PUP_CTRL_DLY_PRE_PSW_LF_ON(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_PUP_CTRL_DLY_PRE_PSW_LF_ON_SHIFT)) & PGMC_BPC_BPC_PUP_CTRL_DLY_PRE_PSW_LF_ON_MASK) -#define PGMC_BPC_BPC_PUP_CTRL_DLY_PRE_PSW_HF_ON_MASK (0xFFC00U) -#define PGMC_BPC_BPC_PUP_CTRL_DLY_PRE_PSW_HF_ON_SHIFT (10U) -/*! DLY_PRE_PSW_HF_ON - Delay from receiving power on request to high fanout power switch truns on, locked by LOCK_CFG field - */ -#define PGMC_BPC_BPC_PUP_CTRL_DLY_PRE_PSW_HF_ON(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_PUP_CTRL_DLY_PRE_PSW_HF_ON_SHIFT)) & PGMC_BPC_BPC_PUP_CTRL_DLY_PRE_PSW_HF_ON_MASK) -#define PGMC_BPC_BPC_PUP_CTRL_DLY_PRE_ISO_OFF_MASK (0x3FF00000U) -#define PGMC_BPC_BPC_PUP_CTRL_DLY_PRE_ISO_OFF_SHIFT (20U) -/*! DLY_PRE_ISO_OFF - Delay from receiving iso off request to isolation disable, locked by LOCK_CFG field - */ -#define PGMC_BPC_BPC_PUP_CTRL_DLY_PRE_ISO_OFF(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_PUP_CTRL_DLY_PRE_ISO_OFF_SHIFT)) & PGMC_BPC_BPC_PUP_CTRL_DLY_PRE_ISO_OFF_MASK) -/*! @} */ - -/*! @name BPC_POWER_STAT - BPC power status */ -/*! @{ */ -#define PGMC_BPC_BPC_POWER_STAT_CM_ISO_REQUEST_MASK (0xFU) -#define PGMC_BPC_BPC_POWER_STAT_CM_ISO_REQUEST_SHIFT (0U) -/*! CM_ISO_REQUEST - CPU mode trans iso request of 4 domains - */ -#define PGMC_BPC_BPC_POWER_STAT_CM_ISO_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_STAT_CM_ISO_REQUEST_SHIFT)) & PGMC_BPC_BPC_POWER_STAT_CM_ISO_REQUEST_MASK) -#define PGMC_BPC_BPC_POWER_STAT_CM_PWR_REQUEST_MASK (0xF0U) -#define PGMC_BPC_BPC_POWER_STAT_CM_PWR_REQUEST_SHIFT (4U) -/*! CM_PWR_REQUEST - CPU mode trans power request of 4 domains - */ -#define PGMC_BPC_BPC_POWER_STAT_CM_PWR_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_STAT_CM_PWR_REQUEST_SHIFT)) & PGMC_BPC_BPC_POWER_STAT_CM_PWR_REQUEST_MASK) -#define PGMC_BPC_BPC_POWER_STAT_SP_ISO_ON_REQUEST_MASK (0x100U) -#define PGMC_BPC_BPC_POWER_STAT_SP_ISO_ON_REQUEST_SHIFT (8U) -/*! SP_ISO_ON_REQUEST - Set point trans iso on request - */ -#define PGMC_BPC_BPC_POWER_STAT_SP_ISO_ON_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_STAT_SP_ISO_ON_REQUEST_SHIFT)) & PGMC_BPC_BPC_POWER_STAT_SP_ISO_ON_REQUEST_MASK) -#define PGMC_BPC_BPC_POWER_STAT_SP_PWR_OFF_REQUEST_MASK (0x200U) -#define PGMC_BPC_BPC_POWER_STAT_SP_PWR_OFF_REQUEST_SHIFT (9U) -/*! SP_PWR_OFF_REQUEST - Set point trans power off request - */ -#define PGMC_BPC_BPC_POWER_STAT_SP_PWR_OFF_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_STAT_SP_PWR_OFF_REQUEST_SHIFT)) & PGMC_BPC_BPC_POWER_STAT_SP_PWR_OFF_REQUEST_MASK) -#define PGMC_BPC_BPC_POWER_STAT_SP_PWR_ON_REQUEST_MASK (0x400U) -#define PGMC_BPC_BPC_POWER_STAT_SP_PWR_ON_REQUEST_SHIFT (10U) -/*! SP_PWR_ON_REQUEST - Set point trans power on request - */ -#define PGMC_BPC_BPC_POWER_STAT_SP_PWR_ON_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_STAT_SP_PWR_ON_REQUEST_SHIFT)) & PGMC_BPC_BPC_POWER_STAT_SP_PWR_ON_REQUEST_MASK) -#define PGMC_BPC_BPC_POWER_STAT_SP_ISO_OFF_REQUEST_MASK (0x800U) -#define PGMC_BPC_BPC_POWER_STAT_SP_ISO_OFF_REQUEST_SHIFT (11U) -/*! SP_ISO_OFF_REQUEST - Set point trans iso off request - */ -#define PGMC_BPC_BPC_POWER_STAT_SP_ISO_OFF_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_STAT_SP_ISO_OFF_REQUEST_SHIFT)) & PGMC_BPC_BPC_POWER_STAT_SP_ISO_OFF_REQUEST_MASK) -#define PGMC_BPC_BPC_POWER_STAT_CPU_POWER_MODE_MASK (0x30000U) -#define PGMC_BPC_BPC_POWER_STAT_CPU_POWER_MODE_SHIFT (16U) -/*! CPU_POWER_MODE - CPU power mode of assigned domain - */ -#define PGMC_BPC_BPC_POWER_STAT_CPU_POWER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_STAT_CPU_POWER_MODE_SHIFT)) & PGMC_BPC_BPC_POWER_STAT_CPU_POWER_MODE_MASK) -#define PGMC_BPC_BPC_POWER_STAT_SET_POINT_MASK (0xF000000U) -#define PGMC_BPC_BPC_POWER_STAT_SET_POINT_SHIFT (24U) -/*! SET_POINT - CPU power mode of assigned domain - */ -#define PGMC_BPC_BPC_POWER_STAT_SET_POINT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_STAT_SET_POINT_SHIFT)) & PGMC_BPC_BPC_POWER_STAT_SET_POINT_MASK) -#define PGMC_BPC_BPC_POWER_STAT_POWER_STABLE_MASK (0x10000000U) -#define PGMC_BPC_BPC_POWER_STAT_POWER_STABLE_SHIFT (28U) -/*! POWER_STABLE - Power supply stable - */ -#define PGMC_BPC_BPC_POWER_STAT_POWER_STABLE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_STAT_POWER_STABLE_SHIFT)) & PGMC_BPC_BPC_POWER_STAT_POWER_STABLE_MASK) -#define PGMC_BPC_BPC_POWER_STAT_ISO_STAT_MASK (0x20000000U) -#define PGMC_BPC_BPC_POWER_STAT_ISO_STAT_SHIFT (29U) -/*! ISO_STAT - Isolation status - */ -#define PGMC_BPC_BPC_POWER_STAT_ISO_STAT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_STAT_ISO_STAT_SHIFT)) & PGMC_BPC_BPC_POWER_STAT_ISO_STAT_MASK) -#define PGMC_BPC_BPC_POWER_STAT_PSW_LF_STAT_MASK (0x40000000U) -#define PGMC_BPC_BPC_POWER_STAT_PSW_LF_STAT_SHIFT (30U) -/*! PSW_LF_STAT - Low fanout power switch status - */ -#define PGMC_BPC_BPC_POWER_STAT_PSW_LF_STAT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_STAT_PSW_LF_STAT_SHIFT)) & PGMC_BPC_BPC_POWER_STAT_PSW_LF_STAT_MASK) -#define PGMC_BPC_BPC_POWER_STAT_PSW_HF_STAT_MASK (0x80000000U) -#define PGMC_BPC_BPC_POWER_STAT_PSW_HF_STAT_SHIFT (31U) -/*! PSW_HF_STAT - High fanout power switch status - */ -#define PGMC_BPC_BPC_POWER_STAT_PSW_HF_STAT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_STAT_PSW_HF_STAT_SHIFT)) & PGMC_BPC_BPC_POWER_STAT_PSW_HF_STAT_MASK) -/*! @} */ - -/*! @name BPC_PSW_ACK_CTRL - BPC PSW acknowledge control */ -/*! @{ */ -#define PGMC_BPC_BPC_PSW_ACK_CTRL_LF_CNT_CFG_MASK (0xFFU) -#define PGMC_BPC_BPC_PSW_ACK_CTRL_LF_CNT_CFG_SHIFT (0U) -/*! LF_CNT_CFG - Low fanout count configure, useage is depending on CNT_MODE, locked by LOCK_CFG field - */ -#define PGMC_BPC_BPC_PSW_ACK_CTRL_LF_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_PSW_ACK_CTRL_LF_CNT_CFG_SHIFT)) & PGMC_BPC_BPC_PSW_ACK_CTRL_LF_CNT_CFG_MASK) -#define PGMC_BPC_BPC_PSW_ACK_CTRL_HF_CNT_CFG_MASK (0xFF000U) -#define PGMC_BPC_BPC_PSW_ACK_CTRL_HF_CNT_CFG_SHIFT (12U) -/*! HF_CNT_CFG - High fanout count configure, useage is depending on CNT_MODE, locked by LOCK_CFG field - */ -#define PGMC_BPC_BPC_PSW_ACK_CTRL_HF_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_PSW_ACK_CTRL_HF_CNT_CFG_SHIFT)) & PGMC_BPC_BPC_PSW_ACK_CTRL_HF_CNT_CFG_MASK) -#define PGMC_BPC_BPC_PSW_ACK_CTRL_CNT_MODE_MASK (0x30000000U) -#define PGMC_BPC_BPC_PSW_ACK_CTRL_CNT_MODE_SHIFT (28U) -/*! CNT_MODE - Count mode - * 0b00..Raise power_on/off done response once power switches change - * 0b01..Raise power_on/off done response once getting power switche acknowledge - * 0b10..Ignore power switches acknowledge, the delay counter starts to count once switches change - * 0b11..Time out mode, the counter starts to count once switches change, then raise power_on/off done response - * when either acknowledge received or counting to LF/HF_CNT_CFG value - */ -#define PGMC_BPC_BPC_PSW_ACK_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_PSW_ACK_CTRL_CNT_MODE_SHIFT)) & PGMC_BPC_BPC_PSW_ACK_CTRL_CNT_MODE_MASK) -#define PGMC_BPC_BPC_PSW_ACK_CTRL_LF_ACK_INVERT_MASK (0x40000000U) -#define PGMC_BPC_BPC_PSW_ACK_CTRL_LF_ACK_INVERT_SHIFT (30U) -/*! LF_ACK_INVERT - Low fanout acknowledge value is inverted from power switch control, locked by LOCK_CFG field - */ -#define PGMC_BPC_BPC_PSW_ACK_CTRL_LF_ACK_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_PSW_ACK_CTRL_LF_ACK_INVERT_SHIFT)) & PGMC_BPC_BPC_PSW_ACK_CTRL_LF_ACK_INVERT_MASK) -#define PGMC_BPC_BPC_PSW_ACK_CTRL_HF_ACK_INVERT_MASK (0x80000000U) -#define PGMC_BPC_BPC_PSW_ACK_CTRL_HF_ACK_INVERT_SHIFT (31U) -/*! HF_ACK_INVERT - High fanout acknowledge value is inverted from power switch control, locked by LOCK_CFG field - */ -#define PGMC_BPC_BPC_PSW_ACK_CTRL_HF_ACK_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_PSW_ACK_CTRL_HF_ACK_INVERT_SHIFT)) & PGMC_BPC_BPC_PSW_ACK_CTRL_HF_ACK_INVERT_MASK) -/*! @} */ - -/*! @name BPC_PSW_ACK_STAT - BPC PSW acknowledge status */ -/*! @{ */ -#define PGMC_BPC_BPC_PSW_ACK_STAT_LF_ACK_CNT_MASK (0xFFU) -#define PGMC_BPC_BPC_PSW_ACK_STAT_LF_ACK_CNT_SHIFT (0U) -/*! LF_ACK_CNT - Low fanout acknowledge count, record the delay from power switch change to acknowledge received - */ -#define PGMC_BPC_BPC_PSW_ACK_STAT_LF_ACK_CNT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_PSW_ACK_STAT_LF_ACK_CNT_SHIFT)) & PGMC_BPC_BPC_PSW_ACK_STAT_LF_ACK_CNT_MASK) -#define PGMC_BPC_BPC_PSW_ACK_STAT_HF_ACK_CNT_MASK (0xFF000U) -#define PGMC_BPC_BPC_PSW_ACK_STAT_HF_ACK_CNT_SHIFT (12U) -/*! HF_ACK_CNT - High fanout acknowledge count, record the delay from power switch change to acknowledge received - */ -#define PGMC_BPC_BPC_PSW_ACK_STAT_HF_ACK_CNT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_PSW_ACK_STAT_HF_ACK_CNT_SHIFT)) & PGMC_BPC_BPC_PSW_ACK_STAT_HF_ACK_CNT_MASK) -#define PGMC_BPC_BPC_PSW_ACK_STAT_LF_ACK_STAT_MASK (0x1000000U) -#define PGMC_BPC_BPC_PSW_ACK_STAT_LF_ACK_STAT_SHIFT (24U) -/*! LF_ACK_STAT - Low fanout acknowledge status - */ -#define PGMC_BPC_BPC_PSW_ACK_STAT_LF_ACK_STAT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_PSW_ACK_STAT_LF_ACK_STAT_SHIFT)) & PGMC_BPC_BPC_PSW_ACK_STAT_LF_ACK_STAT_MASK) -#define PGMC_BPC_BPC_PSW_ACK_STAT_HF_ACK_STAT_MASK (0x2000000U) -#define PGMC_BPC_BPC_PSW_ACK_STAT_HF_ACK_STAT_SHIFT (25U) -/*! HF_ACK_STAT - High fanout acknowledge status - */ -#define PGMC_BPC_BPC_PSW_ACK_STAT_HF_ACK_STAT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_PSW_ACK_STAT_HF_ACK_STAT_SHIFT)) & PGMC_BPC_BPC_PSW_ACK_STAT_HF_ACK_STAT_MASK) -/*! @} */ - /*! @name BPC_FLAG - BPC flag */ /*! @{ */ + #define PGMC_BPC_BPC_FLAG_PDN_FLAG_MASK (0x1U) #define PGMC_BPC_BPC_FLAG_PDN_FLAG_SHIFT (0U) /*! PDN_FLAG - set to 1 after power switch off, cleared by writing 1 @@ -67039,259 +76473,54 @@ typedef struct { /*! @name BPC_SSAR_SAVE_CTRL - BPC SSAR save control */ /*! @{ */ + #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_MASK (0x1U) #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_SHIFT (0U) -/*! SAVE_AT_RUN - Save data at RUN mode, software SSAR save trigger +/*! SAVE_AT_RUN - Save data at RUN mode, software writting 0x1 to trigger SSARC to execute save process */ #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_MASK) + #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_MASK (0x2U) #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_SHIFT (1U) /*! SAVE_AT_WAIT - Save data when domain enters WAIT mode */ #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_MASK) + #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_MASK (0x4U) #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_SHIFT (2U) /*! SAVE_AT_STOP - Save data when domain enters STOP mode */ #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_MASK) + #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_MASK (0x8U) #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_SHIFT (3U) /*! SAVE_AT_SUSPEND - Save data when domain enters SUSPEND mode */ #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_MASK) + #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_MASK (0xFFFF0000U) #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_SHIFT (16U) -/*! SAVE_AT_SP - Save data when system enters a set point. +/*! SAVE_AT_SP - Save data when system enters a Setpoint. */ #define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_MASK) /*! @} */ /*! @name BPC_SSAR_RESTORE_CTRL - BPC SSAR restore control */ /*! @{ */ + #define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_MASK (0x1U) #define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_SHIFT (0U) -/*! RESTORE_AT_RUN - Restore data at RUN mode, software SSAR restore trigger +/*! RESTORE_AT_RUN - Restore data at RUN mode */ #define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_SHIFT)) & PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_MASK) + #define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_MASK (0xFFFF0000U) #define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_SHIFT (16U) -/*! RESTORE_AT_SP - Restore data when system enters a set point. +/*! RESTORE_AT_SP - Restore data when system enters a Setpoint. */ #define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_SHIFT)) & PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_MASK) /*! @} */ -/*! @name BPC_SSAR_STAT - BPC SSAR status */ -/*! @{ */ -#define PGMC_BPC_BPC_SSAR_STAT_SAVED_MASK (0x1U) -#define PGMC_BPC_BPC_SSAR_STAT_SAVED_SHIFT (0U) -/*! SAVED - Indicate data in this power domain is already saved but not restored yet - */ -#define PGMC_BPC_BPC_SSAR_STAT_SAVED(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_STAT_SAVED_SHIFT)) & PGMC_BPC_BPC_SSAR_STAT_SAVED_MASK) -#define PGMC_BPC_BPC_SSAR_STAT_BUSY_SAVE_MASK (0x10U) -#define PGMC_BPC_BPC_SSAR_STAT_BUSY_SAVE_SHIFT (4U) -/*! BUSY_SAVE - Busy requesting SSAR save - */ -#define PGMC_BPC_BPC_SSAR_STAT_BUSY_SAVE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_STAT_BUSY_SAVE_SHIFT)) & PGMC_BPC_BPC_SSAR_STAT_BUSY_SAVE_MASK) -#define PGMC_BPC_BPC_SSAR_STAT_BUSY_RESTORE_MASK (0x20U) -#define PGMC_BPC_BPC_SSAR_STAT_BUSY_RESTORE_SHIFT (5U) -/*! BUSY_RESTORE - Busy requesting SSAR restore - */ -#define PGMC_BPC_BPC_SSAR_STAT_BUSY_RESTORE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_STAT_BUSY_RESTORE_SHIFT)) & PGMC_BPC_BPC_SSAR_STAT_BUSY_RESTORE_MASK) -/*! @} */ - -/*! @name BPC_SSAR_ACK_CTRL - BPC SSAR acknowledge control */ -/*! @{ */ -#define PGMC_BPC_BPC_SSAR_ACK_CTRL_SAVE_CNT_CFG_MASK (0x3FFFU) -#define PGMC_BPC_BPC_SSAR_ACK_CTRL_SAVE_CNT_CFG_SHIFT (0U) -/*! SAVE_CNT_CFG - Save count configure, useage is depending on CNT_MODE, locked by LOCK_CFG field - */ -#define PGMC_BPC_BPC_SSAR_ACK_CTRL_SAVE_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_ACK_CTRL_SAVE_CNT_CFG_SHIFT)) & PGMC_BPC_BPC_SSAR_ACK_CTRL_SAVE_CNT_CFG_MASK) -#define PGMC_BPC_BPC_SSAR_ACK_CTRL_RESTORE_CNT_CFG_MASK (0xFFFC000U) -#define PGMC_BPC_BPC_SSAR_ACK_CTRL_RESTORE_CNT_CFG_SHIFT (14U) -/*! RESTORE_CNT_CFG - Restore count configure, useage is depending on CNT_MODE, locked by LOCK_CFG field - */ -#define PGMC_BPC_BPC_SSAR_ACK_CTRL_RESTORE_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_ACK_CTRL_RESTORE_CNT_CFG_SHIFT)) & PGMC_BPC_BPC_SSAR_ACK_CTRL_RESTORE_CNT_CFG_MASK) -#define PGMC_BPC_BPC_SSAR_ACK_CTRL_CNT_MODE_MASK (0x30000000U) -#define PGMC_BPC_BPC_SSAR_ACK_CTRL_CNT_MODE_SHIFT (28U) -/*! CNT_MODE - Count mode - * 0b00..Counter disable mode: not use counter, raise ssar_save/restore done response to GPC once received acknowledge from SSAR - * 0b01..Counter delay mode: delay after response received from SSAR, delay cycle number is SAVE/RESTORE_CNT_CFG - * 0b10..Ignore SSAR response, the delay counter starts to count once requests start - * 0b11..Time out mode, the counter starts to count once requests start, then raise ssar_done response to GPC - * when either acknowledge received or counting to SAVE/RESTORE_CNT_CFG value - */ -#define PGMC_BPC_BPC_SSAR_ACK_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_ACK_CTRL_CNT_MODE_SHIFT)) & PGMC_BPC_BPC_SSAR_ACK_CTRL_CNT_MODE_MASK) -/*! @} */ - -/*! @name BPC_SSAR_ACK_STAT - BPC SSAR acknowledge status */ -/*! @{ */ -#define PGMC_BPC_BPC_SSAR_ACK_STAT_SAVE_ACK_CNT_MASK (0xFFFFU) -#define PGMC_BPC_BPC_SSAR_ACK_STAT_SAVE_ACK_CNT_SHIFT (0U) -/*! SAVE_ACK_CNT - Save acknowledge count, record the delay from SSAR save request to response received - */ -#define PGMC_BPC_BPC_SSAR_ACK_STAT_SAVE_ACK_CNT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_ACK_STAT_SAVE_ACK_CNT_SHIFT)) & PGMC_BPC_BPC_SSAR_ACK_STAT_SAVE_ACK_CNT_MASK) -#define PGMC_BPC_BPC_SSAR_ACK_STAT_RESTORE_ACK_CNT_MASK (0xFFFF0000U) -#define PGMC_BPC_BPC_SSAR_ACK_STAT_RESTORE_ACK_CNT_SHIFT (16U) -/*! RESTORE_ACK_CNT - Restore acknowledge count, record the delay from SSAR restore request to response received - */ -#define PGMC_BPC_BPC_SSAR_ACK_STAT_RESTORE_ACK_CNT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_ACK_STAT_RESTORE_ACK_CNT_SHIFT)) & PGMC_BPC_BPC_SSAR_ACK_STAT_RESTORE_ACK_CNT_MASK) -/*! @} */ - -/*! @name BPC_MEM_CM_CTRL - BPC memory CPU mode control */ -/*! @{ */ -#define PGMC_BPC_BPC_MEM_CM_CTRL_MLPL_AT_RUN_MASK (0xFU) -#define PGMC_BPC_BPC_MEM_CM_CTRL_MLPL_AT_RUN_SHIFT (0U) -/*! MLPL_AT_RUN - Memory low power level at RUN mode - */ -#define PGMC_BPC_BPC_MEM_CM_CTRL_MLPL_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MEM_CM_CTRL_MLPL_AT_RUN_SHIFT)) & PGMC_BPC_BPC_MEM_CM_CTRL_MLPL_AT_RUN_MASK) -#define PGMC_BPC_BPC_MEM_CM_CTRL_MLPL_AT_WAIT_MASK (0xF0U) -#define PGMC_BPC_BPC_MEM_CM_CTRL_MLPL_AT_WAIT_SHIFT (4U) -/*! MLPL_AT_WAIT - Memory low power level at WAIT mode, locked by LOCK_CFG field - */ -#define PGMC_BPC_BPC_MEM_CM_CTRL_MLPL_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MEM_CM_CTRL_MLPL_AT_WAIT_SHIFT)) & PGMC_BPC_BPC_MEM_CM_CTRL_MLPL_AT_WAIT_MASK) -#define PGMC_BPC_BPC_MEM_CM_CTRL_MLPL_AT_STOP_MASK (0xF00U) -#define PGMC_BPC_BPC_MEM_CM_CTRL_MLPL_AT_STOP_SHIFT (8U) -/*! MLPL_AT_STOP - Memory low power level at STOP mode, locked by LOCK_CFG field - */ -#define PGMC_BPC_BPC_MEM_CM_CTRL_MLPL_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MEM_CM_CTRL_MLPL_AT_STOP_SHIFT)) & PGMC_BPC_BPC_MEM_CM_CTRL_MLPL_AT_STOP_MASK) -#define PGMC_BPC_BPC_MEM_CM_CTRL_MLPL_AT_SUSPEND_MASK (0xF000U) -#define PGMC_BPC_BPC_MEM_CM_CTRL_MLPL_AT_SUSPEND_SHIFT (12U) -/*! MLPL_AT_SUSPEND - Memory low power level at STOP mode, locked by LOCK_CFG field - */ -#define PGMC_BPC_BPC_MEM_CM_CTRL_MLPL_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MEM_CM_CTRL_MLPL_AT_SUSPEND_SHIFT)) & PGMC_BPC_BPC_MEM_CM_CTRL_MLPL_AT_SUSPEND_MASK) -#define PGMC_BPC_BPC_MEM_CM_CTRL_MLPL_SOFT_MASK (0x10000U) -#define PGMC_BPC_BPC_MEM_CM_CTRL_MLPL_SOFT_SHIFT (16U) -/*! MLPL_SOFT - Memory low power level software change request, keep 1 until MLPL transition complete - */ -#define PGMC_BPC_BPC_MEM_CM_CTRL_MLPL_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MEM_CM_CTRL_MLPL_SOFT_SHIFT)) & PGMC_BPC_BPC_MEM_CM_CTRL_MLPL_SOFT_MASK) -/*! @} */ - -/*! @name BPC_MEM_SP_CTRL_0 - BPC memory set point control 0 */ -/*! @{ */ -#define PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP0_MASK (0xFU) -#define PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP0_SHIFT (0U) -/*! MLPL_AT_SP0 - Memory low power level at set point 0, locked by LOCK_CFG field - */ -#define PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP0(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP0_SHIFT)) & PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP0_MASK) -#define PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP1_MASK (0xF0U) -#define PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP1_SHIFT (4U) -/*! MLPL_AT_SP1 - Memory low power level at set point 1, locked by LOCK_CFG field - */ -#define PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP1(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP1_SHIFT)) & PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP1_MASK) -#define PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP2_MASK (0xF00U) -#define PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP2_SHIFT (8U) -/*! MLPL_AT_SP2 - Memory low power level at set point 2, locked by LOCK_CFG field - */ -#define PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP2(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP2_SHIFT)) & PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP2_MASK) -#define PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP3_MASK (0xF000U) -#define PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP3_SHIFT (12U) -/*! MLPL_AT_SP3 - Memory low power level at set point 3, locked by LOCK_CFG field - */ -#define PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP3(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP3_SHIFT)) & PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP3_MASK) -#define PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP4_MASK (0xF0000U) -#define PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP4_SHIFT (16U) -/*! MLPL_AT_SP4 - Memory low power level at set point 4 - */ -#define PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP4(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP4_SHIFT)) & PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP4_MASK) -#define PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP5_MASK (0xF00000U) -#define PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP5_SHIFT (20U) -/*! MLPL_AT_SP5 - Memory low power level at set point 5, locked by LOCK_CFG field - */ -#define PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP5(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP5_SHIFT)) & PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP5_MASK) -#define PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP6_MASK (0xF000000U) -#define PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP6_SHIFT (24U) -/*! MLPL_AT_SP6 - Memory low power level at set point 6 - */ -#define PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP6(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP6_SHIFT)) & PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP6_MASK) -#define PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP7_MASK (0xF0000000U) -#define PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP7_SHIFT (28U) -/*! MLPL_AT_SP7 - Memory low power level at set point 7, locked by LOCK_CFG field - */ -#define PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP7(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP7_SHIFT)) & PGMC_BPC_BPC_MEM_SP_CTRL_0_MLPL_AT_SP7_MASK) -/*! @} */ - -/*! @name BPC_MEM_SP_CTRL_1 - BPC memory set point control 1 */ -/*! @{ */ -#define PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP8_MASK (0xFU) -#define PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP8_SHIFT (0U) -/*! MLPL_AT_SP8 - Memory low power level at set point 8, locked by LOCK_CFG field - */ -#define PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP8(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP8_SHIFT)) & PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP8_MASK) -#define PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP9_MASK (0xF0U) -#define PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP9_SHIFT (4U) -/*! MLPL_AT_SP9 - Memory low power level at set point 9, locked by LOCK_CFG field - */ -#define PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP9(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP9_SHIFT)) & PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP9_MASK) -#define PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP10_MASK (0xF00U) -#define PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP10_SHIFT (8U) -/*! MLPL_AT_SP10 - Memory low power level at set point 10, locked by LOCK_CFG field - */ -#define PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP10(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP10_SHIFT)) & PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP10_MASK) -#define PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP11_MASK (0xF000U) -#define PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP11_SHIFT (12U) -/*! MLPL_AT_SP11 - Memory low power level at set point 11, locked by LOCK_CFG field - */ -#define PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP11(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP11_SHIFT)) & PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP11_MASK) -#define PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP12_MASK (0xF0000U) -#define PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP12_SHIFT (16U) -/*! MLPL_AT_SP12 - Memory low power level at set point 12, locked by LOCK_CFG field - */ -#define PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP12(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP12_SHIFT)) & PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP12_MASK) -#define PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP13_MASK (0xF00000U) -#define PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP13_SHIFT (20U) -/*! MLPL_AT_SP13 - Memory low power level at set point 13, locked by LOCK_CFG field - */ -#define PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP13(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP13_SHIFT)) & PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP13_MASK) -#define PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP14_MASK (0xF000000U) -#define PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP14_SHIFT (24U) -/*! MLPL_AT_SP14 - Memory low power level at set point 14, locked by LOCK_CFG field - */ -#define PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP14(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP14_SHIFT)) & PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP14_MASK) -#define PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP15_MASK (0xF0000000U) -#define PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP15_SHIFT (28U) -/*! MLPL_AT_SP15 - Memory low power level at set point 15, locked by LOCK_CFG field - */ -#define PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP15(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP15_SHIFT)) & PGMC_BPC_BPC_MEM_SP_CTRL_1_MLPL_AT_SP15_MASK) -/*! @} */ - -/*! @name BPC_MEM_STAT - BPC memory status */ -/*! @{ */ -#define PGMC_BPC_BPC_MEM_STAT_CURRENT_MLPL_MASK (0xFU) -#define PGMC_BPC_BPC_MEM_STAT_CURRENT_MLPL_SHIFT (0U) -/*! CURRENT_MLPL - Current low power level - */ -#define PGMC_BPC_BPC_MEM_STAT_CURRENT_MLPL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MEM_STAT_CURRENT_MLPL_SHIFT)) & PGMC_BPC_BPC_MEM_STAT_CURRENT_MLPL_MASK) -#define PGMC_BPC_BPC_MEM_STAT_BUSY_MASK (0x10U) -#define PGMC_BPC_BPC_MEM_STAT_BUSY_SHIFT (4U) -/*! BUSY - Busy requesting low power level - */ -#define PGMC_BPC_BPC_MEM_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MEM_STAT_BUSY_SHIFT)) & PGMC_BPC_BPC_MEM_STAT_BUSY_MASK) -/*! @} */ - -/*! @name BPC_FSM_STAT - BPC FSM status */ -/*! @{ */ -#define PGMC_BPC_BPC_FSM_STAT_ISO_STAT_MASK (0x7U) -#define PGMC_BPC_BPC_FSM_STAT_ISO_STAT_SHIFT (0U) -/*! ISO_STAT - isolation FSM status - */ -#define PGMC_BPC_BPC_FSM_STAT_ISO_STAT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_FSM_STAT_ISO_STAT_SHIFT)) & PGMC_BPC_BPC_FSM_STAT_ISO_STAT_MASK) -#define PGMC_BPC_BPC_FSM_STAT_PSW_STAT_MASK (0xF0U) -#define PGMC_BPC_BPC_FSM_STAT_PSW_STAT_SHIFT (4U) -/*! PSW_STAT - power switch FSM status - */ -#define PGMC_BPC_BPC_FSM_STAT_PSW_STAT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_FSM_STAT_PSW_STAT_SHIFT)) & PGMC_BPC_BPC_FSM_STAT_PSW_STAT_MASK) -#define PGMC_BPC_BPC_FSM_STAT_SAR_STAT_MASK (0x700U) -#define PGMC_BPC_BPC_FSM_STAT_SAR_STAT_SHIFT (8U) -/*! SAR_STAT - SSAR FSM status - */ -#define PGMC_BPC_BPC_FSM_STAT_SAR_STAT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_FSM_STAT_SAR_STAT_SHIFT)) & PGMC_BPC_BPC_FSM_STAT_SAR_STAT_MASK) -#define PGMC_BPC_BPC_FSM_STAT_MEM_STAT_MASK (0x7000U) -#define PGMC_BPC_BPC_FSM_STAT_MEM_STAT_SHIFT (12U) -/*! MEM_STAT - memory FSM status - */ -#define PGMC_BPC_BPC_FSM_STAT_MEM_STAT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_FSM_STAT_MEM_STAT_SHIFT)) & PGMC_BPC_BPC_FSM_STAT_MEM_STAT_MASK) -/*! @} */ - /*! * @} @@ -67354,29 +76583,21 @@ typedef struct { typedef struct { uint8_t RESERVED_0[4]; __IO uint32_t CPC_AUTHEN_CTRL; /**< CPC Authentication Control, offset: 0x4 */ - uint8_t RESERVED_1[4]; - uint32_t CPC_MISC; /**< CPC Miscellaneous, offset: 0xC */ + uint8_t RESERVED_1[8]; __IO uint32_t CPC_CORE_MODE; /**< CPC Core Mode, offset: 0x10 */ __IO uint32_t CPC_CORE_POWER_CTRL; /**< CPC core power control, offset: 0x14 */ - __IO uint32_t CPC_CORE_PDN_CTRL; /**< CPC core power down control, offset: 0x18 */ - __IO uint32_t CPC_CORE_PUP_CTRL; /**< CPC core power up control, offset: 0x1C */ - __I uint32_t CPC_CORE_POWER_STAT; /**< CPC core power status, offset: 0x20 */ - __IO uint32_t CPC_CORE_PSW_ACK_CTRL; /**< CPC core power switch acknowledge control, offset: 0x24 */ - __I uint32_t CPC_CORE_PSW_ACK_STAT; /**< CPC core power switch acknowledge status, offset: 0x28 */ + uint8_t RESERVED_2[20]; __IO uint32_t CPC_FLAG; /**< CPC flag, offset: 0x2C */ - uint8_t RESERVED_2[16]; + uint8_t RESERVED_3[16]; __IO uint32_t CPC_CACHE_MODE; /**< CPC Cache Mode, offset: 0x40 */ __IO uint32_t CPC_CACHE_CM_CTRL; /**< CPC cache CPU mode control, offset: 0x44 */ - __IO uint32_t CPC_CACHE_SP_CTRL_0; /**< CPC cache set point control 0, offset: 0x48 */ - __IO uint32_t CPC_CACHE_SP_CTRL_1; /**< CPC cache set point control 1, offset: 0x4C */ - uint8_t RESERVED_3[4]; - __I uint32_t CPC_CACHE_STAT; /**< CPC cache status, offset: 0x54 */ - uint8_t RESERVED_4[104]; + __IO uint32_t CPC_CACHE_SP_CTRL_0; /**< CPC cache Setpoint control 0, offset: 0x48 */ + __IO uint32_t CPC_CACHE_SP_CTRL_1; /**< CPC cache Setpoint control 1, offset: 0x4C */ + uint8_t RESERVED_4[112]; __IO uint32_t CPC_LMEM_MODE; /**< CPC local memory Mode, offset: 0xC0 */ __IO uint32_t CPC_LMEM_CM_CTRL; /**< CPC local memory CPU mode control, offset: 0xC4 */ - __IO uint32_t CPC_LMEM_SP_CTRL_0; /**< CPC local memory set point control 0, offset: 0xC8 */ - __IO uint32_t CPC_LMEM_SP_CTRL_1; /**< CPC local memory set point control 1, offset: 0xCC */ - __I uint32_t CPC_LMEM_STAT; /**< CPC local memory status, offset: 0xD0 */ + __IO uint32_t CPC_LMEM_SP_CTRL_0; /**< CPC local memory Setpoint control 0, offset: 0xC8 */ + __IO uint32_t CPC_LMEM_SP_CTRL_1; /**< CPC local memory Setpoint control 1, offset: 0xCC */ } PGMC_CPC_Type; /* ---------------------------------------------------------------------------- @@ -67390,31 +76611,37 @@ typedef struct { /*! @name CPC_AUTHEN_CTRL - CPC Authentication Control */ /*! @{ */ + #define PGMC_CPC_CPC_AUTHEN_CTRL_USER_MASK (0x1U) #define PGMC_CPC_CPC_AUTHEN_CTRL_USER_SHIFT (0U) /*! USER - Allow user mode access */ #define PGMC_CPC_CPC_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_USER_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_USER_MASK) + #define PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_MASK (0x2U) #define PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_SHIFT (1U) /*! NONSECURE - Allow non-secure mode access */ #define PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_MASK) + #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U) #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U) /*! LOCK_SETTING - Lock NONSECURE and USER */ #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_MASK) + #define PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U) #define PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U) /*! WHITE_LIST - Domain ID white list */ #define PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_MASK) + #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_MASK (0x1000U) #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U) /*! LOCK_LIST - White list lock */ #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_MASK) + #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U) #define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U) /*! LOCK_CFG - Configuration lock @@ -67424,9 +76651,10 @@ typedef struct { /*! @name CPC_CORE_MODE - CPC Core Mode */ /*! @{ */ + #define PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_MASK (0x3U) #define PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_SHIFT (0U) -/*! CTRL_MODE - Control mode, locked by LOCK_CFG field +/*! CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. * 0b00..Not affected by any low power mode * 0b01..Controlled by CPU power mode of the domain * 0b10..Reserved @@ -67437,36 +76665,43 @@ typedef struct { /*! @name CPC_CORE_POWER_CTRL - CPC core power control */ /*! @{ */ + #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_MASK (0x2U) #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT (1U) /*! PWR_OFF_AT_WAIT - Power off when domain enters WAIT mode */ #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_MASK) + #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_MASK (0x4U) #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT (2U) /*! PWR_OFF_AT_STOP - Power off when domain enters STOP mode */ #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_MASK) + #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK (0x8U) #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT (3U) /*! PWR_OFF_AT_SUSPEND - Power off when domain enters SUSPEND mode */ #define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK) + #define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_MASK (0x100U) #define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_SHIFT (8U) /*! ISO_ON_SOFT - Software isolation on trigger */ #define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_MASK) + #define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_MASK (0x200U) #define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_SHIFT (9U) /*! PSW_OFF_SOFT - Software power off trigger */ #define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_MASK) + #define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_MASK (0x400U) #define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_SHIFT (10U) /*! PSW_ON_SOFT - Software power on trigger */ #define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_MASK) + #define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_MASK (0x800U) #define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_SHIFT (11U) /*! ISO_OFF_SOFT - Software isolation off trigger @@ -67474,153 +76709,9 @@ typedef struct { #define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_MASK) /*! @} */ -/*! @name CPC_CORE_PDN_CTRL - CPC core power down control */ -/*! @{ */ -#define PGMC_CPC_CPC_CORE_PDN_CTRL_DLY_PRE_PSW_LF_OFF_MASK (0x3FFU) -#define PGMC_CPC_CPC_CORE_PDN_CTRL_DLY_PRE_PSW_LF_OFF_SHIFT (0U) -/*! DLY_PRE_PSW_LF_OFF - Delay from receiving power off request to low fanout power switch shut off, locked by LOCK_CFG field - */ -#define PGMC_CPC_CPC_CORE_PDN_CTRL_DLY_PRE_PSW_LF_OFF(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_PDN_CTRL_DLY_PRE_PSW_LF_OFF_SHIFT)) & PGMC_CPC_CPC_CORE_PDN_CTRL_DLY_PRE_PSW_LF_OFF_MASK) -#define PGMC_CPC_CPC_CORE_PDN_CTRL_DLY_PRE_PSW_HF_OFF_MASK (0xFFC00U) -#define PGMC_CPC_CPC_CORE_PDN_CTRL_DLY_PRE_PSW_HF_OFF_SHIFT (10U) -/*! DLY_PRE_PSW_HF_OFF - Delay from receiving power off request to high fanout power switch shut off, locked by LOCK_CFG field - */ -#define PGMC_CPC_CPC_CORE_PDN_CTRL_DLY_PRE_PSW_HF_OFF(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_PDN_CTRL_DLY_PRE_PSW_HF_OFF_SHIFT)) & PGMC_CPC_CPC_CORE_PDN_CTRL_DLY_PRE_PSW_HF_OFF_MASK) -#define PGMC_CPC_CPC_CORE_PDN_CTRL_DLY_PRE_ISO_ON_MASK (0x3FF00000U) -#define PGMC_CPC_CPC_CORE_PDN_CTRL_DLY_PRE_ISO_ON_SHIFT (20U) -/*! DLY_PRE_ISO_ON - Delay from receiving iso_on request to isolation enable, locked by LOCK_CFG field - */ -#define PGMC_CPC_CPC_CORE_PDN_CTRL_DLY_PRE_ISO_ON(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_PDN_CTRL_DLY_PRE_ISO_ON_SHIFT)) & PGMC_CPC_CPC_CORE_PDN_CTRL_DLY_PRE_ISO_ON_MASK) -/*! @} */ - -/*! @name CPC_CORE_PUP_CTRL - CPC core power up control */ -/*! @{ */ -#define PGMC_CPC_CPC_CORE_PUP_CTRL_DLY_PRE_PSW_LF_ON_MASK (0x3FFU) -#define PGMC_CPC_CPC_CORE_PUP_CTRL_DLY_PRE_PSW_LF_ON_SHIFT (0U) -/*! DLY_PRE_PSW_LF_ON - Delay from receiving power on request to low fanout power switch truns on, locked by LOCK_CFG field - */ -#define PGMC_CPC_CPC_CORE_PUP_CTRL_DLY_PRE_PSW_LF_ON(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_PUP_CTRL_DLY_PRE_PSW_LF_ON_SHIFT)) & PGMC_CPC_CPC_CORE_PUP_CTRL_DLY_PRE_PSW_LF_ON_MASK) -#define PGMC_CPC_CPC_CORE_PUP_CTRL_DLY_PRE_PSW_HF_ON_MASK (0xFFC00U) -#define PGMC_CPC_CPC_CORE_PUP_CTRL_DLY_PRE_PSW_HF_ON_SHIFT (10U) -/*! DLY_PRE_PSW_HF_ON - Delay from receiving power on request to high fanout power switch truns on, locked by LOCK_CFG field - */ -#define PGMC_CPC_CPC_CORE_PUP_CTRL_DLY_PRE_PSW_HF_ON(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_PUP_CTRL_DLY_PRE_PSW_HF_ON_SHIFT)) & PGMC_CPC_CPC_CORE_PUP_CTRL_DLY_PRE_PSW_HF_ON_MASK) -#define PGMC_CPC_CPC_CORE_PUP_CTRL_DLY_PRE_ISO_OFF_MASK (0x3FF00000U) -#define PGMC_CPC_CPC_CORE_PUP_CTRL_DLY_PRE_ISO_OFF_SHIFT (20U) -/*! DLY_PRE_ISO_OFF - Delay from receiving iso off request to isolation disable, locked by LOCK_CFG field - */ -#define PGMC_CPC_CPC_CORE_PUP_CTRL_DLY_PRE_ISO_OFF(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_PUP_CTRL_DLY_PRE_ISO_OFF_SHIFT)) & PGMC_CPC_CPC_CORE_PUP_CTRL_DLY_PRE_ISO_OFF_MASK) -/*! @} */ - -/*! @name CPC_CORE_POWER_STAT - CPC core power status */ -/*! @{ */ -#define PGMC_CPC_CPC_CORE_POWER_STAT_CM_ISO_REQUEST_MASK (0xFU) -#define PGMC_CPC_CPC_CORE_POWER_STAT_CM_ISO_REQUEST_SHIFT (0U) -/*! CM_ISO_REQUEST - CPU mode trans iso request of 4 domains - */ -#define PGMC_CPC_CPC_CORE_POWER_STAT_CM_ISO_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_STAT_CM_ISO_REQUEST_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_STAT_CM_ISO_REQUEST_MASK) -#define PGMC_CPC_CPC_CORE_POWER_STAT_CM_PWR_REQUEST_MASK (0xF0U) -#define PGMC_CPC_CPC_CORE_POWER_STAT_CM_PWR_REQUEST_SHIFT (4U) -/*! CM_PWR_REQUEST - CPU mode trans power request of 4 domains - */ -#define PGMC_CPC_CPC_CORE_POWER_STAT_CM_PWR_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_STAT_CM_PWR_REQUEST_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_STAT_CM_PWR_REQUEST_MASK) -#define PGMC_CPC_CPC_CORE_POWER_STAT_CPU_POWER_MODE_MASK (0x30000U) -#define PGMC_CPC_CPC_CORE_POWER_STAT_CPU_POWER_MODE_SHIFT (16U) -/*! CPU_POWER_MODE - CPU power mode of assigned domain - */ -#define PGMC_CPC_CPC_CORE_POWER_STAT_CPU_POWER_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_STAT_CPU_POWER_MODE_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_STAT_CPU_POWER_MODE_MASK) -#define PGMC_CPC_CPC_CORE_POWER_STAT_ISO_FSM_STAT_MASK (0x700000U) -#define PGMC_CPC_CPC_CORE_POWER_STAT_ISO_FSM_STAT_SHIFT (20U) -/*! ISO_FSM_STAT - isolation FSM state - */ -#define PGMC_CPC_CPC_CORE_POWER_STAT_ISO_FSM_STAT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_STAT_ISO_FSM_STAT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_STAT_ISO_FSM_STAT_MASK) -#define PGMC_CPC_CPC_CORE_POWER_STAT_PSW_FSM_STAT_MASK (0xF000000U) -#define PGMC_CPC_CPC_CORE_POWER_STAT_PSW_FSM_STAT_SHIFT (24U) -/*! PSW_FSM_STAT - power switch FSM state - */ -#define PGMC_CPC_CPC_CORE_POWER_STAT_PSW_FSM_STAT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_STAT_PSW_FSM_STAT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_STAT_PSW_FSM_STAT_MASK) -#define PGMC_CPC_CPC_CORE_POWER_STAT_POWER_STABLE_MASK (0x10000000U) -#define PGMC_CPC_CPC_CORE_POWER_STAT_POWER_STABLE_SHIFT (28U) -/*! POWER_STABLE - Power supply stable - */ -#define PGMC_CPC_CPC_CORE_POWER_STAT_POWER_STABLE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_STAT_POWER_STABLE_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_STAT_POWER_STABLE_MASK) -#define PGMC_CPC_CPC_CORE_POWER_STAT_ISO_STAT_MASK (0x20000000U) -#define PGMC_CPC_CPC_CORE_POWER_STAT_ISO_STAT_SHIFT (29U) -/*! ISO_STAT - Isolation status - */ -#define PGMC_CPC_CPC_CORE_POWER_STAT_ISO_STAT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_STAT_ISO_STAT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_STAT_ISO_STAT_MASK) -#define PGMC_CPC_CPC_CORE_POWER_STAT_PSW_LF_STAT_MASK (0x40000000U) -#define PGMC_CPC_CPC_CORE_POWER_STAT_PSW_LF_STAT_SHIFT (30U) -/*! PSW_LF_STAT - Low fanout power switch status - */ -#define PGMC_CPC_CPC_CORE_POWER_STAT_PSW_LF_STAT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_STAT_PSW_LF_STAT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_STAT_PSW_LF_STAT_MASK) -#define PGMC_CPC_CPC_CORE_POWER_STAT_PSW_HF_STAT_MASK (0x80000000U) -#define PGMC_CPC_CPC_CORE_POWER_STAT_PSW_HF_STAT_SHIFT (31U) -/*! PSW_HF_STAT - High fanout power switch status - */ -#define PGMC_CPC_CPC_CORE_POWER_STAT_PSW_HF_STAT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_STAT_PSW_HF_STAT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_STAT_PSW_HF_STAT_MASK) -/*! @} */ - -/*! @name CPC_CORE_PSW_ACK_CTRL - CPC core power switch acknowledge control */ -/*! @{ */ -#define PGMC_CPC_CPC_CORE_PSW_ACK_CTRL_LF_CNT_CFG_MASK (0xFFU) -#define PGMC_CPC_CPC_CORE_PSW_ACK_CTRL_LF_CNT_CFG_SHIFT (0U) -/*! LF_CNT_CFG - Low fanout count configure, useage is depending on CNT_MODE, locked by LOCK_CFG field - */ -#define PGMC_CPC_CPC_CORE_PSW_ACK_CTRL_LF_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_PSW_ACK_CTRL_LF_CNT_CFG_SHIFT)) & PGMC_CPC_CPC_CORE_PSW_ACK_CTRL_LF_CNT_CFG_MASK) -#define PGMC_CPC_CPC_CORE_PSW_ACK_CTRL_HF_CNT_CFG_MASK (0xFF000U) -#define PGMC_CPC_CPC_CORE_PSW_ACK_CTRL_HF_CNT_CFG_SHIFT (12U) -/*! HF_CNT_CFG - High fanout count configure, useage is depending on CNT_MODE, locked by LOCK_CFG field - */ -#define PGMC_CPC_CPC_CORE_PSW_ACK_CTRL_HF_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_PSW_ACK_CTRL_HF_CNT_CFG_SHIFT)) & PGMC_CPC_CPC_CORE_PSW_ACK_CTRL_HF_CNT_CFG_MASK) -#define PGMC_CPC_CPC_CORE_PSW_ACK_CTRL_CNT_MODE_MASK (0x30000000U) -#define PGMC_CPC_CPC_CORE_PSW_ACK_CTRL_CNT_MODE_SHIFT (28U) -/*! CNT_MODE - Count mode - * 0b00..Raise power_on/off done response once power switches change - * 0b01..Raise power_on/off done response once getting power switche acknowledge - * 0b10..Ignore power switches acknowledge, the delay counter starts to count once switches change - * 0b11..Time out mode, the counter starts to count once switches change, then raise power_on/off done response - * when either acknowledge received or counting to LF/HF_CNT_CFG value - */ -#define PGMC_CPC_CPC_CORE_PSW_ACK_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_PSW_ACK_CTRL_CNT_MODE_SHIFT)) & PGMC_CPC_CPC_CORE_PSW_ACK_CTRL_CNT_MODE_MASK) -#define PGMC_CPC_CPC_CORE_PSW_ACK_CTRL_LF_ACK_INVERT_MASK (0x40000000U) -#define PGMC_CPC_CPC_CORE_PSW_ACK_CTRL_LF_ACK_INVERT_SHIFT (30U) -/*! LF_ACK_INVERT - Low fanout acknowledge value is inverted from power switch control, locked by LOCK_CFG field - */ -#define PGMC_CPC_CPC_CORE_PSW_ACK_CTRL_LF_ACK_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_PSW_ACK_CTRL_LF_ACK_INVERT_SHIFT)) & PGMC_CPC_CPC_CORE_PSW_ACK_CTRL_LF_ACK_INVERT_MASK) -#define PGMC_CPC_CPC_CORE_PSW_ACK_CTRL_HF_ACK_INVERT_MASK (0x80000000U) -#define PGMC_CPC_CPC_CORE_PSW_ACK_CTRL_HF_ACK_INVERT_SHIFT (31U) -/*! HF_ACK_INVERT - High fanout acknowledge value is inverted from power switch control, locked by LOCK_CFG field - */ -#define PGMC_CPC_CPC_CORE_PSW_ACK_CTRL_HF_ACK_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_PSW_ACK_CTRL_HF_ACK_INVERT_SHIFT)) & PGMC_CPC_CPC_CORE_PSW_ACK_CTRL_HF_ACK_INVERT_MASK) -/*! @} */ - -/*! @name CPC_CORE_PSW_ACK_STAT - CPC core power switch acknowledge status */ -/*! @{ */ -#define PGMC_CPC_CPC_CORE_PSW_ACK_STAT_LF_ACK_CNT_MASK (0xFFU) -#define PGMC_CPC_CPC_CORE_PSW_ACK_STAT_LF_ACK_CNT_SHIFT (0U) -/*! LF_ACK_CNT - Low fanout acknowledge count, record the delay from power switch change to acknowledge received - */ -#define PGMC_CPC_CPC_CORE_PSW_ACK_STAT_LF_ACK_CNT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_PSW_ACK_STAT_LF_ACK_CNT_SHIFT)) & PGMC_CPC_CPC_CORE_PSW_ACK_STAT_LF_ACK_CNT_MASK) -#define PGMC_CPC_CPC_CORE_PSW_ACK_STAT_HF_ACK_CNT_MASK (0xFF000U) -#define PGMC_CPC_CPC_CORE_PSW_ACK_STAT_HF_ACK_CNT_SHIFT (12U) -/*! HF_ACK_CNT - High fanout acknowledge count, record the delay from power switch change to acknowledge received - */ -#define PGMC_CPC_CPC_CORE_PSW_ACK_STAT_HF_ACK_CNT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_PSW_ACK_STAT_HF_ACK_CNT_SHIFT)) & PGMC_CPC_CPC_CORE_PSW_ACK_STAT_HF_ACK_CNT_MASK) -#define PGMC_CPC_CPC_CORE_PSW_ACK_STAT_LF_ACK_STAT_MASK (0x1000000U) -#define PGMC_CPC_CPC_CORE_PSW_ACK_STAT_LF_ACK_STAT_SHIFT (24U) -/*! LF_ACK_STAT - Low fanout acknowledge status - */ -#define PGMC_CPC_CPC_CORE_PSW_ACK_STAT_LF_ACK_STAT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_PSW_ACK_STAT_LF_ACK_STAT_SHIFT)) & PGMC_CPC_CPC_CORE_PSW_ACK_STAT_LF_ACK_STAT_MASK) -#define PGMC_CPC_CPC_CORE_PSW_ACK_STAT_HF_ACK_STAT_MASK (0x2000000U) -#define PGMC_CPC_CPC_CORE_PSW_ACK_STAT_HF_ACK_STAT_SHIFT (25U) -/*! HF_ACK_STAT - High fanout acknowledge status - */ -#define PGMC_CPC_CPC_CORE_PSW_ACK_STAT_HF_ACK_STAT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_PSW_ACK_STAT_HF_ACK_STAT_SHIFT)) & PGMC_CPC_CPC_CORE_PSW_ACK_STAT_HF_ACK_STAT_MASK) -/*! @} */ - /*! @name CPC_FLAG - CPC flag */ /*! @{ */ + #define PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_MASK (0x1U) #define PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_SHIFT (0U) /*! CORE_PDN_FLAG - set to 1 after core power switch off, cleared by writing 1 @@ -67630,12 +76721,13 @@ typedef struct { /*! @name CPC_CACHE_MODE - CPC Cache Mode */ /*! @{ */ + #define PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_MASK (0x3U) #define PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_SHIFT (0U) -/*! CTRL_MODE - Control mode, locked by LOCK_CFG field +/*! CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. * 0b00..Not affected by any low power mode * 0b01..Controlled by CPU power mode of the domain - * 0b10..Controlled by set point + * 0b10..Controlled by Setpoint * 0b11..Reserved */ #define PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_MASK) @@ -67643,148 +76735,151 @@ typedef struct { /*! @name CPC_CACHE_CM_CTRL - CPC cache CPU mode control */ /*! @{ */ + #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_MASK (0xFU) #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_SHIFT (0U) -/*! MLPL_AT_RUN - Memory low power level at RUN mode +/*! MLPL_AT_RUN - Memory Low Power Level (MLPL) at RUN mode */ #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_MASK) + #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_MASK (0xF0U) #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_SHIFT (4U) -/*! MLPL_AT_WAIT - Memory low power level at WAIT mode, locked by LOCK_CFG field +/*! MLPL_AT_WAIT - Memory Low Power Level (MLPL) at WAIT mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_MASK) + #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_MASK (0xF00U) #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_SHIFT (8U) -/*! MLPL_AT_STOP - Memory low power level at STOP mode, locked by LOCK_CFG field +/*! MLPL_AT_STOP - Memory Low Power Level (MLPL) at STOP mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_MASK) + #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_MASK (0xF000U) #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_SHIFT (12U) -/*! MLPL_AT_SUSPEND - Memory low power level at STOP mode, locked by LOCK_CFG field +/*! MLPL_AT_SUSPEND - Memory Low Power Level (MLPL) at SUSPEND mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_MASK) + #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_MASK (0x10000U) #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_SHIFT (16U) -/*! MLPL_SOFT - Memory low power level software change request, keep 1 until MLPL transition complete +/*! MLPL_SOFT - Memory Low Power Level (MLPL) software change request, keep 1 until MLPL transition complete */ #define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_MASK) /*! @} */ -/*! @name CPC_CACHE_SP_CTRL_0 - CPC cache set point control 0 */ +/*! @name CPC_CACHE_SP_CTRL_0 - CPC cache Setpoint control 0 */ /*! @{ */ + #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_MASK (0xFU) #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_SHIFT (0U) -/*! MLPL_AT_SP0 - Memory low power level at set point 0, locked by LOCK_CFG field +/*! MLPL_AT_SP0 - Memory Low Power Level (MLPL) at Setpoint 0. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_MASK) + #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_MASK (0xF0U) #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_SHIFT (4U) -/*! MLPL_AT_SP1 - Memory low power level at set point 1, locked by LOCK_CFG field +/*! MLPL_AT_SP1 - Memory Low Power Level (MLPL) at Setpoint 1. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_MASK) + #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_MASK (0xF00U) #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_SHIFT (8U) -/*! MLPL_AT_SP2 - Memory low power level at set point 2, locked by LOCK_CFG field +/*! MLPL_AT_SP2 - Memory Low Power Level (MLPL) at Setpoint 2. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_MASK) + #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_MASK (0xF000U) #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_SHIFT (12U) -/*! MLPL_AT_SP3 - Memory low power level at set point 3, locked by LOCK_CFG field +/*! MLPL_AT_SP3 - Memory Low Power Level (MLPL) at Setpoint 3. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_MASK) + #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_MASK (0xF0000U) #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_SHIFT (16U) -/*! MLPL_AT_SP4 - Memory low power level at set point 4, locked by LOCK_CFG field +/*! MLPL_AT_SP4 - Memory Low Power Level (MLPL) at Setpoint 4. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_MASK) + #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_MASK (0xF00000U) #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_SHIFT (20U) -/*! MLPL_AT_SP5 - Memory low power level at set point 5, locked by LOCK_CFG field +/*! MLPL_AT_SP5 - Memory Low Power Level (MLPL) at Setpoint 5. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_MASK) + #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_MASK (0xF000000U) #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_SHIFT (24U) -/*! MLPL_AT_SP6 - Memory low power level at set point 6, locked by LOCK_CFG field +/*! MLPL_AT_SP6 - Memory Low Power Level (MLPL) at Setpoint 6. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_MASK) + #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_MASK (0xF0000000U) #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_SHIFT (28U) -/*! MLPL_AT_SP7 - Memory low power level at set point 7, locked by LOCK_CFG field +/*! MLPL_AT_SP7 - Memory Low Power Level (MLPL) at Setpoint 7. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_MASK) /*! @} */ -/*! @name CPC_CACHE_SP_CTRL_1 - CPC cache set point control 1 */ +/*! @name CPC_CACHE_SP_CTRL_1 - CPC cache Setpoint control 1 */ /*! @{ */ + #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_MASK (0xFU) #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_SHIFT (0U) -/*! MLPL_AT_SP8 - Memory low power level at set point 8, locked by LOCK_CFG field +/*! MLPL_AT_SP8 - Memory Low Power Level (MLPL) at Setpoint 8. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_MASK) + #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_MASK (0xF0U) #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_SHIFT (4U) -/*! MLPL_AT_SP9 - Memory low power level at set point 9, locked by LOCK_CFG field +/*! MLPL_AT_SP9 - Memory Low Power Level (MLPL) at Setpoint 9. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_MASK) + #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_MASK (0xF00U) #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_SHIFT (8U) -/*! MLPL_AT_SP10 - Memory low power level at set point 10, locked by LOCK_CFG field +/*! MLPL_AT_SP10 - Memory Low Power Level (MLPL) at Setpoint 10. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_MASK) + #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_MASK (0xF000U) #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_SHIFT (12U) -/*! MLPL_AT_SP11 - Memory low power level at set point 11, locked by LOCK_CFG field +/*! MLPL_AT_SP11 - Memory Low Power Level (MLPL) at Setpoint 11. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_MASK) + #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_MASK (0xF0000U) #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_SHIFT (16U) -/*! MLPL_AT_SP12 - Memory low power level at set point 12, locked by LOCK_CFG field +/*! MLPL_AT_SP12 - Memory Low Power Level (MLPL) at Setpoint 12. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_MASK) + #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_MASK (0xF00000U) #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_SHIFT (20U) -/*! MLPL_AT_SP13 - Memory low power level at set point 13, locked by LOCK_CFG field +/*! MLPL_AT_SP13 - Memory Low Power Level (MLPL) at Setpoint 13. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_MASK) + #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_MASK (0xF000000U) #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_SHIFT (24U) -/*! MLPL_AT_SP14 - Memory low power level at set point 14, locked by LOCK_CFG field +/*! MLPL_AT_SP14 - Memory Low Power Level (MLPL) at Setpoint 14. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_MASK) + #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_MASK (0xF0000000U) #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_SHIFT (28U) -/*! MLPL_AT_SP15 - Memory low power level at set point 15, locked by LOCK_CFG field +/*! MLPL_AT_SP15 - Memory Low Power Level (MLPL) at Setpoint 15. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_MASK) /*! @} */ -/*! @name CPC_CACHE_STAT - CPC cache status */ -/*! @{ */ -#define PGMC_CPC_CPC_CACHE_STAT_CURRENT_MLPL_MASK (0xFU) -#define PGMC_CPC_CPC_CACHE_STAT_CURRENT_MLPL_SHIFT (0U) -/*! CURRENT_MLPL - Current memory low power level - */ -#define PGMC_CPC_CPC_CACHE_STAT_CURRENT_MLPL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_STAT_CURRENT_MLPL_SHIFT)) & PGMC_CPC_CPC_CACHE_STAT_CURRENT_MLPL_MASK) -#define PGMC_CPC_CPC_CACHE_STAT_BUSY_MASK (0x10U) -#define PGMC_CPC_CPC_CACHE_STAT_BUSY_SHIFT (4U) -/*! BUSY - Busy requesting low power level - */ -#define PGMC_CPC_CPC_CACHE_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_STAT_BUSY_SHIFT)) & PGMC_CPC_CPC_CACHE_STAT_BUSY_MASK) -#define PGMC_CPC_CPC_CACHE_STAT_MEM_FSM_STAT_MASK (0x700U) -#define PGMC_CPC_CPC_CACHE_STAT_MEM_FSM_STAT_SHIFT (8U) -/*! MEM_FSM_STAT - memory FSM state - */ -#define PGMC_CPC_CPC_CACHE_STAT_MEM_FSM_STAT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_STAT_MEM_FSM_STAT_SHIFT)) & PGMC_CPC_CPC_CACHE_STAT_MEM_FSM_STAT_MASK) -/*! @} */ - /*! @name CPC_LMEM_MODE - CPC local memory Mode */ /*! @{ */ + #define PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_MASK (0x3U) #define PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_SHIFT (0U) -/*! CTRL_MODE - Control mode, locked by LOCK_CFG field +/*! CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. * 0b00..Not affected by any low power mode * 0b01..Controlled by CPU power mode of the domain - * 0b10..Controlled by set point + * 0b10..Controlled by Setpoint * 0b11..Reserved */ #define PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_MASK) @@ -67792,140 +76887,142 @@ typedef struct { /*! @name CPC_LMEM_CM_CTRL - CPC local memory CPU mode control */ /*! @{ */ + #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_MASK (0xFU) #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_SHIFT (0U) -/*! MLPL_AT_RUN - Memory low power level at RUN mode +/*! MLPL_AT_RUN - Memory Low Power Level (MLPL) at RUN mode */ #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_MASK) + #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_MASK (0xF0U) #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_SHIFT (4U) -/*! MLPL_AT_WAIT - Memory low power level at WAIT mode, locked by LOCK_CFG field +/*! MLPL_AT_WAIT - Memory Low Power Level (MLPL) at WAIT mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_MASK) + #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_MASK (0xF00U) #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_SHIFT (8U) -/*! MLPL_AT_STOP - Memory low power level at STOP mode, locked by LOCK_CFG field +/*! MLPL_AT_STOP - Memory Low Power Level (MLPL) at STOP mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_MASK) + #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_MASK (0xF000U) #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_SHIFT (12U) -/*! MLPL_AT_SUSPEND - Memory low power level at STOP mode, locked by LOCK_CFG field +/*! MLPL_AT_SUSPEND - Memory Low Power Level (MLPL) at SUSPEND mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_MASK) + #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_MASK (0x10000U) #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_SHIFT (16U) -/*! MLPL_SOFT - Memory low power level software change request, keep 1 until MLPL transition complete +/*! MLPL_SOFT - Memory Low Power Level (MLPL) software change request, keep 1 until MLPL transition complete */ #define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_MASK) /*! @} */ -/*! @name CPC_LMEM_SP_CTRL_0 - CPC local memory set point control 0 */ +/*! @name CPC_LMEM_SP_CTRL_0 - CPC local memory Setpoint control 0 */ /*! @{ */ + #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_MASK (0xFU) #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_SHIFT (0U) -/*! MLPL_AT_SP0 - Memory low power level at set point 0, locked by LOCK_CFG field +/*! MLPL_AT_SP0 - Memory Low Power Level (MLPL) at Setpoint 0. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_MASK) + #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_MASK (0xF0U) #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_SHIFT (4U) -/*! MLPL_AT_SP1 - Memory low power level at set point 1, locked by LOCK_CFG field +/*! MLPL_AT_SP1 - Memory Low Power Level (MLPL) at Setpoint 1. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_MASK) + #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_MASK (0xF00U) #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_SHIFT (8U) -/*! MLPL_AT_SP2 - Memory low power level at set point 2, locked by LOCK_CFG field +/*! MLPL_AT_SP2 - Memory Low Power Level (MLPL) at Setpoint 2. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_MASK) + #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_MASK (0xF000U) #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_SHIFT (12U) -/*! MLPL_AT_SP3 - Memory low power level at set point 3, locked by LOCK_CFG field +/*! MLPL_AT_SP3 - Memory Low Power Level (MLPL) at Setpoint 3. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_MASK) + #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_MASK (0xF0000U) #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_SHIFT (16U) -/*! MLPL_AT_SP4 - Memory low power level at set point 4, locked by LOCK_CFG field +/*! MLPL_AT_SP4 - Memory Low Power Level (MLPL) at Setpoint 4. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_MASK) + #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_MASK (0xF00000U) #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_SHIFT (20U) -/*! MLPL_AT_SP5 - Memory low power level at set point 5, locked by LOCK_CFG field +/*! MLPL_AT_SP5 - Memory Low Power Level (MLPL) at Setpoint 5. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_MASK) + #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_MASK (0xF000000U) #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_SHIFT (24U) -/*! MLPL_AT_SP6 - Memory low power level at set point 6, locked by LOCK_CFG field +/*! MLPL_AT_SP6 - Memory Low Power Level (MLPL) at Setpoint 6. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_MASK) + #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_MASK (0xF0000000U) #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_SHIFT (28U) -/*! MLPL_AT_SP7 - Memory low power level at set point 7, locked by LOCK_CFG field +/*! MLPL_AT_SP7 - Memory Low Power Level (MLPL) at Setpoint 7. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_MASK) /*! @} */ -/*! @name CPC_LMEM_SP_CTRL_1 - CPC local memory set point control 1 */ +/*! @name CPC_LMEM_SP_CTRL_1 - CPC local memory Setpoint control 1 */ /*! @{ */ + #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_MASK (0xFU) #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_SHIFT (0U) -/*! MLPL_AT_SP8 - Memory low power level at set point 8, locked by LOCK_CFG field +/*! MLPL_AT_SP8 - Memory Low Power Level (MLPL) at Setpoint 8. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_MASK) + #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_MASK (0xF0U) #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_SHIFT (4U) -/*! MLPL_AT_SP9 - Memory low power level at set point 9, locked by LOCK_CFG field +/*! MLPL_AT_SP9 - Memory Low Power Level (MLPL) at Setpoint 9. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_MASK) + #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_MASK (0xF00U) #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_SHIFT (8U) -/*! MLPL_AT_SP10 - Memory low power level at set point 10, locked by LOCK_CFG field +/*! MLPL_AT_SP10 - Memory Low Power Level (MLPL) at Setpoint 10. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_MASK) + #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_MASK (0xF000U) #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_SHIFT (12U) -/*! MLPL_AT_SP11 - Memory low power level at set point 11, locked by LOCK_CFG field +/*! MLPL_AT_SP11 - Memory Low Power Level (MLPL) at Setpoint 11. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_MASK) + #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_MASK (0xF0000U) #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_SHIFT (16U) -/*! MLPL_AT_SP12 - Memory low power level at set point 12, locked by LOCK_CFG field +/*! MLPL_AT_SP12 - Memory Low Power Level (MLPL) at Setpoint 12. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_MASK) + #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_MASK (0xF00000U) #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_SHIFT (20U) -/*! MLPL_AT_SP13 - Memory low power level at set point 13, locked by LOCK_CFG field +/*! MLPL_AT_SP13 - Memory Low Power Level (MLPL) at Setpoint 13. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_MASK) + #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_MASK (0xF000000U) #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_SHIFT (24U) -/*! MLPL_AT_SP14 - Memory low power level at set point 14, locked by LOCK_CFG field +/*! MLPL_AT_SP14 - Memory Low Power Level (MLPL) at Setpoint 14. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_MASK) + #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_MASK (0xF0000000U) #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_SHIFT (28U) -/*! MLPL_AT_SP15 - Memory low power level at set point 15, locked by LOCK_CFG field +/*! MLPL_AT_SP15 - Memory Low Power Level (MLPL) at Setpoint 15. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_MASK) /*! @} */ -/*! @name CPC_LMEM_STAT - CPC local memory status */ -/*! @{ */ -#define PGMC_CPC_CPC_LMEM_STAT_CURRENT_MLPL_MASK (0xFU) -#define PGMC_CPC_CPC_LMEM_STAT_CURRENT_MLPL_SHIFT (0U) -/*! CURRENT_MLPL - Current low power level - */ -#define PGMC_CPC_CPC_LMEM_STAT_CURRENT_MLPL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_STAT_CURRENT_MLPL_SHIFT)) & PGMC_CPC_CPC_LMEM_STAT_CURRENT_MLPL_MASK) -#define PGMC_CPC_CPC_LMEM_STAT_BUSY_MASK (0x10U) -#define PGMC_CPC_CPC_LMEM_STAT_BUSY_SHIFT (4U) -/*! BUSY - Busy requesting low power level - */ -#define PGMC_CPC_CPC_LMEM_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_STAT_BUSY_SHIFT)) & PGMC_CPC_CPC_LMEM_STAT_BUSY_MASK) -#define PGMC_CPC_CPC_LMEM_STAT_MEM_FSM_STAT_MASK (0x700U) -#define PGMC_CPC_CPC_LMEM_STAT_MEM_FSM_STAT_SHIFT (8U) -/*! MEM_FSM_STAT - memory FSM state - */ -#define PGMC_CPC_CPC_LMEM_STAT_MEM_FSM_STAT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_STAT_MEM_FSM_STAT_SHIFT)) & PGMC_CPC_CPC_LMEM_STAT_MEM_FSM_STAT_MASK) -/*! @} */ - /*! * @} @@ -67938,7 +77035,7 @@ typedef struct { /** Peripheral PGMC_CPC0 base pointer */ #define PGMC_CPC0 ((PGMC_CPC_Type *)PGMC_CPC0_BASE) /** Peripheral PGMC_CPC1 base address */ -#define PGMC_CPC1_BASE (0x40C8A000u) +#define PGMC_CPC1_BASE (0x40C89400u) /** Peripheral PGMC_CPC1 base pointer */ #define PGMC_CPC1 ((PGMC_CPC_Type *)PGMC_CPC1_BASE) /** Array initializer of PGMC_CPC peripheral base addresses */ @@ -67963,43 +77060,25 @@ typedef struct { /** PGMC_MIF - Register Layout Typedef */ typedef struct { uint8_t RESERVED_0[4]; - __IO uint32_t MPC_AUTHEN_CTRL; /**< MPC Authentication Control, offset: 0x4 */ - __I uint32_t MIF_STAT; /**< MIF Status, offset: 0x8 */ - uint8_t RESERVED_1[4]; + __IO uint32_t MIF_AUTHEN_CTRL; /**< MIF Authentication Control, offset: 0x4 */ + uint8_t RESERVED_1[8]; __IO uint32_t MIF_MLPL_SLEEP; /**< MIF MLPL control of SLEEP, offset: 0x10 */ - __IO uint32_t MIF_DLY_SLEEP; /**< MIF Delay of SLEEP, offset: 0x14 */ - uint8_t RESERVED_2[8]; + uint8_t RESERVED_2[12]; __IO uint32_t MIF_MLPL_IG; /**< MIF MLPL control of IG, offset: 0x20 */ - __IO uint32_t MIF_DLY_IG; /**< MIF Delay of IG, offset: 0x24 */ - uint8_t RESERVED_3[8]; + uint8_t RESERVED_3[12]; __IO uint32_t MIF_MLPL_LS; /**< MIF MLPL control of LS, offset: 0x30 */ - __IO uint32_t MIF_DLY_LS; /**< MIF Delay of LS, offset: 0x34 */ - uint8_t RESERVED_4[8]; + uint8_t RESERVED_4[12]; __IO uint32_t MIF_MLPL_HS; /**< MIF MLPL control of HS, offset: 0x40 */ - __IO uint32_t MIF_DLY_HS; /**< MIF Delay of HS, offset: 0x44 */ - uint8_t RESERVED_5[8]; + uint8_t RESERVED_5[12]; __IO uint32_t MIF_MLPL_STDBY; /**< MIF MLPL control of STDBY, offset: 0x50 */ - __IO uint32_t MIF_DLY_STDBY; /**< MIF Delay of STDBY, offset: 0x54 */ - uint8_t RESERVED_6[8]; + uint8_t RESERVED_6[12]; __IO uint32_t MIF_MLPL_ARR_PDN; /**< MIF MLPL control of array power down, offset: 0x60 */ - __IO uint32_t MIF_DLY_ARR_HF; /**< MIF Delay of array high-fanout power switch, offset: 0x64 */ - __IO uint32_t MIF_DLY_ARR_LF; /**< MIF Delay of array low-fanout power switch, offset: 0x68 */ - uint8_t RESERVED_7[4]; + uint8_t RESERVED_7[12]; __IO uint32_t MIF_MLPL_PER_PDN; /**< MIF MLPL control of peripheral power down, offset: 0x70 */ - __IO uint32_t MIF_DLY_PER_HF; /**< MIF Delay of peripheral high-fanout power switch, offset: 0x74 */ - __IO uint32_t MIF_DLY_PER_LF; /**< MIF Delay of peripheral low-fanout power switch, offset: 0x78 */ - uint8_t RESERVED_8[4]; + uint8_t RESERVED_8[12]; __IO uint32_t MIF_MLPL_INITN; /**< MIF MLPL control of INITN, offset: 0x80 */ - __IO uint32_t MIF_DLY_INITN; /**< MIF Delay of INITN, offset: 0x84 */ - uint8_t RESERVED_9[8]; - __IO uint32_t MIF_MLPL_PSW1_OFF; /**< MIF MLPL control of power switch 1 off, offset: 0x90 */ - __IO uint32_t MIF_DLY_PSW1_OFF; /**< MIF Delay of power switch 1 off, offset: 0x94 */ - uint8_t RESERVED_10[8]; - __IO uint32_t MIF_MLPL_PSW2_OFF; /**< MIF MLPL control of power switch 2 off, offset: 0xA0 */ - __IO uint32_t MIF_DLY_PSW2_OFF; /**< MIF Delay of power switch 2 off, offset: 0xA4 */ - uint8_t RESERVED_11[8]; + uint8_t RESERVED_9[44]; __IO uint32_t MIF_MLPL_ISO; /**< MIF MLPL control of isolation enable, offset: 0xB0 */ - __IO uint32_t MIF_DLY_ISO; /**< MIF Delay of isolation enable, offset: 0xB4 */ } PGMC_MIF_Type; /* ---------------------------------------------------------------------------- @@ -68011,119 +77090,29 @@ typedef struct { * @{ */ -/*! @name MPC_AUTHEN_CTRL - MPC Authentication Control */ +/*! @name MIF_AUTHEN_CTRL - MIF Authentication Control */ /*! @{ */ -#define PGMC_MIF_MPC_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U) -#define PGMC_MIF_MPC_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U) -/*! LOCK_CFG - Configuration lock - */ -#define PGMC_MIF_MPC_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MPC_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_MIF_MPC_AUTHEN_CTRL_LOCK_CFG_MASK) -/*! @} */ -/*! @name MIF_STAT - MIF Status */ -/*! @{ */ -#define PGMC_MIF_MIF_STAT_MLPL_STATE_MASK (0xFU) -#define PGMC_MIF_MIF_STAT_MLPL_STATE_SHIFT (0U) -/*! MLPL_STATE - Memory low power level status - */ -#define PGMC_MIF_MIF_STAT_MLPL_STATE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_STAT_MLPL_STATE_SHIFT)) & PGMC_MIF_MIF_STAT_MLPL_STATE_MASK) -#define PGMC_MIF_MIF_STAT_SLEEP_STATE_MASK (0x10U) -#define PGMC_MIF_MIF_STAT_SLEEP_STATE_SHIFT (4U) -/*! SLEEP_STATE - SLEEP status - */ -#define PGMC_MIF_MIF_STAT_SLEEP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_STAT_SLEEP_STATE_SHIFT)) & PGMC_MIF_MIF_STAT_SLEEP_STATE_MASK) -#define PGMC_MIF_MIF_STAT_IG_STATE_MASK (0x20U) -#define PGMC_MIF_MIF_STAT_IG_STATE_SHIFT (5U) -/*! IG_STATE - IG status - */ -#define PGMC_MIF_MIF_STAT_IG_STATE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_STAT_IG_STATE_SHIFT)) & PGMC_MIF_MIF_STAT_IG_STATE_MASK) -#define PGMC_MIF_MIF_STAT_LS_STATE_MASK (0x40U) -#define PGMC_MIF_MIF_STAT_LS_STATE_SHIFT (6U) -/*! LS_STATE - LS status - */ -#define PGMC_MIF_MIF_STAT_LS_STATE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_STAT_LS_STATE_SHIFT)) & PGMC_MIF_MIF_STAT_LS_STATE_MASK) -#define PGMC_MIF_MIF_STAT_HS_STATE_MASK (0x80U) -#define PGMC_MIF_MIF_STAT_HS_STATE_SHIFT (7U) -/*! HS_STATE - HS status - */ -#define PGMC_MIF_MIF_STAT_HS_STATE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_STAT_HS_STATE_SHIFT)) & PGMC_MIF_MIF_STAT_HS_STATE_MASK) -#define PGMC_MIF_MIF_STAT_STDBY_STATE_MASK (0x100U) -#define PGMC_MIF_MIF_STAT_STDBY_STATE_SHIFT (8U) -/*! STDBY_STATE - STDBY status - */ -#define PGMC_MIF_MIF_STAT_STDBY_STATE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_STAT_STDBY_STATE_SHIFT)) & PGMC_MIF_MIF_STAT_STDBY_STATE_MASK) -#define PGMC_MIF_MIF_STAT_ARR_HF_STATE_MASK (0x200U) -#define PGMC_MIF_MIF_STAT_ARR_HF_STATE_SHIFT (9U) -/*! ARR_HF_STATE - ARR_HF_OFF status - */ -#define PGMC_MIF_MIF_STAT_ARR_HF_STATE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_STAT_ARR_HF_STATE_SHIFT)) & PGMC_MIF_MIF_STAT_ARR_HF_STATE_MASK) -#define PGMC_MIF_MIF_STAT_ARR_LF_STATE_MASK (0x400U) -#define PGMC_MIF_MIF_STAT_ARR_LF_STATE_SHIFT (10U) -/*! ARR_LF_STATE - ARR_LF_OFF status - */ -#define PGMC_MIF_MIF_STAT_ARR_LF_STATE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_STAT_ARR_LF_STATE_SHIFT)) & PGMC_MIF_MIF_STAT_ARR_LF_STATE_MASK) -#define PGMC_MIF_MIF_STAT_PER_HF_STATE_MASK (0x800U) -#define PGMC_MIF_MIF_STAT_PER_HF_STATE_SHIFT (11U) -/*! PER_HF_STATE - PER_HF_OFF status - */ -#define PGMC_MIF_MIF_STAT_PER_HF_STATE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_STAT_PER_HF_STATE_SHIFT)) & PGMC_MIF_MIF_STAT_PER_HF_STATE_MASK) -#define PGMC_MIF_MIF_STAT_PER_LF_STATE_MASK (0x1000U) -#define PGMC_MIF_MIF_STAT_PER_LF_STATE_SHIFT (12U) -/*! PER_LF_STATE - PER_LF_OFF status - */ -#define PGMC_MIF_MIF_STAT_PER_LF_STATE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_STAT_PER_LF_STATE_SHIFT)) & PGMC_MIF_MIF_STAT_PER_LF_STATE_MASK) -#define PGMC_MIF_MIF_STAT_INITN_STATE_MASK (0x2000U) -#define PGMC_MIF_MIF_STAT_INITN_STATE_SHIFT (13U) -/*! INITN_STATE - INITN status - */ -#define PGMC_MIF_MIF_STAT_INITN_STATE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_STAT_INITN_STATE_SHIFT)) & PGMC_MIF_MIF_STAT_INITN_STATE_MASK) -#define PGMC_MIF_MIF_STAT_PSW1_STATE_MASK (0x4000U) -#define PGMC_MIF_MIF_STAT_PSW1_STATE_SHIFT (14U) -/*! PSW1_STATE - PSW1_OFF status - */ -#define PGMC_MIF_MIF_STAT_PSW1_STATE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_STAT_PSW1_STATE_SHIFT)) & PGMC_MIF_MIF_STAT_PSW1_STATE_MASK) -#define PGMC_MIF_MIF_STAT_PSW2_STATE_MASK (0x8000U) -#define PGMC_MIF_MIF_STAT_PSW2_STATE_SHIFT (15U) -/*! PSW2_STATE - PSW2_OFF status - */ -#define PGMC_MIF_MIF_STAT_PSW2_STATE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_STAT_PSW2_STATE_SHIFT)) & PGMC_MIF_MIF_STAT_PSW2_STATE_MASK) -#define PGMC_MIF_MIF_STAT_ISO_STATE_MASK (0x10000U) -#define PGMC_MIF_MIF_STAT_ISO_STATE_SHIFT (16U) -/*! ISO_STATE - ISO_EN status +#define PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U) +#define PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U) +/*! LOCK_CFG - Configuration lock */ -#define PGMC_MIF_MIF_STAT_ISO_STATE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_STAT_ISO_STATE_SHIFT)) & PGMC_MIF_MIF_STAT_ISO_STATE_MASK) +#define PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_MASK) /*! @} */ /*! @name MIF_MLPL_SLEEP - MIF MLPL control of SLEEP */ /*! @{ */ + #define PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL_MASK (0xFFFFU) #define PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL_SHIFT (0U) /*! MLPL_CTRL - Signal behavior at each MLPL */ #define PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL_MASK) -#define PGMC_MIF_MIF_MLPL_SLEEP_BYPASS_VDD_OK_MASK (0x80000000U) -#define PGMC_MIF_MIF_MLPL_SLEEP_BYPASS_VDD_OK_SHIFT (31U) -/*! BYPASS_VDD_OK - Bypass vdd_ok, locked by LOCK_CFG field - */ -#define PGMC_MIF_MIF_MLPL_SLEEP_BYPASS_VDD_OK(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_SLEEP_BYPASS_VDD_OK_SHIFT)) & PGMC_MIF_MIF_MLPL_SLEEP_BYPASS_VDD_OK_MASK) -/*! @} */ - -/*! @name MIF_DLY_SLEEP - MIF Delay of SLEEP */ -/*! @{ */ -#define PGMC_MIF_MIF_DLY_SLEEP_PRE_HI_DLY_MASK (0xFFFFU) -#define PGMC_MIF_MIF_DLY_SLEEP_PRE_HI_DLY_SHIFT (0U) -/*! PRE_HI_DLY - Delay before asserting signal to high, locked by LOCK_CFG field - */ -#define PGMC_MIF_MIF_DLY_SLEEP_PRE_HI_DLY(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_DLY_SLEEP_PRE_HI_DLY_SHIFT)) & PGMC_MIF_MIF_DLY_SLEEP_PRE_HI_DLY_MASK) -#define PGMC_MIF_MIF_DLY_SLEEP_PRE_LO_DLY_MASK (0xFFFF0000U) -#define PGMC_MIF_MIF_DLY_SLEEP_PRE_LO_DLY_SHIFT (16U) -/*! PRE_LO_DLY - Delay before de-asserting signal to low, locked by LOCK_CFG field - */ -#define PGMC_MIF_MIF_DLY_SLEEP_PRE_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_DLY_SLEEP_PRE_LO_DLY_SHIFT)) & PGMC_MIF_MIF_DLY_SLEEP_PRE_LO_DLY_MASK) /*! @} */ /*! @name MIF_MLPL_IG - MIF MLPL control of IG */ /*! @{ */ + #define PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL_MASK (0xFFFFU) #define PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL_SHIFT (0U) /*! MLPL_CTRL - Signal behavior at each MLPL @@ -68131,22 +77120,9 @@ typedef struct { #define PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL_MASK) /*! @} */ -/*! @name MIF_DLY_IG - MIF Delay of IG */ -/*! @{ */ -#define PGMC_MIF_MIF_DLY_IG_PRE_HI_DLY_MASK (0xFFFFU) -#define PGMC_MIF_MIF_DLY_IG_PRE_HI_DLY_SHIFT (0U) -/*! PRE_HI_DLY - Delay before asserting signal to high, locked by LOCK_CFG field - */ -#define PGMC_MIF_MIF_DLY_IG_PRE_HI_DLY(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_DLY_IG_PRE_HI_DLY_SHIFT)) & PGMC_MIF_MIF_DLY_IG_PRE_HI_DLY_MASK) -#define PGMC_MIF_MIF_DLY_IG_PRE_LO_DLY_MASK (0xFFFF0000U) -#define PGMC_MIF_MIF_DLY_IG_PRE_LO_DLY_SHIFT (16U) -/*! PRE_LO_DLY - Delay before de-asserting signal to low, locked by LOCK_CFG field - */ -#define PGMC_MIF_MIF_DLY_IG_PRE_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_DLY_IG_PRE_LO_DLY_SHIFT)) & PGMC_MIF_MIF_DLY_IG_PRE_LO_DLY_MASK) -/*! @} */ - /*! @name MIF_MLPL_LS - MIF MLPL control of LS */ /*! @{ */ + #define PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL_MASK (0xFFFFU) #define PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL_SHIFT (0U) /*! MLPL_CTRL - Signal behavior at each MLPL @@ -68154,22 +77130,9 @@ typedef struct { #define PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL_MASK) /*! @} */ -/*! @name MIF_DLY_LS - MIF Delay of LS */ -/*! @{ */ -#define PGMC_MIF_MIF_DLY_LS_PRE_HI_DLY_MASK (0xFFFFU) -#define PGMC_MIF_MIF_DLY_LS_PRE_HI_DLY_SHIFT (0U) -/*! PRE_HI_DLY - Delay before asserting signal to high, locked by LOCK_CFG field - */ -#define PGMC_MIF_MIF_DLY_LS_PRE_HI_DLY(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_DLY_LS_PRE_HI_DLY_SHIFT)) & PGMC_MIF_MIF_DLY_LS_PRE_HI_DLY_MASK) -#define PGMC_MIF_MIF_DLY_LS_PRE_LO_DLY_MASK (0xFFFF0000U) -#define PGMC_MIF_MIF_DLY_LS_PRE_LO_DLY_SHIFT (16U) -/*! PRE_LO_DLY - Delay before de-asserting signal to low, locked by LOCK_CFG field - */ -#define PGMC_MIF_MIF_DLY_LS_PRE_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_DLY_LS_PRE_LO_DLY_SHIFT)) & PGMC_MIF_MIF_DLY_LS_PRE_LO_DLY_MASK) -/*! @} */ - /*! @name MIF_MLPL_HS - MIF MLPL control of HS */ /*! @{ */ + #define PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL_MASK (0xFFFFU) #define PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL_SHIFT (0U) /*! MLPL_CTRL - Signal behavior at each MLPL @@ -68177,22 +77140,9 @@ typedef struct { #define PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL_MASK) /*! @} */ -/*! @name MIF_DLY_HS - MIF Delay of HS */ -/*! @{ */ -#define PGMC_MIF_MIF_DLY_HS_PRE_HI_DLY_MASK (0xFFFFU) -#define PGMC_MIF_MIF_DLY_HS_PRE_HI_DLY_SHIFT (0U) -/*! PRE_HI_DLY - Delay before asserting signal to high, locked by LOCK_CFG field - */ -#define PGMC_MIF_MIF_DLY_HS_PRE_HI_DLY(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_DLY_HS_PRE_HI_DLY_SHIFT)) & PGMC_MIF_MIF_DLY_HS_PRE_HI_DLY_MASK) -#define PGMC_MIF_MIF_DLY_HS_PRE_LO_DLY_MASK (0xFFFF0000U) -#define PGMC_MIF_MIF_DLY_HS_PRE_LO_DLY_SHIFT (16U) -/*! PRE_LO_DLY - Delay before de-asserting signal to low, locked by LOCK_CFG field - */ -#define PGMC_MIF_MIF_DLY_HS_PRE_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_DLY_HS_PRE_LO_DLY_SHIFT)) & PGMC_MIF_MIF_DLY_HS_PRE_LO_DLY_MASK) -/*! @} */ - /*! @name MIF_MLPL_STDBY - MIF MLPL control of STDBY */ /*! @{ */ + #define PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL_MASK (0xFFFFU) #define PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL_SHIFT (0U) /*! MLPL_CTRL - Signal behavior at each MLPL @@ -68200,22 +77150,9 @@ typedef struct { #define PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL_MASK) /*! @} */ -/*! @name MIF_DLY_STDBY - MIF Delay of STDBY */ -/*! @{ */ -#define PGMC_MIF_MIF_DLY_STDBY_PRE_HI_DLY_MASK (0xFFFFU) -#define PGMC_MIF_MIF_DLY_STDBY_PRE_HI_DLY_SHIFT (0U) -/*! PRE_HI_DLY - Delay before asserting signal to high, locked by LOCK_CFG field - */ -#define PGMC_MIF_MIF_DLY_STDBY_PRE_HI_DLY(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_DLY_STDBY_PRE_HI_DLY_SHIFT)) & PGMC_MIF_MIF_DLY_STDBY_PRE_HI_DLY_MASK) -#define PGMC_MIF_MIF_DLY_STDBY_PRE_LO_DLY_MASK (0xFFFF0000U) -#define PGMC_MIF_MIF_DLY_STDBY_PRE_LO_DLY_SHIFT (16U) -/*! PRE_LO_DLY - Delay before de-asserting signal to low, locked by LOCK_CFG field - */ -#define PGMC_MIF_MIF_DLY_STDBY_PRE_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_DLY_STDBY_PRE_LO_DLY_SHIFT)) & PGMC_MIF_MIF_DLY_STDBY_PRE_LO_DLY_MASK) -/*! @} */ - /*! @name MIF_MLPL_ARR_PDN - MIF MLPL control of array power down */ /*! @{ */ + #define PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL_MASK (0xFFFFU) #define PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL_SHIFT (0U) /*! MLPL_CTRL - Signal behavior at each MLPL @@ -68223,36 +77160,9 @@ typedef struct { #define PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL_MASK) /*! @} */ -/*! @name MIF_DLY_ARR_HF - MIF Delay of array high-fanout power switch */ -/*! @{ */ -#define PGMC_MIF_MIF_DLY_ARR_HF_PRE_HI_DLY_MASK (0xFFFFU) -#define PGMC_MIF_MIF_DLY_ARR_HF_PRE_HI_DLY_SHIFT (0U) -/*! PRE_HI_DLY - Delay before turn off the high-fanout power switch, locked by LOCK_CFG field - */ -#define PGMC_MIF_MIF_DLY_ARR_HF_PRE_HI_DLY(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_DLY_ARR_HF_PRE_HI_DLY_SHIFT)) & PGMC_MIF_MIF_DLY_ARR_HF_PRE_HI_DLY_MASK) -#define PGMC_MIF_MIF_DLY_ARR_HF_PRE_LO_DLY_MASK (0xFFFF0000U) -#define PGMC_MIF_MIF_DLY_ARR_HF_PRE_LO_DLY_SHIFT (16U) -/*! PRE_LO_DLY - Delay before turn on the high-fanout power switch, locked by LOCK_CFG field - */ -#define PGMC_MIF_MIF_DLY_ARR_HF_PRE_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_DLY_ARR_HF_PRE_LO_DLY_SHIFT)) & PGMC_MIF_MIF_DLY_ARR_HF_PRE_LO_DLY_MASK) -/*! @} */ - -/*! @name MIF_DLY_ARR_LF - MIF Delay of array low-fanout power switch */ -/*! @{ */ -#define PGMC_MIF_MIF_DLY_ARR_LF_PRE_HI_DLY_MASK (0xFFFFU) -#define PGMC_MIF_MIF_DLY_ARR_LF_PRE_HI_DLY_SHIFT (0U) -/*! PRE_HI_DLY - Delay before turn off the low-fanout power switch, locked by LOCK_CFG field - */ -#define PGMC_MIF_MIF_DLY_ARR_LF_PRE_HI_DLY(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_DLY_ARR_LF_PRE_HI_DLY_SHIFT)) & PGMC_MIF_MIF_DLY_ARR_LF_PRE_HI_DLY_MASK) -#define PGMC_MIF_MIF_DLY_ARR_LF_PRE_LO_DLY_MASK (0xFFFF0000U) -#define PGMC_MIF_MIF_DLY_ARR_LF_PRE_LO_DLY_SHIFT (16U) -/*! PRE_LO_DLY - Delay before turn on the low-fanout power switch, locked by LOCK_CFG field - */ -#define PGMC_MIF_MIF_DLY_ARR_LF_PRE_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_DLY_ARR_LF_PRE_LO_DLY_SHIFT)) & PGMC_MIF_MIF_DLY_ARR_LF_PRE_LO_DLY_MASK) -/*! @} */ - /*! @name MIF_MLPL_PER_PDN - MIF MLPL control of peripheral power down */ /*! @{ */ + #define PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL_MASK (0xFFFFU) #define PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL_SHIFT (0U) /*! MLPL_CTRL - Signal behavior at each MLPL @@ -68260,110 +77170,25 @@ typedef struct { #define PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL_MASK) /*! @} */ -/*! @name MIF_DLY_PER_HF - MIF Delay of peripheral high-fanout power switch */ -/*! @{ */ -#define PGMC_MIF_MIF_DLY_PER_HF_PRE_HI_DLY_MASK (0xFFFFU) -#define PGMC_MIF_MIF_DLY_PER_HF_PRE_HI_DLY_SHIFT (0U) -/*! PRE_HI_DLY - Delay before turn off the low-fanout power switch, locked by LOCK_CFG field - */ -#define PGMC_MIF_MIF_DLY_PER_HF_PRE_HI_DLY(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_DLY_PER_HF_PRE_HI_DLY_SHIFT)) & PGMC_MIF_MIF_DLY_PER_HF_PRE_HI_DLY_MASK) -#define PGMC_MIF_MIF_DLY_PER_HF_PRE_LO_DLY_MASK (0xFFFF0000U) -#define PGMC_MIF_MIF_DLY_PER_HF_PRE_LO_DLY_SHIFT (16U) -/*! PRE_LO_DLY - Delay before turn on the low-fanout power switch, locked by LOCK_CFG field - */ -#define PGMC_MIF_MIF_DLY_PER_HF_PRE_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_DLY_PER_HF_PRE_LO_DLY_SHIFT)) & PGMC_MIF_MIF_DLY_PER_HF_PRE_LO_DLY_MASK) -/*! @} */ - -/*! @name MIF_DLY_PER_LF - MIF Delay of peripheral low-fanout power switch */ -/*! @{ */ -#define PGMC_MIF_MIF_DLY_PER_LF_PRE_HI_DLY_MASK (0xFFFFU) -#define PGMC_MIF_MIF_DLY_PER_LF_PRE_HI_DLY_SHIFT (0U) -/*! PRE_HI_DLY - Delay before turn off the low-fanout power switch, locked by LOCK_CFG field - */ -#define PGMC_MIF_MIF_DLY_PER_LF_PRE_HI_DLY(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_DLY_PER_LF_PRE_HI_DLY_SHIFT)) & PGMC_MIF_MIF_DLY_PER_LF_PRE_HI_DLY_MASK) -#define PGMC_MIF_MIF_DLY_PER_LF_PRE_LO_DLY_MASK (0xFFFF0000U) -#define PGMC_MIF_MIF_DLY_PER_LF_PRE_LO_DLY_SHIFT (16U) -/*! PRE_LO_DLY - Delay before turn on the low-fanout power switch, locked by LOCK_CFG field - */ -#define PGMC_MIF_MIF_DLY_PER_LF_PRE_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_DLY_PER_LF_PRE_LO_DLY_SHIFT)) & PGMC_MIF_MIF_DLY_PER_LF_PRE_LO_DLY_MASK) -/*! @} */ - /*! @name MIF_MLPL_INITN - MIF MLPL control of INITN */ /*! @{ */ + #define PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL_MASK (0xFFFFU) #define PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL_SHIFT (0U) /*! MLPL_CTRL - Signal behavior at each MLPL */ #define PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL_MASK) + #define PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK_MASK (0x80000000U) #define PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK_SHIFT (31U) -/*! BYPASS_VDD_OK - Bypass vdd_ok, locked by LOCK_CFG field +/*! BYPASS_VDD_OK - Bypass vdd_ok. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK_SHIFT)) & PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK_MASK) /*! @} */ -/*! @name MIF_DLY_INITN - MIF Delay of INITN */ -/*! @{ */ -#define PGMC_MIF_MIF_DLY_INITN_PRE_HI_DLY_MASK (0xFFFFU) -#define PGMC_MIF_MIF_DLY_INITN_PRE_HI_DLY_SHIFT (0U) -/*! PRE_HI_DLY - Delay before asserting signal to high, locked by LOCK_CFG field - */ -#define PGMC_MIF_MIF_DLY_INITN_PRE_HI_DLY(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_DLY_INITN_PRE_HI_DLY_SHIFT)) & PGMC_MIF_MIF_DLY_INITN_PRE_HI_DLY_MASK) -#define PGMC_MIF_MIF_DLY_INITN_PRE_LO_DLY_MASK (0xFFFF0000U) -#define PGMC_MIF_MIF_DLY_INITN_PRE_LO_DLY_SHIFT (16U) -/*! PRE_LO_DLY - Delay before de-asserting signal to low, locked by LOCK_CFG field - */ -#define PGMC_MIF_MIF_DLY_INITN_PRE_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_DLY_INITN_PRE_LO_DLY_SHIFT)) & PGMC_MIF_MIF_DLY_INITN_PRE_LO_DLY_MASK) -/*! @} */ - -/*! @name MIF_MLPL_PSW1_OFF - MIF MLPL control of power switch 1 off */ -/*! @{ */ -#define PGMC_MIF_MIF_MLPL_PSW1_OFF_MLPL_CTRL_MASK (0xFFFFU) -#define PGMC_MIF_MIF_MLPL_PSW1_OFF_MLPL_CTRL_SHIFT (0U) -/*! MLPL_CTRL - Signal behavior at each MLPL - */ -#define PGMC_MIF_MIF_MLPL_PSW1_OFF_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_PSW1_OFF_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_PSW1_OFF_MLPL_CTRL_MASK) -/*! @} */ - -/*! @name MIF_DLY_PSW1_OFF - MIF Delay of power switch 1 off */ -/*! @{ */ -#define PGMC_MIF_MIF_DLY_PSW1_OFF_PRE_HI_DLY_MASK (0xFFFFU) -#define PGMC_MIF_MIF_DLY_PSW1_OFF_PRE_HI_DLY_SHIFT (0U) -/*! PRE_HI_DLY - Delay before asserting signal to high, locked by LOCK_CFG field - */ -#define PGMC_MIF_MIF_DLY_PSW1_OFF_PRE_HI_DLY(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_DLY_PSW1_OFF_PRE_HI_DLY_SHIFT)) & PGMC_MIF_MIF_DLY_PSW1_OFF_PRE_HI_DLY_MASK) -#define PGMC_MIF_MIF_DLY_PSW1_OFF_PRE_LO_DLY_MASK (0xFFFF0000U) -#define PGMC_MIF_MIF_DLY_PSW1_OFF_PRE_LO_DLY_SHIFT (16U) -/*! PRE_LO_DLY - Delay before de-asserting signal to low, locked by LOCK_CFG field - */ -#define PGMC_MIF_MIF_DLY_PSW1_OFF_PRE_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_DLY_PSW1_OFF_PRE_LO_DLY_SHIFT)) & PGMC_MIF_MIF_DLY_PSW1_OFF_PRE_LO_DLY_MASK) -/*! @} */ - -/*! @name MIF_MLPL_PSW2_OFF - MIF MLPL control of power switch 2 off */ -/*! @{ */ -#define PGMC_MIF_MIF_MLPL_PSW2_OFF_MLPL_CTRL_MASK (0xFFFFU) -#define PGMC_MIF_MIF_MLPL_PSW2_OFF_MLPL_CTRL_SHIFT (0U) -/*! MLPL_CTRL - Signal behavior at each MLPL - */ -#define PGMC_MIF_MIF_MLPL_PSW2_OFF_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_PSW2_OFF_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_PSW2_OFF_MLPL_CTRL_MASK) -/*! @} */ - -/*! @name MIF_DLY_PSW2_OFF - MIF Delay of power switch 2 off */ -/*! @{ */ -#define PGMC_MIF_MIF_DLY_PSW2_OFF_PRE_HI_DLY_MASK (0xFFFFU) -#define PGMC_MIF_MIF_DLY_PSW2_OFF_PRE_HI_DLY_SHIFT (0U) -/*! PRE_HI_DLY - Delay before asserting signal to high, locked by LOCK_CFG field - */ -#define PGMC_MIF_MIF_DLY_PSW2_OFF_PRE_HI_DLY(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_DLY_PSW2_OFF_PRE_HI_DLY_SHIFT)) & PGMC_MIF_MIF_DLY_PSW2_OFF_PRE_HI_DLY_MASK) -#define PGMC_MIF_MIF_DLY_PSW2_OFF_PRE_LO_DLY_MASK (0xFFFF0000U) -#define PGMC_MIF_MIF_DLY_PSW2_OFF_PRE_LO_DLY_SHIFT (16U) -/*! PRE_LO_DLY - Delay before de-asserting signal to low, locked by LOCK_CFG field - */ -#define PGMC_MIF_MIF_DLY_PSW2_OFF_PRE_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_DLY_PSW2_OFF_PRE_LO_DLY_SHIFT)) & PGMC_MIF_MIF_DLY_PSW2_OFF_PRE_LO_DLY_MASK) -/*! @} */ - /*! @name MIF_MLPL_ISO - MIF MLPL control of isolation enable */ /*! @{ */ + #define PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL_MASK (0xFFFFU) #define PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL_SHIFT (0U) /*! MLPL_CTRL - Signal behavior at each MLPL @@ -68371,20 +77196,6 @@ typedef struct { #define PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL_MASK) /*! @} */ -/*! @name MIF_DLY_ISO - MIF Delay of isolation enable */ -/*! @{ */ -#define PGMC_MIF_MIF_DLY_ISO_PRE_HI_DLY_MASK (0xFFFFU) -#define PGMC_MIF_MIF_DLY_ISO_PRE_HI_DLY_SHIFT (0U) -/*! PRE_HI_DLY - Delay before asserting signal to high, locked by LOCK_CFG field - */ -#define PGMC_MIF_MIF_DLY_ISO_PRE_HI_DLY(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_DLY_ISO_PRE_HI_DLY_SHIFT)) & PGMC_MIF_MIF_DLY_ISO_PRE_HI_DLY_MASK) -#define PGMC_MIF_MIF_DLY_ISO_PRE_LO_DLY_MASK (0xFFFF0000U) -#define PGMC_MIF_MIF_DLY_ISO_PRE_LO_DLY_SHIFT (16U) -/*! PRE_LO_DLY - Delay before de-asserting signal to low, locked by LOCK_CFG field - */ -#define PGMC_MIF_MIF_DLY_ISO_PRE_LO_DLY(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_DLY_ISO_PRE_LO_DLY_SHIFT)) & PGMC_MIF_MIF_DLY_ISO_PRE_LO_DLY_MASK) -/*! @} */ - /*! * @} @@ -68392,22 +77203,6 @@ typedef struct { /* PGMC_MIF - Peripheral instance base addresses */ -/** Peripheral PGMC_BPC0_MIF base address */ -#define PGMC_BPC0_MIF_BASE (0x40C88100u) -/** Peripheral PGMC_BPC0_MIF base pointer */ -#define PGMC_BPC0_MIF ((PGMC_MIF_Type *)PGMC_BPC0_MIF_BASE) -/** Peripheral PGMC_BPC1_MIF base address */ -#define PGMC_BPC1_MIF_BASE (0x40C88300u) -/** Peripheral PGMC_BPC1_MIF base pointer */ -#define PGMC_BPC1_MIF ((PGMC_MIF_Type *)PGMC_BPC1_MIF_BASE) -/** Peripheral PGMC_BPC2_MIF base address */ -#define PGMC_BPC2_MIF_BASE (0x40C88500u) -/** Peripheral PGMC_BPC2_MIF base pointer */ -#define PGMC_BPC2_MIF ((PGMC_MIF_Type *)PGMC_BPC2_MIF_BASE) -/** Peripheral PGMC_BPC3_MIF base address */ -#define PGMC_BPC3_MIF_BASE (0x40C88700u) -/** Peripheral PGMC_BPC3_MIF base pointer */ -#define PGMC_BPC3_MIF ((PGMC_MIF_Type *)PGMC_BPC3_MIF_BASE) /** Peripheral PGMC_CPC0_MIF0 base address */ #define PGMC_CPC0_MIF0_BASE (0x40C89100u) /** Peripheral PGMC_CPC0_MIF0 base pointer */ @@ -68417,17 +77212,17 @@ typedef struct { /** Peripheral PGMC_CPC0_MIF1 base pointer */ #define PGMC_CPC0_MIF1 ((PGMC_MIF_Type *)PGMC_CPC0_MIF1_BASE) /** Peripheral PGMC_CPC1_MIF0 base address */ -#define PGMC_CPC1_MIF0_BASE (0x40C8A100u) +#define PGMC_CPC1_MIF0_BASE (0x40C89500u) /** Peripheral PGMC_CPC1_MIF0 base pointer */ #define PGMC_CPC1_MIF0 ((PGMC_MIF_Type *)PGMC_CPC1_MIF0_BASE) /** Peripheral PGMC_CPC1_MIF1 base address */ -#define PGMC_CPC1_MIF1_BASE (0x40C8A200u) +#define PGMC_CPC1_MIF1_BASE (0x40C89600u) /** Peripheral PGMC_CPC1_MIF1 base pointer */ #define PGMC_CPC1_MIF1 ((PGMC_MIF_Type *)PGMC_CPC1_MIF1_BASE) /** Array initializer of PGMC_MIF peripheral base addresses */ -#define PGMC_MIF_BASE_ADDRS { PGMC_BPC0_MIF_BASE, PGMC_BPC1_MIF_BASE, PGMC_BPC2_MIF_BASE, PGMC_BPC3_MIF_BASE, PGMC_CPC0_MIF0_BASE, PGMC_CPC0_MIF1_BASE, PGMC_CPC1_MIF0_BASE, PGMC_CPC1_MIF1_BASE } +#define PGMC_MIF_BASE_ADDRS { PGMC_CPC0_MIF0_BASE, PGMC_CPC0_MIF1_BASE, PGMC_CPC1_MIF0_BASE, PGMC_CPC1_MIF1_BASE } /** Array initializer of PGMC_MIF peripheral base pointers */ -#define PGMC_MIF_BASE_PTRS { PGMC_BPC0_MIF, PGMC_BPC1_MIF, PGMC_BPC2_MIF, PGMC_BPC3_MIF, PGMC_CPC0_MIF0, PGMC_CPC0_MIF1, PGMC_CPC1_MIF0, PGMC_CPC1_MIF1 } +#define PGMC_MIF_BASE_PTRS { PGMC_CPC0_MIF0, PGMC_CPC0_MIF1, PGMC_CPC1_MIF0, PGMC_CPC1_MIF1 } /*! * @} @@ -68450,11 +77245,7 @@ typedef struct { uint8_t RESERVED_1[8]; __IO uint32_t PPC_MODE; /**< PPC Mode, offset: 0x10 */ __IO uint32_t PPC_STBY_CM_CTRL; /**< PPC standby CPU mode control, offset: 0x14 */ - __IO uint32_t PPC_STBY_SP_CTRL; /**< PPC standby set point control, offset: 0x18 */ - __IO uint32_t PPC_STBY_PRE_DLY_CTRL; /**< PPC standby pre delay control, offset: 0x1C */ - __IO uint32_t PPC_STBY_ACK_CTRL; /**< PPC standby acknowledge control, offset: 0x20 */ - __I uint32_t PPC_STBY_ACK_STAT; /**< PPC standby acknowledge state, offset: 0x24 */ - __I uint32_t PPC_STBY_STAT; /**< PPC status, offset: 0x28 */ + __IO uint32_t PPC_STBY_SP_CTRL; /**< PPC standby Setpoint control, offset: 0x18 */ } PGMC_PPC_Type; /* ---------------------------------------------------------------------------- @@ -68468,31 +77259,37 @@ typedef struct { /*! @name PPC_AUTHEN_CTRL - PPC Authentication Control */ /*! @{ */ + #define PGMC_PPC_PPC_AUTHEN_CTRL_USER_MASK (0x1U) #define PGMC_PPC_PPC_AUTHEN_CTRL_USER_SHIFT (0U) /*! USER - Allow user mode access */ #define PGMC_PPC_PPC_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_USER_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_USER_MASK) + #define PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_MASK (0x2U) #define PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_SHIFT (1U) /*! NONSECURE - Allow non-secure mode access */ #define PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_MASK) + #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U) #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U) /*! LOCK_SETTING - Lock NONSECURE and USER */ #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_MASK) + #define PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U) #define PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U) /*! WHITE_LIST - Domain ID white list */ #define PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_MASK) + #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_MASK (0x1000U) #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U) /*! LOCK_LIST - White list lock */ #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_MASK) + #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U) #define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U) /*! LOCK_CFG - Configuration lock @@ -68502,44 +77299,55 @@ typedef struct { /*! @name PPC_MODE - PPC Mode */ /*! @{ */ + #define PGMC_PPC_PPC_MODE_CTRL_MODE_MASK (0x3U) #define PGMC_PPC_PPC_MODE_CTRL_MODE_SHIFT (0U) -/*! CTRL_MODE - Control mode, locked by LOCK_CFG field +/*! CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. * 0b00..Not affected by any low power mode * 0b01..Controlled by CPU power mode of the domain - * 0b10..Controlled by set point and system standby + * 0b10..Controlled by Setpoint and system standby * 0b11..Reserved */ #define PGMC_PPC_PPC_MODE_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_MODE_CTRL_MODE_SHIFT)) & PGMC_PPC_PPC_MODE_CTRL_MODE_MASK) + #define PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN_MASK (0x30U) #define PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN_SHIFT (4U) /*! DOMAIN_ASSIGN - Domain assignment of the BPC + * 0b00..Domain 0 + * 0b01..Domain 1 + * 0b10..Domain 2 + * 0b11..Domain 3 */ #define PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN_SHIFT)) & PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN_MASK) /*! @} */ /*! @name PPC_STBY_CM_CTRL - PPC standby CPU mode control */ /*! @{ */ + #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_MASK (0x2U) #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_SHIFT (1U) -/*! STBY_ON_AT_WAIT - PMIC Standby on when domain enters WAIT mode, locked by LOCK_CFG field +/*! STBY_ON_AT_WAIT - PMIC Standby on when domain enters WAIT mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_MASK) + #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_MASK (0x4U) #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_SHIFT (2U) -/*! STBY_ON_AT_STOP - PMIC Standby on when domain enters STOP mode, locked by LOCK_CFG field +/*! STBY_ON_AT_STOP - PMIC Standby on when domain enters STOP mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_MASK) + #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_MASK (0x8U) #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_SHIFT (3U) -/*! STBY_ON_AT_SUSPEND - PMIC Standby on when domain enters SUSPEND mode, locked by LOCK_CFG field +/*! STBY_ON_AT_SUSPEND - PMIC Standby on when domain enters SUSPEND mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_MASK) + #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_MASK (0x100U) #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_SHIFT (8U) /*! STBY_ON_SOFT - Software PMIC standby on trigger */ #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_MASK) + #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_MASK (0x200U) #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_SHIFT (9U) /*! STBY_OFF_SOFT - Software PMIC standby off trigger @@ -68547,146 +77355,23 @@ typedef struct { #define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_MASK) /*! @} */ -/*! @name PPC_STBY_SP_CTRL - PPC standby set point control */ +/*! @name PPC_STBY_SP_CTRL - PPC standby Setpoint control */ /*! @{ */ + #define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE_MASK (0xFFFFU) #define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE_SHIFT (0U) -/*! STBY_ON_AT_SP_ACTIVE - PMIC standby on when system enters set point number, locked by LOCK_CFG field +/*! STBY_ON_AT_SP_ACTIVE - PMIC standby on when system enters Setpoint number. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE_SHIFT)) & PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE_MASK) + #define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_MASK (0xFFFF0000U) #define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_SHIFT (16U) -/*! STBY_ON_AT_SP_SLEEP - PMIC standby on when system enters set point number and system is in standby mode, locked by LOCK_CFG field +/*! STBY_ON_AT_SP_SLEEP - PMIC standby on when system enters Setpoint number and system is in + * standby mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. */ #define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_SHIFT)) & PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_MASK) /*! @} */ -/*! @name PPC_STBY_PRE_DLY_CTRL - PPC standby pre delay control */ -/*! @{ */ -#define PGMC_PPC_PPC_STBY_PRE_DLY_CTRL_DLY_PRE_STBY_ON_MASK (0xFFFFU) -#define PGMC_PPC_PPC_STBY_PRE_DLY_CTRL_DLY_PRE_STBY_ON_SHIFT (0U) -/*! DLY_PRE_STBY_ON - Delay before pmic_standby on, locked by LOCK_CFG field - */ -#define PGMC_PPC_PPC_STBY_PRE_DLY_CTRL_DLY_PRE_STBY_ON(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_PRE_DLY_CTRL_DLY_PRE_STBY_ON_SHIFT)) & PGMC_PPC_PPC_STBY_PRE_DLY_CTRL_DLY_PRE_STBY_ON_MASK) -#define PGMC_PPC_PPC_STBY_PRE_DLY_CTRL_DLY_PRE_STBY_OFF_MASK (0xFFFF0000U) -#define PGMC_PPC_PPC_STBY_PRE_DLY_CTRL_DLY_PRE_STBY_OFF_SHIFT (16U) -/*! DLY_PRE_STBY_OFF - Delay before pmic_standby off, locked by LOCK_CFG field - */ -#define PGMC_PPC_PPC_STBY_PRE_DLY_CTRL_DLY_PRE_STBY_OFF(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_PRE_DLY_CTRL_DLY_PRE_STBY_OFF_SHIFT)) & PGMC_PPC_PPC_STBY_PRE_DLY_CTRL_DLY_PRE_STBY_OFF_MASK) -/*! @} */ - -/*! @name PPC_STBY_ACK_CTRL - PPC standby acknowledge control */ -/*! @{ */ -#define PGMC_PPC_PPC_STBY_ACK_CTRL_STBY_ON_CNT_CFG_MASK (0xFFFU) -#define PGMC_PPC_PPC_STBY_ACK_CTRL_STBY_ON_CNT_CFG_SHIFT (0U) -/*! STBY_ON_CNT_CFG - PMIC standby on acknowledge count configure, useage is depending on STBY_ON_CNT_MODE, locked by LOCK_CFG field - */ -#define PGMC_PPC_PPC_STBY_ACK_CTRL_STBY_ON_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_ACK_CTRL_STBY_ON_CNT_CFG_SHIFT)) & PGMC_PPC_PPC_STBY_ACK_CTRL_STBY_ON_CNT_CFG_MASK) -#define PGMC_PPC_PPC_STBY_ACK_CTRL_STBY_ON_CNT_MODE_MASK (0xC000U) -#define PGMC_PPC_PPC_STBY_ACK_CTRL_STBY_ON_CNT_MODE_SHIFT (14U) -/*! STBY_ON_CNT_MODE - PMIC standby on acknowledge count mode, locked by LOCK_CFG field - * 0b00..Finish the process once pmic_standby signal changes - * 0b01..Finish the process once getting acknowledge from PMIC - * 0b10..Ignore PMIC acknowledge, the delay counter starts to count once pmic_standby chang - * 0b11..Time out mode, the counter starts to count once pmic_standby changes, then finishes the process when - * either acknowledge received or counting to CNT_CFG value - */ -#define PGMC_PPC_PPC_STBY_ACK_CTRL_STBY_ON_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_ACK_CTRL_STBY_ON_CNT_MODE_SHIFT)) & PGMC_PPC_PPC_STBY_ACK_CTRL_STBY_ON_CNT_MODE_MASK) -#define PGMC_PPC_PPC_STBY_ACK_CTRL_STBY_OFF_CNT_CFG_MASK (0xFFF0000U) -#define PGMC_PPC_PPC_STBY_ACK_CTRL_STBY_OFF_CNT_CFG_SHIFT (16U) -/*! STBY_OFF_CNT_CFG - PMIC standby off acknowledge count configure, useage is depending on STBY_OFF_CNT_MODE, locked by LOCK_CFG field - */ -#define PGMC_PPC_PPC_STBY_ACK_CTRL_STBY_OFF_CNT_CFG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_ACK_CTRL_STBY_OFF_CNT_CFG_SHIFT)) & PGMC_PPC_PPC_STBY_ACK_CTRL_STBY_OFF_CNT_CFG_MASK) -#define PGMC_PPC_PPC_STBY_ACK_CTRL_STBY_OFF_CNT_MODE_MASK (0xC0000000U) -#define PGMC_PPC_PPC_STBY_ACK_CTRL_STBY_OFF_CNT_MODE_SHIFT (30U) -/*! STBY_OFF_CNT_MODE - PMIC standby off acknowledge count mode, locked by LOCK_CFG field - */ -#define PGMC_PPC_PPC_STBY_ACK_CTRL_STBY_OFF_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_ACK_CTRL_STBY_OFF_CNT_MODE_SHIFT)) & PGMC_PPC_PPC_STBY_ACK_CTRL_STBY_OFF_CNT_MODE_MASK) -/*! @} */ - -/*! @name PPC_STBY_ACK_STAT - PPC standby acknowledge state */ -/*! @{ */ -#define PGMC_PPC_PPC_STBY_ACK_STAT_STBY_ON_ACK_CNT_MASK (0xFFFU) -#define PGMC_PPC_PPC_STBY_ACK_STAT_STBY_ON_ACK_CNT_SHIFT (0U) -/*! STBY_ON_ACK_CNT - Record the delay from pmic_standby on to acknowledge received - */ -#define PGMC_PPC_PPC_STBY_ACK_STAT_STBY_ON_ACK_CNT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_ACK_STAT_STBY_ON_ACK_CNT_SHIFT)) & PGMC_PPC_PPC_STBY_ACK_STAT_STBY_ON_ACK_CNT_MASK) -#define PGMC_PPC_PPC_STBY_ACK_STAT_STBY_OFF_ACK_CNT_MASK (0xFFF0000U) -#define PGMC_PPC_PPC_STBY_ACK_STAT_STBY_OFF_ACK_CNT_SHIFT (16U) -/*! STBY_OFF_ACK_CNT - Record the delay from pmic_standby off to acknowledge received - */ -#define PGMC_PPC_PPC_STBY_ACK_STAT_STBY_OFF_ACK_CNT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_ACK_STAT_STBY_OFF_ACK_CNT_SHIFT)) & PGMC_PPC_PPC_STBY_ACK_STAT_STBY_OFF_ACK_CNT_MASK) -/*! @} */ - -/*! @name PPC_STBY_STAT - PPC status */ -/*! @{ */ -#define PGMC_PPC_PPC_STBY_STAT_CM_PMIC_REQUEST_MASK (0xFU) -#define PGMC_PPC_PPC_STBY_STAT_CM_PMIC_REQUEST_SHIFT (0U) -/*! CM_PMIC_REQUEST - CPU mode trans pmic request of 4 domains - */ -#define PGMC_PPC_PPC_STBY_STAT_CM_PMIC_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_STAT_CM_PMIC_REQUEST_SHIFT)) & PGMC_PPC_PPC_STBY_STAT_CM_PMIC_REQUEST_MASK) -#define PGMC_PPC_PPC_STBY_STAT_SP_PMIC_DOWN_REQUEST_MASK (0x10U) -#define PGMC_PPC_PPC_STBY_STAT_SP_PMIC_DOWN_REQUEST_SHIFT (4U) -/*! SP_PMIC_DOWN_REQUEST - Set point trans pmic down request - */ -#define PGMC_PPC_PPC_STBY_STAT_SP_PMIC_DOWN_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_STAT_SP_PMIC_DOWN_REQUEST_SHIFT)) & PGMC_PPC_PPC_STBY_STAT_SP_PMIC_DOWN_REQUEST_MASK) -#define PGMC_PPC_PPC_STBY_STAT_SP_PMIC_UP_REQUEST_MASK (0x20U) -#define PGMC_PPC_PPC_STBY_STAT_SP_PMIC_UP_REQUEST_SHIFT (5U) -/*! SP_PMIC_UP_REQUEST - Set point trans pmic up request - */ -#define PGMC_PPC_PPC_STBY_STAT_SP_PMIC_UP_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_STAT_SP_PMIC_UP_REQUEST_SHIFT)) & PGMC_PPC_PPC_STBY_STAT_SP_PMIC_UP_REQUEST_MASK) -#define PGMC_PPC_PPC_STBY_STAT_STBY_IN_REQUEST_MASK (0x40U) -#define PGMC_PPC_PPC_STBY_STAT_STBY_IN_REQUEST_SHIFT (6U) -/*! STBY_IN_REQUEST - standby_pmic_in_request pin status - */ -#define PGMC_PPC_PPC_STBY_STAT_STBY_IN_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_STAT_STBY_IN_REQUEST_SHIFT)) & PGMC_PPC_PPC_STBY_STAT_STBY_IN_REQUEST_MASK) -#define PGMC_PPC_PPC_STBY_STAT_STBY_OUT_REQUEST_MASK (0x80U) -#define PGMC_PPC_PPC_STBY_STAT_STBY_OUT_REQUEST_SHIFT (7U) -/*! STBY_OUT_REQUEST - standby_pmic_out_request pin status - */ -#define PGMC_PPC_PPC_STBY_STAT_STBY_OUT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_STAT_STBY_OUT_REQUEST_SHIFT)) & PGMC_PPC_PPC_STBY_STAT_STBY_OUT_REQUEST_MASK) -#define PGMC_PPC_PPC_STBY_STAT_CM_PMIC_DONE_MASK (0xF00U) -#define PGMC_PPC_PPC_STBY_STAT_CM_PMIC_DONE_SHIFT (8U) -/*! CM_PMIC_DONE - CPU mode trans pmic done of 4 domains - */ -#define PGMC_PPC_PPC_STBY_STAT_CM_PMIC_DONE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_STAT_CM_PMIC_DONE_SHIFT)) & PGMC_PPC_PPC_STBY_STAT_CM_PMIC_DONE_MASK) -#define PGMC_PPC_PPC_STBY_STAT_SP_PMIC_DOWN_DONE_MASK (0x1000U) -#define PGMC_PPC_PPC_STBY_STAT_SP_PMIC_DOWN_DONE_SHIFT (12U) -/*! SP_PMIC_DOWN_DONE - Set point trans pmic down done - */ -#define PGMC_PPC_PPC_STBY_STAT_SP_PMIC_DOWN_DONE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_STAT_SP_PMIC_DOWN_DONE_SHIFT)) & PGMC_PPC_PPC_STBY_STAT_SP_PMIC_DOWN_DONE_MASK) -#define PGMC_PPC_PPC_STBY_STAT_SP_PMIC_UP_DONE_MASK (0x2000U) -#define PGMC_PPC_PPC_STBY_STAT_SP_PMIC_UP_DONE_SHIFT (13U) -/*! SP_PMIC_UP_DONE - Set point trans pmic up done - */ -#define PGMC_PPC_PPC_STBY_STAT_SP_PMIC_UP_DONE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_STAT_SP_PMIC_UP_DONE_SHIFT)) & PGMC_PPC_PPC_STBY_STAT_SP_PMIC_UP_DONE_MASK) -#define PGMC_PPC_PPC_STBY_STAT_STBY_IN_DONE_MASK (0x4000U) -#define PGMC_PPC_PPC_STBY_STAT_STBY_IN_DONE_SHIFT (14U) -/*! STBY_IN_DONE - standby_pmic_in_done pin status - */ -#define PGMC_PPC_PPC_STBY_STAT_STBY_IN_DONE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_STAT_STBY_IN_DONE_SHIFT)) & PGMC_PPC_PPC_STBY_STAT_STBY_IN_DONE_MASK) -#define PGMC_PPC_PPC_STBY_STAT_STBY_OUT_DONE_MASK (0x8000U) -#define PGMC_PPC_PPC_STBY_STAT_STBY_OUT_DONE_SHIFT (15U) -/*! STBY_OUT_DONE - standby_pmic_out_done pin status - */ -#define PGMC_PPC_PPC_STBY_STAT_STBY_OUT_DONE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_STAT_STBY_OUT_DONE_SHIFT)) & PGMC_PPC_PPC_STBY_STAT_STBY_OUT_DONE_MASK) -#define PGMC_PPC_PPC_STBY_STAT_FSM_STAT_MASK (0xF0000U) -#define PGMC_PPC_PPC_STBY_STAT_FSM_STAT_SHIFT (16U) -/*! FSM_STAT - standby FSM state - */ -#define PGMC_PPC_PPC_STBY_STAT_FSM_STAT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_STAT_FSM_STAT_SHIFT)) & PGMC_PPC_PPC_STBY_STAT_FSM_STAT_MASK) -#define PGMC_PPC_PPC_STBY_STAT_PMIC_STBY_PIN_MASK (0x1000000U) -#define PGMC_PPC_PPC_STBY_STAT_PMIC_STBY_PIN_SHIFT (24U) -/*! PMIC_STBY_PIN - pmic_standby pin status - */ -#define PGMC_PPC_PPC_STBY_STAT_PMIC_STBY_PIN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_STAT_PMIC_STBY_PIN_SHIFT)) & PGMC_PPC_PPC_STBY_STAT_PMIC_STBY_PIN_MASK) -#define PGMC_PPC_PPC_STBY_STAT_PMIC_READY_PIN_MASK (0x2000000U) -#define PGMC_PPC_PPC_STBY_STAT_PMIC_READY_PIN_SHIFT (25U) -/*! PMIC_READY_PIN - pmic_standby pin status - */ -#define PGMC_PPC_PPC_STBY_STAT_PMIC_READY_PIN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_STAT_PMIC_READY_PIN_SHIFT)) & PGMC_PPC_PPC_STBY_STAT_PMIC_READY_PIN_MASK) -/*! @} */ - /*! * @} @@ -68745,11 +77430,13 @@ typedef struct { /*! @name CTRL0 - Analog Control Register CTRL0 */ /*! @{ */ + #define PHY_LDO_CTRL0_LINREG_EN_MASK (0x1U) #define PHY_LDO_CTRL0_LINREG_EN_SHIFT (0U) /*! LINREG_EN - LinrReg master enable */ #define PHY_LDO_CTRL0_LINREG_EN(x) (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_EN_SHIFT)) & PHY_LDO_CTRL0_LINREG_EN_MASK) + #define PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_MASK (0x2U) #define PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_SHIFT (1U) /*! LINREG_PWRUPLOAD_DIS - LinReg power-up load disable @@ -68757,11 +77444,13 @@ typedef struct { * 0b1..Internal pull-down disabled */ #define PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS(x) (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_SHIFT)) & PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_MASK) + #define PHY_LDO_CTRL0_LINREG_ILIMIT_EN_MASK (0x4U) #define PHY_LDO_CTRL0_LINREG_ILIMIT_EN_SHIFT (2U) /*! LINREG_ILIMIT_EN - LinReg current-limit enable */ #define PHY_LDO_CTRL0_LINREG_ILIMIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_ILIMIT_EN_SHIFT)) & PHY_LDO_CTRL0_LINREG_ILIMIT_EN_MASK) + #define PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_MASK (0x1F0U) #define PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_SHIFT (4U) /*! LINREG_OUTPUT_TRG - LinReg output voltage target setting @@ -68770,6 +77459,7 @@ typedef struct { * 0b11111..Set output voltage to x.xV */ #define PHY_LDO_CTRL0_LINREG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_SHIFT)) & PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_MASK) + #define PHY_LDO_CTRL0_LINREG_PHY_ISO_B_MASK (0x8000U) #define PHY_LDO_CTRL0_LINREG_PHY_ISO_B_SHIFT (15U) /*! LINREG_PHY_ISO_B - Isolation control for attached PHY load @@ -68779,6 +77469,7 @@ typedef struct { /*! @name STAT0 - Analog Status Register STAT0 */ /*! @{ */ + #define PHY_LDO_STAT0_LINREG_STAT_MASK (0xFU) #define PHY_LDO_STAT0_LINREG_STAT_SHIFT (0U) /*! LINREG_STAT - LinReg Status Bits @@ -68842,6 +77533,7 @@ typedef struct { /*! @name MCR - PIT Module Control Register */ /*! @{ */ + #define PIT_MCR_FRZ_MASK (0x1U) #define PIT_MCR_FRZ_SHIFT (0U) /*! FRZ - Freeze @@ -68849,6 +77541,7 @@ typedef struct { * 0b1..Timers are stopped in Debug mode. */ #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) + #define PIT_MCR_MDIS_MASK (0x2U) #define PIT_MCR_MDIS_SHIFT (1U) /*! MDIS - Module Disable for PIT @@ -68860,6 +77553,7 @@ typedef struct { /*! @name LTMR64H - PIT Upper Lifetime Timer Register */ /*! @{ */ + #define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU) #define PIT_LTMR64H_LTH_SHIFT (0U) /*! LTH - Life Timer value @@ -68869,6 +77563,7 @@ typedef struct { /*! @name LTMR64L - PIT Lower Lifetime Timer Register */ /*! @{ */ + #define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU) #define PIT_LTMR64L_LTL_SHIFT (0U) /*! LTL - Life Timer value @@ -68878,6 +77573,7 @@ typedef struct { /*! @name LDVAL - Timer Load Value Register */ /*! @{ */ + #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) #define PIT_LDVAL_TSV_SHIFT (0U) /*! TSV - Timer Start Value @@ -68890,6 +77586,7 @@ typedef struct { /*! @name CVAL - Current Timer Value Register */ /*! @{ */ + #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) #define PIT_CVAL_TVL_SHIFT (0U) /*! TVL - Current Timer Value @@ -68902,6 +77599,7 @@ typedef struct { /*! @name TCTRL - Timer Control Register */ /*! @{ */ + #define PIT_TCTRL_TEN_MASK (0x1U) #define PIT_TCTRL_TEN_SHIFT (0U) /*! TEN - Timer Enable @@ -68909,6 +77607,7 @@ typedef struct { * 0b1..Timer n is enabled. */ #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) + #define PIT_TCTRL_TIE_MASK (0x2U) #define PIT_TCTRL_TIE_SHIFT (1U) /*! TIE - Timer Interrupt Enable @@ -68916,6 +77615,7 @@ typedef struct { * 0b1..Interrupt is requested whenever TIF is set. */ #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) + #define PIT_TCTRL_CHN_MASK (0x4U) #define PIT_TCTRL_CHN_SHIFT (2U) /*! CHN - Chain Mode @@ -68930,6 +77630,7 @@ typedef struct { /*! @name TFLG - Timer Flag Register */ /*! @{ */ + #define PIT_TFLG_TIF_MASK (0x1U) #define PIT_TFLG_TIF_SHIFT (0U) /*! TIF - Timer Interrupt Flag @@ -68980,38 +77681,38 @@ typedef struct { /** PUF - Register Layout Typedef */ typedef struct { - __IO uint32_t CTRL; /**< Quiddikey Control Register, offset: 0x0 */ - __IO uint32_t KEYINDEX; /**< Quiddikey Key Index Register, offset: 0x4 */ - __IO uint32_t KEYSIZE; /**< Quiddikey Key Size Register, offset: 0x8 */ + __IO uint32_t CTRL; /**< PUF Control Register, offset: 0x0 */ + __IO uint32_t KEYINDEX; /**< PUF Key Index Register, offset: 0x4 */ + __IO uint32_t KEYSIZE; /**< PUF Key Size Register, offset: 0x8 */ uint8_t RESERVED_0[20]; - __I uint32_t STAT; /**< Quiddikey Status Register, offset: 0x20 */ + __I uint32_t STAT; /**< PUF Status Register, offset: 0x20 */ uint8_t RESERVED_1[4]; - __I uint32_t ALLOW; /**< Quiddikey Allow Register, offset: 0x28 */ + __I uint32_t ALLOW; /**< PUF Allow Register, offset: 0x28 */ uint8_t RESERVED_2[20]; - __O uint32_t KEYINPUT; /**< Quiddikey Key Input Register, offset: 0x40 */ - __O uint32_t CODEINPUT; /**< Quiddikey Code Input Register, offset: 0x44 */ - __I uint32_t CODEOUTPUT; /**< Quiddikey Code Output Register, offset: 0x48 */ + __O uint32_t KEYINPUT; /**< PUF Key Input Register, offset: 0x40 */ + __O uint32_t CODEINPUT; /**< PUF Code Input Register, offset: 0x44 */ + __I uint32_t CODEOUTPUT; /**< PUF Code Output Register, offset: 0x48 */ uint8_t RESERVED_3[20]; - __I uint32_t KEYOUTINDEX; /**< Quiddikey Key Output Index Register, offset: 0x60 */ - __I uint32_t KEYOUTPUT; /**< Quiddikey Key Output Register, offset: 0x64 */ + __I uint32_t KEYOUTINDEX; /**< PUF Key Output Index Register, offset: 0x60 */ + __I uint32_t KEYOUTPUT; /**< PUF Key Output Register, offset: 0x64 */ uint8_t RESERVED_4[116]; - __IO uint32_t IFSTAT; /**< Quiddikey Interface Status Register, offset: 0xDC */ + __IO uint32_t IFSTAT; /**< PUF Interface Status Register, offset: 0xDC */ uint8_t RESERVED_5[28]; - __I uint32_t VERSION; /**< Quiddikey Version Register, offset: 0xFC */ - __IO uint32_t INTEN; /**< Quiddikey Interrupt Enable, offset: 0x100 */ - __IO uint32_t INTSTAT; /**< Quiddikey Interrupt Status, offset: 0x104 */ - __IO uint32_t PWRCTRL; /**< Quiddikey Power Control Of RAM, offset: 0x108 */ - __IO uint32_t CFG; /**< Quiddikey Configuration Register, offset: 0x10C */ + __I uint32_t VERSION; /**< PUF Version Register, offset: 0xFC */ + __IO uint32_t INTEN; /**< PUF Interrupt Enable, offset: 0x100 */ + __IO uint32_t INTSTAT; /**< PUF Interrupt Status, offset: 0x104 */ + __IO uint32_t PWRCTRL; /**< PUF Power Control Of RAM, offset: 0x108 */ + __IO uint32_t CFG; /**< PUF Configuration Register, offset: 0x10C */ uint8_t RESERVED_6[240]; - __IO uint32_t KEYLOCK; /**< Quiddikey Key Manager Lock, offset: 0x200 */ - __IO uint32_t KEYENABLE; /**< Quiddikey Key Manager Enable, offset: 0x204 */ - __IO uint32_t KEYRESET; /**< Quiddikey Key Manager Reset, offset: 0x208 */ - __IO uint32_t IDXBLK; /**< Quiddikey Index Block Key Output, offset: 0x20C */ - __IO uint32_t IDXBLK_DP; /**< Quiddikey Index Block Key Output, offset: 0x210 */ - __IO uint32_t KEYMASK[2]; /**< Quiddikey Key Block 0 Mask Enable..Quiddikey Key Block 1 Mask Enable, array offset: 0x214, array step: 0x4 */ + __IO uint32_t KEYLOCK; /**< PUF Key Manager Lock, offset: 0x200 */ + __IO uint32_t KEYENABLE; /**< PUF Key Manager Enable, offset: 0x204 */ + __IO uint32_t KEYRESET; /**< PUF Key Manager Reset, offset: 0x208 */ + __IO uint32_t IDXBLK; /**< PUF Index Block Key Output, offset: 0x20C */ + __IO uint32_t IDXBLK_DP; /**< PUF Index Block Key Output, offset: 0x210 */ + __IO uint32_t KEYMASK[2]; /**< PUF Key Block 0 Mask Enable..PUF Key Block 1 Mask Enable, array offset: 0x214, array step: 0x4 */ uint8_t RESERVED_7[56]; __I uint32_t IDXBLK_STATUS; /**< PUF Index Block Setting Status Register, offset: 0x254 */ - __I uint32_t IDXBLK_SHIFT; /**< Quiddikey Key Manager Shift Status, offset: 0x258 */ + __I uint32_t IDXBLK_SHIFT; /**< PUF Key Manager Shift Status, offset: 0x258 */ } PUF_Type; /* ---------------------------------------------------------------------------- @@ -69023,57 +77724,64 @@ typedef struct { * @{ */ -/*! @name CTRL - Quiddikey Control Register */ +/*! @name CTRL - PUF Control Register */ /*! @{ */ + #define PUF_CTRL_ZEROIZE_MASK (0x1U) #define PUF_CTRL_ZEROIZE_SHIFT (0U) -/*! ZEROIZE - Begin Zeroize operation for Quiddikey and go to Error state - * 0b0..not in ZEROIZE status - * 0b1..in ZEROIZE status +/*! ZEROIZE - Begin Zeroize operation for PUF and go to Error state + * 0b0..No Zeroize operation in progress + * 0b1..Zeroize operation in progress */ #define PUF_CTRL_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ZEROIZE_SHIFT)) & PUF_CTRL_ZEROIZE_MASK) + #define PUF_CTRL_ENROLL_MASK (0x2U) #define PUF_CTRL_ENROLL_SHIFT (1U) /*! ENROLL - Begin Enroll operation - * 0b0..not in ENROLL status - * 0b1..in ENROLL status + * 0b0..No Enroll operation in progress + * 0b1..Enroll operation in progress */ #define PUF_CTRL_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ENROLL_SHIFT)) & PUF_CTRL_ENROLL_MASK) + #define PUF_CTRL_START_MASK (0x4U) #define PUF_CTRL_START_SHIFT (2U) /*! START - Begin Start operation - * 0b0..not in START status - * 0b1..in START status + * 0b0..No Start operation in progress + * 0b1..Start operation in progress */ #define PUF_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_START_SHIFT)) & PUF_CTRL_START_MASK) + #define PUF_CTRL_GENERATEKEY_MASK (0x8U) #define PUF_CTRL_GENERATEKEY_SHIFT (3U) /*! GENERATEKEY - Begin Set Intrinsic Key operation - * 0b0..not in GET_IK status - * 0b1..in GET_IK status + * 0b0..No Set Intrinsic Key operation in progress + * 0b1..Set Intrinsic Key operation in progress */ #define PUF_CTRL_GENERATEKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GENERATEKEY_SHIFT)) & PUF_CTRL_GENERATEKEY_MASK) + #define PUF_CTRL_SETKEY_MASK (0x10U) #define PUF_CTRL_SETKEY_SHIFT (4U) /*! SETKEY - Begin Set User Key operation - * 0b0..not in SET_UK status - * 0b1..in SET_UK status + * 0b0..No Set Key operation in progress + * 0b1..Set Key operation in progress */ #define PUF_CTRL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SETKEY_SHIFT)) & PUF_CTRL_SETKEY_MASK) + #define PUF_CTRL_GETKEY_MASK (0x40U) #define PUF_CTRL_GETKEY_SHIFT (6U) /*! GETKEY - Begin Get Key operation - * 0b0..not in GET_KEY status - * 0b1..in GET_KEY status + * 0b0..No Get Key operation in progress + * 0b1..Get Key operation in progress */ #define PUF_CTRL_GETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GETKEY_SHIFT)) & PUF_CTRL_GETKEY_MASK) /*! @} */ -/*! @name KEYINDEX - Quiddikey Key Index Register */ +/*! @name KEYINDEX - PUF Key Index Register */ /*! @{ */ + #define PUF_KEYINDEX_KEYIDX_MASK (0xFU) #define PUF_KEYINDEX_KEYIDX_SHIFT (0U) -/*! KEYIDX - puf_key_index +/*! KEYIDX - PUF Key Index * 0b0000..USE INDEX0 * 0b0001..USE INDEX1 * 0b0010..USE INDEX2 @@ -69094,8 +77802,9 @@ typedef struct { #define PUF_KEYINDEX_KEYIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINDEX_KEYIDX_SHIFT)) & PUF_KEYINDEX_KEYIDX_MASK) /*! @} */ -/*! @name KEYSIZE - Quiddikey Key Size Register */ +/*! @name KEYSIZE - PUF Key Size Register */ /*! @{ */ + #define PUF_KEYSIZE_KEYSIZE_MASK (0x3FU) #define PUF_KEYSIZE_KEYSIZE_SHIFT (0U) /*! KEYSIZE - PUF Key Size @@ -69167,8 +77876,9 @@ typedef struct { #define PUF_KEYSIZE_KEYSIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYSIZE_KEYSIZE_SHIFT)) & PUF_KEYSIZE_KEYSIZE_MASK) /*! @} */ -/*! @name STAT - Quiddikey Status Register */ +/*! @name STAT - PUF Status Register */ /*! @{ */ + #define PUF_STAT_BUSY_MASK (0x1U) #define PUF_STAT_BUSY_SHIFT (0U) /*! BUSY - puf_busy @@ -69176,6 +77886,7 @@ typedef struct { * 0b1..BUSY */ #define PUF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_BUSY_SHIFT)) & PUF_STAT_BUSY_MASK) + #define PUF_STAT_SUCCESS_MASK (0x2U) #define PUF_STAT_SUCCESS_SHIFT (1U) /*! SUCCESS - puf_ok @@ -69183,84 +77894,87 @@ typedef struct { * 0b1..Last operation was successful */ #define PUF_STAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_SUCCESS_SHIFT)) & PUF_STAT_SUCCESS_MASK) + #define PUF_STAT_ERROR_MASK (0x4U) #define PUF_STAT_ERROR_SHIFT (2U) /*! ERROR - puf_error - * 0b0..Quiddikey is not in the Error state - * 0b1..Quiddikey is in the Error state + * 0b0..PUF is not in the Error state + * 0b1..PUF is in the Error state */ #define PUF_STAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_ERROR_SHIFT)) & PUF_STAT_ERROR_MASK) + #define PUF_STAT_KEYINREQ_MASK (0x10U) #define PUF_STAT_KEYINREQ_SHIFT (4U) /*! KEYINREQ - KI_ir * 0b0..No request for next part of key - * 0b1..Request for next part of key + * 0b1..Request for next part of key in KEYINPUT register */ #define PUF_STAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYINREQ_SHIFT)) & PUF_STAT_KEYINREQ_MASK) + #define PUF_STAT_KEYOUTAVAIL_MASK (0x20U) #define PUF_STAT_KEYOUTAVAIL_SHIFT (5U) /*! KEYOUTAVAIL - KO_or * 0b0..Next part of key is not available - * 0b1..Next part of key is available + * 0b1..Next part of key is available in KEYOUTPUT register */ #define PUF_STAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYOUTAVAIL_SHIFT)) & PUF_STAT_KEYOUTAVAIL_MASK) + #define PUF_STAT_CODEINREQ_MASK (0x40U) #define PUF_STAT_CODEINREQ_SHIFT (6U) /*! CODEINREQ - CI_ir * 0b0..No request for next part of Activation Code/Key Code - * 0b1..request for next part of Activation Code/Key Code + * 0b1..request for next part of Activation Code/Key Code in CODEINPUT register */ #define PUF_STAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEINREQ_SHIFT)) & PUF_STAT_CODEINREQ_MASK) + #define PUF_STAT_CODEOUTAVAIL_MASK (0x80U) #define PUF_STAT_CODEOUTAVAIL_SHIFT (7U) /*! CODEOUTAVAIL - CO_or * 0b0..Next part of Activation Code/Key Code is not available - * 0b1..Next part of Activation Code/Key Code is available + * 0b1..Next part of Activation Code/Key Code is available in CODEOUTPUT register */ #define PUF_STAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEOUTAVAIL_SHIFT)) & PUF_STAT_CODEOUTAVAIL_MASK) /*! @} */ -/*! @name ALLOW - Quiddikey Allow Register */ +/*! @name ALLOW - PUF Allow Register */ /*! @{ */ + #define PUF_ALLOW_ALLOWENROLL_MASK (0x1U) #define PUF_ALLOW_ALLOWENROLL_SHIFT (0U) /*! ALLOWENROLL - Allow Enroll operation - * 0b0..do not allow to perform this operation - * 0b1..allow to perform this operation + * 0b0..Specified operation is not currently allowed + * 0b1..Specified operation is allowed */ #define PUF_ALLOW_ALLOWENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWENROLL_SHIFT)) & PUF_ALLOW_ALLOWENROLL_MASK) + #define PUF_ALLOW_ALLOWSTART_MASK (0x2U) #define PUF_ALLOW_ALLOWSTART_SHIFT (1U) /*! ALLOWSTART - Allow Start operation - * 0b0..do not allow to perform this operation - * 0b1..allow to perform this operation + * 0b0..Specified operation is not currently allowed + * 0b1..Specified operation is allowed */ #define PUF_ALLOW_ALLOWSTART(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSTART_SHIFT)) & PUF_ALLOW_ALLOWSTART_MASK) + #define PUF_ALLOW_ALLOWSETKEY_MASK (0x4U) #define PUF_ALLOW_ALLOWSETKEY_SHIFT (2U) /*! ALLOWSETKEY - Allow Set Key operations - * 0b0..do not allow to perform this operation - * 0b1..allow to perform this operation + * 0b0..Specified operation is not currently allowed + * 0b1..Specified operation is allowed */ #define PUF_ALLOW_ALLOWSETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSETKEY_SHIFT)) & PUF_ALLOW_ALLOWSETKEY_MASK) + #define PUF_ALLOW_ALLOWGETKEY_MASK (0x8U) #define PUF_ALLOW_ALLOWGETKEY_SHIFT (3U) /*! ALLOWGETKEY - Allow Get Key operation - * 0b0..do not allow to perform this operation - * 0b1..allow to perform this operation + * 0b0..Specified operation is not currently allowed + * 0b1..Specified operation is allowed */ #define PUF_ALLOW_ALLOWGETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWGETKEY_SHIFT)) & PUF_ALLOW_ALLOWGETKEY_MASK) -#define PUF_ALLOW_ALLOWBIST_MASK (0x80U) -#define PUF_ALLOW_ALLOWBIST_SHIFT (7U) -/*! ALLOWBIST - Allow BIST to Start - * 0b0..do not allow to perform this operation - * 0b1..allow to perform this operation - */ -#define PUF_ALLOW_ALLOWBIST(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWBIST_SHIFT)) & PUF_ALLOW_ALLOWBIST_MASK) /*! @} */ -/*! @name KEYINPUT - Quiddikey Key Input Register */ +/*! @name KEYINPUT - PUF Key Input Register */ /*! @{ */ + #define PUF_KEYINPUT_KEYIN_MASK (0xFFFFFFFFU) #define PUF_KEYINPUT_KEYIN_SHIFT (0U) /*! KEYIN - Key input data @@ -69268,8 +77982,9 @@ typedef struct { #define PUF_KEYINPUT_KEYIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINPUT_KEYIN_SHIFT)) & PUF_KEYINPUT_KEYIN_MASK) /*! @} */ -/*! @name CODEINPUT - Quiddikey Code Input Register */ +/*! @name CODEINPUT - PUF Code Input Register */ /*! @{ */ + #define PUF_CODEINPUT_CODEIN_MASK (0xFFFFFFFFU) #define PUF_CODEINPUT_CODEIN_SHIFT (0U) /*! CODEIN - AC/KC input data @@ -69277,8 +77992,9 @@ typedef struct { #define PUF_CODEINPUT_CODEIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEINPUT_CODEIN_SHIFT)) & PUF_CODEINPUT_CODEIN_MASK) /*! @} */ -/*! @name CODEOUTPUT - Quiddikey Code Output Register */ +/*! @name CODEOUTPUT - PUF Code Output Register */ /*! @{ */ + #define PUF_CODEOUTPUT_CODEOUT_MASK (0xFFFFFFFFU) #define PUF_CODEOUTPUT_CODEOUT_SHIFT (0U) /*! CODEOUT - AC/KC output data @@ -69286,8 +78002,9 @@ typedef struct { #define PUF_CODEOUTPUT_CODEOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEOUTPUT_CODEOUT_SHIFT)) & PUF_CODEOUTPUT_CODEOUT_MASK) /*! @} */ -/*! @name KEYOUTINDEX - Quiddikey Key Output Index Register */ +/*! @name KEYOUTINDEX - PUF Key Output Index Register */ /*! @{ */ + #define PUF_KEYOUTINDEX_KEYOUTIDX_MASK (0xFFFFFFFFU) #define PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT (0U) /*! KEYOUTIDX - Output Key index @@ -69295,17 +78012,19 @@ typedef struct { #define PUF_KEYOUTINDEX_KEYOUTIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT)) & PUF_KEYOUTINDEX_KEYOUTIDX_MASK) /*! @} */ -/*! @name KEYOUTPUT - Quiddikey Key Output Register */ +/*! @name KEYOUTPUT - PUF Key Output Register */ /*! @{ */ + #define PUF_KEYOUTPUT_KEYOUT_MASK (0xFFFFFFFFU) #define PUF_KEYOUTPUT_KEYOUT_SHIFT (0U) -/*! KEYOUT - Key output data +/*! KEYOUT - Key output data from a Get Key operation */ #define PUF_KEYOUTPUT_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTPUT_KEYOUT_SHIFT)) & PUF_KEYOUTPUT_KEYOUT_MASK) /*! @} */ -/*! @name IFSTAT - Quiddikey Interface Status Register */ +/*! @name IFSTAT - PUF Interface Status Register */ /*! @{ */ + #define PUF_IFSTAT_ERROR_MASK (0x1U) #define PUF_IFSTAT_ERROR_SHIFT (0U) /*! ERROR - APB error has occurred @@ -69315,70 +78034,79 @@ typedef struct { #define PUF_IFSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IFSTAT_ERROR_SHIFT)) & PUF_IFSTAT_ERROR_MASK) /*! @} */ -/*! @name VERSION - Quiddikey Version Register */ +/*! @name VERSION - PUF Version Register */ /*! @{ */ + #define PUF_VERSION_VERSION_MASK (0xFFFFFFFFU) #define PUF_VERSION_VERSION_SHIFT (0U) -/*! VERSION - Version of Quiddikey +/*! VERSION - Version of PUF */ #define PUF_VERSION_VERSION(x) (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_VERSION_SHIFT)) & PUF_VERSION_VERSION_MASK) /*! @} */ -/*! @name INTEN - Quiddikey Interrupt Enable */ +/*! @name INTEN - PUF Interrupt Enable */ /*! @{ */ + #define PUF_INTEN_READYEN_MASK (0x1U) #define PUF_INTEN_READYEN_SHIFT (0U) -/*! READYEN - PUF_FINISH Interrupt Enable - * 0b0..Disable interrupt for PUF finish - * 0b1..Enable interrupt for PUF finish +/*! READYEN - PUF Ready Interrupt Enable + * 0b0..PUF ready interrupt disabled + * 0b1..PUF ready interrupt enabled */ #define PUF_INTEN_READYEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_READYEN_SHIFT)) & PUF_INTEN_READYEN_MASK) -#define PUF_INTEN_SUCCESEN_MASK (0x2U) -#define PUF_INTEN_SUCCESEN_SHIFT (1U) -/*! SUCCESEN - PUF_OK Interrupt Enable - * 0b0..Disable interrupt for PUF successful - * 0b1..Enable interrupt for PUF successful + +#define PUF_INTEN_SUCCESSEN_MASK (0x2U) +#define PUF_INTEN_SUCCESSEN_SHIFT (1U) +/*! SUCCESSEN - PUF_OK Interrupt Enable + * 0b0..PUF successful interrupt disabled + * 0b1..PUF successful interrupt enabled */ -#define PUF_INTEN_SUCCESEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_SUCCESEN_SHIFT)) & PUF_INTEN_SUCCESEN_MASK) +#define PUF_INTEN_SUCCESSEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_SUCCESSEN_SHIFT)) & PUF_INTEN_SUCCESSEN_MASK) + #define PUF_INTEN_ERROREN_MASK (0x4U) #define PUF_INTEN_ERROREN_SHIFT (2U) /*! ERROREN - PUF Error Interrupt Enable - * 0b0..Disable interrupt for PUF error state - * 0b1..Enable interrupt for PUF error state + * 0b0..PUF error interrupt disabled + * 0b1..PUF error interrupt enabled */ #define PUF_INTEN_ERROREN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_ERROREN_SHIFT)) & PUF_INTEN_ERROREN_MASK) + #define PUF_INTEN_KEYINREQEN_MASK (0x10U) #define PUF_INTEN_KEYINREQEN_SHIFT (4U) /*! KEYINREQEN - PUF Key Input Register Interrupt Enable - * 0b0..Disable interrupt for reques next part of key - * 0b1..Enable interrupt for reques next part of key + * 0b0..Key interrupt request disabled + * 0b1..Key interrupt request enabled */ #define PUF_INTEN_KEYINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYINREQEN_SHIFT)) & PUF_INTEN_KEYINREQEN_MASK) + #define PUF_INTEN_KEYOUTAVAILEN_MASK (0x20U) #define PUF_INTEN_KEYOUTAVAILEN_SHIFT (5U) /*! KEYOUTAVAILEN - PUF Key Output Register Interrupt Enable - * 0b0..Disable interrupt for available next part of key - * 0b1..Enable interrupt for available next part of key + * 0b0..Key available interrupt disabled + * 0b1..Key available interrupt enabled */ #define PUF_INTEN_KEYOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYOUTAVAILEN_SHIFT)) & PUF_INTEN_KEYOUTAVAILEN_MASK) + #define PUF_INTEN_CODEINREQEN_MASK (0x40U) #define PUF_INTEN_CODEINREQEN_SHIFT (6U) /*! CODEINREQEN - PUF Code Input Register Interrupt Enable - * 0b0..Disable interrupt request for next part of AC/KC - * 0b1..Enable interrupt request for next part of AC/KC + * 0b0..AC/KC interrupt request disabled + * 0b1..AC/KC interrupt request enabled */ #define PUF_INTEN_CODEINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEINREQEN_SHIFT)) & PUF_INTEN_CODEINREQEN_MASK) + #define PUF_INTEN_CODEOUTAVAILEN_MASK (0x80U) #define PUF_INTEN_CODEOUTAVAILEN_SHIFT (7U) /*! CODEOUTAVAILEN - PUF Code Output Register Interrupt Enable - * 0b0..Disable interrupt for available next part of AC/KC - * 0b1..Enable interrupt for available next part of AC/KC + * 0b0..AC/KC available interrupt disabled + * 0b1..AC/KC available interrupt enabled */ #define PUF_INTEN_CODEOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEOUTAVAILEN_SHIFT)) & PUF_INTEN_CODEOUTAVAILEN_MASK) /*! @} */ -/*! @name INTSTAT - Quiddikey Interrupt Status */ +/*! @name INTSTAT - PUF Interrupt Status */ /*! @{ */ + #define PUF_INTSTAT_READY_MASK (0x1U) #define PUF_INTSTAT_READY_SHIFT (0U) /*! READY - PUF_FINISH Interrupt Status @@ -69386,6 +78114,7 @@ typedef struct { * 0b1..Indicates that last operation is finished */ #define PUF_INTSTAT_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_READY_SHIFT)) & PUF_INTSTAT_READY_MASK) + #define PUF_INTSTAT_SUCCESS_MASK (0x2U) #define PUF_INTSTAT_SUCCESS_SHIFT (1U) /*! SUCCESS - PUF_OK Interrupt Status @@ -69393,13 +78122,15 @@ typedef struct { * 0b1..Indicates that last operation was successful */ #define PUF_INTSTAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_SUCCESS_SHIFT)) & PUF_INTSTAT_SUCCESS_MASK) + #define PUF_INTSTAT_ERROR_MASK (0x4U) #define PUF_INTSTAT_ERROR_SHIFT (2U) /*! ERROR - PUF_ERROR Interrupt Status - * 0b0..Quiddikey is not in the Error state and operations can be performed - * 0b1..Quiddikey is in the Error state and no operations can be performed + * 0b0..PUF is not in the Error state and operations can be performed + * 0b1..PUF is in the Error state and no operations can be performed */ #define PUF_INTSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_ERROR_SHIFT)) & PUF_INTSTAT_ERROR_MASK) + #define PUF_INTSTAT_KEYINREQ_MASK (0x10U) #define PUF_INTSTAT_KEYINREQ_SHIFT (4U) /*! KEYINREQ - PUF Key Input Register Interrupt Status @@ -69407,6 +78138,7 @@ typedef struct { * 0b1..Request for next part of key */ #define PUF_INTSTAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYINREQ_SHIFT)) & PUF_INTSTAT_KEYINREQ_MASK) + #define PUF_INTSTAT_KEYOUTAVAIL_MASK (0x20U) #define PUF_INTSTAT_KEYOUTAVAIL_SHIFT (5U) /*! KEYOUTAVAIL - PUF Key Output Register Interrupt Status @@ -69414,6 +78146,7 @@ typedef struct { * 0b1..Next part of key is available */ #define PUF_INTSTAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYOUTAVAIL_SHIFT)) & PUF_INTSTAT_KEYOUTAVAIL_MASK) + #define PUF_INTSTAT_CODEINREQ_MASK (0x40U) #define PUF_INTSTAT_CODEINREQ_SHIFT (6U) /*! CODEINREQ - PUF Code Input Register Interrupt Status @@ -69421,6 +78154,7 @@ typedef struct { * 0b1..Request for next part of AC/KC */ #define PUF_INTSTAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEINREQ_SHIFT)) & PUF_INTSTAT_CODEINREQ_MASK) + #define PUF_INTSTAT_CODEOUTAVAIL_MASK (0x80U) #define PUF_INTSTAT_CODEOUTAVAIL_SHIFT (7U) /*! CODEOUTAVAIL - PUF Code Output Register Interrupt Status @@ -69430,61 +78164,43 @@ typedef struct { #define PUF_INTSTAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEOUTAVAIL_SHIFT)) & PUF_INTSTAT_CODEOUTAVAIL_MASK) /*! @} */ -/*! @name PWRCTRL - Quiddikey Power Control Of RAM */ +/*! @name PWRCTRL - PUF Power Control Of RAM */ /*! @{ */ + #define PUF_PWRCTRL_RAM_ON_MASK (0x1U) #define PUF_PWRCTRL_RAM_ON_SHIFT (0U) -/*! RAM_ON - puf_ram_on - * 0b0..Leave the PUF RAM in sleep mode - * 0b1..Wake the PUF RAM +/*! RAM_ON - PUF RAM on + * 0b0..PUF RAM is in sleep mode (PUF operation disabled) + * 0b1..PUF RAM is awake (normal PUF operation enabled) */ #define PUF_PWRCTRL_RAM_ON(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAM_ON_SHIFT)) & PUF_PWRCTRL_RAM_ON_MASK) + #define PUF_PWRCTRL_CK_DIS_MASK (0x4U) #define PUF_PWRCTRL_CK_DIS_SHIFT (2U) -/*! CK_DIS - Disable Quiddikey - * 0b1..Disable Quiddikey - * 0b0..Enable Quiddikey +/*! CK_DIS - Clock disable + * 0b0..PUF RAM is clocked (normal PUF operation enabled) + * 0b1..PUF RAM clock is gated/disabled (PUF operation disabled) */ #define PUF_PWRCTRL_CK_DIS(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_CK_DIS_SHIFT)) & PUF_PWRCTRL_CK_DIS_MASK) + #define PUF_PWRCTRL_RAM_INITN_MASK (0x8U) #define PUF_PWRCTRL_RAM_INITN_SHIFT (3U) -/*! RAM_INITN - puf_ram_initn - * 0b0..ACTIVE - * 0b1..NOACTIVE +/*! RAM_INITN - RAM initialization + * 0b0..Reset the PUF RAM (PUF operation disabled) + * 0b1..Do not reset the PUF RAM (normal PUF operation enabled) */ #define PUF_PWRCTRL_RAM_INITN(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAM_INITN_SHIFT)) & PUF_PWRCTRL_RAM_INITN_MASK) -#define PUF_PWRCTRL_RAM_PSW_LARGE_MA_MASK (0x10U) -#define PUF_PWRCTRL_RAM_PSW_LARGE_MA_SHIFT (4U) -/*! RAM_PSW_LARGE_MA - puf_ram_psw_large_ma - * 0b0..NOACTIVE - * 0b1..ACTIVE - */ -#define PUF_PWRCTRL_RAM_PSW_LARGE_MA(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAM_PSW_LARGE_MA_SHIFT)) & PUF_PWRCTRL_RAM_PSW_LARGE_MA_MASK) -#define PUF_PWRCTRL_RAM_PSW_LARGE_MP_MASK (0x20U) -#define PUF_PWRCTRL_RAM_PSW_LARGE_MP_SHIFT (5U) -/*! RAM_PSW_LARGE_MP - puf_ram_psw_large_mp - * 0b0..NOACTIVE - * 0b1..ACTIVE - */ -#define PUF_PWRCTRL_RAM_PSW_LARGE_MP(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAM_PSW_LARGE_MP_SHIFT)) & PUF_PWRCTRL_RAM_PSW_LARGE_MP_MASK) -#define PUF_PWRCTRL_RAM_PSW_SMALL_MA_MASK (0x40U) -#define PUF_PWRCTRL_RAM_PSW_SMALL_MA_SHIFT (6U) -/*! RAM_PSW_SMALL_MA - puf_ram_psw_small_ma - * 0b0..NOACTIVE - * 0b1..ACTIVE - */ -#define PUF_PWRCTRL_RAM_PSW_SMALL_MA(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAM_PSW_SMALL_MA_SHIFT)) & PUF_PWRCTRL_RAM_PSW_SMALL_MA_MASK) -#define PUF_PWRCTRL_RAM_PSW_SMALL_MP_MASK (0x80U) -#define PUF_PWRCTRL_RAM_PSW_SMALL_MP_SHIFT (7U) -/*! RAM_PSW_SMALL_MP - puf_ram_psw_small_mp - * 0b0..NOACTIVE - * 0b1..ACTIVE - */ -#define PUF_PWRCTRL_RAM_PSW_SMALL_MP(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAM_PSW_SMALL_MP_SHIFT)) & PUF_PWRCTRL_RAM_PSW_SMALL_MP_MASK) -/*! @} */ - -/*! @name CFG - Quiddikey Configuration Register */ + +#define PUF_PWRCTRL_RAM_PSW_MASK (0xF0U) +#define PUF_PWRCTRL_RAM_PSW_SHIFT (4U) +/*! RAM_PSW - PUF RAM power switches + */ +#define PUF_PWRCTRL_RAM_PSW(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAM_PSW_SHIFT)) & PUF_PWRCTRL_RAM_PSW_MASK) +/*! @} */ + +/*! @name CFG - PUF Configuration Register */ /*! @{ */ + #define PUF_CFG_PUF_BLOCK_SET_KEY_MASK (0x1U) #define PUF_CFG_PUF_BLOCK_SET_KEY_SHIFT (0U) /*! PUF_BLOCK_SET_KEY - PUF Block Set Key Disable @@ -69492,6 +78208,7 @@ typedef struct { * 0b1..Disable the Set Key state */ #define PUF_CFG_PUF_BLOCK_SET_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_PUF_BLOCK_SET_KEY_SHIFT)) & PUF_CFG_PUF_BLOCK_SET_KEY_MASK) + #define PUF_CFG_PUF_BLOCK_ENROLL_MASK (0x2U) #define PUF_CFG_PUF_BLOCK_ENROLL_SHIFT (1U) /*! PUF_BLOCK_ENROLL - PUF Block Enroll Disable @@ -69501,8 +78218,9 @@ typedef struct { #define PUF_CFG_PUF_BLOCK_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_PUF_BLOCK_ENROLL_SHIFT)) & PUF_CFG_PUF_BLOCK_ENROLL_MASK) /*! @} */ -/*! @name KEYLOCK - Quiddikey Key Manager Lock */ +/*! @name KEYLOCK - PUF Key Manager Lock */ /*! @{ */ + #define PUF_KEYLOCK_LOCK0_MASK (0x3U) #define PUF_KEYLOCK_LOCK0_SHIFT (0U) /*! LOCK0 - Lock Block 0 @@ -69512,6 +78230,7 @@ typedef struct { * 0b00..SNVS Key block locked */ #define PUF_KEYLOCK_LOCK0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_LOCK0_SHIFT)) & PUF_KEYLOCK_LOCK0_MASK) + #define PUF_KEYLOCK_LOCK1_MASK (0xCU) #define PUF_KEYLOCK_LOCK1_SHIFT (2U) /*! LOCK1 - Lock Block 1 @@ -69523,8 +78242,9 @@ typedef struct { #define PUF_KEYLOCK_LOCK1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_LOCK1_SHIFT)) & PUF_KEYLOCK_LOCK1_MASK) /*! @} */ -/*! @name KEYENABLE - Quiddikey Key Manager Enable */ +/*! @name KEYENABLE - PUF Key Manager Enable */ /*! @{ */ + #define PUF_KEYENABLE_ENABLE0_MASK (0x3U) #define PUF_KEYENABLE_ENABLE0_SHIFT (0U) /*! ENABLE0 - Enable Block 0 @@ -69534,6 +78254,7 @@ typedef struct { * 0b00..Key block 0 disabled */ #define PUF_KEYENABLE_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_ENABLE0_SHIFT)) & PUF_KEYENABLE_ENABLE0_MASK) + #define PUF_KEYENABLE_ENABLE1_MASK (0xCU) #define PUF_KEYENABLE_ENABLE1_SHIFT (2U) /*! ENABLE1 - Enable Block 1 @@ -69545,8 +78266,9 @@ typedef struct { #define PUF_KEYENABLE_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_ENABLE1_SHIFT)) & PUF_KEYENABLE_ENABLE1_MASK) /*! @} */ -/*! @name KEYRESET - Quiddikey Key Manager Reset */ +/*! @name KEYRESET - PUF Key Manager Reset */ /*! @{ */ + #define PUF_KEYRESET_RESET0_MASK (0x3U) #define PUF_KEYRESET_RESET0_SHIFT (0U) /*! RESET0 - Reset Block 0 @@ -69556,6 +78278,7 @@ typedef struct { * 0b00..Do not reset key block 0 */ #define PUF_KEYRESET_RESET0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_RESET0_SHIFT)) & PUF_KEYRESET_RESET0_MASK) + #define PUF_KEYRESET_RESET1_MASK (0xCU) #define PUF_KEYRESET_RESET1_SHIFT (2U) /*! RESET1 - Reset Block 1 @@ -69567,83 +78290,99 @@ typedef struct { #define PUF_KEYRESET_RESET1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_RESET1_SHIFT)) & PUF_KEYRESET_RESET1_MASK) /*! @} */ -/*! @name IDXBLK - Quiddikey Index Block Key Output */ +/*! @name IDXBLK - PUF Index Block Key Output */ /*! @{ */ + #define PUF_IDXBLK_IDXBLK0_MASK (0x3U) #define PUF_IDXBLK_IDXBLK0_SHIFT (0U) /*! IDXBLK0 - idxblk0 */ #define PUF_IDXBLK_IDXBLK0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK0_SHIFT)) & PUF_IDXBLK_IDXBLK0_MASK) + #define PUF_IDXBLK_IDXBLK1_MASK (0xCU) #define PUF_IDXBLK_IDXBLK1_SHIFT (2U) /*! IDXBLK1 - idxblk1 */ #define PUF_IDXBLK_IDXBLK1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK1_SHIFT)) & PUF_IDXBLK_IDXBLK1_MASK) + #define PUF_IDXBLK_IDXBLK2_MASK (0x30U) #define PUF_IDXBLK_IDXBLK2_SHIFT (4U) /*! IDXBLK2 - idxblk2 */ #define PUF_IDXBLK_IDXBLK2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK2_SHIFT)) & PUF_IDXBLK_IDXBLK2_MASK) + #define PUF_IDXBLK_IDXBLK3_MASK (0xC0U) #define PUF_IDXBLK_IDXBLK3_SHIFT (6U) /*! IDXBLK3 - idxblk3 */ #define PUF_IDXBLK_IDXBLK3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK3_SHIFT)) & PUF_IDXBLK_IDXBLK3_MASK) + #define PUF_IDXBLK_IDXBLK4_MASK (0x300U) #define PUF_IDXBLK_IDXBLK4_SHIFT (8U) /*! IDXBLK4 - idxblk4 */ #define PUF_IDXBLK_IDXBLK4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK4_SHIFT)) & PUF_IDXBLK_IDXBLK4_MASK) + #define PUF_IDXBLK_IDXBLK5_MASK (0xC00U) #define PUF_IDXBLK_IDXBLK5_SHIFT (10U) /*! IDXBLK5 - idxblk5 */ #define PUF_IDXBLK_IDXBLK5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK5_SHIFT)) & PUF_IDXBLK_IDXBLK5_MASK) + #define PUF_IDXBLK_IDXBLK6_MASK (0x3000U) #define PUF_IDXBLK_IDXBLK6_SHIFT (12U) /*! IDXBLK6 - idxblk6 */ #define PUF_IDXBLK_IDXBLK6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK6_SHIFT)) & PUF_IDXBLK_IDXBLK6_MASK) + #define PUF_IDXBLK_IDXBLK7_MASK (0xC000U) #define PUF_IDXBLK_IDXBLK7_SHIFT (14U) /*! IDXBLK7 - idxblk7 */ #define PUF_IDXBLK_IDXBLK7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK7_SHIFT)) & PUF_IDXBLK_IDXBLK7_MASK) + #define PUF_IDXBLK_IDXBLK8_MASK (0x30000U) #define PUF_IDXBLK_IDXBLK8_SHIFT (16U) /*! IDXBLK8 - idxblk8 */ #define PUF_IDXBLK_IDXBLK8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK8_SHIFT)) & PUF_IDXBLK_IDXBLK8_MASK) + #define PUF_IDXBLK_IDXBLK9_MASK (0xC0000U) #define PUF_IDXBLK_IDXBLK9_SHIFT (18U) /*! IDXBLK9 - idxblk9 */ #define PUF_IDXBLK_IDXBLK9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK9_SHIFT)) & PUF_IDXBLK_IDXBLK9_MASK) + #define PUF_IDXBLK_IDXBLK10_MASK (0x300000U) #define PUF_IDXBLK_IDXBLK10_SHIFT (20U) /*! IDXBLK10 - idxblk10 */ #define PUF_IDXBLK_IDXBLK10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK10_SHIFT)) & PUF_IDXBLK_IDXBLK10_MASK) + #define PUF_IDXBLK_IDXBLK11_MASK (0xC00000U) #define PUF_IDXBLK_IDXBLK11_SHIFT (22U) /*! IDXBLK11 - idxblk11 */ #define PUF_IDXBLK_IDXBLK11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK11_SHIFT)) & PUF_IDXBLK_IDXBLK11_MASK) + #define PUF_IDXBLK_IDXBLK12_MASK (0x3000000U) #define PUF_IDXBLK_IDXBLK12_SHIFT (24U) /*! IDXBLK12 - idxblk12 */ #define PUF_IDXBLK_IDXBLK12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK12_SHIFT)) & PUF_IDXBLK_IDXBLK12_MASK) + #define PUF_IDXBLK_IDXBLK13_MASK (0xC000000U) #define PUF_IDXBLK_IDXBLK13_SHIFT (26U) /*! IDXBLK13 - idxblk13 */ #define PUF_IDXBLK_IDXBLK13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK13_SHIFT)) & PUF_IDXBLK_IDXBLK13_MASK) + #define PUF_IDXBLK_IDXBLK14_MASK (0x30000000U) #define PUF_IDXBLK_IDXBLK14_SHIFT (28U) /*! IDXBLK14 - idxblk14 */ #define PUF_IDXBLK_IDXBLK14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK14_SHIFT)) & PUF_IDXBLK_IDXBLK14_MASK) + #define PUF_IDXBLK_IDXBLK15_MASK (0xC0000000U) #define PUF_IDXBLK_IDXBLK15_SHIFT (30U) /*! IDXBLK15 - idxblk15 @@ -69651,83 +78390,99 @@ typedef struct { #define PUF_IDXBLK_IDXBLK15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK15_SHIFT)) & PUF_IDXBLK_IDXBLK15_MASK) /*! @} */ -/*! @name IDXBLK_DP - Quiddikey Index Block Key Output */ +/*! @name IDXBLK_DP - PUF Index Block Key Output */ /*! @{ */ + #define PUF_IDXBLK_DP_IDXBLK_DP0_MASK (0x3U) #define PUF_IDXBLK_DP_IDXBLK_DP0_SHIFT (0U) /*! IDXBLK_DP0 - idxblk_dp0 */ #define PUF_IDXBLK_DP_IDXBLK_DP0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP0_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP0_MASK) + #define PUF_IDXBLK_DP_IDXBLK_DP1_MASK (0xCU) #define PUF_IDXBLK_DP_IDXBLK_DP1_SHIFT (2U) /*! IDXBLK_DP1 - idxblk_dp1 */ #define PUF_IDXBLK_DP_IDXBLK_DP1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP1_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP1_MASK) + #define PUF_IDXBLK_DP_IDXBLK_DP2_MASK (0x30U) #define PUF_IDXBLK_DP_IDXBLK_DP2_SHIFT (4U) /*! IDXBLK_DP2 - idxblk_dp2 */ #define PUF_IDXBLK_DP_IDXBLK_DP2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP2_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP2_MASK) + #define PUF_IDXBLK_DP_IDXBLK_DP3_MASK (0xC0U) #define PUF_IDXBLK_DP_IDXBLK_DP3_SHIFT (6U) /*! IDXBLK_DP3 - idxblk_dp3 */ #define PUF_IDXBLK_DP_IDXBLK_DP3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP3_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP3_MASK) + #define PUF_IDXBLK_DP_IDXBLK_DP4_MASK (0x300U) #define PUF_IDXBLK_DP_IDXBLK_DP4_SHIFT (8U) /*! IDXBLK_DP4 - idxblk_dp4 */ #define PUF_IDXBLK_DP_IDXBLK_DP4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP4_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP4_MASK) + #define PUF_IDXBLK_DP_IDXBLK_DP5_MASK (0xC00U) #define PUF_IDXBLK_DP_IDXBLK_DP5_SHIFT (10U) /*! IDXBLK_DP5 - idxblk_dp5 */ #define PUF_IDXBLK_DP_IDXBLK_DP5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP5_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP5_MASK) + #define PUF_IDXBLK_DP_IDXBLK_DP6_MASK (0x3000U) #define PUF_IDXBLK_DP_IDXBLK_DP6_SHIFT (12U) /*! IDXBLK_DP6 - idxblk_dp6 */ #define PUF_IDXBLK_DP_IDXBLK_DP6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP6_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP6_MASK) + #define PUF_IDXBLK_DP_IDXBLK_DP7_MASK (0xC000U) #define PUF_IDXBLK_DP_IDXBLK_DP7_SHIFT (14U) /*! IDXBLK_DP7 - idxblk_dp7 */ #define PUF_IDXBLK_DP_IDXBLK_DP7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP7_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP7_MASK) + #define PUF_IDXBLK_DP_IDXBLK_DP8_MASK (0x30000U) #define PUF_IDXBLK_DP_IDXBLK_DP8_SHIFT (16U) /*! IDXBLK_DP8 - idxblk_dp8 */ #define PUF_IDXBLK_DP_IDXBLK_DP8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP8_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP8_MASK) + #define PUF_IDXBLK_DP_IDXBLK_DP9_MASK (0xC0000U) #define PUF_IDXBLK_DP_IDXBLK_DP9_SHIFT (18U) /*! IDXBLK_DP9 - idxblk_dp9 */ #define PUF_IDXBLK_DP_IDXBLK_DP9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP9_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP9_MASK) + #define PUF_IDXBLK_DP_IDXBLK_DP10_MASK (0x300000U) #define PUF_IDXBLK_DP_IDXBLK_DP10_SHIFT (20U) /*! IDXBLK_DP10 - idxblk_dp10 */ #define PUF_IDXBLK_DP_IDXBLK_DP10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP10_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP10_MASK) + #define PUF_IDXBLK_DP_IDXBLK_DP11_MASK (0xC00000U) #define PUF_IDXBLK_DP_IDXBLK_DP11_SHIFT (22U) /*! IDXBLK_DP11 - idxblk_dp11 */ #define PUF_IDXBLK_DP_IDXBLK_DP11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP11_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP11_MASK) + #define PUF_IDXBLK_DP_IDXBLK_DP12_MASK (0x3000000U) #define PUF_IDXBLK_DP_IDXBLK_DP12_SHIFT (24U) /*! IDXBLK_DP12 - idxblk_dp12 */ #define PUF_IDXBLK_DP_IDXBLK_DP12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP12_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP12_MASK) + #define PUF_IDXBLK_DP_IDXBLK_DP13_MASK (0xC000000U) #define PUF_IDXBLK_DP_IDXBLK_DP13_SHIFT (26U) /*! IDXBLK_DP13 - idxblk_dp13 */ #define PUF_IDXBLK_DP_IDXBLK_DP13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP13_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP13_MASK) + #define PUF_IDXBLK_DP_IDXBLK_DP14_MASK (0x30000000U) #define PUF_IDXBLK_DP_IDXBLK_DP14_SHIFT (28U) /*! IDXBLK_DP14 - idxblk_dp14 */ #define PUF_IDXBLK_DP_IDXBLK_DP14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP14_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP14_MASK) + #define PUF_IDXBLK_DP_IDXBLK_DP15_MASK (0xC0000000U) #define PUF_IDXBLK_DP_IDXBLK_DP15_SHIFT (30U) /*! IDXBLK_DP15 - idxblk_dp15 @@ -69735,8 +78490,9 @@ typedef struct { #define PUF_IDXBLK_DP_IDXBLK_DP15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP15_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP15_MASK) /*! @} */ -/*! @name KEYMASK - Quiddikey Key Block 0 Mask Enable..Quiddikey Key Block 1 Mask Enable */ +/*! @name KEYMASK - PUF Key Block 0 Mask Enable..PUF Key Block 1 Mask Enable */ /*! @{ */ + #define PUF_KEYMASK_KEYMASK_MASK (0xFFFFFFFFU) #define PUF_KEYMASK_KEYMASK_SHIFT (0U) /*! KEYMASK - KEYMASK1 @@ -69749,81 +78505,97 @@ typedef struct { /*! @name IDXBLK_STATUS - PUF Index Block Setting Status Register */ /*! @{ */ + #define PUF_IDXBLK_STATUS_IDXBLK_STATUS0_MASK (0x3U) #define PUF_IDXBLK_STATUS_IDXBLK_STATUS0_SHIFT (0U) /*! IDXBLK_STATUS0 - idxblk_status0 */ #define PUF_IDXBLK_STATUS_IDXBLK_STATUS0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS0_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS0_MASK) + #define PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK (0xCU) #define PUF_IDXBLK_STATUS_IDXBLK_STATUS1_SHIFT (2U) /*! IDXBLK_STATUS1 - idxblk_status1 */ #define PUF_IDXBLK_STATUS_IDXBLK_STATUS1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS1_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK) + #define PUF_IDXBLK_STATUS_IDXBLK_STATUS2_MASK (0x30U) #define PUF_IDXBLK_STATUS_IDXBLK_STATUS2_SHIFT (4U) /*! IDXBLK_STATUS2 - idxblk_status2 */ #define PUF_IDXBLK_STATUS_IDXBLK_STATUS2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS2_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS2_MASK) + #define PUF_IDXBLK_STATUS_IDXBLK_STATUS3_MASK (0xC0U) #define PUF_IDXBLK_STATUS_IDXBLK_STATUS3_SHIFT (6U) /*! IDXBLK_STATUS3 - idxblk_status3 */ #define PUF_IDXBLK_STATUS_IDXBLK_STATUS3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS3_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS3_MASK) + #define PUF_IDXBLK_STATUS_IDXBLK_STATUS4_MASK (0x300U) #define PUF_IDXBLK_STATUS_IDXBLK_STATUS4_SHIFT (8U) /*! IDXBLK_STATUS4 - idxblk_status4 */ #define PUF_IDXBLK_STATUS_IDXBLK_STATUS4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS4_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS4_MASK) + #define PUF_IDXBLK_STATUS_IDXBLK_STATUS5_MASK (0xC00U) #define PUF_IDXBLK_STATUS_IDXBLK_STATUS5_SHIFT (10U) /*! IDXBLK_STATUS5 - idxblk_status5 */ #define PUF_IDXBLK_STATUS_IDXBLK_STATUS5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS5_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS5_MASK) + #define PUF_IDXBLK_STATUS_IDXBLK_STATUS6_MASK (0x3000U) #define PUF_IDXBLK_STATUS_IDXBLK_STATUS6_SHIFT (12U) /*! IDXBLK_STATUS6 - idxblk_status6 */ #define PUF_IDXBLK_STATUS_IDXBLK_STATUS6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS6_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS6_MASK) + #define PUF_IDXBLK_STATUS_IDXBLK_STATUS7_MASK (0xC000U) #define PUF_IDXBLK_STATUS_IDXBLK_STATUS7_SHIFT (14U) /*! IDXBLK_STATUS7 - idxblk_status7 */ #define PUF_IDXBLK_STATUS_IDXBLK_STATUS7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS7_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS7_MASK) + #define PUF_IDXBLK_STATUS_IDXBLK_STATUS8_MASK (0x30000U) #define PUF_IDXBLK_STATUS_IDXBLK_STATUS8_SHIFT (16U) /*! IDXBLK_STATUS8 - idxblk_status8 */ #define PUF_IDXBLK_STATUS_IDXBLK_STATUS8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS8_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS8_MASK) + #define PUF_IDXBLK_STATUS_IDXBLK_STATUS9_MASK (0xC0000U) #define PUF_IDXBLK_STATUS_IDXBLK_STATUS9_SHIFT (18U) /*! IDXBLK_STATUS9 - idxblk_status9 */ #define PUF_IDXBLK_STATUS_IDXBLK_STATUS9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS9_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS9_MASK) + #define PUF_IDXBLK_STATUS_IDXBLK_STATUS10_MASK (0x300000U) #define PUF_IDXBLK_STATUS_IDXBLK_STATUS10_SHIFT (20U) /*! IDXBLK_STATUS10 - idxblk_status10 */ #define PUF_IDXBLK_STATUS_IDXBLK_STATUS10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS10_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS10_MASK) + #define PUF_IDXBLK_STATUS_IDXBLK_STATUS11_MASK (0xC00000U) #define PUF_IDXBLK_STATUS_IDXBLK_STATUS11_SHIFT (22U) /*! IDXBLK_STATUS11 - idxblk_status11 */ #define PUF_IDXBLK_STATUS_IDXBLK_STATUS11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS11_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS11_MASK) + #define PUF_IDXBLK_STATUS_IDXBLK_STATUS12_MASK (0x3000000U) #define PUF_IDXBLK_STATUS_IDXBLK_STATUS12_SHIFT (24U) /*! IDXBLK_STATUS12 - idxblk_status12 */ #define PUF_IDXBLK_STATUS_IDXBLK_STATUS12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS12_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS12_MASK) + #define PUF_IDXBLK_STATUS_IDXBLK_STATUS13_MASK (0xC000000U) #define PUF_IDXBLK_STATUS_IDXBLK_STATUS13_SHIFT (26U) /*! IDXBLK_STATUS13 - idxblk_status13 */ #define PUF_IDXBLK_STATUS_IDXBLK_STATUS13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS13_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS13_MASK) + #define PUF_IDXBLK_STATUS_IDXBLK_STATUS14_MASK (0x30000000U) #define PUF_IDXBLK_STATUS_IDXBLK_STATUS14_SHIFT (28U) /*! IDXBLK_STATUS14 - idxblk_status14 */ #define PUF_IDXBLK_STATUS_IDXBLK_STATUS14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS14_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS14_MASK) + #define PUF_IDXBLK_STATUS_IDXBLK_STATUS15_MASK (0xC0000000U) #define PUF_IDXBLK_STATUS_IDXBLK_STATUS15_SHIFT (30U) /*! IDXBLK_STATUS15 - idxblk_status15 @@ -69831,13 +78603,15 @@ typedef struct { #define PUF_IDXBLK_STATUS_IDXBLK_STATUS15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS15_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS15_MASK) /*! @} */ -/*! @name IDXBLK_SHIFT - Quiddikey Key Manager Shift Status */ +/*! @name IDXBLK_SHIFT - PUF Key Manager Shift Status */ /*! @{ */ + #define PUF_IDXBLK_SHIFT_IND_KEY0_MASK (0xFU) #define PUF_IDXBLK_SHIFT_IND_KEY0_SHIFT (0U) /*! IND_KEY0 - Index of key space in block 0 */ #define PUF_IDXBLK_SHIFT_IND_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_SHIFT_IND_KEY0_SHIFT)) & PUF_IDXBLK_SHIFT_IND_KEY0_MASK) + #define PUF_IDXBLK_SHIFT_IND_KEY1_MASK (0xF0U) #define PUF_IDXBLK_SHIFT_IND_KEY1_SHIFT (4U) /*! IND_KEY1 - Index of key space in block 1 @@ -69900,7 +78674,8 @@ typedef struct { __IO uint16_t INTEN; /**< Interrupt Enable Register, array offset: 0x26, array step: 0x60 */ __IO uint16_t DMAEN; /**< DMA Enable Register, array offset: 0x28, array step: 0x60 */ __IO uint16_t TCTRL; /**< Output Trigger Control Register, array offset: 0x2A, array step: 0x60 */ - __IO uint16_t DISMAP[2]; /**< Fault Disable Mapping Register 0..Fault Disable Mapping Register 1, array offset: 0x2C, array step: index*0x60, index2*0x2 */ + __IO uint16_t DISMAP[1]; /**< Fault Disable Mapping Register 0, array offset: 0x2C, array step: index*0x60, index2*0x2 */ + uint8_t RESERVED_1[2]; __IO uint16_t DTCNT0; /**< Deadtime Count Register 0, array offset: 0x30, array step: 0x60 */ __IO uint16_t DTCNT1; /**< Deadtime Count Register 1, array offset: 0x32, array step: 0x60 */ __IO uint16_t CAPTCTRLA; /**< Capture Control A Register, array offset: 0x34, array step: 0x60 */ @@ -69921,8 +78696,7 @@ typedef struct { __I uint16_t CVAL4CYC; /**< Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60 */ __I uint16_t CVAL5; /**< Capture Value 5 Register, array offset: 0x54, array step: 0x60 */ __I uint16_t CVAL5CYC; /**< Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60 */ - __IO uint16_t PHASEDLY; /**< Phase Delay Register, array offset: 0x58, array step: 0x60 */ - uint8_t RESERVED_1[6]; + uint8_t RESERVED_2[8]; } SM[4]; __IO uint16_t OUTEN; /**< Output Enable Register, offset: 0x180 */ __IO uint16_t MASK; /**< Mask Register, offset: 0x182 */ @@ -69948,6 +78722,7 @@ typedef struct { /*! @name CNT - Counter Register */ /*! @{ */ + #define PWM_CNT_CNT_MASK (0xFFFFU) #define PWM_CNT_CNT_SHIFT (0U) /*! CNT - Counter Register Bits @@ -69960,6 +78735,7 @@ typedef struct { /*! @name INIT - Initial Count Register */ /*! @{ */ + #define PWM_INIT_INIT_MASK (0xFFFFU) #define PWM_INIT_INIT_SHIFT (0U) /*! INIT - Initial Count Register Bits @@ -69972,6 +78748,7 @@ typedef struct { /*! @name CTRL2 - Control 2 Register */ /*! @{ */ + #define PWM_CTRL2_CLK_SEL_MASK (0x3U) #define PWM_CTRL2_CLK_SEL_SHIFT (0U) /*! CLK_SEL - Clock Source Select @@ -69982,6 +78759,7 @@ typedef struct { * 0b11..reserved */ #define PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK) + #define PWM_CTRL2_RELOAD_SEL_MASK (0x4U) #define PWM_CTRL2_RELOAD_SEL_SHIFT (2U) /*! RELOAD_SEL - Reload Source Select @@ -69990,6 +78768,7 @@ typedef struct { * in submodule 0 as it will force the RELOAD signal to logic 0. */ #define PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK) + #define PWM_CTRL2_FORCE_SEL_MASK (0x38U) #define PWM_CTRL2_FORCE_SEL_SHIFT (3U) /*! FORCE_SEL - This read/write bit determines the source of the FORCE OUTPUT signal for this submodule. @@ -70006,11 +78785,13 @@ typedef struct { * 0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates. */ #define PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK) + #define PWM_CTRL2_FORCE_MASK (0x40U) #define PWM_CTRL2_FORCE_SHIFT (6U) /*! FORCE - Force Initialization */ #define PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK) + #define PWM_CTRL2_FRCEN_MASK (0x80U) #define PWM_CTRL2_FRCEN_SHIFT (7U) /*! FRCEN - FRCEN @@ -70018,6 +78799,7 @@ typedef struct { * 0b1..Initialization from a FORCE_OUT is enabled. */ #define PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK) + #define PWM_CTRL2_INIT_SEL_MASK (0x300U) #define PWM_CTRL2_INIT_SEL_SHIFT (8U) /*! INIT_SEL - Initialization Control Select @@ -70030,21 +78812,25 @@ typedef struct { * 0b11..EXT_SYNC causes initialization. */ #define PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK) + #define PWM_CTRL2_PWMX_INIT_MASK (0x400U) #define PWM_CTRL2_PWMX_INIT_SHIFT (10U) /*! PWMX_INIT - PWM_X Initial Value */ #define PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK) + #define PWM_CTRL2_PWM45_INIT_MASK (0x800U) #define PWM_CTRL2_PWM45_INIT_SHIFT (11U) /*! PWM45_INIT - PWM45 Initial Value */ #define PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK) + #define PWM_CTRL2_PWM23_INIT_MASK (0x1000U) #define PWM_CTRL2_PWM23_INIT_SHIFT (12U) /*! PWM23_INIT - PWM23 Initial Value */ #define PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK) + #define PWM_CTRL2_INDEP_MASK (0x2000U) #define PWM_CTRL2_INDEP_SHIFT (13U) /*! INDEP - Independent or Complementary Pair Operation @@ -70052,11 +78838,13 @@ typedef struct { * 0b1..PWM_A and PWM_B outputs are independent PWMs. */ #define PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK) + #define PWM_CTRL2_WAITEN_MASK (0x4000U) #define PWM_CTRL2_WAITEN_SHIFT (14U) /*! WAITEN - WAIT Enable */ #define PWM_CTRL2_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK) + #define PWM_CTRL2_DBGEN_MASK (0x8000U) #define PWM_CTRL2_DBGEN_SHIFT (15U) /*! DBGEN - Debug Enable @@ -70069,6 +78857,7 @@ typedef struct { /*! @name CTRL - Control Register */ /*! @{ */ + #define PWM_CTRL_DBLEN_MASK (0x1U) #define PWM_CTRL_DBLEN_SHIFT (0U) /*! DBLEN - Double Switching Enable @@ -70076,6 +78865,7 @@ typedef struct { * 0b1..Double switching enabled. */ #define PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK) + #define PWM_CTRL_DBLX_MASK (0x2U) #define PWM_CTRL_DBLX_SHIFT (1U) /*! DBLX - PWMX Double Switching Enable @@ -70083,6 +78873,7 @@ typedef struct { * 0b1..PWMX double pulse enabled. */ #define PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK) + #define PWM_CTRL_LDMOD_MASK (0x4U) #define PWM_CTRL_LDMOD_SHIFT (2U) /*! LDMOD - Load Mode Select @@ -70091,6 +78882,7 @@ typedef struct { * In this case it is not necessary to set CTRL[FULL] or CTRL[HALF]. */ #define PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK) + #define PWM_CTRL_SPLIT_MASK (0x8U) #define PWM_CTRL_SPLIT_SHIFT (3U) /*! SPLIT - Split the DBLPWM signal to PWMA and PWMB @@ -70098,6 +78890,7 @@ typedef struct { * 0b1..DBLPWM is split to PWMA and PWMB. */ #define PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK) + #define PWM_CTRL_PRSC_MASK (0x70U) #define PWM_CTRL_PRSC_SHIFT (4U) /*! PRSC - Prescaler @@ -70111,6 +78904,7 @@ typedef struct { * 0b111..Prescaler 128 */ #define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK) + #define PWM_CTRL_COMPMODE_MASK (0x80U) #define PWM_CTRL_COMPMODE_SHIFT (7U) /*! COMPMODE - Compare Mode @@ -70124,11 +78918,13 @@ typedef struct { * next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value. */ #define PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK) + #define PWM_CTRL_DT_MASK (0x300U) #define PWM_CTRL_DT_SHIFT (8U) /*! DT - Deadtime */ #define PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK) + #define PWM_CTRL_FULL_MASK (0x400U) #define PWM_CTRL_FULL_SHIFT (10U) /*! FULL - Full Cycle Reload @@ -70136,6 +78932,7 @@ typedef struct { * 0b1..Full-cycle reloads enabled. */ #define PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK) + #define PWM_CTRL_HALF_MASK (0x800U) #define PWM_CTRL_HALF_SHIFT (11U) /*! HALF - Half Cycle Reload @@ -70143,6 +78940,7 @@ typedef struct { * 0b1..Half-cycle reloads enabled. */ #define PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK) + #define PWM_CTRL_LDFQ_MASK (0xF000U) #define PWM_CTRL_LDFQ_SHIFT (12U) /*! LDFQ - Load Frequency @@ -70171,6 +78969,7 @@ typedef struct { /*! @name VAL0 - Value Register 0 */ /*! @{ */ + #define PWM_VAL0_VAL0_MASK (0xFFFFU) #define PWM_VAL0_VAL0_SHIFT (0U) /*! VAL0 - Value Register 0 @@ -70183,6 +78982,7 @@ typedef struct { /*! @name FRACVAL1 - Fractional Value Register 1 */ /*! @{ */ + #define PWM_FRACVAL1_FRACVAL1_MASK (0xF800U) #define PWM_FRACVAL1_FRACVAL1_SHIFT (11U) /*! FRACVAL1 - Fractional Value 1 Register @@ -70195,6 +78995,7 @@ typedef struct { /*! @name VAL1 - Value Register 1 */ /*! @{ */ + #define PWM_VAL1_VAL1_MASK (0xFFFFU) #define PWM_VAL1_VAL1_SHIFT (0U) /*! VAL1 - Value Register 1 @@ -70207,6 +79008,7 @@ typedef struct { /*! @name FRACVAL2 - Fractional Value Register 2 */ /*! @{ */ + #define PWM_FRACVAL2_FRACVAL2_MASK (0xF800U) #define PWM_FRACVAL2_FRACVAL2_SHIFT (11U) /*! FRACVAL2 - Fractional Value 2 @@ -70219,6 +79021,7 @@ typedef struct { /*! @name VAL2 - Value Register 2 */ /*! @{ */ + #define PWM_VAL2_VAL2_MASK (0xFFFFU) #define PWM_VAL2_VAL2_SHIFT (0U) /*! VAL2 - Value Register 2 @@ -70231,6 +79034,7 @@ typedef struct { /*! @name FRACVAL3 - Fractional Value Register 3 */ /*! @{ */ + #define PWM_FRACVAL3_FRACVAL3_MASK (0xF800U) #define PWM_FRACVAL3_FRACVAL3_SHIFT (11U) /*! FRACVAL3 - Fractional Value 3 @@ -70243,6 +79047,7 @@ typedef struct { /*! @name VAL3 - Value Register 3 */ /*! @{ */ + #define PWM_VAL3_VAL3_MASK (0xFFFFU) #define PWM_VAL3_VAL3_SHIFT (0U) /*! VAL3 - Value Register 3 @@ -70255,6 +79060,7 @@ typedef struct { /*! @name FRACVAL4 - Fractional Value Register 4 */ /*! @{ */ + #define PWM_FRACVAL4_FRACVAL4_MASK (0xF800U) #define PWM_FRACVAL4_FRACVAL4_SHIFT (11U) /*! FRACVAL4 - Fractional Value 4 @@ -70267,6 +79073,7 @@ typedef struct { /*! @name VAL4 - Value Register 4 */ /*! @{ */ + #define PWM_VAL4_VAL4_MASK (0xFFFFU) #define PWM_VAL4_VAL4_SHIFT (0U) /*! VAL4 - Value Register 4 @@ -70279,6 +79086,7 @@ typedef struct { /*! @name FRACVAL5 - Fractional Value Register 5 */ /*! @{ */ + #define PWM_FRACVAL5_FRACVAL5_MASK (0xF800U) #define PWM_FRACVAL5_FRACVAL5_SHIFT (11U) /*! FRACVAL5 - Fractional Value 5 @@ -70291,6 +79099,7 @@ typedef struct { /*! @name VAL5 - Value Register 5 */ /*! @{ */ + #define PWM_VAL5_VAL5_MASK (0xFFFFU) #define PWM_VAL5_VAL5_SHIFT (0U) /*! VAL5 - Value Register 5 @@ -70303,6 +79112,7 @@ typedef struct { /*! @name FRCTRL - Fractional Control Register */ /*! @{ */ + #define PWM_FRCTRL_FRAC1_EN_MASK (0x2U) #define PWM_FRCTRL_FRAC1_EN_SHIFT (1U) /*! FRAC1_EN - Fractional Cycle PWM Period Enable @@ -70310,6 +79120,7 @@ typedef struct { * 0b1..Enable fractional cycle length for the PWM period. */ #define PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK) + #define PWM_FRCTRL_FRAC23_EN_MASK (0x4U) #define PWM_FRCTRL_FRAC23_EN_SHIFT (2U) /*! FRAC23_EN - Fractional Cycle Placement Enable for PWM_A @@ -70317,6 +79128,7 @@ typedef struct { * 0b1..Enable fractional cycle placement for PWM_A. */ #define PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK) + #define PWM_FRCTRL_FRAC45_EN_MASK (0x10U) #define PWM_FRCTRL_FRAC45_EN_SHIFT (4U) /*! FRAC45_EN - Fractional Cycle Placement Enable for PWM_B @@ -70324,13 +79136,7 @@ typedef struct { * 0b1..Enable fractional cycle placement for PWM_B. */ #define PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK) -#define PWM_FRCTRL_FRAC_PU_MASK (0x100U) -#define PWM_FRCTRL_FRAC_PU_SHIFT (8U) -/*! FRAC_PU - Fractional Delay Circuit Power Up - * 0b0..Turn off fractional delay logic. - * 0b1..Power up fractional delay logic. - */ -#define PWM_FRCTRL_FRAC_PU(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC_PU_SHIFT)) & PWM_FRCTRL_FRAC_PU_MASK) + #define PWM_FRCTRL_TEST_MASK (0x8000U) #define PWM_FRCTRL_TEST_SHIFT (15U) /*! TEST - Test Status Bit @@ -70343,6 +79149,7 @@ typedef struct { /*! @name OCTRL - Output Control Register */ /*! @{ */ + #define PWM_OCTRL_PWMXFS_MASK (0x3U) #define PWM_OCTRL_PWMXFS_SHIFT (0U) /*! PWMXFS - PWM_X Fault State @@ -70351,6 +79158,7 @@ typedef struct { * 0b10, 0b11..Output is tristated. */ #define PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK) + #define PWM_OCTRL_PWMBFS_MASK (0xCU) #define PWM_OCTRL_PWMBFS_SHIFT (2U) /*! PWMBFS - PWM_B Fault State @@ -70359,6 +79167,7 @@ typedef struct { * 0b10, 0b11..Output is tristated. */ #define PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK) + #define PWM_OCTRL_PWMAFS_MASK (0x30U) #define PWM_OCTRL_PWMAFS_SHIFT (4U) /*! PWMAFS - PWM_A Fault State @@ -70367,6 +79176,7 @@ typedef struct { * 0b10, 0b11..Output is tristated. */ #define PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK) + #define PWM_OCTRL_POLX_MASK (0x100U) #define PWM_OCTRL_POLX_SHIFT (8U) /*! POLX - PWM_X Output Polarity @@ -70374,6 +79184,7 @@ typedef struct { * 0b1..PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state. */ #define PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK) + #define PWM_OCTRL_POLB_MASK (0x200U) #define PWM_OCTRL_POLB_SHIFT (9U) /*! POLB - PWM_B Output Polarity @@ -70381,6 +79192,7 @@ typedef struct { * 0b1..PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state. */ #define PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK) + #define PWM_OCTRL_POLA_MASK (0x400U) #define PWM_OCTRL_POLA_SHIFT (10U) /*! POLA - PWM_A Output Polarity @@ -70388,16 +79200,19 @@ typedef struct { * 0b1..PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state. */ #define PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK) + #define PWM_OCTRL_PWMX_IN_MASK (0x2000U) #define PWM_OCTRL_PWMX_IN_SHIFT (13U) /*! PWMX_IN - PWM_X Input */ #define PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK) + #define PWM_OCTRL_PWMB_IN_MASK (0x4000U) #define PWM_OCTRL_PWMB_IN_SHIFT (14U) /*! PWMB_IN - PWM_B Input */ #define PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK) + #define PWM_OCTRL_PWMA_IN_MASK (0x8000U) #define PWM_OCTRL_PWMA_IN_SHIFT (15U) /*! PWMA_IN - PWM_A Input @@ -70410,6 +79225,7 @@ typedef struct { /*! @name STS - Status Register */ /*! @{ */ + #define PWM_STS_CMPF_MASK (0x3FU) #define PWM_STS_CMPF_SHIFT (0U) /*! CMPF - Compare Flags @@ -70417,36 +79233,43 @@ typedef struct { * 0b000001..A compare event has occurred for a particular VALx value. */ #define PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK) + #define PWM_STS_CFX0_MASK (0x40U) #define PWM_STS_CFX0_SHIFT (6U) /*! CFX0 - Capture Flag X0 */ #define PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK) + #define PWM_STS_CFX1_MASK (0x80U) #define PWM_STS_CFX1_SHIFT (7U) /*! CFX1 - Capture Flag X1 */ #define PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK) + #define PWM_STS_CFB0_MASK (0x100U) #define PWM_STS_CFB0_SHIFT (8U) /*! CFB0 - Capture Flag B0 */ #define PWM_STS_CFB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK) + #define PWM_STS_CFB1_MASK (0x200U) #define PWM_STS_CFB1_SHIFT (9U) /*! CFB1 - Capture Flag B1 */ #define PWM_STS_CFB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK) + #define PWM_STS_CFA0_MASK (0x400U) #define PWM_STS_CFA0_SHIFT (10U) /*! CFA0 - Capture Flag A0 */ #define PWM_STS_CFA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK) + #define PWM_STS_CFA1_MASK (0x800U) #define PWM_STS_CFA1_SHIFT (11U) /*! CFA1 - Capture Flag A1 */ #define PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK) + #define PWM_STS_RF_MASK (0x1000U) #define PWM_STS_RF_SHIFT (12U) /*! RF - Reload Flag @@ -70454,6 +79277,7 @@ typedef struct { * 0b1..New reload cycle since last STS[RF] clearing */ #define PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK) + #define PWM_STS_REF_MASK (0x2000U) #define PWM_STS_REF_SHIFT (13U) /*! REF - Reload Error Flag @@ -70461,6 +79285,7 @@ typedef struct { * 0b1..Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0. */ #define PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK) + #define PWM_STS_RUF_MASK (0x4000U) #define PWM_STS_RUF_SHIFT (14U) /*! RUF - Registers Updated Flag @@ -70475,6 +79300,7 @@ typedef struct { /*! @name INTEN - Interrupt Enable Register */ /*! @{ */ + #define PWM_INTEN_CMPIE_MASK (0x3FU) #define PWM_INTEN_CMPIE_SHIFT (0U) /*! CMPIE - Compare Interrupt Enables @@ -70482,6 +79308,7 @@ typedef struct { * 0b000001..The corresponding STS[CMPF] bit will cause an interrupt request. */ #define PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK) + #define PWM_INTEN_CX0IE_MASK (0x40U) #define PWM_INTEN_CX0IE_SHIFT (6U) /*! CX0IE - Capture X 0 Interrupt Enable @@ -70489,6 +79316,7 @@ typedef struct { * 0b1..Interrupt request enabled for STS[CFX0]. */ #define PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK) + #define PWM_INTEN_CX1IE_MASK (0x80U) #define PWM_INTEN_CX1IE_SHIFT (7U) /*! CX1IE - Capture X 1 Interrupt Enable @@ -70496,6 +79324,7 @@ typedef struct { * 0b1..Interrupt request enabled for STS[CFX1]. */ #define PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK) + #define PWM_INTEN_CB0IE_MASK (0x100U) #define PWM_INTEN_CB0IE_SHIFT (8U) /*! CB0IE - Capture B 0 Interrupt Enable @@ -70503,6 +79332,7 @@ typedef struct { * 0b1..Interrupt request enabled for STS[CFB0]. */ #define PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK) + #define PWM_INTEN_CB1IE_MASK (0x200U) #define PWM_INTEN_CB1IE_SHIFT (9U) /*! CB1IE - Capture B 1 Interrupt Enable @@ -70510,6 +79340,7 @@ typedef struct { * 0b1..Interrupt request enabled for STS[CFB1]. */ #define PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK) + #define PWM_INTEN_CA0IE_MASK (0x400U) #define PWM_INTEN_CA0IE_SHIFT (10U) /*! CA0IE - Capture A 0 Interrupt Enable @@ -70517,6 +79348,7 @@ typedef struct { * 0b1..Interrupt request enabled for STS[CFA0]. */ #define PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK) + #define PWM_INTEN_CA1IE_MASK (0x800U) #define PWM_INTEN_CA1IE_SHIFT (11U) /*! CA1IE - Capture A 1 Interrupt Enable @@ -70524,6 +79356,7 @@ typedef struct { * 0b1..Interrupt request enabled for STS[CFA1]. */ #define PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK) + #define PWM_INTEN_RIE_MASK (0x1000U) #define PWM_INTEN_RIE_SHIFT (12U) /*! RIE - Reload Interrupt Enable @@ -70531,6 +79364,7 @@ typedef struct { * 0b1..STS[RF] CPU interrupt requests enabled */ #define PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK) + #define PWM_INTEN_REIE_MASK (0x2000U) #define PWM_INTEN_REIE_SHIFT (13U) /*! REIE - Reload Error Interrupt Enable @@ -70545,36 +79379,43 @@ typedef struct { /*! @name DMAEN - DMA Enable Register */ /*! @{ */ + #define PWM_DMAEN_CX0DE_MASK (0x1U) #define PWM_DMAEN_CX0DE_SHIFT (0U) /*! CX0DE - Capture X0 FIFO DMA Enable */ #define PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK) + #define PWM_DMAEN_CX1DE_MASK (0x2U) #define PWM_DMAEN_CX1DE_SHIFT (1U) /*! CX1DE - Capture X1 FIFO DMA Enable */ #define PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK) + #define PWM_DMAEN_CB0DE_MASK (0x4U) #define PWM_DMAEN_CB0DE_SHIFT (2U) /*! CB0DE - Capture B0 FIFO DMA Enable */ #define PWM_DMAEN_CB0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK) + #define PWM_DMAEN_CB1DE_MASK (0x8U) #define PWM_DMAEN_CB1DE_SHIFT (3U) /*! CB1DE - Capture B1 FIFO DMA Enable */ #define PWM_DMAEN_CB1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK) + #define PWM_DMAEN_CA0DE_MASK (0x10U) #define PWM_DMAEN_CA0DE_SHIFT (4U) /*! CA0DE - Capture A0 FIFO DMA Enable */ #define PWM_DMAEN_CA0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK) + #define PWM_DMAEN_CA1DE_MASK (0x20U) #define PWM_DMAEN_CA1DE_SHIFT (5U) /*! CA1DE - Capture A1 FIFO DMA Enable */ #define PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK) + #define PWM_DMAEN_CAPTDE_MASK (0xC0U) #define PWM_DMAEN_CAPTDE_SHIFT (6U) /*! CAPTDE - Capture DMA Enable Source Select @@ -70586,6 +79427,7 @@ typedef struct { * 0b11..A local reload (STS[RF] being set) sets the read DMA request. */ #define PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK) + #define PWM_DMAEN_FAND_MASK (0x100U) #define PWM_DMAEN_FAND_SHIFT (8U) /*! FAND - FIFO Watermark AND Control @@ -70593,6 +79435,7 @@ typedef struct { * 0b1..Selected FIFO watermarks are AND'ed together. */ #define PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK) + #define PWM_DMAEN_VALDE_MASK (0x200U) #define PWM_DMAEN_VALDE_SHIFT (9U) /*! VALDE - Value Registers DMA Enable @@ -70607,6 +79450,7 @@ typedef struct { /*! @name TCTRL - Output Trigger Control Register */ /*! @{ */ + #define PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU) #define PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U) /*! OUT_TRIG_EN - Output Trigger Enables @@ -70618,6 +79462,7 @@ typedef struct { * 0b1xxxxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL5 value. */ #define PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK) + #define PWM_TCTRL_TRGFRQ_MASK (0x1000U) #define PWM_TCTRL_TRGFRQ_SHIFT (12U) /*! TRGFRQ - Trigger frequency @@ -70626,18 +79471,20 @@ typedef struct { * is not reloaded every period due to CTRL[LDFQ] being non-zero. */ #define PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK) + #define PWM_TCTRL_PWBOT1_MASK (0x4000U) #define PWM_TCTRL_PWBOT1_SHIFT (14U) -/*! PWBOT1 - Mux Output Trigger 1 Source Select - * 0b0..Route the PWM_OUT_TRIG1 signal to PWM_MUX_TRIG1 port. - * 0b1..Route the PWMB output to the PWM_MUX_TRIG1 port. +/*! PWBOT1 - Output Trigger 1 Source Select + * 0b0..Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port. + * 0b1..Route the PWMB output to the PWM_OUT_TRIG1 port. */ #define PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK) + #define PWM_TCTRL_PWAOT0_MASK (0x8000U) #define PWM_TCTRL_PWAOT0_SHIFT (15U) -/*! PWAOT0 - Mux Output Trigger 0 Source Select - * 0b0..Route the PWM_OUT_TRIG0 signal to PWM_MUX_TRIG0 port. - * 0b1..Route the PWMA output to the PWM_MUX_TRIG0 port. +/*! PWAOT0 - Output Trigger 0 Source Select + * 0b0..Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port. + * 0b1..Route the PWMA output to the PWM_OUT_TRIG0 port. */ #define PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK) /*! @} */ @@ -70645,48 +79492,37 @@ typedef struct { /* The count of PWM_TCTRL */ #define PWM_TCTRL_COUNT (4U) -/*! @name DISMAP - Fault Disable Mapping Register 0..Fault Disable Mapping Register 1 */ +/*! @name DISMAP - Fault Disable Mapping Register 0 */ /*! @{ */ + #define PWM_DISMAP_DIS0A_MASK (0xFU) #define PWM_DISMAP_DIS0A_SHIFT (0U) /*! DIS0A - PWM_A Fault Disable Mask 0 */ #define PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK) -#define PWM_DISMAP_DIS1A_MASK (0xFU) -#define PWM_DISMAP_DIS1A_SHIFT (0U) -/*! DIS1A - PWM_A Fault Disable Mask 1 - */ -#define PWM_DISMAP_DIS1A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1A_SHIFT)) & PWM_DISMAP_DIS1A_MASK) + #define PWM_DISMAP_DIS0B_MASK (0xF0U) #define PWM_DISMAP_DIS0B_SHIFT (4U) /*! DIS0B - PWM_B Fault Disable Mask 0 */ #define PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK) -#define PWM_DISMAP_DIS1B_MASK (0xF0U) -#define PWM_DISMAP_DIS1B_SHIFT (4U) -/*! DIS1B - PWM_B Fault Disable Mask 1 - */ -#define PWM_DISMAP_DIS1B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1B_SHIFT)) & PWM_DISMAP_DIS1B_MASK) + #define PWM_DISMAP_DIS0X_MASK (0xF00U) #define PWM_DISMAP_DIS0X_SHIFT (8U) /*! DIS0X - PWM_X Fault Disable Mask 0 */ #define PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK) -#define PWM_DISMAP_DIS1X_MASK (0xF00U) -#define PWM_DISMAP_DIS1X_SHIFT (8U) -/*! DIS1X - PWM_X Fault Disable Mask 1 - */ -#define PWM_DISMAP_DIS1X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS1X_SHIFT)) & PWM_DISMAP_DIS1X_MASK) /*! @} */ /* The count of PWM_DISMAP */ #define PWM_DISMAP_COUNT (4U) /* The count of PWM_DISMAP */ -#define PWM_DISMAP_COUNT2 (2U) +#define PWM_DISMAP_COUNT2 (1U) /*! @name DTCNT0 - Deadtime Count Register 0 */ /*! @{ */ + #define PWM_DTCNT0_DTCNT0_MASK (0xFFFFU) #define PWM_DTCNT0_DTCNT0_SHIFT (0U) /*! DTCNT0 - DTCNT0 @@ -70699,6 +79535,7 @@ typedef struct { /*! @name DTCNT1 - Deadtime Count Register 1 */ /*! @{ */ + #define PWM_DTCNT1_DTCNT1_MASK (0xFFFFU) #define PWM_DTCNT1_DTCNT1_SHIFT (0U) /*! DTCNT1 - DTCNT1 @@ -70711,6 +79548,7 @@ typedef struct { /*! @name CAPTCTRLA - Capture Control A Register */ /*! @{ */ + #define PWM_CAPTCTRLA_ARMA_MASK (0x1U) #define PWM_CAPTCTRLA_ARMA_SHIFT (0U) /*! ARMA - Arm A @@ -70718,6 +79556,7 @@ typedef struct { * 0b1..Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled. */ #define PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK) + #define PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U) #define PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U) /*! ONESHOTA - One Shot Mode A @@ -70725,6 +79564,7 @@ typedef struct { * 0b1..One Shot */ #define PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK) + #define PWM_CAPTCTRLA_EDGA0_MASK (0xCU) #define PWM_CAPTCTRLA_EDGA0_SHIFT (2U) /*! EDGA0 - Edge A 0 @@ -70734,6 +79574,7 @@ typedef struct { * 0b11..Capture any edge */ #define PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK) + #define PWM_CAPTCTRLA_EDGA1_MASK (0x30U) #define PWM_CAPTCTRLA_EDGA1_SHIFT (4U) /*! EDGA1 - Edge A 1 @@ -70743,6 +79584,7 @@ typedef struct { * 0b11..Capture any edge */ #define PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK) + #define PWM_CAPTCTRLA_INP_SELA_MASK (0x40U) #define PWM_CAPTCTRLA_INP_SELA_SHIFT (6U) /*! INP_SELA - Input Select A @@ -70750,6 +79592,7 @@ typedef struct { * 0b1..Edge Counter */ #define PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK) + #define PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U) #define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U) /*! EDGCNTA_EN - Edge Counter A Enable @@ -70757,16 +79600,19 @@ typedef struct { * 0b1..Edge counter enabled */ #define PWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK) + #define PWM_CAPTCTRLA_CFAWM_MASK (0x300U) #define PWM_CAPTCTRLA_CFAWM_SHIFT (8U) /*! CFAWM - Capture A FIFOs Water Mark */ #define PWM_CAPTCTRLA_CFAWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK) + #define PWM_CAPTCTRLA_CA0CNT_MASK (0x1C00U) #define PWM_CAPTCTRLA_CA0CNT_SHIFT (10U) /*! CA0CNT - Capture A0 FIFO Word Count */ #define PWM_CAPTCTRLA_CA0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK) + #define PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U) #define PWM_CAPTCTRLA_CA1CNT_SHIFT (13U) /*! CA1CNT - Capture A1 FIFO Word Count @@ -70779,11 +79625,13 @@ typedef struct { /*! @name CAPTCOMPA - Capture Compare A Register */ /*! @{ */ + #define PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU) #define PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U) /*! EDGCMPA - Edge Compare A */ #define PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK) + #define PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U) #define PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U) /*! EDGCNTA - Edge Counter A @@ -70796,6 +79644,7 @@ typedef struct { /*! @name CAPTCTRLB - Capture Control B Register */ /*! @{ */ + #define PWM_CAPTCTRLB_ARMB_MASK (0x1U) #define PWM_CAPTCTRLB_ARMB_SHIFT (0U) /*! ARMB - Arm B @@ -70803,6 +79652,7 @@ typedef struct { * 0b1..Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled. */ #define PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK) + #define PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U) #define PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U) /*! ONESHOTB - One Shot Mode B @@ -70810,6 +79660,7 @@ typedef struct { * 0b1..One Shot */ #define PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK) + #define PWM_CAPTCTRLB_EDGB0_MASK (0xCU) #define PWM_CAPTCTRLB_EDGB0_SHIFT (2U) /*! EDGB0 - Edge B 0 @@ -70819,6 +79670,7 @@ typedef struct { * 0b11..Capture any edge */ #define PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK) + #define PWM_CAPTCTRLB_EDGB1_MASK (0x30U) #define PWM_CAPTCTRLB_EDGB1_SHIFT (4U) /*! EDGB1 - Edge B 1 @@ -70828,6 +79680,7 @@ typedef struct { * 0b11..Capture any edge */ #define PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK) + #define PWM_CAPTCTRLB_INP_SELB_MASK (0x40U) #define PWM_CAPTCTRLB_INP_SELB_SHIFT (6U) /*! INP_SELB - Input Select B @@ -70835,6 +79688,7 @@ typedef struct { * 0b1..Edge Counter */ #define PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK) + #define PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U) #define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U) /*! EDGCNTB_EN - Edge Counter B Enable @@ -70842,16 +79696,19 @@ typedef struct { * 0b1..Edge counter enabled */ #define PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK) + #define PWM_CAPTCTRLB_CFBWM_MASK (0x300U) #define PWM_CAPTCTRLB_CFBWM_SHIFT (8U) /*! CFBWM - Capture B FIFOs Water Mark */ #define PWM_CAPTCTRLB_CFBWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK) + #define PWM_CAPTCTRLB_CB0CNT_MASK (0x1C00U) #define PWM_CAPTCTRLB_CB0CNT_SHIFT (10U) /*! CB0CNT - Capture B0 FIFO Word Count */ #define PWM_CAPTCTRLB_CB0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK) + #define PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U) #define PWM_CAPTCTRLB_CB1CNT_SHIFT (13U) /*! CB1CNT - Capture B1 FIFO Word Count @@ -70864,11 +79721,13 @@ typedef struct { /*! @name CAPTCOMPB - Capture Compare B Register */ /*! @{ */ + #define PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU) #define PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U) /*! EDGCMPB - Edge Compare B */ #define PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK) + #define PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U) #define PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U) /*! EDGCNTB - Edge Counter B @@ -70881,6 +79740,7 @@ typedef struct { /*! @name CAPTCTRLX - Capture Control X Register */ /*! @{ */ + #define PWM_CAPTCTRLX_ARMX_MASK (0x1U) #define PWM_CAPTCTRLX_ARMX_SHIFT (0U) /*! ARMX - Arm X @@ -70888,6 +79748,7 @@ typedef struct { * 0b1..Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled. */ #define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK) + #define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U) #define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U) /*! ONESHOTX - One Shot Mode Aux @@ -70895,6 +79756,7 @@ typedef struct { * 0b1..One Shot */ #define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK) + #define PWM_CAPTCTRLX_EDGX0_MASK (0xCU) #define PWM_CAPTCTRLX_EDGX0_SHIFT (2U) /*! EDGX0 - Edge X 0 @@ -70904,6 +79766,7 @@ typedef struct { * 0b11..Capture any edge */ #define PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK) + #define PWM_CAPTCTRLX_EDGX1_MASK (0x30U) #define PWM_CAPTCTRLX_EDGX1_SHIFT (4U) /*! EDGX1 - Edge X 1 @@ -70913,6 +79776,7 @@ typedef struct { * 0b11..Capture any edge */ #define PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK) + #define PWM_CAPTCTRLX_INP_SELX_MASK (0x40U) #define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U) /*! INP_SELX - Input Select X @@ -70920,6 +79784,7 @@ typedef struct { * 0b1..Edge Counter */ #define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK) + #define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U) #define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U) /*! EDGCNTX_EN - Edge Counter X Enable @@ -70927,16 +79792,19 @@ typedef struct { * 0b1..Edge counter enabled */ #define PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK) + #define PWM_CAPTCTRLX_CFXWM_MASK (0x300U) #define PWM_CAPTCTRLX_CFXWM_SHIFT (8U) /*! CFXWM - Capture X FIFOs Water Mark */ #define PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK) + #define PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U) #define PWM_CAPTCTRLX_CX0CNT_SHIFT (10U) /*! CX0CNT - Capture X0 FIFO Word Count */ #define PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK) + #define PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U) #define PWM_CAPTCTRLX_CX1CNT_SHIFT (13U) /*! CX1CNT - Capture X1 FIFO Word Count @@ -70949,11 +79817,13 @@ typedef struct { /*! @name CAPTCOMPX - Capture Compare X Register */ /*! @{ */ + #define PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU) #define PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U) /*! EDGCMPX - Edge Compare X */ #define PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK) + #define PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U) #define PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U) /*! EDGCNTX - Edge Counter X @@ -70966,6 +79836,7 @@ typedef struct { /*! @name CVAL0 - Capture Value 0 Register */ /*! @{ */ + #define PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU) #define PWM_CVAL0_CAPTVAL0_SHIFT (0U) /*! CAPTVAL0 - CAPTVAL0 @@ -70978,6 +79849,7 @@ typedef struct { /*! @name CVAL0CYC - Capture Value 0 Cycle Register */ /*! @{ */ + #define PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU) #define PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U) /*! CVAL0CYC - CVAL0CYC @@ -70990,6 +79862,7 @@ typedef struct { /*! @name CVAL1 - Capture Value 1 Register */ /*! @{ */ + #define PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU) #define PWM_CVAL1_CAPTVAL1_SHIFT (0U) /*! CAPTVAL1 - CAPTVAL1 @@ -71002,6 +79875,7 @@ typedef struct { /*! @name CVAL1CYC - Capture Value 1 Cycle Register */ /*! @{ */ + #define PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU) #define PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U) /*! CVAL1CYC - CVAL1CYC @@ -71014,6 +79888,7 @@ typedef struct { /*! @name CVAL2 - Capture Value 2 Register */ /*! @{ */ + #define PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU) #define PWM_CVAL2_CAPTVAL2_SHIFT (0U) /*! CAPTVAL2 - CAPTVAL2 @@ -71026,6 +79901,7 @@ typedef struct { /*! @name CVAL2CYC - Capture Value 2 Cycle Register */ /*! @{ */ + #define PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU) #define PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U) /*! CVAL2CYC - CVAL2CYC @@ -71038,6 +79914,7 @@ typedef struct { /*! @name CVAL3 - Capture Value 3 Register */ /*! @{ */ + #define PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU) #define PWM_CVAL3_CAPTVAL3_SHIFT (0U) /*! CAPTVAL3 - CAPTVAL3 @@ -71050,6 +79927,7 @@ typedef struct { /*! @name CVAL3CYC - Capture Value 3 Cycle Register */ /*! @{ */ + #define PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU) #define PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U) /*! CVAL3CYC - CVAL3CYC @@ -71062,6 +79940,7 @@ typedef struct { /*! @name CVAL4 - Capture Value 4 Register */ /*! @{ */ + #define PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU) #define PWM_CVAL4_CAPTVAL4_SHIFT (0U) /*! CAPTVAL4 - CAPTVAL4 @@ -71074,6 +79953,7 @@ typedef struct { /*! @name CVAL4CYC - Capture Value 4 Cycle Register */ /*! @{ */ + #define PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU) #define PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U) /*! CVAL4CYC - CVAL4CYC @@ -71086,6 +79966,7 @@ typedef struct { /*! @name CVAL5 - Capture Value 5 Register */ /*! @{ */ + #define PWM_CVAL5_CAPTVAL5_MASK (0xFFFFU) #define PWM_CVAL5_CAPTVAL5_SHIFT (0U) /*! CAPTVAL5 - CAPTVAL5 @@ -71098,6 +79979,7 @@ typedef struct { /*! @name CVAL5CYC - Capture Value 5 Cycle Register */ /*! @{ */ + #define PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU) #define PWM_CVAL5CYC_CVAL5CYC_SHIFT (0U) /*! CVAL5CYC - CVAL5CYC @@ -71108,20 +79990,9 @@ typedef struct { /* The count of PWM_CVAL5CYC */ #define PWM_CVAL5CYC_COUNT (4U) -/*! @name PHASEDLY - Phase Delay Register */ -/*! @{ */ -#define PWM_PHASEDLY_PHASEDLY_MASK (0xFFFFU) -#define PWM_PHASEDLY_PHASEDLY_SHIFT (0U) -/*! PHASEDLY - Initial Count Register Bits - */ -#define PWM_PHASEDLY_PHASEDLY(x) (((uint16_t)(((uint16_t)(x)) << PWM_PHASEDLY_PHASEDLY_SHIFT)) & PWM_PHASEDLY_PHASEDLY_MASK) -/*! @} */ - -/* The count of PWM_PHASEDLY */ -#define PWM_PHASEDLY_COUNT (4U) - /*! @name OUTEN - Output Enable Register */ /*! @{ */ + #define PWM_OUTEN_PWMX_EN_MASK (0xFU) #define PWM_OUTEN_PWMX_EN_SHIFT (0U) /*! PWMX_EN - PWM_X Output Enables @@ -71129,6 +80000,7 @@ typedef struct { * 0b0001..PWM_X output enabled. */ #define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK) + #define PWM_OUTEN_PWMB_EN_MASK (0xF0U) #define PWM_OUTEN_PWMB_EN_SHIFT (4U) /*! PWMB_EN - PWM_B Output Enables @@ -71136,6 +80008,7 @@ typedef struct { * 0b0001..PWM_B output enabled. */ #define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK) + #define PWM_OUTEN_PWMA_EN_MASK (0xF00U) #define PWM_OUTEN_PWMA_EN_SHIFT (8U) /*! PWMA_EN - PWM_A Output Enables @@ -71147,6 +80020,7 @@ typedef struct { /*! @name MASK - Mask Register */ /*! @{ */ + #define PWM_MASK_MASKX_MASK (0xFU) #define PWM_MASK_MASKX_SHIFT (0U) /*! MASKX - PWM_X Masks @@ -71154,6 +80028,7 @@ typedef struct { * 0b0001..PWM_X output masked. */ #define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK) + #define PWM_MASK_MASKB_MASK (0xF0U) #define PWM_MASK_MASKB_SHIFT (4U) /*! MASKB - PWM_B Masks @@ -71161,6 +80036,7 @@ typedef struct { * 0b0001..PWM_B output masked. */ #define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK) + #define PWM_MASK_MASKA_MASK (0xF00U) #define PWM_MASK_MASKA_SHIFT (8U) /*! MASKA - PWM_A Masks @@ -71172,6 +80048,7 @@ typedef struct { /*! @name SWCOUT - Software Controlled Output Register */ /*! @{ */ + #define PWM_SWCOUT_SM0OUT45_MASK (0x1U) #define PWM_SWCOUT_SM0OUT45_SHIFT (0U) /*! SM0OUT45 - Submodule 0 Software Controlled Output 45 @@ -71179,6 +80056,7 @@ typedef struct { * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45. */ #define PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK) + #define PWM_SWCOUT_SM0OUT23_MASK (0x2U) #define PWM_SWCOUT_SM0OUT23_SHIFT (1U) /*! SM0OUT23 - Submodule 0 Software Controlled Output 23 @@ -71186,6 +80064,7 @@ typedef struct { * 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23. */ #define PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK) + #define PWM_SWCOUT_SM1OUT45_MASK (0x4U) #define PWM_SWCOUT_SM1OUT45_SHIFT (2U) /*! SM1OUT45 - Submodule 1 Software Controlled Output 45 @@ -71193,6 +80072,7 @@ typedef struct { * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45. */ #define PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK) + #define PWM_SWCOUT_SM1OUT23_MASK (0x8U) #define PWM_SWCOUT_SM1OUT23_SHIFT (3U) /*! SM1OUT23 - Submodule 1 Software Controlled Output 23 @@ -71200,6 +80080,7 @@ typedef struct { * 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23. */ #define PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK) + #define PWM_SWCOUT_SM2OUT45_MASK (0x10U) #define PWM_SWCOUT_SM2OUT45_SHIFT (4U) /*! SM2OUT45 - Submodule 2 Software Controlled Output 45 @@ -71207,6 +80088,7 @@ typedef struct { * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45. */ #define PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK) + #define PWM_SWCOUT_SM2OUT23_MASK (0x20U) #define PWM_SWCOUT_SM2OUT23_SHIFT (5U) /*! SM2OUT23 - Submodule 2 Software Controlled Output 23 @@ -71214,6 +80096,7 @@ typedef struct { * 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23. */ #define PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK) + #define PWM_SWCOUT_SM3OUT45_MASK (0x40U) #define PWM_SWCOUT_SM3OUT45_SHIFT (6U) /*! SM3OUT45 - Submodule 3 Software Controlled Output 45 @@ -71221,6 +80104,7 @@ typedef struct { * 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45. */ #define PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK) + #define PWM_SWCOUT_SM3OUT23_MASK (0x80U) #define PWM_SWCOUT_SM3OUT23_SHIFT (7U) /*! SM3OUT23 - Submodule 3 Software Controlled Output 23 @@ -71232,6 +80116,7 @@ typedef struct { /*! @name DTSRCSEL - PWM Source Select Register */ /*! @{ */ + #define PWM_DTSRCSEL_SM0SEL45_MASK (0x3U) #define PWM_DTSRCSEL_SM0SEL45_SHIFT (0U) /*! SM0SEL45 - Submodule 0 PWM45 Control Select @@ -71241,6 +80126,7 @@ typedef struct { * 0b11..PWM0_EXTB signal is used by the deadtime logic. */ #define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK) + #define PWM_DTSRCSEL_SM0SEL23_MASK (0xCU) #define PWM_DTSRCSEL_SM0SEL23_SHIFT (2U) /*! SM0SEL23 - Submodule 0 PWM23 Control Select @@ -71250,6 +80136,7 @@ typedef struct { * 0b11..PWM0_EXTA signal is used by the deadtime logic. */ #define PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK) + #define PWM_DTSRCSEL_SM1SEL45_MASK (0x30U) #define PWM_DTSRCSEL_SM1SEL45_SHIFT (4U) /*! SM1SEL45 - Submodule 1 PWM45 Control Select @@ -71259,6 +80146,7 @@ typedef struct { * 0b11..PWM1_EXTB signal is used by the deadtime logic. */ #define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK) + #define PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U) #define PWM_DTSRCSEL_SM1SEL23_SHIFT (6U) /*! SM1SEL23 - Submodule 1 PWM23 Control Select @@ -71268,6 +80156,7 @@ typedef struct { * 0b11..PWM1_EXTA signal is used by the deadtime logic. */ #define PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK) + #define PWM_DTSRCSEL_SM2SEL45_MASK (0x300U) #define PWM_DTSRCSEL_SM2SEL45_SHIFT (8U) /*! SM2SEL45 - Submodule 2 PWM45 Control Select @@ -71277,6 +80166,7 @@ typedef struct { * 0b11..PWM2_EXTB signal is used by the deadtime logic. */ #define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK) + #define PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U) #define PWM_DTSRCSEL_SM2SEL23_SHIFT (10U) /*! SM2SEL23 - Submodule 2 PWM23 Control Select @@ -71286,6 +80176,7 @@ typedef struct { * 0b11..PWM2_EXTA signal is used by the deadtime logic. */ #define PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK) + #define PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U) #define PWM_DTSRCSEL_SM3SEL45_SHIFT (12U) /*! SM3SEL45 - Submodule 3 PWM45 Control Select @@ -71295,6 +80186,7 @@ typedef struct { * 0b11..PWM3_EXTB signal is used by the deadtime logic. */ #define PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK) + #define PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U) #define PWM_DTSRCSEL_SM3SEL23_SHIFT (14U) /*! SM3SEL23 - Submodule 3 PWM23 Control Select @@ -71308,6 +80200,7 @@ typedef struct { /*! @name MCTRL - Master Control Register */ /*! @{ */ + #define PWM_MCTRL_LDOK_MASK (0xFU) #define PWM_MCTRL_LDOK_SHIFT (0U) /*! LDOK - Load Okay @@ -71315,11 +80208,13 @@ typedef struct { * 0b0001..Load prescaler, modulus, and PWM values of the corresponding submodule. */ #define PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK) + #define PWM_MCTRL_CLDOK_MASK (0xF0U) #define PWM_MCTRL_CLDOK_SHIFT (4U) /*! CLDOK - Clear Load Okay */ #define PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK) + #define PWM_MCTRL_RUN_MASK (0xF00U) #define PWM_MCTRL_RUN_SHIFT (8U) /*! RUN - Run @@ -71327,6 +80222,7 @@ typedef struct { * 0b0001..PWM counter is started in the corresponding submodule. */ #define PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK) + #define PWM_MCTRL_IPOL_MASK (0xF000U) #define PWM_MCTRL_IPOL_SHIFT (12U) /*! IPOL - Current Polarity @@ -71338,6 +80234,7 @@ typedef struct { /*! @name MCTRL2 - Master Control 2 Register */ /*! @{ */ + #define PWM_MCTRL2_MONPLL_MASK (0x3U) #define PWM_MCTRL2_MONPLL_SHIFT (0U) /*! MONPLL - Monitor PLL State @@ -71353,6 +80250,7 @@ typedef struct { /*! @name FCTRL - Fault Control Register */ /*! @{ */ + #define PWM_FCTRL_FIE_MASK (0xFU) #define PWM_FCTRL_FIE_SHIFT (0U) /*! FIE - Fault Interrupt Enables @@ -71360,6 +80258,7 @@ typedef struct { * 0b0001..FAULTx CPU interrupt requests enabled. */ #define PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK) + #define PWM_FCTRL_FSAFE_MASK (0xF0U) #define PWM_FCTRL_FSAFE_SHIFT (4U) /*! FSAFE - Fault Safety Mode @@ -71374,6 +80273,7 @@ typedef struct { * FSTS[FFULL]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared. */ #define PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK) + #define PWM_FCTRL_FAUTO_MASK (0xF00U) #define PWM_FCTRL_FAUTO_SHIFT (8U) /*! FAUTO - Automatic Fault Clearing @@ -71387,6 +80287,7 @@ typedef struct { * cannot be cleared. */ #define PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK) + #define PWM_FCTRL_FLVL_MASK (0xF000U) #define PWM_FCTRL_FLVL_SHIFT (12U) /*! FLVL - Fault Level @@ -71398,6 +80299,7 @@ typedef struct { /*! @name FSTS - Fault Status Register */ /*! @{ */ + #define PWM_FSTS_FFLAG_MASK (0xFU) #define PWM_FSTS_FFLAG_SHIFT (0U) /*! FFLAG - Fault Flags @@ -71405,6 +80307,7 @@ typedef struct { * 0b0001..Fault on the FAULTx pin. */ #define PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK) + #define PWM_FSTS_FFULL_MASK (0xF0U) #define PWM_FSTS_FFULL_SHIFT (4U) /*! FFULL - Full Cycle @@ -71412,11 +80315,13 @@ typedef struct { * 0b0001..PWM outputs are re-enabled at the start of a full cycle */ #define PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK) + #define PWM_FSTS_FFPIN_MASK (0xF00U) #define PWM_FSTS_FFPIN_SHIFT (8U) /*! FFPIN - Filtered Fault Pins */ #define PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK) + #define PWM_FSTS_FHALF_MASK (0xF000U) #define PWM_FSTS_FHALF_SHIFT (12U) /*! FHALF - Half Cycle Fault Recovery @@ -71428,16 +80333,19 @@ typedef struct { /*! @name FFILT - Fault Filter Register */ /*! @{ */ + #define PWM_FFILT_FILT_PER_MASK (0xFFU) #define PWM_FFILT_FILT_PER_SHIFT (0U) /*! FILT_PER - Fault Filter Period */ #define PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK) + #define PWM_FFILT_FILT_CNT_MASK (0x700U) #define PWM_FFILT_FILT_CNT_SHIFT (8U) /*! FILT_CNT - Fault Filter Count */ #define PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK) + #define PWM_FFILT_GSTR_MASK (0x8000U) #define PWM_FFILT_GSTR_SHIFT (15U) /*! GSTR - Fault Glitch Stretch Enable @@ -71449,6 +80357,7 @@ typedef struct { /*! @name FTST - Fault Test Register */ /*! @{ */ + #define PWM_FTST_FTEST_MASK (0x1U) #define PWM_FTST_FTEST_SHIFT (0U) /*! FTEST - Fault Test @@ -71460,6 +80369,7 @@ typedef struct { /*! @name FCTRL2 - Fault Control 2 Register */ /*! @{ */ + #define PWM_FCTRL2_NOCOMB_MASK (0xFU) #define PWM_FCTRL2_NOCOMB_SHIFT (0U) /*! NOCOMB - No Combinational Path From Fault Input To PWM Output @@ -71605,21 +80515,35 @@ typedef struct { /*! @name CTRL - Control Register 0 */ /*! @{ */ + #define PXP_CTRL_ENABLE_MASK (0x1U) #define PXP_CTRL_ENABLE_SHIFT (0U) +/*! ENABLE + * 0b1..PXP is enabled + * 0b0..PXP is disabled + */ #define PXP_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK) + #define PXP_CTRL_IRQ_ENABLE_MASK (0x2U) #define PXP_CTRL_IRQ_ENABLE_SHIFT (1U) +/*! IRQ_ENABLE + * 0b1..PXP interrupt is enabled + * 0b0..PXP interrupt is disabled + */ #define PXP_CTRL_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK) + #define PXP_CTRL_NEXT_IRQ_ENABLE_MASK (0x4U) #define PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT (2U) +/*! NEXT_IRQ_ENABLE + * 0b0..Disabled + * 0b1..Enabled + */ #define PXP_CTRL_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK) + #define PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK (0x10U) #define PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT (4U) #define PXP_CTRL_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK) -#define PXP_CTRL_RSVD0_MASK (0xE0U) -#define PXP_CTRL_RSVD0_SHIFT (5U) -#define PXP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD0_SHIFT)) & PXP_CTRL_RSVD0_MASK) + #define PXP_CTRL_ROTATE_MASK (0x300U) #define PXP_CTRL_ROTATE_SHIFT (8U) /*! ROTATE @@ -71629,18 +80553,27 @@ typedef struct { * 0b11..ROT_270 */ #define PXP_CTRL_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE_SHIFT)) & PXP_CTRL_ROTATE_MASK) + #define PXP_CTRL_HFLIP_MASK (0x400U) #define PXP_CTRL_HFLIP_SHIFT (10U) +/*! HFLIP + * 0b0..Horizontal Flip is disabled + * 0b1..Horizontal Flip is enabled + */ #define PXP_CTRL_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP_SHIFT)) & PXP_CTRL_HFLIP_MASK) + #define PXP_CTRL_VFLIP_MASK (0x800U) #define PXP_CTRL_VFLIP_SHIFT (11U) +/*! VFLIP + * 0b0..Vertical Flip is disabled + * 0b1..Vertical Flip is enabled + */ #define PXP_CTRL_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP_SHIFT)) & PXP_CTRL_VFLIP_MASK) -#define PXP_CTRL_RSVD1_MASK (0x3FF000U) -#define PXP_CTRL_RSVD1_SHIFT (12U) -#define PXP_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD1_SHIFT)) & PXP_CTRL_RSVD1_MASK) + #define PXP_CTRL_ROT_POS_MASK (0x400000U) #define PXP_CTRL_ROT_POS_SHIFT (22U) #define PXP_CTRL_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROT_POS_SHIFT)) & PXP_CTRL_ROT_POS_MASK) + #define PXP_CTRL_BLOCK_SIZE_MASK (0x800000U) #define PXP_CTRL_BLOCK_SIZE_SHIFT (23U) /*! BLOCK_SIZE @@ -71648,40 +80581,63 @@ typedef struct { * 0b1..Process 16x16 pixel blocks. */ #define PXP_CTRL_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK) -#define PXP_CTRL_RSVD3_MASK (0xF000000U) -#define PXP_CTRL_RSVD3_SHIFT (24U) -#define PXP_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD3_SHIFT)) & PXP_CTRL_RSVD3_MASK) + #define PXP_CTRL_EN_REPEAT_MASK (0x10000000U) #define PXP_CTRL_EN_REPEAT_SHIFT (28U) +/*! EN_REPEAT + * 0b1..PXP will repeat based on the current configuration register settings + * 0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed + */ #define PXP_CTRL_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_EN_REPEAT_SHIFT)) & PXP_CTRL_EN_REPEAT_MASK) -#define PXP_CTRL_RSVD4_MASK (0x20000000U) -#define PXP_CTRL_RSVD4_SHIFT (29U) -#define PXP_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_RSVD4_SHIFT)) & PXP_CTRL_RSVD4_MASK) + #define PXP_CTRL_CLKGATE_MASK (0x40000000U) #define PXP_CTRL_CLKGATE_SHIFT (30U) +/*! CLKGATE + * 0b0..Normal operation + * 0b1..All clocks to PXP is gated-off + */ #define PXP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK) + #define PXP_CTRL_SFTRST_MASK (0x80000000U) #define PXP_CTRL_SFTRST_SHIFT (31U) +/*! SFTRST + * 0b0..Normal PXP operation is enabled + * 0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value. + */ #define PXP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK) /*! @} */ /*! @name CTRL_SET - Control Register 0 */ /*! @{ */ + #define PXP_CTRL_SET_ENABLE_MASK (0x1U) #define PXP_CTRL_SET_ENABLE_SHIFT (0U) +/*! ENABLE + * 0b1..PXP is enabled + * 0b0..PXP is disabled + */ #define PXP_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK) + #define PXP_CTRL_SET_IRQ_ENABLE_MASK (0x2U) #define PXP_CTRL_SET_IRQ_ENABLE_SHIFT (1U) +/*! IRQ_ENABLE + * 0b1..PXP interrupt is enabled + * 0b0..PXP interrupt is disabled + */ #define PXP_CTRL_SET_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK) + #define PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK (0x4U) #define PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT (2U) +/*! NEXT_IRQ_ENABLE + * 0b0..Disabled + * 0b1..Enabled + */ #define PXP_CTRL_SET_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK) + #define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK (0x10U) #define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT (4U) #define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK) -#define PXP_CTRL_SET_RSVD0_MASK (0xE0U) -#define PXP_CTRL_SET_RSVD0_SHIFT (5U) -#define PXP_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD0_SHIFT)) & PXP_CTRL_SET_RSVD0_MASK) + #define PXP_CTRL_SET_ROTATE_MASK (0x300U) #define PXP_CTRL_SET_ROTATE_SHIFT (8U) /*! ROTATE @@ -71691,18 +80647,27 @@ typedef struct { * 0b11..ROT_270 */ #define PXP_CTRL_SET_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE_SHIFT)) & PXP_CTRL_SET_ROTATE_MASK) + #define PXP_CTRL_SET_HFLIP_MASK (0x400U) #define PXP_CTRL_SET_HFLIP_SHIFT (10U) +/*! HFLIP + * 0b0..Horizontal Flip is disabled + * 0b1..Horizontal Flip is enabled + */ #define PXP_CTRL_SET_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP_SHIFT)) & PXP_CTRL_SET_HFLIP_MASK) + #define PXP_CTRL_SET_VFLIP_MASK (0x800U) #define PXP_CTRL_SET_VFLIP_SHIFT (11U) +/*! VFLIP + * 0b0..Vertical Flip is disabled + * 0b1..Vertical Flip is enabled + */ #define PXP_CTRL_SET_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP_SHIFT)) & PXP_CTRL_SET_VFLIP_MASK) -#define PXP_CTRL_SET_RSVD1_MASK (0x3FF000U) -#define PXP_CTRL_SET_RSVD1_SHIFT (12U) -#define PXP_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD1_SHIFT)) & PXP_CTRL_SET_RSVD1_MASK) + #define PXP_CTRL_SET_ROT_POS_MASK (0x400000U) #define PXP_CTRL_SET_ROT_POS_SHIFT (22U) #define PXP_CTRL_SET_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROT_POS_SHIFT)) & PXP_CTRL_SET_ROT_POS_MASK) + #define PXP_CTRL_SET_BLOCK_SIZE_MASK (0x800000U) #define PXP_CTRL_SET_BLOCK_SIZE_SHIFT (23U) /*! BLOCK_SIZE @@ -71710,40 +80675,63 @@ typedef struct { * 0b1..Process 16x16 pixel blocks. */ #define PXP_CTRL_SET_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK) -#define PXP_CTRL_SET_RSVD3_MASK (0xF000000U) -#define PXP_CTRL_SET_RSVD3_SHIFT (24U) -#define PXP_CTRL_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD3_SHIFT)) & PXP_CTRL_SET_RSVD3_MASK) + #define PXP_CTRL_SET_EN_REPEAT_MASK (0x10000000U) #define PXP_CTRL_SET_EN_REPEAT_SHIFT (28U) +/*! EN_REPEAT + * 0b1..PXP will repeat based on the current configuration register settings + * 0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed + */ #define PXP_CTRL_SET_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_EN_REPEAT_SHIFT)) & PXP_CTRL_SET_EN_REPEAT_MASK) -#define PXP_CTRL_SET_RSVD4_MASK (0x20000000U) -#define PXP_CTRL_SET_RSVD4_SHIFT (29U) -#define PXP_CTRL_SET_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_RSVD4_SHIFT)) & PXP_CTRL_SET_RSVD4_MASK) + #define PXP_CTRL_SET_CLKGATE_MASK (0x40000000U) #define PXP_CTRL_SET_CLKGATE_SHIFT (30U) +/*! CLKGATE + * 0b0..Normal operation + * 0b1..All clocks to PXP is gated-off + */ #define PXP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK) + #define PXP_CTRL_SET_SFTRST_MASK (0x80000000U) #define PXP_CTRL_SET_SFTRST_SHIFT (31U) +/*! SFTRST + * 0b0..Normal PXP operation is enabled + * 0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value. + */ #define PXP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK) /*! @} */ /*! @name CTRL_CLR - Control Register 0 */ /*! @{ */ + #define PXP_CTRL_CLR_ENABLE_MASK (0x1U) #define PXP_CTRL_CLR_ENABLE_SHIFT (0U) +/*! ENABLE + * 0b1..PXP is enabled + * 0b0..PXP is disabled + */ #define PXP_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK) + #define PXP_CTRL_CLR_IRQ_ENABLE_MASK (0x2U) #define PXP_CTRL_CLR_IRQ_ENABLE_SHIFT (1U) +/*! IRQ_ENABLE + * 0b1..PXP interrupt is enabled + * 0b0..PXP interrupt is disabled + */ #define PXP_CTRL_CLR_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK) + #define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK (0x4U) #define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT (2U) +/*! NEXT_IRQ_ENABLE + * 0b0..Disabled + * 0b1..Enabled + */ #define PXP_CTRL_CLR_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK) + #define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK (0x10U) #define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT (4U) #define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK) -#define PXP_CTRL_CLR_RSVD0_MASK (0xE0U) -#define PXP_CTRL_CLR_RSVD0_SHIFT (5U) -#define PXP_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD0_SHIFT)) & PXP_CTRL_CLR_RSVD0_MASK) + #define PXP_CTRL_CLR_ROTATE_MASK (0x300U) #define PXP_CTRL_CLR_ROTATE_SHIFT (8U) /*! ROTATE @@ -71753,18 +80741,27 @@ typedef struct { * 0b11..ROT_270 */ #define PXP_CTRL_CLR_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE_SHIFT)) & PXP_CTRL_CLR_ROTATE_MASK) + #define PXP_CTRL_CLR_HFLIP_MASK (0x400U) #define PXP_CTRL_CLR_HFLIP_SHIFT (10U) +/*! HFLIP + * 0b0..Horizontal Flip is disabled + * 0b1..Horizontal Flip is enabled + */ #define PXP_CTRL_CLR_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP_SHIFT)) & PXP_CTRL_CLR_HFLIP_MASK) + #define PXP_CTRL_CLR_VFLIP_MASK (0x800U) #define PXP_CTRL_CLR_VFLIP_SHIFT (11U) +/*! VFLIP + * 0b0..Vertical Flip is disabled + * 0b1..Vertical Flip is enabled + */ #define PXP_CTRL_CLR_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP_SHIFT)) & PXP_CTRL_CLR_VFLIP_MASK) -#define PXP_CTRL_CLR_RSVD1_MASK (0x3FF000U) -#define PXP_CTRL_CLR_RSVD1_SHIFT (12U) -#define PXP_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD1_SHIFT)) & PXP_CTRL_CLR_RSVD1_MASK) + #define PXP_CTRL_CLR_ROT_POS_MASK (0x400000U) #define PXP_CTRL_CLR_ROT_POS_SHIFT (22U) #define PXP_CTRL_CLR_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROT_POS_SHIFT)) & PXP_CTRL_CLR_ROT_POS_MASK) + #define PXP_CTRL_CLR_BLOCK_SIZE_MASK (0x800000U) #define PXP_CTRL_CLR_BLOCK_SIZE_SHIFT (23U) /*! BLOCK_SIZE @@ -71772,40 +80769,63 @@ typedef struct { * 0b1..Process 16x16 pixel blocks. */ #define PXP_CTRL_CLR_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK) -#define PXP_CTRL_CLR_RSVD3_MASK (0xF000000U) -#define PXP_CTRL_CLR_RSVD3_SHIFT (24U) -#define PXP_CTRL_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD3_SHIFT)) & PXP_CTRL_CLR_RSVD3_MASK) + #define PXP_CTRL_CLR_EN_REPEAT_MASK (0x10000000U) #define PXP_CTRL_CLR_EN_REPEAT_SHIFT (28U) +/*! EN_REPEAT + * 0b1..PXP will repeat based on the current configuration register settings + * 0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed + */ #define PXP_CTRL_CLR_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_EN_REPEAT_SHIFT)) & PXP_CTRL_CLR_EN_REPEAT_MASK) -#define PXP_CTRL_CLR_RSVD4_MASK (0x20000000U) -#define PXP_CTRL_CLR_RSVD4_SHIFT (29U) -#define PXP_CTRL_CLR_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_RSVD4_SHIFT)) & PXP_CTRL_CLR_RSVD4_MASK) + #define PXP_CTRL_CLR_CLKGATE_MASK (0x40000000U) #define PXP_CTRL_CLR_CLKGATE_SHIFT (30U) +/*! CLKGATE + * 0b0..Normal operation + * 0b1..All clocks to PXP is gated-off + */ #define PXP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK) + #define PXP_CTRL_CLR_SFTRST_MASK (0x80000000U) #define PXP_CTRL_CLR_SFTRST_SHIFT (31U) +/*! SFTRST + * 0b0..Normal PXP operation is enabled + * 0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value. + */ #define PXP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK) /*! @} */ /*! @name CTRL_TOG - Control Register 0 */ /*! @{ */ + #define PXP_CTRL_TOG_ENABLE_MASK (0x1U) #define PXP_CTRL_TOG_ENABLE_SHIFT (0U) +/*! ENABLE + * 0b1..PXP is enabled + * 0b0..PXP is disabled + */ #define PXP_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK) + #define PXP_CTRL_TOG_IRQ_ENABLE_MASK (0x2U) #define PXP_CTRL_TOG_IRQ_ENABLE_SHIFT (1U) +/*! IRQ_ENABLE + * 0b1..PXP interrupt is enabled + * 0b0..PXP interrupt is disabled + */ #define PXP_CTRL_TOG_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK) + #define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK (0x4U) #define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT (2U) +/*! NEXT_IRQ_ENABLE + * 0b0..Disabled + * 0b1..Enabled + */ #define PXP_CTRL_TOG_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK) + #define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK (0x10U) #define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT (4U) #define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK) -#define PXP_CTRL_TOG_RSVD0_MASK (0xE0U) -#define PXP_CTRL_TOG_RSVD0_SHIFT (5U) -#define PXP_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD0_SHIFT)) & PXP_CTRL_TOG_RSVD0_MASK) + #define PXP_CTRL_TOG_ROTATE_MASK (0x300U) #define PXP_CTRL_TOG_ROTATE_SHIFT (8U) /*! ROTATE @@ -71815,18 +80835,27 @@ typedef struct { * 0b11..ROT_270 */ #define PXP_CTRL_TOG_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE_SHIFT)) & PXP_CTRL_TOG_ROTATE_MASK) + #define PXP_CTRL_TOG_HFLIP_MASK (0x400U) #define PXP_CTRL_TOG_HFLIP_SHIFT (10U) +/*! HFLIP + * 0b0..Horizontal Flip is disabled + * 0b1..Horizontal Flip is enabled + */ #define PXP_CTRL_TOG_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP_SHIFT)) & PXP_CTRL_TOG_HFLIP_MASK) + #define PXP_CTRL_TOG_VFLIP_MASK (0x800U) #define PXP_CTRL_TOG_VFLIP_SHIFT (11U) +/*! VFLIP + * 0b0..Vertical Flip is disabled + * 0b1..Vertical Flip is enabled + */ #define PXP_CTRL_TOG_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP_SHIFT)) & PXP_CTRL_TOG_VFLIP_MASK) -#define PXP_CTRL_TOG_RSVD1_MASK (0x3FF000U) -#define PXP_CTRL_TOG_RSVD1_SHIFT (12U) -#define PXP_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD1_SHIFT)) & PXP_CTRL_TOG_RSVD1_MASK) + #define PXP_CTRL_TOG_ROT_POS_MASK (0x400000U) #define PXP_CTRL_TOG_ROT_POS_SHIFT (22U) #define PXP_CTRL_TOG_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROT_POS_SHIFT)) & PXP_CTRL_TOG_ROT_POS_MASK) + #define PXP_CTRL_TOG_BLOCK_SIZE_MASK (0x800000U) #define PXP_CTRL_TOG_BLOCK_SIZE_SHIFT (23U) /*! BLOCK_SIZE @@ -71834,49 +80863,79 @@ typedef struct { * 0b1..Process 16x16 pixel blocks. */ #define PXP_CTRL_TOG_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK) -#define PXP_CTRL_TOG_RSVD3_MASK (0xF000000U) -#define PXP_CTRL_TOG_RSVD3_SHIFT (24U) -#define PXP_CTRL_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD3_SHIFT)) & PXP_CTRL_TOG_RSVD3_MASK) + #define PXP_CTRL_TOG_EN_REPEAT_MASK (0x10000000U) #define PXP_CTRL_TOG_EN_REPEAT_SHIFT (28U) +/*! EN_REPEAT + * 0b1..PXP will repeat based on the current configuration register settings + * 0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed + */ #define PXP_CTRL_TOG_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_EN_REPEAT_SHIFT)) & PXP_CTRL_TOG_EN_REPEAT_MASK) -#define PXP_CTRL_TOG_RSVD4_MASK (0x20000000U) -#define PXP_CTRL_TOG_RSVD4_SHIFT (29U) -#define PXP_CTRL_TOG_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_RSVD4_SHIFT)) & PXP_CTRL_TOG_RSVD4_MASK) + #define PXP_CTRL_TOG_CLKGATE_MASK (0x40000000U) #define PXP_CTRL_TOG_CLKGATE_SHIFT (30U) +/*! CLKGATE + * 0b0..Normal operation + * 0b1..All clocks to PXP is gated-off + */ #define PXP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK) + #define PXP_CTRL_TOG_SFTRST_MASK (0x80000000U) #define PXP_CTRL_TOG_SFTRST_SHIFT (31U) +/*! SFTRST + * 0b0..Normal PXP operation is enabled + * 0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value. + */ #define PXP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK) /*! @} */ /*! @name STAT - Status Register */ /*! @{ */ + #define PXP_STAT_IRQ_MASK (0x1U) #define PXP_STAT_IRQ_SHIFT (0U) +/*! IRQ + * 0b0..No interrupt + * 0b1..Interrupt generated + */ #define PXP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ_SHIFT)) & PXP_STAT_IRQ_MASK) + #define PXP_STAT_AXI_WRITE_ERROR_MASK (0x2U) #define PXP_STAT_AXI_WRITE_ERROR_SHIFT (1U) +/*! AXI_WRITE_ERROR + * 0b0..AXI write is normal + * 0b1..AXI write error has occurred + */ #define PXP_STAT_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_MASK) + #define PXP_STAT_AXI_READ_ERROR_MASK (0x4U) #define PXP_STAT_AXI_READ_ERROR_SHIFT (2U) +/*! AXI_READ_ERROR + * 0b0..AXI read is normal + * 0b1..AXI read error has occurred + */ #define PXP_STAT_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_SHIFT)) & PXP_STAT_AXI_READ_ERROR_MASK) + #define PXP_STAT_NEXT_IRQ_MASK (0x8U) #define PXP_STAT_NEXT_IRQ_SHIFT (3U) #define PXP_STAT_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_NEXT_IRQ_SHIFT)) & PXP_STAT_NEXT_IRQ_MASK) + #define PXP_STAT_AXI_ERROR_ID_MASK (0xF0U) #define PXP_STAT_AXI_ERROR_ID_SHIFT (4U) #define PXP_STAT_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_SHIFT)) & PXP_STAT_AXI_ERROR_ID_MASK) + #define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) #define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +/*! LUT_DMA_LOAD_DONE_IRQ + * 0b0..LUT DMA LOAD transfer is active + * 0b1..LUT DMA LOAD transfer is complete + */ #define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK) -#define PXP_STAT_RSVD2_MASK (0xFE00U) -#define PXP_STAT_RSVD2_SHIFT (9U) -#define PXP_STAT_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_RSVD2_SHIFT)) & PXP_STAT_RSVD2_MASK) + #define PXP_STAT_BLOCKY_MASK (0xFF0000U) #define PXP_STAT_BLOCKY_SHIFT (16U) #define PXP_STAT_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKY_SHIFT)) & PXP_STAT_BLOCKY_MASK) + #define PXP_STAT_BLOCKX_MASK (0xFF000000U) #define PXP_STAT_BLOCKX_SHIFT (24U) #define PXP_STAT_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK) @@ -71884,30 +80943,51 @@ typedef struct { /*! @name STAT_SET - Status Register */ /*! @{ */ + #define PXP_STAT_SET_IRQ_MASK (0x1U) #define PXP_STAT_SET_IRQ_SHIFT (0U) +/*! IRQ + * 0b0..No interrupt + * 0b1..Interrupt generated + */ #define PXP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ_SHIFT)) & PXP_STAT_SET_IRQ_MASK) + #define PXP_STAT_SET_AXI_WRITE_ERROR_MASK (0x2U) #define PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT (1U) +/*! AXI_WRITE_ERROR + * 0b0..AXI write is normal + * 0b1..AXI write error has occurred + */ #define PXP_STAT_SET_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_MASK) + #define PXP_STAT_SET_AXI_READ_ERROR_MASK (0x4U) #define PXP_STAT_SET_AXI_READ_ERROR_SHIFT (2U) +/*! AXI_READ_ERROR + * 0b0..AXI read is normal + * 0b1..AXI read error has occurred + */ #define PXP_STAT_SET_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_MASK) + #define PXP_STAT_SET_NEXT_IRQ_MASK (0x8U) #define PXP_STAT_SET_NEXT_IRQ_SHIFT (3U) #define PXP_STAT_SET_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_NEXT_IRQ_SHIFT)) & PXP_STAT_SET_NEXT_IRQ_MASK) + #define PXP_STAT_SET_AXI_ERROR_ID_MASK (0xF0U) #define PXP_STAT_SET_AXI_ERROR_ID_SHIFT (4U) #define PXP_STAT_SET_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_MASK) + #define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) #define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +/*! LUT_DMA_LOAD_DONE_IRQ + * 0b0..LUT DMA LOAD transfer is active + * 0b1..LUT DMA LOAD transfer is complete + */ #define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK) -#define PXP_STAT_SET_RSVD2_MASK (0xFE00U) -#define PXP_STAT_SET_RSVD2_SHIFT (9U) -#define PXP_STAT_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_RSVD2_SHIFT)) & PXP_STAT_SET_RSVD2_MASK) + #define PXP_STAT_SET_BLOCKY_MASK (0xFF0000U) #define PXP_STAT_SET_BLOCKY_SHIFT (16U) #define PXP_STAT_SET_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKY_SHIFT)) & PXP_STAT_SET_BLOCKY_MASK) + #define PXP_STAT_SET_BLOCKX_MASK (0xFF000000U) #define PXP_STAT_SET_BLOCKX_SHIFT (24U) #define PXP_STAT_SET_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK) @@ -71915,30 +80995,51 @@ typedef struct { /*! @name STAT_CLR - Status Register */ /*! @{ */ + #define PXP_STAT_CLR_IRQ_MASK (0x1U) #define PXP_STAT_CLR_IRQ_SHIFT (0U) +/*! IRQ + * 0b0..No interrupt + * 0b1..Interrupt generated + */ #define PXP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ_SHIFT)) & PXP_STAT_CLR_IRQ_MASK) + #define PXP_STAT_CLR_AXI_WRITE_ERROR_MASK (0x2U) #define PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT (1U) +/*! AXI_WRITE_ERROR + * 0b0..AXI write is normal + * 0b1..AXI write error has occurred + */ #define PXP_STAT_CLR_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_MASK) + #define PXP_STAT_CLR_AXI_READ_ERROR_MASK (0x4U) #define PXP_STAT_CLR_AXI_READ_ERROR_SHIFT (2U) +/*! AXI_READ_ERROR + * 0b0..AXI read is normal + * 0b1..AXI read error has occurred + */ #define PXP_STAT_CLR_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_MASK) + #define PXP_STAT_CLR_NEXT_IRQ_MASK (0x8U) #define PXP_STAT_CLR_NEXT_IRQ_SHIFT (3U) #define PXP_STAT_CLR_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_NEXT_IRQ_SHIFT)) & PXP_STAT_CLR_NEXT_IRQ_MASK) + #define PXP_STAT_CLR_AXI_ERROR_ID_MASK (0xF0U) #define PXP_STAT_CLR_AXI_ERROR_ID_SHIFT (4U) #define PXP_STAT_CLR_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_MASK) + #define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) #define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +/*! LUT_DMA_LOAD_DONE_IRQ + * 0b0..LUT DMA LOAD transfer is active + * 0b1..LUT DMA LOAD transfer is complete + */ #define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK) -#define PXP_STAT_CLR_RSVD2_MASK (0xFE00U) -#define PXP_STAT_CLR_RSVD2_SHIFT (9U) -#define PXP_STAT_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_RSVD2_SHIFT)) & PXP_STAT_CLR_RSVD2_MASK) + #define PXP_STAT_CLR_BLOCKY_MASK (0xFF0000U) #define PXP_STAT_CLR_BLOCKY_SHIFT (16U) #define PXP_STAT_CLR_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKY_SHIFT)) & PXP_STAT_CLR_BLOCKY_MASK) + #define PXP_STAT_CLR_BLOCKX_MASK (0xFF000000U) #define PXP_STAT_CLR_BLOCKX_SHIFT (24U) #define PXP_STAT_CLR_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK) @@ -71946,30 +81047,51 @@ typedef struct { /*! @name STAT_TOG - Status Register */ /*! @{ */ + #define PXP_STAT_TOG_IRQ_MASK (0x1U) #define PXP_STAT_TOG_IRQ_SHIFT (0U) +/*! IRQ + * 0b0..No interrupt + * 0b1..Interrupt generated + */ #define PXP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ_SHIFT)) & PXP_STAT_TOG_IRQ_MASK) + #define PXP_STAT_TOG_AXI_WRITE_ERROR_MASK (0x2U) #define PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT (1U) +/*! AXI_WRITE_ERROR + * 0b0..AXI write is normal + * 0b1..AXI write error has occurred + */ #define PXP_STAT_TOG_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_MASK) + #define PXP_STAT_TOG_AXI_READ_ERROR_MASK (0x4U) #define PXP_STAT_TOG_AXI_READ_ERROR_SHIFT (2U) +/*! AXI_READ_ERROR + * 0b0..AXI read is normal + * 0b1..AXI read error has occurred + */ #define PXP_STAT_TOG_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_MASK) + #define PXP_STAT_TOG_NEXT_IRQ_MASK (0x8U) #define PXP_STAT_TOG_NEXT_IRQ_SHIFT (3U) #define PXP_STAT_TOG_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_NEXT_IRQ_SHIFT)) & PXP_STAT_TOG_NEXT_IRQ_MASK) + #define PXP_STAT_TOG_AXI_ERROR_ID_MASK (0xF0U) #define PXP_STAT_TOG_AXI_ERROR_ID_SHIFT (4U) #define PXP_STAT_TOG_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_MASK) + #define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U) #define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U) +/*! LUT_DMA_LOAD_DONE_IRQ + * 0b0..LUT DMA LOAD transfer is active + * 0b1..LUT DMA LOAD transfer is complete + */ #define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK) -#define PXP_STAT_TOG_RSVD2_MASK (0xFE00U) -#define PXP_STAT_TOG_RSVD2_SHIFT (9U) -#define PXP_STAT_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_RSVD2_SHIFT)) & PXP_STAT_TOG_RSVD2_MASK) + #define PXP_STAT_TOG_BLOCKY_MASK (0xFF0000U) #define PXP_STAT_TOG_BLOCKY_SHIFT (16U) #define PXP_STAT_TOG_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKY_SHIFT)) & PXP_STAT_TOG_BLOCKY_MASK) + #define PXP_STAT_TOG_BLOCKX_MASK (0xFF000000U) #define PXP_STAT_TOG_BLOCKX_SHIFT (24U) #define PXP_STAT_TOG_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK) @@ -71977,6 +81099,7 @@ typedef struct { /*! @name OUT_CTRL - Output Buffer Control Register */ /*! @{ */ + #define PXP_OUT_CTRL_FORMAT_MASK (0x1FU) #define PXP_OUT_CTRL_FORMAT_SHIFT (0U) /*! FORMAT @@ -71999,9 +81122,7 @@ typedef struct { * 0b11011..16-bit pixels (2-plane VU) */ #define PXP_OUT_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK) -#define PXP_OUT_CTRL_RSVD0_MASK (0xE0U) -#define PXP_OUT_CTRL_RSVD0_SHIFT (5U) -#define PXP_OUT_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_RSVD0_SHIFT)) & PXP_OUT_CTRL_RSVD0_MASK) + #define PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK (0x300U) #define PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT (8U) /*! INTERLACED_OUTPUT @@ -72011,12 +81132,15 @@ typedef struct { * 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2. */ #define PXP_OUT_CTRL_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK) -#define PXP_OUT_CTRL_RSVD1_MASK (0x7FFC00U) -#define PXP_OUT_CTRL_RSVD1_SHIFT (10U) -#define PXP_OUT_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_RSVD1_SHIFT)) & PXP_OUT_CTRL_RSVD1_MASK) + #define PXP_OUT_CTRL_ALPHA_OUTPUT_MASK (0x800000U) #define PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT (23U) +/*! ALPHA_OUTPUT + * 0b0..Retain + * 0b1..Overwritten + */ #define PXP_OUT_CTRL_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK) + #define PXP_OUT_CTRL_ALPHA_MASK (0xFF000000U) #define PXP_OUT_CTRL_ALPHA_SHIFT (24U) #define PXP_OUT_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK) @@ -72024,6 +81148,7 @@ typedef struct { /*! @name OUT_CTRL_SET - Output Buffer Control Register */ /*! @{ */ + #define PXP_OUT_CTRL_SET_FORMAT_MASK (0x1FU) #define PXP_OUT_CTRL_SET_FORMAT_SHIFT (0U) /*! FORMAT @@ -72046,9 +81171,7 @@ typedef struct { * 0b11011..16-bit pixels (2-plane VU) */ #define PXP_OUT_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK) -#define PXP_OUT_CTRL_SET_RSVD0_MASK (0xE0U) -#define PXP_OUT_CTRL_SET_RSVD0_SHIFT (5U) -#define PXP_OUT_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_RSVD0_SHIFT)) & PXP_OUT_CTRL_SET_RSVD0_MASK) + #define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK (0x300U) #define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U) /*! INTERLACED_OUTPUT @@ -72058,12 +81181,15 @@ typedef struct { * 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2. */ #define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK) -#define PXP_OUT_CTRL_SET_RSVD1_MASK (0x7FFC00U) -#define PXP_OUT_CTRL_SET_RSVD1_SHIFT (10U) -#define PXP_OUT_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_RSVD1_SHIFT)) & PXP_OUT_CTRL_SET_RSVD1_MASK) + #define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK (0x800000U) #define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT (23U) +/*! ALPHA_OUTPUT + * 0b0..Retain + * 0b1..Overwritten + */ #define PXP_OUT_CTRL_SET_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK) + #define PXP_OUT_CTRL_SET_ALPHA_MASK (0xFF000000U) #define PXP_OUT_CTRL_SET_ALPHA_SHIFT (24U) #define PXP_OUT_CTRL_SET_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK) @@ -72071,6 +81197,7 @@ typedef struct { /*! @name OUT_CTRL_CLR - Output Buffer Control Register */ /*! @{ */ + #define PXP_OUT_CTRL_CLR_FORMAT_MASK (0x1FU) #define PXP_OUT_CTRL_CLR_FORMAT_SHIFT (0U) /*! FORMAT @@ -72093,9 +81220,7 @@ typedef struct { * 0b11011..16-bit pixels (2-plane VU) */ #define PXP_OUT_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK) -#define PXP_OUT_CTRL_CLR_RSVD0_MASK (0xE0U) -#define PXP_OUT_CTRL_CLR_RSVD0_SHIFT (5U) -#define PXP_OUT_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_RSVD0_SHIFT)) & PXP_OUT_CTRL_CLR_RSVD0_MASK) + #define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK (0x300U) #define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U) /*! INTERLACED_OUTPUT @@ -72105,12 +81230,15 @@ typedef struct { * 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2. */ #define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK) -#define PXP_OUT_CTRL_CLR_RSVD1_MASK (0x7FFC00U) -#define PXP_OUT_CTRL_CLR_RSVD1_SHIFT (10U) -#define PXP_OUT_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_RSVD1_SHIFT)) & PXP_OUT_CTRL_CLR_RSVD1_MASK) + #define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK (0x800000U) #define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT (23U) +/*! ALPHA_OUTPUT + * 0b0..Retain + * 0b1..Overwritten + */ #define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK) + #define PXP_OUT_CTRL_CLR_ALPHA_MASK (0xFF000000U) #define PXP_OUT_CTRL_CLR_ALPHA_SHIFT (24U) #define PXP_OUT_CTRL_CLR_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK) @@ -72118,6 +81246,7 @@ typedef struct { /*! @name OUT_CTRL_TOG - Output Buffer Control Register */ /*! @{ */ + #define PXP_OUT_CTRL_TOG_FORMAT_MASK (0x1FU) #define PXP_OUT_CTRL_TOG_FORMAT_SHIFT (0U) /*! FORMAT @@ -72140,9 +81269,7 @@ typedef struct { * 0b11011..16-bit pixels (2-plane VU) */ #define PXP_OUT_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK) -#define PXP_OUT_CTRL_TOG_RSVD0_MASK (0xE0U) -#define PXP_OUT_CTRL_TOG_RSVD0_SHIFT (5U) -#define PXP_OUT_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_RSVD0_SHIFT)) & PXP_OUT_CTRL_TOG_RSVD0_MASK) + #define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK (0x300U) #define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U) /*! INTERLACED_OUTPUT @@ -72152,12 +81279,15 @@ typedef struct { * 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2. */ #define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK) -#define PXP_OUT_CTRL_TOG_RSVD1_MASK (0x7FFC00U) -#define PXP_OUT_CTRL_TOG_RSVD1_SHIFT (10U) -#define PXP_OUT_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_RSVD1_SHIFT)) & PXP_OUT_CTRL_TOG_RSVD1_MASK) + #define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK (0x800000U) #define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT (23U) +/*! ALPHA_OUTPUT + * 0b0..Retain + * 0b1..Overwritten + */ #define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK) + #define PXP_OUT_CTRL_TOG_ALPHA_MASK (0xFF000000U) #define PXP_OUT_CTRL_TOG_ALPHA_SHIFT (24U) #define PXP_OUT_CTRL_TOG_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK) @@ -72165,6 +81295,7 @@ typedef struct { /*! @name OUT_BUF - Output Frame Buffer Pointer */ /*! @{ */ + #define PXP_OUT_BUF_ADDR_MASK (0xFFFFFFFFU) #define PXP_OUT_BUF_ADDR_SHIFT (0U) #define PXP_OUT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF_ADDR_SHIFT)) & PXP_OUT_BUF_ADDR_MASK) @@ -72172,6 +81303,7 @@ typedef struct { /*! @name OUT_BUF2 - Output Frame Buffer Pointer #2 */ /*! @{ */ + #define PXP_OUT_BUF2_ADDR_MASK (0xFFFFFFFFU) #define PXP_OUT_BUF2_ADDR_SHIFT (0U) #define PXP_OUT_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF2_ADDR_SHIFT)) & PXP_OUT_BUF2_ADDR_MASK) @@ -72179,96 +81311,75 @@ typedef struct { /*! @name OUT_PITCH - Output Buffer Pitch */ /*! @{ */ + #define PXP_OUT_PITCH_PITCH_MASK (0xFFFFU) #define PXP_OUT_PITCH_PITCH_SHIFT (0U) #define PXP_OUT_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_PITCH_SHIFT)) & PXP_OUT_PITCH_PITCH_MASK) -#define PXP_OUT_PITCH_RSVD_MASK (0xFFFF0000U) -#define PXP_OUT_PITCH_RSVD_SHIFT (16U) -#define PXP_OUT_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_RSVD_SHIFT)) & PXP_OUT_PITCH_RSVD_MASK) /*! @} */ /*! @name OUT_LRC - Output Surface Lower Right Coordinate */ /*! @{ */ + #define PXP_OUT_LRC_Y_MASK (0x3FFFU) #define PXP_OUT_LRC_Y_SHIFT (0U) #define PXP_OUT_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_Y_SHIFT)) & PXP_OUT_LRC_Y_MASK) -#define PXP_OUT_LRC_RSVD0_MASK (0xC000U) -#define PXP_OUT_LRC_RSVD0_SHIFT (14U) -#define PXP_OUT_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_RSVD0_SHIFT)) & PXP_OUT_LRC_RSVD0_MASK) + #define PXP_OUT_LRC_X_MASK (0x3FFF0000U) #define PXP_OUT_LRC_X_SHIFT (16U) #define PXP_OUT_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_X_SHIFT)) & PXP_OUT_LRC_X_MASK) -#define PXP_OUT_LRC_RSVD1_MASK (0xC0000000U) -#define PXP_OUT_LRC_RSVD1_SHIFT (30U) -#define PXP_OUT_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_RSVD1_SHIFT)) & PXP_OUT_LRC_RSVD1_MASK) /*! @} */ /*! @name OUT_PS_ULC - Processed Surface Upper Left Coordinate */ /*! @{ */ + #define PXP_OUT_PS_ULC_Y_MASK (0x3FFFU) #define PXP_OUT_PS_ULC_Y_SHIFT (0U) #define PXP_OUT_PS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_Y_SHIFT)) & PXP_OUT_PS_ULC_Y_MASK) -#define PXP_OUT_PS_ULC_RSVD0_MASK (0xC000U) -#define PXP_OUT_PS_ULC_RSVD0_SHIFT (14U) -#define PXP_OUT_PS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_RSVD0_SHIFT)) & PXP_OUT_PS_ULC_RSVD0_MASK) + #define PXP_OUT_PS_ULC_X_MASK (0x3FFF0000U) #define PXP_OUT_PS_ULC_X_SHIFT (16U) #define PXP_OUT_PS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_X_SHIFT)) & PXP_OUT_PS_ULC_X_MASK) -#define PXP_OUT_PS_ULC_RSVD1_MASK (0xC0000000U) -#define PXP_OUT_PS_ULC_RSVD1_SHIFT (30U) -#define PXP_OUT_PS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_RSVD1_SHIFT)) & PXP_OUT_PS_ULC_RSVD1_MASK) /*! @} */ /*! @name OUT_PS_LRC - Processed Surface Lower Right Coordinate */ /*! @{ */ + #define PXP_OUT_PS_LRC_Y_MASK (0x3FFFU) #define PXP_OUT_PS_LRC_Y_SHIFT (0U) #define PXP_OUT_PS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_Y_SHIFT)) & PXP_OUT_PS_LRC_Y_MASK) -#define PXP_OUT_PS_LRC_RSVD0_MASK (0xC000U) -#define PXP_OUT_PS_LRC_RSVD0_SHIFT (14U) -#define PXP_OUT_PS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_RSVD0_SHIFT)) & PXP_OUT_PS_LRC_RSVD0_MASK) + #define PXP_OUT_PS_LRC_X_MASK (0x3FFF0000U) #define PXP_OUT_PS_LRC_X_SHIFT (16U) #define PXP_OUT_PS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_X_SHIFT)) & PXP_OUT_PS_LRC_X_MASK) -#define PXP_OUT_PS_LRC_RSVD1_MASK (0xC0000000U) -#define PXP_OUT_PS_LRC_RSVD1_SHIFT (30U) -#define PXP_OUT_PS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_RSVD1_SHIFT)) & PXP_OUT_PS_LRC_RSVD1_MASK) /*! @} */ /*! @name OUT_AS_ULC - Alpha Surface Upper Left Coordinate */ /*! @{ */ + #define PXP_OUT_AS_ULC_Y_MASK (0x3FFFU) #define PXP_OUT_AS_ULC_Y_SHIFT (0U) #define PXP_OUT_AS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_Y_SHIFT)) & PXP_OUT_AS_ULC_Y_MASK) -#define PXP_OUT_AS_ULC_RSVD0_MASK (0xC000U) -#define PXP_OUT_AS_ULC_RSVD0_SHIFT (14U) -#define PXP_OUT_AS_ULC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_RSVD0_SHIFT)) & PXP_OUT_AS_ULC_RSVD0_MASK) + #define PXP_OUT_AS_ULC_X_MASK (0x3FFF0000U) #define PXP_OUT_AS_ULC_X_SHIFT (16U) #define PXP_OUT_AS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_X_SHIFT)) & PXP_OUT_AS_ULC_X_MASK) -#define PXP_OUT_AS_ULC_RSVD1_MASK (0xC0000000U) -#define PXP_OUT_AS_ULC_RSVD1_SHIFT (30U) -#define PXP_OUT_AS_ULC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_RSVD1_SHIFT)) & PXP_OUT_AS_ULC_RSVD1_MASK) /*! @} */ /*! @name OUT_AS_LRC - Alpha Surface Lower Right Coordinate */ /*! @{ */ + #define PXP_OUT_AS_LRC_Y_MASK (0x3FFFU) #define PXP_OUT_AS_LRC_Y_SHIFT (0U) #define PXP_OUT_AS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_Y_SHIFT)) & PXP_OUT_AS_LRC_Y_MASK) -#define PXP_OUT_AS_LRC_RSVD0_MASK (0xC000U) -#define PXP_OUT_AS_LRC_RSVD0_SHIFT (14U) -#define PXP_OUT_AS_LRC_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_RSVD0_SHIFT)) & PXP_OUT_AS_LRC_RSVD0_MASK) + #define PXP_OUT_AS_LRC_X_MASK (0x3FFF0000U) #define PXP_OUT_AS_LRC_X_SHIFT (16U) #define PXP_OUT_AS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_X_SHIFT)) & PXP_OUT_AS_LRC_X_MASK) -#define PXP_OUT_AS_LRC_RSVD1_MASK (0xC0000000U) -#define PXP_OUT_AS_LRC_RSVD1_SHIFT (30U) -#define PXP_OUT_AS_LRC_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_RSVD1_SHIFT)) & PXP_OUT_AS_LRC_RSVD1_MASK) /*! @} */ /*! @name PS_CTRL - Processed Surface (PS) Control Register */ /*! @{ */ + #define PXP_PS_CTRL_FORMAT_MASK (0x3FU) #define PXP_PS_CTRL_FORMAT_SHIFT (0U) /*! FORMAT @@ -72292,12 +81403,15 @@ typedef struct { * 0b101101..16-bit pixels with alpha at the low 4 bits */ #define PXP_PS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK) + #define PXP_PS_CTRL_WB_SWAP_MASK (0x40U) #define PXP_PS_CTRL_WB_SWAP_SHIFT (6U) +/*! WB_SWAP + * 0b0..Byte swap is disabled + * 0b1..Byte swap is enabled + */ #define PXP_PS_CTRL_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK) -#define PXP_PS_CTRL_RSVD0_MASK (0x80U) -#define PXP_PS_CTRL_RSVD0_SHIFT (7U) -#define PXP_PS_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_RSVD0_SHIFT)) & PXP_PS_CTRL_RSVD0_MASK) + #define PXP_PS_CTRL_DECY_MASK (0x300U) #define PXP_PS_CTRL_DECY_SHIFT (8U) /*! DECY @@ -72307,6 +81421,7 @@ typedef struct { * 0b11..Decimate PS by 8. */ #define PXP_PS_CTRL_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK) + #define PXP_PS_CTRL_DECX_MASK (0xC00U) #define PXP_PS_CTRL_DECX_SHIFT (10U) /*! DECX @@ -72316,13 +81431,11 @@ typedef struct { * 0b11..Decimate PS by 8. */ #define PXP_PS_CTRL_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK) -#define PXP_PS_CTRL_RSVD1_MASK (0xFFFFF000U) -#define PXP_PS_CTRL_RSVD1_SHIFT (12U) -#define PXP_PS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_RSVD1_SHIFT)) & PXP_PS_CTRL_RSVD1_MASK) /*! @} */ /*! @name PS_CTRL_SET - Processed Surface (PS) Control Register */ /*! @{ */ + #define PXP_PS_CTRL_SET_FORMAT_MASK (0x3FU) #define PXP_PS_CTRL_SET_FORMAT_SHIFT (0U) /*! FORMAT @@ -72346,12 +81459,15 @@ typedef struct { * 0b101101..16-bit pixels with alpha at the low 4 bits */ #define PXP_PS_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK) + #define PXP_PS_CTRL_SET_WB_SWAP_MASK (0x40U) #define PXP_PS_CTRL_SET_WB_SWAP_SHIFT (6U) +/*! WB_SWAP + * 0b0..Byte swap is disabled + * 0b1..Byte swap is enabled + */ #define PXP_PS_CTRL_SET_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK) -#define PXP_PS_CTRL_SET_RSVD0_MASK (0x80U) -#define PXP_PS_CTRL_SET_RSVD0_SHIFT (7U) -#define PXP_PS_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_RSVD0_SHIFT)) & PXP_PS_CTRL_SET_RSVD0_MASK) + #define PXP_PS_CTRL_SET_DECY_MASK (0x300U) #define PXP_PS_CTRL_SET_DECY_SHIFT (8U) /*! DECY @@ -72361,6 +81477,7 @@ typedef struct { * 0b11..Decimate PS by 8. */ #define PXP_PS_CTRL_SET_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK) + #define PXP_PS_CTRL_SET_DECX_MASK (0xC00U) #define PXP_PS_CTRL_SET_DECX_SHIFT (10U) /*! DECX @@ -72370,13 +81487,11 @@ typedef struct { * 0b11..Decimate PS by 8. */ #define PXP_PS_CTRL_SET_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK) -#define PXP_PS_CTRL_SET_RSVD1_MASK (0xFFFFF000U) -#define PXP_PS_CTRL_SET_RSVD1_SHIFT (12U) -#define PXP_PS_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_RSVD1_SHIFT)) & PXP_PS_CTRL_SET_RSVD1_MASK) /*! @} */ /*! @name PS_CTRL_CLR - Processed Surface (PS) Control Register */ /*! @{ */ + #define PXP_PS_CTRL_CLR_FORMAT_MASK (0x3FU) #define PXP_PS_CTRL_CLR_FORMAT_SHIFT (0U) /*! FORMAT @@ -72400,12 +81515,15 @@ typedef struct { * 0b101101..16-bit pixels with alpha at the low 4 bits */ #define PXP_PS_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK) + #define PXP_PS_CTRL_CLR_WB_SWAP_MASK (0x40U) #define PXP_PS_CTRL_CLR_WB_SWAP_SHIFT (6U) +/*! WB_SWAP + * 0b0..Byte swap is disabled + * 0b1..Byte swap is enabled + */ #define PXP_PS_CTRL_CLR_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK) -#define PXP_PS_CTRL_CLR_RSVD0_MASK (0x80U) -#define PXP_PS_CTRL_CLR_RSVD0_SHIFT (7U) -#define PXP_PS_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_RSVD0_SHIFT)) & PXP_PS_CTRL_CLR_RSVD0_MASK) + #define PXP_PS_CTRL_CLR_DECY_MASK (0x300U) #define PXP_PS_CTRL_CLR_DECY_SHIFT (8U) /*! DECY @@ -72415,6 +81533,7 @@ typedef struct { * 0b11..Decimate PS by 8. */ #define PXP_PS_CTRL_CLR_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK) + #define PXP_PS_CTRL_CLR_DECX_MASK (0xC00U) #define PXP_PS_CTRL_CLR_DECX_SHIFT (10U) /*! DECX @@ -72424,13 +81543,11 @@ typedef struct { * 0b11..Decimate PS by 8. */ #define PXP_PS_CTRL_CLR_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK) -#define PXP_PS_CTRL_CLR_RSVD1_MASK (0xFFFFF000U) -#define PXP_PS_CTRL_CLR_RSVD1_SHIFT (12U) -#define PXP_PS_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_RSVD1_SHIFT)) & PXP_PS_CTRL_CLR_RSVD1_MASK) /*! @} */ /*! @name PS_CTRL_TOG - Processed Surface (PS) Control Register */ /*! @{ */ + #define PXP_PS_CTRL_TOG_FORMAT_MASK (0x3FU) #define PXP_PS_CTRL_TOG_FORMAT_SHIFT (0U) /*! FORMAT @@ -72454,12 +81571,15 @@ typedef struct { * 0b101101..16-bit pixels with alpha at the low 4 bits */ #define PXP_PS_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK) + #define PXP_PS_CTRL_TOG_WB_SWAP_MASK (0x40U) #define PXP_PS_CTRL_TOG_WB_SWAP_SHIFT (6U) +/*! WB_SWAP + * 0b0..Byte swap is disabled + * 0b1..Byte swap is enabled + */ #define PXP_PS_CTRL_TOG_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK) -#define PXP_PS_CTRL_TOG_RSVD0_MASK (0x80U) -#define PXP_PS_CTRL_TOG_RSVD0_SHIFT (7U) -#define PXP_PS_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_RSVD0_SHIFT)) & PXP_PS_CTRL_TOG_RSVD0_MASK) + #define PXP_PS_CTRL_TOG_DECY_MASK (0x300U) #define PXP_PS_CTRL_TOG_DECY_SHIFT (8U) /*! DECY @@ -72469,6 +81589,7 @@ typedef struct { * 0b11..Decimate PS by 8. */ #define PXP_PS_CTRL_TOG_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK) + #define PXP_PS_CTRL_TOG_DECX_MASK (0xC00U) #define PXP_PS_CTRL_TOG_DECX_SHIFT (10U) /*! DECX @@ -72478,13 +81599,11 @@ typedef struct { * 0b11..Decimate PS by 8. */ #define PXP_PS_CTRL_TOG_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK) -#define PXP_PS_CTRL_TOG_RSVD1_MASK (0xFFFFF000U) -#define PXP_PS_CTRL_TOG_RSVD1_SHIFT (12U) -#define PXP_PS_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_RSVD1_SHIFT)) & PXP_PS_CTRL_TOG_RSVD1_MASK) /*! @} */ /*! @name PS_BUF - PS Input Buffer Address */ /*! @{ */ + #define PXP_PS_BUF_ADDR_MASK (0xFFFFFFFFU) #define PXP_PS_BUF_ADDR_SHIFT (0U) #define PXP_PS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BUF_ADDR_SHIFT)) & PXP_PS_BUF_ADDR_MASK) @@ -72492,6 +81611,7 @@ typedef struct { /*! @name PS_UBUF - PS U/Cb or 2 Plane UV Input Buffer Address */ /*! @{ */ + #define PXP_PS_UBUF_ADDR_MASK (0xFFFFFFFFU) #define PXP_PS_UBUF_ADDR_SHIFT (0U) #define PXP_PS_UBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_UBUF_ADDR_SHIFT)) & PXP_PS_UBUF_ADDR_MASK) @@ -72499,6 +81619,7 @@ typedef struct { /*! @name PS_VBUF - PS V/Cr Input Buffer Address */ /*! @{ */ + #define PXP_PS_VBUF_ADDR_MASK (0xFFFFFFFFU) #define PXP_PS_VBUF_ADDR_SHIFT (0U) #define PXP_PS_VBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_VBUF_ADDR_SHIFT)) & PXP_PS_VBUF_ADDR_MASK) @@ -72506,81 +81627,63 @@ typedef struct { /*! @name PS_PITCH - Processed Surface Pitch */ /*! @{ */ + #define PXP_PS_PITCH_PITCH_MASK (0xFFFFU) #define PXP_PS_PITCH_PITCH_SHIFT (0U) #define PXP_PS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_PITCH_SHIFT)) & PXP_PS_PITCH_PITCH_MASK) -#define PXP_PS_PITCH_RSVD_MASK (0xFFFF0000U) -#define PXP_PS_PITCH_RSVD_SHIFT (16U) -#define PXP_PS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_RSVD_SHIFT)) & PXP_PS_PITCH_RSVD_MASK) /*! @} */ /*! @name PS_BACKGROUND - PS Background Color */ /*! @{ */ + #define PXP_PS_BACKGROUND_COLOR_MASK (0xFFFFFFU) #define PXP_PS_BACKGROUND_COLOR_SHIFT (0U) #define PXP_PS_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_COLOR_SHIFT)) & PXP_PS_BACKGROUND_COLOR_MASK) -#define PXP_PS_BACKGROUND_RSVD_MASK (0xFF000000U) -#define PXP_PS_BACKGROUND_RSVD_SHIFT (24U) -#define PXP_PS_BACKGROUND_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_RSVD_SHIFT)) & PXP_PS_BACKGROUND_RSVD_MASK) /*! @} */ /*! @name PS_SCALE - PS Scale Factor Register */ /*! @{ */ + #define PXP_PS_SCALE_XSCALE_MASK (0x7FFFU) #define PXP_PS_SCALE_XSCALE_SHIFT (0U) #define PXP_PS_SCALE_XSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_XSCALE_SHIFT)) & PXP_PS_SCALE_XSCALE_MASK) -#define PXP_PS_SCALE_RSVD1_MASK (0x8000U) -#define PXP_PS_SCALE_RSVD1_SHIFT (15U) -#define PXP_PS_SCALE_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_RSVD1_SHIFT)) & PXP_PS_SCALE_RSVD1_MASK) + #define PXP_PS_SCALE_YSCALE_MASK (0x7FFF0000U) #define PXP_PS_SCALE_YSCALE_SHIFT (16U) #define PXP_PS_SCALE_YSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_YSCALE_SHIFT)) & PXP_PS_SCALE_YSCALE_MASK) -#define PXP_PS_SCALE_RSVD2_MASK (0x80000000U) -#define PXP_PS_SCALE_RSVD2_SHIFT (31U) -#define PXP_PS_SCALE_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_RSVD2_SHIFT)) & PXP_PS_SCALE_RSVD2_MASK) /*! @} */ /*! @name PS_OFFSET - PS Scale Offset Register */ /*! @{ */ + #define PXP_PS_OFFSET_XOFFSET_MASK (0xFFFU) #define PXP_PS_OFFSET_XOFFSET_SHIFT (0U) #define PXP_PS_OFFSET_XOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_XOFFSET_SHIFT)) & PXP_PS_OFFSET_XOFFSET_MASK) -#define PXP_PS_OFFSET_RSVD1_MASK (0xF000U) -#define PXP_PS_OFFSET_RSVD1_SHIFT (12U) -#define PXP_PS_OFFSET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_RSVD1_SHIFT)) & PXP_PS_OFFSET_RSVD1_MASK) + #define PXP_PS_OFFSET_YOFFSET_MASK (0xFFF0000U) #define PXP_PS_OFFSET_YOFFSET_SHIFT (16U) #define PXP_PS_OFFSET_YOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_YOFFSET_SHIFT)) & PXP_PS_OFFSET_YOFFSET_MASK) -#define PXP_PS_OFFSET_RSVD2_MASK (0xF0000000U) -#define PXP_PS_OFFSET_RSVD2_SHIFT (28U) -#define PXP_PS_OFFSET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_RSVD2_SHIFT)) & PXP_PS_OFFSET_RSVD2_MASK) /*! @} */ /*! @name PS_CLRKEYLOW - PS Color Key Low */ /*! @{ */ + #define PXP_PS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU) #define PXP_PS_CLRKEYLOW_PIXEL_SHIFT (0U) #define PXP_PS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_PIXEL_MASK) -#define PXP_PS_CLRKEYLOW_RSVD1_MASK (0xFF000000U) -#define PXP_PS_CLRKEYLOW_RSVD1_SHIFT (24U) -#define PXP_PS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_RSVD1_SHIFT)) & PXP_PS_CLRKEYLOW_RSVD1_MASK) /*! @} */ /*! @name PS_CLRKEYHIGH - PS Color Key High */ /*! @{ */ + #define PXP_PS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU) #define PXP_PS_CLRKEYHIGH_PIXEL_SHIFT (0U) #define PXP_PS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_PIXEL_MASK) -#define PXP_PS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U) -#define PXP_PS_CLRKEYHIGH_RSVD1_SHIFT (24U) -#define PXP_PS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_RSVD1_SHIFT)) & PXP_PS_CLRKEYHIGH_RSVD1_MASK) /*! @} */ /*! @name AS_CTRL - Alpha Surface Control */ /*! @{ */ -#define PXP_AS_CTRL_RSVD0_MASK (0x1U) -#define PXP_AS_CTRL_RSVD0_SHIFT (0U) -#define PXP_AS_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD0_SHIFT)) & PXP_AS_CTRL_RSVD0_MASK) + #define PXP_AS_CTRL_ALPHA_CTRL_MASK (0x6U) #define PXP_AS_CTRL_ALPHA_CTRL_SHIFT (1U) /*! ALPHA_CTRL @@ -72591,9 +81694,15 @@ typedef struct { * 0b11..Enable ROPs. The ROP field indicates an operation to be performed on the alpha surface and PS pixels. */ #define PXP_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK) + #define PXP_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U) #define PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U) +/*! ENABLE_COLORKEY + * 0b0..Disabled + * 0b1..Enabled + */ #define PXP_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK) + #define PXP_AS_CTRL_FORMAT_MASK (0xF0U) #define PXP_AS_CTRL_FORMAT_SHIFT (4U) /*! FORMAT @@ -72609,9 +81718,11 @@ typedef struct { * 0b1110..16-bit pixels without alpha */ #define PXP_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK) + #define PXP_AS_CTRL_ALPHA_MASK (0xFF00U) #define PXP_AS_CTRL_ALPHA_SHIFT (8U) #define PXP_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_SHIFT)) & PXP_AS_CTRL_ALPHA_MASK) + #define PXP_AS_CTRL_ROP_MASK (0xF0000U) #define PXP_AS_CTRL_ROP_SHIFT (16U) /*! ROP @@ -72629,16 +81740,19 @@ typedef struct { * 0b1011..AS XNOR PS */ #define PXP_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK) + #define PXP_AS_CTRL_ALPHA_INVERT_MASK (0x100000U) #define PXP_AS_CTRL_ALPHA_INVERT_SHIFT (20U) +/*! ALPHA_INVERT + * 0b0..Not inverted + * 0b1..Inverted + */ #define PXP_AS_CTRL_ALPHA_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA_INVERT_MASK) -#define PXP_AS_CTRL_RSVD1_MASK (0xFFE00000U) -#define PXP_AS_CTRL_RSVD1_SHIFT (21U) -#define PXP_AS_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_RSVD1_SHIFT)) & PXP_AS_CTRL_RSVD1_MASK) /*! @} */ /*! @name AS_BUF - Alpha Surface Buffer Pointer */ /*! @{ */ + #define PXP_AS_BUF_ADDR_MASK (0xFFFFFFFFU) #define PXP_AS_BUF_ADDR_SHIFT (0U) #define PXP_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_BUF_ADDR_SHIFT)) & PXP_AS_BUF_ADDR_MASK) @@ -72646,90 +81760,83 @@ typedef struct { /*! @name AS_PITCH - Alpha Surface Pitch */ /*! @{ */ + #define PXP_AS_PITCH_PITCH_MASK (0xFFFFU) #define PXP_AS_PITCH_PITCH_SHIFT (0U) #define PXP_AS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_PITCH_SHIFT)) & PXP_AS_PITCH_PITCH_MASK) -#define PXP_AS_PITCH_RSVD_MASK (0xFFFF0000U) -#define PXP_AS_PITCH_RSVD_SHIFT (16U) -#define PXP_AS_PITCH_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_RSVD_SHIFT)) & PXP_AS_PITCH_RSVD_MASK) /*! @} */ /*! @name AS_CLRKEYLOW - Overlay Color Key Low */ /*! @{ */ + #define PXP_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU) #define PXP_AS_CLRKEYLOW_PIXEL_SHIFT (0U) #define PXP_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_PIXEL_MASK) -#define PXP_AS_CLRKEYLOW_RSVD1_MASK (0xFF000000U) -#define PXP_AS_CLRKEYLOW_RSVD1_SHIFT (24U) -#define PXP_AS_CLRKEYLOW_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_RSVD1_SHIFT)) & PXP_AS_CLRKEYLOW_RSVD1_MASK) /*! @} */ /*! @name AS_CLRKEYHIGH - Overlay Color Key High */ /*! @{ */ + #define PXP_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU) #define PXP_AS_CLRKEYHIGH_PIXEL_SHIFT (0U) #define PXP_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_PIXEL_MASK) -#define PXP_AS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U) -#define PXP_AS_CLRKEYHIGH_RSVD1_SHIFT (24U) -#define PXP_AS_CLRKEYHIGH_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_RSVD1_SHIFT)) & PXP_AS_CLRKEYHIGH_RSVD1_MASK) /*! @} */ /*! @name CSC1_COEF0 - Color Space Conversion Coefficient Register 0 */ /*! @{ */ + #define PXP_CSC1_COEF0_Y_OFFSET_MASK (0x1FFU) #define PXP_CSC1_COEF0_Y_OFFSET_SHIFT (0U) #define PXP_CSC1_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_Y_OFFSET_SHIFT)) & PXP_CSC1_COEF0_Y_OFFSET_MASK) + #define PXP_CSC1_COEF0_UV_OFFSET_MASK (0x3FE00U) #define PXP_CSC1_COEF0_UV_OFFSET_SHIFT (9U) #define PXP_CSC1_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_UV_OFFSET_SHIFT)) & PXP_CSC1_COEF0_UV_OFFSET_MASK) + #define PXP_CSC1_COEF0_C0_MASK (0x1FFC0000U) #define PXP_CSC1_COEF0_C0_SHIFT (18U) #define PXP_CSC1_COEF0_C0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_C0_SHIFT)) & PXP_CSC1_COEF0_C0_MASK) -#define PXP_CSC1_COEF0_RSVD1_MASK (0x20000000U) -#define PXP_CSC1_COEF0_RSVD1_SHIFT (29U) -#define PXP_CSC1_COEF0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_RSVD1_SHIFT)) & PXP_CSC1_COEF0_RSVD1_MASK) + #define PXP_CSC1_COEF0_BYPASS_MASK (0x40000000U) #define PXP_CSC1_COEF0_BYPASS_SHIFT (30U) #define PXP_CSC1_COEF0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_BYPASS_SHIFT)) & PXP_CSC1_COEF0_BYPASS_MASK) + #define PXP_CSC1_COEF0_YCBCR_MODE_MASK (0x80000000U) #define PXP_CSC1_COEF0_YCBCR_MODE_SHIFT (31U) +/*! YCBCR_MODE + * 0b0..YUV to RGB + * 0b1..YCbCr to RGB + */ #define PXP_CSC1_COEF0_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK) /*! @} */ /*! @name CSC1_COEF1 - Color Space Conversion Coefficient Register 1 */ /*! @{ */ + #define PXP_CSC1_COEF1_C4_MASK (0x7FFU) #define PXP_CSC1_COEF1_C4_SHIFT (0U) #define PXP_CSC1_COEF1_C4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C4_SHIFT)) & PXP_CSC1_COEF1_C4_MASK) -#define PXP_CSC1_COEF1_RSVD0_MASK (0xF800U) -#define PXP_CSC1_COEF1_RSVD0_SHIFT (11U) -#define PXP_CSC1_COEF1_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_RSVD0_SHIFT)) & PXP_CSC1_COEF1_RSVD0_MASK) + #define PXP_CSC1_COEF1_C1_MASK (0x7FF0000U) #define PXP_CSC1_COEF1_C1_SHIFT (16U) #define PXP_CSC1_COEF1_C1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C1_SHIFT)) & PXP_CSC1_COEF1_C1_MASK) -#define PXP_CSC1_COEF1_RSVD1_MASK (0xF8000000U) -#define PXP_CSC1_COEF1_RSVD1_SHIFT (27U) -#define PXP_CSC1_COEF1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_RSVD1_SHIFT)) & PXP_CSC1_COEF1_RSVD1_MASK) /*! @} */ /*! @name CSC1_COEF2 - Color Space Conversion Coefficient Register 2 */ /*! @{ */ + #define PXP_CSC1_COEF2_C3_MASK (0x7FFU) #define PXP_CSC1_COEF2_C3_SHIFT (0U) #define PXP_CSC1_COEF2_C3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C3_SHIFT)) & PXP_CSC1_COEF2_C3_MASK) -#define PXP_CSC1_COEF2_RSVD0_MASK (0xF800U) -#define PXP_CSC1_COEF2_RSVD0_SHIFT (11U) -#define PXP_CSC1_COEF2_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_RSVD0_SHIFT)) & PXP_CSC1_COEF2_RSVD0_MASK) + #define PXP_CSC1_COEF2_C2_MASK (0x7FF0000U) #define PXP_CSC1_COEF2_C2_SHIFT (16U) #define PXP_CSC1_COEF2_C2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C2_SHIFT)) & PXP_CSC1_COEF2_C2_MASK) -#define PXP_CSC1_COEF2_RSVD1_MASK (0xF8000000U) -#define PXP_CSC1_COEF2_RSVD1_SHIFT (27U) -#define PXP_CSC1_COEF2_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_RSVD1_SHIFT)) & PXP_CSC1_COEF2_RSVD1_MASK) /*! @} */ /*! @name POWER - PXP Power Control Register */ /*! @{ */ + #define PXP_POWER_ROT_MEM_LP_STATE_MASK (0xE00U) #define PXP_POWER_ROT_MEM_LP_STATE_SHIFT (9U) /*! ROT_MEM_LP_STATE @@ -72739,19 +81846,15 @@ typedef struct { * 0b100..Shut Down Mode. Shut Down periphery and core, no memory retention. */ #define PXP_POWER_ROT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_ROT_MEM_LP_STATE_SHIFT)) & PXP_POWER_ROT_MEM_LP_STATE_MASK) -#define PXP_POWER_CTRL_MASK (0xFFFFF000U) -#define PXP_POWER_CTRL_SHIFT (12U) -#define PXP_POWER_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_CTRL_SHIFT)) & PXP_POWER_CTRL_MASK) /*! @} */ /*! @name NEXT - Next Frame Pointer */ /*! @{ */ + #define PXP_NEXT_ENABLED_MASK (0x1U) #define PXP_NEXT_ENABLED_SHIFT (0U) #define PXP_NEXT_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_ENABLED_SHIFT)) & PXP_NEXT_ENABLED_MASK) -#define PXP_NEXT_RSVD_MASK (0x2U) -#define PXP_NEXT_RSVD_SHIFT (1U) -#define PXP_NEXT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_RSVD_SHIFT)) & PXP_NEXT_RSVD_MASK) + #define PXP_NEXT_POINTER_MASK (0xFFFFFFFCU) #define PXP_NEXT_POINTER_SHIFT (2U) #define PXP_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_POINTER_SHIFT)) & PXP_NEXT_POINTER_MASK) @@ -72759,36 +81862,91 @@ typedef struct { /*! @name PORTER_DUFF_CTRL - PXP Alpha Engine A Control Register. */ /*! @{ */ -#define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_MASK (0x1U) -#define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_SHIFT (0U) -#define PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_SHIFT)) & PXP_PORTER_DUFF_CTRL_POTER_DUFF_ENABLE_MASK) + +#define PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK (0x1U) +#define PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_SHIFT (0U) +/*! PORTER_DUFF_ENABLE + * 0b0..Disabled + * 0b1..Enabled + */ +#define PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_SHIFT)) & PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK) + #define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK (0x6U) #define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT (1U) +/*! S0_S1_FACTOR_MODE + * 0b00..1 + * 0b01..0 + * 0b10..Straight alpha + * 0b11..Inverse alpha + */ #define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK) + #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK (0x18U) #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT (3U) +/*! S0_GLOBAL_ALPHA_MODE + * 0b00..Global alpha + * 0b01..Local alpha + * 0b10..Scaled alpha + * 0b11..Scaled alpha + */ #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK) + #define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK (0x20U) #define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT (5U) +/*! S0_ALPHA_MODE + * 0b0..Straight mode + * 0b1..Inverted mode + */ #define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK) + #define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK (0x40U) #define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT (6U) +/*! S0_COLOR_MODE + * 0b0..Original pixel + * 0b1..Scaled pixel + */ #define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK) + #define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK (0x300U) #define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT (8U) +/*! S1_S0_FACTOR_MODE + * 0b00..1 + * 0b01..0 + * 0b10..Straight alpha + * 0b11..Inverse alpha + */ #define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK) + #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK (0xC00U) #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT (10U) +/*! S1_GLOBAL_ALPHA_MODE + * 0b00..Global alpha + * 0b01..Local alpha + * 0b10..Scaled alpha + * 0b11..Scaled alpha + */ #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK) + #define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK (0x1000U) #define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT (12U) +/*! S1_ALPHA_MODE + * 0b0..Straight mode + * 0b1..Inverted mode + */ #define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK) + #define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK (0x2000U) #define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT (13U) +/*! S1_COLOR_MODE + * 0b0..Original pixel + * 0b1..Scaled pixel + */ #define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK) + #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK (0xFF0000U) #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT (16U) #define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK) + #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK (0xFF000000U) #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT (24U) #define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK) @@ -72857,21 +82015,25 @@ typedef struct { /*! @name VIR - Version Information */ /*! @{ */ + #define RDC_VIR_NDID_MASK (0xFU) #define RDC_VIR_NDID_SHIFT (0U) /*! NDID - Number of Domains */ #define RDC_VIR_NDID(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NDID_SHIFT)) & RDC_VIR_NDID_MASK) + #define RDC_VIR_NMSTR_MASK (0xFF0U) #define RDC_VIR_NMSTR_SHIFT (4U) /*! NMSTR - Number of Masters */ #define RDC_VIR_NMSTR(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NMSTR_SHIFT)) & RDC_VIR_NMSTR_MASK) + #define RDC_VIR_NPER_MASK (0xFF000U) #define RDC_VIR_NPER_SHIFT (12U) /*! NPER - Number of Peripherals */ #define RDC_VIR_NPER(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NPER_SHIFT)) & RDC_VIR_NPER_MASK) + #define RDC_VIR_NRGN_MASK (0xFF00000U) #define RDC_VIR_NRGN_SHIFT (20U) /*! NRGN - Number of Memory Regions @@ -72881,11 +82043,13 @@ typedef struct { /*! @name STAT - Status */ /*! @{ */ + #define RDC_STAT_DID_MASK (0xFU) #define RDC_STAT_DID_SHIFT (0U) /*! DID - Domain ID */ #define RDC_STAT_DID(x) (((uint32_t)(((uint32_t)(x)) << RDC_STAT_DID_SHIFT)) & RDC_STAT_DID_MASK) + #define RDC_STAT_PDS_MASK (0x100U) #define RDC_STAT_PDS_SHIFT (8U) /*! PDS - Power Domain Status @@ -72897,6 +82061,7 @@ typedef struct { /*! @name INTCTRL - Interrupt and Control */ /*! @{ */ + #define RDC_INTCTRL_RCI_EN_MASK (0x1U) #define RDC_INTCTRL_RCI_EN_SHIFT (0U) /*! RCI_EN - Restoration Complete Interrupt @@ -72908,6 +82073,7 @@ typedef struct { /*! @name INTSTAT - Interrupt Status */ /*! @{ */ + #define RDC_INTSTAT_INT_MASK (0x1U) #define RDC_INTSTAT_INT_SHIFT (0U) /*! INT - Interrupt Status @@ -72919,16 +82085,20 @@ typedef struct { /*! @name MDA - Master Domain Assignment */ /*! @{ */ + #define RDC_MDA_DID_MASK (0x3U) #define RDC_MDA_DID_SHIFT (0U) /*! DID - Domain ID * 0b00..Master assigned to Processing Domain 0 * 0b01..Master assigned to Processing Domain 1 + * 0b10..Reserved + * 0b11..Reserved */ #define RDC_MDA_DID(x) (((uint32_t)(((uint32_t)(x)) << RDC_MDA_DID_SHIFT)) & RDC_MDA_DID_MASK) + #define RDC_MDA_LCK_MASK (0x80000000U) #define RDC_MDA_LCK_SHIFT (31U) -/*! LCK +/*! LCK - Assignment Lock * 0b0..Not Locked * 0b1..Locked */ @@ -72940,6 +82110,7 @@ typedef struct { /*! @name PDAP - Peripheral Domain Access Permissions */ /*! @{ */ + #define RDC_PDAP_D0W_MASK (0x1U) #define RDC_PDAP_D0W_SHIFT (0U) /*! D0W - Domain 0 Write Access @@ -72947,6 +82118,7 @@ typedef struct { * 0b1..Write Access Allowed */ #define RDC_PDAP_D0W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0W_SHIFT)) & RDC_PDAP_D0W_MASK) + #define RDC_PDAP_D0R_MASK (0x2U) #define RDC_PDAP_D0R_SHIFT (1U) /*! D0R - Domain 0 Read Access @@ -72954,6 +82126,7 @@ typedef struct { * 0b1..Read Access Allowed */ #define RDC_PDAP_D0R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0R_SHIFT)) & RDC_PDAP_D0R_MASK) + #define RDC_PDAP_D1W_MASK (0x4U) #define RDC_PDAP_D1W_SHIFT (2U) /*! D1W - Domain 1 Write Access @@ -72961,6 +82134,7 @@ typedef struct { * 0b1..Write Access Allowed */ #define RDC_PDAP_D1W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1W_SHIFT)) & RDC_PDAP_D1W_MASK) + #define RDC_PDAP_D1R_MASK (0x8U) #define RDC_PDAP_D1R_SHIFT (3U) /*! D1R - Domain 1 Read Access @@ -72968,6 +82142,7 @@ typedef struct { * 0b1..Read Access Allowed */ #define RDC_PDAP_D1R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1R_SHIFT)) & RDC_PDAP_D1R_MASK) + #define RDC_PDAP_SREQ_MASK (0x40000000U) #define RDC_PDAP_SREQ_SHIFT (30U) /*! SREQ - Semaphore Required @@ -72975,6 +82150,7 @@ typedef struct { * 0b1..Semaphores are enforced */ #define RDC_PDAP_SREQ(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_SREQ_SHIFT)) & RDC_PDAP_SREQ_MASK) + #define RDC_PDAP_LCK_MASK (0x80000000U) #define RDC_PDAP_LCK_SHIFT (31U) /*! LCK - Peripheral Permissions Lock @@ -72989,6 +82165,7 @@ typedef struct { /*! @name MRSA - Memory Region Start Address */ /*! @{ */ + #define RDC_MRSA_SADR_MASK (0xFFFFFF80U) #define RDC_MRSA_SADR_SHIFT (7U) /*! SADR - Start address for memory region @@ -73001,6 +82178,7 @@ typedef struct { /*! @name MREA - Memory Region End Address */ /*! @{ */ + #define RDC_MREA_EADR_MASK (0xFFFFFF80U) #define RDC_MREA_EADR_SHIFT (7U) /*! EADR - Upper bound for memory region @@ -73013,6 +82191,7 @@ typedef struct { /*! @name MRC - Memory Region Control */ /*! @{ */ + #define RDC_MRC_D0W_MASK (0x1U) #define RDC_MRC_D0W_SHIFT (0U) /*! D0W - Domain 0 Write Access to Region @@ -73020,6 +82199,7 @@ typedef struct { * 0b1..Processing Domain 0 has Write access to the memory region */ #define RDC_MRC_D0W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0W_SHIFT)) & RDC_MRC_D0W_MASK) + #define RDC_MRC_D0R_MASK (0x2U) #define RDC_MRC_D0R_SHIFT (1U) /*! D0R - Domain 0 Read Access to Region @@ -73027,6 +82207,7 @@ typedef struct { * 0b1..Processing Domain 0 has Read access to the memory region */ #define RDC_MRC_D0R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0R_SHIFT)) & RDC_MRC_D0R_MASK) + #define RDC_MRC_D1W_MASK (0x4U) #define RDC_MRC_D1W_SHIFT (2U) /*! D1W - Domain 1 Write Access to Region @@ -73034,6 +82215,7 @@ typedef struct { * 0b1..Processing Domain 1 has Write access to the memory region */ #define RDC_MRC_D1W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1W_SHIFT)) & RDC_MRC_D1W_MASK) + #define RDC_MRC_D1R_MASK (0x8U) #define RDC_MRC_D1R_SHIFT (3U) /*! D1R - Domain 1 Read Access to Region @@ -73041,6 +82223,7 @@ typedef struct { * 0b1..Processing Domain 1 has Read access to the memory region */ #define RDC_MRC_D1R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1R_SHIFT)) & RDC_MRC_D1R_MASK) + #define RDC_MRC_ENA_MASK (0x40000000U) #define RDC_MRC_ENA_SHIFT (30U) /*! ENA - Region Enable @@ -73048,6 +82231,7 @@ typedef struct { * 0b1..Memory boundaries, domain permissions and controls are in effect. */ #define RDC_MRC_ENA(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_ENA_SHIFT)) & RDC_MRC_ENA_MASK) + #define RDC_MRC_LCK_MASK (0x80000000U) #define RDC_MRC_LCK_SHIFT (31U) /*! LCK - Region Lock @@ -73062,18 +82246,23 @@ typedef struct { /*! @name MRVS - Memory Region Violation Status */ /*! @{ */ + #define RDC_MRVS_VDID_MASK (0x3U) #define RDC_MRVS_VDID_SHIFT (0U) /*! VDID - Violating Domain ID * 0b00..Processing Domain 0 * 0b01..Processing Domain 1 + * 0b10..Reserved + * 0b11..Reserved */ #define RDC_MRVS_VDID(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VDID_SHIFT)) & RDC_MRVS_VDID_MASK) + #define RDC_MRVS_AD_MASK (0x10U) #define RDC_MRVS_AD_SHIFT (4U) /*! AD - Access Denied */ #define RDC_MRVS_AD(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_AD_SHIFT)) & RDC_MRVS_AD_MASK) + #define RDC_MRVS_VADR_MASK (0xFFFFFFE0U) #define RDC_MRVS_VADR_SHIFT (5U) /*! VADR - Violating Address @@ -73119,8 +82308,11 @@ typedef struct { /** RDC_SEMAPHORE - Register Layout Typedef */ typedef struct { __IO uint8_t GATE[64]; /**< Gate Register, array offset: 0x0, array step: 0x1 */ - __IO uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x40 */ - __IO uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x42 */ + uint8_t RESERVED_0[2]; + union { /* offset: 0x42 */ + __IO uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x42 */ + __IO uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x42 */ + }; } RDC_SEMAPHORE_Type; /* ---------------------------------------------------------------------------- @@ -73134,6 +82326,7 @@ typedef struct { /*! @name GATE - Gate Register */ /*! @{ */ + #define RDC_SEMAPHORE_GATE_GTFSM_MASK (0xFU) #define RDC_SEMAPHORE_GATE_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. @@ -73155,13 +82348,14 @@ typedef struct { * 0b1111..The gate has been locked by processor with master_index = 14. */ #define RDC_SEMAPHORE_GATE_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE_GTFSM_MASK) + #define RDC_SEMAPHORE_GATE_LDOM_MASK (0x30U) #define RDC_SEMAPHORE_GATE_LDOM_SHIFT (4U) /*! LDOM - * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.) + * 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.) * 0b01..The gate has been locked by domain 1. - * 0b10..The gate has been locked by domain 2. - * 0b11..The gate has been locked by domain 3. + * 0b10..Reserved + * 0b11..Reserved */ #define RDC_SEMAPHORE_GATE_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE_LDOM_MASK) /*! @} */ @@ -73169,21 +82363,13 @@ typedef struct { /* The count of RDC_SEMAPHORE_GATE */ #define RDC_SEMAPHORE_GATE_COUNT (64U) -/*! @name RSTGT_W - Reset Gate Write */ -/*! @{ */ -#define RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK (0xFFU) -#define RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT (0U) -#define RDC_SEMAPHORE_RSTGT_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK) -#define RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK (0xFF00U) -#define RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT (8U) -#define RDC_SEMAPHORE_RSTGT_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK) -/*! @} */ - /*! @name RSTGT_R - Reset Gate Read */ /*! @{ */ + #define RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK (0xFU) #define RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT (0U) #define RDC_SEMAPHORE_RSTGT_R_RSTGMS(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK) + #define RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK (0x30U) #define RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT (4U) /*! RSTGSM @@ -73195,11 +82381,24 @@ typedef struct { * 0b11..This state encoding is never used and therefore reserved. */ #define RDC_SEMAPHORE_RSTGT_R_RSTGSM(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK) + #define RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK (0xFF00U) #define RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT (8U) #define RDC_SEMAPHORE_RSTGT_R_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK) /*! @} */ +/*! @name RSTGT_W - Reset Gate Write */ +/*! @{ */ + +#define RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK (0xFFU) +#define RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT (0U) +#define RDC_SEMAPHORE_RSTGT_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK) + +#define RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK (0xFF00U) +#define RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT (8U) +#define RDC_SEMAPHORE_RSTGT_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK) +/*! @} */ + /*! * @} @@ -73225,290 +82424,6 @@ typedef struct { */ /* end of group RDC_SEMAPHORE_Peripheral_Access_Layer */ -/* ---------------------------------------------------------------------------- - -- ROM Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer - * @{ - */ - -/** ROM - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[212]; - __IO uint32_t ROMPATCHD[8]; /**< ROMC Data Registers, array offset: 0xD4, array step: 0x4 */ - __IO uint32_t ROMPATCHCNTL; /**< ROMC Control Register, offset: 0xF4 */ - uint32_t ROMPATCHENH; /**< ROMC Enable Register High, offset: 0xF8 */ - __IO uint32_t ROMPATCHENL; /**< ROMC Enable Register Low, offset: 0xFC */ - __IO uint32_t ROMPATCHA[16]; /**< ROMC Address Registers, array offset: 0x100, array step: 0x4 */ - uint8_t RESERVED_1[200]; - __IO uint32_t ROMPATCHSR; /**< ROMC Status Register, offset: 0x208 */ -} ROM_Type; - -/* ---------------------------------------------------------------------------- - -- ROM Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup ROM_Register_Masks ROM Register Masks - * @{ - */ - -/*! @name ROMPATCHD - ROMC Data Registers */ -/*! @{ */ -#define ROM_ROMPATCHD_DATAX_MASK (0xFFFFFFFFU) -#define ROM_ROMPATCHD_DATAX_SHIFT (0U) -/*! DATAX - Data Fix Registers - */ -#define ROM_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x)) << ROM_ROMPATCHD_DATAX_SHIFT)) & ROM_ROMPATCHD_DATAX_MASK) -/*! @} */ - -/* The count of ROM_ROMPATCHD */ -#define ROM_ROMPATCHD_COUNT (8U) - -/*! @name ROMPATCHCNTL - ROMC Control Register */ -/*! @{ */ -#define ROM_ROMPATCHCNTL_DATAFIX0_MASK (0x1U) -#define ROM_ROMPATCHCNTL_DATAFIX0_SHIFT (0U) -/*! DATAFIX0 - Data Fix Enable - * 0b0..Trigger an opcode patch for ROMPATCHnA - * 0b1..Trigger a data fix for ROMPATCHnA - */ -#define ROM_ROMPATCHCNTL_DATAFIX0(x) (((uint32_t)(((uint32_t)(x)) << ROM_ROMPATCHCNTL_DATAFIX0_SHIFT)) & ROM_ROMPATCHCNTL_DATAFIX0_MASK) -#define ROM_ROMPATCHCNTL_DATAFIX1_MASK (0x2U) -#define ROM_ROMPATCHCNTL_DATAFIX1_SHIFT (1U) -/*! DATAFIX1 - Data Fix Enable - * 0b0..Trigger an opcode patch for ROMPATCHnA - * 0b1..Trigger a data fix for ROMPATCHnA - */ -#define ROM_ROMPATCHCNTL_DATAFIX1(x) (((uint32_t)(((uint32_t)(x)) << ROM_ROMPATCHCNTL_DATAFIX1_SHIFT)) & ROM_ROMPATCHCNTL_DATAFIX1_MASK) -#define ROM_ROMPATCHCNTL_DATAFIX2_MASK (0x4U) -#define ROM_ROMPATCHCNTL_DATAFIX2_SHIFT (2U) -/*! DATAFIX2 - Data Fix Enable - * 0b0..Trigger an opcode patch for ROMPATCHnA - * 0b1..Trigger a data fix for ROMPATCHnA - */ -#define ROM_ROMPATCHCNTL_DATAFIX2(x) (((uint32_t)(((uint32_t)(x)) << ROM_ROMPATCHCNTL_DATAFIX2_SHIFT)) & ROM_ROMPATCHCNTL_DATAFIX2_MASK) -#define ROM_ROMPATCHCNTL_DATAFIX3_MASK (0x8U) -#define ROM_ROMPATCHCNTL_DATAFIX3_SHIFT (3U) -/*! DATAFIX3 - Data Fix Enable - * 0b0..Trigger an opcode patch for ROMPATCHnA - * 0b1..Trigger a data fix for ROMPATCHnA - */ -#define ROM_ROMPATCHCNTL_DATAFIX3(x) (((uint32_t)(((uint32_t)(x)) << ROM_ROMPATCHCNTL_DATAFIX3_SHIFT)) & ROM_ROMPATCHCNTL_DATAFIX3_MASK) -#define ROM_ROMPATCHCNTL_DATAFIX4_MASK (0x10U) -#define ROM_ROMPATCHCNTL_DATAFIX4_SHIFT (4U) -/*! DATAFIX4 - Data Fix Enable - * 0b0..Trigger an opcode patch for ROMPATCHnA - * 0b1..Trigger a data fix for ROMPATCHnA - */ -#define ROM_ROMPATCHCNTL_DATAFIX4(x) (((uint32_t)(((uint32_t)(x)) << ROM_ROMPATCHCNTL_DATAFIX4_SHIFT)) & ROM_ROMPATCHCNTL_DATAFIX4_MASK) -#define ROM_ROMPATCHCNTL_DATAFIX5_MASK (0x20U) -#define ROM_ROMPATCHCNTL_DATAFIX5_SHIFT (5U) -/*! DATAFIX5 - Data Fix Enable - * 0b0..Trigger an opcode patch for ROMPATCHnA - * 0b1..Trigger a data fix for ROMPATCHnA - */ -#define ROM_ROMPATCHCNTL_DATAFIX5(x) (((uint32_t)(((uint32_t)(x)) << ROM_ROMPATCHCNTL_DATAFIX5_SHIFT)) & ROM_ROMPATCHCNTL_DATAFIX5_MASK) -#define ROM_ROMPATCHCNTL_DATAFIX6_MASK (0x40U) -#define ROM_ROMPATCHCNTL_DATAFIX6_SHIFT (6U) -/*! DATAFIX6 - Data Fix Enable - * 0b0..Trigger an opcode patch for ROMPATCHnA - * 0b1..Trigger a data fix for ROMPATCHnA - */ -#define ROM_ROMPATCHCNTL_DATAFIX6(x) (((uint32_t)(((uint32_t)(x)) << ROM_ROMPATCHCNTL_DATAFIX6_SHIFT)) & ROM_ROMPATCHCNTL_DATAFIX6_MASK) -#define ROM_ROMPATCHCNTL_DATAFIX7_MASK (0x80U) -#define ROM_ROMPATCHCNTL_DATAFIX7_SHIFT (7U) -/*! DATAFIX7 - Data Fix Enable - * 0b0..Trigger an opcode patch for ROMPATCHnA - * 0b1..Trigger a data fix for ROMPATCHnA - */ -#define ROM_ROMPATCHCNTL_DATAFIX7(x) (((uint32_t)(((uint32_t)(x)) << ROM_ROMPATCHCNTL_DATAFIX7_SHIFT)) & ROM_ROMPATCHCNTL_DATAFIX7_MASK) -#define ROM_ROMPATCHCNTL_DIS_MASK (0x20000000U) -#define ROM_ROMPATCHCNTL_DIS_SHIFT (29U) -/*! DIS - ROMC Disable - * 0b0..Does not affect any ROMC functions (default) - * 0b1..Disables all ROMC functions: data fixing and opcode patching - */ -#define ROM_ROMPATCHCNTL_DIS(x) (((uint32_t)(((uint32_t)(x)) << ROM_ROMPATCHCNTL_DIS_SHIFT)) & ROM_ROMPATCHCNTL_DIS_MASK) -/*! @} */ - -/*! @name ROMPATCHENL - ROMC Enable Register Low */ -/*! @{ */ -#define ROM_ROMPATCHENL_ENABLE0_MASK (0x1U) -#define ROM_ROMPATCHENL_ENABLE0_SHIFT (0U) -/*! ENABLE0 - Enable Address Comparator n - * 0b0..Address comparator n is disabled - * 0b1..Address comparator n is enabled - */ -#define ROM_ROMPATCHENL_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << ROM_ROMPATCHENL_ENABLE0_SHIFT)) & ROM_ROMPATCHENL_ENABLE0_MASK) -#define ROM_ROMPATCHENL_ENABLE1_MASK (0x2U) -#define ROM_ROMPATCHENL_ENABLE1_SHIFT (1U) -/*! ENABLE1 - Enable Address Comparator n - * 0b0..Address comparator n is disabled - * 0b1..Address comparator n is enabled - */ -#define ROM_ROMPATCHENL_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << ROM_ROMPATCHENL_ENABLE1_SHIFT)) & ROM_ROMPATCHENL_ENABLE1_MASK) -#define ROM_ROMPATCHENL_ENABLE2_MASK (0x4U) -#define ROM_ROMPATCHENL_ENABLE2_SHIFT (2U) -/*! ENABLE2 - Enable Address Comparator n - * 0b0..Address comparator n is disabled - * 0b1..Address comparator n is enabled - */ -#define ROM_ROMPATCHENL_ENABLE2(x) (((uint32_t)(((uint32_t)(x)) << ROM_ROMPATCHENL_ENABLE2_SHIFT)) & ROM_ROMPATCHENL_ENABLE2_MASK) -#define ROM_ROMPATCHENL_ENABLE3_MASK (0x8U) -#define ROM_ROMPATCHENL_ENABLE3_SHIFT (3U) -/*! ENABLE3 - Enable Address Comparator n - * 0b0..Address comparator n is disabled - * 0b1..Address comparator n is enabled - */ -#define ROM_ROMPATCHENL_ENABLE3(x) (((uint32_t)(((uint32_t)(x)) << ROM_ROMPATCHENL_ENABLE3_SHIFT)) & ROM_ROMPATCHENL_ENABLE3_MASK) -#define ROM_ROMPATCHENL_ENABLE4_MASK (0x10U) -#define ROM_ROMPATCHENL_ENABLE4_SHIFT (4U) -/*! ENABLE4 - Enable Address Comparator n - * 0b0..Address comparator n is disabled - * 0b1..Address comparator n is enabled - */ -#define ROM_ROMPATCHENL_ENABLE4(x) (((uint32_t)(((uint32_t)(x)) << ROM_ROMPATCHENL_ENABLE4_SHIFT)) & ROM_ROMPATCHENL_ENABLE4_MASK) -#define ROM_ROMPATCHENL_ENABLE5_MASK (0x20U) -#define ROM_ROMPATCHENL_ENABLE5_SHIFT (5U) -/*! ENABLE5 - Enable Address Comparator n - * 0b0..Address comparator n is disabled - * 0b1..Address comparator n is enabled - */ -#define ROM_ROMPATCHENL_ENABLE5(x) (((uint32_t)(((uint32_t)(x)) << ROM_ROMPATCHENL_ENABLE5_SHIFT)) & ROM_ROMPATCHENL_ENABLE5_MASK) -#define ROM_ROMPATCHENL_ENABLE6_MASK (0x40U) -#define ROM_ROMPATCHENL_ENABLE6_SHIFT (6U) -/*! ENABLE6 - Enable Address Comparator n - * 0b0..Address comparator n is disabled - * 0b1..Address comparator n is enabled - */ -#define ROM_ROMPATCHENL_ENABLE6(x) (((uint32_t)(((uint32_t)(x)) << ROM_ROMPATCHENL_ENABLE6_SHIFT)) & ROM_ROMPATCHENL_ENABLE6_MASK) -#define ROM_ROMPATCHENL_ENABLE7_MASK (0x80U) -#define ROM_ROMPATCHENL_ENABLE7_SHIFT (7U) -/*! ENABLE7 - Enable Address Comparator n - * 0b0..Address comparator n is disabled - * 0b1..Address comparator n is enabled - */ -#define ROM_ROMPATCHENL_ENABLE7(x) (((uint32_t)(((uint32_t)(x)) << ROM_ROMPATCHENL_ENABLE7_SHIFT)) & ROM_ROMPATCHENL_ENABLE7_MASK) -#define ROM_ROMPATCHENL_ENABLE8_MASK (0x100U) -#define ROM_ROMPATCHENL_ENABLE8_SHIFT (8U) -/*! ENABLE8 - Enable Address Comparator n - * 0b0..Address comparator n is disabled - * 0b1..Address comparator n is enabled - */ -#define ROM_ROMPATCHENL_ENABLE8(x) (((uint32_t)(((uint32_t)(x)) << ROM_ROMPATCHENL_ENABLE8_SHIFT)) & ROM_ROMPATCHENL_ENABLE8_MASK) -#define ROM_ROMPATCHENL_ENABLE9_MASK (0x200U) -#define ROM_ROMPATCHENL_ENABLE9_SHIFT (9U) -/*! ENABLE9 - Enable Address Comparator n - * 0b0..Address comparator n is disabled - * 0b1..Address comparator n is enabled - */ -#define ROM_ROMPATCHENL_ENABLE9(x) (((uint32_t)(((uint32_t)(x)) << ROM_ROMPATCHENL_ENABLE9_SHIFT)) & ROM_ROMPATCHENL_ENABLE9_MASK) -#define ROM_ROMPATCHENL_ENABLE10_MASK (0x400U) -#define ROM_ROMPATCHENL_ENABLE10_SHIFT (10U) -/*! ENABLE10 - Enable Address Comparator n - * 0b0..Address comparator n is disabled - * 0b1..Address comparator n is enabled - */ -#define ROM_ROMPATCHENL_ENABLE10(x) (((uint32_t)(((uint32_t)(x)) << ROM_ROMPATCHENL_ENABLE10_SHIFT)) & ROM_ROMPATCHENL_ENABLE10_MASK) -#define ROM_ROMPATCHENL_ENABLE11_MASK (0x800U) -#define ROM_ROMPATCHENL_ENABLE11_SHIFT (11U) -/*! ENABLE11 - Enable Address Comparator n - * 0b0..Address comparator n is disabled - * 0b1..Address comparator n is enabled - */ -#define ROM_ROMPATCHENL_ENABLE11(x) (((uint32_t)(((uint32_t)(x)) << ROM_ROMPATCHENL_ENABLE11_SHIFT)) & ROM_ROMPATCHENL_ENABLE11_MASK) -#define ROM_ROMPATCHENL_ENABLE12_MASK (0x1000U) -#define ROM_ROMPATCHENL_ENABLE12_SHIFT (12U) -/*! ENABLE12 - Enable Address Comparator n - * 0b0..Address comparator n is disabled - * 0b1..Address comparator n is enabled - */ -#define ROM_ROMPATCHENL_ENABLE12(x) (((uint32_t)(((uint32_t)(x)) << ROM_ROMPATCHENL_ENABLE12_SHIFT)) & ROM_ROMPATCHENL_ENABLE12_MASK) -#define ROM_ROMPATCHENL_ENABLE13_MASK (0x2000U) -#define ROM_ROMPATCHENL_ENABLE13_SHIFT (13U) -/*! ENABLE13 - Enable Address Comparator n - * 0b0..Address comparator n is disabled - * 0b1..Address comparator n is enabled - */ -#define ROM_ROMPATCHENL_ENABLE13(x) (((uint32_t)(((uint32_t)(x)) << ROM_ROMPATCHENL_ENABLE13_SHIFT)) & ROM_ROMPATCHENL_ENABLE13_MASK) -#define ROM_ROMPATCHENL_ENABLE14_MASK (0x4000U) -#define ROM_ROMPATCHENL_ENABLE14_SHIFT (14U) -/*! ENABLE14 - Enable Address Comparator n - * 0b0..Address comparator n is disabled - * 0b1..Address comparator n is enabled - */ -#define ROM_ROMPATCHENL_ENABLE14(x) (((uint32_t)(((uint32_t)(x)) << ROM_ROMPATCHENL_ENABLE14_SHIFT)) & ROM_ROMPATCHENL_ENABLE14_MASK) -#define ROM_ROMPATCHENL_ENABLE15_MASK (0x8000U) -#define ROM_ROMPATCHENL_ENABLE15_SHIFT (15U) -/*! ENABLE15 - Enable Address Comparator n - * 0b0..Address comparator n is disabled - * 0b1..Address comparator n is enabled - */ -#define ROM_ROMPATCHENL_ENABLE15(x) (((uint32_t)(((uint32_t)(x)) << ROM_ROMPATCHENL_ENABLE15_SHIFT)) & ROM_ROMPATCHENL_ENABLE15_MASK) -/*! @} */ - -/*! @name ROMPATCHA - ROMC Address Registers */ -/*! @{ */ -#define ROM_ROMPATCHA_THUMBX_MASK (0x1U) -#define ROM_ROMPATCHA_THUMBX_SHIFT (0U) -/*! THUMBX - THUMB Comparator Select - * 0b0..ARM patch - * 0b1..THUMB patch (ignore if a data fix) - */ -#define ROM_ROMPATCHA_THUMBX(x) (((uint32_t)(((uint32_t)(x)) << ROM_ROMPATCHA_THUMBX_SHIFT)) & ROM_ROMPATCHA_THUMBX_MASK) -#define ROM_ROMPATCHA_ADDRX_MASK (0x7FFFFEU) -#define ROM_ROMPATCHA_ADDRX_SHIFT (1U) -/*! ADDRX - Address Comparator Registers - */ -#define ROM_ROMPATCHA_ADDRX(x) (((uint32_t)(((uint32_t)(x)) << ROM_ROMPATCHA_ADDRX_SHIFT)) & ROM_ROMPATCHA_ADDRX_MASK) -/*! @} */ - -/* The count of ROM_ROMPATCHA */ -#define ROM_ROMPATCHA_COUNT (16U) - -/*! @name ROMPATCHSR - ROMC Status Register */ -/*! @{ */ -#define ROM_ROMPATCHSR_SOURCE_MASK (0x3FU) -#define ROM_ROMPATCHSR_SOURCE_SHIFT (0U) -/*! SOURCE - ROMC Source Number - * 0b000000..Address Comparator 0 matched - * 0b000001..Address Comparator 1 matched - * 0b001111..Address Comparator 15 matched - */ -#define ROM_ROMPATCHSR_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << ROM_ROMPATCHSR_SOURCE_SHIFT)) & ROM_ROMPATCHSR_SOURCE_MASK) -#define ROM_ROMPATCHSR_SW_MASK (0x20000U) -#define ROM_ROMPATCHSR_SW_SHIFT (17U) -/*! SW - ROMC AHB Multiple Address Comparator Match Indicator - * 0b0..No event or comparator collisions have occurred - * 0b1..A collision has occurred - */ -#define ROM_ROMPATCHSR_SW(x) (((uint32_t)(((uint32_t)(x)) << ROM_ROMPATCHSR_SW_SHIFT)) & ROM_ROMPATCHSR_SW_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group ROM_Register_Masks */ - - -/* ROM - Peripheral instance base addresses */ -/** Peripheral ROM base address */ -#define ROM_BASE (0x40CA4000u) -/** Peripheral ROM base pointer */ -#define ROM ((ROM_Type *)ROM_BASE) -/** Array initializer of ROM peripheral base addresses */ -#define ROM_BASE_ADDRS { ROM_BASE } -/** Array initializer of ROM peripheral base pointers */ -#define ROM_BASE_PTRS { ROM } - -/*! - * @} - */ /* end of group ROM_Peripheral_Access_Layer */ - - /* ---------------------------------------------------------------------------- -- RTWDOG Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -73537,6 +82452,7 @@ typedef struct { /*! @name CS - Watchdog Control and Status Register */ /*! @{ */ + #define RTWDOG_CS_STOP_MASK (0x1U) #define RTWDOG_CS_STOP_SHIFT (0U) /*! STOP - Stop Enable @@ -73544,6 +82460,7 @@ typedef struct { * 0b1..Watchdog enabled in chip stop mode. */ #define RTWDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK) + #define RTWDOG_CS_WAIT_MASK (0x2U) #define RTWDOG_CS_WAIT_SHIFT (1U) /*! WAIT - Wait Enable @@ -73551,6 +82468,7 @@ typedef struct { * 0b1..Watchdog enabled in chip wait mode. */ #define RTWDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK) + #define RTWDOG_CS_DBG_MASK (0x4U) #define RTWDOG_CS_DBG_SHIFT (2U) /*! DBG - Debug Enable @@ -73558,6 +82476,7 @@ typedef struct { * 0b1..Watchdog enabled in chip debug mode. */ #define RTWDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK) + #define RTWDOG_CS_TST_MASK (0x18U) #define RTWDOG_CS_TST_SHIFT (3U) /*! TST - Watchdog Test @@ -73568,6 +82487,7 @@ typedef struct { * 0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH]. */ #define RTWDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK) + #define RTWDOG_CS_UPDATE_MASK (0x20U) #define RTWDOG_CS_UPDATE_SHIFT (5U) /*! UPDATE - Allow updates @@ -73575,6 +82495,7 @@ typedef struct { * 0b1..Updates allowed. Software can modify the watchdog configuration registers within 255 bus clocks after performing the unlock write sequence. */ #define RTWDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK) + #define RTWDOG_CS_INT_MASK (0x40U) #define RTWDOG_CS_INT_SHIFT (6U) /*! INT - Watchdog Interrupt @@ -73582,6 +82503,7 @@ typedef struct { * 0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 255 bus clocks from the interrupt vector fetch. */ #define RTWDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK) + #define RTWDOG_CS_EN_MASK (0x80U) #define RTWDOG_CS_EN_SHIFT (7U) /*! EN - Watchdog Enable @@ -73589,11 +82511,13 @@ typedef struct { * 0b1..Watchdog enabled. */ #define RTWDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK) + #define RTWDOG_CS_CLK_MASK (0x300U) #define RTWDOG_CS_CLK_SHIFT (8U) /*! CLK - Watchdog Clock */ #define RTWDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK) + #define RTWDOG_CS_RCS_MASK (0x400U) #define RTWDOG_CS_RCS_SHIFT (10U) /*! RCS - Reconfiguration Success @@ -73601,6 +82525,7 @@ typedef struct { * 0b1..Reconfiguration is successful. */ #define RTWDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK) + #define RTWDOG_CS_ULK_MASK (0x800U) #define RTWDOG_CS_ULK_SHIFT (11U) /*! ULK - Unlock status @@ -73608,6 +82533,7 @@ typedef struct { * 0b1..WDOG is unlocked. */ #define RTWDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK) + #define RTWDOG_CS_PRES_MASK (0x1000U) #define RTWDOG_CS_PRES_SHIFT (12U) /*! PRES - Watchdog prescaler @@ -73615,6 +82541,7 @@ typedef struct { * 0b1..256 prescaler enabled. */ #define RTWDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK) + #define RTWDOG_CS_CMD32EN_MASK (0x2000U) #define RTWDOG_CS_CMD32EN_SHIFT (13U) /*! CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words @@ -73622,6 +82549,7 @@ typedef struct { * 0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported. */ #define RTWDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK) + #define RTWDOG_CS_FLG_MASK (0x4000U) #define RTWDOG_CS_FLG_SHIFT (14U) /*! FLG - Watchdog Interrupt Flag @@ -73629,6 +82557,7 @@ typedef struct { * 0b1..An interrupt occurred. */ #define RTWDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK) + #define RTWDOG_CS_WIN_MASK (0x8000U) #define RTWDOG_CS_WIN_SHIFT (15U) /*! WIN - Watchdog Window @@ -73640,11 +82569,13 @@ typedef struct { /*! @name CNT - Watchdog Counter Register */ /*! @{ */ + #define RTWDOG_CNT_CNTLOW_MASK (0xFFU) #define RTWDOG_CNT_CNTLOW_SHIFT (0U) /*! CNTLOW - Low byte of the Watchdog Counter */ #define RTWDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK) + #define RTWDOG_CNT_CNTHIGH_MASK (0xFF00U) #define RTWDOG_CNT_CNTHIGH_SHIFT (8U) /*! CNTHIGH - High byte of the Watchdog Counter @@ -73654,11 +82585,13 @@ typedef struct { /*! @name TOVAL - Watchdog Timeout Value Register */ /*! @{ */ + #define RTWDOG_TOVAL_TOVALLOW_MASK (0xFFU) #define RTWDOG_TOVAL_TOVALLOW_SHIFT (0U) /*! TOVALLOW - Low byte of the timeout value */ #define RTWDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK) + #define RTWDOG_TOVAL_TOVALHIGH_MASK (0xFF00U) #define RTWDOG_TOVAL_TOVALHIGH_SHIFT (8U) /*! TOVALHIGH - High byte of the timeout value @@ -73668,11 +82601,13 @@ typedef struct { /*! @name WIN - Watchdog Window Register */ /*! @{ */ + #define RTWDOG_WIN_WINLOW_MASK (0xFFU) #define RTWDOG_WIN_WINLOW_SHIFT (0U) /*! WINLOW - Low byte of Watchdog Window */ #define RTWDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK) + #define RTWDOG_WIN_WINHIGH_MASK (0xFF00U) #define RTWDOG_WIN_WINHIGH_SHIFT (8U) /*! WINHIGH - High byte of Watchdog Window @@ -73722,7 +82657,7 @@ typedef struct { /** SEMA4 - Register Layout Typedef */ typedef struct { - __IO uint8_t GATE[16]; /**< Semaphores Gate 0 Register..Semaphores Gate 15 Register, array offset: 0x0, array step: 0x1 */ + __IO uint8_t GATE[16]; /**< Semaphores Gate n Register, array offset: 0x0, array step: 0x1 */ uint8_t RESERVED_0[48]; struct { /* offset: 0x40, array step: 0x8 */ __IO uint16_t CPINE; /**< Semaphores Processor n IRQ Notification Enable, array offset: 0x40, array step: 0x8 */ @@ -73748,8 +82683,9 @@ typedef struct { * @{ */ -/*! @name GATE - Semaphores Gate 0 Register..Semaphores Gate 15 Register */ +/*! @name GATE - Semaphores Gate n Register */ /*! @{ */ + #define SEMA4_GATE_GTFSM_MASK (0x3U) #define SEMA4_GATE_GTFSM_SHIFT (0U) /*! GTFSM - Gate Finite State Machine. @@ -73767,6 +82703,7 @@ typedef struct { /*! @name CPINE - Semaphores Processor n IRQ Notification Enable */ /*! @{ */ + #define SEMA4_CPINE_INE7_MASK (0x1U) #define SEMA4_CPINE_INE7_SHIFT (0U) /*! INE7 - Interrupt Request Notification Enable 7. This field is a bitmap to enable the generation @@ -73775,6 +82712,7 @@ typedef struct { * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE7(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE7_SHIFT)) & SEMA4_CPINE_INE7_MASK) + #define SEMA4_CPINE_INE6_MASK (0x2U) #define SEMA4_CPINE_INE6_SHIFT (1U) /*! INE6 - Interrupt Request Notification Enable 6. This field is a bitmap to enable the generation @@ -73783,6 +82721,7 @@ typedef struct { * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE6(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE6_SHIFT)) & SEMA4_CPINE_INE6_MASK) + #define SEMA4_CPINE_INE5_MASK (0x4U) #define SEMA4_CPINE_INE5_SHIFT (2U) /*! INE5 - Interrupt Request Notification Enable 5. This field is a bitmap to enable the generation @@ -73791,6 +82730,7 @@ typedef struct { * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE5(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE5_SHIFT)) & SEMA4_CPINE_INE5_MASK) + #define SEMA4_CPINE_INE4_MASK (0x8U) #define SEMA4_CPINE_INE4_SHIFT (3U) /*! INE4 - Interrupt Request Notification Enable 4. This field is a bitmap to enable the generation @@ -73799,6 +82739,7 @@ typedef struct { * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE4(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE4_SHIFT)) & SEMA4_CPINE_INE4_MASK) + #define SEMA4_CPINE_INE3_MASK (0x10U) #define SEMA4_CPINE_INE3_SHIFT (4U) /*! INE3 @@ -73806,6 +82747,7 @@ typedef struct { * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE3(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE3_SHIFT)) & SEMA4_CPINE_INE3_MASK) + #define SEMA4_CPINE_INE2_MASK (0x20U) #define SEMA4_CPINE_INE2_SHIFT (5U) /*! INE2 @@ -73813,6 +82755,7 @@ typedef struct { * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE2(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE2_SHIFT)) & SEMA4_CPINE_INE2_MASK) + #define SEMA4_CPINE_INE1_MASK (0x40U) #define SEMA4_CPINE_INE1_SHIFT (6U) /*! INE1 @@ -73820,6 +82763,7 @@ typedef struct { * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE1(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE1_SHIFT)) & SEMA4_CPINE_INE1_MASK) + #define SEMA4_CPINE_INE0_MASK (0x80U) #define SEMA4_CPINE_INE0_SHIFT (7U) /*! INE0 @@ -73827,6 +82771,7 @@ typedef struct { * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE0(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE0_SHIFT)) & SEMA4_CPINE_INE0_MASK) + #define SEMA4_CPINE_INE15_MASK (0x100U) #define SEMA4_CPINE_INE15_SHIFT (8U) /*! INE15 - Interrupt Request Notification Enable 15. This field is a bitmap to enable the @@ -73835,6 +82780,7 @@ typedef struct { * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE15(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE15_SHIFT)) & SEMA4_CPINE_INE15_MASK) + #define SEMA4_CPINE_INE14_MASK (0x200U) #define SEMA4_CPINE_INE14_SHIFT (9U) /*! INE14 - Interrupt Request Notification Enable 14. This field is a bitmap to enable the @@ -73843,6 +82789,7 @@ typedef struct { * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE14(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE14_SHIFT)) & SEMA4_CPINE_INE14_MASK) + #define SEMA4_CPINE_INE13_MASK (0x400U) #define SEMA4_CPINE_INE13_SHIFT (10U) /*! INE13 - Interrupt Request Notification Enable 13. This field is a bitmap to enable the @@ -73851,6 +82798,7 @@ typedef struct { * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE13(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE13_SHIFT)) & SEMA4_CPINE_INE13_MASK) + #define SEMA4_CPINE_INE12_MASK (0x800U) #define SEMA4_CPINE_INE12_SHIFT (11U) /*! INE12 - Interrupt Request Notification Enable 12. This field is a bitmap to enable the @@ -73859,6 +82807,7 @@ typedef struct { * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE12(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE12_SHIFT)) & SEMA4_CPINE_INE12_MASK) + #define SEMA4_CPINE_INE11_MASK (0x1000U) #define SEMA4_CPINE_INE11_SHIFT (12U) /*! INE11 - Interrupt Request Notification Enable 11. This field is a bitmap to enable the @@ -73867,6 +82816,7 @@ typedef struct { * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE11(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE11_SHIFT)) & SEMA4_CPINE_INE11_MASK) + #define SEMA4_CPINE_INE10_MASK (0x2000U) #define SEMA4_CPINE_INE10_SHIFT (13U) /*! INE10 - Interrupt Request Notification Enable 10. This field is a bitmap to enable the @@ -73875,6 +82825,7 @@ typedef struct { * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE10(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE10_SHIFT)) & SEMA4_CPINE_INE10_MASK) + #define SEMA4_CPINE_INE9_MASK (0x4000U) #define SEMA4_CPINE_INE9_SHIFT (14U) /*! INE9 - Interrupt Request Notification Enable 9. This field is a bitmap to enable the generation @@ -73883,6 +82834,7 @@ typedef struct { * 0b1..The generation of the notification interrupt is enabled. */ #define SEMA4_CPINE_INE9(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE9_SHIFT)) & SEMA4_CPINE_INE9_MASK) + #define SEMA4_CPINE_INE8_MASK (0x8000U) #define SEMA4_CPINE_INE8_SHIFT (15U) /*! INE8 - Interrupt Request Notification Enable 8. This field is a bitmap to enable the generation @@ -73898,51 +82850,67 @@ typedef struct { /*! @name CPNTF - Semaphores Processor n IRQ Notification */ /*! @{ */ + #define SEMA4_CPNTF_GN7_MASK (0x1U) #define SEMA4_CPNTF_GN7_SHIFT (0U) #define SEMA4_CPNTF_GN7(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN7_SHIFT)) & SEMA4_CPNTF_GN7_MASK) + #define SEMA4_CPNTF_GN6_MASK (0x2U) #define SEMA4_CPNTF_GN6_SHIFT (1U) #define SEMA4_CPNTF_GN6(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN6_SHIFT)) & SEMA4_CPNTF_GN6_MASK) + #define SEMA4_CPNTF_GN5_MASK (0x4U) #define SEMA4_CPNTF_GN5_SHIFT (2U) #define SEMA4_CPNTF_GN5(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN5_SHIFT)) & SEMA4_CPNTF_GN5_MASK) + #define SEMA4_CPNTF_GN4_MASK (0x8U) #define SEMA4_CPNTF_GN4_SHIFT (3U) #define SEMA4_CPNTF_GN4(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN4_SHIFT)) & SEMA4_CPNTF_GN4_MASK) + #define SEMA4_CPNTF_GN3_MASK (0x10U) #define SEMA4_CPNTF_GN3_SHIFT (4U) #define SEMA4_CPNTF_GN3(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN3_SHIFT)) & SEMA4_CPNTF_GN3_MASK) + #define SEMA4_CPNTF_GN2_MASK (0x20U) #define SEMA4_CPNTF_GN2_SHIFT (5U) #define SEMA4_CPNTF_GN2(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN2_SHIFT)) & SEMA4_CPNTF_GN2_MASK) + #define SEMA4_CPNTF_GN1_MASK (0x40U) #define SEMA4_CPNTF_GN1_SHIFT (6U) #define SEMA4_CPNTF_GN1(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN1_SHIFT)) & SEMA4_CPNTF_GN1_MASK) + #define SEMA4_CPNTF_GN0_MASK (0x80U) #define SEMA4_CPNTF_GN0_SHIFT (7U) #define SEMA4_CPNTF_GN0(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN0_SHIFT)) & SEMA4_CPNTF_GN0_MASK) + #define SEMA4_CPNTF_GN15_MASK (0x100U) #define SEMA4_CPNTF_GN15_SHIFT (8U) #define SEMA4_CPNTF_GN15(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN15_SHIFT)) & SEMA4_CPNTF_GN15_MASK) + #define SEMA4_CPNTF_GN14_MASK (0x200U) #define SEMA4_CPNTF_GN14_SHIFT (9U) #define SEMA4_CPNTF_GN14(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN14_SHIFT)) & SEMA4_CPNTF_GN14_MASK) + #define SEMA4_CPNTF_GN13_MASK (0x400U) #define SEMA4_CPNTF_GN13_SHIFT (10U) #define SEMA4_CPNTF_GN13(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN13_SHIFT)) & SEMA4_CPNTF_GN13_MASK) + #define SEMA4_CPNTF_GN12_MASK (0x800U) #define SEMA4_CPNTF_GN12_SHIFT (11U) #define SEMA4_CPNTF_GN12(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN12_SHIFT)) & SEMA4_CPNTF_GN12_MASK) + #define SEMA4_CPNTF_GN11_MASK (0x1000U) #define SEMA4_CPNTF_GN11_SHIFT (12U) #define SEMA4_CPNTF_GN11(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN11_SHIFT)) & SEMA4_CPNTF_GN11_MASK) + #define SEMA4_CPNTF_GN10_MASK (0x2000U) #define SEMA4_CPNTF_GN10_SHIFT (13U) #define SEMA4_CPNTF_GN10(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN10_SHIFT)) & SEMA4_CPNTF_GN10_MASK) + #define SEMA4_CPNTF_GN9_MASK (0x4000U) #define SEMA4_CPNTF_GN9_SHIFT (14U) #define SEMA4_CPNTF_GN9(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN9_SHIFT)) & SEMA4_CPNTF_GN9_MASK) + #define SEMA4_CPNTF_GN8_MASK (0x8000U) #define SEMA4_CPNTF_GN8_SHIFT (15U) #define SEMA4_CPNTF_GN8(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN8_SHIFT)) & SEMA4_CPNTF_GN8_MASK) @@ -73953,9 +82921,11 @@ typedef struct { /*! @name RSTGT - Semaphores (Secure) Reset Gate n */ /*! @{ */ + #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK (0xFFU) #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT (0U) #define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT)) & SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK) + #define SEMA4_RSTGT_RSTGTN_MASK (0xFF00U) #define SEMA4_RSTGT_RSTGTN_SHIFT (8U) #define SEMA4_RSTGT_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGTN_SHIFT)) & SEMA4_RSTGT_RSTGTN_MASK) @@ -73963,9 +82933,11 @@ typedef struct { /*! @name RSTNTF - Semaphores (Secure) Reset IRQ Notification */ /*! @{ */ + #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK (0xFFU) #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT (0U) #define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT)) & SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK) + #define SEMA4_RSTNTF_RSTNTN_MASK (0xFF00U) #define SEMA4_RSTNTF_RSTNTN_SHIFT (8U) #define SEMA4_RSTNTF_RSTNTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNTN_SHIFT)) & SEMA4_RSTNTF_RSTNTN_MASK) @@ -74004,63 +82976,64 @@ typedef struct { /** SEMC - Register Layout Typedef */ typedef struct { __IO uint32_t MCR; /**< Module Control Register, offset: 0x0 */ - __IO uint32_t IOCR; /**< IO Mux Control Register, offset: 0x4 */ + __IO uint32_t IOCR; /**< IO MUX Control Register, offset: 0x4 */ __IO uint32_t BMCR0; /**< Bus (AXI) Master Control Register 0, offset: 0x8 */ __IO uint32_t BMCR1; /**< Bus (AXI) Master Control Register 1, offset: 0xC */ - __IO uint32_t BR[9]; /**< Base Register 0 (For SDRAM CS0 device)..Base Register 8 (For NAND device), array offset: 0x10, array step: 0x4 */ + __IO uint32_t BR[9]; /**< Base Register 0..Base Register 8, array offset: 0x10, array step: 0x4 */ __IO uint32_t DLLCR; /**< DLL Control Register, offset: 0x34 */ __IO uint32_t INTEN; /**< Interrupt Enable Register, offset: 0x38 */ - __IO uint32_t INTR; /**< Interrupt Enable Register, offset: 0x3C */ - __IO uint32_t SDRAMCR0; /**< SDRAM control register 0, offset: 0x40 */ - __IO uint32_t SDRAMCR1; /**< SDRAM control register 1, offset: 0x44 */ - __IO uint32_t SDRAMCR2; /**< SDRAM control register 2, offset: 0x48 */ - __IO uint32_t SDRAMCR3; /**< SDRAM control register 3, offset: 0x4C */ - __IO uint32_t NANDCR0; /**< NAND control register 0, offset: 0x50 */ - __IO uint32_t NANDCR1; /**< NAND control register 1, offset: 0x54 */ - __IO uint32_t NANDCR2; /**< NAND control register 2, offset: 0x58 */ - __IO uint32_t NANDCR3; /**< NAND control register 3, offset: 0x5C */ - __IO uint32_t NORCR0; /**< NOR control register 0, offset: 0x60 */ - __IO uint32_t NORCR1; /**< NOR control register 1, offset: 0x64 */ - __IO uint32_t NORCR2; /**< NOR control register 2, offset: 0x68 */ - __IO uint32_t NORCR3; /**< NOR control register 3, offset: 0x6C */ - __IO uint32_t SRAMCR0; /**< SRAM control register 0, offset: 0x70 */ - __IO uint32_t SRAMCR1; /**< SRAM control register 1, offset: 0x74 */ - __IO uint32_t SRAMCR2; /**< SRAM control register 2, offset: 0x78 */ - uint32_t SRAMCR3; /**< SRAM control register 3, offset: 0x7C */ - __IO uint32_t DBICR0; /**< DBI-B control register 0, offset: 0x80 */ - __IO uint32_t DBICR1; /**< DBI-B control register 1, offset: 0x84 */ - uint8_t RESERVED_0[8]; - __IO uint32_t IPCR0; /**< IP Command control register 0, offset: 0x90 */ - __IO uint32_t IPCR1; /**< IP Command control register 1, offset: 0x94 */ - __IO uint32_t IPCR2; /**< IP Command control register 2, offset: 0x98 */ - __IO uint32_t IPCMD; /**< IP Command register, offset: 0x9C */ - __IO uint32_t IPTXDAT; /**< TX DATA register (for IP Command), offset: 0xA0 */ + __IO uint32_t INTR; /**< Interrupt Register, offset: 0x3C */ + __IO uint32_t SDRAMCR0; /**< SDRAM Control Register 0, offset: 0x40 */ + __IO uint32_t SDRAMCR1; /**< SDRAM Control Register 1, offset: 0x44 */ + __IO uint32_t SDRAMCR2; /**< SDRAM Control Register 2, offset: 0x48 */ + __IO uint32_t SDRAMCR3; /**< SDRAM Control Register 3, offset: 0x4C */ + __IO uint32_t NANDCR0; /**< NAND Control Register 0, offset: 0x50 */ + __IO uint32_t NANDCR1; /**< NAND Control Register 1, offset: 0x54 */ + __IO uint32_t NANDCR2; /**< NAND Control Register 2, offset: 0x58 */ + __IO uint32_t NANDCR3; /**< NAND Control Register 3, offset: 0x5C */ + __IO uint32_t NORCR0; /**< NOR Control Register 0, offset: 0x60 */ + __IO uint32_t NORCR1; /**< NOR Control Register 1, offset: 0x64 */ + __IO uint32_t NORCR2; /**< NOR Control Register 2, offset: 0x68 */ + __IO uint32_t NORCR3; /**< NOR Control Register 3, offset: 0x6C */ + __IO uint32_t SRAMCR0; /**< SRAM Control Register 0, offset: 0x70 */ + __IO uint32_t SRAMCR1; /**< SRAM Control Register 1, offset: 0x74 */ + __IO uint32_t SRAMCR2; /**< SRAM Control Register 2, offset: 0x78 */ + uint32_t SRAMCR3; /**< SRAM Control Register 3, offset: 0x7C */ + __IO uint32_t DBICR0; /**< DBI-B Control Register 0, offset: 0x80 */ + __IO uint32_t DBICR1; /**< DBI-B Control Register 1, offset: 0x84 */ + __IO uint32_t DBICR2; /**< DBI-B Control Register 2, offset: 0x88 */ + uint8_t RESERVED_0[4]; + __IO uint32_t IPCR0; /**< IP Command Control Register 0, offset: 0x90 */ + __IO uint32_t IPCR1; /**< IP Command Control Register 1, offset: 0x94 */ + __IO uint32_t IPCR2; /**< IP Command Control Register 2, offset: 0x98 */ + __IO uint32_t IPCMD; /**< IP Command Register, offset: 0x9C */ + __IO uint32_t IPTXDAT; /**< TX DATA Register, offset: 0xA0 */ uint8_t RESERVED_1[12]; - __I uint32_t IPRXDAT; /**< RX DATA register (for IP Command), offset: 0xB0 */ + __I uint32_t IPRXDAT; /**< RX DATA Register, offset: 0xB0 */ uint8_t RESERVED_2[12]; - __I uint32_t STS0; /**< Status register 0, offset: 0xC0 */ - uint32_t STS1; /**< Status register 1, offset: 0xC4 */ - __I uint32_t STS2; /**< Status register 2, offset: 0xC8 */ - uint32_t STS3; /**< Status register 3, offset: 0xCC */ - uint32_t STS4; /**< Status register 4, offset: 0xD0 */ - uint32_t STS5; /**< Status register 5, offset: 0xD4 */ - uint32_t STS6; /**< Status register 6, offset: 0xD8 */ - uint32_t STS7; /**< Status register 7, offset: 0xDC */ - uint32_t STS8; /**< Status register 8, offset: 0xE0 */ - uint32_t STS9; /**< Status register 9, offset: 0xE4 */ - uint32_t STS10; /**< Status register 10, offset: 0xE8 */ - uint32_t STS11; /**< Status register 11, offset: 0xEC */ - __I uint32_t STS12; /**< Status register 12, offset: 0xF0 */ - __I uint32_t STS13; /**< Status register 13, offset: 0xF4 */ - uint32_t STS14; /**< Status register 14, offset: 0xF8 */ - uint32_t STS15; /**< Status register 15, offset: 0xFC */ - __IO uint32_t BR9; /**< Base Register 9 (For PSRAM device 1), offset: 0x100 */ - __IO uint32_t BR10; /**< Base Register 10 (For PSRAM device 2), offset: 0x104 */ - __IO uint32_t BR11; /**< Base Register 11 (For PSRAM device 3), offset: 0x108 */ + __I uint32_t STS0; /**< Status Register 0, offset: 0xC0 */ + uint32_t STS1; /**< Status Register 1, offset: 0xC4 */ + __I uint32_t STS2; /**< Status Register 2, offset: 0xC8 */ + uint32_t STS3; /**< Status Register 3, offset: 0xCC */ + uint32_t STS4; /**< Status Register 4, offset: 0xD0 */ + uint32_t STS5; /**< Status Register 5, offset: 0xD4 */ + uint32_t STS6; /**< Status Register 6, offset: 0xD8 */ + uint32_t STS7; /**< Status Register 7, offset: 0xDC */ + uint32_t STS8; /**< Status Register 8, offset: 0xE0 */ + uint32_t STS9; /**< Status Register 9, offset: 0xE4 */ + uint32_t STS10; /**< Status Register 10, offset: 0xE8 */ + uint32_t STS11; /**< Status Register 11, offset: 0xEC */ + __I uint32_t STS12; /**< Status Register 12, offset: 0xF0 */ + __I uint32_t STS13; /**< Status Register 13, offset: 0xF4 */ + uint32_t STS14; /**< Status Register 14, offset: 0xF8 */ + uint32_t STS15; /**< Status Register 15, offset: 0xFC */ + __IO uint32_t BR9; /**< Base Register 9, offset: 0x100 */ + __IO uint32_t BR10; /**< Base Register 10, offset: 0x104 */ + __IO uint32_t BR11; /**< Base Register 11, offset: 0x108 */ uint8_t RESERVED_3[20]; - __IO uint32_t SRAMCR4; /**< SRAM control register 4, offset: 0x120 */ - __IO uint32_t SRAMCR5; /**< SRAM control register 5, offset: 0x124 */ - __IO uint32_t SRAMCR6; /**< SRAM control register 6, offset: 0x128 */ + __IO uint32_t SRAMCR4; /**< SRAM Control Register 4, offset: 0x120 */ + __IO uint32_t SRAMCR5; /**< SRAM Control Register 5, offset: 0x124 */ + __IO uint32_t SRAMCR6; /**< SRAM Control Register 6, offset: 0x128 */ uint8_t RESERVED_4[36]; __IO uint32_t DCCR; /**< Delay Chain Control Register, offset: 0x150 */ } SEMC_Type; @@ -74076,11 +83049,15 @@ typedef struct { /*! @name MCR - Module Control Register */ /*! @{ */ + #define SEMC_MCR_SWRST_MASK (0x1U) #define SEMC_MCR_SWRST_SHIFT (0U) /*! SWRST - Software Reset + * 0b0..No reset + * 0b1..Reset */ #define SEMC_MCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK) + #define SEMC_MCR_MDIS_MASK (0x2U) #define SEMC_MCR_MDIS_SHIFT (1U) /*! MDIS - Module Disable @@ -74088,6 +83065,7 @@ typedef struct { * 0b1..Module disabled */ #define SEMC_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK) + #define SEMC_MCR_DQSMD_MASK (0x4U) #define SEMC_MCR_DQSMD_SHIFT (2U) /*! DQSMD - DQS (read strobe) mode @@ -74095,154 +83073,167 @@ typedef struct { * 0b1..Dummy read strobe loopbacked from DQS pad */ #define SEMC_MCR_DQSMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK) + #define SEMC_MCR_WPOL0_MASK (0x40U) #define SEMC_MCR_WPOL0_SHIFT (6U) -/*! WPOL0 - WAIT/RDY# polarity for NOR/PSRAM - * 0b0..Active low - * 0b1..Active high +/*! WPOL0 - WAIT/RDY polarity for SRAM/NOR + * 0b0..WAIT/RDY polarity is not changed. + * 0b1..WAIT/RDY polarity is inverted. */ #define SEMC_MCR_WPOL0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK) + #define SEMC_MCR_WPOL1_MASK (0x80U) #define SEMC_MCR_WPOL1_SHIFT (7U) -/*! WPOL1 - WAIT/RDY# polarity for NAND - * 0b0..Active low - * 0b1..Active high +/*! WPOL1 - R/B# polarity for NAND device + * 0b0..R/B# polarity is not changed. + * 0b1..R/B# polarity is inverted. */ #define SEMC_MCR_WPOL1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK) + #define SEMC_MCR_CTO_MASK (0xFF0000U) #define SEMC_MCR_CTO_SHIFT (16U) /*! CTO - Command Execution timeout cycles */ #define SEMC_MCR_CTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK) + #define SEMC_MCR_BTO_MASK (0x1F000000U) #define SEMC_MCR_BTO_SHIFT (24U) /*! BTO - Bus timeout cycles * 0b00000..255*1 - * 0b00001-0b11110..255*2 - 255*2^30 - * 0b11111..255*2^31 + * 0b00001..255*2 + * 0b11111..255*231 */ #define SEMC_MCR_BTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK) /*! @} */ -/*! @name IOCR - IO Mux Control Register */ +/*! @name IOCR - IO MUX Control Register */ /*! @{ */ + #define SEMC_IOCR_MUX_A8_MASK (0xFU) #define SEMC_IOCR_MUX_A8_SHIFT (0U) -/*! MUX_A8 - SEMC_A8 output selection - * 0b0000-0b0011..SDRAM Address bit (A8) +/*! MUX_A8 - SEMC_ADDR08 output selection + * 0b0000-0b0011..SDRAM Address bit 8 (A8) or NOR/SRAM Address bit 24 (A24) in ADMUX 16bit mode * 0b0100..NAND CE# * 0b0101..NOR CE# - * 0b0110..PSRAM CE# 0 + * 0b0110..SRAM CE# 0 * 0b0111..DBI CSX - * 0b1000..PSRAM CE# 1 - * 0b1001..PSRAM CE# 2 - * 0b1010..PSRAM CE# 3 - * 0b1011-0b1111..SDRAM Address bit (A8) + * 0b1000..SRAM CE# 1 + * 0b1001..SRAM CE# 2 + * 0b1010..SRAM CE# 3 + * 0b1011-0b1111..SDRAM Address bit 8 (A8) or NOR/SRAM Address bit 24 (A24) in ADMUX 16bit mode */ #define SEMC_IOCR_MUX_A8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK) + #define SEMC_IOCR_MUX_CSX0_MASK (0xF0U) #define SEMC_IOCR_MUX_CSX0_SHIFT (4U) /*! MUX_CSX0 - SEMC_CSX0 output selection - * 0b0000..NOR/PSRAM Address bit 24 (A24) + * 0b0000..NOR/SRAM Address bit 24 (A24) in Non-ADMUX mode * 0b0001..SDRAM CS1 * 0b0010..SDRAM CS2 * 0b0011..SDRAM CS3 * 0b0100..NAND CE# * 0b0101..NOR CE# - * 0b0110..PSRAM CE# 0 + * 0b0110..SRAM CE# 0 * 0b0111..DBI CSX - * 0b1000..PSRAM CE# 1 - * 0b1001..PSRAM CE# 2 - * 0b1010..PSRAM CE# 3 - * 0b1011-0b1111..NOR/PSRAM Address bit 24 (A24) + * 0b1000..SRAM CE# 1 + * 0b1001..SRAM CE# 2 + * 0b1010..SRAM CE# 3 + * 0b1011-0b1111..NOR/SRAM Address bit 24 (A24) */ #define SEMC_IOCR_MUX_CSX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK) + #define SEMC_IOCR_MUX_CSX1_MASK (0xF00U) #define SEMC_IOCR_MUX_CSX1_SHIFT (8U) /*! MUX_CSX1 - SEMC_CSX1 output selection - * 0b0000..NOR/PSRAM Address bit 25 (A25) + * 0b0000..NOR/SRAM Address bit 25 (A25) in Non-ADMUX mode * 0b0001..SDRAM CS1 * 0b0010..SDRAM CS2 * 0b0011..SDRAM CS3 * 0b0100..NAND CE# * 0b0101..NOR CE# - * 0b0110..PSRAM CE# 0 + * 0b0110..SRAM CE# 0 * 0b0111..DBI CSX - * 0b1000..PSRAM CE# 1 - * 0b1001..PSRAM CE# 2 - * 0b1010..PSRAM CE# 3 - * 0b1011-0b1111..NOR/PSRAM Address bit 25 (A25) + * 0b1000..SRAM CE# 1 + * 0b1001..SRAM CE# 2 + * 0b1010..SRAM CE# 3 + * 0b1011-0b1111..NOR/SRAM Address bit 25 (A25) */ #define SEMC_IOCR_MUX_CSX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK) + #define SEMC_IOCR_MUX_CSX2_MASK (0xF000U) #define SEMC_IOCR_MUX_CSX2_SHIFT (12U) /*! MUX_CSX2 - SEMC_CSX2 output selection - * 0b0000..NOR/PSRAM Address bit 26 (A26) + * 0b0000..NOR/SRAM Address bit 26 (A26) in Non-ADMUX mode * 0b0001..SDRAM CS1 * 0b0010..SDRAM CS2 * 0b0011..SDRAM CS3 * 0b0100..NAND CE# * 0b0101..NOR CE# - * 0b0110..PSRAM CE# 0 + * 0b0110..SRAM CE# 0 * 0b0111..DBI CSX - * 0b1000..PSRAM CE# 1 - * 0b1001..PSRAM CE# 2 - * 0b1010..PSRAM CE# 3 - * 0b1011-0b1111..NOR/PSRAM Address bit 26 (A26) + * 0b1000..SRAM CE# 1 + * 0b1001..SRAM CE# 2 + * 0b1010..SRAM CE# 3 + * 0b1011-0b1111..NOR/SRAM Address bit 26 (A26) */ #define SEMC_IOCR_MUX_CSX2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK) + #define SEMC_IOCR_MUX_CSX3_MASK (0xF0000U) #define SEMC_IOCR_MUX_CSX3_SHIFT (16U) /*! MUX_CSX3 - SEMC_CSX3 output selection - * 0b0000..NOR/PSRAM Address bit 27 (A27) + * 0b0000..NOR/SRAM Address bit 27 (A27) in Non-ADMUX mode * 0b0001..SDRAM CS1 * 0b0010..SDRAM CS2 * 0b0011..SDRAM CS3 * 0b0100..NAND CE# * 0b0101..NOR CE# - * 0b0110..PSRAM CE# 0 + * 0b0110..SRAM CE# 0 * 0b0111..DBI CSX - * 0b1000..PSRAM CE# 1 - * 0b1001..PSRAM CE# 2 - * 0b1010..PSRAM CE# 3 - * 0b1011-0b1111..NOR/PSRAM Address bit 27 (A27) + * 0b1000..SRAM CE# 1 + * 0b1001..SRAM CE# 2 + * 0b1010..SRAM CE# 3 + * 0b1011-0b1111..NOR/SRAM Address bit 27 (A27) */ #define SEMC_IOCR_MUX_CSX3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK) + #define SEMC_IOCR_MUX_RDY_MASK (0xF00000U) #define SEMC_IOCR_MUX_RDY_SHIFT (20U) /*! MUX_RDY - SEMC_RDY function selection - * 0b0000..NAND Ready/Wait# input + * 0b0000..NAND R/B# input * 0b0001..SDRAM CS1 * 0b0010..SDRAM CS2 * 0b0011..SDRAM CS3 - * 0b0100..NOR/PSRAM Address bit 27 (A27) + * 0b0100..NOR/SRAM Address bit 27 (A27) in Non-ADMUX mode * 0b0101..NOR CE# - * 0b0110..PSRAM CE# 0 + * 0b0110..SRAM CE# 0 * 0b0111..DBI CSX - * 0b1000..PSRAM CE# 1 - * 0b1001..PSRAM CE# 2 - * 0b1010..PSRAM CE# 3 - * 0b1011-0b1111..NOR/PSRAM Address bit 27 (A27) + * 0b1000..SRAM CE# 1 + * 0b1001..SRAM CE# 2 + * 0b1010..SRAM CE# 3 + * 0b1011-0b1111..NOR/SRAM Address bit 27 */ #define SEMC_IOCR_MUX_RDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK) + #define SEMC_IOCR_MUX_CLKX0_MASK (0x3000000U) #define SEMC_IOCR_MUX_CLKX0_SHIFT (24U) /*! MUX_CLKX0 - SEMC_CLKX0 function selection * 0b00..Keep low * 0b01..NOR clock * 0b10..SRAM clock - * 0b11..NOR and SRAM clock + * 0b11..NOR and SRAM clock, suitable for Multi-Chip Product package */ #define SEMC_IOCR_MUX_CLKX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX0_SHIFT)) & SEMC_IOCR_MUX_CLKX0_MASK) + #define SEMC_IOCR_MUX_CLKX1_MASK (0xC000000U) #define SEMC_IOCR_MUX_CLKX1_SHIFT (26U) /*! MUX_CLKX1 - SEMC_CLKX1 function selection * 0b00..Keep low * 0b01..NOR clock * 0b10..SRAM clock - * 0b11..NOR and SRAM clock + * 0b11..NOR and SRAM clock, suitable for Multi-Chip Product package */ #define SEMC_IOCR_MUX_CLKX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX1_SHIFT)) & SEMC_IOCR_MUX_CLKX1_MASK) + #define SEMC_IOCR_CLKX0_AO_MASK (0x10000000U) #define SEMC_IOCR_CLKX0_AO_SHIFT (28U) /*! CLKX0_AO - SEMC_CLKX0 Always On @@ -74250,6 +83241,7 @@ typedef struct { * 0b1..SEMC_CLKX0 is always on */ #define SEMC_IOCR_CLKX0_AO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_CLKX0_AO_SHIFT)) & SEMC_IOCR_CLKX0_AO_MASK) + #define SEMC_IOCR_CLKX1_AO_MASK (0x20000000U) #define SEMC_IOCR_CLKX1_AO_SHIFT (29U) /*! CLKX1_AO - SEMC_CLKX1 Always On @@ -74261,73 +83253,77 @@ typedef struct { /*! @name BMCR0 - Bus (AXI) Master Control Register 0 */ /*! @{ */ + #define SEMC_BMCR0_WQOS_MASK (0xFU) #define SEMC_BMCR0_WQOS_SHIFT (0U) -/*! WQOS - Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a - * priority indicator for the associated write or read transaction. A higher value indicates a higher - * priority transaction. AxQOS is multiplied by WQOS to get weight score. +/*! WQOS - Weight of QOS */ #define SEMC_BMCR0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK) + #define SEMC_BMCR0_WAGE_MASK (0xF0U) #define SEMC_BMCR0_WAGE_SHIFT (4U) -/*! WAGE - Weight of AGE calculation. Each command in queue has an age signal to indicate its wait - * period. It is multiplied by WAGE to get weight score. +/*! WAGE - Weight of AGE */ #define SEMC_BMCR0_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK) + #define SEMC_BMCR0_WSH_MASK (0xFF00U) #define SEMC_BMCR0_WSH_SHIFT (8U) -/*! WSH - Weight of Slave Hit without read/write switch. This weight score is valid when queue - * command's slave is same as current executing command without read/write operation switch. +/*! WSH - Weight of Slave Hit without read/write switch */ #define SEMC_BMCR0_WSH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK) + #define SEMC_BMCR0_WRWS_MASK (0xFF0000U) #define SEMC_BMCR0_WRWS_SHIFT (16U) -/*! WRWS - Weight of slave hit with Read/Write Switch. This weight score is valid when queue - * command's slave is same as current executing command with read/write operation switch. +/*! WRWS - Weight of slave hit with Read/Write Switch */ #define SEMC_BMCR0_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK) /*! @} */ /*! @name BMCR1 - Bus (AXI) Master Control Register 1 */ /*! @{ */ + #define SEMC_BMCR1_WQOS_MASK (0xFU) #define SEMC_BMCR1_WQOS_SHIFT (0U) -/*! WQOS - Weight of QOS calculation. AXI bus access has AxQOS signal set, which is used as a - * priority indicator for the associated write or read transaction. A higher value indicates a higher - * priority transaction. AxQOS is multiplied by WQOS to get weight score. +/*! WQOS - Weight of QOS */ #define SEMC_BMCR1_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK) + #define SEMC_BMCR1_WAGE_MASK (0xF0U) #define SEMC_BMCR1_WAGE_SHIFT (4U) -/*! WAGE - Weight of AGE calculation. Each command in queue has an age signal to indicate its wait - * period. It is multiplied by WAGE to get weight score. +/*! WAGE - Weight of AGE */ #define SEMC_BMCR1_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK) + #define SEMC_BMCR1_WPH_MASK (0xFF00U) #define SEMC_BMCR1_WPH_SHIFT (8U) -/*! WPH - Weight of Page Hit. This weight score is valid when queue command's page hits current executing command. +/*! WPH - Weight of Page Hit */ #define SEMC_BMCR1_WPH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK) + #define SEMC_BMCR1_WRWS_MASK (0xFF0000U) #define SEMC_BMCR1_WRWS_SHIFT (16U) -/*! WRWS - Weight of slave hit without Read/Write Switch. This weight score is valid when queue - * command's read/write operation is same as current executing command. +/*! WRWS - Weight of slave hit without Read/Write Switch */ #define SEMC_BMCR1_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK) + #define SEMC_BMCR1_WBR_MASK (0xFF000000U) #define SEMC_BMCR1_WBR_SHIFT (24U) -/*! WBR - Weight of Bank Rotation. This weight score is valid when queue command's bank is not same as current executing command. +/*! WBR - Weight of Bank Rotation */ #define SEMC_BMCR1_WBR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK) /*! @} */ -/*! @name BR - Base Register 0 (For SDRAM CS0 device)..Base Register 8 (For NAND device) */ +/*! @name BR - Base Register 0..Base Register 8 */ /*! @{ */ + #define SEMC_BR_VLD_MASK (0x1U) #define SEMC_BR_VLD_SHIFT (0U) /*! VLD - Valid + * 0b0..The memory is invalid, can not be accessed. + * 0b1..The memory is valid, can be accessed. */ #define SEMC_BR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK) + #define SEMC_BR_MS_MASK (0x3EU) #define SEMC_BR_MS_SHIFT (1U) /*! MS - Memory size @@ -74354,6 +83350,7 @@ typedef struct { * 0b10100-0b11111..4GB */ #define SEMC_BR_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK) + #define SEMC_BR_BA_MASK (0xFFFFF000U) #define SEMC_BR_BA_SHIFT (12U) /*! BA - Base Address @@ -74366,38 +83363,47 @@ typedef struct { /*! @name DLLCR - DLL Control Register */ /*! @{ */ + #define SEMC_DLLCR_DLLEN_MASK (0x1U) #define SEMC_DLLCR_DLLEN_SHIFT (0U) -/*! DLLEN - DLL calibration enable. +/*! DLLEN - DLL calibration enable + * 0b0..DLL calibration is disabled. + * 0b1..DLL calibration is enabled. */ #define SEMC_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLEN_SHIFT)) & SEMC_DLLCR_DLLEN_MASK) + #define SEMC_DLLCR_DLLRESET_MASK (0x2U) #define SEMC_DLLCR_DLLRESET_SHIFT (1U) -/*! DLLRESET - Software could force a reset on DLL by setting this field to 0x1. This causes the DLL - * to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset - * action is edge triggered, so software need to clear this bit after set this bit (no delay - * limitation). +/*! DLLRESET - DLL Reset + * 0b0..DLL is not reset. + * 0b1..DLL is reset. */ #define SEMC_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLRESET_SHIFT)) & SEMC_DLLCR_DLLRESET_MASK) + #define SEMC_DLLCR_SLVDLYTARGET_MASK (0x78U) #define SEMC_DLLCR_SLVDLYTARGET_SHIFT (3U) -/*! SLVDLYTARGET - The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (ipgclock). +/*! SLVDLYTARGET - Delay Target for Slave */ #define SEMC_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_SLVDLYTARGET_SHIFT)) & SEMC_DLLCR_SLVDLYTARGET_MASK) + #define SEMC_DLLCR_OVRDEN_MASK (0x100U) #define SEMC_DLLCR_OVRDEN_SHIFT (8U) -/*! OVRDEN - Slave clock delay line delay cell number selection override enable. +/*! OVRDEN - Override Enable + * 0b0..The delay cell number is not overridden. + * 0b1..The delay cell number is overridden. */ #define SEMC_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDEN_SHIFT)) & SEMC_DLLCR_OVRDEN_MASK) + #define SEMC_DLLCR_OVRDVAL_MASK (0x7E00U) #define SEMC_DLLCR_OVRDVAL_SHIFT (9U) -/*! OVRDVAL - Slave clock delay line delay cell number selection override value. +/*! OVRDVAL - Override Value */ #define SEMC_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDVAL_SHIFT)) & SEMC_DLLCR_OVRDVAL_MASK) /*! @} */ /*! @name INTEN - Interrupt Enable Register */ /*! @{ */ + #define SEMC_INTEN_IPCMDDONEEN_MASK (0x1U) #define SEMC_INTEN_IPCMDDONEEN_SHIFT (0U) /*! IPCMDDONEEN - IP command done interrupt enable @@ -74405,6 +83411,7 @@ typedef struct { * 0b1..Interrupt is enabled */ #define SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK) + #define SEMC_INTEN_IPCMDERREN_MASK (0x2U) #define SEMC_INTEN_IPCMDERREN_SHIFT (1U) /*! IPCMDERREN - IP command error interrupt enable @@ -74412,6 +83419,7 @@ typedef struct { * 0b1..Interrupt is enabled */ #define SEMC_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK) + #define SEMC_INTEN_AXICMDERREN_MASK (0x4U) #define SEMC_INTEN_AXICMDERREN_SHIFT (2U) /*! AXICMDERREN - AXI command error interrupt enable @@ -74419,6 +83427,7 @@ typedef struct { * 0b1..Interrupt is enabled */ #define SEMC_INTEN_AXICMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK) + #define SEMC_INTEN_AXIBUSERREN_MASK (0x8U) #define SEMC_INTEN_AXIBUSERREN_SHIFT (3U) /*! AXIBUSERREN - AXI bus error interrupt enable @@ -74426,6 +83435,7 @@ typedef struct { * 0b1..Interrupt is enabled */ #define SEMC_INTEN_AXIBUSERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK) + #define SEMC_INTEN_NDPAGEENDEN_MASK (0x10U) #define SEMC_INTEN_NDPAGEENDEN_SHIFT (4U) /*! NDPAGEENDEN - NAND page end interrupt enable @@ -74433,6 +83443,7 @@ typedef struct { * 0b1..Interrupt is enabled */ #define SEMC_INTEN_NDPAGEENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK) + #define SEMC_INTEN_NDNOPENDEN_MASK (0x20U) #define SEMC_INTEN_NDNOPENDEN_SHIFT (5U) /*! NDNOPENDEN - NAND no pending AXI access interrupt enable @@ -74442,42 +83453,61 @@ typedef struct { #define SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK) /*! @} */ -/*! @name INTR - Interrupt Enable Register */ +/*! @name INTR - Interrupt Register */ /*! @{ */ + #define SEMC_INTR_IPCMDDONE_MASK (0x1U) #define SEMC_INTR_IPCMDDONE_SHIFT (0U) /*! IPCMDDONE - IP command normal done interrupt + * 0b0..IP command is not done. + * 0b1..IP command is done. */ #define SEMC_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK) + #define SEMC_INTR_IPCMDERR_MASK (0x2U) #define SEMC_INTR_IPCMDERR_SHIFT (1U) /*! IPCMDERR - IP command error done interrupt + * 0b0..No IP command error. + * 0b1..IP command error occurs. */ #define SEMC_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK) + #define SEMC_INTR_AXICMDERR_MASK (0x4U) #define SEMC_INTR_AXICMDERR_SHIFT (2U) /*! AXICMDERR - AXI command error interrupt + * 0b0..No AXI command error. + * 0b1..AXI command error occurs. */ #define SEMC_INTR_AXICMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK) + #define SEMC_INTR_AXIBUSERR_MASK (0x8U) #define SEMC_INTR_AXIBUSERR_SHIFT (3U) /*! AXIBUSERR - AXI bus error interrupt + * 0b0..No AXI bus error. + * 0b1..AXI bus error occurs. */ #define SEMC_INTR_AXIBUSERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK) + #define SEMC_INTR_NDPAGEEND_MASK (0x10U) #define SEMC_INTR_NDPAGEEND_SHIFT (4U) /*! NDPAGEEND - NAND page end interrupt + * 0b0..The last address of main space in the NAND is not written by AXI command. + * 0b1..The last address of main space in the NAND is written by AXI command. */ #define SEMC_INTR_NDPAGEEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK) + #define SEMC_INTR_NDNOPEND_MASK (0x20U) #define SEMC_INTR_NDNOPEND_SHIFT (5U) -/*! NDNOPEND - NAND no pending AXI access interrupt +/*! NDNOPEND - NAND no pending AXI write transaction interrupt + * 0b0..At least one NAND AXI write transaction is pending or no NAND write transaction is sent to the queue. + * 0b1..All NAND AXI write pending transactions are finished. */ #define SEMC_INTR_NDNOPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK) /*! @} */ -/*! @name SDRAMCR0 - SDRAM control register 0 */ +/*! @name SDRAMCR0 - SDRAM Control Register 0 */ /*! @{ */ + #define SEMC_SDRAMCR0_PS_MASK (0x3U) #define SEMC_SDRAMCR0_PS_SHIFT (0U) /*! PS - Port Size @@ -74487,6 +83517,7 @@ typedef struct { * 0b11..Reserved */ #define SEMC_SDRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK) + #define SEMC_SDRAMCR0_BL_MASK (0x70U) #define SEMC_SDRAMCR0_BL_SHIFT (4U) /*! BL - Burst Length @@ -74500,22 +83531,25 @@ typedef struct { * 0b111..8 */ #define SEMC_SDRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK) + #define SEMC_SDRAMCR0_COL8_MASK (0x80U) #define SEMC_SDRAMCR0_COL8_SHIFT (7U) -/*! COL8 - Column 8 selection bit +/*! COL8 - Column 8 selection * 0b0..Column address bit number is decided by COL field. * 0b1..Column address bit number is 8. COL field is ignored. */ #define SEMC_SDRAMCR0_COL8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL8_SHIFT)) & SEMC_SDRAMCR0_COL8_MASK) + #define SEMC_SDRAMCR0_COL_MASK (0x300U) #define SEMC_SDRAMCR0_COL_SHIFT (8U) /*! COL - Column address bit number - * 0b00..12 bit - * 0b01..11 bit - * 0b10..10 bit - * 0b11..9 bit + * 0b00..12 + * 0b01..11 + * 0b10..10 + * 0b11..9 */ #define SEMC_SDRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK) + #define SEMC_SDRAMCR0_CL_MASK (0xC00U) #define SEMC_SDRAMCR0_CL_SHIFT (10U) /*! CL - CAS Latency @@ -74525,6 +83559,7 @@ typedef struct { * 0b11..3 */ #define SEMC_SDRAMCR0_CL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK) + #define SEMC_SDRAMCR0_BANK2_MASK (0x4000U) #define SEMC_SDRAMCR0_BANK2_SHIFT (14U) /*! BANK2 - 2 Bank selection bit @@ -74534,73 +83569,87 @@ typedef struct { #define SEMC_SDRAMCR0_BANK2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BANK2_SHIFT)) & SEMC_SDRAMCR0_BANK2_MASK) /*! @} */ -/*! @name SDRAMCR1 - SDRAM control register 1 */ +/*! @name SDRAMCR1 - SDRAM Control Register 1 */ /*! @{ */ + #define SEMC_SDRAMCR1_PRE2ACT_MASK (0xFU) #define SEMC_SDRAMCR1_PRE2ACT_SHIFT (0U) -/*! PRE2ACT - PRECHARGE to ACT/Refresh wait time +/*! PRE2ACT - PRECHARGE to ACTIVE/REFRESH command wait time */ #define SEMC_SDRAMCR1_PRE2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK) + #define SEMC_SDRAMCR1_ACT2RW_MASK (0xF0U) #define SEMC_SDRAMCR1_ACT2RW_SHIFT (4U) -/*! ACT2RW - ACT to Read/Write wait time +/*! ACT2RW - ACTIVE to READ/WRITE delay */ #define SEMC_SDRAMCR1_ACT2RW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK) + #define SEMC_SDRAMCR1_RFRC_MASK (0x1F00U) #define SEMC_SDRAMCR1_RFRC_SHIFT (8U) -/*! RFRC - Refresh recovery time +/*! RFRC - REFRESH recovery time */ #define SEMC_SDRAMCR1_RFRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK) + #define SEMC_SDRAMCR1_WRC_MASK (0xE000U) #define SEMC_SDRAMCR1_WRC_SHIFT (13U) -/*! WRC - Write recovery time +/*! WRC - WRITE recovery time */ #define SEMC_SDRAMCR1_WRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK) + #define SEMC_SDRAMCR1_CKEOFF_MASK (0xF0000U) #define SEMC_SDRAMCR1_CKEOFF_SHIFT (16U) -/*! CKEOFF - CKE OFF minimum time +/*! CKEOFF - CKE off minimum time */ #define SEMC_SDRAMCR1_CKEOFF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK) + #define SEMC_SDRAMCR1_ACT2PRE_MASK (0xF00000U) #define SEMC_SDRAMCR1_ACT2PRE_SHIFT (20U) -/*! ACT2PRE - ACT to Precharge minimum time +/*! ACT2PRE - ACTIVE to PRECHARGE minimum time */ #define SEMC_SDRAMCR1_ACT2PRE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK) /*! @} */ -/*! @name SDRAMCR2 - SDRAM control register 2 */ +/*! @name SDRAMCR2 - SDRAM Control Register 2 */ /*! @{ */ + #define SEMC_SDRAMCR2_SRRC_MASK (0xFFU) #define SEMC_SDRAMCR2_SRRC_SHIFT (0U) -/*! SRRC - Self Refresh Recovery time +/*! SRRC - SELF REFRESH recovery time */ #define SEMC_SDRAMCR2_SRRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK) + #define SEMC_SDRAMCR2_REF2REF_MASK (0xFF00U) #define SEMC_SDRAMCR2_REF2REF_SHIFT (8U) -/*! REF2REF - Refresh to Refresh wait time +/*! REF2REF - REFRESH to REFRESH delay */ #define SEMC_SDRAMCR2_REF2REF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK) + #define SEMC_SDRAMCR2_ACT2ACT_MASK (0xFF0000U) #define SEMC_SDRAMCR2_ACT2ACT_SHIFT (16U) -/*! ACT2ACT - ACT to ACT wait time +/*! ACT2ACT - ACTIVE to ACTIVE delay */ #define SEMC_SDRAMCR2_ACT2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK) + #define SEMC_SDRAMCR2_ITO_MASK (0xFF000000U) #define SEMC_SDRAMCR2_ITO_SHIFT (24U) -/*! ITO - SDRAM Idle timeout +/*! ITO - SDRAM idle timeout * 0b00000000..IDLE timeout period is 256*Prescale period. * 0b00000001-0b11111111..IDLE timeout period is ITO*Prescale period. */ #define SEMC_SDRAMCR2_ITO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK) /*! @} */ -/*! @name SDRAMCR3 - SDRAM control register 3 */ +/*! @name SDRAMCR3 - SDRAM Control Register 3 */ /*! @{ */ + #define SEMC_SDRAMCR3_REN_MASK (0x1U) #define SEMC_SDRAMCR3_REN_SHIFT (0U) /*! REN - Refresh enable + * 0b0..The SEMC does not send AUTO REFRESH command automatically + * 0b1..The SEMC sends AUTO REFRESH command automatically */ #define SEMC_SDRAMCR3_REN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK) + #define SEMC_SDRAMCR3_REBL_MASK (0xEU) #define SEMC_SDRAMCR3_REBL_SHIFT (1U) /*! REBL - Refresh burst length @@ -74614,31 +83663,35 @@ typedef struct { * 0b111..8 */ #define SEMC_SDRAMCR3_REBL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK) + #define SEMC_SDRAMCR3_PRESCALE_MASK (0xFF00U) #define SEMC_SDRAMCR3_PRESCALE_SHIFT (8U) -/*! PRESCALE - Prescaler timer period - * 0b00000000..256*16 clock cycles - * 0b00000001-0b11111111..PRESCALE*16 clock cycles +/*! PRESCALE - Prescaler period + * 0b00000000..(256*16+1) clock cycles + * 0b00000001-0b11111111..(PRESCALE*16+1) clock cycles */ #define SEMC_SDRAMCR3_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK) + #define SEMC_SDRAMCR3_RT_MASK (0xFF0000U) #define SEMC_SDRAMCR3_RT_SHIFT (16U) /*! RT - Refresh timer period - * 0b00000000..256*Prescaler period - * 0b00000001-0b11111111..RT*Prescaler period + * 0b00000000..(256+1)*(Prescaler period) + * 0b00000001-0b11111111..(RT+1)*(Prescaler period) */ #define SEMC_SDRAMCR3_RT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK) + #define SEMC_SDRAMCR3_UT_MASK (0xFF000000U) #define SEMC_SDRAMCR3_UT_SHIFT (24U) -/*! UT - Refresh urgent threshold - * 0b00000000..256*Prescaler period - * 0b00000001-0b11111111..UT*Prescaler period +/*! UT - Urgent refresh threshold + * 0b00000000..256*(Prescaler period) + * 0b00000001-0b11111111..UT*(Prescaler period) */ #define SEMC_SDRAMCR3_UT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK) /*! @} */ -/*! @name NANDCR0 - NAND control register 0 */ +/*! @name NANDCR0 - NAND Control Register 0 */ /*! @{ */ + #define SEMC_NANDCR0_PS_MASK (0x1U) #define SEMC_NANDCR0_PS_SHIFT (0U) /*! PS - Port Size @@ -74646,13 +83699,15 @@ typedef struct { * 0b1..16bit */ #define SEMC_NANDCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK) + #define SEMC_NANDCR0_SYNCEN_MASK (0x2U) #define SEMC_NANDCR0_SYNCEN_SHIFT (1U) -/*! SYNCEN - Select NAND controller mode. - * 0b0..ASYNC mode is enabled. - * 0b1..SYNC mode is enabled. +/*! SYNCEN - Synchronous Mode Enable + * 0b0..Asynchronous mode is enabled. + * 0b1..Synchronous mode is enabled. */ #define SEMC_NANDCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_SYNCEN_SHIFT)) & SEMC_NANDCR0_SYNCEN_MASK) + #define SEMC_NANDCR0_BL_MASK (0x70U) #define SEMC_NANDCR0_BL_SHIFT (4U) /*! BL - Burst Length @@ -74666,6 +83721,7 @@ typedef struct { * 0b111..64 */ #define SEMC_NANDCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK) + #define SEMC_NANDCR0_EDO_MASK (0x80U) #define SEMC_NANDCR0_EDO_SHIFT (7U) /*! EDO - EDO mode enabled @@ -74673,6 +83729,7 @@ typedef struct { * 0b1..EDO mode enabled */ #define SEMC_NANDCR0_EDO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK) + #define SEMC_NANDCR0_COL_MASK (0x700U) #define SEMC_NANDCR0_COL_SHIFT (8U) /*! COL - Column address bit number @@ -74688,43 +83745,51 @@ typedef struct { #define SEMC_NANDCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK) /*! @} */ -/*! @name NANDCR1 - NAND control register 1 */ +/*! @name NANDCR1 - NAND Control Register 1 */ /*! @{ */ + #define SEMC_NANDCR1_CES_MASK (0xFU) #define SEMC_NANDCR1_CES_SHIFT (0U) -/*! CES - CE setup time +/*! CES - CE# setup time */ #define SEMC_NANDCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK) + #define SEMC_NANDCR1_CEH_MASK (0xF0U) #define SEMC_NANDCR1_CEH_SHIFT (4U) -/*! CEH - CE hold time +/*! CEH - CE# hold time */ #define SEMC_NANDCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK) + #define SEMC_NANDCR1_WEL_MASK (0xF00U) #define SEMC_NANDCR1_WEL_SHIFT (8U) /*! WEL - WE# low time */ #define SEMC_NANDCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK) + #define SEMC_NANDCR1_WEH_MASK (0xF000U) #define SEMC_NANDCR1_WEH_SHIFT (12U) /*! WEH - WE# high time */ #define SEMC_NANDCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK) + #define SEMC_NANDCR1_REL_MASK (0xF0000U) #define SEMC_NANDCR1_REL_SHIFT (16U) /*! REL - RE# low time */ #define SEMC_NANDCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK) + #define SEMC_NANDCR1_REH_MASK (0xF00000U) #define SEMC_NANDCR1_REH_SHIFT (20U) /*! REH - RE# high time */ #define SEMC_NANDCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK) + #define SEMC_NANDCR1_TA_MASK (0xF000000U) #define SEMC_NANDCR1_TA_SHIFT (24U) /*! TA - Turnaround time */ #define SEMC_NANDCR1_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK) + #define SEMC_NANDCR1_CEITV_MASK (0xF0000000U) #define SEMC_NANDCR1_CEITV_SHIFT (28U) /*! CEITV - CE# interval time @@ -74732,81 +83797,95 @@ typedef struct { #define SEMC_NANDCR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK) /*! @} */ -/*! @name NANDCR2 - NAND control register 2 */ +/*! @name NANDCR2 - NAND Control Register 2 */ /*! @{ */ + #define SEMC_NANDCR2_TWHR_MASK (0x3FU) #define SEMC_NANDCR2_TWHR_SHIFT (0U) -/*! TWHR - WE# high to RE# low wait time +/*! TWHR - WE# high to RE# low time */ #define SEMC_NANDCR2_TWHR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK) + #define SEMC_NANDCR2_TRHW_MASK (0xFC0U) #define SEMC_NANDCR2_TRHW_SHIFT (6U) -/*! TRHW - RE# high to WE# low wait time +/*! TRHW - RE# high to WE# low time */ #define SEMC_NANDCR2_TRHW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK) + #define SEMC_NANDCR2_TADL_MASK (0x3F000U) #define SEMC_NANDCR2_TADL_SHIFT (12U) -/*! TADL - ALE to write data start wait time +/*! TADL - Address cycle to data loading time */ #define SEMC_NANDCR2_TADL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK) + #define SEMC_NANDCR2_TRR_MASK (0xFC0000U) #define SEMC_NANDCR2_TRR_SHIFT (18U) -/*! TRR - Ready to RE# low wait time +/*! TRR - Ready to RE# low time */ #define SEMC_NANDCR2_TRR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK) + #define SEMC_NANDCR2_TWB_MASK (0x3F000000U) #define SEMC_NANDCR2_TWB_SHIFT (24U) -/*! TWB - WE# high to busy wait time +/*! TWB - WE# high to busy time */ #define SEMC_NANDCR2_TWB(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK) /*! @} */ -/*! @name NANDCR3 - NAND control register 3 */ +/*! @name NANDCR3 - NAND Control Register 3 */ /*! @{ */ + #define SEMC_NANDCR3_NDOPT1_MASK (0x1U) #define SEMC_NANDCR3_NDOPT1_SHIFT (0U) /*! NDOPT1 - NAND option bit 1 */ #define SEMC_NANDCR3_NDOPT1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK) + #define SEMC_NANDCR3_NDOPT2_MASK (0x2U) #define SEMC_NANDCR3_NDOPT2_SHIFT (1U) /*! NDOPT2 - NAND option bit 2 */ #define SEMC_NANDCR3_NDOPT2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK) + #define SEMC_NANDCR3_NDOPT3_MASK (0x4U) #define SEMC_NANDCR3_NDOPT3_SHIFT (2U) /*! NDOPT3 - NAND option bit 3 */ #define SEMC_NANDCR3_NDOPT3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK) + #define SEMC_NANDCR3_CLE_MASK (0x8U) #define SEMC_NANDCR3_CLE_SHIFT (3U) /*! CLE - NAND CLE Option */ #define SEMC_NANDCR3_CLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_CLE_SHIFT)) & SEMC_NANDCR3_CLE_MASK) + #define SEMC_NANDCR3_RDS_MASK (0xF0000U) #define SEMC_NANDCR3_RDS_SHIFT (16U) -/*! RDS - Read Data Setup time. +/*! RDS - Read Data Setup time */ #define SEMC_NANDCR3_RDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDS_SHIFT)) & SEMC_NANDCR3_RDS_MASK) + #define SEMC_NANDCR3_RDH_MASK (0xF00000U) #define SEMC_NANDCR3_RDH_SHIFT (20U) -/*! RDH - Read Data Hold time. +/*! RDH - Read Data Hold time */ #define SEMC_NANDCR3_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDH_SHIFT)) & SEMC_NANDCR3_RDH_MASK) + #define SEMC_NANDCR3_WDS_MASK (0xF000000U) #define SEMC_NANDCR3_WDS_SHIFT (24U) -/*! WDS - Write Data Setup time. +/*! WDS - Write Data Setup time */ #define SEMC_NANDCR3_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDS_SHIFT)) & SEMC_NANDCR3_WDS_MASK) + #define SEMC_NANDCR3_WDH_MASK (0xF0000000U) #define SEMC_NANDCR3_WDH_SHIFT (28U) -/*! WDH - Write Data Hold time. +/*! WDH - Write Data Hold time */ #define SEMC_NANDCR3_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDH_SHIFT)) & SEMC_NANDCR3_WDH_MASK) /*! @} */ -/*! @name NORCR0 - NOR control register 0 */ +/*! @name NORCR0 - NOR Control Register 0 */ /*! @{ */ + #define SEMC_NORCR0_PS_MASK (0x1U) #define SEMC_NORCR0_PS_SHIFT (0U) /*! PS - Port Size @@ -74814,13 +83893,15 @@ typedef struct { * 0b1..16bit */ #define SEMC_NORCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK) + #define SEMC_NORCR0_SYNCEN_MASK (0x2U) #define SEMC_NORCR0_SYNCEN_SHIFT (1U) -/*! SYNCEN - Select NOR controller mode. - * 0b0..ASYNC mode is enabled. - * 0b1..SYNC mode is enabled. +/*! SYNCEN - Synchronous Mode Enable + * 0b0..Asynchronous mode is enabled. + * 0b1..Synchronous mode is enabled. Only fixed latency mode is supported. */ #define SEMC_NORCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_SYNCEN_SHIFT)) & SEMC_NORCR0_SYNCEN_MASK) + #define SEMC_NORCR0_BL_MASK (0x70U) #define SEMC_NORCR0_BL_SHIFT (4U) /*! BL - Burst Length @@ -74834,6 +83915,7 @@ typedef struct { * 0b111..64 */ #define SEMC_NORCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK) + #define SEMC_NORCR0_AM_MASK (0x300U) #define SEMC_NORCR0_AM_SHIFT (8U) /*! AM - Address Mode @@ -74843,13 +83925,15 @@ typedef struct { * 0b11..Address/Data non-MUX mode (Non-ADMUX) */ #define SEMC_NORCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK) + #define SEMC_NORCR0_ADVP_MASK (0x400U) #define SEMC_NORCR0_ADVP_SHIFT (10U) -/*! ADVP - ADV# polarity +/*! ADVP - ADV# Polarity * 0b0..ADV# is active low. * 0b1..ADV# is active high. */ #define SEMC_NORCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK) + #define SEMC_NORCR0_ADVH_MASK (0x800U) #define SEMC_NORCR0_ADVH_SHIFT (11U) /*! ADVH - ADV# level control during address hold state @@ -74857,6 +83941,7 @@ typedef struct { * 0b1..ADV# is low during address hold state. */ #define SEMC_NORCR0_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVH_SHIFT)) & SEMC_NORCR0_ADVH_MASK) + #define SEMC_NORCR0_COL_MASK (0xF000U) #define SEMC_NORCR0_COL_SHIFT (12U) /*! COL - Column Address bit width @@ -74880,43 +83965,51 @@ typedef struct { #define SEMC_NORCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK) /*! @} */ -/*! @name NORCR1 - NOR control register 1 */ +/*! @name NORCR1 - NOR Control Register 1 */ /*! @{ */ + #define SEMC_NORCR1_CES_MASK (0xFU) #define SEMC_NORCR1_CES_SHIFT (0U) /*! CES - CE setup time */ #define SEMC_NORCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK) + #define SEMC_NORCR1_CEH_MASK (0xF0U) #define SEMC_NORCR1_CEH_SHIFT (4U) /*! CEH - CE hold time */ #define SEMC_NORCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK) + #define SEMC_NORCR1_AS_MASK (0xF00U) #define SEMC_NORCR1_AS_SHIFT (8U) /*! AS - Address setup time */ #define SEMC_NORCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK) + #define SEMC_NORCR1_AH_MASK (0xF000U) #define SEMC_NORCR1_AH_SHIFT (12U) /*! AH - Address hold time */ #define SEMC_NORCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK) + #define SEMC_NORCR1_WEL_MASK (0xF0000U) #define SEMC_NORCR1_WEL_SHIFT (16U) /*! WEL - WE low time */ #define SEMC_NORCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK) + #define SEMC_NORCR1_WEH_MASK (0xF00000U) #define SEMC_NORCR1_WEH_SHIFT (20U) /*! WEH - WE high time */ #define SEMC_NORCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK) + #define SEMC_NORCR1_REL_MASK (0xF000000U) #define SEMC_NORCR1_REL_SHIFT (24U) /*! REL - RE low time */ #define SEMC_NORCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK) + #define SEMC_NORCR1_REH_MASK (0xF0000000U) #define SEMC_NORCR1_REH_SHIFT (28U) /*! REH - RE high time @@ -74924,33 +84017,39 @@ typedef struct { #define SEMC_NORCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK) /*! @} */ -/*! @name NORCR2 - NOR control register 2 */ +/*! @name NORCR2 - NOR Control Register 2 */ /*! @{ */ + #define SEMC_NORCR2_TA_MASK (0xF00U) #define SEMC_NORCR2_TA_SHIFT (8U) /*! TA - Turnaround time */ #define SEMC_NORCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK) + #define SEMC_NORCR2_AWDH_MASK (0xF000U) #define SEMC_NORCR2_AWDH_SHIFT (12U) /*! AWDH - Address to write data hold time */ #define SEMC_NORCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK) + #define SEMC_NORCR2_LC_MASK (0xF0000U) #define SEMC_NORCR2_LC_SHIFT (16U) /*! LC - Latency count */ #define SEMC_NORCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK) + #define SEMC_NORCR2_RD_MASK (0xF00000U) #define SEMC_NORCR2_RD_SHIFT (20U) /*! RD - Read time */ #define SEMC_NORCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK) + #define SEMC_NORCR2_CEITV_MASK (0xF000000U) #define SEMC_NORCR2_CEITV_SHIFT (24U) /*! CEITV - CE# interval time */ #define SEMC_NORCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK) + #define SEMC_NORCR2_RDH_MASK (0xF0000000U) #define SEMC_NORCR2_RDH_SHIFT (28U) /*! RDH - Read hold time @@ -74958,13 +84057,15 @@ typedef struct { #define SEMC_NORCR2_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK) /*! @} */ -/*! @name NORCR3 - NOR control register 3 */ +/*! @name NORCR3 - NOR Control Register 3 */ /*! @{ */ + #define SEMC_NORCR3_ASSR_MASK (0xFU) #define SEMC_NORCR3_ASSR_SHIFT (0U) /*! ASSR - Address setup time for SYNC read */ #define SEMC_NORCR3_ASSR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_ASSR_SHIFT)) & SEMC_NORCR3_ASSR_MASK) + #define SEMC_NORCR3_AHSR_MASK (0xF0U) #define SEMC_NORCR3_AHSR_SHIFT (4U) /*! AHSR - Address hold time for SYNC read @@ -74972,8 +84073,9 @@ typedef struct { #define SEMC_NORCR3_AHSR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_AHSR_SHIFT)) & SEMC_NORCR3_AHSR_MASK) /*! @} */ -/*! @name SRAMCR0 - SRAM control register 0 */ +/*! @name SRAMCR0 - SRAM Control Register 0 */ /*! @{ */ + #define SEMC_SRAMCR0_PS_MASK (0x1U) #define SEMC_SRAMCR0_PS_SHIFT (0U) /*! PS - Port Size @@ -74981,27 +84083,31 @@ typedef struct { * 0b1..16bit */ #define SEMC_SRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK) + #define SEMC_SRAMCR0_SYNCEN_MASK (0x2U) #define SEMC_SRAMCR0_SYNCEN_SHIFT (1U) -/*! SYNCEN - Select SRAM controller mode. - * 0b0..ASYNC mode is enabled. - * 0b1..SYNC mode is enabled. +/*! SYNCEN - Synchronous Mode Enable + * 0b0..Asynchronous mode is enabled. + * 0b1..Synchronous mode is enabled. Only fixed latency mode is supported. */ #define SEMC_SRAMCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_SYNCEN_SHIFT)) & SEMC_SRAMCR0_SYNCEN_MASK) + #define SEMC_SRAMCR0_WAITEN_MASK (0x4U) #define SEMC_SRAMCR0_WAITEN_SHIFT (2U) /*! WAITEN - Wait Enable - * 0b0..SEMC does not monitor wait pin. - * 0b1..SEMC monitors wait pin. SEMC does not transfer/receive data when wait pin is asserted. + * 0b0..The SEMC does not monitor wait pin. + * 0b1..The SEMC monitors wait pin. The SEMC does not transfer/receive data when wait pin is asserted. */ #define SEMC_SRAMCR0_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_WAITEN_SHIFT)) & SEMC_SRAMCR0_WAITEN_MASK) + #define SEMC_SRAMCR0_WAITSP_MASK (0x8U) #define SEMC_SRAMCR0_WAITSP_SHIFT (3U) /*! WAITSP - Wait Sample - * 0b0..Wait pin is directly used by SEMC. + * 0b0..Wait pin is directly used by the SEMC. * 0b1..Wait pin is sampled by internal clock before it is used. */ #define SEMC_SRAMCR0_WAITSP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_WAITSP_SHIFT)) & SEMC_SRAMCR0_WAITSP_MASK) + #define SEMC_SRAMCR0_BL_MASK (0x70U) #define SEMC_SRAMCR0_BL_SHIFT (4U) /*! BL - Burst Length @@ -75015,6 +84121,7 @@ typedef struct { * 0b111..64 */ #define SEMC_SRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK) + #define SEMC_SRAMCR0_AM_MASK (0x300U) #define SEMC_SRAMCR0_AM_SHIFT (8U) /*! AM - Address Mode @@ -75024,6 +84131,7 @@ typedef struct { * 0b11..Address/Data non-MUX mode (Non-ADMUX) */ #define SEMC_SRAMCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK) + #define SEMC_SRAMCR0_ADVP_MASK (0x400U) #define SEMC_SRAMCR0_ADVP_SHIFT (10U) /*! ADVP - ADV# polarity @@ -75031,6 +84139,7 @@ typedef struct { * 0b1..ADV# is active high. */ #define SEMC_SRAMCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK) + #define SEMC_SRAMCR0_ADVH_MASK (0x800U) #define SEMC_SRAMCR0_ADVH_SHIFT (11U) /*! ADVH - ADV# level control during address hold state @@ -75038,6 +84147,7 @@ typedef struct { * 0b1..ADV# is low during address hold state. */ #define SEMC_SRAMCR0_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVH_SHIFT)) & SEMC_SRAMCR0_ADVH_MASK) + #define SEMC_SRAMCR0_COL_MASK (0xF000U) #define SEMC_SRAMCR0_COL_SHIFT (12U) /*! COL - Column Address bit width @@ -75061,43 +84171,51 @@ typedef struct { #define SEMC_SRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK) /*! @} */ -/*! @name SRAMCR1 - SRAM control register 1 */ +/*! @name SRAMCR1 - SRAM Control Register 1 */ /*! @{ */ + #define SEMC_SRAMCR1_CES_MASK (0xFU) #define SEMC_SRAMCR1_CES_SHIFT (0U) /*! CES - CE setup time */ #define SEMC_SRAMCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK) + #define SEMC_SRAMCR1_CEH_MASK (0xF0U) #define SEMC_SRAMCR1_CEH_SHIFT (4U) /*! CEH - CE hold time */ #define SEMC_SRAMCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK) + #define SEMC_SRAMCR1_AS_MASK (0xF00U) #define SEMC_SRAMCR1_AS_SHIFT (8U) /*! AS - Address setup time */ #define SEMC_SRAMCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK) + #define SEMC_SRAMCR1_AH_MASK (0xF000U) #define SEMC_SRAMCR1_AH_SHIFT (12U) /*! AH - Address hold time */ #define SEMC_SRAMCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK) + #define SEMC_SRAMCR1_WEL_MASK (0xF0000U) #define SEMC_SRAMCR1_WEL_SHIFT (16U) /*! WEL - WE low time */ #define SEMC_SRAMCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK) + #define SEMC_SRAMCR1_WEH_MASK (0xF00000U) #define SEMC_SRAMCR1_WEH_SHIFT (20U) /*! WEH - WE high time */ #define SEMC_SRAMCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK) + #define SEMC_SRAMCR1_REL_MASK (0xF000000U) #define SEMC_SRAMCR1_REL_SHIFT (24U) /*! REL - RE low time */ #define SEMC_SRAMCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK) + #define SEMC_SRAMCR1_REH_MASK (0xF0000000U) #define SEMC_SRAMCR1_REH_SHIFT (28U) /*! REH - RE high time @@ -75105,43 +84223,51 @@ typedef struct { #define SEMC_SRAMCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK) /*! @} */ -/*! @name SRAMCR2 - SRAM control register 2 */ +/*! @name SRAMCR2 - SRAM Control Register 2 */ /*! @{ */ + #define SEMC_SRAMCR2_WDS_MASK (0xFU) #define SEMC_SRAMCR2_WDS_SHIFT (0U) /*! WDS - Write Data setup time */ #define SEMC_SRAMCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK) + #define SEMC_SRAMCR2_WDH_MASK (0xF0U) #define SEMC_SRAMCR2_WDH_SHIFT (4U) /*! WDH - Write Data hold time */ #define SEMC_SRAMCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK) + #define SEMC_SRAMCR2_TA_MASK (0xF00U) #define SEMC_SRAMCR2_TA_SHIFT (8U) /*! TA - Turnaround time */ #define SEMC_SRAMCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK) + #define SEMC_SRAMCR2_AWDH_MASK (0xF000U) #define SEMC_SRAMCR2_AWDH_SHIFT (12U) /*! AWDH - Address to write data hold time */ #define SEMC_SRAMCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK) + #define SEMC_SRAMCR2_LC_MASK (0xF0000U) #define SEMC_SRAMCR2_LC_SHIFT (16U) /*! LC - Latency count */ #define SEMC_SRAMCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK) + #define SEMC_SRAMCR2_RD_MASK (0xF00000U) #define SEMC_SRAMCR2_RD_SHIFT (20U) /*! RD - Read time */ #define SEMC_SRAMCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK) + #define SEMC_SRAMCR2_CEITV_MASK (0xF000000U) #define SEMC_SRAMCR2_CEITV_SHIFT (24U) /*! CEITV - CE# interval time */ #define SEMC_SRAMCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK) + #define SEMC_SRAMCR2_RDH_MASK (0xF0000000U) #define SEMC_SRAMCR2_RDH_SHIFT (28U) /*! RDH - Read hold time @@ -75149,8 +84275,9 @@ typedef struct { #define SEMC_SRAMCR2_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RDH_SHIFT)) & SEMC_SRAMCR2_RDH_MASK) /*! @} */ -/*! @name DBICR0 - DBI-B control register 0 */ +/*! @name DBICR0 - DBI-B Control Register 0 */ /*! @{ */ + #define SEMC_DBICR0_PS_MASK (0x1U) #define SEMC_DBICR0_PS_SHIFT (0U) /*! PS - Port Size @@ -75158,6 +84285,7 @@ typedef struct { * 0b1..16bit */ #define SEMC_DBICR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK) + #define SEMC_DBICR0_BL_MASK (0x70U) #define SEMC_DBICR0_BL_SHIFT (4U) /*! BL - Burst Length @@ -75171,6 +84299,7 @@ typedef struct { * 0b111..64 */ #define SEMC_DBICR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK) + #define SEMC_DBICR0_COL_MASK (0xF000U) #define SEMC_DBICR0_COL_SHIFT (12U) /*! COL - Column Address bit width @@ -75194,47 +84323,59 @@ typedef struct { #define SEMC_DBICR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK) /*! @} */ -/*! @name DBICR1 - DBI-B control register 1 */ +/*! @name DBICR1 - DBI-B Control Register 1 */ /*! @{ */ + #define SEMC_DBICR1_CES_MASK (0xFU) #define SEMC_DBICR1_CES_SHIFT (0U) /*! CES - CSX Setup Time */ #define SEMC_DBICR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK) + #define SEMC_DBICR1_CEH_MASK (0xF0U) #define SEMC_DBICR1_CEH_SHIFT (4U) /*! CEH - CSX Hold Time */ #define SEMC_DBICR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK) + #define SEMC_DBICR1_WEL_MASK (0xF00U) #define SEMC_DBICR1_WEL_SHIFT (8U) /*! WEL - WRX Low Time */ #define SEMC_DBICR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK) + #define SEMC_DBICR1_WEH_MASK (0xF000U) #define SEMC_DBICR1_WEH_SHIFT (12U) /*! WEH - WRX High Time */ #define SEMC_DBICR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK) -#define SEMC_DBICR1_REL_MASK (0xF0000U) + +#define SEMC_DBICR1_REL_MASK (0x7F0000U) #define SEMC_DBICR1_REL_SHIFT (16U) -/*! REL - RDX Low Time bit [3:0] +/*! REL - RDX Low Time */ #define SEMC_DBICR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK) -#define SEMC_DBICR1_REH_MASK (0xF00000U) -#define SEMC_DBICR1_REH_SHIFT (20U) -/*! REH - RDX High Time bit [3:0] + +#define SEMC_DBICR1_REH_MASK (0x7F000000U) +#define SEMC_DBICR1_REH_SHIFT (24U) +/*! REH - RDX High Time */ #define SEMC_DBICR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK) -#define SEMC_DBICR1_CEITV_MASK (0xF000000U) -#define SEMC_DBICR1_CEITV_SHIFT (24U) +/*! @} */ + +/*! @name DBICR2 - DBI-B Control Register 2 */ +/*! @{ */ + +#define SEMC_DBICR2_CEITV_MASK (0xFU) +#define SEMC_DBICR2_CEITV_SHIFT (0U) /*! CEITV - CSX interval time */ -#define SEMC_DBICR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEITV_SHIFT)) & SEMC_DBICR1_CEITV_MASK) +#define SEMC_DBICR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR2_CEITV_SHIFT)) & SEMC_DBICR2_CEITV_MASK) /*! @} */ -/*! @name IPCR0 - IP Command control register 0 */ +/*! @name IPCR0 - IP Command Control Register 0 */ /*! @{ */ + #define SEMC_IPCR0_SA_MASK (0xFFFFFFFFU) #define SEMC_IPCR0_SA_SHIFT (0U) /*! SA - Slave address @@ -75242,8 +84383,9 @@ typedef struct { #define SEMC_IPCR0_SA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK) /*! @} */ -/*! @name IPCR1 - IP Command control register 1 */ +/*! @name IPCR1 - IP Command Control Register 1 */ /*! @{ */ + #define SEMC_IPCR1_DATSZ_MASK (0x7U) #define SEMC_IPCR1_DATSZ_SHIFT (0U) /*! DATSZ - Data Size in Byte @@ -75257,6 +84399,7 @@ typedef struct { * 0b111..4 */ #define SEMC_IPCR1_DATSZ(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK) + #define SEMC_IPCR1_NAND_EXT_ADDR_MASK (0xFF00U) #define SEMC_IPCR1_NAND_EXT_ADDR_SHIFT (8U) /*! NAND_EXT_ADDR - NAND Extended Address @@ -75264,73 +84407,79 @@ typedef struct { #define SEMC_IPCR1_NAND_EXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_NAND_EXT_ADDR_SHIFT)) & SEMC_IPCR1_NAND_EXT_ADDR_MASK) /*! @} */ -/*! @name IPCR2 - IP Command control register 2 */ +/*! @name IPCR2 - IP Command Control Register 2 */ /*! @{ */ + #define SEMC_IPCR2_BM0_MASK (0x1U) #define SEMC_IPCR2_BM0_SHIFT (0U) -/*! BM0 - Byte Mask for Byte 0 (IPTXD bit 7:0) - * 0b0..Byte Unmasked - * 0b1..Byte Masked +/*! BM0 - Byte Mask for Byte 0 (IPTXDAT bit 7:0) + * 0b0..Byte is unmasked + * 0b1..Byte is masked */ #define SEMC_IPCR2_BM0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK) + #define SEMC_IPCR2_BM1_MASK (0x2U) #define SEMC_IPCR2_BM1_SHIFT (1U) -/*! BM1 - Byte Mask for Byte 1 (IPTXD bit 15:8) - * 0b0..Byte Unmasked - * 0b1..Byte Masked +/*! BM1 - Byte Mask for Byte 1 (IPTXDAT bit 15:8) + * 0b0..Byte is unmasked + * 0b1..Byte is masked */ #define SEMC_IPCR2_BM1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK) + #define SEMC_IPCR2_BM2_MASK (0x4U) #define SEMC_IPCR2_BM2_SHIFT (2U) -/*! BM2 - Byte Mask for Byte 2 (IPTXD bit 23:16) - * 0b0..Byte Unmasked - * 0b1..Byte Masked +/*! BM2 - Byte Mask for Byte 2 (IPTXDAT bit 23:16) + * 0b0..Byte is unmasked + * 0b1..Byte is masked */ #define SEMC_IPCR2_BM2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK) + #define SEMC_IPCR2_BM3_MASK (0x8U) #define SEMC_IPCR2_BM3_SHIFT (3U) -/*! BM3 - Byte Mask for Byte 3 (IPTXD bit 31:24) - * 0b0..Byte Unmasked - * 0b1..Byte Masked +/*! BM3 - Byte Mask for Byte 3 (IPTXDAT bit 31:24) + * 0b0..Byte is unmasked + * 0b1..Byte is masked */ #define SEMC_IPCR2_BM3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK) /*! @} */ -/*! @name IPCMD - IP Command register */ +/*! @name IPCMD - IP Command Register */ /*! @{ */ + #define SEMC_IPCMD_CMD_MASK (0xFFFFU) #define SEMC_IPCMD_CMD_SHIFT (0U) #define SEMC_IPCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK) + #define SEMC_IPCMD_KEY_MASK (0xFFFF0000U) #define SEMC_IPCMD_KEY_SHIFT (16U) #define SEMC_IPCMD_KEY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK) /*! @} */ -/*! @name IPTXDAT - TX DATA register (for IP Command) */ +/*! @name IPTXDAT - TX DATA Register */ /*! @{ */ + #define SEMC_IPTXDAT_DAT_MASK (0xFFFFFFFFU) #define SEMC_IPTXDAT_DAT_SHIFT (0U) -/*! DAT - data - */ #define SEMC_IPTXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK) /*! @} */ -/*! @name IPRXDAT - RX DATA register (for IP Command) */ +/*! @name IPRXDAT - RX DATA Register */ /*! @{ */ + #define SEMC_IPRXDAT_DAT_MASK (0xFFFFFFFFU) #define SEMC_IPRXDAT_DAT_SHIFT (0U) -/*! DAT - data - */ #define SEMC_IPRXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK) /*! @} */ -/*! @name STS0 - Status register 0 */ +/*! @name STS0 - Status Register 0 */ /*! @{ */ + #define SEMC_STS0_IDLE_MASK (0x1U) #define SEMC_STS0_IDLE_SHIFT (0U) -/*! IDLE - Indicating whether SEMC is in IDLE state. +/*! IDLE - Indicating whether the SEMC is in idle state. */ #define SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK) + #define SEMC_STS0_NARDY_MASK (0x2U) #define SEMC_STS0_NARDY_SHIFT (1U) /*! NARDY - Indicating NAND device Ready/WAIT# pin level. @@ -75340,8 +84489,9 @@ typedef struct { #define SEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK) /*! @} */ -/*! @name STS2 - Status register 2 */ +/*! @name STS2 - Status Register 2 */ /*! @{ */ + #define SEMC_STS2_NDWRPEND_MASK (0x8U) #define SEMC_STS2_NDWRPEND_SHIFT (3U) /*! NDWRPEND - This field indicating whether there is pending AXI command (write) to NAND device. @@ -75351,8 +84501,9 @@ typedef struct { #define SEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK) /*! @} */ -/*! @name STS12 - Status register 12 */ +/*! @name STS12 - Status Register 12 */ /*! @{ */ + #define SEMC_STS12_NDADDR_MASK (0xFFFFFFFFU) #define SEMC_STS12_NDADDR_SHIFT (0U) /*! NDADDR - This field indicating the last write address (AXI command) to NAND device (without base address in SEMC_BR4). @@ -75360,23 +84511,31 @@ typedef struct { #define SEMC_STS12_NDADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK) /*! @} */ -/*! @name STS13 - Status register 13 */ +/*! @name STS13 - Status Register 13 */ /*! @{ */ + #define SEMC_STS13_SLVLOCK_MASK (0x1U) #define SEMC_STS13_SLVLOCK_SHIFT (0U) /*! SLVLOCK - Sample clock slave delay line locked. + * 0b0..Slave delay line is not locked. + * 0b1..Slave delay line is locked. */ #define SEMC_STS13_SLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVLOCK_SHIFT)) & SEMC_STS13_SLVLOCK_MASK) + #define SEMC_STS13_REFLOCK_MASK (0x2U) #define SEMC_STS13_REFLOCK_SHIFT (1U) /*! REFLOCK - Sample clock reference delay line locked. + * 0b0..Reference delay line is not locked. + * 0b1..Reference delay line is locked. */ #define SEMC_STS13_REFLOCK(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFLOCK_SHIFT)) & SEMC_STS13_REFLOCK_MASK) + #define SEMC_STS13_SLVSEL_MASK (0xFCU) #define SEMC_STS13_SLVSEL_SHIFT (2U) -/*! SLVSEL - Sample clock slave delay line delay cell number selection . +/*! SLVSEL - Sample clock slave delay line delay cell number selection. */ #define SEMC_STS13_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVSEL_SHIFT)) & SEMC_STS13_SLVSEL_MASK) + #define SEMC_STS13_REFSEL_MASK (0x3F00U) #define SEMC_STS13_REFSEL_SHIFT (8U) /*! REFSEL - Sample clock reference delay line delay cell number selection. @@ -75384,13 +84543,17 @@ typedef struct { #define SEMC_STS13_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFSEL_SHIFT)) & SEMC_STS13_REFSEL_MASK) /*! @} */ -/*! @name BR9 - Base Register 9 (For PSRAM device 1) */ +/*! @name BR9 - Base Register 9 */ /*! @{ */ + #define SEMC_BR9_VLD_MASK (0x1U) #define SEMC_BR9_VLD_SHIFT (0U) /*! VLD - Valid + * 0b0..The memory is invalid, can not be accessed. + * 0b1..The memory is valid, can be accessed. */ #define SEMC_BR9_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_VLD_SHIFT)) & SEMC_BR9_VLD_MASK) + #define SEMC_BR9_MS_MASK (0x3EU) #define SEMC_BR9_MS_SHIFT (1U) /*! MS - Memory size @@ -75417,6 +84580,7 @@ typedef struct { * 0b10100-0b11111..4GB */ #define SEMC_BR9_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_MS_SHIFT)) & SEMC_BR9_MS_MASK) + #define SEMC_BR9_BA_MASK (0xFFFFF000U) #define SEMC_BR9_BA_SHIFT (12U) /*! BA - Base Address @@ -75424,13 +84588,17 @@ typedef struct { #define SEMC_BR9_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_BA_SHIFT)) & SEMC_BR9_BA_MASK) /*! @} */ -/*! @name BR10 - Base Register 10 (For PSRAM device 2) */ +/*! @name BR10 - Base Register 10 */ /*! @{ */ + #define SEMC_BR10_VLD_MASK (0x1U) #define SEMC_BR10_VLD_SHIFT (0U) /*! VLD - Valid + * 0b0..The memory is invalid, can not be accessed. + * 0b1..The memory is valid, can be accessed. */ #define SEMC_BR10_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_VLD_SHIFT)) & SEMC_BR10_VLD_MASK) + #define SEMC_BR10_MS_MASK (0x3EU) #define SEMC_BR10_MS_SHIFT (1U) /*! MS - Memory size @@ -75457,6 +84625,7 @@ typedef struct { * 0b10100-0b11111..4GB */ #define SEMC_BR10_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_MS_SHIFT)) & SEMC_BR10_MS_MASK) + #define SEMC_BR10_BA_MASK (0xFFFFF000U) #define SEMC_BR10_BA_SHIFT (12U) /*! BA - Base Address @@ -75464,13 +84633,17 @@ typedef struct { #define SEMC_BR10_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_BA_SHIFT)) & SEMC_BR10_BA_MASK) /*! @} */ -/*! @name BR11 - Base Register 11 (For PSRAM device 3) */ +/*! @name BR11 - Base Register 11 */ /*! @{ */ + #define SEMC_BR11_VLD_MASK (0x1U) #define SEMC_BR11_VLD_SHIFT (0U) /*! VLD - Valid + * 0b0..The memory is invalid, can not be accessed. + * 0b1..The memory is valid, can be accessed. */ #define SEMC_BR11_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_VLD_SHIFT)) & SEMC_BR11_VLD_MASK) + #define SEMC_BR11_MS_MASK (0x3EU) #define SEMC_BR11_MS_SHIFT (1U) /*! MS - Memory size @@ -75497,6 +84670,7 @@ typedef struct { * 0b10100-0b11111..4GB */ #define SEMC_BR11_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_MS_SHIFT)) & SEMC_BR11_MS_MASK) + #define SEMC_BR11_BA_MASK (0xFFFFF000U) #define SEMC_BR11_BA_SHIFT (12U) /*! BA - Base Address @@ -75504,8 +84678,9 @@ typedef struct { #define SEMC_BR11_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_BA_SHIFT)) & SEMC_BR11_BA_MASK) /*! @} */ -/*! @name SRAMCR4 - SRAM control register 4 */ +/*! @name SRAMCR4 - SRAM Control Register 4 */ /*! @{ */ + #define SEMC_SRAMCR4_PS_MASK (0x1U) #define SEMC_SRAMCR4_PS_SHIFT (0U) /*! PS - Port Size @@ -75513,27 +84688,31 @@ typedef struct { * 0b1..16bit */ #define SEMC_SRAMCR4_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_PS_SHIFT)) & SEMC_SRAMCR4_PS_MASK) + #define SEMC_SRAMCR4_SYNCEN_MASK (0x2U) #define SEMC_SRAMCR4_SYNCEN_SHIFT (1U) -/*! SYNCEN - Select SRAM controller mode. - * 0b0..ASYNC mode is enabled. - * 0b1..SYNC mode is enabled. +/*! SYNCEN - Synchronous Mode Enable + * 0b0..Asynchronous mode is enabled. + * 0b1..Synchronous mode is enabled. Only fixed latency mode is supported. */ #define SEMC_SRAMCR4_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_SYNCEN_SHIFT)) & SEMC_SRAMCR4_SYNCEN_MASK) + #define SEMC_SRAMCR4_WAITEN_MASK (0x4U) #define SEMC_SRAMCR4_WAITEN_SHIFT (2U) /*! WAITEN - Wait Enable - * 0b0..SEMC does not monitor wait pin. - * 0b1..SEMC monitors wait pin. SEMC does not transfer/receive data when wait pin is asserted. + * 0b0..The SEMC does not monitor wait pin. + * 0b1..The SEMC monitors wait pin. The SEMC does not transfer/receive data when wait pin is asserted. */ #define SEMC_SRAMCR4_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_WAITEN_SHIFT)) & SEMC_SRAMCR4_WAITEN_MASK) + #define SEMC_SRAMCR4_WAITSP_MASK (0x8U) #define SEMC_SRAMCR4_WAITSP_SHIFT (3U) /*! WAITSP - Wait Sample - * 0b0..Wait pin is directly used by SEMC. + * 0b0..Wait pin is directly used by the SEMC. * 0b1..Wait pin is sampled by internal clock before it is used. */ #define SEMC_SRAMCR4_WAITSP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_WAITSP_SHIFT)) & SEMC_SRAMCR4_WAITSP_MASK) + #define SEMC_SRAMCR4_BL_MASK (0x70U) #define SEMC_SRAMCR4_BL_SHIFT (4U) /*! BL - Burst Length @@ -75547,6 +84726,7 @@ typedef struct { * 0b111..64 */ #define SEMC_SRAMCR4_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_BL_SHIFT)) & SEMC_SRAMCR4_BL_MASK) + #define SEMC_SRAMCR4_AM_MASK (0x300U) #define SEMC_SRAMCR4_AM_SHIFT (8U) /*! AM - Address Mode @@ -75556,6 +84736,7 @@ typedef struct { * 0b11..Address/Data non-MUX mode (Non-ADMUX) */ #define SEMC_SRAMCR4_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_AM_SHIFT)) & SEMC_SRAMCR4_AM_MASK) + #define SEMC_SRAMCR4_ADVP_MASK (0x400U) #define SEMC_SRAMCR4_ADVP_SHIFT (10U) /*! ADVP - ADV# polarity @@ -75563,6 +84744,7 @@ typedef struct { * 0b1..ADV# is active high. */ #define SEMC_SRAMCR4_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_ADVP_SHIFT)) & SEMC_SRAMCR4_ADVP_MASK) + #define SEMC_SRAMCR4_ADVH_MASK (0x800U) #define SEMC_SRAMCR4_ADVH_SHIFT (11U) /*! ADVH - ADV# level control during address hold state @@ -75570,6 +84752,7 @@ typedef struct { * 0b1..ADV# is low during address hold state. */ #define SEMC_SRAMCR4_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_ADVH_SHIFT)) & SEMC_SRAMCR4_ADVH_MASK) + #define SEMC_SRAMCR4_COL_MASK (0xF000U) #define SEMC_SRAMCR4_COL_SHIFT (12U) /*! COL - Column Address bit width @@ -75593,43 +84776,51 @@ typedef struct { #define SEMC_SRAMCR4_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_COL_SHIFT)) & SEMC_SRAMCR4_COL_MASK) /*! @} */ -/*! @name SRAMCR5 - SRAM control register 5 */ +/*! @name SRAMCR5 - SRAM Control Register 5 */ /*! @{ */ + #define SEMC_SRAMCR5_CES_MASK (0xFU) #define SEMC_SRAMCR5_CES_SHIFT (0U) /*! CES - CE setup time */ #define SEMC_SRAMCR5_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CES_SHIFT)) & SEMC_SRAMCR5_CES_MASK) + #define SEMC_SRAMCR5_CEH_MASK (0xF0U) #define SEMC_SRAMCR5_CEH_SHIFT (4U) /*! CEH - CE hold time */ #define SEMC_SRAMCR5_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CEH_SHIFT)) & SEMC_SRAMCR5_CEH_MASK) + #define SEMC_SRAMCR5_AS_MASK (0xF00U) #define SEMC_SRAMCR5_AS_SHIFT (8U) /*! AS - Address setup time */ #define SEMC_SRAMCR5_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_AS_SHIFT)) & SEMC_SRAMCR5_AS_MASK) + #define SEMC_SRAMCR5_AH_MASK (0xF000U) #define SEMC_SRAMCR5_AH_SHIFT (12U) /*! AH - Address hold time */ #define SEMC_SRAMCR5_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_AH_SHIFT)) & SEMC_SRAMCR5_AH_MASK) + #define SEMC_SRAMCR5_WEL_MASK (0xF0000U) #define SEMC_SRAMCR5_WEL_SHIFT (16U) /*! WEL - WE low time */ #define SEMC_SRAMCR5_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_WEL_SHIFT)) & SEMC_SRAMCR5_WEL_MASK) + #define SEMC_SRAMCR5_WEH_MASK (0xF00000U) #define SEMC_SRAMCR5_WEH_SHIFT (20U) /*! WEH - WE high time */ #define SEMC_SRAMCR5_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_WEH_SHIFT)) & SEMC_SRAMCR5_WEH_MASK) + #define SEMC_SRAMCR5_REL_MASK (0xF000000U) #define SEMC_SRAMCR5_REL_SHIFT (24U) /*! REL - RE low time */ #define SEMC_SRAMCR5_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_REL_SHIFT)) & SEMC_SRAMCR5_REL_MASK) + #define SEMC_SRAMCR5_REH_MASK (0xF0000000U) #define SEMC_SRAMCR5_REH_SHIFT (28U) /*! REH - RE high time @@ -75637,43 +84828,51 @@ typedef struct { #define SEMC_SRAMCR5_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_REH_SHIFT)) & SEMC_SRAMCR5_REH_MASK) /*! @} */ -/*! @name SRAMCR6 - SRAM control register 6 */ +/*! @name SRAMCR6 - SRAM Control Register 6 */ /*! @{ */ + #define SEMC_SRAMCR6_WDS_MASK (0xFU) #define SEMC_SRAMCR6_WDS_SHIFT (0U) /*! WDS - Write Data setup time */ #define SEMC_SRAMCR6_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_WDS_SHIFT)) & SEMC_SRAMCR6_WDS_MASK) + #define SEMC_SRAMCR6_WDH_MASK (0xF0U) #define SEMC_SRAMCR6_WDH_SHIFT (4U) /*! WDH - Write Data hold time */ #define SEMC_SRAMCR6_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_WDH_SHIFT)) & SEMC_SRAMCR6_WDH_MASK) + #define SEMC_SRAMCR6_TA_MASK (0xF00U) #define SEMC_SRAMCR6_TA_SHIFT (8U) /*! TA - Turnaround time */ #define SEMC_SRAMCR6_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_TA_SHIFT)) & SEMC_SRAMCR6_TA_MASK) + #define SEMC_SRAMCR6_AWDH_MASK (0xF000U) #define SEMC_SRAMCR6_AWDH_SHIFT (12U) /*! AWDH - Address to write data hold time */ #define SEMC_SRAMCR6_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_AWDH_SHIFT)) & SEMC_SRAMCR6_AWDH_MASK) + #define SEMC_SRAMCR6_LC_MASK (0xF0000U) #define SEMC_SRAMCR6_LC_SHIFT (16U) /*! LC - Latency count */ #define SEMC_SRAMCR6_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_LC_SHIFT)) & SEMC_SRAMCR6_LC_MASK) + #define SEMC_SRAMCR6_RD_MASK (0xF00000U) #define SEMC_SRAMCR6_RD_SHIFT (20U) /*! RD - Read time */ #define SEMC_SRAMCR6_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_RD_SHIFT)) & SEMC_SRAMCR6_RD_MASK) + #define SEMC_SRAMCR6_CEITV_MASK (0xF000000U) #define SEMC_SRAMCR6_CEITV_SHIFT (24U) /*! CEITV - CE# interval time */ #define SEMC_SRAMCR6_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_CEITV_SHIFT)) & SEMC_SRAMCR6_CEITV_MASK) + #define SEMC_SRAMCR6_RDH_MASK (0xF0000000U) #define SEMC_SRAMCR6_RDH_SHIFT (28U) /*! RDH - Read hold time @@ -75683,44 +84882,60 @@ typedef struct { /*! @name DCCR - Delay Chain Control Register */ /*! @{ */ + #define SEMC_DCCR_SDRAMEN_MASK (0x1U) #define SEMC_DCCR_SDRAMEN_SHIFT (0U) -/*! SDRAMEN - Clock delay line delay cell number selection enable for SDRAM. +/*! SDRAMEN - Delay chain insertion enable for SRAM device. + * 0b0..Delay chain is not inserted. + * 0b1..Delay chain is inserted. */ #define SEMC_DCCR_SDRAMEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SDRAMEN_SHIFT)) & SEMC_DCCR_SDRAMEN_MASK) + #define SEMC_DCCR_SDRAMVAL_MASK (0x3EU) #define SEMC_DCCR_SDRAMVAL_SHIFT (1U) -/*! SDRAMVAL - Clock delay line delay cell number selection value for SDRAM. +/*! SDRAMVAL - Clock delay line delay cell number selection value for SDRAM device. */ #define SEMC_DCCR_SDRAMVAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SDRAMVAL_SHIFT)) & SEMC_DCCR_SDRAMVAL_MASK) + #define SEMC_DCCR_NOREN_MASK (0x100U) #define SEMC_DCCR_NOREN_SHIFT (8U) -/*! NOREN - Clock delay line delay cell number selection enable for NOR. +/*! NOREN - Delay chain insertion enable for NOR device. + * 0b0..Delay chain is not inserted. + * 0b1..Delay chain is inserted. */ #define SEMC_DCCR_NOREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_NOREN_SHIFT)) & SEMC_DCCR_NOREN_MASK) + #define SEMC_DCCR_NORVAL_MASK (0x3E00U) #define SEMC_DCCR_NORVAL_SHIFT (9U) -/*! NORVAL - Clock delay line delay cell number selection value for NOR. +/*! NORVAL - Clock delay line delay cell number selection value for NOR device. */ #define SEMC_DCCR_NORVAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_NORVAL_SHIFT)) & SEMC_DCCR_NORVAL_MASK) + #define SEMC_DCCR_SRAM0EN_MASK (0x10000U) #define SEMC_DCCR_SRAM0EN_SHIFT (16U) -/*! SRAM0EN - Clock delay line delay cell number selection enable for SRAM0. +/*! SRAM0EN - Delay chain insertion enable for SRAM device 0. + * 0b0..Delay chain is not inserted. + * 0b1..Delay chain is inserted. */ #define SEMC_DCCR_SRAM0EN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAM0EN_SHIFT)) & SEMC_DCCR_SRAM0EN_MASK) + #define SEMC_DCCR_SRAM0VAL_MASK (0x3E0000U) #define SEMC_DCCR_SRAM0VAL_SHIFT (17U) -/*! SRAM0VAL - Clock delay line delay cell number selection value for SRAM0. +/*! SRAM0VAL - Clock delay line delay cell number selection value for SRAM device 0. */ #define SEMC_DCCR_SRAM0VAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAM0VAL_SHIFT)) & SEMC_DCCR_SRAM0VAL_MASK) + #define SEMC_DCCR_SRAMXEN_MASK (0x1000000U) #define SEMC_DCCR_SRAMXEN_SHIFT (24U) -/*! SRAMXEN - Clock delay line delay cell number selection enable for SRAM1-3. +/*! SRAMXEN - Delay chain insertion enable for SRAM device 1-3. + * 0b0..Delay chain is not inserted. + * 0b1..Delay chain is inserted. */ #define SEMC_DCCR_SRAMXEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAMXEN_SHIFT)) & SEMC_DCCR_SRAMXEN_MASK) + #define SEMC_DCCR_SRAMXVAL_MASK (0x3E000000U) #define SEMC_DCCR_SRAMXVAL_SHIFT (25U) -/*! SRAMXVAL - Clock delay line delay cell number selection value for SRAM1-3. +/*! SRAMXVAL - Clock delay line delay cell number selection value for SRAM device 1-3. */ #define SEMC_DCCR_SRAMXVAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAMXVAL_SHIFT)) & SEMC_DCCR_SRAMXVAL_MASK) /*! @} */ @@ -75748,237 +84963,6 @@ typedef struct { */ /* end of group SEMC_Peripheral_Access_Layer */ -/* ---------------------------------------------------------------------------- - -- SFA Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SFA_Peripheral_Access_Layer SFA Peripheral Access Layer - * @{ - */ - -/** SFA - Register Layout Typedef */ -typedef struct { - __IO uint32_t CTRL; /**< Signal Frequency Analyser (SFA) Control, offset: 0x0 */ - __IO uint32_t CTRL_EXT; /**< Signal Frequency Analyser (SFA) Control Extended, offset: 0x4 */ - __IO uint32_t CNT_STAT; /**< Signal Frequency Analyser Count Status Register, offset: 0x8 */ - __I uint32_t CUT_CNT; /**< Signal Frequency Analyser Clock Under Test Counter, offset: 0xC */ - __I uint32_t REF_CNT; /**< Signal Frequency Analyser Reference Clock Counter, offset: 0x10 */ - __IO uint32_t CUT_TARGET; /**< Signal Frequency Analyser Clock Under Test Target Count, offset: 0x14 */ - __IO uint32_t REF_TARGET; /**< Signal Frequency Analyser Reference Clock Target Count, offset: 0x18 */ - __I uint32_t REF_CNT_ST_SAVED; /**< Signal Frequency Analyser Reference Clock Count Start Saved Register, offset: 0x1C */ - __I uint32_t REF_CNT_END_SAVED; /**< Signal Frequency Analyser Reference Clock Count End Saved Register, offset: 0x20 */ -} SFA_Type; - -/* ---------------------------------------------------------------------------- - -- SFA Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup SFA_Register_Masks SFA Register Masks - * @{ - */ - -/*! @name CTRL - Signal Frequency Analyser (SFA) Control */ -/*! @{ */ -#define SFA_CTRL_MODE_MASK (0x3U) -#define SFA_CTRL_MODE_SHIFT (0U) -/*! MODE - MEASUREMENT MODE - * 0b00..Frequency measurement performed with REF frequency > CUT Frequency. - * 0b01..Frequency measurement performed with REF frequency < CUT Frequency. - * 0b10..CUT period measurement performed. - * 0b11..Trigger based measurement performed. Note, each trigger pulse must be held for at least 2 ref_clk cycles. - */ -#define SFA_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << SFA_CTRL_MODE_SHIFT)) & SFA_CTRL_MODE_MASK) -#define SFA_CTRL_TRIG_START_POL_MASK (0x4U) -#define SFA_CTRL_TRIG_START_POL_SHIFT (2U) -/*! TRIG_START_POL - Trigger Start Polarity - * 0b0..Rising edge of TRIGGER[TRIG_START_SEL] will begin the measurement sequence. - * 0b1..Falling edge of TRIGGER[TRIG_START_SEL] will begin the measurement sequence. - */ -#define SFA_CTRL_TRIG_START_POL(x) (((uint32_t)(((uint32_t)(x)) << SFA_CTRL_TRIG_START_POL_SHIFT)) & SFA_CTRL_TRIG_START_POL_MASK) -#define SFA_CTRL_TRIG_END_POL_MASK (0x8U) -#define SFA_CTRL_TRIG_END_POL_SHIFT (3U) -/*! TRIG_END_POL - Trigger End Polarity - * 0b0..Rising edge of TRIGER[TRIG_END_SEL] will end the measurement sequence. - * 0b1..Falling edge of TRIGGER[TRIG_END_SEL] will end the measurement sequence. - */ -#define SFA_CTRL_TRIG_END_POL(x) (((uint32_t)(((uint32_t)(x)) << SFA_CTRL_TRIG_END_POL_SHIFT)) & SFA_CTRL_TRIG_END_POL_MASK) -#define SFA_CTRL_SFA_TRIG_MEAS_EN_MASK (0x10U) -#define SFA_CTRL_SFA_TRIG_MEAS_EN_SHIFT (4U) -/*! SFA_TRIG_MEAS_EN - SFA Triggered Measurement Enable - * 0b0..The measurement will start by default with a dummy write to the REF and CUT counters. - * 0b1..The measurement will start after receiging a dummy write to the REF_CNT followed by receiving the trigger - * edge selected by TRIG_START_SEL and TRIG_START_POL. - */ -#define SFA_CTRL_SFA_TRIG_MEAS_EN(x) (((uint32_t)(((uint32_t)(x)) << SFA_CTRL_SFA_TRIG_MEAS_EN_SHIFT)) & SFA_CTRL_SFA_TRIG_MEAS_EN_MASK) -#define SFA_CTRL_SFA_IRQ_EN_MASK (0x20U) -#define SFA_CTRL_SFA_IRQ_EN_SHIFT (5U) -/*! SFA_IRQ_EN - SFA Interrupt Enable - * 0b0..Interrupts are disabled. - * 0b1..Interrupts are enabled. - */ -#define SFA_CTRL_SFA_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << SFA_CTRL_SFA_IRQ_EN_SHIFT)) & SFA_CTRL_SFA_IRQ_EN_MASK) -#define SFA_CTRL_SFA_EN_MASK (0x40U) -#define SFA_CTRL_SFA_EN_SHIFT (6U) -/*! SFA_EN - SFA Enable - * 0b0..The SFA is disabled. - * 0b1..The SFA is enabled. - */ -#define SFA_CTRL_SFA_EN(x) (((uint32_t)(((uint32_t)(x)) << SFA_CTRL_SFA_EN_SHIFT)) & SFA_CTRL_SFA_EN_MASK) -#define SFA_CTRL_TRIG_START_SEL_MASK (0xF00U) -#define SFA_CTRL_TRIG_START_SEL_SHIFT (8U) -/*! TRIG_START_SEL - Signal MUX For Trigger Based Measurement Start - */ -#define SFA_CTRL_TRIG_START_SEL(x) (((uint32_t)(((uint32_t)(x)) << SFA_CTRL_TRIG_START_SEL_SHIFT)) & SFA_CTRL_TRIG_START_SEL_MASK) -#define SFA_CTRL_TRIG_END_SEL_MASK (0xF000U) -#define SFA_CTRL_TRIG_END_SEL_SHIFT (12U) -/*! TRIG_END_SEL - Signal MUX For Trigger Based Measurement End - */ -#define SFA_CTRL_TRIG_END_SEL(x) (((uint32_t)(((uint32_t)(x)) << SFA_CTRL_TRIG_END_SEL_SHIFT)) & SFA_CTRL_TRIG_END_SEL_MASK) -#define SFA_CTRL_CUT_PREDIV_MASK (0xFF0000U) -#define SFA_CTRL_CUT_PREDIV_SHIFT (16U) -/*! CUT_PREDIV - CUT_PREDIV - * 0b00000000..No Divide - * 0b00000001..No Divide - * 0b00000010..Divide by 2 - * 0b00000011..Divide by 2 - * 0b00000100..Divide by 4 - * 0b00000101..Divide by 4 - * 0b00000110..Divide by 6 - * 0b00000111..Divide by 6 - * 0b00001000..Divide by 8 - * 0b00001001..Divide by 8 - * 0b00001010-0b11111101..Divide by CUT_PREDIV - CUT_PREDIV%2 - * 0b11111110..Divide by 254 - * 0b11111111..Divide by 254 - */ -#define SFA_CTRL_CUT_PREDIV(x) (((uint32_t)(((uint32_t)(x)) << SFA_CTRL_CUT_PREDIV_SHIFT)) & SFA_CTRL_CUT_PREDIV_MASK) -#define SFA_CTRL_CUT_SEL_MASK (0xF000000U) -#define SFA_CTRL_CUT_SEL_SHIFT (24U) -/*! CUT_SEL - CUT_SEL - */ -#define SFA_CTRL_CUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << SFA_CTRL_CUT_SEL_SHIFT)) & SFA_CTRL_CUT_SEL_MASK) -#define SFA_CTRL_CUT_PIN_EN_MASK (0x80000000U) -#define SFA_CTRL_CUT_PIN_EN_SHIFT (31U) -/*! CUT_PIN_EN - CUT_PIN_EN - */ -#define SFA_CTRL_CUT_PIN_EN(x) (((uint32_t)(((uint32_t)(x)) << SFA_CTRL_CUT_PIN_EN_SHIFT)) & SFA_CTRL_CUT_PIN_EN_MASK) -/*! @} */ - -/*! @name CTRL_EXT - Signal Frequency Analyser (SFA) Control Extended */ -/*! @{ */ -#define SFA_CTRL_EXT_CUT_CLK_EN_MASK (0xFFFFU) -#define SFA_CTRL_EXT_CUT_CLK_EN_SHIFT (0U) -/*! CUT_CLK_EN - CUT_CLK_EN - */ -#define SFA_CTRL_EXT_CUT_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SFA_CTRL_EXT_CUT_CLK_EN_SHIFT)) & SFA_CTRL_EXT_CUT_CLK_EN_MASK) -/*! @} */ - -/*! @name CNT_STAT - Signal Frequency Analyser Count Status Register */ -/*! @{ */ -#define SFA_CNT_STAT_REF_STOPPED_MASK (0x1U) -#define SFA_CNT_STAT_REF_STOPPED_SHIFT (0U) -/*! REF_STOPPED - REF_STOPPED - */ -#define SFA_CNT_STAT_REF_STOPPED(x) (((uint32_t)(((uint32_t)(x)) << SFA_CNT_STAT_REF_STOPPED_SHIFT)) & SFA_CNT_STAT_REF_STOPPED_MASK) -#define SFA_CNT_STAT_CUT_STOPPED_MASK (0x2U) -#define SFA_CNT_STAT_CUT_STOPPED_SHIFT (1U) -/*! CUT_STOPPED - CUT_STOPPED - */ -#define SFA_CNT_STAT_CUT_STOPPED(x) (((uint32_t)(((uint32_t)(x)) << SFA_CNT_STAT_CUT_STOPPED_SHIFT)) & SFA_CNT_STAT_CUT_STOPPED_MASK) -#define SFA_CNT_STAT_MEAS_STARTED_MASK (0x4U) -#define SFA_CNT_STAT_MEAS_STARTED_SHIFT (2U) -/*! MEAS_STARTED - Measurement Started Flag - */ -#define SFA_CNT_STAT_MEAS_STARTED(x) (((uint32_t)(((uint32_t)(x)) << SFA_CNT_STAT_MEAS_STARTED_SHIFT)) & SFA_CNT_STAT_MEAS_STARTED_MASK) -#define SFA_CNT_STAT_REF_CNT_TIMEOUT_MASK (0x8U) -#define SFA_CNT_STAT_REF_CNT_TIMEOUT_SHIFT (3U) -/*! REF_CNT_TIMEOUT - Reference Counter Time Out - */ -#define SFA_CNT_STAT_REF_CNT_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SFA_CNT_STAT_REF_CNT_TIMEOUT_SHIFT)) & SFA_CNT_STAT_REF_CNT_TIMEOUT_MASK) -#define SFA_CNT_STAT_SFA_IRQ_MASK (0x10U) -#define SFA_CNT_STAT_SFA_IRQ_SHIFT (4U) -/*! SFA_IRQ - SFA Interrupt Request - */ -#define SFA_CNT_STAT_SFA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SFA_CNT_STAT_SFA_IRQ_SHIFT)) & SFA_CNT_STAT_SFA_IRQ_MASK) -/*! @} */ - -/*! @name CUT_CNT - Signal Frequency Analyser Clock Under Test Counter */ -/*! @{ */ -#define SFA_CUT_CNT_CUT_CNT_MASK (0xFFFFFFFFU) -#define SFA_CUT_CNT_CUT_CNT_SHIFT (0U) -/*! CUT_CNT - CUT_CNT - */ -#define SFA_CUT_CNT_CUT_CNT(x) (((uint32_t)(((uint32_t)(x)) << SFA_CUT_CNT_CUT_CNT_SHIFT)) & SFA_CUT_CNT_CUT_CNT_MASK) -/*! @} */ - -/*! @name REF_CNT - Signal Frequency Analyser Reference Clock Counter */ -/*! @{ */ -#define SFA_REF_CNT_REF_CNT_MASK (0xFFFFFFFFU) -#define SFA_REF_CNT_REF_CNT_SHIFT (0U) -/*! REF_CNT - REF_CNT - */ -#define SFA_REF_CNT_REF_CNT(x) (((uint32_t)(((uint32_t)(x)) << SFA_REF_CNT_REF_CNT_SHIFT)) & SFA_REF_CNT_REF_CNT_MASK) -/*! @} */ - -/*! @name CUT_TARGET - Signal Frequency Analyser Clock Under Test Target Count */ -/*! @{ */ -#define SFA_CUT_TARGET_CUT_TARGET_MASK (0xFFFFFFFFU) -#define SFA_CUT_TARGET_CUT_TARGET_SHIFT (0U) -/*! CUT_TARGET - CUT_TARGET - */ -#define SFA_CUT_TARGET_CUT_TARGET(x) (((uint32_t)(((uint32_t)(x)) << SFA_CUT_TARGET_CUT_TARGET_SHIFT)) & SFA_CUT_TARGET_CUT_TARGET_MASK) -/*! @} */ - -/*! @name REF_TARGET - Signal Frequency Analyser Reference Clock Target Count */ -/*! @{ */ -#define SFA_REF_TARGET_REF_TARGET_MASK (0xFFFFFFFFU) -#define SFA_REF_TARGET_REF_TARGET_SHIFT (0U) -/*! REF_TARGET - REF_TARGET - */ -#define SFA_REF_TARGET_REF_TARGET(x) (((uint32_t)(((uint32_t)(x)) << SFA_REF_TARGET_REF_TARGET_SHIFT)) & SFA_REF_TARGET_REF_TARGET_MASK) -/*! @} */ - -/*! @name REF_CNT_ST_SAVED - Signal Frequency Analyser Reference Clock Count Start Saved Register */ -/*! @{ */ -#define SFA_REF_CNT_ST_SAVED_REF_CNT_ST_SAVED_MASK (0xFFFFFFFFU) -#define SFA_REF_CNT_ST_SAVED_REF_CNT_ST_SAVED_SHIFT (0U) -/*! REF_CNT_ST_SAVED - REF_CNT_ST_SAVED - */ -#define SFA_REF_CNT_ST_SAVED_REF_CNT_ST_SAVED(x) (((uint32_t)(((uint32_t)(x)) << SFA_REF_CNT_ST_SAVED_REF_CNT_ST_SAVED_SHIFT)) & SFA_REF_CNT_ST_SAVED_REF_CNT_ST_SAVED_MASK) -/*! @} */ - -/*! @name REF_CNT_END_SAVED - Signal Frequency Analyser Reference Clock Count End Saved Register */ -/*! @{ */ -#define SFA_REF_CNT_END_SAVED_REF_CNT_END_SAVED_MASK (0xFFFFFFFFU) -#define SFA_REF_CNT_END_SAVED_REF_CNT_END_SAVED_SHIFT (0U) -/*! REF_CNT_END_SAVED - REF_CNT_END_SAVED - */ -#define SFA_REF_CNT_END_SAVED_REF_CNT_END_SAVED(x) (((uint32_t)(((uint32_t)(x)) << SFA_REF_CNT_END_SAVED_REF_CNT_END_SAVED_SHIFT)) & SFA_REF_CNT_END_SAVED_REF_CNT_END_SAVED_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group SFA_Register_Masks */ - - -/* SFA - Peripheral instance base addresses */ -/** Peripheral SFA base address */ -#define SFA_BASE (0x4000C000u) -/** Peripheral SFA base pointer */ -#define SFA ((SFA_Type *)SFA_BASE) -/** Array initializer of SFA peripheral base addresses */ -#define SFA_BASE_ADDRS { SFA_BASE } -/** Array initializer of SFA peripheral base pointers */ -#define SFA_BASE_PTRS { SFA } - -/*! - * @} - */ /* end of group SFA_Peripheral_Access_Layer */ - - /* ---------------------------------------------------------------------------- -- SNVS Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -76015,7 +84999,7 @@ typedef struct { __IO uint32_t LPTAR; /**< SNVS_LP Time Alarm Register, offset: 0x58 */ __IO uint32_t LPSMCMR; /**< SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C */ __IO uint32_t LPSMCLR; /**< SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60 */ - __IO uint32_t LPPGDR; /**< SNVS_LP Power Glitch Detector Register, offset: 0x64 */ + __IO uint32_t LPLVDR; /**< SNVS_LP Digital Low-Voltage Detector Register, offset: 0x64 */ __IO uint32_t LPGPR0_LEGACY_ALIAS; /**< SNVS_LP General Purpose Register 0 (legacy alias), offset: 0x68 */ __IO uint32_t LPZMKR[8]; /**< SNVS_LP Zeroizable Master Key Register, array offset: 0x6C, array step: 0x4 */ uint8_t RESERVED_0[4]; @@ -76049,6 +85033,7 @@ typedef struct { /*! @name HPLR - SNVS_HP Lock Register */ /*! @{ */ + #define SNVS_HPLR_ZMK_WSL_MASK (0x1U) #define SNVS_HPLR_ZMK_WSL_SHIFT (0U) /*! ZMK_WSL @@ -76056,6 +85041,7 @@ typedef struct { * 0b1..Write access is not allowed */ #define SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK) + #define SNVS_HPLR_ZMK_RSL_MASK (0x2U) #define SNVS_HPLR_ZMK_RSL_SHIFT (1U) /*! ZMK_RSL @@ -76063,6 +85049,7 @@ typedef struct { * 0b1..Read access is not allowed */ #define SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK) + #define SNVS_HPLR_SRTC_SL_MASK (0x4U) #define SNVS_HPLR_SRTC_SL_SHIFT (2U) /*! SRTC_SL @@ -76070,6 +85057,7 @@ typedef struct { * 0b1..Write access is not allowed */ #define SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK) + #define SNVS_HPLR_LPCALB_SL_MASK (0x8U) #define SNVS_HPLR_LPCALB_SL_SHIFT (3U) /*! LPCALB_SL @@ -76077,6 +85065,7 @@ typedef struct { * 0b1..Write access is not allowed */ #define SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK) + #define SNVS_HPLR_MC_SL_MASK (0x10U) #define SNVS_HPLR_MC_SL_SHIFT (4U) /*! MC_SL @@ -76084,6 +85073,7 @@ typedef struct { * 0b1..Write access (increment) is not allowed */ #define SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK) + #define SNVS_HPLR_GPR_SL_MASK (0x20U) #define SNVS_HPLR_GPR_SL_SHIFT (5U) /*! GPR_SL @@ -76091,6 +85081,7 @@ typedef struct { * 0b1..Write access is not allowed */ #define SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK) + #define SNVS_HPLR_LPSVCR_SL_MASK (0x40U) #define SNVS_HPLR_LPSVCR_SL_SHIFT (6U) /*! LPSVCR_SL @@ -76098,6 +85089,7 @@ typedef struct { * 0b1..Write access is not allowed */ #define SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK) + #define SNVS_HPLR_LPTGFCR_SL_MASK (0x80U) #define SNVS_HPLR_LPTGFCR_SL_SHIFT (7U) /*! LPTGFCR_SL @@ -76105,6 +85097,7 @@ typedef struct { * 0b1..Write access is not allowed */ #define SNVS_HPLR_LPTGFCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTGFCR_SL_SHIFT)) & SNVS_HPLR_LPTGFCR_SL_MASK) + #define SNVS_HPLR_LPSECR_SL_MASK (0x100U) #define SNVS_HPLR_LPSECR_SL_SHIFT (8U) /*! LPSECR_SL @@ -76112,6 +85105,7 @@ typedef struct { * 0b1..Write access is not allowed */ #define SNVS_HPLR_LPSECR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSECR_SL_SHIFT)) & SNVS_HPLR_LPSECR_SL_MASK) + #define SNVS_HPLR_MKS_SL_MASK (0x200U) #define SNVS_HPLR_MKS_SL_SHIFT (9U) /*! MKS_SL @@ -76119,6 +85113,7 @@ typedef struct { * 0b1..Write access is not allowed */ #define SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK) + #define SNVS_HPLR_HPSVCR_L_MASK (0x10000U) #define SNVS_HPLR_HPSVCR_L_SHIFT (16U) /*! HPSVCR_L @@ -76126,6 +85121,7 @@ typedef struct { * 0b1..Write access is not allowed */ #define SNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK) + #define SNVS_HPLR_HPSICR_L_MASK (0x20000U) #define SNVS_HPLR_HPSICR_L_SHIFT (17U) /*! HPSICR_L @@ -76133,6 +85129,7 @@ typedef struct { * 0b1..Write access is not allowed */ #define SNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK) + #define SNVS_HPLR_HAC_L_MASK (0x40000U) #define SNVS_HPLR_HAC_L_SHIFT (18U) /*! HAC_L @@ -76140,6 +85137,7 @@ typedef struct { * 0b1..Write access is not allowed */ #define SNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK) + #define SNVS_HPLR_AT1_SL_MASK (0x1000000U) #define SNVS_HPLR_AT1_SL_SHIFT (24U) /*! AT1_SL @@ -76147,6 +85145,7 @@ typedef struct { * 0b1..Write access is not allowed. */ #define SNVS_HPLR_AT1_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT1_SL_SHIFT)) & SNVS_HPLR_AT1_SL_MASK) + #define SNVS_HPLR_AT2_SL_MASK (0x2000000U) #define SNVS_HPLR_AT2_SL_SHIFT (25U) /*! AT2_SL @@ -76154,6 +85153,7 @@ typedef struct { * 0b1..Write access is not allowed. */ #define SNVS_HPLR_AT2_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT2_SL_SHIFT)) & SNVS_HPLR_AT2_SL_MASK) + #define SNVS_HPLR_AT3_SL_MASK (0x4000000U) #define SNVS_HPLR_AT3_SL_SHIFT (26U) /*! AT3_SL @@ -76161,6 +85161,7 @@ typedef struct { * 0b1..Write access is not allowed. */ #define SNVS_HPLR_AT3_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT3_SL_SHIFT)) & SNVS_HPLR_AT3_SL_MASK) + #define SNVS_HPLR_AT4_SL_MASK (0x8000000U) #define SNVS_HPLR_AT4_SL_SHIFT (27U) /*! AT4_SL @@ -76168,6 +85169,7 @@ typedef struct { * 0b1..Write access is not allowed. */ #define SNVS_HPLR_AT4_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT4_SL_SHIFT)) & SNVS_HPLR_AT4_SL_MASK) + #define SNVS_HPLR_AT5_SL_MASK (0x10000000U) #define SNVS_HPLR_AT5_SL_SHIFT (28U) /*! AT5_SL @@ -76179,9 +85181,11 @@ typedef struct { /*! @name HPCOMR - SNVS_HP Command Register */ /*! @{ */ + #define SNVS_HPCOMR_SSM_ST_MASK (0x1U) #define SNVS_HPCOMR_SSM_ST_SHIFT (0U) #define SNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK) + #define SNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U) #define SNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U) /*! SSM_ST_DIS @@ -76189,6 +85193,7 @@ typedef struct { * 0b1..Secure to Trusted State transition is disabled */ #define SNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK) + #define SNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U) #define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U) /*! SSM_SFNS_DIS @@ -76196,6 +85201,7 @@ typedef struct { * 0b1..Soft Fail to Non-Secure State transition is disabled */ #define SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK) + #define SNVS_HPCOMR_LP_SWR_MASK (0x10U) #define SNVS_HPCOMR_LP_SWR_SHIFT (4U) /*! LP_SWR @@ -76203,6 +85209,7 @@ typedef struct { * 0b1..Reset LP section */ #define SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK) + #define SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U) #define SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U) /*! LP_SWR_DIS @@ -76210,15 +85217,19 @@ typedef struct { * 0b1..LP software reset is disabled */ #define SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK) + #define SNVS_HPCOMR_SW_SV_MASK (0x100U) #define SNVS_HPCOMR_SW_SV_SHIFT (8U) #define SNVS_HPCOMR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK) + #define SNVS_HPCOMR_SW_FSV_MASK (0x200U) #define SNVS_HPCOMR_SW_FSV_SHIFT (9U) #define SNVS_HPCOMR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK) + #define SNVS_HPCOMR_SW_LPSV_MASK (0x400U) #define SNVS_HPCOMR_SW_LPSV_SHIFT (10U) #define SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK) + #define SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U) #define SNVS_HPCOMR_PROG_ZMK_SHIFT (12U) /*! PROG_ZMK @@ -76226,6 +85237,7 @@ typedef struct { * 0b1..Activate hardware key programming mechanism */ #define SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK) + #define SNVS_HPCOMR_MKS_EN_MASK (0x2000U) #define SNVS_HPCOMR_MKS_EN_SHIFT (13U) /*! MKS_EN @@ -76233,6 +85245,7 @@ typedef struct { * 0b1..SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR */ #define SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK) + #define SNVS_HPCOMR_HAC_EN_MASK (0x10000U) #define SNVS_HPCOMR_HAC_EN_SHIFT (16U) /*! HAC_EN @@ -76240,6 +85253,7 @@ typedef struct { * 0b1..High Assurance Counter is enabled */ #define SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK) + #define SNVS_HPCOMR_HAC_LOAD_MASK (0x20000U) #define SNVS_HPCOMR_HAC_LOAD_SHIFT (17U) /*! HAC_LOAD @@ -76247,6 +85261,7 @@ typedef struct { * 0b1..Load the HAC */ #define SNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK) + #define SNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U) #define SNVS_HPCOMR_HAC_CLEAR_SHIFT (18U) /*! HAC_CLEAR @@ -76254,9 +85269,11 @@ typedef struct { * 0b1..Clear the HAC */ #define SNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK) + #define SNVS_HPCOMR_HAC_STOP_MASK (0x80000U) #define SNVS_HPCOMR_HAC_STOP_SHIFT (19U) #define SNVS_HPCOMR_HAC_STOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK) + #define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U) #define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U) #define SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK) @@ -76264,6 +85281,7 @@ typedef struct { /*! @name HPCR - SNVS_HP Control Register */ /*! @{ */ + #define SNVS_HPCR_RTC_EN_MASK (0x1U) #define SNVS_HPCR_RTC_EN_SHIFT (0U) /*! RTC_EN @@ -76271,6 +85289,7 @@ typedef struct { * 0b1..RTC is enabled */ #define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK) + #define SNVS_HPCR_HPTA_EN_MASK (0x2U) #define SNVS_HPCR_HPTA_EN_SHIFT (1U) /*! HPTA_EN @@ -76278,6 +85297,7 @@ typedef struct { * 0b1..HP Time Alarm Interrupt is enabled */ #define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK) + #define SNVS_HPCR_DIS_PI_MASK (0x4U) #define SNVS_HPCR_DIS_PI_SHIFT (2U) /*! DIS_PI @@ -76285,6 +85305,7 @@ typedef struct { * 0b1..Disable periodic interrupt in the function interrupt */ #define SNVS_HPCR_DIS_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK) + #define SNVS_HPCR_PI_EN_MASK (0x8U) #define SNVS_HPCR_PI_EN_SHIFT (3U) /*! PI_EN @@ -76292,6 +85313,7 @@ typedef struct { * 0b1..HP Periodic Interrupt is enabled */ #define SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK) + #define SNVS_HPCR_PI_FREQ_MASK (0xF0U) #define SNVS_HPCR_PI_FREQ_SHIFT (4U) /*! PI_FREQ @@ -76313,6 +85335,7 @@ typedef struct { * 0b1111..- bit 15 of the HPRTCLR is selected as a source of the periodic interrupt */ #define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK) + #define SNVS_HPCR_HPCALB_EN_MASK (0x100U) #define SNVS_HPCR_HPCALB_EN_SHIFT (8U) /*! HPCALB_EN @@ -76320,6 +85343,7 @@ typedef struct { * 0b1..HP Timer calibration enabled */ #define SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK) + #define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U) #define SNVS_HPCR_HPCALB_VAL_SHIFT (10U) /*! HPCALB_VAL @@ -76333,6 +85357,7 @@ typedef struct { * 0b11111..-1 counts per each 32768 ticks of the counter */ #define SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK) + #define SNVS_HPCR_HP_TS_MASK (0x10000U) #define SNVS_HPCR_HP_TS_SHIFT (16U) /*! HP_TS @@ -76340,9 +85365,11 @@ typedef struct { * 0b1..Synchronize the HP Time Counter to the LP Time Counter */ #define SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK) + #define SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U) #define SNVS_HPCR_BTN_CONFIG_SHIFT (24U) #define SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK) + #define SNVS_HPCR_BTN_MASK_MASK (0x8000000U) #define SNVS_HPCR_BTN_MASK_SHIFT (27U) #define SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK) @@ -76350,48 +85377,47 @@ typedef struct { /*! @name HPSICR - SNVS_HP Security Interrupt Control Register */ /*! @{ */ -#define SNVS_HPSICR_SV0_EN_MASK (0x1U) -#define SNVS_HPSICR_SV0_EN_SHIFT (0U) -/*! SV0_EN - * 0b0..Security Violation 0 Interrupt is Disabled - * 0b1..Security Violation 0 Interrupt is Enabled - */ -#define SNVS_HPSICR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV0_EN_SHIFT)) & SNVS_HPSICR_SV0_EN_MASK) -#define SNVS_HPSICR_SV1_EN_MASK (0x2U) -#define SNVS_HPSICR_SV1_EN_SHIFT (1U) -/*! SV1_EN - * 0b0..Security Violation 1 Interrupt is Disabled - * 0b1..Security Violation 1 Interrupt is Enabled - */ -#define SNVS_HPSICR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV1_EN_SHIFT)) & SNVS_HPSICR_SV1_EN_MASK) -#define SNVS_HPSICR_SV2_EN_MASK (0x4U) -#define SNVS_HPSICR_SV2_EN_SHIFT (2U) -/*! SV2_EN - * 0b0..Security Violation 2 Interrupt is Disabled - * 0b1..Security Violation 2 Interrupt is Enabled - */ -#define SNVS_HPSICR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV2_EN_SHIFT)) & SNVS_HPSICR_SV2_EN_MASK) -#define SNVS_HPSICR_SV3_EN_MASK (0x8U) -#define SNVS_HPSICR_SV3_EN_SHIFT (3U) -/*! SV3_EN - * 0b0..Security Violation 3 Interrupt is Disabled - * 0b1..Security Violation 3 Interrupt is Enabled - */ -#define SNVS_HPSICR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV3_EN_SHIFT)) & SNVS_HPSICR_SV3_EN_MASK) -#define SNVS_HPSICR_SV4_EN_MASK (0x10U) -#define SNVS_HPSICR_SV4_EN_SHIFT (4U) -/*! SV4_EN - * 0b0..Security Violation 4 Interrupt is Disabled - * 0b1..Security Violation 4 Interrupt is Enabled - */ -#define SNVS_HPSICR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV4_EN_SHIFT)) & SNVS_HPSICR_SV4_EN_MASK) -#define SNVS_HPSICR_SV5_EN_MASK (0x20U) -#define SNVS_HPSICR_SV5_EN_SHIFT (5U) -/*! SV5_EN - * 0b0..Security Violation 5 Interrupt is Disabled - * 0b1..Security Violation 5 Interrupt is Enabled - */ -#define SNVS_HPSICR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SV5_EN_SHIFT)) & SNVS_HPSICR_SV5_EN_MASK) + +#define SNVS_HPSICR_CAAM_EN_MASK (0x1U) +#define SNVS_HPSICR_CAAM_EN_SHIFT (0U) +/*! CAAM_EN + * 0b0..CAAM Security Violation Interrupt is Disabled + * 0b1..CAAM Security Violation Interrupt is Enabled + */ +#define SNVS_HPSICR_CAAM_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_CAAM_EN_SHIFT)) & SNVS_HPSICR_CAAM_EN_MASK) + +#define SNVS_HPSICR_JTAGC_EN_MASK (0x2U) +#define SNVS_HPSICR_JTAGC_EN_SHIFT (1U) +/*! JTAGC_EN + * 0b0..JTAG Active Interrupt is Disabled + * 0b1..JTAG Active Interrupt is Enabled + */ +#define SNVS_HPSICR_JTAGC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_JTAGC_EN_SHIFT)) & SNVS_HPSICR_JTAGC_EN_MASK) + +#define SNVS_HPSICR_WDOG2_EN_MASK (0x4U) +#define SNVS_HPSICR_WDOG2_EN_SHIFT (2U) +/*! WDOG2_EN + * 0b0..Watchdog 2 Reset Interrupt is Disabled + * 0b1..Watchdog 2 Reset Interrupt is Enabled + */ +#define SNVS_HPSICR_WDOG2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_WDOG2_EN_SHIFT)) & SNVS_HPSICR_WDOG2_EN_MASK) + +#define SNVS_HPSICR_SRC_EN_MASK (0x10U) +#define SNVS_HPSICR_SRC_EN_SHIFT (4U) +/*! SRC_EN + * 0b0..Internal Boot Interrupt is Disabled + * 0b1..Internal Boot Interrupt is Enabled + */ +#define SNVS_HPSICR_SRC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SRC_EN_SHIFT)) & SNVS_HPSICR_SRC_EN_MASK) + +#define SNVS_HPSICR_OCOTP_EN_MASK (0x20U) +#define SNVS_HPSICR_OCOTP_EN_SHIFT (5U) +/*! OCOTP_EN + * 0b0..OCOTP attack error Interrupt is Disabled + * 0b1..OCOTP attack error Interrupt is Enabled + */ +#define SNVS_HPSICR_OCOTP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_OCOTP_EN_SHIFT)) & SNVS_HPSICR_OCOTP_EN_MASK) + #define SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U) #define SNVS_HPSICR_LPSVI_EN_SHIFT (31U) /*! LPSVI_EN @@ -76403,49 +85429,48 @@ typedef struct { /*! @name HPSVCR - SNVS_HP Security Violation Control Register */ /*! @{ */ -#define SNVS_HPSVCR_SV0_CFG_MASK (0x1U) -#define SNVS_HPSVCR_SV0_CFG_SHIFT (0U) -/*! SV0_CFG - * 0b0..Security Violation 0 is a non-fatal violation - * 0b1..Security Violation 0 is a fatal violation - */ -#define SNVS_HPSVCR_SV0_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV0_CFG_SHIFT)) & SNVS_HPSVCR_SV0_CFG_MASK) -#define SNVS_HPSVCR_SV1_CFG_MASK (0x2U) -#define SNVS_HPSVCR_SV1_CFG_SHIFT (1U) -/*! SV1_CFG - * 0b0..Security Violation 1 is a non-fatal violation - * 0b1..Security Violation 1 is a fatal violation - */ -#define SNVS_HPSVCR_SV1_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV1_CFG_SHIFT)) & SNVS_HPSVCR_SV1_CFG_MASK) -#define SNVS_HPSVCR_SV2_CFG_MASK (0x4U) -#define SNVS_HPSVCR_SV2_CFG_SHIFT (2U) -/*! SV2_CFG - * 0b0..Security Violation 2 is a non-fatal violation - * 0b1..Security Violation 2 is a fatal violation - */ -#define SNVS_HPSVCR_SV2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV2_CFG_SHIFT)) & SNVS_HPSVCR_SV2_CFG_MASK) -#define SNVS_HPSVCR_SV3_CFG_MASK (0x8U) -#define SNVS_HPSVCR_SV3_CFG_SHIFT (3U) -/*! SV3_CFG - * 0b0..Security Violation 3 is a non-fatal violation - * 0b1..Security Violation 3 is a fatal violation - */ -#define SNVS_HPSVCR_SV3_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV3_CFG_SHIFT)) & SNVS_HPSVCR_SV3_CFG_MASK) -#define SNVS_HPSVCR_SV4_CFG_MASK (0x10U) -#define SNVS_HPSVCR_SV4_CFG_SHIFT (4U) -/*! SV4_CFG - * 0b0..Security Violation 4 is a non-fatal violation - * 0b1..Security Violation 4 is a fatal violation - */ -#define SNVS_HPSVCR_SV4_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV4_CFG_SHIFT)) & SNVS_HPSVCR_SV4_CFG_MASK) -#define SNVS_HPSVCR_SV5_CFG_MASK (0x60U) -#define SNVS_HPSVCR_SV5_CFG_SHIFT (5U) -/*! SV5_CFG - * 0b00..Security Violation 5 is disabled - * 0b01..Security Violation 5 is a non-fatal violation - * 0b1x..Security Violation 5 is a fatal violation - */ -#define SNVS_HPSVCR_SV5_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SV5_CFG_SHIFT)) & SNVS_HPSVCR_SV5_CFG_MASK) + +#define SNVS_HPSVCR_CAAM_CFG_MASK (0x1U) +#define SNVS_HPSVCR_CAAM_CFG_SHIFT (0U) +/*! CAAM_CFG + * 0b0..CAAM Security Violation is a non-fatal violation + * 0b1..CAAM Security Violation is a fatal violation + */ +#define SNVS_HPSVCR_CAAM_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_CAAM_CFG_SHIFT)) & SNVS_HPSVCR_CAAM_CFG_MASK) + +#define SNVS_HPSVCR_JTAGC_CFG_MASK (0x2U) +#define SNVS_HPSVCR_JTAGC_CFG_SHIFT (1U) +/*! JTAGC_CFG + * 0b0..JTAG Active is a non-fatal violation + * 0b1..JTAG Active is a fatal violation + */ +#define SNVS_HPSVCR_JTAGC_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_JTAGC_CFG_SHIFT)) & SNVS_HPSVCR_JTAGC_CFG_MASK) + +#define SNVS_HPSVCR_WDOG2_CFG_MASK (0x4U) +#define SNVS_HPSVCR_WDOG2_CFG_SHIFT (2U) +/*! WDOG2_CFG + * 0b0..Watchdog 2 Reset is a non-fatal violation + * 0b1..Watchdog 2 Reset is a fatal violation + */ +#define SNVS_HPSVCR_WDOG2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_WDOG2_CFG_SHIFT)) & SNVS_HPSVCR_WDOG2_CFG_MASK) + +#define SNVS_HPSVCR_SRC_CFG_MASK (0x10U) +#define SNVS_HPSVCR_SRC_CFG_SHIFT (4U) +/*! SRC_CFG + * 0b0..Internal Boot is a non-fatal violation + * 0b1..Internal Boot is a fatal violation + */ +#define SNVS_HPSVCR_SRC_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SRC_CFG_SHIFT)) & SNVS_HPSVCR_SRC_CFG_MASK) + +#define SNVS_HPSVCR_OCOTP_CFG_MASK (0x60U) +#define SNVS_HPSVCR_OCOTP_CFG_SHIFT (5U) +/*! OCOTP_CFG + * 0b00..OCOTP attack error is disabled + * 0b01..OCOTP attack error is a non-fatal violation + * 0b1x..OCOTP attack error is a fatal violation + */ +#define SNVS_HPSVCR_OCOTP_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_OCOTP_CFG_SHIFT)) & SNVS_HPSVCR_OCOTP_CFG_MASK) + #define SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U) #define SNVS_HPSVCR_LPSV_CFG_SHIFT (30U) /*! LPSV_CFG @@ -76458,6 +85483,7 @@ typedef struct { /*! @name HPSR - SNVS_HP Status Register */ /*! @{ */ + #define SNVS_HPSR_HPTA_MASK (0x1U) #define SNVS_HPSR_HPTA_SHIFT (0U) /*! HPTA @@ -76465,6 +85491,7 @@ typedef struct { * 0b1..A time alarm interrupt occurred. */ #define SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK) + #define SNVS_HPSR_PI_MASK (0x2U) #define SNVS_HPSR_PI_SHIFT (1U) /*! PI @@ -76472,15 +85499,19 @@ typedef struct { * 0b1..A periodic interrupt occurred. */ #define SNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK) + #define SNVS_HPSR_LPDIS_MASK (0x10U) #define SNVS_HPSR_LPDIS_SHIFT (4U) #define SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK) + #define SNVS_HPSR_BTN_MASK (0x40U) #define SNVS_HPSR_BTN_SHIFT (6U) #define SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK) + #define SNVS_HPSR_BI_MASK (0x80U) #define SNVS_HPSR_BI_SHIFT (7U) #define SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK) + #define SNVS_HPSR_SSM_STATE_MASK (0xF00U) #define SNVS_HPSR_SSM_STATE_SHIFT (8U) /*! SSM_STATE @@ -76494,15 +85525,21 @@ typedef struct { * 0b1111..Secure */ #define SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK) -#define SNVS_HPSR_SECURITY_CONFIG_MASK (0xF000U) -#define SNVS_HPSR_SECURITY_CONFIG_SHIFT (12U) -/*! SECURITY_CONFIG - * 0b0000, 0b1000..FAB configuration - * 0b0001, 0b0010, 0b0011..OPEN configuration - * 0b1010, 0b1001, 0b1011..CLOSED configuration - * 0bx1xx..FIELD RETURN configuration - */ -#define SNVS_HPSR_SECURITY_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SECURITY_CONFIG_SHIFT)) & SNVS_HPSR_SECURITY_CONFIG_MASK) + +#define SNVS_HPSR_SYS_SECURITY_CFG_MASK (0x7000U) +#define SNVS_HPSR_SYS_SECURITY_CFG_SHIFT (12U) +/*! SYS_SECURITY_CFG + * 0b000..Fab Configuration - the default configuration of newly fabricated chips + * 0b001..Open Configuration - the configuration after NXP-programmable fuses have been blown + * 0b011..Closed Configuration - the configuration after OEM-programmable fuses have been blown + * 0b111..Field Return Configuration - the configuration of chips that are returned to NXP for analysis + */ +#define SNVS_HPSR_SYS_SECURITY_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURITY_CFG_SHIFT)) & SNVS_HPSR_SYS_SECURITY_CFG_MASK) + +#define SNVS_HPSR_SYS_SECURE_BOOT_MASK (0x8000U) +#define SNVS_HPSR_SYS_SECURE_BOOT_SHIFT (15U) +#define SNVS_HPSR_SYS_SECURE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURE_BOOT_SHIFT)) & SNVS_HPSR_SYS_SECURE_BOOT_MASK) + #define SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U) #define SNVS_HPSR_OTPMK_ZERO_SHIFT (27U) /*! OTPMK_ZERO @@ -76510,6 +85547,7 @@ typedef struct { * 0b1..The OTPMK is zero. */ #define SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK) + #define SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U) #define SNVS_HPSR_ZMK_ZERO_SHIFT (31U) /*! ZMK_ZERO @@ -76521,60 +85559,63 @@ typedef struct { /*! @name HPSVSR - SNVS_HP Security Violation Status Register */ /*! @{ */ -#define SNVS_HPSVSR_SV0_MASK (0x1U) -#define SNVS_HPSVSR_SV0_SHIFT (0U) -/*! SV0 - * 0b0..No Security Violation 0 security violation was detected. - * 0b1..Security Violation 0 security violation was detected. - */ -#define SNVS_HPSVSR_SV0(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV0_SHIFT)) & SNVS_HPSVSR_SV0_MASK) -#define SNVS_HPSVSR_SV1_MASK (0x2U) -#define SNVS_HPSVSR_SV1_SHIFT (1U) -/*! SV1 - * 0b0..No Security Violation 1 security violation was detected. - * 0b1..Security Violation 1 security violation was detected. - */ -#define SNVS_HPSVSR_SV1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV1_SHIFT)) & SNVS_HPSVSR_SV1_MASK) -#define SNVS_HPSVSR_SV2_MASK (0x4U) -#define SNVS_HPSVSR_SV2_SHIFT (2U) -/*! SV2 - * 0b0..No Security Violation 2 security violation was detected. - * 0b1..Security Violation 2 security violation was detected. - */ -#define SNVS_HPSVSR_SV2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV2_SHIFT)) & SNVS_HPSVSR_SV2_MASK) -#define SNVS_HPSVSR_SV3_MASK (0x8U) -#define SNVS_HPSVSR_SV3_SHIFT (3U) -/*! SV3 - * 0b0..No Security Violation 3 security violation was detected. - * 0b1..Security Violation 3 security violation was detected. - */ -#define SNVS_HPSVSR_SV3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV3_SHIFT)) & SNVS_HPSVSR_SV3_MASK) -#define SNVS_HPSVSR_SV4_MASK (0x10U) -#define SNVS_HPSVSR_SV4_SHIFT (4U) -/*! SV4 - * 0b0..No Security Violation 4 security violation was detected. - * 0b1..Security Violation 4 security violation was detected. - */ -#define SNVS_HPSVSR_SV4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV4_SHIFT)) & SNVS_HPSVSR_SV4_MASK) -#define SNVS_HPSVSR_SV5_MASK (0x20U) -#define SNVS_HPSVSR_SV5_SHIFT (5U) -/*! SV5 - * 0b0..No Security Violation 5 security violation was detected. - * 0b1..Security Violation 5 security violation was detected. - */ -#define SNVS_HPSVSR_SV5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SV5_SHIFT)) & SNVS_HPSVSR_SV5_MASK) + +#define SNVS_HPSVSR_CAAM_MASK (0x1U) +#define SNVS_HPSVSR_CAAM_SHIFT (0U) +/*! CAAM + * 0b0..No CAAM Security Violation security violation was detected. + * 0b1..CAAM Security Violation security violation was detected. + */ +#define SNVS_HPSVSR_CAAM(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_CAAM_SHIFT)) & SNVS_HPSVSR_CAAM_MASK) + +#define SNVS_HPSVSR_JTAGC_MASK (0x2U) +#define SNVS_HPSVSR_JTAGC_SHIFT (1U) +/*! JTAGC + * 0b0..No JTAG Active security violation was detected. + * 0b1..JTAG Active security violation was detected. + */ +#define SNVS_HPSVSR_JTAGC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_JTAGC_SHIFT)) & SNVS_HPSVSR_JTAGC_MASK) + +#define SNVS_HPSVSR_WDOG2_MASK (0x4U) +#define SNVS_HPSVSR_WDOG2_SHIFT (2U) +/*! WDOG2 + * 0b0..No Watchdog 2 Reset security violation was detected. + * 0b1..Watchdog 2 Reset security violation was detected. + */ +#define SNVS_HPSVSR_WDOG2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_WDOG2_SHIFT)) & SNVS_HPSVSR_WDOG2_MASK) + +#define SNVS_HPSVSR_SRC_MASK (0x10U) +#define SNVS_HPSVSR_SRC_SHIFT (4U) +/*! SRC + * 0b0..No Internal Boot security violation was detected. + * 0b1..Internal Boot security violation was detected. + */ +#define SNVS_HPSVSR_SRC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SRC_SHIFT)) & SNVS_HPSVSR_SRC_MASK) + +#define SNVS_HPSVSR_OCOTP_MASK (0x20U) +#define SNVS_HPSVSR_OCOTP_SHIFT (5U) +/*! OCOTP + * 0b0..No OCOTP attack error security violation was detected. + * 0b1..OCOTP attack error security violation was detected. + */ +#define SNVS_HPSVSR_OCOTP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_OCOTP_SHIFT)) & SNVS_HPSVSR_OCOTP_MASK) + #define SNVS_HPSVSR_SW_SV_MASK (0x2000U) #define SNVS_HPSVSR_SW_SV_SHIFT (13U) #define SNVS_HPSVSR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK) + #define SNVS_HPSVSR_SW_FSV_MASK (0x4000U) #define SNVS_HPSVSR_SW_FSV_SHIFT (14U) #define SNVS_HPSVSR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK) + #define SNVS_HPSVSR_SW_LPSV_MASK (0x8000U) #define SNVS_HPSVSR_SW_LPSV_SHIFT (15U) #define SNVS_HPSVSR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK) + #define SNVS_HPSVSR_ZMK_SYNDROME_MASK (0x1FF0000U) #define SNVS_HPSVSR_ZMK_SYNDROME_SHIFT (16U) #define SNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK) + #define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U) #define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U) /*! ZMK_ECC_FAIL @@ -76582,6 +85623,7 @@ typedef struct { * 0b1..ZMK ECC Failure was detected. */ #define SNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK) + #define SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U) #define SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U) #define SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK) @@ -76589,6 +85631,7 @@ typedef struct { /*! @name HPHACIVR - SNVS_HP High Assurance Counter IV Register */ /*! @{ */ + #define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU) #define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U) #define SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK) @@ -76596,6 +85639,7 @@ typedef struct { /*! @name HPHACR - SNVS_HP High Assurance Counter Register */ /*! @{ */ + #define SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU) #define SNVS_HPHACR_HAC_COUNTER_SHIFT (0U) #define SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK) @@ -76603,6 +85647,7 @@ typedef struct { /*! @name HPRTCMR - SNVS_HP Real Time Counter MSB Register */ /*! @{ */ + #define SNVS_HPRTCMR_RTC_MASK (0x7FFFU) #define SNVS_HPRTCMR_RTC_SHIFT (0U) #define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK) @@ -76610,6 +85655,7 @@ typedef struct { /*! @name HPRTCLR - SNVS_HP Real Time Counter LSB Register */ /*! @{ */ + #define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU) #define SNVS_HPRTCLR_RTC_SHIFT (0U) #define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK) @@ -76617,6 +85663,7 @@ typedef struct { /*! @name HPTAMR - SNVS_HP Time Alarm MSB Register */ /*! @{ */ + #define SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU) #define SNVS_HPTAMR_HPTA_MS_SHIFT (0U) #define SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK) @@ -76624,6 +85671,7 @@ typedef struct { /*! @name HPTALR - SNVS_HP Time Alarm LSB Register */ /*! @{ */ + #define SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU) #define SNVS_HPTALR_HPTA_LS_SHIFT (0U) #define SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK) @@ -76631,6 +85679,7 @@ typedef struct { /*! @name LPLR - SNVS_LP Lock Register */ /*! @{ */ + #define SNVS_LPLR_ZMK_WHL_MASK (0x1U) #define SNVS_LPLR_ZMK_WHL_SHIFT (0U) /*! ZMK_WHL @@ -76638,6 +85687,7 @@ typedef struct { * 0b1..Write access is not allowed. */ #define SNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK) + #define SNVS_LPLR_ZMK_RHL_MASK (0x2U) #define SNVS_LPLR_ZMK_RHL_SHIFT (1U) /*! ZMK_RHL @@ -76645,6 +85695,7 @@ typedef struct { * 0b1..Read access is not allowed. */ #define SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK) + #define SNVS_LPLR_SRTC_HL_MASK (0x4U) #define SNVS_LPLR_SRTC_HL_SHIFT (2U) /*! SRTC_HL @@ -76652,6 +85703,7 @@ typedef struct { * 0b1..Write access is not allowed. */ #define SNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK) + #define SNVS_LPLR_LPCALB_HL_MASK (0x8U) #define SNVS_LPLR_LPCALB_HL_SHIFT (3U) /*! LPCALB_HL @@ -76659,6 +85711,7 @@ typedef struct { * 0b1..Write access is not allowed. */ #define SNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK) + #define SNVS_LPLR_MC_HL_MASK (0x10U) #define SNVS_LPLR_MC_HL_SHIFT (4U) /*! MC_HL @@ -76666,6 +85719,7 @@ typedef struct { * 0b1..Write access (increment) is not allowed. */ #define SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK) + #define SNVS_LPLR_GPR_HL_MASK (0x20U) #define SNVS_LPLR_GPR_HL_SHIFT (5U) /*! GPR_HL @@ -76673,6 +85727,7 @@ typedef struct { * 0b1..Write access is not allowed. */ #define SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK) + #define SNVS_LPLR_LPSVCR_HL_MASK (0x40U) #define SNVS_LPLR_LPSVCR_HL_SHIFT (6U) /*! LPSVCR_HL @@ -76680,6 +85735,7 @@ typedef struct { * 0b1..Write access is not allowed. */ #define SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK) + #define SNVS_LPLR_LPTGFCR_HL_MASK (0x80U) #define SNVS_LPLR_LPTGFCR_HL_SHIFT (7U) /*! LPTGFCR_HL @@ -76687,6 +85743,7 @@ typedef struct { * 0b1..Write access is not allowed. */ #define SNVS_LPLR_LPTGFCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTGFCR_HL_SHIFT)) & SNVS_LPLR_LPTGFCR_HL_MASK) + #define SNVS_LPLR_LPSECR_HL_MASK (0x100U) #define SNVS_LPLR_LPSECR_HL_SHIFT (8U) /*! LPSECR_HL @@ -76694,6 +85751,7 @@ typedef struct { * 0b1..Write access is not allowed. */ #define SNVS_LPLR_LPSECR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSECR_HL_SHIFT)) & SNVS_LPLR_LPSECR_HL_MASK) + #define SNVS_LPLR_MKS_HL_MASK (0x200U) #define SNVS_LPLR_MKS_HL_SHIFT (9U) /*! MKS_HL @@ -76701,6 +85759,7 @@ typedef struct { * 0b1..Write access is not allowed. */ #define SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK) + #define SNVS_LPLR_AT1_HL_MASK (0x1000000U) #define SNVS_LPLR_AT1_HL_SHIFT (24U) /*! AT1_HL @@ -76708,6 +85767,7 @@ typedef struct { * 0b1..Write access is not allowed. */ #define SNVS_LPLR_AT1_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT1_HL_SHIFT)) & SNVS_LPLR_AT1_HL_MASK) + #define SNVS_LPLR_AT2_HL_MASK (0x2000000U) #define SNVS_LPLR_AT2_HL_SHIFT (25U) /*! AT2_HL @@ -76715,6 +85775,7 @@ typedef struct { * 0b1..Write access is not allowed. */ #define SNVS_LPLR_AT2_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT2_HL_SHIFT)) & SNVS_LPLR_AT2_HL_MASK) + #define SNVS_LPLR_AT3_HL_MASK (0x4000000U) #define SNVS_LPLR_AT3_HL_SHIFT (26U) /*! AT3_HL @@ -76722,6 +85783,7 @@ typedef struct { * 0b1..Write access is not allowed. */ #define SNVS_LPLR_AT3_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT3_HL_SHIFT)) & SNVS_LPLR_AT3_HL_MASK) + #define SNVS_LPLR_AT4_HL_MASK (0x8000000U) #define SNVS_LPLR_AT4_HL_SHIFT (27U) /*! AT4_HL @@ -76729,6 +85791,7 @@ typedef struct { * 0b1..Write access is not allowed. */ #define SNVS_LPLR_AT4_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT4_HL_SHIFT)) & SNVS_LPLR_AT4_HL_MASK) + #define SNVS_LPLR_AT5_HL_MASK (0x10000000U) #define SNVS_LPLR_AT5_HL_SHIFT (28U) /*! AT5_HL @@ -76740,6 +85803,7 @@ typedef struct { /*! @name LPCR - SNVS_LP Control Register */ /*! @{ */ + #define SNVS_LPCR_SRTC_ENV_MASK (0x1U) #define SNVS_LPCR_SRTC_ENV_SHIFT (0U) /*! SRTC_ENV @@ -76747,6 +85811,7 @@ typedef struct { * 0b1..SRTC is enabled and valid. */ #define SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK) + #define SNVS_LPCR_LPTA_EN_MASK (0x2U) #define SNVS_LPCR_LPTA_EN_SHIFT (1U) /*! LPTA_EN @@ -76754,6 +85819,7 @@ typedef struct { * 0b1..LP time alarm interrupt is enabled. */ #define SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK) + #define SNVS_LPCR_MC_ENV_MASK (0x4U) #define SNVS_LPCR_MC_ENV_SHIFT (2U) /*! MC_ENV @@ -76761,16 +85827,19 @@ typedef struct { * 0b1..MC is enabled and valid. */ #define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK) + #define SNVS_LPCR_LPWUI_EN_MASK (0x8U) #define SNVS_LPCR_LPWUI_EN_SHIFT (3U) #define SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK) + #define SNVS_LPCR_SRTC_INV_EN_MASK (0x10U) #define SNVS_LPCR_SRTC_INV_EN_SHIFT (4U) /*! SRTC_INV_EN - * 0b0..SRTC stays valid in the case of security violation. + * 0b0..SRTC stays valid in the case of security violation (other than a software violation (HPSVSR[SW_LPSV] = 1 or HPCOMR[SW_LPSV] = 1)). * 0b1..SRTC is invalidated in the case of security violation. */ #define SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK) + #define SNVS_LPCR_DP_EN_MASK (0x20U) #define SNVS_LPCR_DP_EN_SHIFT (5U) /*! DP_EN @@ -76778,6 +85847,7 @@ typedef struct { * 0b1..Dumb PMIC enabled. */ #define SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK) + #define SNVS_LPCR_TOP_MASK (0x40U) #define SNVS_LPCR_TOP_SHIFT (6U) /*! TOP @@ -76785,9 +85855,11 @@ typedef struct { * 0b1..Turn off system power. */ #define SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK) -#define SNVS_LPCR_PWR_GLITCH_EN_MASK (0x80U) -#define SNVS_LPCR_PWR_GLITCH_EN_SHIFT (7U) -#define SNVS_LPCR_PWR_GLITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PWR_GLITCH_EN_SHIFT)) & SNVS_LPCR_PWR_GLITCH_EN_MASK) + +#define SNVS_LPCR_LVD_EN_MASK (0x80U) +#define SNVS_LPCR_LVD_EN_SHIFT (7U) +#define SNVS_LPCR_LVD_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LVD_EN_SHIFT)) & SNVS_LPCR_LVD_EN_MASK) + #define SNVS_LPCR_LPCALB_EN_MASK (0x100U) #define SNVS_LPCR_LPCALB_EN_SHIFT (8U) /*! LPCALB_EN @@ -76795,6 +85867,7 @@ typedef struct { * 0b1..SRTC Time calibration is enabled. */ #define SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK) + #define SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U) #define SNVS_LPCR_LPCALB_VAL_SHIFT (10U) /*! LPCALB_VAL @@ -76808,21 +85881,27 @@ typedef struct { * 0b11111..-1 counts per each 32768 ticks of the counter clock */ #define SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK) + #define SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U) #define SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U) #define SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK) + #define SNVS_LPCR_DEBOUNCE_MASK (0xC0000U) #define SNVS_LPCR_DEBOUNCE_SHIFT (18U) #define SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK) + #define SNVS_LPCR_ON_TIME_MASK (0x300000U) #define SNVS_LPCR_ON_TIME_SHIFT (20U) #define SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK) + #define SNVS_LPCR_PK_EN_MASK (0x400000U) #define SNVS_LPCR_PK_EN_SHIFT (22U) #define SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK) + #define SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U) #define SNVS_LPCR_PK_OVERRIDE_SHIFT (23U) #define SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK) + #define SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U) #define SNVS_LPCR_GPR_Z_DIS_SHIFT (24U) #define SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK) @@ -76830,6 +85909,7 @@ typedef struct { /*! @name LPMKCR - SNVS_LP Master Key Control Register */ /*! @{ */ + #define SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U) #define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U) /*! MASTER_KEY_SEL @@ -76838,6 +85918,7 @@ typedef struct { * 0b11..Select combined master key when MKS_EN bit is set . */ #define SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK) + #define SNVS_LPMKCR_ZMK_HWP_MASK (0x4U) #define SNVS_LPMKCR_ZMK_HWP_SHIFT (2U) /*! ZMK_HWP @@ -76845,6 +85926,7 @@ typedef struct { * 0b1..ZMK is in the hardware programming mode. */ #define SNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK) + #define SNVS_LPMKCR_ZMK_VAL_MASK (0x8U) #define SNVS_LPMKCR_ZMK_VAL_SHIFT (3U) /*! ZMK_VAL @@ -76852,6 +85934,7 @@ typedef struct { * 0b1..ZMK is valid. */ #define SNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK) + #define SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U) #define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U) /*! ZMK_ECC_EN @@ -76859,6 +85942,7 @@ typedef struct { * 0b1..ZMK ECC check is enabled. */ #define SNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK) + #define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U) #define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U) #define SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK) @@ -76866,55 +85950,55 @@ typedef struct { /*! @name LPSVCR - SNVS_LP Security Violation Control Register */ /*! @{ */ -#define SNVS_LPSVCR_SV0_EN_MASK (0x1U) -#define SNVS_LPSVCR_SV0_EN_SHIFT (0U) -/*! SV0_EN - * 0b0..Security Violation 0 is disabled in the LP domain. - * 0b1..Security Violation 0 is enabled in the LP domain. - */ -#define SNVS_LPSVCR_SV0_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV0_EN_SHIFT)) & SNVS_LPSVCR_SV0_EN_MASK) -#define SNVS_LPSVCR_SV1_EN_MASK (0x2U) -#define SNVS_LPSVCR_SV1_EN_SHIFT (1U) -/*! SV1_EN - * 0b0..Security Violation 1 is disabled in the LP domain. - * 0b1..Security Violation 1 is enabled in the LP domain. - */ -#define SNVS_LPSVCR_SV1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV1_EN_SHIFT)) & SNVS_LPSVCR_SV1_EN_MASK) -#define SNVS_LPSVCR_SV2_EN_MASK (0x4U) -#define SNVS_LPSVCR_SV2_EN_SHIFT (2U) -/*! SV2_EN - * 0b0..Security Violation 2 is disabled in the LP domain. - * 0b1..Security Violation 2 is enabled in the LP domain. - */ -#define SNVS_LPSVCR_SV2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV2_EN_SHIFT)) & SNVS_LPSVCR_SV2_EN_MASK) -#define SNVS_LPSVCR_SV3_EN_MASK (0x8U) -#define SNVS_LPSVCR_SV3_EN_SHIFT (3U) -/*! SV3_EN - * 0b0..Security Violation 3 is disabled in the LP domain. - * 0b1..Security Violation 3 is enabled in the LP domain. - */ -#define SNVS_LPSVCR_SV3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV3_EN_SHIFT)) & SNVS_LPSVCR_SV3_EN_MASK) -#define SNVS_LPSVCR_SV4_EN_MASK (0x10U) -#define SNVS_LPSVCR_SV4_EN_SHIFT (4U) -/*! SV4_EN - * 0b0..Security Violation 4 is disabled in the LP domain. - * 0b1..Security Violation 4 is enabled in the LP domain. - */ -#define SNVS_LPSVCR_SV4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV4_EN_SHIFT)) & SNVS_LPSVCR_SV4_EN_MASK) -#define SNVS_LPSVCR_SV5_EN_MASK (0x20U) -#define SNVS_LPSVCR_SV5_EN_SHIFT (5U) -/*! SV5_EN - * 0b0..Security Violation 5 is disabled in the LP domain. - * 0b1..Security Violation 5 is enabled in the LP domain. - */ -#define SNVS_LPSVCR_SV5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SV5_EN_SHIFT)) & SNVS_LPSVCR_SV5_EN_MASK) + +#define SNVS_LPSVCR_CAAM_EN_MASK (0x1U) +#define SNVS_LPSVCR_CAAM_EN_SHIFT (0U) +/*! CAAM_EN + * 0b0..CAAM Security Violation is disabled in the LP domain. + * 0b1..CAAM Security Violation is enabled in the LP domain. + */ +#define SNVS_LPSVCR_CAAM_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_CAAM_EN_SHIFT)) & SNVS_LPSVCR_CAAM_EN_MASK) + +#define SNVS_LPSVCR_JTAGC_EN_MASK (0x2U) +#define SNVS_LPSVCR_JTAGC_EN_SHIFT (1U) +/*! JTAGC_EN + * 0b0..JTAG Active is disabled in the LP domain. + * 0b1..JTAG Active is enabled in the LP domain. + */ +#define SNVS_LPSVCR_JTAGC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_JTAGC_EN_SHIFT)) & SNVS_LPSVCR_JTAGC_EN_MASK) + +#define SNVS_LPSVCR_WDOG2_EN_MASK (0x4U) +#define SNVS_LPSVCR_WDOG2_EN_SHIFT (2U) +/*! WDOG2_EN + * 0b0..Watchdog 2 Reset is disabled in the LP domain. + * 0b1..Watchdog 2 Reset is enabled in the LP domain. + */ +#define SNVS_LPSVCR_WDOG2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_WDOG2_EN_SHIFT)) & SNVS_LPSVCR_WDOG2_EN_MASK) + +#define SNVS_LPSVCR_SRC_EN_MASK (0x10U) +#define SNVS_LPSVCR_SRC_EN_SHIFT (4U) +/*! SRC_EN + * 0b0..Internal Boot is disabled in the LP domain. + * 0b1..Internal Boot is enabled in the LP domain. + */ +#define SNVS_LPSVCR_SRC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SRC_EN_SHIFT)) & SNVS_LPSVCR_SRC_EN_MASK) + +#define SNVS_LPSVCR_OCOTP_EN_MASK (0x20U) +#define SNVS_LPSVCR_OCOTP_EN_SHIFT (5U) +/*! OCOTP_EN + * 0b0..OCOTP attack error is disabled in the LP domain. + * 0b1..OCOTP attack error is enabled in the LP domain. + */ +#define SNVS_LPSVCR_OCOTP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_OCOTP_EN_SHIFT)) & SNVS_LPSVCR_OCOTP_EN_MASK) /*! @} */ /*! @name LPTGFCR - SNVS_LP Tamper Glitch Filters Configuration Register */ /*! @{ */ + #define SNVS_LPTGFCR_WMTGF_MASK (0x1FU) #define SNVS_LPTGFCR_WMTGF_SHIFT (0U) #define SNVS_LPTGFCR_WMTGF(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_WMTGF_SHIFT)) & SNVS_LPTGFCR_WMTGF_MASK) + #define SNVS_LPTGFCR_WMTGF_EN_MASK (0x80U) #define SNVS_LPTGFCR_WMTGF_EN_SHIFT (7U) /*! WMTGF_EN @@ -76922,9 +86006,11 @@ typedef struct { * 0b1..Wire-mesh tamper glitch filter is enabled. */ #define SNVS_LPTGFCR_WMTGF_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_WMTGF_EN_SHIFT)) & SNVS_LPTGFCR_WMTGF_EN_MASK) + #define SNVS_LPTGFCR_ETGF1_MASK (0x7F0000U) #define SNVS_LPTGFCR_ETGF1_SHIFT (16U) #define SNVS_LPTGFCR_ETGF1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF1_SHIFT)) & SNVS_LPTGFCR_ETGF1_MASK) + #define SNVS_LPTGFCR_ETGF1_EN_MASK (0x800000U) #define SNVS_LPTGFCR_ETGF1_EN_SHIFT (23U) /*! ETGF1_EN @@ -76932,9 +86018,11 @@ typedef struct { * 0b1..External tamper glitch filter 1 is enabled. */ #define SNVS_LPTGFCR_ETGF1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF1_EN_SHIFT)) & SNVS_LPTGFCR_ETGF1_EN_MASK) + #define SNVS_LPTGFCR_ETGF2_MASK (0x7F000000U) #define SNVS_LPTGFCR_ETGF2_SHIFT (24U) #define SNVS_LPTGFCR_ETGF2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF2_SHIFT)) & SNVS_LPTGFCR_ETGF2_MASK) + #define SNVS_LPTGFCR_ETGF2_EN_MASK (0x80000000U) #define SNVS_LPTGFCR_ETGF2_EN_SHIFT (31U) /*! ETGF2_EN @@ -76946,6 +86034,7 @@ typedef struct { /*! @name LPTDCR - SNVS_LP Tamper Detect Configuration Register */ /*! @{ */ + #define SNVS_LPTDCR_SRTCR_EN_MASK (0x2U) #define SNVS_LPTDCR_SRTCR_EN_SHIFT (1U) /*! SRTCR_EN @@ -76953,6 +86042,7 @@ typedef struct { * 0b1..SRTC rollover is enabled. */ #define SNVS_LPTDCR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK) + #define SNVS_LPTDCR_MCR_EN_MASK (0x4U) #define SNVS_LPTDCR_MCR_EN_SHIFT (2U) /*! MCR_EN @@ -76960,6 +86050,7 @@ typedef struct { * 0b1..MC rollover is enabled. */ #define SNVS_LPTDCR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK) + #define SNVS_LPTDCR_CT_EN_MASK (0x10U) #define SNVS_LPTDCR_CT_EN_SHIFT (4U) /*! CT_EN @@ -76967,6 +86058,7 @@ typedef struct { * 0b1..Clock tamper is enabled. */ #define SNVS_LPTDCR_CT_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_CT_EN_SHIFT)) & SNVS_LPTDCR_CT_EN_MASK) + #define SNVS_LPTDCR_TT_EN_MASK (0x20U) #define SNVS_LPTDCR_TT_EN_SHIFT (5U) /*! TT_EN @@ -76974,6 +86066,7 @@ typedef struct { * 0b1..Temperature tamper is enabled. */ #define SNVS_LPTDCR_TT_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_TT_EN_SHIFT)) & SNVS_LPTDCR_TT_EN_MASK) + #define SNVS_LPTDCR_VT_EN_MASK (0x40U) #define SNVS_LPTDCR_VT_EN_SHIFT (6U) /*! VT_EN @@ -76981,6 +86074,7 @@ typedef struct { * 0b1..Voltage tamper is enabled. */ #define SNVS_LPTDCR_VT_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_VT_EN_SHIFT)) & SNVS_LPTDCR_VT_EN_MASK) + #define SNVS_LPTDCR_WMT1_EN_MASK (0x80U) #define SNVS_LPTDCR_WMT1_EN_SHIFT (7U) /*! WMT1_EN @@ -76988,6 +86082,7 @@ typedef struct { * 0b1..Wire-mesh tamper 1 is enabled. */ #define SNVS_LPTDCR_WMT1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_WMT1_EN_SHIFT)) & SNVS_LPTDCR_WMT1_EN_MASK) + #define SNVS_LPTDCR_WMT2_EN_MASK (0x100U) #define SNVS_LPTDCR_WMT2_EN_SHIFT (8U) /*! WMT2_EN @@ -76995,6 +86090,7 @@ typedef struct { * 0b1..Wire-mesh tamper 2 is enabled. */ #define SNVS_LPTDCR_WMT2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_WMT2_EN_SHIFT)) & SNVS_LPTDCR_WMT2_EN_MASK) + #define SNVS_LPTDCR_ET1_EN_MASK (0x200U) #define SNVS_LPTDCR_ET1_EN_SHIFT (9U) /*! ET1_EN @@ -77002,6 +86098,7 @@ typedef struct { * 0b1..External tamper 1 is enabled. */ #define SNVS_LPTDCR_ET1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK) + #define SNVS_LPTDCR_ET2_EN_MASK (0x400U) #define SNVS_LPTDCR_ET2_EN_SHIFT (10U) /*! ET2_EN @@ -77009,6 +86106,7 @@ typedef struct { * 0b1..External tamper 2 is enabled. */ #define SNVS_LPTDCR_ET2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET2_EN_SHIFT)) & SNVS_LPTDCR_ET2_EN_MASK) + #define SNVS_LPTDCR_ET1P_MASK (0x800U) #define SNVS_LPTDCR_ET1P_SHIFT (11U) /*! ET1P @@ -77016,6 +86114,7 @@ typedef struct { * 0b1..External tamper 1 is active high. */ #define SNVS_LPTDCR_ET1P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK) + #define SNVS_LPTDCR_ET2P_MASK (0x1000U) #define SNVS_LPTDCR_ET2P_SHIFT (12U) /*! ET2P @@ -77023,21 +86122,27 @@ typedef struct { * 0b1..External tamper 2 is active high. */ #define SNVS_LPTDCR_ET2P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET2P_SHIFT)) & SNVS_LPTDCR_ET2P_MASK) + #define SNVS_LPTDCR_PFD_OBSERV_MASK (0x4000U) #define SNVS_LPTDCR_PFD_OBSERV_SHIFT (14U) #define SNVS_LPTDCR_PFD_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK) + #define SNVS_LPTDCR_POR_OBSERV_MASK (0x8000U) #define SNVS_LPTDCR_POR_OBSERV_SHIFT (15U) #define SNVS_LPTDCR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK) + #define SNVS_LPTDCR_LTDC_MASK (0x70000U) #define SNVS_LPTDCR_LTDC_SHIFT (16U) #define SNVS_LPTDCR_LTDC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_LTDC_SHIFT)) & SNVS_LPTDCR_LTDC_MASK) + #define SNVS_LPTDCR_HTDC_MASK (0x700000U) #define SNVS_LPTDCR_HTDC_SHIFT (20U) #define SNVS_LPTDCR_HTDC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_HTDC_SHIFT)) & SNVS_LPTDCR_HTDC_MASK) + #define SNVS_LPTDCR_VRC_MASK (0x7000000U) #define SNVS_LPTDCR_VRC_SHIFT (24U) #define SNVS_LPTDCR_VRC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_VRC_SHIFT)) & SNVS_LPTDCR_VRC_MASK) + #define SNVS_LPTDCR_OSCB_MASK (0x10000000U) #define SNVS_LPTDCR_OSCB_SHIFT (28U) /*! OSCB @@ -77049,6 +86154,7 @@ typedef struct { /*! @name LPSR - SNVS_LP Status Register */ /*! @{ */ + #define SNVS_LPSR_LPTA_MASK (0x1U) #define SNVS_LPSR_LPTA_SHIFT (0U) /*! LPTA @@ -77056,6 +86162,7 @@ typedef struct { * 0b1..A time alarm interrupt occurred. */ #define SNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK) + #define SNVS_LPSR_SRTCR_MASK (0x2U) #define SNVS_LPSR_SRTCR_SHIFT (1U) /*! SRTCR @@ -77063,6 +86170,7 @@ typedef struct { * 0b1..SRTC has reached its maximum value. */ #define SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK) + #define SNVS_LPSR_MCR_MASK (0x4U) #define SNVS_LPSR_MCR_SHIFT (2U) /*! MCR @@ -77070,9 +86178,15 @@ typedef struct { * 0b1..MC has reached its maximum value. */ #define SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK) -#define SNVS_LPSR_PGD_MASK (0x8U) -#define SNVS_LPSR_PGD_SHIFT (3U) -#define SNVS_LPSR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_PGD_SHIFT)) & SNVS_LPSR_PGD_MASK) + +#define SNVS_LPSR_LVD_MASK (0x8U) +#define SNVS_LPSR_LVD_SHIFT (3U) +/*! LVD + * 0b0..No low voltage event detected. + * 0b1..Low voltage event is detected. + */ +#define SNVS_LPSR_LVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LVD_SHIFT)) & SNVS_LPSR_LVD_MASK) + #define SNVS_LPSR_CTD_MASK (0x10U) #define SNVS_LPSR_CTD_SHIFT (4U) /*! CTD @@ -77080,6 +86194,7 @@ typedef struct { * 0b1..Clock tamper is detected. */ #define SNVS_LPSR_CTD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_CTD_SHIFT)) & SNVS_LPSR_CTD_MASK) + #define SNVS_LPSR_TTD_MASK (0x20U) #define SNVS_LPSR_TTD_SHIFT (5U) /*! TTD @@ -77087,6 +86202,7 @@ typedef struct { * 0b1..Temperature tamper is detected. */ #define SNVS_LPSR_TTD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_TTD_SHIFT)) & SNVS_LPSR_TTD_MASK) + #define SNVS_LPSR_VTD_MASK (0x40U) #define SNVS_LPSR_VTD_SHIFT (6U) /*! VTD @@ -77094,6 +86210,7 @@ typedef struct { * 0b1..Voltage tampering detected. */ #define SNVS_LPSR_VTD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_VTD_SHIFT)) & SNVS_LPSR_VTD_MASK) + #define SNVS_LPSR_WMT1D_MASK (0x80U) #define SNVS_LPSR_WMT1D_SHIFT (7U) /*! WMT1D @@ -77101,6 +86218,7 @@ typedef struct { * 0b1..Wire-mesh tampering 1 detected. */ #define SNVS_LPSR_WMT1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_WMT1D_SHIFT)) & SNVS_LPSR_WMT1D_MASK) + #define SNVS_LPSR_WMT2D_MASK (0x100U) #define SNVS_LPSR_WMT2D_SHIFT (8U) /*! WMT2D @@ -77108,6 +86226,7 @@ typedef struct { * 0b1..Wire-mesh tampering 2 detected. */ #define SNVS_LPSR_WMT2D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_WMT2D_SHIFT)) & SNVS_LPSR_WMT2D_MASK) + #define SNVS_LPSR_ET1D_MASK (0x200U) #define SNVS_LPSR_ET1D_SHIFT (9U) /*! ET1D @@ -77115,6 +86234,7 @@ typedef struct { * 0b1..External tampering 1 detected. */ #define SNVS_LPSR_ET1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK) + #define SNVS_LPSR_ET2D_MASK (0x400U) #define SNVS_LPSR_ET2D_SHIFT (10U) /*! ET2D @@ -77122,6 +86242,7 @@ typedef struct { * 0b1..External tampering 2 detected. */ #define SNVS_LPSR_ET2D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET2D_SHIFT)) & SNVS_LPSR_ET2D_MASK) + #define SNVS_LPSR_ESVD_MASK (0x10000U) #define SNVS_LPSR_ESVD_SHIFT (16U) /*! ESVD @@ -77129,6 +86250,7 @@ typedef struct { * 0b1..External security violation is detected. */ #define SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK) + #define SNVS_LPSR_EO_MASK (0x20000U) #define SNVS_LPSR_EO_SHIFT (17U) /*! EO @@ -77136,6 +86258,7 @@ typedef struct { * 0b1..Emergency off was detected. */ #define SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK) + #define SNVS_LPSR_SPOF_MASK (0x40000U) #define SNVS_LPSR_SPOF_SHIFT (18U) /*! SPOF @@ -77143,6 +86266,7 @@ typedef struct { * 0b1..Set Power Off was detected. */ #define SNVS_LPSR_SPOF(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPOF_SHIFT)) & SNVS_LPSR_SPOF_MASK) + #define SNVS_LPSR_LPNS_MASK (0x40000000U) #define SNVS_LPSR_LPNS_SHIFT (30U) /*! LPNS @@ -77150,6 +86274,7 @@ typedef struct { * 0b1..LP section was programmed in the non-secure state. */ #define SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK) + #define SNVS_LPSR_LPS_MASK (0x80000000U) #define SNVS_LPSR_LPS_SHIFT (31U) /*! LPS @@ -77161,6 +86286,7 @@ typedef struct { /*! @name LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register */ /*! @{ */ + #define SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU) #define SNVS_LPSRTCMR_SRTC_SHIFT (0U) #define SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK) @@ -77168,6 +86294,7 @@ typedef struct { /*! @name LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register */ /*! @{ */ + #define SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU) #define SNVS_LPSRTCLR_SRTC_SHIFT (0U) #define SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK) @@ -77175,6 +86302,7 @@ typedef struct { /*! @name LPTAR - SNVS_LP Time Alarm Register */ /*! @{ */ + #define SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU) #define SNVS_LPTAR_LPTA_SHIFT (0U) #define SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK) @@ -77182,9 +86310,11 @@ typedef struct { /*! @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */ /*! @{ */ + #define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU) #define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U) #define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK) + #define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U) #define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U) #define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK) @@ -77192,20 +86322,23 @@ typedef struct { /*! @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */ /*! @{ */ + #define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU) #define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U) #define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK) /*! @} */ -/*! @name LPPGDR - SNVS_LP Power Glitch Detector Register */ +/*! @name LPLVDR - SNVS_LP Digital Low-Voltage Detector Register */ /*! @{ */ -#define SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU) -#define SNVS_LPPGDR_PGD_SHIFT (0U) -#define SNVS_LPPGDR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK) + +#define SNVS_LPLVDR_LVD_MASK (0xFFFFFFFFU) +#define SNVS_LPLVDR_LVD_SHIFT (0U) +#define SNVS_LPLVDR_LVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLVDR_LVD_SHIFT)) & SNVS_LPLVDR_LVD_MASK) /*! @} */ /*! @name LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias) */ /*! @{ */ + #define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU) #define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U) #define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK) @@ -77213,6 +86346,7 @@ typedef struct { /*! @name LPZMKR - SNVS_LP Zeroizable Master Key Register */ /*! @{ */ + #define SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU) #define SNVS_LPZMKR_ZMK_SHIFT (0U) #define SNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK) @@ -77223,6 +86357,7 @@ typedef struct { /*! @name LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3 */ /*! @{ */ + #define SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU) #define SNVS_LPGPR_ALIAS_GPR_SHIFT (0U) #define SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK) @@ -77233,6 +86368,7 @@ typedef struct { /*! @name LPTDC2R - SNVS_LP Tamper Detectors Config 2 Register */ /*! @{ */ + #define SNVS_LPTDC2R_ET3_EN_MASK (0x1U) #define SNVS_LPTDC2R_ET3_EN_SHIFT (0U) /*! ET3_EN @@ -77240,6 +86376,7 @@ typedef struct { * 0b1..External tamper 3 is enabled. */ #define SNVS_LPTDC2R_ET3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET3_EN_SHIFT)) & SNVS_LPTDC2R_ET3_EN_MASK) + #define SNVS_LPTDC2R_ET4_EN_MASK (0x2U) #define SNVS_LPTDC2R_ET4_EN_SHIFT (1U) /*! ET4_EN @@ -77247,6 +86384,7 @@ typedef struct { * 0b1..External tamper 4 is enabled. */ #define SNVS_LPTDC2R_ET4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET4_EN_SHIFT)) & SNVS_LPTDC2R_ET4_EN_MASK) + #define SNVS_LPTDC2R_ET5_EN_MASK (0x4U) #define SNVS_LPTDC2R_ET5_EN_SHIFT (2U) /*! ET5_EN @@ -77254,6 +86392,7 @@ typedef struct { * 0b1..External tamper 5 is enabled. */ #define SNVS_LPTDC2R_ET5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET5_EN_SHIFT)) & SNVS_LPTDC2R_ET5_EN_MASK) + #define SNVS_LPTDC2R_ET6_EN_MASK (0x8U) #define SNVS_LPTDC2R_ET6_EN_SHIFT (3U) /*! ET6_EN @@ -77261,6 +86400,7 @@ typedef struct { * 0b1..External tamper 6 is enabled. */ #define SNVS_LPTDC2R_ET6_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET6_EN_SHIFT)) & SNVS_LPTDC2R_ET6_EN_MASK) + #define SNVS_LPTDC2R_ET7_EN_MASK (0x10U) #define SNVS_LPTDC2R_ET7_EN_SHIFT (4U) /*! ET7_EN @@ -77268,6 +86408,7 @@ typedef struct { * 0b1..External tamper 7 is enabled. */ #define SNVS_LPTDC2R_ET7_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET7_EN_SHIFT)) & SNVS_LPTDC2R_ET7_EN_MASK) + #define SNVS_LPTDC2R_ET8_EN_MASK (0x20U) #define SNVS_LPTDC2R_ET8_EN_SHIFT (5U) /*! ET8_EN @@ -77275,6 +86416,7 @@ typedef struct { * 0b1..External tamper 8 is enabled. */ #define SNVS_LPTDC2R_ET8_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET8_EN_SHIFT)) & SNVS_LPTDC2R_ET8_EN_MASK) + #define SNVS_LPTDC2R_ET9_EN_MASK (0x40U) #define SNVS_LPTDC2R_ET9_EN_SHIFT (6U) /*! ET9_EN @@ -77282,6 +86424,7 @@ typedef struct { * 0b1..External tamper 9 is enabled. */ #define SNVS_LPTDC2R_ET9_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET9_EN_SHIFT)) & SNVS_LPTDC2R_ET9_EN_MASK) + #define SNVS_LPTDC2R_ET10_EN_MASK (0x80U) #define SNVS_LPTDC2R_ET10_EN_SHIFT (7U) /*! ET10_EN @@ -77289,6 +86432,7 @@ typedef struct { * 0b1..External tamper 10 is enabled. */ #define SNVS_LPTDC2R_ET10_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET10_EN_SHIFT)) & SNVS_LPTDC2R_ET10_EN_MASK) + #define SNVS_LPTDC2R_ET3P_MASK (0x10000U) #define SNVS_LPTDC2R_ET3P_SHIFT (16U) /*! ET3P @@ -77296,6 +86440,7 @@ typedef struct { * 0b1..External tamper 3 active high. */ #define SNVS_LPTDC2R_ET3P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET3P_SHIFT)) & SNVS_LPTDC2R_ET3P_MASK) + #define SNVS_LPTDC2R_ET4P_MASK (0x20000U) #define SNVS_LPTDC2R_ET4P_SHIFT (17U) /*! ET4P @@ -77303,6 +86448,7 @@ typedef struct { * 0b1..External tamper 4 is active high. */ #define SNVS_LPTDC2R_ET4P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET4P_SHIFT)) & SNVS_LPTDC2R_ET4P_MASK) + #define SNVS_LPTDC2R_ET5P_MASK (0x40000U) #define SNVS_LPTDC2R_ET5P_SHIFT (18U) /*! ET5P @@ -77310,6 +86456,7 @@ typedef struct { * 0b1..External tamper 5 is active high. */ #define SNVS_LPTDC2R_ET5P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET5P_SHIFT)) & SNVS_LPTDC2R_ET5P_MASK) + #define SNVS_LPTDC2R_ET6P_MASK (0x80000U) #define SNVS_LPTDC2R_ET6P_SHIFT (19U) /*! ET6P @@ -77317,6 +86464,7 @@ typedef struct { * 0b1..External tamper 6 is active high. */ #define SNVS_LPTDC2R_ET6P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET6P_SHIFT)) & SNVS_LPTDC2R_ET6P_MASK) + #define SNVS_LPTDC2R_ET7P_MASK (0x100000U) #define SNVS_LPTDC2R_ET7P_SHIFT (20U) /*! ET7P @@ -77324,6 +86472,7 @@ typedef struct { * 0b1..External tamper 7 is active high. */ #define SNVS_LPTDC2R_ET7P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET7P_SHIFT)) & SNVS_LPTDC2R_ET7P_MASK) + #define SNVS_LPTDC2R_ET8P_MASK (0x200000U) #define SNVS_LPTDC2R_ET8P_SHIFT (21U) /*! ET8P @@ -77331,6 +86480,7 @@ typedef struct { * 0b1..External tamper 8 is active high. */ #define SNVS_LPTDC2R_ET8P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET8P_SHIFT)) & SNVS_LPTDC2R_ET8P_MASK) + #define SNVS_LPTDC2R_ET9P_MASK (0x400000U) #define SNVS_LPTDC2R_ET9P_SHIFT (22U) /*! ET9P @@ -77338,6 +86488,7 @@ typedef struct { * 0b1..External tamper 9 is active high. */ #define SNVS_LPTDC2R_ET9P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET9P_SHIFT)) & SNVS_LPTDC2R_ET9P_MASK) + #define SNVS_LPTDC2R_ET10P_MASK (0x800000U) #define SNVS_LPTDC2R_ET10P_SHIFT (23U) /*! ET10P @@ -77349,6 +86500,7 @@ typedef struct { /*! @name LPTDSR - SNVS_LP Tamper Detectors Status Register */ /*! @{ */ + #define SNVS_LPTDSR_ET3D_MASK (0x1U) #define SNVS_LPTDSR_ET3D_SHIFT (0U) /*! ET3D @@ -77356,6 +86508,7 @@ typedef struct { * 0b1..External tamper 3 is detected. */ #define SNVS_LPTDSR_ET3D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET3D_SHIFT)) & SNVS_LPTDSR_ET3D_MASK) + #define SNVS_LPTDSR_ET4D_MASK (0x2U) #define SNVS_LPTDSR_ET4D_SHIFT (1U) /*! ET4D @@ -77363,6 +86516,7 @@ typedef struct { * 0b1..External tamper 4 is detected. */ #define SNVS_LPTDSR_ET4D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET4D_SHIFT)) & SNVS_LPTDSR_ET4D_MASK) + #define SNVS_LPTDSR_ET5D_MASK (0x4U) #define SNVS_LPTDSR_ET5D_SHIFT (2U) /*! ET5D @@ -77370,6 +86524,7 @@ typedef struct { * 0b1..External tamper 5 is detected. */ #define SNVS_LPTDSR_ET5D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET5D_SHIFT)) & SNVS_LPTDSR_ET5D_MASK) + #define SNVS_LPTDSR_ET6D_MASK (0x8U) #define SNVS_LPTDSR_ET6D_SHIFT (3U) /*! ET6D @@ -77377,6 +86532,7 @@ typedef struct { * 0b1..External tamper 6 is detected. */ #define SNVS_LPTDSR_ET6D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET6D_SHIFT)) & SNVS_LPTDSR_ET6D_MASK) + #define SNVS_LPTDSR_ET7D_MASK (0x10U) #define SNVS_LPTDSR_ET7D_SHIFT (4U) /*! ET7D @@ -77384,6 +86540,7 @@ typedef struct { * 0b1..External tamper 7 is detected. */ #define SNVS_LPTDSR_ET7D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET7D_SHIFT)) & SNVS_LPTDSR_ET7D_MASK) + #define SNVS_LPTDSR_ET8D_MASK (0x20U) #define SNVS_LPTDSR_ET8D_SHIFT (5U) /*! ET8D @@ -77391,6 +86548,7 @@ typedef struct { * 0b1..External tamper 8 is detected. */ #define SNVS_LPTDSR_ET8D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET8D_SHIFT)) & SNVS_LPTDSR_ET8D_MASK) + #define SNVS_LPTDSR_ET9D_MASK (0x40U) #define SNVS_LPTDSR_ET9D_SHIFT (6U) /*! ET9D @@ -77398,6 +86556,7 @@ typedef struct { * 0b1..External tamper 9 is detected. */ #define SNVS_LPTDSR_ET9D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET9D_SHIFT)) & SNVS_LPTDSR_ET9D_MASK) + #define SNVS_LPTDSR_ET10D_MASK (0x80U) #define SNVS_LPTDSR_ET10D_SHIFT (7U) /*! ET10D @@ -77409,9 +86568,11 @@ typedef struct { /*! @name LPTGF1CR - SNVS_LP Tamper Glitch Filter 1 Configuration Register */ /*! @{ */ + #define SNVS_LPTGF1CR_ETGF3_MASK (0x7FU) #define SNVS_LPTGF1CR_ETGF3_SHIFT (0U) #define SNVS_LPTGF1CR_ETGF3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF3_SHIFT)) & SNVS_LPTGF1CR_ETGF3_MASK) + #define SNVS_LPTGF1CR_ETGF3_EN_MASK (0x80U) #define SNVS_LPTGF1CR_ETGF3_EN_SHIFT (7U) /*! ETGF3_EN @@ -77419,9 +86580,11 @@ typedef struct { * 0b1..External tamper glitch filter 3 is enabled. */ #define SNVS_LPTGF1CR_ETGF3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF3_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF3_EN_MASK) + #define SNVS_LPTGF1CR_ETGF4_MASK (0x7F00U) #define SNVS_LPTGF1CR_ETGF4_SHIFT (8U) #define SNVS_LPTGF1CR_ETGF4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF4_SHIFT)) & SNVS_LPTGF1CR_ETGF4_MASK) + #define SNVS_LPTGF1CR_ETGF4_EN_MASK (0x8000U) #define SNVS_LPTGF1CR_ETGF4_EN_SHIFT (15U) /*! ETGF4_EN @@ -77429,9 +86592,11 @@ typedef struct { * 0b1..External tamper glitch filter 4 is enabled. */ #define SNVS_LPTGF1CR_ETGF4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF4_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF4_EN_MASK) + #define SNVS_LPTGF1CR_ETGF5_MASK (0x7F0000U) #define SNVS_LPTGF1CR_ETGF5_SHIFT (16U) #define SNVS_LPTGF1CR_ETGF5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF5_SHIFT)) & SNVS_LPTGF1CR_ETGF5_MASK) + #define SNVS_LPTGF1CR_ETGF5_EN_MASK (0x800000U) #define SNVS_LPTGF1CR_ETGF5_EN_SHIFT (23U) /*! ETGF5_EN @@ -77439,9 +86604,11 @@ typedef struct { * 0b1..External tamper glitch filter 5 is enabled. */ #define SNVS_LPTGF1CR_ETGF5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF5_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF5_EN_MASK) + #define SNVS_LPTGF1CR_ETGF6_MASK (0x7F000000U) #define SNVS_LPTGF1CR_ETGF6_SHIFT (24U) #define SNVS_LPTGF1CR_ETGF6(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF6_SHIFT)) & SNVS_LPTGF1CR_ETGF6_MASK) + #define SNVS_LPTGF1CR_ETGF6_EN_MASK (0x80000000U) #define SNVS_LPTGF1CR_ETGF6_EN_SHIFT (31U) /*! ETGF6_EN @@ -77453,9 +86620,11 @@ typedef struct { /*! @name LPTGF2CR - SNVS_LP Tamper Glitch Filter 2 Configuration Register */ /*! @{ */ + #define SNVS_LPTGF2CR_ETGF7_MASK (0x7FU) #define SNVS_LPTGF2CR_ETGF7_SHIFT (0U) #define SNVS_LPTGF2CR_ETGF7(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF7_SHIFT)) & SNVS_LPTGF2CR_ETGF7_MASK) + #define SNVS_LPTGF2CR_ETGF7_EN_MASK (0x80U) #define SNVS_LPTGF2CR_ETGF7_EN_SHIFT (7U) /*! ETGF7_EN @@ -77463,9 +86632,11 @@ typedef struct { * 0b1..External tamper glitch filter 7 is enabled. */ #define SNVS_LPTGF2CR_ETGF7_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF7_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF7_EN_MASK) + #define SNVS_LPTGF2CR_ETGF8_MASK (0x7F00U) #define SNVS_LPTGF2CR_ETGF8_SHIFT (8U) #define SNVS_LPTGF2CR_ETGF8(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF8_SHIFT)) & SNVS_LPTGF2CR_ETGF8_MASK) + #define SNVS_LPTGF2CR_ETGF8_EN_MASK (0x8000U) #define SNVS_LPTGF2CR_ETGF8_EN_SHIFT (15U) /*! ETGF8_EN @@ -77473,9 +86644,11 @@ typedef struct { * 0b1..External tamper glitch filter 8 is enabled. */ #define SNVS_LPTGF2CR_ETGF8_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF8_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF8_EN_MASK) + #define SNVS_LPTGF2CR_ETGF9_MASK (0x7F0000U) #define SNVS_LPTGF2CR_ETGF9_SHIFT (16U) #define SNVS_LPTGF2CR_ETGF9(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF9_SHIFT)) & SNVS_LPTGF2CR_ETGF9_MASK) + #define SNVS_LPTGF2CR_ETGF9_EN_MASK (0x800000U) #define SNVS_LPTGF2CR_ETGF9_EN_SHIFT (23U) /*! ETGF9_EN @@ -77483,9 +86656,11 @@ typedef struct { * 0b1..External tamper glitch filter 9 is enabled. */ #define SNVS_LPTGF2CR_ETGF9_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF9_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF9_EN_MASK) + #define SNVS_LPTGF2CR_ETGF10_MASK (0x7F000000U) #define SNVS_LPTGF2CR_ETGF10_SHIFT (24U) #define SNVS_LPTGF2CR_ETGF10(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF10_SHIFT)) & SNVS_LPTGF2CR_ETGF10_MASK) + #define SNVS_LPTGF2CR_ETGF10_EN_MASK (0x80000000U) #define SNVS_LPTGF2CR_ETGF10_EN_SHIFT (31U) /*! ETGF10_EN @@ -77497,9 +86672,11 @@ typedef struct { /*! @name LPATCR - SNVS_LP Active Tamper 1 Configuration Register..SNVS_LP Active Tamper 5 Configuration Register */ /*! @{ */ + #define SNVS_LPATCR_Seed_MASK (0xFFFFU) #define SNVS_LPATCR_Seed_SHIFT (0U) #define SNVS_LPATCR_Seed(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCR_Seed_SHIFT)) & SNVS_LPATCR_Seed_MASK) + #define SNVS_LPATCR_Polynomial_MASK (0xFFFF0000U) #define SNVS_LPATCR_Polynomial_SHIFT (16U) #define SNVS_LPATCR_Polynomial(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCR_Polynomial_SHIFT)) & SNVS_LPATCR_Polynomial_MASK) @@ -77510,6 +86687,7 @@ typedef struct { /*! @name LPATCTLR - SNVS_LP Active Tamper Control Register */ /*! @{ */ + #define SNVS_LPATCTLR_AT1_EN_MASK (0x1U) #define SNVS_LPATCTLR_AT1_EN_SHIFT (0U) /*! AT1_EN @@ -77517,6 +86695,7 @@ typedef struct { * 0b1..Active Tamper 1 is enabled. */ #define SNVS_LPATCTLR_AT1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT1_EN_SHIFT)) & SNVS_LPATCTLR_AT1_EN_MASK) + #define SNVS_LPATCTLR_AT2_EN_MASK (0x2U) #define SNVS_LPATCTLR_AT2_EN_SHIFT (1U) /*! AT2_EN @@ -77524,6 +86703,7 @@ typedef struct { * 0b1..Active Tamper 2 is enabled. */ #define SNVS_LPATCTLR_AT2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT2_EN_SHIFT)) & SNVS_LPATCTLR_AT2_EN_MASK) + #define SNVS_LPATCTLR_AT3_EN_MASK (0x4U) #define SNVS_LPATCTLR_AT3_EN_SHIFT (2U) /*! AT3_EN @@ -77531,6 +86711,7 @@ typedef struct { * 0b1..Active Tamper 3 is enabled. */ #define SNVS_LPATCTLR_AT3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT3_EN_SHIFT)) & SNVS_LPATCTLR_AT3_EN_MASK) + #define SNVS_LPATCTLR_AT4_EN_MASK (0x8U) #define SNVS_LPATCTLR_AT4_EN_SHIFT (3U) /*! AT4_EN @@ -77538,6 +86719,7 @@ typedef struct { * 0b1..Active Tamper 4 is enabled. */ #define SNVS_LPATCTLR_AT4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT4_EN_SHIFT)) & SNVS_LPATCTLR_AT4_EN_MASK) + #define SNVS_LPATCTLR_AT5_EN_MASK (0x10U) #define SNVS_LPATCTLR_AT5_EN_SHIFT (4U) /*! AT5_EN @@ -77545,6 +86727,7 @@ typedef struct { * 0b1..Active Tamper 5 is enabled. */ #define SNVS_LPATCTLR_AT5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT5_EN_SHIFT)) & SNVS_LPATCTLR_AT5_EN_MASK) + #define SNVS_LPATCTLR_AT1_PAD_EN_MASK (0x10000U) #define SNVS_LPATCTLR_AT1_PAD_EN_SHIFT (16U) /*! AT1_PAD_EN @@ -77552,6 +86735,7 @@ typedef struct { * 0b1..Active Tamper 1 is enabled. */ #define SNVS_LPATCTLR_AT1_PAD_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT1_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT1_PAD_EN_MASK) + #define SNVS_LPATCTLR_AT2_PAD_EN_MASK (0x20000U) #define SNVS_LPATCTLR_AT2_PAD_EN_SHIFT (17U) /*! AT2_PAD_EN @@ -77559,6 +86743,7 @@ typedef struct { * 0b1..Active Tamper 2 is enabled. */ #define SNVS_LPATCTLR_AT2_PAD_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT2_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT2_PAD_EN_MASK) + #define SNVS_LPATCTLR_AT3_PAD_EN_MASK (0x40000U) #define SNVS_LPATCTLR_AT3_PAD_EN_SHIFT (18U) /*! AT3_PAD_EN @@ -77566,6 +86751,7 @@ typedef struct { * 0b1..Active Tamper 3 is enabled */ #define SNVS_LPATCTLR_AT3_PAD_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT3_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT3_PAD_EN_MASK) + #define SNVS_LPATCTLR_AT4_PAD_EN_MASK (0x80000U) #define SNVS_LPATCTLR_AT4_PAD_EN_SHIFT (19U) /*! AT4_PAD_EN @@ -77573,6 +86759,7 @@ typedef struct { * 0b1..Active Tamper 4 is enabled. */ #define SNVS_LPATCTLR_AT4_PAD_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT4_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT4_PAD_EN_MASK) + #define SNVS_LPATCTLR_AT5_PAD_EN_MASK (0x100000U) #define SNVS_LPATCTLR_AT5_PAD_EN_SHIFT (20U) /*! AT5_PAD_EN @@ -77584,18 +86771,23 @@ typedef struct { /*! @name LPATCLKR - SNVS_LP Active Tamper Clock Control Register */ /*! @{ */ + #define SNVS_LPATCLKR_AT1_CLK_CTL_MASK (0x3U) #define SNVS_LPATCLKR_AT1_CLK_CTL_SHIFT (0U) #define SNVS_LPATCLKR_AT1_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT1_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT1_CLK_CTL_MASK) + #define SNVS_LPATCLKR_AT2_CLK_CTL_MASK (0x30U) #define SNVS_LPATCLKR_AT2_CLK_CTL_SHIFT (4U) #define SNVS_LPATCLKR_AT2_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT2_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT2_CLK_CTL_MASK) + #define SNVS_LPATCLKR_AT3_CLK_CTL_MASK (0x300U) #define SNVS_LPATCLKR_AT3_CLK_CTL_SHIFT (8U) #define SNVS_LPATCLKR_AT3_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT3_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT3_CLK_CTL_MASK) + #define SNVS_LPATCLKR_AT4_CLK_CTL_MASK (0x3000U) #define SNVS_LPATCLKR_AT4_CLK_CTL_SHIFT (12U) #define SNVS_LPATCLKR_AT4_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT4_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT4_CLK_CTL_MASK) + #define SNVS_LPATCLKR_AT5_CLK_CTL_MASK (0x30000U) #define SNVS_LPATCLKR_AT5_CLK_CTL_SHIFT (16U) #define SNVS_LPATCLKR_AT5_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT5_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT5_CLK_CTL_MASK) @@ -77603,27 +86795,35 @@ typedef struct { /*! @name LPATRC1R - SNVS_LP Active Tamper Routing Control 1 Register */ /*! @{ */ + #define SNVS_LPATRC1R_ET1RCTL_MASK (0x7U) #define SNVS_LPATRC1R_ET1RCTL_SHIFT (0U) #define SNVS_LPATRC1R_ET1RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET1RCTL_SHIFT)) & SNVS_LPATRC1R_ET1RCTL_MASK) + #define SNVS_LPATRC1R_ET2RCTL_MASK (0x70U) #define SNVS_LPATRC1R_ET2RCTL_SHIFT (4U) #define SNVS_LPATRC1R_ET2RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET2RCTL_SHIFT)) & SNVS_LPATRC1R_ET2RCTL_MASK) + #define SNVS_LPATRC1R_ET3RCTL_MASK (0x700U) #define SNVS_LPATRC1R_ET3RCTL_SHIFT (8U) #define SNVS_LPATRC1R_ET3RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET3RCTL_SHIFT)) & SNVS_LPATRC1R_ET3RCTL_MASK) + #define SNVS_LPATRC1R_ET4RCTL_MASK (0x7000U) #define SNVS_LPATRC1R_ET4RCTL_SHIFT (12U) #define SNVS_LPATRC1R_ET4RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET4RCTL_SHIFT)) & SNVS_LPATRC1R_ET4RCTL_MASK) + #define SNVS_LPATRC1R_ET5RCTL_MASK (0x70000U) #define SNVS_LPATRC1R_ET5RCTL_SHIFT (16U) #define SNVS_LPATRC1R_ET5RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET5RCTL_SHIFT)) & SNVS_LPATRC1R_ET5RCTL_MASK) + #define SNVS_LPATRC1R_ET6RCTL_MASK (0x700000U) #define SNVS_LPATRC1R_ET6RCTL_SHIFT (20U) #define SNVS_LPATRC1R_ET6RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET6RCTL_SHIFT)) & SNVS_LPATRC1R_ET6RCTL_MASK) + #define SNVS_LPATRC1R_ET7RCTL_MASK (0x7000000U) #define SNVS_LPATRC1R_ET7RCTL_SHIFT (24U) #define SNVS_LPATRC1R_ET7RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET7RCTL_SHIFT)) & SNVS_LPATRC1R_ET7RCTL_MASK) + #define SNVS_LPATRC1R_ET8RCTL_MASK (0x70000000U) #define SNVS_LPATRC1R_ET8RCTL_SHIFT (28U) #define SNVS_LPATRC1R_ET8RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET8RCTL_SHIFT)) & SNVS_LPATRC1R_ET8RCTL_MASK) @@ -77631,9 +86831,11 @@ typedef struct { /*! @name LPATRC2R - SNVS_LP Active Tamper Routing Control 2 Register */ /*! @{ */ + #define SNVS_LPATRC2R_ET9RCTL_MASK (0x7U) #define SNVS_LPATRC2R_ET9RCTL_SHIFT (0U) #define SNVS_LPATRC2R_ET9RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC2R_ET9RCTL_SHIFT)) & SNVS_LPATRC2R_ET9RCTL_MASK) + #define SNVS_LPATRC2R_ET10RCTL_MASK (0x70U) #define SNVS_LPATRC2R_ET10RCTL_SHIFT (4U) #define SNVS_LPATRC2R_ET10RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC2R_ET10RCTL_SHIFT)) & SNVS_LPATRC2R_ET10RCTL_MASK) @@ -77641,6 +86843,7 @@ typedef struct { /*! @name LPGPR - SNVS_LP General Purpose Registers 0 .. 3 */ /*! @{ */ + #define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU) #define SNVS_LPGPR_GPR_SHIFT (0U) #define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK) @@ -77651,12 +86854,15 @@ typedef struct { /*! @name HPVIDR1 - SNVS_HP Version ID Register 1 */ /*! @{ */ + #define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU) #define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U) #define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK) + #define SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U) #define SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U) #define SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK) + #define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U) #define SNVS_HPVIDR1_IP_ID_SHIFT (16U) #define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK) @@ -77664,15 +86870,11 @@ typedef struct { /*! @name HPVIDR2 - SNVS_HP Version ID Register 2 */ /*! @{ */ -#define SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU) -#define SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U) -#define SNVS_HPVIDR2_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK) + #define SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U) #define SNVS_HPVIDR2_ECO_REV_SHIFT (8U) #define SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK) -#define SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U) -#define SNVS_HPVIDR2_INTG_OPT_SHIFT (16U) -#define SNVS_HPVIDR2_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK) + #define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U) #define SNVS_HPVIDR2_IP_ERA_SHIFT (24U) #define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK) @@ -77694,9 +86896,9 @@ typedef struct { /** Array initializer of SNVS peripheral base pointers */ #define SNVS_BASE_PTRS { SNVS } /** Interrupt vectors for the SNVS peripheral type */ -#define SNVS_IRQS { SNVS_LP_WRAPPER_IRQn } -#define SNVS_CONSOLIDATED_IRQS { SNVS_HP_WRAPPER_IRQn } -#define SNVS_SECURITY_IRQS { SNVS_HP_WRAPPER_TZ_IRQn } +#define SNVS_IRQS { SNVS_PULSE_EVENT_IRQn } +#define SNVS_CONSOLIDATED_IRQS { SNVS_HP_NON_TZ_IRQn } +#define SNVS_SECURITY_IRQS { SNVS_HP_TZ_IRQn } /*! * @} @@ -77749,113 +86951,131 @@ typedef struct { /*! @name SCR - SPDIF Configuration Register */ /*! @{ */ + #define SPDIF_SCR_USRC_SEL_MASK (0x3U) #define SPDIF_SCR_USRC_SEL_SHIFT (0U) -/*! USrc_Sel +/*! USrc_Sel - USrc_Sel * 0b00..No embedded U channel * 0b01..U channel from SPDIF receive block (CD mode) * 0b10..Reserved * 0b11..U channel from on chip transmitter */ #define SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK) + #define SPDIF_SCR_TXSEL_MASK (0x1CU) #define SPDIF_SCR_TXSEL_SHIFT (2U) -/*! TxSel +/*! TxSel - TxSel * 0b000..Off and output 0 * 0b001..Feed-through SPDIFIN * 0b101..Tx Normal operation */ #define SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK) + #define SPDIF_SCR_VALCTRL_MASK (0x20U) #define SPDIF_SCR_VALCTRL_SHIFT (5U) -/*! ValCtrl +/*! ValCtrl - ValCtrl * 0b0..Outgoing Validity always set * 0b1..Outgoing Validity always clear */ #define SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK) -#define SPDIF_SCR_INPUT_SOURCESELECTOR_MASK (0xC0U) -#define SPDIF_SCR_INPUT_SOURCESELECTOR_SHIFT (6U) -/*! Input_SourceSelector - * 0b00..EBU_In1 + +#define SPDIF_SCR_INPUTSRCSEL_MASK (0xC0U) +#define SPDIF_SCR_INPUTSRCSEL_SHIFT (6U) +/*! InputSrcSel - InputSrcSel + * 0b00..SPDIF_IN + * 0b01-0b11..None */ -#define SPDIF_SCR_INPUT_SOURCESELECTOR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_INPUT_SOURCESELECTOR_SHIFT)) & SPDIF_SCR_INPUT_SOURCESELECTOR_MASK) +#define SPDIF_SCR_INPUTSRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_INPUTSRCSEL_SHIFT)) & SPDIF_SCR_INPUTSRCSEL_MASK) + #define SPDIF_SCR_DMA_TX_EN_MASK (0x100U) #define SPDIF_SCR_DMA_TX_EN_SHIFT (8U) +/*! DMA_TX_En - DMA_TX_En + */ #define SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK) + #define SPDIF_SCR_DMA_RX_EN_MASK (0x200U) #define SPDIF_SCR_DMA_RX_EN_SHIFT (9U) +/*! DMA_Rx_En - DMA_Rx_En + */ #define SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK) + #define SPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U) #define SPDIF_SCR_TXFIFO_CTRL_SHIFT (10U) -/*! TxFIFO_Ctrl +/*! TxFIFO_Ctrl - TxFIFO_Ctrl * 0b00..Send out digital zero on SPDIF Tx * 0b01..Tx Normal operation * 0b10..Reset to 1 sample remaining * 0b11..Reserved */ #define SPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK) + #define SPDIF_SCR_SOFT_RESET_MASK (0x1000U) #define SPDIF_SCR_SOFT_RESET_SHIFT (12U) +/*! soft_reset - soft_reset + */ #define SPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK) + #define SPDIF_SCR_LOW_POWER_MASK (0x2000U) #define SPDIF_SCR_LOW_POWER_SHIFT (13U) -#define SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK) -#define SPDIF_SCR_RAW_CAPTURE_MODE_MASK (0x4000U) -#define SPDIF_SCR_RAW_CAPTURE_MODE_SHIFT (14U) -/*! RAW_CAPTURE_MODE - * 0b0..Recovery data only includes data - * 0b1..Recovery data includes data, VUCP bits, and sync code (preamble information) +/*! LOW_POWER - LOW_POWER */ -#define SPDIF_SCR_RAW_CAPTURE_MODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RAW_CAPTURE_MODE_SHIFT)) & SPDIF_SCR_RAW_CAPTURE_MODE_MASK) +#define SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK) + #define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U) #define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U) -/*! TxFIFOEmpty_Sel +/*! TxFIFOEmpty_Sel - TxFIFOEmpty_Sel * 0b00..Empty interrupt if 0 sample in Tx left and right FIFOs * 0b01..Empty interrupt if at most 4 sample in Tx left and right FIFOs * 0b10..Empty interrupt if at most 8 sample in Tx left and right FIFOs * 0b11..Empty interrupt if at most 12 sample in Tx left and right FIFOs */ #define SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK) + #define SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U) #define SPDIF_SCR_TXAUTOSYNC_SHIFT (17U) -/*! TxAutoSync +/*! TxAutoSync - TxAutoSync * 0b0..Tx FIFO auto sync off * 0b1..Tx FIFO auto sync on */ #define SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK) + #define SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U) #define SPDIF_SCR_RXAUTOSYNC_SHIFT (18U) -/*! RxAutoSync +/*! RxAutoSync - RxAutoSync * 0b0..Rx FIFO auto sync off * 0b1..RxFIFO auto sync on */ #define SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK) + #define SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U) #define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U) -/*! RxFIFOFull_Sel +/*! RxFIFOFull_Sel - RxFIFOFull_Sel * 0b00..Full interrupt if at least 1 sample in Rx left and right FIFOs * 0b01..Full interrupt if at least 4 sample in Rx left and right FIFOs * 0b10..Full interrupt if at least 8 sample in Rx left and right FIFOs * 0b11..Full interrupt if at least 16 sample in Rx left and right FIFO */ #define SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK) + #define SPDIF_SCR_RXFIFO_RST_MASK (0x200000U) #define SPDIF_SCR_RXFIFO_RST_SHIFT (21U) -/*! RxFIFO_Rst +/*! RxFIFO_Rst - RxFIFO_Rst * 0b0..Normal operation * 0b1..Reset register to 1 sample remaining */ #define SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK) + #define SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U) #define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U) -/*! RxFIFO_Off_On +/*! RxFIFO_Off_On - RxFIFO_Off_On * 0b0..SPDIF Rx FIFO is on * 0b1..SPDIF Rx FIFO is off. Does not accept data from interface */ #define SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK) + #define SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U) #define SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U) -/*! RxFIFO_Ctrl +/*! RxFIFO_Ctrl - RxFIFO_Ctrl * 0b0..Normal operation * 0b1..Always read zero from Rx data register */ @@ -77864,20 +87084,22 @@ typedef struct { /*! @name SRCD - CDText Control Register */ /*! @{ */ -#define SPDIF_SRCD_EBU_1_USYNCMODE_MASK (0x2U) -#define SPDIF_SRCD_EBU_1_USYNCMODE_SHIFT (1U) -/*! EBU_1_USyncMode + +#define SPDIF_SRCD_USYNCMODE_MASK (0x2U) +#define SPDIF_SRCD_USYNCMODE_SHIFT (1U) +/*! USyncMode - USyncMode * 0b0..Non-CD data * 0b1..CD user channel subcode */ -#define SPDIF_SRCD_EBU_1_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_EBU_1_USYNCMODE_SHIFT)) & SPDIF_SRCD_EBU_1_USYNCMODE_MASK) +#define SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK) /*! @} */ /*! @name SRPC - PhaseConfig Register */ /*! @{ */ + #define SPDIF_SRPC_GAINSEL_MASK (0x38U) #define SPDIF_SRPC_GAINSEL_SHIFT (3U) -/*! GainSel +/*! GainSel - GainSel * 0b000..24*(2**10) * 0b001..16*(2**10) * 0b010..12*(2**10) @@ -77887,12 +87109,16 @@ typedef struct { * 0b110..3*(2**10) */ #define SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK) + #define SPDIF_SRPC_LOCK_MASK (0x40U) #define SPDIF_SRPC_LOCK_SHIFT (6U) +/*! LOCK - LOCK + */ #define SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK) + #define SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U) #define SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U) -/*! ClkSrc_Sel +/*! ClkSrc_Sel - ClkSrc_Sel * 0b0000..if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC) * 0b0001..if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT) * 0b0011..if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK @@ -77905,275 +87131,459 @@ typedef struct { /*! @name SIE - InterruptEn Register */ /*! @{ */ + #define SPDIF_SIE_RXFIFOFUL_MASK (0x1U) #define SPDIF_SIE_RXFIFOFUL_SHIFT (0U) +/*! RxFIFOFul - RxFIFOFul + */ #define SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK) + #define SPDIF_SIE_TXEM_MASK (0x2U) #define SPDIF_SIE_TXEM_SHIFT (1U) +/*! TxEm - TxEm + */ #define SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK) + #define SPDIF_SIE_LOCKLOSS_MASK (0x4U) #define SPDIF_SIE_LOCKLOSS_SHIFT (2U) +/*! LockLoss - LockLoss + */ #define SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK) + #define SPDIF_SIE_RXFIFORESYN_MASK (0x8U) #define SPDIF_SIE_RXFIFORESYN_SHIFT (3U) +/*! RxFIFOResyn - RxFIFOResyn + */ #define SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK) + #define SPDIF_SIE_RXFIFOUNOV_MASK (0x10U) #define SPDIF_SIE_RXFIFOUNOV_SHIFT (4U) +/*! RxFIFOUnOv - RxFIFOUnOv + */ #define SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK) + #define SPDIF_SIE_UQERR_MASK (0x20U) #define SPDIF_SIE_UQERR_SHIFT (5U) +/*! UQErr - UQErr + */ #define SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK) + #define SPDIF_SIE_UQSYNC_MASK (0x40U) #define SPDIF_SIE_UQSYNC_SHIFT (6U) +/*! UQSync - UQSync + */ #define SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK) + #define SPDIF_SIE_QRXOV_MASK (0x80U) #define SPDIF_SIE_QRXOV_SHIFT (7U) +/*! QRxOv - QRxOv + */ #define SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK) + #define SPDIF_SIE_QRXFUL_MASK (0x100U) #define SPDIF_SIE_QRXFUL_SHIFT (8U) +/*! QRxFul - QRxFul + */ #define SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK) + #define SPDIF_SIE_URXOV_MASK (0x200U) #define SPDIF_SIE_URXOV_SHIFT (9U) +/*! URxOv - URxOv + */ #define SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK) + #define SPDIF_SIE_URXFUL_MASK (0x400U) #define SPDIF_SIE_URXFUL_SHIFT (10U) +/*! URxFul - URxFul + */ #define SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK) + #define SPDIF_SIE_BITERR_MASK (0x4000U) #define SPDIF_SIE_BITERR_SHIFT (14U) +/*! BitErr - BitErr + */ #define SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK) + #define SPDIF_SIE_SYMERR_MASK (0x8000U) #define SPDIF_SIE_SYMERR_SHIFT (15U) +/*! SymErr - SymErr + */ #define SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK) + #define SPDIF_SIE_VALNOGOOD_MASK (0x10000U) #define SPDIF_SIE_VALNOGOOD_SHIFT (16U) +/*! ValNoGood - ValNoGood + */ #define SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK) + #define SPDIF_SIE_CNEW_MASK (0x20000U) #define SPDIF_SIE_CNEW_SHIFT (17U) +/*! CNew - CNew + */ #define SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK) + #define SPDIF_SIE_TXRESYN_MASK (0x40000U) #define SPDIF_SIE_TXRESYN_SHIFT (18U) +/*! TxResyn - TxResyn + */ #define SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK) + #define SPDIF_SIE_TXUNOV_MASK (0x80000U) #define SPDIF_SIE_TXUNOV_SHIFT (19U) +/*! TxUnOv - TxUnOv + */ #define SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK) + #define SPDIF_SIE_LOCK_MASK (0x100000U) #define SPDIF_SIE_LOCK_SHIFT (20U) +/*! Lock - Lock + */ #define SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK) /*! @} */ /*! @name SIC - InterruptClear Register */ /*! @{ */ + #define SPDIF_SIC_LOCKLOSS_MASK (0x4U) #define SPDIF_SIC_LOCKLOSS_SHIFT (2U) +/*! LockLoss - LockLoss + */ #define SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK) + #define SPDIF_SIC_RXFIFORESYN_MASK (0x8U) #define SPDIF_SIC_RXFIFORESYN_SHIFT (3U) +/*! RxFIFOResyn - RxFIFOResyn + */ #define SPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK) + #define SPDIF_SIC_RXFIFOUNOV_MASK (0x10U) #define SPDIF_SIC_RXFIFOUNOV_SHIFT (4U) +/*! RxFIFOUnOv - RxFIFOUnOv + */ #define SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK) + #define SPDIF_SIC_UQERR_MASK (0x20U) #define SPDIF_SIC_UQERR_SHIFT (5U) +/*! UQErr - UQErr + */ #define SPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK) + #define SPDIF_SIC_UQSYNC_MASK (0x40U) #define SPDIF_SIC_UQSYNC_SHIFT (6U) +/*! UQSync - UQSync + */ #define SPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK) + #define SPDIF_SIC_QRXOV_MASK (0x80U) #define SPDIF_SIC_QRXOV_SHIFT (7U) +/*! QRxOv - QRxOv + */ #define SPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK) + #define SPDIF_SIC_URXOV_MASK (0x200U) #define SPDIF_SIC_URXOV_SHIFT (9U) +/*! URxOv - URxOv + */ #define SPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK) + #define SPDIF_SIC_BITERR_MASK (0x4000U) #define SPDIF_SIC_BITERR_SHIFT (14U) +/*! BitErr - BitErr + */ #define SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK) + #define SPDIF_SIC_SYMERR_MASK (0x8000U) #define SPDIF_SIC_SYMERR_SHIFT (15U) +/*! SymErr - SymErr + */ #define SPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK) + #define SPDIF_SIC_VALNOGOOD_MASK (0x10000U) #define SPDIF_SIC_VALNOGOOD_SHIFT (16U) +/*! ValNoGood - ValNoGood + */ #define SPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK) + #define SPDIF_SIC_CNEW_MASK (0x20000U) #define SPDIF_SIC_CNEW_SHIFT (17U) +/*! CNew - CNew + */ #define SPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK) + #define SPDIF_SIC_TXRESYN_MASK (0x40000U) #define SPDIF_SIC_TXRESYN_SHIFT (18U) +/*! TxResyn - TxResyn + */ #define SPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK) + #define SPDIF_SIC_TXUNOV_MASK (0x80000U) #define SPDIF_SIC_TXUNOV_SHIFT (19U) +/*! TxUnOv - TxUnOv + */ #define SPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK) + #define SPDIF_SIC_LOCK_MASK (0x100000U) #define SPDIF_SIC_LOCK_SHIFT (20U) +/*! Lock - Lock + */ #define SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK) /*! @} */ /*! @name SIS - InterruptStat Register */ /*! @{ */ + #define SPDIF_SIS_RXFIFOFUL_MASK (0x1U) #define SPDIF_SIS_RXFIFOFUL_SHIFT (0U) +/*! RxFIFOFul - RxFIFOFul + */ #define SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK) + #define SPDIF_SIS_TXEM_MASK (0x2U) #define SPDIF_SIS_TXEM_SHIFT (1U) +/*! TxEm - TxEm + */ #define SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK) + #define SPDIF_SIS_LOCKLOSS_MASK (0x4U) #define SPDIF_SIS_LOCKLOSS_SHIFT (2U) +/*! LockLoss - LockLoss + */ #define SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK) + #define SPDIF_SIS_RXFIFORESYN_MASK (0x8U) #define SPDIF_SIS_RXFIFORESYN_SHIFT (3U) +/*! RxFIFOResyn - RxFIFOResyn + */ #define SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK) + #define SPDIF_SIS_RXFIFOUNOV_MASK (0x10U) #define SPDIF_SIS_RXFIFOUNOV_SHIFT (4U) +/*! RxFIFOUnOv - RxFIFOUnOv + */ #define SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK) + #define SPDIF_SIS_UQERR_MASK (0x20U) #define SPDIF_SIS_UQERR_SHIFT (5U) +/*! UQErr - UQErr + */ #define SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK) + #define SPDIF_SIS_UQSYNC_MASK (0x40U) #define SPDIF_SIS_UQSYNC_SHIFT (6U) +/*! UQSync - UQSync + */ #define SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK) + #define SPDIF_SIS_QRXOV_MASK (0x80U) #define SPDIF_SIS_QRXOV_SHIFT (7U) +/*! QRxOv - QRxOv + */ #define SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK) + #define SPDIF_SIS_QRXFUL_MASK (0x100U) #define SPDIF_SIS_QRXFUL_SHIFT (8U) +/*! QRxFul - QRxFul + */ #define SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK) + #define SPDIF_SIS_URXOV_MASK (0x200U) #define SPDIF_SIS_URXOV_SHIFT (9U) +/*! URxOv - URxOv + */ #define SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK) + #define SPDIF_SIS_URXFUL_MASK (0x400U) #define SPDIF_SIS_URXFUL_SHIFT (10U) +/*! URxFul - URxFul + */ #define SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK) + #define SPDIF_SIS_BITERR_MASK (0x4000U) #define SPDIF_SIS_BITERR_SHIFT (14U) +/*! BitErr - BitErr + */ #define SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK) + #define SPDIF_SIS_SYMERR_MASK (0x8000U) #define SPDIF_SIS_SYMERR_SHIFT (15U) +/*! SymErr - SymErr + */ #define SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK) + #define SPDIF_SIS_VALNOGOOD_MASK (0x10000U) #define SPDIF_SIS_VALNOGOOD_SHIFT (16U) +/*! ValNoGood - ValNoGood + */ #define SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK) + #define SPDIF_SIS_CNEW_MASK (0x20000U) #define SPDIF_SIS_CNEW_SHIFT (17U) +/*! CNew - CNew + */ #define SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK) + #define SPDIF_SIS_TXRESYN_MASK (0x40000U) #define SPDIF_SIS_TXRESYN_SHIFT (18U) +/*! TxResyn - TxResyn + */ #define SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK) + #define SPDIF_SIS_TXUNOV_MASK (0x80000U) #define SPDIF_SIS_TXUNOV_SHIFT (19U) +/*! TxUnOv - TxUnOv + */ #define SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK) + #define SPDIF_SIS_LOCK_MASK (0x100000U) #define SPDIF_SIS_LOCK_SHIFT (20U) +/*! Lock - Lock + */ #define SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK) /*! @} */ /*! @name SRL - SPDIFRxLeft Register */ /*! @{ */ + #define SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU) #define SPDIF_SRL_RXDATALEFT_SHIFT (0U) +/*! RxDataLeft - RxDataLeft + */ #define SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK) /*! @} */ /*! @name SRR - SPDIFRxRight Register */ /*! @{ */ + #define SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU) #define SPDIF_SRR_RXDATARIGHT_SHIFT (0U) +/*! RxDataRight - RxDataRight + */ #define SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK) /*! @} */ /*! @name SRCSH - SPDIFRxCChannel_h Register */ /*! @{ */ + #define SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU) #define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U) +/*! RxCChannel_h - RxCChannel_h + */ #define SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK) /*! @} */ /*! @name SRCSL - SPDIFRxCChannel_l Register */ /*! @{ */ + #define SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU) #define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U) +/*! RxCChannel_l - RxCChannel_l + */ #define SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK) /*! @} */ /*! @name SRU - UchannelRx Register */ /*! @{ */ + #define SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU) #define SPDIF_SRU_RXUCHANNEL_SHIFT (0U) +/*! RxUChannel - RxUChannel + */ #define SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK) /*! @} */ /*! @name SRQ - QchannelRx Register */ /*! @{ */ + #define SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU) #define SPDIF_SRQ_RXQCHANNEL_SHIFT (0U) +/*! RxQChannel - RxQChannel + */ #define SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK) /*! @} */ /*! @name STL - SPDIFTxLeft Register */ /*! @{ */ + #define SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU) #define SPDIF_STL_TXDATALEFT_SHIFT (0U) +/*! TxDataLeft - TxDataLeft + */ #define SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK) /*! @} */ /*! @name STR - SPDIFTxRight Register */ /*! @{ */ + #define SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU) #define SPDIF_STR_TXDATARIGHT_SHIFT (0U) +/*! TxDataRight - TxDataRight + */ #define SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK) /*! @} */ /*! @name STCSCH - SPDIFTxCChannelCons_h Register */ /*! @{ */ + #define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU) #define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U) +/*! TxCChannelCons_h - TxCChannelCons_h + */ #define SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK) /*! @} */ /*! @name STCSCL - SPDIFTxCChannelCons_l Register */ /*! @{ */ + #define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU) #define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U) +/*! TxCChannelCons_l - TxCChannelCons_l + */ #define SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK) /*! @} */ /*! @name SRFM - FreqMeas Register */ /*! @{ */ + #define SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU) #define SPDIF_SRFM_FREQMEAS_SHIFT (0U) +/*! FreqMeas - FreqMeas + */ #define SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK) /*! @} */ /*! @name STC - SPDIFTxClk Register */ /*! @{ */ + #define SPDIF_STC_TXCLK_DF_MASK (0x7FU) #define SPDIF_STC_TXCLK_DF_SHIFT (0U) -/*! TxClk_DF +/*! TxClk_DF - TxClk_DF * 0b0000000..divider factor is 1 * 0b0000001..divider factor is 2 * 0b1111111..divider factor is 128 */ #define SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK) + #define SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U) #define SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U) -/*! tx_all_clk_en +/*! tx_all_clk_en - tx_all_clk_en * 0b0..disable transfer clock. * 0b1..enable transfer clock. */ #define SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK) + #define SPDIF_STC_TXCLK_SOURCE_MASK (0x700U) #define SPDIF_STC_TXCLK_SOURCE_SHIFT (8U) -/*! TxClk_Source - * 0b000..XTALOSC input (XTALOSC clock) - * 0b001..tx_clk input (from SPDIF0_CLK_ROOT. See CCM.) - * 0b010..tx_clk1 (from SAI1) - * 0b011..tx_clk2 SPDIF_EXT_CLK, from pads - * 0b100..tx_clk3 (from SAI2) +/*! TxClk_Source - TxClk_Source + * 0b000..REF_CLK_32K input (XTALOSC 32 kHz clock) + * 0b001..tx_clk input (from SPDIF0_CLK_ROOT. See clock control block for more information.) + * 0b011..SPDIF_EXT_CLK, from pads * 0b101..ipg_clk input (frequency divided) - * 0b110..tx_clk4 (from SAI3) */ #define SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK) + #define SPDIF_STC_SYSCLK_DF_MASK (0xFF800U) #define SPDIF_STC_SYSCLK_DF_SHIFT (11U) -/*! SYSCLK_DF +/*! SYSCLK_DF - SYSCLK_DF * 0b000000000..no clock signal * 0b000000001..divider factor is 2 * 0b111111111..divider factor is 512 @@ -78204,6 +87614,99 @@ typedef struct { */ /* end of group SPDIF_Peripheral_Access_Layer */ +/* ---------------------------------------------------------------------------- + -- SRAM Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRAM_Peripheral_Access_Layer SRAM Peripheral Access Layer + * @{ + */ + +/** SRAM - Register Layout Typedef */ +typedef struct { + uint8_t RESERVED_0[12288]; + __IO uint32_t CTRL; /**< Control Register, offset: 0x3000 */ +} SRAM_Type; + +/* ---------------------------------------------------------------------------- + -- SRAM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRAM_Register_Masks SRAM Register Masks + * @{ + */ + +/*! @name CTRL - Control Register */ +/*! @{ */ + +#define SRAM_CTRL_RAM_RD_EN_MASK (0x1U) +#define SRAM_CTRL_RAM_RD_EN_SHIFT (0U) +/*! RAM_RD_EN - RAM Read Enable (with lock) + * 0b0..Disable read access + * 0b1..Enable read access + */ +#define SRAM_CTRL_RAM_RD_EN(x) (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_RAM_RD_EN_SHIFT)) & SRAM_CTRL_RAM_RD_EN_MASK) + +#define SRAM_CTRL_RAM_WR_EN_MASK (0x2U) +#define SRAM_CTRL_RAM_WR_EN_SHIFT (1U) +/*! RAM_WR_EN - RAM Write Enable (with lock) + * 0b0..Disable write access + * 0b1..Enable write access + */ +#define SRAM_CTRL_RAM_WR_EN(x) (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_RAM_WR_EN_SHIFT)) & SRAM_CTRL_RAM_WR_EN_MASK) + +#define SRAM_CTRL_PWR_EN_MASK (0x3CU) +#define SRAM_CTRL_PWR_EN_SHIFT (2U) +/*! PWR_EN - Power Enable (with lock) + */ +#define SRAM_CTRL_PWR_EN(x) (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_PWR_EN_SHIFT)) & SRAM_CTRL_PWR_EN_MASK) + +#define SRAM_CTRL_TAMPER_BLOCK_EN_MASK (0x40U) +#define SRAM_CTRL_TAMPER_BLOCK_EN_SHIFT (6U) +/*! TAMPER_BLOCK_EN - Tamper Block Enable (with lock) + * 0b0..Allow R/W access to secure RAM when tamper is detected + * 0b1..Block R/W access to secure RAM when tamper is detected + */ +#define SRAM_CTRL_TAMPER_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_TAMPER_BLOCK_EN_SHIFT)) & SRAM_CTRL_TAMPER_BLOCK_EN_MASK) + +#define SRAM_CTRL_TAMPER_PWR_OFF_EN_MASK (0x80U) +#define SRAM_CTRL_TAMPER_PWR_OFF_EN_SHIFT (7U) +/*! TAMPER_PWR_OFF_EN - Turn off power on tamper event (with lock) + * 0b0..Disable the turn off function when tamper is detected + * 0b1..Turn off power for all secure RAM banks when tamper is detected + */ +#define SRAM_CTRL_TAMPER_PWR_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_TAMPER_PWR_OFF_EN_SHIFT)) & SRAM_CTRL_TAMPER_PWR_OFF_EN_MASK) + +#define SRAM_CTRL_LOCK_BIT_MASK (0xFF0000U) +#define SRAM_CTRL_LOCK_BIT_SHIFT (16U) +/*! LOCK_BIT - Lock bits + */ +#define SRAM_CTRL_LOCK_BIT(x) (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_LOCK_BIT_SHIFT)) & SRAM_CTRL_LOCK_BIT_MASK) +/*! @} */ + + +/*! + * @} + */ /* end of group SRAM_Register_Masks */ + + +/* SRAM - Peripheral instance base addresses */ +/** Peripheral SRAM base address */ +#define SRAM_BASE (0x40C9C000u) +/** Peripheral SRAM base pointer */ +#define SRAM ((SRAM_Type *)SRAM_BASE) +/** Array initializer of SRAM peripheral base addresses */ +#define SRAM_BASE_ADDRS { SRAM_BASE } +/** Array initializer of SRAM peripheral base pointers */ +#define SRAM_BASE_PTRS { SRAM } + +/*! + * @} + */ /* end of group SRAM_Peripheral_Access_Layer */ + + /* ---------------------------------------------------------------------------- -- SRC Peripheral Access Layer ---------------------------------------------------------------------------- */ @@ -78224,55 +87727,55 @@ typedef struct { uint8_t RESERVED_0[412]; __IO uint32_t AUTHEN_MEGA; /**< Slice Authentication Register, offset: 0x200 */ __IO uint32_t CTRL_MEGA; /**< Slice Control Register, offset: 0x204 */ - __IO uint32_t SETPOINT_MEGA; /**< Slice SetPoint Config Register, offset: 0x208 */ + __IO uint32_t SETPOINT_MEGA; /**< Slice Setpoint Config Register, offset: 0x208 */ __IO uint32_t DOMAIN_MEGA; /**< Slice Domain Config Register, offset: 0x20C */ __IO uint32_t STAT_MEGA; /**< Slice Status Register, offset: 0x210 */ uint8_t RESERVED_1[12]; __IO uint32_t AUTHEN_DISPLAY; /**< Slice Authentication Register, offset: 0x220 */ __IO uint32_t CTRL_DISPLAY; /**< Slice Control Register, offset: 0x224 */ - __IO uint32_t SETPOINT_DISPLAY; /**< Slice SetPoint Config Register, offset: 0x228 */ + __IO uint32_t SETPOINT_DISPLAY; /**< Slice Setpoint Config Register, offset: 0x228 */ __IO uint32_t DOMAIN_DISPLAY; /**< Slice Domain Config Register, offset: 0x22C */ __IO uint32_t STAT_DISPLAY; /**< Slice Status Register, offset: 0x230 */ uint8_t RESERVED_2[12]; __IO uint32_t AUTHEN_WAKEUP; /**< Slice Authentication Register, offset: 0x240 */ __IO uint32_t CTRL_WAKEUP; /**< Slice Control Register, offset: 0x244 */ - __IO uint32_t SETPOINT_WAKEUP; /**< Slice SetPoint Config Register, offset: 0x248 */ + __IO uint32_t SETPOINT_WAKEUP; /**< Slice Setpoint Config Register, offset: 0x248 */ __IO uint32_t DOMAIN_WAKEUP; /**< Slice Domain Config Register, offset: 0x24C */ __IO uint32_t STAT_WAKEUP; /**< Slice Status Register, offset: 0x250 */ uint8_t RESERVED_3[44]; __IO uint32_t AUTHEN_M4CORE; /**< Slice Authentication Register, offset: 0x280 */ __IO uint32_t CTRL_M4CORE; /**< Slice Control Register, offset: 0x284 */ - __IO uint32_t SETPOINT_M4CORE; /**< Slice SetPoint Config Register, offset: 0x288 */ + __IO uint32_t SETPOINT_M4CORE; /**< Slice Setpoint Config Register, offset: 0x288 */ __IO uint32_t DOMAIN_M4CORE; /**< Slice Domain Config Register, offset: 0x28C */ __IO uint32_t STAT_M4CORE; /**< Slice Status Register, offset: 0x290 */ uint8_t RESERVED_4[12]; __IO uint32_t AUTHEN_M7CORE; /**< Slice Authentication Register, offset: 0x2A0 */ __IO uint32_t CTRL_M7CORE; /**< Slice Control Register, offset: 0x2A4 */ - __IO uint32_t SETPOINT_M7CORE; /**< Slice SetPoint Config Register, offset: 0x2A8 */ + __IO uint32_t SETPOINT_M7CORE; /**< Slice Setpoint Config Register, offset: 0x2A8 */ __IO uint32_t DOMAIN_M7CORE; /**< Slice Domain Config Register, offset: 0x2AC */ __IO uint32_t STAT_M7CORE; /**< Slice Status Register, offset: 0x2B0 */ uint8_t RESERVED_5[12]; __IO uint32_t AUTHEN_M4DEBUG; /**< Slice Authentication Register, offset: 0x2C0 */ __IO uint32_t CTRL_M4DEBUG; /**< Slice Control Register, offset: 0x2C4 */ - __IO uint32_t SETPOINT_M4DEBUG; /**< Slice SetPoint Config Register, offset: 0x2C8 */ + __IO uint32_t SETPOINT_M4DEBUG; /**< Slice Setpoint Config Register, offset: 0x2C8 */ __IO uint32_t DOMAIN_M4DEBUG; /**< Slice Domain Config Register, offset: 0x2CC */ __IO uint32_t STAT_M4DEBUG; /**< Slice Status Register, offset: 0x2D0 */ uint8_t RESERVED_6[12]; __IO uint32_t AUTHEN_M7DEBUG; /**< Slice Authentication Register, offset: 0x2E0 */ __IO uint32_t CTRL_M7DEBUG; /**< Slice Control Register, offset: 0x2E4 */ - __IO uint32_t SETPOINT_M7DEBUG; /**< Slice SetPoint Config Register, offset: 0x2E8 */ + __IO uint32_t SETPOINT_M7DEBUG; /**< Slice Setpoint Config Register, offset: 0x2E8 */ __IO uint32_t DOMAIN_M7DEBUG; /**< Slice Domain Config Register, offset: 0x2EC */ __IO uint32_t STAT_M7DEBUG; /**< Slice Status Register, offset: 0x2F0 */ uint8_t RESERVED_7[12]; __IO uint32_t AUTHEN_USBPHY1; /**< Slice Authentication Register, offset: 0x300 */ __IO uint32_t CTRL_USBPHY1; /**< Slice Control Register, offset: 0x304 */ - __IO uint32_t SETPOINT_USBPHY1; /**< Slice SetPoint Config Register, offset: 0x308 */ + __IO uint32_t SETPOINT_USBPHY1; /**< Slice Setpoint Config Register, offset: 0x308 */ __IO uint32_t DOMAIN_USBPHY1; /**< Slice Domain Config Register, offset: 0x30C */ __IO uint32_t STAT_USBPHY1; /**< Slice Status Register, offset: 0x310 */ uint8_t RESERVED_8[12]; __IO uint32_t AUTHEN_USBPHY2; /**< Slice Authentication Register, offset: 0x320 */ __IO uint32_t CTRL_USBPHY2; /**< Slice Control Register, offset: 0x324 */ - __IO uint32_t SETPOINT_USBPHY2; /**< Slice SetPoint Config Register, offset: 0x328 */ + __IO uint32_t SETPOINT_USBPHY2; /**< Slice Setpoint Config Register, offset: 0x328 */ __IO uint32_t DOMAIN_USBPHY2; /**< Slice Domain Config Register, offset: 0x32C */ __IO uint32_t STAT_USBPHY2; /**< Slice Status Register, offset: 0x330 */ } SRC_Type; @@ -78288,6 +87791,7 @@ typedef struct { /*! @name SCR - SRC Control Register */ /*! @{ */ + #define SRC_SCR_BT_RELEASE_M4_MASK (0x1U) #define SRC_SCR_BT_RELEASE_M4_SHIFT (0U) /*! BT_RELEASE_M4 @@ -78295,6 +87799,7 @@ typedef struct { * 0b1..cm4 core reset is released */ #define SRC_SCR_BT_RELEASE_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_BT_RELEASE_M4_SHIFT)) & SRC_SCR_BT_RELEASE_M4_MASK) + #define SRC_SCR_BT_RELEASE_M7_MASK (0x2U) #define SRC_SCR_BT_RELEASE_M7_SHIFT (1U) /*! BT_RELEASE_M7 @@ -78306,102 +87811,113 @@ typedef struct { /*! @name SRMR - SRC Reset Mode Register */ /*! @{ */ + #define SRC_SRMR_WDOG_RESET_MODE_MASK (0x3U) #define SRC_SRMR_WDOG_RESET_MODE_SHIFT (0U) /*! WDOG_RESET_MODE - Wdog reset mode configuration * 0b00..reset system - * 0b01..invalid configuration - * 0b10..invalid configuration + * 0b01..reserved + * 0b10..reserved * 0b11..do not reset anything */ #define SRC_SRMR_WDOG_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG_RESET_MODE_MASK) + #define SRC_SRMR_WDOG3_RESET_MODE_MASK (0xCU) #define SRC_SRMR_WDOG3_RESET_MODE_SHIFT (2U) /*! WDOG3_RESET_MODE - Wdog3 reset mode configuration * 0b00..reset system - * 0b01..invalid configuration - * 0b10..invalid configuration + * 0b01..reserved + * 0b10..reserved * 0b11..do not reset anything */ #define SRC_SRMR_WDOG3_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG3_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG3_RESET_MODE_MASK) + #define SRC_SRMR_WDOG4_RESET_MODE_MASK (0x30U) #define SRC_SRMR_WDOG4_RESET_MODE_SHIFT (4U) /*! WDOG4_RESET_MODE - Wdog4 reset mode configuration * 0b00..reset system - * 0b01..invalid configuration - * 0b10..invalid configuration + * 0b01..reserved + * 0b10..reserved * 0b11..do not reset anything */ #define SRC_SRMR_WDOG4_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG4_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG4_RESET_MODE_MASK) + #define SRC_SRMR_M4LOCKUP_RESET_MODE_MASK (0xC0U) #define SRC_SRMR_M4LOCKUP_RESET_MODE_SHIFT (6U) /*! M4LOCKUP_RESET_MODE - M4 core lockup reset mode configuration * 0b00..reset system - * 0b01..invalid configuration - * 0b10..invalid configuration + * 0b01..reserved + * 0b10..reserved * 0b11..do not reset anything */ #define SRC_SRMR_M4LOCKUP_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M4LOCKUP_RESET_MODE_SHIFT)) & SRC_SRMR_M4LOCKUP_RESET_MODE_MASK) + #define SRC_SRMR_M7LOCKUP_RESET_MODE_MASK (0x300U) #define SRC_SRMR_M7LOCKUP_RESET_MODE_SHIFT (8U) /*! M7LOCKUP_RESET_MODE - M7 core lockup reset mode configuration * 0b00..reset system - * 0b01..invalid configuration - * 0b10..invalid configuration + * 0b01..reserved + * 0b10..reserved * 0b11..do not reset anything */ #define SRC_SRMR_M7LOCKUP_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M7LOCKUP_RESET_MODE_SHIFT)) & SRC_SRMR_M7LOCKUP_RESET_MODE_MASK) + #define SRC_SRMR_M4REQ_RESET_MODE_MASK (0xC00U) #define SRC_SRMR_M4REQ_RESET_MODE_SHIFT (10U) /*! M4REQ_RESET_MODE - M4 request reset configuration * 0b00..reset system - * 0b01..invalid configuration - * 0b10..invalid configuration + * 0b01..reserved + * 0b10..reserved * 0b11..do not reset anything */ #define SRC_SRMR_M4REQ_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M4REQ_RESET_MODE_SHIFT)) & SRC_SRMR_M4REQ_RESET_MODE_MASK) + #define SRC_SRMR_M7REQ_RESET_MODE_MASK (0x3000U) #define SRC_SRMR_M7REQ_RESET_MODE_SHIFT (12U) /*! M7REQ_RESET_MODE - M7 request reset configuration * 0b00..reset system - * 0b01..invalid configuration - * 0b10..invalid configuration + * 0b01..reserved + * 0b10..reserved * 0b11..do not reset anything */ #define SRC_SRMR_M7REQ_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M7REQ_RESET_MODE_SHIFT)) & SRC_SRMR_M7REQ_RESET_MODE_MASK) + #define SRC_SRMR_TEMPSENSE_RESET_MODE_MASK (0xC000U) #define SRC_SRMR_TEMPSENSE_RESET_MODE_SHIFT (14U) /*! TEMPSENSE_RESET_MODE - Tempsense reset mode configuration * 0b00..reset system - * 0b01..invalid configuration - * 0b10..invalid configuration + * 0b01..reserved + * 0b10..reserved * 0b11..do not reset anything */ #define SRC_SRMR_TEMPSENSE_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_TEMPSENSE_RESET_MODE_SHIFT)) & SRC_SRMR_TEMPSENSE_RESET_MODE_MASK) + #define SRC_SRMR_CSU_RESET_MODE_MASK (0x30000U) #define SRC_SRMR_CSU_RESET_MODE_SHIFT (16U) /*! CSU_RESET_MODE - CSU reset mode configuration * 0b00..reset system - * 0b01..invalid configuration - * 0b10..invalid configuration + * 0b01..reserved + * 0b10..reserved * 0b11..do not reset anything */ #define SRC_SRMR_CSU_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_CSU_RESET_MODE_SHIFT)) & SRC_SRMR_CSU_RESET_MODE_MASK) + #define SRC_SRMR_JTAGSW_RESET_MODE_MASK (0xC0000U) #define SRC_SRMR_JTAGSW_RESET_MODE_SHIFT (18U) /*! JTAGSW_RESET_MODE - Jtag SW reset mode configuration * 0b00..reset system - * 0b01..invalid configuration - * 0b10..invalid configuration + * 0b01..reserved + * 0b10..reserved * 0b11..do not reset anything */ #define SRC_SRMR_JTAGSW_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_JTAGSW_RESET_MODE_SHIFT)) & SRC_SRMR_JTAGSW_RESET_MODE_MASK) + #define SRC_SRMR_OVERVOLT_RESET_MODE_MASK (0x300000U) #define SRC_SRMR_OVERVOLT_RESET_MODE_SHIFT (20U) /*! OVERVOLT_RESET_MODE - Jtag SW reset mode configuration * 0b00..reset system - * 0b01..invalid configuration - * 0b10..invalid configuration + * 0b01..reserved + * 0b10..reserved * 0b11..do not reset anything */ #define SRC_SRMR_OVERVOLT_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_OVERVOLT_RESET_MODE_SHIFT)) & SRC_SRMR_OVERVOLT_RESET_MODE_MASK) @@ -78409,15 +87925,19 @@ typedef struct { /*! @name SBMR1 - SRC Boot Mode Register 1 */ /*! @{ */ + #define SRC_SBMR1_BOOT_CFG1_MASK (0xFFU) #define SRC_SBMR1_BOOT_CFG1_SHIFT (0U) #define SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK) + #define SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U) #define SRC_SBMR1_BOOT_CFG2_SHIFT (8U) #define SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK) + #define SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U) #define SRC_SBMR1_BOOT_CFG3_SHIFT (16U) #define SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK) + #define SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U) #define SRC_SBMR1_BOOT_CFG4_SHIFT (24U) #define SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK) @@ -78425,12 +87945,15 @@ typedef struct { /*! @name SBMR2 - SRC Boot Mode Register 2 */ /*! @{ */ + #define SRC_SBMR2_SEC_CONFIG_MASK (0x3U) #define SRC_SBMR2_SEC_CONFIG_SHIFT (0U) #define SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK) + #define SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U) #define SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U) #define SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK) + #define SRC_SBMR2_BMOD_MASK (0x3000000U) #define SRC_SBMR2_BMOD_SHIFT (24U) #define SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK) @@ -78438,6 +87961,7 @@ typedef struct { /*! @name SRSR - SRC Reset Status Register */ /*! @{ */ + #define SRC_SRSR_IPP_RESET_B_M7_MASK (0x1U) #define SRC_SRSR_IPP_RESET_B_M7_SHIFT (0U) /*! IPP_RESET_B_M7 @@ -78445,6 +87969,7 @@ typedef struct { * 0b1..Reset is a result of ipp_reset_b pin. */ #define SRC_SRSR_IPP_RESET_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_M7_SHIFT)) & SRC_SRSR_IPP_RESET_B_M7_MASK) + #define SRC_SRSR_M7_REQUEST_M7_MASK (0x2U) #define SRC_SRSR_M7_REQUEST_M7_SHIFT (1U) /*! M7_REQUEST_M7 @@ -78452,6 +87977,7 @@ typedef struct { * 0b1..Reset is a result of m7 reset request. */ #define SRC_SRSR_M7_REQUEST_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_REQUEST_M7_SHIFT)) & SRC_SRSR_M7_REQUEST_M7_MASK) + #define SRC_SRSR_M7_LOCKUP_M7_MASK (0x4U) #define SRC_SRSR_M7_LOCKUP_M7_SHIFT (2U) /*! M7_LOCKUP_M7 @@ -78459,6 +87985,7 @@ typedef struct { * 0b1..Reset is a result of the mentioned case. */ #define SRC_SRSR_M7_LOCKUP_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_LOCKUP_M7_SHIFT)) & SRC_SRSR_M7_LOCKUP_M7_MASK) + #define SRC_SRSR_CSU_RESET_B_M7_MASK (0x8U) #define SRC_SRSR_CSU_RESET_B_M7_SHIFT (3U) /*! CSU_RESET_B_M7 @@ -78466,6 +87993,7 @@ typedef struct { * 0b1..Reset is a result of the csu_reset_b event. */ #define SRC_SRSR_CSU_RESET_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_M7_SHIFT)) & SRC_SRSR_CSU_RESET_B_M7_MASK) + #define SRC_SRSR_IPP_USER_RESET_B_M7_MASK (0x10U) #define SRC_SRSR_IPP_USER_RESET_B_M7_SHIFT (4U) /*! IPP_USER_RESET_B_M7 @@ -78473,6 +88001,7 @@ typedef struct { * 0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event. */ #define SRC_SRSR_IPP_USER_RESET_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_M7_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_M7_MASK) + #define SRC_SRSR_WDOG_RST_B_M7_MASK (0x20U) #define SRC_SRSR_WDOG_RST_B_M7_SHIFT (5U) /*! WDOG_RST_B_M7 @@ -78480,6 +88009,7 @@ typedef struct { * 0b1..Reset is a result of the watchdog time-out event. */ #define SRC_SRSR_WDOG_RST_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG_RST_B_M7_MASK) + #define SRC_SRSR_JTAG_RST_B_M7_MASK (0x40U) #define SRC_SRSR_JTAG_RST_B_M7_SHIFT (6U) /*! JTAG_RST_B_M7 @@ -78487,6 +88017,7 @@ typedef struct { * 0b1..Reset is a result of HIGH-Z reset from JTAG. */ #define SRC_SRSR_JTAG_RST_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_M7_SHIFT)) & SRC_SRSR_JTAG_RST_B_M7_MASK) + #define SRC_SRSR_JTAG_SW_RST_M7_MASK (0x80U) #define SRC_SRSR_JTAG_SW_RST_M7_SHIFT (7U) /*! JTAG_SW_RST_M7 @@ -78494,6 +88025,7 @@ typedef struct { * 0b1..Reset is a result of software reset from JTAG. */ #define SRC_SRSR_JTAG_SW_RST_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_M7_SHIFT)) & SRC_SRSR_JTAG_SW_RST_M7_MASK) + #define SRC_SRSR_WDOG3_RST_B_M7_MASK (0x100U) #define SRC_SRSR_WDOG3_RST_B_M7_SHIFT (8U) /*! WDOG3_RST_B_M7 @@ -78501,6 +88033,7 @@ typedef struct { * 0b1..Reset is a result of the watchdog3 time-out event. */ #define SRC_SRSR_WDOG3_RST_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG3_RST_B_M7_MASK) + #define SRC_SRSR_WDOG4_RST_B_M7_MASK (0x200U) #define SRC_SRSR_WDOG4_RST_B_M7_SHIFT (9U) /*! WDOG4_RST_B_M7 @@ -78508,6 +88041,7 @@ typedef struct { * 0b1..Reset is a result of the watchdog4 time-out event. */ #define SRC_SRSR_WDOG4_RST_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG4_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG4_RST_B_M7_MASK) + #define SRC_SRSR_TEMPSENSE_RST_B_M7_MASK (0x400U) #define SRC_SRSR_TEMPSENSE_RST_B_M7_SHIFT (10U) /*! TEMPSENSE_RST_B_M7 @@ -78515,6 +88049,7 @@ typedef struct { * 0b1..Reset is a result of software reset from Temperature Sensor. */ #define SRC_SRSR_TEMPSENSE_RST_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_M7_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_M7_MASK) + #define SRC_SRSR_M4_REQUEST_M7_MASK (0x800U) #define SRC_SRSR_M4_REQUEST_M7_SHIFT (11U) /*! M4_REQUEST_M7 @@ -78522,6 +88057,7 @@ typedef struct { * 0b1..Reset is a result of m4 reset request. */ #define SRC_SRSR_M4_REQUEST_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_REQUEST_M7_SHIFT)) & SRC_SRSR_M4_REQUEST_M7_MASK) + #define SRC_SRSR_M4_LOCKUP_M7_MASK (0x1000U) #define SRC_SRSR_M4_LOCKUP_M7_SHIFT (12U) /*! M4_LOCKUP_M7 @@ -78529,6 +88065,7 @@ typedef struct { * 0b1..Reset is a result of the mentioned case. */ #define SRC_SRSR_M4_LOCKUP_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_LOCKUP_M7_SHIFT)) & SRC_SRSR_M4_LOCKUP_M7_MASK) + #define SRC_SRSR_OVERVOLT_RST_M7_MASK (0x2000U) #define SRC_SRSR_OVERVOLT_RST_M7_SHIFT (13U) /*! OVERVOLT_RST_M7 @@ -78536,6 +88073,7 @@ typedef struct { * 0b1..Reset is a result of the mentioned case. */ #define SRC_SRSR_OVERVOLT_RST_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_OVERVOLT_RST_M7_SHIFT)) & SRC_SRSR_OVERVOLT_RST_M7_MASK) + #define SRC_SRSR_CDOG_RST_M7_MASK (0x4000U) #define SRC_SRSR_CDOG_RST_M7_SHIFT (14U) /*! CDOG_RST_M7 @@ -78543,6 +88081,7 @@ typedef struct { * 0b1..Reset is a result of the mentioned case. */ #define SRC_SRSR_CDOG_RST_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CDOG_RST_M7_SHIFT)) & SRC_SRSR_CDOG_RST_M7_MASK) + #define SRC_SRSR_IPP_RESET_B_M4_MASK (0x10000U) #define SRC_SRSR_IPP_RESET_B_M4_SHIFT (16U) /*! IPP_RESET_B_M4 @@ -78550,6 +88089,7 @@ typedef struct { * 0b1..Reset is a result of ipp_reset_b pin. */ #define SRC_SRSR_IPP_RESET_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_M4_SHIFT)) & SRC_SRSR_IPP_RESET_B_M4_MASK) + #define SRC_SRSR_M4_REQUEST_M4_MASK (0x20000U) #define SRC_SRSR_M4_REQUEST_M4_SHIFT (17U) /*! M4_REQUEST_M4 @@ -78557,6 +88097,7 @@ typedef struct { * 0b1..Reset is a result of m4 reset request. */ #define SRC_SRSR_M4_REQUEST_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_REQUEST_M4_SHIFT)) & SRC_SRSR_M4_REQUEST_M4_MASK) + #define SRC_SRSR_M4_LOCKUP_M4_MASK (0x40000U) #define SRC_SRSR_M4_LOCKUP_M4_SHIFT (18U) /*! M4_LOCKUP_M4 @@ -78564,6 +88105,7 @@ typedef struct { * 0b1..Reset is a result of the mentioned case. */ #define SRC_SRSR_M4_LOCKUP_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_LOCKUP_M4_SHIFT)) & SRC_SRSR_M4_LOCKUP_M4_MASK) + #define SRC_SRSR_CSU_RESET_B_M4_MASK (0x80000U) #define SRC_SRSR_CSU_RESET_B_M4_SHIFT (19U) /*! CSU_RESET_B_M4 @@ -78571,6 +88113,7 @@ typedef struct { * 0b1..Reset is a result of the csu_reset_b event. */ #define SRC_SRSR_CSU_RESET_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_M4_SHIFT)) & SRC_SRSR_CSU_RESET_B_M4_MASK) + #define SRC_SRSR_IPP_USER_RESET_B_M4_MASK (0x100000U) #define SRC_SRSR_IPP_USER_RESET_B_M4_SHIFT (20U) /*! IPP_USER_RESET_B_M4 @@ -78578,6 +88121,7 @@ typedef struct { * 0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event. */ #define SRC_SRSR_IPP_USER_RESET_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_M4_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_M4_MASK) + #define SRC_SRSR_WDOG_RST_B_M4_MASK (0x200000U) #define SRC_SRSR_WDOG_RST_B_M4_SHIFT (21U) /*! WDOG_RST_B_M4 @@ -78585,6 +88129,7 @@ typedef struct { * 0b1..Reset is a result of the watchdog time-out event. */ #define SRC_SRSR_WDOG_RST_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG_RST_B_M4_MASK) + #define SRC_SRSR_JTAG_RST_B_M4_MASK (0x400000U) #define SRC_SRSR_JTAG_RST_B_M4_SHIFT (22U) /*! JTAG_RST_B_M4 @@ -78592,6 +88137,7 @@ typedef struct { * 0b1..Reset is a result of HIGH-Z reset from JTAG. */ #define SRC_SRSR_JTAG_RST_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_M4_SHIFT)) & SRC_SRSR_JTAG_RST_B_M4_MASK) + #define SRC_SRSR_JTAG_SW_RST_M4_MASK (0x800000U) #define SRC_SRSR_JTAG_SW_RST_M4_SHIFT (23U) /*! JTAG_SW_RST_M4 @@ -78599,6 +88145,7 @@ typedef struct { * 0b1..Reset is a result of software reset from JTAG. */ #define SRC_SRSR_JTAG_SW_RST_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_M4_SHIFT)) & SRC_SRSR_JTAG_SW_RST_M4_MASK) + #define SRC_SRSR_WDOG3_RST_B_M4_MASK (0x1000000U) #define SRC_SRSR_WDOG3_RST_B_M4_SHIFT (24U) /*! WDOG3_RST_B_M4 @@ -78606,6 +88153,7 @@ typedef struct { * 0b1..Reset is a result of the watchdog3 time-out event. */ #define SRC_SRSR_WDOG3_RST_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG3_RST_B_M4_MASK) + #define SRC_SRSR_WDOG4_RST_B_M4_MASK (0x2000000U) #define SRC_SRSR_WDOG4_RST_B_M4_SHIFT (25U) /*! WDOG4_RST_B_M4 @@ -78613,6 +88161,7 @@ typedef struct { * 0b1..Reset is a result of the watchdog4 time-out event. */ #define SRC_SRSR_WDOG4_RST_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG4_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG4_RST_B_M4_MASK) + #define SRC_SRSR_TEMPSENSE_RST_B_M4_MASK (0x4000000U) #define SRC_SRSR_TEMPSENSE_RST_B_M4_SHIFT (26U) /*! TEMPSENSE_RST_B_M4 @@ -78620,6 +88169,7 @@ typedef struct { * 0b1..Reset is a result of software reset from Temperature Sensor. */ #define SRC_SRSR_TEMPSENSE_RST_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_M4_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_M4_MASK) + #define SRC_SRSR_M7_REQUEST_M4_MASK (0x8000000U) #define SRC_SRSR_M7_REQUEST_M4_SHIFT (27U) /*! M7_REQUEST_M4 @@ -78627,6 +88177,7 @@ typedef struct { * 0b1..Reset is a result of m7 reset request. */ #define SRC_SRSR_M7_REQUEST_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_REQUEST_M4_SHIFT)) & SRC_SRSR_M7_REQUEST_M4_MASK) + #define SRC_SRSR_M7_LOCKUP_M4_MASK (0x10000000U) #define SRC_SRSR_M7_LOCKUP_M4_SHIFT (28U) /*! M7_LOCKUP_M4 @@ -78634,6 +88185,7 @@ typedef struct { * 0b1..Reset is a result of the mentioned case. */ #define SRC_SRSR_M7_LOCKUP_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_LOCKUP_M4_SHIFT)) & SRC_SRSR_M7_LOCKUP_M4_MASK) + #define SRC_SRSR_OVERVOLT_RST_M4_MASK (0x20000000U) #define SRC_SRSR_OVERVOLT_RST_M4_SHIFT (29U) /*! OVERVOLT_RST_M4 @@ -78641,6 +88193,7 @@ typedef struct { * 0b1..Reset is a result of the mentioned case. */ #define SRC_SRSR_OVERVOLT_RST_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_OVERVOLT_RST_M4_SHIFT)) & SRC_SRSR_OVERVOLT_RST_M4_MASK) + #define SRC_SRSR_CDOG_RST_M4_MASK (0x40000000U) #define SRC_SRSR_CDOG_RST_M4_SHIFT (30U) /*! CDOG_RST_M4 @@ -78652,8 +88205,11 @@ typedef struct { /*! @name GPR - SRC General Purpose Register */ /*! @{ */ + #define SRC_GPR_GPR_MASK (0xFFFFFFFFU) #define SRC_GPR_GPR_SHIFT (0U) +/*! GPR - General Purpose Register. + */ #define SRC_GPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_GPR_SHIFT)) & SRC_GPR_GPR_MASK) /*! @} */ @@ -78662,53 +88218,63 @@ typedef struct { /*! @name AUTHEN_MEGA - Slice Authentication Register */ /*! @{ */ + #define SRC_AUTHEN_MEGA_DOMAIN_MODE_MASK (0x1U) #define SRC_AUTHEN_MEGA_DOMAIN_MODE_SHIFT (0U) /*! DOMAIN_MODE - * 0b0..slice hardware reset will Not be triggered by cpu power mode transition - * 0b1..slice hardware reset will be triggered by cpu power mode transition. Do not set this bit and SETPOINT_MODE at the same time. + * 0b0..slice hardware reset will NOT be triggered by CPU power mode transition + * 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time. */ #define SRC_AUTHEN_MEGA_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_MEGA_DOMAIN_MODE_MASK) + #define SRC_AUTHEN_MEGA_SETPOINT_MODE_MASK (0x2U) #define SRC_AUTHEN_MEGA_SETPOINT_MODE_SHIFT (1U) /*! SETPOINT_MODE - * 0b0..slice hardware reset will Not be triggered by set point transition - * 0b1..slice hardware reset will be triggered by set point transition. Do not set this bit and DOMAIN_MODE at the same time. + * 0b0..slice hardware reset will NOT be triggered by Setpoint transition + * 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time. */ #define SRC_AUTHEN_MEGA_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_MEGA_SETPOINT_MODE_MASK) + #define SRC_AUTHEN_MEGA_LOCK_MODE_MASK (0x80U) #define SRC_AUTHEN_MEGA_LOCK_MODE_SHIFT (7U) -/*! LOCK_MODE - domain/setpoint mode lock +/*! LOCK_MODE - Domain/Setpoint mode lock */ #define SRC_AUTHEN_MEGA_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_MODE_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_MODE_MASK) + #define SRC_AUTHEN_MEGA_ASSIGN_LIST_MASK (0xF00U) #define SRC_AUTHEN_MEGA_ASSIGN_LIST_SHIFT (8U) #define SRC_AUTHEN_MEGA_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_MEGA_ASSIGN_LIST_MASK) + #define SRC_AUTHEN_MEGA_LOCK_ASSIGN_MASK (0x8000U) #define SRC_AUTHEN_MEGA_LOCK_ASSIGN_SHIFT (15U) /*! LOCK_ASSIGN - Assign list lock */ #define SRC_AUTHEN_MEGA_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_ASSIGN_MASK) + #define SRC_AUTHEN_MEGA_WHITE_LIST_MASK (0xF0000U) #define SRC_AUTHEN_MEGA_WHITE_LIST_SHIFT (16U) /*! WHITE_LIST - Domain ID white list */ #define SRC_AUTHEN_MEGA_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_WHITE_LIST_SHIFT)) & SRC_AUTHEN_MEGA_WHITE_LIST_MASK) + #define SRC_AUTHEN_MEGA_LOCK_LIST_MASK (0x800000U) #define SRC_AUTHEN_MEGA_LOCK_LIST_SHIFT (23U) /*! LOCK_LIST - White list lock */ #define SRC_AUTHEN_MEGA_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_LIST_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_LIST_MASK) + #define SRC_AUTHEN_MEGA_USER_MASK (0x1000000U) #define SRC_AUTHEN_MEGA_USER_SHIFT (24U) /*! USER - Allow user mode access */ #define SRC_AUTHEN_MEGA_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_USER_SHIFT)) & SRC_AUTHEN_MEGA_USER_MASK) + #define SRC_AUTHEN_MEGA_NONSECURE_MASK (0x2000000U) #define SRC_AUTHEN_MEGA_NONSECURE_SHIFT (25U) /*! NONSECURE - Allow non-secure mode access */ #define SRC_AUTHEN_MEGA_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_NONSECURE_SHIFT)) & SRC_AUTHEN_MEGA_NONSECURE_MASK) + #define SRC_AUTHEN_MEGA_LOCK_SETTING_MASK (0x80000000U) #define SRC_AUTHEN_MEGA_LOCK_SETTING_SHIFT (31U) /*! LOCK_SETTING - Lock NONSECURE and USER @@ -78718,6 +88284,7 @@ typedef struct { /*! @name CTRL_MEGA - Slice Control Register */ /*! @{ */ + #define SRC_CTRL_MEGA_SW_RESET_MASK (0x1U) #define SRC_CTRL_MEGA_SW_RESET_SHIFT (0U) /*! SW_RESET @@ -78727,240 +88294,209 @@ typedef struct { #define SRC_CTRL_MEGA_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_MEGA_SW_RESET_SHIFT)) & SRC_CTRL_MEGA_SW_RESET_MASK) /*! @} */ -/*! @name SETPOINT_MEGA - Slice SetPoint Config Register */ +/*! @name SETPOINT_MEGA - Slice Setpoint Config Register */ /*! @{ */ + #define SRC_SETPOINT_MEGA_SETPOINT0_MASK (0x1U) #define SRC_SETPOINT_MEGA_SETPOINT0_SHIFT (0U) -/*! SETPOINT0 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT0 - SETPOINT0 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_MEGA_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT0_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT0_MASK) + #define SRC_SETPOINT_MEGA_SETPOINT1_MASK (0x2U) #define SRC_SETPOINT_MEGA_SETPOINT1_SHIFT (1U) -/*! SETPOINT1 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT1 - SETPOINT1 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_MEGA_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT1_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT1_MASK) + #define SRC_SETPOINT_MEGA_SETPOINT2_MASK (0x4U) #define SRC_SETPOINT_MEGA_SETPOINT2_SHIFT (2U) -/*! SETPOINT2 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT2 - SETPOINT2 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_MEGA_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT2_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT2_MASK) + #define SRC_SETPOINT_MEGA_SETPOINT3_MASK (0x8U) #define SRC_SETPOINT_MEGA_SETPOINT3_SHIFT (3U) -/*! SETPOINT3 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT3 - SETPOINT3 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_MEGA_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT3_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT3_MASK) + #define SRC_SETPOINT_MEGA_SETPOINT4_MASK (0x10U) #define SRC_SETPOINT_MEGA_SETPOINT4_SHIFT (4U) -/*! SETPOINT4 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT4 - SETPOINT4 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_MEGA_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT4_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT4_MASK) + #define SRC_SETPOINT_MEGA_SETPOINT5_MASK (0x20U) #define SRC_SETPOINT_MEGA_SETPOINT5_SHIFT (5U) -/*! SETPOINT5 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT5 - SETPOINT5 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_MEGA_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT5_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT5_MASK) + #define SRC_SETPOINT_MEGA_SETPOINT6_MASK (0x40U) #define SRC_SETPOINT_MEGA_SETPOINT6_SHIFT (6U) -/*! SETPOINT6 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT6 - SETPOINT6 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_MEGA_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT6_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT6_MASK) + #define SRC_SETPOINT_MEGA_SETPOINT7_MASK (0x80U) #define SRC_SETPOINT_MEGA_SETPOINT7_SHIFT (7U) -/*! SETPOINT7 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT7 - SETPOINT7 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_MEGA_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT7_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT7_MASK) + #define SRC_SETPOINT_MEGA_SETPOINT8_MASK (0x100U) #define SRC_SETPOINT_MEGA_SETPOINT8_SHIFT (8U) -/*! SETPOINT8 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT8 - SETPOINT8 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_MEGA_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT8_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT8_MASK) + #define SRC_SETPOINT_MEGA_SETPOINT9_MASK (0x200U) #define SRC_SETPOINT_MEGA_SETPOINT9_SHIFT (9U) -/*! SETPOINT9 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT9 - SETPOINT9 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_MEGA_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT9_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT9_MASK) + #define SRC_SETPOINT_MEGA_SETPOINT10_MASK (0x400U) #define SRC_SETPOINT_MEGA_SETPOINT10_SHIFT (10U) -/*! SETPOINT10 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT10 - SETPOINT10 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_MEGA_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT10_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT10_MASK) + #define SRC_SETPOINT_MEGA_SETPOINT11_MASK (0x800U) #define SRC_SETPOINT_MEGA_SETPOINT11_SHIFT (11U) -/*! SETPOINT11 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT11 - SETPOINT11 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_MEGA_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT11_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT11_MASK) + #define SRC_SETPOINT_MEGA_SETPOINT12_MASK (0x1000U) #define SRC_SETPOINT_MEGA_SETPOINT12_SHIFT (12U) -/*! SETPOINT12 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT12 - SETPOINT12 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_MEGA_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT12_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT12_MASK) + #define SRC_SETPOINT_MEGA_SETPOINT13_MASK (0x2000U) #define SRC_SETPOINT_MEGA_SETPOINT13_SHIFT (13U) -/*! SETPOINT13 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT13 - SETPOINT13 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_MEGA_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT13_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT13_MASK) + #define SRC_SETPOINT_MEGA_SETPOINT14_MASK (0x4000U) #define SRC_SETPOINT_MEGA_SETPOINT14_SHIFT (14U) -/*! SETPOINT14 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT14 - SETPOINT14 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_MEGA_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT14_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT14_MASK) + #define SRC_SETPOINT_MEGA_SETPOINT15_MASK (0x8000U) #define SRC_SETPOINT_MEGA_SETPOINT15_SHIFT (15U) -/*! SETPOINT15 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT15 - SETPOINT15 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_MEGA_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT15_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT15_MASK) /*! @} */ /*! @name DOMAIN_MEGA - Slice Domain Config Register */ /*! @{ */ + #define SRC_DOMAIN_MEGA_CPU0_RUN_MASK (0x1U) #define SRC_DOMAIN_MEGA_CPU0_RUN_SHIFT (0U) -/*! CPU0_RUN - * 0b0..slice reset will be de-asserted when cpu0 in run mode - * 0b1..slice reset will be asserted when cpu0 in run mode +/*! CPU0_RUN - CPU mode setting for RUN + * 0b0..Slice reset will be de-asserted when CPU0 in RUN mode + * 0b1..Slice reset will be asserted when CPU0 in RUN mode */ #define SRC_DOMAIN_MEGA_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_RUN_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_RUN_MASK) + #define SRC_DOMAIN_MEGA_CPU0_WAIT_MASK (0x2U) #define SRC_DOMAIN_MEGA_CPU0_WAIT_SHIFT (1U) -/*! CPU0_WAIT - * 0b0..slice reset will be de-asserted when cpu0 in wait mode - * 0b1..slice reset will be asserted when cpu0 in wait mode +/*! CPU0_WAIT - CPU mode setting for WAIT + * 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode + * 0b1..Slice reset will be asserted when CPU0 in WAIT mode */ #define SRC_DOMAIN_MEGA_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_WAIT_MASK) + #define SRC_DOMAIN_MEGA_CPU0_STOP_MASK (0x4U) #define SRC_DOMAIN_MEGA_CPU0_STOP_SHIFT (2U) -/*! CPU0_STOP - * 0b0..slice reset will be de-asserted when cpu0 in stop mode - * 0b1..slice reset will be asserted when cpu0 in stop mode +/*! CPU0_STOP - CPU mode setting for STOP + * 0b0..Slice reset will be de-asserted when CPU0 in STOP mode + * 0b1..Slice reset will be asserted when CPU0 in STOP mode */ #define SRC_DOMAIN_MEGA_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_STOP_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_STOP_MASK) + #define SRC_DOMAIN_MEGA_CPU0_SUSP_MASK (0x8U) #define SRC_DOMAIN_MEGA_CPU0_SUSP_SHIFT (3U) -/*! CPU0_SUSP - * 0b0..slice reset will be de-asserted when cpu0 in suspend mode - * 0b1..slice reset will be asserted when cpu0 in suspend mode +/*! CPU0_SUSP - CPU mode setting for SUSPEND + * 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode + * 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode */ #define SRC_DOMAIN_MEGA_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_SUSP_MASK) + #define SRC_DOMAIN_MEGA_CPU1_RUN_MASK (0x10U) #define SRC_DOMAIN_MEGA_CPU1_RUN_SHIFT (4U) -/*! CPU1_RUN - * 0b0..slice reset will be de-asserted when cpu1 in run mode - * 0b1..slice reset will be asserted when cpu1 in run mode +/*! CPU1_RUN - CPU mode setting for RUN + * 0b0..Slice reset will be de-asserted when CPU1 in RUN mode + * 0b1..Slice reset will be asserted when CPU1 in RUN mode */ #define SRC_DOMAIN_MEGA_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_RUN_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_RUN_MASK) + #define SRC_DOMAIN_MEGA_CPU1_WAIT_MASK (0x20U) #define SRC_DOMAIN_MEGA_CPU1_WAIT_SHIFT (5U) -/*! CPU1_WAIT - * 0b0..slice reset will be de-asserted when cpu1 in wait mode - * 0b1..slice reset will be asserted when cpu1 in wait mode +/*! CPU1_WAIT - CPU mode setting for WAIT + * 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode + * 0b1..Slice reset will be asserted when CPU1 in WAIT mode */ #define SRC_DOMAIN_MEGA_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_WAIT_MASK) + #define SRC_DOMAIN_MEGA_CPU1_STOP_MASK (0x40U) #define SRC_DOMAIN_MEGA_CPU1_STOP_SHIFT (6U) -/*! CPU1_STOP - * 0b0..slice reset will be de-asserted when cpu1 in stop mode - * 0b1..slice reset will be asserted when cpu1 in stop mode +/*! CPU1_STOP - CPU mode setting for STOP + * 0b0..Slice reset will be de-asserted when CPU1 in STOP mode + * 0b1..Slice reset will be asserted when CPU1 in STOP mode */ #define SRC_DOMAIN_MEGA_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_STOP_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_STOP_MASK) + #define SRC_DOMAIN_MEGA_CPU1_SUSP_MASK (0x80U) #define SRC_DOMAIN_MEGA_CPU1_SUSP_SHIFT (7U) -/*! CPU1_SUSP - * 0b0..slice reset will be de-asserted when cpu1 in suspend mode - * 0b1..slice reset will be asserted when cpu1 in suspend mode +/*! CPU1_SUSP - CPU mode setting for SUSPEND + * 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode + * 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode */ #define SRC_DOMAIN_MEGA_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_SUSP_MASK) -#define SRC_DOMAIN_MEGA_CPU2_RUN_MASK (0x100U) -#define SRC_DOMAIN_MEGA_CPU2_RUN_SHIFT (8U) -/*! CPU2_RUN - * 0b0..slice reset will be de-asserted when cpu2 in run mode - * 0b1..slice reset will be asserted when cpu2 in run mode - */ -#define SRC_DOMAIN_MEGA_CPU2_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU2_RUN_SHIFT)) & SRC_DOMAIN_MEGA_CPU2_RUN_MASK) -#define SRC_DOMAIN_MEGA_CPU2_WAIT_MASK (0x200U) -#define SRC_DOMAIN_MEGA_CPU2_WAIT_SHIFT (9U) -/*! CPU2_WAIT - * 0b0..slice reset will be de-asserted when cpu2 in wait mode - * 0b1..slice reset will be asserted when cpu2 in wait mode - */ -#define SRC_DOMAIN_MEGA_CPU2_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU2_WAIT_SHIFT)) & SRC_DOMAIN_MEGA_CPU2_WAIT_MASK) -#define SRC_DOMAIN_MEGA_CPU2_STOP_MASK (0x400U) -#define SRC_DOMAIN_MEGA_CPU2_STOP_SHIFT (10U) -/*! CPU2_STOP - * 0b0..slice reset will be de-asserted when cpu2 in stop mode - * 0b1..slice reset will be asserted when cpu2 in stop mode - */ -#define SRC_DOMAIN_MEGA_CPU2_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU2_STOP_SHIFT)) & SRC_DOMAIN_MEGA_CPU2_STOP_MASK) -#define SRC_DOMAIN_MEGA_CPU2_SUSP_MASK (0x800U) -#define SRC_DOMAIN_MEGA_CPU2_SUSP_SHIFT (11U) -/*! CPU2_SUSP - * 0b0..slice reset will be de-asserted when cpu2 in suspend mode - * 0b1..slice reset will be asserted when cpu2 in suspend mode - */ -#define SRC_DOMAIN_MEGA_CPU2_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU2_SUSP_SHIFT)) & SRC_DOMAIN_MEGA_CPU2_SUSP_MASK) -#define SRC_DOMAIN_MEGA_CPU3_RUN_MASK (0x1000U) -#define SRC_DOMAIN_MEGA_CPU3_RUN_SHIFT (12U) -/*! CPU3_RUN - * 0b0..slice reset will be de-asserted when cpu3 in run mode - * 0b1..slice reset will be asserted when cpu3 in run mode - */ -#define SRC_DOMAIN_MEGA_CPU3_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU3_RUN_SHIFT)) & SRC_DOMAIN_MEGA_CPU3_RUN_MASK) -#define SRC_DOMAIN_MEGA_CPU3_WAIT_MASK (0x2000U) -#define SRC_DOMAIN_MEGA_CPU3_WAIT_SHIFT (13U) -/*! CPU3_WAIT - * 0b0..slice reset will be de-asserted when cpu3 in wait mode - * 0b1..slice reset will be asserted when cpu3 in wait mode - */ -#define SRC_DOMAIN_MEGA_CPU3_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU3_WAIT_SHIFT)) & SRC_DOMAIN_MEGA_CPU3_WAIT_MASK) -#define SRC_DOMAIN_MEGA_CPU3_STOP_MASK (0x4000U) -#define SRC_DOMAIN_MEGA_CPU3_STOP_SHIFT (14U) -/*! CPU3_STOP - * 0b0..slice reset will be de-asserted when cpu3 in stop mode - * 0b1..slice reset will be asserted when cpu3 in stop mode - */ -#define SRC_DOMAIN_MEGA_CPU3_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU3_STOP_SHIFT)) & SRC_DOMAIN_MEGA_CPU3_STOP_MASK) -#define SRC_DOMAIN_MEGA_CPU3_SUSP_MASK (0x8000U) -#define SRC_DOMAIN_MEGA_CPU3_SUSP_SHIFT (15U) -/*! CPU3_SUSP - * 0b0..slice reset will be de-asserted when cpu3 in suspend mode - * 0b1..slice reset will be asserted when cpu3 in suspend mode - */ -#define SRC_DOMAIN_MEGA_CPU3_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU3_SUSP_SHIFT)) & SRC_DOMAIN_MEGA_CPU3_SUSP_MASK) /*! @} */ /*! @name STAT_MEGA - Slice Status Register */ /*! @{ */ + #define SRC_STAT_MEGA_UNDER_RST_MASK (0x1U) #define SRC_STAT_MEGA_UNDER_RST_SHIFT (0U) /*! UNDER_RST @@ -78968,6 +88504,7 @@ typedef struct { * 0b1..the reset is in process */ #define SRC_STAT_MEGA_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_UNDER_RST_SHIFT)) & SRC_STAT_MEGA_UNDER_RST_MASK) + #define SRC_STAT_MEGA_RST_BY_HW_MASK (0x4U) #define SRC_STAT_MEGA_RST_BY_HW_SHIFT (2U) /*! RST_BY_HW @@ -78975,6 +88512,7 @@ typedef struct { * 0b1..the reset is caused by the power mode transfer */ #define SRC_STAT_MEGA_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_RST_BY_HW_SHIFT)) & SRC_STAT_MEGA_RST_BY_HW_MASK) + #define SRC_STAT_MEGA_RST_BY_SW_MASK (0x8U) #define SRC_STAT_MEGA_RST_BY_SW_SHIFT (3U) /*! RST_BY_SW @@ -78986,53 +88524,63 @@ typedef struct { /*! @name AUTHEN_DISPLAY - Slice Authentication Register */ /*! @{ */ + #define SRC_AUTHEN_DISPLAY_DOMAIN_MODE_MASK (0x1U) #define SRC_AUTHEN_DISPLAY_DOMAIN_MODE_SHIFT (0U) /*! DOMAIN_MODE - * 0b0..slice hardware reset will Not be triggered by cpu power mode transition - * 0b1..slice hardware reset will be triggered by cpu power mode transition. Do not set this bit and SETPOINT_MODE at the same time. + * 0b0..slice hardware reset will NOT be triggered by CPU power mode transition + * 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time. */ #define SRC_AUTHEN_DISPLAY_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_DOMAIN_MODE_MASK) + #define SRC_AUTHEN_DISPLAY_SETPOINT_MODE_MASK (0x2U) #define SRC_AUTHEN_DISPLAY_SETPOINT_MODE_SHIFT (1U) /*! SETPOINT_MODE - * 0b0..slice hardware reset will Not be triggered by set point transition - * 0b1..slice hardware reset will be triggered by set point transition. Do not set this bit and DOMAIN_MODE at the same time. + * 0b0..slice hardware reset will NOT be triggered by Setpoint transition + * 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time. */ #define SRC_AUTHEN_DISPLAY_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_SETPOINT_MODE_MASK) + #define SRC_AUTHEN_DISPLAY_LOCK_MODE_MASK (0x80U) #define SRC_AUTHEN_DISPLAY_LOCK_MODE_SHIFT (7U) -/*! LOCK_MODE - domain/setpoint mode lock +/*! LOCK_MODE - Domain/Setpoint mode lock */ #define SRC_AUTHEN_DISPLAY_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_MODE_MASK) + #define SRC_AUTHEN_DISPLAY_ASSIGN_LIST_MASK (0xF00U) #define SRC_AUTHEN_DISPLAY_ASSIGN_LIST_SHIFT (8U) #define SRC_AUTHEN_DISPLAY_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_ASSIGN_LIST_MASK) + #define SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_MASK (0x8000U) #define SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_SHIFT (15U) /*! LOCK_ASSIGN - Assign list lock */ #define SRC_AUTHEN_DISPLAY_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_MASK) + #define SRC_AUTHEN_DISPLAY_WHITE_LIST_MASK (0xF0000U) #define SRC_AUTHEN_DISPLAY_WHITE_LIST_SHIFT (16U) /*! WHITE_LIST - Domain ID white list */ #define SRC_AUTHEN_DISPLAY_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_WHITE_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_WHITE_LIST_MASK) + #define SRC_AUTHEN_DISPLAY_LOCK_LIST_MASK (0x800000U) #define SRC_AUTHEN_DISPLAY_LOCK_LIST_SHIFT (23U) /*! LOCK_LIST - White list lock */ #define SRC_AUTHEN_DISPLAY_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_LIST_MASK) + #define SRC_AUTHEN_DISPLAY_USER_MASK (0x1000000U) #define SRC_AUTHEN_DISPLAY_USER_SHIFT (24U) /*! USER - Allow user mode access */ #define SRC_AUTHEN_DISPLAY_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_USER_SHIFT)) & SRC_AUTHEN_DISPLAY_USER_MASK) + #define SRC_AUTHEN_DISPLAY_NONSECURE_MASK (0x2000000U) #define SRC_AUTHEN_DISPLAY_NONSECURE_SHIFT (25U) /*! NONSECURE - Allow non-secure mode access */ #define SRC_AUTHEN_DISPLAY_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_NONSECURE_SHIFT)) & SRC_AUTHEN_DISPLAY_NONSECURE_MASK) + #define SRC_AUTHEN_DISPLAY_LOCK_SETTING_MASK (0x80000000U) #define SRC_AUTHEN_DISPLAY_LOCK_SETTING_SHIFT (31U) /*! LOCK_SETTING - Lock NONSECURE and USER @@ -79042,6 +88590,7 @@ typedef struct { /*! @name CTRL_DISPLAY - Slice Control Register */ /*! @{ */ + #define SRC_CTRL_DISPLAY_SW_RESET_MASK (0x1U) #define SRC_CTRL_DISPLAY_SW_RESET_SHIFT (0U) /*! SW_RESET @@ -79051,240 +88600,209 @@ typedef struct { #define SRC_CTRL_DISPLAY_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_DISPLAY_SW_RESET_SHIFT)) & SRC_CTRL_DISPLAY_SW_RESET_MASK) /*! @} */ -/*! @name SETPOINT_DISPLAY - Slice SetPoint Config Register */ +/*! @name SETPOINT_DISPLAY - Slice Setpoint Config Register */ /*! @{ */ + #define SRC_SETPOINT_DISPLAY_SETPOINT0_MASK (0x1U) #define SRC_SETPOINT_DISPLAY_SETPOINT0_SHIFT (0U) -/*! SETPOINT0 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT0 - SETPOINT0 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_DISPLAY_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT0_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT0_MASK) + #define SRC_SETPOINT_DISPLAY_SETPOINT1_MASK (0x2U) #define SRC_SETPOINT_DISPLAY_SETPOINT1_SHIFT (1U) -/*! SETPOINT1 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT1 - SETPOINT1 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_DISPLAY_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT1_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT1_MASK) + #define SRC_SETPOINT_DISPLAY_SETPOINT2_MASK (0x4U) #define SRC_SETPOINT_DISPLAY_SETPOINT2_SHIFT (2U) -/*! SETPOINT2 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT2 - SETPOINT2 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_DISPLAY_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT2_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT2_MASK) + #define SRC_SETPOINT_DISPLAY_SETPOINT3_MASK (0x8U) #define SRC_SETPOINT_DISPLAY_SETPOINT3_SHIFT (3U) -/*! SETPOINT3 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT3 - SETPOINT3 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_DISPLAY_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT3_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT3_MASK) + #define SRC_SETPOINT_DISPLAY_SETPOINT4_MASK (0x10U) #define SRC_SETPOINT_DISPLAY_SETPOINT4_SHIFT (4U) -/*! SETPOINT4 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT4 - SETPOINT4 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_DISPLAY_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT4_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT4_MASK) + #define SRC_SETPOINT_DISPLAY_SETPOINT5_MASK (0x20U) #define SRC_SETPOINT_DISPLAY_SETPOINT5_SHIFT (5U) -/*! SETPOINT5 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT5 - SETPOINT5 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_DISPLAY_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT5_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT5_MASK) + #define SRC_SETPOINT_DISPLAY_SETPOINT6_MASK (0x40U) #define SRC_SETPOINT_DISPLAY_SETPOINT6_SHIFT (6U) -/*! SETPOINT6 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT6 - SETPOINT6 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_DISPLAY_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT6_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT6_MASK) + #define SRC_SETPOINT_DISPLAY_SETPOINT7_MASK (0x80U) #define SRC_SETPOINT_DISPLAY_SETPOINT7_SHIFT (7U) -/*! SETPOINT7 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT7 - SETPOINT7 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_DISPLAY_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT7_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT7_MASK) + #define SRC_SETPOINT_DISPLAY_SETPOINT8_MASK (0x100U) #define SRC_SETPOINT_DISPLAY_SETPOINT8_SHIFT (8U) -/*! SETPOINT8 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT8 - SETPOINT8 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_DISPLAY_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT8_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT8_MASK) + #define SRC_SETPOINT_DISPLAY_SETPOINT9_MASK (0x200U) #define SRC_SETPOINT_DISPLAY_SETPOINT9_SHIFT (9U) -/*! SETPOINT9 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT9 - SETPOINT9 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_DISPLAY_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT9_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT9_MASK) + #define SRC_SETPOINT_DISPLAY_SETPOINT10_MASK (0x400U) #define SRC_SETPOINT_DISPLAY_SETPOINT10_SHIFT (10U) -/*! SETPOINT10 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT10 - SETPOINT10 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_DISPLAY_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT10_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT10_MASK) + #define SRC_SETPOINT_DISPLAY_SETPOINT11_MASK (0x800U) #define SRC_SETPOINT_DISPLAY_SETPOINT11_SHIFT (11U) -/*! SETPOINT11 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT11 - SETPOINT11 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_DISPLAY_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT11_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT11_MASK) + #define SRC_SETPOINT_DISPLAY_SETPOINT12_MASK (0x1000U) #define SRC_SETPOINT_DISPLAY_SETPOINT12_SHIFT (12U) -/*! SETPOINT12 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT12 - SETPOINT12 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_DISPLAY_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT12_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT12_MASK) + #define SRC_SETPOINT_DISPLAY_SETPOINT13_MASK (0x2000U) #define SRC_SETPOINT_DISPLAY_SETPOINT13_SHIFT (13U) -/*! SETPOINT13 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT13 - SETPOINT13 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_DISPLAY_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT13_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT13_MASK) + #define SRC_SETPOINT_DISPLAY_SETPOINT14_MASK (0x4000U) #define SRC_SETPOINT_DISPLAY_SETPOINT14_SHIFT (14U) -/*! SETPOINT14 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT14 - SETPOINT14 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_DISPLAY_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT14_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT14_MASK) + #define SRC_SETPOINT_DISPLAY_SETPOINT15_MASK (0x8000U) #define SRC_SETPOINT_DISPLAY_SETPOINT15_SHIFT (15U) -/*! SETPOINT15 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT15 - SETPOINT15 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_DISPLAY_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT15_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT15_MASK) /*! @} */ /*! @name DOMAIN_DISPLAY - Slice Domain Config Register */ /*! @{ */ + #define SRC_DOMAIN_DISPLAY_CPU0_RUN_MASK (0x1U) #define SRC_DOMAIN_DISPLAY_CPU0_RUN_SHIFT (0U) -/*! CPU0_RUN - * 0b0..slice reset will be de-asserted when cpu0 in run mode - * 0b1..slice reset will be asserted when cpu0 in run mode +/*! CPU0_RUN - CPU mode setting for RUN + * 0b0..Slice reset will be de-asserted when CPU0 in RUN mode + * 0b1..Slice reset will be asserted when CPU0 in RUN mode */ #define SRC_DOMAIN_DISPLAY_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_RUN_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_RUN_MASK) + #define SRC_DOMAIN_DISPLAY_CPU0_WAIT_MASK (0x2U) #define SRC_DOMAIN_DISPLAY_CPU0_WAIT_SHIFT (1U) -/*! CPU0_WAIT - * 0b0..slice reset will be de-asserted when cpu0 in wait mode - * 0b1..slice reset will be asserted when cpu0 in wait mode +/*! CPU0_WAIT - CPU mode setting for WAIT + * 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode + * 0b1..Slice reset will be asserted when CPU0 in WAIT mode */ #define SRC_DOMAIN_DISPLAY_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_WAIT_MASK) + #define SRC_DOMAIN_DISPLAY_CPU0_STOP_MASK (0x4U) #define SRC_DOMAIN_DISPLAY_CPU0_STOP_SHIFT (2U) -/*! CPU0_STOP - * 0b0..slice reset will be de-asserted when cpu0 in stop mode - * 0b1..slice reset will be asserted when cpu0 in stop mode +/*! CPU0_STOP - CPU mode setting for STOP + * 0b0..Slice reset will be de-asserted when CPU0 in STOP mode + * 0b1..Slice reset will be asserted when CPU0 in STOP mode */ #define SRC_DOMAIN_DISPLAY_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_STOP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_STOP_MASK) + #define SRC_DOMAIN_DISPLAY_CPU0_SUSP_MASK (0x8U) #define SRC_DOMAIN_DISPLAY_CPU0_SUSP_SHIFT (3U) -/*! CPU0_SUSP - * 0b0..slice reset will be de-asserted when cpu0 in suspend mode - * 0b1..slice reset will be asserted when cpu0 in suspend mode +/*! CPU0_SUSP - CPU mode setting for SUSPEND + * 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode + * 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode */ #define SRC_DOMAIN_DISPLAY_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_SUSP_MASK) + #define SRC_DOMAIN_DISPLAY_CPU1_RUN_MASK (0x10U) #define SRC_DOMAIN_DISPLAY_CPU1_RUN_SHIFT (4U) -/*! CPU1_RUN - * 0b0..slice reset will be de-asserted when cpu1 in run mode - * 0b1..slice reset will be asserted when cpu1 in run mode +/*! CPU1_RUN - CPU mode setting for RUN + * 0b0..Slice reset will be de-asserted when CPU1 in RUN mode + * 0b1..Slice reset will be asserted when CPU1 in RUN mode */ #define SRC_DOMAIN_DISPLAY_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_RUN_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_RUN_MASK) + #define SRC_DOMAIN_DISPLAY_CPU1_WAIT_MASK (0x20U) #define SRC_DOMAIN_DISPLAY_CPU1_WAIT_SHIFT (5U) -/*! CPU1_WAIT - * 0b0..slice reset will be de-asserted when cpu1 in wait mode - * 0b1..slice reset will be asserted when cpu1 in wait mode +/*! CPU1_WAIT - CPU mode setting for WAIT + * 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode + * 0b1..Slice reset will be asserted when CPU1 in WAIT mode */ #define SRC_DOMAIN_DISPLAY_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_WAIT_MASK) + #define SRC_DOMAIN_DISPLAY_CPU1_STOP_MASK (0x40U) #define SRC_DOMAIN_DISPLAY_CPU1_STOP_SHIFT (6U) -/*! CPU1_STOP - * 0b0..slice reset will be de-asserted when cpu1 in stop mode - * 0b1..slice reset will be asserted when cpu1 in stop mode +/*! CPU1_STOP - CPU mode setting for STOP + * 0b0..Slice reset will be de-asserted when CPU1 in STOP mode + * 0b1..Slice reset will be asserted when CPU1 in STOP mode */ #define SRC_DOMAIN_DISPLAY_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_STOP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_STOP_MASK) + #define SRC_DOMAIN_DISPLAY_CPU1_SUSP_MASK (0x80U) #define SRC_DOMAIN_DISPLAY_CPU1_SUSP_SHIFT (7U) -/*! CPU1_SUSP - * 0b0..slice reset will be de-asserted when cpu1 in suspend mode - * 0b1..slice reset will be asserted when cpu1 in suspend mode +/*! CPU1_SUSP - CPU mode setting for SUSPEND + * 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode + * 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode */ #define SRC_DOMAIN_DISPLAY_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_SUSP_MASK) -#define SRC_DOMAIN_DISPLAY_CPU2_RUN_MASK (0x100U) -#define SRC_DOMAIN_DISPLAY_CPU2_RUN_SHIFT (8U) -/*! CPU2_RUN - * 0b0..slice reset will be de-asserted when cpu2 in run mode - * 0b1..slice reset will be asserted when cpu2 in run mode - */ -#define SRC_DOMAIN_DISPLAY_CPU2_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU2_RUN_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU2_RUN_MASK) -#define SRC_DOMAIN_DISPLAY_CPU2_WAIT_MASK (0x200U) -#define SRC_DOMAIN_DISPLAY_CPU2_WAIT_SHIFT (9U) -/*! CPU2_WAIT - * 0b0..slice reset will be de-asserted when cpu2 in wait mode - * 0b1..slice reset will be asserted when cpu2 in wait mode - */ -#define SRC_DOMAIN_DISPLAY_CPU2_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU2_WAIT_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU2_WAIT_MASK) -#define SRC_DOMAIN_DISPLAY_CPU2_STOP_MASK (0x400U) -#define SRC_DOMAIN_DISPLAY_CPU2_STOP_SHIFT (10U) -/*! CPU2_STOP - * 0b0..slice reset will be de-asserted when cpu2 in stop mode - * 0b1..slice reset will be asserted when cpu2 in stop mode - */ -#define SRC_DOMAIN_DISPLAY_CPU2_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU2_STOP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU2_STOP_MASK) -#define SRC_DOMAIN_DISPLAY_CPU2_SUSP_MASK (0x800U) -#define SRC_DOMAIN_DISPLAY_CPU2_SUSP_SHIFT (11U) -/*! CPU2_SUSP - * 0b0..slice reset will be de-asserted when cpu2 in suspend mode - * 0b1..slice reset will be asserted when cpu2 in suspend mode - */ -#define SRC_DOMAIN_DISPLAY_CPU2_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU2_SUSP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU2_SUSP_MASK) -#define SRC_DOMAIN_DISPLAY_CPU3_RUN_MASK (0x1000U) -#define SRC_DOMAIN_DISPLAY_CPU3_RUN_SHIFT (12U) -/*! CPU3_RUN - * 0b0..slice reset will be de-asserted when cpu3 in run mode - * 0b1..slice reset will be asserted when cpu3 in run mode - */ -#define SRC_DOMAIN_DISPLAY_CPU3_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU3_RUN_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU3_RUN_MASK) -#define SRC_DOMAIN_DISPLAY_CPU3_WAIT_MASK (0x2000U) -#define SRC_DOMAIN_DISPLAY_CPU3_WAIT_SHIFT (13U) -/*! CPU3_WAIT - * 0b0..slice reset will be de-asserted when cpu3 in wait mode - * 0b1..slice reset will be asserted when cpu3 in wait mode - */ -#define SRC_DOMAIN_DISPLAY_CPU3_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU3_WAIT_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU3_WAIT_MASK) -#define SRC_DOMAIN_DISPLAY_CPU3_STOP_MASK (0x4000U) -#define SRC_DOMAIN_DISPLAY_CPU3_STOP_SHIFT (14U) -/*! CPU3_STOP - * 0b0..slice reset will be de-asserted when cpu3 in stop mode - * 0b1..slice reset will be asserted when cpu3 in stop mode - */ -#define SRC_DOMAIN_DISPLAY_CPU3_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU3_STOP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU3_STOP_MASK) -#define SRC_DOMAIN_DISPLAY_CPU3_SUSP_MASK (0x8000U) -#define SRC_DOMAIN_DISPLAY_CPU3_SUSP_SHIFT (15U) -/*! CPU3_SUSP - * 0b0..slice reset will be de-asserted when cpu3 in suspend mode - * 0b1..slice reset will be asserted when cpu3 in suspend mode - */ -#define SRC_DOMAIN_DISPLAY_CPU3_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU3_SUSP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU3_SUSP_MASK) /*! @} */ /*! @name STAT_DISPLAY - Slice Status Register */ /*! @{ */ + #define SRC_STAT_DISPLAY_UNDER_RST_MASK (0x1U) #define SRC_STAT_DISPLAY_UNDER_RST_SHIFT (0U) /*! UNDER_RST @@ -79292,6 +88810,7 @@ typedef struct { * 0b1..the reset is in process */ #define SRC_STAT_DISPLAY_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_UNDER_RST_SHIFT)) & SRC_STAT_DISPLAY_UNDER_RST_MASK) + #define SRC_STAT_DISPLAY_RST_BY_HW_MASK (0x4U) #define SRC_STAT_DISPLAY_RST_BY_HW_SHIFT (2U) /*! RST_BY_HW @@ -79299,6 +88818,7 @@ typedef struct { * 0b1..the reset is caused by the power mode transfer */ #define SRC_STAT_DISPLAY_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_RST_BY_HW_SHIFT)) & SRC_STAT_DISPLAY_RST_BY_HW_MASK) + #define SRC_STAT_DISPLAY_RST_BY_SW_MASK (0x8U) #define SRC_STAT_DISPLAY_RST_BY_SW_SHIFT (3U) /*! RST_BY_SW @@ -79310,53 +88830,63 @@ typedef struct { /*! @name AUTHEN_WAKEUP - Slice Authentication Register */ /*! @{ */ + #define SRC_AUTHEN_WAKEUP_DOMAIN_MODE_MASK (0x1U) #define SRC_AUTHEN_WAKEUP_DOMAIN_MODE_SHIFT (0U) /*! DOMAIN_MODE - * 0b0..slice hardware reset will Not be triggered by cpu power mode transition - * 0b1..slice hardware reset will be triggered by cpu power mode transition. Do not set this bit and SETPOINT_MODE at the same time. + * 0b0..slice hardware reset will NOT be triggered by CPU power mode transition + * 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time. */ #define SRC_AUTHEN_WAKEUP_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_DOMAIN_MODE_MASK) + #define SRC_AUTHEN_WAKEUP_SETPOINT_MODE_MASK (0x2U) #define SRC_AUTHEN_WAKEUP_SETPOINT_MODE_SHIFT (1U) /*! SETPOINT_MODE - * 0b0..slice hardware reset will Not be triggered by set point transition - * 0b1..slice hardware reset will be triggered by set point transition. Do not set this bit and DOMAIN_MODE at the same time. + * 0b0..slice hardware reset will NOT be triggered by Setpoint transition + * 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time. */ #define SRC_AUTHEN_WAKEUP_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_SETPOINT_MODE_MASK) + #define SRC_AUTHEN_WAKEUP_LOCK_MODE_MASK (0x80U) #define SRC_AUTHEN_WAKEUP_LOCK_MODE_SHIFT (7U) -/*! LOCK_MODE - domain/setpoint mode lock +/*! LOCK_MODE - Domain/Setpoint mode lock */ #define SRC_AUTHEN_WAKEUP_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_MODE_MASK) + #define SRC_AUTHEN_WAKEUP_ASSIGN_LIST_MASK (0xF00U) #define SRC_AUTHEN_WAKEUP_ASSIGN_LIST_SHIFT (8U) #define SRC_AUTHEN_WAKEUP_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_ASSIGN_LIST_MASK) + #define SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_MASK (0x8000U) #define SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_SHIFT (15U) /*! LOCK_ASSIGN - Assign list lock */ #define SRC_AUTHEN_WAKEUP_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_MASK) + #define SRC_AUTHEN_WAKEUP_WHITE_LIST_MASK (0xF0000U) #define SRC_AUTHEN_WAKEUP_WHITE_LIST_SHIFT (16U) /*! WHITE_LIST - Domain ID white list */ #define SRC_AUTHEN_WAKEUP_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_WHITE_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_WHITE_LIST_MASK) + #define SRC_AUTHEN_WAKEUP_LOCK_LIST_MASK (0x800000U) #define SRC_AUTHEN_WAKEUP_LOCK_LIST_SHIFT (23U) /*! LOCK_LIST - White list lock */ #define SRC_AUTHEN_WAKEUP_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_LIST_MASK) + #define SRC_AUTHEN_WAKEUP_USER_MASK (0x1000000U) #define SRC_AUTHEN_WAKEUP_USER_SHIFT (24U) /*! USER - Allow user mode access */ #define SRC_AUTHEN_WAKEUP_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_USER_SHIFT)) & SRC_AUTHEN_WAKEUP_USER_MASK) + #define SRC_AUTHEN_WAKEUP_NONSECURE_MASK (0x2000000U) #define SRC_AUTHEN_WAKEUP_NONSECURE_SHIFT (25U) /*! NONSECURE - Allow non-secure mode access */ #define SRC_AUTHEN_WAKEUP_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_NONSECURE_SHIFT)) & SRC_AUTHEN_WAKEUP_NONSECURE_MASK) + #define SRC_AUTHEN_WAKEUP_LOCK_SETTING_MASK (0x80000000U) #define SRC_AUTHEN_WAKEUP_LOCK_SETTING_SHIFT (31U) /*! LOCK_SETTING - Lock NONSECURE and USER @@ -79366,6 +88896,7 @@ typedef struct { /*! @name CTRL_WAKEUP - Slice Control Register */ /*! @{ */ + #define SRC_CTRL_WAKEUP_SW_RESET_MASK (0x1U) #define SRC_CTRL_WAKEUP_SW_RESET_SHIFT (0U) /*! SW_RESET @@ -79375,240 +88906,209 @@ typedef struct { #define SRC_CTRL_WAKEUP_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_WAKEUP_SW_RESET_SHIFT)) & SRC_CTRL_WAKEUP_SW_RESET_MASK) /*! @} */ -/*! @name SETPOINT_WAKEUP - Slice SetPoint Config Register */ +/*! @name SETPOINT_WAKEUP - Slice Setpoint Config Register */ /*! @{ */ + #define SRC_SETPOINT_WAKEUP_SETPOINT0_MASK (0x1U) #define SRC_SETPOINT_WAKEUP_SETPOINT0_SHIFT (0U) -/*! SETPOINT0 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT0 - SETPOINT0 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_WAKEUP_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT0_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT0_MASK) + #define SRC_SETPOINT_WAKEUP_SETPOINT1_MASK (0x2U) #define SRC_SETPOINT_WAKEUP_SETPOINT1_SHIFT (1U) -/*! SETPOINT1 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT1 - SETPOINT1 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_WAKEUP_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT1_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT1_MASK) + #define SRC_SETPOINT_WAKEUP_SETPOINT2_MASK (0x4U) #define SRC_SETPOINT_WAKEUP_SETPOINT2_SHIFT (2U) -/*! SETPOINT2 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT2 - SETPOINT2 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_WAKEUP_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT2_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT2_MASK) + #define SRC_SETPOINT_WAKEUP_SETPOINT3_MASK (0x8U) #define SRC_SETPOINT_WAKEUP_SETPOINT3_SHIFT (3U) -/*! SETPOINT3 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT3 - SETPOINT3 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_WAKEUP_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT3_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT3_MASK) + #define SRC_SETPOINT_WAKEUP_SETPOINT4_MASK (0x10U) #define SRC_SETPOINT_WAKEUP_SETPOINT4_SHIFT (4U) -/*! SETPOINT4 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT4 - SETPOINT4 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_WAKEUP_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT4_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT4_MASK) + #define SRC_SETPOINT_WAKEUP_SETPOINT5_MASK (0x20U) #define SRC_SETPOINT_WAKEUP_SETPOINT5_SHIFT (5U) -/*! SETPOINT5 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT5 - SETPOINT5 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_WAKEUP_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT5_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT5_MASK) + #define SRC_SETPOINT_WAKEUP_SETPOINT6_MASK (0x40U) #define SRC_SETPOINT_WAKEUP_SETPOINT6_SHIFT (6U) -/*! SETPOINT6 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT6 - SETPOINT6 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_WAKEUP_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT6_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT6_MASK) + #define SRC_SETPOINT_WAKEUP_SETPOINT7_MASK (0x80U) #define SRC_SETPOINT_WAKEUP_SETPOINT7_SHIFT (7U) -/*! SETPOINT7 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT7 - SETPOINT7 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_WAKEUP_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT7_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT7_MASK) + #define SRC_SETPOINT_WAKEUP_SETPOINT8_MASK (0x100U) #define SRC_SETPOINT_WAKEUP_SETPOINT8_SHIFT (8U) -/*! SETPOINT8 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT8 - SETPOINT8 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_WAKEUP_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT8_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT8_MASK) + #define SRC_SETPOINT_WAKEUP_SETPOINT9_MASK (0x200U) #define SRC_SETPOINT_WAKEUP_SETPOINT9_SHIFT (9U) -/*! SETPOINT9 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT9 - SETPOINT9 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_WAKEUP_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT9_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT9_MASK) + #define SRC_SETPOINT_WAKEUP_SETPOINT10_MASK (0x400U) #define SRC_SETPOINT_WAKEUP_SETPOINT10_SHIFT (10U) -/*! SETPOINT10 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT10 - SETPOINT10 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_WAKEUP_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT10_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT10_MASK) + #define SRC_SETPOINT_WAKEUP_SETPOINT11_MASK (0x800U) #define SRC_SETPOINT_WAKEUP_SETPOINT11_SHIFT (11U) -/*! SETPOINT11 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT11 - SETPOINT11 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_WAKEUP_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT11_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT11_MASK) + #define SRC_SETPOINT_WAKEUP_SETPOINT12_MASK (0x1000U) #define SRC_SETPOINT_WAKEUP_SETPOINT12_SHIFT (12U) -/*! SETPOINT12 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT12 - SETPOINT12 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_WAKEUP_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT12_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT12_MASK) + #define SRC_SETPOINT_WAKEUP_SETPOINT13_MASK (0x2000U) #define SRC_SETPOINT_WAKEUP_SETPOINT13_SHIFT (13U) -/*! SETPOINT13 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT13 - SETPOINT13 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_WAKEUP_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT13_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT13_MASK) + #define SRC_SETPOINT_WAKEUP_SETPOINT14_MASK (0x4000U) #define SRC_SETPOINT_WAKEUP_SETPOINT14_SHIFT (14U) -/*! SETPOINT14 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT14 - SETPOINT14 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_WAKEUP_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT14_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT14_MASK) + #define SRC_SETPOINT_WAKEUP_SETPOINT15_MASK (0x8000U) #define SRC_SETPOINT_WAKEUP_SETPOINT15_SHIFT (15U) -/*! SETPOINT15 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT15 - SETPOINT15 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_WAKEUP_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT15_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT15_MASK) /*! @} */ /*! @name DOMAIN_WAKEUP - Slice Domain Config Register */ /*! @{ */ + #define SRC_DOMAIN_WAKEUP_CPU0_RUN_MASK (0x1U) #define SRC_DOMAIN_WAKEUP_CPU0_RUN_SHIFT (0U) -/*! CPU0_RUN - * 0b0..slice reset will be de-asserted when cpu0 in run mode - * 0b1..slice reset will be asserted when cpu0 in run mode +/*! CPU0_RUN - CPU mode setting for RUN + * 0b0..Slice reset will be de-asserted when CPU0 in RUN mode + * 0b1..Slice reset will be asserted when CPU0 in RUN mode */ #define SRC_DOMAIN_WAKEUP_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_RUN_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_RUN_MASK) + #define SRC_DOMAIN_WAKEUP_CPU0_WAIT_MASK (0x2U) #define SRC_DOMAIN_WAKEUP_CPU0_WAIT_SHIFT (1U) -/*! CPU0_WAIT - * 0b0..slice reset will be de-asserted when cpu0 in wait mode - * 0b1..slice reset will be asserted when cpu0 in wait mode +/*! CPU0_WAIT - CPU mode setting for WAIT + * 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode + * 0b1..Slice reset will be asserted when CPU0 in WAIT mode */ #define SRC_DOMAIN_WAKEUP_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_WAIT_MASK) + #define SRC_DOMAIN_WAKEUP_CPU0_STOP_MASK (0x4U) #define SRC_DOMAIN_WAKEUP_CPU0_STOP_SHIFT (2U) -/*! CPU0_STOP - * 0b0..slice reset will be de-asserted when cpu0 in stop mode - * 0b1..slice reset will be asserted when cpu0 in stop mode +/*! CPU0_STOP - CPU mode setting for STOP + * 0b0..Slice reset will be de-asserted when CPU0 in STOP mode + * 0b1..Slice reset will be asserted when CPU0 in STOP mode */ #define SRC_DOMAIN_WAKEUP_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_STOP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_STOP_MASK) + #define SRC_DOMAIN_WAKEUP_CPU0_SUSP_MASK (0x8U) #define SRC_DOMAIN_WAKEUP_CPU0_SUSP_SHIFT (3U) -/*! CPU0_SUSP - * 0b0..slice reset will be de-asserted when cpu0 in suspend mode - * 0b1..slice reset will be asserted when cpu0 in suspend mode +/*! CPU0_SUSP - CPU mode setting for SUSPEND + * 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode + * 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode */ #define SRC_DOMAIN_WAKEUP_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_SUSP_MASK) + #define SRC_DOMAIN_WAKEUP_CPU1_RUN_MASK (0x10U) #define SRC_DOMAIN_WAKEUP_CPU1_RUN_SHIFT (4U) -/*! CPU1_RUN - * 0b0..slice reset will be de-asserted when cpu1 in run mode - * 0b1..slice reset will be asserted when cpu1 in run mode +/*! CPU1_RUN - CPU mode setting for RUN + * 0b0..Slice reset will be de-asserted when CPU1 in RUN mode + * 0b1..Slice reset will be asserted when CPU1 in RUN mode */ #define SRC_DOMAIN_WAKEUP_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_RUN_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_RUN_MASK) + #define SRC_DOMAIN_WAKEUP_CPU1_WAIT_MASK (0x20U) #define SRC_DOMAIN_WAKEUP_CPU1_WAIT_SHIFT (5U) -/*! CPU1_WAIT - * 0b0..slice reset will be de-asserted when cpu1 in wait mode - * 0b1..slice reset will be asserted when cpu1 in wait mode +/*! CPU1_WAIT - CPU mode setting for WAIT + * 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode + * 0b1..Slice reset will be asserted when CPU1 in WAIT mode */ #define SRC_DOMAIN_WAKEUP_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_WAIT_MASK) + #define SRC_DOMAIN_WAKEUP_CPU1_STOP_MASK (0x40U) #define SRC_DOMAIN_WAKEUP_CPU1_STOP_SHIFT (6U) -/*! CPU1_STOP - * 0b0..slice reset will be de-asserted when cpu1 in stop mode - * 0b1..slice reset will be asserted when cpu1 in stop mode +/*! CPU1_STOP - CPU mode setting for STOP + * 0b0..Slice reset will be de-asserted when CPU1 in STOP mode + * 0b1..Slice reset will be asserted when CPU1 in STOP mode */ #define SRC_DOMAIN_WAKEUP_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_STOP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_STOP_MASK) + #define SRC_DOMAIN_WAKEUP_CPU1_SUSP_MASK (0x80U) #define SRC_DOMAIN_WAKEUP_CPU1_SUSP_SHIFT (7U) -/*! CPU1_SUSP - * 0b0..slice reset will be de-asserted when cpu1 in suspend mode - * 0b1..slice reset will be asserted when cpu1 in suspend mode +/*! CPU1_SUSP - CPU mode setting for SUSPEND + * 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode + * 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode */ #define SRC_DOMAIN_WAKEUP_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_SUSP_MASK) -#define SRC_DOMAIN_WAKEUP_CPU2_RUN_MASK (0x100U) -#define SRC_DOMAIN_WAKEUP_CPU2_RUN_SHIFT (8U) -/*! CPU2_RUN - * 0b0..slice reset will be de-asserted when cpu2 in run mode - * 0b1..slice reset will be asserted when cpu2 in run mode - */ -#define SRC_DOMAIN_WAKEUP_CPU2_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU2_RUN_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU2_RUN_MASK) -#define SRC_DOMAIN_WAKEUP_CPU2_WAIT_MASK (0x200U) -#define SRC_DOMAIN_WAKEUP_CPU2_WAIT_SHIFT (9U) -/*! CPU2_WAIT - * 0b0..slice reset will be de-asserted when cpu2 in wait mode - * 0b1..slice reset will be asserted when cpu2 in wait mode - */ -#define SRC_DOMAIN_WAKEUP_CPU2_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU2_WAIT_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU2_WAIT_MASK) -#define SRC_DOMAIN_WAKEUP_CPU2_STOP_MASK (0x400U) -#define SRC_DOMAIN_WAKEUP_CPU2_STOP_SHIFT (10U) -/*! CPU2_STOP - * 0b0..slice reset will be de-asserted when cpu2 in stop mode - * 0b1..slice reset will be asserted when cpu2 in stop mode - */ -#define SRC_DOMAIN_WAKEUP_CPU2_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU2_STOP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU2_STOP_MASK) -#define SRC_DOMAIN_WAKEUP_CPU2_SUSP_MASK (0x800U) -#define SRC_DOMAIN_WAKEUP_CPU2_SUSP_SHIFT (11U) -/*! CPU2_SUSP - * 0b0..slice reset will be de-asserted when cpu2 in suspend mode - * 0b1..slice reset will be asserted when cpu2 in suspend mode - */ -#define SRC_DOMAIN_WAKEUP_CPU2_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU2_SUSP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU2_SUSP_MASK) -#define SRC_DOMAIN_WAKEUP_CPU3_RUN_MASK (0x1000U) -#define SRC_DOMAIN_WAKEUP_CPU3_RUN_SHIFT (12U) -/*! CPU3_RUN - * 0b0..slice reset will be de-asserted when cpu3 in run mode - * 0b1..slice reset will be asserted when cpu3 in run mode - */ -#define SRC_DOMAIN_WAKEUP_CPU3_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU3_RUN_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU3_RUN_MASK) -#define SRC_DOMAIN_WAKEUP_CPU3_WAIT_MASK (0x2000U) -#define SRC_DOMAIN_WAKEUP_CPU3_WAIT_SHIFT (13U) -/*! CPU3_WAIT - * 0b0..slice reset will be de-asserted when cpu3 in wait mode - * 0b1..slice reset will be asserted when cpu3 in wait mode - */ -#define SRC_DOMAIN_WAKEUP_CPU3_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU3_WAIT_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU3_WAIT_MASK) -#define SRC_DOMAIN_WAKEUP_CPU3_STOP_MASK (0x4000U) -#define SRC_DOMAIN_WAKEUP_CPU3_STOP_SHIFT (14U) -/*! CPU3_STOP - * 0b0..slice reset will be de-asserted when cpu3 in stop mode - * 0b1..slice reset will be asserted when cpu3 in stop mode - */ -#define SRC_DOMAIN_WAKEUP_CPU3_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU3_STOP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU3_STOP_MASK) -#define SRC_DOMAIN_WAKEUP_CPU3_SUSP_MASK (0x8000U) -#define SRC_DOMAIN_WAKEUP_CPU3_SUSP_SHIFT (15U) -/*! CPU3_SUSP - * 0b0..slice reset will be de-asserted when cpu3 in suspend mode - * 0b1..slice reset will be asserted when cpu3 in suspend mode - */ -#define SRC_DOMAIN_WAKEUP_CPU3_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU3_SUSP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU3_SUSP_MASK) /*! @} */ /*! @name STAT_WAKEUP - Slice Status Register */ /*! @{ */ + #define SRC_STAT_WAKEUP_UNDER_RST_MASK (0x1U) #define SRC_STAT_WAKEUP_UNDER_RST_SHIFT (0U) /*! UNDER_RST @@ -79616,6 +89116,7 @@ typedef struct { * 0b1..the reset is in process */ #define SRC_STAT_WAKEUP_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_UNDER_RST_SHIFT)) & SRC_STAT_WAKEUP_UNDER_RST_MASK) + #define SRC_STAT_WAKEUP_RST_BY_HW_MASK (0x4U) #define SRC_STAT_WAKEUP_RST_BY_HW_SHIFT (2U) /*! RST_BY_HW @@ -79623,6 +89124,7 @@ typedef struct { * 0b1..the reset is caused by the power mode transfer */ #define SRC_STAT_WAKEUP_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_RST_BY_HW_SHIFT)) & SRC_STAT_WAKEUP_RST_BY_HW_MASK) + #define SRC_STAT_WAKEUP_RST_BY_SW_MASK (0x8U) #define SRC_STAT_WAKEUP_RST_BY_SW_SHIFT (3U) /*! RST_BY_SW @@ -79634,53 +89136,63 @@ typedef struct { /*! @name AUTHEN_M4CORE - Slice Authentication Register */ /*! @{ */ + #define SRC_AUTHEN_M4CORE_DOMAIN_MODE_MASK (0x1U) #define SRC_AUTHEN_M4CORE_DOMAIN_MODE_SHIFT (0U) /*! DOMAIN_MODE - * 0b0..slice hardware reset will Not be triggered by cpu power mode transition - * 0b1..slice hardware reset will be triggered by cpu power mode transition. Do not set this bit and SETPOINT_MODE at the same time. + * 0b0..slice hardware reset will NOT be triggered by CPU power mode transition + * 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time. */ #define SRC_AUTHEN_M4CORE_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_DOMAIN_MODE_MASK) + #define SRC_AUTHEN_M4CORE_SETPOINT_MODE_MASK (0x2U) #define SRC_AUTHEN_M4CORE_SETPOINT_MODE_SHIFT (1U) /*! SETPOINT_MODE - * 0b0..slice hardware reset will Not be triggered by set point transition - * 0b1..slice hardware reset will be triggered by set point transition. Do not set this bit and DOMAIN_MODE at the same time. + * 0b0..slice hardware reset will NOT be triggered by Setpoint transition + * 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time. */ #define SRC_AUTHEN_M4CORE_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_SETPOINT_MODE_MASK) + #define SRC_AUTHEN_M4CORE_LOCK_MODE_MASK (0x80U) #define SRC_AUTHEN_M4CORE_LOCK_MODE_SHIFT (7U) -/*! LOCK_MODE - domain/setpoint mode lock +/*! LOCK_MODE - Domain/Setpoint mode lock */ #define SRC_AUTHEN_M4CORE_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_MODE_MASK) + #define SRC_AUTHEN_M4CORE_ASSIGN_LIST_MASK (0xF00U) #define SRC_AUTHEN_M4CORE_ASSIGN_LIST_SHIFT (8U) #define SRC_AUTHEN_M4CORE_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_ASSIGN_LIST_MASK) + #define SRC_AUTHEN_M4CORE_LOCK_ASSIGN_MASK (0x8000U) #define SRC_AUTHEN_M4CORE_LOCK_ASSIGN_SHIFT (15U) /*! LOCK_ASSIGN - Assign list lock */ #define SRC_AUTHEN_M4CORE_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_ASSIGN_MASK) + #define SRC_AUTHEN_M4CORE_WHITE_LIST_MASK (0xF0000U) #define SRC_AUTHEN_M4CORE_WHITE_LIST_SHIFT (16U) /*! WHITE_LIST - Domain ID white list */ #define SRC_AUTHEN_M4CORE_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_WHITE_LIST_MASK) + #define SRC_AUTHEN_M4CORE_LOCK_LIST_MASK (0x800000U) #define SRC_AUTHEN_M4CORE_LOCK_LIST_SHIFT (23U) /*! LOCK_LIST - White list lock */ #define SRC_AUTHEN_M4CORE_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_LIST_MASK) + #define SRC_AUTHEN_M4CORE_USER_MASK (0x1000000U) #define SRC_AUTHEN_M4CORE_USER_SHIFT (24U) /*! USER - Allow user mode access */ #define SRC_AUTHEN_M4CORE_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_USER_SHIFT)) & SRC_AUTHEN_M4CORE_USER_MASK) + #define SRC_AUTHEN_M4CORE_NONSECURE_MASK (0x2000000U) #define SRC_AUTHEN_M4CORE_NONSECURE_SHIFT (25U) /*! NONSECURE - Allow non-secure mode access */ #define SRC_AUTHEN_M4CORE_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_NONSECURE_SHIFT)) & SRC_AUTHEN_M4CORE_NONSECURE_MASK) + #define SRC_AUTHEN_M4CORE_LOCK_SETTING_MASK (0x80000000U) #define SRC_AUTHEN_M4CORE_LOCK_SETTING_SHIFT (31U) /*! LOCK_SETTING - Lock NONSECURE and USER @@ -79690,6 +89202,7 @@ typedef struct { /*! @name CTRL_M4CORE - Slice Control Register */ /*! @{ */ + #define SRC_CTRL_M4CORE_SW_RESET_MASK (0x1U) #define SRC_CTRL_M4CORE_SW_RESET_SHIFT (0U) /*! SW_RESET @@ -79699,240 +89212,209 @@ typedef struct { #define SRC_CTRL_M4CORE_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M4CORE_SW_RESET_SHIFT)) & SRC_CTRL_M4CORE_SW_RESET_MASK) /*! @} */ -/*! @name SETPOINT_M4CORE - Slice SetPoint Config Register */ +/*! @name SETPOINT_M4CORE - Slice Setpoint Config Register */ /*! @{ */ + #define SRC_SETPOINT_M4CORE_SETPOINT0_MASK (0x1U) #define SRC_SETPOINT_M4CORE_SETPOINT0_SHIFT (0U) -/*! SETPOINT0 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT0 - SETPOINT0 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4CORE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT0_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT0_MASK) + #define SRC_SETPOINT_M4CORE_SETPOINT1_MASK (0x2U) #define SRC_SETPOINT_M4CORE_SETPOINT1_SHIFT (1U) -/*! SETPOINT1 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT1 - SETPOINT1 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4CORE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT1_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT1_MASK) + #define SRC_SETPOINT_M4CORE_SETPOINT2_MASK (0x4U) #define SRC_SETPOINT_M4CORE_SETPOINT2_SHIFT (2U) -/*! SETPOINT2 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT2 - SETPOINT2 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4CORE_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT2_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT2_MASK) + #define SRC_SETPOINT_M4CORE_SETPOINT3_MASK (0x8U) #define SRC_SETPOINT_M4CORE_SETPOINT3_SHIFT (3U) -/*! SETPOINT3 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT3 - SETPOINT3 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4CORE_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT3_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT3_MASK) + #define SRC_SETPOINT_M4CORE_SETPOINT4_MASK (0x10U) #define SRC_SETPOINT_M4CORE_SETPOINT4_SHIFT (4U) -/*! SETPOINT4 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT4 - SETPOINT4 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4CORE_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT4_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT4_MASK) + #define SRC_SETPOINT_M4CORE_SETPOINT5_MASK (0x20U) #define SRC_SETPOINT_M4CORE_SETPOINT5_SHIFT (5U) -/*! SETPOINT5 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT5 - SETPOINT5 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4CORE_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT5_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT5_MASK) + #define SRC_SETPOINT_M4CORE_SETPOINT6_MASK (0x40U) #define SRC_SETPOINT_M4CORE_SETPOINT6_SHIFT (6U) -/*! SETPOINT6 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT6 - SETPOINT6 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4CORE_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT6_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT6_MASK) + #define SRC_SETPOINT_M4CORE_SETPOINT7_MASK (0x80U) #define SRC_SETPOINT_M4CORE_SETPOINT7_SHIFT (7U) -/*! SETPOINT7 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT7 - SETPOINT7 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4CORE_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT7_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT7_MASK) + #define SRC_SETPOINT_M4CORE_SETPOINT8_MASK (0x100U) #define SRC_SETPOINT_M4CORE_SETPOINT8_SHIFT (8U) -/*! SETPOINT8 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT8 - SETPOINT8 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4CORE_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT8_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT8_MASK) + #define SRC_SETPOINT_M4CORE_SETPOINT9_MASK (0x200U) #define SRC_SETPOINT_M4CORE_SETPOINT9_SHIFT (9U) -/*! SETPOINT9 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT9 - SETPOINT9 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4CORE_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT9_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT9_MASK) + #define SRC_SETPOINT_M4CORE_SETPOINT10_MASK (0x400U) #define SRC_SETPOINT_M4CORE_SETPOINT10_SHIFT (10U) -/*! SETPOINT10 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT10 - SETPOINT10 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4CORE_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT10_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT10_MASK) + #define SRC_SETPOINT_M4CORE_SETPOINT11_MASK (0x800U) #define SRC_SETPOINT_M4CORE_SETPOINT11_SHIFT (11U) -/*! SETPOINT11 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT11 - SETPOINT11 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4CORE_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT11_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT11_MASK) + #define SRC_SETPOINT_M4CORE_SETPOINT12_MASK (0x1000U) #define SRC_SETPOINT_M4CORE_SETPOINT12_SHIFT (12U) -/*! SETPOINT12 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT12 - SETPOINT12 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4CORE_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT12_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT12_MASK) + #define SRC_SETPOINT_M4CORE_SETPOINT13_MASK (0x2000U) #define SRC_SETPOINT_M4CORE_SETPOINT13_SHIFT (13U) -/*! SETPOINT13 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT13 - SETPOINT13 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4CORE_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT13_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT13_MASK) + #define SRC_SETPOINT_M4CORE_SETPOINT14_MASK (0x4000U) #define SRC_SETPOINT_M4CORE_SETPOINT14_SHIFT (14U) -/*! SETPOINT14 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT14 - SETPOINT14 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4CORE_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT14_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT14_MASK) + #define SRC_SETPOINT_M4CORE_SETPOINT15_MASK (0x8000U) #define SRC_SETPOINT_M4CORE_SETPOINT15_SHIFT (15U) -/*! SETPOINT15 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT15 - SETPOINT15 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4CORE_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT15_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT15_MASK) /*! @} */ /*! @name DOMAIN_M4CORE - Slice Domain Config Register */ /*! @{ */ + #define SRC_DOMAIN_M4CORE_CPU0_RUN_MASK (0x1U) #define SRC_DOMAIN_M4CORE_CPU0_RUN_SHIFT (0U) -/*! CPU0_RUN - * 0b0..slice reset will be de-asserted when cpu0 in run mode - * 0b1..slice reset will be asserted when cpu0 in run mode +/*! CPU0_RUN - CPU mode setting for RUN + * 0b0..Slice reset will be de-asserted when CPU0 in RUN mode + * 0b1..Slice reset will be asserted when CPU0 in RUN mode */ #define SRC_DOMAIN_M4CORE_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_RUN_MASK) + #define SRC_DOMAIN_M4CORE_CPU0_WAIT_MASK (0x2U) #define SRC_DOMAIN_M4CORE_CPU0_WAIT_SHIFT (1U) -/*! CPU0_WAIT - * 0b0..slice reset will be de-asserted when cpu0 in wait mode - * 0b1..slice reset will be asserted when cpu0 in wait mode +/*! CPU0_WAIT - CPU mode setting for WAIT + * 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode + * 0b1..Slice reset will be asserted when CPU0 in WAIT mode */ #define SRC_DOMAIN_M4CORE_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_WAIT_MASK) + #define SRC_DOMAIN_M4CORE_CPU0_STOP_MASK (0x4U) #define SRC_DOMAIN_M4CORE_CPU0_STOP_SHIFT (2U) -/*! CPU0_STOP - * 0b0..slice reset will be de-asserted when cpu0 in stop mode - * 0b1..slice reset will be asserted when cpu0 in stop mode +/*! CPU0_STOP - CPU mode setting for STOP + * 0b0..Slice reset will be de-asserted when CPU0 in STOP mode + * 0b1..Slice reset will be asserted when CPU0 in STOP mode */ #define SRC_DOMAIN_M4CORE_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_STOP_MASK) + #define SRC_DOMAIN_M4CORE_CPU0_SUSP_MASK (0x8U) #define SRC_DOMAIN_M4CORE_CPU0_SUSP_SHIFT (3U) -/*! CPU0_SUSP - * 0b0..slice reset will be de-asserted when cpu0 in suspend mode - * 0b1..slice reset will be asserted when cpu0 in suspend mode +/*! CPU0_SUSP - CPU mode setting for SUSPEND + * 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode + * 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode */ #define SRC_DOMAIN_M4CORE_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_SUSP_MASK) + #define SRC_DOMAIN_M4CORE_CPU1_RUN_MASK (0x10U) #define SRC_DOMAIN_M4CORE_CPU1_RUN_SHIFT (4U) -/*! CPU1_RUN - * 0b0..slice reset will be de-asserted when cpu1 in run mode - * 0b1..slice reset will be asserted when cpu1 in run mode +/*! CPU1_RUN - CPU mode setting for RUN + * 0b0..Slice reset will be de-asserted when CPU1 in RUN mode + * 0b1..Slice reset will be asserted when CPU1 in RUN mode */ #define SRC_DOMAIN_M4CORE_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_RUN_MASK) + #define SRC_DOMAIN_M4CORE_CPU1_WAIT_MASK (0x20U) #define SRC_DOMAIN_M4CORE_CPU1_WAIT_SHIFT (5U) -/*! CPU1_WAIT - * 0b0..slice reset will be de-asserted when cpu1 in wait mode - * 0b1..slice reset will be asserted when cpu1 in wait mode +/*! CPU1_WAIT - CPU mode setting for WAIT + * 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode + * 0b1..Slice reset will be asserted when CPU1 in WAIT mode */ #define SRC_DOMAIN_M4CORE_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_WAIT_MASK) + #define SRC_DOMAIN_M4CORE_CPU1_STOP_MASK (0x40U) #define SRC_DOMAIN_M4CORE_CPU1_STOP_SHIFT (6U) -/*! CPU1_STOP - * 0b0..slice reset will be de-asserted when cpu1 in stop mode - * 0b1..slice reset will be asserted when cpu1 in stop mode +/*! CPU1_STOP - CPU mode setting for STOP + * 0b0..Slice reset will be de-asserted when CPU1 in STOP mode + * 0b1..Slice reset will be asserted when CPU1 in STOP mode */ #define SRC_DOMAIN_M4CORE_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_STOP_MASK) + #define SRC_DOMAIN_M4CORE_CPU1_SUSP_MASK (0x80U) #define SRC_DOMAIN_M4CORE_CPU1_SUSP_SHIFT (7U) -/*! CPU1_SUSP - * 0b0..slice reset will be de-asserted when cpu1 in suspend mode - * 0b1..slice reset will be asserted when cpu1 in suspend mode +/*! CPU1_SUSP - CPU mode setting for SUSPEND + * 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode + * 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode */ #define SRC_DOMAIN_M4CORE_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_SUSP_MASK) -#define SRC_DOMAIN_M4CORE_CPU2_RUN_MASK (0x100U) -#define SRC_DOMAIN_M4CORE_CPU2_RUN_SHIFT (8U) -/*! CPU2_RUN - * 0b0..slice reset will be de-asserted when cpu2 in run mode - * 0b1..slice reset will be asserted when cpu2 in run mode - */ -#define SRC_DOMAIN_M4CORE_CPU2_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU2_RUN_SHIFT)) & SRC_DOMAIN_M4CORE_CPU2_RUN_MASK) -#define SRC_DOMAIN_M4CORE_CPU2_WAIT_MASK (0x200U) -#define SRC_DOMAIN_M4CORE_CPU2_WAIT_SHIFT (9U) -/*! CPU2_WAIT - * 0b0..slice reset will be de-asserted when cpu2 in wait mode - * 0b1..slice reset will be asserted when cpu2 in wait mode - */ -#define SRC_DOMAIN_M4CORE_CPU2_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU2_WAIT_SHIFT)) & SRC_DOMAIN_M4CORE_CPU2_WAIT_MASK) -#define SRC_DOMAIN_M4CORE_CPU2_STOP_MASK (0x400U) -#define SRC_DOMAIN_M4CORE_CPU2_STOP_SHIFT (10U) -/*! CPU2_STOP - * 0b0..slice reset will be de-asserted when cpu2 in stop mode - * 0b1..slice reset will be asserted when cpu2 in stop mode - */ -#define SRC_DOMAIN_M4CORE_CPU2_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU2_STOP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU2_STOP_MASK) -#define SRC_DOMAIN_M4CORE_CPU2_SUSP_MASK (0x800U) -#define SRC_DOMAIN_M4CORE_CPU2_SUSP_SHIFT (11U) -/*! CPU2_SUSP - * 0b0..slice reset will be de-asserted when cpu2 in suspend mode - * 0b1..slice reset will be asserted when cpu2 in suspend mode - */ -#define SRC_DOMAIN_M4CORE_CPU2_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU2_SUSP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU2_SUSP_MASK) -#define SRC_DOMAIN_M4CORE_CPU3_RUN_MASK (0x1000U) -#define SRC_DOMAIN_M4CORE_CPU3_RUN_SHIFT (12U) -/*! CPU3_RUN - * 0b0..slice reset will be de-asserted when cpu3 in run mode - * 0b1..slice reset will be asserted when cpu3 in run mode - */ -#define SRC_DOMAIN_M4CORE_CPU3_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU3_RUN_SHIFT)) & SRC_DOMAIN_M4CORE_CPU3_RUN_MASK) -#define SRC_DOMAIN_M4CORE_CPU3_WAIT_MASK (0x2000U) -#define SRC_DOMAIN_M4CORE_CPU3_WAIT_SHIFT (13U) -/*! CPU3_WAIT - * 0b0..slice reset will be de-asserted when cpu3 in wait mode - * 0b1..slice reset will be asserted when cpu3 in wait mode - */ -#define SRC_DOMAIN_M4CORE_CPU3_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU3_WAIT_SHIFT)) & SRC_DOMAIN_M4CORE_CPU3_WAIT_MASK) -#define SRC_DOMAIN_M4CORE_CPU3_STOP_MASK (0x4000U) -#define SRC_DOMAIN_M4CORE_CPU3_STOP_SHIFT (14U) -/*! CPU3_STOP - * 0b0..slice reset will be de-asserted when cpu3 in stop mode - * 0b1..slice reset will be asserted when cpu3 in stop mode - */ -#define SRC_DOMAIN_M4CORE_CPU3_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU3_STOP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU3_STOP_MASK) -#define SRC_DOMAIN_M4CORE_CPU3_SUSP_MASK (0x8000U) -#define SRC_DOMAIN_M4CORE_CPU3_SUSP_SHIFT (15U) -/*! CPU3_SUSP - * 0b0..slice reset will be de-asserted when cpu3 in suspend mode - * 0b1..slice reset will be asserted when cpu3 in suspend mode - */ -#define SRC_DOMAIN_M4CORE_CPU3_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU3_SUSP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU3_SUSP_MASK) /*! @} */ /*! @name STAT_M4CORE - Slice Status Register */ /*! @{ */ + #define SRC_STAT_M4CORE_UNDER_RST_MASK (0x1U) #define SRC_STAT_M4CORE_UNDER_RST_SHIFT (0U) /*! UNDER_RST @@ -79940,6 +89422,7 @@ typedef struct { * 0b1..the reset is in process */ #define SRC_STAT_M4CORE_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_UNDER_RST_SHIFT)) & SRC_STAT_M4CORE_UNDER_RST_MASK) + #define SRC_STAT_M4CORE_RST_BY_HW_MASK (0x4U) #define SRC_STAT_M4CORE_RST_BY_HW_SHIFT (2U) /*! RST_BY_HW @@ -79947,6 +89430,7 @@ typedef struct { * 0b1..the reset is caused by the power mode transfer */ #define SRC_STAT_M4CORE_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_RST_BY_HW_SHIFT)) & SRC_STAT_M4CORE_RST_BY_HW_MASK) + #define SRC_STAT_M4CORE_RST_BY_SW_MASK (0x8U) #define SRC_STAT_M4CORE_RST_BY_SW_SHIFT (3U) /*! RST_BY_SW @@ -79958,53 +89442,63 @@ typedef struct { /*! @name AUTHEN_M7CORE - Slice Authentication Register */ /*! @{ */ + #define SRC_AUTHEN_M7CORE_DOMAIN_MODE_MASK (0x1U) #define SRC_AUTHEN_M7CORE_DOMAIN_MODE_SHIFT (0U) /*! DOMAIN_MODE - * 0b0..slice hardware reset will Not be triggered by cpu power mode transition - * 0b1..slice hardware reset will be triggered by cpu power mode transition. Do not set this bit and SETPOINT_MODE at the same time. + * 0b0..slice hardware reset will NOT be triggered by CPU power mode transition + * 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time. */ #define SRC_AUTHEN_M7CORE_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_DOMAIN_MODE_MASK) + #define SRC_AUTHEN_M7CORE_SETPOINT_MODE_MASK (0x2U) #define SRC_AUTHEN_M7CORE_SETPOINT_MODE_SHIFT (1U) /*! SETPOINT_MODE - * 0b0..slice hardware reset will Not be triggered by set point transition - * 0b1..slice hardware reset will be triggered by set point transition. Do not set this bit and DOMAIN_MODE at the same time. + * 0b0..slice hardware reset will NOT be triggered by Setpoint transition + * 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time. */ #define SRC_AUTHEN_M7CORE_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_SETPOINT_MODE_MASK) + #define SRC_AUTHEN_M7CORE_LOCK_MODE_MASK (0x80U) #define SRC_AUTHEN_M7CORE_LOCK_MODE_SHIFT (7U) -/*! LOCK_MODE - domain/setpoint mode lock +/*! LOCK_MODE - Domain/Setpoint mode lock */ #define SRC_AUTHEN_M7CORE_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_MODE_MASK) + #define SRC_AUTHEN_M7CORE_ASSIGN_LIST_MASK (0xF00U) #define SRC_AUTHEN_M7CORE_ASSIGN_LIST_SHIFT (8U) #define SRC_AUTHEN_M7CORE_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_ASSIGN_LIST_MASK) + #define SRC_AUTHEN_M7CORE_LOCK_ASSIGN_MASK (0x8000U) #define SRC_AUTHEN_M7CORE_LOCK_ASSIGN_SHIFT (15U) /*! LOCK_ASSIGN - Assign list lock */ #define SRC_AUTHEN_M7CORE_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_ASSIGN_MASK) + #define SRC_AUTHEN_M7CORE_WHITE_LIST_MASK (0xF0000U) #define SRC_AUTHEN_M7CORE_WHITE_LIST_SHIFT (16U) /*! WHITE_LIST - Domain ID white list */ #define SRC_AUTHEN_M7CORE_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_WHITE_LIST_MASK) + #define SRC_AUTHEN_M7CORE_LOCK_LIST_MASK (0x800000U) #define SRC_AUTHEN_M7CORE_LOCK_LIST_SHIFT (23U) /*! LOCK_LIST - White list lock */ #define SRC_AUTHEN_M7CORE_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_LIST_MASK) + #define SRC_AUTHEN_M7CORE_USER_MASK (0x1000000U) #define SRC_AUTHEN_M7CORE_USER_SHIFT (24U) /*! USER - Allow user mode access */ #define SRC_AUTHEN_M7CORE_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_USER_SHIFT)) & SRC_AUTHEN_M7CORE_USER_MASK) + #define SRC_AUTHEN_M7CORE_NONSECURE_MASK (0x2000000U) #define SRC_AUTHEN_M7CORE_NONSECURE_SHIFT (25U) /*! NONSECURE - Allow non-secure mode access */ #define SRC_AUTHEN_M7CORE_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_NONSECURE_SHIFT)) & SRC_AUTHEN_M7CORE_NONSECURE_MASK) + #define SRC_AUTHEN_M7CORE_LOCK_SETTING_MASK (0x80000000U) #define SRC_AUTHEN_M7CORE_LOCK_SETTING_SHIFT (31U) /*! LOCK_SETTING - Lock NONSECURE and USER @@ -80014,6 +89508,7 @@ typedef struct { /*! @name CTRL_M7CORE - Slice Control Register */ /*! @{ */ + #define SRC_CTRL_M7CORE_SW_RESET_MASK (0x1U) #define SRC_CTRL_M7CORE_SW_RESET_SHIFT (0U) /*! SW_RESET @@ -80023,240 +89518,209 @@ typedef struct { #define SRC_CTRL_M7CORE_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M7CORE_SW_RESET_SHIFT)) & SRC_CTRL_M7CORE_SW_RESET_MASK) /*! @} */ -/*! @name SETPOINT_M7CORE - Slice SetPoint Config Register */ +/*! @name SETPOINT_M7CORE - Slice Setpoint Config Register */ /*! @{ */ + #define SRC_SETPOINT_M7CORE_SETPOINT0_MASK (0x1U) #define SRC_SETPOINT_M7CORE_SETPOINT0_SHIFT (0U) -/*! SETPOINT0 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT0 - SETPOINT0 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7CORE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT0_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT0_MASK) + #define SRC_SETPOINT_M7CORE_SETPOINT1_MASK (0x2U) #define SRC_SETPOINT_M7CORE_SETPOINT1_SHIFT (1U) -/*! SETPOINT1 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT1 - SETPOINT1 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7CORE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT1_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT1_MASK) + #define SRC_SETPOINT_M7CORE_SETPOINT2_MASK (0x4U) #define SRC_SETPOINT_M7CORE_SETPOINT2_SHIFT (2U) -/*! SETPOINT2 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT2 - SETPOINT2 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7CORE_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT2_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT2_MASK) + #define SRC_SETPOINT_M7CORE_SETPOINT3_MASK (0x8U) #define SRC_SETPOINT_M7CORE_SETPOINT3_SHIFT (3U) -/*! SETPOINT3 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT3 - SETPOINT3 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7CORE_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT3_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT3_MASK) + #define SRC_SETPOINT_M7CORE_SETPOINT4_MASK (0x10U) #define SRC_SETPOINT_M7CORE_SETPOINT4_SHIFT (4U) -/*! SETPOINT4 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT4 - SETPOINT4 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7CORE_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT4_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT4_MASK) + #define SRC_SETPOINT_M7CORE_SETPOINT5_MASK (0x20U) #define SRC_SETPOINT_M7CORE_SETPOINT5_SHIFT (5U) -/*! SETPOINT5 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT5 - SETPOINT5 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7CORE_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT5_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT5_MASK) + #define SRC_SETPOINT_M7CORE_SETPOINT6_MASK (0x40U) #define SRC_SETPOINT_M7CORE_SETPOINT6_SHIFT (6U) -/*! SETPOINT6 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT6 - SETPOINT6 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7CORE_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT6_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT6_MASK) + #define SRC_SETPOINT_M7CORE_SETPOINT7_MASK (0x80U) #define SRC_SETPOINT_M7CORE_SETPOINT7_SHIFT (7U) -/*! SETPOINT7 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT7 - SETPOINT7 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7CORE_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT7_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT7_MASK) + #define SRC_SETPOINT_M7CORE_SETPOINT8_MASK (0x100U) #define SRC_SETPOINT_M7CORE_SETPOINT8_SHIFT (8U) -/*! SETPOINT8 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT8 - SETPOINT8 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7CORE_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT8_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT8_MASK) + #define SRC_SETPOINT_M7CORE_SETPOINT9_MASK (0x200U) #define SRC_SETPOINT_M7CORE_SETPOINT9_SHIFT (9U) -/*! SETPOINT9 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT9 - SETPOINT9 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7CORE_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT9_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT9_MASK) + #define SRC_SETPOINT_M7CORE_SETPOINT10_MASK (0x400U) #define SRC_SETPOINT_M7CORE_SETPOINT10_SHIFT (10U) -/*! SETPOINT10 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT10 - SETPOINT10 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7CORE_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT10_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT10_MASK) + #define SRC_SETPOINT_M7CORE_SETPOINT11_MASK (0x800U) #define SRC_SETPOINT_M7CORE_SETPOINT11_SHIFT (11U) -/*! SETPOINT11 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT11 - SETPOINT11 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7CORE_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT11_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT11_MASK) + #define SRC_SETPOINT_M7CORE_SETPOINT12_MASK (0x1000U) #define SRC_SETPOINT_M7CORE_SETPOINT12_SHIFT (12U) -/*! SETPOINT12 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT12 - SETPOINT12 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7CORE_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT12_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT12_MASK) + #define SRC_SETPOINT_M7CORE_SETPOINT13_MASK (0x2000U) #define SRC_SETPOINT_M7CORE_SETPOINT13_SHIFT (13U) -/*! SETPOINT13 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT13 - SETPOINT13 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7CORE_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT13_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT13_MASK) + #define SRC_SETPOINT_M7CORE_SETPOINT14_MASK (0x4000U) #define SRC_SETPOINT_M7CORE_SETPOINT14_SHIFT (14U) -/*! SETPOINT14 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT14 - SETPOINT14 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7CORE_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT14_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT14_MASK) + #define SRC_SETPOINT_M7CORE_SETPOINT15_MASK (0x8000U) #define SRC_SETPOINT_M7CORE_SETPOINT15_SHIFT (15U) -/*! SETPOINT15 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT15 - SETPOINT15 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7CORE_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT15_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT15_MASK) /*! @} */ /*! @name DOMAIN_M7CORE - Slice Domain Config Register */ /*! @{ */ + #define SRC_DOMAIN_M7CORE_CPU0_RUN_MASK (0x1U) #define SRC_DOMAIN_M7CORE_CPU0_RUN_SHIFT (0U) -/*! CPU0_RUN - * 0b0..slice reset will be de-asserted when cpu0 in run mode - * 0b1..slice reset will be asserted when cpu0 in run mode +/*! CPU0_RUN - CPU mode setting for RUN + * 0b0..Slice reset will be de-asserted when CPU0 in RUN mode + * 0b1..Slice reset will be asserted when CPU0 in RUN mode */ #define SRC_DOMAIN_M7CORE_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_RUN_MASK) + #define SRC_DOMAIN_M7CORE_CPU0_WAIT_MASK (0x2U) #define SRC_DOMAIN_M7CORE_CPU0_WAIT_SHIFT (1U) -/*! CPU0_WAIT - * 0b0..slice reset will be de-asserted when cpu0 in wait mode - * 0b1..slice reset will be asserted when cpu0 in wait mode +/*! CPU0_WAIT - CPU mode setting for WAIT + * 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode + * 0b1..Slice reset will be asserted when CPU0 in WAIT mode */ #define SRC_DOMAIN_M7CORE_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_WAIT_MASK) + #define SRC_DOMAIN_M7CORE_CPU0_STOP_MASK (0x4U) #define SRC_DOMAIN_M7CORE_CPU0_STOP_SHIFT (2U) -/*! CPU0_STOP - * 0b0..slice reset will be de-asserted when cpu0 in stop mode - * 0b1..slice reset will be asserted when cpu0 in stop mode +/*! CPU0_STOP - CPU mode setting for STOP + * 0b0..Slice reset will be de-asserted when CPU0 in STOP mode + * 0b1..Slice reset will be asserted when CPU0 in STOP mode */ #define SRC_DOMAIN_M7CORE_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_STOP_MASK) + #define SRC_DOMAIN_M7CORE_CPU0_SUSP_MASK (0x8U) #define SRC_DOMAIN_M7CORE_CPU0_SUSP_SHIFT (3U) -/*! CPU0_SUSP - * 0b0..slice reset will be de-asserted when cpu0 in suspend mode - * 0b1..slice reset will be asserted when cpu0 in suspend mode +/*! CPU0_SUSP - CPU mode setting for SUSPEND + * 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode + * 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode */ #define SRC_DOMAIN_M7CORE_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_SUSP_MASK) + #define SRC_DOMAIN_M7CORE_CPU1_RUN_MASK (0x10U) #define SRC_DOMAIN_M7CORE_CPU1_RUN_SHIFT (4U) -/*! CPU1_RUN - * 0b0..slice reset will be de-asserted when cpu1 in run mode - * 0b1..slice reset will be asserted when cpu1 in run mode +/*! CPU1_RUN - CPU mode setting for RUN + * 0b0..Slice reset will be de-asserted when CPU1 in RUN mode + * 0b1..Slice reset will be asserted when CPU1 in RUN mode */ #define SRC_DOMAIN_M7CORE_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_RUN_MASK) + #define SRC_DOMAIN_M7CORE_CPU1_WAIT_MASK (0x20U) #define SRC_DOMAIN_M7CORE_CPU1_WAIT_SHIFT (5U) -/*! CPU1_WAIT - * 0b0..slice reset will be de-asserted when cpu1 in wait mode - * 0b1..slice reset will be asserted when cpu1 in wait mode +/*! CPU1_WAIT - CPU mode setting for WAIT + * 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode + * 0b1..Slice reset will be asserted when CPU1 in WAIT mode */ #define SRC_DOMAIN_M7CORE_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_WAIT_MASK) + #define SRC_DOMAIN_M7CORE_CPU1_STOP_MASK (0x40U) #define SRC_DOMAIN_M7CORE_CPU1_STOP_SHIFT (6U) -/*! CPU1_STOP - * 0b0..slice reset will be de-asserted when cpu1 in stop mode - * 0b1..slice reset will be asserted when cpu1 in stop mode +/*! CPU1_STOP - CPU mode setting for STOP + * 0b0..Slice reset will be de-asserted when CPU1 in STOP mode + * 0b1..Slice reset will be asserted when CPU1 in STOP mode */ #define SRC_DOMAIN_M7CORE_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_STOP_MASK) + #define SRC_DOMAIN_M7CORE_CPU1_SUSP_MASK (0x80U) #define SRC_DOMAIN_M7CORE_CPU1_SUSP_SHIFT (7U) -/*! CPU1_SUSP - * 0b0..slice reset will be de-asserted when cpu1 in suspend mode - * 0b1..slice reset will be asserted when cpu1 in suspend mode +/*! CPU1_SUSP - CPU mode setting for SUSPEND + * 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode + * 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode */ #define SRC_DOMAIN_M7CORE_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_SUSP_MASK) -#define SRC_DOMAIN_M7CORE_CPU2_RUN_MASK (0x100U) -#define SRC_DOMAIN_M7CORE_CPU2_RUN_SHIFT (8U) -/*! CPU2_RUN - * 0b0..slice reset will be de-asserted when cpu2 in run mode - * 0b1..slice reset will be asserted when cpu2 in run mode - */ -#define SRC_DOMAIN_M7CORE_CPU2_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU2_RUN_SHIFT)) & SRC_DOMAIN_M7CORE_CPU2_RUN_MASK) -#define SRC_DOMAIN_M7CORE_CPU2_WAIT_MASK (0x200U) -#define SRC_DOMAIN_M7CORE_CPU2_WAIT_SHIFT (9U) -/*! CPU2_WAIT - * 0b0..slice reset will be de-asserted when cpu2 in wait mode - * 0b1..slice reset will be asserted when cpu2 in wait mode - */ -#define SRC_DOMAIN_M7CORE_CPU2_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU2_WAIT_SHIFT)) & SRC_DOMAIN_M7CORE_CPU2_WAIT_MASK) -#define SRC_DOMAIN_M7CORE_CPU2_STOP_MASK (0x400U) -#define SRC_DOMAIN_M7CORE_CPU2_STOP_SHIFT (10U) -/*! CPU2_STOP - * 0b0..slice reset will be de-asserted when cpu2 in stop mode - * 0b1..slice reset will be asserted when cpu2 in stop mode - */ -#define SRC_DOMAIN_M7CORE_CPU2_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU2_STOP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU2_STOP_MASK) -#define SRC_DOMAIN_M7CORE_CPU2_SUSP_MASK (0x800U) -#define SRC_DOMAIN_M7CORE_CPU2_SUSP_SHIFT (11U) -/*! CPU2_SUSP - * 0b0..slice reset will be de-asserted when cpu2 in suspend mode - * 0b1..slice reset will be asserted when cpu2 in suspend mode - */ -#define SRC_DOMAIN_M7CORE_CPU2_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU2_SUSP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU2_SUSP_MASK) -#define SRC_DOMAIN_M7CORE_CPU3_RUN_MASK (0x1000U) -#define SRC_DOMAIN_M7CORE_CPU3_RUN_SHIFT (12U) -/*! CPU3_RUN - * 0b0..slice reset will be de-asserted when cpu3 in run mode - * 0b1..slice reset will be asserted when cpu3 in run mode - */ -#define SRC_DOMAIN_M7CORE_CPU3_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU3_RUN_SHIFT)) & SRC_DOMAIN_M7CORE_CPU3_RUN_MASK) -#define SRC_DOMAIN_M7CORE_CPU3_WAIT_MASK (0x2000U) -#define SRC_DOMAIN_M7CORE_CPU3_WAIT_SHIFT (13U) -/*! CPU3_WAIT - * 0b0..slice reset will be de-asserted when cpu3 in wait mode - * 0b1..slice reset will be asserted when cpu3 in wait mode - */ -#define SRC_DOMAIN_M7CORE_CPU3_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU3_WAIT_SHIFT)) & SRC_DOMAIN_M7CORE_CPU3_WAIT_MASK) -#define SRC_DOMAIN_M7CORE_CPU3_STOP_MASK (0x4000U) -#define SRC_DOMAIN_M7CORE_CPU3_STOP_SHIFT (14U) -/*! CPU3_STOP - * 0b0..slice reset will be de-asserted when cpu3 in stop mode - * 0b1..slice reset will be asserted when cpu3 in stop mode - */ -#define SRC_DOMAIN_M7CORE_CPU3_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU3_STOP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU3_STOP_MASK) -#define SRC_DOMAIN_M7CORE_CPU3_SUSP_MASK (0x8000U) -#define SRC_DOMAIN_M7CORE_CPU3_SUSP_SHIFT (15U) -/*! CPU3_SUSP - * 0b0..slice reset will be de-asserted when cpu3 in suspend mode - * 0b1..slice reset will be asserted when cpu3 in suspend mode - */ -#define SRC_DOMAIN_M7CORE_CPU3_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU3_SUSP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU3_SUSP_MASK) /*! @} */ /*! @name STAT_M7CORE - Slice Status Register */ /*! @{ */ + #define SRC_STAT_M7CORE_UNDER_RST_MASK (0x1U) #define SRC_STAT_M7CORE_UNDER_RST_SHIFT (0U) /*! UNDER_RST @@ -80264,6 +89728,7 @@ typedef struct { * 0b1..the reset is in process */ #define SRC_STAT_M7CORE_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_UNDER_RST_SHIFT)) & SRC_STAT_M7CORE_UNDER_RST_MASK) + #define SRC_STAT_M7CORE_RST_BY_HW_MASK (0x4U) #define SRC_STAT_M7CORE_RST_BY_HW_SHIFT (2U) /*! RST_BY_HW @@ -80271,6 +89736,7 @@ typedef struct { * 0b1..the reset is caused by the power mode transfer */ #define SRC_STAT_M7CORE_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_RST_BY_HW_SHIFT)) & SRC_STAT_M7CORE_RST_BY_HW_MASK) + #define SRC_STAT_M7CORE_RST_BY_SW_MASK (0x8U) #define SRC_STAT_M7CORE_RST_BY_SW_SHIFT (3U) /*! RST_BY_SW @@ -80282,53 +89748,63 @@ typedef struct { /*! @name AUTHEN_M4DEBUG - Slice Authentication Register */ /*! @{ */ + #define SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_MASK (0x1U) #define SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_SHIFT (0U) /*! DOMAIN_MODE - * 0b0..slice hardware reset will Not be triggered by cpu power mode transition - * 0b1..slice hardware reset will be triggered by cpu power mode transition. Do not set this bit and SETPOINT_MODE at the same time. + * 0b0..slice hardware reset will NOT be triggered by CPU power mode transition + * 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time. */ #define SRC_AUTHEN_M4DEBUG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_MASK) + #define SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_MASK (0x2U) #define SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_SHIFT (1U) /*! SETPOINT_MODE - * 0b0..slice hardware reset will Not be triggered by set point transition - * 0b1..slice hardware reset will be triggered by set point transition. Do not set this bit and DOMAIN_MODE at the same time. + * 0b0..slice hardware reset will NOT be triggered by Setpoint transition + * 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time. */ #define SRC_AUTHEN_M4DEBUG_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_MASK) + #define SRC_AUTHEN_M4DEBUG_LOCK_MODE_MASK (0x80U) #define SRC_AUTHEN_M4DEBUG_LOCK_MODE_SHIFT (7U) -/*! LOCK_MODE - domain/setpoint mode lock +/*! LOCK_MODE - Domain/Setpoint mode lock */ #define SRC_AUTHEN_M4DEBUG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_MODE_MASK) + #define SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_MASK (0xF00U) #define SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_SHIFT (8U) #define SRC_AUTHEN_M4DEBUG_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_MASK) + #define SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_MASK (0x8000U) #define SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_SHIFT (15U) /*! LOCK_ASSIGN - Assign list lock */ #define SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_MASK) + #define SRC_AUTHEN_M4DEBUG_WHITE_LIST_MASK (0xF0000U) #define SRC_AUTHEN_M4DEBUG_WHITE_LIST_SHIFT (16U) /*! WHITE_LIST - Domain ID white list */ #define SRC_AUTHEN_M4DEBUG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_WHITE_LIST_MASK) + #define SRC_AUTHEN_M4DEBUG_LOCK_LIST_MASK (0x800000U) #define SRC_AUTHEN_M4DEBUG_LOCK_LIST_SHIFT (23U) /*! LOCK_LIST - White list lock */ #define SRC_AUTHEN_M4DEBUG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_LIST_MASK) + #define SRC_AUTHEN_M4DEBUG_USER_MASK (0x1000000U) #define SRC_AUTHEN_M4DEBUG_USER_SHIFT (24U) /*! USER - Allow user mode access */ #define SRC_AUTHEN_M4DEBUG_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_USER_SHIFT)) & SRC_AUTHEN_M4DEBUG_USER_MASK) + #define SRC_AUTHEN_M4DEBUG_NONSECURE_MASK (0x2000000U) #define SRC_AUTHEN_M4DEBUG_NONSECURE_SHIFT (25U) /*! NONSECURE - Allow non-secure mode access */ #define SRC_AUTHEN_M4DEBUG_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_NONSECURE_SHIFT)) & SRC_AUTHEN_M4DEBUG_NONSECURE_MASK) + #define SRC_AUTHEN_M4DEBUG_LOCK_SETTING_MASK (0x80000000U) #define SRC_AUTHEN_M4DEBUG_LOCK_SETTING_SHIFT (31U) /*! LOCK_SETTING - Lock NONSECURE and USER @@ -80338,6 +89814,7 @@ typedef struct { /*! @name CTRL_M4DEBUG - Slice Control Register */ /*! @{ */ + #define SRC_CTRL_M4DEBUG_SW_RESET_MASK (0x1U) #define SRC_CTRL_M4DEBUG_SW_RESET_SHIFT (0U) /*! SW_RESET @@ -80347,240 +89824,209 @@ typedef struct { #define SRC_CTRL_M4DEBUG_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M4DEBUG_SW_RESET_SHIFT)) & SRC_CTRL_M4DEBUG_SW_RESET_MASK) /*! @} */ -/*! @name SETPOINT_M4DEBUG - Slice SetPoint Config Register */ +/*! @name SETPOINT_M4DEBUG - Slice Setpoint Config Register */ /*! @{ */ + #define SRC_SETPOINT_M4DEBUG_SETPOINT0_MASK (0x1U) #define SRC_SETPOINT_M4DEBUG_SETPOINT0_SHIFT (0U) -/*! SETPOINT0 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT0 - SETPOINT0 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4DEBUG_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT0_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT0_MASK) + #define SRC_SETPOINT_M4DEBUG_SETPOINT1_MASK (0x2U) #define SRC_SETPOINT_M4DEBUG_SETPOINT1_SHIFT (1U) -/*! SETPOINT1 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT1 - SETPOINT1 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4DEBUG_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT1_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT1_MASK) + #define SRC_SETPOINT_M4DEBUG_SETPOINT2_MASK (0x4U) #define SRC_SETPOINT_M4DEBUG_SETPOINT2_SHIFT (2U) -/*! SETPOINT2 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT2 - SETPOINT2 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4DEBUG_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT2_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT2_MASK) + #define SRC_SETPOINT_M4DEBUG_SETPOINT3_MASK (0x8U) #define SRC_SETPOINT_M4DEBUG_SETPOINT3_SHIFT (3U) -/*! SETPOINT3 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT3 - SETPOINT3 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4DEBUG_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT3_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT3_MASK) + #define SRC_SETPOINT_M4DEBUG_SETPOINT4_MASK (0x10U) #define SRC_SETPOINT_M4DEBUG_SETPOINT4_SHIFT (4U) -/*! SETPOINT4 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT4 - SETPOINT4 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4DEBUG_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT4_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT4_MASK) + #define SRC_SETPOINT_M4DEBUG_SETPOINT5_MASK (0x20U) #define SRC_SETPOINT_M4DEBUG_SETPOINT5_SHIFT (5U) -/*! SETPOINT5 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT5 - SETPOINT5 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4DEBUG_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT5_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT5_MASK) + #define SRC_SETPOINT_M4DEBUG_SETPOINT6_MASK (0x40U) #define SRC_SETPOINT_M4DEBUG_SETPOINT6_SHIFT (6U) -/*! SETPOINT6 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT6 - SETPOINT6 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4DEBUG_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT6_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT6_MASK) + #define SRC_SETPOINT_M4DEBUG_SETPOINT7_MASK (0x80U) #define SRC_SETPOINT_M4DEBUG_SETPOINT7_SHIFT (7U) -/*! SETPOINT7 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT7 - SETPOINT7 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4DEBUG_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT7_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT7_MASK) + #define SRC_SETPOINT_M4DEBUG_SETPOINT8_MASK (0x100U) #define SRC_SETPOINT_M4DEBUG_SETPOINT8_SHIFT (8U) -/*! SETPOINT8 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT8 - SETPOINT8 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4DEBUG_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT8_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT8_MASK) + #define SRC_SETPOINT_M4DEBUG_SETPOINT9_MASK (0x200U) #define SRC_SETPOINT_M4DEBUG_SETPOINT9_SHIFT (9U) -/*! SETPOINT9 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT9 - SETPOINT9 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4DEBUG_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT9_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT9_MASK) + #define SRC_SETPOINT_M4DEBUG_SETPOINT10_MASK (0x400U) #define SRC_SETPOINT_M4DEBUG_SETPOINT10_SHIFT (10U) -/*! SETPOINT10 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT10 - SETPOINT10 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4DEBUG_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT10_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT10_MASK) + #define SRC_SETPOINT_M4DEBUG_SETPOINT11_MASK (0x800U) #define SRC_SETPOINT_M4DEBUG_SETPOINT11_SHIFT (11U) -/*! SETPOINT11 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT11 - SETPOINT11 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4DEBUG_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT11_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT11_MASK) + #define SRC_SETPOINT_M4DEBUG_SETPOINT12_MASK (0x1000U) #define SRC_SETPOINT_M4DEBUG_SETPOINT12_SHIFT (12U) -/*! SETPOINT12 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT12 - SETPOINT12 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4DEBUG_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT12_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT12_MASK) + #define SRC_SETPOINT_M4DEBUG_SETPOINT13_MASK (0x2000U) #define SRC_SETPOINT_M4DEBUG_SETPOINT13_SHIFT (13U) -/*! SETPOINT13 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT13 - SETPOINT13 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4DEBUG_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT13_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT13_MASK) + #define SRC_SETPOINT_M4DEBUG_SETPOINT14_MASK (0x4000U) #define SRC_SETPOINT_M4DEBUG_SETPOINT14_SHIFT (14U) -/*! SETPOINT14 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT14 - SETPOINT14 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4DEBUG_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT14_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT14_MASK) + #define SRC_SETPOINT_M4DEBUG_SETPOINT15_MASK (0x8000U) #define SRC_SETPOINT_M4DEBUG_SETPOINT15_SHIFT (15U) -/*! SETPOINT15 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT15 - SETPOINT15 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M4DEBUG_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT15_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT15_MASK) /*! @} */ /*! @name DOMAIN_M4DEBUG - Slice Domain Config Register */ /*! @{ */ + #define SRC_DOMAIN_M4DEBUG_CPU0_RUN_MASK (0x1U) #define SRC_DOMAIN_M4DEBUG_CPU0_RUN_SHIFT (0U) -/*! CPU0_RUN - * 0b0..slice reset will be de-asserted when cpu0 in run mode - * 0b1..slice reset will be asserted when cpu0 in run mode +/*! CPU0_RUN - CPU mode setting for RUN + * 0b0..Slice reset will be de-asserted when CPU0 in RUN mode + * 0b1..Slice reset will be asserted when CPU0 in RUN mode */ #define SRC_DOMAIN_M4DEBUG_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_RUN_MASK) + #define SRC_DOMAIN_M4DEBUG_CPU0_WAIT_MASK (0x2U) #define SRC_DOMAIN_M4DEBUG_CPU0_WAIT_SHIFT (1U) -/*! CPU0_WAIT - * 0b0..slice reset will be de-asserted when cpu0 in wait mode - * 0b1..slice reset will be asserted when cpu0 in wait mode +/*! CPU0_WAIT - CPU mode setting for WAIT + * 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode + * 0b1..Slice reset will be asserted when CPU0 in WAIT mode */ #define SRC_DOMAIN_M4DEBUG_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_WAIT_MASK) + #define SRC_DOMAIN_M4DEBUG_CPU0_STOP_MASK (0x4U) #define SRC_DOMAIN_M4DEBUG_CPU0_STOP_SHIFT (2U) -/*! CPU0_STOP - * 0b0..slice reset will be de-asserted when cpu0 in stop mode - * 0b1..slice reset will be asserted when cpu0 in stop mode +/*! CPU0_STOP - CPU mode setting for STOP + * 0b0..Slice reset will be de-asserted when CPU0 in STOP mode + * 0b1..Slice reset will be asserted when CPU0 in STOP mode */ #define SRC_DOMAIN_M4DEBUG_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_STOP_MASK) + #define SRC_DOMAIN_M4DEBUG_CPU0_SUSP_MASK (0x8U) #define SRC_DOMAIN_M4DEBUG_CPU0_SUSP_SHIFT (3U) -/*! CPU0_SUSP - * 0b0..slice reset will be de-asserted when cpu0 in suspend mode - * 0b1..slice reset will be asserted when cpu0 in suspend mode +/*! CPU0_SUSP - CPU mode setting for SUSPEND + * 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode + * 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode */ #define SRC_DOMAIN_M4DEBUG_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_SUSP_MASK) + #define SRC_DOMAIN_M4DEBUG_CPU1_RUN_MASK (0x10U) #define SRC_DOMAIN_M4DEBUG_CPU1_RUN_SHIFT (4U) -/*! CPU1_RUN - * 0b0..slice reset will be de-asserted when cpu1 in run mode - * 0b1..slice reset will be asserted when cpu1 in run mode +/*! CPU1_RUN - CPU mode setting for RUN + * 0b0..Slice reset will be de-asserted when CPU1 in RUN mode + * 0b1..Slice reset will be asserted when CPU1 in RUN mode */ #define SRC_DOMAIN_M4DEBUG_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_RUN_MASK) + #define SRC_DOMAIN_M4DEBUG_CPU1_WAIT_MASK (0x20U) #define SRC_DOMAIN_M4DEBUG_CPU1_WAIT_SHIFT (5U) -/*! CPU1_WAIT - * 0b0..slice reset will be de-asserted when cpu1 in wait mode - * 0b1..slice reset will be asserted when cpu1 in wait mode +/*! CPU1_WAIT - CPU mode setting for WAIT + * 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode + * 0b1..Slice reset will be asserted when CPU1 in WAIT mode */ #define SRC_DOMAIN_M4DEBUG_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_WAIT_MASK) + #define SRC_DOMAIN_M4DEBUG_CPU1_STOP_MASK (0x40U) #define SRC_DOMAIN_M4DEBUG_CPU1_STOP_SHIFT (6U) -/*! CPU1_STOP - * 0b0..slice reset will be de-asserted when cpu1 in stop mode - * 0b1..slice reset will be asserted when cpu1 in stop mode +/*! CPU1_STOP - CPU mode setting for STOP + * 0b0..Slice reset will be de-asserted when CPU1 in STOP mode + * 0b1..Slice reset will be asserted when CPU1 in STOP mode */ #define SRC_DOMAIN_M4DEBUG_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_STOP_MASK) + #define SRC_DOMAIN_M4DEBUG_CPU1_SUSP_MASK (0x80U) #define SRC_DOMAIN_M4DEBUG_CPU1_SUSP_SHIFT (7U) -/*! CPU1_SUSP - * 0b0..slice reset will be de-asserted when cpu1 in suspend mode - * 0b1..slice reset will be asserted when cpu1 in suspend mode +/*! CPU1_SUSP - CPU mode setting for SUSPEND + * 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode + * 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode */ #define SRC_DOMAIN_M4DEBUG_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_SUSP_MASK) -#define SRC_DOMAIN_M4DEBUG_CPU2_RUN_MASK (0x100U) -#define SRC_DOMAIN_M4DEBUG_CPU2_RUN_SHIFT (8U) -/*! CPU2_RUN - * 0b0..slice reset will be de-asserted when cpu2 in run mode - * 0b1..slice reset will be asserted when cpu2 in run mode - */ -#define SRC_DOMAIN_M4DEBUG_CPU2_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU2_RUN_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU2_RUN_MASK) -#define SRC_DOMAIN_M4DEBUG_CPU2_WAIT_MASK (0x200U) -#define SRC_DOMAIN_M4DEBUG_CPU2_WAIT_SHIFT (9U) -/*! CPU2_WAIT - * 0b0..slice reset will be de-asserted when cpu2 in wait mode - * 0b1..slice reset will be asserted when cpu2 in wait mode - */ -#define SRC_DOMAIN_M4DEBUG_CPU2_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU2_WAIT_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU2_WAIT_MASK) -#define SRC_DOMAIN_M4DEBUG_CPU2_STOP_MASK (0x400U) -#define SRC_DOMAIN_M4DEBUG_CPU2_STOP_SHIFT (10U) -/*! CPU2_STOP - * 0b0..slice reset will be de-asserted when cpu2 in stop mode - * 0b1..slice reset will be asserted when cpu2 in stop mode - */ -#define SRC_DOMAIN_M4DEBUG_CPU2_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU2_STOP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU2_STOP_MASK) -#define SRC_DOMAIN_M4DEBUG_CPU2_SUSP_MASK (0x800U) -#define SRC_DOMAIN_M4DEBUG_CPU2_SUSP_SHIFT (11U) -/*! CPU2_SUSP - * 0b0..slice reset will be de-asserted when cpu2 in suspend mode - * 0b1..slice reset will be asserted when cpu2 in suspend mode - */ -#define SRC_DOMAIN_M4DEBUG_CPU2_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU2_SUSP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU2_SUSP_MASK) -#define SRC_DOMAIN_M4DEBUG_CPU3_RUN_MASK (0x1000U) -#define SRC_DOMAIN_M4DEBUG_CPU3_RUN_SHIFT (12U) -/*! CPU3_RUN - * 0b0..slice reset will be de-asserted when cpu3 in run mode - * 0b1..slice reset will be asserted when cpu3 in run mode - */ -#define SRC_DOMAIN_M4DEBUG_CPU3_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU3_RUN_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU3_RUN_MASK) -#define SRC_DOMAIN_M4DEBUG_CPU3_WAIT_MASK (0x2000U) -#define SRC_DOMAIN_M4DEBUG_CPU3_WAIT_SHIFT (13U) -/*! CPU3_WAIT - * 0b0..slice reset will be de-asserted when cpu3 in wait mode - * 0b1..slice reset will be asserted when cpu3 in wait mode - */ -#define SRC_DOMAIN_M4DEBUG_CPU3_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU3_WAIT_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU3_WAIT_MASK) -#define SRC_DOMAIN_M4DEBUG_CPU3_STOP_MASK (0x4000U) -#define SRC_DOMAIN_M4DEBUG_CPU3_STOP_SHIFT (14U) -/*! CPU3_STOP - * 0b0..slice reset will be de-asserted when cpu3 in stop mode - * 0b1..slice reset will be asserted when cpu3 in stop mode - */ -#define SRC_DOMAIN_M4DEBUG_CPU3_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU3_STOP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU3_STOP_MASK) -#define SRC_DOMAIN_M4DEBUG_CPU3_SUSP_MASK (0x8000U) -#define SRC_DOMAIN_M4DEBUG_CPU3_SUSP_SHIFT (15U) -/*! CPU3_SUSP - * 0b0..slice reset will be de-asserted when cpu3 in suspend mode - * 0b1..slice reset will be asserted when cpu3 in suspend mode - */ -#define SRC_DOMAIN_M4DEBUG_CPU3_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU3_SUSP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU3_SUSP_MASK) /*! @} */ /*! @name STAT_M4DEBUG - Slice Status Register */ /*! @{ */ + #define SRC_STAT_M4DEBUG_UNDER_RST_MASK (0x1U) #define SRC_STAT_M4DEBUG_UNDER_RST_SHIFT (0U) /*! UNDER_RST @@ -80588,6 +90034,7 @@ typedef struct { * 0b1..the reset is in process */ #define SRC_STAT_M4DEBUG_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_UNDER_RST_SHIFT)) & SRC_STAT_M4DEBUG_UNDER_RST_MASK) + #define SRC_STAT_M4DEBUG_RST_BY_HW_MASK (0x4U) #define SRC_STAT_M4DEBUG_RST_BY_HW_SHIFT (2U) /*! RST_BY_HW @@ -80595,6 +90042,7 @@ typedef struct { * 0b1..the reset is caused by the power mode transfer */ #define SRC_STAT_M4DEBUG_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_RST_BY_HW_SHIFT)) & SRC_STAT_M4DEBUG_RST_BY_HW_MASK) + #define SRC_STAT_M4DEBUG_RST_BY_SW_MASK (0x8U) #define SRC_STAT_M4DEBUG_RST_BY_SW_SHIFT (3U) /*! RST_BY_SW @@ -80606,53 +90054,63 @@ typedef struct { /*! @name AUTHEN_M7DEBUG - Slice Authentication Register */ /*! @{ */ + #define SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_MASK (0x1U) #define SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_SHIFT (0U) /*! DOMAIN_MODE - * 0b0..slice hardware reset will Not be triggered by cpu power mode transition - * 0b1..slice hardware reset will be triggered by cpu power mode transition. Do not set this bit and SETPOINT_MODE at the same time. + * 0b0..slice hardware reset will NOT be triggered by CPU power mode transition + * 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time. */ #define SRC_AUTHEN_M7DEBUG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_MASK) + #define SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_MASK (0x2U) #define SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_SHIFT (1U) /*! SETPOINT_MODE - * 0b0..slice hardware reset will Not be triggered by set point transition - * 0b1..slice hardware reset will be triggered by set point transition. Do not set this bit and DOMAIN_MODE at the same time. + * 0b0..slice hardware reset will NOT be triggered by Setpoint transition + * 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time. */ #define SRC_AUTHEN_M7DEBUG_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_MASK) + #define SRC_AUTHEN_M7DEBUG_LOCK_MODE_MASK (0x80U) #define SRC_AUTHEN_M7DEBUG_LOCK_MODE_SHIFT (7U) -/*! LOCK_MODE - domain/setpoint mode lock +/*! LOCK_MODE - Domain/Setpoint mode lock */ #define SRC_AUTHEN_M7DEBUG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_MODE_MASK) + #define SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_MASK (0xF00U) #define SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_SHIFT (8U) #define SRC_AUTHEN_M7DEBUG_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_MASK) + #define SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_MASK (0x8000U) #define SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_SHIFT (15U) /*! LOCK_ASSIGN - Assign list lock */ #define SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_MASK) + #define SRC_AUTHEN_M7DEBUG_WHITE_LIST_MASK (0xF0000U) #define SRC_AUTHEN_M7DEBUG_WHITE_LIST_SHIFT (16U) /*! WHITE_LIST - Domain ID white list */ #define SRC_AUTHEN_M7DEBUG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_WHITE_LIST_MASK) + #define SRC_AUTHEN_M7DEBUG_LOCK_LIST_MASK (0x800000U) #define SRC_AUTHEN_M7DEBUG_LOCK_LIST_SHIFT (23U) /*! LOCK_LIST - White list lock */ #define SRC_AUTHEN_M7DEBUG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_LIST_MASK) + #define SRC_AUTHEN_M7DEBUG_USER_MASK (0x1000000U) #define SRC_AUTHEN_M7DEBUG_USER_SHIFT (24U) /*! USER - Allow user mode access */ #define SRC_AUTHEN_M7DEBUG_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_USER_SHIFT)) & SRC_AUTHEN_M7DEBUG_USER_MASK) + #define SRC_AUTHEN_M7DEBUG_NONSECURE_MASK (0x2000000U) #define SRC_AUTHEN_M7DEBUG_NONSECURE_SHIFT (25U) /*! NONSECURE - Allow non-secure mode access */ #define SRC_AUTHEN_M7DEBUG_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_NONSECURE_SHIFT)) & SRC_AUTHEN_M7DEBUG_NONSECURE_MASK) + #define SRC_AUTHEN_M7DEBUG_LOCK_SETTING_MASK (0x80000000U) #define SRC_AUTHEN_M7DEBUG_LOCK_SETTING_SHIFT (31U) /*! LOCK_SETTING - Lock NONSECURE and USER @@ -80662,6 +90120,7 @@ typedef struct { /*! @name CTRL_M7DEBUG - Slice Control Register */ /*! @{ */ + #define SRC_CTRL_M7DEBUG_SW_RESET_MASK (0x1U) #define SRC_CTRL_M7DEBUG_SW_RESET_SHIFT (0U) /*! SW_RESET @@ -80671,240 +90130,209 @@ typedef struct { #define SRC_CTRL_M7DEBUG_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M7DEBUG_SW_RESET_SHIFT)) & SRC_CTRL_M7DEBUG_SW_RESET_MASK) /*! @} */ -/*! @name SETPOINT_M7DEBUG - Slice SetPoint Config Register */ +/*! @name SETPOINT_M7DEBUG - Slice Setpoint Config Register */ /*! @{ */ + #define SRC_SETPOINT_M7DEBUG_SETPOINT0_MASK (0x1U) #define SRC_SETPOINT_M7DEBUG_SETPOINT0_SHIFT (0U) -/*! SETPOINT0 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT0 - SETPOINT0 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7DEBUG_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT0_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT0_MASK) + #define SRC_SETPOINT_M7DEBUG_SETPOINT1_MASK (0x2U) #define SRC_SETPOINT_M7DEBUG_SETPOINT1_SHIFT (1U) -/*! SETPOINT1 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT1 - SETPOINT1 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7DEBUG_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT1_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT1_MASK) + #define SRC_SETPOINT_M7DEBUG_SETPOINT2_MASK (0x4U) #define SRC_SETPOINT_M7DEBUG_SETPOINT2_SHIFT (2U) -/*! SETPOINT2 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT2 - SETPOINT2 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7DEBUG_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT2_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT2_MASK) + #define SRC_SETPOINT_M7DEBUG_SETPOINT3_MASK (0x8U) #define SRC_SETPOINT_M7DEBUG_SETPOINT3_SHIFT (3U) -/*! SETPOINT3 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT3 - SETPOINT3 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7DEBUG_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT3_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT3_MASK) + #define SRC_SETPOINT_M7DEBUG_SETPOINT4_MASK (0x10U) #define SRC_SETPOINT_M7DEBUG_SETPOINT4_SHIFT (4U) -/*! SETPOINT4 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT4 - SETPOINT4 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7DEBUG_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT4_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT4_MASK) + #define SRC_SETPOINT_M7DEBUG_SETPOINT5_MASK (0x20U) #define SRC_SETPOINT_M7DEBUG_SETPOINT5_SHIFT (5U) -/*! SETPOINT5 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT5 - SETPOINT5 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7DEBUG_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT5_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT5_MASK) + #define SRC_SETPOINT_M7DEBUG_SETPOINT6_MASK (0x40U) #define SRC_SETPOINT_M7DEBUG_SETPOINT6_SHIFT (6U) -/*! SETPOINT6 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT6 - SETPOINT6 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7DEBUG_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT6_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT6_MASK) + #define SRC_SETPOINT_M7DEBUG_SETPOINT7_MASK (0x80U) #define SRC_SETPOINT_M7DEBUG_SETPOINT7_SHIFT (7U) -/*! SETPOINT7 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT7 - SETPOINT7 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7DEBUG_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT7_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT7_MASK) + #define SRC_SETPOINT_M7DEBUG_SETPOINT8_MASK (0x100U) #define SRC_SETPOINT_M7DEBUG_SETPOINT8_SHIFT (8U) -/*! SETPOINT8 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT8 - SETPOINT8 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7DEBUG_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT8_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT8_MASK) + #define SRC_SETPOINT_M7DEBUG_SETPOINT9_MASK (0x200U) #define SRC_SETPOINT_M7DEBUG_SETPOINT9_SHIFT (9U) -/*! SETPOINT9 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT9 - SETPOINT9 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7DEBUG_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT9_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT9_MASK) + #define SRC_SETPOINT_M7DEBUG_SETPOINT10_MASK (0x400U) #define SRC_SETPOINT_M7DEBUG_SETPOINT10_SHIFT (10U) -/*! SETPOINT10 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT10 - SETPOINT10 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7DEBUG_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT10_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT10_MASK) + #define SRC_SETPOINT_M7DEBUG_SETPOINT11_MASK (0x800U) #define SRC_SETPOINT_M7DEBUG_SETPOINT11_SHIFT (11U) -/*! SETPOINT11 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT11 - SETPOINT11 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7DEBUG_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT11_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT11_MASK) + #define SRC_SETPOINT_M7DEBUG_SETPOINT12_MASK (0x1000U) #define SRC_SETPOINT_M7DEBUG_SETPOINT12_SHIFT (12U) -/*! SETPOINT12 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT12 - SETPOINT12 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7DEBUG_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT12_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT12_MASK) + #define SRC_SETPOINT_M7DEBUG_SETPOINT13_MASK (0x2000U) #define SRC_SETPOINT_M7DEBUG_SETPOINT13_SHIFT (13U) -/*! SETPOINT13 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT13 - SETPOINT13 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7DEBUG_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT13_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT13_MASK) + #define SRC_SETPOINT_M7DEBUG_SETPOINT14_MASK (0x4000U) #define SRC_SETPOINT_M7DEBUG_SETPOINT14_SHIFT (14U) -/*! SETPOINT14 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT14 - SETPOINT14 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7DEBUG_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT14_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT14_MASK) + #define SRC_SETPOINT_M7DEBUG_SETPOINT15_MASK (0x8000U) #define SRC_SETPOINT_M7DEBUG_SETPOINT15_SHIFT (15U) -/*! SETPOINT15 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT15 - SETPOINT15 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_M7DEBUG_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT15_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT15_MASK) /*! @} */ /*! @name DOMAIN_M7DEBUG - Slice Domain Config Register */ /*! @{ */ + #define SRC_DOMAIN_M7DEBUG_CPU0_RUN_MASK (0x1U) #define SRC_DOMAIN_M7DEBUG_CPU0_RUN_SHIFT (0U) -/*! CPU0_RUN - * 0b0..slice reset will be de-asserted when cpu0 in run mode - * 0b1..slice reset will be asserted when cpu0 in run mode +/*! CPU0_RUN - CPU mode setting for RUN + * 0b0..Slice reset will be de-asserted when CPU0 in RUN mode + * 0b1..Slice reset will be asserted when CPU0 in RUN mode */ #define SRC_DOMAIN_M7DEBUG_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_RUN_MASK) + #define SRC_DOMAIN_M7DEBUG_CPU0_WAIT_MASK (0x2U) #define SRC_DOMAIN_M7DEBUG_CPU0_WAIT_SHIFT (1U) -/*! CPU0_WAIT - * 0b0..slice reset will be de-asserted when cpu0 in wait mode - * 0b1..slice reset will be asserted when cpu0 in wait mode +/*! CPU0_WAIT - CPU mode setting for WAIT + * 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode + * 0b1..Slice reset will be asserted when CPU0 in WAIT mode */ #define SRC_DOMAIN_M7DEBUG_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_WAIT_MASK) + #define SRC_DOMAIN_M7DEBUG_CPU0_STOP_MASK (0x4U) #define SRC_DOMAIN_M7DEBUG_CPU0_STOP_SHIFT (2U) -/*! CPU0_STOP - * 0b0..slice reset will be de-asserted when cpu0 in stop mode - * 0b1..slice reset will be asserted when cpu0 in stop mode +/*! CPU0_STOP - CPU mode setting for STOP + * 0b0..Slice reset will be de-asserted when CPU0 in STOP mode + * 0b1..Slice reset will be asserted when CPU0 in STOP mode */ #define SRC_DOMAIN_M7DEBUG_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_STOP_MASK) + #define SRC_DOMAIN_M7DEBUG_CPU0_SUSP_MASK (0x8U) #define SRC_DOMAIN_M7DEBUG_CPU0_SUSP_SHIFT (3U) -/*! CPU0_SUSP - * 0b0..slice reset will be de-asserted when cpu0 in suspend mode - * 0b1..slice reset will be asserted when cpu0 in suspend mode +/*! CPU0_SUSP - CPU mode setting for SUSPEND + * 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode + * 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode */ #define SRC_DOMAIN_M7DEBUG_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_SUSP_MASK) + #define SRC_DOMAIN_M7DEBUG_CPU1_RUN_MASK (0x10U) #define SRC_DOMAIN_M7DEBUG_CPU1_RUN_SHIFT (4U) -/*! CPU1_RUN - * 0b0..slice reset will be de-asserted when cpu1 in run mode - * 0b1..slice reset will be asserted when cpu1 in run mode +/*! CPU1_RUN - CPU mode setting for RUN + * 0b0..Slice reset will be de-asserted when CPU1 in RUN mode + * 0b1..Slice reset will be asserted when CPU1 in RUN mode */ #define SRC_DOMAIN_M7DEBUG_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_RUN_MASK) + #define SRC_DOMAIN_M7DEBUG_CPU1_WAIT_MASK (0x20U) #define SRC_DOMAIN_M7DEBUG_CPU1_WAIT_SHIFT (5U) -/*! CPU1_WAIT - * 0b0..slice reset will be de-asserted when cpu1 in wait mode - * 0b1..slice reset will be asserted when cpu1 in wait mode +/*! CPU1_WAIT - CPU mode setting for WAIT + * 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode + * 0b1..Slice reset will be asserted when CPU1 in WAIT mode */ #define SRC_DOMAIN_M7DEBUG_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_WAIT_MASK) + #define SRC_DOMAIN_M7DEBUG_CPU1_STOP_MASK (0x40U) #define SRC_DOMAIN_M7DEBUG_CPU1_STOP_SHIFT (6U) -/*! CPU1_STOP - * 0b0..slice reset will be de-asserted when cpu1 in stop mode - * 0b1..slice reset will be asserted when cpu1 in stop mode +/*! CPU1_STOP - CPU mode setting for STOP + * 0b0..Slice reset will be de-asserted when CPU1 in STOP mode + * 0b1..Slice reset will be asserted when CPU1 in STOP mode */ #define SRC_DOMAIN_M7DEBUG_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_STOP_MASK) + #define SRC_DOMAIN_M7DEBUG_CPU1_SUSP_MASK (0x80U) #define SRC_DOMAIN_M7DEBUG_CPU1_SUSP_SHIFT (7U) -/*! CPU1_SUSP - * 0b0..slice reset will be de-asserted when cpu1 in suspend mode - * 0b1..slice reset will be asserted when cpu1 in suspend mode +/*! CPU1_SUSP - CPU mode setting for SUSPEND + * 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode + * 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode */ #define SRC_DOMAIN_M7DEBUG_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_SUSP_MASK) -#define SRC_DOMAIN_M7DEBUG_CPU2_RUN_MASK (0x100U) -#define SRC_DOMAIN_M7DEBUG_CPU2_RUN_SHIFT (8U) -/*! CPU2_RUN - * 0b0..slice reset will be de-asserted when cpu2 in run mode - * 0b1..slice reset will be asserted when cpu2 in run mode - */ -#define SRC_DOMAIN_M7DEBUG_CPU2_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU2_RUN_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU2_RUN_MASK) -#define SRC_DOMAIN_M7DEBUG_CPU2_WAIT_MASK (0x200U) -#define SRC_DOMAIN_M7DEBUG_CPU2_WAIT_SHIFT (9U) -/*! CPU2_WAIT - * 0b0..slice reset will be de-asserted when cpu2 in wait mode - * 0b1..slice reset will be asserted when cpu2 in wait mode - */ -#define SRC_DOMAIN_M7DEBUG_CPU2_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU2_WAIT_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU2_WAIT_MASK) -#define SRC_DOMAIN_M7DEBUG_CPU2_STOP_MASK (0x400U) -#define SRC_DOMAIN_M7DEBUG_CPU2_STOP_SHIFT (10U) -/*! CPU2_STOP - * 0b0..slice reset will be de-asserted when cpu2 in stop mode - * 0b1..slice reset will be asserted when cpu2 in stop mode - */ -#define SRC_DOMAIN_M7DEBUG_CPU2_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU2_STOP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU2_STOP_MASK) -#define SRC_DOMAIN_M7DEBUG_CPU2_SUSP_MASK (0x800U) -#define SRC_DOMAIN_M7DEBUG_CPU2_SUSP_SHIFT (11U) -/*! CPU2_SUSP - * 0b0..slice reset will be de-asserted when cpu2 in suspend mode - * 0b1..slice reset will be asserted when cpu2 in suspend mode - */ -#define SRC_DOMAIN_M7DEBUG_CPU2_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU2_SUSP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU2_SUSP_MASK) -#define SRC_DOMAIN_M7DEBUG_CPU3_RUN_MASK (0x1000U) -#define SRC_DOMAIN_M7DEBUG_CPU3_RUN_SHIFT (12U) -/*! CPU3_RUN - * 0b0..slice reset will be de-asserted when cpu3 in run mode - * 0b1..slice reset will be asserted when cpu3 in run mode - */ -#define SRC_DOMAIN_M7DEBUG_CPU3_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU3_RUN_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU3_RUN_MASK) -#define SRC_DOMAIN_M7DEBUG_CPU3_WAIT_MASK (0x2000U) -#define SRC_DOMAIN_M7DEBUG_CPU3_WAIT_SHIFT (13U) -/*! CPU3_WAIT - * 0b0..slice reset will be de-asserted when cpu3 in wait mode - * 0b1..slice reset will be asserted when cpu3 in wait mode - */ -#define SRC_DOMAIN_M7DEBUG_CPU3_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU3_WAIT_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU3_WAIT_MASK) -#define SRC_DOMAIN_M7DEBUG_CPU3_STOP_MASK (0x4000U) -#define SRC_DOMAIN_M7DEBUG_CPU3_STOP_SHIFT (14U) -/*! CPU3_STOP - * 0b0..slice reset will be de-asserted when cpu3 in stop mode - * 0b1..slice reset will be asserted when cpu3 in stop mode - */ -#define SRC_DOMAIN_M7DEBUG_CPU3_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU3_STOP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU3_STOP_MASK) -#define SRC_DOMAIN_M7DEBUG_CPU3_SUSP_MASK (0x8000U) -#define SRC_DOMAIN_M7DEBUG_CPU3_SUSP_SHIFT (15U) -/*! CPU3_SUSP - * 0b0..slice reset will be de-asserted when cpu3 in suspend mode - * 0b1..slice reset will be asserted when cpu3 in suspend mode - */ -#define SRC_DOMAIN_M7DEBUG_CPU3_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU3_SUSP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU3_SUSP_MASK) /*! @} */ /*! @name STAT_M7DEBUG - Slice Status Register */ /*! @{ */ + #define SRC_STAT_M7DEBUG_UNDER_RST_MASK (0x1U) #define SRC_STAT_M7DEBUG_UNDER_RST_SHIFT (0U) /*! UNDER_RST @@ -80912,6 +90340,7 @@ typedef struct { * 0b1..the reset is in process */ #define SRC_STAT_M7DEBUG_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_UNDER_RST_SHIFT)) & SRC_STAT_M7DEBUG_UNDER_RST_MASK) + #define SRC_STAT_M7DEBUG_RST_BY_HW_MASK (0x4U) #define SRC_STAT_M7DEBUG_RST_BY_HW_SHIFT (2U) /*! RST_BY_HW @@ -80919,6 +90348,7 @@ typedef struct { * 0b1..the reset is caused by the power mode transfer */ #define SRC_STAT_M7DEBUG_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_RST_BY_HW_SHIFT)) & SRC_STAT_M7DEBUG_RST_BY_HW_MASK) + #define SRC_STAT_M7DEBUG_RST_BY_SW_MASK (0x8U) #define SRC_STAT_M7DEBUG_RST_BY_SW_SHIFT (3U) /*! RST_BY_SW @@ -80930,53 +90360,63 @@ typedef struct { /*! @name AUTHEN_USBPHY1 - Slice Authentication Register */ /*! @{ */ + #define SRC_AUTHEN_USBPHY1_DOMAIN_MODE_MASK (0x1U) #define SRC_AUTHEN_USBPHY1_DOMAIN_MODE_SHIFT (0U) /*! DOMAIN_MODE - * 0b0..slice hardware reset will Not be triggered by cpu power mode transition - * 0b1..slice hardware reset will be triggered by cpu power mode transition. Do not set this bit and SETPOINT_MODE at the same time. + * 0b0..slice hardware reset will NOT be triggered by CPU power mode transition + * 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time. */ #define SRC_AUTHEN_USBPHY1_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_DOMAIN_MODE_MASK) + #define SRC_AUTHEN_USBPHY1_SETPOINT_MODE_MASK (0x2U) #define SRC_AUTHEN_USBPHY1_SETPOINT_MODE_SHIFT (1U) /*! SETPOINT_MODE - * 0b0..slice hardware reset will Not be triggered by set point transition - * 0b1..slice hardware reset will be triggered by set point transition. Do not set this bit and DOMAIN_MODE at the same time. + * 0b0..slice hardware reset will NOT be triggered by Setpoint transition + * 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time. */ #define SRC_AUTHEN_USBPHY1_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_SETPOINT_MODE_MASK) + #define SRC_AUTHEN_USBPHY1_LOCK_MODE_MASK (0x80U) #define SRC_AUTHEN_USBPHY1_LOCK_MODE_SHIFT (7U) -/*! LOCK_MODE - domain/setpoint mode lock +/*! LOCK_MODE - Domain/Setpoint mode lock */ #define SRC_AUTHEN_USBPHY1_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_MODE_MASK) + #define SRC_AUTHEN_USBPHY1_ASSIGN_LIST_MASK (0xF00U) #define SRC_AUTHEN_USBPHY1_ASSIGN_LIST_SHIFT (8U) #define SRC_AUTHEN_USBPHY1_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_ASSIGN_LIST_MASK) + #define SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_MASK (0x8000U) #define SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_SHIFT (15U) /*! LOCK_ASSIGN - Assign list lock */ #define SRC_AUTHEN_USBPHY1_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_MASK) + #define SRC_AUTHEN_USBPHY1_WHITE_LIST_MASK (0xF0000U) #define SRC_AUTHEN_USBPHY1_WHITE_LIST_SHIFT (16U) /*! WHITE_LIST - Domain ID white list */ #define SRC_AUTHEN_USBPHY1_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_WHITE_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_WHITE_LIST_MASK) + #define SRC_AUTHEN_USBPHY1_LOCK_LIST_MASK (0x800000U) #define SRC_AUTHEN_USBPHY1_LOCK_LIST_SHIFT (23U) /*! LOCK_LIST - White list lock */ #define SRC_AUTHEN_USBPHY1_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_LIST_MASK) + #define SRC_AUTHEN_USBPHY1_USER_MASK (0x1000000U) #define SRC_AUTHEN_USBPHY1_USER_SHIFT (24U) /*! USER - Allow user mode access */ #define SRC_AUTHEN_USBPHY1_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_USER_SHIFT)) & SRC_AUTHEN_USBPHY1_USER_MASK) + #define SRC_AUTHEN_USBPHY1_NONSECURE_MASK (0x2000000U) #define SRC_AUTHEN_USBPHY1_NONSECURE_SHIFT (25U) /*! NONSECURE - Allow non-secure mode access */ #define SRC_AUTHEN_USBPHY1_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_NONSECURE_SHIFT)) & SRC_AUTHEN_USBPHY1_NONSECURE_MASK) + #define SRC_AUTHEN_USBPHY1_LOCK_SETTING_MASK (0x80000000U) #define SRC_AUTHEN_USBPHY1_LOCK_SETTING_SHIFT (31U) /*! LOCK_SETTING - Lock NONSECURE and USER @@ -80986,6 +90426,7 @@ typedef struct { /*! @name CTRL_USBPHY1 - Slice Control Register */ /*! @{ */ + #define SRC_CTRL_USBPHY1_SW_RESET_MASK (0x1U) #define SRC_CTRL_USBPHY1_SW_RESET_SHIFT (0U) /*! SW_RESET @@ -80995,240 +90436,209 @@ typedef struct { #define SRC_CTRL_USBPHY1_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_USBPHY1_SW_RESET_SHIFT)) & SRC_CTRL_USBPHY1_SW_RESET_MASK) /*! @} */ -/*! @name SETPOINT_USBPHY1 - Slice SetPoint Config Register */ +/*! @name SETPOINT_USBPHY1 - Slice Setpoint Config Register */ /*! @{ */ + #define SRC_SETPOINT_USBPHY1_SETPOINT0_MASK (0x1U) #define SRC_SETPOINT_USBPHY1_SETPOINT0_SHIFT (0U) -/*! SETPOINT0 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT0 - SETPOINT0 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY1_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT0_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT0_MASK) + #define SRC_SETPOINT_USBPHY1_SETPOINT1_MASK (0x2U) #define SRC_SETPOINT_USBPHY1_SETPOINT1_SHIFT (1U) -/*! SETPOINT1 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT1 - SETPOINT1 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY1_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT1_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT1_MASK) + #define SRC_SETPOINT_USBPHY1_SETPOINT2_MASK (0x4U) #define SRC_SETPOINT_USBPHY1_SETPOINT2_SHIFT (2U) -/*! SETPOINT2 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT2 - SETPOINT2 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY1_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT2_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT2_MASK) + #define SRC_SETPOINT_USBPHY1_SETPOINT3_MASK (0x8U) #define SRC_SETPOINT_USBPHY1_SETPOINT3_SHIFT (3U) -/*! SETPOINT3 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT3 - SETPOINT3 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY1_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT3_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT3_MASK) + #define SRC_SETPOINT_USBPHY1_SETPOINT4_MASK (0x10U) #define SRC_SETPOINT_USBPHY1_SETPOINT4_SHIFT (4U) -/*! SETPOINT4 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT4 - SETPOINT4 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY1_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT4_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT4_MASK) + #define SRC_SETPOINT_USBPHY1_SETPOINT5_MASK (0x20U) #define SRC_SETPOINT_USBPHY1_SETPOINT5_SHIFT (5U) -/*! SETPOINT5 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT5 - SETPOINT5 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY1_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT5_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT5_MASK) + #define SRC_SETPOINT_USBPHY1_SETPOINT6_MASK (0x40U) #define SRC_SETPOINT_USBPHY1_SETPOINT6_SHIFT (6U) -/*! SETPOINT6 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT6 - SETPOINT6 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY1_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT6_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT6_MASK) + #define SRC_SETPOINT_USBPHY1_SETPOINT7_MASK (0x80U) #define SRC_SETPOINT_USBPHY1_SETPOINT7_SHIFT (7U) -/*! SETPOINT7 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT7 - SETPOINT7 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY1_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT7_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT7_MASK) + #define SRC_SETPOINT_USBPHY1_SETPOINT8_MASK (0x100U) #define SRC_SETPOINT_USBPHY1_SETPOINT8_SHIFT (8U) -/*! SETPOINT8 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT8 - SETPOINT8 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY1_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT8_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT8_MASK) + #define SRC_SETPOINT_USBPHY1_SETPOINT9_MASK (0x200U) #define SRC_SETPOINT_USBPHY1_SETPOINT9_SHIFT (9U) -/*! SETPOINT9 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT9 - SETPOINT9 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY1_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT9_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT9_MASK) + #define SRC_SETPOINT_USBPHY1_SETPOINT10_MASK (0x400U) #define SRC_SETPOINT_USBPHY1_SETPOINT10_SHIFT (10U) -/*! SETPOINT10 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT10 - SETPOINT10 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY1_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT10_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT10_MASK) + #define SRC_SETPOINT_USBPHY1_SETPOINT11_MASK (0x800U) #define SRC_SETPOINT_USBPHY1_SETPOINT11_SHIFT (11U) -/*! SETPOINT11 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT11 - SETPOINT11 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY1_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT11_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT11_MASK) + #define SRC_SETPOINT_USBPHY1_SETPOINT12_MASK (0x1000U) #define SRC_SETPOINT_USBPHY1_SETPOINT12_SHIFT (12U) -/*! SETPOINT12 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT12 - SETPOINT12 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY1_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT12_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT12_MASK) + #define SRC_SETPOINT_USBPHY1_SETPOINT13_MASK (0x2000U) #define SRC_SETPOINT_USBPHY1_SETPOINT13_SHIFT (13U) -/*! SETPOINT13 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT13 - SETPOINT13 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY1_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT13_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT13_MASK) + #define SRC_SETPOINT_USBPHY1_SETPOINT14_MASK (0x4000U) #define SRC_SETPOINT_USBPHY1_SETPOINT14_SHIFT (14U) -/*! SETPOINT14 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT14 - SETPOINT14 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY1_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT14_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT14_MASK) + #define SRC_SETPOINT_USBPHY1_SETPOINT15_MASK (0x8000U) #define SRC_SETPOINT_USBPHY1_SETPOINT15_SHIFT (15U) -/*! SETPOINT15 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT15 - SETPOINT15 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY1_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT15_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT15_MASK) /*! @} */ /*! @name DOMAIN_USBPHY1 - Slice Domain Config Register */ /*! @{ */ + #define SRC_DOMAIN_USBPHY1_CPU0_RUN_MASK (0x1U) #define SRC_DOMAIN_USBPHY1_CPU0_RUN_SHIFT (0U) -/*! CPU0_RUN - * 0b0..slice reset will be de-asserted when cpu0 in run mode - * 0b1..slice reset will be asserted when cpu0 in run mode +/*! CPU0_RUN - CPU mode setting for RUN + * 0b0..Slice reset will be de-asserted when CPU0 in RUN mode + * 0b1..Slice reset will be asserted when CPU0 in RUN mode */ #define SRC_DOMAIN_USBPHY1_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_RUN_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_RUN_MASK) + #define SRC_DOMAIN_USBPHY1_CPU0_WAIT_MASK (0x2U) #define SRC_DOMAIN_USBPHY1_CPU0_WAIT_SHIFT (1U) -/*! CPU0_WAIT - * 0b0..slice reset will be de-asserted when cpu0 in wait mode - * 0b1..slice reset will be asserted when cpu0 in wait mode +/*! CPU0_WAIT - CPU mode setting for WAIT + * 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode + * 0b1..Slice reset will be asserted when CPU0 in WAIT mode */ #define SRC_DOMAIN_USBPHY1_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_WAIT_MASK) + #define SRC_DOMAIN_USBPHY1_CPU0_STOP_MASK (0x4U) #define SRC_DOMAIN_USBPHY1_CPU0_STOP_SHIFT (2U) -/*! CPU0_STOP - * 0b0..slice reset will be de-asserted when cpu0 in stop mode - * 0b1..slice reset will be asserted when cpu0 in stop mode +/*! CPU0_STOP - CPU mode setting for STOP + * 0b0..Slice reset will be de-asserted when CPU0 in STOP mode + * 0b1..Slice reset will be asserted when CPU0 in STOP mode */ #define SRC_DOMAIN_USBPHY1_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_STOP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_STOP_MASK) + #define SRC_DOMAIN_USBPHY1_CPU0_SUSP_MASK (0x8U) #define SRC_DOMAIN_USBPHY1_CPU0_SUSP_SHIFT (3U) -/*! CPU0_SUSP - * 0b0..slice reset will be de-asserted when cpu0 in suspend mode - * 0b1..slice reset will be asserted when cpu0 in suspend mode +/*! CPU0_SUSP - CPU mode setting for SUSPEND + * 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode + * 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode */ #define SRC_DOMAIN_USBPHY1_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_SUSP_MASK) + #define SRC_DOMAIN_USBPHY1_CPU1_RUN_MASK (0x10U) #define SRC_DOMAIN_USBPHY1_CPU1_RUN_SHIFT (4U) -/*! CPU1_RUN - * 0b0..slice reset will be de-asserted when cpu1 in run mode - * 0b1..slice reset will be asserted when cpu1 in run mode +/*! CPU1_RUN - CPU mode setting for RUN + * 0b0..Slice reset will be de-asserted when CPU1 in RUN mode + * 0b1..Slice reset will be asserted when CPU1 in RUN mode */ #define SRC_DOMAIN_USBPHY1_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_RUN_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_RUN_MASK) + #define SRC_DOMAIN_USBPHY1_CPU1_WAIT_MASK (0x20U) #define SRC_DOMAIN_USBPHY1_CPU1_WAIT_SHIFT (5U) -/*! CPU1_WAIT - * 0b0..slice reset will be de-asserted when cpu1 in wait mode - * 0b1..slice reset will be asserted when cpu1 in wait mode +/*! CPU1_WAIT - CPU mode setting for WAIT + * 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode + * 0b1..Slice reset will be asserted when CPU1 in WAIT mode */ #define SRC_DOMAIN_USBPHY1_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_WAIT_MASK) + #define SRC_DOMAIN_USBPHY1_CPU1_STOP_MASK (0x40U) #define SRC_DOMAIN_USBPHY1_CPU1_STOP_SHIFT (6U) -/*! CPU1_STOP - * 0b0..slice reset will be de-asserted when cpu1 in stop mode - * 0b1..slice reset will be asserted when cpu1 in stop mode +/*! CPU1_STOP - CPU mode setting for STOP + * 0b0..Slice reset will be de-asserted when CPU1 in STOP mode + * 0b1..Slice reset will be asserted when CPU1 in STOP mode */ #define SRC_DOMAIN_USBPHY1_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_STOP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_STOP_MASK) + #define SRC_DOMAIN_USBPHY1_CPU1_SUSP_MASK (0x80U) #define SRC_DOMAIN_USBPHY1_CPU1_SUSP_SHIFT (7U) -/*! CPU1_SUSP - * 0b0..slice reset will be de-asserted when cpu1 in suspend mode - * 0b1..slice reset will be asserted when cpu1 in suspend mode +/*! CPU1_SUSP - CPU mode setting for SUSPEND + * 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode + * 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode */ #define SRC_DOMAIN_USBPHY1_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_SUSP_MASK) -#define SRC_DOMAIN_USBPHY1_CPU2_RUN_MASK (0x100U) -#define SRC_DOMAIN_USBPHY1_CPU2_RUN_SHIFT (8U) -/*! CPU2_RUN - * 0b0..slice reset will be de-asserted when cpu2 in run mode - * 0b1..slice reset will be asserted when cpu2 in run mode - */ -#define SRC_DOMAIN_USBPHY1_CPU2_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU2_RUN_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU2_RUN_MASK) -#define SRC_DOMAIN_USBPHY1_CPU2_WAIT_MASK (0x200U) -#define SRC_DOMAIN_USBPHY1_CPU2_WAIT_SHIFT (9U) -/*! CPU2_WAIT - * 0b0..slice reset will be de-asserted when cpu2 in wait mode - * 0b1..slice reset will be asserted when cpu2 in wait mode - */ -#define SRC_DOMAIN_USBPHY1_CPU2_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU2_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU2_WAIT_MASK) -#define SRC_DOMAIN_USBPHY1_CPU2_STOP_MASK (0x400U) -#define SRC_DOMAIN_USBPHY1_CPU2_STOP_SHIFT (10U) -/*! CPU2_STOP - * 0b0..slice reset will be de-asserted when cpu2 in stop mode - * 0b1..slice reset will be asserted when cpu2 in stop mode - */ -#define SRC_DOMAIN_USBPHY1_CPU2_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU2_STOP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU2_STOP_MASK) -#define SRC_DOMAIN_USBPHY1_CPU2_SUSP_MASK (0x800U) -#define SRC_DOMAIN_USBPHY1_CPU2_SUSP_SHIFT (11U) -/*! CPU2_SUSP - * 0b0..slice reset will be de-asserted when cpu2 in suspend mode - * 0b1..slice reset will be asserted when cpu2 in suspend mode - */ -#define SRC_DOMAIN_USBPHY1_CPU2_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU2_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU2_SUSP_MASK) -#define SRC_DOMAIN_USBPHY1_CPU3_RUN_MASK (0x1000U) -#define SRC_DOMAIN_USBPHY1_CPU3_RUN_SHIFT (12U) -/*! CPU3_RUN - * 0b0..slice reset will be de-asserted when cpu3 in run mode - * 0b1..slice reset will be asserted when cpu3 in run mode - */ -#define SRC_DOMAIN_USBPHY1_CPU3_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU3_RUN_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU3_RUN_MASK) -#define SRC_DOMAIN_USBPHY1_CPU3_WAIT_MASK (0x2000U) -#define SRC_DOMAIN_USBPHY1_CPU3_WAIT_SHIFT (13U) -/*! CPU3_WAIT - * 0b0..slice reset will be de-asserted when cpu3 in wait mode - * 0b1..slice reset will be asserted when cpu3 in wait mode - */ -#define SRC_DOMAIN_USBPHY1_CPU3_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU3_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU3_WAIT_MASK) -#define SRC_DOMAIN_USBPHY1_CPU3_STOP_MASK (0x4000U) -#define SRC_DOMAIN_USBPHY1_CPU3_STOP_SHIFT (14U) -/*! CPU3_STOP - * 0b0..slice reset will be de-asserted when cpu3 in stop mode - * 0b1..slice reset will be asserted when cpu3 in stop mode - */ -#define SRC_DOMAIN_USBPHY1_CPU3_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU3_STOP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU3_STOP_MASK) -#define SRC_DOMAIN_USBPHY1_CPU3_SUSP_MASK (0x8000U) -#define SRC_DOMAIN_USBPHY1_CPU3_SUSP_SHIFT (15U) -/*! CPU3_SUSP - * 0b0..slice reset will be de-asserted when cpu3 in suspend mode - * 0b1..slice reset will be asserted when cpu3 in suspend mode - */ -#define SRC_DOMAIN_USBPHY1_CPU3_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU3_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU3_SUSP_MASK) /*! @} */ /*! @name STAT_USBPHY1 - Slice Status Register */ /*! @{ */ + #define SRC_STAT_USBPHY1_UNDER_RST_MASK (0x1U) #define SRC_STAT_USBPHY1_UNDER_RST_SHIFT (0U) /*! UNDER_RST @@ -81236,6 +90646,7 @@ typedef struct { * 0b1..the reset is in process */ #define SRC_STAT_USBPHY1_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_UNDER_RST_SHIFT)) & SRC_STAT_USBPHY1_UNDER_RST_MASK) + #define SRC_STAT_USBPHY1_RST_BY_HW_MASK (0x4U) #define SRC_STAT_USBPHY1_RST_BY_HW_SHIFT (2U) /*! RST_BY_HW @@ -81243,6 +90654,7 @@ typedef struct { * 0b1..the reset is caused by the power mode transfer */ #define SRC_STAT_USBPHY1_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_RST_BY_HW_SHIFT)) & SRC_STAT_USBPHY1_RST_BY_HW_MASK) + #define SRC_STAT_USBPHY1_RST_BY_SW_MASK (0x8U) #define SRC_STAT_USBPHY1_RST_BY_SW_SHIFT (3U) /*! RST_BY_SW @@ -81254,53 +90666,63 @@ typedef struct { /*! @name AUTHEN_USBPHY2 - Slice Authentication Register */ /*! @{ */ + #define SRC_AUTHEN_USBPHY2_DOMAIN_MODE_MASK (0x1U) #define SRC_AUTHEN_USBPHY2_DOMAIN_MODE_SHIFT (0U) /*! DOMAIN_MODE - * 0b0..slice hardware reset will Not be triggered by cpu power mode transition - * 0b1..slice hardware reset will be triggered by cpu power mode transition. Do not set this bit and SETPOINT_MODE at the same time. + * 0b0..slice hardware reset will NOT be triggered by CPU power mode transition + * 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time. */ #define SRC_AUTHEN_USBPHY2_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_DOMAIN_MODE_MASK) + #define SRC_AUTHEN_USBPHY2_SETPOINT_MODE_MASK (0x2U) #define SRC_AUTHEN_USBPHY2_SETPOINT_MODE_SHIFT (1U) /*! SETPOINT_MODE - * 0b0..slice hardware reset will Not be triggered by set point transition - * 0b1..slice hardware reset will be triggered by set point transition. Do not set this bit and DOMAIN_MODE at the same time. + * 0b0..slice hardware reset will NOT be triggered by Setpoint transition + * 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time. */ #define SRC_AUTHEN_USBPHY2_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_SETPOINT_MODE_MASK) + #define SRC_AUTHEN_USBPHY2_LOCK_MODE_MASK (0x80U) #define SRC_AUTHEN_USBPHY2_LOCK_MODE_SHIFT (7U) -/*! LOCK_MODE - domain/setpoint mode lock +/*! LOCK_MODE - Domain/Setpoint mode lock */ #define SRC_AUTHEN_USBPHY2_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_MODE_MASK) + #define SRC_AUTHEN_USBPHY2_ASSIGN_LIST_MASK (0xF00U) #define SRC_AUTHEN_USBPHY2_ASSIGN_LIST_SHIFT (8U) #define SRC_AUTHEN_USBPHY2_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_ASSIGN_LIST_MASK) + #define SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_MASK (0x8000U) #define SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_SHIFT (15U) /*! LOCK_ASSIGN - Assign list lock */ #define SRC_AUTHEN_USBPHY2_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_MASK) + #define SRC_AUTHEN_USBPHY2_WHITE_LIST_MASK (0xF0000U) #define SRC_AUTHEN_USBPHY2_WHITE_LIST_SHIFT (16U) /*! WHITE_LIST - Domain ID white list */ #define SRC_AUTHEN_USBPHY2_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_WHITE_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_WHITE_LIST_MASK) + #define SRC_AUTHEN_USBPHY2_LOCK_LIST_MASK (0x800000U) #define SRC_AUTHEN_USBPHY2_LOCK_LIST_SHIFT (23U) /*! LOCK_LIST - White list lock */ #define SRC_AUTHEN_USBPHY2_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_LIST_MASK) + #define SRC_AUTHEN_USBPHY2_USER_MASK (0x1000000U) #define SRC_AUTHEN_USBPHY2_USER_SHIFT (24U) /*! USER - Allow user mode access */ #define SRC_AUTHEN_USBPHY2_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_USER_SHIFT)) & SRC_AUTHEN_USBPHY2_USER_MASK) + #define SRC_AUTHEN_USBPHY2_NONSECURE_MASK (0x2000000U) #define SRC_AUTHEN_USBPHY2_NONSECURE_SHIFT (25U) /*! NONSECURE - Allow non-secure mode access */ #define SRC_AUTHEN_USBPHY2_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_NONSECURE_SHIFT)) & SRC_AUTHEN_USBPHY2_NONSECURE_MASK) + #define SRC_AUTHEN_USBPHY2_LOCK_SETTING_MASK (0x80000000U) #define SRC_AUTHEN_USBPHY2_LOCK_SETTING_SHIFT (31U) /*! LOCK_SETTING - Lock NONSECURE and USER @@ -81310,6 +90732,7 @@ typedef struct { /*! @name CTRL_USBPHY2 - Slice Control Register */ /*! @{ */ + #define SRC_CTRL_USBPHY2_SW_RESET_MASK (0x1U) #define SRC_CTRL_USBPHY2_SW_RESET_SHIFT (0U) /*! SW_RESET @@ -81319,240 +90742,209 @@ typedef struct { #define SRC_CTRL_USBPHY2_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_USBPHY2_SW_RESET_SHIFT)) & SRC_CTRL_USBPHY2_SW_RESET_MASK) /*! @} */ -/*! @name SETPOINT_USBPHY2 - Slice SetPoint Config Register */ +/*! @name SETPOINT_USBPHY2 - Slice Setpoint Config Register */ /*! @{ */ + #define SRC_SETPOINT_USBPHY2_SETPOINT0_MASK (0x1U) #define SRC_SETPOINT_USBPHY2_SETPOINT0_SHIFT (0U) -/*! SETPOINT0 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT0 - SETPOINT0 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY2_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT0_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT0_MASK) + #define SRC_SETPOINT_USBPHY2_SETPOINT1_MASK (0x2U) #define SRC_SETPOINT_USBPHY2_SETPOINT1_SHIFT (1U) -/*! SETPOINT1 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT1 - SETPOINT1 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY2_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT1_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT1_MASK) + #define SRC_SETPOINT_USBPHY2_SETPOINT2_MASK (0x4U) #define SRC_SETPOINT_USBPHY2_SETPOINT2_SHIFT (2U) -/*! SETPOINT2 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT2 - SETPOINT2 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY2_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT2_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT2_MASK) + #define SRC_SETPOINT_USBPHY2_SETPOINT3_MASK (0x8U) #define SRC_SETPOINT_USBPHY2_SETPOINT3_SHIFT (3U) -/*! SETPOINT3 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT3 - SETPOINT3 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY2_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT3_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT3_MASK) + #define SRC_SETPOINT_USBPHY2_SETPOINT4_MASK (0x10U) #define SRC_SETPOINT_USBPHY2_SETPOINT4_SHIFT (4U) -/*! SETPOINT4 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT4 - SETPOINT4 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY2_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT4_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT4_MASK) + #define SRC_SETPOINT_USBPHY2_SETPOINT5_MASK (0x20U) #define SRC_SETPOINT_USBPHY2_SETPOINT5_SHIFT (5U) -/*! SETPOINT5 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT5 - SETPOINT5 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY2_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT5_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT5_MASK) + #define SRC_SETPOINT_USBPHY2_SETPOINT6_MASK (0x40U) #define SRC_SETPOINT_USBPHY2_SETPOINT6_SHIFT (6U) -/*! SETPOINT6 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT6 - SETPOINT6 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY2_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT6_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT6_MASK) + #define SRC_SETPOINT_USBPHY2_SETPOINT7_MASK (0x80U) #define SRC_SETPOINT_USBPHY2_SETPOINT7_SHIFT (7U) -/*! SETPOINT7 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT7 - SETPOINT7 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY2_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT7_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT7_MASK) + #define SRC_SETPOINT_USBPHY2_SETPOINT8_MASK (0x100U) #define SRC_SETPOINT_USBPHY2_SETPOINT8_SHIFT (8U) -/*! SETPOINT8 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT8 - SETPOINT8 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY2_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT8_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT8_MASK) + #define SRC_SETPOINT_USBPHY2_SETPOINT9_MASK (0x200U) #define SRC_SETPOINT_USBPHY2_SETPOINT9_SHIFT (9U) -/*! SETPOINT9 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT9 - SETPOINT9 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY2_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT9_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT9_MASK) + #define SRC_SETPOINT_USBPHY2_SETPOINT10_MASK (0x400U) #define SRC_SETPOINT_USBPHY2_SETPOINT10_SHIFT (10U) -/*! SETPOINT10 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT10 - SETPOINT10 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY2_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT10_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT10_MASK) + #define SRC_SETPOINT_USBPHY2_SETPOINT11_MASK (0x800U) #define SRC_SETPOINT_USBPHY2_SETPOINT11_SHIFT (11U) -/*! SETPOINT11 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT11 - SETPOINT11 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY2_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT11_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT11_MASK) + #define SRC_SETPOINT_USBPHY2_SETPOINT12_MASK (0x1000U) #define SRC_SETPOINT_USBPHY2_SETPOINT12_SHIFT (12U) -/*! SETPOINT12 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT12 - SETPOINT12 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY2_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT12_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT12_MASK) + #define SRC_SETPOINT_USBPHY2_SETPOINT13_MASK (0x2000U) #define SRC_SETPOINT_USBPHY2_SETPOINT13_SHIFT (13U) -/*! SETPOINT13 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT13 - SETPOINT13 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY2_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT13_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT13_MASK) + #define SRC_SETPOINT_USBPHY2_SETPOINT14_MASK (0x4000U) #define SRC_SETPOINT_USBPHY2_SETPOINT14_SHIFT (14U) -/*! SETPOINT14 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT14 - SETPOINT14 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY2_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT14_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT14_MASK) + #define SRC_SETPOINT_USBPHY2_SETPOINT15_MASK (0x8000U) #define SRC_SETPOINT_USBPHY2_SETPOINT15_SHIFT (15U) -/*! SETPOINT15 - * 0b0..slice reset will be de-asserted when system in set point n - * 0b1..slice reset will be asserted when system in set point n +/*! SETPOINT15 - SETPOINT15 + * 0b0..Slice reset will be de-asserted when system in Setpoint n + * 0b1..Slice reset will be asserted when system in Setpoint n */ #define SRC_SETPOINT_USBPHY2_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT15_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT15_MASK) /*! @} */ /*! @name DOMAIN_USBPHY2 - Slice Domain Config Register */ /*! @{ */ + #define SRC_DOMAIN_USBPHY2_CPU0_RUN_MASK (0x1U) #define SRC_DOMAIN_USBPHY2_CPU0_RUN_SHIFT (0U) -/*! CPU0_RUN - * 0b0..slice reset will be de-asserted when cpu0 in run mode - * 0b1..slice reset will be asserted when cpu0 in run mode +/*! CPU0_RUN - CPU mode setting for RUN + * 0b0..Slice reset will be de-asserted when CPU0 in RUN mode + * 0b1..Slice reset will be asserted when CPU0 in RUN mode */ #define SRC_DOMAIN_USBPHY2_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_RUN_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_RUN_MASK) + #define SRC_DOMAIN_USBPHY2_CPU0_WAIT_MASK (0x2U) #define SRC_DOMAIN_USBPHY2_CPU0_WAIT_SHIFT (1U) -/*! CPU0_WAIT - * 0b0..slice reset will be de-asserted when cpu0 in wait mode - * 0b1..slice reset will be asserted when cpu0 in wait mode +/*! CPU0_WAIT - CPU mode setting for WAIT + * 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode + * 0b1..Slice reset will be asserted when CPU0 in WAIT mode */ #define SRC_DOMAIN_USBPHY2_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_WAIT_MASK) + #define SRC_DOMAIN_USBPHY2_CPU0_STOP_MASK (0x4U) #define SRC_DOMAIN_USBPHY2_CPU0_STOP_SHIFT (2U) -/*! CPU0_STOP - * 0b0..slice reset will be de-asserted when cpu0 in stop mode - * 0b1..slice reset will be asserted when cpu0 in stop mode +/*! CPU0_STOP - CPU mode setting for STOP + * 0b0..Slice reset will be de-asserted when CPU0 in STOP mode + * 0b1..Slice reset will be asserted when CPU0 in STOP mode */ #define SRC_DOMAIN_USBPHY2_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_STOP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_STOP_MASK) + #define SRC_DOMAIN_USBPHY2_CPU0_SUSP_MASK (0x8U) #define SRC_DOMAIN_USBPHY2_CPU0_SUSP_SHIFT (3U) -/*! CPU0_SUSP - * 0b0..slice reset will be de-asserted when cpu0 in suspend mode - * 0b1..slice reset will be asserted when cpu0 in suspend mode +/*! CPU0_SUSP - CPU mode setting for SUSPEND + * 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode + * 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode */ #define SRC_DOMAIN_USBPHY2_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_SUSP_MASK) + #define SRC_DOMAIN_USBPHY2_CPU1_RUN_MASK (0x10U) #define SRC_DOMAIN_USBPHY2_CPU1_RUN_SHIFT (4U) -/*! CPU1_RUN - * 0b0..slice reset will be de-asserted when cpu1 in run mode - * 0b1..slice reset will be asserted when cpu1 in run mode +/*! CPU1_RUN - CPU mode setting for RUN + * 0b0..Slice reset will be de-asserted when CPU1 in RUN mode + * 0b1..Slice reset will be asserted when CPU1 in RUN mode */ #define SRC_DOMAIN_USBPHY2_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_RUN_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_RUN_MASK) + #define SRC_DOMAIN_USBPHY2_CPU1_WAIT_MASK (0x20U) #define SRC_DOMAIN_USBPHY2_CPU1_WAIT_SHIFT (5U) -/*! CPU1_WAIT - * 0b0..slice reset will be de-asserted when cpu1 in wait mode - * 0b1..slice reset will be asserted when cpu1 in wait mode +/*! CPU1_WAIT - CPU mode setting for WAIT + * 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode + * 0b1..Slice reset will be asserted when CPU1 in WAIT mode */ #define SRC_DOMAIN_USBPHY2_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_WAIT_MASK) + #define SRC_DOMAIN_USBPHY2_CPU1_STOP_MASK (0x40U) #define SRC_DOMAIN_USBPHY2_CPU1_STOP_SHIFT (6U) -/*! CPU1_STOP - * 0b0..slice reset will be de-asserted when cpu1 in stop mode - * 0b1..slice reset will be asserted when cpu1 in stop mode +/*! CPU1_STOP - CPU mode setting for STOP + * 0b0..Slice reset will be de-asserted when CPU1 in STOP mode + * 0b1..Slice reset will be asserted when CPU1 in STOP mode */ #define SRC_DOMAIN_USBPHY2_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_STOP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_STOP_MASK) + #define SRC_DOMAIN_USBPHY2_CPU1_SUSP_MASK (0x80U) #define SRC_DOMAIN_USBPHY2_CPU1_SUSP_SHIFT (7U) -/*! CPU1_SUSP - * 0b0..slice reset will be de-asserted when cpu1 in suspend mode - * 0b1..slice reset will be asserted when cpu1 in suspend mode +/*! CPU1_SUSP - CPU mode setting for SUSPEND + * 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode + * 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode */ #define SRC_DOMAIN_USBPHY2_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_SUSP_MASK) -#define SRC_DOMAIN_USBPHY2_CPU2_RUN_MASK (0x100U) -#define SRC_DOMAIN_USBPHY2_CPU2_RUN_SHIFT (8U) -/*! CPU2_RUN - * 0b0..slice reset will be de-asserted when cpu2 in run mode - * 0b1..slice reset will be asserted when cpu2 in run mode - */ -#define SRC_DOMAIN_USBPHY2_CPU2_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU2_RUN_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU2_RUN_MASK) -#define SRC_DOMAIN_USBPHY2_CPU2_WAIT_MASK (0x200U) -#define SRC_DOMAIN_USBPHY2_CPU2_WAIT_SHIFT (9U) -/*! CPU2_WAIT - * 0b0..slice reset will be de-asserted when cpu2 in wait mode - * 0b1..slice reset will be asserted when cpu2 in wait mode - */ -#define SRC_DOMAIN_USBPHY2_CPU2_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU2_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU2_WAIT_MASK) -#define SRC_DOMAIN_USBPHY2_CPU2_STOP_MASK (0x400U) -#define SRC_DOMAIN_USBPHY2_CPU2_STOP_SHIFT (10U) -/*! CPU2_STOP - * 0b0..slice reset will be de-asserted when cpu2 in stop mode - * 0b1..slice reset will be asserted when cpu2 in stop mode - */ -#define SRC_DOMAIN_USBPHY2_CPU2_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU2_STOP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU2_STOP_MASK) -#define SRC_DOMAIN_USBPHY2_CPU2_SUSP_MASK (0x800U) -#define SRC_DOMAIN_USBPHY2_CPU2_SUSP_SHIFT (11U) -/*! CPU2_SUSP - * 0b0..slice reset will be de-asserted when cpu2 in suspend mode - * 0b1..slice reset will be asserted when cpu2 in suspend mode - */ -#define SRC_DOMAIN_USBPHY2_CPU2_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU2_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU2_SUSP_MASK) -#define SRC_DOMAIN_USBPHY2_CPU3_RUN_MASK (0x1000U) -#define SRC_DOMAIN_USBPHY2_CPU3_RUN_SHIFT (12U) -/*! CPU3_RUN - * 0b0..slice reset will be de-asserted when cpu3 in run mode - * 0b1..slice reset will be asserted when cpu3 in run mode - */ -#define SRC_DOMAIN_USBPHY2_CPU3_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU3_RUN_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU3_RUN_MASK) -#define SRC_DOMAIN_USBPHY2_CPU3_WAIT_MASK (0x2000U) -#define SRC_DOMAIN_USBPHY2_CPU3_WAIT_SHIFT (13U) -/*! CPU3_WAIT - * 0b0..slice reset will be de-asserted when cpu3 in wait mode - * 0b1..slice reset will be asserted when cpu3 in wait mode - */ -#define SRC_DOMAIN_USBPHY2_CPU3_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU3_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU3_WAIT_MASK) -#define SRC_DOMAIN_USBPHY2_CPU3_STOP_MASK (0x4000U) -#define SRC_DOMAIN_USBPHY2_CPU3_STOP_SHIFT (14U) -/*! CPU3_STOP - * 0b0..slice reset will be de-asserted when cpu3 in stop mode - * 0b1..slice reset will be asserted when cpu3 in stop mode - */ -#define SRC_DOMAIN_USBPHY2_CPU3_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU3_STOP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU3_STOP_MASK) -#define SRC_DOMAIN_USBPHY2_CPU3_SUSP_MASK (0x8000U) -#define SRC_DOMAIN_USBPHY2_CPU3_SUSP_SHIFT (15U) -/*! CPU3_SUSP - * 0b0..slice reset will be de-asserted when cpu3 in suspend mode - * 0b1..slice reset will be asserted when cpu3 in suspend mode - */ -#define SRC_DOMAIN_USBPHY2_CPU3_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU3_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU3_SUSP_MASK) /*! @} */ /*! @name STAT_USBPHY2 - Slice Status Register */ /*! @{ */ + #define SRC_STAT_USBPHY2_UNDER_RST_MASK (0x1U) #define SRC_STAT_USBPHY2_UNDER_RST_SHIFT (0U) /*! UNDER_RST @@ -81560,6 +90952,7 @@ typedef struct { * 0b1..the reset is in process */ #define SRC_STAT_USBPHY2_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_UNDER_RST_SHIFT)) & SRC_STAT_USBPHY2_UNDER_RST_MASK) + #define SRC_STAT_USBPHY2_RST_BY_HW_MASK (0x4U) #define SRC_STAT_USBPHY2_RST_BY_HW_SHIFT (2U) /*! RST_BY_HW @@ -81567,6 +90960,7 @@ typedef struct { * 0b1..the reset is caused by the power mode transfer */ #define SRC_STAT_USBPHY2_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_RST_BY_HW_SHIFT)) & SRC_STAT_USBPHY2_RST_BY_HW_MASK) + #define SRC_STAT_USBPHY2_RST_BY_SW_MASK (0x8U) #define SRC_STAT_USBPHY2_RST_BY_SW_SHIFT (3U) /*! RST_BY_SW @@ -81608,11 +91002,11 @@ typedef struct { /** SSARC_HP - Register Layout Typedef */ typedef struct { - struct { /* offset: 0x0, array step: 0x20 */ - __IO uint32_t SRAM0; /**< Description Address 0 Register..Description Address 1023 Register, array offset: 0x0, array step: 0x20 */ - __IO uint32_t SRAM1; /**< Description Data 0 Register..Description Data 1023 Register, array offset: 0x4, array step: 0x20 */ - __IO uint32_t SRAM2; /**< Description 0 Register..Description 1023 Register, array offset: 0x8, array step: 0x20 */ - uint8_t RESERVED_0[20]; + struct { /* offset: 0x0, array step: 0x10 */ + __IO uint32_t SRAM0; /**< Description Address Register, array offset: 0x0, array step: 0x10 */ + __IO uint32_t SRAM1; /**< Description Data Register, array offset: 0x4, array step: 0x10 */ + __IO uint32_t SRAM2; /**< Description Control Register, array offset: 0x8, array step: 0x10 */ + uint8_t RESERVED_0[4]; } DESC[1024]; } SSARC_HP_Type; @@ -81625,8 +91019,9 @@ typedef struct { * @{ */ -/*! @name SRAM0 - Description Address 0 Register..Description Address 1023 Register */ +/*! @name SRAM0 - Description Address Register */ /*! @{ */ + #define SSARC_HP_SRAM0_ADDR_MASK (0xFFFFFFFFU) #define SSARC_HP_SRAM0_ADDR_SHIFT (0U) /*! ADDR - Address field @@ -81637,8 +91032,9 @@ typedef struct { /* The count of SSARC_HP_SRAM0 */ #define SSARC_HP_SRAM0_COUNT (1024U) -/*! @name SRAM1 - Description Data 0 Register..Description Data 1023 Register */ +/*! @name SRAM1 - Description Data Register */ /*! @{ */ + #define SSARC_HP_SRAM1_DATA_MASK (0xFFFFFFFFU) #define SSARC_HP_SRAM1_DATA_SHIFT (0U) /*! DATA - Data field @@ -81649,34 +91045,46 @@ typedef struct { /* The count of SSARC_HP_SRAM1 */ #define SSARC_HP_SRAM1_COUNT (1024U) -/*! @name SRAM2 - Description 0 Register..Description 1023 Register */ +/*! @name SRAM2 - Description Control Register */ /*! @{ */ + #define SSARC_HP_SRAM2_TYPE_MASK (0x7U) #define SSARC_HP_SRAM2_TYPE_SHIFT (0U) /*! TYPE - Type field - * 0b000..read the register value on save operation and write it back on restore operation - * 0b001..always write a fixed value from DATA[31:0] - * 0b010..read register, OR with the DATA[31:0], and write it back - * 0b011..read register, AND with the DATA[31:0], and write it back - * 0b100..delay for number of cycles based on the DATA[31:0] - * 0b101..read the register until read_data[31:0] & DATA[31:0] == 0 - * 0b110..read the register until read_data[31:0] & DATA[31:0] != 0 + * 0b000..SR + * 0b001..WO + * 0b010..RMW_OR + * 0b011..RMW_AND + * 0b100..DELAY + * 0b101..POLLING_0 + * 0b110..POLLING_1 * 0b111..Reserved */ #define SSARC_HP_SRAM2_TYPE(x) (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM2_TYPE_SHIFT)) & SSARC_HP_SRAM2_TYPE_MASK) + #define SSARC_HP_SRAM2_SV_EN_MASK (0x10U) #define SSARC_HP_SRAM2_SV_EN_SHIFT (4U) -/*! SV_EN - SV Enable +/*! SV_EN - Save Enable + * 0b0..Do not use this descriptor in the save operation + * 0b1..Use this descriptor in the save operation */ #define SSARC_HP_SRAM2_SV_EN(x) (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM2_SV_EN_SHIFT)) & SSARC_HP_SRAM2_SV_EN_MASK) + #define SSARC_HP_SRAM2_RT_EN_MASK (0x20U) #define SSARC_HP_SRAM2_RT_EN_SHIFT (5U) -/*! RT_EN - RT Enable +/*! RT_EN - Restore Enable + * 0b0..Do not use this descriptor for the restore operation + * 0b1..Use this descriptor for the restore operation */ #define SSARC_HP_SRAM2_RT_EN(x) (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM2_RT_EN_SHIFT)) & SSARC_HP_SRAM2_RT_EN_MASK) + #define SSARC_HP_SRAM2_SIZE_MASK (0xC0U) #define SSARC_HP_SRAM2_SIZE_SHIFT (6U) /*! SIZE - Size field + * 0b00..8-bit + * 0b01..16-bit + * 0b10..32-bit + * 0b11..Reserved */ #define SSARC_HP_SRAM2_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM2_SIZE_SHIFT)) & SSARC_HP_SRAM2_SIZE_MASK) /*! @} */ @@ -81743,16 +91151,19 @@ typedef struct { /*! @name DESC_CTRL0 - Descriptor Control0 0 Register..Descriptor Control0 15 Register */ /*! @{ */ + #define SSARC_LP_DESC_CTRL0_START_MASK (0x3FFU) #define SSARC_LP_DESC_CTRL0_START_SHIFT (0U) /*! START - Start index */ #define SSARC_LP_DESC_CTRL0_START(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_START_SHIFT)) & SSARC_LP_DESC_CTRL0_START_MASK) + #define SSARC_LP_DESC_CTRL0_END_MASK (0xFFC00U) #define SSARC_LP_DESC_CTRL0_END_SHIFT (10U) /*! END - End index */ #define SSARC_LP_DESC_CTRL0_END(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_END_SHIFT)) & SSARC_LP_DESC_CTRL0_END_MASK) + #define SSARC_LP_DESC_CTRL0_SV_ORDER_MASK (0x100000U) #define SSARC_LP_DESC_CTRL0_SV_ORDER_SHIFT (20U) /*! SV_ORDER - Save Order @@ -81760,6 +91171,7 @@ typedef struct { * 0b1..Descriptors within the group are processed from end to start */ #define SSARC_LP_DESC_CTRL0_SV_ORDER(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_SV_ORDER_SHIFT)) & SSARC_LP_DESC_CTRL0_SV_ORDER_MASK) + #define SSARC_LP_DESC_CTRL0_RT_ORDER_MASK (0x200000U) #define SSARC_LP_DESC_CTRL0_RT_ORDER_SHIFT (21U) /*! RT_ORDER - Restore order @@ -81774,6 +91186,7 @@ typedef struct { /*! @name DESC_CTRL1 - Descriptor Control1 0 Register..Descriptor Control1 15 Register */ /*! @{ */ + #define SSARC_LP_DESC_CTRL1_SW_TRIG_SV_MASK (0x1U) #define SSARC_LP_DESC_CTRL1_SW_TRIG_SV_SHIFT (0U) /*! SW_TRIG_SV - Software trigger save @@ -81781,6 +91194,7 @@ typedef struct { * 0b0..No software save request/software restore request complete */ #define SSARC_LP_DESC_CTRL1_SW_TRIG_SV(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SW_TRIG_SV_SHIFT)) & SSARC_LP_DESC_CTRL1_SW_TRIG_SV_MASK) + #define SSARC_LP_DESC_CTRL1_SW_TRIG_RT_MASK (0x2U) #define SSARC_LP_DESC_CTRL1_SW_TRIG_RT_SHIFT (1U) /*! SW_TRIG_RT - Software trigger restore @@ -81788,9 +91202,21 @@ typedef struct { * 0b0..No software restore request/software restore request complete */ #define SSARC_LP_DESC_CTRL1_SW_TRIG_RT(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SW_TRIG_RT_SHIFT)) & SSARC_LP_DESC_CTRL1_SW_TRIG_RT_MASK) + #define SSARC_LP_DESC_CTRL1_POWER_DOMAIN_MASK (0x70U) #define SSARC_LP_DESC_CTRL1_POWER_DOMAIN_SHIFT (4U) +/*! POWER_DOMAIN + * 0b000..PGMC_BPC0 + * 0b001..PGMC_BPC1 + * 0b010..PGMC_BPC2 + * 0b011..PGMC_BPC3 + * 0b100..PGMC_BPC4 + * 0b101..PGMC_BPC5 + * 0b110..PGMC_BPC6 + * 0b111..PGMC_BPC7 + */ #define SSARC_LP_DESC_CTRL1_POWER_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_POWER_DOMAIN_SHIFT)) & SSARC_LP_DESC_CTRL1_POWER_DOMAIN_MASK) + #define SSARC_LP_DESC_CTRL1_GP_EN_MASK (0x80U) #define SSARC_LP_DESC_CTRL1_GP_EN_SHIFT (7U) /*! GP_EN - Group Enable @@ -81798,28 +91224,33 @@ typedef struct { * 0b1..Group enabled */ #define SSARC_LP_DESC_CTRL1_GP_EN(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_GP_EN_SHIFT)) & SSARC_LP_DESC_CTRL1_GP_EN_MASK) + #define SSARC_LP_DESC_CTRL1_SV_PRIORITY_MASK (0xF00U) #define SSARC_LP_DESC_CTRL1_SV_PRIORITY_SHIFT (8U) /*! SV_PRIORITY - Save Priority */ #define SSARC_LP_DESC_CTRL1_SV_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SV_PRIORITY_SHIFT)) & SSARC_LP_DESC_CTRL1_SV_PRIORITY_MASK) + #define SSARC_LP_DESC_CTRL1_RT_PRIORITY_MASK (0xF000U) #define SSARC_LP_DESC_CTRL1_RT_PRIORITY_SHIFT (12U) /*! RT_PRIORITY - Restore Priority */ #define SSARC_LP_DESC_CTRL1_RT_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_RT_PRIORITY_SHIFT)) & SSARC_LP_DESC_CTRL1_RT_PRIORITY_MASK) -#define SSARC_LP_DESC_CTRL1_RESD_MASK (0x30000U) -#define SSARC_LP_DESC_CTRL1_RESD_SHIFT (16U) -/*! RESD - Restore Domain + +#define SSARC_LP_DESC_CTRL1_CPUD_MASK (0x30000U) +#define SSARC_LP_DESC_CTRL1_CPUD_SHIFT (16U) +/*! CPUD - CPU Domain */ -#define SSARC_LP_DESC_CTRL1_RESD(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_RESD_SHIFT)) & SSARC_LP_DESC_CTRL1_RESD_MASK) +#define SSARC_LP_DESC_CTRL1_CPUD(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_CPUD_SHIFT)) & SSARC_LP_DESC_CTRL1_CPUD_MASK) + #define SSARC_LP_DESC_CTRL1_RL_MASK (0x40000U) #define SSARC_LP_DESC_CTRL1_RL_SHIFT (18U) /*! RL - Read Lock - * 0b1..Group is locked (write access not allowed) - * 0b0..Group is unlocked (write access allowed) + * 0b1..Group is locked (read access not allowed) + * 0b0..Group is unlocked (read access allowed) */ #define SSARC_LP_DESC_CTRL1_RL(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_RL_SHIFT)) & SSARC_LP_DESC_CTRL1_RL_MASK) + #define SSARC_LP_DESC_CTRL1_WL_MASK (0x80000U) #define SSARC_LP_DESC_CTRL1_WL_SHIFT (19U) /*! WL - Write Lock @@ -81827,6 +91258,7 @@ typedef struct { * 0b0..Group is unlocked (write access allowed) */ #define SSARC_LP_DESC_CTRL1_WL(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_WL_SHIFT)) & SSARC_LP_DESC_CTRL1_WL_MASK) + #define SSARC_LP_DESC_CTRL1_DL_MASK (0x100000U) #define SSARC_LP_DESC_CTRL1_DL_SHIFT (20U) /*! DL - Domain lock @@ -81841,6 +91273,7 @@ typedef struct { /*! @name DESC_ADDR_UP - Descriptor Address Up 0 Register..Descriptor Address Up 15 Register */ /*! @{ */ + #define SSARC_LP_DESC_ADDR_UP_ADDR_UP_MASK (0xFFFFFFFFU) #define SSARC_LP_DESC_ADDR_UP_ADDR_UP_SHIFT (0U) /*! ADDR_UP - Address field (High) @@ -81853,6 +91286,7 @@ typedef struct { /*! @name DESC_ADDR_DOWN - Descriptor Address Down 0 Register..Descriptor Address Down 15 Register */ /*! @{ */ + #define SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_MASK (0xFFFFFFFFU) #define SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_SHIFT (0U) /*! ADDR_DOWN - Address field (Low) @@ -81865,13 +91299,15 @@ typedef struct { /*! @name CTRL - Control Register */ /*! @{ */ + #define SSARC_LP_CTRL_DIS_HW_REQ_MASK (0x8000000U) #define SSARC_LP_CTRL_DIS_HW_REQ_SHIFT (27U) /*! DIS_HW_REQ - Save/Restore request disable - * 0b0..GPC save/restore requests enabled - * 0b0..GPC save/restore + * 0b0..PGMC save/restore requests enabled + * 0b1..PGMC save/restore requests disabled */ #define SSARC_LP_CTRL_DIS_HW_REQ(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_CTRL_DIS_HW_REQ_SHIFT)) & SSARC_LP_CTRL_DIS_HW_REQ_MASK) + #define SSARC_LP_CTRL_SW_RESET_MASK (0x80000000U) #define SSARC_LP_CTRL_SW_RESET_SHIFT (31U) /*! SW_RESET - Software reset @@ -81881,30 +91317,35 @@ typedef struct { /*! @name INT_STATUS - Interrupt Status Register */ /*! @{ */ + #define SSARC_LP_INT_STATUS_ERR_INDEX_MASK (0x3FFU) #define SSARC_LP_INT_STATUS_ERR_INDEX_SHIFT (0U) /*! ERR_INDEX - Error Index */ #define SSARC_LP_INT_STATUS_ERR_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_ERR_INDEX_SHIFT)) & SSARC_LP_INT_STATUS_ERR_INDEX_MASK) + #define SSARC_LP_INT_STATUS_AHB_RESP_MASK (0xC00U) #define SSARC_LP_INT_STATUS_AHB_RESP_SHIFT (10U) /*! AHB_RESP - AHB Bus response field */ #define SSARC_LP_INT_STATUS_AHB_RESP(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_AHB_RESP_SHIFT)) & SSARC_LP_INT_STATUS_AHB_RESP_MASK) + #define SSARC_LP_INT_STATUS_GROUP_CONFLICT_MASK (0x8000000U) #define SSARC_LP_INT_STATUS_GROUP_CONFLICT_SHIFT (27U) /*! GROUP_CONFLICT - Group Conflict field * 0b1..A group conflict error has occurred - * 0b1..No group conflict error + * 0b0..No group conflict error */ #define SSARC_LP_INT_STATUS_GROUP_CONFLICT(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_GROUP_CONFLICT_SHIFT)) & SSARC_LP_INT_STATUS_GROUP_CONFLICT_MASK) + #define SSARC_LP_INT_STATUS_TIMEOUT_MASK (0x10000000U) #define SSARC_LP_INT_STATUS_TIMEOUT_SHIFT (28U) /*! TIMEOUT - Timeout field * 0b1..A timeout event has occurred - * 0b1..No timeout event + * 0b0..No timeout event */ #define SSARC_LP_INT_STATUS_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_TIMEOUT_SHIFT)) & SSARC_LP_INT_STATUS_TIMEOUT_MASK) + #define SSARC_LP_INT_STATUS_SW_REQ_DONE_MASK (0x20000000U) #define SSARC_LP_INT_STATUS_SW_REQ_DONE_SHIFT (29U) /*! SW_REQ_DONE - Software Request Done @@ -81912,6 +91353,7 @@ typedef struct { * 0b0..No software triggered requests or software triggered request still in progress */ #define SSARC_LP_INT_STATUS_SW_REQ_DONE(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_SW_REQ_DONE_SHIFT)) & SSARC_LP_INT_STATUS_SW_REQ_DONE_MASK) + #define SSARC_LP_INT_STATUS_AHB_ERR_MASK (0x40000000U) #define SSARC_LP_INT_STATUS_AHB_ERR_SHIFT (30U) /*! AHB_ERR - AHB Error field @@ -81919,6 +91361,7 @@ typedef struct { * 0b0..No AHB error */ #define SSARC_LP_INT_STATUS_AHB_ERR(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_AHB_ERR_SHIFT)) & SSARC_LP_INT_STATUS_AHB_ERR_MASK) + #define SSARC_LP_INT_STATUS_ADDR_ERR_MASK (0x80000000U) #define SSARC_LP_INT_STATUS_ADDR_ERR_SHIFT (31U) /*! ADDR_ERR - Address Error field @@ -81930,6 +91373,7 @@ typedef struct { /*! @name HP_TIMEOUT - HP Timeout Register */ /*! @{ */ + #define SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_MASK (0xFFFFFFFFU) #define SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_SHIFT (0U) /*! TIMEOUT_VALUE - Time out value @@ -81939,11 +91383,13 @@ typedef struct { /*! @name HW_GROUP_PENDING - Hardware Request Pending Register */ /*! @{ */ + #define SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_MASK (0xFFFFU) #define SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_SHIFT (0U) /*! HW_SAVE_PENDING - This field indicates which groups are pending for save from hardware request */ #define SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_SHIFT)) & SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_MASK) + #define SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_MASK (0xFFFF0000U) #define SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_SHIFT (16U) /*! HW_RESTORE_PENDING - This field indicates which groups are pending for restore from hardware request @@ -81953,11 +91399,13 @@ typedef struct { /*! @name SW_GROUP_PENDING - Software Request Pending Register */ /*! @{ */ + #define SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_MASK (0xFFFFU) #define SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_SHIFT (0U) /*! SW_SAVE_PENDING - This field indicates which groups are pending for save from software request */ #define SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_SHIFT)) & SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_MASK) + #define SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_MASK (0xFFFF0000U) #define SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_SHIFT (16U) /*! SW_RESTORE_PENDING - This field indicates which groups are pending for restore from software request @@ -82013,10 +91461,7 @@ typedef struct { __IO uint32_t RANGE1_SET; /**< Temperature Sensor Range Register 1, offset: 0x34 */ __IO uint32_t RANGE1_CLR; /**< Temperature Sensor Range Register 1, offset: 0x38 */ __IO uint32_t RANGE1_TOG; /**< Temperature Sensor Range Register 1, offset: 0x3C */ - __IO uint32_t OFFSET_COMP; /**< Temperature Sensor Offset Compensation Register, offset: 0x40 */ - __IO uint32_t OFFSET_COMP_SET; /**< Temperature Sensor Offset Compensation Register, offset: 0x44 */ - __IO uint32_t OFFSET_COMP_CLR; /**< Temperature Sensor Offset Compensation Register, offset: 0x48 */ - __IO uint32_t OFFSET_COMP_TOG; /**< Temperature Sensor Offset Compensation Register, offset: 0x4C */ + uint8_t RESERVED_0[16]; __IO uint32_t STATUS0; /**< Temperature Sensor Status Register 0, offset: 0x50 */ } TMPSNS_Type; @@ -82031,16 +91476,21 @@ typedef struct { /*! @name CTRL0 - Temperature Sensor Control Register 0 */ /*! @{ */ + #define TMPSNS_CTRL0_SLOPE_CAL_MASK (0x3FU) #define TMPSNS_CTRL0_SLOPE_CAL_SHIFT (0U) /*! SLOPE_CAL - Ramp slope calibration control */ #define TMPSNS_CTRL0_SLOPE_CAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_SLOPE_CAL_MASK) + #define TMPSNS_CTRL0_V_SEL_MASK (0x300U) #define TMPSNS_CTRL0_V_SEL_SHIFT (8U) -/*! V_SEL - Votlage select +/*! V_SEL - Voltage Select + * 0b00..Normal temperature measuring mode + * 0b01-0b10..Reserved */ #define TMPSNS_CTRL0_V_SEL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_V_SEL_SHIFT)) & TMPSNS_CTRL0_V_SEL_MASK) + #define TMPSNS_CTRL0_IBIAS_TRIM_MASK (0xF000U) #define TMPSNS_CTRL0_IBIAS_TRIM_SHIFT (12U) /*! IBIAS_TRIM - Current bias trim value @@ -82050,16 +91500,19 @@ typedef struct { /*! @name CTRL0_SET - Temperature Sensor Control Register 0 */ /*! @{ */ + #define TMPSNS_CTRL0_SET_SLOPE_CAL_MASK (0x3FU) #define TMPSNS_CTRL0_SET_SLOPE_CAL_SHIFT (0U) /*! SLOPE_CAL - Ramp slope calibration control */ #define TMPSNS_CTRL0_SET_SLOPE_CAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_SET_SLOPE_CAL_MASK) + #define TMPSNS_CTRL0_SET_V_SEL_MASK (0x300U) #define TMPSNS_CTRL0_SET_V_SEL_SHIFT (8U) -/*! V_SEL - Votlage select +/*! V_SEL - Voltage Select */ #define TMPSNS_CTRL0_SET_V_SEL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_V_SEL_SHIFT)) & TMPSNS_CTRL0_SET_V_SEL_MASK) + #define TMPSNS_CTRL0_SET_IBIAS_TRIM_MASK (0xF000U) #define TMPSNS_CTRL0_SET_IBIAS_TRIM_SHIFT (12U) /*! IBIAS_TRIM - Current bias trim value @@ -82069,16 +91522,19 @@ typedef struct { /*! @name CTRL0_CLR - Temperature Sensor Control Register 0 */ /*! @{ */ + #define TMPSNS_CTRL0_CLR_SLOPE_CAL_MASK (0x3FU) #define TMPSNS_CTRL0_CLR_SLOPE_CAL_SHIFT (0U) /*! SLOPE_CAL - Ramp slope calibration control */ #define TMPSNS_CTRL0_CLR_SLOPE_CAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_CLR_SLOPE_CAL_MASK) + #define TMPSNS_CTRL0_CLR_V_SEL_MASK (0x300U) #define TMPSNS_CTRL0_CLR_V_SEL_SHIFT (8U) -/*! V_SEL - Votlage select +/*! V_SEL - Voltage Select */ #define TMPSNS_CTRL0_CLR_V_SEL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_V_SEL_SHIFT)) & TMPSNS_CTRL0_CLR_V_SEL_MASK) + #define TMPSNS_CTRL0_CLR_IBIAS_TRIM_MASK (0xF000U) #define TMPSNS_CTRL0_CLR_IBIAS_TRIM_SHIFT (12U) /*! IBIAS_TRIM - Current bias trim value @@ -82088,16 +91544,19 @@ typedef struct { /*! @name CTRL0_TOG - Temperature Sensor Control Register 0 */ /*! @{ */ + #define TMPSNS_CTRL0_TOG_SLOPE_CAL_MASK (0x3FU) #define TMPSNS_CTRL0_TOG_SLOPE_CAL_SHIFT (0U) /*! SLOPE_CAL - Ramp slope calibration control */ #define TMPSNS_CTRL0_TOG_SLOPE_CAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_TOG_SLOPE_CAL_MASK) + #define TMPSNS_CTRL0_TOG_V_SEL_MASK (0x300U) #define TMPSNS_CTRL0_TOG_V_SEL_SHIFT (8U) -/*! V_SEL - Votlage select +/*! V_SEL - Voltage Select */ #define TMPSNS_CTRL0_TOG_V_SEL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_V_SEL_SHIFT)) & TMPSNS_CTRL0_TOG_V_SEL_MASK) + #define TMPSNS_CTRL0_TOG_IBIAS_TRIM_MASK (0xF000U) #define TMPSNS_CTRL0_TOG_IBIAS_TRIM_SHIFT (12U) /*! IBIAS_TRIM - Current bias trim value @@ -82107,20 +91566,23 @@ typedef struct { /*! @name CTRL1 - Temperature Sensor Control Register 1 */ /*! @{ */ + #define TMPSNS_CTRL1_FREQ_MASK (0xFFFFU) #define TMPSNS_CTRL1_FREQ_SHIFT (0U) /*! FREQ - Temperature Measurement Frequency - * 0b0000000000000000..Single Reading Mode. New reading available everytime START bit is set to 1 from 0. + * 0b0000000000000000..Single Reading Mode. New reading available every time CTRL1[START] bit is set to 1 from 0. * 0b0000000000000001-0b1111111111111111..Continuous Reading Mode. Next temperature reading taken after programmed number of cycles after current reading is complete. */ #define TMPSNS_CTRL1_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_FREQ_SHIFT)) & TMPSNS_CTRL1_FREQ_MASK) + #define TMPSNS_CTRL1_FINISH_IE_MASK (0x10000U) #define TMPSNS_CTRL1_FINISH_IE_SHIFT (16U) -/*! FINISH_IE - Measurment finished interrupt enable +/*! FINISH_IE - Measurement finished interrupt enable * 0b0..Interrupt is disabled * 0b1..Interrupt is enabled */ #define TMPSNS_CTRL1_FINISH_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_FINISH_IE_MASK) + #define TMPSNS_CTRL1_LOW_TEMP_IE_MASK (0x20000U) #define TMPSNS_CTRL1_LOW_TEMP_IE_SHIFT (17U) /*! LOW_TEMP_IE - Low temperature interrupt enable @@ -82128,6 +91590,7 @@ typedef struct { * 0b1..Interrupt is enabled */ #define TMPSNS_CTRL1_LOW_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_LOW_TEMP_IE_MASK) + #define TMPSNS_CTRL1_HIGH_TEMP_IE_MASK (0x40000U) #define TMPSNS_CTRL1_HIGH_TEMP_IE_SHIFT (18U) /*! HIGH_TEMP_IE - High temperature interrupt enable @@ -82135,6 +91598,7 @@ typedef struct { * 0b1..Interrupt is enabled */ #define TMPSNS_CTRL1_HIGH_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_HIGH_TEMP_IE_MASK) + #define TMPSNS_CTRL1_PANIC_TEMP_IE_MASK (0x80000U) #define TMPSNS_CTRL1_PANIC_TEMP_IE_SHIFT (19U) /*! PANIC_TEMP_IE - Panic temperature interrupt enable @@ -82142,6 +91606,7 @@ typedef struct { * 0b1..Interrupt is enabled */ #define TMPSNS_CTRL1_PANIC_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_PANIC_TEMP_IE_MASK) + #define TMPSNS_CTRL1_START_MASK (0x400000U) #define TMPSNS_CTRL1_START_SHIFT (22U) /*! START - Start Temperature Measurement @@ -82149,6 +91614,7 @@ typedef struct { * 0b1..Initiate a new temperature reading */ #define TMPSNS_CTRL1_START(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_START_SHIFT)) & TMPSNS_CTRL1_START_MASK) + #define TMPSNS_CTRL1_PWD_MASK (0x800000U) #define TMPSNS_CTRL1_PWD_SHIFT (23U) /*! PWD - Temperature Sensor Power Down @@ -82156,11 +91622,13 @@ typedef struct { * 0b1..Sensor is powered down */ #define TMPSNS_CTRL1_PWD(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PWD_SHIFT)) & TMPSNS_CTRL1_PWD_MASK) + #define TMPSNS_CTRL1_RFU_MASK (0x7F000000U) #define TMPSNS_CTRL1_RFU_SHIFT (24U) /*! RFU - Read/Writeable field. Reserved for future use */ #define TMPSNS_CTRL1_RFU(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_RFU_SHIFT)) & TMPSNS_CTRL1_RFU_MASK) + #define TMPSNS_CTRL1_PWD_FULL_MASK (0x80000000U) #define TMPSNS_CTRL1_PWD_FULL_SHIFT (31U) /*! PWD_FULL - Temperature Sensor Full Power Down @@ -82172,46 +91640,55 @@ typedef struct { /*! @name CTRL1_SET - Temperature Sensor Control Register 1 */ /*! @{ */ + #define TMPSNS_CTRL1_SET_FREQ_MASK (0xFFFFU) #define TMPSNS_CTRL1_SET_FREQ_SHIFT (0U) /*! FREQ - Temperature Measurement Frequency */ #define TMPSNS_CTRL1_SET_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_FREQ_SHIFT)) & TMPSNS_CTRL1_SET_FREQ_MASK) + #define TMPSNS_CTRL1_SET_FINISH_IE_MASK (0x10000U) #define TMPSNS_CTRL1_SET_FINISH_IE_SHIFT (16U) -/*! FINISH_IE - Measurment finished interrupt enable +/*! FINISH_IE - Measurement finished interrupt enable */ #define TMPSNS_CTRL1_SET_FINISH_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_SET_FINISH_IE_MASK) + #define TMPSNS_CTRL1_SET_LOW_TEMP_IE_MASK (0x20000U) #define TMPSNS_CTRL1_SET_LOW_TEMP_IE_SHIFT (17U) /*! LOW_TEMP_IE - Low temperature interrupt enable */ #define TMPSNS_CTRL1_SET_LOW_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_LOW_TEMP_IE_MASK) + #define TMPSNS_CTRL1_SET_HIGH_TEMP_IE_MASK (0x40000U) #define TMPSNS_CTRL1_SET_HIGH_TEMP_IE_SHIFT (18U) /*! HIGH_TEMP_IE - High temperature interrupt enable */ #define TMPSNS_CTRL1_SET_HIGH_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_HIGH_TEMP_IE_MASK) + #define TMPSNS_CTRL1_SET_PANIC_TEMP_IE_MASK (0x80000U) #define TMPSNS_CTRL1_SET_PANIC_TEMP_IE_SHIFT (19U) /*! PANIC_TEMP_IE - Panic temperature interrupt enable */ #define TMPSNS_CTRL1_SET_PANIC_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_PANIC_TEMP_IE_MASK) + #define TMPSNS_CTRL1_SET_START_MASK (0x400000U) #define TMPSNS_CTRL1_SET_START_SHIFT (22U) /*! START - Start Temperature Measurement */ #define TMPSNS_CTRL1_SET_START(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_START_SHIFT)) & TMPSNS_CTRL1_SET_START_MASK) + #define TMPSNS_CTRL1_SET_PWD_MASK (0x800000U) #define TMPSNS_CTRL1_SET_PWD_SHIFT (23U) /*! PWD - Temperature Sensor Power Down */ #define TMPSNS_CTRL1_SET_PWD(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PWD_SHIFT)) & TMPSNS_CTRL1_SET_PWD_MASK) + #define TMPSNS_CTRL1_SET_RFU_MASK (0x7F000000U) #define TMPSNS_CTRL1_SET_RFU_SHIFT (24U) /*! RFU - Read/Writeable field. Reserved for future use */ #define TMPSNS_CTRL1_SET_RFU(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_RFU_SHIFT)) & TMPSNS_CTRL1_SET_RFU_MASK) + #define TMPSNS_CTRL1_SET_PWD_FULL_MASK (0x80000000U) #define TMPSNS_CTRL1_SET_PWD_FULL_SHIFT (31U) /*! PWD_FULL - Temperature Sensor Full Power Down @@ -82221,46 +91698,55 @@ typedef struct { /*! @name CTRL1_CLR - Temperature Sensor Control Register 1 */ /*! @{ */ + #define TMPSNS_CTRL1_CLR_FREQ_MASK (0xFFFFU) #define TMPSNS_CTRL1_CLR_FREQ_SHIFT (0U) /*! FREQ - Temperature Measurement Frequency */ #define TMPSNS_CTRL1_CLR_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_FREQ_SHIFT)) & TMPSNS_CTRL1_CLR_FREQ_MASK) + #define TMPSNS_CTRL1_CLR_FINISH_IE_MASK (0x10000U) #define TMPSNS_CTRL1_CLR_FINISH_IE_SHIFT (16U) -/*! FINISH_IE - Measurment finished interrupt enable +/*! FINISH_IE - Measurement finished interrupt enable */ #define TMPSNS_CTRL1_CLR_FINISH_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_CLR_FINISH_IE_MASK) + #define TMPSNS_CTRL1_CLR_LOW_TEMP_IE_MASK (0x20000U) #define TMPSNS_CTRL1_CLR_LOW_TEMP_IE_SHIFT (17U) /*! LOW_TEMP_IE - Low temperature interrupt enable */ #define TMPSNS_CTRL1_CLR_LOW_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_LOW_TEMP_IE_MASK) + #define TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_MASK (0x40000U) #define TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_SHIFT (18U) /*! HIGH_TEMP_IE - High temperature interrupt enable */ #define TMPSNS_CTRL1_CLR_HIGH_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_MASK) + #define TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_MASK (0x80000U) #define TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_SHIFT (19U) /*! PANIC_TEMP_IE - Panic temperature interrupt enable */ #define TMPSNS_CTRL1_CLR_PANIC_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_MASK) + #define TMPSNS_CTRL1_CLR_START_MASK (0x400000U) #define TMPSNS_CTRL1_CLR_START_SHIFT (22U) /*! START - Start Temperature Measurement */ #define TMPSNS_CTRL1_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_START_SHIFT)) & TMPSNS_CTRL1_CLR_START_MASK) + #define TMPSNS_CTRL1_CLR_PWD_MASK (0x800000U) #define TMPSNS_CTRL1_CLR_PWD_SHIFT (23U) /*! PWD - Temperature Sensor Power Down */ #define TMPSNS_CTRL1_CLR_PWD(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PWD_SHIFT)) & TMPSNS_CTRL1_CLR_PWD_MASK) + #define TMPSNS_CTRL1_CLR_RFU_MASK (0x7F000000U) #define TMPSNS_CTRL1_CLR_RFU_SHIFT (24U) /*! RFU - Read/Writeable field. Reserved for future use */ #define TMPSNS_CTRL1_CLR_RFU(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_RFU_SHIFT)) & TMPSNS_CTRL1_CLR_RFU_MASK) + #define TMPSNS_CTRL1_CLR_PWD_FULL_MASK (0x80000000U) #define TMPSNS_CTRL1_CLR_PWD_FULL_SHIFT (31U) /*! PWD_FULL - Temperature Sensor Full Power Down @@ -82270,46 +91756,55 @@ typedef struct { /*! @name CTRL1_TOG - Temperature Sensor Control Register 1 */ /*! @{ */ + #define TMPSNS_CTRL1_TOG_FREQ_MASK (0xFFFFU) #define TMPSNS_CTRL1_TOG_FREQ_SHIFT (0U) /*! FREQ - Temperature Measurement Frequency */ #define TMPSNS_CTRL1_TOG_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_FREQ_SHIFT)) & TMPSNS_CTRL1_TOG_FREQ_MASK) + #define TMPSNS_CTRL1_TOG_FINISH_IE_MASK (0x10000U) #define TMPSNS_CTRL1_TOG_FINISH_IE_SHIFT (16U) -/*! FINISH_IE - Measurment finished interrupt enable +/*! FINISH_IE - Measurement finished interrupt enable */ #define TMPSNS_CTRL1_TOG_FINISH_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_TOG_FINISH_IE_MASK) + #define TMPSNS_CTRL1_TOG_LOW_TEMP_IE_MASK (0x20000U) #define TMPSNS_CTRL1_TOG_LOW_TEMP_IE_SHIFT (17U) /*! LOW_TEMP_IE - Low temperature interrupt enable */ #define TMPSNS_CTRL1_TOG_LOW_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_LOW_TEMP_IE_MASK) + #define TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_MASK (0x40000U) #define TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_SHIFT (18U) /*! HIGH_TEMP_IE - High temperature interrupt enable */ #define TMPSNS_CTRL1_TOG_HIGH_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_MASK) + #define TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_MASK (0x80000U) #define TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_SHIFT (19U) /*! PANIC_TEMP_IE - Panic temperature interrupt enable */ #define TMPSNS_CTRL1_TOG_PANIC_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_MASK) + #define TMPSNS_CTRL1_TOG_START_MASK (0x400000U) #define TMPSNS_CTRL1_TOG_START_SHIFT (22U) /*! START - Start Temperature Measurement */ #define TMPSNS_CTRL1_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_START_SHIFT)) & TMPSNS_CTRL1_TOG_START_MASK) + #define TMPSNS_CTRL1_TOG_PWD_MASK (0x800000U) #define TMPSNS_CTRL1_TOG_PWD_SHIFT (23U) /*! PWD - Temperature Sensor Power Down */ #define TMPSNS_CTRL1_TOG_PWD(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PWD_SHIFT)) & TMPSNS_CTRL1_TOG_PWD_MASK) + #define TMPSNS_CTRL1_TOG_RFU_MASK (0x7F000000U) #define TMPSNS_CTRL1_TOG_RFU_SHIFT (24U) /*! RFU - Read/Writeable field. Reserved for future use */ #define TMPSNS_CTRL1_TOG_RFU(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_RFU_SHIFT)) & TMPSNS_CTRL1_TOG_RFU_MASK) + #define TMPSNS_CTRL1_TOG_PWD_FULL_MASK (0x80000000U) #define TMPSNS_CTRL1_TOG_PWD_FULL_SHIFT (31U) /*! PWD_FULL - Temperature Sensor Full Power Down @@ -82319,11 +91814,13 @@ typedef struct { /*! @name RANGE0 - Temperature Sensor Range Register 0 */ /*! @{ */ + #define TMPSNS_RANGE0_LOW_TEMP_VAL_MASK (0xFFFU) #define TMPSNS_RANGE0_LOW_TEMP_VAL_SHIFT (0U) /*! LOW_TEMP_VAL - Low temperature threshold value */ #define TMPSNS_RANGE0_LOW_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_LOW_TEMP_VAL_MASK) + #define TMPSNS_RANGE0_HIGH_TEMP_VAL_MASK (0xFFF0000U) #define TMPSNS_RANGE0_HIGH_TEMP_VAL_SHIFT (16U) /*! HIGH_TEMP_VAL - High temperature threshold value @@ -82333,11 +91830,13 @@ typedef struct { /*! @name RANGE0_SET - Temperature Sensor Range Register 0 */ /*! @{ */ + #define TMPSNS_RANGE0_SET_LOW_TEMP_VAL_MASK (0xFFFU) #define TMPSNS_RANGE0_SET_LOW_TEMP_VAL_SHIFT (0U) /*! LOW_TEMP_VAL - Low temperature threshold value */ #define TMPSNS_RANGE0_SET_LOW_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_SET_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_SET_LOW_TEMP_VAL_MASK) + #define TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_MASK (0xFFF0000U) #define TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_SHIFT (16U) /*! HIGH_TEMP_VAL - High temperature threshold value @@ -82347,11 +91846,13 @@ typedef struct { /*! @name RANGE0_CLR - Temperature Sensor Range Register 0 */ /*! @{ */ + #define TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_MASK (0xFFFU) #define TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_SHIFT (0U) /*! LOW_TEMP_VAL - Low temperature threshold value */ #define TMPSNS_RANGE0_CLR_LOW_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_MASK) + #define TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_MASK (0xFFF0000U) #define TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_SHIFT (16U) /*! HIGH_TEMP_VAL - High temperature threshold value @@ -82361,11 +91862,13 @@ typedef struct { /*! @name RANGE0_TOG - Temperature Sensor Range Register 0 */ /*! @{ */ + #define TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_MASK (0xFFFU) #define TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_SHIFT (0U) /*! LOW_TEMP_VAL - Low temperature threshold value */ #define TMPSNS_RANGE0_TOG_LOW_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_MASK) + #define TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_MASK (0xFFF0000U) #define TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_SHIFT (16U) /*! HIGH_TEMP_VAL - High temperature threshold value @@ -82375,6 +91878,7 @@ typedef struct { /*! @name RANGE1 - Temperature Sensor Range Register 1 */ /*! @{ */ + #define TMPSNS_RANGE1_PANIC_TEMP_VAL_MASK (0xFFFU) #define TMPSNS_RANGE1_PANIC_TEMP_VAL_SHIFT (0U) /*! PANIC_TEMP_VAL - Panic temperature threshold value @@ -82384,6 +91888,7 @@ typedef struct { /*! @name RANGE1_SET - Temperature Sensor Range Register 1 */ /*! @{ */ + #define TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_MASK (0xFFFU) #define TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_SHIFT (0U) /*! PANIC_TEMP_VAL - Panic temperature threshold value @@ -82393,6 +91898,7 @@ typedef struct { /*! @name RANGE1_CLR - Temperature Sensor Range Register 1 */ /*! @{ */ + #define TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_MASK (0xFFFU) #define TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_SHIFT (0U) /*! PANIC_TEMP_VAL - Panic temperature threshold value @@ -82402,6 +91908,7 @@ typedef struct { /*! @name RANGE1_TOG - Temperature Sensor Range Register 1 */ /*! @{ */ + #define TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_MASK (0xFFFU) #define TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_SHIFT (0U) /*! PANIC_TEMP_VAL - Panic temperature threshold value @@ -82409,100 +91916,23 @@ typedef struct { #define TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_MASK) /*! @} */ -/*! @name OFFSET_COMP - Temperature Sensor Offset Compensation Register */ -/*! @{ */ -#define TMPSNS_OFFSET_COMP_HW_COMP_DIS_MASK (0x1U) -#define TMPSNS_OFFSET_COMP_HW_COMP_DIS_SHIFT (0U) -/*! HW_COMP_DIS - Hardware compensation disable bit - * 0b0..Hardware compensation is enabled - * 0b1..Hardware compensation is disabled - */ -#define TMPSNS_OFFSET_COMP_HW_COMP_DIS(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_OFFSET_COMP_HW_COMP_DIS_SHIFT)) & TMPSNS_OFFSET_COMP_HW_COMP_DIS_MASK) -#define TMPSNS_OFFSET_COMP_HW_COMP_SMPL_SIZ_MASK (0x4U) -#define TMPSNS_OFFSET_COMP_HW_COMP_SMPL_SIZ_SHIFT (2U) -/*! HW_COMP_SMPL_SIZ - Hardware compensation sample size control bit - * 0b0..Sample size is 16 - * 0b1..Sample size is 32 - */ -#define TMPSNS_OFFSET_COMP_HW_COMP_SMPL_SIZ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_OFFSET_COMP_HW_COMP_SMPL_SIZ_SHIFT)) & TMPSNS_OFFSET_COMP_HW_COMP_SMPL_SIZ_MASK) -#define TMPSNS_OFFSET_COMP_SW_COMP_SEL_TGL_MASK (0x10U) -#define TMPSNS_OFFSET_COMP_SW_COMP_SEL_TGL_SHIFT (4U) -/*! SW_COMP_SEL_TGL - Software compensation toggle control bit - */ -#define TMPSNS_OFFSET_COMP_SW_COMP_SEL_TGL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_OFFSET_COMP_SW_COMP_SEL_TGL_SHIFT)) & TMPSNS_OFFSET_COMP_SW_COMP_SEL_TGL_MASK) -/*! @} */ - -/*! @name OFFSET_COMP_SET - Temperature Sensor Offset Compensation Register */ -/*! @{ */ -#define TMPSNS_OFFSET_COMP_SET_HW_COMP_DIS_MASK (0x1U) -#define TMPSNS_OFFSET_COMP_SET_HW_COMP_DIS_SHIFT (0U) -/*! HW_COMP_DIS - Hardware compensation disable bit - */ -#define TMPSNS_OFFSET_COMP_SET_HW_COMP_DIS(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_OFFSET_COMP_SET_HW_COMP_DIS_SHIFT)) & TMPSNS_OFFSET_COMP_SET_HW_COMP_DIS_MASK) -#define TMPSNS_OFFSET_COMP_SET_HW_COMP_SMPL_SIZ_MASK (0x4U) -#define TMPSNS_OFFSET_COMP_SET_HW_COMP_SMPL_SIZ_SHIFT (2U) -/*! HW_COMP_SMPL_SIZ - Hardware compensation sample size control bit - */ -#define TMPSNS_OFFSET_COMP_SET_HW_COMP_SMPL_SIZ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_OFFSET_COMP_SET_HW_COMP_SMPL_SIZ_SHIFT)) & TMPSNS_OFFSET_COMP_SET_HW_COMP_SMPL_SIZ_MASK) -#define TMPSNS_OFFSET_COMP_SET_SW_COMP_SEL_TGL_MASK (0x10U) -#define TMPSNS_OFFSET_COMP_SET_SW_COMP_SEL_TGL_SHIFT (4U) -/*! SW_COMP_SEL_TGL - Software compensation toggle control bit - */ -#define TMPSNS_OFFSET_COMP_SET_SW_COMP_SEL_TGL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_OFFSET_COMP_SET_SW_COMP_SEL_TGL_SHIFT)) & TMPSNS_OFFSET_COMP_SET_SW_COMP_SEL_TGL_MASK) -/*! @} */ - -/*! @name OFFSET_COMP_CLR - Temperature Sensor Offset Compensation Register */ -/*! @{ */ -#define TMPSNS_OFFSET_COMP_CLR_HW_COMP_DIS_MASK (0x1U) -#define TMPSNS_OFFSET_COMP_CLR_HW_COMP_DIS_SHIFT (0U) -/*! HW_COMP_DIS - Hardware compensation disable bit - */ -#define TMPSNS_OFFSET_COMP_CLR_HW_COMP_DIS(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_OFFSET_COMP_CLR_HW_COMP_DIS_SHIFT)) & TMPSNS_OFFSET_COMP_CLR_HW_COMP_DIS_MASK) -#define TMPSNS_OFFSET_COMP_CLR_HW_COMP_SMPL_SIZ_MASK (0x4U) -#define TMPSNS_OFFSET_COMP_CLR_HW_COMP_SMPL_SIZ_SHIFT (2U) -/*! HW_COMP_SMPL_SIZ - Hardware compensation sample size control bit - */ -#define TMPSNS_OFFSET_COMP_CLR_HW_COMP_SMPL_SIZ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_OFFSET_COMP_CLR_HW_COMP_SMPL_SIZ_SHIFT)) & TMPSNS_OFFSET_COMP_CLR_HW_COMP_SMPL_SIZ_MASK) -#define TMPSNS_OFFSET_COMP_CLR_SW_COMP_SEL_TGL_MASK (0x10U) -#define TMPSNS_OFFSET_COMP_CLR_SW_COMP_SEL_TGL_SHIFT (4U) -/*! SW_COMP_SEL_TGL - Software compensation toggle control bit - */ -#define TMPSNS_OFFSET_COMP_CLR_SW_COMP_SEL_TGL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_OFFSET_COMP_CLR_SW_COMP_SEL_TGL_SHIFT)) & TMPSNS_OFFSET_COMP_CLR_SW_COMP_SEL_TGL_MASK) -/*! @} */ - -/*! @name OFFSET_COMP_TOG - Temperature Sensor Offset Compensation Register */ -/*! @{ */ -#define TMPSNS_OFFSET_COMP_TOG_HW_COMP_DIS_MASK (0x1U) -#define TMPSNS_OFFSET_COMP_TOG_HW_COMP_DIS_SHIFT (0U) -/*! HW_COMP_DIS - Hardware compensation disable bit - */ -#define TMPSNS_OFFSET_COMP_TOG_HW_COMP_DIS(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_OFFSET_COMP_TOG_HW_COMP_DIS_SHIFT)) & TMPSNS_OFFSET_COMP_TOG_HW_COMP_DIS_MASK) -#define TMPSNS_OFFSET_COMP_TOG_HW_COMP_SMPL_SIZ_MASK (0x4U) -#define TMPSNS_OFFSET_COMP_TOG_HW_COMP_SMPL_SIZ_SHIFT (2U) -/*! HW_COMP_SMPL_SIZ - Hardware compensation sample size control bit - */ -#define TMPSNS_OFFSET_COMP_TOG_HW_COMP_SMPL_SIZ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_OFFSET_COMP_TOG_HW_COMP_SMPL_SIZ_SHIFT)) & TMPSNS_OFFSET_COMP_TOG_HW_COMP_SMPL_SIZ_MASK) -#define TMPSNS_OFFSET_COMP_TOG_SW_COMP_SEL_TGL_MASK (0x10U) -#define TMPSNS_OFFSET_COMP_TOG_SW_COMP_SEL_TGL_SHIFT (4U) -/*! SW_COMP_SEL_TGL - Software compensation toggle control bit - */ -#define TMPSNS_OFFSET_COMP_TOG_SW_COMP_SEL_TGL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_OFFSET_COMP_TOG_SW_COMP_SEL_TGL_SHIFT)) & TMPSNS_OFFSET_COMP_TOG_SW_COMP_SEL_TGL_MASK) -/*! @} */ - /*! @name STATUS0 - Temperature Sensor Status Register 0 */ /*! @{ */ + #define TMPSNS_STATUS0_TEMP_VAL_MASK (0xFFFU) #define TMPSNS_STATUS0_TEMP_VAL_SHIFT (0U) /*! TEMP_VAL - Measured temperature value */ #define TMPSNS_STATUS0_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_TEMP_VAL_SHIFT)) & TMPSNS_STATUS0_TEMP_VAL_MASK) + #define TMPSNS_STATUS0_FINISH_MASK (0x10000U) #define TMPSNS_STATUS0_FINISH_SHIFT (16U) /*! FINISH - Temperature measurement complete - * 0b0..Temperature sensor is busy (if START = 1)or no new reading has been initiated (if START = 0) + * 0b0..Temperature sensor is busy (if CTRL1[START] = 1)or no new reading has been initiated (if CTRL1[START] = 0) * 0b1..Temperature reading is complete and new temperature value available for reading */ #define TMPSNS_STATUS0_FINISH(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_FINISH_SHIFT)) & TMPSNS_STATUS0_FINISH_MASK) + #define TMPSNS_STATUS0_LOW_TEMP_MASK (0x20000U) #define TMPSNS_STATUS0_LOW_TEMP_SHIFT (17U) /*! LOW_TEMP - Low temperature alarm bit @@ -82510,6 +91940,7 @@ typedef struct { * 0b1..Low temperature alert */ #define TMPSNS_STATUS0_LOW_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_LOW_TEMP_SHIFT)) & TMPSNS_STATUS0_LOW_TEMP_MASK) + #define TMPSNS_STATUS0_HIGH_TEMP_MASK (0x40000U) #define TMPSNS_STATUS0_HIGH_TEMP_SHIFT (18U) /*! HIGH_TEMP - High temperature alarm bit @@ -82517,6 +91948,7 @@ typedef struct { * 0b1..High temperature alert */ #define TMPSNS_STATUS0_HIGH_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_HIGH_TEMP_SHIFT)) & TMPSNS_STATUS0_HIGH_TEMP_MASK) + #define TMPSNS_STATUS0_PANIC_TEMP_MASK (0x80000U) #define TMPSNS_STATUS0_PANIC_TEMP_SHIFT (19U) /*! PANIC_TEMP - Panic temperature alarm bit @@ -82588,6 +92020,7 @@ typedef struct { /*! @name COMP1 - Timer Channel Compare Register 1 */ /*! @{ */ + #define TMR_COMP1_COMPARISON_1_MASK (0xFFFFU) #define TMR_COMP1_COMPARISON_1_SHIFT (0U) /*! COMPARISON_1 - Comparison Value 1 @@ -82600,6 +92033,7 @@ typedef struct { /*! @name COMP2 - Timer Channel Compare Register 2 */ /*! @{ */ + #define TMR_COMP2_COMPARISON_2_MASK (0xFFFFU) #define TMR_COMP2_COMPARISON_2_SHIFT (0U) /*! COMPARISON_2 - Comparison Value 2 @@ -82612,6 +92046,7 @@ typedef struct { /*! @name CAPT - Timer Channel Capture Register */ /*! @{ */ + #define TMR_CAPT_CAPTURE_MASK (0xFFFFU) #define TMR_CAPT_CAPTURE_SHIFT (0U) /*! CAPTURE - Capture Value @@ -82624,6 +92059,7 @@ typedef struct { /*! @name LOAD - Timer Channel Load Register */ /*! @{ */ + #define TMR_LOAD_LOAD_MASK (0xFFFFU) #define TMR_LOAD_LOAD_SHIFT (0U) /*! LOAD - Timer Load Register @@ -82636,6 +92072,7 @@ typedef struct { /*! @name HOLD - Timer Channel Hold Register */ /*! @{ */ + #define TMR_HOLD_HOLD_MASK (0xFFFFU) #define TMR_HOLD_HOLD_SHIFT (0U) /*! HOLD - HOLD @@ -82648,6 +92085,7 @@ typedef struct { /*! @name CNTR - Timer Channel Counter Register */ /*! @{ */ + #define TMR_CNTR_COUNTER_MASK (0xFFFFU) #define TMR_CNTR_COUNTER_SHIFT (0U) /*! COUNTER - COUNTER @@ -82660,6 +92098,7 @@ typedef struct { /*! @name CTRL - Timer Channel Control Register */ /*! @{ */ + #define TMR_CTRL_OUTMODE_MASK (0x7U) #define TMR_CTRL_OUTMODE_SHIFT (0U) /*! OUTMODE - Output Mode @@ -82673,6 +92112,7 @@ typedef struct { * 0b111..Enable gated clock output while counter is active */ #define TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK) + #define TMR_CTRL_COINIT_MASK (0x8U) #define TMR_CTRL_COINIT_SHIFT (3U) /*! COINIT - Co-Channel Initialization @@ -82680,6 +92120,7 @@ typedef struct { * 0b1..Co-channel counter/timers may force a re-initialization of this counter/timer */ #define TMR_CTRL_COINIT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK) + #define TMR_CTRL_DIR_MASK (0x10U) #define TMR_CTRL_DIR_SHIFT (4U) /*! DIR - Count Direction @@ -82687,6 +92128,7 @@ typedef struct { * 0b1..Count down. */ #define TMR_CTRL_DIR(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK) + #define TMR_CTRL_LENGTH_MASK (0x20U) #define TMR_CTRL_LENGTH_SHIFT (5U) /*! LENGTH - Count Length @@ -82698,6 +92140,7 @@ typedef struct { * value is reached, re-initializes, counts until COMP1 value is reached, and so on. */ #define TMR_CTRL_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK) + #define TMR_CTRL_ONCE_MASK (0x40U) #define TMR_CTRL_ONCE_SHIFT (6U) /*! ONCE - Count Once @@ -82708,6 +92151,7 @@ typedef struct { * the COMP2 value, and then stops. */ #define TMR_CTRL_ONCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK) + #define TMR_CTRL_SCS_MASK (0x180U) #define TMR_CTRL_SCS_SHIFT (7U) /*! SCS - Secondary Count Source @@ -82717,6 +92161,7 @@ typedef struct { * 0b11..Counter 3 input pin */ #define TMR_CTRL_SCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK) + #define TMR_CTRL_PCS_MASK (0x1E00U) #define TMR_CTRL_PCS_SHIFT (9U) /*! PCS - Primary Count Source @@ -82738,6 +92183,7 @@ typedef struct { * 0b1111..IP bus clock divide by 128 prescaler */ #define TMR_CTRL_PCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK) + #define TMR_CTRL_CM_MASK (0xE000U) #define TMR_CTRL_CM_SHIFT (13U) /*! CM - Count Mode @@ -82761,6 +92207,7 @@ typedef struct { /*! @name SCTRL - Timer Channel Status and Control Register */ /*! @{ */ + #define TMR_SCTRL_OEN_MASK (0x1U) #define TMR_SCTRL_OEN_SHIFT (0U) /*! OEN - Output Enable @@ -82769,6 +92216,7 @@ typedef struct { * their input see the driven value. The polarity of the signal is determined by OPS. */ #define TMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK) + #define TMR_SCTRL_OPS_MASK (0x2U) #define TMR_SCTRL_OPS_SHIFT (1U) /*! OPS - Output Polarity Select @@ -82776,26 +92224,31 @@ typedef struct { * 0b1..Inverted polarity. */ #define TMR_SCTRL_OPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK) + #define TMR_SCTRL_FORCE_MASK (0x4U) #define TMR_SCTRL_FORCE_SHIFT (2U) /*! FORCE - Force OFLAG Output */ #define TMR_SCTRL_FORCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK) + #define TMR_SCTRL_VAL_MASK (0x8U) #define TMR_SCTRL_VAL_SHIFT (3U) /*! VAL - Forced OFLAG Value */ #define TMR_SCTRL_VAL(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK) + #define TMR_SCTRL_EEOF_MASK (0x10U) #define TMR_SCTRL_EEOF_SHIFT (4U) /*! EEOF - Enable External OFLAG Force */ #define TMR_SCTRL_EEOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK) + #define TMR_SCTRL_MSTR_MASK (0x20U) #define TMR_SCTRL_MSTR_SHIFT (5U) /*! MSTR - Master Mode */ #define TMR_SCTRL_MSTR(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK) + #define TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U) #define TMR_SCTRL_CAPTURE_MODE_SHIFT (6U) /*! CAPTURE_MODE - Input Capture Mode @@ -82805,41 +92258,49 @@ typedef struct { * 0b11..Load capture register on both edges of input */ #define TMR_SCTRL_CAPTURE_MODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK) + #define TMR_SCTRL_INPUT_MASK (0x100U) #define TMR_SCTRL_INPUT_SHIFT (8U) /*! INPUT - External Input Signal */ #define TMR_SCTRL_INPUT(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK) + #define TMR_SCTRL_IPS_MASK (0x200U) #define TMR_SCTRL_IPS_SHIFT (9U) /*! IPS - Input Polarity Select */ #define TMR_SCTRL_IPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK) + #define TMR_SCTRL_IEFIE_MASK (0x400U) #define TMR_SCTRL_IEFIE_SHIFT (10U) /*! IEFIE - Input Edge Flag Interrupt Enable */ #define TMR_SCTRL_IEFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK) + #define TMR_SCTRL_IEF_MASK (0x800U) #define TMR_SCTRL_IEF_SHIFT (11U) /*! IEF - Input Edge Flag */ #define TMR_SCTRL_IEF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK) + #define TMR_SCTRL_TOFIE_MASK (0x1000U) #define TMR_SCTRL_TOFIE_SHIFT (12U) /*! TOFIE - Timer Overflow Flag Interrupt Enable */ #define TMR_SCTRL_TOFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK) + #define TMR_SCTRL_TOF_MASK (0x2000U) #define TMR_SCTRL_TOF_SHIFT (13U) /*! TOF - Timer Overflow Flag */ #define TMR_SCTRL_TOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK) + #define TMR_SCTRL_TCFIE_MASK (0x4000U) #define TMR_SCTRL_TCFIE_SHIFT (14U) /*! TCFIE - Timer Compare Flag Interrupt Enable */ #define TMR_SCTRL_TCFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK) + #define TMR_SCTRL_TCF_MASK (0x8000U) #define TMR_SCTRL_TCF_SHIFT (15U) /*! TCF - Timer Compare Flag @@ -82852,6 +92313,7 @@ typedef struct { /*! @name CMPLD1 - Timer Channel Comparator Load Register 1 */ /*! @{ */ + #define TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU) #define TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U) /*! COMPARATOR_LOAD_1 - COMPARATOR_LOAD_1 @@ -82864,6 +92326,7 @@ typedef struct { /*! @name CMPLD2 - Timer Channel Comparator Load Register 2 */ /*! @{ */ + #define TMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU) #define TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U) /*! COMPARATOR_LOAD_2 - COMPARATOR_LOAD_2 @@ -82876,6 +92339,7 @@ typedef struct { /*! @name CSCTRL - Timer Channel Comparator Status and Control Register */ /*! @{ */ + #define TMR_CSCTRL_CL1_MASK (0x3U) #define TMR_CSCTRL_CL1_SHIFT (0U) /*! CL1 - Compare Load Control 1 @@ -82885,6 +92349,7 @@ typedef struct { * 0b11..Reserved */ #define TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK) + #define TMR_CSCTRL_CL2_MASK (0xCU) #define TMR_CSCTRL_CL2_SHIFT (2U) /*! CL2 - Compare Load Control 2 @@ -82894,26 +92359,31 @@ typedef struct { * 0b11..Reserved */ #define TMR_CSCTRL_CL2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK) + #define TMR_CSCTRL_TCF1_MASK (0x10U) #define TMR_CSCTRL_TCF1_SHIFT (4U) /*! TCF1 - Timer Compare 1 Interrupt Flag */ #define TMR_CSCTRL_TCF1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK) + #define TMR_CSCTRL_TCF2_MASK (0x20U) #define TMR_CSCTRL_TCF2_SHIFT (5U) /*! TCF2 - Timer Compare 2 Interrupt Flag */ #define TMR_CSCTRL_TCF2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK) + #define TMR_CSCTRL_TCF1EN_MASK (0x40U) #define TMR_CSCTRL_TCF1EN_SHIFT (6U) /*! TCF1EN - Timer Compare 1 Interrupt Enable */ #define TMR_CSCTRL_TCF1EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK) + #define TMR_CSCTRL_TCF2EN_MASK (0x80U) #define TMR_CSCTRL_TCF2EN_SHIFT (7U) /*! TCF2EN - Timer Compare 2 Interrupt Enable */ #define TMR_CSCTRL_TCF2EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK) + #define TMR_CSCTRL_UP_MASK (0x200U) #define TMR_CSCTRL_UP_SHIFT (9U) /*! UP - Counting Direction Indicator @@ -82921,6 +92391,7 @@ typedef struct { * 0b1..The last count was in the UP direction. */ #define TMR_CSCTRL_UP(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK) + #define TMR_CSCTRL_TCI_MASK (0x400U) #define TMR_CSCTRL_TCI_SHIFT (10U) /*! TCI - Triggered Count Initialization Control @@ -82928,6 +92399,7 @@ typedef struct { * 0b1..Reload the counter upon receiving a second trigger event while still counting from the first trigger event. */ #define TMR_CSCTRL_TCI(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK) + #define TMR_CSCTRL_ROC_MASK (0x800U) #define TMR_CSCTRL_ROC_SHIFT (11U) /*! ROC - Reload on Capture @@ -82935,6 +92407,7 @@ typedef struct { * 0b1..Reload the counter on a capture event. */ #define TMR_CSCTRL_ROC(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK) + #define TMR_CSCTRL_ALT_LOAD_MASK (0x1000U) #define TMR_CSCTRL_ALT_LOAD_SHIFT (12U) /*! ALT_LOAD - Alternative Load Enable @@ -82942,6 +92415,7 @@ typedef struct { * 0b1..Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction. */ #define TMR_CSCTRL_ALT_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK) + #define TMR_CSCTRL_FAULT_MASK (0x2000U) #define TMR_CSCTRL_FAULT_SHIFT (13U) /*! FAULT - Fault Enable @@ -82949,6 +92423,7 @@ typedef struct { * 0b1..Fault function enabled. */ #define TMR_CSCTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK) + #define TMR_CSCTRL_DBG_EN_MASK (0xC000U) #define TMR_CSCTRL_DBG_EN_SHIFT (14U) /*! DBG_EN - Debug Actions Enable @@ -82965,11 +92440,13 @@ typedef struct { /*! @name FILT - Timer Channel Input Filter Register */ /*! @{ */ + #define TMR_FILT_FILT_PER_MASK (0xFFU) #define TMR_FILT_FILT_PER_SHIFT (0U) /*! FILT_PER - Input Filter Sample Period */ #define TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK) + #define TMR_FILT_FILT_CNT_MASK (0x700U) #define TMR_FILT_FILT_CNT_SHIFT (8U) /*! FILT_CNT - Input Filter Sample Count @@ -82982,16 +92459,19 @@ typedef struct { /*! @name DMA - Timer Channel DMA Enable Register */ /*! @{ */ + #define TMR_DMA_IEFDE_MASK (0x1U) #define TMR_DMA_IEFDE_SHIFT (0U) /*! IEFDE - Input Edge Flag DMA Enable */ #define TMR_DMA_IEFDE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK) + #define TMR_DMA_CMPLD1DE_MASK (0x2U) #define TMR_DMA_CMPLD1DE_SHIFT (1U) /*! CMPLD1DE - Comparator Preload Register 1 DMA Enable */ #define TMR_DMA_CMPLD1DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK) + #define TMR_DMA_CMPLD2DE_MASK (0x4U) #define TMR_DMA_CMPLD2DE_SHIFT (2U) /*! CMPLD2DE - Comparator Preload Register 2 DMA Enable @@ -83004,6 +92484,7 @@ typedef struct { /*! @name ENBL - Timer Channel Enable Register */ /*! @{ */ + #define TMR_ENBL_ENBL_MASK (0xFU) #define TMR_ENBL_ENBL_SHIFT (0U) /*! ENBL - Timer Channel Enable @@ -83129,31 +92610,42 @@ typedef struct { /*! @name ID - Identification register */ /*! @{ */ + #define USB_ID_ID_MASK (0x3FU) #define USB_ID_ID_SHIFT (0U) +/*! ID - ID + */ #define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK) + #define USB_ID_NID_MASK (0x3F00U) #define USB_ID_NID_SHIFT (8U) +/*! NID - NID + */ #define USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK) + #define USB_ID_REVISION_MASK (0xFF0000U) #define USB_ID_REVISION_SHIFT (16U) +/*! REVISION - REVISION + */ #define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK) /*! @} */ /*! @name HWGENERAL - Hardware General */ /*! @{ */ + #define USB_HWGENERAL_PHYW_MASK (0x30U) #define USB_HWGENERAL_PHYW_SHIFT (4U) -/*! PHYW - * 0b00..8 bit wide data bus Software non-programmable - * 0b01..16 bit wide data bus Software non-programmable - * 0b10..Reset to 8 bit wide data bus Software programmable - * 0b11..Reset to 16 bit wide data bus Software programmable +/*! PHYW - PHYW + * 0b00..8 bit wide data bus (Software non-programmable) + * 0b01..16 bit wide data bus (Software non-programmable) + * 0b10..Reset to 8 bit wide data bus (Software programmable) + * 0b11..Reset to 16 bit wide data bus (Software programmable) */ #define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK) + #define USB_HWGENERAL_PHYM_MASK (0x1C0U) #define USB_HWGENERAL_PHYM_SHIFT (6U) -/*! PHYM +/*! PHYM - PHYM * 0b000..UTMI/UMTI+ * 0b001..ULPI DDR * 0b010..ULPI @@ -83164,9 +92656,10 @@ typedef struct { * 0b111..Software programmable - reset to Serial */ #define USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK) + #define USB_HWGENERAL_SM_MASK (0x600U) #define USB_HWGENERAL_SM_SHIFT (9U) -/*! SM +/*! SM - SM * 0b00..No Serial Engine, always use parallel signalling. * 0b01..Serial Engine present, always use serial signalling for FS/LS. * 0b10..Software programmable - Reset to use parallel signalling for FS/LS @@ -83177,81 +92670,110 @@ typedef struct { /*! @name HWHOST - Host Hardware Parameters */ /*! @{ */ + #define USB_HWHOST_HC_MASK (0x1U) #define USB_HWHOST_HC_SHIFT (0U) -/*! HC +/*! HC - HC * 0b1..Supported * 0b0..Not supported */ #define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK) + #define USB_HWHOST_NPORT_MASK (0xEU) #define USB_HWHOST_NPORT_SHIFT (1U) +/*! NPORT - NPORT + */ #define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK) /*! @} */ /*! @name HWDEVICE - Device Hardware Parameters */ /*! @{ */ + #define USB_HWDEVICE_DC_MASK (0x1U) #define USB_HWDEVICE_DC_SHIFT (0U) -/*! DC +/*! DC - DC * 0b1..Supported * 0b0..Not supported */ #define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK) + #define USB_HWDEVICE_DEVEP_MASK (0x3EU) #define USB_HWDEVICE_DEVEP_SHIFT (1U) +/*! DEVEP - DEVEP + */ #define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK) /*! @} */ /*! @name HWTXBUF - TX Buffer Hardware Parameters */ /*! @{ */ + #define USB_HWTXBUF_TXBURST_MASK (0xFFU) #define USB_HWTXBUF_TXBURST_SHIFT (0U) +/*! TXBURST - TXBURST + */ #define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK) + #define USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U) #define USB_HWTXBUF_TXCHANADD_SHIFT (16U) +/*! TXCHANADD - TXCHANADD + */ #define USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK) /*! @} */ /*! @name HWRXBUF - RX Buffer Hardware Parameters */ /*! @{ */ + #define USB_HWRXBUF_RXBURST_MASK (0xFFU) #define USB_HWRXBUF_RXBURST_SHIFT (0U) +/*! RXBURST - RXBURST + */ #define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK) + #define USB_HWRXBUF_RXADD_MASK (0xFF00U) #define USB_HWRXBUF_RXADD_SHIFT (8U) +/*! RXADD - RXADD + */ #define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK) /*! @} */ /*! @name GPTIMER0LD - General Purpose Timer #0 Load */ /*! @{ */ + #define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU) #define USB_GPTIMER0LD_GPTLD_SHIFT (0U) +/*! GPTLD - GPTLD + */ #define USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK) /*! @} */ /*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */ /*! @{ */ + #define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU) #define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U) +/*! GPTCNT - GPTCNT + */ #define USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK) + #define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U) #define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U) -/*! GPTMODE +/*! GPTMODE - GPTMODE * 0b0..One Shot Mode * 0b1..Repeat Mode */ #define USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK) + #define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U) #define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U) -/*! GPTRST +/*! GPTRST - GPTRST * 0b0..No action * 0b1..Load counter value from GPTLD bits in n_GPTIMER0LD */ #define USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK) + #define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U) #define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U) -/*! GPTRUN +/*! GPTRUN - GPTRUN * 0b0..Stop counting * 0b1..Run */ @@ -83260,33 +92782,42 @@ typedef struct { /*! @name GPTIMER1LD - General Purpose Timer #1 Load */ /*! @{ */ + #define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU) #define USB_GPTIMER1LD_GPTLD_SHIFT (0U) +/*! GPTLD - GPTLD + */ #define USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK) /*! @} */ /*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */ /*! @{ */ + #define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU) #define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U) +/*! GPTCNT - GPTCNT + */ #define USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK) + #define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U) #define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U) -/*! GPTMODE +/*! GPTMODE - GPTMODE * 0b0..One Shot Mode * 0b1..Repeat Mode */ #define USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK) + #define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U) #define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U) -/*! GPTRST +/*! GPTRST - GPTRST * 0b0..No action * 0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD */ #define USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK) + #define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U) #define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U) -/*! GPTRUN +/*! GPTRUN - GPTRUN * 0b0..Stop counting * 0b1..Run */ @@ -83295,9 +92826,10 @@ typedef struct { /*! @name SBUSCFG - System Bus Config */ /*! @{ */ + #define USB_SBUSCFG_AHBBRST_MASK (0x7U) #define USB_SBUSCFG_AHBBRST_SHIFT (0U) -/*! AHBBRST +/*! AHBBRST - AHBBRST * 0b000..Incremental burst of unspecified length only * 0b001..INCR4 burst, then single transfer * 0b010..INCR8 burst, INCR4 burst, then single transfer @@ -83312,136 +92844,214 @@ typedef struct { /*! @name CAPLENGTH - Capability Registers Length */ /*! @{ */ + #define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU) #define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U) +/*! CAPLENGTH - CAPLENGTH + */ #define USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK) /*! @} */ /*! @name HCIVERSION - Host Controller Interface Version */ /*! @{ */ + #define USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU) #define USB_HCIVERSION_HCIVERSION_SHIFT (0U) +/*! HCIVERSION - HCIVERSION + */ #define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK) /*! @} */ /*! @name HCSPARAMS - Host Controller Structural Parameters */ /*! @{ */ + #define USB_HCSPARAMS_N_PORTS_MASK (0xFU) #define USB_HCSPARAMS_N_PORTS_SHIFT (0U) +/*! N_PORTS - N_PORTS + */ #define USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK) + #define USB_HCSPARAMS_PPC_MASK (0x10U) #define USB_HCSPARAMS_PPC_SHIFT (4U) +/*! PPC - PPC + */ #define USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK) + #define USB_HCSPARAMS_N_PCC_MASK (0xF00U) #define USB_HCSPARAMS_N_PCC_SHIFT (8U) +/*! N_PCC - N_PCC + */ #define USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK) + #define USB_HCSPARAMS_N_CC_MASK (0xF000U) #define USB_HCSPARAMS_N_CC_SHIFT (12U) -/*! N_CC +/*! N_CC - N_CC * 0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported. * 0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported. */ #define USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK) + #define USB_HCSPARAMS_PI_MASK (0x10000U) #define USB_HCSPARAMS_PI_SHIFT (16U) +/*! PI - PI + */ #define USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK) + #define USB_HCSPARAMS_N_PTT_MASK (0xF00000U) #define USB_HCSPARAMS_N_PTT_SHIFT (20U) +/*! N_PTT - N_PTT + */ #define USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK) + #define USB_HCSPARAMS_N_TT_MASK (0xF000000U) #define USB_HCSPARAMS_N_TT_SHIFT (24U) +/*! N_TT - N_TT + */ #define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK) /*! @} */ /*! @name HCCPARAMS - Host Controller Capability Parameters */ /*! @{ */ + #define USB_HCCPARAMS_ADC_MASK (0x1U) #define USB_HCCPARAMS_ADC_SHIFT (0U) +/*! ADC - ADC + */ #define USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK) + #define USB_HCCPARAMS_PFL_MASK (0x2U) #define USB_HCCPARAMS_PFL_SHIFT (1U) +/*! PFL - PFL + */ #define USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK) + #define USB_HCCPARAMS_ASP_MASK (0x4U) #define USB_HCCPARAMS_ASP_SHIFT (2U) +/*! ASP - ASP + */ #define USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK) + #define USB_HCCPARAMS_IST_MASK (0xF0U) #define USB_HCCPARAMS_IST_SHIFT (4U) +/*! IST - IST + */ #define USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK) + #define USB_HCCPARAMS_EECP_MASK (0xFF00U) #define USB_HCCPARAMS_EECP_SHIFT (8U) +/*! EECP - EECP + */ #define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK) /*! @} */ /*! @name DCIVERSION - Device Controller Interface Version */ /*! @{ */ + #define USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU) #define USB_DCIVERSION_DCIVERSION_SHIFT (0U) +/*! DCIVERSION - DCIVERSION + */ #define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK) /*! @} */ /*! @name DCCPARAMS - Device Controller Capability Parameters */ /*! @{ */ + #define USB_DCCPARAMS_DEN_MASK (0x1FU) #define USB_DCCPARAMS_DEN_SHIFT (0U) +/*! DEN - DEN + */ #define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK) + #define USB_DCCPARAMS_DC_MASK (0x80U) #define USB_DCCPARAMS_DC_SHIFT (7U) +/*! DC - DC + */ #define USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK) + #define USB_DCCPARAMS_HC_MASK (0x100U) #define USB_DCCPARAMS_HC_SHIFT (8U) +/*! HC - HC + */ #define USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK) /*! @} */ /*! @name USBCMD - USB Command Register */ /*! @{ */ + #define USB_USBCMD_RS_MASK (0x1U) #define USB_USBCMD_RS_SHIFT (0U) +/*! RS - RS + */ #define USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK) + #define USB_USBCMD_RST_MASK (0x2U) #define USB_USBCMD_RST_SHIFT (1U) +/*! RST - RST + */ #define USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK) + #define USB_USBCMD_FS_1_MASK (0xCU) #define USB_USBCMD_FS_1_SHIFT (2U) +/*! FS_1 - FS_1 + */ #define USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK) + #define USB_USBCMD_PSE_MASK (0x10U) #define USB_USBCMD_PSE_SHIFT (4U) -/*! PSE +/*! PSE - PSE * 0b0..Do not process the Periodic Schedule * 0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule. */ #define USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK) + #define USB_USBCMD_ASE_MASK (0x20U) #define USB_USBCMD_ASE_SHIFT (5U) -/*! ASE +/*! ASE - ASE * 0b0..Do not process the Asynchronous Schedule. * 0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule. */ #define USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK) + #define USB_USBCMD_IAA_MASK (0x40U) #define USB_USBCMD_IAA_SHIFT (6U) +/*! IAA - IAA + */ #define USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK) + #define USB_USBCMD_ASP_MASK (0x300U) #define USB_USBCMD_ASP_SHIFT (8U) +/*! ASP - ASP + */ #define USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK) + #define USB_USBCMD_ASPE_MASK (0x800U) #define USB_USBCMD_ASPE_SHIFT (11U) +/*! ASPE - ASPE + */ #define USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK) + #define USB_USBCMD_SUTW_MASK (0x2000U) #define USB_USBCMD_SUTW_SHIFT (13U) +/*! SUTW - SUTW + */ #define USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK) + #define USB_USBCMD_ATDTW_MASK (0x4000U) #define USB_USBCMD_ATDTW_SHIFT (14U) +/*! ATDTW - ATDTW + */ #define USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK) + #define USB_USBCMD_FS_2_MASK (0x8000U) #define USB_USBCMD_FS_2_SHIFT (15U) -/*! FS_2 - * 0b0..1024 elements (4096 bytes) Default value - * 0b1..512 elements (2048 bytes) +/*! FS_2 - FS_2 */ #define USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK) + #define USB_USBCMD_ITC_MASK (0xFF0000U) #define USB_USBCMD_ITC_SHIFT (16U) -/*! ITC +/*! ITC - ITC * 0b00000000..Immediate (no threshold) * 0b00000001..1 micro-frame * 0b00000010..2 micro-frames @@ -83456,113 +93066,210 @@ typedef struct { /*! @name USBSTS - USB Status Register */ /*! @{ */ + #define USB_USBSTS_UI_MASK (0x1U) #define USB_USBSTS_UI_SHIFT (0U) +/*! UI - UI + */ #define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK) + #define USB_USBSTS_UEI_MASK (0x2U) #define USB_USBSTS_UEI_SHIFT (1U) +/*! UEI - UEI + */ #define USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK) + #define USB_USBSTS_PCI_MASK (0x4U) #define USB_USBSTS_PCI_SHIFT (2U) +/*! PCI - PCI + */ #define USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK) + #define USB_USBSTS_FRI_MASK (0x8U) #define USB_USBSTS_FRI_SHIFT (3U) +/*! FRI - FRI + */ #define USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK) + #define USB_USBSTS_SEI_MASK (0x10U) #define USB_USBSTS_SEI_SHIFT (4U) +/*! SEI - SEI + */ #define USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK) + #define USB_USBSTS_AAI_MASK (0x20U) #define USB_USBSTS_AAI_SHIFT (5U) +/*! AAI - AAI + */ #define USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK) + #define USB_USBSTS_URI_MASK (0x40U) #define USB_USBSTS_URI_SHIFT (6U) +/*! URI - URI + */ #define USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK) + #define USB_USBSTS_SRI_MASK (0x80U) #define USB_USBSTS_SRI_SHIFT (7U) +/*! SRI - SRI + */ #define USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK) + #define USB_USBSTS_SLI_MASK (0x100U) #define USB_USBSTS_SLI_SHIFT (8U) +/*! SLI - SLI + */ #define USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK) + #define USB_USBSTS_ULPII_MASK (0x400U) #define USB_USBSTS_ULPII_SHIFT (10U) +/*! ULPII - ULPII + */ #define USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK) + #define USB_USBSTS_HCH_MASK (0x1000U) #define USB_USBSTS_HCH_SHIFT (12U) +/*! HCH - HCH + */ #define USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK) + #define USB_USBSTS_RCL_MASK (0x2000U) #define USB_USBSTS_RCL_SHIFT (13U) +/*! RCL - RCL + */ #define USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK) + #define USB_USBSTS_PS_MASK (0x4000U) #define USB_USBSTS_PS_SHIFT (14U) +/*! PS - PS + */ #define USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK) + #define USB_USBSTS_AS_MASK (0x8000U) #define USB_USBSTS_AS_SHIFT (15U) +/*! AS - AS + */ #define USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK) + #define USB_USBSTS_NAKI_MASK (0x10000U) #define USB_USBSTS_NAKI_SHIFT (16U) +/*! NAKI - NAKI + */ #define USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK) + #define USB_USBSTS_TI0_MASK (0x1000000U) #define USB_USBSTS_TI0_SHIFT (24U) +/*! TI0 - TI0 + */ #define USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK) + #define USB_USBSTS_TI1_MASK (0x2000000U) #define USB_USBSTS_TI1_SHIFT (25U) +/*! TI1 - TI1 + */ #define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK) /*! @} */ /*! @name USBINTR - Interrupt Enable Register */ /*! @{ */ + #define USB_USBINTR_UE_MASK (0x1U) #define USB_USBINTR_UE_SHIFT (0U) +/*! UE - UE + */ #define USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK) + #define USB_USBINTR_UEE_MASK (0x2U) #define USB_USBINTR_UEE_SHIFT (1U) +/*! UEE - UEE + */ #define USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK) + #define USB_USBINTR_PCE_MASK (0x4U) #define USB_USBINTR_PCE_SHIFT (2U) +/*! PCE - PCE + */ #define USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK) + #define USB_USBINTR_FRE_MASK (0x8U) #define USB_USBINTR_FRE_SHIFT (3U) +/*! FRE - FRE + */ #define USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK) + #define USB_USBINTR_SEE_MASK (0x10U) #define USB_USBINTR_SEE_SHIFT (4U) +/*! SEE - SEE + */ #define USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK) + #define USB_USBINTR_AAE_MASK (0x20U) #define USB_USBINTR_AAE_SHIFT (5U) +/*! AAE - AAE + */ #define USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK) + #define USB_USBINTR_URE_MASK (0x40U) #define USB_USBINTR_URE_SHIFT (6U) +/*! URE - URE + */ #define USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK) + #define USB_USBINTR_SRE_MASK (0x80U) #define USB_USBINTR_SRE_SHIFT (7U) +/*! SRE - SRE + */ #define USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK) + #define USB_USBINTR_SLE_MASK (0x100U) #define USB_USBINTR_SLE_SHIFT (8U) +/*! SLE - SLE + */ #define USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK) + #define USB_USBINTR_ULPIE_MASK (0x400U) #define USB_USBINTR_ULPIE_SHIFT (10U) +/*! ULPIE - ULPIE + */ #define USB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK) + #define USB_USBINTR_NAKE_MASK (0x10000U) #define USB_USBINTR_NAKE_SHIFT (16U) +/*! NAKE - NAKE + */ #define USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK) + #define USB_USBINTR_UAIE_MASK (0x40000U) #define USB_USBINTR_UAIE_SHIFT (18U) +/*! UAIE - UAIE + */ #define USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK) + #define USB_USBINTR_UPIE_MASK (0x80000U) #define USB_USBINTR_UPIE_SHIFT (19U) +/*! UPIE - UPIE + */ #define USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK) + #define USB_USBINTR_TIE0_MASK (0x1000000U) #define USB_USBINTR_TIE0_SHIFT (24U) +/*! TIE0 - TIE0 + */ #define USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK) + #define USB_USBINTR_TIE1_MASK (0x2000000U) #define USB_USBINTR_TIE1_SHIFT (25U) +/*! TIE1 - TIE1 + */ #define USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK) /*! @} */ /*! @name FRINDEX - USB Frame Index */ /*! @{ */ + #define USB_FRINDEX_FRINDEX_MASK (0x3FFFU) #define USB_FRINDEX_FRINDEX_SHIFT (0U) -/*! FRINDEX +/*! FRINDEX - FRINDEX * 0b00000000000000..(1024) 12 * 0b00000000000001..(512) 11 * 0b00000000000010..(256) 10 @@ -83577,83 +93284,126 @@ typedef struct { /*! @name DEVICEADDR - Device Address */ /*! @{ */ + #define USB_DEVICEADDR_USBADRA_MASK (0x1000000U) #define USB_DEVICEADDR_USBADRA_SHIFT (24U) +/*! USBADRA - USBADRA + */ #define USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK) + #define USB_DEVICEADDR_USBADR_MASK (0xFE000000U) #define USB_DEVICEADDR_USBADR_SHIFT (25U) +/*! USBADR - USBADR + */ #define USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK) /*! @} */ /*! @name PERIODICLISTBASE - Frame List Base Address */ /*! @{ */ + #define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U) #define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U) +/*! BASEADR - BASEADR + */ #define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK) /*! @} */ /*! @name ASYNCLISTADDR - Next Asynch. Address */ /*! @{ */ + #define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U) #define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U) +/*! ASYBASE - ASYBASE + */ #define USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK) /*! @} */ /*! @name ENDPTLISTADDR - Endpoint List Address */ /*! @{ */ + #define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U) #define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U) +/*! EPBASE - EPBASE + */ #define USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK) /*! @} */ /*! @name BURSTSIZE - Programmable Burst Size */ /*! @{ */ + #define USB_BURSTSIZE_RXPBURST_MASK (0xFFU) #define USB_BURSTSIZE_RXPBURST_SHIFT (0U) +/*! RXPBURST - RXPBURST + */ #define USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK) + #define USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U) #define USB_BURSTSIZE_TXPBURST_SHIFT (8U) +/*! TXPBURST - TXPBURST + */ #define USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK) /*! @} */ /*! @name TXFILLTUNING - TX FIFO Fill Tuning */ /*! @{ */ + #define USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU) #define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U) +/*! TXSCHOH - TXSCHOH + */ #define USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK) + #define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U) #define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U) +/*! TXSCHHEALTH - TXSCHHEALTH + */ #define USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK) + #define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U) #define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U) +/*! TXFIFOTHRES - TXFIFOTHRES + */ #define USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK) /*! @} */ /*! @name ENDPTNAK - Endpoint NAK */ /*! @{ */ + #define USB_ENDPTNAK_EPRN_MASK (0xFFU) #define USB_ENDPTNAK_EPRN_SHIFT (0U) +/*! EPRN - EPRN + */ #define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK) + #define USB_ENDPTNAK_EPTN_MASK (0xFF0000U) #define USB_ENDPTNAK_EPTN_SHIFT (16U) +/*! EPTN - EPTN + */ #define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK) /*! @} */ /*! @name ENDPTNAKEN - Endpoint NAK Enable */ /*! @{ */ + #define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU) #define USB_ENDPTNAKEN_EPRNE_SHIFT (0U) +/*! EPRNE - EPRNE + */ #define USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK) + #define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U) #define USB_ENDPTNAKEN_EPTNE_SHIFT (16U) +/*! EPTNE - EPTNE + */ #define USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK) /*! @} */ /*! @name CONFIGFLAG - Configure Flag Register */ /*! @{ */ + #define USB_CONFIGFLAG_CF_MASK (0x1U) #define USB_CONFIGFLAG_CF_SHIFT (0U) -/*! CF +/*! CF - CF * 0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller. * 0b1..Port routing control logic default-routes all ports to this host controller. */ @@ -83662,67 +93412,104 @@ typedef struct { /*! @name PORTSC1 - Port Status & Control */ /*! @{ */ + #define USB_PORTSC1_CCS_MASK (0x1U) #define USB_PORTSC1_CCS_SHIFT (0U) +/*! CCS - CCS + */ #define USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK) + #define USB_PORTSC1_CSC_MASK (0x2U) #define USB_PORTSC1_CSC_SHIFT (1U) +/*! CSC - CSC + */ #define USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK) + #define USB_PORTSC1_PE_MASK (0x4U) #define USB_PORTSC1_PE_SHIFT (2U) +/*! PE - PE + */ #define USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK) + #define USB_PORTSC1_PEC_MASK (0x8U) #define USB_PORTSC1_PEC_SHIFT (3U) +/*! PEC - PEC + */ #define USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK) + #define USB_PORTSC1_OCA_MASK (0x10U) #define USB_PORTSC1_OCA_SHIFT (4U) -/*! OCA +/*! OCA - OCA * 0b1..This port currently has an over-current condition * 0b0..This port does not have an over-current condition. */ #define USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK) + #define USB_PORTSC1_OCC_MASK (0x20U) #define USB_PORTSC1_OCC_SHIFT (5U) +/*! OCC - OCC + */ #define USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK) + #define USB_PORTSC1_FPR_MASK (0x40U) #define USB_PORTSC1_FPR_SHIFT (6U) +/*! FPR - FPR + */ #define USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK) + #define USB_PORTSC1_SUSP_MASK (0x80U) #define USB_PORTSC1_SUSP_SHIFT (7U) +/*! SUSP - SUSP + */ #define USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK) + #define USB_PORTSC1_PR_MASK (0x100U) #define USB_PORTSC1_PR_SHIFT (8U) +/*! PR - PR + */ #define USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK) + #define USB_PORTSC1_HSP_MASK (0x200U) #define USB_PORTSC1_HSP_SHIFT (9U) +/*! HSP - HSP + */ #define USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK) + #define USB_PORTSC1_LS_MASK (0xC00U) #define USB_PORTSC1_LS_SHIFT (10U) -/*! LS +/*! LS - LS * 0b00..SE0 * 0b10..J-state * 0b01..K-state * 0b11..Undefined */ #define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK) + #define USB_PORTSC1_PP_MASK (0x1000U) #define USB_PORTSC1_PP_SHIFT (12U) +/*! PP - PP + */ #define USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK) + #define USB_PORTSC1_PO_MASK (0x2000U) #define USB_PORTSC1_PO_SHIFT (13U) +/*! PO - PO + */ #define USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK) + #define USB_PORTSC1_PIC_MASK (0xC000U) #define USB_PORTSC1_PIC_SHIFT (14U) -/*! PIC +/*! PIC - PIC * 0b00..Port indicators are off * 0b01..Amber * 0b10..Green * 0b11..Undefined */ #define USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK) + #define USB_PORTSC1_PTC_MASK (0xF0000U) #define USB_PORTSC1_PTC_SHIFT (16U) -/*! PTC +/*! PTC - PTC * 0b0000..TEST_MODE_DISABLE * 0b0001..J_STATE * 0b0010..K_STATE @@ -83731,276 +93518,464 @@ typedef struct { * 0b0101..FORCE_ENABLE_HS * 0b0110..FORCE_ENABLE_FS * 0b0111..FORCE_ENABLE_LS + * 0b1000-0b1111..Reserved */ #define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK) + #define USB_PORTSC1_WKCN_MASK (0x100000U) #define USB_PORTSC1_WKCN_SHIFT (20U) +/*! WKCN - WKCN + */ #define USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK) + #define USB_PORTSC1_WKDC_MASK (0x200000U) #define USB_PORTSC1_WKDC_SHIFT (21U) +/*! WKDC - WKDC + */ #define USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK) + #define USB_PORTSC1_WKOC_MASK (0x400000U) #define USB_PORTSC1_WKOC_SHIFT (22U) +/*! WKOC - WKOC + */ #define USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK) + #define USB_PORTSC1_PHCD_MASK (0x800000U) #define USB_PORTSC1_PHCD_SHIFT (23U) -/*! PHCD +/*! PHCD - PHCD * 0b1..Disable PHY clock * 0b0..Enable PHY clock */ #define USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK) + #define USB_PORTSC1_PFSC_MASK (0x1000000U) #define USB_PORTSC1_PFSC_SHIFT (24U) -/*! PFSC +/*! PFSC - PFSC * 0b1..Forced to full speed * 0b0..Normal operation */ #define USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK) + #define USB_PORTSC1_PTS_2_MASK (0x2000000U) #define USB_PORTSC1_PTS_2_SHIFT (25U) +/*! PTS_2 - PTS_2 + */ #define USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK) + #define USB_PORTSC1_PSPD_MASK (0xC000000U) #define USB_PORTSC1_PSPD_SHIFT (26U) -/*! PSPD +/*! PSPD - PSPD * 0b00..Full Speed * 0b01..Low Speed * 0b10..High Speed * 0b11..Undefined */ #define USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK) + #define USB_PORTSC1_PTW_MASK (0x10000000U) #define USB_PORTSC1_PTW_SHIFT (28U) -/*! PTW +/*! PTW - PTW * 0b0..Select the 8-bit UTMI interface [60MHz] * 0b1..Select the 16-bit UTMI interface [30MHz] */ #define USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK) + #define USB_PORTSC1_STS_MASK (0x20000000U) #define USB_PORTSC1_STS_SHIFT (29U) +/*! STS - STS + */ #define USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK) + #define USB_PORTSC1_PTS_1_MASK (0xC0000000U) #define USB_PORTSC1_PTS_1_SHIFT (30U) +/*! PTS_1 - PTS_1 + */ #define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK) /*! @} */ /*! @name OTGSC - On-The-Go Status & control */ /*! @{ */ + #define USB_OTGSC_VD_MASK (0x1U) #define USB_OTGSC_VD_SHIFT (0U) +/*! VD - VD + */ #define USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK) + #define USB_OTGSC_VC_MASK (0x2U) #define USB_OTGSC_VC_SHIFT (1U) +/*! VC - VC + */ #define USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK) + #define USB_OTGSC_OT_MASK (0x8U) #define USB_OTGSC_OT_SHIFT (3U) +/*! OT - OT + */ #define USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK) + #define USB_OTGSC_DP_MASK (0x10U) #define USB_OTGSC_DP_SHIFT (4U) +/*! DP - DP + */ #define USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK) + #define USB_OTGSC_IDPU_MASK (0x20U) #define USB_OTGSC_IDPU_SHIFT (5U) +/*! IDPU - IDPU + */ #define USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK) + #define USB_OTGSC_ID_MASK (0x100U) #define USB_OTGSC_ID_SHIFT (8U) +/*! ID - ID + */ #define USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK) + #define USB_OTGSC_AVV_MASK (0x200U) #define USB_OTGSC_AVV_SHIFT (9U) +/*! AVV - AVV + */ #define USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK) + #define USB_OTGSC_ASV_MASK (0x400U) #define USB_OTGSC_ASV_SHIFT (10U) +/*! ASV - ASV + */ #define USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK) + #define USB_OTGSC_BSV_MASK (0x800U) #define USB_OTGSC_BSV_SHIFT (11U) +/*! BSV - BSV + */ #define USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK) + #define USB_OTGSC_BSE_MASK (0x1000U) #define USB_OTGSC_BSE_SHIFT (12U) +/*! BSE - BSE + */ #define USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK) + #define USB_OTGSC_TOG_1MS_MASK (0x2000U) #define USB_OTGSC_TOG_1MS_SHIFT (13U) +/*! TOG_1MS - TOG_1MS + */ #define USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK) + #define USB_OTGSC_DPS_MASK (0x4000U) #define USB_OTGSC_DPS_SHIFT (14U) +/*! DPS - DPS + */ #define USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK) + #define USB_OTGSC_IDIS_MASK (0x10000U) #define USB_OTGSC_IDIS_SHIFT (16U) +/*! IDIS - IDIS + */ #define USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK) + #define USB_OTGSC_AVVIS_MASK (0x20000U) #define USB_OTGSC_AVVIS_SHIFT (17U) +/*! AVVIS - AVVIS + */ #define USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK) + #define USB_OTGSC_ASVIS_MASK (0x40000U) #define USB_OTGSC_ASVIS_SHIFT (18U) +/*! ASVIS - ASVIS + */ #define USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK) + #define USB_OTGSC_BSVIS_MASK (0x80000U) #define USB_OTGSC_BSVIS_SHIFT (19U) +/*! BSVIS - BSVIS + */ #define USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK) + #define USB_OTGSC_BSEIS_MASK (0x100000U) #define USB_OTGSC_BSEIS_SHIFT (20U) +/*! BSEIS - BSEIS + */ #define USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK) + #define USB_OTGSC_STATUS_1MS_MASK (0x200000U) #define USB_OTGSC_STATUS_1MS_SHIFT (21U) +/*! STATUS_1MS - STATUS_1MS + */ #define USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK) + #define USB_OTGSC_DPIS_MASK (0x400000U) #define USB_OTGSC_DPIS_SHIFT (22U) +/*! DPIS - DPIS + */ #define USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK) + #define USB_OTGSC_IDIE_MASK (0x1000000U) #define USB_OTGSC_IDIE_SHIFT (24U) +/*! IDIE - IDIE + */ #define USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK) + #define USB_OTGSC_AVVIE_MASK (0x2000000U) #define USB_OTGSC_AVVIE_SHIFT (25U) +/*! AVVIE - AVVIE + */ #define USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK) + #define USB_OTGSC_ASVIE_MASK (0x4000000U) #define USB_OTGSC_ASVIE_SHIFT (26U) +/*! ASVIE - ASVIE + */ #define USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK) + #define USB_OTGSC_BSVIE_MASK (0x8000000U) #define USB_OTGSC_BSVIE_SHIFT (27U) +/*! BSVIE - BSVIE + */ #define USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK) + #define USB_OTGSC_BSEIE_MASK (0x10000000U) #define USB_OTGSC_BSEIE_SHIFT (28U) +/*! BSEIE - BSEIE + */ #define USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK) + #define USB_OTGSC_EN_1MS_MASK (0x20000000U) #define USB_OTGSC_EN_1MS_SHIFT (29U) +/*! EN_1MS - EN_1MS + */ #define USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK) + #define USB_OTGSC_DPIE_MASK (0x40000000U) #define USB_OTGSC_DPIE_SHIFT (30U) +/*! DPIE - DPIE + */ #define USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK) /*! @} */ /*! @name USBMODE - USB Device Mode */ /*! @{ */ + #define USB_USBMODE_CM_MASK (0x3U) #define USB_USBMODE_CM_SHIFT (0U) -/*! CM +/*! CM - CM * 0b00..Idle [Default for combination host/device] * 0b01..Reserved * 0b10..Device Controller [Default for device only controller] * 0b11..Host Controller [Default for host only controller] */ #define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK) + #define USB_USBMODE_ES_MASK (0x4U) #define USB_USBMODE_ES_SHIFT (2U) -/*! ES +/*! ES - ES * 0b0..Little Endian [Default] * 0b1..Big Endian */ #define USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK) + #define USB_USBMODE_SLOM_MASK (0x8U) #define USB_USBMODE_SLOM_SHIFT (3U) -/*! SLOM +/*! SLOM - SLOM * 0b0..Setup Lockouts On (default); - * 0b1..Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMDUSB Command Register . + * 0b1..Setup Lockouts Off */ #define USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK) + #define USB_USBMODE_SDIS_MASK (0x10U) #define USB_USBMODE_SDIS_SHIFT (4U) +/*! SDIS - SDIS + */ #define USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK) /*! @} */ /*! @name ENDPTSETUPSTAT - Endpoint Setup Status */ /*! @{ */ + #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU) #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U) +/*! ENDPTSETUPSTAT - ENDPTSETUPSTAT + */ #define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK) /*! @} */ /*! @name ENDPTPRIME - Endpoint Prime */ /*! @{ */ + #define USB_ENDPTPRIME_PERB_MASK (0xFFU) #define USB_ENDPTPRIME_PERB_SHIFT (0U) +/*! PERB - PERB + */ #define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK) + #define USB_ENDPTPRIME_PETB_MASK (0xFF0000U) #define USB_ENDPTPRIME_PETB_SHIFT (16U) +/*! PETB - PETB + */ #define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK) /*! @} */ /*! @name ENDPTFLUSH - Endpoint Flush */ /*! @{ */ + #define USB_ENDPTFLUSH_FERB_MASK (0xFFU) #define USB_ENDPTFLUSH_FERB_SHIFT (0U) +/*! FERB - FERB + */ #define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK) + #define USB_ENDPTFLUSH_FETB_MASK (0xFF0000U) #define USB_ENDPTFLUSH_FETB_SHIFT (16U) +/*! FETB - FETB + */ #define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK) /*! @} */ /*! @name ENDPTSTAT - Endpoint Status */ /*! @{ */ + #define USB_ENDPTSTAT_ERBR_MASK (0xFFU) #define USB_ENDPTSTAT_ERBR_SHIFT (0U) +/*! ERBR - ERBR + */ #define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK) + #define USB_ENDPTSTAT_ETBR_MASK (0xFF0000U) #define USB_ENDPTSTAT_ETBR_SHIFT (16U) +/*! ETBR - ETBR + */ #define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK) /*! @} */ /*! @name ENDPTCOMPLETE - Endpoint Complete */ /*! @{ */ + #define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU) #define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U) +/*! ERCE - ERCE + */ #define USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK) + #define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U) #define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U) +/*! ETCE - ETCE + */ #define USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK) /*! @} */ /*! @name ENDPTCTRL0 - Endpoint Control0 */ /*! @{ */ + #define USB_ENDPTCTRL0_RXS_MASK (0x1U) #define USB_ENDPTCTRL0_RXS_SHIFT (0U) +/*! RXS - RXS + */ #define USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK) + #define USB_ENDPTCTRL0_RXT_MASK (0xCU) #define USB_ENDPTCTRL0_RXT_SHIFT (2U) +/*! RXT - RXT + */ #define USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK) + #define USB_ENDPTCTRL0_RXE_MASK (0x80U) #define USB_ENDPTCTRL0_RXE_SHIFT (7U) +/*! RXE - RXE + */ #define USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK) + #define USB_ENDPTCTRL0_TXS_MASK (0x10000U) #define USB_ENDPTCTRL0_TXS_SHIFT (16U) +/*! TXS - TXS + */ #define USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK) + #define USB_ENDPTCTRL0_TXT_MASK (0xC0000U) #define USB_ENDPTCTRL0_TXT_SHIFT (18U) +/*! TXT - TXT + */ #define USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK) + #define USB_ENDPTCTRL0_TXE_MASK (0x800000U) #define USB_ENDPTCTRL0_TXE_SHIFT (23U) +/*! TXE - TXE + */ #define USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK) /*! @} */ /*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */ /*! @{ */ + #define USB_ENDPTCTRL_RXS_MASK (0x1U) #define USB_ENDPTCTRL_RXS_SHIFT (0U) +/*! RXS - RXS + */ #define USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK) + #define USB_ENDPTCTRL_RXD_MASK (0x2U) #define USB_ENDPTCTRL_RXD_SHIFT (1U) +/*! RXD - RXD + */ #define USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK) + #define USB_ENDPTCTRL_RXT_MASK (0xCU) #define USB_ENDPTCTRL_RXT_SHIFT (2U) +/*! RXT - RXT + */ #define USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK) + #define USB_ENDPTCTRL_RXI_MASK (0x20U) #define USB_ENDPTCTRL_RXI_SHIFT (5U) +/*! RXI - RXI + */ #define USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK) + #define USB_ENDPTCTRL_RXR_MASK (0x40U) #define USB_ENDPTCTRL_RXR_SHIFT (6U) +/*! RXR - RXR + */ #define USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK) + #define USB_ENDPTCTRL_RXE_MASK (0x80U) #define USB_ENDPTCTRL_RXE_SHIFT (7U) +/*! RXE - RXE + */ #define USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK) + #define USB_ENDPTCTRL_TXS_MASK (0x10000U) #define USB_ENDPTCTRL_TXS_SHIFT (16U) +/*! TXS - TXS + */ #define USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK) + #define USB_ENDPTCTRL_TXD_MASK (0x20000U) #define USB_ENDPTCTRL_TXD_SHIFT (17U) +/*! TXD - TXD + */ #define USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK) + #define USB_ENDPTCTRL_TXT_MASK (0xC0000U) #define USB_ENDPTCTRL_TXT_SHIFT (18U) +/*! TXT - TXT + */ #define USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK) + #define USB_ENDPTCTRL_TXI_MASK (0x200000U) #define USB_ENDPTCTRL_TXI_SHIFT (21U) +/*! TXI - TXI + */ #define USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK) + #define USB_ENDPTCTRL_TXR_MASK (0x400000U) #define USB_ENDPTCTRL_TXR_SHIFT (22U) +/*! TXR - TXR + */ #define USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK) + #define USB_ENDPTCTRL_TXE_MASK (0x800000U) #define USB_ENDPTCTRL_TXE_SHIFT (23U) +/*! TXE - TXE + */ #define USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK) /*! @} */ @@ -84014,20 +93989,18 @@ typedef struct { /* USB - Peripheral instance base addresses */ -/** Peripheral USB1 base address */ -#define USB1_BASE (0x40430000u) -/** Peripheral USB1 base pointer */ -#define USB1 ((USB_Type *)USB1_BASE) -/** Peripheral USB2 base address */ -#define USB2_BASE (0x4042C000u) -/** Peripheral USB2 base pointer */ -#define USB2 ((USB_Type *)USB2_BASE) +/** Peripheral USB__USB_OTG1 base address */ +#define USB__USB_OTG1_BASE (0x40430000u) +/** Peripheral USB__USB_OTG1 base pointer */ +#define USB__USB_OTG1 ((USB_Type *)USB__USB_OTG1_BASE) +/** Peripheral USB__USB_OTG2 base address */ +#define USB__USB_OTG2_BASE (0x4042C000u) +/** Peripheral USB__USB_OTG2 base pointer */ +#define USB__USB_OTG2 ((USB_Type *)USB__USB_OTG2_BASE) /** Array initializer of USB peripheral base addresses */ -#define USB_BASE_ADDRS { 0u, USB1_BASE, USB2_BASE } +#define USB_BASE_ADDRS { 0u, USB__USB_OTG1_BASE, USB__USB_OTG2_BASE } /** Array initializer of USB peripheral base pointers */ -#define USB_BASE_PTRS { (USB_Type *)0u, USB1, USB2 } -/** Interrupt vectors for the USB peripheral type */ -#define USB_IRQS { NotAvail_IRQn, USB_OTG1_IRQn, USB_OTG2_IRQn } +#define USB_BASE_PTRS { (USB_Type *)0u, USB__USB_OTG1, USB__USB_OTG2 } /* Backward compatibility */ #define GPTIMER0CTL GPTIMER0CTRL #define GPTIMER1CTL GPTIMER1CTRL @@ -84595,7 +94568,7 @@ typedef struct { #define USBHS_EPCR_TXE(x) USB_ENDPTCTRL_TXE(x) #define USBHS_EPCR_COUNT USB_ENDPTCTRL_COUNT #define USBHS_Type USB_Type -#define USBHS_BASE_ADDRS { USB1_BASE, USB2_BASE } +#define USBHS_BASE_ADDRS { USB__USB_OTG1_BASE, USB__USB_OTG2_BASE } #define USBHS_IRQS { USB_OTG1_IRQn, USB_OTG2_IRQn } #define USBHS_IRQHandler USB_OTG1_IRQHandler @@ -84639,6 +94612,7 @@ typedef struct { /*! @name CONTROL - Control register */ /*! @{ */ + #define USBHSDCD_CONTROL_IACK_MASK (0x1U) #define USBHSDCD_CONTROL_IACK_SHIFT (0U) /*! IACK - Interrupt Acknowledge @@ -84646,6 +94620,7 @@ typedef struct { * 0b1..Clear the IF bit (interrupt flag). */ #define USBHSDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IACK_SHIFT)) & USBHSDCD_CONTROL_IACK_MASK) + #define USBHSDCD_CONTROL_IF_MASK (0x100U) #define USBHSDCD_CONTROL_IF_SHIFT (8U) /*! IF - Interrupt Flag @@ -84653,6 +94628,7 @@ typedef struct { * 0b1..An interrupt is pending. */ #define USBHSDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IF_SHIFT)) & USBHSDCD_CONTROL_IF_MASK) + #define USBHSDCD_CONTROL_IE_MASK (0x10000U) #define USBHSDCD_CONTROL_IE_SHIFT (16U) /*! IE - Interrupt Enable @@ -84660,6 +94636,7 @@ typedef struct { * 0b1..Enable interrupts to the system. */ #define USBHSDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IE_SHIFT)) & USBHSDCD_CONTROL_IE_MASK) + #define USBHSDCD_CONTROL_BC12_MASK (0x20000U) #define USBHSDCD_CONTROL_BC12_SHIFT (17U) /*! BC12 - BC12 @@ -84667,6 +94644,7 @@ typedef struct { * 0b1..Compatible with BC1.2 */ #define USBHSDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_BC12_SHIFT)) & USBHSDCD_CONTROL_BC12_MASK) + #define USBHSDCD_CONTROL_START_MASK (0x1000000U) #define USBHSDCD_CONTROL_START_SHIFT (24U) /*! START - Start Change Detection Sequence @@ -84674,6 +94652,7 @@ typedef struct { * 0b1..Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect. */ #define USBHSDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_START_SHIFT)) & USBHSDCD_CONTROL_START_MASK) + #define USBHSDCD_CONTROL_SR_MASK (0x2000000U) #define USBHSDCD_CONTROL_SR_SHIFT (25U) /*! SR - Software Reset @@ -84685,6 +94664,7 @@ typedef struct { /*! @name CLOCK - Clock register */ /*! @{ */ + #define USBHSDCD_CLOCK_CLOCK_UNIT_MASK (0x1U) #define USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT (0U) /*! CLOCK_UNIT - Unit of Measurement Encoding for Clock Speed @@ -84692,6 +94672,7 @@ typedef struct { * 0b1..MHz Speed (between 1 MHz and 1023 MHz) */ #define USBHSDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBHSDCD_CLOCK_CLOCK_UNIT_MASK) + #define USBHSDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU) #define USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT (2U) /*! CLOCK_SPEED - Numerical Value of Clock Speed in Binary @@ -84701,6 +94682,7 @@ typedef struct { /*! @name STATUS - Status register */ /*! @{ */ + #define USBHSDCD_STATUS_SEQ_RES_MASK (0x30000U) #define USBHSDCD_STATUS_SEQ_RES_SHIFT (16U) /*! SEQ_RES - Charger Detection Sequence Results @@ -84712,6 +94694,7 @@ typedef struct { * 0b11..Attached to a DCP. */ #define USBHSDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_RES_SHIFT)) & USBHSDCD_STATUS_SEQ_RES_MASK) + #define USBHSDCD_STATUS_SEQ_STAT_MASK (0xC0000U) #define USBHSDCD_STATUS_SEQ_STAT_SHIFT (18U) /*! SEQ_STAT - Charger Detection Sequence Status @@ -84721,6 +94704,7 @@ typedef struct { * 0b11..Charger type detection is complete. */ #define USBHSDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_STAT_SHIFT)) & USBHSDCD_STATUS_SEQ_STAT_MASK) + #define USBHSDCD_STATUS_ERR_MASK (0x100000U) #define USBHSDCD_STATUS_ERR_SHIFT (20U) /*! ERR - Error Flag @@ -84728,13 +94712,15 @@ typedef struct { * 0b1..Error in the detection sequence. See the SEQ_STAT field to determine the phase in which the error occurred. */ #define USBHSDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ERR_SHIFT)) & USBHSDCD_STATUS_ERR_MASK) + #define USBHSDCD_STATUS_TO_MASK (0x200000U) #define USBHSDCD_STATUS_TO_SHIFT (21U) /*! TO - Timeout Flag - * 0b0..The detection sequence has not been running for over 1 s. + * 0b0..The detection sequence has not been running for over 1s. * 0b1..It has been over 1 s since the data pin contact was detected and debounced. */ #define USBHSDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TO_SHIFT)) & USBHSDCD_STATUS_TO_MASK) + #define USBHSDCD_STATUS_ACTIVE_MASK (0x400000U) #define USBHSDCD_STATUS_ACTIVE_SHIFT (22U) /*! ACTIVE - Active Status Indicator @@ -84746,6 +94732,7 @@ typedef struct { /*! @name SIGNAL_OVERRIDE - Signal Override Register */ /*! @{ */ + #define USBHSDCD_SIGNAL_OVERRIDE_PS_MASK (0x3U) #define USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT (0U) /*! PS - Phase Selection @@ -84760,56 +94747,71 @@ typedef struct { /*! @name TIMER0 - TIMER0 register */ /*! @{ */ + #define USBHSDCD_TIMER0_TUNITCON_MASK (0xFFFU) #define USBHSDCD_TIMER0_TUNITCON_SHIFT (0U) /*! TUNITCON - Unit Connection Timer Elapse (in ms) */ #define USBHSDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TUNITCON_SHIFT)) & USBHSDCD_TIMER0_TUNITCON_MASK) + #define USBHSDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U) #define USBHSDCD_TIMER0_TSEQ_INIT_SHIFT (16U) /*! TSEQ_INIT - Sequence Initiation Time + * 0b0000000000-0b1111111111..0ms - 1023ms */ #define USBHSDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBHSDCD_TIMER0_TSEQ_INIT_MASK) /*! @} */ /*! @name TIMER1 - TIMER1 register */ /*! @{ */ + #define USBHSDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU) #define USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT (0U) /*! TVDPSRC_ON - Time Period Comparator Enabled + * 0b0000000001-0b1111111111..1ms - 1023ms */ #define USBHSDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBHSDCD_TIMER1_TVDPSRC_ON_MASK) + #define USBHSDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U) #define USBHSDCD_TIMER1_TDCD_DBNC_SHIFT (16U) /*! TDCD_DBNC - Time Period to Debounce D+ Signal + * 0b0000000001-0b1111111111..1ms - 1023ms */ #define USBHSDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBHSDCD_TIMER1_TDCD_DBNC_MASK) /*! @} */ /*! @name TIMER2_BC11 - TIMER2_BC11 register */ /*! @{ */ + #define USBHSDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU) #define USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U) /*! CHECK_DM - Time Before Check of D- Line + * 0b0001-0b1111..1ms - 15ms */ #define USBHSDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBHSDCD_TIMER2_BC11_CHECK_DM_MASK) + #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U) #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U) /*! TVDPSRC_CON - Time Period Before Enabling D+ Pullup + * 0b0000000001-0b1111111111..1ms - 1023ms */ #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK) /*! @} */ /*! @name TIMER2_BC12 - TIMER2_BC12 register */ /*! @{ */ + #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU) #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U) /*! TVDMSRC_ON - TVDMSRC_ON + * 0b0000000000-0b0000101000..0ms - 40ms */ #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK) + #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U) #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U) /*! TWAIT_AFTER_PRD - TWAIT_AFTER_PRD + * 0b0000000001-0b1111111111..1ms - 1023ms */ #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK) /*! @} */ @@ -84850,8 +94852,10 @@ typedef struct { /** USBNC - Register Layout Typedef */ typedef struct { - uint8_t RESERVED_0[512]; - __IO uint32_t USB_OTGn_CTRL; /**< USB OTG1 Control Register, offset: 0x200 */ + __IO uint32_t CTRL1; /**< USB OTG Control 1 Register, offset: 0x0 */ + __IO uint32_t CTRL2; /**< USB OTG Control 2 Register, offset: 0x4 */ + uint8_t RESERVED_0[8]; + __IO uint32_t HSIC_CTRL; /**< USB Host HSIC Control Register, offset: 0x10 */ } USBNC_Type; /* ---------------------------------------------------------------------------- @@ -84863,78 +94867,151 @@ typedef struct { * @{ */ -/*! @name USB_OTGn_CTRL - USB OTG1 Control Register */ +/*! @name CTRL1 - USB OTG Control 1 Register */ /*! @{ */ -#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK (0x80U) -#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT (7U) -/*! OVER_CUR_DIS + +#define USBNC_CTRL1_OVER_CUR_DIS_MASK (0x80U) +#define USBNC_CTRL1_OVER_CUR_DIS_SHIFT (7U) +/*! OVER_CUR_DIS - OVER_CUR_DIS * 0b1..Disables overcurrent detection * 0b0..Enables overcurrent detection */ -#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK) -#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK (0x100U) -#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT (8U) -/*! OVER_CUR_POL +#define USBNC_CTRL1_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_DIS_SHIFT)) & USBNC_CTRL1_OVER_CUR_DIS_MASK) + +#define USBNC_CTRL1_OVER_CUR_POL_MASK (0x100U) +#define USBNC_CTRL1_OVER_CUR_POL_SHIFT (8U) +/*! OVER_CUR_POL - OVER_CUR_POL * 0b1..Low active (low on this signal represents an overcurrent condition) * 0b0..High active (high on this signal represents an overcurrent condition) */ -#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK) -#define USBNC_USB_OTGn_CTRL_PWR_POL_MASK (0x200U) -#define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT (9U) -/*! PWR_POL +#define USBNC_CTRL1_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_POL_SHIFT)) & USBNC_CTRL1_OVER_CUR_POL_MASK) + +#define USBNC_CTRL1_PWR_POL_MASK (0x200U) +#define USBNC_CTRL1_PWR_POL_SHIFT (9U) +/*! PWR_POL - PWR_POL * 0b1..PMIC Power Pin is High active. * 0b0..PMIC Power Pin is Low active. */ -#define USBNC_USB_OTGn_CTRL_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT)) & USBNC_USB_OTGn_CTRL_PWR_POL_MASK) -#define USBNC_USB_OTGn_CTRL_WIE_MASK (0x400U) -#define USBNC_USB_OTGn_CTRL_WIE_SHIFT (10U) -/*! WIE +#define USBNC_CTRL1_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_PWR_POL_SHIFT)) & USBNC_CTRL1_PWR_POL_MASK) + +#define USBNC_CTRL1_WIE_MASK (0x400U) +#define USBNC_CTRL1_WIE_SHIFT (10U) +/*! WIE - WIE * 0b1..Interrupt Enabled * 0b0..Interrupt Disabled */ -#define USBNC_USB_OTGn_CTRL_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIE_SHIFT)) & USBNC_USB_OTGn_CTRL_WIE_MASK) -#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK (0x4000U) -#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT (14U) -/*! WKUP_SW_EN +#define USBNC_CTRL1_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIE_SHIFT)) & USBNC_CTRL1_WIE_MASK) + +#define USBNC_CTRL1_WKUP_SW_EN_MASK (0x4000U) +#define USBNC_CTRL1_WKUP_SW_EN_SHIFT (14U) +/*! WKUP_SW_EN - WKUP_SW_EN * 0b1..Enable * 0b0..Disable */ -#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK) -#define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK (0x8000U) -#define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT (15U) -/*! WKUP_SW +#define USBNC_CTRL1_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_EN_SHIFT)) & USBNC_CTRL1_WKUP_SW_EN_MASK) + +#define USBNC_CTRL1_WKUP_SW_MASK (0x8000U) +#define USBNC_CTRL1_WKUP_SW_SHIFT (15U) +/*! WKUP_SW - WKUP_SW * 0b1..Force wake-up * 0b0..Inactive */ -#define USBNC_USB_OTGn_CTRL_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_SW_MASK) -#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK (0x10000U) -#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT (16U) -/*! WKUP_ID_EN +#define USBNC_CTRL1_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_SHIFT)) & USBNC_CTRL1_WKUP_SW_MASK) + +#define USBNC_CTRL1_WKUP_ID_EN_MASK (0x10000U) +#define USBNC_CTRL1_WKUP_ID_EN_SHIFT (16U) +/*! WKUP_ID_EN - WKUP_ID_EN * 0b1..Enable * 0b0..Disable */ -#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK) -#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK (0x20000U) -#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT (17U) -/*! WKUP_VBUS_EN +#define USBNC_CTRL1_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_ID_EN_SHIFT)) & USBNC_CTRL1_WKUP_ID_EN_MASK) + +#define USBNC_CTRL1_WKUP_VBUS_EN_MASK (0x20000U) +#define USBNC_CTRL1_WKUP_VBUS_EN_SHIFT (17U) +/*! WKUP_VBUS_EN - WKUP_VBUS_EN * 0b1..Enable * 0b0..Disable */ -#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK) -#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK (0x20000000U) -#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT (29U) -/*! WKUP_DPDM_EN +#define USBNC_CTRL1_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_VBUS_EN_SHIFT)) & USBNC_CTRL1_WKUP_VBUS_EN_MASK) + +#define USBNC_CTRL1_WKUP_DPDM_EN_MASK (0x20000000U) +#define USBNC_CTRL1_WKUP_DPDM_EN_SHIFT (29U) +/*! WKUP_DPDM_EN - Wake-up on DPDM change enable * 0b1..(Default) DPDM changes wake-up to be enabled, it is for device only. * 0b0..DPDM changes wake-up to be disabled only when VBUS is 0. */ -#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT)) & USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK) -#define USBNC_USB_OTGn_CTRL_WIR_MASK (0x80000000U) -#define USBNC_USB_OTGn_CTRL_WIR_SHIFT (31U) -/*! WIR +#define USBNC_CTRL1_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_DPDM_EN_SHIFT)) & USBNC_CTRL1_WKUP_DPDM_EN_MASK) + +#define USBNC_CTRL1_WIR_MASK (0x80000000U) +#define USBNC_CTRL1_WIR_SHIFT (31U) +/*! WIR - WIR * 0b1..Wake-up Interrupt Request received * 0b0..No wake-up interrupt request received */ -#define USBNC_USB_OTGn_CTRL_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_USB_OTGn_CTRL_WIR_SHIFT)) & USBNC_USB_OTGn_CTRL_WIR_MASK) +#define USBNC_CTRL1_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIR_SHIFT)) & USBNC_CTRL1_WIR_MASK) +/*! @} */ + +/*! @name CTRL2 - USB OTG Control 2 Register */ +/*! @{ */ + +#define USBNC_CTRL2_VBUS_SOURCE_SEL_MASK (0x3U) +#define USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT (0U) +/*! VBUS_SOURCE_SEL - VBUS_SOURCE_SEL + * 0b00..vbus_valid + * 0b01..sess_valid + * 0b10..sess_valid + * 0b11..sess_valid + */ +#define USBNC_CTRL2_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT)) & USBNC_CTRL2_VBUS_SOURCE_SEL_MASK) + +#define USBNC_CTRL2_AUTURESUME_EN_MASK (0x4U) +#define USBNC_CTRL2_AUTURESUME_EN_SHIFT (2U) +/*! AUTURESUME_EN - Auto Resume Enable + * 0b0..Default + */ +#define USBNC_CTRL2_AUTURESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_AUTURESUME_EN_SHIFT)) & USBNC_CTRL2_AUTURESUME_EN_MASK) + +#define USBNC_CTRL2_LOWSPEED_EN_MASK (0x8U) +#define USBNC_CTRL2_LOWSPEED_EN_SHIFT (3U) +/*! LOWSPEED_EN - LOWSPEED_EN + * 0b0..Default + */ +#define USBNC_CTRL2_LOWSPEED_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_LOWSPEED_EN_SHIFT)) & USBNC_CTRL2_LOWSPEED_EN_MASK) + +#define USBNC_CTRL2_UTMI_CLK_VLD_MASK (0x80000000U) +#define USBNC_CTRL2_UTMI_CLK_VLD_SHIFT (31U) +/*! UTMI_CLK_VLD - UTMI_CLK_VLD + * 0b0..Default + */ +#define USBNC_CTRL2_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_UTMI_CLK_VLD_SHIFT)) & USBNC_CTRL2_UTMI_CLK_VLD_MASK) +/*! @} */ + +/*! @name HSIC_CTRL - USB Host HSIC Control Register */ +/*! @{ */ + +#define USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK (0x800U) +#define USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT (11U) +/*! HSIC_CLK_ON - HSIC_CLK_ON + * 0b1..Active + * 0b0..Inactive + */ +#define USBNC_HSIC_CTRL_HSIC_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT)) & USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK) + +#define USBNC_HSIC_CTRL_HSIC_EN_MASK (0x1000U) +#define USBNC_HSIC_CTRL_HSIC_EN_SHIFT (12U) +/*! HSIC_EN - HSIC_EN + * 0b1..Enabled + * 0b0..Disabled + */ +#define USBNC_HSIC_CTRL_HSIC_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_EN_SHIFT)) & USBNC_HSIC_CTRL_HSIC_EN_MASK) + +#define USBNC_HSIC_CTRL_CLK_VLD_MASK (0x80000000U) +#define USBNC_HSIC_CTRL_CLK_VLD_SHIFT (31U) +/*! CLK_VLD - CLK_VLD + * 0b1..Valid + * 0b0..Invalid + */ +#define USBNC_HSIC_CTRL_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_CLK_VLD_SHIFT)) & USBNC_HSIC_CTRL_CLK_VLD_MASK) /*! @} */ @@ -84944,18 +95021,51 @@ typedef struct { /* USBNC - Peripheral instance base addresses */ -/** Peripheral USBNC1 base address */ -#define USBNC1_BASE (0x40430000u) -/** Peripheral USBNC1 base pointer */ -#define USBNC1 ((USBNC_Type *)USBNC1_BASE) -/** Peripheral USBNC2 base address */ -#define USBNC2_BASE (0x4042C000u) -/** Peripheral USBNC2 base pointer */ -#define USBNC2 ((USBNC_Type *)USBNC2_BASE) +/** Peripheral USB__USBNC_OTG1 base address */ +#define USB__USBNC_OTG1_BASE (0x40430200u) +/** Peripheral USB__USBNC_OTG1 base pointer */ +#define USB__USBNC_OTG1 ((USBNC_Type *)USB__USBNC_OTG1_BASE) +/** Peripheral USB__USBNC_OTG2 base address */ +#define USB__USBNC_OTG2_BASE (0x4042C200u) +/** Peripheral USB__USBNC_OTG2 base pointer */ +#define USB__USBNC_OTG2 ((USBNC_Type *)USB__USBNC_OTG2_BASE) /** Array initializer of USBNC peripheral base addresses */ -#define USBNC_BASE_ADDRS { 0u, USBNC1_BASE, USBNC2_BASE } +#define USBNC_BASE_ADDRS { 0u, USB__USBNC_OTG1_BASE, USB__USBNC_OTG2_BASE } /** Array initializer of USBNC peripheral base pointers */ -#define USBNC_BASE_PTRS { (USBNC_Type *)0u, USBNC1, USBNC2 } +#define USBNC_BASE_PTRS { (USBNC_Type *)0u, USB__USBNC_OTG1, USB__USBNC_OTG2 } +/* Backward compatibility */ +#define USB_OTGn_CTRL CTRL1 +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK USBNC_CTRL1_OVER_CUR_DIS_MASK +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT USBNC_CTRL1_OVER_CUR_DIS_SHIFT +#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) USBNC_CTRL1_OVER_CUR_DIS(x) +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK USBNC_CTRL1_OVER_CUR_POL_MASK +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT USBNC_CTRL1_OVER_CUR_POL_SHIFT +#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) USBNC_CTRL1_OVER_CUR_POL(x) +#define USBNC_USB_OTGn_CTRL_PWR_POL_MASK USBNC_CTRL1_PWR_POL_MASK +#define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT USBNC_CTRL1_PWR_POL_SHIFT +#define USBNC_USB_OTGn_CTRL_PWR_POL(x) USBNC_CTRL1_PWR_POL(x) +#define USBNC_USB_OTGn_CTRL_WIE_MASK USBNC_CTRL1_WIE_MASK +#define USBNC_USB_OTGn_CTRL_WIE_SHIFT USBNC_CTRL1_WIE_SHIFT +#define USBNC_USB_OTGn_CTRL_WIE(x) USBNC_CTRL1_WIE(x) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK USBNC_CTRL1_WKUP_SW_EN_MASK +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT USBNC_CTRL1_WKUP_SW_EN_SHIFT +#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) USBNC_CTRL1_WKUP_SW_EN(x) +#define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK USBNC_CTRL1_WKUP_SW_MASK +#define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT USBNC_CTRL1_WKUP_SW_SHIFT +#define USBNC_USB_OTGn_CTRL_WKUP_SW(x) USBNC_CTRL1_WKUP_SW(x) +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK USBNC_CTRL1_WKUP_ID_EN_MASK +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT USBNC_CTRL1_WKUP_ID_EN_SHIFT +#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) USBNC_CTRL1_WKUP_ID_EN(x) +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK USBNC_CTRL1_WKUP_VBUS_EN_MASK +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT USBNC_CTRL1_WKUP_VBUS_EN_SHIFT +#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) USBNC_CTRL1_WKUP_VBUS_EN(x) +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK USBNC_CTRL1_WKUP_DPDM_EN_MASK +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT USBNC_CTRL1_WKUP_DPDM_EN_SHIFT +#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) USBNC_CTRL1_WKUP_DPDM_EN(x) +#define USBNC_USB_OTGn_CTRL_WIR_MASK USBNC_CTRL1_WIR_MASK +#define USBNC_USB_OTGn_CTRL_WIR_SHIFT USBNC_CTRL1_WIR_SHIFT +#define USBNC_USB_OTGn_CTRL_WIR(x) USBNC_CTRL1_WIR(x) + /*! * @} @@ -84991,11 +95101,12 @@ typedef struct { __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */ __IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */ uint8_t RESERVED_0[12]; - __IO uint32_t DEBUG0; /**< USB PHY Debug Register 0, offset: 0x50 */ - __IO uint32_t DEBUG0_SET; /**< USB PHY Debug Register 0, offset: 0x54 */ - __IO uint32_t DEBUG0_CLR; /**< USB PHY Debug Register 0, offset: 0x58 */ - __IO uint32_t DEBUG0_TOG; /**< USB PHY Debug Register 0, offset: 0x5C */ - uint8_t RESERVED_1[16]; + __IO uint32_t DEBUGr; /**< USB PHY Debug Register, offset: 0x50 */ + __IO uint32_t DEBUG_SET; /**< USB PHY Debug Register, offset: 0x54 */ + __IO uint32_t DEBUG_CLR; /**< USB PHY Debug Register, offset: 0x58 */ + __IO uint32_t DEBUG_TOG; /**< USB PHY Debug Register, offset: 0x5C */ + __I uint32_t DEBUG0_STATUS; /**< UTMI Debug Status Register 0, offset: 0x60 */ + uint8_t RESERVED_1[12]; __IO uint32_t DEBUG1; /**< UTMI Debug Status Register 1, offset: 0x70 */ __IO uint32_t DEBUG1_SET; /**< UTMI Debug Status Register 1, offset: 0x74 */ __IO uint32_t DEBUG1_CLR; /**< UTMI Debug Status Register 1, offset: 0x78 */ @@ -85048,52 +95159,59 @@ typedef struct { /*! @name PWD - USB PHY Power-Down Register */ /*! @{ */ + #define USBPHY_PWD_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_TXPWDFS_SHIFT (10U) -/*! TXPWDFS +/*! TXPWDFS - TXPWDFS * 0b0..Normal operation. * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output */ #define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK) + #define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS +/*! TXPWDIBIAS - TXPWDIBIAS * 0b0..Normal operation * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB * is in suspend mode. This effectively powers down the entire USB transmit path */ #define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK) + #define USBPHY_PWD_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I +/*! TXPWDV2I - TXPWDV2I * 0b0..Normal operation. * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror */ #define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK) + #define USBPHY_PWD_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_RXPWDENV_SHIFT (17U) -/*! RXPWDENV +/*! RXPWDENV - RXPWDENV * 0b0..Normal operation. * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) */ #define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK) + #define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 +/*! RXPWD1PT1 - RXPWD1PT1 * 0b0..Normal operation * 0b1..Power-down the USB full-speed differential receiver. */ #define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK) + #define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF +/*! RXPWDDIFF - RXPWDDIFF * 0b0..Normal operation. * 0b1..Power-down the USB high-speed differential receiver */ #define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK) + #define USBPHY_PWD_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_RXPWDRX_SHIFT (20U) -/*! RXPWDRX +/*! RXPWDRX - RXPWDRX * 0b0..Normal operation * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver */ @@ -85102,411 +95220,239 @@ typedef struct { /*! @name PWD_SET - USB PHY Power-Down Register */ /*! @{ */ + #define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output +/*! TXPWDFS - TXPWDFS */ #define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK) + #define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - * 0b0..Normal operation - * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB - * is in suspend mode. This effectively powers down the entire USB transmit path +/*! TXPWDIBIAS - TXPWDIBIAS */ #define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK) + #define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror +/*! TXPWDV2I - TXPWDV2I */ #define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK) + #define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) +/*! RXPWDENV - RXPWDENV */ #define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK) + #define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - * 0b0..Normal operation - * 0b1..Power-down the USB full-speed differential receiver. +/*! RXPWD1PT1 - RXPWD1PT1 */ #define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK) + #define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed differential receiver +/*! RXPWDDIFF - RXPWDDIFF */ #define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK) + #define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - * 0b0..Normal operation - * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver +/*! RXPWDRX - RXPWDRX */ #define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK) /*! @} */ /*! @name PWD_CLR - USB PHY Power-Down Register */ /*! @{ */ + #define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output +/*! TXPWDFS - TXPWDFS */ #define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK) + #define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - * 0b0..Normal operation - * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB - * is in suspend mode. This effectively powers down the entire USB transmit path +/*! TXPWDIBIAS - TXPWDIBIAS */ #define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK) + #define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror +/*! TXPWDV2I - TXPWDV2I */ #define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK) + #define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) +/*! RXPWDENV - RXPWDENV */ #define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK) + #define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - * 0b0..Normal operation - * 0b1..Power-down the USB full-speed differential receiver. +/*! RXPWD1PT1 - RXPWD1PT1 */ #define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK) + #define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed differential receiver +/*! RXPWDDIFF - RXPWDDIFF */ #define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK) + #define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - * 0b0..Normal operation - * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver +/*! RXPWDRX - RXPWDRX */ #define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK) /*! @} */ /*! @name PWD_TOG - USB PHY Power-Down Register */ /*! @{ */ + #define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U) #define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U) -/*! TXPWDFS - * 0b0..Normal operation. - * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output +/*! TXPWDFS - TXPWDFS */ #define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK) + #define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U) #define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U) -/*! TXPWDIBIAS - * 0b0..Normal operation - * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB - * is in suspend mode. This effectively powers down the entire USB transmit path +/*! TXPWDIBIAS - TXPWDIBIAS */ #define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK) + #define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U) #define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U) -/*! TXPWDV2I - * 0b0..Normal operation. - * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror +/*! TXPWDV2I - TXPWDV2I */ #define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK) + #define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U) #define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U) -/*! RXPWDENV - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal) +/*! RXPWDENV - RXPWDENV */ #define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK) + #define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U) #define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U) -/*! RXPWD1PT1 - * 0b0..Normal operation - * 0b1..Power-down the USB full-speed differential receiver. +/*! RXPWD1PT1 - RXPWD1PT1 */ #define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK) + #define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U) #define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U) -/*! RXPWDDIFF - * 0b0..Normal operation. - * 0b1..Power-down the USB high-speed differential receiver +/*! RXPWDDIFF - RXPWDDIFF */ #define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK) + #define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U) #define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U) -/*! RXPWDRX - * 0b0..Normal operation - * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver +/*! RXPWDRX - RXPWDRX */ #define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK) /*! @} */ /*! @name TX - USB PHY Transmitter Control Register */ /*! @{ */ + #define USBPHY_TX_D_CAL_MASK (0xFU) #define USBPHY_TX_D_CAL_SHIFT (0U) -/*! D_CAL +/*! D_CAL - D_CAL * 0b0000..Maximum current, approximately 19% above nominal. * 0b0111..Nominal * 0b1111..Minimum current, approximately 19% below nominal. */ #define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK) -#define USBPHY_TX_TXCAL45DM_MASK (0xF00U) -#define USBPHY_TX_TXCAL45DM_SHIFT (8U) -/*! TXCAL45DM - * 0b0000..+19.95% - * 0b0001..+17.35% - * 0b0010..+14.85% - * 0b0011..+12.46% - * 0b0100..+9.07% - * 0b0101..+5.87% - * 0b0110..+2.85% - * 0b0111..0% - * 0b1000..-2.70% - * 0b1001..-5.25% - * 0b1010..-7.67% - * 0b1011..-9.98% - * 0b1100..-12.17% - * 0b1101..-14.25% - * 0b1110..-18.14% - * 0b1111..-21.68% - */ -#define USBPHY_TX_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK) -#define USBPHY_TX_TXENCAL45DM_MASK (0x2000U) -#define USBPHY_TX_TXENCAL45DM_SHIFT (13U) -#define USBPHY_TX_TXENCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DM_SHIFT)) & USBPHY_TX_TXENCAL45DM_MASK) + +#define USBPHY_TX_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_TXCAL45DN_SHIFT (8U) +/*! TXCAL45DN - TXCAL45DN + */ +#define USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK) + #define USBPHY_TX_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_TXCAL45DP_SHIFT (16U) -/*! TXCAL45DP - * 0b0000..+19.95% - * 0b0001..+17.35% - * 0b0010..+14.85% - * 0b0011..+12.46% - * 0b0100..+9.07% - * 0b0101..+5.87% - * 0b0110..+2.85% - * 0b0111..0% - * 0b1000..-2.70% - * 0b1001..-5.25% - * 0b1010..-7.67% - * 0b1011..-9.98% - * 0b1100..-12.17% - * 0b1101..-14.25% - * 0b1110..-18.14% - * 0b1111..-21.68% +/*! TXCAL45DP - TXCAL45DP */ #define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK) -#define USBPHY_TX_TXENCAL45DP_MASK (0x200000U) -#define USBPHY_TX_TXENCAL45DP_SHIFT (21U) -#define USBPHY_TX_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXENCAL45DP_SHIFT)) & USBPHY_TX_TXENCAL45DP_MASK) /*! @} */ /*! @name TX_SET - USB PHY Transmitter Control Register */ /*! @{ */ + #define USBPHY_TX_SET_D_CAL_MASK (0xFU) #define USBPHY_TX_SET_D_CAL_SHIFT (0U) -/*! D_CAL - * 0b0000..Maximum current, approximately 19% above nominal. - * 0b0111..Nominal - * 0b1111..Minimum current, approximately 19% below nominal. +/*! D_CAL - D_CAL */ #define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK) -#define USBPHY_TX_SET_TXCAL45DM_MASK (0xF00U) -#define USBPHY_TX_SET_TXCAL45DM_SHIFT (8U) -/*! TXCAL45DM - * 0b0000..+19.95% - * 0b0001..+17.35% - * 0b0010..+14.85% - * 0b0011..+12.46% - * 0b0100..+9.07% - * 0b0101..+5.87% - * 0b0110..+2.85% - * 0b0111..0% - * 0b1000..-2.70% - * 0b1001..-5.25% - * 0b1010..-7.67% - * 0b1011..-9.98% - * 0b1100..-12.17% - * 0b1101..-14.25% - * 0b1110..-18.14% - * 0b1111..-21.68% - */ -#define USBPHY_TX_SET_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK) -#define USBPHY_TX_SET_TXENCAL45DM_MASK (0x2000U) -#define USBPHY_TX_SET_TXENCAL45DM_SHIFT (13U) -#define USBPHY_TX_SET_TXENCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DM_SHIFT)) & USBPHY_TX_SET_TXENCAL45DM_MASK) + +#define USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_SET_TXCAL45DN_SHIFT (8U) +/*! TXCAL45DN - TXCAL45DN + */ +#define USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK) + #define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U) -/*! TXCAL45DP - * 0b0000..+19.95% - * 0b0001..+17.35% - * 0b0010..+14.85% - * 0b0011..+12.46% - * 0b0100..+9.07% - * 0b0101..+5.87% - * 0b0110..+2.85% - * 0b0111..0% - * 0b1000..-2.70% - * 0b1001..-5.25% - * 0b1010..-7.67% - * 0b1011..-9.98% - * 0b1100..-12.17% - * 0b1101..-14.25% - * 0b1110..-18.14% - * 0b1111..-21.68% +/*! TXCAL45DP - TXCAL45DP */ #define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK) -#define USBPHY_TX_SET_TXENCAL45DP_MASK (0x200000U) -#define USBPHY_TX_SET_TXENCAL45DP_SHIFT (21U) -#define USBPHY_TX_SET_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXENCAL45DP_SHIFT)) & USBPHY_TX_SET_TXENCAL45DP_MASK) /*! @} */ /*! @name TX_CLR - USB PHY Transmitter Control Register */ /*! @{ */ + #define USBPHY_TX_CLR_D_CAL_MASK (0xFU) #define USBPHY_TX_CLR_D_CAL_SHIFT (0U) -/*! D_CAL - * 0b0000..Maximum current, approximately 19% above nominal. - * 0b0111..Nominal - * 0b1111..Minimum current, approximately 19% below nominal. +/*! D_CAL - D_CAL */ #define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK) -#define USBPHY_TX_CLR_TXCAL45DM_MASK (0xF00U) -#define USBPHY_TX_CLR_TXCAL45DM_SHIFT (8U) -/*! TXCAL45DM - * 0b0000..+19.95% - * 0b0001..+17.35% - * 0b0010..+14.85% - * 0b0011..+12.46% - * 0b0100..+9.07% - * 0b0101..+5.87% - * 0b0110..+2.85% - * 0b0111..0% - * 0b1000..-2.70% - * 0b1001..-5.25% - * 0b1010..-7.67% - * 0b1011..-9.98% - * 0b1100..-12.17% - * 0b1101..-14.25% - * 0b1110..-18.14% - * 0b1111..-21.68% - */ -#define USBPHY_TX_CLR_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK) -#define USBPHY_TX_CLR_TXENCAL45DM_MASK (0x2000U) -#define USBPHY_TX_CLR_TXENCAL45DM_SHIFT (13U) -#define USBPHY_TX_CLR_TXENCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DM_MASK) + +#define USBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_CLR_TXCAL45DN_SHIFT (8U) +/*! TXCAL45DN - TXCAL45DN + */ +#define USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK) + #define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U) -/*! TXCAL45DP - * 0b0000..+19.95% - * 0b0001..+17.35% - * 0b0010..+14.85% - * 0b0011..+12.46% - * 0b0100..+9.07% - * 0b0101..+5.87% - * 0b0110..+2.85% - * 0b0111..0% - * 0b1000..-2.70% - * 0b1001..-5.25% - * 0b1010..-7.67% - * 0b1011..-9.98% - * 0b1100..-12.17% - * 0b1101..-14.25% - * 0b1110..-18.14% - * 0b1111..-21.68% +/*! TXCAL45DP - TXCAL45DP */ #define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK) -#define USBPHY_TX_CLR_TXENCAL45DP_MASK (0x200000U) -#define USBPHY_TX_CLR_TXENCAL45DP_SHIFT (21U) -#define USBPHY_TX_CLR_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXENCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXENCAL45DP_MASK) /*! @} */ /*! @name TX_TOG - USB PHY Transmitter Control Register */ /*! @{ */ + #define USBPHY_TX_TOG_D_CAL_MASK (0xFU) #define USBPHY_TX_TOG_D_CAL_SHIFT (0U) -/*! D_CAL - * 0b0000..Maximum current, approximately 19% above nominal. - * 0b0111..Nominal - * 0b1111..Minimum current, approximately 19% below nominal. +/*! D_CAL - D_CAL */ #define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK) -#define USBPHY_TX_TOG_TXCAL45DM_MASK (0xF00U) -#define USBPHY_TX_TOG_TXCAL45DM_SHIFT (8U) -/*! TXCAL45DM - * 0b0000..+19.95% - * 0b0001..+17.35% - * 0b0010..+14.85% - * 0b0011..+12.46% - * 0b0100..+9.07% - * 0b0101..+5.87% - * 0b0110..+2.85% - * 0b0111..0% - * 0b1000..-2.70% - * 0b1001..-5.25% - * 0b1010..-7.67% - * 0b1011..-9.98% - * 0b1100..-12.17% - * 0b1101..-14.25% - * 0b1110..-18.14% - * 0b1111..-21.68% - */ -#define USBPHY_TX_TOG_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK) -#define USBPHY_TX_TOG_TXENCAL45DM_MASK (0x2000U) -#define USBPHY_TX_TOG_TXENCAL45DM_SHIFT (13U) -#define USBPHY_TX_TOG_TXENCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DM_MASK) + +#define USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U) +#define USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U) +/*! TXCAL45DN - TXCAL45DN + */ +#define USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK) + #define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U) #define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U) -/*! TXCAL45DP - * 0b0000..+19.95% - * 0b0001..+17.35% - * 0b0010..+14.85% - * 0b0011..+12.46% - * 0b0100..+9.07% - * 0b0101..+5.87% - * 0b0110..+2.85% - * 0b0111..0% - * 0b1000..-2.70% - * 0b1001..-5.25% - * 0b1010..-7.67% - * 0b1011..-9.98% - * 0b1100..-12.17% - * 0b1101..-14.25% - * 0b1110..-18.14% - * 0b1111..-21.68% +/*! TXCAL45DP - TXCAL45DP */ #define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK) -#define USBPHY_TX_TOG_TXENCAL45DP_MASK (0x200000U) -#define USBPHY_TX_TOG_TXENCAL45DP_SHIFT (21U) -#define USBPHY_TX_TOG_TXENCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXENCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXENCAL45DP_MASK) /*! @} */ /*! @name RX - USB PHY Receiver Control Register */ /*! @{ */ + #define USBPHY_RX_ENVADJ_MASK (0x7U) #define USBPHY_RX_ENVADJ_SHIFT (0U) -/*! ENVADJ +/*! ENVADJ - ENVADJ * 0b000..Trip-Level Voltage is 0.1000 V * 0b001..Trip-Level Voltage is 0.1125 V * 0b010..Trip-Level Voltage is 0.1250 V @@ -85514,9 +95460,10 @@ typedef struct { * 0b1xx..Reserved */ #define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK) + #define USBPHY_RX_DISCONADJ_MASK (0x70U) #define USBPHY_RX_DISCONADJ_SHIFT (4U) -/*! DISCONADJ +/*! DISCONADJ - DISCONADJ * 0b000..Trip-Level Voltage is 0.56875 V * 0b001..Trip-Level Voltage is 0.55000 V * 0b010..Trip-Level Voltage is 0.58125 V @@ -85524,9 +95471,10 @@ typedef struct { * 0b1xx..Reserved */ #define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK) + #define USBPHY_RX_RXDBYPASS_MASK (0x400000U) #define USBPHY_RX_RXDBYPASS_SHIFT (22U) -/*! RXDBYPASS +/*! RXDBYPASS - RXDBYPASS * 0b0..Normal operation. * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver */ @@ -85535,318 +95483,795 @@ typedef struct { /*! @name RX_SET - USB PHY Receiver Control Register */ /*! @{ */ + #define USBPHY_RX_SET_ENVADJ_MASK (0x7U) #define USBPHY_RX_SET_ENVADJ_SHIFT (0U) -/*! ENVADJ - * 0b000..Trip-Level Voltage is 0.1000 V - * 0b001..Trip-Level Voltage is 0.1125 V - * 0b010..Trip-Level Voltage is 0.1250 V - * 0b011..Trip-Level Voltage is 0.0875 V - * 0b1xx..Reserved +/*! ENVADJ - ENVADJ */ #define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK) + #define USBPHY_RX_SET_DISCONADJ_MASK (0x70U) #define USBPHY_RX_SET_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - * 0b000..Trip-Level Voltage is 0.56875 V - * 0b001..Trip-Level Voltage is 0.55000 V - * 0b010..Trip-Level Voltage is 0.58125 V - * 0b011..Trip-Level Voltage is 0.60000 V - * 0b1xx..Reserved +/*! DISCONADJ - DISCONADJ */ #define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK) + #define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U) #define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U) -/*! RXDBYPASS - * 0b0..Normal operation. - * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver +/*! RXDBYPASS - RXDBYPASS */ #define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK) /*! @} */ /*! @name RX_CLR - USB PHY Receiver Control Register */ /*! @{ */ + #define USBPHY_RX_CLR_ENVADJ_MASK (0x7U) #define USBPHY_RX_CLR_ENVADJ_SHIFT (0U) -/*! ENVADJ - * 0b000..Trip-Level Voltage is 0.1000 V - * 0b001..Trip-Level Voltage is 0.1125 V - * 0b010..Trip-Level Voltage is 0.1250 V - * 0b011..Trip-Level Voltage is 0.0875 V - * 0b1xx..Reserved +/*! ENVADJ - ENVADJ */ #define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK) + #define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U) #define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - * 0b000..Trip-Level Voltage is 0.56875 V - * 0b001..Trip-Level Voltage is 0.55000 V - * 0b010..Trip-Level Voltage is 0.58125 V - * 0b011..Trip-Level Voltage is 0.60000 V - * 0b1xx..Reserved +/*! DISCONADJ - DISCONADJ */ #define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK) + #define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U) #define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U) -/*! RXDBYPASS - * 0b0..Normal operation. - * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver +/*! RXDBYPASS - RXDBYPASS */ #define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK) /*! @} */ /*! @name RX_TOG - USB PHY Receiver Control Register */ /*! @{ */ + #define USBPHY_RX_TOG_ENVADJ_MASK (0x7U) #define USBPHY_RX_TOG_ENVADJ_SHIFT (0U) -/*! ENVADJ - * 0b000..Trip-Level Voltage is 0.1000 V - * 0b001..Trip-Level Voltage is 0.1125 V - * 0b010..Trip-Level Voltage is 0.1250 V - * 0b011..Trip-Level Voltage is 0.0875 V - * 0b1xx..Reserved +/*! ENVADJ - ENVADJ */ #define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK) + #define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U) #define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U) -/*! DISCONADJ - * 0b000..Trip-Level Voltage is 0.56875 V - * 0b001..Trip-Level Voltage is 0.55000 V - * 0b010..Trip-Level Voltage is 0.58125 V - * 0b011..Trip-Level Voltage is 0.60000 V - * 0b1xx..Reserved +/*! DISCONADJ - DISCONADJ */ #define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK) + #define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U) #define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U) -/*! RXDBYPASS - * 0b0..Normal operation. - * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver +/*! RXDBYPASS - RXDBYPASS */ #define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK) /*! @} */ /*! @name CTRL - USB PHY General Control Register */ /*! @{ */ + +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U) +/*! ENOTG_ID_CHG_IRQ - ENOTG_ID_CHG_IRQ + */ +#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK) + #define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U) +/*! ENHOSTDISCONDETECT - ENHOSTDISCONDETECT + */ #define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U) +/*! ENIRQHOSTDISCON - ENIRQHOSTDISCON + */ +#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK) + #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U) +/*! HOSTDISCONDETECT_IRQ - HOSTDISCONDETECT_IRQ + */ #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK) -#define USBPHY_CTRL_ENDEVPLUGINDET_MASK (0x10U) -#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT (4U) -/*! ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection - * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + +#define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U) +/*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection + * 0b0..Disables 200kohm pullup resistors on DP and DN pins + * 0b1..Enables 200kohm pullup resistors on DP and DN pins + */ +#define USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK) + +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U) +/*! DEVPLUGIN_POLARITY - DEVPLUGIN_POLARITY + */ +#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U) +/*! OTG_ID_CHG_IRQ - OTG_ID_CHG_IRQ + */ +#define USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK) + +#define USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U) +/*! ENOTGIDDETECT - ENOTGIDDETECT + */ +#define USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK) + +#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U) +/*! RESUMEIRQSTICKY - RESUMEIRQSTICKY + */ +#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U) +/*! ENIRQRESUMEDETECT - ENIRQRESUMEDETECT */ -#define USBPHY_CTRL_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK) +#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U) +/*! RESUME_IRQ - RESUME_IRQ + */ +#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U) +/*! ENIRQDEVPLUGIN - ENIRQDEVPLUGIN + */ +#define USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK) + #define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U) +/*! DEVPLUGIN_IRQ - DEVPLUGIN_IRQ + */ #define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK) + #define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U) +/*! ENUTMILEVEL2 - ENUTMILEVEL2 + */ #define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK) + #define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U) +/*! ENUTMILEVEL3 - ENUTMILEVEL3 + */ #define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U) +/*! ENIRQWAKEUP - ENIRQWAKEUP + */ +#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U) +/*! WAKEUP_IRQ - WAKEUP_IRQ + */ +#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK) + #define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U) +/*! AUTORESUME_EN - AUTORESUME_EN + */ #define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK) + #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U) +/*! ENAUTOCLR_CLKGATE - ENAUTOCLR_CLKGATE + */ #define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK) + #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U) +/*! ENAUTOCLR_PHY_PWD - ENAUTOCLR_PHY_PWD + */ #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U) +/*! ENDPDMCHG_WKUP - ENDPDMCHG_WKUP + */ +#define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK) + +#define USBPHY_CTRL_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_ENIDCHG_WKUP_SHIFT (22U) +/*! ENIDCHG_WKUP - ENIDCHG_WKUP + */ +#define USBPHY_CTRL_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK) + +#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U) +/*! ENVBUSCHG_WKUP - ENVBUSCHG_WKUP + */ +#define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK) + #define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U) #define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U) +/*! FSDLL_RST_EN - FSDLL_RST_EN + */ #define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK) + #define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U) #define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U) +/*! OTG_ID_VALUE - OTG_ID_VALUE + */ #define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK) + #define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U) #define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U) +/*! HOST_FORCE_LS_SE0 - HOST_FORCE_LS_SE0 + */ #define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK) + #define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U) #define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U) +/*! UTMI_SUSPENDM - UTMI_SUSPENDM + */ #define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK) + #define USBPHY_CTRL_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_CLKGATE_SHIFT (30U) +/*! CLKGATE - CLKGATE + */ #define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK) + #define USBPHY_CTRL_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_SFTRST_SHIFT (31U) +/*! SFTRST - SFTRST + */ #define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK) /*! @} */ /*! @name CTRL_SET - USB PHY General Control Register */ /*! @{ */ + +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U) +/*! ENOTG_ID_CHG_IRQ - ENOTG_ID_CHG_IRQ + */ +#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK) + #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U) +/*! ENHOSTDISCONDETECT - ENHOSTDISCONDETECT + */ #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U) +/*! ENIRQHOSTDISCON - ENIRQHOSTDISCON + */ +#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK) + #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U) +/*! HOSTDISCONDETECT_IRQ - HOSTDISCONDETECT_IRQ + */ #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK) -#define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK (0x10U) -#define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT (4U) -/*! ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection - * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U) +/*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection + */ +#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK) + +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U) +/*! DEVPLUGIN_POLARITY - DEVPLUGIN_POLARITY + */ +#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U) +/*! OTG_ID_CHG_IRQ - OTG_ID_CHG_IRQ + */ +#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK) + +#define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U) +/*! ENOTGIDDETECT - ENOTGIDDETECT + */ +#define USBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK) + +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U) +/*! RESUMEIRQSTICKY - RESUMEIRQSTICKY + */ +#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U) +/*! ENIRQRESUMEDETECT - ENIRQRESUMEDETECT + */ +#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U) +/*! RESUME_IRQ - RESUME_IRQ + */ +#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U) +/*! ENIRQDEVPLUGIN - ENIRQDEVPLUGIN */ -#define USBPHY_CTRL_SET_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK) +#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK) + #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U) +/*! DEVPLUGIN_IRQ - DEVPLUGIN_IRQ + */ #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK) + #define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U) +/*! ENUTMILEVEL2 - ENUTMILEVEL2 + */ #define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK) + #define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U) +/*! ENUTMILEVEL3 - ENUTMILEVEL3 + */ #define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U) +/*! ENIRQWAKEUP - ENIRQWAKEUP + */ +#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U) +/*! WAKEUP_IRQ - WAKEUP_IRQ + */ +#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK) + #define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U) +/*! AUTORESUME_EN - AUTORESUME_EN + */ #define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK) + #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U) +/*! ENAUTOCLR_CLKGATE - ENAUTOCLR_CLKGATE + */ #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK) + #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U) +/*! ENAUTOCLR_PHY_PWD - ENAUTOCLR_PHY_PWD + */ #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U) +/*! ENDPDMCHG_WKUP - ENDPDMCHG_WKUP + */ +#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK) + +#define USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT (22U) +/*! ENIDCHG_WKUP - ENIDCHG_WKUP + */ +#define USBPHY_CTRL_SET_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK) + +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U) +/*! ENVBUSCHG_WKUP - ENVBUSCHG_WKUP + */ +#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK) + #define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U) #define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U) +/*! FSDLL_RST_EN - FSDLL_RST_EN + */ #define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK) + #define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U) #define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U) +/*! OTG_ID_VALUE - OTG_ID_VALUE + */ #define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK) + #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U) #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U) +/*! HOST_FORCE_LS_SE0 - HOST_FORCE_LS_SE0 + */ #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK) + #define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U) #define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U) +/*! UTMI_SUSPENDM - UTMI_SUSPENDM + */ #define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK) + #define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U) +/*! CLKGATE - CLKGATE + */ #define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK) + #define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_SET_SFTRST_SHIFT (31U) +/*! SFTRST - SFTRST + */ #define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK) /*! @} */ /*! @name CTRL_CLR - USB PHY General Control Register */ /*! @{ */ + +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U) +/*! ENOTG_ID_CHG_IRQ - ENOTG_ID_CHG_IRQ + */ +#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK) + #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U) +/*! ENHOSTDISCONDETECT - ENHOSTDISCONDETECT + */ #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U) +/*! ENIRQHOSTDISCON - ENIRQHOSTDISCON + */ +#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK) + #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U) +/*! HOSTDISCONDETECT_IRQ - HOSTDISCONDETECT_IRQ + */ #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK) -#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK (0x10U) -#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT (4U) -/*! ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection - * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U) +/*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection + */ +#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK) + +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U) +/*! DEVPLUGIN_POLARITY - DEVPLUGIN_POLARITY + */ +#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U) +/*! OTG_ID_CHG_IRQ - OTG_ID_CHG_IRQ + */ +#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK) + +#define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U) +/*! ENOTGIDDETECT - ENOTGIDDETECT + */ +#define USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK) + +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U) +/*! RESUMEIRQSTICKY - RESUMEIRQSTICKY */ -#define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK) +#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U) +/*! ENIRQRESUMEDETECT - ENIRQRESUMEDETECT + */ +#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U) +/*! RESUME_IRQ - RESUME_IRQ + */ +#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U) +/*! ENIRQDEVPLUGIN - ENIRQDEVPLUGIN + */ +#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK) + #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U) +/*! DEVPLUGIN_IRQ - DEVPLUGIN_IRQ + */ #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK) + #define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U) +/*! ENUTMILEVEL2 - ENUTMILEVEL2 + */ #define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK) + #define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U) +/*! ENUTMILEVEL3 - ENUTMILEVEL3 + */ #define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U) +/*! ENIRQWAKEUP - ENIRQWAKEUP + */ +#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U) +/*! WAKEUP_IRQ - WAKEUP_IRQ + */ +#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK) + #define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U) +/*! AUTORESUME_EN - AUTORESUME_EN + */ #define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK) + #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U) +/*! ENAUTOCLR_CLKGATE - ENAUTOCLR_CLKGATE + */ #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK) + #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U) +/*! ENAUTOCLR_PHY_PWD - ENAUTOCLR_PHY_PWD + */ #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U) +/*! ENDPDMCHG_WKUP - ENDPDMCHG_WKUP + */ +#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK) + +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT (22U) +/*! ENIDCHG_WKUP - ENIDCHG_WKUP + */ +#define USBPHY_CTRL_CLR_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK) + +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U) +/*! ENVBUSCHG_WKUP - ENVBUSCHG_WKUP + */ +#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK) + #define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U) #define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U) +/*! FSDLL_RST_EN - FSDLL_RST_EN + */ #define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK) + #define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U) #define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U) +/*! OTG_ID_VALUE - OTG_ID_VALUE + */ #define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK) + #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U) #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U) +/*! HOST_FORCE_LS_SE0 - HOST_FORCE_LS_SE0 + */ #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK) + #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U) #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U) +/*! UTMI_SUSPENDM - UTMI_SUSPENDM + */ #define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK) + #define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U) +/*! CLKGATE - CLKGATE + */ #define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK) + #define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U) +/*! SFTRST - SFTRST + */ #define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK) /*! @} */ /*! @name CTRL_TOG - USB PHY General Control Register */ /*! @{ */ + +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U) +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U) +/*! ENOTG_ID_CHG_IRQ - ENOTG_ID_CHG_IRQ + */ +#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK) + #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U) #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U) +/*! ENHOSTDISCONDETECT - ENHOSTDISCONDETECT + */ #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK) + +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U) +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U) +/*! ENIRQHOSTDISCON - ENIRQHOSTDISCON + */ +#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK) + #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U) #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U) +/*! HOSTDISCONDETECT_IRQ - HOSTDISCONDETECT_IRQ + */ #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK) -#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK (0x10U) -#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT (4U) -/*! ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection - * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default) - * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins + +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U) +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U) +/*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection + */ +#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK) + +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U) +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U) +/*! DEVPLUGIN_POLARITY - DEVPLUGIN_POLARITY + */ +#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK) + +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U) +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U) +/*! OTG_ID_CHG_IRQ - OTG_ID_CHG_IRQ + */ +#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK) + +#define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U) +#define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U) +/*! ENOTGIDDETECT - ENOTGIDDETECT + */ +#define USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK) + +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U) +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U) +/*! RESUMEIRQSTICKY - RESUMEIRQSTICKY + */ +#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK) + +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U) +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U) +/*! ENIRQRESUMEDETECT - ENIRQRESUMEDETECT + */ +#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK) + +#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U) +#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U) +/*! RESUME_IRQ - RESUME_IRQ + */ +#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK) + +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U) +/*! ENIRQDEVPLUGIN - ENIRQDEVPLUGIN */ -#define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK) +#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK) + #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U) #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U) +/*! DEVPLUGIN_IRQ - DEVPLUGIN_IRQ + */ #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK) + #define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U) #define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U) +/*! ENUTMILEVEL2 - ENUTMILEVEL2 + */ #define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK) + #define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U) #define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U) +/*! ENUTMILEVEL3 - ENUTMILEVEL3 + */ #define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK) + +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U) +#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U) +/*! ENIRQWAKEUP - ENIRQWAKEUP + */ +#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK) + +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U) +#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U) +/*! WAKEUP_IRQ - WAKEUP_IRQ + */ +#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK) + #define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U) #define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U) +/*! AUTORESUME_EN - AUTORESUME_EN + */ #define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK) + #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U) #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U) +/*! ENAUTOCLR_CLKGATE - ENAUTOCLR_CLKGATE + */ #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK) + #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U) #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U) +/*! ENAUTOCLR_PHY_PWD - ENAUTOCLR_PHY_PWD + */ #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK) + +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U) +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U) +/*! ENDPDMCHG_WKUP - ENDPDMCHG_WKUP + */ +#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK) + +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK (0x400000U) +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT (22U) +/*! ENIDCHG_WKUP - ENIDCHG_WKUP + */ +#define USBPHY_CTRL_TOG_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK) + +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U) +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U) +/*! ENVBUSCHG_WKUP - ENVBUSCHG_WKUP + */ +#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK) + #define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U) #define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U) +/*! FSDLL_RST_EN - FSDLL_RST_EN + */ #define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK) + #define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U) #define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U) +/*! OTG_ID_VALUE - OTG_ID_VALUE + */ #define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK) + #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U) #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U) +/*! HOST_FORCE_LS_SE0 - HOST_FORCE_LS_SE0 + */ #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK) + #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U) #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U) +/*! UTMI_SUSPENDM - UTMI_SUSPENDM + */ #define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK) + #define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U) #define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U) +/*! CLKGATE - CLKGATE + */ #define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK) + #define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U) #define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U) +/*! SFTRST - SFTRST + */ #define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK) /*! @} */ /*! @name STATUS - USB PHY Status Register */ /*! @{ */ + #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U) #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U) -/*! HOSTDISCONDETECT_STATUS +/*! HOSTDISCONDETECT_STATUS - HOSTDISCONDETECT_STATUS * 0b0..USB cable disconnect has not been detected at the local host * 0b1..USB cable disconnect has been detected at the local host */ #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK) + #define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U) #define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U) /*! DEVPLUGIN_STATUS - Status indicator for non-standard resistive plugged-in detection @@ -85854,178 +96279,359 @@ typedef struct { * 0b1..Cable attachment to a USB host is detected */ #define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK) + #define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U) #define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U) +/*! OTGID_STATUS - OTGID_STATUS + */ #define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK) + #define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U) #define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U) +/*! RESUME_STATUS - RESUME_STATUS + */ #define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK) /*! @} */ -/*! @name DEBUG0 - USB PHY Debug Register 0 */ -/*! @{ */ -#define USBPHY_DEBUG0_OTGIDPIOLOCK_MASK (0x1U) -#define USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT (0U) -#define USBPHY_DEBUG0_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_OTGIDPIOLOCK_MASK) -#define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_MASK (0x2U) -#define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_SHIFT (1U) -#define USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_DEBUG_INTERFACE_HOLD_MASK) -#define USBPHY_DEBUG0_HSTPULLDOWN_MASK (0xCU) -#define USBPHY_DEBUG0_HSTPULLDOWN_SHIFT (2U) -#define USBPHY_DEBUG0_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_HSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_ENHSTPULLDOWN_MASK (0x30U) -#define USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT (4U) -#define USBPHY_DEBUG0_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_ENHSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_TX2RXCOUNT_MASK (0xF00U) -#define USBPHY_DEBUG0_TX2RXCOUNT_SHIFT (8U) -#define USBPHY_DEBUG0_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_ENTX2RXCOUNT_MASK (0x1000U) -#define USBPHY_DEBUG0_ENTX2RXCOUNT_SHIFT (12U) -#define USBPHY_DEBUG0_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_ENTX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_SQUELCHRESETCOUNT_MASK (0x1F0000U) -#define USBPHY_DEBUG0_SQUELCHRESETCOUNT_SHIFT (16U) -#define USBPHY_DEBUG0_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_SQUELCHRESETCOUNT_MASK) -#define USBPHY_DEBUG0_ENSQUELCHRESET_MASK (0x1000000U) -#define USBPHY_DEBUG0_ENSQUELCHRESET_SHIFT (24U) -#define USBPHY_DEBUG0_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_ENSQUELCHRESET_MASK) -#define USBPHY_DEBUG0_SQUELCHRESETLENGTH_MASK (0x1E000000U) -#define USBPHY_DEBUG0_SQUELCHRESETLENGTH_SHIFT (25U) -#define USBPHY_DEBUG0_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_SQUELCHRESETLENGTH_MASK) -#define USBPHY_DEBUG0_HOST_RESUME_DEBUG_MASK (0x20000000U) -#define USBPHY_DEBUG0_HOST_RESUME_DEBUG_SHIFT (29U) -#define USBPHY_DEBUG0_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_HOST_RESUME_DEBUG_MASK) -#define USBPHY_DEBUG0_CLKGATE_MASK (0x40000000U) -#define USBPHY_DEBUG0_CLKGATE_SHIFT (30U) -#define USBPHY_DEBUG0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLKGATE_SHIFT)) & USBPHY_DEBUG0_CLKGATE_MASK) -/*! @} */ - -/*! @name DEBUG0_SET - USB PHY Debug Register 0 */ -/*! @{ */ -#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK (0x1U) -#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT (0U) -#define USBPHY_DEBUG0_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_SET_OTGIDPIOLOCK_MASK) -#define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U) -#define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U) -#define USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_SET_DEBUG_INTERFACE_HOLD_MASK) -#define USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK (0xCU) -#define USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT (2U) -#define USBPHY_DEBUG0_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_HSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK (0x30U) -#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT (4U) -#define USBPHY_DEBUG0_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_SET_ENHSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_SET_TX2RXCOUNT_MASK (0xF00U) -#define USBPHY_DEBUG0_SET_TX2RXCOUNT_SHIFT (8U) -#define USBPHY_DEBUG0_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_TX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_SET_ENTX2RXCOUNT_MASK (0x1000U) -#define USBPHY_DEBUG0_SET_ENTX2RXCOUNT_SHIFT (12U) -#define USBPHY_DEBUG0_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_ENTX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U) -#define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_SHIFT (16U) -#define USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_SET_SQUELCHRESETCOUNT_MASK) -#define USBPHY_DEBUG0_SET_ENSQUELCHRESET_MASK (0x1000000U) -#define USBPHY_DEBUG0_SET_ENSQUELCHRESET_SHIFT (24U) -#define USBPHY_DEBUG0_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_SET_ENSQUELCHRESET_MASK) -#define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U) -#define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_SHIFT (25U) -#define USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_SET_SQUELCHRESETLENGTH_MASK) -#define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_MASK (0x20000000U) -#define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_SHIFT (29U) -#define USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_SET_HOST_RESUME_DEBUG_MASK) -#define USBPHY_DEBUG0_SET_CLKGATE_MASK (0x40000000U) -#define USBPHY_DEBUG0_SET_CLKGATE_SHIFT (30U) -#define USBPHY_DEBUG0_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG0_SET_CLKGATE_MASK) -/*! @} */ - -/*! @name DEBUG0_CLR - USB PHY Debug Register 0 */ -/*! @{ */ -#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK (0x1U) -#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT (0U) -#define USBPHY_DEBUG0_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_CLR_OTGIDPIOLOCK_MASK) -#define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U) -#define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U) -#define USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_CLR_DEBUG_INTERFACE_HOLD_MASK) -#define USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK (0xCU) -#define USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT (2U) -#define USBPHY_DEBUG0_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_HSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK (0x30U) -#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT (4U) -#define USBPHY_DEBUG0_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_CLR_ENHSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_CLR_TX2RXCOUNT_MASK (0xF00U) -#define USBPHY_DEBUG0_CLR_TX2RXCOUNT_SHIFT (8U) -#define USBPHY_DEBUG0_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_TX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_MASK (0x1000U) -#define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_SHIFT (12U) -#define USBPHY_DEBUG0_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_ENTX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U) -#define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_SHIFT (16U) -#define USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_CLR_SQUELCHRESETCOUNT_MASK) -#define USBPHY_DEBUG0_CLR_ENSQUELCHRESET_MASK (0x1000000U) -#define USBPHY_DEBUG0_CLR_ENSQUELCHRESET_SHIFT (24U) -#define USBPHY_DEBUG0_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_CLR_ENSQUELCHRESET_MASK) -#define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U) -#define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_SHIFT (25U) -#define USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_CLR_SQUELCHRESETLENGTH_MASK) -#define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) -#define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_SHIFT (29U) -#define USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_CLR_HOST_RESUME_DEBUG_MASK) -#define USBPHY_DEBUG0_CLR_CLKGATE_MASK (0x40000000U) -#define USBPHY_DEBUG0_CLR_CLKGATE_SHIFT (30U) -#define USBPHY_DEBUG0_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG0_CLR_CLKGATE_MASK) -/*! @} */ - -/*! @name DEBUG0_TOG - USB PHY Debug Register 0 */ -/*! @{ */ -#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK (0x1U) -#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT (0U) -#define USBPHY_DEBUG0_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG0_TOG_OTGIDPIOLOCK_MASK) -#define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U) -#define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U) -#define USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG0_TOG_DEBUG_INTERFACE_HOLD_MASK) -#define USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK (0xCU) -#define USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT (2U) -#define USBPHY_DEBUG0_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_HSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK (0x30U) -#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT (4U) -#define USBPHY_DEBUG0_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG0_TOG_ENHSTPULLDOWN_MASK) -#define USBPHY_DEBUG0_TOG_TX2RXCOUNT_MASK (0xF00U) -#define USBPHY_DEBUG0_TOG_TX2RXCOUNT_SHIFT (8U) -#define USBPHY_DEBUG0_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_TX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_MASK (0x1000U) -#define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_SHIFT (12U) -#define USBPHY_DEBUG0_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_ENTX2RXCOUNT_MASK) -#define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U) -#define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_SHIFT (16U) -#define USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG0_TOG_SQUELCHRESETCOUNT_MASK) -#define USBPHY_DEBUG0_TOG_ENSQUELCHRESET_MASK (0x1000000U) -#define USBPHY_DEBUG0_TOG_ENSQUELCHRESET_SHIFT (24U) -#define USBPHY_DEBUG0_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG0_TOG_ENSQUELCHRESET_MASK) -#define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U) -#define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_SHIFT (25U) -#define USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG0_TOG_SQUELCHRESETLENGTH_MASK) -#define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U) -#define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_SHIFT (29U) -#define USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG0_TOG_HOST_RESUME_DEBUG_MASK) -#define USBPHY_DEBUG0_TOG_CLKGATE_MASK (0x40000000U) -#define USBPHY_DEBUG0_TOG_CLKGATE_SHIFT (30U) -#define USBPHY_DEBUG0_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG0_TOG_CLKGATE_MASK) +/*! @name DEBUG - USB PHY Debug Register */ +/*! @{ */ + +#define USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U) +/*! OTGIDPIOLOCK - OTGIDPIOLOCK + */ +#define USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK) + +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U) +/*! DEBUG_INTERFACE_HOLD - DEBUG_INTERFACE_HOLD + */ +#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK) + +#define USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U) +/*! HSTPULLDOWN - HSTPULLDOWN + */ +#define USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK) + +#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U) +/*! ENHSTPULLDOWN - ENHSTPULLDOWN + */ +#define USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK) + +#define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U) +/*! TX2RXCOUNT - TX2RXCOUNT + */ +#define USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK) + +#define USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U) +/*! ENTX2RXCOUNT - ENTX2RXCOUNT + */ +#define USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK) + +#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U) +/*! SQUELCHRESETCOUNT - SQUELCHRESETCOUNT + */ +#define USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK) + +#define USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U) +/*! ENSQUELCHRESET - ENSQUELCHRESET + */ +#define USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK) + +#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U) +/*! SQUELCHRESETLENGTH - SQUELCHRESETLENGTH + */ +#define USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK) + +#define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U) +/*! HOST_RESUME_DEBUG - HOST_RESUME_DEBUG + */ +#define USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK) + +#define USBPHY_DEBUG_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_CLKGATE_SHIFT (30U) +/*! CLKGATE - CLKGATE + */ +#define USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK) +/*! @} */ + +/*! @name DEBUG_SET - USB PHY Debug Register */ +/*! @{ */ + +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U) +/*! OTGIDPIOLOCK - OTGIDPIOLOCK + */ +#define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK) + +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U) +/*! DEBUG_INTERFACE_HOLD - DEBUG_INTERFACE_HOLD + */ +#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK) + +#define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U) +/*! HSTPULLDOWN - HSTPULLDOWN + */ +#define USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK) + +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U) +/*! ENHSTPULLDOWN - ENHSTPULLDOWN + */ +#define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK) + +#define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U) +/*! TX2RXCOUNT - TX2RXCOUNT + */ +#define USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK) + +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U) +/*! ENTX2RXCOUNT - ENTX2RXCOUNT + */ +#define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK) + +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U) +/*! SQUELCHRESETCOUNT - SQUELCHRESETCOUNT + */ +#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK) + +#define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U) +/*! ENSQUELCHRESET - ENSQUELCHRESET + */ +#define USBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK) + +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U) +/*! SQUELCHRESETLENGTH - SQUELCHRESETLENGTH + */ +#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK) + +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U) +/*! HOST_RESUME_DEBUG - HOST_RESUME_DEBUG + */ +#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK) + +#define USBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_SET_CLKGATE_SHIFT (30U) +/*! CLKGATE - CLKGATE + */ +#define USBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK) +/*! @} */ + +/*! @name DEBUG_CLR - USB PHY Debug Register */ +/*! @{ */ + +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U) +/*! OTGIDPIOLOCK - OTGIDPIOLOCK + */ +#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK) + +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U) +/*! DEBUG_INTERFACE_HOLD - DEBUG_INTERFACE_HOLD + */ +#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK) + +#define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U) +/*! HSTPULLDOWN - HSTPULLDOWN + */ +#define USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK) + +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U) +/*! ENHSTPULLDOWN - ENHSTPULLDOWN + */ +#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK) + +#define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U) +/*! TX2RXCOUNT - TX2RXCOUNT + */ +#define USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK) + +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U) +/*! ENTX2RXCOUNT - ENTX2RXCOUNT + */ +#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK) + +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U) +/*! SQUELCHRESETCOUNT - SQUELCHRESETCOUNT + */ +#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK) + +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U) +/*! ENSQUELCHRESET - ENSQUELCHRESET + */ +#define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK) + +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U) +/*! SQUELCHRESETLENGTH - SQUELCHRESETLENGTH + */ +#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK) + +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U) +/*! HOST_RESUME_DEBUG - HOST_RESUME_DEBUG + */ +#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK) + +#define USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U) +/*! CLKGATE - CLKGATE + */ +#define USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK) +/*! @} */ + +/*! @name DEBUG_TOG - USB PHY Debug Register */ +/*! @{ */ + +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U) +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U) +/*! OTGIDPIOLOCK - OTGIDPIOLOCK + */ +#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK) + +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U) +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U) +/*! DEBUG_INTERFACE_HOLD - DEBUG_INTERFACE_HOLD + */ +#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK) + +#define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU) +#define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U) +/*! HSTPULLDOWN - HSTPULLDOWN + */ +#define USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK) + +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U) +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U) +/*! ENHSTPULLDOWN - ENHSTPULLDOWN + */ +#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK) + +#define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U) +#define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U) +/*! TX2RXCOUNT - TX2RXCOUNT + */ +#define USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK) + +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U) +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U) +/*! ENTX2RXCOUNT - ENTX2RXCOUNT + */ +#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK) + +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U) +/*! SQUELCHRESETCOUNT - SQUELCHRESETCOUNT + */ +#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK) + +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U) +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U) +/*! ENSQUELCHRESET - ENSQUELCHRESET + */ +#define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK) + +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U) +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U) +/*! SQUELCHRESETLENGTH - SQUELCHRESETLENGTH + */ +#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK) + +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U) +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U) +/*! HOST_RESUME_DEBUG - HOST_RESUME_DEBUG + */ +#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK) + +#define USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U) +#define USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U) +/*! CLKGATE - CLKGATE + */ +#define USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK) +/*! @} */ + +/*! @name DEBUG0_STATUS - UTMI Debug Status Register 0 */ +/*! @{ */ + +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU) +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U) +/*! LOOP_BACK_FAIL_COUNT - LOOP_BACK_FAIL_COUNT + */ +#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK) + +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U) +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U) +/*! UTMI_RXERROR_FAIL_COUNT - UTMI_RXERROR_FAIL_COUNT + */ +#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK) + +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U) +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U) +/*! SQUELCH_COUNT - SQUELCH_COUNT + */ +#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK) /*! @} */ /*! @name DEBUG1 - UTMI Debug Status Register 1 */ /*! @{ */ + #define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U) #define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U) -/*! ENTAILADJVD +/*! ENTAILADJVD - ENTAILADJVD * 0b00..Delay is nominal * 0b01..Delay is +20% * 0b10..Delay is -20% * 0b11..Delay is -40% */ #define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK) + +#define USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U) +#define USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U) +/*! USB2_REFBIAS_SELFBIASOFF - Set to 1 to disable self bias, 100 us after power up refbias(usb2_refbias_pwd).This can reduce noise on power. + */ +#define USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_MASK) + +#define USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U) +#define USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_SHIFT (16U) +/*! USB2_REFBIAS_PWDVBGUP - Powers down the bandgap detect logic, will affect vbgup on misc1 register. + */ +#define USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_MASK) + +#define USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_MASK (0x20000U) +#define USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_SHIFT (17U) +/*! USB2_REFBIAS_LOWPWR - to be added + */ +#define USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_MASK) + #define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) #define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT (18U) /*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap */ #define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK) + #define USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK (0x600000U) #define USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT (21U) /*! USB2_REFBIAS_TST - Bias current control for usb2_phy @@ -86035,20 +96641,37 @@ typedef struct { /*! @name DEBUG1_SET - UTMI Debug Status Register 1 */ /*! @{ */ + #define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U) #define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U) -/*! ENTAILADJVD - * 0b00..Delay is nominal - * 0b01..Delay is +20% - * 0b10..Delay is -20% - * 0b11..Delay is -40% +/*! ENTAILADJVD - ENTAILADJVD */ #define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK) + +#define USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U) +#define USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U) +/*! USB2_REFBIAS_SELFBIASOFF - Set to 1 to disable self bias, 100 us after power up refbias(usb2_refbias_pwd).This can reduce noise on power. + */ +#define USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_MASK) + +#define USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U) +#define USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_SHIFT (16U) +/*! USB2_REFBIAS_PWDVBGUP - Powers down the bandgap detect logic, will affect vbgup on misc1 register. + */ +#define USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_MASK) + +#define USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_MASK (0x20000U) +#define USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_SHIFT (17U) +/*! USB2_REFBIAS_LOWPWR - to be added + */ +#define USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_MASK) + #define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) #define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT (18U) /*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap */ #define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK) + #define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK (0x600000U) #define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT (21U) /*! USB2_REFBIAS_TST - Bias current control for usb2_phy @@ -86058,20 +96681,37 @@ typedef struct { /*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */ /*! @{ */ + #define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U) #define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U) -/*! ENTAILADJVD - * 0b00..Delay is nominal - * 0b01..Delay is +20% - * 0b10..Delay is -20% - * 0b11..Delay is -40% +/*! ENTAILADJVD - ENTAILADJVD */ #define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK) + +#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U) +#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U) +/*! USB2_REFBIAS_SELFBIASOFF - Set to 1 to disable self bias, 100 us after power up refbias(usb2_refbias_pwd).This can reduce noise on power. + */ +#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_MASK) + +#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U) +#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_SHIFT (16U) +/*! USB2_REFBIAS_PWDVBGUP - Powers down the bandgap detect logic, will affect vbgup on misc1 register. + */ +#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_MASK) + +#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_MASK (0x20000U) +#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_SHIFT (17U) +/*! USB2_REFBIAS_LOWPWR - to be added + */ +#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_MASK) + #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT (18U) /*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap */ #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK) + #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK (0x600000U) #define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT (21U) /*! USB2_REFBIAS_TST - Bias current control for usb2_phy @@ -86081,20 +96721,37 @@ typedef struct { /*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */ /*! @{ */ + #define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U) #define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U) -/*! ENTAILADJVD - * 0b00..Delay is nominal - * 0b01..Delay is +20% - * 0b10..Delay is -20% - * 0b11..Delay is -40% +/*! ENTAILADJVD - ENTAILADJVD */ #define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK) + +#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U) +#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U) +/*! USB2_REFBIAS_SELFBIASOFF - Set to 1 to disable self bias, 100 us after power up refbias(usb2_refbias_pwd).This can reduce noise on power. + */ +#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_MASK) + +#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U) +#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_SHIFT (16U) +/*! USB2_REFBIAS_PWDVBGUP - Powers down the bandgap detect logic, will affect vbgup on misc1 register. + */ +#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_MASK) + +#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_MASK (0x20000U) +#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_SHIFT (17U) +/*! USB2_REFBIAS_LOWPWR - to be added + */ +#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_MASK) + #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U) #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT (18U) /*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap */ #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK) + #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK (0x600000U) #define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT (21U) /*! USB2_REFBIAS_TST - Bias current control for usb2_phy @@ -86104,49 +96761,82 @@ typedef struct { /*! @name VERSION - UTMI RTL Version */ /*! @{ */ + #define USBPHY_VERSION_STEP_MASK (0xFFFFU) #define USBPHY_VERSION_STEP_SHIFT (0U) +/*! STEP - STEP + */ #define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK) + #define USBPHY_VERSION_MINOR_MASK (0xFF0000U) #define USBPHY_VERSION_MINOR_SHIFT (16U) +/*! MINOR - MINOR + */ #define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK) + #define USBPHY_VERSION_MAJOR_MASK (0xFF000000U) #define USBPHY_VERSION_MAJOR_SHIFT (24U) +/*! MAJOR - MAJOR + */ #define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK) /*! @} */ /*! @name PLL_SIC - USB PHY PLL Control/Status Register */ /*! @{ */ + +#define USBPHY_PLL_SIC_PLL_POSTDIV_MASK (0x1CU) +#define USBPHY_PLL_SIC_PLL_POSTDIV_SHIFT (2U) +/*! PLL_POSTDIV - PLL_POSTDIV + */ +#define USBPHY_PLL_SIC_PLL_POSTDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_PLL_POSTDIV_MASK) + #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U) +/*! PLL_EN_USB_CLKS - PLL_EN_USB_CLKS + */ #define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK) + #define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U) +/*! PLL_POWER - PLL_POWER + */ #define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK) + #define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U) +/*! PLL_ENABLE - PLL_ENABLE + */ #define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK) + #define USBPHY_PLL_SIC_PLL_BYPASS_MASK (0x10000U) #define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT (16U) +/*! PLL_BYPASS - PLL_BYPASS + */ #define USBPHY_PLL_SIC_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK) + #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL +/*! REFBIAS_PWD_SEL - REFBIAS_PWD_SEL * 0b0..Selects PLL_POWER to control the reference bias * 0b1..Selects REFBIAS_PWD to control the reference bias. */ #define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK) + #define USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U) /*! REFBIAS_PWD - Power down the reference bias */ #define USBPHY_PLL_SIC_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK) + #define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U) +/*! PLL_REG_ENABLE - PLL_REG_ENABLE + */ #define USBPHY_PLL_SIC_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK) + #define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL +/*! PLL_DIV_SEL - PLL_DIV_SEL * 0b000..Divide by 13 * 0b001..Divide by 15 * 0b010..Divide by 16 @@ -86157,9 +96847,10 @@ typedef struct { * 0b111..Divide by 240 */ #define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK) + #define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK +/*! PLL_LOCK - PLL_LOCK * 0b0..PLL is not currently locked * 0b1..PLL is currently locked */ @@ -86168,162 +96859,202 @@ typedef struct { /*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */ /*! @{ */ + +#define USBPHY_PLL_SIC_SET_PLL_POSTDIV_MASK (0x1CU) +#define USBPHY_PLL_SIC_SET_PLL_POSTDIV_SHIFT (2U) +/*! PLL_POSTDIV - PLL_POSTDIV + */ +#define USBPHY_PLL_SIC_SET_PLL_POSTDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POSTDIV_MASK) + #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U) +/*! PLL_EN_USB_CLKS - PLL_EN_USB_CLKS + */ #define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK) + #define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U) +/*! PLL_POWER - PLL_POWER + */ #define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK) + #define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U) +/*! PLL_ENABLE - PLL_ENABLE + */ #define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK) + #define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK (0x10000U) #define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT (16U) +/*! PLL_BYPASS - PLL_BYPASS + */ #define USBPHY_PLL_SIC_SET_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK) + #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - * 0b0..Selects PLL_POWER to control the reference bias - * 0b1..Selects REFBIAS_PWD to control the reference bias. +/*! REFBIAS_PWD_SEL - REFBIAS_PWD_SEL */ #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK) + #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U) /*! REFBIAS_PWD - Power down the reference bias */ #define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK) + #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U) +/*! PLL_REG_ENABLE - PLL_REG_ENABLE + */ #define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK) + #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - * 0b000..Divide by 13 - * 0b001..Divide by 15 - * 0b010..Divide by 16 - * 0b011..Divide by 20 - * 0b100..Divide by 22 - * 0b101..Divide by 25 - * 0b110..Divide by 30 - * 0b111..Divide by 240 +/*! PLL_DIV_SEL - PLL_DIV_SEL */ #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK) + #define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - * 0b0..PLL is not currently locked - * 0b1..PLL is currently locked +/*! PLL_LOCK - PLL_LOCK */ #define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK) /*! @} */ /*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */ /*! @{ */ + +#define USBPHY_PLL_SIC_CLR_PLL_POSTDIV_MASK (0x1CU) +#define USBPHY_PLL_SIC_CLR_PLL_POSTDIV_SHIFT (2U) +/*! PLL_POSTDIV - PLL_POSTDIV + */ +#define USBPHY_PLL_SIC_CLR_PLL_POSTDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POSTDIV_MASK) + #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U) +/*! PLL_EN_USB_CLKS - PLL_EN_USB_CLKS + */ #define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK) + #define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U) +/*! PLL_POWER - PLL_POWER + */ #define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK) + #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U) +/*! PLL_ENABLE - PLL_ENABLE + */ #define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK) + #define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK (0x10000U) #define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT (16U) +/*! PLL_BYPASS - PLL_BYPASS + */ #define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK) + #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - * 0b0..Selects PLL_POWER to control the reference bias - * 0b1..Selects REFBIAS_PWD to control the reference bias. +/*! REFBIAS_PWD_SEL - REFBIAS_PWD_SEL */ #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK) + #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U) /*! REFBIAS_PWD - Power down the reference bias */ #define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK) + #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U) +/*! PLL_REG_ENABLE - PLL_REG_ENABLE + */ #define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK) + #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - * 0b000..Divide by 13 - * 0b001..Divide by 15 - * 0b010..Divide by 16 - * 0b011..Divide by 20 - * 0b100..Divide by 22 - * 0b101..Divide by 25 - * 0b110..Divide by 30 - * 0b111..Divide by 240 +/*! PLL_DIV_SEL - PLL_DIV_SEL */ #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK) + #define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - * 0b0..PLL is not currently locked - * 0b1..PLL is currently locked +/*! PLL_LOCK - PLL_LOCK */ #define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK) /*! @} */ /*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */ /*! @{ */ + +#define USBPHY_PLL_SIC_TOG_PLL_POSTDIV_MASK (0x1CU) +#define USBPHY_PLL_SIC_TOG_PLL_POSTDIV_SHIFT (2U) +/*! PLL_POSTDIV - PLL_POSTDIV + */ +#define USBPHY_PLL_SIC_TOG_PLL_POSTDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POSTDIV_MASK) + #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U) #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U) +/*! PLL_EN_USB_CLKS - PLL_EN_USB_CLKS + */ #define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK) + #define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U) #define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U) +/*! PLL_POWER - PLL_POWER + */ #define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK) + #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U) #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U) +/*! PLL_ENABLE - PLL_ENABLE + */ #define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK) + #define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK (0x10000U) #define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT (16U) +/*! PLL_BYPASS - PLL_BYPASS + */ #define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK) + #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U) #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U) -/*! REFBIAS_PWD_SEL - * 0b0..Selects PLL_POWER to control the reference bias - * 0b1..Selects REFBIAS_PWD to control the reference bias. +/*! REFBIAS_PWD_SEL - REFBIAS_PWD_SEL */ #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK) + #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U) #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U) /*! REFBIAS_PWD - Power down the reference bias */ #define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK) + #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U) #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U) +/*! PLL_REG_ENABLE - PLL_REG_ENABLE + */ #define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK) + #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U) #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U) -/*! PLL_DIV_SEL - * 0b000..Divide by 13 - * 0b001..Divide by 15 - * 0b010..Divide by 16 - * 0b011..Divide by 20 - * 0b100..Divide by 22 - * 0b101..Divide by 25 - * 0b110..Divide by 30 - * 0b111..Divide by 240 +/*! PLL_DIV_SEL - PLL_DIV_SEL */ #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK) + #define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U) #define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U) -/*! PLL_LOCK - * 0b0..PLL is not currently locked - * 0b1..PLL is currently locked +/*! PLL_LOCK - PLL_LOCK */ #define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK) /*! @} */ /*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */ /*! @{ */ + #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH +/*! VBUSVALID_THRESH - VBUSVALID_THRESH * 0b000..4.0 V * 0b001..4.1 V * 0b010..4.2 V @@ -86334,6 +97065,7 @@ typedef struct { * 0b111..4.7 V */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK) + #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U) /*! VBUS_OVERRIDE_EN - VBUS detect signal override enable @@ -86341,26 +97073,31 @@ typedef struct { * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND */ #define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK) + #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U) /*! SESSEND_OVERRIDE - Override value for SESSEND */ #define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U) /*! BVALID_OVERRIDE - Override value for B-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U) /*! AVALID_OVERRIDE - Override value for A-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U) /*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U) /*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller @@ -86368,6 +97105,7 @@ typedef struct { * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK) + #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U) /*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller @@ -86377,6 +97115,19 @@ typedef struct { * 0b11..Reserved, do not use */ #define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT (11U) +/*! ID_OVERRIDE_EN - TBA + */ +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT (12U) +/*! ID_OVERRIDE - TBA + */ +#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U) /*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID @@ -86384,13 +97135,16 @@ typedef struct { * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. */ #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK) -#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x100000U) + +#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x700000U) #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U) /*! PWRUP_CMPS - Enables the VBUS_VALID comparator - * 0b0..Powers down the VBUS_VALID comparator - * 0b1..Enables the VBUS_VALID comparator (default) + * 0b000..Powers down the VBUS_VALID comparator + * 0b001..Enables the SESS_VALID comparator (default) + * 0b010..Enables the 3Vdetect (default) */ #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK) + #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) /*! DISCHARGE_VBUS - Controls VBUS discharge resistor @@ -86398,281 +97152,283 @@ typedef struct { * 0b1..VBUS discharge resistor is enabled */ #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK) + #define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK (0x80000000U) #define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT (31U) /*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection - * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP - * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP + * 0b0..Disable resistive charger detection resistors on DP and DP + * 0b1..Enable resistive charger detection resistors on DP and DP */ #define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK) /*! @} */ /*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */ /*! @{ */ + #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0 V - * 0b001..4.1 V - * 0b010..4.2 V - * 0b011..4.3 V - * 0b100..4.4 V (Default) - * 0b101..4.5 V - * 0b110..4.6 V - * 0b111..4.7 V +/*! VBUSVALID_THRESH - VBUSVALID_THRESH */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) + #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U) /*! VBUS_OVERRIDE_EN - VBUS detect signal override enable - * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK) + #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U) /*! SESSEND_OVERRIDE - Override value for SESSEND */ #define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U) /*! BVALID_OVERRIDE - Override value for B-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U) /*! AVALID_OVERRIDE - Override value for A-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U) /*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U) /*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller - * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK) + #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U) /*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller - * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b01..Use the Session Valid comparator results for signal reported to the USB controller - * 0b10..Use the Session Valid comparator results for signal reported to the USB controller - * 0b11..Reserved, do not use */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT (11U) +/*! ID_OVERRIDE_EN - TBA + */ +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT (12U) +/*! ID_OVERRIDE - TBA + */ +#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U) /*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID - * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results - * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. */ #define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK) -#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x100000U) + +#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x700000U) #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U) /*! PWRUP_CMPS - Enables the VBUS_VALID comparator - * 0b0..Powers down the VBUS_VALID comparator - * 0b1..Enables the VBUS_VALID comparator (default) */ #define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK) + #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) /*! DISCHARGE_VBUS - Controls VBUS discharge resistor - * 0b0..VBUS discharge resistor is disabled (Default) - * 0b1..VBUS discharge resistor is enabled */ #define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) + #define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK (0x80000000U) #define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT (31U) /*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection - * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP - * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP */ #define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK) /*! @} */ /*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */ /*! @{ */ + #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0 V - * 0b001..4.1 V - * 0b010..4.2 V - * 0b011..4.3 V - * 0b100..4.4 V (Default) - * 0b101..4.5 V - * 0b110..4.6 V - * 0b111..4.7 V +/*! VBUSVALID_THRESH - VBUSVALID_THRESH */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) + #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U) /*! VBUS_OVERRIDE_EN - VBUS detect signal override enable - * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK) + #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U) /*! SESSEND_OVERRIDE - Override value for SESSEND */ #define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U) /*! BVALID_OVERRIDE - Override value for B-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U) /*! AVALID_OVERRIDE - Override value for A-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U) /*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U) /*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller - * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK) + #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U) /*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller - * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b01..Use the Session Valid comparator results for signal reported to the USB controller - * 0b10..Use the Session Valid comparator results for signal reported to the USB controller - * 0b11..Reserved, do not use */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT (11U) +/*! ID_OVERRIDE_EN - TBA + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT (12U) +/*! ID_OVERRIDE - TBA + */ +#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U) /*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID - * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results - * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. */ #define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK) -#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x100000U) + +#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x700000U) #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U) /*! PWRUP_CMPS - Enables the VBUS_VALID comparator - * 0b0..Powers down the VBUS_VALID comparator - * 0b1..Enables the VBUS_VALID comparator (default) */ #define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK) + #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) /*! DISCHARGE_VBUS - Controls VBUS discharge resistor - * 0b0..VBUS discharge resistor is disabled (Default) - * 0b1..VBUS discharge resistor is enabled */ #define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) + #define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK (0x80000000U) #define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT (31U) /*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection - * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP - * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP */ #define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK) /*! @} */ /*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */ /*! @{ */ + #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0 V - * 0b001..4.1 V - * 0b010..4.2 V - * 0b011..4.3 V - * 0b100..4.4 V (Default) - * 0b101..4.5 V - * 0b110..4.6 V - * 0b111..4.7 V +/*! VBUSVALID_THRESH - VBUSVALID_THRESH */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) + #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U) /*! VBUS_OVERRIDE_EN - VBUS detect signal override enable - * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default) - * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK) + #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U) #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U) /*! SESSEND_OVERRIDE - Override value for SESSEND */ #define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U) #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U) /*! BVALID_OVERRIDE - Override value for B-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U) #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U) /*! AVALID_OVERRIDE - Override value for A-Device Session Valid */ #define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U) /*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U) /*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller - * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK) + #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U) /*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller - * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default) - * 0b01..Use the Session Valid comparator results for signal reported to the USB controller - * 0b10..Use the Session Valid comparator results for signal reported to the USB controller - * 0b11..Reserved, do not use */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK (0x800U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT (11U) +/*! ID_OVERRIDE_EN - TBA + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK) + +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK (0x1000U) +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT (12U) +/*! ID_OVERRIDE - TBA + */ +#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK) + #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U) #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U) /*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID - * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results - * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V. */ #define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK) -#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x100000U) + +#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x700000U) #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U) /*! PWRUP_CMPS - Enables the VBUS_VALID comparator - * 0b0..Powers down the VBUS_VALID comparator - * 0b1..Enables the VBUS_VALID comparator (default) */ #define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK) + #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) /*! DISCHARGE_VBUS - Controls VBUS discharge resistor - * 0b0..VBUS discharge resistor is disabled (Default) - * 0b1..VBUS discharge resistor is enabled */ #define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) + #define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK (0x80000000U) #define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT (31U) /*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection - * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP - * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP */ #define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK) /*! @} */ /*! @name USB1_VBUS_DET_STAT - USB PHY VBUS Detector Status Register */ /*! @{ */ + #define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK (0x1U) #define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT (0U) /*! SESSEND - Session End indicator @@ -86680,6 +97436,7 @@ typedef struct { * 0b1..The VBUS voltage is below the Session Valid threshold */ #define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK) + #define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK (0x2U) #define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT (1U) /*! BVALID - B-Device Session Valid status @@ -86687,6 +97444,7 @@ typedef struct { * 0b1..The VBUS voltage is above the Session Valid threshold */ #define USBPHY_USB1_VBUS_DET_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK) + #define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK (0x4U) #define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT (2U) /*! AVALID - A-Device Session Valid status @@ -86694,6 +97452,7 @@ typedef struct { * 0b1..The VBUS voltage is above the Session Valid threshold */ #define USBPHY_USB1_VBUS_DET_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK) + #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U) #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U) /*! VBUS_VALID - VBUS voltage status @@ -86701,6 +97460,7 @@ typedef struct { * 0b1..VBUS is above the comparator threshold */ #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK) + #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U) #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U) /*! VBUS_VALID_3V - VBUS_VALID_3V detector status @@ -86712,62 +97472,73 @@ typedef struct { /*! @name USB1_CHRG_DETECT - USB PHY Charger Detect Control Register */ /*! @{ */ + #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK (0x4U) #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT (2U) +/*! PULLUP_DP - PULLUP_DP + */ #define USBPHY_USB1_CHRG_DETECT_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK) -#define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_MASK (0x800000U) -#define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_SHIFT (23U) -/*! BGR_IBIAS - USB charge detector bias current reference - * 0b0..Bias current is derived from the USB PHY internal current generator. - * 0b1..Bias current is derived from the reference generator of the bandgap. + +#define USBPHY_USB1_CHRG_DETECT_BGR_BIAS_MASK (0x800000U) +#define USBPHY_USB1_CHRG_DETECT_BGR_BIAS_SHIFT (23U) +/*! BGR_BIAS - BGR_BIAS + * 0b0..Use local bias powered from USB1_VBUS for 10uA reference (Default) + * 0b1..Use bandgap bias powered from VREGIN0/VREGIN1 for 10uA reference */ -#define USBPHY_USB1_CHRG_DETECT_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_BGR_IBIAS_MASK) +#define USBPHY_USB1_CHRG_DETECT_BGR_BIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_BGR_BIAS_MASK) /*! @} */ /*! @name USB1_CHRG_DETECT_SET - USB PHY Charger Detect Control Register */ /*! @{ */ + #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK (0x4U) #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT (2U) +/*! PULLUP_DP - PULLUP_DP + */ #define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK) -#define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_MASK (0x800000U) -#define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_SHIFT (23U) -/*! BGR_IBIAS - USB charge detector bias current reference - * 0b0..Bias current is derived from the USB PHY internal current generator. - * 0b1..Bias current is derived from the reference generator of the bandgap. + +#define USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_MASK (0x800000U) +#define USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_SHIFT (23U) +/*! BGR_BIAS - BGR_BIAS */ -#define USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_BGR_IBIAS_MASK) +#define USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_MASK) /*! @} */ /*! @name USB1_CHRG_DETECT_CLR - USB PHY Charger Detect Control Register */ /*! @{ */ + #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK (0x4U) #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT (2U) +/*! PULLUP_DP - PULLUP_DP + */ #define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK) -#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_MASK (0x800000U) -#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_SHIFT (23U) -/*! BGR_IBIAS - USB charge detector bias current reference - * 0b0..Bias current is derived from the USB PHY internal current generator. - * 0b1..Bias current is derived from the reference generator of the bandgap. + +#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_MASK (0x800000U) +#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_SHIFT (23U) +/*! BGR_BIAS - BGR_BIAS */ -#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_BGR_IBIAS_MASK) +#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_MASK) /*! @} */ /*! @name USB1_CHRG_DETECT_TOG - USB PHY Charger Detect Control Register */ /*! @{ */ + #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK (0x4U) #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT (2U) +/*! PULLUP_DP - PULLUP_DP + */ #define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK) -#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_MASK (0x800000U) -#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_SHIFT (23U) -/*! BGR_IBIAS - USB charge detector bias current reference - * 0b0..Bias current is derived from the USB PHY internal current generator. - * 0b1..Bias current is derived from the reference generator of the bandgap. + +#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_MASK (0x800000U) +#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_SHIFT (23U) +/*! BGR_BIAS - BGR_BIAS */ -#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_BGR_IBIAS_MASK) +#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_MASK) /*! @} */ /*! @name USB1_CHRG_DET_STAT - USB PHY Charger Detect Status Register */ /*! @{ */ + #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U) #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U) /*! PLUG_CONTACT - Battery Charging Data Contact Detection phase output @@ -86775,6 +97546,7 @@ typedef struct { * 0b1..A USB cable attachment between the device and host has been detected */ #define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK) + #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U) #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U) /*! CHRG_DETECTED - Battery Charging Primary Detection phase output @@ -86782,20 +97554,23 @@ typedef struct { * 0b1..Charging Port has been detected */ #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK) -#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK (0x4U) -#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT (2U) -/*! DM_STATE - * 0b0..USB_DM pin voltage is < 0.8V - * 0b1..USB_DM pin voltage is > 2.0V + +#define USBPHY_USB1_CHRG_DET_STAT_DN_STATE_MASK (0x4U) +#define USBPHY_USB1_CHRG_DET_STAT_DN_STATE_SHIFT (2U) +/*! DN_STATE - DN_STATE + * 0b0..DN pin voltage is < 0.8V + * 0b1..DN pin voltage is > 2.0V */ -#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK) +#define USBPHY_USB1_CHRG_DET_STAT_DN_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DN_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DN_STATE_MASK) + #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK (0x8U) #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U) -/*! DP_STATE - * 0b0..USB_DP pin voltage is < 0.8V - * 0b1..USB_DP pin voltage is > 2.0V +/*! DP_STATE - DP_STATE + * 0b0..DP pin voltage is < 0.8V + * 0b1..DP pin voltage is > 2.0V */ #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK) + #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U) #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U) /*! SECDET_DCP - Battery Charging Secondary Detection phase output @@ -86807,434 +97582,740 @@ typedef struct { /*! @name ANACTRL - USB PHY Analog Control Register */ /*! @{ */ + #define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. +/*! DEV_PULLDOWN - DEV_PULLDOWN + * 0b0..The 15kohm nominal pulldowns on the DP and DN pinsare disabled in device mode. + * 0b1..The 15kohm nominal pulldowns on the DP and DN pinsare enabled in device mode. */ #define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK) /*! @} */ /*! @name ANACTRL_SET - USB PHY Analog Control Register */ /*! @{ */ + #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. +/*! DEV_PULLDOWN - DEV_PULLDOWN */ #define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK) /*! @} */ /*! @name ANACTRL_CLR - USB PHY Analog Control Register */ /*! @{ */ + #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. +/*! DEV_PULLDOWN - DEV_PULLDOWN */ #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK) /*! @} */ /*! @name ANACTRL_TOG - USB PHY Analog Control Register */ /*! @{ */ + #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U) #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U) -/*! DEV_PULLDOWN - * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode. - * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode. +/*! DEV_PULLDOWN - DEV_PULLDOWN */ #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK) /*! @} */ /*! @name USB1_LOOPBACK - USB PHY Loopback Control/Status Register */ /*! @{ */ + #define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK (0x1U) #define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT (0U) +/*! UTMI_TESTSTART - UTMI_TESTSTART + */ #define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK) + #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK (0x2U) #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT (1U) +/*! UTMI_DIG_TST0 - UTMI_DIG_TST0 + */ #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK) + #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK (0x4U) #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT (2U) +/*! UTMI_DIG_TST1 - UTMI_DIG_TST1 + */ #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK) + #define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK (0x8U) #define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT (3U) +/*! TSTI_TX_HS_MODE - TSTI_TX_HS_MODE + */ #define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK) + #define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK (0x10U) #define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT (4U) +/*! TSTI_TX_LS_MODE - TSTI_TX_LS_MODE + */ #define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK) + #define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK (0x20U) #define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT (5U) +/*! TSTI_TX_EN - TSTI_TX_EN + */ #define USBPHY_USB1_LOOPBACK_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK) + #define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK (0x40U) #define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT (6U) +/*! TSTI_TX_HIZ - TSTI_TX_HIZ + */ #define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK) + #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK (0x80U) #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT (7U) +/*! UTMO_DIG_TST0 - UTMO_DIG_TST0 + */ #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK) + #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK (0x100U) #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT (8U) +/*! UTMO_DIG_TST1 - UTMO_DIG_TST1 + */ #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK) + #define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK (0x8000U) #define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT (15U) +/*! TSTI_HSFS_MODE_EN - TSTI_HSFS_MODE_EN + */ #define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK) + #define USBPHY_USB1_LOOPBACK_TSTPKT_MASK (0xFF0000U) #define USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT (16U) +/*! TSTPKT - TSTPKT + */ #define USBPHY_USB1_LOOPBACK_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTPKT_MASK) /*! @} */ /*! @name USB1_LOOPBACK_SET - USB PHY Loopback Control/Status Register */ /*! @{ */ + #define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U) #define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT (0U) +/*! UTMI_TESTSTART - UTMI_TESTSTART + */ #define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK) + #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK (0x2U) #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT (1U) +/*! UTMI_DIG_TST0 - UTMI_DIG_TST0 + */ #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK) + #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK (0x4U) #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT (2U) +/*! UTMI_DIG_TST1 - UTMI_DIG_TST1 + */ #define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK) + #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK (0x8U) #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT (3U) +/*! TSTI_TX_HS_MODE - TSTI_TX_HS_MODE + */ #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK) + #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK (0x10U) #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT (4U) +/*! TSTI_TX_LS_MODE - TSTI_TX_LS_MODE + */ #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK) + #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK (0x20U) #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT (5U) +/*! TSTI_TX_EN - TSTI_TX_EN + */ #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK) + #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK (0x40U) #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT (6U) +/*! TSTI_TX_HIZ - TSTI_TX_HIZ + */ #define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK) + #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK (0x80U) #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT (7U) +/*! UTMO_DIG_TST0 - UTMO_DIG_TST0 + */ #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK) + #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK (0x100U) #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT (8U) +/*! UTMO_DIG_TST1 - UTMO_DIG_TST1 + */ #define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK) + #define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK (0x8000U) #define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT (15U) +/*! TSTI_HSFS_MODE_EN - TSTI_HSFS_MODE_EN + */ #define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK) + #define USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK (0xFF0000U) #define USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT (16U) +/*! TSTPKT - TSTPKT + */ #define USBPHY_USB1_LOOPBACK_SET_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK) /*! @} */ /*! @name USB1_LOOPBACK_CLR - USB PHY Loopback Control/Status Register */ /*! @{ */ + #define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U) #define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT (0U) +/*! UTMI_TESTSTART - UTMI_TESTSTART + */ #define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK) + #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK (0x2U) #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT (1U) +/*! UTMI_DIG_TST0 - UTMI_DIG_TST0 + */ #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK) + #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK (0x4U) #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT (2U) +/*! UTMI_DIG_TST1 - UTMI_DIG_TST1 + */ #define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK) + #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK (0x8U) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT (3U) +/*! TSTI_TX_HS_MODE - TSTI_TX_HS_MODE + */ #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK) + #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK (0x10U) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT (4U) +/*! TSTI_TX_LS_MODE - TSTI_TX_LS_MODE + */ #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK) + #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK (0x20U) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT (5U) +/*! TSTI_TX_EN - TSTI_TX_EN + */ #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK) + #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK (0x40U) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT (6U) +/*! TSTI_TX_HIZ - TSTI_TX_HIZ + */ #define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK) + #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK (0x80U) #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT (7U) +/*! UTMO_DIG_TST0 - UTMO_DIG_TST0 + */ #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK) + #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK (0x100U) #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT (8U) +/*! UTMO_DIG_TST1 - UTMO_DIG_TST1 + */ #define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK) + #define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK (0x8000U) #define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT (15U) +/*! TSTI_HSFS_MODE_EN - TSTI_HSFS_MODE_EN + */ #define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK) + #define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK (0xFF0000U) #define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT (16U) +/*! TSTPKT - TSTPKT + */ #define USBPHY_USB1_LOOPBACK_CLR_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK) /*! @} */ /*! @name USB1_LOOPBACK_TOG - USB PHY Loopback Control/Status Register */ /*! @{ */ + #define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U) #define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT (0U) +/*! UTMI_TESTSTART - UTMI_TESTSTART + */ #define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK) + #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK (0x2U) #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT (1U) +/*! UTMI_DIG_TST0 - UTMI_DIG_TST0 + */ #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK) + #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK (0x4U) #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT (2U) +/*! UTMI_DIG_TST1 - UTMI_DIG_TST1 + */ #define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK) + #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK (0x8U) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT (3U) +/*! TSTI_TX_HS_MODE - TSTI_TX_HS_MODE + */ #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK) + #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK (0x10U) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT (4U) +/*! TSTI_TX_LS_MODE - TSTI_TX_LS_MODE + */ #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK) + #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK (0x20U) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT (5U) +/*! TSTI_TX_EN - TSTI_TX_EN + */ #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK) + #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK (0x40U) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT (6U) +/*! TSTI_TX_HIZ - TSTI_TX_HIZ + */ #define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK) + #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK (0x80U) #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT (7U) +/*! UTMO_DIG_TST0 - UTMO_DIG_TST0 + */ #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK) + #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK (0x100U) #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT (8U) +/*! UTMO_DIG_TST1 - UTMO_DIG_TST1 + */ #define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK) + #define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK (0x8000U) #define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT (15U) +/*! TSTI_HSFS_MODE_EN - TSTI_HSFS_MODE_EN + */ #define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK) + #define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK (0xFF0000U) #define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT (16U) +/*! TSTPKT - TSTPKT + */ #define USBPHY_USB1_LOOPBACK_TOG_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK) /*! @} */ /*! @name USB1_LOOPBACK_HSFSCNT - USB PHY Loopback Packet Number Select Register */ /*! @{ */ + #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK (0xFFFFU) #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT (0U) +/*! TSTI_HS_NUMBER - TSTI_HS_NUMBER + */ #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK) + #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK (0xFFFF0000U) #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT (16U) +/*! TSTI_FS_NUMBER - TSTI_FS_NUMBER + */ #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK) /*! @} */ /*! @name USB1_LOOPBACK_HSFSCNT_SET - USB PHY Loopback Packet Number Select Register */ /*! @{ */ + #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK (0xFFFFU) #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT (0U) +/*! TSTI_HS_NUMBER - TSTI_HS_NUMBER + */ #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK) + #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK (0xFFFF0000U) #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT (16U) +/*! TSTI_FS_NUMBER - TSTI_FS_NUMBER + */ #define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK) /*! @} */ /*! @name USB1_LOOPBACK_HSFSCNT_CLR - USB PHY Loopback Packet Number Select Register */ /*! @{ */ + #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK (0xFFFFU) #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT (0U) +/*! TSTI_HS_NUMBER - TSTI_HS_NUMBER + */ #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK) + #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK (0xFFFF0000U) #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT (16U) +/*! TSTI_FS_NUMBER - TSTI_FS_NUMBER + */ #define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK) /*! @} */ /*! @name USB1_LOOPBACK_HSFSCNT_TOG - USB PHY Loopback Packet Number Select Register */ /*! @{ */ + #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK (0xFFFFU) #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT (0U) +/*! TSTI_HS_NUMBER - TSTI_HS_NUMBER + */ #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK) + #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK (0xFFFF0000U) #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT (16U) +/*! TSTI_FS_NUMBER - TSTI_FS_NUMBER + */ #define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK) /*! @} */ /*! @name TRIM_OVERRIDE_EN - USB PHY Trim Override Enable Register */ /*! @{ */ + #define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U) +/*! TRIM_DIV_SEL_OVERRIDE - TRIM_DIV_SEL_OVERRIDE + */ #define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U) +/*! TRIM_ENV_TAIL_ADJ_VD_OVERRIDE - TRIM_ENV_TAIL_ADJ_VD_OVERRIDE + */ #define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U) +/*! TRIM_TX_D_CAL_OVERRIDE - TRIM_TX_D_CAL_OVERRIDE + */ #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U) +/*! TRIM_TX_CAL45DP_OVERRIDE - TRIM_TX_CAL45DP_OVERRIDE + */ #define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK) -#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U) -#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U) -#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U) +#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U) +/*! TRIM_TX_CAL45DN_OVERRIDE - TRIM_TX_CAL45DN_OVERRIDE + */ +#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U) /*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment. */ #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U) /*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control */ #define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U) +/*! TRIM_USB2_REFBIAS_VBGADJ - TRIM_USB2_REFBIAS_VBGADJ + */ #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_MASK (0x6000U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_SHIFT (13U) +/*! TRIM_USB2_REFBIAS_TST - TRIM_USB2_REFBIAS_TST + */ #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U) +/*! TRIM_PLL_CTRL0_DIV_SEL - TRIM_PLL_CTRL0_DIV_SEL + */ #define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U) +/*! TRIM_USB_REG_ENV_TAIL_ADJ_VD - TRIM_USB_REG_ENV_TAIL_ADJ_VD + */ #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT (20U) +/*! TRIM_USBPHY_TX_D_CAL - TRIM_USBPHY_TX_D_CAL + */ #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U) #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U) +/*! TRIM_USBPHY_TX_CAL45DP - TRIM_USBPHY_TX_CAL45DP + */ #define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK) -#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U) -#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U) -#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U) +#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U) +/*! TRIM_USBPHY_TX_CAL45DN - TRIM_USBPHY_TX_CAL45DN + */ +#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_MASK) /*! @} */ /*! @name TRIM_OVERRIDE_EN_SET - USB PHY Trim Override Enable Register */ /*! @{ */ + #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U) +/*! TRIM_DIV_SEL_OVERRIDE - TRIM_DIV_SEL_OVERRIDE + */ #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U) +/*! TRIM_ENV_TAIL_ADJ_VD_OVERRIDE - TRIM_ENV_TAIL_ADJ_VD_OVERRIDE + */ #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U) +/*! TRIM_TX_D_CAL_OVERRIDE - TRIM_TX_D_CAL_OVERRIDE + */ #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U) +/*! TRIM_TX_CAL45DP_OVERRIDE - TRIM_TX_CAL45DP_OVERRIDE + */ #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK) -#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U) -#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U) -#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U) +#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U) +/*! TRIM_TX_CAL45DN_OVERRIDE - TRIM_TX_CAL45DN_OVERRIDE + */ +#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U) /*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment. */ #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U) /*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control */ #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U) +/*! TRIM_USB2_REFBIAS_VBGADJ - TRIM_USB2_REFBIAS_VBGADJ + */ #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_MASK (0x6000U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_SHIFT (13U) +/*! TRIM_USB2_REFBIAS_TST - TRIM_USB2_REFBIAS_TST + */ #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U) +/*! TRIM_PLL_CTRL0_DIV_SEL - TRIM_PLL_CTRL0_DIV_SEL + */ #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U) +/*! TRIM_USB_REG_ENV_TAIL_ADJ_VD - TRIM_USB_REG_ENV_TAIL_ADJ_VD + */ #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT (20U) +/*! TRIM_USBPHY_TX_D_CAL - TRIM_USBPHY_TX_D_CAL + */ #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U) #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U) +/*! TRIM_USBPHY_TX_CAL45DP - TRIM_USBPHY_TX_CAL45DP + */ #define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK) -#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U) -#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U) -#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U) +#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U) +/*! TRIM_USBPHY_TX_CAL45DN - TRIM_USBPHY_TX_CAL45DN + */ +#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_MASK) /*! @} */ /*! @name TRIM_OVERRIDE_EN_CLR - USB PHY Trim Override Enable Register */ /*! @{ */ + #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U) +/*! TRIM_DIV_SEL_OVERRIDE - TRIM_DIV_SEL_OVERRIDE + */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U) +/*! TRIM_ENV_TAIL_ADJ_VD_OVERRIDE - TRIM_ENV_TAIL_ADJ_VD_OVERRIDE + */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U) +/*! TRIM_TX_D_CAL_OVERRIDE - TRIM_TX_D_CAL_OVERRIDE + */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U) +/*! TRIM_TX_CAL45DP_OVERRIDE - TRIM_TX_CAL45DP_OVERRIDE + */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK) -#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U) -#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U) -#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U) +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U) +/*! TRIM_TX_CAL45DN_OVERRIDE - TRIM_TX_CAL45DN_OVERRIDE + */ +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U) /*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment. */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U) /*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U) +/*! TRIM_USB2_REFBIAS_VBGADJ - TRIM_USB2_REFBIAS_VBGADJ + */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_MASK (0x6000U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_SHIFT (13U) +/*! TRIM_USB2_REFBIAS_TST - TRIM_USB2_REFBIAS_TST + */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U) +/*! TRIM_PLL_CTRL0_DIV_SEL - TRIM_PLL_CTRL0_DIV_SEL + */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U) +/*! TRIM_USB_REG_ENV_TAIL_ADJ_VD - TRIM_USB_REG_ENV_TAIL_ADJ_VD + */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT (20U) +/*! TRIM_USBPHY_TX_D_CAL - TRIM_USBPHY_TX_D_CAL + */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U) #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U) +/*! TRIM_USBPHY_TX_CAL45DP - TRIM_USBPHY_TX_CAL45DP + */ #define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK) -#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U) -#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U) -#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U) +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U) +/*! TRIM_USBPHY_TX_CAL45DN - TRIM_USBPHY_TX_CAL45DN + */ +#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_MASK) /*! @} */ /*! @name TRIM_OVERRIDE_EN_TOG - USB PHY Trim Override Enable Register */ /*! @{ */ + #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U) +/*! TRIM_DIV_SEL_OVERRIDE - TRIM_DIV_SEL_OVERRIDE + */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U) +/*! TRIM_ENV_TAIL_ADJ_VD_OVERRIDE - TRIM_ENV_TAIL_ADJ_VD_OVERRIDE + */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U) +/*! TRIM_TX_D_CAL_OVERRIDE - TRIM_TX_D_CAL_OVERRIDE + */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U) +/*! TRIM_TX_CAL45DP_OVERRIDE - TRIM_TX_CAL45DP_OVERRIDE + */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK) -#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U) -#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U) -#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U) +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U) +/*! TRIM_TX_CAL45DN_OVERRIDE - TRIM_TX_CAL45DN_OVERRIDE + */ +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U) /*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment. */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U) /*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U) +/*! TRIM_USB2_REFBIAS_VBGADJ - TRIM_USB2_REFBIAS_VBGADJ + */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_MASK (0x6000U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_SHIFT (13U) +/*! TRIM_USB2_REFBIAS_TST - TRIM_USB2_REFBIAS_TST + */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U) +/*! TRIM_PLL_CTRL0_DIV_SEL - TRIM_PLL_CTRL0_DIV_SEL + */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U) +/*! TRIM_USB_REG_ENV_TAIL_ADJ_VD - TRIM_USB_REG_ENV_TAIL_ADJ_VD + */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT (20U) +/*! TRIM_USBPHY_TX_D_CAL - TRIM_USBPHY_TX_D_CAL + */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK) + #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U) #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U) +/*! TRIM_USBPHY_TX_CAL45DP - TRIM_USBPHY_TX_CAL45DP + */ #define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK) -#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U) -#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U) -#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_MASK) + +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U) +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U) +/*! TRIM_USBPHY_TX_CAL45DN - TRIM_USBPHY_TX_CAL45DN + */ +#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_MASK) /*! @} */ @@ -87258,421 +98339,18 @@ typedef struct { #define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 } /** Interrupt vectors for the USBPHY peripheral type */ #define USBPHY_IRQS { NotAvail_IRQn, USBPHY1_IRQn, USBPHY2_IRQn } +/* Backward compatibility */ +#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK +#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT +#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x) +#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK +#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT +#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x) -/*! - * @} - */ /* end of group USBPHY_Peripheral_Access_Layer */ - - -/* ---------------------------------------------------------------------------- - -- USB_ANALOG Peripheral Access Layer - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_ANALOG_Peripheral_Access_Layer USB_ANALOG Peripheral Access Layer - * @{ - */ - -/** USB_ANALOG - Register Layout Typedef */ -typedef struct { - uint8_t RESERVED_0[416]; - struct { /* offset: 0x1A0, array step: 0x60 */ - __IO uint32_t VBUS_DETECT; /**< USB VBUS Detect Register, array offset: 0x1A0, array step: 0x60 */ - __IO uint32_t VBUS_DETECT_SET; /**< USB VBUS Detect Register, array offset: 0x1A4, array step: 0x60 */ - __IO uint32_t VBUS_DETECT_CLR; /**< USB VBUS Detect Register, array offset: 0x1A8, array step: 0x60 */ - __IO uint32_t VBUS_DETECT_TOG; /**< USB VBUS Detect Register, array offset: 0x1AC, array step: 0x60 */ - __IO uint32_t CHRG_DETECT; /**< USB Charger Detect Register, array offset: 0x1B0, array step: 0x60 */ - __IO uint32_t CHRG_DETECT_SET; /**< USB Charger Detect Register, array offset: 0x1B4, array step: 0x60 */ - __IO uint32_t CHRG_DETECT_CLR; /**< USB Charger Detect Register, array offset: 0x1B8, array step: 0x60 */ - __IO uint32_t CHRG_DETECT_TOG; /**< USB Charger Detect Register, array offset: 0x1BC, array step: 0x60 */ - __I uint32_t VBUS_DETECT_STAT; /**< USB VBUS Detect Status Register, array offset: 0x1C0, array step: 0x60 */ - uint8_t RESERVED_0[12]; - __I uint32_t CHRG_DETECT_STAT; /**< USB Charger Detect Status Register, array offset: 0x1D0, array step: 0x60 */ - uint8_t RESERVED_1[28]; - __IO uint32_t MISC; /**< USB Misc Register, array offset: 0x1F0, array step: 0x60 */ - __IO uint32_t MISC_SET; /**< USB Misc Register, array offset: 0x1F4, array step: 0x60 */ - __IO uint32_t MISC_CLR; /**< USB Misc Register, array offset: 0x1F8, array step: 0x60 */ - __IO uint32_t MISC_TOG; /**< USB Misc Register, array offset: 0x1FC, array step: 0x60 */ - } INSTANCE[2]; - __I uint32_t DIGPROG; /**< Chip Silicon Version, offset: 0x260 */ -} USB_ANALOG_Type; - -/* ---------------------------------------------------------------------------- - -- USB_ANALOG Register Masks - ---------------------------------------------------------------------------- */ - -/*! - * @addtogroup USB_ANALOG_Register_Masks USB_ANALOG Register Masks - * @{ - */ - -/*! @name VBUS_DETECT - USB VBUS Detect Register */ -/*! @{ */ -#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U) -#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0V - * 0b001..4.1V - * 0b010..4.2V - * 0b011..4.3V - * 0b100..4.4V (default) - * 0b101..4.5V - * 0b110..4.6V - * 0b111..4.7V - */ -#define USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_THRESH_MASK) -#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) -#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT (20U) -#define USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_VBUSVALID_PWRUP_CMPS_MASK) -#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U) -#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U) -#define USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_DISCHARGE_VBUS_MASK) -#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK (0x8000000U) -#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT (27U) -#define USB_ANALOG_VBUS_DETECT_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CHARGE_VBUS_MASK) -/*! @} */ - -/* The count of USB_ANALOG_VBUS_DETECT */ -#define USB_ANALOG_VBUS_DETECT_COUNT (2U) - -/*! @name VBUS_DETECT_SET - USB VBUS Detect Register */ -/*! @{ */ -#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U) -#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0V - * 0b001..4.1V - * 0b010..4.2V - * 0b011..4.3V - * 0b100..4.4V (default) - * 0b101..4.5V - * 0b110..4.6V - * 0b111..4.7V - */ -#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK) -#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) -#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT (20U) -#define USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_VBUSVALID_PWRUP_CMPS_MASK) -#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U) -#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U) -#define USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK) -#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK (0x8000000U) -#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT (27U) -#define USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_SET_CHARGE_VBUS_MASK) -/*! @} */ - -/* The count of USB_ANALOG_VBUS_DETECT_SET */ -#define USB_ANALOG_VBUS_DETECT_SET_COUNT (2U) - -/*! @name VBUS_DETECT_CLR - USB VBUS Detect Register */ -/*! @{ */ -#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U) -#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0V - * 0b001..4.1V - * 0b010..4.2V - * 0b011..4.3V - * 0b100..4.4V (default) - * 0b101..4.5V - * 0b110..4.6V - * 0b111..4.7V - */ -#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK) -#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) -#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT (20U) -#define USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_VBUSVALID_PWRUP_CMPS_MASK) -#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U) -#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U) -#define USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK) -#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK (0x8000000U) -#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT (27U) -#define USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_CLR_CHARGE_VBUS_MASK) -/*! @} */ - -/* The count of USB_ANALOG_VBUS_DETECT_CLR */ -#define USB_ANALOG_VBUS_DETECT_CLR_COUNT (2U) - -/*! @name VBUS_DETECT_TOG - USB VBUS Detect Register */ -/*! @{ */ -#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U) -#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U) -/*! VBUSVALID_THRESH - * 0b000..4.0V - * 0b001..4.1V - * 0b010..4.2V - * 0b011..4.3V - * 0b100..4.4V (default) - * 0b101..4.5V - * 0b110..4.6V - * 0b111..4.7V - */ -#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK) -#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK (0x100000U) -#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT (20U) -#define USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_VBUSVALID_PWRUP_CMPS_MASK) -#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U) -#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U) -#define USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK) -#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK (0x8000000U) -#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT (27U) -#define USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_SHIFT)) & USB_ANALOG_VBUS_DETECT_TOG_CHARGE_VBUS_MASK) -/*! @} */ - -/* The count of USB_ANALOG_VBUS_DETECT_TOG */ -#define USB_ANALOG_VBUS_DETECT_TOG_COUNT (2U) - -/*! @name CHRG_DETECT - USB Charger Detect Register */ -/*! @{ */ -#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK (0x40000U) -#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT (18U) -/*! CHK_CONTACT - * 0b0..Do not check the contact of USB plug. - * 0b1..Check whether the USB plug has been in contact with each other - */ -#define USB_ANALOG_CHRG_DETECT_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CONTACT_MASK) -#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK (0x80000U) -#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT (19U) -/*! CHK_CHRG_B - * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. - * 0b1..Do not check whether a charger is connected to the USB port. - */ -#define USB_ANALOG_CHRG_DETECT_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CHK_CHRG_B_MASK) -#define USB_ANALOG_CHRG_DETECT_EN_B_MASK (0x100000U) -#define USB_ANALOG_CHRG_DETECT_EN_B_SHIFT (20U) -/*! EN_B - * 0b0..Enable the charger detector. - * 0b1..Disable the charger detector. - */ -#define USB_ANALOG_CHRG_DETECT_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_EN_B_MASK) -/*! @} */ - -/* The count of USB_ANALOG_CHRG_DETECT */ -#define USB_ANALOG_CHRG_DETECT_COUNT (2U) - -/*! @name CHRG_DETECT_SET - USB Charger Detect Register */ -/*! @{ */ -#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK (0x40000U) -#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT (18U) -/*! CHK_CONTACT - * 0b0..Do not check the contact of USB plug. - * 0b1..Check whether the USB plug has been in contact with each other - */ -#define USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CONTACT_MASK) -#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK (0x80000U) -#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT (19U) -/*! CHK_CHRG_B - * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. - * 0b1..Do not check whether a charger is connected to the USB port. - */ -#define USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_CHK_CHRG_B_MASK) -#define USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK (0x100000U) -#define USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT (20U) -/*! EN_B - * 0b0..Enable the charger detector. - * 0b1..Disable the charger detector. - */ -#define USB_ANALOG_CHRG_DETECT_SET_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_SET_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_SET_EN_B_MASK) -/*! @} */ - -/* The count of USB_ANALOG_CHRG_DETECT_SET */ -#define USB_ANALOG_CHRG_DETECT_SET_COUNT (2U) - -/*! @name CHRG_DETECT_CLR - USB Charger Detect Register */ -/*! @{ */ -#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK (0x40000U) -#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT (18U) -/*! CHK_CONTACT - * 0b0..Do not check the contact of USB plug. - * 0b1..Check whether the USB plug has been in contact with each other - */ -#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CONTACT_MASK) -#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK (0x80000U) -#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT (19U) -/*! CHK_CHRG_B - * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. - * 0b1..Do not check whether a charger is connected to the USB port. - */ -#define USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_CHK_CHRG_B_MASK) -#define USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK (0x100000U) -#define USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT (20U) -/*! EN_B - * 0b0..Enable the charger detector. - * 0b1..Disable the charger detector. - */ -#define USB_ANALOG_CHRG_DETECT_CLR_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_CLR_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_CLR_EN_B_MASK) -/*! @} */ - -/* The count of USB_ANALOG_CHRG_DETECT_CLR */ -#define USB_ANALOG_CHRG_DETECT_CLR_COUNT (2U) - -/*! @name CHRG_DETECT_TOG - USB Charger Detect Register */ -/*! @{ */ -#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK (0x40000U) -#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT (18U) -/*! CHK_CONTACT - * 0b0..Do not check the contact of USB plug. - * 0b1..Check whether the USB plug has been in contact with each other - */ -#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CONTACT_MASK) -#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK (0x80000U) -#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT (19U) -/*! CHK_CHRG_B - * 0b0..Check whether a charger (either a dedicated charger or a host charger) is connected to USB port. - * 0b1..Do not check whether a charger is connected to the USB port. - */ -#define USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_CHK_CHRG_B_MASK) -#define USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK (0x100000U) -#define USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT (20U) -/*! EN_B - * 0b0..Enable the charger detector. - * 0b1..Disable the charger detector. - */ -#define USB_ANALOG_CHRG_DETECT_TOG_EN_B(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_TOG_EN_B_SHIFT)) & USB_ANALOG_CHRG_DETECT_TOG_EN_B_MASK) -/*! @} */ - -/* The count of USB_ANALOG_CHRG_DETECT_TOG */ -#define USB_ANALOG_CHRG_DETECT_TOG_COUNT (2U) - -/*! @name VBUS_DETECT_STAT - USB VBUS Detect Status Register */ -/*! @{ */ -#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK (0x1U) -#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT (0U) -#define USB_ANALOG_VBUS_DETECT_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_SESSEND_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_SESSEND_MASK) -#define USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK (0x2U) -#define USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT (1U) -#define USB_ANALOG_VBUS_DETECT_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_BVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_BVALID_MASK) -#define USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK (0x4U) -#define USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT (2U) -#define USB_ANALOG_VBUS_DETECT_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_AVALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_AVALID_MASK) -#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK (0x8U) -#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT (3U) -#define USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_SHIFT)) & USB_ANALOG_VBUS_DETECT_STAT_VBUS_VALID_MASK) -/*! @} */ - -/* The count of USB_ANALOG_VBUS_DETECT_STAT */ -#define USB_ANALOG_VBUS_DETECT_STAT_COUNT (2U) - -/*! @name CHRG_DETECT_STAT - USB Charger Detect Status Register */ -/*! @{ */ -#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK (0x1U) -#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT (0U) -/*! PLUG_CONTACT - * 0b0..The USB plug has not made contact. - * 0b1..The USB plug has made good contact. - */ -#define USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_PLUG_CONTACT_MASK) -#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK (0x2U) -#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT (1U) -/*! CHRG_DETECTED - * 0b0..The USB port is not connected to a charger. - * 0b1..A charger (either a dedicated charger or a host charger) is connected to the USB port. - */ -#define USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_CHRG_DETECTED_MASK) -#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK (0x4U) -#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT (2U) -#define USB_ANALOG_CHRG_DETECT_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DM_STATE_MASK) -#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK (0x8U) -#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT (3U) -#define USB_ANALOG_CHRG_DETECT_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_SHIFT)) & USB_ANALOG_CHRG_DETECT_STAT_DP_STATE_MASK) -/*! @} */ - -/* The count of USB_ANALOG_CHRG_DETECT_STAT */ -#define USB_ANALOG_CHRG_DETECT_STAT_COUNT (2U) - -/*! @name MISC - USB Misc Register */ -/*! @{ */ -#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK (0x1U) -#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT (0U) -#define USB_ANALOG_MISC_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_HS_USE_EXTERNAL_R_MASK) -#define USB_ANALOG_MISC_EN_DEGLITCH_MASK (0x2U) -#define USB_ANALOG_MISC_EN_DEGLITCH_SHIFT (1U) -#define USB_ANALOG_MISC_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_EN_DEGLITCH_MASK) -#define USB_ANALOG_MISC_EN_CLK_UTMI_MASK (0x40000000U) -#define USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT (30U) -#define USB_ANALOG_MISC_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_EN_CLK_UTMI_MASK) -/*! @} */ - -/* The count of USB_ANALOG_MISC */ -#define USB_ANALOG_MISC_COUNT (2U) - -/*! @name MISC_SET - USB Misc Register */ -/*! @{ */ -#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK (0x1U) -#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT (0U) -#define USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_SET_HS_USE_EXTERNAL_R_MASK) -#define USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK (0x2U) -#define USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT (1U) -#define USB_ANALOG_MISC_SET_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_SET_EN_DEGLITCH_MASK) -#define USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK (0x40000000U) -#define USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT (30U) -#define USB_ANALOG_MISC_SET_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_SET_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_SET_EN_CLK_UTMI_MASK) -/*! @} */ - -/* The count of USB_ANALOG_MISC_SET */ -#define USB_ANALOG_MISC_SET_COUNT (2U) - -/*! @name MISC_CLR - USB Misc Register */ -/*! @{ */ -#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK (0x1U) -#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT (0U) -#define USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_CLR_HS_USE_EXTERNAL_R_MASK) -#define USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK (0x2U) -#define USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT (1U) -#define USB_ANALOG_MISC_CLR_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_CLR_EN_DEGLITCH_MASK) -#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK (0x40000000U) -#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT (30U) -#define USB_ANALOG_MISC_CLR_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_CLR_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_CLR_EN_CLK_UTMI_MASK) -/*! @} */ - -/* The count of USB_ANALOG_MISC_CLR */ -#define USB_ANALOG_MISC_CLR_COUNT (2U) - -/*! @name MISC_TOG - USB Misc Register */ -/*! @{ */ -#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK (0x1U) -#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT (0U) -#define USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_SHIFT)) & USB_ANALOG_MISC_TOG_HS_USE_EXTERNAL_R_MASK) -#define USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK (0x2U) -#define USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT (1U) -#define USB_ANALOG_MISC_TOG_EN_DEGLITCH(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_DEGLITCH_SHIFT)) & USB_ANALOG_MISC_TOG_EN_DEGLITCH_MASK) -#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK (0x40000000U) -#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT (30U) -#define USB_ANALOG_MISC_TOG_EN_CLK_UTMI(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_MISC_TOG_EN_CLK_UTMI_SHIFT)) & USB_ANALOG_MISC_TOG_EN_CLK_UTMI_MASK) -/*! @} */ - -/* The count of USB_ANALOG_MISC_TOG */ -#define USB_ANALOG_MISC_TOG_COUNT (2U) - -/*! @name DIGPROG - Chip Silicon Version */ -/*! @{ */ -#define USB_ANALOG_DIGPROG_MINOR_MASK (0xFFU) -#define USB_ANALOG_DIGPROG_MINOR_SHIFT (0U) -#define USB_ANALOG_DIGPROG_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_MINOR_SHIFT)) & USB_ANALOG_DIGPROG_MINOR_MASK) -#define USB_ANALOG_DIGPROG_MAJOR_MASK (0xFFFF00U) -#define USB_ANALOG_DIGPROG_MAJOR_SHIFT (8U) -#define USB_ANALOG_DIGPROG_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USB_ANALOG_DIGPROG_MAJOR_SHIFT)) & USB_ANALOG_DIGPROG_MAJOR_MASK) -/*! @} */ - - -/*! - * @} - */ /* end of group USB_ANALOG_Register_Masks */ - - -/* USB_ANALOG - Peripheral instance base addresses */ -/** Peripheral USB_ANALOG base address */ -#define USB_ANALOG_BASE (0x40C84000u) -/** Peripheral USB_ANALOG base pointer */ -#define USB_ANALOG ((USB_ANALOG_Type *)USB_ANALOG_BASE) -/** Array initializer of USB_ANALOG peripheral base addresses */ -#define USB_ANALOG_BASE_ADDRS { USB_ANALOG_BASE } -/** Array initializer of USB_ANALOG peripheral base pointers */ -#define USB_ANALOG_BASE_PTRS { USB_ANALOG } /*! * @} - */ /* end of group USB_ANALOG_Peripheral_Access_Layer */ + */ /* end of group USBPHY_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- @@ -87721,31 +98399,6 @@ typedef struct { __IO uint32_t MMC_BOOT; /**< MMC Boot, offset: 0xC4 */ __IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */ __IO uint32_t TUNING_CTRL; /**< Tuning Control, offset: 0xCC */ - uint8_t RESERVED_4[48]; - __I uint32_t CQVER; /**< Command Queuing Version, offset: 0x100 */ - __I uint32_t CQCAP; /**< Command Queuing Capabilities, offset: 0x104 */ - __IO uint32_t CQCFG; /**< Command Queuing Configuration, offset: 0x108 */ - __IO uint32_t CQCTL; /**< Command Queuing Control, offset: 0x10C */ - __IO uint32_t CQIS; /**< Command Queuing Interrupt Status, offset: 0x110 */ - __IO uint32_t CQISTE; /**< Command Queuing Interrupt Status Enable, offset: 0x114 */ - __IO uint32_t CQISGE; /**< Command Queuing Interrupt Signal Enable, offset: 0x118 */ - __IO uint32_t CQIC; /**< Command Queuing Interrupt Coalescing, offset: 0x11C */ - __IO uint32_t CQTDLBA; /**< Command Queuing Task Descriptor List Base Address, offset: 0x120 */ - __IO uint32_t CQTDLBAU; /**< Command Queuing Task Descriptor List Base Address Upper 32 Bits, offset: 0x124 */ - __IO uint32_t CQTDBR; /**< Command Queuing Task Doorbell, offset: 0x128 */ - __IO uint32_t CQTCN; /**< Command Queuing Task Completion Notification, offset: 0x12C */ - __I uint32_t CQDQS; /**< Command Queuing Device Queue Status, offset: 0x130 */ - __I uint32_t CQDPT; /**< Command Queuing Device Pending Tasks, offset: 0x134 */ - __IO uint32_t CQTCLR; /**< Command Queuing Task Clear, offset: 0x138 */ - uint8_t RESERVED_5[4]; - __IO uint32_t CQSSC1; /**< Command Queuing Send Status Configuration 1, offset: 0x140 */ - __IO uint32_t CQSSC2; /**< Command Queuing Send Status Configuration 2, offset: 0x144 */ - __I uint32_t CQCRDCT; /**< Command Queuing Command Response for Direct-Command Task, offset: 0x148 */ - uint8_t RESERVED_6[4]; - __IO uint32_t CQRMEM; /**< Command Queuing Response Mode Error Mask, offset: 0x150 */ - __I uint32_t CQTERRI; /**< Command Queuing Task Error Information, offset: 0x154 */ - __I uint32_t CQCRI; /**< Command Queuing Command Response Index, offset: 0x158 */ - __I uint32_t CQCRA; /**< Command Queuing Command Response Argument, offset: 0x15C */ } USDHC_Type; /* ---------------------------------------------------------------------------- @@ -87759,6 +98412,7 @@ typedef struct { /*! @name DS_ADDR - DMA System Address */ /*! @{ */ + #define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU) #define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U) /*! DS_ADDR - System address @@ -87768,6 +98422,7 @@ typedef struct { /*! @name BLK_ATT - Block Attributes */ /*! @{ */ + #define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU) #define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U) /*! BLKSIZE - Transfer block size @@ -87782,6 +98437,7 @@ typedef struct { * 0b0000000000000..No data transfer */ #define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK) + #define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U) #define USDHC_BLK_ATT_BLKCNT_SHIFT (16U) /*! BLKCNT - Blocks count for current transfer @@ -87795,6 +98451,7 @@ typedef struct { /*! @name CMD_ARG - Command Argument */ /*! @{ */ + #define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU) #define USDHC_CMD_ARG_CMDARG_SHIFT (0U) /*! CMDARG - Command argument @@ -87804,6 +98461,7 @@ typedef struct { /*! @name CMD_XFR_TYP - Command Transfer Type */ /*! @{ */ + #define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U) #define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U) /*! RSPTYP - Response type select @@ -87813,6 +98471,7 @@ typedef struct { * 0b11..Response length 48, check busy after response */ #define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK) + #define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U) #define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U) /*! CCCEN - Command CRC check enable @@ -87820,6 +98479,7 @@ typedef struct { * 0b0..Disables command CRC check */ #define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK) + #define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U) #define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U) /*! CICEN - Command index check enable @@ -87827,6 +98487,7 @@ typedef struct { * 0b0..Disable command index check */ #define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK) + #define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U) #define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U) /*! DPSEL - Data present select @@ -87834,6 +98495,7 @@ typedef struct { * 0b0..No data present */ #define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK) + #define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U) #define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U) /*! CMDTYP - Command type @@ -87843,6 +98505,7 @@ typedef struct { * 0b00..Normal other commands */ #define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK) + #define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U) #define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U) /*! CMDINX - Command index @@ -87852,6 +98515,7 @@ typedef struct { /*! @name CMD_RSP0 - Command Response0 */ /*! @{ */ + #define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U) /*! CMDRSP0 - Command response 0 @@ -87861,6 +98525,7 @@ typedef struct { /*! @name CMD_RSP1 - Command Response1 */ /*! @{ */ + #define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U) /*! CMDRSP1 - Command response 1 @@ -87870,6 +98535,7 @@ typedef struct { /*! @name CMD_RSP2 - Command Response2 */ /*! @{ */ + #define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U) /*! CMDRSP2 - Command response 2 @@ -87879,6 +98545,7 @@ typedef struct { /*! @name CMD_RSP3 - Command Response3 */ /*! @{ */ + #define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU) #define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U) /*! CMDRSP3 - Command response 3 @@ -87888,6 +98555,7 @@ typedef struct { /*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */ /*! @{ */ + #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU) #define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U) /*! DATCONT - Data content @@ -87897,6 +98565,7 @@ typedef struct { /*! @name PRES_STATE - Present State */ /*! @{ */ + #define USDHC_PRES_STATE_CIHB_MASK (0x1U) #define USDHC_PRES_STATE_CIHB_SHIFT (0U) /*! CIHB - Command inhibit (CMD) @@ -87904,13 +98573,15 @@ typedef struct { * 0b0..Can issue command using only CMD line */ #define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK) + #define USDHC_PRES_STATE_CDIHB_MASK (0x2U) #define USDHC_PRES_STATE_CDIHB_SHIFT (1U) -/*! CDIHB - Command inhibit (DATA) +/*! CDIHB - Command Inhibit Data (DATA) * 0b1..Cannot issue command that uses the DATA line * 0b0..Can issue command that uses the DATA line */ #define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK) + #define USDHC_PRES_STATE_DLA_MASK (0x4U) #define USDHC_PRES_STATE_DLA_SHIFT (2U) /*! DLA - Data line active @@ -87918,6 +98589,7 @@ typedef struct { * 0b0..DATA line inactive */ #define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK) + #define USDHC_PRES_STATE_SDSTB_MASK (0x8U) #define USDHC_PRES_STATE_SDSTB_SHIFT (3U) /*! SDSTB - SD clock stable @@ -87925,6 +98597,7 @@ typedef struct { * 0b0..Clock is changing frequency and not stable. */ #define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK) + #define USDHC_PRES_STATE_IPGOFF_MASK (0x10U) #define USDHC_PRES_STATE_IPGOFF_SHIFT (4U) /*! IPGOFF - Peripheral clock gated off internally @@ -87932,6 +98605,7 @@ typedef struct { * 0b0..Peripheral clock is active. */ #define USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK) + #define USDHC_PRES_STATE_HCKOFF_MASK (0x20U) #define USDHC_PRES_STATE_HCKOFF_SHIFT (5U) /*! HCKOFF - HCLK gated off internally @@ -87939,6 +98613,7 @@ typedef struct { * 0b0..HCLK is active. */ #define USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK) + #define USDHC_PRES_STATE_PEROFF_MASK (0x40U) #define USDHC_PRES_STATE_PEROFF_SHIFT (6U) /*! PEROFF - IPG_PERCLK gated off internally @@ -87946,6 +98621,7 @@ typedef struct { * 0b0..IPG_PERCLK is active. */ #define USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK) + #define USDHC_PRES_STATE_SDOFF_MASK (0x80U) #define USDHC_PRES_STATE_SDOFF_SHIFT (7U) /*! SDOFF - SD clock gated off internally @@ -87953,6 +98629,7 @@ typedef struct { * 0b0..SD clock is active. */ #define USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK) + #define USDHC_PRES_STATE_WTA_MASK (0x100U) #define USDHC_PRES_STATE_WTA_SHIFT (8U) /*! WTA - Write transfer active @@ -87960,6 +98637,7 @@ typedef struct { * 0b0..No valid data */ #define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK) + #define USDHC_PRES_STATE_RTA_MASK (0x200U) #define USDHC_PRES_STATE_RTA_SHIFT (9U) /*! RTA - Read transfer active @@ -87967,6 +98645,7 @@ typedef struct { * 0b0..No valid data */ #define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK) + #define USDHC_PRES_STATE_BWEN_MASK (0x400U) #define USDHC_PRES_STATE_BWEN_SHIFT (10U) /*! BWEN - Buffer write enable @@ -87974,6 +98653,7 @@ typedef struct { * 0b0..Write disable */ #define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK) + #define USDHC_PRES_STATE_BREN_MASK (0x800U) #define USDHC_PRES_STATE_BREN_SHIFT (11U) /*! BREN - Buffer read enable @@ -87981,20 +98661,23 @@ typedef struct { * 0b0..Read disable */ #define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK) + #define USDHC_PRES_STATE_RTR_MASK (0x1000U) #define USDHC_PRES_STATE_RTR_SHIFT (12U) -/*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode and EMMC HS200 mode) +/*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode,and EMMC HS200 mode) * 0b1..Sampling clock needs re-tuning * 0b0..Fixed or well tuned sampling clock */ #define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK) + #define USDHC_PRES_STATE_TSCD_MASK (0x8000U) #define USDHC_PRES_STATE_TSCD_SHIFT (15U) -/*! TSCD - Tape select change done +/*! TSCD - Tap select change done * 0b1..Delay cell select change is finished. * 0b0..Delay cell select change is not finished. */ #define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK) + #define USDHC_PRES_STATE_CINST_MASK (0x10000U) #define USDHC_PRES_STATE_CINST_SHIFT (16U) /*! CINST - Card inserted @@ -88002,6 +98685,7 @@ typedef struct { * 0b0..Power on reset or no card */ #define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK) + #define USDHC_PRES_STATE_CDPL_MASK (0x40000U) #define USDHC_PRES_STATE_CDPL_SHIFT (18U) /*! CDPL - Card detect pin level @@ -88009,6 +98693,7 @@ typedef struct { * 0b0..No card present (CD_B = 1) */ #define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK) + #define USDHC_PRES_STATE_WPSPL_MASK (0x80000U) #define USDHC_PRES_STATE_WPSPL_SHIFT (19U) /*! WPSPL - Write protect switch pin level @@ -88016,11 +98701,13 @@ typedef struct { * 0b0..Write protected (WP = 1) */ #define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK) + #define USDHC_PRES_STATE_CLSL_MASK (0x800000U) #define USDHC_PRES_STATE_CLSL_SHIFT (23U) /*! CLSL - CMD line signal level */ #define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK) + #define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U) #define USDHC_PRES_STATE_DLSL_SHIFT (24U) /*! DLSL - DATA[7:0] line signal level @@ -88038,6 +98725,7 @@ typedef struct { /*! @name PROT_CTRL - Protocol Control */ /*! @{ */ + #define USDHC_PROT_CTRL_DTW_MASK (0x6U) #define USDHC_PROT_CTRL_DTW_SHIFT (1U) /*! DTW - Data transfer width @@ -88047,6 +98735,7 @@ typedef struct { * 0b11..Reserved */ #define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK) + #define USDHC_PROT_CTRL_D3CD_MASK (0x8U) #define USDHC_PROT_CTRL_D3CD_SHIFT (3U) /*! D3CD - DATA3 as card detection pin @@ -88054,6 +98743,7 @@ typedef struct { * 0b0..DATA3 does not monitor card insertion */ #define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK) + #define USDHC_PROT_CTRL_EMODE_MASK (0x30U) #define USDHC_PROT_CTRL_EMODE_SHIFT (4U) /*! EMODE - Endian mode @@ -88063,6 +98753,7 @@ typedef struct { * 0b11..Reserved */ #define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK) + #define USDHC_PROT_CTRL_CDTL_MASK (0x40U) #define USDHC_PROT_CTRL_CDTL_SHIFT (6U) /*! CDTL - Card detect test level @@ -88070,6 +98761,7 @@ typedef struct { * 0b0..Card detect test level is 0, no card inserted */ #define USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK) + #define USDHC_PROT_CTRL_CDSS_MASK (0x80U) #define USDHC_PROT_CTRL_CDSS_SHIFT (7U) /*! CDSS - Card detect signal selection @@ -88077,6 +98769,7 @@ typedef struct { * 0b0..Card detection level is selected (for normal purpose). */ #define USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK) + #define USDHC_PROT_CTRL_DMASEL_MASK (0x300U) #define USDHC_PROT_CTRL_DMASEL_SHIFT (8U) /*! DMASEL - DMA select @@ -88086,6 +98779,7 @@ typedef struct { * 0b11..Reserved */ #define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK) + #define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U) #define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U) /*! SABGREQ - Stop at block gap request @@ -88093,6 +98787,7 @@ typedef struct { * 0b0..Transfer */ #define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK) + #define USDHC_PROT_CTRL_CREQ_MASK (0x20000U) #define USDHC_PROT_CTRL_CREQ_SHIFT (17U) /*! CREQ - Continue request @@ -88100,6 +98795,7 @@ typedef struct { * 0b0..No effect */ #define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK) + #define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U) #define USDHC_PROT_CTRL_RWCTL_SHIFT (18U) /*! RWCTL - Read wait control @@ -88107,6 +98803,7 @@ typedef struct { * 0b0..Disables read wait control and stop SD clock at block gap when SABGREQ field is set */ #define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK) + #define USDHC_PROT_CTRL_IABG_MASK (0x80000U) #define USDHC_PROT_CTRL_IABG_SHIFT (19U) /*! IABG - Interrupt at block gap @@ -88114,11 +98811,13 @@ typedef struct { * 0b0..Disables interrupt at block gap */ #define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK) + #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U) #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U) /*! RD_DONE_NO_8CLK - Read performed number 8 clock */ #define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK) + #define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U) #define USDHC_PROT_CTRL_WECINT_SHIFT (24U) /*! WECINT - Wakeup event enable on card interrupt @@ -88126,6 +98825,7 @@ typedef struct { * 0b0..Disables wakeup event enable on card interrupt */ #define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK) + #define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U) #define USDHC_PROT_CTRL_WECINS_SHIFT (25U) /*! WECINS - Wakeup event enable on SD card insertion @@ -88133,6 +98833,7 @@ typedef struct { * 0b0..Disable wakeup event enable on SD card insertion */ #define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK) + #define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U) #define USDHC_PROT_CTRL_WECRM_SHIFT (26U) /*! WECRM - Wakeup event enable on SD card removal @@ -88140,6 +98841,7 @@ typedef struct { * 0b0..Disables wakeup event enable on SD card removal */ #define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK) + #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U) #define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U) /*! NON_EXACT_BLK_RD - Non-exact block read @@ -88151,6 +98853,7 @@ typedef struct { /*! @name SYS_CTRL - System Control */ /*! @{ */ + #define USDHC_SYS_CTRL_DVS_MASK (0xF0U) #define USDHC_SYS_CTRL_DVS_SHIFT (4U) /*! DVS - Divisor @@ -88160,11 +98863,13 @@ typedef struct { * 0b1111..Divide-by-16 */ #define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK) + #define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U) #define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U) /*! SDCLKFS - SDCLK frequency select */ #define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK) + #define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U) #define USDHC_SYS_CTRL_DTOCV_SHIFT (16U) /*! DTOCV - Data timeout counter value @@ -88186,11 +98891,13 @@ typedef struct { * 0b0000..SDCLK x 2 14 */ #define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK) + #define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U) #define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U) /*! IPP_RST_N - Hardware reset */ #define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK) + #define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U) #define USDHC_SYS_CTRL_RSTA_SHIFT (24U) /*! RSTA - Software reset for all @@ -88198,6 +98905,7 @@ typedef struct { * 0b0..No reset */ #define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK) + #define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U) #define USDHC_SYS_CTRL_RSTC_SHIFT (25U) /*! RSTC - Software reset for CMD line @@ -88205,6 +98913,7 @@ typedef struct { * 0b0..No reset */ #define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK) + #define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U) #define USDHC_SYS_CTRL_RSTD_SHIFT (26U) /*! RSTD - Software reset for data line @@ -88212,11 +98921,13 @@ typedef struct { * 0b0..No reset */ #define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK) + #define USDHC_SYS_CTRL_INITA_MASK (0x8000000U) #define USDHC_SYS_CTRL_INITA_SHIFT (27U) /*! INITA - Initialization active */ #define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK) + #define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U) #define USDHC_SYS_CTRL_RSTT_SHIFT (28U) /*! RSTT - Reset tuning @@ -88226,6 +98937,7 @@ typedef struct { /*! @name INT_STATUS - Interrupt Status */ /*! @{ */ + #define USDHC_INT_STATUS_CC_MASK (0x1U) #define USDHC_INT_STATUS_CC_SHIFT (0U) /*! CC - Command complete @@ -88233,6 +98945,7 @@ typedef struct { * 0b0..Command not complete */ #define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK) + #define USDHC_INT_STATUS_TC_MASK (0x2U) #define USDHC_INT_STATUS_TC_SHIFT (1U) /*! TC - Transfer complete @@ -88240,6 +98953,7 @@ typedef struct { * 0b0..Transfer does not complete */ #define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK) + #define USDHC_INT_STATUS_BGE_MASK (0x4U) #define USDHC_INT_STATUS_BGE_SHIFT (2U) /*! BGE - Block gap event @@ -88247,6 +98961,7 @@ typedef struct { * 0b0..No block gap event */ #define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK) + #define USDHC_INT_STATUS_DINT_MASK (0x8U) #define USDHC_INT_STATUS_DINT_SHIFT (3U) /*! DINT - DMA interrupt @@ -88254,6 +98969,7 @@ typedef struct { * 0b0..No DMA interrupt */ #define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK) + #define USDHC_INT_STATUS_BWR_MASK (0x10U) #define USDHC_INT_STATUS_BWR_SHIFT (4U) /*! BWR - Buffer write ready @@ -88261,6 +98977,7 @@ typedef struct { * 0b0..Not ready to write buffer */ #define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK) + #define USDHC_INT_STATUS_BRR_MASK (0x20U) #define USDHC_INT_STATUS_BRR_SHIFT (5U) /*! BRR - Buffer read ready @@ -88268,6 +98985,7 @@ typedef struct { * 0b0..Not ready to read buffer */ #define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK) + #define USDHC_INT_STATUS_CINS_MASK (0x40U) #define USDHC_INT_STATUS_CINS_SHIFT (6U) /*! CINS - Card insertion @@ -88275,6 +98993,7 @@ typedef struct { * 0b0..Card state unstable or removed */ #define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK) + #define USDHC_INT_STATUS_CRM_MASK (0x80U) #define USDHC_INT_STATUS_CRM_SHIFT (7U) /*! CRM - Card removal @@ -88282,6 +99001,7 @@ typedef struct { * 0b0..Card state unstable or inserted */ #define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK) + #define USDHC_INT_STATUS_CINT_MASK (0x100U) #define USDHC_INT_STATUS_CINT_SHIFT (8U) /*! CINT - Card interrupt @@ -88289,6 +99009,7 @@ typedef struct { * 0b0..No card interrupt */ #define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK) + #define USDHC_INT_STATUS_RTE_MASK (0x1000U) #define USDHC_INT_STATUS_RTE_SHIFT (12U) /*! RTE - Re-tuning event: (only for SD3.0 SDR104 mode and EMMC HS200 mode) @@ -88296,16 +99017,13 @@ typedef struct { * 0b0..Re-tuning is not required. */ #define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK) -#define USDHC_INT_STATUS_TP_MASK (0x2000U) -#define USDHC_INT_STATUS_TP_SHIFT (13U) + +#define USDHC_INT_STATUS_TP_MASK (0x4000U) +#define USDHC_INT_STATUS_TP_SHIFT (14U) /*! TP - Tuning pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode) */ #define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK) -#define USDHC_INT_STATUS_CQI_MASK (0x4000U) -#define USDHC_INT_STATUS_CQI_SHIFT (14U) -/*! CQI - Command queuing interrupt - */ -#define USDHC_INT_STATUS_CQI(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CQI_SHIFT)) & USDHC_INT_STATUS_CQI_MASK) + #define USDHC_INT_STATUS_CTOE_MASK (0x10000U) #define USDHC_INT_STATUS_CTOE_SHIFT (16U) /*! CTOE - Command timeout error @@ -88313,6 +99031,7 @@ typedef struct { * 0b0..No error */ #define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK) + #define USDHC_INT_STATUS_CCE_MASK (0x20000U) #define USDHC_INT_STATUS_CCE_SHIFT (17U) /*! CCE - Command CRC error @@ -88320,6 +99039,7 @@ typedef struct { * 0b0..No error */ #define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK) + #define USDHC_INT_STATUS_CEBE_MASK (0x40000U) #define USDHC_INT_STATUS_CEBE_SHIFT (18U) /*! CEBE - Command end bit error @@ -88327,6 +99047,7 @@ typedef struct { * 0b0..No error */ #define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK) + #define USDHC_INT_STATUS_CIE_MASK (0x80000U) #define USDHC_INT_STATUS_CIE_SHIFT (19U) /*! CIE - Command index error @@ -88334,6 +99055,7 @@ typedef struct { * 0b0..No error */ #define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK) + #define USDHC_INT_STATUS_DTOE_MASK (0x100000U) #define USDHC_INT_STATUS_DTOE_SHIFT (20U) /*! DTOE - Data timeout error @@ -88341,6 +99063,7 @@ typedef struct { * 0b0..No error */ #define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK) + #define USDHC_INT_STATUS_DCE_MASK (0x200000U) #define USDHC_INT_STATUS_DCE_SHIFT (21U) /*! DCE - Data CRC error @@ -88348,6 +99071,7 @@ typedef struct { * 0b0..No error */ #define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK) + #define USDHC_INT_STATUS_DEBE_MASK (0x400000U) #define USDHC_INT_STATUS_DEBE_SHIFT (22U) /*! DEBE - Data end bit error @@ -88355,6 +99079,7 @@ typedef struct { * 0b0..No error */ #define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK) + #define USDHC_INT_STATUS_AC12E_MASK (0x1000000U) #define USDHC_INT_STATUS_AC12E_SHIFT (24U) /*! AC12E - Auto CMD12 error @@ -88362,11 +99087,13 @@ typedef struct { * 0b0..No error */ #define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK) + #define USDHC_INT_STATUS_TNE_MASK (0x4000000U) #define USDHC_INT_STATUS_TNE_SHIFT (26U) /*! TNE - Tuning error: (only for SD3.0 SDR104 mode and EMMC HS200 mode) */ #define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK) + #define USDHC_INT_STATUS_DMAE_MASK (0x10000000U) #define USDHC_INT_STATUS_DMAE_SHIFT (28U) /*! DMAE - DMA error @@ -88378,6 +99105,7 @@ typedef struct { /*! @name INT_STATUS_EN - Interrupt Status Enable */ /*! @{ */ + #define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U) #define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U) /*! CCSEN - Command complete status enable @@ -88385,6 +99113,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK) + #define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U) #define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U) /*! TCSEN - Transfer complete status enable @@ -88392,6 +99121,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK) + #define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U) #define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U) /*! BGESEN - Block gap event status enable @@ -88399,6 +99129,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK) + #define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U) #define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U) /*! DINTSEN - DMA interrupt status enable @@ -88406,6 +99137,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK) + #define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U) #define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U) /*! BWRSEN - Buffer write ready status enable @@ -88413,6 +99145,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK) + #define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U) #define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U) /*! BRRSEN - Buffer read ready status enable @@ -88420,6 +99153,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK) + #define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U) #define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U) /*! CINSSEN - Card insertion status enable @@ -88427,6 +99161,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK) + #define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U) #define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U) /*! CRMSEN - Card removal status enable @@ -88434,6 +99169,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK) + #define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U) #define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U) /*! CINTSEN - Card interrupt status enable @@ -88441,6 +99177,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK) + #define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U) #define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U) /*! RTESEN - Re-tuning event status enable @@ -88448,20 +99185,15 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK) -#define USDHC_INT_STATUS_EN_TPSEN_MASK (0x2000U) -#define USDHC_INT_STATUS_EN_TPSEN_SHIFT (13U) + +#define USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U) +#define USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U) /*! TPSEN - Tuning pass status enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK) -#define USDHC_INT_STATUS_EN_CQISEN_MASK (0x4000U) -#define USDHC_INT_STATUS_EN_CQISEN_SHIFT (14U) -/*! CQISEN - Command queuing status enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_STATUS_EN_CQISEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CQISEN_SHIFT)) & USDHC_INT_STATUS_EN_CQISEN_MASK) + #define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U) #define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U) /*! CTOESEN - Command timeout error status enable @@ -88469,6 +99201,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK) + #define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U) #define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U) /*! CCESEN - Command CRC error status enable @@ -88476,6 +99209,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK) + #define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U) #define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U) /*! CEBESEN - Command end bit error status enable @@ -88483,6 +99217,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK) + #define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U) #define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U) /*! CIESEN - Command index error status enable @@ -88490,6 +99225,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK) + #define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U) #define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U) /*! DTOESEN - Data timeout error status enable @@ -88497,6 +99233,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK) + #define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U) #define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U) /*! DCESEN - Data CRC error status enable @@ -88504,6 +99241,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK) + #define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U) #define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U) /*! DEBESEN - Data end bit error status enable @@ -88511,6 +99249,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK) + #define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U) #define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U) /*! AC12ESEN - Auto CMD12 error status enable @@ -88518,6 +99257,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK) + #define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U) #define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U) /*! TNESEN - Tuning error status enable @@ -88525,6 +99265,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK) + #define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U) #define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U) /*! DMAESEN - DMA error status enable @@ -88536,6 +99277,7 @@ typedef struct { /*! @name INT_SIGNAL_EN - Interrupt Signal Enable */ /*! @{ */ + #define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U) #define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U) /*! CCIEN - Command complete interrupt enable @@ -88543,6 +99285,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK) + #define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U) #define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U) /*! TCIEN - Transfer complete interrupt enable @@ -88550,6 +99293,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK) + #define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U) #define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U) /*! BGEIEN - Block gap event interrupt enable @@ -88557,6 +99301,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK) + #define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U) #define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U) /*! DINTIEN - DMA interrupt enable @@ -88564,6 +99309,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK) + #define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U) #define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U) /*! BWRIEN - Buffer write ready interrupt enable @@ -88571,6 +99317,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK) + #define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U) #define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U) /*! BRRIEN - Buffer read ready interrupt enable @@ -88578,6 +99325,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK) + #define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U) #define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U) /*! CINSIEN - Card insertion interrupt enable @@ -88585,6 +99333,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK) + #define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U) #define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U) /*! CRMIEN - Card removal interrupt enable @@ -88592,6 +99341,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK) + #define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U) #define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U) /*! CINTIEN - Card interrupt enable @@ -88599,6 +99349,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK) + #define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U) #define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U) /*! RTEIEN - Re-tuning event interrupt enable @@ -88606,20 +99357,15 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK) -#define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x2000U) -#define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (13U) -/*! TPIEN - Tuning pass interrupt enable + +#define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U) +#define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U) +/*! TPIEN - Tuning Pass interrupt enable * 0b1..Enabled * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK) -#define USDHC_INT_SIGNAL_EN_CQIIEN_MASK (0x4000U) -#define USDHC_INT_SIGNAL_EN_CQIIEN_SHIFT (14U) -/*! CQIIEN - Command queuing signal enable - * 0b1..Enabled - * 0b0..Masked - */ -#define USDHC_INT_SIGNAL_EN_CQIIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CQIIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CQIIEN_MASK) + #define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U) #define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U) /*! CTOEIEN - Command timeout error interrupt enable @@ -88627,6 +99373,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK) + #define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U) #define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U) /*! CCEIEN - Command CRC error interrupt enable @@ -88634,6 +99381,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK) + #define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U) #define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U) /*! CEBEIEN - Command end bit error interrupt enable @@ -88641,6 +99389,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK) + #define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U) #define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U) /*! CIEIEN - Command index error interrupt enable @@ -88648,6 +99397,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK) + #define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U) #define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U) /*! DTOEIEN - Data timeout error interrupt enable @@ -88655,6 +99405,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK) + #define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U) #define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U) /*! DCEIEN - Data CRC error interrupt enable @@ -88662,6 +99413,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK) + #define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U) #define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U) /*! DEBEIEN - Data end bit error interrupt enable @@ -88669,6 +99421,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK) + #define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U) #define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U) /*! AC12EIEN - Auto CMD12 error interrupt enable @@ -88676,6 +99429,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK) + #define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U) #define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U) /*! TNEIEN - Tuning error interrupt enable @@ -88683,6 +99437,7 @@ typedef struct { * 0b0..Masked */ #define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK) + #define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U) #define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U) /*! DMAEIEN - DMA error interrupt enable @@ -88694,6 +99449,7 @@ typedef struct { /*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */ /*! @{ */ + #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U) /*! AC12NE - Auto CMD12 not executed @@ -88701,6 +99457,7 @@ typedef struct { * 0b0..Executed */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK) + #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U) /*! AC12TOE - Auto CMD12 / 23 timeout error @@ -88708,6 +99465,7 @@ typedef struct { * 0b0..No error */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK) + #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U) /*! AC12EBE - Auto CMD12 / 23 end bit error @@ -88715,6 +99473,7 @@ typedef struct { * 0b0..No error */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK) + #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U) /*! AC12CE - Auto CMD12 / 23 CRC error @@ -88722,6 +99481,7 @@ typedef struct { * 0b0..No CRC error */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK) + #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U) #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U) /*! AC12IE - Auto CMD12 / 23 index error @@ -88729,6 +99489,7 @@ typedef struct { * 0b0..No error */ #define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK) + #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U) #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U) /*! CNIBAC12E - Command not issued by Auto CMD12 error @@ -88736,11 +99497,15 @@ typedef struct { * 0b0..No error */ #define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK) + #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U) #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U) /*! EXECUTE_TUNING - Execute tuning + * 0b1..Start tuning procedure + * 0b0..Tuning procedure is aborted */ #define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK) + #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U) #define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U) /*! SMP_CLK_SEL - Sample clock select @@ -88752,42 +99517,33 @@ typedef struct { /*! @name HOST_CTRL_CAP - Host Controller Capabilities */ /*! @{ */ + #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U) #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U) /*! SDR50_SUPPORT - SDR50 support */ #define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK) + #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U) #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U) /*! SDR104_SUPPORT - SDR104 support */ #define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK) + #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U) #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U) /*! DDR50_SUPPORT - DDR50 support */ #define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK) -#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U) -#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U) -/*! TIME_COUNT_RETUNING - Time counter for retuning - */ -#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK) + #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U) #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U) /*! USE_TUNING_SDR50 - Use Tuning for SDR50 - * 0b1..SDR50 requires tuning. - * 0b0..SDR does not require tuning. + * 0b1..SDR50 supports tuning + * 0b0..SDR50 does not support tuning */ #define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK) -#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U) -#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U) -/*! RETUNING_MODE - Retuning Mode - * 0b00..Mode 1 - * 0b01..Mode 2 - * 0b10..Mode 3 - * 0b11..Reserved - */ -#define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK) + #define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U) #define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U) /*! MBL - Max block length @@ -88797,6 +99553,7 @@ typedef struct { * 0b011..4096 bytes */ #define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK) + #define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U) #define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U) /*! ADMAS - ADMA support @@ -88804,6 +99561,7 @@ typedef struct { * 0b0..Advanced DMA not supported */ #define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK) + #define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U) #define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U) /*! HSS - High speed support @@ -88811,6 +99569,7 @@ typedef struct { * 0b0..High speed not supported */ #define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK) + #define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U) #define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U) /*! DMAS - DMA support @@ -88818,6 +99577,7 @@ typedef struct { * 0b0..DMA not supported */ #define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK) + #define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U) #define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U) /*! SRS - Suspend / resume support @@ -88825,6 +99585,7 @@ typedef struct { * 0b0..Not supported */ #define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK) + #define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U) #define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U) /*! VS33 - Voltage support 3.3 V @@ -88832,6 +99593,7 @@ typedef struct { * 0b0..3.3 V not supported */ #define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK) + #define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U) #define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U) /*! VS30 - Voltage support 3.0 V @@ -88839,6 +99601,7 @@ typedef struct { * 0b0..3.0 V not supported */ #define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK) + #define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U) #define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U) /*! VS18 - Voltage support 1.8 V @@ -88850,11 +99613,13 @@ typedef struct { /*! @name WTMK_LVL - Watermark Level */ /*! @{ */ + #define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU) #define USDHC_WTMK_LVL_RD_WML_SHIFT (0U) /*! RD_WML - Read watermark level */ #define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK) + #define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U) #define USDHC_WTMK_LVL_WR_WML_SHIFT (16U) /*! WR_WML - Write watermark level @@ -88864,6 +99629,7 @@ typedef struct { /*! @name MIX_CTRL - Mixer Control */ /*! @{ */ + #define USDHC_MIX_CTRL_DMAEN_MASK (0x1U) #define USDHC_MIX_CTRL_DMAEN_SHIFT (0U) /*! DMAEN - DMA enable @@ -88871,6 +99637,7 @@ typedef struct { * 0b0..Disable */ #define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK) + #define USDHC_MIX_CTRL_BCEN_MASK (0x2U) #define USDHC_MIX_CTRL_BCEN_SHIFT (1U) /*! BCEN - Block count enable @@ -88878,6 +99645,7 @@ typedef struct { * 0b0..Disable */ #define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK) + #define USDHC_MIX_CTRL_AC12EN_MASK (0x4U) #define USDHC_MIX_CTRL_AC12EN_SHIFT (2U) /*! AC12EN - Auto CMD12 enable @@ -88885,11 +99653,13 @@ typedef struct { * 0b0..Disable */ #define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK) + #define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U) #define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U) /*! DDR_EN - Dual data rate mode selection */ #define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK) + #define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U) #define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U) /*! DTDSEL - Data transfer direction select @@ -88897,6 +99667,7 @@ typedef struct { * 0b0..Write (Host to card) */ #define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK) + #define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U) #define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U) /*! MSBSEL - Multi / Single block select @@ -88904,16 +99675,19 @@ typedef struct { * 0b0..Single block */ #define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK) + #define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U) #define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U) /*! NIBBLE_POS - Nibble position indication */ #define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK) + #define USDHC_MIX_CTRL_AC23EN_MASK (0x80U) #define USDHC_MIX_CTRL_AC23EN_SHIFT (7U) /*! AC23EN - Auto CMD23 enable */ #define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK) + #define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U) #define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U) /*! EXE_TUNE - Execute tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) @@ -88921,6 +99695,7 @@ typedef struct { * 0b0..Not tuned or tuning completed */ #define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK) + #define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U) #define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U) /*! SMP_CLK_SEL - Clock selection @@ -88928,6 +99703,7 @@ typedef struct { * 0b0..Fixed clock is used to sample data / cmd */ #define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK) + #define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U) #define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U) /*! AUTO_TUNE_EN - Auto tuning enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode) @@ -88935,6 +99711,7 @@ typedef struct { * 0b0..Disable auto tuning */ #define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK) + #define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U) #define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U) /*! FBCLK_SEL - Feedback clock source selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode) @@ -88942,100 +99719,113 @@ typedef struct { * 0b0..Feedback clock comes from the loopback CLK */ #define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK) + #define USDHC_MIX_CTRL_HS400_MODE_MASK (0x4000000U) #define USDHC_MIX_CTRL_HS400_MODE_SHIFT (26U) /*! HS400_MODE - Enable HS400 mode */ #define USDHC_MIX_CTRL_HS400_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_HS400_MODE_MASK) -#define USDHC_MIX_CTRL_EN_HS400_MODE_MASK (0x8000000U) -#define USDHC_MIX_CTRL_EN_HS400_MODE_SHIFT (27U) -/*! EN_HS400_MODE - Enable enhance HS400 mode - */ -#define USDHC_MIX_CTRL_EN_HS400_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EN_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_EN_HS400_MODE_MASK) /*! @} */ /*! @name FORCE_EVENT - Force Event */ /*! @{ */ + #define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U) #define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U) /*! FEVTAC12NE - Force event auto command 12 not executed */ #define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK) + #define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U) #define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U) /*! FEVTAC12TOE - Force event auto command 12 time out error */ #define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK) + #define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U) #define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U) /*! FEVTAC12CE - Force event auto command 12 CRC error */ #define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK) + #define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U) #define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U) /*! FEVTAC12EBE - Force event Auto Command 12 end bit error */ #define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK) + #define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U) #define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U) /*! FEVTAC12IE - Force event Auto Command 12 index error */ #define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK) + #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U) #define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U) /*! FEVTCNIBAC12E - Force event command not executed by Auto Command 12 error */ #define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK) + #define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U) #define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U) /*! FEVTCTOE - Force event command time out error */ #define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK) + #define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U) #define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U) /*! FEVTCCE - Force event command CRC error */ #define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK) + #define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U) #define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U) /*! FEVTCEBE - Force event command end bit error */ #define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK) + #define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U) #define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U) /*! FEVTCIE - Force event command index error */ #define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK) + #define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U) #define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U) /*! FEVTDTOE - Force event data time out error */ #define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK) + #define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U) #define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U) /*! FEVTDCE - Force event data CRC error */ #define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK) + #define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U) #define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U) /*! FEVTDEBE - Force event data end bit error */ #define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK) + #define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U) #define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U) /*! FEVTAC12E - Force event Auto Command 12 error */ #define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK) + #define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U) #define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U) /*! FEVTTNE - Force tuning error */ #define USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK) + #define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U) #define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U) /*! FEVTDMAE - Force event DMA error */ #define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK) + #define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U) #define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U) /*! FEVTCINT - Force event card interrupt @@ -89045,11 +99835,13 @@ typedef struct { /*! @name ADMA_ERR_STATUS - ADMA Error Status */ /*! @{ */ + #define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U) #define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U) /*! ADMAES - ADMA error state (when ADMA error is occurred) */ #define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK) + #define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U) #define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U) /*! ADMALME - ADMA length mismatch error @@ -89057,6 +99849,7 @@ typedef struct { * 0b0..No error */ #define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK) + #define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U) #define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U) /*! ADMADCE - ADMA descriptor error @@ -89068,6 +99861,7 @@ typedef struct { /*! @name ADMA_SYS_ADDR - ADMA System Address */ /*! @{ */ + #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU) #define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U) /*! ADS_ADDR - ADMA system address @@ -89077,51 +99871,61 @@ typedef struct { /*! @name DLL_CTRL - DLL (Delay Line) Control */ /*! @{ */ + #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U) #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U) /*! DLL_CTRL_ENABLE - DLL and delay chain */ #define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK) + #define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U) #define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U) /*! DLL_CTRL_RESET - DLL reset */ #define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK) + #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) /*! DLL_CTRL_SLV_FORCE_UPD - DLL slave delay line */ #define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK) + #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U) /*! DLL_CTRL_SLV_DLY_TARGET0 - DLL slave delay target0 */ #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK) + #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U) #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U) /*! DLL_CTRL_GATE_UPDATE - DLL gate update */ #define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK) + #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) /*! DLL_CTRL_SLV_OVERRIDE - DLL slave override */ #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK) + #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) /*! DLL_CTRL_SLV_OVERRIDE_VAL - DLL slave override val */ #define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) + #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U) /*! DLL_CTRL_SLV_DLY_TARGET1 - DLL slave delay target1 */ #define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK) + #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) /*! DLL_CTRL_SLV_UPDATE_INT - Slave delay line update interval */ #define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK) + #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) #define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) /*! DLL_CTRL_REF_UPDATE_INT - DLL control loop update interval @@ -89131,21 +99935,25 @@ typedef struct { /*! @name DLL_STATUS - DLL Status */ /*! @{ */ + #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U) #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U) /*! DLL_STS_SLV_LOCK - Slave delay-line lock status */ #define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK) + #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U) #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U) /*! DLL_STS_REF_LOCK - Reference DLL lock status */ #define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK) + #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU) #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U) /*! DLL_STS_SLV_SEL - Slave delay line select status */ #define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK) + #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U) #define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U) /*! DLL_STS_REF_SEL - Reference delay line select taps @@ -89155,41 +99963,49 @@ typedef struct { /*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */ /*! @{ */ + #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U) /*! DLY_CELL_SET_POST - Delay cells on the feedback clock between CLK_OUT and CLK_POST */ #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK) + #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U) /*! DLY_CELL_SET_OUT - Delay cells on the feedback clock between CLK_PRE and CLK_OUT */ #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK) + #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U) #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U) /*! DLY_CELL_SET_PRE - delay cells on the feedback clock between the feedback clock and CLK_PRE */ #define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK) + #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U) #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U) /*! NXT_ERR - NXT error */ #define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK) + #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U) #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U) /*! TAP_SEL_POST - Delay cells added on the feedback clock between CLK_OUT and CLK_POST */ #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK) + #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U) #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U) /*! TAP_SEL_OUT - Delay cells added on the feedback clock between CLK_PRE and CLK_OUT */ #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK) + #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U) #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U) /*! TAP_SEL_PRE - TAP_SEL_PRE */ #define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK) + #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U) #define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U) /*! PRE_ERR - PRE error @@ -89199,46 +100015,55 @@ typedef struct { /*! @name STROBE_DLL_CTRL - Strobe DLL control */ /*! @{ */ + #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK (0x1U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT (0U) /*! STROBE_DLL_CTRL_ENABLE - Strobe DLL control enable */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK) + #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK (0x2U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT (1U) /*! STROBE_DLL_CTRL_RESET - Strobe DLL control reset */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK) + #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U) /*! STROBE_DLL_CTRL_SLV_FORCE_UPD - Strobe DLL control slave force updated */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK) + #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U) /*! STROBE_DLL_CTRL_SLV_DLY_TARGET - Strobe DLL Control Slave Delay Target */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK) + #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK (0x80U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT (7U) /*! STROBE_DLL_CTRL_GATE_UPDATE - Strobe DLL control gate update */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK) + #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U) /*! STROBE_DLL_CTRL_SLV_OVERRIDE - Strobe DLL control slave override */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK) + #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U) /*! STROBE_DLL_CTRL_SLV_OVERRIDE_VAL - Strobe DLL control slave Override value */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK) + #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U) /*! STROBE_DLL_CTRL_SLV_UPDATE_INT - Strobe DLL control slave update interval */ #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK) + #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U) #define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U) /*! STROBE_DLL_CTRL_REF_UPDATE_INT - Strobe DLL control reference update interval @@ -89248,21 +100073,25 @@ typedef struct { /*! @name STROBE_DLL_STATUS - Strobe DLL status */ /*! @{ */ + #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK (0x1U) #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT (0U) /*! STROBE_DLL_STS_SLV_LOCK - Strobe DLL status slave lock */ #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK) + #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK (0x2U) #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT (1U) /*! STROBE_DLL_STS_REF_LOCK - Strobe DLL status reference lock */ #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK) + #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK (0x1FCU) #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT (2U) /*! STROBE_DLL_STS_SLV_SEL - Strobe DLL status slave select */ #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK) + #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK (0xFE00U) #define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT (9U) /*! STROBE_DLL_STS_REF_SEL - Strobe DLL status reference select @@ -89272,6 +100101,7 @@ typedef struct { /*! @name VEND_SPEC - Vendor Specific Register */ /*! @{ */ + #define USDHC_VEND_SPEC_VSELECT_MASK (0x2U) #define USDHC_VEND_SPEC_VSELECT_SHIFT (1U) /*! VSELECT - Voltage selection @@ -89279,6 +100109,7 @@ typedef struct { * 0b0..Change the voltage to high voltage range, around 3.0 V */ #define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK) + #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U) #define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U) /*! CONFLICT_CHK_EN - Conflict check enable @@ -89286,6 +100117,7 @@ typedef struct { * 0b1..Conflict check enable */ #define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK) + #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U) #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U) /*! AC12_WR_CHKBUSY_EN - Check busy enable @@ -89293,6 +100125,7 @@ typedef struct { * 0b1..Check busy after auto CMD12 for write data packet */ #define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK) + #define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U) #define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U) /*! FRC_SDCLK_ON - Force CLK @@ -89300,6 +100133,7 @@ typedef struct { * 0b1..Force CLK active */ #define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK) + #define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U) #define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U) /*! CRC_CHK_DIS - CRC Check Disable @@ -89307,6 +100141,7 @@ typedef struct { * 0b1..Ignore CRC16 check for every read data packet and ignore CRC fields check for every write data packet */ #define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK) + #define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U) #define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U) /*! CMD_BYTE_EN - Byte access @@ -89318,21 +100153,23 @@ typedef struct { /*! @name MMC_BOOT - MMC Boot */ /*! @{ */ + #define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU) #define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U) -/*! DTOCV_ACK - DTOCV_ACK - * 0b0000..SDCLK x 2^32 - * 0b0001..SDCLK x 2^33 - * 0b0010..SDCLK x 2^18 - * 0b0011..SDCLK x 2^19 - * 0b0100..SDCLK x 2^20 - * 0b0101..SDCLK x 2^21 - * 0b0110..SDCLK x 2^22 - * 0b0111..SDCLK x 2^23 - * 0b1110..SDCLK x 2^30 - * 0b1111..SDCLK x 2^31 +/*! DTOCV_ACK - Boot ACK time out + * 0b0000..SDCLK x 2^14 + * 0b0001..SDCLK x 2^15 + * 0b0010..SDCLK x 2^16 + * 0b0011..SDCLK x 2^17 + * 0b0100..SDCLK x 2^18 + * 0b0101..SDCLK x 2^19 + * 0b0110..SDCLK x 2^20 + * 0b0111..SDCLK x 2^21 + * 0b1110..SDCLK x 2^28 + * 0b1111..SDCLK x 2^29 */ #define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK) + #define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U) #define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U) /*! BOOT_ACK - BOOT ACK @@ -89340,6 +100177,7 @@ typedef struct { * 0b1..Ack */ #define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK) + #define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U) #define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U) /*! BOOT_MODE - Boot mode @@ -89347,6 +100185,7 @@ typedef struct { * 0b1..Alternative boot */ #define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK) + #define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U) #define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U) /*! BOOT_EN - Boot enable @@ -89354,11 +100193,13 @@ typedef struct { * 0b1..Fast boot enable */ #define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK) + #define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U) #define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U) /*! AUTO_SABG_EN - Auto stop at block gap */ #define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK) + #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U) #define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U) /*! DISABLE_TIME_OUT - Time out @@ -89366,6 +100207,7 @@ typedef struct { * 0b1..Disable time out */ #define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK) + #define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U) #define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U) /*! BOOT_BLK_CNT - Stop At Block Gap value of automatic mode @@ -89375,6 +100217,7 @@ typedef struct { /*! @name VEND_SPEC2 - Vendor Specific 2 Register */ /*! @{ */ + #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U) #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U) /*! CARD_INT_D3_TEST - Card interrupt detection test @@ -89382,16 +100225,19 @@ typedef struct { * 0b1..Check the card interrupt by ignoring the status of DATA3. */ #define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK) + #define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U) #define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U) /*! TUNING_8bit_EN - Tuning 8bit enable */ #define USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK) + #define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U) #define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U) /*! TUNING_1bit_EN - Tuning 1bit enable */ #define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK) + #define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U) #define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U) /*! TUNING_CMD_EN - Tuning command enable @@ -89399,16 +100245,19 @@ typedef struct { * 0b1..Auto tuning circuit checks the CMD line. */ #define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK) + #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK (0x400U) #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT (10U) /*! HS400_WR_CLK_STOP_EN - HS400 write clock stop enable */ #define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK) + #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK (0x800U) #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT (11U) /*! HS400_RD_CLK_STOP_EN - HS400 read clock stop enable */ #define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK) + #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U) #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U) /*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23 @@ -89416,45 +100265,41 @@ typedef struct { * 0b0..Disable */ #define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK) -#define USDHC_VEND_SPEC2_EN_32K_CLK_MASK (0x8000U) -#define USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT (15U) -/*! EN_32K_CLK - Enable 32khz clock for card detection - */ -#define USDHC_VEND_SPEC2_EN_32K_CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_EN_32K_CLK_SHIFT)) & USDHC_VEND_SPEC2_EN_32K_CLK_MASK) -#define USDHC_VEND_SPEC2_FBCLK_TAP_SEL_MASK (0xFFFF0000U) -#define USDHC_VEND_SPEC2_FBCLK_TAP_SEL_SHIFT (16U) -/*! FBCLK_TAP_SEL - Enable extra delay on internal feedback clock - */ -#define USDHC_VEND_SPEC2_FBCLK_TAP_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_FBCLK_TAP_SEL_SHIFT)) & USDHC_VEND_SPEC2_FBCLK_TAP_SEL_MASK) /*! @} */ /*! @name TUNING_CTRL - Tuning Control */ /*! @{ */ + #define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0x7FU) #define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U) /*! TUNING_START_TAP - Tuning start */ #define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK) + #define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK (0x80U) #define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT (7U) /*! DIS_CMD_CHK_FOR_STD_TUNING - Disable command check for standard tuning */ #define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT)) & USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK) + #define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U) #define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U) /*! TUNING_COUNTER - Tuning counter */ #define USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK) + #define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U) #define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U) /*! TUNING_STEP - TUNING_STEP */ #define USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK) + #define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U) #define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U) /*! TUNING_WINDOW - Data window */ #define USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK) + #define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U) #define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U) /*! STD_TUNING_EN - Standard tuning circuit and procedure enable @@ -89462,361 +100307,6 @@ typedef struct { #define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK) /*! @} */ -/*! @name CQVER - Command Queuing Version */ -/*! @{ */ -#define USDHC_CQVER_VERSION_SUFFIX_MASK (0xFU) -#define USDHC_CQVER_VERSION_SUFFIX_SHIFT (0U) -/*! VERSION_SUFFIX - e •MMC version suffix - */ -#define USDHC_CQVER_VERSION_SUFFIX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQVER_VERSION_SUFFIX_SHIFT)) & USDHC_CQVER_VERSION_SUFFIX_MASK) -#define USDHC_CQVER_MINOR_VN_MASK (0xF0U) -#define USDHC_CQVER_MINOR_VN_SHIFT (4U) -/*! MINOR_VN - e •MMC minor version number - */ -#define USDHC_CQVER_MINOR_VN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQVER_MINOR_VN_SHIFT)) & USDHC_CQVER_MINOR_VN_MASK) -#define USDHC_CQVER_MAJOR_VN_MASK (0xF00U) -#define USDHC_CQVER_MAJOR_VN_SHIFT (8U) -/*! MAJOR_VN - e •MMC major version number - */ -#define USDHC_CQVER_MAJOR_VN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQVER_MAJOR_VN_SHIFT)) & USDHC_CQVER_MAJOR_VN_MASK) -/*! @} */ - -/*! @name CQCAP - Command Queuing Capabilities */ -/*! @{ */ -#define USDHC_CQCAP_ITCFVAL_MASK (0x3FFU) -#define USDHC_CQCAP_ITCFVAL_SHIFT (0U) -/*! ITCFVAL - Internal timer clock frequency value - */ -#define USDHC_CQCAP_ITCFVAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCAP_ITCFVAL_SHIFT)) & USDHC_CQCAP_ITCFVAL_MASK) -#define USDHC_CQCAP_ITCFMUL_MASK (0xF000U) -#define USDHC_CQCAP_ITCFMUL_SHIFT (12U) -/*! ITCFMUL - Internal timer clock frequency multiplier - * 0b0001..0.001 MHz - * 0b0010..0.01 MHz - * 0b0011..0.1 MHz - * 0b0100..1 MHz - * 0b0101..10 MHz - * 0b0110-0b1001..Reserved - */ -#define USDHC_CQCAP_ITCFMUL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCAP_ITCFMUL_SHIFT)) & USDHC_CQCAP_ITCFMUL_MASK) -/*! @} */ - -/*! @name CQCFG - Command Queuing Configuration */ -/*! @{ */ -#define USDHC_CQCFG_CQUE_MASK (0x1U) -#define USDHC_CQCFG_CQUE_SHIFT (0U) -/*! CQUE - Command queuing enable - */ -#define USDHC_CQCFG_CQUE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCFG_CQUE_SHIFT)) & USDHC_CQCFG_CQUE_MASK) -#define USDHC_CQCFG_TDS_MASK (0x100U) -#define USDHC_CQCFG_TDS_SHIFT (8U) -/*! TDS - Task descriptor size - * 0b0..Task descriptor size is 64 bits - * 0b1..Task descriptor size is 128 bits - */ -#define USDHC_CQCFG_TDS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCFG_TDS_SHIFT)) & USDHC_CQCFG_TDS_MASK) -#define USDHC_CQCFG_DCMDE_MASK (0x1000U) -#define USDHC_CQCFG_DCMDE_SHIFT (12U) -/*! DCMDE - Direct command (DCMD) enable - * 0b0..Task descriptor in slot #31 is a Data Transfer Task Descriptor - * 0b1..Task descriptor in slot #31 is a DCMD Task Descriptor - */ -#define USDHC_CQCFG_DCMDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCFG_DCMDE_SHIFT)) & USDHC_CQCFG_DCMDE_MASK) -/*! @} */ - -/*! @name CQCTL - Command Queuing Control */ -/*! @{ */ -#define USDHC_CQCTL_HALT_MASK (0x1U) -#define USDHC_CQCTL_HALT_SHIFT (0U) -/*! HALT - Halt - */ -#define USDHC_CQCTL_HALT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCTL_HALT_SHIFT)) & USDHC_CQCTL_HALT_MASK) -#define USDHC_CQCTL_CLEAR_MASK (0x100U) -#define USDHC_CQCTL_CLEAR_SHIFT (8U) -/*! CLEAR - Clear all tasks - */ -#define USDHC_CQCTL_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCTL_CLEAR_SHIFT)) & USDHC_CQCTL_CLEAR_MASK) -/*! @} */ - -/*! @name CQIS - Command Queuing Interrupt Status */ -/*! @{ */ -#define USDHC_CQIS_HAC_MASK (0x1U) -#define USDHC_CQIS_HAC_SHIFT (0U) -/*! HAC - Halt complete interrupt - */ -#define USDHC_CQIS_HAC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_HAC_SHIFT)) & USDHC_CQIS_HAC_MASK) -#define USDHC_CQIS_TCC_MASK (0x2U) -#define USDHC_CQIS_TCC_SHIFT (1U) -/*! TCC - Task complete interrupt - */ -#define USDHC_CQIS_TCC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_TCC_SHIFT)) & USDHC_CQIS_TCC_MASK) -#define USDHC_CQIS_RED_MASK (0x4U) -#define USDHC_CQIS_RED_SHIFT (2U) -/*! RED - Response error detected interrupt - */ -#define USDHC_CQIS_RED(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_RED_SHIFT)) & USDHC_CQIS_RED_MASK) -#define USDHC_CQIS_TCL_MASK (0x8U) -#define USDHC_CQIS_TCL_SHIFT (3U) -/*! TCL - Task cleared - */ -#define USDHC_CQIS_TCL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIS_TCL_SHIFT)) & USDHC_CQIS_TCL_MASK) -/*! @} */ - -/*! @name CQISTE - Command Queuing Interrupt Status Enable */ -/*! @{ */ -#define USDHC_CQISTE_HAC_STE_MASK (0x1U) -#define USDHC_CQISTE_HAC_STE_SHIFT (0U) -/*! HAC_STE - Halt complete status enable - * 0b0..CQIS[HAC] is disabled - * 0b1..CQIS[HAC] is set when its interrupt condition is active - */ -#define USDHC_CQISTE_HAC_STE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_HAC_STE_SHIFT)) & USDHC_CQISTE_HAC_STE_MASK) -#define USDHC_CQISTE_TCC_STE_MASK (0x2U) -#define USDHC_CQISTE_TCC_STE_SHIFT (1U) -/*! TCC_STE - Task complete status enable - * 0b0..CQIS[TCC] is disabled - * 0b1..CQIS[TCC] is set when its interrupt condition is active - */ -#define USDHC_CQISTE_TCC_STE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_TCC_STE_SHIFT)) & USDHC_CQISTE_TCC_STE_MASK) -#define USDHC_CQISTE_RED_STE_MASK (0x4U) -#define USDHC_CQISTE_RED_STE_SHIFT (2U) -/*! RED_STE - Response error detected status enable - * 0b0..CQIS[RED] is disabled - * 0b1..CQIS[RED] is set when its interrupt condition is active - */ -#define USDHC_CQISTE_RED_STE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_RED_STE_SHIFT)) & USDHC_CQISTE_RED_STE_MASK) -#define USDHC_CQISTE_TCL_STE_MASK (0x8U) -#define USDHC_CQISTE_TCL_STE_SHIFT (3U) -/*! TCL_STE - Task cleared status enable - * 0b0..CQIS[TCL] is disabled - * 0b1..CQIS[TCL] is set when its interrupt condition is active - */ -#define USDHC_CQISTE_TCL_STE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISTE_TCL_STE_SHIFT)) & USDHC_CQISTE_TCL_STE_MASK) -/*! @} */ - -/*! @name CQISGE - Command Queuing Interrupt Signal Enable */ -/*! @{ */ -#define USDHC_CQISGE_HAC_SGE_MASK (0x1U) -#define USDHC_CQISGE_HAC_SGE_SHIFT (0U) -/*! HAC_SGE - Halt complete signal enable - */ -#define USDHC_CQISGE_HAC_SGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_HAC_SGE_SHIFT)) & USDHC_CQISGE_HAC_SGE_MASK) -#define USDHC_CQISGE_TCC_SGE_MASK (0x2U) -#define USDHC_CQISGE_TCC_SGE_SHIFT (1U) -/*! TCC_SGE - Task complete signal enable - */ -#define USDHC_CQISGE_TCC_SGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_TCC_SGE_SHIFT)) & USDHC_CQISGE_TCC_SGE_MASK) -#define USDHC_CQISGE_RED_SGE_MASK (0x4U) -#define USDHC_CQISGE_RED_SGE_SHIFT (2U) -/*! RED_SGE - Response error detected signal enable - */ -#define USDHC_CQISGE_RED_SGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_RED_SGE_SHIFT)) & USDHC_CQISGE_RED_SGE_MASK) -#define USDHC_CQISGE_TCL_SGE_MASK (0x8U) -#define USDHC_CQISGE_TCL_SGE_SHIFT (3U) -/*! TCL_SGE - Task cleared signal enable - */ -#define USDHC_CQISGE_TCL_SGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQISGE_TCL_SGE_SHIFT)) & USDHC_CQISGE_TCL_SGE_MASK) -/*! @} */ - -/*! @name CQIC - Command Queuing Interrupt Coalescing */ -/*! @{ */ -#define USDHC_CQIC_ICTOVAL_MASK (0x7FU) -#define USDHC_CQIC_ICTOVAL_SHIFT (0U) -/*! ICTOVAL - Interrupt coalescing timeout value - */ -#define USDHC_CQIC_ICTOVAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICTOVAL_SHIFT)) & USDHC_CQIC_ICTOVAL_MASK) -#define USDHC_CQIC_ICTOVALWEN_MASK (0x80U) -#define USDHC_CQIC_ICTOVALWEN_SHIFT (7U) -/*! ICTOVALWEN - Interrupt coalescing timeout value write enable - */ -#define USDHC_CQIC_ICTOVALWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICTOVALWEN_SHIFT)) & USDHC_CQIC_ICTOVALWEN_MASK) -#define USDHC_CQIC_ICCTH_MASK (0x1F00U) -#define USDHC_CQIC_ICCTH_SHIFT (8U) -/*! ICCTH - Interrupt coalescing counter threshold - */ -#define USDHC_CQIC_ICCTH(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICCTH_SHIFT)) & USDHC_CQIC_ICCTH_MASK) -#define USDHC_CQIC_ICCTHWEN_MASK (0x8000U) -#define USDHC_CQIC_ICCTHWEN_SHIFT (15U) -/*! ICCTHWEN - Interrupt coalescing counter threshold write enable - */ -#define USDHC_CQIC_ICCTHWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICCTHWEN_SHIFT)) & USDHC_CQIC_ICCTHWEN_MASK) -#define USDHC_CQIC_ICCTR_MASK (0x10000U) -#define USDHC_CQIC_ICCTR_SHIFT (16U) -/*! ICCTR - Counter and timer reset - */ -#define USDHC_CQIC_ICCTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICCTR_SHIFT)) & USDHC_CQIC_ICCTR_MASK) -#define USDHC_CQIC_ICSB_MASK (0x100000U) -#define USDHC_CQIC_ICSB_SHIFT (20U) -/*! ICSB - Interrupt coalescing status - * 0b0..No task completions have occurred since last counter reset (IC counter =0) - * 0b1..At least one task completion has been counted (IC counter >0) - */ -#define USDHC_CQIC_ICSB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICSB_SHIFT)) & USDHC_CQIC_ICSB_MASK) -#define USDHC_CQIC_ICENDIS_MASK (0x80000000U) -#define USDHC_CQIC_ICENDIS_SHIFT (31U) -/*! ICENDIS - Interrupt coalescing enable/disable - */ -#define USDHC_CQIC_ICENDIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQIC_ICENDIS_SHIFT)) & USDHC_CQIC_ICENDIS_MASK) -/*! @} */ - -/*! @name CQTDLBA - Command Queuing Task Descriptor List Base Address */ -/*! @{ */ -#define USDHC_CQTDLBA_TDLBA_MASK (0xFFFFFFFFU) -#define USDHC_CQTDLBA_TDLBA_SHIFT (0U) -/*! TDLBA - Task descriptor list base address - */ -#define USDHC_CQTDLBA_TDLBA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTDLBA_TDLBA_SHIFT)) & USDHC_CQTDLBA_TDLBA_MASK) -/*! @} */ - -/*! @name CQTDLBAU - Command Queuing Task Descriptor List Base Address Upper 32 Bits */ -/*! @{ */ -#define USDHC_CQTDLBAU_TDLBAU_MASK (0xFFFFFFFFU) -#define USDHC_CQTDLBAU_TDLBAU_SHIFT (0U) -/*! TDLBAU - Task descriptor list base address - */ -#define USDHC_CQTDLBAU_TDLBAU(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTDLBAU_TDLBAU_SHIFT)) & USDHC_CQTDLBAU_TDLBAU_MASK) -/*! @} */ - -/*! @name CQTDBR - Command Queuing Task Doorbell */ -/*! @{ */ -#define USDHC_CQTDBR_TDBR_MASK (0xFFFFFFFFU) -#define USDHC_CQTDBR_TDBR_SHIFT (0U) -/*! TDBR - Task doorbell - */ -#define USDHC_CQTDBR_TDBR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTDBR_TDBR_SHIFT)) & USDHC_CQTDBR_TDBR_MASK) -/*! @} */ - -/*! @name CQTCN - Command Queuing Task Completion Notification */ -/*! @{ */ -#define USDHC_CQTCN_TCN_MASK (0xFFFFFFFFU) -#define USDHC_CQTCN_TCN_SHIFT (0U) -/*! TCN - Task complete notification - */ -#define USDHC_CQTCN_TCN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTCN_TCN_SHIFT)) & USDHC_CQTCN_TCN_MASK) -/*! @} */ - -/*! @name CQDQS - Command Queuing Device Queue Status */ -/*! @{ */ -#define USDHC_CQDQS_DQS_MASK (0xFFFFFFFFU) -#define USDHC_CQDQS_DQS_SHIFT (0U) -/*! DQS - Device queue status - */ -#define USDHC_CQDQS_DQS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQDQS_DQS_SHIFT)) & USDHC_CQDQS_DQS_MASK) -/*! @} */ - -/*! @name CQDPT - Command Queuing Device Pending Tasks */ -/*! @{ */ -#define USDHC_CQDPT_DPT_MASK (0xFFFFFFFFU) -#define USDHC_CQDPT_DPT_SHIFT (0U) -/*! DPT - Device pending tasks - */ -#define USDHC_CQDPT_DPT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQDPT_DPT_SHIFT)) & USDHC_CQDPT_DPT_MASK) -/*! @} */ - -/*! @name CQTCLR - Command Queuing Task Clear */ -/*! @{ */ -#define USDHC_CQTCLR_TCLR_MASK (0xFFFFFFFFU) -#define USDHC_CQTCLR_TCLR_SHIFT (0U) -/*! TCLR - Task clear - */ -#define USDHC_CQTCLR_TCLR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTCLR_TCLR_SHIFT)) & USDHC_CQTCLR_TCLR_MASK) -/*! @} */ - -/*! @name CQSSC1 - Command Queuing Send Status Configuration 1 */ -/*! @{ */ -#define USDHC_CQSSC1_CIT_MASK (0xFFFFU) -#define USDHC_CQSSC1_CIT_SHIFT (0U) -/*! CIT - Send status command idle timer - */ -#define USDHC_CQSSC1_CIT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQSSC1_CIT_SHIFT)) & USDHC_CQSSC1_CIT_MASK) -#define USDHC_CQSSC1_CBC_MASK (0xF0000U) -#define USDHC_CQSSC1_CBC_SHIFT (16U) -/*! CBC - Send status command block counter - */ -#define USDHC_CQSSC1_CBC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQSSC1_CBC_SHIFT)) & USDHC_CQSSC1_CBC_MASK) -/*! @} */ - -/*! @name CQSSC2 - Command Queuing Send Status Configuration 2 */ -/*! @{ */ -#define USDHC_CQSSC2_SSC2_MASK (0xFFFFU) -#define USDHC_CQSSC2_SSC2_SHIFT (0U) -/*! SSC2 - Send queue status RCA - */ -#define USDHC_CQSSC2_SSC2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQSSC2_SSC2_SHIFT)) & USDHC_CQSSC2_SSC2_MASK) -/*! @} */ - -/*! @name CQCRDCT - Command Queuing Command Response for Direct-Command Task */ -/*! @{ */ -#define USDHC_CQCRDCT_CRDCT_MASK (0xFFFFFFFFU) -#define USDHC_CQCRDCT_CRDCT_SHIFT (0U) -/*! CRDCT - Direct command last response - */ -#define USDHC_CQCRDCT_CRDCT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCRDCT_CRDCT_SHIFT)) & USDHC_CQCRDCT_CRDCT_MASK) -/*! @} */ - -/*! @name CQRMEM - Command Queuing Response Mode Error Mask */ -/*! @{ */ -#define USDHC_CQRMEM_RMEM_MASK (0xFFFFFFFFU) -#define USDHC_CQRMEM_RMEM_SHIFT (0U) -/*! RMEM - Response mode error mask - * 0b00000000000000000000000000000000..When a R1/R1b response is received, bit i in the device status is ignored - * 0b00000000000000000000000000000001..When a R1/R1b response is received, with bit i in the device status set, a RED interrupt is generated - */ -#define USDHC_CQRMEM_RMEM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQRMEM_RMEM_SHIFT)) & USDHC_CQRMEM_RMEM_MASK) -/*! @} */ - -/*! @name CQTERRI - Command Queuing Task Error Information */ -/*! @{ */ -#define USDHC_CQTERRI_RMECI_MASK (0x3FU) -#define USDHC_CQTERRI_RMECI_SHIFT (0U) -/*! RMECI - Response mode error command index - */ -#define USDHC_CQTERRI_RMECI(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_RMECI_SHIFT)) & USDHC_CQTERRI_RMECI_MASK) -#define USDHC_CQTERRI_RMETID_MASK (0x1F00U) -#define USDHC_CQTERRI_RMETID_SHIFT (8U) -/*! RMETID - Response mode error task ID - */ -#define USDHC_CQTERRI_RMETID(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_RMETID_SHIFT)) & USDHC_CQTERRI_RMETID_MASK) -#define USDHC_CQTERRI_RMEFV_MASK (0x8000U) -#define USDHC_CQTERRI_RMEFV_SHIFT (15U) -/*! RMEFV - Response mode error fields valid - */ -#define USDHC_CQTERRI_RMEFV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_RMEFV_SHIFT)) & USDHC_CQTERRI_RMEFV_MASK) -#define USDHC_CQTERRI_DTECI_MASK (0x3F0000U) -#define USDHC_CQTERRI_DTECI_SHIFT (16U) -/*! DTECI - Data transfer error command index - */ -#define USDHC_CQTERRI_DTECI(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_DTECI_SHIFT)) & USDHC_CQTERRI_DTECI_MASK) -#define USDHC_CQTERRI_DTETID_MASK (0x1F000000U) -#define USDHC_CQTERRI_DTETID_SHIFT (24U) -/*! DTETID - Data transfer error task ID - */ -#define USDHC_CQTERRI_DTETID(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_DTETID_SHIFT)) & USDHC_CQTERRI_DTETID_MASK) -#define USDHC_CQTERRI_DTEFV_MASK (0x80000000U) -#define USDHC_CQTERRI_DTEFV_SHIFT (31U) -/*! DTEFV - Data transfer error fields valid - */ -#define USDHC_CQTERRI_DTEFV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQTERRI_DTEFV_SHIFT)) & USDHC_CQTERRI_DTEFV_MASK) -/*! @} */ - -/*! @name CQCRI - Command Queuing Command Response Index */ -/*! @{ */ -#define USDHC_CQCRI_LCMDRI_MASK (0x3FU) -#define USDHC_CQCRI_LCMDRI_SHIFT (0U) -/*! LCMDRI - Last command response index - */ -#define USDHC_CQCRI_LCMDRI(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCRI_LCMDRI_SHIFT)) & USDHC_CQCRI_LCMDRI_MASK) -/*! @} */ - -/*! @name CQCRA - Command Queuing Command Response Argument */ -/*! @{ */ -#define USDHC_CQCRA_LCMDRA_MASK (0xFFFFFFFFU) -#define USDHC_CQCRA_LCMDRA_SHIFT (0U) -/*! LCMDRA - Last command response argument - */ -#define USDHC_CQCRA_LCMDRA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CQCRA_LCMDRA_SHIFT)) & USDHC_CQCRA_LCMDRA_MASK) -/*! @} */ - /*! * @} @@ -89861,38 +100351,27 @@ typedef struct { __IO uint32_t CLR; /**< Video mux Control Register, offset: 0x8 */ __IO uint32_t TOG; /**< Video mux Control Register, offset: 0xC */ } VID_MUX_CTRL; - struct { /* offset: 0x10 */ - __IO uint32_t RW; /**< CTRL_FENCE_VC Register, offset: 0x10 */ - __IO uint32_t SET; /**< CTRL_FENCE_VC Register, offset: 0x14 */ - __IO uint32_t CLR; /**< CTRL_FENCE_VC Register, offset: 0x18 */ - __IO uint32_t TOG; /**< CTRL_FENCE_VC Register, offset: 0x1C */ - } STREAM_FENCING_CTRL; + uint8_t RESERVED_0[16]; struct { /* offset: 0x20 */ - __IO uint32_t RW; /**< PLM Control register, offset: 0x20 */ - __IO uint32_t SET; /**< PLM Control register, offset: 0x24 */ - __IO uint32_t CLR; /**< PLM Control register, offset: 0x28 */ - __IO uint32_t TOG; /**< PLM Control register, offset: 0x2C */ + __IO uint32_t RW; /**< Pixel Link Master(PLM) Control Register, offset: 0x20 */ + __IO uint32_t SET; /**< Pixel Link Master(PLM) Control Register, offset: 0x24 */ + __IO uint32_t CLR; /**< Pixel Link Master(PLM) Control Register, offset: 0x28 */ + __IO uint32_t TOG; /**< Pixel Link Master(PLM) Control Register, offset: 0x2C */ } PLM_CTRL; struct { /* offset: 0x30 */ - __IO uint32_t RW; /**< YUV420_CTRL, offset: 0x30 */ - __IO uint32_t SET; /**< YUV420_CTRL, offset: 0x34 */ - __IO uint32_t CLR; /**< YUV420_CTRL, offset: 0x38 */ - __IO uint32_t TOG; /**< YUV420_CTRL, offset: 0x3C */ + __IO uint32_t RW; /**< YUV420 Control Register, offset: 0x30 */ + __IO uint32_t SET; /**< YUV420 Control Register, offset: 0x34 */ + __IO uint32_t CLR; /**< YUV420 Control Register, offset: 0x38 */ + __IO uint32_t TOG; /**< YUV420 Control Register, offset: 0x3C */ } YUV420_CTRL; - struct { /* offset: 0x40 */ - __I uint32_t RW; /**< STREAM_FENCING_STAT register, offset: 0x40 */ - __I uint32_t SET; /**< STREAM_FENCING_STAT register, offset: 0x44 */ - __I uint32_t CLR; /**< STREAM_FENCING_STAT register, offset: 0x48 */ - __I uint32_t TOG; /**< STREAM_FENCING_STAT register, offset: 0x4C */ - } STREAM_FENCING_STAT; + uint8_t RESERVED_1[16]; struct { /* offset: 0x50 */ - __IO uint32_t RW; /**< PRG Base Address Register, offset: 0x50 */ - __IO uint32_t SET; /**< PRG Base Address Register, offset: 0x54 */ - __IO uint32_t CLR; /**< PRG Base Address Register, offset: 0x58 */ - __IO uint32_t TOG; /**< PRG Base Address Register, offset: 0x5C */ + __IO uint32_t RW; /**< Data Disable Register, offset: 0x50 */ + __IO uint32_t SET; /**< Data Disable Register, offset: 0x54 */ + __IO uint32_t CLR; /**< Data Disable Register, offset: 0x58 */ + __IO uint32_t TOG; /**< Data Disable Register, offset: 0x5C */ } CFG_DT_DISABLE; - __IO uint32_t VC_INTERLACED; /**< VC_INTERLACED, offset: 0x60 */ - uint8_t RESERVED_0[12]; + uint8_t RESERVED_2[16]; struct { /* offset: 0x70 */ __IO uint32_t RW; /**< MIPI DSI Control Register, offset: 0x70 */ __IO uint32_t SET; /**< MIPI DSI Control Register, offset: 0x74 */ @@ -89912,130 +100391,123 @@ typedef struct { /*! @name VID_MUX_CTRL - Video mux Control Register */ /*! @{ */ + #define VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_MASK (0x1U) #define VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_SHIFT (0U) -/*! CSI_SEL - CSI sensor data input mux selector. +/*! CSI_SEL - CSI sensor data input mux selector + * 0b0..CSI sensor data is from Parallel CSI + * 0b1..CSI sensor data is from MIPI CSI */ #define VIDEO_MUX_VID_MUX_CTRL_CSI_SEL(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_MASK) + #define VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_MASK (0x2U) #define VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_SHIFT (1U) /*! LCDIF2_SEL - LCDIF2 sensor data input mux selector + * 0b0..LCDIFv2 sensor data is from Parallel CSI + * 0b1..LCDIFv2 sensor data is from MIPI CSI */ #define VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_MASK) + #define VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_MASK (0x4U) #define VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_SHIFT (2U) -/*! MIPI_DSI_SEL - MIPI DSI video data input mux selector. +/*! MIPI_DSI_SEL - MIPI DSI video data input mux selector + * 0b0..MIPI DSI video data is from eLCDIF + * 0b1..MIPI DSI video data is from LCDIFv2 */ #define VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_MASK) + #define VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_MASK (0x8U) #define VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_SHIFT (3U) +/*! PARA_LCD_SEL - Parallel LCDIF video data input mux selector + * 0b0..Parallel LCDIF video data is from eLCDIF + * 0b1..Parallel LCDIF video data is from LCDIFv2 + */ #define VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_MASK) /*! @} */ -/*! @name STREAM_FENCING_CTRL - CTRL_FENCE_VC Register */ +/*! @name PLM_CTRL - Pixel Link Master(PLM) Control Register */ /*! @{ */ -#define VIDEO_MUX_STREAM_FENCING_CTRL_FENCE_VC0_MASK (0x1U) -#define VIDEO_MUX_STREAM_FENCING_CTRL_FENCE_VC0_SHIFT (0U) -#define VIDEO_MUX_STREAM_FENCING_CTRL_FENCE_VC0(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_STREAM_FENCING_CTRL_FENCE_VC0_SHIFT)) & VIDEO_MUX_STREAM_FENCING_CTRL_FENCE_VC0_MASK) -#define VIDEO_MUX_STREAM_FENCING_CTRL_FENCE_VC1_MASK (0x2U) -#define VIDEO_MUX_STREAM_FENCING_CTRL_FENCE_VC1_SHIFT (1U) -#define VIDEO_MUX_STREAM_FENCING_CTRL_FENCE_VC1(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_STREAM_FENCING_CTRL_FENCE_VC1_SHIFT)) & VIDEO_MUX_STREAM_FENCING_CTRL_FENCE_VC1_MASK) -#define VIDEO_MUX_STREAM_FENCING_CTRL_FENCE_VC2_MASK (0x4U) -#define VIDEO_MUX_STREAM_FENCING_CTRL_FENCE_VC2_SHIFT (2U) -#define VIDEO_MUX_STREAM_FENCING_CTRL_FENCE_VC2(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_STREAM_FENCING_CTRL_FENCE_VC2_SHIFT)) & VIDEO_MUX_STREAM_FENCING_CTRL_FENCE_VC2_MASK) -#define VIDEO_MUX_STREAM_FENCING_CTRL_FENCE_VC3_MASK (0x8U) -#define VIDEO_MUX_STREAM_FENCING_CTRL_FENCE_VC3_SHIFT (3U) -#define VIDEO_MUX_STREAM_FENCING_CTRL_FENCE_VC3(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_STREAM_FENCING_CTRL_FENCE_VC3_SHIFT)) & VIDEO_MUX_STREAM_FENCING_CTRL_FENCE_VC3_MASK) -/*! @} */ -/*! @name PLM_CTRL - PLM Control register */ -/*! @{ */ #define VIDEO_MUX_PLM_CTRL_ENABLE_MASK (0x1U) #define VIDEO_MUX_PLM_CTRL_ENABLE_SHIFT (0U) -/*! ENABLE - Enable bit +/*! ENABLE - Enable the output of HYSNC and VSYNC + * 0b0..No active HSYNC and VSYNC output + * 0b1..Active HSYNC and VSYNC output */ #define VIDEO_MUX_PLM_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_ENABLE_SHIFT)) & VIDEO_MUX_PLM_CTRL_ENABLE_MASK) + #define VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_MASK (0x2U) #define VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_SHIFT (1U) /*! VSYNC_OVERRIDE - VSYNC override + * 0b1..VSYNC is asserted + * 0b0..VSYNC is not asserted */ #define VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_MASK) + #define VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_MASK (0x4U) #define VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_SHIFT (2U) /*! HSYNC_OVERRIDE - HSYNC override + * 0b1..HSYNC is asserted + * 0b0..HSYNC is not asserted */ #define VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_MASK) + #define VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK (0x8U) #define VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_SHIFT (3U) -/*! VALID_OVERRIDE - valid override +/*! VALID_OVERRIDE - Valid override + * 0b0..HSYNC and VSYNC is asserted + * 0b1..HSYNC and VSYNC is not asserted */ #define VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK) + #define VIDEO_MUX_PLM_CTRL_POLARITY_MASK (0x10U) #define VIDEO_MUX_PLM_CTRL_POLARITY_SHIFT (4U) +/*! POLARITY - Polarity of HYSNC/VSYNC + * 0b0..Keep the current polarity of HSYNC and VSYNC + * 0b1..Invert the polarity of HSYNC and VSYNC + */ #define VIDEO_MUX_PLM_CTRL_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_POLARITY_SHIFT)) & VIDEO_MUX_PLM_CTRL_POLARITY_MASK) /*! @} */ -/*! @name YUV420_CTRL - YUV420_CTRL */ +/*! @name YUV420_CTRL - YUV420 Control Register */ /*! @{ */ + #define VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_MASK (0x1U) #define VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_SHIFT (0U) +/*! FST_LN_DATA_TYPE - Data type of First Line + * 0b0..Odd (default) + * 0b1..Even + */ #define VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_SHIFT)) & VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_MASK) /*! @} */ -/*! @name STREAM_FENCING_STAT - STREAM_FENCING_STAT register */ +/*! @name CFG_DT_DISABLE - Data Disable Register */ /*! @{ */ -#define VIDEO_MUX_STREAM_FENCING_STAT_VC0_FENCED_MASK (0x1U) -#define VIDEO_MUX_STREAM_FENCING_STAT_VC0_FENCED_SHIFT (0U) -#define VIDEO_MUX_STREAM_FENCING_STAT_VC0_FENCED(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_STREAM_FENCING_STAT_VC0_FENCED_SHIFT)) & VIDEO_MUX_STREAM_FENCING_STAT_VC0_FENCED_MASK) -#define VIDEO_MUX_STREAM_FENCING_STAT_VC1_FENCED_MASK (0x2U) -#define VIDEO_MUX_STREAM_FENCING_STAT_VC1_FENCED_SHIFT (1U) -#define VIDEO_MUX_STREAM_FENCING_STAT_VC1_FENCED(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_STREAM_FENCING_STAT_VC1_FENCED_SHIFT)) & VIDEO_MUX_STREAM_FENCING_STAT_VC1_FENCED_MASK) -#define VIDEO_MUX_STREAM_FENCING_STAT_VC2_FENCED_MASK (0x4U) -#define VIDEO_MUX_STREAM_FENCING_STAT_VC2_FENCED_SHIFT (2U) -#define VIDEO_MUX_STREAM_FENCING_STAT_VC2_FENCED(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_STREAM_FENCING_STAT_VC2_FENCED_SHIFT)) & VIDEO_MUX_STREAM_FENCING_STAT_VC2_FENCED_MASK) -#define VIDEO_MUX_STREAM_FENCING_STAT_VC3_FENCED_MASK (0x8U) -#define VIDEO_MUX_STREAM_FENCING_STAT_VC3_FENCED_SHIFT (3U) -#define VIDEO_MUX_STREAM_FENCING_STAT_VC3_FENCED(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_STREAM_FENCING_STAT_VC3_FENCED_SHIFT)) & VIDEO_MUX_STREAM_FENCING_STAT_VC3_FENCED_MASK) -/*! @} */ -/*! @name CFG_DT_DISABLE - PRG Base Address Register */ -/*! @{ */ #define VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_MASK (0xFFFFFFU) #define VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_SHIFT (0U) -#define VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_SHIFT)) & VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_MASK) -/*! @} */ - -/*! @name VC_INTERLACED - VC_INTERLACED */ -/*! @{ */ -#define VIDEO_MUX_VC_INTERLACED_VC0_INTERLACED_MASK (0x1U) -#define VIDEO_MUX_VC_INTERLACED_VC0_INTERLACED_SHIFT (0U) -/*! VC0_INTERLACED - VC0_INTERLACED - */ -#define VIDEO_MUX_VC_INTERLACED_VC0_INTERLACED(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VC_INTERLACED_VC0_INTERLACED_SHIFT)) & VIDEO_MUX_VC_INTERLACED_VC0_INTERLACED_MASK) -#define VIDEO_MUX_VC_INTERLACED_VC1_INTERLACED_MASK (0x2U) -#define VIDEO_MUX_VC_INTERLACED_VC1_INTERLACED_SHIFT (1U) -/*! VC1_INTERLACED - VC1_INTERLACED - */ -#define VIDEO_MUX_VC_INTERLACED_VC1_INTERLACED(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VC_INTERLACED_VC1_INTERLACED_SHIFT)) & VIDEO_MUX_VC_INTERLACED_VC1_INTERLACED_MASK) -#define VIDEO_MUX_VC_INTERLACED_VC2_INTERLACED_MASK (0x4U) -#define VIDEO_MUX_VC_INTERLACED_VC2_INTERLACED_SHIFT (2U) -/*! VC2_INTERLACED - VC2_INTERLACED +/*! CFG_DT_DISABLE - Data Type Disable */ -#define VIDEO_MUX_VC_INTERLACED_VC2_INTERLACED(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VC_INTERLACED_VC2_INTERLACED_SHIFT)) & VIDEO_MUX_VC_INTERLACED_VC2_INTERLACED_MASK) -#define VIDEO_MUX_VC_INTERLACED_VC3_INTERLACED_MASK (0x8U) -#define VIDEO_MUX_VC_INTERLACED_VC3_INTERLACED_SHIFT (3U) -/*! VC3_INTERLACED - VC3_INTERLACED - */ -#define VIDEO_MUX_VC_INTERLACED_VC3_INTERLACED(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VC_INTERLACED_VC3_INTERLACED_SHIFT)) & VIDEO_MUX_VC_INTERLACED_VC3_INTERLACED_MASK) +#define VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_SHIFT)) & VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_MASK) /*! @} */ /*! @name MIPI_DSI_CTRL - MIPI DSI Control Register */ /*! @{ */ + #define VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_MASK (0x1U) #define VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_SHIFT (0U) +/*! DPI_SD - Shut Down - Control to shutdown display (type 4 only) + * 0b0..No effect + * 0b1..Send shutdown command + */ #define VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_SHIFT)) & VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_MASK) + #define VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_MASK (0x2U) #define VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_SHIFT (1U) +/*! DPI_CM - Color Mode control + * 0b0..Normal Mode + * 0b1..Low-color mode + */ #define VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_SHIFT)) & VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_MASK) /*! @} */ @@ -90095,30 +100567,6 @@ typedef struct { __IO uint32_t CLR; /**< Fractional PLL Denominator Control Register, offset: 0x38 */ __IO uint32_t TOG; /**< Fractional PLL Denominator Control Register, offset: 0x3C */ } DENOMINATOR; - struct { /* offset: 0x40 */ - uint32_t RW; /**< Fractional PLL Reserved Control Register, offset: 0x40 */ - uint32_t SET; /**< Fractional PLL Reserved Control Register, offset: 0x44 */ - uint32_t CLR; /**< Fractional PLL Reserved Control Register, offset: 0x48 */ - uint32_t TOG; /**< Fractional PLL Reserved Control Register, offset: 0x4C */ - } CTRL4; - struct { /* offset: 0x50 */ - __I uint32_t RW; /**< Analog Status Register STAT0, offset: 0x50 */ - __I uint32_t SET; /**< Analog Status Register STAT0, offset: 0x54 */ - __I uint32_t CLR; /**< Analog Status Register STAT0, offset: 0x58 */ - __I uint32_t TOG; /**< Analog Status Register STAT0, offset: 0x5C */ - } STAT0; - struct { /* offset: 0x60 */ - __I uint32_t RW; /**< Analog Status Register STAT1, offset: 0x60 */ - __I uint32_t SET; /**< Analog Status Register STAT1, offset: 0x64 */ - __I uint32_t CLR; /**< Analog Status Register STAT1, offset: 0x68 */ - __I uint32_t TOG; /**< Analog Status Register STAT1, offset: 0x6C */ - } STAT1; - struct { /* offset: 0x70 */ - __I uint32_t RW; /**< Analog Status Register STAT2, offset: 0x70 */ - __I uint32_t SET; /**< Analog Status Register STAT2, offset: 0x74 */ - __I uint32_t CLR; /**< Analog Status Register STAT2, offset: 0x78 */ - __I uint32_t TOG; /**< Analog Status Register STAT2, offset: 0x7C */ - } STAT2; } VIDEO_PLL_Type; /* ---------------------------------------------------------------------------- @@ -90132,105 +100580,109 @@ typedef struct { /*! @name CTRL0 - Fractional PLL Control Register */ /*! @{ */ + #define VIDEO_PLL_CTRL0_DIV_SELECT_MASK (0x7FU) #define VIDEO_PLL_CTRL0_DIV_SELECT_SHIFT (0U) /*! DIV_SELECT - DIV_SELECT */ #define VIDEO_PLL_CTRL0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_DIV_SELECT_SHIFT)) & VIDEO_PLL_CTRL0_DIV_SELECT_MASK) -#define VIDEO_PLL_CTRL0_HALF_LF_MASK (0x200U) -#define VIDEO_PLL_CTRL0_HALF_LF_SHIFT (9U) -/*! HALF_LF - HALF_LF - */ -#define VIDEO_PLL_CTRL0_HALF_LF(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_HALF_LF_SHIFT)) & VIDEO_PLL_CTRL0_HALF_LF_MASK) -#define VIDEO_PLL_CTRL0_DOUBLE_LF_MASK (0x400U) -#define VIDEO_PLL_CTRL0_DOUBLE_LF_SHIFT (10U) -/*! DOUBLE_LF - DOUBLE_LF - */ -#define VIDEO_PLL_CTRL0_DOUBLE_LF(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_DOUBLE_LF_SHIFT)) & VIDEO_PLL_CTRL0_DOUBLE_LF_MASK) -#define VIDEO_PLL_CTRL0_HALF_CP_MASK (0x800U) -#define VIDEO_PLL_CTRL0_HALF_CP_SHIFT (11U) -/*! HALF_CP - HALF_CP - */ -#define VIDEO_PLL_CTRL0_HALF_CP(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_HALF_CP_SHIFT)) & VIDEO_PLL_CTRL0_HALF_CP_MASK) -#define VIDEO_PLL_CTRL0_DOUBLE_CP_MASK (0x1000U) -#define VIDEO_PLL_CTRL0_DOUBLE_CP_SHIFT (12U) -/*! DOUBLE_CP - DOUBLE_CP - */ -#define VIDEO_PLL_CTRL0_DOUBLE_CP(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_DOUBLE_CP_SHIFT)) & VIDEO_PLL_CTRL0_DOUBLE_CP_MASK) + +#define VIDEO_PLL_CTRL0_ENABLE_ALT_MASK (0x100U) +#define VIDEO_PLL_CTRL0_ENABLE_ALT_SHIFT (8U) +/*! ENABLE_ALT - ENABLE_ALT + * 0b0..Disable the alternate clock output + * 0b1..Enable the alternate clock output which is the output of the post_divider, and cannot be bypassed + */ +#define VIDEO_PLL_CTRL0_ENABLE_ALT(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_ENABLE_ALT_SHIFT)) & VIDEO_PLL_CTRL0_ENABLE_ALT_MASK) + #define VIDEO_PLL_CTRL0_HOLD_RING_OFF_MASK (0x2000U) #define VIDEO_PLL_CTRL0_HOLD_RING_OFF_SHIFT (13U) -/*! HOLD_RING_OFF - HOLD_RING_OFF +/*! HOLD_RING_OFF - PLL Start up initialization + * 0b0..Normal operation + * 0b1..Initialize PLL start up */ #define VIDEO_PLL_CTRL0_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_HOLD_RING_OFF_SHIFT)) & VIDEO_PLL_CTRL0_HOLD_RING_OFF_MASK) + #define VIDEO_PLL_CTRL0_POWERUP_MASK (0x4000U) #define VIDEO_PLL_CTRL0_POWERUP_SHIFT (14U) /*! POWERUP - POWERUP + * 0b1..Power Up the PLL + * 0b0..Power down the PLL */ #define VIDEO_PLL_CTRL0_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_POWERUP_SHIFT)) & VIDEO_PLL_CTRL0_POWERUP_MASK) + #define VIDEO_PLL_CTRL0_ENABLE_MASK (0x8000U) #define VIDEO_PLL_CTRL0_ENABLE_SHIFT (15U) /*! ENABLE - ENABLE + * 0b1..Enable the clock output + * 0b0..Disable the clock output */ #define VIDEO_PLL_CTRL0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_ENABLE_SHIFT)) & VIDEO_PLL_CTRL0_ENABLE_MASK) + #define VIDEO_PLL_CTRL0_BYPASS_MASK (0x10000U) #define VIDEO_PLL_CTRL0_BYPASS_SHIFT (16U) /*! BYPASS - BYPASS + * 0b1..Bypass the PLL + * 0b0..No Bypass */ #define VIDEO_PLL_CTRL0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_BYPASS_SHIFT)) & VIDEO_PLL_CTRL0_BYPASS_MASK) + #define VIDEO_PLL_CTRL0_DITHER_EN_MASK (0x20000U) #define VIDEO_PLL_CTRL0_DITHER_EN_SHIFT (17U) /*! DITHER_EN - DITHER_EN + * 0b0..Disable Dither + * 0b1..Enable Dither */ #define VIDEO_PLL_CTRL0_DITHER_EN(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_DITHER_EN_SHIFT)) & VIDEO_PLL_CTRL0_DITHER_EN_MASK) -#define VIDEO_PLL_CTRL0_PFD_OFFSET_EN_MASK (0x40000U) -#define VIDEO_PLL_CTRL0_PFD_OFFSET_EN_SHIFT (18U) -/*! PFD_OFFSET_EN - PFD_OFFSET_EN - */ -#define VIDEO_PLL_CTRL0_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_PFD_OFFSET_EN_SHIFT)) & VIDEO_PLL_CTRL0_PFD_OFFSET_EN_MASK) + #define VIDEO_PLL_CTRL0_BIAS_TRIM_MASK (0x380000U) #define VIDEO_PLL_CTRL0_BIAS_TRIM_SHIFT (19U) /*! BIAS_TRIM - BIAS_TRIM */ #define VIDEO_PLL_CTRL0_BIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_BIAS_TRIM_SHIFT)) & VIDEO_PLL_CTRL0_BIAS_TRIM_MASK) + #define VIDEO_PLL_CTRL0_PLL_REG_EN_MASK (0x400000U) #define VIDEO_PLL_CTRL0_PLL_REG_EN_SHIFT (22U) /*! PLL_REG_EN - PLL_REG_EN */ #define VIDEO_PLL_CTRL0_PLL_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_PLL_REG_EN_SHIFT)) & VIDEO_PLL_CTRL0_PLL_REG_EN_MASK) -#define VIDEO_PLL_CTRL0_REGULATOR_VOLT_TRIM_MASK (0x1800000U) -#define VIDEO_PLL_CTRL0_REGULATOR_VOLT_TRIM_SHIFT (23U) -/*! REGULATOR_VOLT_TRIM - Regulator trim - */ -#define VIDEO_PLL_CTRL0_REGULATOR_VOLT_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_REGULATOR_VOLT_TRIM_SHIFT)) & VIDEO_PLL_CTRL0_REGULATOR_VOLT_TRIM_MASK) + #define VIDEO_PLL_CTRL0_POST_DIV_SEL_MASK (0xE000000U) #define VIDEO_PLL_CTRL0_POST_DIV_SEL_SHIFT (25U) /*! POST_DIV_SEL - Post Divide Select + * 0b000..Divide by 1 + * 0b001..Divide by 2 + * 0b010..Divide by 4 + * 0b011..Divide by 8 + * 0b100..Divide by 16 + * 0b101..Divide by 32 */ #define VIDEO_PLL_CTRL0_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & VIDEO_PLL_CTRL0_POST_DIV_SEL_MASK) -#define VIDEO_PLL_CTRL0_TEST_MODE_MASK (0x40000000U) -#define VIDEO_PLL_CTRL0_TEST_MODE_SHIFT (30U) -/*! TEST_MODE - TEST_MODE - */ -#define VIDEO_PLL_CTRL0_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_TEST_MODE_SHIFT)) & VIDEO_PLL_CTRL0_TEST_MODE_MASK) -#define VIDEO_PLL_CTRL0_TEST_MUX_ENABLE_MASK (0x80000000U) -#define VIDEO_PLL_CTRL0_TEST_MUX_ENABLE_SHIFT (31U) -/*! TEST_MUX_ENABLE - TEST_MUX_ENABLE + +#define VIDEO_PLL_CTRL0_BIAS_SELECT_MASK (0x20000000U) +#define VIDEO_PLL_CTRL0_BIAS_SELECT_SHIFT (29U) +/*! BIAS_SELECT - BIAS_SELECT + * 0b0..Used in SoCs with a bias current of 10uA + * 0b1..Used in SoCs with a bias current of 2uA */ -#define VIDEO_PLL_CTRL0_TEST_MUX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_TEST_MUX_ENABLE_SHIFT)) & VIDEO_PLL_CTRL0_TEST_MUX_ENABLE_MASK) +#define VIDEO_PLL_CTRL0_BIAS_SELECT(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_BIAS_SELECT_SHIFT)) & VIDEO_PLL_CTRL0_BIAS_SELECT_MASK) /*! @} */ /*! @name SPREAD_SPECTRUM - Fractional PLL Spread Spectrum Control Register */ /*! @{ */ + #define VIDEO_PLL_SPREAD_SPECTRUM_STEP_MASK (0x7FFFU) #define VIDEO_PLL_SPREAD_SPECTRUM_STEP_SHIFT (0U) /*! STEP - Step */ #define VIDEO_PLL_SPREAD_SPECTRUM_STEP(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_SPREAD_SPECTRUM_STEP_SHIFT)) & VIDEO_PLL_SPREAD_SPECTRUM_STEP_MASK) + #define VIDEO_PLL_SPREAD_SPECTRUM_ENABLE_MASK (0x8000U) #define VIDEO_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT (15U) /*! ENABLE - Enable */ #define VIDEO_PLL_SPREAD_SPECTRUM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT)) & VIDEO_PLL_SPREAD_SPECTRUM_ENABLE_MASK) + #define VIDEO_PLL_SPREAD_SPECTRUM_STOP_MASK (0xFFFF0000U) #define VIDEO_PLL_SPREAD_SPECTRUM_STOP_SHIFT (16U) /*! STOP - Stop @@ -90240,6 +100692,7 @@ typedef struct { /*! @name NUMERATOR - Fractional PLL Numerator Control Register */ /*! @{ */ + #define VIDEO_PLL_NUMERATOR_NUM_MASK (0x3FFFFFFFU) #define VIDEO_PLL_NUMERATOR_NUM_SHIFT (0U) /*! NUM - Numerator @@ -90249,6 +100702,7 @@ typedef struct { /*! @name DENOMINATOR - Fractional PLL Denominator Control Register */ /*! @{ */ + #define VIDEO_PLL_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU) #define VIDEO_PLL_DENOMINATOR_DENOM_SHIFT (0U) /*! DENOM - Denominator @@ -90256,33 +100710,6 @@ typedef struct { #define VIDEO_PLL_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_DENOMINATOR_DENOM_SHIFT)) & VIDEO_PLL_DENOMINATOR_DENOM_MASK) /*! @} */ -/*! @name STAT0 - Analog Status Register STAT0 */ -/*! @{ */ -#define VIDEO_PLL_STAT0_REG_MASK (0xFFFFFFFFU) -#define VIDEO_PLL_STAT0_REG_SHIFT (0U) -/*! REG - STAT0 Register - */ -#define VIDEO_PLL_STAT0_REG(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_STAT0_REG_SHIFT)) & VIDEO_PLL_STAT0_REG_MASK) -/*! @} */ - -/*! @name STAT1 - Analog Status Register STAT1 */ -/*! @{ */ -#define VIDEO_PLL_STAT1_REG_MASK (0xFFFFFFFFU) -#define VIDEO_PLL_STAT1_REG_SHIFT (0U) -/*! REG - STAT1 Register - */ -#define VIDEO_PLL_STAT1_REG(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_STAT1_REG_SHIFT)) & VIDEO_PLL_STAT1_REG_MASK) -/*! @} */ - -/*! @name STAT2 - Analog Status Register STAT2 */ -/*! @{ */ -#define VIDEO_PLL_STAT2_REG_MASK (0xFFFFFFFFU) -#define VIDEO_PLL_STAT2_REG_SHIFT (0U) -/*! REG - STAT2 Register - */ -#define VIDEO_PLL_STAT2_REG(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_STAT2_REG_SHIFT)) & VIDEO_PLL_STAT2_REG_MASK) -/*! @} */ - /*! * @} @@ -90341,26 +100768,31 @@ typedef struct { /*! @name CTRL0 - Analog Control Register CTRL0 */ /*! @{ */ + #define VMBANDGAP_CTRL0_REFTOP_PWD_MASK (0x1U) #define VMBANDGAP_CTRL0_REFTOP_PWD_SHIFT (0U) /*! REFTOP_PWD - Master power-down for bandgap module */ #define VMBANDGAP_CTRL0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_PWD_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_PWD_MASK) + #define VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK (0x2U) #define VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_SHIFT (1U) /*! REFTOP_LINREGREF_PWD - Power-down for bandgap voltage-reference buffer */ #define VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK) + #define VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK (0x4U) #define VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT (2U) /*! REFTOP_PWDVBGUP - Power-down VBGUP detector in bandgap */ #define VMBANDGAP_CTRL0_REFTOP_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK) + #define VMBANDGAP_CTRL0_REFTOP_LOWPOWER_MASK (0x8U) #define VMBANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT (3U) /*! REFTOP_LOWPOWER - Low-power control bit */ #define VMBANDGAP_CTRL0_REFTOP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_LOWPOWER_MASK) + #define VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK (0x10U) #define VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_SHIFT (4U) /*! REFTOP_SELFBIASOFF - bandgap self-bias control bit @@ -90370,21 +100802,25 @@ typedef struct { /*! @name STAT0 - Analog Status Register STAT0 */ /*! @{ */ + #define VMBANDGAP_STAT0_REFTOP_VBGUP_MASK (0x1U) #define VMBANDGAP_STAT0_REFTOP_VBGUP_SHIFT (0U) /*! REFTOP_VBGUP - Brief description here */ #define VMBANDGAP_STAT0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_REFTOP_VBGUP_SHIFT)) & VMBANDGAP_STAT0_REFTOP_VBGUP_MASK) + #define VMBANDGAP_STAT0_VDD1_PORB_MASK (0x2U) #define VMBANDGAP_STAT0_VDD1_PORB_SHIFT (1U) /*! VDD1_PORB - Brief description here */ #define VMBANDGAP_STAT0_VDD1_PORB(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_VDD1_PORB_SHIFT)) & VMBANDGAP_STAT0_VDD1_PORB_MASK) + #define VMBANDGAP_STAT0_VDD2_PORB_MASK (0x4U) #define VMBANDGAP_STAT0_VDD2_PORB_SHIFT (2U) /*! VDD2_PORB - Brief description here */ #define VMBANDGAP_STAT0_VDD2_PORB(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_VDD2_PORB_SHIFT)) & VMBANDGAP_STAT0_VDD2_PORB_MASK) + #define VMBANDGAP_STAT0_VDD3_PORB_MASK (0x8U) #define VMBANDGAP_STAT0_VDD3_PORB_SHIFT (3U) /*! VDD3_PORB - Brief description here @@ -90442,6 +100878,7 @@ typedef struct { /*! @name WCR - Watchdog Control Register */ /*! @{ */ + #define WDOG_WCR_WDZST_MASK (0x1U) #define WDOG_WCR_WDZST_SHIFT (0U) /*! WDZST - WDZST @@ -90449,6 +100886,7 @@ typedef struct { * 0b1..Suspend the watchdog timer. */ #define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK) + #define WDOG_WCR_WDBG_MASK (0x2U) #define WDOG_WCR_WDBG_SHIFT (1U) /*! WDBG - WDBG @@ -90456,6 +100894,7 @@ typedef struct { * 0b1..Suspend the watchdog timer. */ #define WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK) + #define WDOG_WCR_WDE_MASK (0x4U) #define WDOG_WCR_WDE_SHIFT (2U) /*! WDE - WDE @@ -90463,6 +100902,7 @@ typedef struct { * 0b1..Enable the Watchdog. */ #define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK) + #define WDOG_WCR_WDT_MASK (0x8U) #define WDOG_WCR_WDT_SHIFT (3U) /*! WDT - WDT @@ -90470,6 +100910,7 @@ typedef struct { * 0b1..Assert WDOG_B upon a Watchdog Time-out event. */ #define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK) + #define WDOG_WCR_SRS_MASK (0x10U) #define WDOG_WCR_SRS_SHIFT (4U) /*! SRS - SRS @@ -90477,6 +100918,7 @@ typedef struct { * 0b1..No effect on the system (Default). */ #define WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK) + #define WDOG_WCR_WDA_MASK (0x20U) #define WDOG_WCR_WDA_SHIFT (5U) /*! WDA - WDA @@ -90484,13 +100926,15 @@ typedef struct { * 0b1..No effect on system (Default). */ #define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK) + #define WDOG_WCR_SRE_MASK (0x40U) #define WDOG_WCR_SRE_SHIFT (6U) -/*! SRE - software reset extension, an option way to generate software reset +/*! SRE - Software Reset Extension, an optional way to generate software reset * 0b0..using original way to generate software reset (default) * 0b1..using new way to generate software reset. */ #define WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK) + #define WDOG_WCR_WDW_MASK (0x80U) #define WDOG_WCR_WDW_SHIFT (7U) /*! WDW - WDW @@ -90498,6 +100942,7 @@ typedef struct { * 0b1..Suspend WDOG timer operation. */ #define WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK) + #define WDOG_WCR_WT_MASK (0xFF00U) #define WDOG_WCR_WT_SHIFT (8U) /*! WT - WT @@ -90512,6 +100957,7 @@ typedef struct { /*! @name WSR - Watchdog Service Register */ /*! @{ */ + #define WDOG_WSR_WSR_MASK (0xFFFFU) #define WDOG_WSR_WSR_SHIFT (0U) /*! WSR - WSR @@ -90523,6 +100969,7 @@ typedef struct { /*! @name WRSR - Watchdog Reset Status Register */ /*! @{ */ + #define WDOG_WRSR_SFTW_MASK (0x1U) #define WDOG_WRSR_SFTW_SHIFT (0U) /*! SFTW - SFTW @@ -90530,6 +100977,7 @@ typedef struct { * 0b1..Reset is the result of a software reset. */ #define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK) + #define WDOG_WRSR_TOUT_MASK (0x2U) #define WDOG_WRSR_TOUT_SHIFT (1U) /*! TOUT - TOUT @@ -90537,6 +100985,7 @@ typedef struct { * 0b1..Reset is the result of a WDOG timeout. */ #define WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK) + #define WDOG_WRSR_POR_MASK (0x10U) #define WDOG_WRSR_POR_SHIFT (4U) /*! POR - POR @@ -90548,6 +100997,7 @@ typedef struct { /*! @name WICR - Watchdog Interrupt Control Register */ /*! @{ */ + #define WDOG_WICR_WICT_MASK (0xFFU) #define WDOG_WICR_WICT_SHIFT (0U) /*! WICT - WICT @@ -90557,6 +101007,7 @@ typedef struct { * 0b11111111..WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds. */ #define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK) + #define WDOG_WICR_WTIS_MASK (0x4000U) #define WDOG_WICR_WTIS_SHIFT (14U) /*! WTIS - WTIS @@ -90564,6 +101015,7 @@ typedef struct { * 0b1..Interrupt has occurred */ #define WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK) + #define WDOG_WICR_WIE_MASK (0x8000U) #define WDOG_WICR_WIE_SHIFT (15U) /*! WIE - WIE @@ -90575,6 +101027,7 @@ typedef struct { /*! @name WMCR - Watchdog Miscellaneous Control Register */ /*! @{ */ + #define WDOG_WMCR_PDE_MASK (0x1U) #define WDOG_WMCR_PDE_SHIFT (0U) /*! PDE - PDE @@ -90725,9 +101178,11 @@ typedef struct { /*! @name SEL0 - Crossbar A Select Register 0 */ /*! @{ */ + #define XBARA_SEL0_SEL0_MASK (0xFFU) #define XBARA_SEL0_SEL0_SHIFT (0U) #define XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK) + #define XBARA_SEL0_SEL1_MASK (0xFF00U) #define XBARA_SEL0_SEL1_SHIFT (8U) #define XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK) @@ -90735,9 +101190,11 @@ typedef struct { /*! @name SEL1 - Crossbar A Select Register 1 */ /*! @{ */ + #define XBARA_SEL1_SEL2_MASK (0xFFU) #define XBARA_SEL1_SEL2_SHIFT (0U) #define XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK) + #define XBARA_SEL1_SEL3_MASK (0xFF00U) #define XBARA_SEL1_SEL3_SHIFT (8U) #define XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK) @@ -90745,9 +101202,11 @@ typedef struct { /*! @name SEL2 - Crossbar A Select Register 2 */ /*! @{ */ + #define XBARA_SEL2_SEL4_MASK (0xFFU) #define XBARA_SEL2_SEL4_SHIFT (0U) #define XBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK) + #define XBARA_SEL2_SEL5_MASK (0xFF00U) #define XBARA_SEL2_SEL5_SHIFT (8U) #define XBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK) @@ -90755,9 +101214,11 @@ typedef struct { /*! @name SEL3 - Crossbar A Select Register 3 */ /*! @{ */ + #define XBARA_SEL3_SEL6_MASK (0xFFU) #define XBARA_SEL3_SEL6_SHIFT (0U) #define XBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK) + #define XBARA_SEL3_SEL7_MASK (0xFF00U) #define XBARA_SEL3_SEL7_SHIFT (8U) #define XBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK) @@ -90765,9 +101226,11 @@ typedef struct { /*! @name SEL4 - Crossbar A Select Register 4 */ /*! @{ */ + #define XBARA_SEL4_SEL8_MASK (0xFFU) #define XBARA_SEL4_SEL8_SHIFT (0U) #define XBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK) + #define XBARA_SEL4_SEL9_MASK (0xFF00U) #define XBARA_SEL4_SEL9_SHIFT (8U) #define XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK) @@ -90775,9 +101238,11 @@ typedef struct { /*! @name SEL5 - Crossbar A Select Register 5 */ /*! @{ */ + #define XBARA_SEL5_SEL10_MASK (0xFFU) #define XBARA_SEL5_SEL10_SHIFT (0U) #define XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK) + #define XBARA_SEL5_SEL11_MASK (0xFF00U) #define XBARA_SEL5_SEL11_SHIFT (8U) #define XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK) @@ -90785,9 +101250,11 @@ typedef struct { /*! @name SEL6 - Crossbar A Select Register 6 */ /*! @{ */ + #define XBARA_SEL6_SEL12_MASK (0xFFU) #define XBARA_SEL6_SEL12_SHIFT (0U) #define XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK) + #define XBARA_SEL6_SEL13_MASK (0xFF00U) #define XBARA_SEL6_SEL13_SHIFT (8U) #define XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK) @@ -90795,9 +101262,11 @@ typedef struct { /*! @name SEL7 - Crossbar A Select Register 7 */ /*! @{ */ + #define XBARA_SEL7_SEL14_MASK (0xFFU) #define XBARA_SEL7_SEL14_SHIFT (0U) #define XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK) + #define XBARA_SEL7_SEL15_MASK (0xFF00U) #define XBARA_SEL7_SEL15_SHIFT (8U) #define XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK) @@ -90805,9 +101274,11 @@ typedef struct { /*! @name SEL8 - Crossbar A Select Register 8 */ /*! @{ */ + #define XBARA_SEL8_SEL16_MASK (0xFFU) #define XBARA_SEL8_SEL16_SHIFT (0U) #define XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK) + #define XBARA_SEL8_SEL17_MASK (0xFF00U) #define XBARA_SEL8_SEL17_SHIFT (8U) #define XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK) @@ -90815,9 +101286,11 @@ typedef struct { /*! @name SEL9 - Crossbar A Select Register 9 */ /*! @{ */ + #define XBARA_SEL9_SEL18_MASK (0xFFU) #define XBARA_SEL9_SEL18_SHIFT (0U) #define XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK) + #define XBARA_SEL9_SEL19_MASK (0xFF00U) #define XBARA_SEL9_SEL19_SHIFT (8U) #define XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK) @@ -90825,9 +101298,11 @@ typedef struct { /*! @name SEL10 - Crossbar A Select Register 10 */ /*! @{ */ + #define XBARA_SEL10_SEL20_MASK (0xFFU) #define XBARA_SEL10_SEL20_SHIFT (0U) #define XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK) + #define XBARA_SEL10_SEL21_MASK (0xFF00U) #define XBARA_SEL10_SEL21_SHIFT (8U) #define XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK) @@ -90835,9 +101310,11 @@ typedef struct { /*! @name SEL11 - Crossbar A Select Register 11 */ /*! @{ */ + #define XBARA_SEL11_SEL22_MASK (0xFFU) #define XBARA_SEL11_SEL22_SHIFT (0U) #define XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK) + #define XBARA_SEL11_SEL23_MASK (0xFF00U) #define XBARA_SEL11_SEL23_SHIFT (8U) #define XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK) @@ -90845,9 +101322,11 @@ typedef struct { /*! @name SEL12 - Crossbar A Select Register 12 */ /*! @{ */ + #define XBARA_SEL12_SEL24_MASK (0xFFU) #define XBARA_SEL12_SEL24_SHIFT (0U) #define XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK) + #define XBARA_SEL12_SEL25_MASK (0xFF00U) #define XBARA_SEL12_SEL25_SHIFT (8U) #define XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK) @@ -90855,9 +101334,11 @@ typedef struct { /*! @name SEL13 - Crossbar A Select Register 13 */ /*! @{ */ + #define XBARA_SEL13_SEL26_MASK (0xFFU) #define XBARA_SEL13_SEL26_SHIFT (0U) #define XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK) + #define XBARA_SEL13_SEL27_MASK (0xFF00U) #define XBARA_SEL13_SEL27_SHIFT (8U) #define XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK) @@ -90865,9 +101346,11 @@ typedef struct { /*! @name SEL14 - Crossbar A Select Register 14 */ /*! @{ */ + #define XBARA_SEL14_SEL28_MASK (0xFFU) #define XBARA_SEL14_SEL28_SHIFT (0U) #define XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK) + #define XBARA_SEL14_SEL29_MASK (0xFF00U) #define XBARA_SEL14_SEL29_SHIFT (8U) #define XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK) @@ -90875,9 +101358,11 @@ typedef struct { /*! @name SEL15 - Crossbar A Select Register 15 */ /*! @{ */ + #define XBARA_SEL15_SEL30_MASK (0xFFU) #define XBARA_SEL15_SEL30_SHIFT (0U) #define XBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK) + #define XBARA_SEL15_SEL31_MASK (0xFF00U) #define XBARA_SEL15_SEL31_SHIFT (8U) #define XBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK) @@ -90885,9 +101370,11 @@ typedef struct { /*! @name SEL16 - Crossbar A Select Register 16 */ /*! @{ */ + #define XBARA_SEL16_SEL32_MASK (0xFFU) #define XBARA_SEL16_SEL32_SHIFT (0U) #define XBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK) + #define XBARA_SEL16_SEL33_MASK (0xFF00U) #define XBARA_SEL16_SEL33_SHIFT (8U) #define XBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK) @@ -90895,9 +101382,11 @@ typedef struct { /*! @name SEL17 - Crossbar A Select Register 17 */ /*! @{ */ + #define XBARA_SEL17_SEL34_MASK (0xFFU) #define XBARA_SEL17_SEL34_SHIFT (0U) #define XBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK) + #define XBARA_SEL17_SEL35_MASK (0xFF00U) #define XBARA_SEL17_SEL35_SHIFT (8U) #define XBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK) @@ -90905,9 +101394,11 @@ typedef struct { /*! @name SEL18 - Crossbar A Select Register 18 */ /*! @{ */ + #define XBARA_SEL18_SEL36_MASK (0xFFU) #define XBARA_SEL18_SEL36_SHIFT (0U) #define XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK) + #define XBARA_SEL18_SEL37_MASK (0xFF00U) #define XBARA_SEL18_SEL37_SHIFT (8U) #define XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK) @@ -90915,9 +101406,11 @@ typedef struct { /*! @name SEL19 - Crossbar A Select Register 19 */ /*! @{ */ + #define XBARA_SEL19_SEL38_MASK (0xFFU) #define XBARA_SEL19_SEL38_SHIFT (0U) #define XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK) + #define XBARA_SEL19_SEL39_MASK (0xFF00U) #define XBARA_SEL19_SEL39_SHIFT (8U) #define XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK) @@ -90925,9 +101418,11 @@ typedef struct { /*! @name SEL20 - Crossbar A Select Register 20 */ /*! @{ */ + #define XBARA_SEL20_SEL40_MASK (0xFFU) #define XBARA_SEL20_SEL40_SHIFT (0U) #define XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK) + #define XBARA_SEL20_SEL41_MASK (0xFF00U) #define XBARA_SEL20_SEL41_SHIFT (8U) #define XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK) @@ -90935,9 +101430,11 @@ typedef struct { /*! @name SEL21 - Crossbar A Select Register 21 */ /*! @{ */ + #define XBARA_SEL21_SEL42_MASK (0xFFU) #define XBARA_SEL21_SEL42_SHIFT (0U) #define XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK) + #define XBARA_SEL21_SEL43_MASK (0xFF00U) #define XBARA_SEL21_SEL43_SHIFT (8U) #define XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK) @@ -90945,9 +101442,11 @@ typedef struct { /*! @name SEL22 - Crossbar A Select Register 22 */ /*! @{ */ + #define XBARA_SEL22_SEL44_MASK (0xFFU) #define XBARA_SEL22_SEL44_SHIFT (0U) #define XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK) + #define XBARA_SEL22_SEL45_MASK (0xFF00U) #define XBARA_SEL22_SEL45_SHIFT (8U) #define XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK) @@ -90955,9 +101454,11 @@ typedef struct { /*! @name SEL23 - Crossbar A Select Register 23 */ /*! @{ */ + #define XBARA_SEL23_SEL46_MASK (0xFFU) #define XBARA_SEL23_SEL46_SHIFT (0U) #define XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK) + #define XBARA_SEL23_SEL47_MASK (0xFF00U) #define XBARA_SEL23_SEL47_SHIFT (8U) #define XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK) @@ -90965,9 +101466,11 @@ typedef struct { /*! @name SEL24 - Crossbar A Select Register 24 */ /*! @{ */ + #define XBARA_SEL24_SEL48_MASK (0xFFU) #define XBARA_SEL24_SEL48_SHIFT (0U) #define XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK) + #define XBARA_SEL24_SEL49_MASK (0xFF00U) #define XBARA_SEL24_SEL49_SHIFT (8U) #define XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK) @@ -90975,9 +101478,11 @@ typedef struct { /*! @name SEL25 - Crossbar A Select Register 25 */ /*! @{ */ + #define XBARA_SEL25_SEL50_MASK (0xFFU) #define XBARA_SEL25_SEL50_SHIFT (0U) #define XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK) + #define XBARA_SEL25_SEL51_MASK (0xFF00U) #define XBARA_SEL25_SEL51_SHIFT (8U) #define XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK) @@ -90985,9 +101490,11 @@ typedef struct { /*! @name SEL26 - Crossbar A Select Register 26 */ /*! @{ */ + #define XBARA_SEL26_SEL52_MASK (0xFFU) #define XBARA_SEL26_SEL52_SHIFT (0U) #define XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK) + #define XBARA_SEL26_SEL53_MASK (0xFF00U) #define XBARA_SEL26_SEL53_SHIFT (8U) #define XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK) @@ -90995,9 +101502,11 @@ typedef struct { /*! @name SEL27 - Crossbar A Select Register 27 */ /*! @{ */ + #define XBARA_SEL27_SEL54_MASK (0xFFU) #define XBARA_SEL27_SEL54_SHIFT (0U) #define XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK) + #define XBARA_SEL27_SEL55_MASK (0xFF00U) #define XBARA_SEL27_SEL55_SHIFT (8U) #define XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK) @@ -91005,9 +101514,11 @@ typedef struct { /*! @name SEL28 - Crossbar A Select Register 28 */ /*! @{ */ + #define XBARA_SEL28_SEL56_MASK (0xFFU) #define XBARA_SEL28_SEL56_SHIFT (0U) #define XBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK) + #define XBARA_SEL28_SEL57_MASK (0xFF00U) #define XBARA_SEL28_SEL57_SHIFT (8U) #define XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK) @@ -91015,9 +101526,11 @@ typedef struct { /*! @name SEL29 - Crossbar A Select Register 29 */ /*! @{ */ + #define XBARA_SEL29_SEL58_MASK (0xFFU) #define XBARA_SEL29_SEL58_SHIFT (0U) #define XBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK) + #define XBARA_SEL29_SEL59_MASK (0xFF00U) #define XBARA_SEL29_SEL59_SHIFT (8U) #define XBARA_SEL29_SEL59(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK) @@ -91025,9 +101538,11 @@ typedef struct { /*! @name SEL30 - Crossbar A Select Register 30 */ /*! @{ */ + #define XBARA_SEL30_SEL60_MASK (0xFFU) #define XBARA_SEL30_SEL60_SHIFT (0U) #define XBARA_SEL30_SEL60(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK) + #define XBARA_SEL30_SEL61_MASK (0xFF00U) #define XBARA_SEL30_SEL61_SHIFT (8U) #define XBARA_SEL30_SEL61(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK) @@ -91035,9 +101550,11 @@ typedef struct { /*! @name SEL31 - Crossbar A Select Register 31 */ /*! @{ */ + #define XBARA_SEL31_SEL62_MASK (0xFFU) #define XBARA_SEL31_SEL62_SHIFT (0U) #define XBARA_SEL31_SEL62(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK) + #define XBARA_SEL31_SEL63_MASK (0xFF00U) #define XBARA_SEL31_SEL63_SHIFT (8U) #define XBARA_SEL31_SEL63(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK) @@ -91045,9 +101562,11 @@ typedef struct { /*! @name SEL32 - Crossbar A Select Register 32 */ /*! @{ */ + #define XBARA_SEL32_SEL64_MASK (0xFFU) #define XBARA_SEL32_SEL64_SHIFT (0U) #define XBARA_SEL32_SEL64(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK) + #define XBARA_SEL32_SEL65_MASK (0xFF00U) #define XBARA_SEL32_SEL65_SHIFT (8U) #define XBARA_SEL32_SEL65(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK) @@ -91055,9 +101574,11 @@ typedef struct { /*! @name SEL33 - Crossbar A Select Register 33 */ /*! @{ */ + #define XBARA_SEL33_SEL66_MASK (0xFFU) #define XBARA_SEL33_SEL66_SHIFT (0U) #define XBARA_SEL33_SEL66(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK) + #define XBARA_SEL33_SEL67_MASK (0xFF00U) #define XBARA_SEL33_SEL67_SHIFT (8U) #define XBARA_SEL33_SEL67(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK) @@ -91065,9 +101586,11 @@ typedef struct { /*! @name SEL34 - Crossbar A Select Register 34 */ /*! @{ */ + #define XBARA_SEL34_SEL68_MASK (0xFFU) #define XBARA_SEL34_SEL68_SHIFT (0U) #define XBARA_SEL34_SEL68(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK) + #define XBARA_SEL34_SEL69_MASK (0xFF00U) #define XBARA_SEL34_SEL69_SHIFT (8U) #define XBARA_SEL34_SEL69(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK) @@ -91075,9 +101598,11 @@ typedef struct { /*! @name SEL35 - Crossbar A Select Register 35 */ /*! @{ */ + #define XBARA_SEL35_SEL70_MASK (0xFFU) #define XBARA_SEL35_SEL70_SHIFT (0U) #define XBARA_SEL35_SEL70(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK) + #define XBARA_SEL35_SEL71_MASK (0xFF00U) #define XBARA_SEL35_SEL71_SHIFT (8U) #define XBARA_SEL35_SEL71(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK) @@ -91085,9 +101610,11 @@ typedef struct { /*! @name SEL36 - Crossbar A Select Register 36 */ /*! @{ */ + #define XBARA_SEL36_SEL72_MASK (0xFFU) #define XBARA_SEL36_SEL72_SHIFT (0U) #define XBARA_SEL36_SEL72(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK) + #define XBARA_SEL36_SEL73_MASK (0xFF00U) #define XBARA_SEL36_SEL73_SHIFT (8U) #define XBARA_SEL36_SEL73(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK) @@ -91095,9 +101622,11 @@ typedef struct { /*! @name SEL37 - Crossbar A Select Register 37 */ /*! @{ */ + #define XBARA_SEL37_SEL74_MASK (0xFFU) #define XBARA_SEL37_SEL74_SHIFT (0U) #define XBARA_SEL37_SEL74(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK) + #define XBARA_SEL37_SEL75_MASK (0xFF00U) #define XBARA_SEL37_SEL75_SHIFT (8U) #define XBARA_SEL37_SEL75(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK) @@ -91105,9 +101634,11 @@ typedef struct { /*! @name SEL38 - Crossbar A Select Register 38 */ /*! @{ */ + #define XBARA_SEL38_SEL76_MASK (0xFFU) #define XBARA_SEL38_SEL76_SHIFT (0U) #define XBARA_SEL38_SEL76(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK) + #define XBARA_SEL38_SEL77_MASK (0xFF00U) #define XBARA_SEL38_SEL77_SHIFT (8U) #define XBARA_SEL38_SEL77(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK) @@ -91115,9 +101646,11 @@ typedef struct { /*! @name SEL39 - Crossbar A Select Register 39 */ /*! @{ */ + #define XBARA_SEL39_SEL78_MASK (0xFFU) #define XBARA_SEL39_SEL78_SHIFT (0U) #define XBARA_SEL39_SEL78(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK) + #define XBARA_SEL39_SEL79_MASK (0xFF00U) #define XBARA_SEL39_SEL79_SHIFT (8U) #define XBARA_SEL39_SEL79(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK) @@ -91125,9 +101658,11 @@ typedef struct { /*! @name SEL40 - Crossbar A Select Register 40 */ /*! @{ */ + #define XBARA_SEL40_SEL80_MASK (0xFFU) #define XBARA_SEL40_SEL80_SHIFT (0U) #define XBARA_SEL40_SEL80(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK) + #define XBARA_SEL40_SEL81_MASK (0xFF00U) #define XBARA_SEL40_SEL81_SHIFT (8U) #define XBARA_SEL40_SEL81(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK) @@ -91135,9 +101670,11 @@ typedef struct { /*! @name SEL41 - Crossbar A Select Register 41 */ /*! @{ */ + #define XBARA_SEL41_SEL82_MASK (0xFFU) #define XBARA_SEL41_SEL82_SHIFT (0U) #define XBARA_SEL41_SEL82(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK) + #define XBARA_SEL41_SEL83_MASK (0xFF00U) #define XBARA_SEL41_SEL83_SHIFT (8U) #define XBARA_SEL41_SEL83(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK) @@ -91145,9 +101682,11 @@ typedef struct { /*! @name SEL42 - Crossbar A Select Register 42 */ /*! @{ */ + #define XBARA_SEL42_SEL84_MASK (0xFFU) #define XBARA_SEL42_SEL84_SHIFT (0U) #define XBARA_SEL42_SEL84(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK) + #define XBARA_SEL42_SEL85_MASK (0xFF00U) #define XBARA_SEL42_SEL85_SHIFT (8U) #define XBARA_SEL42_SEL85(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK) @@ -91155,9 +101694,11 @@ typedef struct { /*! @name SEL43 - Crossbar A Select Register 43 */ /*! @{ */ + #define XBARA_SEL43_SEL86_MASK (0xFFU) #define XBARA_SEL43_SEL86_SHIFT (0U) #define XBARA_SEL43_SEL86(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK) + #define XBARA_SEL43_SEL87_MASK (0xFF00U) #define XBARA_SEL43_SEL87_SHIFT (8U) #define XBARA_SEL43_SEL87(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK) @@ -91165,9 +101706,11 @@ typedef struct { /*! @name SEL44 - Crossbar A Select Register 44 */ /*! @{ */ + #define XBARA_SEL44_SEL88_MASK (0xFFU) #define XBARA_SEL44_SEL88_SHIFT (0U) #define XBARA_SEL44_SEL88(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK) + #define XBARA_SEL44_SEL89_MASK (0xFF00U) #define XBARA_SEL44_SEL89_SHIFT (8U) #define XBARA_SEL44_SEL89(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK) @@ -91175,9 +101718,11 @@ typedef struct { /*! @name SEL45 - Crossbar A Select Register 45 */ /*! @{ */ + #define XBARA_SEL45_SEL90_MASK (0xFFU) #define XBARA_SEL45_SEL90_SHIFT (0U) #define XBARA_SEL45_SEL90(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK) + #define XBARA_SEL45_SEL91_MASK (0xFF00U) #define XBARA_SEL45_SEL91_SHIFT (8U) #define XBARA_SEL45_SEL91(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK) @@ -91185,9 +101730,11 @@ typedef struct { /*! @name SEL46 - Crossbar A Select Register 46 */ /*! @{ */ + #define XBARA_SEL46_SEL92_MASK (0xFFU) #define XBARA_SEL46_SEL92_SHIFT (0U) #define XBARA_SEL46_SEL92(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK) + #define XBARA_SEL46_SEL93_MASK (0xFF00U) #define XBARA_SEL46_SEL93_SHIFT (8U) #define XBARA_SEL46_SEL93(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK) @@ -91195,9 +101742,11 @@ typedef struct { /*! @name SEL47 - Crossbar A Select Register 47 */ /*! @{ */ + #define XBARA_SEL47_SEL94_MASK (0xFFU) #define XBARA_SEL47_SEL94_SHIFT (0U) #define XBARA_SEL47_SEL94(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK) + #define XBARA_SEL47_SEL95_MASK (0xFF00U) #define XBARA_SEL47_SEL95_SHIFT (8U) #define XBARA_SEL47_SEL95(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK) @@ -91205,9 +101754,11 @@ typedef struct { /*! @name SEL48 - Crossbar A Select Register 48 */ /*! @{ */ + #define XBARA_SEL48_SEL96_MASK (0xFFU) #define XBARA_SEL48_SEL96_SHIFT (0U) #define XBARA_SEL48_SEL96(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK) + #define XBARA_SEL48_SEL97_MASK (0xFF00U) #define XBARA_SEL48_SEL97_SHIFT (8U) #define XBARA_SEL48_SEL97(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK) @@ -91215,9 +101766,11 @@ typedef struct { /*! @name SEL49 - Crossbar A Select Register 49 */ /*! @{ */ + #define XBARA_SEL49_SEL98_MASK (0xFFU) #define XBARA_SEL49_SEL98_SHIFT (0U) #define XBARA_SEL49_SEL98(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK) + #define XBARA_SEL49_SEL99_MASK (0xFF00U) #define XBARA_SEL49_SEL99_SHIFT (8U) #define XBARA_SEL49_SEL99(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK) @@ -91225,9 +101778,11 @@ typedef struct { /*! @name SEL50 - Crossbar A Select Register 50 */ /*! @{ */ + #define XBARA_SEL50_SEL100_MASK (0xFFU) #define XBARA_SEL50_SEL100_SHIFT (0U) #define XBARA_SEL50_SEL100(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK) + #define XBARA_SEL50_SEL101_MASK (0xFF00U) #define XBARA_SEL50_SEL101_SHIFT (8U) #define XBARA_SEL50_SEL101(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK) @@ -91235,9 +101790,11 @@ typedef struct { /*! @name SEL51 - Crossbar A Select Register 51 */ /*! @{ */ + #define XBARA_SEL51_SEL102_MASK (0xFFU) #define XBARA_SEL51_SEL102_SHIFT (0U) #define XBARA_SEL51_SEL102(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK) + #define XBARA_SEL51_SEL103_MASK (0xFF00U) #define XBARA_SEL51_SEL103_SHIFT (8U) #define XBARA_SEL51_SEL103(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK) @@ -91245,9 +101802,11 @@ typedef struct { /*! @name SEL52 - Crossbar A Select Register 52 */ /*! @{ */ + #define XBARA_SEL52_SEL104_MASK (0xFFU) #define XBARA_SEL52_SEL104_SHIFT (0U) #define XBARA_SEL52_SEL104(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK) + #define XBARA_SEL52_SEL105_MASK (0xFF00U) #define XBARA_SEL52_SEL105_SHIFT (8U) #define XBARA_SEL52_SEL105(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK) @@ -91255,9 +101814,11 @@ typedef struct { /*! @name SEL53 - Crossbar A Select Register 53 */ /*! @{ */ + #define XBARA_SEL53_SEL106_MASK (0xFFU) #define XBARA_SEL53_SEL106_SHIFT (0U) #define XBARA_SEL53_SEL106(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK) + #define XBARA_SEL53_SEL107_MASK (0xFF00U) #define XBARA_SEL53_SEL107_SHIFT (8U) #define XBARA_SEL53_SEL107(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK) @@ -91265,9 +101826,11 @@ typedef struct { /*! @name SEL54 - Crossbar A Select Register 54 */ /*! @{ */ + #define XBARA_SEL54_SEL108_MASK (0xFFU) #define XBARA_SEL54_SEL108_SHIFT (0U) #define XBARA_SEL54_SEL108(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK) + #define XBARA_SEL54_SEL109_MASK (0xFF00U) #define XBARA_SEL54_SEL109_SHIFT (8U) #define XBARA_SEL54_SEL109(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK) @@ -91275,9 +101838,11 @@ typedef struct { /*! @name SEL55 - Crossbar A Select Register 55 */ /*! @{ */ + #define XBARA_SEL55_SEL110_MASK (0xFFU) #define XBARA_SEL55_SEL110_SHIFT (0U) #define XBARA_SEL55_SEL110(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK) + #define XBARA_SEL55_SEL111_MASK (0xFF00U) #define XBARA_SEL55_SEL111_SHIFT (8U) #define XBARA_SEL55_SEL111(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK) @@ -91285,9 +101850,11 @@ typedef struct { /*! @name SEL56 - Crossbar A Select Register 56 */ /*! @{ */ + #define XBARA_SEL56_SEL112_MASK (0xFFU) #define XBARA_SEL56_SEL112_SHIFT (0U) #define XBARA_SEL56_SEL112(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK) + #define XBARA_SEL56_SEL113_MASK (0xFF00U) #define XBARA_SEL56_SEL113_SHIFT (8U) #define XBARA_SEL56_SEL113(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK) @@ -91295,9 +101862,11 @@ typedef struct { /*! @name SEL57 - Crossbar A Select Register 57 */ /*! @{ */ + #define XBARA_SEL57_SEL114_MASK (0xFFU) #define XBARA_SEL57_SEL114_SHIFT (0U) #define XBARA_SEL57_SEL114(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK) + #define XBARA_SEL57_SEL115_MASK (0xFF00U) #define XBARA_SEL57_SEL115_SHIFT (8U) #define XBARA_SEL57_SEL115(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK) @@ -91305,9 +101874,11 @@ typedef struct { /*! @name SEL58 - Crossbar A Select Register 58 */ /*! @{ */ + #define XBARA_SEL58_SEL116_MASK (0xFFU) #define XBARA_SEL58_SEL116_SHIFT (0U) #define XBARA_SEL58_SEL116(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK) + #define XBARA_SEL58_SEL117_MASK (0xFF00U) #define XBARA_SEL58_SEL117_SHIFT (8U) #define XBARA_SEL58_SEL117(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK) @@ -91315,9 +101886,11 @@ typedef struct { /*! @name SEL59 - Crossbar A Select Register 59 */ /*! @{ */ + #define XBARA_SEL59_SEL118_MASK (0xFFU) #define XBARA_SEL59_SEL118_SHIFT (0U) #define XBARA_SEL59_SEL118(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK) + #define XBARA_SEL59_SEL119_MASK (0xFF00U) #define XBARA_SEL59_SEL119_SHIFT (8U) #define XBARA_SEL59_SEL119(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK) @@ -91325,9 +101898,11 @@ typedef struct { /*! @name SEL60 - Crossbar A Select Register 60 */ /*! @{ */ + #define XBARA_SEL60_SEL120_MASK (0xFFU) #define XBARA_SEL60_SEL120_SHIFT (0U) #define XBARA_SEL60_SEL120(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK) + #define XBARA_SEL60_SEL121_MASK (0xFF00U) #define XBARA_SEL60_SEL121_SHIFT (8U) #define XBARA_SEL60_SEL121(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK) @@ -91335,9 +101910,11 @@ typedef struct { /*! @name SEL61 - Crossbar A Select Register 61 */ /*! @{ */ + #define XBARA_SEL61_SEL122_MASK (0xFFU) #define XBARA_SEL61_SEL122_SHIFT (0U) #define XBARA_SEL61_SEL122(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK) + #define XBARA_SEL61_SEL123_MASK (0xFF00U) #define XBARA_SEL61_SEL123_SHIFT (8U) #define XBARA_SEL61_SEL123(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK) @@ -91345,9 +101922,11 @@ typedef struct { /*! @name SEL62 - Crossbar A Select Register 62 */ /*! @{ */ + #define XBARA_SEL62_SEL124_MASK (0xFFU) #define XBARA_SEL62_SEL124_SHIFT (0U) #define XBARA_SEL62_SEL124(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK) + #define XBARA_SEL62_SEL125_MASK (0xFF00U) #define XBARA_SEL62_SEL125_SHIFT (8U) #define XBARA_SEL62_SEL125(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK) @@ -91355,9 +101934,11 @@ typedef struct { /*! @name SEL63 - Crossbar A Select Register 63 */ /*! @{ */ + #define XBARA_SEL63_SEL126_MASK (0xFFU) #define XBARA_SEL63_SEL126_SHIFT (0U) #define XBARA_SEL63_SEL126(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK) + #define XBARA_SEL63_SEL127_MASK (0xFF00U) #define XBARA_SEL63_SEL127_SHIFT (8U) #define XBARA_SEL63_SEL127(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK) @@ -91365,9 +101946,11 @@ typedef struct { /*! @name SEL64 - Crossbar A Select Register 64 */ /*! @{ */ + #define XBARA_SEL64_SEL128_MASK (0xFFU) #define XBARA_SEL64_SEL128_SHIFT (0U) #define XBARA_SEL64_SEL128(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK) + #define XBARA_SEL64_SEL129_MASK (0xFF00U) #define XBARA_SEL64_SEL129_SHIFT (8U) #define XBARA_SEL64_SEL129(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK) @@ -91375,9 +101958,11 @@ typedef struct { /*! @name SEL65 - Crossbar A Select Register 65 */ /*! @{ */ + #define XBARA_SEL65_SEL130_MASK (0xFFU) #define XBARA_SEL65_SEL130_SHIFT (0U) #define XBARA_SEL65_SEL130(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK) + #define XBARA_SEL65_SEL131_MASK (0xFF00U) #define XBARA_SEL65_SEL131_SHIFT (8U) #define XBARA_SEL65_SEL131(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK) @@ -91385,9 +101970,11 @@ typedef struct { /*! @name SEL66 - Crossbar A Select Register 66 */ /*! @{ */ + #define XBARA_SEL66_SEL132_MASK (0xFFU) #define XBARA_SEL66_SEL132_SHIFT (0U) #define XBARA_SEL66_SEL132(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL66_SEL132_SHIFT)) & XBARA_SEL66_SEL132_MASK) + #define XBARA_SEL66_SEL133_MASK (0xFF00U) #define XBARA_SEL66_SEL133_SHIFT (8U) #define XBARA_SEL66_SEL133(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL66_SEL133_SHIFT)) & XBARA_SEL66_SEL133_MASK) @@ -91395,9 +101982,11 @@ typedef struct { /*! @name SEL67 - Crossbar A Select Register 67 */ /*! @{ */ + #define XBARA_SEL67_SEL134_MASK (0xFFU) #define XBARA_SEL67_SEL134_SHIFT (0U) #define XBARA_SEL67_SEL134(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL67_SEL134_SHIFT)) & XBARA_SEL67_SEL134_MASK) + #define XBARA_SEL67_SEL135_MASK (0xFF00U) #define XBARA_SEL67_SEL135_SHIFT (8U) #define XBARA_SEL67_SEL135(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL67_SEL135_SHIFT)) & XBARA_SEL67_SEL135_MASK) @@ -91405,9 +101994,11 @@ typedef struct { /*! @name SEL68 - Crossbar A Select Register 68 */ /*! @{ */ + #define XBARA_SEL68_SEL136_MASK (0xFFU) #define XBARA_SEL68_SEL136_SHIFT (0U) #define XBARA_SEL68_SEL136(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL68_SEL136_SHIFT)) & XBARA_SEL68_SEL136_MASK) + #define XBARA_SEL68_SEL137_MASK (0xFF00U) #define XBARA_SEL68_SEL137_SHIFT (8U) #define XBARA_SEL68_SEL137(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL68_SEL137_SHIFT)) & XBARA_SEL68_SEL137_MASK) @@ -91415,9 +102006,11 @@ typedef struct { /*! @name SEL69 - Crossbar A Select Register 69 */ /*! @{ */ + #define XBARA_SEL69_SEL138_MASK (0xFFU) #define XBARA_SEL69_SEL138_SHIFT (0U) #define XBARA_SEL69_SEL138(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL69_SEL138_SHIFT)) & XBARA_SEL69_SEL138_MASK) + #define XBARA_SEL69_SEL139_MASK (0xFF00U) #define XBARA_SEL69_SEL139_SHIFT (8U) #define XBARA_SEL69_SEL139(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL69_SEL139_SHIFT)) & XBARA_SEL69_SEL139_MASK) @@ -91425,9 +102018,11 @@ typedef struct { /*! @name SEL70 - Crossbar A Select Register 70 */ /*! @{ */ + #define XBARA_SEL70_SEL140_MASK (0xFFU) #define XBARA_SEL70_SEL140_SHIFT (0U) #define XBARA_SEL70_SEL140(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL70_SEL140_SHIFT)) & XBARA_SEL70_SEL140_MASK) + #define XBARA_SEL70_SEL141_MASK (0xFF00U) #define XBARA_SEL70_SEL141_SHIFT (8U) #define XBARA_SEL70_SEL141(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL70_SEL141_SHIFT)) & XBARA_SEL70_SEL141_MASK) @@ -91435,9 +102030,11 @@ typedef struct { /*! @name SEL71 - Crossbar A Select Register 71 */ /*! @{ */ + #define XBARA_SEL71_SEL142_MASK (0xFFU) #define XBARA_SEL71_SEL142_SHIFT (0U) #define XBARA_SEL71_SEL142(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL71_SEL142_SHIFT)) & XBARA_SEL71_SEL142_MASK) + #define XBARA_SEL71_SEL143_MASK (0xFF00U) #define XBARA_SEL71_SEL143_SHIFT (8U) #define XBARA_SEL71_SEL143(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL71_SEL143_SHIFT)) & XBARA_SEL71_SEL143_MASK) @@ -91445,9 +102042,11 @@ typedef struct { /*! @name SEL72 - Crossbar A Select Register 72 */ /*! @{ */ + #define XBARA_SEL72_SEL144_MASK (0xFFU) #define XBARA_SEL72_SEL144_SHIFT (0U) #define XBARA_SEL72_SEL144(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL72_SEL144_SHIFT)) & XBARA_SEL72_SEL144_MASK) + #define XBARA_SEL72_SEL145_MASK (0xFF00U) #define XBARA_SEL72_SEL145_SHIFT (8U) #define XBARA_SEL72_SEL145(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL72_SEL145_SHIFT)) & XBARA_SEL72_SEL145_MASK) @@ -91455,9 +102054,11 @@ typedef struct { /*! @name SEL73 - Crossbar A Select Register 73 */ /*! @{ */ + #define XBARA_SEL73_SEL146_MASK (0xFFU) #define XBARA_SEL73_SEL146_SHIFT (0U) #define XBARA_SEL73_SEL146(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL73_SEL146_SHIFT)) & XBARA_SEL73_SEL146_MASK) + #define XBARA_SEL73_SEL147_MASK (0xFF00U) #define XBARA_SEL73_SEL147_SHIFT (8U) #define XBARA_SEL73_SEL147(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL73_SEL147_SHIFT)) & XBARA_SEL73_SEL147_MASK) @@ -91465,9 +102066,11 @@ typedef struct { /*! @name SEL74 - Crossbar A Select Register 74 */ /*! @{ */ + #define XBARA_SEL74_SEL148_MASK (0xFFU) #define XBARA_SEL74_SEL148_SHIFT (0U) #define XBARA_SEL74_SEL148(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL74_SEL148_SHIFT)) & XBARA_SEL74_SEL148_MASK) + #define XBARA_SEL74_SEL149_MASK (0xFF00U) #define XBARA_SEL74_SEL149_SHIFT (8U) #define XBARA_SEL74_SEL149(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL74_SEL149_SHIFT)) & XBARA_SEL74_SEL149_MASK) @@ -91475,9 +102078,11 @@ typedef struct { /*! @name SEL75 - Crossbar A Select Register 75 */ /*! @{ */ + #define XBARA_SEL75_SEL150_MASK (0xFFU) #define XBARA_SEL75_SEL150_SHIFT (0U) #define XBARA_SEL75_SEL150(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL75_SEL150_SHIFT)) & XBARA_SEL75_SEL150_MASK) + #define XBARA_SEL75_SEL151_MASK (0xFF00U) #define XBARA_SEL75_SEL151_SHIFT (8U) #define XBARA_SEL75_SEL151(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL75_SEL151_SHIFT)) & XBARA_SEL75_SEL151_MASK) @@ -91485,9 +102090,11 @@ typedef struct { /*! @name SEL76 - Crossbar A Select Register 76 */ /*! @{ */ + #define XBARA_SEL76_SEL152_MASK (0xFFU) #define XBARA_SEL76_SEL152_SHIFT (0U) #define XBARA_SEL76_SEL152(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL76_SEL152_SHIFT)) & XBARA_SEL76_SEL152_MASK) + #define XBARA_SEL76_SEL153_MASK (0xFF00U) #define XBARA_SEL76_SEL153_SHIFT (8U) #define XBARA_SEL76_SEL153(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL76_SEL153_SHIFT)) & XBARA_SEL76_SEL153_MASK) @@ -91495,9 +102102,11 @@ typedef struct { /*! @name SEL77 - Crossbar A Select Register 77 */ /*! @{ */ + #define XBARA_SEL77_SEL154_MASK (0xFFU) #define XBARA_SEL77_SEL154_SHIFT (0U) #define XBARA_SEL77_SEL154(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL77_SEL154_SHIFT)) & XBARA_SEL77_SEL154_MASK) + #define XBARA_SEL77_SEL155_MASK (0xFF00U) #define XBARA_SEL77_SEL155_SHIFT (8U) #define XBARA_SEL77_SEL155(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL77_SEL155_SHIFT)) & XBARA_SEL77_SEL155_MASK) @@ -91505,9 +102114,11 @@ typedef struct { /*! @name SEL78 - Crossbar A Select Register 78 */ /*! @{ */ + #define XBARA_SEL78_SEL156_MASK (0xFFU) #define XBARA_SEL78_SEL156_SHIFT (0U) #define XBARA_SEL78_SEL156(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL78_SEL156_SHIFT)) & XBARA_SEL78_SEL156_MASK) + #define XBARA_SEL78_SEL157_MASK (0xFF00U) #define XBARA_SEL78_SEL157_SHIFT (8U) #define XBARA_SEL78_SEL157(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL78_SEL157_SHIFT)) & XBARA_SEL78_SEL157_MASK) @@ -91515,9 +102126,11 @@ typedef struct { /*! @name SEL79 - Crossbar A Select Register 79 */ /*! @{ */ + #define XBARA_SEL79_SEL158_MASK (0xFFU) #define XBARA_SEL79_SEL158_SHIFT (0U) #define XBARA_SEL79_SEL158(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL79_SEL158_SHIFT)) & XBARA_SEL79_SEL158_MASK) + #define XBARA_SEL79_SEL159_MASK (0xFF00U) #define XBARA_SEL79_SEL159_SHIFT (8U) #define XBARA_SEL79_SEL159(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL79_SEL159_SHIFT)) & XBARA_SEL79_SEL159_MASK) @@ -91525,9 +102138,11 @@ typedef struct { /*! @name SEL80 - Crossbar A Select Register 80 */ /*! @{ */ + #define XBARA_SEL80_SEL160_MASK (0xFFU) #define XBARA_SEL80_SEL160_SHIFT (0U) #define XBARA_SEL80_SEL160(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL80_SEL160_SHIFT)) & XBARA_SEL80_SEL160_MASK) + #define XBARA_SEL80_SEL161_MASK (0xFF00U) #define XBARA_SEL80_SEL161_SHIFT (8U) #define XBARA_SEL80_SEL161(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL80_SEL161_SHIFT)) & XBARA_SEL80_SEL161_MASK) @@ -91535,9 +102150,11 @@ typedef struct { /*! @name SEL81 - Crossbar A Select Register 81 */ /*! @{ */ + #define XBARA_SEL81_SEL162_MASK (0xFFU) #define XBARA_SEL81_SEL162_SHIFT (0U) #define XBARA_SEL81_SEL162(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL81_SEL162_SHIFT)) & XBARA_SEL81_SEL162_MASK) + #define XBARA_SEL81_SEL163_MASK (0xFF00U) #define XBARA_SEL81_SEL163_SHIFT (8U) #define XBARA_SEL81_SEL163(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL81_SEL163_SHIFT)) & XBARA_SEL81_SEL163_MASK) @@ -91545,9 +102162,11 @@ typedef struct { /*! @name SEL82 - Crossbar A Select Register 82 */ /*! @{ */ + #define XBARA_SEL82_SEL164_MASK (0xFFU) #define XBARA_SEL82_SEL164_SHIFT (0U) #define XBARA_SEL82_SEL164(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL82_SEL164_SHIFT)) & XBARA_SEL82_SEL164_MASK) + #define XBARA_SEL82_SEL165_MASK (0xFF00U) #define XBARA_SEL82_SEL165_SHIFT (8U) #define XBARA_SEL82_SEL165(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL82_SEL165_SHIFT)) & XBARA_SEL82_SEL165_MASK) @@ -91555,9 +102174,11 @@ typedef struct { /*! @name SEL83 - Crossbar A Select Register 83 */ /*! @{ */ + #define XBARA_SEL83_SEL166_MASK (0xFFU) #define XBARA_SEL83_SEL166_SHIFT (0U) #define XBARA_SEL83_SEL166(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL83_SEL166_SHIFT)) & XBARA_SEL83_SEL166_MASK) + #define XBARA_SEL83_SEL167_MASK (0xFF00U) #define XBARA_SEL83_SEL167_SHIFT (8U) #define XBARA_SEL83_SEL167(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL83_SEL167_SHIFT)) & XBARA_SEL83_SEL167_MASK) @@ -91565,9 +102186,11 @@ typedef struct { /*! @name SEL84 - Crossbar A Select Register 84 */ /*! @{ */ + #define XBARA_SEL84_SEL168_MASK (0xFFU) #define XBARA_SEL84_SEL168_SHIFT (0U) #define XBARA_SEL84_SEL168(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL84_SEL168_SHIFT)) & XBARA_SEL84_SEL168_MASK) + #define XBARA_SEL84_SEL169_MASK (0xFF00U) #define XBARA_SEL84_SEL169_SHIFT (8U) #define XBARA_SEL84_SEL169(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL84_SEL169_SHIFT)) & XBARA_SEL84_SEL169_MASK) @@ -91575,9 +102198,11 @@ typedef struct { /*! @name SEL85 - Crossbar A Select Register 85 */ /*! @{ */ + #define XBARA_SEL85_SEL170_MASK (0xFFU) #define XBARA_SEL85_SEL170_SHIFT (0U) #define XBARA_SEL85_SEL170(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL85_SEL170_SHIFT)) & XBARA_SEL85_SEL170_MASK) + #define XBARA_SEL85_SEL171_MASK (0xFF00U) #define XBARA_SEL85_SEL171_SHIFT (8U) #define XBARA_SEL85_SEL171(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL85_SEL171_SHIFT)) & XBARA_SEL85_SEL171_MASK) @@ -91585,9 +102210,11 @@ typedef struct { /*! @name SEL86 - Crossbar A Select Register 86 */ /*! @{ */ + #define XBARA_SEL86_SEL172_MASK (0xFFU) #define XBARA_SEL86_SEL172_SHIFT (0U) #define XBARA_SEL86_SEL172(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL86_SEL172_SHIFT)) & XBARA_SEL86_SEL172_MASK) + #define XBARA_SEL86_SEL173_MASK (0xFF00U) #define XBARA_SEL86_SEL173_SHIFT (8U) #define XBARA_SEL86_SEL173(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL86_SEL173_SHIFT)) & XBARA_SEL86_SEL173_MASK) @@ -91595,9 +102222,11 @@ typedef struct { /*! @name SEL87 - Crossbar A Select Register 87 */ /*! @{ */ + #define XBARA_SEL87_SEL174_MASK (0xFFU) #define XBARA_SEL87_SEL174_SHIFT (0U) #define XBARA_SEL87_SEL174(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL87_SEL174_SHIFT)) & XBARA_SEL87_SEL174_MASK) + #define XBARA_SEL87_SEL175_MASK (0xFF00U) #define XBARA_SEL87_SEL175_SHIFT (8U) #define XBARA_SEL87_SEL175(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL87_SEL175_SHIFT)) & XBARA_SEL87_SEL175_MASK) @@ -91605,6 +102234,7 @@ typedef struct { /*! @name CTRL0 - Crossbar A Control Register 0 */ /*! @{ */ + #define XBARA_CTRL0_DEN0_MASK (0x1U) #define XBARA_CTRL0_DEN0_SHIFT (0U) /*! DEN0 - DMA Enable for XBAR_OUT0 @@ -91612,6 +102242,7 @@ typedef struct { * 0b1..DMA enabled */ #define XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK) + #define XBARA_CTRL0_IEN0_MASK (0x2U) #define XBARA_CTRL0_IEN0_SHIFT (1U) /*! IEN0 - Interrupt Enable for XBAR_OUT0 @@ -91619,6 +102250,7 @@ typedef struct { * 0b1..Interrupt enabled */ #define XBARA_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK) + #define XBARA_CTRL0_EDGE0_MASK (0xCU) #define XBARA_CTRL0_EDGE0_SHIFT (2U) /*! EDGE0 - Active edge for edge detection on XBAR_OUT0 @@ -91628,6 +102260,7 @@ typedef struct { * 0b11..STS0 asserts on rising and falling edges of XBAR_OUT0 */ #define XBARA_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK) + #define XBARA_CTRL0_STS0_MASK (0x10U) #define XBARA_CTRL0_STS0_SHIFT (4U) /*! STS0 - Edge detection status for XBAR_OUT0 @@ -91635,6 +102268,7 @@ typedef struct { * 0b1..Active edge detected on XBAR_OUT0 */ #define XBARA_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK) + #define XBARA_CTRL0_DEN1_MASK (0x100U) #define XBARA_CTRL0_DEN1_SHIFT (8U) /*! DEN1 - DMA Enable for XBAR_OUT1 @@ -91642,6 +102276,7 @@ typedef struct { * 0b1..DMA enabled */ #define XBARA_CTRL0_DEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK) + #define XBARA_CTRL0_IEN1_MASK (0x200U) #define XBARA_CTRL0_IEN1_SHIFT (9U) /*! IEN1 - Interrupt Enable for XBAR_OUT1 @@ -91649,6 +102284,7 @@ typedef struct { * 0b1..Interrupt enabled */ #define XBARA_CTRL0_IEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK) + #define XBARA_CTRL0_EDGE1_MASK (0xC00U) #define XBARA_CTRL0_EDGE1_SHIFT (10U) /*! EDGE1 - Active edge for edge detection on XBAR_OUT1 @@ -91658,6 +102294,7 @@ typedef struct { * 0b11..STS1 asserts on rising and falling edges of XBAR_OUT1 */ #define XBARA_CTRL0_EDGE1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK) + #define XBARA_CTRL0_STS1_MASK (0x1000U) #define XBARA_CTRL0_STS1_SHIFT (12U) /*! STS1 - Edge detection status for XBAR_OUT1 @@ -91669,6 +102306,7 @@ typedef struct { /*! @name CTRL1 - Crossbar A Control Register 1 */ /*! @{ */ + #define XBARA_CTRL1_DEN2_MASK (0x1U) #define XBARA_CTRL1_DEN2_SHIFT (0U) /*! DEN2 - DMA Enable for XBAR_OUT2 @@ -91676,6 +102314,7 @@ typedef struct { * 0b1..DMA enabled */ #define XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK) + #define XBARA_CTRL1_IEN2_MASK (0x2U) #define XBARA_CTRL1_IEN2_SHIFT (1U) /*! IEN2 - Interrupt Enable for XBAR_OUT2 @@ -91683,6 +102322,7 @@ typedef struct { * 0b1..Interrupt enabled */ #define XBARA_CTRL1_IEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK) + #define XBARA_CTRL1_EDGE2_MASK (0xCU) #define XBARA_CTRL1_EDGE2_SHIFT (2U) /*! EDGE2 - Active edge for edge detection on XBAR_OUT2 @@ -91692,6 +102332,7 @@ typedef struct { * 0b11..STS2 asserts on rising and falling edges of XBAR_OUT2 */ #define XBARA_CTRL1_EDGE2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK) + #define XBARA_CTRL1_STS2_MASK (0x10U) #define XBARA_CTRL1_STS2_SHIFT (4U) /*! STS2 - Edge detection status for XBAR_OUT2 @@ -91699,6 +102340,7 @@ typedef struct { * 0b1..Active edge detected on XBAR_OUT2 */ #define XBARA_CTRL1_STS2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK) + #define XBARA_CTRL1_DEN3_MASK (0x100U) #define XBARA_CTRL1_DEN3_SHIFT (8U) /*! DEN3 - DMA Enable for XBAR_OUT3 @@ -91706,6 +102348,7 @@ typedef struct { * 0b1..DMA enabled */ #define XBARA_CTRL1_DEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK) + #define XBARA_CTRL1_IEN3_MASK (0x200U) #define XBARA_CTRL1_IEN3_SHIFT (9U) /*! IEN3 - Interrupt Enable for XBAR_OUT3 @@ -91713,6 +102356,7 @@ typedef struct { * 0b1..Interrupt enabled */ #define XBARA_CTRL1_IEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK) + #define XBARA_CTRL1_EDGE3_MASK (0xC00U) #define XBARA_CTRL1_EDGE3_SHIFT (10U) /*! EDGE3 - Active edge for edge detection on XBAR_OUT3 @@ -91722,6 +102366,7 @@ typedef struct { * 0b11..STS3 asserts on rising and falling edges of XBAR_OUT3 */ #define XBARA_CTRL1_EDGE3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK) + #define XBARA_CTRL1_STS3_MASK (0x1000U) #define XBARA_CTRL1_STS3_SHIFT (12U) /*! STS3 - Edge detection status for XBAR_OUT3 @@ -91784,9 +102429,11 @@ typedef struct { /*! @name SEL0 - Crossbar B Select Register 0 */ /*! @{ */ + #define XBARB_SEL0_SEL0_MASK (0x7FU) #define XBARB_SEL0_SEL0_SHIFT (0U) #define XBARB_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK) + #define XBARB_SEL0_SEL1_MASK (0x7F00U) #define XBARB_SEL0_SEL1_SHIFT (8U) #define XBARB_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK) @@ -91794,9 +102441,11 @@ typedef struct { /*! @name SEL1 - Crossbar B Select Register 1 */ /*! @{ */ + #define XBARB_SEL1_SEL2_MASK (0x7FU) #define XBARB_SEL1_SEL2_SHIFT (0U) #define XBARB_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK) + #define XBARB_SEL1_SEL3_MASK (0x7F00U) #define XBARB_SEL1_SEL3_SHIFT (8U) #define XBARB_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK) @@ -91804,9 +102453,11 @@ typedef struct { /*! @name SEL2 - Crossbar B Select Register 2 */ /*! @{ */ + #define XBARB_SEL2_SEL4_MASK (0x7FU) #define XBARB_SEL2_SEL4_SHIFT (0U) #define XBARB_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK) + #define XBARB_SEL2_SEL5_MASK (0x7F00U) #define XBARB_SEL2_SEL5_SHIFT (8U) #define XBARB_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK) @@ -91814,9 +102465,11 @@ typedef struct { /*! @name SEL3 - Crossbar B Select Register 3 */ /*! @{ */ + #define XBARB_SEL3_SEL6_MASK (0x7FU) #define XBARB_SEL3_SEL6_SHIFT (0U) #define XBARB_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK) + #define XBARB_SEL3_SEL7_MASK (0x7F00U) #define XBARB_SEL3_SEL7_SHIFT (8U) #define XBARB_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK) @@ -91824,9 +102477,11 @@ typedef struct { /*! @name SEL4 - Crossbar B Select Register 4 */ /*! @{ */ + #define XBARB_SEL4_SEL8_MASK (0x7FU) #define XBARB_SEL4_SEL8_SHIFT (0U) #define XBARB_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK) + #define XBARB_SEL4_SEL9_MASK (0x7F00U) #define XBARB_SEL4_SEL9_SHIFT (8U) #define XBARB_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK) @@ -91834,9 +102489,11 @@ typedef struct { /*! @name SEL5 - Crossbar B Select Register 5 */ /*! @{ */ + #define XBARB_SEL5_SEL10_MASK (0x7FU) #define XBARB_SEL5_SEL10_SHIFT (0U) #define XBARB_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK) + #define XBARB_SEL5_SEL11_MASK (0x7F00U) #define XBARB_SEL5_SEL11_SHIFT (8U) #define XBARB_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK) @@ -91844,9 +102501,11 @@ typedef struct { /*! @name SEL6 - Crossbar B Select Register 6 */ /*! @{ */ + #define XBARB_SEL6_SEL12_MASK (0x7FU) #define XBARB_SEL6_SEL12_SHIFT (0U) #define XBARB_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK) + #define XBARB_SEL6_SEL13_MASK (0x7F00U) #define XBARB_SEL6_SEL13_SHIFT (8U) #define XBARB_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK) @@ -91854,9 +102513,11 @@ typedef struct { /*! @name SEL7 - Crossbar B Select Register 7 */ /*! @{ */ + #define XBARB_SEL7_SEL14_MASK (0x7FU) #define XBARB_SEL7_SEL14_SHIFT (0U) #define XBARB_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK) + #define XBARB_SEL7_SEL15_MASK (0x7F00U) #define XBARB_SEL7_SEL15_SHIFT (8U) #define XBARB_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK) @@ -91934,43 +102595,43 @@ typedef struct { /*! @name ECC_CTRL - ECC Control Register */ /*! @{ */ + #define XECC_ECC_CTRL_ECC_EN_MASK (0x1U) #define XECC_ECC_CTRL_ECC_EN_SHIFT (0U) /*! ECC_EN - ECC Function Enable - * 0b0..Disable. - * 0b1..Enable. + * 0b0..Disable + * 0b1..Enable */ #define XECC_ECC_CTRL_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_CTRL_ECC_EN_SHIFT)) & XECC_ECC_CTRL_ECC_EN_MASK) + #define XECC_ECC_CTRL_WECC_EN_MASK (0x2U) #define XECC_ECC_CTRL_WECC_EN_SHIFT (1U) /*! WECC_EN - Write ECC Encode Function Enable - * 0b0..Disable. - * 0b1..Enable. + * 0b0..Disable + * 0b1..Enable */ #define XECC_ECC_CTRL_WECC_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_CTRL_WECC_EN_SHIFT)) & XECC_ECC_CTRL_WECC_EN_MASK) + #define XECC_ECC_CTRL_RECC_EN_MASK (0x4U) #define XECC_ECC_CTRL_RECC_EN_SHIFT (2U) /*! RECC_EN - Read ECC Function Enable - * 0b0..Disable. - * 0b1..Enable. + * 0b0..Disable + * 0b1..Enable */ #define XECC_ECC_CTRL_RECC_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_CTRL_RECC_EN_SHIFT)) & XECC_ECC_CTRL_RECC_EN_MASK) + #define XECC_ECC_CTRL_SWAP_EN_MASK (0x8U) #define XECC_ECC_CTRL_SWAP_EN_SHIFT (3U) /*! SWAP_EN - Swap Data Enable - * 0b0..Disable. - * 0b1..Enable. + * 0b0..Disable + * 0b1..Enable */ #define XECC_ECC_CTRL_SWAP_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_CTRL_SWAP_EN_SHIFT)) & XECC_ECC_CTRL_SWAP_EN_MASK) -#define XECC_ECC_CTRL_Reserved1_MASK (0xFFFFFFF0U) -#define XECC_ECC_CTRL_Reserved1_SHIFT (4U) -/*! Reserved1 - Reserved - */ -#define XECC_ECC_CTRL_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_CTRL_Reserved1_SHIFT)) & XECC_ECC_CTRL_Reserved1_MASK) /*! @} */ /*! @name ERR_STATUS - Error Interrupt Status Register */ /*! @{ */ + #define XECC_ERR_STATUS_SINGLE_ERR_MASK (0x1U) #define XECC_ERR_STATUS_SINGLE_ERR_SHIFT (0U) /*! SINGLE_ERR - Single Bit Error @@ -91978,6 +102639,7 @@ typedef struct { * 0b1..Single bit error happens. */ #define XECC_ERR_STATUS_SINGLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_SINGLE_ERR_SHIFT)) & XECC_ERR_STATUS_SINGLE_ERR_MASK) + #define XECC_ERR_STATUS_MULTI_ERR_MASK (0x2U) #define XECC_ERR_STATUS_MULTI_ERR_SHIFT (1U) /*! MULTI_ERR - Multiple Bits Error @@ -91985,6 +102647,7 @@ typedef struct { * 0b1..Multiple bits error happens. */ #define XECC_ERR_STATUS_MULTI_ERR(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_MULTI_ERR_SHIFT)) & XECC_ERR_STATUS_MULTI_ERR_MASK) + #define XECC_ERR_STATUS_Reserved1_MASK (0xFFFFFFFCU) #define XECC_ERR_STATUS_Reserved1_SHIFT (2U) /*! Reserved1 - Reserved @@ -91994,6 +102657,7 @@ typedef struct { /*! @name ERR_STAT_EN - Error Interrupt Status Enable Register */ /*! @{ */ + #define XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_MASK (0x1U) #define XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_SHIFT (0U) /*! SINGLE_ERR_STAT_EN - Single Bit Error Status Enable @@ -92001,6 +102665,7 @@ typedef struct { * 0b1..Enabled */ #define XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_SHIFT)) & XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_MASK) + #define XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_MASK (0x2U) #define XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_SHIFT (1U) /*! MULIT_ERR_STAT_EN - Multiple Bits Error Status Enable @@ -92008,6 +102673,7 @@ typedef struct { * 0b1..Enabled */ #define XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_SHIFT)) & XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_MASK) + #define XECC_ERR_STAT_EN_Reserved1_MASK (0xFFFFFFFCU) #define XECC_ERR_STAT_EN_Reserved1_SHIFT (2U) /*! Reserved1 - Reserved @@ -92017,6 +102683,7 @@ typedef struct { /*! @name ERR_SIG_EN - Error Interrupt Enable Register */ /*! @{ */ + #define XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_MASK (0x1U) #define XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_SHIFT (0U) /*! SINGLE_ERR_SIG_EN - Single Bit Error Interrupt Enable @@ -92024,6 +102691,7 @@ typedef struct { * 0b1..Enabled */ #define XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_SHIFT)) & XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_MASK) + #define XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_MASK (0x2U) #define XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_SHIFT (1U) /*! MULTI_ERR_SIG_EN - Multiple Bits Error Interrupt Enable @@ -92031,6 +102699,7 @@ typedef struct { * 0b1..Enabled */ #define XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_SHIFT)) & XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_MASK) + #define XECC_ERR_SIG_EN_Reserved1_MASK (0xFFFFFFFCU) #define XECC_ERR_SIG_EN_Reserved1_SHIFT (2U) /*! Reserved1 - Reserved @@ -92040,6 +102709,7 @@ typedef struct { /*! @name ERR_DATA_INJ - Error Injection On Write Data */ /*! @{ */ + #define XECC_ERR_DATA_INJ_ERR_DATA_INJ_MASK (0xFFFFFFFFU) #define XECC_ERR_DATA_INJ_ERR_DATA_INJ_SHIFT (0U) /*! ERR_DATA_INJ - Error Injection On Write Data @@ -92049,6 +102719,7 @@ typedef struct { /*! @name ERR_ECC_INJ - Error Injection On ECC Code of Write Data */ /*! @{ */ + #define XECC_ERR_ECC_INJ_ERR_ECC_INJ_MASK (0xFFFFFFFFU) #define XECC_ERR_ECC_INJ_ERR_ECC_INJ_SHIFT (0U) /*! ERR_ECC_INJ - Error Injection On ECC Code of Write Data @@ -92058,6 +102729,7 @@ typedef struct { /*! @name SINGLE_ERR_ADDR - Single Error Address */ /*! @{ */ + #define XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR_MASK (0xFFFFFFFFU) #define XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR_SHIFT (0U) /*! SINGLE_ERR_ADDR - Single Error Address @@ -92067,6 +102739,7 @@ typedef struct { /*! @name SINGLE_ERR_DATA - Single Error Read Data */ /*! @{ */ + #define XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU) #define XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA_SHIFT (0U) /*! SINGLE_ERR_DATA - Single Error Read Data @@ -92076,6 +102749,7 @@ typedef struct { /*! @name SINGLE_ERR_ECC - Single Error ECC Code */ /*! @{ */ + #define XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC_MASK (0xFFFFFFFFU) #define XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC_SHIFT (0U) /*! SINGLE_ERR_ECC - Single Error ECC code @@ -92085,6 +102759,7 @@ typedef struct { /*! @name SINGLE_ERR_POS - Single Error Bit Position */ /*! @{ */ + #define XECC_SINGLE_ERR_POS_SINGLE_ERR_POS_MASK (0xFFFFFFFFU) #define XECC_SINGLE_ERR_POS_SINGLE_ERR_POS_SHIFT (0U) /*! SINGLE_ERR_POS - Single Error bit Position @@ -92094,11 +102769,13 @@ typedef struct { /*! @name SINGLE_ERR_BIT_FIELD - Single Error Bit Field */ /*! @{ */ + #define XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD_MASK (0xFFU) #define XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD_SHIFT (0U) /*! SINGLE_ERR_BIT_FIELD - Single Error Bit Field */ #define XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD(x) (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD_SHIFT)) & XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD_MASK) + #define XECC_SINGLE_ERR_BIT_FIELD_Reserved1_MASK (0xFFFFFF00U) #define XECC_SINGLE_ERR_BIT_FIELD_Reserved1_SHIFT (8U) /*! Reserved1 - Reserved @@ -92108,6 +102785,7 @@ typedef struct { /*! @name MULTI_ERR_ADDR - Multiple Error Address */ /*! @{ */ + #define XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR_MASK (0xFFFFFFFFU) #define XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR_SHIFT (0U) /*! MULTI_ERR_ADDR - Multiple Error Address @@ -92117,6 +102795,7 @@ typedef struct { /*! @name MULTI_ERR_DATA - Multiple Error Read Data */ /*! @{ */ + #define XECC_MULTI_ERR_DATA_MULTI_ERR_DATA_MASK (0xFFFFFFFFU) #define XECC_MULTI_ERR_DATA_MULTI_ERR_DATA_SHIFT (0U) /*! MULTI_ERR_DATA - Multiple Error Read Data @@ -92126,6 +102805,7 @@ typedef struct { /*! @name MULTI_ERR_ECC - Multiple Error ECC code */ /*! @{ */ + #define XECC_MULTI_ERR_ECC_MULTI_ERR_ECC_MASK (0xFFFFFFFFU) #define XECC_MULTI_ERR_ECC_MULTI_ERR_ECC_SHIFT (0U) /*! MULTI_ERR_ECC - Multiple Error ECC code @@ -92135,11 +102815,13 @@ typedef struct { /*! @name MULTI_ERR_BIT_FIELD - Multiple Error Bit Field */ /*! @{ */ + #define XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD_MASK (0xFFU) #define XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD_SHIFT (0U) /*! MULTI_ERR_BIT_FIELD - Multiple Error Bit Field */ #define XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD(x) (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD_SHIFT)) & XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD_MASK) + #define XECC_MULTI_ERR_BIT_FIELD_Reserved1_MASK (0xFFFFFF00U) #define XECC_MULTI_ERR_BIT_FIELD_Reserved1_SHIFT (8U) /*! Reserved1 - Reserved @@ -92149,6 +102831,7 @@ typedef struct { /*! @name ECC_BASE_ADDR0 - ECC Region 0 Base Address */ /*! @{ */ + #define XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0_MASK (0xFFFFFFFFU) #define XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0_SHIFT (0U) /*! ECC_BASE_ADDR0 - ECC Region 0 Base Address @@ -92158,6 +102841,7 @@ typedef struct { /*! @name ECC_END_ADDR0 - ECC Region 0 End Address */ /*! @{ */ + #define XECC_ECC_END_ADDR0_ECC_END_ADDR0_MASK (0xFFFFFFFFU) #define XECC_ECC_END_ADDR0_ECC_END_ADDR0_SHIFT (0U) /*! ECC_END_ADDR0 - ECC Region 0 End Address @@ -92167,6 +102851,7 @@ typedef struct { /*! @name ECC_BASE_ADDR1 - ECC Region 1 Base Address */ /*! @{ */ + #define XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1_MASK (0xFFFFFFFFU) #define XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1_SHIFT (0U) /*! ECC_BASE_ADDR1 - ECC Region 1 Base Address @@ -92176,6 +102861,7 @@ typedef struct { /*! @name ECC_END_ADDR1 - ECC Region 1 End Address */ /*! @{ */ + #define XECC_ECC_END_ADDR1_ECC_END_ADDR1_MASK (0xFFFFFFFFU) #define XECC_ECC_END_ADDR1_ECC_END_ADDR1_SHIFT (0U) /*! ECC_END_ADDR1 - ECC Region 1 End Address @@ -92185,6 +102871,7 @@ typedef struct { /*! @name ECC_BASE_ADDR2 - ECC Region 2 Base Address */ /*! @{ */ + #define XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2_MASK (0xFFFFFFFFU) #define XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2_SHIFT (0U) /*! ECC_BASE_ADDR2 - ECC Region 2 Base Address @@ -92194,6 +102881,7 @@ typedef struct { /*! @name ECC_END_ADDR2 - ECC Region 2 End Address */ /*! @{ */ + #define XECC_ECC_END_ADDR2_ECC_END_ADDR2_MASK (0xFFFFFFFFU) #define XECC_ECC_END_ADDR2_ECC_END_ADDR2_SHIFT (0U) /*! ECC_END_ADDR2 - ECC Region 2 End Address @@ -92203,6 +102891,7 @@ typedef struct { /*! @name ECC_BASE_ADDR3 - ECC Region 3 Base Address */ /*! @{ */ + #define XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3_MASK (0xFFFFFFFFU) #define XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3_SHIFT (0U) /*! ECC_BASE_ADDR3 - ECC Region 3 Base Address @@ -92212,6 +102901,7 @@ typedef struct { /*! @name ECC_END_ADDR3 - ECC Region 3 End Address */ /*! @{ */ + #define XECC_ECC_END_ADDR3_ECC_END_ADDR3_MASK (0xFFFFFFFFU) #define XECC_ECC_END_ADDR3_ECC_END_ADDR3_SHIFT (0U) /*! ECC_END_ADDR3 - ECC Region 3 End Address @@ -92280,10 +102970,10 @@ typedef struct { __IO uint32_t MRC_MRGD_W1; /**< Memory Region Descriptor, array offset: 0x8004, array step: index*0x400, index2*0x20 */ __IO uint32_t MRC_MRGD_W2; /**< Memory Region Descriptor, array offset: 0x8008, array step: index*0x400, index2*0x20 */ __IO uint32_t MRC_MRGD_W3; /**< Memory Region Descriptor, array offset: 0x800C, array step: index*0x400, index2*0x20 */ - __IO uint32_t MRC_MRGD_W4; /**< Memory Region Descriptor, array offset: 0x8010, array step: index*0x400, index2*0x20 */ + uint8_t RESERVED_0[4]; __IO uint32_t MRC_MRGD_W5; /**< Memory Region Descriptor, array offset: 0x8014, array step: index*0x400, index2*0x20 */ __IO uint32_t MRC_MRGD_W6; /**< Memory Region Descriptor, array offset: 0x8018, array step: index*0x400, index2*0x20 */ - uint8_t RESERVED_0[4]; + uint8_t RESERVED_1[4]; } MRCI_MRGDJ[32][32]; } XRDC2_Type; @@ -92298,13 +102988,15 @@ typedef struct { /*! @name MCR - Module Control Register */ /*! @{ */ + #define XRDC2_MCR_GVLDM_MASK (0x1U) #define XRDC2_MCR_GVLDM_SHIFT (0U) /*! GVLDM - Global Valid MDAC - * 0b0..MDACs are disabled. DID and SID set to 0 for all transactions. + * 0b0..MDACs are disabled. * 0b1..MDACs are enabled. */ #define XRDC2_MCR_GVLDM(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDM_SHIFT)) & XRDC2_MCR_GVLDM_MASK) + #define XRDC2_MCR_GVLDC_MASK (0x2U) #define XRDC2_MCR_GVLDC_SHIFT (1U) /*! GVLDC - Global Valid Access Control @@ -92312,6 +103004,7 @@ typedef struct { * 0b1..Access controls are enabled. */ #define XRDC2_MCR_GVLDC(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDC_SHIFT)) & XRDC2_MCR_GVLDC_MASK) + #define XRDC2_MCR_GCL_MASK (0x30U) #define XRDC2_MCR_GCL_SHIFT (4U) /*! GCL - Global Configuration Lock @@ -92325,16 +103018,19 @@ typedef struct { /*! @name SR - Status Register */ /*! @{ */ -#define XRDC2_SR_DID_MASK (0xFU) -#define XRDC2_SR_DID_SHIFT (0U) -/*! DID - Domain identifier number + +#define XRDC2_SR_DIN_MASK (0xFU) +#define XRDC2_SR_DIN_SHIFT (0U) +/*! DIN - Domain Identifier Number */ -#define XRDC2_SR_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_DID_SHIFT)) & XRDC2_SR_DID_MASK) +#define XRDC2_SR_DIN(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_DIN_SHIFT)) & XRDC2_SR_DIN_MASK) + #define XRDC2_SR_HRL_MASK (0xF0U) #define XRDC2_SR_HRL_SHIFT (4U) /*! HRL - Hardware Revision Level */ #define XRDC2_SR_HRL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_HRL_SHIFT)) & XRDC2_SR_HRL_MASK) + #define XRDC2_SR_GCLO_MASK (0xF00U) #define XRDC2_SR_GCLO_SHIFT (8U) /*! GCLO - Global Configuration Lock Owner @@ -92344,46 +103040,55 @@ typedef struct { /*! @name MSC_MSAC_W0 - Memory Slot Access Control */ /*! @{ */ + #define XRDC2_MSC_MSAC_W0_D0ACP_MASK (0x7U) #define XRDC2_MSC_MSAC_W0_D0ACP_SHIFT (0U) /*! D0ACP - Domain "x" access control policy */ #define XRDC2_MSC_MSAC_W0_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D0ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D0ACP_MASK) + #define XRDC2_MSC_MSAC_W0_D1ACP_MASK (0x38U) #define XRDC2_MSC_MSAC_W0_D1ACP_SHIFT (3U) /*! D1ACP - Domain "x" access control policy */ #define XRDC2_MSC_MSAC_W0_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D1ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D1ACP_MASK) + #define XRDC2_MSC_MSAC_W0_D2ACP_MASK (0x1C0U) #define XRDC2_MSC_MSAC_W0_D2ACP_SHIFT (6U) /*! D2ACP - Domain "x" access control policy */ #define XRDC2_MSC_MSAC_W0_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D2ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D2ACP_MASK) + #define XRDC2_MSC_MSAC_W0_D3ACP_MASK (0xE00U) #define XRDC2_MSC_MSAC_W0_D3ACP_SHIFT (9U) /*! D3ACP - Domain "x" access control policy */ #define XRDC2_MSC_MSAC_W0_D3ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D3ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D3ACP_MASK) + #define XRDC2_MSC_MSAC_W0_D4ACP_MASK (0x7000U) #define XRDC2_MSC_MSAC_W0_D4ACP_SHIFT (12U) /*! D4ACP - Domain "x" access control policy */ #define XRDC2_MSC_MSAC_W0_D4ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D4ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D4ACP_MASK) + #define XRDC2_MSC_MSAC_W0_D5ACP_MASK (0x38000U) #define XRDC2_MSC_MSAC_W0_D5ACP_SHIFT (15U) /*! D5ACP - Domain "x" access control policy */ #define XRDC2_MSC_MSAC_W0_D5ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D5ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D5ACP_MASK) + #define XRDC2_MSC_MSAC_W0_D6ACP_MASK (0x1C0000U) #define XRDC2_MSC_MSAC_W0_D6ACP_SHIFT (18U) /*! D6ACP - Domain "x" access control policy */ #define XRDC2_MSC_MSAC_W0_D6ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D6ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D6ACP_MASK) + #define XRDC2_MSC_MSAC_W0_D7ACP_MASK (0xE00000U) #define XRDC2_MSC_MSAC_W0_D7ACP_SHIFT (21U) /*! D7ACP - Domain "x" access control policy */ #define XRDC2_MSC_MSAC_W0_D7ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D7ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D7ACP_MASK) + #define XRDC2_MSC_MSAC_W0_EALO_MASK (0xF000000U) #define XRDC2_MSC_MSAC_W0_EALO_SHIFT (24U) /*! EALO - Exclusive Access Lock Owner @@ -92396,46 +103101,55 @@ typedef struct { /*! @name MSC_MSAC_W1 - Memory Slot Access Control */ /*! @{ */ + #define XRDC2_MSC_MSAC_W1_D8ACP_MASK (0x7U) #define XRDC2_MSC_MSAC_W1_D8ACP_SHIFT (0U) /*! D8ACP - Domain "x" access control policy */ #define XRDC2_MSC_MSAC_W1_D8ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D8ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D8ACP_MASK) + #define XRDC2_MSC_MSAC_W1_D9ACP_MASK (0x38U) #define XRDC2_MSC_MSAC_W1_D9ACP_SHIFT (3U) /*! D9ACP - Domain "x" access control policy */ #define XRDC2_MSC_MSAC_W1_D9ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D9ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D9ACP_MASK) + #define XRDC2_MSC_MSAC_W1_D10ACP_MASK (0x1C0U) #define XRDC2_MSC_MSAC_W1_D10ACP_SHIFT (6U) /*! D10ACP - Domain "x" access control policy */ #define XRDC2_MSC_MSAC_W1_D10ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D10ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D10ACP_MASK) + #define XRDC2_MSC_MSAC_W1_D11ACP_MASK (0xE00U) #define XRDC2_MSC_MSAC_W1_D11ACP_SHIFT (9U) /*! D11ACP - Domain "x" access control policy */ #define XRDC2_MSC_MSAC_W1_D11ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D11ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D11ACP_MASK) + #define XRDC2_MSC_MSAC_W1_D12ACP_MASK (0x7000U) #define XRDC2_MSC_MSAC_W1_D12ACP_SHIFT (12U) /*! D12ACP - Domain "x" access control policy */ #define XRDC2_MSC_MSAC_W1_D12ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D12ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D12ACP_MASK) + #define XRDC2_MSC_MSAC_W1_D13ACP_MASK (0x38000U) #define XRDC2_MSC_MSAC_W1_D13ACP_SHIFT (15U) /*! D13ACP - Domain "x" access control policy */ #define XRDC2_MSC_MSAC_W1_D13ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D13ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D13ACP_MASK) + #define XRDC2_MSC_MSAC_W1_D14ACP_MASK (0x1C0000U) #define XRDC2_MSC_MSAC_W1_D14ACP_SHIFT (18U) /*! D14ACP - Domain "x" access control policy */ #define XRDC2_MSC_MSAC_W1_D14ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D14ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D14ACP_MASK) + #define XRDC2_MSC_MSAC_W1_D15ACP_MASK (0xE00000U) #define XRDC2_MSC_MSAC_W1_D15ACP_SHIFT (21U) /*! D15ACP - Domain "x" access control policy */ #define XRDC2_MSC_MSAC_W1_D15ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D15ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D15ACP_MASK) + #define XRDC2_MSC_MSAC_W1_EAL_MASK (0x3000000U) #define XRDC2_MSC_MSAC_W1_EAL_SHIFT (24U) /*! EAL - Exclusive Access Lock @@ -92445,6 +103159,7 @@ typedef struct { * 0b11..Lock enabled, lock state = not available. */ #define XRDC2_MSC_MSAC_W1_EAL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_EAL_SHIFT)) & XRDC2_MSC_MSAC_W1_EAL_MASK) + #define XRDC2_MSC_MSAC_W1_DL2_MASK (0x60000000U) #define XRDC2_MSC_MSAC_W1_DL2_SHIFT (29U) /*! DL2 - Descriptor Lock @@ -92454,6 +103169,7 @@ typedef struct { * 0b11..Lock enabled, descriptor registers are read-only until the next reset. */ #define XRDC2_MSC_MSAC_W1_DL2(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_DL2_SHIFT)) & XRDC2_MSC_MSAC_W1_DL2_MASK) + #define XRDC2_MSC_MSAC_W1_VLD_MASK (0x80000000U) #define XRDC2_MSC_MSAC_W1_VLD_SHIFT (31U) /*! VLD - Valid @@ -92468,11 +103184,13 @@ typedef struct { /*! @name MDAC_MDA_W0 - Master Domain Assignment */ /*! @{ */ + #define XRDC2_MDAC_MDA_W0_MASK_MASK (0xFFFFU) #define XRDC2_MDAC_MDA_W0_MASK_SHIFT (0U) /*! MASK - Mask */ #define XRDC2_MDAC_MDA_W0_MASK(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W0_MASK_SHIFT)) & XRDC2_MDAC_MDA_W0_MASK_MASK) + #define XRDC2_MDAC_MDA_W0_MATCH_MASK (0xFFFF0000U) #define XRDC2_MDAC_MDA_W0_MATCH_SHIFT (16U) /*! MATCH - Match @@ -92488,34 +103206,33 @@ typedef struct { /*! @name MDAC_MDA_W1 - Master Domain Assignment */ /*! @{ */ -#define XRDC2_MDAC_MDA_W1_SID_MASK (0xFFFFU) -#define XRDC2_MDAC_MDA_W1_SID_SHIFT (0U) -/*! SID - Stream Identifier - */ -#define XRDC2_MDAC_MDA_W1_SID(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_SID_SHIFT)) & XRDC2_MDAC_MDA_W1_SID_MASK) + #define XRDC2_MDAC_MDA_W1_DID_MASK (0xF0000U) #define XRDC2_MDAC_MDA_W1_DID_SHIFT (16U) /*! DID - Domain Identifier */ #define XRDC2_MDAC_MDA_W1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_DID_SHIFT)) & XRDC2_MDAC_MDA_W1_DID_MASK) + #define XRDC2_MDAC_MDA_W1_PA_MASK (0x3000000U) #define XRDC2_MDAC_MDA_W1_PA_SHIFT (24U) /*! PA - Privileged attribute * 0b00..Use the bus master's privileged/user attribute directly. - * 0b01..Use the bus master's privileged/user attribute directly. Also, drive to the SID[0] output signal. + * 0b01..Use the bus master's privileged/user attribute directly. * 0b10..Force the bus attribute for this master to user. * 0b11..Force the bus attribute for this master to privileged. */ #define XRDC2_MDAC_MDA_W1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_PA_SHIFT)) & XRDC2_MDAC_MDA_W1_PA_MASK) + #define XRDC2_MDAC_MDA_W1_SA_MASK (0xC000000U) #define XRDC2_MDAC_MDA_W1_SA_SHIFT (26U) /*! SA - Secure attribute * 0b00..Use the bus master's secure/nonsecure attribute directly. - * 0b01..Use the bus master's secure/nonsecure attribute directly. Also, drive to the SID[1] output signal. + * 0b01..Use the bus master's secure/nonsecure attribute directly. * 0b10..Force the bus attribute for this master to secure. * 0b11..Force the bus attribute for this master to nonsecure. */ #define XRDC2_MDAC_MDA_W1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_SA_SHIFT)) & XRDC2_MDAC_MDA_W1_SA_MASK) + #define XRDC2_MDAC_MDA_W1_DL_MASK (0x40000000U) #define XRDC2_MDAC_MDA_W1_DL_SHIFT (30U) /*! DL - Descriptor Lock @@ -92523,6 +103240,7 @@ typedef struct { * 0b1..Lock enabled, registers are read-only until the next reset. */ #define XRDC2_MDAC_MDA_W1_DL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_DL_SHIFT)) & XRDC2_MDAC_MDA_W1_DL_MASK) + #define XRDC2_MDAC_MDA_W1_VLD_MASK (0x80000000U) #define XRDC2_MDAC_MDA_W1_VLD_SHIFT (31U) /*! VLD - Valid @@ -92540,46 +103258,55 @@ typedef struct { /*! @name PAC_PDAC_W0 - Peripheral Domain Access Control */ /*! @{ */ + #define XRDC2_PAC_PDAC_W0_D0ACP_MASK (0x7U) #define XRDC2_PAC_PDAC_W0_D0ACP_SHIFT (0U) /*! D0ACP - Domain "x" access control policy */ #define XRDC2_PAC_PDAC_W0_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D0ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D0ACP_MASK) + #define XRDC2_PAC_PDAC_W0_D1ACP_MASK (0x38U) #define XRDC2_PAC_PDAC_W0_D1ACP_SHIFT (3U) /*! D1ACP - Domain "x" access control policy */ #define XRDC2_PAC_PDAC_W0_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D1ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D1ACP_MASK) + #define XRDC2_PAC_PDAC_W0_D2ACP_MASK (0x1C0U) #define XRDC2_PAC_PDAC_W0_D2ACP_SHIFT (6U) /*! D2ACP - Domain "x" access control policy */ #define XRDC2_PAC_PDAC_W0_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D2ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D2ACP_MASK) + #define XRDC2_PAC_PDAC_W0_D3ACP_MASK (0xE00U) #define XRDC2_PAC_PDAC_W0_D3ACP_SHIFT (9U) /*! D3ACP - Domain "x" access control policy */ #define XRDC2_PAC_PDAC_W0_D3ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D3ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D3ACP_MASK) + #define XRDC2_PAC_PDAC_W0_D4ACP_MASK (0x7000U) #define XRDC2_PAC_PDAC_W0_D4ACP_SHIFT (12U) /*! D4ACP - Domain "x" access control policy */ #define XRDC2_PAC_PDAC_W0_D4ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D4ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D4ACP_MASK) + #define XRDC2_PAC_PDAC_W0_D5ACP_MASK (0x38000U) #define XRDC2_PAC_PDAC_W0_D5ACP_SHIFT (15U) /*! D5ACP - Domain "x" access control policy */ #define XRDC2_PAC_PDAC_W0_D5ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D5ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D5ACP_MASK) + #define XRDC2_PAC_PDAC_W0_D6ACP_MASK (0x1C0000U) #define XRDC2_PAC_PDAC_W0_D6ACP_SHIFT (18U) /*! D6ACP - Domain "x" access control policy */ #define XRDC2_PAC_PDAC_W0_D6ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D6ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D6ACP_MASK) + #define XRDC2_PAC_PDAC_W0_D7ACP_MASK (0xE00000U) #define XRDC2_PAC_PDAC_W0_D7ACP_SHIFT (21U) /*! D7ACP - Domain "x" access control policy */ #define XRDC2_PAC_PDAC_W0_D7ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D7ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D7ACP_MASK) + #define XRDC2_PAC_PDAC_W0_EALO_MASK (0xF000000U) #define XRDC2_PAC_PDAC_W0_EALO_SHIFT (24U) /*! EALO - Exclusive Access Lock Owner @@ -92595,46 +103322,55 @@ typedef struct { /*! @name PAC_PDAC_W1 - Peripheral Domain Access Control */ /*! @{ */ + #define XRDC2_PAC_PDAC_W1_D8ACP_MASK (0x7U) #define XRDC2_PAC_PDAC_W1_D8ACP_SHIFT (0U) /*! D8ACP - Domain "x" access control policy */ #define XRDC2_PAC_PDAC_W1_D8ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D8ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D8ACP_MASK) + #define XRDC2_PAC_PDAC_W1_D9ACP_MASK (0x38U) #define XRDC2_PAC_PDAC_W1_D9ACP_SHIFT (3U) /*! D9ACP - Domain "x" access control policy */ #define XRDC2_PAC_PDAC_W1_D9ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D9ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D9ACP_MASK) + #define XRDC2_PAC_PDAC_W1_D10ACP_MASK (0x1C0U) #define XRDC2_PAC_PDAC_W1_D10ACP_SHIFT (6U) /*! D10ACP - Domain "x" access control policy */ #define XRDC2_PAC_PDAC_W1_D10ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D10ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D10ACP_MASK) + #define XRDC2_PAC_PDAC_W1_D11ACP_MASK (0xE00U) #define XRDC2_PAC_PDAC_W1_D11ACP_SHIFT (9U) /*! D11ACP - Domain "x" access control policy */ #define XRDC2_PAC_PDAC_W1_D11ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D11ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D11ACP_MASK) + #define XRDC2_PAC_PDAC_W1_D12ACP_MASK (0x7000U) #define XRDC2_PAC_PDAC_W1_D12ACP_SHIFT (12U) /*! D12ACP - Domain "x" access control policy */ #define XRDC2_PAC_PDAC_W1_D12ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D12ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D12ACP_MASK) + #define XRDC2_PAC_PDAC_W1_D13ACP_MASK (0x38000U) #define XRDC2_PAC_PDAC_W1_D13ACP_SHIFT (15U) /*! D13ACP - Domain "x" access control policy */ #define XRDC2_PAC_PDAC_W1_D13ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D13ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D13ACP_MASK) + #define XRDC2_PAC_PDAC_W1_D14ACP_MASK (0x1C0000U) #define XRDC2_PAC_PDAC_W1_D14ACP_SHIFT (18U) /*! D14ACP - Domain "x" access control policy */ #define XRDC2_PAC_PDAC_W1_D14ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D14ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D14ACP_MASK) + #define XRDC2_PAC_PDAC_W1_D15ACP_MASK (0xE00000U) #define XRDC2_PAC_PDAC_W1_D15ACP_SHIFT (21U) /*! D15ACP - Domain "x" access control policy */ #define XRDC2_PAC_PDAC_W1_D15ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D15ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D15ACP_MASK) + #define XRDC2_PAC_PDAC_W1_EAL_MASK (0x3000000U) #define XRDC2_PAC_PDAC_W1_EAL_SHIFT (24U) /*! EAL - Exclusive Access Lock @@ -92644,6 +103380,7 @@ typedef struct { * 0b11..Lock enabled, lock state = not available. */ #define XRDC2_PAC_PDAC_W1_EAL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_EAL_SHIFT)) & XRDC2_PAC_PDAC_W1_EAL_MASK) + #define XRDC2_PAC_PDAC_W1_DL2_MASK (0x60000000U) #define XRDC2_PAC_PDAC_W1_DL2_SHIFT (29U) /*! DL2 - Descriptor Lock @@ -92653,6 +103390,7 @@ typedef struct { * 0b11..Lock enabled, descriptor registers are read-only until the next reset. */ #define XRDC2_PAC_PDAC_W1_DL2(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_DL2_SHIFT)) & XRDC2_PAC_PDAC_W1_DL2_MASK) + #define XRDC2_PAC_PDAC_W1_VLD_MASK (0x80000000U) #define XRDC2_PAC_PDAC_W1_VLD_SHIFT (31U) /*! VLD - Valid @@ -92670,6 +103408,7 @@ typedef struct { /*! @name MRC_MRGD_W0 - Memory Region Descriptor */ /*! @{ */ + #define XRDC2_MRC_MRGD_W0_SRTADDR_MASK (0xFFFFF000U) #define XRDC2_MRC_MRGD_W0_SRTADDR_SHIFT (12U) /*! SRTADDR - Start Address @@ -92685,6 +103424,7 @@ typedef struct { /*! @name MRC_MRGD_W1 - Memory Region Descriptor */ /*! @{ */ + #define XRDC2_MRC_MRGD_W1_SRTADDR_MASK (0xFU) #define XRDC2_MRC_MRGD_W1_SRTADDR_SHIFT (0U) /*! SRTADDR - Start Address @@ -92700,6 +103440,7 @@ typedef struct { /*! @name MRC_MRGD_W2 - Memory Region Descriptor */ /*! @{ */ + #define XRDC2_MRC_MRGD_W2_ENDADDR_MASK (0xFFFFF000U) #define XRDC2_MRC_MRGD_W2_ENDADDR_SHIFT (12U) /*! ENDADDR - End Address @@ -92715,6 +103456,7 @@ typedef struct { /*! @name MRC_MRGD_W3 - Memory Region Descriptor */ /*! @{ */ + #define XRDC2_MRC_MRGD_W3_ENDADDR_MASK (0xFU) #define XRDC2_MRC_MRGD_W3_ENDADDR_SHIFT (0U) /*! ENDADDR - End Address @@ -92728,70 +103470,57 @@ typedef struct { /* The count of XRDC2_MRC_MRGD_W3 */ #define XRDC2_MRC_MRGD_W3_COUNT2 (32U) -/*! @name MRC_MRGD_W4 - Memory Region Descriptor */ -/*! @{ */ -#define XRDC2_MRC_MRGD_W4_RMSG_MASK (0xFU) -#define XRDC2_MRC_MRGD_W4_RMSG_SHIFT (0U) -/*! RMSG - Relay Message - */ -#define XRDC2_MRC_MRGD_W4_RMSG(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W4_RMSG_SHIFT)) & XRDC2_MRC_MRGD_W4_RMSG_MASK) -#define XRDC2_MRC_MRGD_W4_DET_MASK (0x10000000U) -#define XRDC2_MRC_MRGD_W4_DET_SHIFT (28U) -/*! DET - Detour Switch - * 0b0..Do not re-route address. - * 0b1..Re-route address. - */ -#define XRDC2_MRC_MRGD_W4_DET(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W4_DET_SHIFT)) & XRDC2_MRC_MRGD_W4_DET_MASK) -/*! @} */ - -/* The count of XRDC2_MRC_MRGD_W4 */ -#define XRDC2_MRC_MRGD_W4_COUNT (32U) - -/* The count of XRDC2_MRC_MRGD_W4 */ -#define XRDC2_MRC_MRGD_W4_COUNT2 (32U) - /*! @name MRC_MRGD_W5 - Memory Region Descriptor */ /*! @{ */ + #define XRDC2_MRC_MRGD_W5_D0ACP_MASK (0x7U) #define XRDC2_MRC_MRGD_W5_D0ACP_SHIFT (0U) /*! D0ACP - Domain "x" access control policy */ #define XRDC2_MRC_MRGD_W5_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D0ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D0ACP_MASK) + #define XRDC2_MRC_MRGD_W5_D1ACP_MASK (0x38U) #define XRDC2_MRC_MRGD_W5_D1ACP_SHIFT (3U) /*! D1ACP - Domain "x" access control policy */ #define XRDC2_MRC_MRGD_W5_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D1ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D1ACP_MASK) + #define XRDC2_MRC_MRGD_W5_D2ACP_MASK (0x1C0U) #define XRDC2_MRC_MRGD_W5_D2ACP_SHIFT (6U) /*! D2ACP - Domain "x" access control policy */ #define XRDC2_MRC_MRGD_W5_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D2ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D2ACP_MASK) + #define XRDC2_MRC_MRGD_W5_D3ACP_MASK (0xE00U) #define XRDC2_MRC_MRGD_W5_D3ACP_SHIFT (9U) /*! D3ACP - Domain "x" access control policy */ #define XRDC2_MRC_MRGD_W5_D3ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D3ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D3ACP_MASK) + #define XRDC2_MRC_MRGD_W5_D4ACP_MASK (0x7000U) #define XRDC2_MRC_MRGD_W5_D4ACP_SHIFT (12U) /*! D4ACP - Domain "x" access control policy */ #define XRDC2_MRC_MRGD_W5_D4ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D4ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D4ACP_MASK) + #define XRDC2_MRC_MRGD_W5_D5ACP_MASK (0x38000U) #define XRDC2_MRC_MRGD_W5_D5ACP_SHIFT (15U) /*! D5ACP - Domain "x" access control policy */ #define XRDC2_MRC_MRGD_W5_D5ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D5ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D5ACP_MASK) + #define XRDC2_MRC_MRGD_W5_D6ACP_MASK (0x1C0000U) #define XRDC2_MRC_MRGD_W5_D6ACP_SHIFT (18U) /*! D6ACP - Domain "x" access control policy */ #define XRDC2_MRC_MRGD_W5_D6ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D6ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D6ACP_MASK) + #define XRDC2_MRC_MRGD_W5_D7ACP_MASK (0xE00000U) #define XRDC2_MRC_MRGD_W5_D7ACP_SHIFT (21U) /*! D7ACP - Domain "x" access control policy */ #define XRDC2_MRC_MRGD_W5_D7ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D7ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D7ACP_MASK) + #define XRDC2_MRC_MRGD_W5_EALO_MASK (0xF000000U) #define XRDC2_MRC_MRGD_W5_EALO_SHIFT (24U) /*! EALO - Exclusive Access Lock Owner @@ -92807,46 +103536,55 @@ typedef struct { /*! @name MRC_MRGD_W6 - Memory Region Descriptor */ /*! @{ */ + #define XRDC2_MRC_MRGD_W6_D8ACP_MASK (0x7U) #define XRDC2_MRC_MRGD_W6_D8ACP_SHIFT (0U) /*! D8ACP - Domain "x" access control policy */ #define XRDC2_MRC_MRGD_W6_D8ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D8ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D8ACP_MASK) + #define XRDC2_MRC_MRGD_W6_D9ACP_MASK (0x38U) #define XRDC2_MRC_MRGD_W6_D9ACP_SHIFT (3U) /*! D9ACP - Domain "x" access control policy */ #define XRDC2_MRC_MRGD_W6_D9ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D9ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D9ACP_MASK) + #define XRDC2_MRC_MRGD_W6_D10ACP_MASK (0x1C0U) #define XRDC2_MRC_MRGD_W6_D10ACP_SHIFT (6U) /*! D10ACP - Domain "x" access control policy */ #define XRDC2_MRC_MRGD_W6_D10ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D10ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D10ACP_MASK) + #define XRDC2_MRC_MRGD_W6_D11ACP_MASK (0xE00U) #define XRDC2_MRC_MRGD_W6_D11ACP_SHIFT (9U) /*! D11ACP - Domain "x" access control policy */ #define XRDC2_MRC_MRGD_W6_D11ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D11ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D11ACP_MASK) + #define XRDC2_MRC_MRGD_W6_D12ACP_MASK (0x7000U) #define XRDC2_MRC_MRGD_W6_D12ACP_SHIFT (12U) /*! D12ACP - Domain "x" access control policy */ #define XRDC2_MRC_MRGD_W6_D12ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D12ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D12ACP_MASK) + #define XRDC2_MRC_MRGD_W6_D13ACP_MASK (0x38000U) #define XRDC2_MRC_MRGD_W6_D13ACP_SHIFT (15U) /*! D13ACP - Domain "x" access control policy */ #define XRDC2_MRC_MRGD_W6_D13ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D13ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D13ACP_MASK) + #define XRDC2_MRC_MRGD_W6_D14ACP_MASK (0x1C0000U) #define XRDC2_MRC_MRGD_W6_D14ACP_SHIFT (18U) /*! D14ACP - Domain "x" access control policy */ #define XRDC2_MRC_MRGD_W6_D14ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D14ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D14ACP_MASK) + #define XRDC2_MRC_MRGD_W6_D15ACP_MASK (0xE00000U) #define XRDC2_MRC_MRGD_W6_D15ACP_SHIFT (21U) /*! D15ACP - Domain "x" access control policy */ #define XRDC2_MRC_MRGD_W6_D15ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D15ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D15ACP_MASK) + #define XRDC2_MRC_MRGD_W6_EAL_MASK (0x3000000U) #define XRDC2_MRC_MRGD_W6_EAL_SHIFT (24U) /*! EAL - Exclusive Access Lock @@ -92856,6 +103594,7 @@ typedef struct { * 0b11..Lock enabled, lock state = not available. */ #define XRDC2_MRC_MRGD_W6_EAL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_EAL_SHIFT)) & XRDC2_MRC_MRGD_W6_EAL_MASK) + #define XRDC2_MRC_MRGD_W6_DL2_MASK (0x60000000U) #define XRDC2_MRC_MRGD_W6_DL2_SHIFT (29U) /*! DL2 - Descriptor Lock @@ -92865,6 +103604,7 @@ typedef struct { * 0b11..Lock enabled, descriptor registers are read-only until the next reset. */ #define XRDC2_MRC_MRGD_W6_DL2(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_DL2_SHIFT)) & XRDC2_MRC_MRGD_W6_DL2_MASK) + #define XRDC2_MRC_MRGD_W6_VLD_MASK (0x80000000U) #define XRDC2_MRC_MRGD_W6_VLD_SHIFT (31U) /*! VLD - Valid diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/MIMXRT1176_cm7_features.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/MIMXRT1176_cm7_features.h index 260d9197e28..2710b9e3cd8 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/MIMXRT1176_cm7_features.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/MIMXRT1176_cm7_features.h @@ -1,7 +1,7 @@ /* ** ################################################################### -** Version: rev. 0.1, 2018-03-05 -** Build: b200804 +** Version: rev. 1.0, 2020-12-29 +** Build: b201229 ** ** Abstract: ** Chip specific module features. @@ -18,6 +18,8 @@ ** Revisions: ** - rev. 0.1 (2018-03-05) ** Initial version. +** - rev. 1.0 (2020-12-29) +** Update feature files to align with IMXRT1170RM Rev.0. ** ** ################################################################### */ @@ -29,8 +31,6 @@ /* @brief ACMP availability on the SoC. */ #define FSL_FEATURE_SOC_ACMP_COUNT (4) -/* @brief AIPSTZ availability on the SoC. */ -#define FSL_FEATURE_SOC_AIPSTZ_COUNT (4) /* @brief AOI availability on the SoC. */ #define FSL_FEATURE_SOC_AOI_COUNT (2) /* @brief ASRC availability on the SoC. */ @@ -67,8 +67,6 @@ #define FSL_FEATURE_SOC_FLEXRAM_COUNT (1) /* @brief FLEXSPI availability on the SoC. */ #define FSL_FEATURE_SOC_FLEXSPI_COUNT (2) -/* @brief SFA availability on the SoC. */ -#define FSL_FEATURE_SOC_SFA_COUNT (1) /* @brief GPT availability on the SoC. */ #define FSL_FEATURE_SOC_GPT_COUNT (6) /* @brief I2S availability on the SoC. */ @@ -115,8 +113,6 @@ #define FSL_FEATURE_SOC_RDC_COUNT (1) /* @brief RDC_SEMAPHORE availability on the SoC. */ #define FSL_FEATURE_SOC_RDC_SEMAPHORE_COUNT (2) -/* @brief ROMC availability on the SoC. */ -#define FSL_FEATURE_SOC_ROMC_COUNT (1) /* @brief SEMA4 availability on the SoC. */ #define FSL_FEATURE_SOC_SEMA4_COUNT (1) /* @brief SEMC availability on the SoC. */ @@ -137,8 +133,6 @@ #define FSL_FEATURE_SOC_USBNC_COUNT (2) /* @brief USBPHY availability on the SoC. */ #define FSL_FEATURE_SOC_USBPHY_COUNT (2) -/* @brief USB_ANALOG availability on the SoC. */ -#define FSL_FEATURE_SOC_USB_ANALOG_COUNT (1) /* @brief USDHC availability on the SoC. */ #define FSL_FEATURE_SOC_USDHC_COUNT (2) /* @brief WDOG availability on the SoC. */ @@ -156,6 +150,10 @@ #define FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL (1) /* @brief Has TRIGm_CHAIN_a_b IEn_EN. */ #define FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN (1) +/* @brief Has no TSC0 trigger related bitfields (bit field CTRL[EXT0_TRIG_ENABLE], CTRL[EXT0_TRIG_PRIORITY]). */ +#define FSL_FEATURE_ADC_ETC_HAS_NO_TSC0_TRIG (1) +/* @brief Has no TSC1 trigger related bitfields (bit field CTRL[EXT1_TRIG_ENABLE], CTRL[EXT1_TRIG_PRIORITY]). */ +#define FSL_FEATURE_ADC_ETC_HAS_NO_TSC1_TRIG (1) /* AOI module features */ @@ -164,6 +162,11 @@ /* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */ #define FSL_FEATURE_AOI_EVENT_COUNT (4) +/* ASRC module features */ + +/* @brief Register name is ASPRM or ASPRMn */ +#define FSL_FEATURE_ASRC_PARAMETER_REGISTER_NAME_ASPRM (1) + /* AUDIO_PLL module features */ /* No feature definitions */ @@ -206,12 +209,25 @@ #define FSL_FEATURE_FLEXCAN_HAS_EXTRA_MB_INT (1) /* @brief Has memory error control (register MECR). */ #define FSL_FEATURE_FLEXCAN_HAS_MEMORY_ERROR_CONTROL (1) +/* @brief Init memory base 1 */ +#define FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_1 (0x80) +/* @brief Init memory size 1 */ +#define FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_1 (0xA60) +/* @brief Init memory base 2 */ +#define FSL_FEATURE_FLEXCAN_INIT_MEMORY_BASE_2 (0xF28) +/* @brief Init memory size 2 */ +#define FSL_FEATURE_FLEXCAN_INIT_MEMORY_SIZE_2 (0xD8) /* CCM module features */ /* @brief Is affected by errata with ID 50235 (Incorrect clock setting for CAN affects by LPUART clock gate). */ #define FSL_FEATURE_CCM_HAS_ERRATA_50235 (0) +/* CDOG module features */ + +/* @brief SOC has no reset driver. */ +#define FSL_FEATURE_CDOG_HAS_NO_RESET (1) + /* IGPIO module features */ /* @brief Has data register set DR_SET. */ @@ -234,12 +250,22 @@ /* @brief Has C1 INNSEL Bit */ #define FSL_FEATURE_ACMP_HAS_C1_INNSEL_BIT (0) /* @brief Has C1 DACOE Bit */ -#define FSL_FEATURE_ACMP_HAS_C1_DACOE_BIT (1) +#define FSL_FEATURE_ACMP_HAS_C1_DACOE_BIT (0) /* @brief Has C1 DMODE Bit */ #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (1) /* @brief Has C2 RRE Bit */ #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (0) +/* CSI module features */ + +/* @brief If CSI registers don't have prefix. */ +#define FSL_FEATURE_CSI_NO_REG_PREFIX (1) + +/* DAC12 module features */ + +/* @brief Has no ITRM register. */ +#define FSL_FEATURE_DAC12_HAS_NO_ITRM_REGISTER (1) + /* DCDC module features */ /* @brief Has CTRL register (register CTRL0/1). */ @@ -288,6 +314,8 @@ #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) /* @brief Has DMA Channel Always ON function (register bit CHCFG0[A_ON]). */ #define FSL_FEATURE_DMAMUX_HAS_A_ON (1) +/* @brief Register CHCFGn width. */ +#define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (32) /* ENET module features */ @@ -323,6 +351,10 @@ #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) +/* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ +#define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (1) +/* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ +#define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) /* ENET_QOS module features */ @@ -372,6 +404,8 @@ #define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (16) /* @brief Has FLEXRAM_MAGIC_ADDR. */ #define FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR (1) +/* @brief If FLEXRAM has ECC function. */ +#define FSL_FEATURE_FLEXRAM_HAS_ECC (1) /* FLEXSPI module features */ @@ -384,15 +418,15 @@ /* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */ #define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (0) -/* GPC_CPU_MODE_CTRL module features */ +/* GPC_CPU_CTRL module features */ /* No feature definitions */ -/* GPC_SET_POINT_CTRL module features */ +/* GPC_SP_CTRL module features */ /* No feature definitions */ -/* GPC_STBY_POINT_CTRL module features */ +/* GPC_STBY_CTRL module features */ /* No feature definitions */ @@ -424,7 +458,11 @@ /* @brief Clut RAM offset, see datail in RM */ #define FSL_FEATURE_LCDIFV2_CLUT_RAM_OFFSET (0x2000) -/* @brief CSC count in Layer */ +/* @brief Init doamin count, register INIT[n]_ENABLE. */ +#define FSL_FEATURE_LCDIFV2_INT_DOMAIN_COUNT (2) +/* @brief Layer count */ +#define FSL_FEATURE_LCDIFV2_LAYER_COUNT (8) +/* @brief CSC count in layer, register CSC_COEF[n]. */ #define FSL_FEATURE_LCDIFV2_LAYER_CSC_COUNT (2) /* LPADC module features */ @@ -537,6 +575,16 @@ /* @brief Has LPUART_PINCFG. */ #define FSL_FEATURE_LPUART_HAS_PINCFG (1) +/* CSI2RX module features */ + +/* @brief If MIPI_CSI2RX registers don't have prefix. */ +#define FSL_FEATURE_CSI2RX_HAS_NO_REG_PREFIX (1) + +/* DSI_HOST module features */ + +/* @brief Has separate submodules */ +#define FSL_FEATURE_MIPI_DSI_HAS_SEPARATE_SUBMODULE (1) + /* MU module features */ /* @brief MU side for current core */ @@ -546,7 +594,7 @@ /* @brief MU Has register SR[RS], BSR[ARS] */ #define FSL_FEATURE_MU_HAS_SR_RS (1) /* @brief MU Has register CR[RDIE], CR[RAIE], SR[RDIP], SR[RAIP] */ -#define FSL_FEATURE_MU_HAS_RESET_INT (1) +#define FSL_FEATURE_MU_HAS_RESET_INT (0) /* @brief MU Has register SR[MURIP] */ #define FSL_FEATURE_MU_HAS_SR_MURIP (0) /* @brief MU Has register SR[HRIP] */ @@ -583,8 +631,6 @@ #define FSL_FEATURE_OCOTP_HAS_TIMING_CTRL (0) /* @brief Support lock eFuse word write lock, (CTRL[WORDLOCK]). */ #define FSL_FEATURE_OCOTP_HAS_WORDLOCK (1) -/* @brief Has status register. (Register HW_OCOTP_OUT_STATUS0). */ -#define FSL_FEATURE_OCOTP_HAS_STATUS (1) /* OSC_RC_400M module features */ @@ -607,11 +653,11 @@ /* No feature definitions */ -/* PGMC_MIF module features */ +/* PGMC_CPC module features */ /* No feature definitions */ -/* PGMC_CPC module features */ +/* PGMC_MIF module features */ /* No feature definitions */ @@ -646,6 +692,8 @@ #define FSL_FEATURE_PWM_HAS_CHANNELX (1) /* @brief If (e)FlexPWM has fractional feature. */ #define FSL_FEATURE_PWM_HAS_FRACTIONAL (1) +/* @brief If (e)FlexPWM has mux trigger source select bit field. */ +#define FSL_FEATURE_PWM_HAS_MUX_TRIGGER_SOURCE_SEL (1) /* @brief Number of submodules in each (e)FlexPWM module. */ #define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U) /* @brief Number of fault channel in each (e)FlexPWM module. */ @@ -702,7 +750,7 @@ /* @brief Has register of MDR */ #define FSL_FEATURE_SAI_HAS_MDR (0) /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */ -#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0) +#define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (1) /* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ @@ -722,11 +770,21 @@ #define FSL_FEATURE_SEMC_HAS_SRAM_RDH_TIME (1) /* @brief Width of SDRAMCR0[PS] bitfields. */ #define FSL_FEATURE_SEMC_SUPPORT_SDRAM_PS_BITWIDTH (2) +/* @brief If SEMC has errata 050577. */ +#define FSL_FEATURE_SEMC_ERRATA_050577 (0) +/* @brief If sdram support column address 8 bit (register bit field SRAMCR0[CLO8]). */ +#define FSL_FEATURE_SEMC_SDRAM_SUPPORT_COLUMN_ADDRESS_8BIT (1) +/* @brief If SEMC has register DBICR2 (register DBICR2). */ +#define FSL_FEATURE_SEMC_HAS_DBICR2 (1) /* SNVS module features */ /* @brief Has Secure Real Time Counter Enabled and Valid (bit field LPCR[SRTC_ENV]). */ #define FSL_FEATURE_SNVS_HAS_SRTC (1) +/* @brief Has No SV3 (bit field HPSICR[SV3_EN]). */ +#define FSL_FEATURE_SNVS_HAS_NO_SV3 (1) +/* @brief Number of TAMPER. */ +#define FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER (10) /* SSARC_HP module features */ @@ -743,13 +801,6 @@ /* @brief L1 DCACHE line size in byte. */ #define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (32) -/* USBHS module features */ - -/* @brief EHCI module instance count */ -#define FSL_FEATURE_USBHS_EHCI_COUNT (2) -/* @brief Number of endpoints supported */ -#define FSL_FEATURE_USBHS_ENDPT_COUNT (8) - /* USBPHY module features */ /* @brief USBPHY contain DCD analog module */ @@ -759,6 +810,13 @@ /* @brief USBPHY is 28FDSOI */ #define FSL_FEATURE_USBPHY_28FDSOI (1) +/* USBHS module features */ + +/* @brief EHCI module instance count */ +#define FSL_FEATURE_USBHS_EHCI_COUNT (2) +/* @brief Number of endpoints supported */ +#define FSL_FEATURE_USBHS_ENDPT_COUNT (8) + /* USDHC module features */ /* @brief Has external DMA support (VEND_SPEC[EXT_DMA_EN]) */ @@ -773,6 +831,16 @@ #define FSL_FEATURE_USDHC_HAS_RESET (0) /* @brief USDHC has no bitfield WTMK_LVL[WR_BRST_LEN] and WTMK_LVL[RD_BRST_LEN] */ #define FSL_FEATURE_USDHC_HAS_NO_RW_BURST_LEN (1) +/* @brief If USDHC instance support 8 bit width */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_8_BIT_WIDTHn(x) \ + (((x) == USDHC1) ? (0) : \ + (((x) == USDHC2) ? (1) : (-1))) +/* @brief If USDHC instance support HS400 mode */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_HS400_MODEn(x) (1) +/* @brief If USDHC instance support 1v8 signal */ +#define FSL_FEATURE_USDHC_INSTANCE_SUPPORT_1V8_SIGNALn(x) (1) +/* @brief Has no retuning time counter (HOST_CTRL_CAP[TIME_COUNT_RETURNING]) */ +#define FSL_FEATURE_USDHC_REGISTER_HOST_CTRL_CAP_HAS_NO_RETUNING_TIME_COUNTER (1) /* VIDEO_PLL module features */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/system_MIMXRT1176_cm7.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/system_MIMXRT1176_cm7.c index 98a759a3e5c..e6043c1b947 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/system_MIMXRT1176_cm7.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/system_MIMXRT1176_cm7.c @@ -10,9 +10,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: IMXRT1170RM, Rev E, 12/2019 -** Version: rev. 0.1, 2018-03-05 -** Build: b200219 +** Reference manual: IMXRT1170RM, Rev 0, 12/2020 +** Version: rev. 1.0, 2020-12-29 +** Build: b210203 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -20,7 +20,7 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2020 NXP +** Copyright 2016-2021 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -31,14 +31,16 @@ ** Revisions: ** - rev. 0.1 (2018-03-05) ** Initial version. +** - rev. 1.0 (2020-12-29) +** Update header files to align with IMXRT1170RM Rev.0. ** ** ################################################################### */ /*! * @file MIMXRT1176_cm7 - * @version 0.1 - * @date 2018-03-05 + * @version 1.0 + * @date 2021-02-03 * @brief Device specific configuration file for MIMXRT1176_cm7 (implementation * file) * @@ -64,10 +66,7 @@ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; void SystemInit (void) { #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) - SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Secure mode */ - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access in Non-secure mode */ - #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ #if defined(__MCUXPRESSO) @@ -80,11 +79,11 @@ void SystemInit (void) { #if (DISABLE_WDOG) if ((WDOG1->WCR & WDOG_WCR_WDE_MASK) != 0U) { - WDOG1->WCR &= ~WDOG_WCR_WDE_MASK; + WDOG1->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK; } if ((WDOG2->WCR & WDOG_WCR_WDE_MASK) != 0U) { - WDOG2->WCR &= ~WDOG_WCR_WDE_MASK; + WDOG2->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK; } if ((RTWDOG3->CS & RTWDOG_CS_CMD32EN_MASK) != 0U) { @@ -131,11 +130,13 @@ void SystemInit (void) { /* Clear bit 13 to its reset value since it might be set by ROM. */ IOMUXC_GPR->GPR28 &= ~IOMUXC_GPR_GPR28_CACHE_USB_MASK; +#if defined(ROM_ECC_ENABLED) /* When ECC is enabled, SRC->SRSR need to be cleared since only correct SRSR value can trigger ROM ECC preload procedure. Save SRSR to SRC->GPR[10] so that application can still check SRSR value from SRC->GPR[10]. */ SRC->GPR[10] = SRC->SRSR; /* clear SRSR */ - SRC->SRSR = 0xFFFFFFFF; + SRC->SRSR = 0xFFFFFFFFU; +#endif /* Enable entry to thread mode when divide by zero */ SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk; @@ -162,3 +163,4 @@ void SystemCoreClockUpdate (void) { __attribute__ ((weak)) void SystemInitHook (void) { /* Void implementation of the weak function. */ } + diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/system_MIMXRT1176_cm7.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/system_MIMXRT1176_cm7.h index 13dc5425ef9..e57dcad0c71 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/system_MIMXRT1176_cm7.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/device/system_MIMXRT1176_cm7.h @@ -10,9 +10,9 @@ ** Keil ARM C/C++ Compiler ** MCUXpresso Compiler ** -** Reference manual: IMXRT1170RM, Rev E, 12/2019 -** Version: rev. 0.1, 2018-03-05 -** Build: b200219 +** Reference manual: IMXRT1170RM, Rev 0, 12/2020 +** Version: rev. 1.0, 2020-12-29 +** Build: b210203 ** ** Abstract: ** Provides a system configuration function and a global variable that @@ -20,7 +20,7 @@ ** the oscillator (PLL) that is part of the microcontroller device. ** ** Copyright 2016 Freescale Semiconductor, Inc. -** Copyright 2016-2020 NXP +** Copyright 2016-2021 NXP ** All rights reserved. ** ** SPDX-License-Identifier: BSD-3-Clause @@ -31,14 +31,16 @@ ** Revisions: ** - rev. 0.1 (2018-03-05) ** Initial version. +** - rev. 1.0 (2020-12-29) +** Update header files to align with IMXRT1170RM Rev.0. ** ** ################################################################### */ /*! * @file MIMXRT1176_cm7 - * @version 0.1 - * @date 2018-03-05 + * @version 1.0 + * @date 2021-02-03 * @brief Device specific configuration file for MIMXRT1176_cm7 (header file) * * Provides a system configuration function and a global variable that contains diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_anatop.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_anatop.c deleted file mode 100644 index 31b6fc4c867..00000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_anatop.c +++ /dev/null @@ -1,240 +0,0 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include "fsl_anatop.h" -#include "fsl_anatop_ai.h" -#include "fsl_clock.h" - -/* Component ID definition, used by tools. */ -#ifndef FSL_COMPONENT_ID -#define FSL_COMPONENT_ID "platform.drivers.anatop" -#endif - -/******************************************************************************* - * Code - ******************************************************************************/ -/* CM7 FBB config */ -void ANATOP_Cm7FbbCfg(void) -{ - /* anatop_cm7_fbb_config! */; - ANATOP_InitWbiasCfg(true, false); - ANATOP_WbCfg1p8Cfg(0x01EE); - /* This is to enable PW/NW regulator path to CM7 FBB and disable regulator - * path to LPSR/SOC RBB. Since RVT does not support FBB. - */ - ANATOP_WbPwrSwEn1p8(1); - /* Enable wbias */ - ANATOP_EnableWbias(true); -} - -void ANATOP_InitWbiasCfg(bool fbb_on, bool rbb_on) -{ - if(fbb_on) - { - /* This is to select FBB regulator target voltage as 0.6V for CM7 LVT. */ - /* Set wb_nw_lvl_1p8 and wb_pw_lvl_1p8 in PMU_BIAS_CTRL to 4b’0001! */; - ANATOP_WbiasPwlvl_1p8(0x1); - ANATOP_WbiasNwlvl_1p8(0x1); - } - else if(rbb_on) - { - ANATOP_WbiasPwlvl_1p8(0x5); - ANATOP_WbiasNwlvl_1p8(0x5); - } - else - { - ANATOP_WbiasPwlvl_1p8(0x0); - ANATOP_WbiasNwlvl_1p8(0x0); - } -} - -void ANATOP_WbiasPwlvl_1p8(uint32_t pw_lvl_1p8) -{ - uint32_t reg; - /* If wb_en_1p8=1, these bits set the vbb_rpw voltage level! */; - reg = ANADIG_PMU->PMU_BIAS_CTRL; - reg &= ~ANADIG_PMU_PMU_BIAS_CTRL_WB_PW_LVL_1P8_MASK; - reg |= ANADIG_PMU_PMU_BIAS_CTRL_WB_PW_LVL_1P8(pw_lvl_1p8); - ANADIG_PMU->PMU_BIAS_CTRL = reg; - /* anatop_wbias_pw_lvl_1p8: finished. */; -} - -void ANATOP_WbiasNwlvl_1p8(uint32_t nw_lvl_1p8) -{ - uint32_t reg; - /* If wb_en_1p8=1, these bits set the vbb_rnw voltage level! */; - reg = ANADIG_PMU->PMU_BIAS_CTRL; - reg &= ~ANADIG_PMU_PMU_BIAS_CTRL_WB_NW_LVL_1P8_MASK; - reg |= ANADIG_PMU_PMU_BIAS_CTRL_WB_NW_LVL_1P8(nw_lvl_1p8); - ANADIG_PMU->PMU_BIAS_CTRL = reg; - /* anatop_wbias_nw_lvl_1p8: finished. */; -} - -void ANATOP_WbCfg1p8Cfg(uint32_t wb_cfg_1p8) -{ - uint32_t reg; - /* anatop_wb_cfg_1p8_cfg. */; - /* Wb_cfg_1p8<0> = 0, NW tracking regulator is used */ - /* Wb_cfg_1p8<1> = 1, LVT selection */ - /* Wb_cfg_1p8<4:2> = 3’b011, drive strength for M7 FBB */ - /* Wb_cfg_1p8<5:8> = 4’b1111 use osc frequency */ - reg = ANADIG_PMU->PMU_BIAS_CTRL; - reg &= ~ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK; - reg |= ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8(wb_cfg_1p8); - ANADIG_PMU->PMU_BIAS_CTRL = reg; -} - -void ANATOP_WbPwrSwEn1p8(uint32_t wb_pwr_sw_en_1p8) -{ - uint32_t reg; - /* Set wb_pwr_sw_en_1p8 in PMU_BIAS_CTRL2! */; - reg = ANADIG_PMU->PMU_BIAS_CTRL2; - reg &= ~ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK; - reg |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(wb_pwr_sw_en_1p8); - ANADIG_PMU->PMU_BIAS_CTRL2 = reg; -} - -void ANATOP_EnableWbias(bool enable) -{ - uint32_t reg; - reg = ANADIG_PMU->PMU_BIAS_CTRL2; - reg &= ~ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK; - reg |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN(enable); - ANADIG_PMU->PMU_BIAS_CTRL2 = reg; -} - -void ANATOP_EnablePllLdo() -{ - uint32_t r = ANATOP_AI_Read(kAI_Itf_Ldo, 0); - if (r != 0x105) - { - ANATOP_AI_Write(kAI_Itf_Ldo, 0, 0x105); - ANATOP_AI_Read(kAI_Itf_Ldo, 0); - ANADIG_PMU->PMU_POWER_DETECT_CTRL = ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_MASK; - ANADIG_MISC->VDDSOC_AI_CTRL &= ~ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK; - SDK_DelayAtLeastUs(1, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - ANADIG_PMU->PMU_REF_CTRL |= 0x10; - } -} - -void ANATOP_DisablePllLdo() -{ - ANATOP_AI_Write(kAI_Itf_Ldo, 0, 0); -} - -void ANATOP_TrimLdoLpsrDig(uint32_t target_voltage) -{ - uint8_t trim_value; - uint32_t reg; - - trim_value = (target_voltage - 628)/20; - reg = ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG; - reg &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRIM_MASK; - reg |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRIM(trim_value); - ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG = reg; -} - -void ANATOP_LdoLpsrAnaBypassOn() -{ - /* HP mode */ - ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK; - SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - /* tracking */ - ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_MASK; - SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - /* set BYPASS */ - ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK; - SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - /* Disable LDO */ - ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK; -} - -void ANATOP_LdoLpsrAnaBypassOff() -{ - /* Enable LDO and HP mode */ - ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA &= ~(ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK | - ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK); - SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - /* Clear BYPASS */ - ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK; - SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - /* Disable tracking */ - ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_MASK; -} - -void ANATOP_LdoLpsrDigBypassOn() -{ - /* HP mode */ - ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_HP_EN_MASK; - SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - /* tracking */ - ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_MASK; - SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - /* set BYPASS */ - ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK; - SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - /* Disable LDO */ - ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK; -} - -void ANATOP_LdoLpsrDigBypassOff() -{ - /* Enable LDO and HP mode */ - ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG |= (ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK | - ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_HP_EN_MASK); - SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - /* Clear BYPASS */ - ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK; - SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - /* Disable tracking */ - ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_MASK; -} - -void ANATOP_BothLdoLpsrBypassOn() -{ - /* HP mode */ - ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK; - /* HP mode */ - ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_HP_EN_MASK; - SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - /* tracking */ - ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_MASK; - /* tracking */ - ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_MASK; - SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - /* set BYPASS */ - ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK; - /* set BYPASS */ - ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK; - SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - /* Disable LDO */ - ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK; - /* Disable LDO */ - ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK; -} - -void ANATOP_BothLdoLpsrBypassOff() -{ - /* Enable LDO */ - ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK; - /* Enable LDO */ - ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK; - /* HP mode */ - ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK; - /* HP mode */ - ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_HP_EN_MASK; - SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - /* Clear BYPASS */ - ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK; - /* Clear BYPASS */ - ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK; - SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - /* Disable tracking */ - ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_MASK; - /* Disable tracking */ - ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_MASK; -} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_anatop.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_anatop.h deleted file mode 100644 index f5d980ff761..00000000000 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_anatop.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright 2019 NXP - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef _FSL_ANATOP_H_ -#define _FSL_ANATOP_H_ -#endif - -#include "fsl_common.h" - -/*! @addtogroup anatop */ -/*! @{ */ - -/*! @file */ - -/******************************************************************************* - * Configurations - ******************************************************************************/ - -/******************************************************************************* - * Definitions - ******************************************************************************/ - -/*! @name Driver version */ -/*@{*/ -/*! @brief ANATOP driver version 2.0.0. */ -#define FSL_ANATOP_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) -/*@}*/ - -/******************************************************************************* - * API - ******************************************************************************/ - -#if defined(__cplusplus) -extern "C" { -#endif /* __cplusplus */ - -void ANATOP_Cm7FbbCfg(void); -void ANATOP_InitWbiasCfg(bool fbb_on, bool rbb_on); -void ANATOP_WbiasPwlvl_1p8(uint32_t pw_lvl_1p8); -void ANATOP_WbiasNwlvl_1p8(uint32_t nw_lvl_1p8); -void ANATOP_WbCfg1p8Cfg(uint32_t wb_cfg_1p8); -void ANATOP_WbPwrSwEn1p8(uint32_t wb_pwr_sw_en_1p8); -void ANATOP_EnableWbias(bool enable); -void ANATOP_TrimLdoLpsrDig(uint32_t target_voltage); - -/*! - * @brief bypass LPSR LDO - * - */ -void ANATOP_LdoLpsrAnaBypassOn(void); - -/*! - * @brief Enable PLL LDO - * - */ -void ANATOP_EnablePllLdo(void); -/* @} */ - -#if defined(__cplusplus) -} -#endif /* __cplusplus */ - -/*! @} */ - -# - diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_anatop_ai.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_anatop_ai.c index f7c97c8ecde..c78ded8d50d 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_anatop_ai.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_anatop_ai.c @@ -11,14 +11,14 @@ #define FSL_COMPONENT_ID "platform.drivers.anatop_ai" #endif -uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, uint8_t addr, uint32_t wdata) +uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, anatop_ai_reg_t addr, uint32_t wdata) { uint32_t temp; uint32_t rdata; uint32_t pre_toggle_done; uint32_t toggle_done; - switch(itf) + switch (itf) { case kAI_Itf_Ldo: if (isWrite) @@ -26,57 +26,75 @@ uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, uint8_t addr, uint3 ANADIG_MISC->VDDSOC_AI_CTRL &= ~ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK; temp = ANADIG_MISC->VDDSOC_AI_CTRL; temp &= ~ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK; - temp |= (addr << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT) & ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK; - ANADIG_MISC->VDDSOC_AI_CTRL = temp; - ANADIG_MISC->VDDSOC_AI_WDATA = wdata ; /* write ai data */ + temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT) & + ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK; + ANADIG_MISC->VDDSOC_AI_CTRL = temp; + ANADIG_MISC->VDDSOC_AI_WDATA = wdata; /* write ai data */ ANADIG_PMU->PMU_LDO_PLL ^= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK; /* toggle */ } else /* read */ { temp = ANADIG_MISC->VDDSOC_AI_CTRL; temp &= ~ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK; - temp |= (1 << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_SHIFT) & ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK; + temp |= (1UL << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_SHIFT) & + ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK; ANADIG_MISC->VDDSOC_AI_CTRL = temp; - temp = ANADIG_MISC->VDDSOC_AI_CTRL; + temp = ANADIG_MISC->VDDSOC_AI_CTRL; temp &= ~ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK; - temp |= (addr << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT) & ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK; + temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT) & + ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK; ANADIG_MISC->VDDSOC_AI_CTRL = temp; ANADIG_PMU->PMU_LDO_PLL ^= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK; /* toggle */ - rdata = ANADIG_MISC->VDDSOC_AI_RDATA; /* read data */ + rdata = ANADIG_MISC->VDDSOC_AI_RDATA; /* read data */ return rdata; } break; case kAI_Itf_1g: if (isWrite) { - pre_toggle_done = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK; /* get pre_toggle_done */ + pre_toggle_done = + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK; /* get pre_toggle_done */ ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK; temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G; temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK; - temp |= (addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK; - ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G = temp; - ANADIG_MISC->VDDSOC2PLL_AI_WDATA_1G = wdata ; /* write ai data */ - ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G ^= ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK; /* toggle */ + temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT) & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK; + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G = temp; + ANADIG_MISC->VDDSOC2PLL_AI_WDATA_1G = wdata; /* write ai data */ + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G ^= + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK; /* toggle */ do { - toggle_done = (ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK); /* wait toggle done toggle */ + toggle_done = + (ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK); /* wait toggle done + toggle */ } while (toggle_done == pre_toggle_done); } else { - pre_toggle_done = (ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK); /* get pre_toggle_done */ + pre_toggle_done = + (ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK); /* get pre_toggle_done */ temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G; temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK; - temp |= (1 << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_SHIFT) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK; + temp |= (1UL << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_SHIFT) & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK; ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G = temp; - temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G; + temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G; temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK; - temp |= (addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK; + temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT) & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK; ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G = temp; - ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G ^= ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK; /* toggle */ + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G ^= + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK; /* toggle */ do { - toggle_done = (ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK); /* wait toggle done toggle */ + toggle_done = + (ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK); /* wait toggle done + toggle */ } while (toggle_done == pre_toggle_done); rdata = ANADIG_MISC->VDDSOC2PLL_AI_RDATA_1G; /* read data */ return rdata; @@ -85,37 +103,55 @@ uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, uint8_t addr, uint3 case kAI_Itf_Audio: if (isWrite) { - pre_toggle_done = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK; /* get pre_toggle_done */ - ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK; + pre_toggle_done = + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK; /* get pre_toggle_done */ + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &= + ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK; temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO; temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK; - temp |= (addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK; - ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO = temp; - ANADIG_MISC->VDDSOC2PLL_AI_WDATA_AUDIO = wdata ; /* write ai data */ - ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO ^= ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK; /* toggle */ + temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT) & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK; + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO = temp; + ANADIG_MISC->VDDSOC2PLL_AI_WDATA_AUDIO = wdata; /* write ai data */ + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO ^= + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK; /* toggle */ do { - toggle_done = (ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK); /* wait toggle done toggle */ + toggle_done = + (ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK); /* wait toggle done + toggle */ } while (toggle_done == pre_toggle_done); - ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK; + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &= + ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK; } else { - pre_toggle_done = (ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK); /* get pre_toggle_done */ + pre_toggle_done = + (ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK); /* get pre_toggle_done + */ temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO; temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK; - temp |= (1 << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_SHIFT) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK; + temp |= (1UL << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_SHIFT) & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK; ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO = temp; temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO; temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK; - temp |= (addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK; + temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT) & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK; ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO = temp; - ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO ^= ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK; /* toggle */ + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO ^= + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK; /* toggle */ do { - toggle_done = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK; /* wait toggle done toggle */ + toggle_done = + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK; /* wait toggle done + toggle */ } while (toggle_done == pre_toggle_done); rdata = ANADIG_MISC->VDDSOC2PLL_AI_RDATA_AUDIO; /* read data */ return rdata; @@ -124,39 +160,55 @@ uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, uint8_t addr, uint3 case kAI_Itf_Video: if (isWrite) { - pre_toggle_done = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* get pre_toggle_done */ + pre_toggle_done = + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* get pre_toggle_done */ - ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK; + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &= + ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK; temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO; temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK; - temp |= (addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK; - ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO = temp; - ANADIG_MISC->VDDSOC2PLL_AI_WDATA_VIDEO = wdata ; /* write ai data */ - ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO ^= ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK; /* toggle */ + temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT) & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK; + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO = temp; + ANADIG_MISC->VDDSOC2PLL_AI_WDATA_VIDEO = wdata; /* write ai data */ + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO ^= + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK; /* toggle */ do { - toggle_done = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* wait toggle done toggle */ - } - while (toggle_done == pre_toggle_done); - ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK; + toggle_done = + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* wait toggle done + toggle */ + } while (toggle_done == pre_toggle_done); + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &= + ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK; } else { - pre_toggle_done = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* get pre_toggle_done */ + pre_toggle_done = + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* get pre_toggle_done */ temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO; temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK; - temp |= (1 << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_SHIFT) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK; + temp |= (1UL << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_SHIFT) & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK; ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO = temp; temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO; temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK; - temp |= (addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK; + temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT) & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK; ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO = temp; - ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO ^= ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK; /* toggle */ + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO ^= + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK; /* toggle */ do { - toggle_done = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* wait toggle done toggle */ + toggle_done = + ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO & + ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* wait toggle done + toggle */ } while (toggle_done == pre_toggle_done); rdata = ANADIG_MISC->VDDSOC2PLL_AI_RDATA_VIDEO; /* read data */ return rdata; @@ -165,118 +217,138 @@ uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, uint8_t addr, uint3 case kAI_Itf_400m: if (isWrite) { - pre_toggle_done = ANADIG_MISC->VDDLPSR_AI400M_CTRL & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* get pre_toggle_done */ + pre_toggle_done = + ANADIG_MISC->VDDLPSR_AI400M_CTRL & + ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* get pre_toggle_done */ ANADIG_MISC->VDDLPSR_AI400M_CTRL &= ~ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK; temp = ANADIG_MISC->VDDLPSR_AI400M_CTRL; temp &= ~ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK; - temp |= (addr << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK; - ANADIG_MISC->VDDLPSR_AI400M_CTRL = temp; - ANADIG_MISC->VDDLPSR_AI400M_WDATA = wdata ; /* write ai data */ - ANADIG_MISC->VDDLPSR_AI400M_CTRL ^= ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK; /* toggle */ + temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT) & + ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK; + ANADIG_MISC->VDDLPSR_AI400M_CTRL = temp; + ANADIG_MISC->VDDLPSR_AI400M_WDATA = wdata; /* write ai data */ + ANADIG_MISC->VDDLPSR_AI400M_CTRL ^= + ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK; /* toggle */ do { - toggle_done = ANADIG_MISC->VDDLPSR_AI400M_CTRL & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* wait toggle done toggle */ + toggle_done = + ANADIG_MISC->VDDLPSR_AI400M_CTRL & + ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* wait toggle done toggle */ } while (toggle_done == pre_toggle_done); } else { - pre_toggle_done = ANADIG_MISC->VDDLPSR_AI400M_CTRL & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* get pre_toggle_done */ + pre_toggle_done = + ANADIG_MISC->VDDLPSR_AI400M_CTRL & + ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* get pre_toggle_done */ temp = ANADIG_MISC->VDDLPSR_AI400M_CTRL; temp &= ~ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK; - temp |= (1 << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_SHIFT) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK; + temp |= (1UL << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_SHIFT) & + ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK; ANADIG_MISC->VDDLPSR_AI400M_CTRL = temp; temp = ANADIG_MISC->VDDLPSR_AI400M_CTRL; temp &= ~ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK; - temp |= (addr << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK; + temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT) & + ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK; ANADIG_MISC->VDDLPSR_AI400M_CTRL = temp; - ANADIG_MISC->VDDLPSR_AI400M_CTRL ^= ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK; /* toggle */ + ANADIG_MISC->VDDLPSR_AI400M_CTRL ^= + ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK; /* toggle */ do { - toggle_done = ANADIG_MISC->VDDLPSR_AI400M_CTRL & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* wait toggle done toggle */ + toggle_done = + ANADIG_MISC->VDDLPSR_AI400M_CTRL & + ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* wait toggle done toggle */ } while (toggle_done == pre_toggle_done); rdata = ANADIG_MISC->VDDLPSR_AI400M_RDATA; /* read data */ return rdata; } break; case kAI_Itf_Temp: - if(isWrite) + if (isWrite) { ANADIG_MISC->VDDLPSR_AI_CTRL &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK; temp = ANADIG_MISC->VDDLPSR_AI_CTRL; temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK; - temp |= (addr << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK; - ANADIG_MISC->VDDLPSR_AI_CTRL = temp; - ANADIG_MISC->VDDLPSR_AI_WDATA = wdata ; /* write ai data */ - ANADIG_TEMPSENSOR->TEMPSENSOR ^= ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_MASK; /* toggle */ + temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT) & + ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK; + ANADIG_MISC->VDDLPSR_AI_CTRL = temp; + ANADIG_MISC->VDDLPSR_AI_WDATA = wdata; /* write ai data */ + ANADIG_TEMPSENSOR->TEMPSENSOR ^= ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_MASK; /* toggle */ } else { temp = ANADIG_MISC->VDDLPSR_AI_CTRL; temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK; - temp |= (1 << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK; + temp |= (1UL << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT) & + ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK; ANADIG_MISC->VDDLPSR_AI_CTRL = temp; temp = ANADIG_MISC->VDDLPSR_AI_CTRL; temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK; - temp |= (addr << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK; + temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT) & + ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK; ANADIG_MISC->VDDLPSR_AI_CTRL = temp; ANADIG_TEMPSENSOR->TEMPSENSOR ^= ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_MASK; /* toggle */ - rdata = ANADIG_MISC->VDDLPSR_AI_RDATA_TMPSNS ; /* read data */ + rdata = ANADIG_MISC->VDDLPSR_AI_RDATA_TMPSNS; /* read data */ return rdata; } break; case kAI_Itf_Bandgap: - if(isWrite) + if (isWrite) { ANADIG_MISC->VDDLPSR_AI_CTRL &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK; temp = ANADIG_MISC->VDDLPSR_AI_CTRL; temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK; - temp |= (addr << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK; - ANADIG_MISC->VDDLPSR_AI_CTRL = temp; - ANADIG_MISC->VDDLPSR_AI_WDATA = wdata ; /* write ai data */ + temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT) & + ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK; + ANADIG_MISC->VDDLPSR_AI_CTRL = temp; + ANADIG_MISC->VDDLPSR_AI_WDATA = wdata; /* write ai data */ ANADIG_PMU->PMU_REF_CTRL ^= ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_MASK; /* toggle */ } else { temp = ANADIG_MISC->VDDLPSR_AI_CTRL; temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK; - temp |= (1 << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK; + temp |= (1UL << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT) & + ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK; ANADIG_MISC->VDDLPSR_AI_CTRL = temp; temp = ANADIG_MISC->VDDLPSR_AI_CTRL; temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK; - temp |= (addr<VDDLPSR_AI_CTRL = temp; ANADIG_PMU->PMU_REF_CTRL ^= ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_MASK; /* toggle */ - rdata = ANADIG_MISC->VDDLPSR_AI_RDATA_REFTOP; /* read data */ + rdata = ANADIG_MISC->VDDLPSR_AI_RDATA_REFTOP; /* read data */ return rdata; } break; default: - assert(false); + /* This branch should never be hit. */ break; } return 0; } -void ANATOP_AI_Write(anatop_ai_itf_t itf, uint8_t addr, uint32_t wdata) +void ANATOP_AI_Write(anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata) { - ANATOP_AI_Access(itf, true, addr, wdata); + (void)ANATOP_AI_Access(itf, true, addr, wdata); } -uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, uint8_t addr) +uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, anatop_ai_reg_t addr) { uint32_t rdata; rdata = ANATOP_AI_Access(itf, false, addr, 0); return rdata; } -void ANATOP_AI_WriteWithMaskShift(anatop_ai_itf_t itf, uint8_t addr, uint32_t wdata, uint32_t mask, uint32_t shift) +void ANATOP_AI_WriteWithMaskShift( + anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata, uint32_t mask, uint32_t shift) { uint32_t rdata; rdata = ANATOP_AI_Read(itf, addr); diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_anatop_ai.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_anatop_ai.h index 2ef2bc0ecbf..12886c1e2ce 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_anatop_ai.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_anatop_ai.h @@ -22,15 +22,490 @@ typedef enum _anatop_ai_itf { - kAI_Itf_Ldo = 0, - kAI_Itf_1g = 1, - kAI_Itf_Audio = 2, - kAI_Itf_Video = 3, - kAI_Itf_400m = 4, - kAI_Itf_Temp = 5, + kAI_Itf_Ldo = 0, + kAI_Itf_1g = 1, + kAI_Itf_Audio = 2, + kAI_Itf_Video = 3, + kAI_Itf_400m = 4, + kAI_Itf_Temp = 5, kAI_Itf_Bandgap = 6, } anatop_ai_itf_t; +typedef enum _anatop_ai_reg +{ + kAI_PHY_LDO_CTRL0 = 0x0, + kAI_PHY_LDO_CTRL0_SET = 0x4, + kAI_PHY_LDO_CTRL0_CLR = 0x8, + kAI_PHY_LDO_CTRL0_TOG = 0xC, + kAI_PHY_LDO_STAT0 = 0x50, + kAI_PHY_LDO_STAT0_SET = 0x54, + kAI_PHY_LDO_STAT0_CLR = 0x58, + kAI_PHY_LDO_STAT0_TOG = 0x5C, + + kAI_BANDGAP_CTRL0 = 0x0, + kAI_BANDGAP_STAT0 = 0x50, + + kAI_RCOSC400M_CTRL0 = 0x0, + kAI_RCOSC400M_CTRL0_SET = 0x4, + kAI_RCOSC400M_CTRL0_CLR = 0x8, + kAI_RCOSC400M_CTRL0_TOG = 0xC, + kAI_RCOSC400M_CTRL1 = 0x10, + kAI_RCOSC400M_CTRL1_SET = 0x14, + kAI_RCOSC400M_CTRL1_CLR = 0x18, + kAI_RCOSC400M_CTRL1_TOG = 0x1C, + kAI_RCOSC400M_CTRL2 = 0x20, + kAI_RCOSC400M_CTRL2_SET = 0x24, + kAI_RCOSC400M_CTRL2_CLR = 0x28, + kAI_RCOSC400M_CTRL2_TOG = 0x2C, + kAI_RCOSC400M_CTRL3 = 0x30, + kAI_RCOSC400M_CTRL3_SET = 0x34, + kAI_RCOSC400M_CTRL3_CLR = 0x38, + kAI_RCOSC400M_CTRL3_TOG = 0x3C, + kAI_RCOSC400M_STAT0 = 0x50, + kAI_RCOSC400M_STAT0_SET = 0x54, + kAI_RCOSC400M_STAT0_CLR = 0x58, + kAI_RCOSC400M_STAT0_TOG = 0x5C, + kAI_RCOSC400M_STAT1 = 0x60, + kAI_RCOSC400M_STAT1_SET = 0x64, + kAI_RCOSC400M_STAT1_CLR = 0x68, + kAI_RCOSC400M_STAT1_TOG = 0x6C, + kAI_RCOSC400M_STAT2 = 0x70, + kAI_RCOSC400M_STAT2_SET = 0x74, + kAI_RCOSC400M_STAT2_CLR = 0x78, + kAI_RCOSC400M_STAT2_TOG = 0x7C, + + kAI_PLL1G_CTRL0 = 0x0, + kAI_PLL1G_CTRL0_SET = 0x4, + kAI_PLL1G_CTRL0_CLR = 0x8, + kAI_PLL1G_CTRL1 = 0x10, + kAI_PLL1G_CTRL1_SET = 0x14, + kAI_PLL1G_CTRL1_CLR = 0x18, + kAI_PLL1G_CTRL2 = 0x20, + kAI_PLL1G_CTRL2_SET = 0x24, + kAI_PLL1G_CTRL2_CLR = 0x28, + kAI_PLL1G_CTRL3 = 0x30, + kAI_PLL1G_CTRL3_SET = 0x34, + kAI_PLL1G_CTRL3_CLR = 0x38, + + kAI_PLLAUDIO_CTRL0 = 0x0, + kAI_PLLAUDIO_CTRL0_SET = 0x4, + kAI_PLLAUDIO_CTRL0_CLR = 0x8, + kAI_PLLAUDIO_CTRL1 = 0x10, + kAI_PLLAUDIO_CTRL1_SET = 0x14, + kAI_PLLAUDIO_CTRL1_CLR = 0x18, + kAI_PLLAUDIO_CTRL2 = 0x20, + kAI_PLLAUDIO_CTRL2_SET = 0x24, + kAI_PLLAUDIO_CTRL2_CLR = 0x28, + kAI_PLLAUDIO_CTRL3 = 0x30, + kAI_PLLAUDIO_CTRL3_SET = 0x34, + kAI_PLLAUDIO_CTRL3_CLR = 0x38, + + kAI_PLLVIDEO_CTRL0 = 0x0, + kAI_PLLVIDEO_CTRL0_SET = 0x4, + kAI_PLLVIDEO_CTRL0_CLR = 0x8, + kAI_PLLVIDEO_CTRL1 = 0x10, + kAI_PLLVIDEO_CTRL1_SET = 0x14, + kAI_PLLVIDEO_CTRL1_CLR = 0x18, + kAI_PLLVIDEO_CTRL2 = 0x20, + kAI_PLLVIDEO_CTRL2_SET = 0x24, + kAI_PLLVIDEO_CTRL2_CLR = 0x28, + kAI_PLLVIDEO_CTRL3 = 0x30, + kAI_PLLVIDEO_CTRL3_SET = 0x34, + kAI_PLLVIDEO_CTRL3_CLR = 0x38, +} anatop_ai_reg_t; + +/* ---------------------------------------------------------------------------- + -- AI PHY_LDO CTRL0 Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AI_Register_Masks PHY_LDO Register Masks + * @{ + */ + +/*! @name CTRL0 - CTRL0 Register */ +/*! @{ */ +#define AI_PHY_LDO_CTRL0_LINREG_EN(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_LINREG_EN_SHIFT)) & AI_PHY_LDO_CTRL0_LINREG_EN_MASK) +#define AI_PHY_LDO_CTRL0_LINREG_EN_MASK (0x1U) +#define AI_PHY_LDO_CTRL0_LINREG_EN_SHIFT (0U) + +/*! LINREG_EN - LinReg master enable + * LinReg master enable. Setting this bit will enable the regular + */ + +#define AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_SHIFT)) & AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_MASK) +#define AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_MASK (0x2U) +#define AI_PHY_LDO_CTRL0_PWRUPLOAD_DIS_SHIFT (1U) +/*! LINREG_PWRUPLOAD_DIS - LinReg power-up load disable + * 0b0..Internal pull-down enabled + * 0b1..Internal pull-down disabled + */ + +#define AI_PHY_LDO_CTRL0_LIMIT_EN(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_LIMIT_EN_SHIFT)) & AI_PHY_LDO_CTRL0_LIMIT_EN_MASK) +#define AI_PHY_LDO_CTRL0_LIMIT_EN_MASK (0x4U) +#define AI_PHY_LDO_CTRL0_LIMIT_EN_SHIFT (2U) +/*! LINREG_LIMIT_EN - LinReg current limit enable + * LinReg current-limit enable. Setting this bit will enable the + * current-limiter in the regulator + */ + +#define AI_PHY_LDO_CTRL0_OUTPUT_TRG(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_OUTPUT_TRG_SHIFT)) & AI_PHY_LDO_CTRL0_OUTPUT_TRG_MASK) +#define AI_PHY_LDO_CTRL0_OUTPUT_TRG_MASK (0x1F0U) +#define AI_PHY_LDO_CTRL0_OUTPUT_TRG_SHIFT (4U) +/*! LINREG_OUTPUT_TRG - LinReg output voltage target setting + * 0b00000..Set output voltage to x.xV + * 0b10000..Set output voltage to 1.0V + * 0b11111..Set output voltage to x.xV + */ + +#define AI_PHY_LDO_CTRL0_PHY_ISO_B(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_CTRL0_PHY_ISO_B_SHIFT)) & AI_PHY_LDO_CTRL0_PHY_ISO_B_MASK) +#define AI_PHY_LDO_CTRL0_PHY_ISO_B_MASK (0x8000U) +#define AI_PHY_LDO_CTRL0_PHY_ISO_B_SHIFT (15U) +/*! LINREG_PHY_ISO_B - Isolation control for attached PHY load + * This control bit is to be used by the system controller to isolate the + * attached PHY load when the LinReg is powered down. During a power-up + * event of the regulator it is expected that this control signal is set high + * at least 100us after the main regulator is enabled. During a power-down + * event of the regulator it is expected that this control signal is set low + * before the main regulator is disabled/power-down. + */ +/*! @} */ + +/*! @name STAT0 - STAT0 Register */ +/*! @{ */ +#define AI_PHY_LDO_STAT0_LINREG_STAT(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PHY_LDO_STAT0_LINREG_STAT_SHIFT)) & AI_PHY_LDO_STAT0_LINREG_STAT_MASK) +#define AI_PHY_LDO_STAT0_LINREG_STAT_MASK (0xFU) +#define AI_PHY_LDO_STAT0_LINREG_STAT_SHIFT (0U) + +/*! LINREG_STAT - LinReg status bits + * LinReg status bits. + */ + +/*! @} */ +/*! @} */ + +/*! + * @addtogroup AI_Register_Masks BANDGAP Register Masks + * @{ + */ + +/*! @name CTRL0 - CTRL0 Register */ +/*! @{ */ +#define AI_BANDGAP_CTRL0_REFTOP_PWD(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_PWD_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_PWD_MASK) +#define AI_BANDGAP_CTRL0_REFTOP_PWD_MASK (0x1U) +#define AI_BANDGAP_CTRL0_REFTOP_PWD_SHIFT (0U) +/*! REFTOP_PWD - This bit fully powers down the bandgap module. + * Setting this bit high will disable reference output currents and voltages from the + * bandgap and will affect functionality and validity of the voltage detectors. + */ + +#define AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_SHIFT)) & \ + AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK) +#define AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK (0x2U) +#define AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_SHIFT (1U) +/*! + * REFOP_LINREGREF_PWD - This bit powers down only the voltage reference output section of the bandgap. + * Setting this bit high will affect functionality and validity + * of the voltage detectors. + */ + +#define AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK) +#define AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK (0x4U) +#define AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT (2U) +/*! + * REFTOP_PWDVBGUP - This bit powers down the VBGUP detector of the bandgap + * without affecting any additional functionality. + */ + +#define AI_BANDGAP_CTRL0_REFTOP_LOWPOWER(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_MASK) +#define AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_MASK (0x8U) +#define AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT (3U) +/*! + * REFTOP_LOWPOWER - This bit enables the low-power operation of the + * bandgap by cutting the bias currents in half to the main amplifiers. + * This will save power but could affect the accuracy of the output voltages and currents. + */ + +#define AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_SHIFT)) & \ + AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK) +#define AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK (0x10U) +#define AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_SHIFT (4U) +/*! + * REFTOP_SELFBIASOFF - Control bit to disable the self-bias circuit in the bandgap. + * The self-bias circuit is used by the bandgap during startup. This bit should be + * set high after the bandgap has stabilized and is necessary for best noise performance + * of modules using the outputs of the bandgap. It is expected that this control bit + * be set low any time that either the bandgap is fully powered-down or the 1.8V supply is removed. + */ + +#define AI_BANDGAP_CTRL0_REFTOP_VBGADJ(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_VBGADJ_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_VBGADJ_MASK) +#define AI_BANDGAP_CTRL0_REFTOP_VBGADJ_MASK (0xE0U) +#define AI_BANDGAP_CTRL0_REFTOP_VBGADJ_SHIFT (5U) +/*! + * REFTOP_VBGADJ - These bits allow the output VBG voltage of the bandgap to be trimmed + * 000 : nominal + * 001 : +10mV + * 010 : +20mV + * 011 : +30mV + * 100 : -10mV + * 101 : -20mV + * 110 : -30mV + * 111 : -40mV + */ + +#define AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_SHIFT)) & AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_MASK) +#define AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_MASK (0x1C00U) +#define AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_SHIFT (10U) +/*! + * REFTOP_IBZTCADJ - These bits allow trimming of the ZTC bias currents from the bandgap to + * the temperature sensors. Assuming a typical process corner the expected values of output + * currents are: + * 000 : 11.5 uA + * 001 : 11.8 uA + * 010 : 12.1 uA + * 100 : 12.4 uA (Nominal expected from MX8QM tempsensor) + * 101 : 12.7 uA + * 110 : 13.0 uA + * 111 : 13.3 uA + */ + +/*! @} */ + +/*! @name STAT0 - STAT0 Register */ +/*! @{ */ +#define AI_BANDGAP_STAT0_REFTOP_VBGUP(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_BANDGAP_STAT0_REFTOP_VBGUP_SHIFT)) & AI_BANDGAP_STAT0_REFTOP_VBGUP_MASK) +#define AI_BANDGAP_STAT0_REFTOP_VBGUP_MASK (0x1U) +#define AI_BANDGAP_STAT0_REFTOP_VBGUP_SHIFT (0U) +/*! @} */ + +/*! @} */ + +/*! + * @addtogroup AI_Register_Masks RCOSC 400M Register Masks + * @{ + */ + +/*! @name CTRL0 - CTRL0 Register */ +/*! @{ */ +#define AI_RCOSC400M_CTRL0_REF_CLK_DIV(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL0_REF_CLK_DIV_SHIFT)) & AI_RCOSC400M_CTRL0_REF_CLK_DIV_MASK) +#define AI_RCOSC400M_CTRL0_REF_CLK_DIV_MASK (0x3F000000U) +#define AI_RCOSC400M_CTRL0_REF_CLK_DIV_SHIFT (24U) +/*! @} */ + +/*! @name CTRL1 - CTRL1 Register */ +/*! @{ */ +#define AI_RCOSC400M_CTRL1_HYST_MINUS(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL1_HYST_MINUS_SHIFT)) & AI_RCOSC400M_CTRL1_HYST_MINUS_MASK) +#define AI_RCOSC400M_CTRL1_HYST_MINUS_MASK (0xFU) +#define AI_RCOSC400M_CTRL1_HYST_MINUS_SHIFT (0U) + +#define AI_RCOSC400M_CTRL1_HYST_PLUS(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL1_HYST_PLUS_SHIFT)) & AI_RCOSC400M_CTRL1_HYST_PLUS_MASK) +#define AI_RCOSC400M_CTRL1_HYST_PLUS_MASK (0xF00U) +#define AI_RCOSC400M_CTRL1_HYST_PLUS_SHIFT (8U) + +#define AI_RCOSC400M_CTRL1_TARGET_COUNT(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL1_TARGET_COUNT_SHIFT)) & AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK) +#define AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK (0xFFFF0000U) +#define AI_RCOSC400M_CTRL1_TARGET_COUNT_SHIFT (16U) +/*! @} */ + +/*! @name CTRL2 - CTRL2 Register */ +/*! @{ */ +#define AI_RCOSC400M_CTRL2_TUNE_BYP(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_TUNE_BYP_SHIFT)) & AI_RCOSC400M_CTRL2_TUNE_BYP_MASK) +#define AI_RCOSC400M_CTRL2_TUNE_BYP_MASK (0x400U) +#define AI_RCOSC400M_CTRL2_TUNE_BYP_SHIFT (10U) + +#define AI_RCOSC400M_CTRL2_TUNE_EN(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_TUNE_EN_SHIFT)) & AI_RCOSC400M_CTRL2_TUNE_EN_MASK) +#define AI_RCOSC400M_CTRL2_TUNE_EN_MASK (0x1000U) +#define AI_RCOSC400M_CTRL2_TUNE_EN_SHIFT (12U) + +#define AI_RCOSC400M_CTRL2_TUNE_START(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_TUNE_START_SHIFT)) & AI_RCOSC400M_CTRL2_TUNE_START_MASK) +#define AI_RCOSC400M_CTRL2_TUNE_START_MASK (0x4000U) +#define AI_RCOSC400M_CTRL2_TUNE_START_SHIFT (14U) + +#define AI_RCOSC400M_CTRL2_OSC_TUNE_VAL(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK) +#define AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK (0xFF000000U) +#define AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_SHIFT (24U) +/*! @} */ + +/*! @name CTRL3 - CTRL3 Register */ +/*! @{ */ +#define AI_RCOSC400M_CTRL3_CLR_ERR(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_CLR_ERR_SHIFT)) & AI_RCOSC400M_CTRL3_CLR_ERR_MASK) +#define AI_RCOSC400M_CTRL3_CLR_ERR_MASK (0x1U) +#define AI_RCOSC400M_CTRL3_CLR_ERR_SHIFT (0U) + +#define AI_RCOSC400M_CTRL3_EN_1M_CLK(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_EN_1M_CLK_SHIFT)) & AI_RCOSC400M_CTRL3_EN_1M_CLK_MASK) +#define AI_RCOSC400M_CTRL3_EN_1M_CLK_MASK (0x100U) +#define AI_RCOSC400M_CTRL3_EN_1M_CLK_SHIFT (8U) + +#define AI_RCOSC400M_CTRL3_MUX_1M_CLK(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_MUX_1M_CLK_SHIFT)) & AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK) +#define AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK (0x400U) +#define AI_RCOSC400M_CTRL3_MUX_1M_CLK_SHIFT (10U) + +#define AI_RCOSC400M_CTRL3_COUNT_1M_CLK(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_CTRL3_COUNT_1M_CLK_SHIFT)) & AI_RCOSC400M_CTRL3_COUNT_1M_CLK_MASK) +#define AI_RCOSC400M_CTRL3_COUNT_1M_CLK_MASK (0xFFFF0000U) +#define AI_RCOSC400M_CTRL3_COUNT_1M_CLK_SHIFT (16U) +/*! @} */ + +/*! @name STAT0 - STAT0 Register */ +/*! @{ */ +#define AI_RCOSC400M_STAT0_CLK1M_ERR(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_STAT0_CLK1M_ERR_SHIFT)) & AI_RCOSC400M_STAT0_CLK1M_ERR_MASK) +#define AI_RCOSC400M_STAT0_CLK1M_ERR_MASK (0x1U) +#define AI_RCOSC400M_STAT0_CLK1M_ERR_SHIFT (0U) +/*! @} */ + +/*! @name STAT1 - STAT1 Register */ +/*! @{ */ +#define AI_RCOSC400M_STAT1_CURR_COUNT_VAL(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_STAT1_CURR_COUNT_VAL_SHIFT)) & AI_RCOSC400M_STAT1_CURR_COUNT_VAL_MASK) +#define AI_RCOSC400M_STAT1_CURR_COUNT_VAL_MASK (0xFFFF0000U) +#define AI_RCOSC400M_STAT1_CURR_COUNT_VAL_SHIFT (16U) +/*! @} */ + +/*! @name STAT2 - STAT2 Register */ +/*! @{ */ +#define AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT)) & \ + AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL_MASK) +#define AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL_MASK (0xFF000000U) +#define AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT (24U) +/*! @} */ + +/*! + * @addtogroup AI_Register_Masks PLL 1G Register Masks + * @{ + */ + +/*! @name CTRL0 - CTRL0 Register */ +/*! @{ */ +#define AI_PLL1G_CTRL0_HOLD_RING_OFF(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_HOLD_RING_OFF_SHIFT)) & AI_PLL1G_CTRL0_HOLD_RING_OFF_MASK) +#define AI_PLL1G_CTRL0_HOLD_RING_OFF_MASK (0x2000UL) +#define AI_PLL1G_CTRL0_HOLD_RING_OFF_SHIFT (13U) + +#define AI_PLL1G_CTRL0_POWER_UP(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_POWER_UP_SHIFT)) & AI_PLL1G_CTRL0_POWER_UP_MASK) +#define AI_PLL1G_CTRL0_POWER_UP_MASK (0x4000UL) +#define AI_PLL1G_CTRL0_POWER_UP_SHIFT (14U) + +#define AI_PLL1G_CTRL0_ENABLE(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_ENABLE_SHIFT)) & AI_PLL1G_CTRL0_ENABLE_MASK) +#define AI_PLL1G_CTRL0_ENABLE_MASK (0x8000UL) +#define AI_PLL1G_CTRL0_ENABLE_SHIFT (15U) + +#define AI_PLL1G_CTRL0_BYPASS(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_BYPASS_SHIFT)) & AI_PLL1G_CTRL0_BYPASS_MASK) +#define AI_PLL1G_CTRL0_BYPASS_MASK (0x10000UL) +#define AI_PLL1G_CTRL0_BYPASS_SHIFT (16U) + +#define AI_PLL1G_CTRL0_PLL_REG_EN(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PLL1G_CTRL0_PLL_REG_EN_SHIFT)) & AI_PLL1G_CTRL0_PLL_REG_EN_MASK) +#define AI_PLL1G_CTRL0_PLL_REG_EN_MASK (0x400000UL) +#define AI_PLL1G_CTRL0_PLL_REG_EN_SHIFT (22U) +/*! @} */ +/*! + * @} + */ + +/*! + * @addtogroup AI_Register_Masks PLL AUDIO Register Masks + * @{ + */ + +/*! @name CTRL0 - CTRL0 Register */ +/*! @{ */ +#define AI_PLLAUDIO_CTRL0_HOLD_RING_OFF(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_HOLD_RING_OFF_SHIFT)) & AI_PLLAUDIO_CTRL0_HOLD_RING_OFF_MASK) +#define AI_PLLAUDIO_CTRL0_HOLD_RING_OFF_MASK (0x2000UL) +#define AI_PLLAUDIO_CTRL0_HOLD_RING_OFF_SHIFT (13U) + +#define AI_PLLAUDIO_CTRL0_POWER_UP(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_POWER_UP_SHIFT)) & AI_PLLAUDIO_CTRL0_POWER_UP_MASK) +#define AI_PLLAUDIO_CTRL0_POWER_UP_MASK (0x4000UL) +#define AI_PLLAUDIO_CTRL0_POWER_UP_SHIFT (14U) + +#define AI_PLLAUDIO_CTRL0_ENABLE(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_ENABLE_SHIFT)) & AI_PLLAUDIO_CTRL0_ENABLE_MASK) +#define AI_PLLAUDIO_CTRL0_ENABLE_MASK (0x8000UL) +#define AI_PLLAUDIO_CTRL0_ENABLE_SHIFT (15U) + +#define AI_PLLAUDIO_CTRL0_BYPASS(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_BYPASS_SHIFT)) & AI_PLLAUDIO_CTRL0_BYPASS_MASK) +#define AI_PLLAUDIO_CTRL0_BYPASS_MASK (0x10000UL) +#define AI_PLLAUDIO_CTRL0_BYPASS_SHIFT (16U) + +#define AI_PLLAUDIO_CTRL0_PLL_REG_EN(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PLLAUDIO_CTRL0_PLL_REG_EN_SHIFT)) & AI_PLLAUDIO_CTRL0_PLL_REG_EN_MASK) +#define AI_PLLAUDIO_CTRL0_PLL_REG_EN_MASK (0x400000UL) +#define AI_PLLAUDIO_CTRL0_PLL_REG_EN_SHIFT (22U) +/*! @} */ +/*! + * @} + */ + +/*! + * @addtogroup AI_Register_Masks PLL VIDEO Register Masks + * @{ + */ + +/*! @name CTRL0 - CTRL0 Register */ +/*! @{ */ +#define AI_PLLVIDEO_CTRL0_HOLD_RING_OFF(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_HOLD_RING_OFF_SHIFT)) & AI_PLLVIDEO_CTRL0_HOLD_RING_OFF_MASK) +#define AI_PLLVIDEO_CTRL0_HOLD_RING_OFF_MASK (0x2000UL) +#define AI_PLLVIDEO_CTRL0_HOLD_RING_OFF_SHIFT (13U) + +#define AI_PLLVIDEO_CTRL0_POWER_UP(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_POWER_UP_SHIFT)) & AI_PLLVIDEO_CTRL0_POWER_UP_MASK) +#define AI_PLLVIDEO_CTRL0_POWER_UP_MASK (0x4000UL) +#define AI_PLLVIDEO_CTRL0_POWER_UP_SHIFT (14U) + +#define AI_PLLVIDEO_CTRL0_ENABLE(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_ENABLE_SHIFT)) & AI_PLLVIDEO_CTRL0_ENABLE_MASK) +#define AI_PLLVIDEO_CTRL0_ENABLE_MASK (0x8000UL) +#define AI_PLLVIDEO_CTRL0_ENABLE_SHIFT (15U) + +#define AI_PLLVIDEO_CTRL0_BYPASS(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_BYPASS_SHIFT)) & AI_PLLVIDEO_CTRL0_BYPASS_MASK) +#define AI_PLLVIDEO_CTRL0_BYPASS_MASK (0x10000UL) +#define AI_PLLVIDEO_CTRL0_BYPASS_SHIFT (16U) + +#define AI_PLLVIDEO_CTRL0_PLL_REG_EN(x) \ + (((uint32_t)(((uint32_t)(x)) << AI_PLLVIDEO_CTRL0_PLL_REG_EN_SHIFT)) & AI_PLLVIDEO_CTRL0_PLL_REG_EN_MASK) +#define AI_PLLVIDEO_CTRL0_PLL_REG_EN_MASK (0x400000UL) +#define AI_PLLVIDEO_CTRL0_PLL_REG_EN_SHIFT (22U) +/*! @} */ +/*! + * @} + */ + +/*! @} */ + /******************************************************************************* * API ******************************************************************************/ @@ -39,7 +514,6 @@ typedef enum _anatop_ai_itf extern "C" { #endif /* __cplusplus */ - /*! * @brief AI interface access * @@ -49,7 +523,7 @@ extern "C" { * @param wdata data to be set * */ -uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, uint8_t addr, uint32_t wdata); +uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, anatop_ai_reg_t addr, uint32_t wdata); /*! * @brief AI interface writing @@ -59,7 +533,7 @@ uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, uint8_t addr, uint3 * @param wdata data to be set * */ -void ANATOP_AI_Write(anatop_ai_itf_t itf, uint8_t addr, uint32_t wdata); +void ANATOP_AI_Write(anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata); /*! * @brief AI interface reading @@ -69,7 +543,7 @@ void ANATOP_AI_Write(anatop_ai_itf_t itf, uint8_t addr, uint32_t wdata); * @return data read * */ -uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, uint8_t addr); +uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, anatop_ai_reg_t addr); /*! * @brief AI interface write with mask and shift @@ -81,7 +555,8 @@ uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, uint8_t addr); * @param shift bit field shift * */ -void ANATOP_AI_WriteWithMaskShift(anatop_ai_itf_t itf, uint8_t addr, uint32_t wdata, uint32_t mask, uint32_t shift); +void ANATOP_AI_WriteWithMaskShift( + anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata, uint32_t mask, uint32_t shift); /* @} */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_clock.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_clock.c index aead7b1e120..9fcc2f13ad6 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_clock.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_clock.c @@ -6,7 +6,7 @@ */ #include "fsl_clock.h" -#include "fsl_anatop.h" +#include "fsl_pmu.h" #include "fsl_anatop_ai.h" /* Component ID definition, used by tools. */ #ifndef FSL_COMPONENT_ID @@ -21,7 +21,7 @@ achieve better performance, it is depend on the IDE Floating point settings, if in IDE, clock_64b_t will switch to double type automatically. only support IAR and MDK here */ #if __FPU_USED -#if ((defined(__ICCARM__)) || (defined(__GNUC__))) +#if (defined(__ICCARM__)) #if (__ARMVFP__ >= __ARMFPV5__) && \ (__ARM_FP == 0xE) /*0xe implies support for half, single and double precision operations*/ @@ -30,6 +30,14 @@ typedef double clock_64b_t; typedef uint64_t clock_64b_t; #endif +#elif (defined(__GNUC__)) + +#if (__ARM_FP == 0xE) /*0xe implies support for half, single and double precision operations*/ +typedef double clock_64b_t; +#else +typedef uint64_t clock_64b_t; +#endif + #elif defined(__CC_ARM) || defined(__ARMCC_VERSION) #if defined __TARGET_FPU_FPV5_D16 @@ -46,6 +54,28 @@ typedef uint64_t clock_64b_t; typedef uint64_t clock_64b_t; #endif +#define PLL_AI_CTRL0_REG kAI_PLL1G_CTRL0 +#define PLL_AI_CTRL0_SET_REG kAI_PLL1G_CTRL0_SET +#define PLL_AI_CTRL0_CLR_REG kAI_PLL1G_CTRL0_CLR +#define PLL_AI_CTRL1_REG kAI_PLL1G_CTRL1 +#define PLL_AI_CTRL1_SET_REG kAI_PLL1G_CTRL1_SET +#define PLL_AI_CTRL1_CLR_REG kAI_PLL1G_CTRL1_CLR +#define PLL_AI_CTRL2_REG kAI_PLL1G_CTRL2 +#define PLL_AI_CTRL2_SET_REG kAI_PLL1G_CTRL2_SET +#define PLL_AI_CTRL2_CLR_REG kAI_PLL1G_CTRL2_CLR +#define PLL_AI_CTRL3_REG kAI_PLL1G_CTRL3 +#define PLL_AI_CTRL3_SET_REG kAI_PLL1G_CTRL3_SET +#define PLL_AI_CTRL3_CLR_REG kAI_PLL1G_CTRL3_CLR + +#define PLL_AI_CTRL0_HOLD_RING_OFF_MASK AI_PLL1G_CTRL0_HOLD_RING_OFF_MASK + +#define PLL_AI_CTRL0_POWER_UP_MASK AI_PLL1G_CTRL0_POWER_UP_MASK + +#define PLL_AI_CTRL0_ENABLE_MASK AI_PLL1G_CTRL0_ENABLE_MASK + +#define PLL_AI_CTRL0_BYPASS_MASK AI_PLL1G_CTRL0_BYPASS_MASK + +#define PLL_AI_CTRL0_PLL_REG_EN_MASK AI_PLL1G_CTRL0_PLL_REG_EN_MASK /******************************************************************************* * Variables ******************************************************************************/ @@ -53,7 +83,30 @@ typedef uint64_t clock_64b_t; /******************************************************************************* * Prototypes ******************************************************************************/ - +static void ANATOP_PllSetPower(anatop_ai_itf_t itf, bool enable); +static void ANATOP_PllBypass(anatop_ai_itf_t itf, bool bypass); +static void ANATOP_PllEnablePllReg(anatop_ai_itf_t itf, bool enable); +static void ANATOP_PllHoldRingOff(anatop_ai_itf_t itf, bool off); +static void ANATOP_PllToggleHoldRingOff(anatop_ai_itf_t itf, uint32_t delay_us); +static void ANATOP_PllEnableClk(anatop_ai_itf_t itf, bool enable); +static void ANATOP_PllConfigure(anatop_ai_itf_t itf, + uint8_t div, + uint32_t numer, + uint8_t post_div, + uint32_t denom, + const clock_pll_ss_config_t *ss); +static void ANATOP_AudioPllGate(bool enable); +static void ANATOP_AudioPllSwEnClk(bool enable); +static void ANATOP_VideoPllGate(bool enable); +static void ANATOP_VideoPllSwEnClk(bool enable); +static void ANATOP_SysPll1Gate(bool enable); +static void ANATOP_SysPll1Div2En(bool enable); +static void ANATOP_SysPll1Div5En(bool enable); +static void ANATOP_SysPll1SwEnClk(bool enable); +static void ANATOP_SysPll1WaitStable(void); +#ifndef GET_FREQ_FROM_OBS +static uint32_t CLOCK_GetAvPllFreq(clock_pll_t pll); +#endif /******************************************************************************* * Code ******************************************************************************/ @@ -63,188 +116,205 @@ typedef uint64_t clock_64b_t; void CLOCK_InitArmPll(const clock_arm_pll_config_t *config) { - assert((config->loopDivider <= ARM_PLL_DIV_SEL_MAX) && (config->loopDivider >= ARM_PLL_DIV_SEL_MIN)); + assert((config->loopDivider <= (uint32_t)ARM_PLL_DIV_SEL_MAX) && + (config->loopDivider >= (uint32_t)ARM_PLL_DIV_SEL_MIN)); uint32_t reg; - if ((ANADIG_PLL->PLL_ARM_CTRL & (ANADIG_PLL_PLL_ARM_CTRL_POWERUP_MASK)) && - ((ANADIG_PLL->PLL_ARM_CTRL & (ANADIG_PLL_PLL_ARM_CTRL_DIV_SELECT(config->loopDivider))) == - (ANADIG_PLL_PLL_ARM_CTRL_DIV_SELECT(config->loopDivider))) && - ((ANADIG_PLL->PLL_ARM_CTRL & (ANADIG_PLL_PLL_ARM_CTRL_POST_DIV_SEL(config->postDivider))) == - (ANADIG_PLL_PLL_ARM_CTRL_POST_DIV_SEL(config->postDivider)))) + if (((ANADIG_PLL->ARM_PLL_CTRL & (ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK)) != 0UL) && + ((ANADIG_PLL->ARM_PLL_CTRL & (ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT(config->loopDivider))) == + (ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT(config->loopDivider))) && + ((ANADIG_PLL->ARM_PLL_CTRL & (ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL(config->postDivider))) == + (ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL(config->postDivider)))) { /* no need to reconfigure the PLL if all the configuration is the same */ - if (!(ANADIG_PLL->PLL_ARM_CTRL & ANADIG_PLL_PLL_ARM_CTRL_ENABLE_CLK_MASK)) + if ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK) == 0UL) { - ANADIG_PLL->PLL_ARM_CTRL |= ANADIG_PLL_PLL_ARM_CTRL_ENABLE_CLK_MASK; + ANADIG_PLL->ARM_PLL_CTRL |= ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK; } - if ((ANADIG_PLL->PLL_ARM_CTRL & ANADIG_PLL_PLL_ARM_CTRL_PLL_ARM_GATE_MASK)) + if ((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK) != 0UL) { - ANADIG_PLL->PLL_ARM_CTRL &= ~ANADIG_PLL_PLL_ARM_CTRL_PLL_ARM_GATE_MASK; + ANADIG_PLL->ARM_PLL_CTRL &= ~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK; } return; } - ANATOP_EnablePllLdo(); + PMU_StaticEnablePllLdo(ANADIG_PMU); - reg = ANADIG_PLL->PLL_ARM_CTRL & (~ANADIG_PLL_PLL_ARM_CTRL_PLL_ARM_STABLE_MASK); - if (reg & (ANADIG_PLL_PLL_ARM_CTRL_POWERUP_MASK | ANADIG_PLL_PLL_ARM_CTRL_ENABLE_CLK_MASK)) + reg = ANADIG_PLL->ARM_PLL_CTRL & (~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK); + if ((reg & (ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK | ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK)) != 0UL) { /* Power down the PLL. */ - reg &= ~(ANADIG_PLL_PLL_ARM_CTRL_POWERUP_MASK | ANADIG_PLL_PLL_ARM_CTRL_ENABLE_CLK_MASK); - reg |= ANADIG_PLL_PLL_ARM_CTRL_PLL_ARM_GATE_MASK; - ANADIG_PLL->PLL_ARM_CTRL = reg; + reg &= ~(ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK | ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK); + reg |= ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK; + ANADIG_PLL->ARM_PLL_CTRL = reg; } /* Set the configuration. */ - reg &= ~(ANADIG_PLL_PLL_ARM_CTRL_DIV_SELECT_MASK | ANADIG_PLL_PLL_ARM_CTRL_POST_DIV_SEL_MASK); - reg |= (ANADIG_PLL_PLL_ARM_CTRL_DIV_SELECT(config->loopDivider) | - ANADIG_PLL_PLL_ARM_CTRL_POST_DIV_SEL(config->postDivider)) | - ANADIG_PLL_PLL_ARM_CTRL_PLL_ARM_GATE_MASK | ANADIG_PLL_PLL_ARM_CTRL_POWERUP_MASK; - ANADIG_PLL->PLL_ARM_CTRL = reg; + reg &= ~(ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK | ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK); + reg |= (ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT(config->loopDivider) | + ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL(config->postDivider)) | + ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK | ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK; + ANADIG_PLL->ARM_PLL_CTRL = reg; __DSB(); __ISB(); SDK_DelayAtLeastUs(30, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* Wait for the PLL stable, */ - while (0U == (ANADIG_PLL->PLL_ARM_CTRL & ANADIG_PLL_PLL_ARM_CTRL_PLL_ARM_STABLE_MASK)) + while (0U == (ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK)) { } /* Enable and ungate the clock. */ - reg |= ANADIG_PLL_PLL_ARM_CTRL_ENABLE_CLK_MASK; - reg &= ~ANADIG_PLL_PLL_ARM_CTRL_PLL_ARM_GATE_MASK; - ANADIG_PLL->PLL_ARM_CTRL = reg; + reg |= ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK; + reg &= ~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK; + ANADIG_PLL->ARM_PLL_CTRL = reg; } void CLOCK_DeinitArmPll(void) { - uint32_t reg = ANADIG_PLL->PLL_ARM_CTRL & (~ANADIG_PLL_PLL_ARM_CTRL_PLL_ARM_STABLE_MASK); + uint32_t reg = ANADIG_PLL->ARM_PLL_CTRL & (~ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK); - reg &= ~(ANADIG_PLL_PLL_ARM_CTRL_POWERUP_MASK | ANADIG_PLL_PLL_ARM_CTRL_ENABLE_CLK_MASK); - reg |= ANADIG_PLL_PLL_ARM_CTRL_PLL_ARM_GATE_MASK; - ANADIG_PLL->PLL_ARM_CTRL = reg; + reg &= ~(ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK | ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK); + reg |= ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK; + ANADIG_PLL->ARM_PLL_CTRL = reg; +} + +void CLOCK_CalcPllSpreadSpectrum(uint32_t factor, uint32_t range, uint32_t mod, clock_pll_ss_config_t *ss) +{ + assert(ss != NULL); + + ss->stop = factor * range / XTAL_FREQ; + ss->step = (mod << 1) * ss->stop / XTAL_FREQ; } -#define SYS_PLL2_DIV_SEL_MIN 54 -#define SYS_PLL2_DIV_SEL_MAX 108 /* 528PLL */ -void CLOCK_InitSysPll2(const clock_sys_pll_config_t *config) +void CLOCK_InitSysPll2(const clock_sys_pll2_config_t *config) { uint32_t reg; - if ((ANADIG_PLL->PLL_528_CTRL & ANADIG_PLL_PLL_528_CTRL_POWERUP_MASK) && - ((ANADIG_PLL->PLL_528_MFN == config->mfn) && (ANADIG_PLL->PLL_528_MFI == config->mfi))) + if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK)) { - /* no need to reconfigure the PLL if all the configuration is the same */ - if (!(ANADIG_PLL->PLL_528_CTRL & ANADIG_PLL_PLL_528_CTRL_ENABLE_CLK_MASK)) + if ((config == NULL) || + ((0UL == (ANADIG_PLL->SYS_PLL2_SS & ANADIG_PLL_SYS_PLL2_SS_ENABLE_MASK)) && (!config->ssEnable)) || + ((ANADIG_PLL_SYS_PLL2_SS_ENABLE(config->ssEnable) | ANADIG_PLL_SYS_PLL2_SS_STOP(config->ss->stop) | + ANADIG_PLL_SYS_PLL2_SS_STEP(config->ss->step)) == ANADIG_PLL->SYS_PLL2_SS)) { - ANADIG_PLL->PLL_528_CTRL |= ANADIG_PLL_PLL_528_CTRL_ENABLE_CLK_MASK; - } + /* no need to reconfigure the PLL if all the configuration is the same */ + if (0UL == (ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK)) + { + ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK; + } - if ((ANADIG_PLL->PLL_528_CTRL & ANADIG_PLL_PLL_528_CTRL_PLL_528_GATE_MASK)) - { - ANADIG_PLL->PLL_528_CTRL &= ~ANADIG_PLL_PLL_528_CTRL_PLL_528_GATE_MASK; + if ((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK)) + { + ANADIG_PLL->SYS_PLL2_CTRL &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK; + } + return; } - return; } - ANATOP_EnablePllLdo(); + PMU_StaticEnablePllLdo(ANADIG_PMU); /* Gate all PFDs */ - ANADIG_PLL->PLL_528_PFD |= - ANADIG_PLL_PLL_528_PFD_PFD0_DIV1_CLKGATE(1) | ANADIG_PLL_PLL_528_PFD_PFD1_DIV1_CLKGATE(1) | - ANADIG_PLL_PLL_528_PFD_PFD2_DIV1_CLKGATE(1) | ANADIG_PLL_PLL_528_PFD_PFD3_DIV1_CLKGATE(1); + ANADIG_PLL->SYS_PLL2_PFD |= + ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE(1) | ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE(1) | + ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE(1) | ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE(1); - reg = ANADIG_PLL->PLL_528_CTRL; - if (reg & (ANADIG_PLL_PLL_528_CTRL_POWERUP_MASK | ANADIG_PLL_PLL_528_CTRL_ENABLE_CLK_MASK)) + reg = ANADIG_PLL->SYS_PLL2_CTRL; + if ((reg & (ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK | ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK)) != 0UL) { /* Power down the PLL. */ - reg &= ~(ANADIG_PLL_PLL_528_CTRL_POWERUP_MASK | ANADIG_PLL_PLL_528_CTRL_ENABLE_CLK_MASK); - reg |= ANADIG_PLL_PLL_528_CTRL_PLL_528_GATE_MASK; - ANADIG_PLL->PLL_528_CTRL = reg; + reg &= ~(ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK | ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK); + reg |= ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK; + ANADIG_PLL->SYS_PLL2_CTRL = reg; } /* Config PLL */ - ANADIG_PLL->PLL_528_MFD = 0x0FFFFFFFUL; - ANADIG_PLL->PLL_528_MFN = config->mfn; - ANADIG_PLL->PLL_528_MFI = config->mfi; + if ((config != NULL) && (config->ssEnable) && (config->ss != NULL)) + { + ANADIG_PLL->SYS_PLL2_MFD = ANADIG_PLL_SYS_PLL2_MFD_MFD(config->mfd); + ANADIG_PLL->SYS_PLL2_SS = (ANADIG_PLL_SYS_PLL2_SS_ENABLE_MASK | ANADIG_PLL_SYS_PLL2_SS_STOP(config->ss->stop) | + ANADIG_PLL_SYS_PLL2_SS_STEP(config->ss->step)); + } /* REG_EN = 1, GATE = 1, DIV_SEL = 0, POWERUP = 0 */ - reg = ANADIG_PLL_PLL_528_CTRL_PLL_REG_EN(1) | ANADIG_PLL_PLL_528_CTRL_PLL_528_GATE(1); - ANADIG_PLL->PLL_528_CTRL = reg; + reg = ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN(1) | ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE(1); + ANADIG_PLL->SYS_PLL2_CTRL = reg; /* Wait until LDO is stable */ SDK_DelayAtLeastUs(30, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* REG_EN = 1, GATE = 1, DIV_SEL = 0, POWERUP = 1, HOLDRING_OFF = 1 */ - reg |= ANADIG_PLL_PLL_528_CTRL_POWERUP(1) | ANADIG_PLL_PLL_528_CTRL_HOLD_RING_OFF_MASK; - ANADIG_PLL->PLL_528_CTRL = reg; + reg |= ANADIG_PLL_SYS_PLL2_CTRL_POWERUP(1) | ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_MASK; + ANADIG_PLL->SYS_PLL2_CTRL = reg; SDK_DelayAtLeastUs(250, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* REG_EN = 1, GATE = 1, DIV_SEL = 0, POWERUP = 1, HOLDRING_OFF = 0 */ - reg &= ~ANADIG_PLL_PLL_528_CTRL_HOLD_RING_OFF_MASK; - ANADIG_PLL->PLL_528_CTRL = reg; + reg &= ~ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_MASK; + ANADIG_PLL->SYS_PLL2_CTRL = reg; /* Wait for PLL stable */ - while (ANADIG_PLL_PLL_528_CTRL_PLL_528_STABLE_MASK != - (ANADIG_PLL->PLL_528_CTRL & ANADIG_PLL_PLL_528_CTRL_PLL_528_STABLE_MASK)) + while (ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_MASK != + (ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_MASK)) { } /* REG_EN = 1, GATE = 1, DIV_SEL = 0, POWERUP = 1, HOLDRING_OFF = 0, CLK = 1*/ - reg |= ANADIG_PLL_PLL_528_CTRL_ENABLE_CLK_MASK; - ANADIG_PLL->PLL_528_CTRL = reg; + reg |= ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK; + ANADIG_PLL->SYS_PLL2_CTRL = reg; /* REG_EN = 1, GATE = 0, DIV_SEL = 0, POWERUP = 1, HOLDRING_OFF = 0, CLK = 1*/ - reg &= ~ANADIG_PLL_PLL_528_CTRL_PLL_528_GATE_MASK; - ANADIG_PLL->PLL_528_CTRL = reg; - ANADIG_PLL->PLL_528_PFD &= - ~(ANADIG_PLL_PLL_528_PFD_PFD0_DIV1_CLKGATE(1) | ANADIG_PLL_PLL_528_PFD_PFD1_DIV1_CLKGATE(1) | - ANADIG_PLL_PLL_528_PFD_PFD2_DIV1_CLKGATE(1) | ANADIG_PLL_PLL_528_PFD_PFD3_DIV1_CLKGATE(1)); + reg &= ~ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK; + ANADIG_PLL->SYS_PLL2_CTRL = reg; + ANADIG_PLL->SYS_PLL2_PFD &= + ~(ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE(1) | ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE(1) | + ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE(1) | ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE(1)); } void CLOCK_DeinitSysPll2(void) { - ANADIG_PLL->PLL_528_PFD |= - ANADIG_PLL_PLL_528_PFD_PFD0_DIV1_CLKGATE(1) | ANADIG_PLL_PLL_528_PFD_PFD1_DIV1_CLKGATE(1) | - ANADIG_PLL_PLL_528_PFD_PFD2_DIV1_CLKGATE(1) | ANADIG_PLL_PLL_528_PFD_PFD3_DIV1_CLKGATE(1); + ANADIG_PLL->SYS_PLL2_PFD |= + ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE(1) | ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE(1) | + ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE(1) | ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE(1); + + ANADIG_PLL->SYS_PLL2_CTRL |= ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK; + ANADIG_PLL->SYS_PLL2_CTRL &= ~(ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK | ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK | + ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_MASK); - ANADIG_PLL->PLL_528_CTRL |= ANADIG_PLL_PLL_528_CTRL_PLL_528_GATE_MASK; - ANADIG_PLL->PLL_528_CTRL &= ~(ANADIG_PLL_PLL_528_CTRL_ENABLE_CLK_MASK | ANADIG_PLL_PLL_528_CTRL_POWERUP_MASK | - ANADIG_PLL_PLL_528_CTRL_PLL_REG_EN_MASK); + ANADIG_PLL->SYS_PLL2_SS &= ~ANADIG_PLL_SYS_PLL2_SS_ENABLE_MASK; } -#define PFD_FRAC_MIN 12 -#define PFD_FRAC_MAX 35 +#define PFD_FRAC_MIN 12U +#define PFD_FRAC_MAX 35U void CLOCK_InitPfd(clock_pll_t pll, clock_pfd_t pfd, uint8_t frac) { - volatile uint32_t *pfdCtrl = 0, *pfdUpdate = 0, stable; + volatile uint32_t *pfdCtrl = NULL, *pfdUpdate = NULL, stable; - assert(frac <= PFD_FRAC_MAX && frac >= PFD_FRAC_MIN); + assert(frac <= (uint8_t)PFD_FRAC_MAX && frac >= (uint8_t)PFD_FRAC_MIN); switch (pll) { case kCLOCK_PllSys2: - pfdCtrl = &ANADIG_PLL->PLL_528_PFD; - pfdUpdate = &ANADIG_PLL->PLL_528_UPDATE; + pfdCtrl = &ANADIG_PLL->SYS_PLL2_PFD; + pfdUpdate = &ANADIG_PLL->SYS_PLL2_UPDATE; break; case kCLOCK_PllSys3: - pfdCtrl = &ANADIG_PLL->PLL_480_PFD; - pfdUpdate = &ANADIG_PLL->PLL_480_UPDATE; + pfdCtrl = &ANADIG_PLL->SYS_PLL3_PFD; + pfdUpdate = &ANADIG_PLL->SYS_PLL3_UPDATE; break; default: assert(false); break; } - stable = *pfdCtrl & (ANADIG_PLL_PLL_528_PFD_PFD0_STABLE_MASK << (8 * (uint32_t)pfd)); - *pfdCtrl |= (ANADIG_PLL_PLL_528_PFD_PFD0_DIV1_CLKGATE_MASK << (8 * (uint32_t)pfd)); + stable = *pfdCtrl & ((uint32_t)ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_MASK << (8UL * (uint32_t)pfd)); + *pfdCtrl |= ((uint32_t)ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_MASK << (8UL * (uint32_t)pfd)); /* all pfds support to be updated on-the-fly after corresponding PLL is stable */ - *pfdCtrl &= ~(ANADIG_PLL_PLL_528_PFD_PFD0_FRAC_MASK << (8 * (uint32_t)pfd)); - *pfdCtrl |= (ANADIG_PLL_PLL_528_PFD_PFD0_FRAC(frac) << (8 * (uint32_t)pfd)); + *pfdCtrl &= ~((uint32_t)ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_MASK << (8UL * (uint32_t)pfd)); + *pfdCtrl |= (ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC(frac) << (8UL * (uint32_t)pfd)); - *pfdUpdate ^= (ANADIG_PLL_PLL_528_UPDATE_PFD0_UPDATE_MASK << (uint32_t)pfd); - *pfdCtrl &= ~(ANADIG_PLL_PLL_528_PFD_PFD0_DIV1_CLKGATE_MASK << (8 * (uint32_t)pfd)); + *pfdUpdate ^= ((uint32_t)ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_MASK << (uint32_t)pfd); + *pfdCtrl &= ~((uint32_t)ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_MASK << (8UL * (uint32_t)pfd)); /* Wait for stablizing */ - while (stable == (*pfdCtrl & (ANADIG_PLL_PLL_528_PFD_PFD0_STABLE_MASK << (8 * (uint32_t)pfd)))) + while (stable == (*pfdCtrl & ((uint32_t)ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_MASK << (8UL * (uint32_t)pfd)))) { } } @@ -253,41 +323,43 @@ void CLOCK_InitPfd(clock_pll_t pll, clock_pfd_t pfd, uint8_t frac) uint32_t CLOCK_GetPfdFreq(clock_pll_t pll, clock_pfd_t pfd) { uint32_t pllFreq = 0, frac = 0; - assert((pll == kCLOCK_PllSys2) || (pll == kCLOCK_PllSys3)); + assert((pll == kCLOCK_PllSys2) || (pll == kCLOCK_PllSys3)); switch (pll) { case kCLOCK_PllSys2: - frac = (ANADIG_PLL->PLL_528_PFD & (ANADIG_PLL_PLL_528_PFD_PFD0_FRAC_MASK << (8 * (uint32_t)pfd))); - pllFreq = SYS_PLL2_FREQ; + frac = (ANADIG_PLL->SYS_PLL2_PFD & + ((uint32_t)ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_MASK << (8UL * (uint32_t)pfd))); + pllFreq = (uint32_t)SYS_PLL2_FREQ; break; case kCLOCK_PllSys3: - frac = (ANADIG_PLL->PLL_480_PFD & (ANADIG_PLL_PLL_480_PFD_PFD0_FRAC_MASK << (8 * (uint32_t)pfd))); - pllFreq = SYS_PLL3_FREQ; + frac = (ANADIG_PLL->SYS_PLL3_PFD & + ((uint32_t)ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_MASK << (8UL * (uint32_t)pfd))); + pllFreq = (uint32_t)SYS_PLL3_FREQ; break; default: assert(false); break; } - frac = frac >> (8 * (uint32_t)pfd); - assert((frac >= PFD_FRAC_MIN) && (frac <= PFD_FRAC_MAX)); - return (frac ? pllFreq / frac * 18 : 0); + frac = frac >> (8UL * (uint32_t)pfd); + assert((frac >= (uint32_t)PFD_FRAC_MIN) && (frac <= (uint32_t)PFD_FRAC_MAX)); + return ((frac != 0UL) ? (pllFreq / frac * 18UL) : 0UL); } #else uint32_t CLOCK_GetPfdFreq(clock_pll_t pll, clock_pfd_t pfd) { uint32_t freq = 0; - assert((pll == kCLOCK_PllSys2) || (pll == kCLOCK_PllSys3)); + assert((pll == kCLOCK_PllSys2) || (pll == kCLOCK_PllSys3)); switch (pll) { case kCLOCK_PllSys2: - /* PLL_528_PFD0 OBS index starts from 234 */ + /* SYS_PLL2_PFD0 OBS index starts from 234 */ freq = CLOCK_GetFreqFromObs(pfd + 234, 2); break; case kCLOCK_PllSys3: - /* PLL_480_PFD0 OBS index starts from 241 */ + /* SYS_PLL3_PFD0 OBS index starts from 241 */ freq = CLOCK_GetFreqFromObs(pfd + 241, 2); break; default: @@ -297,36 +369,32 @@ uint32_t CLOCK_GetPfdFreq(clock_pll_t pll, clock_pfd_t pfd) } #endif -#define SYS_PLL3_DIV_SEL_MIN 54 -#define SYS_PLL3_DIV_SEL_MAX 108 /* 480PLL */ -void CLOCK_InitSysPll3(const clock_sys_pll3_config_t *config) +void CLOCK_InitSysPll3(void) { uint32_t reg; - if ((ANADIG_PLL->PLL_480_CTRL & ANADIG_PLL_PLL_480_CTRL_POWERUP_MASK) && - ((ANADIG_PLL->PLL_480_CTRL & ANADIG_PLL_PLL_480_CTRL_DIV_SELECT(config->divSelect)) == - ANADIG_PLL_PLL_480_CTRL_DIV_SELECT(config->divSelect))) + if (0UL != (ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_MASK)) { /* no need to reconfigure the PLL if all the configuration is the same */ - if (!(ANADIG_PLL->PLL_480_CTRL & ANADIG_PLL_PLL_480_CTRL_ENABLE_CLK_MASK)) + if (0UL == (ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK)) { - ANADIG_PLL->PLL_480_CTRL |= ANADIG_PLL_PLL_480_CTRL_ENABLE_CLK_MASK; + ANADIG_PLL->SYS_PLL3_CTRL |= ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK; } - if ((ANADIG_PLL->PLL_480_CTRL & ANADIG_PLL_PLL_480_CTRL_PLL_480_GATE_MASK)) + if (0UL != (ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_MASK)) { - ANADIG_PLL->PLL_480_CTRL &= ~ANADIG_PLL_PLL_480_CTRL_PLL_480_GATE_MASK; + ANADIG_PLL->SYS_PLL3_CTRL &= ~ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_MASK; } return; } - ANATOP_EnablePllLdo(); + PMU_StaticEnablePllLdo(ANADIG_PMU); /* Gate all PFDs */ - ANADIG_PLL->PLL_480_PFD |= - ANADIG_PLL_PLL_480_PFD_PFD0_DIV1_CLKGATE(1) | ANADIG_PLL_PLL_480_PFD_PFD1_DIV1_CLKGATE(1) | - ANADIG_PLL_PLL_480_PFD_PFD2_DIV1_CLKGATE(1) | ANADIG_PLL_PLL_480_PFD_PFD3_DIV1_CLKGATE(1); + ANADIG_PLL->SYS_PLL3_PFD |= + ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE(1) | ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE(1) | + ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE(1) | ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE(1); /* * 1. configure PLL registres * 2. Enable internal LDO @@ -336,86 +404,136 @@ void CLOCK_InitSysPll3(const clock_sys_pll3_config_t *config) * 6. Wait PLL lock * 7. Enable clock output, release pfd_gate */ - reg = ANADIG_PLL_PLL_480_CTRL_DIV_SELECT(config->divSelect) | ANADIG_PLL_PLL_480_CTRL_PLL_REG_EN(1) | - ANADIG_PLL_PLL_480_CTRL_PLL_480_GATE(1); - ANADIG_PLL->PLL_480_CTRL = reg; + reg = ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN(1) | ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE(1); + ANADIG_PLL->SYS_PLL3_CTRL = reg; SDK_DelayAtLeastUs(30, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - reg |= ANADIG_PLL_PLL_480_CTRL_POWERUP(1) | ANADIG_PLL_PLL_480_CTRL_HOLD_RING_OFF_MASK; - ANADIG_PLL->PLL_480_CTRL = reg; + reg |= ANADIG_PLL_SYS_PLL3_CTRL_POWERUP(1) | ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_MASK; + ANADIG_PLL->SYS_PLL3_CTRL = reg; SDK_DelayAtLeastUs(30, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - reg &= ~ANADIG_PLL_PLL_480_CTRL_HOLD_RING_OFF_MASK; - ANADIG_PLL->PLL_480_CTRL = reg; + reg &= ~ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_MASK; + ANADIG_PLL->SYS_PLL3_CTRL = reg; /* Wait for PLL stable */ - while (ANADIG_PLL_PLL_480_CTRL_PLL_480_STABLE_MASK != - (ANADIG_PLL->PLL_480_CTRL & ANADIG_PLL_PLL_480_CTRL_PLL_480_STABLE_MASK)) + while (ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_MASK != + (ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_MASK)) { } - reg |= ANADIG_PLL_PLL_480_CTRL_ENABLE_CLK(1) | ANADIG_PLL_PLL_480_CTRL_PLL_480_DIV2(1); - ANADIG_PLL->PLL_480_CTRL = reg; + reg |= ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK(1) | ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2(1); + ANADIG_PLL->SYS_PLL3_CTRL = reg; - reg &= ~ANADIG_PLL_PLL_480_CTRL_PLL_480_GATE_MASK; - ANADIG_PLL->PLL_480_CTRL = reg; + reg &= ~ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_MASK; + ANADIG_PLL->SYS_PLL3_CTRL = reg; } void CLOCK_DeinitSysPll3(void) { + ANADIG_PLL->SYS_PLL3_PFD |= + ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE(1) | ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE(1) | + ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE(1) | ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE(1); + + ANADIG_PLL->SYS_PLL3_CTRL |= ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_MASK; + ANADIG_PLL->SYS_PLL3_CTRL &= ~(ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK | ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_MASK | + ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_MASK); } -void ANATOP_PllSetPower(anatop_ai_itf_t itf, bool enable) +void CLOCK_SetPllBypass(clock_pll_t pll, bool bypass) { - ANATOP_AI_Write(itf, enable ? 0x04 : 0x08, 0x4000 | (enable ? 0x2000 : 0)); + switch (pll) + { + case kCLOCK_PllArm: + ANADIG_PLL->ARM_PLL_CTRL = bypass ? (ANADIG_PLL->ARM_PLL_CTRL | ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK) : + (ANADIG_PLL->ARM_PLL_CTRL & ~ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK); + break; + case kCLOCK_PllSys1: + ANATOP_PllBypass(kAI_Itf_1g, bypass); + break; + case kCLOCK_PllSys2: + ANADIG_PLL->SYS_PLL2_CTRL = bypass ? (ANADIG_PLL->SYS_PLL2_CTRL | ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) : + (ANADIG_PLL->SYS_PLL2_CTRL & ~ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK); + break; + case kCLOCK_PllSys3: + ANADIG_PLL->SYS_PLL3_CTRL = bypass ? (ANADIG_PLL->SYS_PLL3_CTRL | ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK) : + (ANADIG_PLL->SYS_PLL3_CTRL & ~ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK); + break; + case kCLOCK_PllAudio: + ANATOP_PllBypass(kAI_Itf_Audio, bypass); + break; + case kCLOCK_PllVideo: + ANATOP_PllBypass(kAI_Itf_Video, bypass); + break; + default: + assert(0); + break; + } +} + +static void ANATOP_PllSetPower(anatop_ai_itf_t itf, bool enable) +{ + ANATOP_AI_Write(itf, enable ? PLL_AI_CTRL0_SET_REG : PLL_AI_CTRL0_CLR_REG, + PLL_AI_CTRL0_POWER_UP_MASK | (enable ? PLL_AI_CTRL0_HOLD_RING_OFF_MASK : 0UL)); } -void ANATOP_PllBypass(anatop_ai_itf_t itf, bool bypass) +static void ANATOP_PllBypass(anatop_ai_itf_t itf, bool bypass) { - ANATOP_AI_Write(itf, bypass ? 0x04 : 0x08, 0x10000); + ANATOP_AI_Write(itf, bypass ? PLL_AI_CTRL0_SET_REG : PLL_AI_CTRL0_CLR_REG, PLL_AI_CTRL0_BYPASS_MASK); } -void ANATOP_PllEnablePllReg(anatop_ai_itf_t itf, bool enable) +static void ANATOP_PllEnablePllReg(anatop_ai_itf_t itf, bool enable) { - ANATOP_AI_Write(itf, enable ? 0x04 : 0x08, 0x400000); + ANATOP_AI_Write(itf, enable ? PLL_AI_CTRL0_SET_REG : PLL_AI_CTRL0_CLR_REG, PLL_AI_CTRL0_PLL_REG_EN_MASK); } -void ANATOP_PllHoldRingOff(anatop_ai_itf_t itf, bool off) +static void ANATOP_PllHoldRingOff(anatop_ai_itf_t itf, bool off) { - ANATOP_AI_Write(itf, off ? 0x04 : 0x08, 0x2000); + ANATOP_AI_Write(itf, off ? PLL_AI_CTRL0_SET_REG : PLL_AI_CTRL0_CLR_REG, PLL_AI_CTRL0_HOLD_RING_OFF_MASK); } -void ANATOP_PllToggleHoldRingOff(anatop_ai_itf_t itf, uint32_t delay_us) +static void ANATOP_PllToggleHoldRingOff(anatop_ai_itf_t itf, uint32_t delay_us) { ANATOP_PllHoldRingOff(itf, true); SDK_DelayAtLeastUs(delay_us, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); ANATOP_PllHoldRingOff(itf, false); } +void ANATOP_PllEnableSs(anatop_ai_itf_t itf, bool enable) +{ + ANATOP_AI_Write(itf, enable ? PLL_AI_CTRL0_SET_REG : PLL_AI_CTRL0_CLR_REG, PLL_AI_CTRL0_ENABLE_MASK); +} + void ANATOP_PllEnableClk(anatop_ai_itf_t itf, bool enable) { - ANATOP_AI_Write(itf, enable ? 0x04 : 0x08, 0x8000); + ANATOP_AI_Write(itf, enable ? PLL_AI_CTRL0_SET_REG : PLL_AI_CTRL0_CLR_REG, PLL_AI_CTRL0_ENABLE_MASK); } -void ANATOP_PllConfigure(anatop_ai_itf_t itf, uint8_t div, uint32_t numer, uint8_t post_div, uint32_t denom) +void ANATOP_PllConfigure( + anatop_ai_itf_t itf, uint8_t div, uint32_t numer, uint8_t post_div, uint32_t denom, const clock_pll_ss_config_t *ss) { if (itf != kAI_Itf_1g) { ANATOP_PllSetPower(itf, false); } - ANATOP_AI_Write(itf, 0x30, denom); - ANATOP_AI_Write(itf, 0x20, numer); - ANATOP_AI_WriteWithMaskShift(itf, 0x00, div, 0x7f, 0); + if (ss) + { + ANATOP_AI_Write(itf, PLL_AI_CTRL1_REG, + AUDIO_PLL_SPREAD_SPECTRUM_STEP(ss->step) | AUDIO_PLL_SPREAD_SPECTRUM_STOP(ss->stop) | + AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_MASK); + } + ANATOP_AI_Write(itf, PLL_AI_CTRL3_REG, denom); + ANATOP_AI_Write(itf, PLL_AI_CTRL2_REG, numer); + ANATOP_AI_WriteWithMaskShift(itf, PLL_AI_CTRL0_REG, div, 0x7f, 0); if (itf != kAI_Itf_1g) { - ANATOP_AI_WriteWithMaskShift(itf, 0x00, post_div, 0xE000000, 25); + ANATOP_AI_WriteWithMaskShift(itf, PLL_AI_CTRL0_REG, post_div, 0xE000000UL, 25UL); } ANATOP_PllEnablePllReg(itf, true); SDK_DelayAtLeastUs(100, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); ANATOP_PllSetPower(itf, true); } -void ANATOP_AudioPllGate(bool enable) +static void ANATOP_AudioPllGate(bool enable) { if (!enable) { @@ -427,7 +545,7 @@ void ANATOP_AudioPllGate(bool enable) } } -void ANATOP_AudioPllSwEnClk(bool enable) +static void ANATOP_AudioPllSwEnClk(bool enable) { if (!enable) { @@ -439,12 +557,19 @@ void ANATOP_AudioPllSwEnClk(bool enable) } } -status_t CLOCK_InitAudioPllWithFreq(uint32_t freqInMhz) +status_t CLOCK_InitAudioPllWithFreq(uint32_t freqInMhz, bool ssEnable, uint32_t ssRange, uint32_t ssMod) { clock_audio_pll_config_t config = {0}; + config.ssEnable = ssEnable; if (kStatus_Success == CLOCK_CalcAvPllFreq(&config, freqInMhz)) { + if (config.ssEnable) + { + clock_pll_ss_config_t ss = {0}; + CLOCK_CalcPllSpreadSpectrum(config.denominator, ssRange, ssMod, &ss); + config.ss = &ss; + } CLOCK_InitAudioPll(&config); return kStatus_Success; } @@ -456,7 +581,7 @@ void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config) uint32_t reg; bool pllStable = false; - ANATOP_EnablePllLdo(); + PMU_StaticEnablePllLdo(ANADIG_PMU); reg = ANADIG_PLL->PLL_AUDIO_CTRL; if ((reg & (ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_MASK | ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK)) == @@ -480,8 +605,8 @@ void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config) ANATOP_AudioPllSwEnClk(true); /* configure pll */ - ANATOP_PllConfigure(kAI_Itf_Audio, config->loopDivider, config->numerator, config->postDivider, - config->denominator); + ANATOP_PllConfigure(kAI_Itf_Audio, config->loopDivider, config->numerator, config->postDivider, config->denominator, + (config->ssEnable && config->ss) ? config->ss : NULL); /* toggle hold ring off */ ANATOP_PllToggleHoldRingOff(kAI_Itf_Audio, 225); @@ -508,10 +633,27 @@ void CLOCK_DeinitAudioPll(void) ANATOP_AudioPllGate(true); ANATOP_PllEnableClk(kAI_Itf_Audio, false); ANATOP_PllSetPower(kAI_Itf_Audio, false); + ANATOP_PllEnableSs(kAI_Itf_Audio, false); ANATOP_PllEnablePllReg(kAI_Itf_Audio, false); } -void ANATOP_VideoPllGate(bool enable) +void CLOCK_GPC_SetAudioPllOutputFreq(const clock_audio_pll_gpc_config_t *config) +{ + assert(config != NULL); + + ANADIG_PLL->PLL_AUDIO_DIV_SELECT = config->loopDivider; + ANADIG_PLL->PLL_AUDIO_NUMERATOR = config->numerator; + ANADIG_PLL->PLL_AUDIO_DENOMINATOR = config->denominator; + if ((config->ss != NULL) && config->ssEnable) + { + ANADIG_PLL->PLL_AUDIO_SS = ANADIG_PLL_PLL_AUDIO_SS_STEP(config->ss->step) | + ANADIG_PLL_PLL_AUDIO_SS_STOP(config->ss->stop) | ANADIG_PLL_PLL_AUDIO_SS_ENABLE_MASK; + } + + ANADIG_PLL->PLL_AUDIO_CTRL |= ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK; +} + +static void ANATOP_VideoPllGate(bool enable) { if (!enable) { @@ -523,7 +665,7 @@ void ANATOP_VideoPllGate(bool enable) } } -void ANATOP_VideoPllSwEnClk(bool enable) +static void ANATOP_VideoPllSwEnClk(bool enable) { if (!enable) { @@ -535,11 +677,11 @@ void ANATOP_VideoPllSwEnClk(bool enable) } } -status_t CLOCK_CalcArmPllFreq(clock_arm_pll_config_t *cfg, uint32_t freqInMhz) +status_t CLOCK_CalcArmPllFreq(clock_arm_pll_config_t *config, uint32_t freqInMhz) { - assert(cfg); - uint32_t refFreq = (XTAL_FREQ / 1000000) * 104; /* MHz */ - assert((freqInMhz <= refFreq) && (freqInMhz >= 156)); + assert(config != NULL); + uint32_t refFreq = (XTAL_FREQ / 1000000UL) * 104UL; /* MHz */ + assert((freqInMhz <= refFreq) && (freqInMhz >= 156UL)); /* * ARM_PLL (156Mhz - 2496Mhz configureable ) @@ -552,33 +694,33 @@ status_t CLOCK_CalcArmPllFreq(clock_arm_pll_config_t *cfg, uint32_t freqInMhz) if (freqInMhz >= refFreq) { - cfg->postDivider = kCLOCK_PllPostDiv1; - cfg->loopDivider = 208; + config->postDivider = kCLOCK_PllPostDiv1; + config->loopDivider = 208; } else if (freqInMhz >= (refFreq >> 1)) { - cfg->postDivider = kCLOCK_PllPostDiv1; - cfg->loopDivider = freqInMhz / 12 ; + config->postDivider = kCLOCK_PllPostDiv1; + config->loopDivider = freqInMhz / 12UL; } else if (freqInMhz >= (refFreq >> 2)) { - cfg->postDivider = kCLOCK_PllPostDiv2; - cfg->loopDivider = freqInMhz / 6; + config->postDivider = kCLOCK_PllPostDiv2; + config->loopDivider = freqInMhz / 6UL; } else if (freqInMhz >= (refFreq >> 3)) { - cfg->postDivider = kCLOCK_PllPostDiv4; - cfg->loopDivider = freqInMhz / 3; + config->postDivider = kCLOCK_PllPostDiv4; + config->loopDivider = freqInMhz / 3UL; } else if (freqInMhz > (refFreq >> 4)) { - cfg->postDivider = kCLOCK_PllPostDiv8; - cfg->loopDivider = 2 * freqInMhz / 3; + config->postDivider = kCLOCK_PllPostDiv8; + config->loopDivider = 2UL * freqInMhz / 3UL; } else { - cfg->postDivider = kCLOCK_PllPostDiv8; - cfg->loopDivider = 104; + config->postDivider = kCLOCK_PllPostDiv8; + config->loopDivider = 104; } return kStatus_Success; } @@ -594,13 +736,13 @@ status_t CLOCK_InitArmPllWithFreq(uint32_t freqInMhz) return kStatus_Fail; } -status_t CLOCK_CalcAvPllFreq(clock_av_pll_config_t *cfg, uint32_t freqInMhz) +status_t CLOCK_CalcAvPllFreq(clock_av_pll_config_t *config, uint32_t freqInMhz) { - assert(cfg); + assert(config != NULL); - uint32_t refFreq = (XTAL_FREQ / 1000000) * 54; /* MHz */ + uint32_t refFreq = (XTAL_FREQ / 1000000UL) * 54UL; /* MHz */ - assert((freqInMhz <= refFreq) && (freqInMhz > 20)); + assert((freqInMhz <= refFreq) && (freqInMhz > 20UL)); /* * AUDIO_PLL/VIDEO_PLL (20.3125MHZ--- 1300MHZ configureable ) @@ -613,49 +755,49 @@ status_t CLOCK_CalcAvPllFreq(clock_av_pll_config_t *cfg, uint32_t freqInMhz) * 252357290/(2^28 - 1))/2^0= 651.65M */ - cfg->denominator = 0x0FFFFFFF; + config->denominator = 0x0FFFFFFF; if (freqInMhz >= refFreq) { - cfg->postDivider = 0; - cfg->loopDivider = 54; - cfg->numerator = 0; + config->postDivider = 0; + config->loopDivider = 54; + config->numerator = 0; } else if (freqInMhz >= (refFreq >> 1)) { - cfg->postDivider = 0; - cfg->loopDivider = freqInMhz / 24; - cfg->numerator = (cfg->denominator / 24) * (freqInMhz % 24); + config->postDivider = 0; + config->loopDivider = (uint8_t)(freqInMhz / 24UL); + config->numerator = (config->denominator / 24UL) * (freqInMhz % 24UL); } else if (freqInMhz >= (refFreq >> 2)) { - cfg->postDivider = 1; - cfg->loopDivider = freqInMhz / 12; - cfg->numerator = (cfg->denominator / 12) * (freqInMhz % 12); + config->postDivider = 1; + config->loopDivider = (uint8_t)(freqInMhz / 12UL); + config->numerator = (config->denominator / 12UL) * (freqInMhz % 12UL); } else if (freqInMhz >= (refFreq >> 3)) { - cfg->postDivider = 2; - cfg->loopDivider = freqInMhz / 6; - cfg->numerator = (cfg->denominator / 6) * (freqInMhz % 6); + config->postDivider = 2; + config->loopDivider = (uint8_t)(freqInMhz / 6UL); + config->numerator = (config->denominator / 6UL) * (freqInMhz % 6UL); } else if (freqInMhz >= (refFreq >> 4)) { - cfg->postDivider = 3; - cfg->loopDivider = freqInMhz / 3; - cfg->numerator = (cfg->denominator / 3) * (freqInMhz % 3); + config->postDivider = 3; + config->loopDivider = (uint8_t)(freqInMhz / 3UL); + config->numerator = (config->denominator / 3UL) * (freqInMhz % 3UL); } else if (freqInMhz >= (refFreq >> 5)) { - cfg->postDivider = 4; - cfg->loopDivider = freqInMhz * 2 / 3; - cfg->numerator = (cfg->denominator * 2 / 3) * (freqInMhz * 2 % 3); + config->postDivider = 4; + config->loopDivider = (uint8_t)(freqInMhz * 2UL / 3UL); + config->numerator = (config->denominator * 2UL / 3UL) * (freqInMhz * 2UL % 3UL); } else if (freqInMhz > (refFreq >> 6)) { - cfg->postDivider = 5; - cfg->loopDivider = freqInMhz * 4 / 3; - cfg->numerator = (cfg->denominator * 4 / 3) * (freqInMhz * 4 % 3); + config->postDivider = 5; + config->loopDivider = (uint8_t)(freqInMhz * 4UL / 3UL); + config->numerator = (config->denominator * 4UL / 3UL) * (freqInMhz * 4UL % 3UL); } else { @@ -664,11 +806,19 @@ status_t CLOCK_CalcAvPllFreq(clock_av_pll_config_t *cfg, uint32_t freqInMhz) return kStatus_Success; } -status_t CLOCK_InitVideoPllWithFreq(uint32_t freqInMhz) +status_t CLOCK_InitVideoPllWithFreq(uint32_t freqInMhz, bool ssEnable, uint32_t ssRange, uint32_t ssMod) { clock_video_pll_config_t config = {0}; + config.ssEnable = ssEnable; + if (kStatus_Success == CLOCK_CalcAvPllFreq(&config, freqInMhz)) { + if (config.ssEnable) + { + clock_pll_ss_config_t ss = {0}; + CLOCK_CalcPllSpreadSpectrum(config.denominator, ssRange, ssMod, &ss); + config.ss = &ss; + } CLOCK_InitVideoPll(&config); return kStatus_Success; } @@ -680,7 +830,7 @@ void CLOCK_InitVideoPll(const clock_video_pll_config_t *config) uint32_t reg; bool pllStable = false; - ANATOP_EnablePllLdo(); + PMU_StaticEnablePllLdo(ANADIG_PMU); reg = ANADIG_PLL->PLL_VIDEO_CTRL; if ((reg & (ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_MASK | ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK)) == @@ -704,8 +854,8 @@ void CLOCK_InitVideoPll(const clock_video_pll_config_t *config) ANATOP_VideoPllSwEnClk(true); /* configure pll */ - ANATOP_PllConfigure(kAI_Itf_Video, config->loopDivider, config->numerator, config->postDivider, - config->denominator); + ANATOP_PllConfigure(kAI_Itf_Video, config->loopDivider, config->numerator, config->postDivider, config->denominator, + (config->ssEnable && config->ss) ? config->ss : NULL); /* toggle hold ring off */ ANATOP_PllToggleHoldRingOff(kAI_Itf_Video, 225); @@ -732,73 +882,92 @@ void CLOCK_DeinitVideoPll(void) ANATOP_VideoPllGate(true); ANATOP_PllEnableClk(kAI_Itf_Video, false); ANATOP_PllSetPower(kAI_Itf_Video, false); + ANATOP_PllEnableSs(kAI_Itf_Video, false); ANATOP_PllEnablePllReg(kAI_Itf_Video, false); } -void ANATOP_SysPll1Gate(bool enable) +void CLOCK_GPC_SetVideoPllOutputFreq(const clock_video_pll_gpc_config_t *config) +{ + assert(config != NULL); + + ANADIG_PLL->PLL_VIDEO_DIV_SELECT = config->loopDivider; + ANADIG_PLL->PLL_VIDEO_NUMERATOR = config->numerator; + ANADIG_PLL->PLL_VIDEO_DENOMINATOR = config->denominator; + + if ((config->ss != NULL) && config->ssEnable) + { + ANADIG_PLL->PLL_VIDEO_SS = ANADIG_PLL_PLL_VIDEO_SS_STEP(config->ss->step) | + ANADIG_PLL_PLL_VIDEO_SS_STOP(config->ss->stop) | ANADIG_PLL_PLL_VIDEO_SS_ENABLE_MASK; + } + + ANADIG_PLL->PLL_VIDEO_CTRL |= ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK; +} + +static void ANATOP_SysPll1Gate(bool enable) { if (!enable) { - ANADIG_PLL->PLL_1G_CTRL &= ~ANADIG_PLL_PLL_1G_CTRL_PLL_1G_GATE_MASK; + ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK; } else { - ANADIG_PLL->PLL_1G_CTRL |= ANADIG_PLL_PLL_1G_CTRL_PLL_1G_GATE_MASK; + ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK; } } -void ANATOP_SysPll1Div2En(bool enable) +static void ANATOP_SysPll1Div2En(bool enable) { if (!enable) { - ANADIG_PLL->PLL_1G_CTRL &= ~ANADIG_PLL_PLL_1G_CTRL_PLL_1G_DIV2_MASK; + ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK; } else { - ANADIG_PLL->PLL_1G_CTRL |= ANADIG_PLL_PLL_1G_CTRL_PLL_1G_DIV2_MASK; + ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK; } } -void ANATOP_SysPll1Div5En(bool enable) +static void ANATOP_SysPll1Div5En(bool enable) { if (!enable) { - ANADIG_PLL->PLL_1G_CTRL &= ~ANADIG_PLL_PLL_1G_CTRL_PLL_1G_DIV5_MASK; + ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK; } else { - ANADIG_PLL->PLL_1G_CTRL |= ANADIG_PLL_PLL_1G_CTRL_PLL_1G_DIV5_MASK; + ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK; } } -void ANATOP_SysPll1SwEnClk(bool enable) +static void ANATOP_SysPll1SwEnClk(bool enable) { if (!enable) { - ANADIG_PLL->PLL_1G_CTRL &= ~ANADIG_PLL_PLL_1G_CTRL_ENABLE_CLK_MASK; + ANADIG_PLL->SYS_PLL1_CTRL &= ~ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK; } else { - ANADIG_PLL->PLL_1G_CTRL |= ANADIG_PLL_PLL_1G_CTRL_ENABLE_CLK_MASK; + ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK; } } -void ANATOP_SysPll1WaitStable(void) +static void ANATOP_SysPll1WaitStable(void) { uint32_t reg; do { - reg = ANADIG_PLL->PLL_1G_CTRL; - } while ((reg & ANADIG_PLL_PLL_1G_CTRL_PLL_1G_STABLE_MASK) != - ANADIG_PLL_PLL_1G_CTRL_PLL_1G_STABLE_MASK); /* wait for PLL locked */ + reg = ANADIG_PLL->SYS_PLL1_CTRL; + } while ((reg & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_MASK) != + ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_MASK); /* wait for PLL locked */ } /* 1GPLL */ void CLOCK_InitSysPll1(const clock_sys_pll1_config_t *config) { uint32_t div, numerator, denominator; + bool err = false; - ANATOP_EnablePllLdo(); + PMU_StaticEnablePllLdo(ANADIG_PMU); /* bypass pll */ ANATOP_PllBypass(kAI_Itf_1g, true); @@ -806,23 +975,30 @@ void CLOCK_InitSysPll1(const clock_sys_pll1_config_t *config) ANATOP_SysPll1SwEnClk(true); denominator = 0x0FFFFFFF; - switch (XTAL_FREQ / 100000) + switch ((uint32_t)(XTAL_FREQ / 100000UL)) { - case 240: - div = 41; - numerator = 178956970; + case 240UL: + div = 41UL; + numerator = 178956970UL; break; - case 192: - div = 52; - numerator = 22369621; + case 192UL: + div = 52UL; + numerator = 22369621UL; break; default: assert(false); - return; + err = true; + break; + } + + if (err || (config->ssEnable && !config->ss)) + { + return; } /* configure pll */ - ANATOP_PllConfigure(kAI_Itf_1g, div, numerator, 0, denominator); + ANATOP_PllConfigure(kAI_Itf_1g, div, numerator, 0, denominator, + (config->ssEnable && config->ss) ? config->ss : NULL); /* toggle hold ring off */ ANATOP_PllToggleHoldRingOff(kAI_Itf_1g, 225); @@ -851,87 +1027,376 @@ void CLOCK_DeinitSysPll1(void) ANATOP_SysPll1Gate(true); ANATOP_PllEnableClk(kAI_Itf_1g, false); ANATOP_PllSetPower(kAI_Itf_1g, false); + ANATOP_PllEnableSs(kAI_Itf_1g, false); ANATOP_PllEnablePllReg(kAI_Itf_1g, false); } -void CLOCK_EnableOsc24M(void) +void CLOCK_GPC_SetSysPll1OutputFreq(const clock_sys_pll1_gpc_config_t *config) { - if (!(ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_EN_MASK)) + assert(config != NULL); + + ANADIG_PLL->SYS_PLL1_DIV_SELECT = config->loopDivider; + ANADIG_PLL->SYS_PLL1_NUMERATOR = config->numerator; + ANADIG_PLL->SYS_PLL1_DENOMINATOR = config->denominator; + + if ((config->ss != NULL) && config->ssEnable) { - ANADIG_OSC->OSC_24M_CTRL = ANADIG_OSC_OSC_24M_CTRL_OSC_EN_MASK - | ANADIG_OSC_OSC_24M_CTRL_LP_EN_MASK; + ANADIG_PLL->SYS_PLL1_SS = ANADIG_PLL_SYS_PLL1_SS_STEP(config->ss->step) | + ANADIG_PLL_SYS_PLL1_SS_STOP(config->ss->stop) | ANADIG_PLL_SYS_PLL1_SS_ENABLE_MASK; + } + + ANADIG_PLL->SYS_PLL1_CTRL |= ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK; +} + +void CLOCK_OSC_EnableOsc24M(void) +{ + if (0UL == (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_EN_MASK)) + { + ANADIG_OSC->OSC_24M_CTRL = ANADIG_OSC_OSC_24M_CTRL_OSC_EN_MASK | ANADIG_OSC_OSC_24M_CTRL_LP_EN_MASK; while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK != - (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)) + (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)) + { + } + } +} + +/*! + * brief Set the work mode of 24MHz crystal oscillator, the available modes are high gian mode, low power mode, and + * bypass mode. + * + * param workMode The work mode of 24MHz crystal oscillator, please refer to @ref clock_24MOsc_mode_t for details. + */ +void CLOCK_OSC_SetOsc24MWorkMode(clock_24MOsc_mode_t workMode) +{ + uint32_t tmp32; + + tmp32 = ANADIG_OSC->OSC_24M_CTRL; + tmp32 &= ~(ANADIG_OSC_OSC_24M_CTRL_LP_EN_MASK | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_MASK); + tmp32 |= (((uint32_t)workMode << ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_SHIFT) & + (ANADIG_OSC_OSC_24M_CTRL_LP_EN_MASK | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_MASK)); + ANADIG_OSC->OSC_24M_CTRL = tmp32; +} + +/*! + * brief Configure the 16MHz oscillator. + * + * param source Used to select the source for 16MHz RC oscillator, please refer to clock_16MOsc_source_t. + * param enablePowerSave Enable/disable power save mode function at 16MHz OSC. + * - \b true Enable power save mode function at 16MHz osc. + * - \b false Disable power save mode function at 16MHz osc. + * param enableClockOut Enable/Disable clock output for 16MHz RCOSC. + * - \b true Enable clock output for 16MHz RCOSC. + * - \b false Disable clock output for 16MHz RCOSC. + */ +void CLOCK_OSC_SetOsc16MConfig(clock_16MOsc_source_t source, bool enablePowerSave, bool enableClockOut) +{ + uint32_t tmp32; + + tmp32 = ANADIG_OSC->OSC_16M_CTRL; + tmp32 &= ~(ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK | ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_MASK | + ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_MASK); + tmp32 |= ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M(enableClockOut) | + ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE(enablePowerSave) | ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M(source); + ANADIG_OSC->OSC_16M_CTRL = tmp32; +} + +/*! + * brief Set the divide value for ref_clk to generate slow clock. + * + * note slow_clk = ref_clk / (divValue + 1), and the recommand divide value is 24. + * + * param divValue The divide value to be set, the available range is 0~63. + */ +void CLOCK_OSC_SetOscRc400MRefClkDiv(uint8_t divValue) +{ + uint32_t tmp32; + + tmp32 = ANATOP_AI_Read(kAI_Itf_400m, kAI_RCOSC400M_CTRL0); + tmp32 = ((tmp32 & ~AI_RCOSC400M_CTRL0_REF_CLK_DIV_MASK) | AI_RCOSC400M_CTRL0_REF_CLK_DIV(divValue)); + ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL0, tmp32); +} + +/*! + * brief Set the target count for the fast clock. + * + * param targetCount The desired target for the fast clock, should be the number of clock cycles of the fast_clk per + * divided ref_clk. + */ +void CLOCK_OSC_SetOscRc400MFastClkCount(uint16_t targetCount) +{ + uint32_t tmp32; + + tmp32 = ANATOP_AI_Read(kAI_Itf_400m, kAI_RCOSC400M_CTRL1); + tmp32 = ((tmp32 & ~AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK) | AI_RCOSC400M_CTRL1_TARGET_COUNT(targetCount)); + ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL1, tmp32); +} + +/*! + * brief Set the negative and positive hysteresis value for the tuned clock. + * + * note The hysteresis value should be set after the clock is tuned. + * + * param negHysteresis The negative hysteresis value for the turned clock, this value in number of clock cycles of the + * fast clock + * param posHysteresis The positive hysteresis value for the turned clock, this value in number of clock cycles of the + * fast clock + */ +void CLOCK_OSC_SetOscRc400MHysteresisValue(uint8_t negHysteresis, uint8_t posHysteresis) +{ + uint32_t tmp32; + + tmp32 = ANATOP_AI_Read(kAI_Itf_400m, kAI_RCOSC400M_CTRL1); + tmp32 = ((tmp32 & ~(AI_RCOSC400M_CTRL1_HYST_PLUS_MASK | AI_RCOSC400M_CTRL1_HYST_MINUS_MASK)) | + (AI_RCOSC400M_CTRL1_HYST_PLUS(posHysteresis) | AI_RCOSC400M_CTRL1_HYST_MINUS(negHysteresis))); + ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL1, tmp32); +} + +/*! + * brief Bypass/un-bypass the tune logic + * + * param enableBypass Used to control whether to bypass the turn logic. + * - \b true Bypass the tune logic and use the programmed oscillator frequency to run the oscillator. + * Function CLOCK_OSC_SetOscRc400MTuneValue() can be used to set oscillator frequency. + * - \b false Use the output of tune logic to run the oscillator. + */ +void CLOCK_OSC_BypassOscRc400MTuneLogic(bool enableBypass) +{ + if (enableBypass) + { + ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL2_SET, AI_RCOSC400M_CTRL2_TUNE_BYP_MASK); + } + else + { + ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL2_CLR, AI_RCOSC400M_CTRL2_TUNE_BYP_MASK); + } +} + +/*! + * brief Start/Stop the tune logic. + * + * param enable Used to start or stop the tune logic. + * - \b true Start tuning + * - \b false Stop tuning and reset the tuning logic. + */ +void CLOCK_OSC_EnableOscRc400MTuneLogic(bool enable) +{ + if (enable) + { + ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL2_SET, AI_RCOSC400M_CTRL2_TUNE_START_MASK); + } + else + { + ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL2_CLR, AI_RCOSC400M_CTRL2_TUNE_START_MASK); + } +} + +/*! + * brief Freeze/Unfreeze the tuning value. + * + * param enableFreeze Used to control whether to freeze the tune value. + * - \b true Freeze the tune at the current tuned value and the oscillator runs at tje frozen tune value. + * - \b false Unfreezes and continues the tune operation. + */ +void CLOCK_OSC_FreezeOscRc400MTuneValue(bool enableFreeze) +{ + if (enableFreeze) + { + ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL2_SET, AI_RCOSC400M_CTRL2_TUNE_EN_MASK); + } + else + { + ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL2_CLR, AI_RCOSC400M_CTRL2_TUNE_EN_MASK); + } +} + +/*! + * @brief Set the 400MHz RC oscillator tune value when the tune logic is disabled. + * + * @param tuneValue The tune value to determine the frequency of Oscillator. + */ +void CLOCK_OSC_SetOscRc400MTuneValue(uint8_t tuneValue) +{ + uint32_t tmp32; + + tmp32 = ANATOP_AI_Read(kAI_Itf_400m, kAI_RCOSC400M_CTRL2); + tmp32 &= ~AI_RCOSC400M_CTRL2_OSC_TUNE_VAL_MASK; + tmp32 |= AI_RCOSC400M_CTRL2_OSC_TUNE_VAL(tuneValue); + ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL2, tmp32); +} + +/*! + * brief Set the behavior of the 1MHz output clock, such as disable the 1MHz clock output, + * enable the free-running 1MHz clock output, enable the locked 1MHz clock output. + * + * note The 1MHz clock is divided from 400M RC Oscillator. + * + * param behavior The behavior of 1MHz output clock, please refer to clock_1MHzOut_behavior_t for details. + */ +void CLOCK_OSC_Set1MHzOutputBehavior(clock_1MHzOut_behavior_t behavior) +{ + uint32_t tmp32; + + tmp32 = ANATOP_AI_Read(kAI_Itf_400m, kAI_RCOSC400M_CTRL3); + tmp32 &= ~(AI_RCOSC400M_CTRL3_EN_1M_CLK_MASK | AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK); + + if (behavior == kCLOCK_1MHzOutDisable) + { + tmp32 |= AI_RCOSC400M_CTRL3_EN_1M_CLK_MASK; + } + else + { + if (behavior == kCLOCK_1MHzOutEnableLocked1Mhz) { + tmp32 |= AI_RCOSC400M_CTRL3_MUX_1M_CLK_MASK; } } + ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL3, tmp32); +} + +/*! + * brief Set the count for the locked 1MHz clock out. + * + * param count Used to set the desired target for the locked 1MHz clock out, the value in number of clock cycles of the + * osc_out_400M per divided ref_clk. + */ +void CLOCK_OSC_SetLocked1MHzCount(uint16_t count) +{ + uint32_t tmp32; + uint16_t targetCount; + uint16_t hystMinus; + uint16_t diffCount; + + tmp32 = ANATOP_AI_Read(kAI_Itf_400m, kAI_RCOSC400M_CTRL1); + targetCount = (uint16_t)((tmp32 & AI_RCOSC400M_CTRL1_TARGET_COUNT_MASK) >> AI_RCOSC400M_CTRL1_TARGET_COUNT_SHIFT); + hystMinus = (uint16_t)((tmp32 & AI_RCOSC400M_CTRL1_HYST_MINUS_MASK) >> AI_RCOSC400M_CTRL1_HYST_MINUS_SHIFT); + diffCount = targetCount - hystMinus - count; + + /* The count for the locked 1MHz clock should be 4 to 8 counts less than CTRL[TARGET_COUNT] - CTRL1[HYST_MINUS]. */ + if ((diffCount >= 4U) && (diffCount <= 8U)) + { + tmp32 = (tmp32 & ~AI_RCOSC400M_CTRL3_COUNT_1M_CLK_MASK) | AI_RCOSC400M_CTRL3_COUNT_1M_CLK(count); + ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL3, tmp32); + } +} + +/*! + * brief Check the error flag for locked 1MHz clock out. + * + * return The error flag for locked 1MHz clock out. + * - \b true The count value has been reached within one diviced ref clock period + * - \b false No effect. + */ +bool CLOCK_OSC_CheckLocked1MHzErrorFlag(void) +{ + uint32_t tmp32; + + tmp32 = ANATOP_AI_Read(kAI_Itf_400m, kAI_RCOSC400M_STAT0); + + return ((tmp32 & AI_RCOSC400M_STAT0_CLK1M_ERR_MASK) == AI_RCOSC400M_STAT0_CLK1M_ERR_MASK); +} + +/*! + * brief Clear the error flag for locked 1MHz clock out. + */ +void CLOCK_OSC_ClearLocked1MHzErrorFlag(void) +{ + ANATOP_AI_Write(kAI_Itf_400m, kAI_RCOSC400M_CTRL3_SET, AI_RCOSC400M_CTRL3_CLR_ERR_MASK); } -uint32_t CLOCK_GetAvPllFreq(clock_pll_t pll) +/*! + * brief Get current count for the fast clock during the tune process. + * + * return The current count for the fast clock. + */ +uint16_t CLOCK_OSC_GetCurrentOscRc400MFastClockCount(void) +{ + uint32_t tmp32; + + tmp32 = ANATOP_AI_Read(kAI_Itf_400m, kAI_RCOSC400M_STAT1); + + return ((tmp32 & AI_RCOSC400M_STAT1_CURR_COUNT_VAL_MASK) >> AI_RCOSC400M_STAT1_CURR_COUNT_VAL_SHIFT); +} + +/*! + * brief Get current tune value used by oscillator during tune process. + * + * return The current tune value. + */ +uint8_t CLOCK_OSC_GetCurrentOscRc400MTuneValue(void) +{ + uint32_t tmp32; + + tmp32 = ANATOP_AI_Read(kAI_Itf_400m, kAI_RCOSC400M_STAT2); + + return ((tmp32 & AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL_MASK) >> AI_RCOSC400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT); +} + +#ifndef GET_FREQ_FROM_OBS +static uint32_t CLOCK_GetAvPllFreq(clock_pll_t pll) { uint32_t freq = 0; uint32_t div; uint32_t post_div; + double tmpDouble; double denom; double numer; assert((pll == kCLOCK_PllAudio) || (pll == kCLOCK_PllVideo)); - div = ANATOP_AI_Read(pll == kCLOCK_PllAudio ? kAI_Itf_Audio : kAI_Itf_Video, 0); - post_div = (div & (0xE000000)) >> 25; - div &= 0x7f; + div = ANATOP_AI_Read(pll == kCLOCK_PllAudio ? kAI_Itf_Audio : kAI_Itf_Video, PLL_AI_CTRL0_REG); + post_div = (div & (0xE000000UL)) >> 25UL; + div &= 0x7fUL; + denom = (double)ANATOP_AI_Read(pll == kCLOCK_PllAudio ? kAI_Itf_Audio : kAI_Itf_Video, PLL_AI_CTRL3_REG); + numer = (double)ANATOP_AI_Read(pll == kCLOCK_PllAudio ? kAI_Itf_Audio : kAI_Itf_Video, PLL_AI_CTRL2_REG); - denom = ANATOP_AI_Read(pll == kCLOCK_PllAudio ? kAI_Itf_Audio : kAI_Itf_Video, 0x30); - numer = ANATOP_AI_Read(pll == kCLOCK_PllAudio ? kAI_Itf_Audio : kAI_Itf_Video, 0x20); + tmpDouble = ((double)XTAL_FREQ * ((double)div + (numer / denom)) / (double)(1UL << post_div)); + freq = (uint32_t)tmpDouble; - freq = (uint32_t)(XTAL_FREQ * (div + numer/denom) / (1 << post_div)); return freq; } +#endif uint32_t CLOCK_GetPllFreq(clock_pll_t pll) { uint32_t freq = 0; #ifndef GET_FREQ_FROM_OBS - uint32_t divSelect, postDiv, mfi, mfn, mfd; + uint32_t divSelect, postDiv; #endif switch (pll) { case kCLOCK_PllArm: #ifndef GET_FREQ_FROM_OBS - divSelect = (ANADIG_PLL->PLL_ARM_CTRL & ANADIG_PLL_PLL_ARM_CTRL_DIV_SELECT_MASK) >> - ANADIG_PLL_PLL_ARM_CTRL_DIV_SELECT_SHIFT; - postDiv = (ANADIG_PLL->PLL_ARM_CTRL & ANADIG_PLL_PLL_ARM_CTRL_POST_DIV_SEL_MASK) >> - ANADIG_PLL_PLL_ARM_CTRL_POST_DIV_SEL_SHIFT; - postDiv = (1 << (postDiv + 1)); - freq = XTAL_FREQ / (2 * postDiv); + divSelect = (ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK) >> + ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_SHIFT; + postDiv = (ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK) >> + ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_SHIFT; + postDiv = (1UL << (postDiv + 1UL)); + freq = XTAL_FREQ / (2UL * postDiv); freq *= divSelect; #else - freq = CLOCK_GetFreqFromObs(CCM_OBS_PLL_ARM_OUT); + freq = CLOCK_GetFreqFromObs(CCM_OBS_ARM_PLL_OUT); #endif break; case kCLOCK_PllSys1: #ifndef GET_FREQ_FROM_OBS freq = SYS_PLL1_FREQ; #else - freq = CLOCK_GetFreqFromObs(CCM_OBS_PLL_1G_OUT); + freq = CLOCK_GetFreqFromObs(CCM_OBS_SYS_PLL1_OUT); #endif break; case kCLOCK_PllSys2: #ifndef GET_FREQ_FROM_OBS - mfi = (ANADIG_PLL->PLL_528_MFI & ANADIG_PLL_PLL_528_MFI_MFI_MASK) >> ANADIG_PLL_PLL_528_MFI_MFI_SHIFT; - mfn = (ANADIG_PLL->PLL_528_MFN & ANADIG_PLL_PLL_528_MFN_MFN_MASK) >> ANADIG_PLL_PLL_528_MFN_MFN_SHIFT; - mfd = (ANADIG_PLL->PLL_528_MFD & ANADIG_PLL_PLL_528_MFD_MFD_MASK) >> ANADIG_PLL_PLL_528_MFD_MFD_SHIFT; - freq = XTAL_FREQ * (mfi + mfn / mfd); + freq = SYS_PLL2_FREQ; #else - freq = CLOCK_GetFreqFromObs(CCM_OBS_PLL_528_OUT); + freq = CLOCK_GetFreqFromObs(CCM_OBS_SYS_PLL2_OUT); #endif break; case kCLOCK_PllSys3: #ifndef GET_FREQ_FROM_OBS freq = SYS_PLL3_FREQ; #else - freq = CLOCK_GetFreqFromObs(CCM_OBS_PLL_480_OUT); + freq = CLOCK_GetFreqFromObs(CCM_OBS_SYS_PLL3_OUT); #endif break; case kCLOCK_PllAudio: @@ -963,15 +1428,7 @@ uint32_t CLOCK_GetFreq(clock_name_t name) { case kCLOCK_OscRc16M: #ifndef GET_FREQ_FROM_OBS - /* If select 16M. */ - if (0UL != (ANADIG_OSC->OSC_4M16M_CTRL & ANADIG_OSC_OSC_4M16M_CTRL_SEL_16M_MASK)) - { - freq = 16000000U; - } - else - { - freq = 4000000U; - } + freq = 16000000U; #else freq = CLOCK_GetFreqFromObs(CCM_OBS_OSC_RC_16M); #endif @@ -1046,10 +1503,10 @@ uint32_t CLOCK_GetFreq(clock_name_t name) freq = CLOCK_GetPllFreq(kCLOCK_PllSys1); break; case kCLOCK_SysPll1Div2: - freq = CLOCK_GetPllFreq(kCLOCK_PllSys1) / 2; + freq = CLOCK_GetPllFreq(kCLOCK_PllSys1) / 2UL; break; case kCLOCK_SysPll1Div5: - freq = CLOCK_GetPllFreq(kCLOCK_PllSys1) / 5; + freq = CLOCK_GetPllFreq(kCLOCK_PllSys1) / 5UL; break; case kCLOCK_AudioPll: case kCLOCK_AudioPllOut: @@ -1075,48 +1532,32 @@ void CLOCK_SetGroupConfig(clock_group_t group, const clock_group_config_t *confi { assert(group < kCLOCK_Group_Last); - CCM->CLOCK_GROUP[group].CONTROL = - ((config->clockOff ? CCM_CLOCK_GROUP_CONTROL_OFF_MASK : 0U) | - (config->resetDiv << CCM_CLOCK_GROUP_CONTROL_RSTDIV_SHIFT) | - (config->div0 << CCM_CLOCK_GROUP_CONTROL_DIV0_SHIFT) | (config->div1 << CCM_CLOCK_GROUP_CONTROL_DIV1_SHIFT) | - (config->div2 << CCM_CLOCK_GROUP_CONTROL_DIV2_SHIFT) | (config->div3 << CCM_CLOCK_GROUP_CONTROL_DIV3_SHIFT)); - - CCM->CLOCK_GROUP[group].CONTROL_EXTEND = ((config->div4 << CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV4_SHIFT) | - (config->div5 << CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV5_SHIFT) | - (config->div6 << CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV6_SHIFT) | - (config->div7 << CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV7_SHIFT) | - (config->div8 << CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV8_SHIFT) | - (config->div9 << CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV9_SHIFT) | - (config->div10 << CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV10_SHIFT) | - (config->div11 << CCM_CLOCK_GROUP_CONTROL_EXTEND_DIV11_SHIFT)); + CCM->CLOCK_GROUP[group].CONTROL = ((config->clockOff ? CCM_CLOCK_GROUP_CONTROL_OFF_MASK : 0U) | + (config->resetDiv << CCM_CLOCK_GROUP_CONTROL_RSTDIV_SHIFT) | + (config->div0 << CCM_CLOCK_GROUP_CONTROL_DIV0_SHIFT)); } -void CLOCK_TrimOscRc400M(void) +void CLOCK_OSC_TrimOscRc400M(bool enable, bool bypass, uint16_t trim) { - uint32_t trimRegValue = ANADIG_OSC->OSC_OTP_TRIM_VALUE_200M; - uint32_t trimEnable = (trimRegValue & (1u << 9)) ? 1 : 0; - uint32_t trimBypass = (trimRegValue & (1u << 8)) ? 1 : 0; - uint32_t trimValue = trimRegValue & 0xFF; - - if (trimEnable) + if (enable) { - ANADIG_MISC->VDDLPSR_AI400M_CTRL = 0x20; - ANADIG_MISC->VDDLPSR_AI400M_WDATA = (trimBypass << 10) | (trimValue << 24); + ANADIG_MISC->VDDLPSR_AI400M_CTRL = 0x20; + ANADIG_MISC->VDDLPSR_AI400M_WDATA = (bypass << 10) | (trim << 24); ANADIG_MISC->VDDLPSR_AI400M_CTRL |= 0x100; SDK_DelayAtLeastUs(1, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); ANADIG_MISC->VDDLPSR_AI400M_CTRL &= ~0x100; } } -void CLOCK_EnableOscRc400M(void) +void CLOCK_OSC_EnableOscRc400M(void) { - ANADIG_OSC->OSC_200M_CTRL1 &= ~0x1; - ANADIG_OSC->OSC_200M_CTRL2 |= 0x1; + ANADIG_OSC->OSC_400M_CTRL1 &= ~ANADIG_OSC_OSC_400M_CTRL1_PWD_MASK; + ANADIG_OSC->OSC_400M_CTRL2 |= ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_MASK; } uint32_t CLOCK_GetFreqFromObs(uint32_t obsSigIndex, uint32_t obsIndex) { - CCM_OBS->OBSERVE[obsIndex].CONTROL = CCM_OBS_OBSERVE_CONTROL_OFF_MASK; /* turn off detect */ + CCM_OBS->OBSERVE[obsIndex].CONTROL = CCM_OBS_OBSERVE_CONTROL_OFF_MASK; /* turn off detect */ CCM_OBS->OBSERVE[obsIndex].CONTROL_SET = CCM_OBS_OBSERVE_CONTROL_RESET_MASK; /* reset slice */ CCM_OBS->OBSERVE[obsIndex].CONTROL_CLR = CCM_OBS_OBSERVE_CONTROL_RAW_MASK; /* select raw obsSigIndex */ CCM_OBS->OBSERVE[obsIndex].CONTROL &= ~CCM_OBS_OBSERVE_CONTROL_SELECT_MASK; /* Select observed obsSigIndex */ @@ -1125,11 +1566,11 @@ uint32_t CLOCK_GetFreqFromObs(uint32_t obsSigIndex, uint32_t obsIndex) CCM_OBS->OBSERVE[obsIndex].CONTROL_CLR = CCM_OBS_OBSERVE_CONTROL_RESET_MASK | CCM_OBS_OBSERVE_CONTROL_OFF_MASK; /* unreset and turn on detect */ - while (CCM_OBS->OBSERVE[obsIndex].FREQUENCY_CURRENT == 0) + while (CCM_OBS->OBSERVE[obsIndex].FREQUENCY_CURRENT == 0UL) { } - return (CCM_OBS->OBSERVE[obsIndex].FREQUENCY_CURRENT * (CCM_OBS_DIV + 1)); + return (CCM_OBS->OBSERVE[obsIndex].FREQUENCY_CURRENT * ((uint32_t)CCM_OBS_DIV + 1UL)); } /*! brief Enable USB HS clock. @@ -1158,18 +1599,19 @@ bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq) */ bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) { - uint32_t phyPllDiv = 0U; + uint32_t phyPllDiv = 0U; uint16_t multiplier = 0U; + bool err = false; CLOCK_EnableClock(kCLOCK_Usb); USBPHY1->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; USBPHY1->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_POWER(1) | USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK); - if (480000000U % freq) + if ((480000000UL % freq) != 0UL) { return false; } - multiplier = 480000000 / freq; + multiplier = (uint16_t)(480000000UL / freq); switch (multiplier) { @@ -1215,18 +1657,25 @@ bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) } default: { - return false; + err = true; + break; } } + + if (err) + { + return false; + } + USBPHY1->PLL_SIC = (USBPHY1->PLL_SIC & ~(USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)) | phyPllDiv; USBPHY1->PLL_SIC_CLR = USBPHY_PLL_SIC_PLL_BYPASS_MASK; USBPHY1->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK); USBPHY1->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; - USBPHY1->PWD_SET = 0x0; + USBPHY1->PWD_SET = 0x0; - while (!(USBPHY1->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK)) + while (0UL == (USBPHY1->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK)) { } return true; @@ -1257,18 +1706,19 @@ bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq) } bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) { - uint32_t phyPllDiv = 0U; + uint32_t phyPllDiv = 0U; uint16_t multiplier = 0U; + bool err = false; CLOCK_EnableClock(kCLOCK_Usb); USBPHY2->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK; USBPHY2->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_POWER(1) | USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK); - if (480000000U % freq) + if ((480000000UL % freq) != 0UL) { return false; } - multiplier = 480000000 / freq; + multiplier = (uint16_t)(uint32_t)(480000000UL / freq); switch (multiplier) { @@ -1314,18 +1764,24 @@ bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq) } default: { - return false; + err = true; + break; } } + + if (err) + { + return false; + } USBPHY2->PLL_SIC = (USBPHY2->PLL_SIC & ~(USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)) | phyPllDiv; USBPHY2->PLL_SIC_CLR = USBPHY_PLL_SIC_PLL_BYPASS_MASK; USBPHY2->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK); USBPHY2->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK; - USBPHY2->PWD_SET = 0x0; + USBPHY2->PWD_SET = 0x0; - while (!(USBPHY2->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK)) + while (0UL == (USBPHY2->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK)) { } return true; @@ -1339,3 +1795,72 @@ void CLOCK_DisableUsbhs1PhyPllClock(void) USBPHY2->PLL_SIC_CLR = (USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK); USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */ } + +void CLOCK_OSCPLL_ControlBySetPointMode(clock_name_t name, uint16_t spValue, uint16_t stbyValue) +{ + /* Set control mode to unassigned mode. */ + CCM->OSCPLL[name].AUTHEN &= + ~(CCM_OSCPLL_AUTHEN_CPULPM_MASK | CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK | CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK); + /* Change SetPoint value in unassigned mode. */ + CCM->OSCPLL[name].SETPOINT = CCM_OSCPLL_SETPOINT_STANDBY(stbyValue) | CCM_OSCPLL_SETPOINT_SETPOINT(spValue); + /* Set control mode to SetPoint mode. */ + CCM->OSCPLL[name].AUTHEN |= CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK; +} + +void CLOCK_OSCPLL_ControlByCpuLowPowerMode(clock_name_t name, + uint8_t domainId, + clock_level_t level0, + clock_level_t level1) +{ + /* Set control mode to unassigned mode. */ + CCM->OSCPLL[name].AUTHEN &= + ~(CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK | CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK | CCM_OSCPLL_AUTHEN_CPULPM_MASK); + /* Change clock depend level for each domain in unassigned mode. */ + CCM->OSCPLL[name].DOMAINr = ((domainId & (1 << 1)) ? CCM_OSCPLL_DOMAIN_LEVEL1(level1) : 0) | + ((domainId & (1 << 0)) ? CCM_OSCPLL_DOMAIN_LEVEL0(level0) : 0); + /* Set control mode to CPU low power mode and update whitelist. */ + CCM->OSCPLL[name].AUTHEN = (CCM->OSCPLL[name].AUTHEN & ~CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK) | + CCM_OSCPLL_AUTHEN_CPULPM_MASK | CCM_OSCPLL_AUTHEN_WHITE_LIST(domainId); +} + +void CLOCK_ROOT_ControlBySetPointMode(clock_root_t name, const clock_root_setpoint_config_t *spTable) +{ + uint8_t i; + + /* Set control mode to unassigned mode. */ + CLOCK_ROOT_ControlByUnassignedMode(name); + /* Change SetPoint value in unassigned mode. */ + for (i = 0; i < 16; i++) + { + CLOCK_ROOT_ConfigSetPoint(name, i, spTable + i); + } + /* Set control mode to SetPoint mode. */ + CLOCK_ROOT_EnableSetPointControl(name); +} + +void CLOCK_LPCG_ControlBySetPointMode(clock_lpcg_t name, uint16_t spValue, uint16_t stbyValue) +{ + /* Set control mode to unassigned mode. */ + CCM->LPCG[name].AUTHEN &= + ~(CCM_LPCG_AUTHEN_CPULPM_MASK | CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK | CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK); + /* Change SetPoint value in unassigned mode. */ + CCM->LPCG[name].SETPOINT = CCM_LPCG_SETPOINT_STANDBY(stbyValue) | CCM_LPCG_SETPOINT_SETPOINT(spValue); + /* Set control mode to SetPoint mode. */ + CCM->LPCG[name].AUTHEN |= CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK; +} + +void CLOCK_LPCG_ControlByCpuLowPowerMode(clock_lpcg_t name, + uint8_t domainId, + clock_level_t level0, + clock_level_t level1) +{ + /* Set control mode to unassigned mode. */ + CCM->LPCG[name].AUTHEN &= + ~(CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK | CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK | CCM_LPCG_AUTHEN_CPULPM_MASK); + /* Change clock depend level for each domain in unassigned mode. */ + CCM->LPCG[name].DOMAINr = ((domainId & (1 << 1)) ? CCM_LPCG_DOMAIN_LEVEL1(level1) : 0) | + ((domainId & (1 << 0)) ? CCM_LPCG_DOMAIN_LEVEL0(level0) : 0); + /* Set control mode to CPU low power mode and update whitelist. */ + CCM->LPCG[name].AUTHEN = (CCM->LPCG[name].AUTHEN & ~CCM_LPCG_AUTHEN_WHITE_LIST_MASK) | CCM_LPCG_AUTHEN_CPULPM_MASK | + CCM_LPCG_AUTHEN_WHITE_LIST(domainId); +} diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_clock.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_clock.h index 352f940e512..c9e47147ed5 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_clock.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_clock.h @@ -40,7 +40,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief CLOCK driver version. */ -#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 1, 10)) +#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) /* Definition for delay API in clock driver, users can redefine it to the real application. */ #ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY @@ -51,45 +51,40 @@ #endif #endif -/* analog pll definition */ -#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U) -#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U) -#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U) - /*@}*/ /*! * @brief CCM registers offset. */ -#define CCSR_OFFSET 0x0C -#define CBCDR_OFFSET 0x14 -#define CBCMR_OFFSET 0x18 +#define CCSR_OFFSET 0x0C +#define CBCDR_OFFSET 0x14 +#define CBCMR_OFFSET 0x18 #define CSCMR1_OFFSET 0x1C #define CSCMR2_OFFSET 0x20 #define CSCDR1_OFFSET 0x24 -#define CDCDR_OFFSET 0x30 +#define CDCDR_OFFSET 0x30 #define CSCDR2_OFFSET 0x38 #define CSCDR3_OFFSET 0x3C -#define CACRR_OFFSET 0x10 +#define CACRR_OFFSET 0x10 #define CS1CDR_OFFSET 0x28 #define CS2CDR_OFFSET 0x2C /*! * @brief CCM Analog registers offset. */ -#define PLL_ARM_OFFSET 0x00 -#define PLL_SYS_OFFSET 0x30 -#define PLL_USB1_OFFSET 0x10 +#define ARM_PLL_OFFSET 0x00 +#define PLL_SYS_OFFSET 0x30 +#define PLL_USB1_OFFSET 0x10 #define PLL_AUDIO_OFFSET 0x70 #define PLL_VIDEO_OFFSET 0xA0 -#define PLL_ENET_OFFSET 0xE0 -#define PLL_USB2_OFFSET 0x20 +#define PLL_ENET_OFFSET 0xE0 +#define PLL_USB2_OFFSET 0x20 #define CCM_TUPLE(reg, shift, mask, busyShift) \ (int)((reg & 0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U)) -#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple)&0xFFU)))) -#define CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU) -#define CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU)))) +#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((tuple)&0xFFU)))) +#define CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8U) & 0x1FU) +#define CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 13U) & 0x1FFFU) << ((((tuple) >> 8U) & 0x1FU)))) #define CCM_TUPLE_BUSY_SHIFT(tuple) (((tuple) >> 26U) & 0x3FU) #define CCM_BUSY_WAIT (0x20U) @@ -97,7 +92,7 @@ /*! * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields. */ -#define CCM_ANALOG_TUPLE(reg, shift) (((reg & 0xFFFU) << 16U) | (shift)) +#define CCM_ANALOG_TUPLE(reg, shift) (((reg & 0xFFFU) << 16U) | (shift)) #define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)tuple) & 0x1FU) #define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \ (*((volatile uint32_t *)((uint32_t)base + (((uint32_t)tuple >> 16U) & 0xFFFU) + off))) @@ -107,19 +102,21 @@ * @brief SYS_PLL_FREQ frequency in Hz. */ #define SYS_PLL1_FREQ (1000000000U) -#define SYS_PLL2_FREQ (528000000U) -#define SYS_PLL3_FREQ (480000000U) -#define XTAL_FREQ (24000000U) +#define SYS_PLL2_MFI (22) +#define SYS_PLL2_FREQ (XTAL_FREQ * SYS_PLL2_MFI) +#define SYS_PLL3_MFI (20) +#define SYS_PLL3_FREQ (XTAL_FREQ * SYS_PLL3_MFI) +#define XTAL_FREQ (24000000U) /*! @brief Clock gate name array for ADC. */ -#define LPADC_CLOCKS \ - { \ +#define LPADC_CLOCKS \ + { \ kCLOCK_IpInvalid, kCLOCK_Lpadc1, kCLOCK_Lpadc2 \ } /*! @brief Clock gate name array for ADC. */ -#define ADC_ETC_CLOCKS \ - { \ +#define ADC_ETC_CLOCKS \ + { \ kCLOCK_Adc_Etc \ } @@ -131,7 +128,7 @@ /*! @brief Clock gate name array for DCDC. */ #define DCDC_CLOCKS \ - { \ + { \ kCLOCK_Dcdc \ } @@ -149,61 +146,68 @@ /*! @brief Clock gate name array for SSARC. */ #define SSARC_CLOCKS \ - { \ + { \ kCLOCK_Ssarc \ } /*! @brief Clock gate name array for WDOG. */ -#define WDOG_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2, kCLOCK_Wdog3, kCLOCK_Wdog4\ +#define WDOG_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2, kCLOCK_Wdog3, kCLOCK_Wdog4 \ } /*! @brief Clock gate name array for EWM. */ -#define EWM_CLOCKS \ - { \ +#define EWM_CLOCKS \ + { \ kCLOCK_Ewm0 \ } /*! @brief Clock gate name array for Sema. */ #define SEMA_CLOCKS \ - { \ + { \ kCLOCK_Sema \ } /*! @brief Clock gate name array for MU. */ -#define MU_CLOCKS \ - { \ - kCLOCK_Mu_A, kCLOCK_Mu_B \ +#if (__CORTEX_M == 7) +#define MU_CLOCKS \ + { \ + kCLOCK_Mu_A \ + } +#else +#define MU_CLOCKS \ + { \ + kCLOCK_Mu_B \ } +#endif /*! @brief Clock gate name array for EDMA. */ -#define EDMA_CLOCKS \ - { \ +#define EDMA_CLOCKS \ + { \ kCLOCK_Edma, kCLOCK_Edma_Lpsr \ } /*! @brief Clock gate name array for FLEXRAM. */ #define FLEXRAM_CLOCKS \ - { \ + { \ kCLOCK_Flexram \ } /*! @brief Clock gate name array for LMEM. */ #define LMEM_CLOCKS \ - { \ + { \ kCLOCK_Lmem \ } /*! @brief Clock gate name array for FLEXSPI. */ -#define FLEXSPI_CLOCKS \ - { \ +#define FLEXSPI_CLOCKS \ + { \ kCLOCK_IpInvalid, kCLOCK_Flexspi1, kCLOCK_Flexspi2 \ } /*! @brief Clock gate name array for RDC. */ -#define RDC_CLOCKS \ - { \ +#define RDC_CLOCKS \ + { \ kCLOCK_Rdc, kCLOCK_M7_Xrdc, kCLOCK_M4_Xrdc \ } @@ -227,13 +231,13 @@ /*! @brief Clock ip name array for IEE. */ #define IEE_CLOCKS \ - { \ + { \ kCLOCK_Iee \ } /*! @brief Clock ip name array for KEY_MANAGER. */ -#define KEYMANAGER_CLOCKS \ - { \ +#define KEYMANAGER_CLOCKS \ + { \ kCLOCK_Key_Manager \ } @@ -245,51 +249,50 @@ /*! @brief Clock ip name array for OCOTP. */ #define OCOTP_CLOCKS \ - { \ + { \ kCLOCK_Ocotp \ } /*! @brief Clock ip name array for CAAM. */ #define CAAM_CLOCKS \ { \ - kCLOCK_Caam\ + kCLOCK_Caam \ } /*! @brief Clock ip name array for XBAR. */ -#define XBAR_CLOCKS \ - { \ +#define XBAR_CLOCKS \ + { \ kCLOCK_IpInvalid, kCLOCK_Xbar1, kCLOCK_Xbar2, kCLOCK_Xbar3 \ } /*! @brief Clock ip name array for IOMUXC. */ -#define IOMUXC_CLOCKS \ - { \ +#define IOMUXC_CLOCKS \ + { \ kCLOCK_Iomuxc, kCLOCK_Iomuxc_Lpsr \ } /*! @brief Clock ip name array for GPIO. */ -#define GPIO_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, \ - kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, \ - kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, \ +#define GPIO_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, \ + kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, kCLOCK_Gpio, \ } /*! @brief Clock ip name array for KPP. */ #define KPP_CLOCKS \ - { \ + { \ kCLOCK_Kpp \ } /*! @brief Clock ip name array for FLEXIO. */ -#define FLEXIO_CLOCKS \ - { \ +#define FLEXIO_CLOCKS \ + { \ kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 \ } /*! @brief Clock ip name array for DAC. */ #define DAC_CLOCKS \ - { \ + { \ kCLOCK_Dac \ } @@ -300,16 +303,15 @@ } /*! @brief Clock ip name array for PIT. */ -#define PIT_CLOCKS \ - { \ +#define PIT_CLOCKS \ + { \ kCLOCK_IpInvalid, kCLOCK_Pit1, kCLOCK_Pit2 \ } /*! @brief Clock ip name array for GPT. */ -#define GPT_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2, kCLOCK_Gpt3, kCLOCK_Gpt4, \ - kCLOCK_Gpt5, kCLOCK_Gpt6 \ +#define GPT_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2, kCLOCK_Gpt3, kCLOCK_Gpt4, kCLOCK_Gpt5, kCLOCK_Gpt6 \ } /*! @brief Clock ip name array for QTIMER. */ @@ -343,56 +345,53 @@ } /*! @brief Clock ip name array for LPUART. */ -#define LPUART_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, \ - kCLOCK_Lpuart4, kCLOCK_Lpuart5, kCLOCK_Lpuart6, kCLOCK_Lpuart7, \ - kCLOCK_Lpuart8, kCLOCK_Lpuart9, kCLOCK_Lpuart10, kCLOCK_Lpuart11, \ - kCLOCK_Lpuart12 \ +#define LPUART_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \ + kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8, kCLOCK_Lpuart9, kCLOCK_Lpuart10, kCLOCK_Lpuart11, \ + kCLOCK_Lpuart12 \ } /*! @brief Clock ip name array for LPI2C. */ -#define LPI2C_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4, \ - kCLOCK_Lpi2c5, kCLOCK_Lpi2c6 \ +#define LPI2C_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4, kCLOCK_Lpi2c5, kCLOCK_Lpi2c6 \ } /*! @brief Clock ip name array for LPSPI. */ -#define LPSPI_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4, \ - kCLOCK_Lpspi5, kCLOCK_Lpspi6 \ +#define LPSPI_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4, kCLOCK_Lpspi5, kCLOCK_Lpspi6 \ } /*! @brief Clock ip name array for EMVSIM. */ -#define EMVSIM_CLOCKS \ - { \ - kCLOCK_IpInvalid, kCLOCK_Sim1, kCLOCK_Sim2 \ +#define EMVSIM_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Sim1, kCLOCK_Sim2 \ } /*! @brief Clock ip name array for ENET. */ -#define ENET_CLOCKS \ - { \ +#define ENET_CLOCKS \ + { \ kCLOCK_Enet, kCLOCK_Enet_1g \ } /*! @brief Clock ip name array for ENET_QOS. */ -#define ENETQOS_CLOCKS \ - { \ +#define ENETQOS_CLOCKS \ + { \ kCLOCK_Enet_Qos \ } /*! @brief Clock ip name array for USB. */ -#define USB_CLOCKS \ - { \ +#define USB_CLOCKS \ + { \ kCLOCK_Usb \ } -/*! @brief Clock ip name array for SDIO. */ -#define SDIO_CLOCKS \ - { \ - kCLOCK_Sdio \ +/*! @brief Clock ip name array for CDOG. */ +#define CDOG_CLOCKS \ + { \ + kCLOCK_Cdog \ } /*! @brief Clock ip name array for USDHC. */ @@ -402,8 +401,8 @@ } /*! @brief Clock ip name array for ASRC. */ -#define ASRC_CLOCKS \ - { \ +#define ASRC_CLOCKS \ + { \ kCLOCK_Asrc \ } @@ -426,8 +425,8 @@ } /*! @brief Clock ip name array for SAI. */ -#define SAI_CLOCKS \ - { \ +#define SAI_CLOCKS \ + { \ kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3, kCLOCK_Sai4 \ } @@ -439,32 +438,32 @@ /*! @brief Clock ip name array for GPU2d. */ #define GPU2D_CLOCKS \ - { \ + { \ kCLOCK_Gpu2d \ } /*! @brief Clock ip name array for LCDIF. */ #define LCDIF_CLOCKS \ { \ - kCLOCK_Lcdif \ + kCLOCK_Lcdif \ } /*! @brief Clock ip name array for LCDIFV2. */ #define LCDIFV2_CLOCKS \ - { \ + { \ kCLOCK_Lcdifv2 \ } /*! @brief Clock ip name array for MIPI_DSI. */ #define MIPI_DSI_HOST_CLOCKS \ - { \ - kCLOCK_Mipi_Dsi \ + { \ + kCLOCK_Mipi_Dsi \ } /*! @brief Clock ip name array for MIPI_CSI. */ #define MIPI_CSI2RX_CLOCKS \ - { \ - kCLOCK_Mipi_Csi \ + { \ + kCLOCK_Mipi_Csi \ } /*! @brief Clock ip name array for CSI. */ @@ -473,22 +472,16 @@ kCLOCK_Csi \ } -/*! @brief Clock ip name array for DCIC_MIPI. */ -#define DCIC_MIPI_CLOCKS \ - { \ - kCLOCK_Dcic_Mipi \ - } - -/*! @brief Clock ip name array for DCIC_LCD. */ -#define DCIC_LCD_CLOCKS \ - { \ - kCLOCK_Dcic_Lcd \ +/*! @brief Clock ip name array for DCIC. */ +#define DCIC_CLOCKS \ + { \ + kCLOCK_IpInvalid, kCLOCK_Dcic_Mipi, kCLOCK_Dcic_Lcd \ } /*! @brief Clock ip name array for DMAMUX_CLOCKS. */ -#define DMAMUX_CLOCKS \ - { \ - kCLOCK_Edma, kCLOCK_Edma_Lpsr \ +#define DMAMUX_CLOCKS \ + { \ + kCLOCK_Edma, kCLOCK_Edma_Lpsr \ } /*! @brief Clock ip name array for XBARA. */ @@ -506,145 +499,145 @@ /* Clock LPCG index */ typedef enum _clock_lpcg { - kCLOCK_M7 = 0, - kCLOCK_M4 = 1, - kCLOCK_Sim_M7 = 2, - kCLOCK_Sim_M = 3, - kCLOCK_Sim_Disp = 4, - kCLOCK_Sim_Per = 5, - kCLOCK_Sim_Lpsr = 6, - kCLOCK_Anadig = 7, - kCLOCK_Dcdc = 8, - kCLOCK_Src = 9, - kCLOCK_Ccm = 10, - kCLOCK_Gpc = 11, - kCLOCK_Ssarc = 12, - kCLOCK_Sim_R = 13, - kCLOCK_Wdog1 = 14, - kCLOCK_Wdog2 = 15, - kCLOCK_Wdog3 = 16, - kCLOCK_Wdog4 = 17, - kCLOCK_Ewm0 = 18, - kCLOCK_Sema = 19, - kCLOCK_Mu_A = 20, - kCLOCK_Mu_B = 21, - kCLOCK_Edma = 22, - kCLOCK_Edma_Lpsr = 23, - kCLOCK_Romcp = 24, - kCLOCK_Ocram = 25, - kCLOCK_Flexram = 26, - kCLOCK_Lmem = 27, - kCLOCK_Flexspi1 = 28, - kCLOCK_Flexspi2 = 29, - kCLOCK_Rdc = 30, - kCLOCK_M7_Xrdc = 31, - kCLOCK_M4_Xrdc = 32, - kCLOCK_Semc = 33, - kCLOCK_Xecc = 34, - kCLOCK_Iee = 35, + kCLOCK_M7 = 0, + kCLOCK_M4 = 1, + kCLOCK_Sim_M7 = 2, + kCLOCK_Sim_M = 3, + kCLOCK_Sim_Disp = 4, + kCLOCK_Sim_Per = 5, + kCLOCK_Sim_Lpsr = 6, + kCLOCK_Anadig = 7, + kCLOCK_Dcdc = 8, + kCLOCK_Src = 9, + kCLOCK_Ccm = 10, + kCLOCK_Gpc = 11, + kCLOCK_Ssarc = 12, + kCLOCK_Sim_R = 13, + kCLOCK_Wdog1 = 14, + kCLOCK_Wdog2 = 15, + kCLOCK_Wdog3 = 16, + kCLOCK_Wdog4 = 17, + kCLOCK_Ewm0 = 18, + kCLOCK_Sema = 19, + kCLOCK_Mu_A = 20, + kCLOCK_Mu_B = 21, + kCLOCK_Edma = 22, + kCLOCK_Edma_Lpsr = 23, + kCLOCK_Romcp = 24, + kCLOCK_Ocram = 25, + kCLOCK_Flexram = 26, + kCLOCK_Lmem = 27, + kCLOCK_Flexspi1 = 28, + kCLOCK_Flexspi2 = 29, + kCLOCK_Rdc = 30, + kCLOCK_M7_Xrdc = 31, + kCLOCK_M4_Xrdc = 32, + kCLOCK_Semc = 33, + kCLOCK_Xecc = 34, + kCLOCK_Iee = 35, kCLOCK_Key_Manager = 36, - kCLOCK_Puf = 36, - kCLOCK_Ocotp = 37, - kCLOCK_Snvs_Hp = 38, - kCLOCK_Snvs = 39, - kCLOCK_Caam = 40, - kCLOCK_Jtag_Mux = 41, - kCLOCK_Cstrace = 42, - kCLOCK_Xbar1 = 43, - kCLOCK_Xbar2 = 44, - kCLOCK_Xbar3 = 45, - kCLOCK_Aoi1 = 46, - kCLOCK_Aoi2 = 47, - kCLOCK_Adc_Etc = 48, - kCLOCK_Iomuxc = 49, + kCLOCK_Puf = 36, + kCLOCK_Ocotp = 37, + kCLOCK_Snvs_Hp = 38, + kCLOCK_Snvs = 39, + kCLOCK_Caam = 40, + kCLOCK_Jtag_Mux = 41, + kCLOCK_Cstrace = 42, + kCLOCK_Xbar1 = 43, + kCLOCK_Xbar2 = 44, + kCLOCK_Xbar3 = 45, + kCLOCK_Aoi1 = 46, + kCLOCK_Aoi2 = 47, + kCLOCK_Adc_Etc = 48, + kCLOCK_Iomuxc = 49, kCLOCK_Iomuxc_Lpsr = 50, - kCLOCK_Gpio = 51, - kCLOCK_Kpp = 52, - kCLOCK_Flexio1 = 53, - kCLOCK_Flexio2 = 54, - kCLOCK_Lpadc1 = 55, - kCLOCK_Lpadc2 = 56, - kCLOCK_Dac = 57, - kCLOCK_Acmp1 = 58, - kCLOCK_Acmp2 = 59, - kCLOCK_Acmp3 = 60, - kCLOCK_Acmp4 = 61, - kCLOCK_Pit1 = 62, - kCLOCK_Pit2 = 63, - kCLOCK_Gpt1 = 64, - kCLOCK_Gpt2 = 65, - kCLOCK_Gpt3 = 66, - kCLOCK_Gpt4 = 67, - kCLOCK_Gpt5 = 68, - kCLOCK_Gpt6 = 69, - kCLOCK_Qtimer1 = 70, - kCLOCK_Qtimer2 = 71, - kCLOCK_Qtimer3 = 72, - kCLOCK_Qtimer4 = 73, - kCLOCK_Enc1 = 74, - kCLOCK_Enc2 = 75, - kCLOCK_Enc3 = 76, - kCLOCK_Enc4 = 77, - kCLOCK_Hrtimer = 78, - kCLOCK_Pwm1 = 79, - kCLOCK_Pwm2 = 80, - kCLOCK_Pwm3 = 81, - kCLOCK_Pwm4 = 82, - kCLOCK_Can1 = 83, - kCLOCK_Can2 = 84, - kCLOCK_Can3 = 85, - kCLOCK_Lpuart1 = 86, - kCLOCK_Lpuart2 = 87, - kCLOCK_Lpuart3 = 88, - kCLOCK_Lpuart4 = 89, - kCLOCK_Lpuart5 = 90, - kCLOCK_Lpuart6 = 91, - kCLOCK_Lpuart7 = 92, - kCLOCK_Lpuart8 = 93, - kCLOCK_Lpuart9 = 94, - kCLOCK_Lpuart10 = 95, - kCLOCK_Lpuart11 = 96, - kCLOCK_Lpuart12 = 97, - kCLOCK_Lpi2c1 = 98, - kCLOCK_Lpi2c2 = 99, - kCLOCK_Lpi2c3 = 100, - kCLOCK_Lpi2c4 = 101, - kCLOCK_Lpi2c5 = 102, - kCLOCK_Lpi2c6 = 103, - kCLOCK_Lpspi1 = 104, - kCLOCK_Lpspi2 = 105, - kCLOCK_Lpspi3 = 106, - kCLOCK_Lpspi4 = 107, - kCLOCK_Lpspi5 = 108, - kCLOCK_Lpspi6 = 109, - kCLOCK_Sim1 = 110, - kCLOCK_Sim2 = 111, - kCLOCK_Enet = 112, - kCLOCK_Enet_1g = 113, - kCLOCK_Enet_Qos = 114, - kCLOCK_Usb = 115, - kCLOCK_Sdio = 116, - kCLOCK_Usdhc1 = 117, - kCLOCK_Usdhc2 = 118, - kCLOCK_Asrc = 119, - kCLOCK_Mqs = 120, - kCLOCK_Pdm = 121, - kCLOCK_Spdif = 122, - kCLOCK_Sai1 = 123, - kCLOCK_Sai2 = 124, - kCLOCK_Sai3 = 125, - kCLOCK_Sai4 = 126, - kCLOCK_Pxp = 127, - kCLOCK_Gpu2d = 128, - kCLOCK_Lcdif = 129, - kCLOCK_Lcdifv2 = 130, - kCLOCK_Mipi_Dsi = 131, - kCLOCK_Mipi_Csi = 132, - kCLOCK_Csi = 133, - kCLOCK_Dcic_Mipi = 134, - kCLOCK_Dcic_Lcd = 135, - kCLOCK_Video_Mux = 136, - kCLOCK_Uniq_Edt_I = 137, + kCLOCK_Gpio = 51, + kCLOCK_Kpp = 52, + kCLOCK_Flexio1 = 53, + kCLOCK_Flexio2 = 54, + kCLOCK_Lpadc1 = 55, + kCLOCK_Lpadc2 = 56, + kCLOCK_Dac = 57, + kCLOCK_Acmp1 = 58, + kCLOCK_Acmp2 = 59, + kCLOCK_Acmp3 = 60, + kCLOCK_Acmp4 = 61, + kCLOCK_Pit1 = 62, + kCLOCK_Pit2 = 63, + kCLOCK_Gpt1 = 64, + kCLOCK_Gpt2 = 65, + kCLOCK_Gpt3 = 66, + kCLOCK_Gpt4 = 67, + kCLOCK_Gpt5 = 68, + kCLOCK_Gpt6 = 69, + kCLOCK_Qtimer1 = 70, + kCLOCK_Qtimer2 = 71, + kCLOCK_Qtimer3 = 72, + kCLOCK_Qtimer4 = 73, + kCLOCK_Enc1 = 74, + kCLOCK_Enc2 = 75, + kCLOCK_Enc3 = 76, + kCLOCK_Enc4 = 77, + kCLOCK_Hrtimer = 78, + kCLOCK_Pwm1 = 79, + kCLOCK_Pwm2 = 80, + kCLOCK_Pwm3 = 81, + kCLOCK_Pwm4 = 82, + kCLOCK_Can1 = 83, + kCLOCK_Can2 = 84, + kCLOCK_Can3 = 85, + kCLOCK_Lpuart1 = 86, + kCLOCK_Lpuart2 = 87, + kCLOCK_Lpuart3 = 88, + kCLOCK_Lpuart4 = 89, + kCLOCK_Lpuart5 = 90, + kCLOCK_Lpuart6 = 91, + kCLOCK_Lpuart7 = 92, + kCLOCK_Lpuart8 = 93, + kCLOCK_Lpuart9 = 94, + kCLOCK_Lpuart10 = 95, + kCLOCK_Lpuart11 = 96, + kCLOCK_Lpuart12 = 97, + kCLOCK_Lpi2c1 = 98, + kCLOCK_Lpi2c2 = 99, + kCLOCK_Lpi2c3 = 100, + kCLOCK_Lpi2c4 = 101, + kCLOCK_Lpi2c5 = 102, + kCLOCK_Lpi2c6 = 103, + kCLOCK_Lpspi1 = 104, + kCLOCK_Lpspi2 = 105, + kCLOCK_Lpspi3 = 106, + kCLOCK_Lpspi4 = 107, + kCLOCK_Lpspi5 = 108, + kCLOCK_Lpspi6 = 109, + kCLOCK_Sim1 = 110, + kCLOCK_Sim2 = 111, + kCLOCK_Enet = 112, + kCLOCK_Enet_1g = 113, + kCLOCK_Enet_Qos = 114, + kCLOCK_Usb = 115, + kCLOCK_Cdog = 116, + kCLOCK_Usdhc1 = 117, + kCLOCK_Usdhc2 = 118, + kCLOCK_Asrc = 119, + kCLOCK_Mqs = 120, + kCLOCK_Pdm = 121, + kCLOCK_Spdif = 122, + kCLOCK_Sai1 = 123, + kCLOCK_Sai2 = 124, + kCLOCK_Sai3 = 125, + kCLOCK_Sai4 = 126, + kCLOCK_Pxp = 127, + kCLOCK_Gpu2d = 128, + kCLOCK_Lcdif = 129, + kCLOCK_Lcdifv2 = 130, + kCLOCK_Mipi_Dsi = 131, + kCLOCK_Mipi_Csi = 132, + kCLOCK_Csi = 133, + kCLOCK_Dcic_Mipi = 134, + kCLOCK_Dcic_Lcd = 135, + kCLOCK_Video_Mux = 136, + kCLOCK_Uniq_Edt_I = 137, kCLOCK_IpInvalid, } clock_lpcg_t; @@ -652,251 +645,152 @@ typedef enum _clock_lpcg /* Clock name */ typedef enum _clock_name { - kCLOCK_OscRc16M = 0, - kCLOCK_OscRc48M = 1, + kCLOCK_OscRc16M = 0, + kCLOCK_OscRc48M = 1, kCLOCK_OscRc48MDiv2 = 2, - kCLOCK_OscRc400M = 3, - kCLOCK_Osc24M = 4, - kCLOCK_Osc24MOut = 5, - kCLOCK_ArmPll = 6, - kCLOCK_ArmPllOut = 7, - kCLOCK_SysPll2 = 8, - kCLOCK_SysPll2Out = 9, - kCLOCK_SysPll2Pfd0 = 10, - kCLOCK_SysPll2Pfd1 = 11, - kCLOCK_SysPll2Pfd2 = 12, - kCLOCK_SysPll2Pfd3 = 13, - kCLOCK_SysPll3 = 14, - kCLOCK_SysPll3Out = 15, - kCLOCK_SysPll3Div2 = 16, - kCLOCK_SysPll3Pfd0 = 17, - kCLOCK_SysPll3Pfd1 = 18, - kCLOCK_SysPll3Pfd2 = 19, - kCLOCK_SysPll3Pfd3 = 20, - kCLOCK_SysPll1 = 21, - kCLOCK_SysPll1Out = 22, - kCLOCK_SysPll1Div2 = 23, - kCLOCK_SysPll1Div5 = 24, - kCLOCK_AudioPll = 25, - kCLOCK_AudioPllOut = 26, - kCLOCK_VideoPll = 27, - kCLOCK_VideoPllOut = 28, + kCLOCK_OscRc400M = 3, + kCLOCK_Osc24M = 4, + kCLOCK_Osc24MOut = 5, + kCLOCK_ArmPll = 6, + kCLOCK_ArmPllOut = 7, + kCLOCK_SysPll2 = 8, + kCLOCK_SysPll2Out = 9, + kCLOCK_SysPll2Pfd0 = 10, + kCLOCK_SysPll2Pfd1 = 11, + kCLOCK_SysPll2Pfd2 = 12, + kCLOCK_SysPll2Pfd3 = 13, + kCLOCK_SysPll3 = 14, + kCLOCK_SysPll3Out = 15, + kCLOCK_SysPll3Div2 = 16, + kCLOCK_SysPll3Pfd0 = 17, + kCLOCK_SysPll3Pfd1 = 18, + kCLOCK_SysPll3Pfd2 = 19, + kCLOCK_SysPll3Pfd3 = 20, + kCLOCK_SysPll1 = 21, + kCLOCK_SysPll1Out = 22, + kCLOCK_SysPll1Div2 = 23, + kCLOCK_SysPll1Div5 = 24, + kCLOCK_AudioPll = 25, + kCLOCK_AudioPllOut = 26, + kCLOCK_VideoPll = 27, + kCLOCK_VideoPllOut = 28, kCLOCK_CpuClk, kCLOCK_CoreSysClk, } clock_name_t; /* Clock OBSERVE SIGNALS */ -#define CCM_OBS_CCM_SOC_POWERDOWN 1, 2 -#define CCM_OBS_M7_1_CH_POWERDOWN 2, 2 -#define CCM_OBS_M7_2_CH_POWERDOWN 3, 2 -#define CCM_OBS_OSC_RC_16M_CH_SILENT_N 32, 0 -#define CCM_OBS_OSC_RC_48M_CH_SILENT_N 33, 0 -#define CCM_OBS_OSC_RC_48M_DIV2_CH_SILENT_N 34, 0 -#define CCM_OBS_OSC_RC_400M_CH_SILENT_N 35, 0 -#define CCM_OBS_OSC_24M_OUT_CH_SILENT_N 37, 0 -#define CCM_OBS_PLL_ARM_OUT_CH_SILENT_N 39, 1 -#define CCM_OBS_PLL_528_OUT_CH_SILENT_N 41, 1 -#define CCM_OBS_PLL_528_PFD0_CH_SILENT_N 42, 1 -#define CCM_OBS_PLL_528_PFD1_CH_SILENT_N 43, 1 -#define CCM_OBS_PLL_528_PFD2_CH_SILENT_N 44, 1 -#define CCM_OBS_PLL_528_PFD3_CH_SILENT_N 45, 1 -#define CCM_OBS_PLL_480_OUT_CH_SILENT_N 47, 1 -#define CCM_OBS_PLL_480_DIV2_CH_SILENT_N 48, 1 -#define CCM_OBS_PLL_480_PFD0_CH_SILENT_N 49, 1 -#define CCM_OBS_PLL_480_PFD1_CH_SILENT_N 50, 1 -#define CCM_OBS_PLL_480_PFD2_CH_SILENT_N 51, 1 -#define CCM_OBS_PLL_480_PFD3_CH_SILENT_N 52, 1 -#define CCM_OBS_PLL_1G_OUT_CH_SILENT_N 54, 1 -#define CCM_OBS_PLL_1G_DIV2_CH_SILENT_N 55, 1 -#define CCM_OBS_PLL_1G_DIV5_CH_SILENT_N 56, 1 -#define CCM_OBS_PLL_AUDIO_OUT_CH_SILENT_N 58, 0 -#define CCM_OBS_PLL_VIDEO_OUT_CH_SILENT_N 60, 1 -#define CCM_OBS_CCM_SOC_OSC_RC_16M_IN_USE 64, 2 -#define CCM_OBS_CCM_SOC_OSC_RC_48M_IN_USE 65, 2 -#define CCM_OBS_CCM_SOC_OSC_RC_48M_DIV2_IN_USE 66, 2 -#define CCM_OBS_CCM_SOC_OSC_RC_400M_IN_USE 67, 2 -#define CCM_OBS_CCM_SOC_OSC_24M_OUT_IN_USE 69, 2 -#define CCM_OBS_CCM_SOC_PLL_ARM_OUT_IN_USE 71, 2 -#define CCM_OBS_CCM_SOC_PLL_528_OUT_IN_USE 73, 2 -#define CCM_OBS_CCM_SOC_PLL_528_PFD0_IN_USE 74, 2 -#define CCM_OBS_CCM_SOC_PLL_528_PFD1_IN_USE 75, 2 -#define CCM_OBS_CCM_SOC_PLL_528_PFD2_IN_USE 76, 2 -#define CCM_OBS_CCM_SOC_PLL_528_PFD3_IN_USE 77, 2 -#define CCM_OBS_CCM_SOC_PLL_480_OUT_IN_USE 79, 2 -#define CCM_OBS_CCM_SOC_PLL_480_DIV2_IN_USE 80, 2 -#define CCM_OBS_CCM_SOC_PLL_480_PFD0_IN_USE 81, 2 -#define CCM_OBS_CCM_SOC_PLL_480_PFD1_IN_USE 82, 2 -#define CCM_OBS_CCM_SOC_PLL_480_PFD2_IN_USE 83, 2 -#define CCM_OBS_CCM_SOC_PLL_480_PFD3_IN_USE 84, 2 -#define CCM_OBS_CCM_SOC_PLL_1G_OUT_IN_USE 86, 2 -#define CCM_OBS_CCM_SOC_PLL_1G_DIV2_IN_USE 87, 2 -#define CCM_OBS_CCM_SOC_PLL_1G_DIV5_IN_USE 88, 2 -#define CCM_OBS_CCM_SOC_PLL_AUDIO_OUT_IN_USE 90, 2 -#define CCM_OBS_CCM_SOC_PLL_VIDEO_OUT_IN_USE 92, 2 -#define CCM_OBS_M7_CLK_ROOT 128, 4 -#define CCM_OBS_M4_CLK_ROOT 129, 0 -#define CCM_OBS_BUS_CLK_ROOT 130, 2 -#define CCM_OBS_BUS_LPSR_CLK_ROOT 131, 0 -#define CCM_OBS_SEMC_CLK_ROOT 132, 2 -#define CCM_OBS_CSSYS_CLK_ROOT 133, 2 -#define CCM_OBS_CSTRACE_CLK_ROOT 134, 2 -#define CCM_OBS_M4_SYSTICK_CLK_ROOT 135, 0 -#define CCM_OBS_M7_SYSTICK_CLK_ROOT 136, 2 -#define CCM_OBS_ADC1_CLK_ROOT 137, 2 -#define CCM_OBS_ADC2_CLK_ROOT 138, 2 -#define CCM_OBS_ACMP_CLK_ROOT 139, 2 -#define CCM_OBS_FLEXIO1_CLK_ROOT 140, 2 -#define CCM_OBS_FLEXIO2_CLK_ROOT 141, 2 -#define CCM_OBS_GPT1_CLK_ROOT 142, 2 -#define CCM_OBS_GPT2_CLK_ROOT 143, 2 -#define CCM_OBS_GPT3_CLK_ROOT 144, 2 -#define CCM_OBS_GPT4_CLK_ROOT 145, 2 -#define CCM_OBS_GPT5_CLK_ROOT 146, 2 -#define CCM_OBS_GPT6_CLK_ROOT 147, 2 -#define CCM_OBS_FLEXSPI1_CLK_ROOT 148, 2 -#define CCM_OBS_FLEXSPI2_CLK_ROOT 149, 2 -#define CCM_OBS_CAN1_CLK_ROOT 150, 2 -#define CCM_OBS_CAN2_CLK_ROOT 151, 2 -#define CCM_OBS_CAN3_CLK_ROOT 152, 0 -#define CCM_OBS_LPUART1_CLK_ROOT 153, 2 -#define CCM_OBS_LPUART2_CLK_ROOT 154, 2 -#define CCM_OBS_LPUART3_CLK_ROOT 155, 2 -#define CCM_OBS_LPUART4_CLK_ROOT 156, 2 -#define CCM_OBS_LPUART5_CLK_ROOT 157, 2 -#define CCM_OBS_LPUART6_CLK_ROOT 158, 2 -#define CCM_OBS_LPUART7_CLK_ROOT 159, 2 -#define CCM_OBS_LPUART8_CLK_ROOT 160, 2 -#define CCM_OBS_LPUART9_CLK_ROOT 161, 2 -#define CCM_OBS_LPUART10_CLK_ROOT 162, 2 -#define CCM_OBS_LPUART11_CLK_ROOT 163, 0 -#define CCM_OBS_LPUART12_CLK_ROOT 164, 0 -#define CCM_OBS_LPI2C1_CLK_ROOT 165, 2 -#define CCM_OBS_LPI2C2_CLK_ROOT 166, 2 -#define CCM_OBS_LPI2C3_CLK_ROOT 167, 2 -#define CCM_OBS_LPI2C4_CLK_ROOT 168, 2 -#define CCM_OBS_LPI2C5_CLK_ROOT 169, 0 -#define CCM_OBS_LPI2C6_CLK_ROOT 170, 0 -#define CCM_OBS_LPSPI1_CLK_ROOT 171, 2 -#define CCM_OBS_LPSPI2_CLK_ROOT 172, 2 -#define CCM_OBS_LPSPI3_CLK_ROOT 173, 2 -#define CCM_OBS_LPSPI4_CLK_ROOT 174, 2 -#define CCM_OBS_LPSPI5_CLK_ROOT 175, 0 -#define CCM_OBS_LPSPI6_CLK_ROOT 176, 0 -#define CCM_OBS_EMV1_CLK_ROOT 177, 2 -#define CCM_OBS_EMV2_CLK_ROOT 178, 2 -#define CCM_OBS_ENET1_CLK_ROOT 179, 2 -#define CCM_OBS_ENET2_CLK_ROOT 180, 2 -#define CCM_OBS_ENET_QOS_CLK_ROOT 181, 2 -#define CCM_OBS_ENET_25M_CLK_ROOT 182, 2 -#define CCM_OBS_ENET_TIMER1_CLK_ROOT 183, 2 -#define CCM_OBS_ENET_TIMER2_CLK_ROOT 184, 2 -#define CCM_OBS_ENET_TIMER3_CLK_ROOT 185, 2 -#define CCM_OBS_USDHC1_CLK_ROOT 186, 2 -#define CCM_OBS_USDHC2_CLK_ROOT 187, 2 -#define CCM_OBS_ASRC_CLK_ROOT 188, 2 -#define CCM_OBS_MQS_CLK_ROOT 189, 2 -#define CCM_OBS_MIC_CLK_ROOT 190, 0 -#define CCM_OBS_SPDIF_CLK_ROOT 191, 2 -#define CCM_OBS_SAI1_CLK_ROOT 192, 2 -#define CCM_OBS_SAI2_CLK_ROOT 193, 2 -#define CCM_OBS_SAI3_CLK_ROOT 194, 2 -#define CCM_OBS_SAI4_CLK_ROOT 195, 0 -#define CCM_OBS_GC355_CLK_ROOT 196, 2 -#define CCM_OBS_LCDIF_CLK_ROOT 197, 2 -#define CCM_OBS_LCDIFV2_CLK_ROOT 198, 2 -#define CCM_OBS_MIPI_REF_CLK_ROOT 199, 2 -#define CCM_OBS_MIPI_ESC_CLK_ROOT 200, 2 -#define CCM_OBS_CSI2_CLK_ROOT 201, 2 -#define CCM_OBS_CSI2_ESC_CLK_ROOT 202, 2 -#define CCM_OBS_CSI2_UI_CLK_ROOT 203, 2 -#define CCM_OBS_CSI_CLK_ROOT 204, 2 -#define CCM_OBS_CCM_CKO1_CLK_ROOT 205, 0 -#define CCM_OBS_CCM_CKO2_CLK_ROOT 206, 2 -#define CCM_OBS_CM7_CORE_STCLKEN 207, 4 -#define CCM_OBS_CCM_FLEXRAM_CLK_ROOT 208, 4 -#define CCM_OBS_MIPI_DSI_TXESC 209, 2 -#define CCM_OBS_MIPI_DSI_RXESC 210, 2 -#define CCM_OBS_OSC_RC_16M 224, 0 -#define CCM_OBS_OSC_RC_48M 225, 0 -#define CCM_OBS_OSC_RC_48M_DIV2 226, 0 -#define CCM_OBS_OSC_RC_400M 227, 0 -#define CCM_OBS_OSC_24M_OUT 229, 0 -#define CCM_OBS_PLL_ARM_OUT 231, 2 -#define CCM_OBS_PLL_528_OUT 233, 2 -#define CCM_OBS_PLL_528_PFD0 234, 2 -#define CCM_OBS_PLL_528_PFD1 235, 2 -#define CCM_OBS_PLL_528_PFD2 236, 2 -#define CCM_OBS_PLL_528_PFD3 237, 2 -#define CCM_OBS_PLL_480_OUT 239, 2 -#define CCM_OBS_PLL_480_DIV2 240, 2 -#define CCM_OBS_PLL_480_PFD0 241, 2 -#define CCM_OBS_PLL_480_PFD1 242, 2 -#define CCM_OBS_PLL_480_PFD2 243, 2 -#define CCM_OBS_PLL_480_PFD3 244, 2 -#define CCM_OBS_PLL_1G_OUT 246, 2 -#define CCM_OBS_PLL_1G_DIV2 247, 2 -#define CCM_OBS_PLL_1G_DIV5 248, 2 -#define CCM_OBS_PLL_AUDIO_OUT 250, 2 -#define CCM_OBS_PLL_VIDEO_OUT 252, 2 -#define CCM_OBS_OSC_32K 253, 0 -#define CCM_OBS_CPU_POWER_MODE_0_0 256, 0 -#define CCM_OBS_CPU_POWER_MODE_0_1 257, 0 -#define CCM_OBS_CPU_MODE_TRANS_LPCG_DONE_0 258, 0 -#define CCM_OBS_CPU_MODE_TRANS_LPCG_REQUEST_0 259, 0 -#define CCM_OBS_CPU_MODE_TRANS_OSCPLL_DONE_0 260, 0 -#define CCM_OBS_CPU_MODE_TRANS_OSCPLL_REQUEST_0 261, 0 -#define CCM_OBS_CPU_POWER_MODE_1_0 264, 0 -#define CCM_OBS_CPU_POWER_MODE_1_1 265, 0 -#define CCM_OBS_CPU_MODE_TRANS_LPCG_DONE_1 266, 0 -#define CCM_OBS_CPU_MODE_TRANS_LPCG_REQUEST_1 267, 0 -#define CCM_OBS_CPU_MODE_TRANS_OSCPLL_DONE_1 268, 0 -#define CCM_OBS_CPU_MODE_TRANS_OSCPLL_REQUEST_1 269, 0 -#define CCM_OBS_CPU_POWER_MODE_2_0 272, 0 -#define CCM_OBS_CPU_POWER_MODE_2_1 273, 0 -#define CCM_OBS_CPU_MODE_TRANS_LPCG_DONE_2 274, 0 -#define CCM_OBS_CPU_MODE_TRANS_LPCG_REQUEST_2 275, 0 -#define CCM_OBS_CPU_MODE_TRANS_OSCPLL_DONE_2 276, 0 -#define CCM_OBS_CPU_MODE_TRANS_OSCPLL_REQUEST_2 277, 0 -#define CCM_OBS_CPU_POWER_MODE_3_0 280, 0 -#define CCM_OBS_CPU_POWER_MODE_3_1 281, 0 -#define CCM_OBS_CPU_MODE_TRANS_LPCG_DONE_3 282, 0 -#define CCM_OBS_CPU_MODE_TRANS_LPCG_REQUEST_3 283, 0 -#define CCM_OBS_CPU_MODE_TRANS_OSCPLL_DONE_3 284, 0 -#define CCM_OBS_CPU_MODE_TRANS_OSCPLL_REQUEST_3 285, 0 -#define CCM_OBS_SETPOINT_0 288, 0 -#define CCM_OBS_SETPOINT_1 289, 0 -#define CCM_OBS_SETPOINT_2 290, 0 -#define CCM_OBS_SETPOINT_3 291, 0 -#define CCM_OBS_SETPOINT_TRANS_LPCG_OFF_DONE 292, 0 -#define CCM_OBS_SETPOINT_TRANS_LPCG_OFF_REQUEST 293, 0 -#define CCM_OBS_SETPOINT_TRANS_LPCG_ON_DONE 294, 0 -#define CCM_OBS_SETPOINT_TRANS_LPCG_ON_REQUEST 295, 0 -#define CCM_OBS_STANDBY_TRANS_LPCG_IN_DONE 296, 0 -#define CCM_OBS_STANDBY_TRANS_LPCG_IN_REQUEST 297, 0 -#define CCM_OBS_STANDBY_TRANS_LPCG_OUT_DONE 298, 0 -#define CCM_OBS_STANDBY_TRANS_LPCG_OUT_REQUEST 299, 0 -#define CCM_OBS_SETPOINT_TRANS_GROUP_DOWN_DONE 300, 0 -#define CCM_OBS_SETPOINT_TRANS_GROUP_DOWN_REQUES 301, 0 -#define CCM_OBS_SETPOINT_TRANS_GROUP_UP_DONE 302, 0 -#define CCM_OBS_SETPOINT_TRANS_GROUP_UP_REQUEST 303, 0 -#define CCM_OBS_SETPOINT_TRANS_ROOT_DOWN_DONE 304, 0 -#define CCM_OBS_SETPOINT_TRANS_ROOT_DOWN_REQUEST 305, 0 -#define CCM_OBS_SETPOINT_TRANS_ROOT_UP_DONE 306, 0 -#define CCM_OBS_SETPOINT_TRANS_ROOT_UP_REQUEST 307, 0 -#define CCM_OBS_SETPOINT_TRANS_OSCPLL_OFF_DONE 308, 0 -#define CCM_OBS_SETPOINT_TRANS_OSCPLL_OFF_REQUES 309, 0 -#define CCM_OBS_SETPOINT_TRANS_OSCPLL_ON_DONE 310, 0 -#define CCM_OBS_SETPOINT_TRANS_OSCPLL_ON_REQUEST 311, 0 -#define CCM_OBS_STANDBY_TRANS_OSCPLL_IN_DONE 312, 0 -#define CCM_OBS_STANDBY_TRANS_OSCPLL_IN_REQUEST 313, 0 -#define CCM_OBS_STANDBY_TRANS_OSCPLL_OUT_DONE 314, 0 -#define CCM_OBS_STANDBY_TRANS_OSCPLL_OUT_REQUEST 315, 0 - -#define CCM_OBS_DIV 3 +#define CCM_OBS_M7_CLK_ROOT 128, 4 +#define CCM_OBS_M4_CLK_ROOT 129, 0 +#define CCM_OBS_BUS_CLK_ROOT 130, 2 +#define CCM_OBS_BUS_LPSR_CLK_ROOT 131, 0 +#define CCM_OBS_SEMC_CLK_ROOT 132, 2 +#define CCM_OBS_CSSYS_CLK_ROOT 133, 2 +#define CCM_OBS_CSTRACE_CLK_ROOT 134, 2 +#define CCM_OBS_M4_SYSTICK_CLK_ROOT 135, 0 +#define CCM_OBS_M7_SYSTICK_CLK_ROOT 136, 2 +#define CCM_OBS_ADC1_CLK_ROOT 137, 2 +#define CCM_OBS_ADC2_CLK_ROOT 138, 2 +#define CCM_OBS_ACMP_CLK_ROOT 139, 2 +#define CCM_OBS_FLEXIO1_CLK_ROOT 140, 2 +#define CCM_OBS_FLEXIO2_CLK_ROOT 141, 2 +#define CCM_OBS_GPT1_CLK_ROOT 142, 2 +#define CCM_OBS_GPT2_CLK_ROOT 143, 2 +#define CCM_OBS_GPT3_CLK_ROOT 144, 2 +#define CCM_OBS_GPT4_CLK_ROOT 145, 2 +#define CCM_OBS_GPT5_CLK_ROOT 146, 2 +#define CCM_OBS_GPT6_CLK_ROOT 147, 2 +#define CCM_OBS_FLEXSPI1_CLK_ROOT 148, 2 +#define CCM_OBS_FLEXSPI2_CLK_ROOT 149, 2 +#define CCM_OBS_CAN1_CLK_ROOT 150, 2 +#define CCM_OBS_CAN2_CLK_ROOT 151, 2 +#define CCM_OBS_CAN3_CLK_ROOT 152, 0 +#define CCM_OBS_LPUART1_CLK_ROOT 153, 2 +#define CCM_OBS_LPUART2_CLK_ROOT 154, 2 +#define CCM_OBS_LPUART3_CLK_ROOT 155, 2 +#define CCM_OBS_LPUART4_CLK_ROOT 156, 2 +#define CCM_OBS_LPUART5_CLK_ROOT 157, 2 +#define CCM_OBS_LPUART6_CLK_ROOT 158, 2 +#define CCM_OBS_LPUART7_CLK_ROOT 159, 2 +#define CCM_OBS_LPUART8_CLK_ROOT 160, 2 +#define CCM_OBS_LPUART9_CLK_ROOT 161, 2 +#define CCM_OBS_LPUART10_CLK_ROOT 162, 2 +#define CCM_OBS_LPUART11_CLK_ROOT 163, 0 +#define CCM_OBS_LPUART12_CLK_ROOT 164, 0 +#define CCM_OBS_LPI2C1_CLK_ROOT 165, 2 +#define CCM_OBS_LPI2C2_CLK_ROOT 166, 2 +#define CCM_OBS_LPI2C3_CLK_ROOT 167, 2 +#define CCM_OBS_LPI2C4_CLK_ROOT 168, 2 +#define CCM_OBS_LPI2C5_CLK_ROOT 169, 0 +#define CCM_OBS_LPI2C6_CLK_ROOT 170, 0 +#define CCM_OBS_LPSPI1_CLK_ROOT 171, 2 +#define CCM_OBS_LPSPI2_CLK_ROOT 172, 2 +#define CCM_OBS_LPSPI3_CLK_ROOT 173, 2 +#define CCM_OBS_LPSPI4_CLK_ROOT 174, 2 +#define CCM_OBS_LPSPI5_CLK_ROOT 175, 0 +#define CCM_OBS_LPSPI6_CLK_ROOT 176, 0 +#define CCM_OBS_EMV1_CLK_ROOT 177, 2 +#define CCM_OBS_EMV2_CLK_ROOT 178, 2 +#define CCM_OBS_ENET1_CLK_ROOT 179, 2 +#define CCM_OBS_ENET2_CLK_ROOT 180, 2 +#define CCM_OBS_ENET_QOS_CLK_ROOT 181, 2 +#define CCM_OBS_ENET_25M_CLK_ROOT 182, 2 +#define CCM_OBS_ENET_TIMER1_CLK_ROOT 183, 2 +#define CCM_OBS_ENET_TIMER2_CLK_ROOT 184, 2 +#define CCM_OBS_ENET_TIMER3_CLK_ROOT 185, 2 +#define CCM_OBS_USDHC1_CLK_ROOT 186, 2 +#define CCM_OBS_USDHC2_CLK_ROOT 187, 2 +#define CCM_OBS_ASRC_CLK_ROOT 188, 2 +#define CCM_OBS_MQS_CLK_ROOT 189, 2 +#define CCM_OBS_MIC_CLK_ROOT 190, 0 +#define CCM_OBS_SPDIF_CLK_ROOT 191, 2 +#define CCM_OBS_SAI1_CLK_ROOT 192, 2 +#define CCM_OBS_SAI2_CLK_ROOT 193, 2 +#define CCM_OBS_SAI3_CLK_ROOT 194, 2 +#define CCM_OBS_SAI4_CLK_ROOT 195, 0 +#define CCM_OBS_GC355_CLK_ROOT 196, 2 +#define CCM_OBS_LCDIF_CLK_ROOT 197, 2 +#define CCM_OBS_LCDIFV2_CLK_ROOT 198, 2 +#define CCM_OBS_MIPI_REF_CLK_ROOT 199, 2 +#define CCM_OBS_MIPI_ESC_CLK_ROOT 200, 2 +#define CCM_OBS_CSI2_CLK_ROOT 201, 2 +#define CCM_OBS_CSI2_ESC_CLK_ROOT 202, 2 +#define CCM_OBS_CSI2_UI_CLK_ROOT 203, 2 +#define CCM_OBS_CSI_CLK_ROOT 204, 2 +#define CCM_OBS_CCM_CKO1_CLK_ROOT 205, 0 +#define CCM_OBS_CCM_CKO2_CLK_ROOT 206, 2 +#define CCM_OBS_CM7_CORE_STCLKEN 207, 4 +#define CCM_OBS_CCM_FLEXRAM_CLK_ROOT 208, 4 +#define CCM_OBS_MIPI_DSI_TXESC 209, 2 +#define CCM_OBS_MIPI_DSI_RXESC 210, 2 +#define CCM_OBS_OSC_RC_16M 224, 0 +#define CCM_OBS_OSC_RC_48M 225, 0 +#define CCM_OBS_OSC_RC_48M_DIV2 226, 0 +#define CCM_OBS_OSC_RC_400M 227, 0 +#define CCM_OBS_OSC_24M_OUT 229, 0 +#define CCM_OBS_ARM_PLL_OUT 231, 2 +#define CCM_OBS_SYS_PLL2_OUT 233, 2 +#define CCM_OBS_SYS_PLL2_PFD0 234, 2 +#define CCM_OBS_SYS_PLL2_PFD1 235, 2 +#define CCM_OBS_SYS_PLL2_PFD2 236, 2 +#define CCM_OBS_SYS_PLL2_PFD3 237, 2 +#define CCM_OBS_SYS_PLL3_OUT 239, 2 +#define CCM_OBS_SYS_PLL3_DIV2 240, 2 +#define CCM_OBS_SYS_PLL3_PFD0 241, 2 +#define CCM_OBS_SYS_PLL3_PFD1 242, 2 +#define CCM_OBS_SYS_PLL3_PFD2 243, 2 +#define CCM_OBS_SYS_PLL3_PFD3 244, 2 +#define CCM_OBS_SYS_PLL1_OUT 246, 2 +#define CCM_OBS_SYS_PLL1_DIV2 247, 2 +#define CCM_OBS_SYS_PLL1_DIV5 248, 2 +#define CCM_OBS_PLL_AUDIO_OUT 250, 2 +#define CCM_OBS_PLL_VIDEO_OUT 252, 2 + +#define CCM_OBS_DIV 3 /* Clock Source Definitions */ -#define ROOT_CLOCK_SOURCES \ - { /*SRC0, SRC1, SRC2, SRC3, SRC4, SRC5, SRC6, SRC7, name index */ \ +/* clang-format off */ +static const clock_name_t source[][8] = { + /*SRC0, SRC1, SRC2, SRC3, SRC4, SRC5, SRC6, SRC7, name index */ \ {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_ArmPllOut, kCLOCK_SysPll1Out, kCLOCK_SysPll3Out, kCLOCK_VideoPllOut}, /* M7 0 */ \ {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Pfd3, kCLOCK_SysPll3Out, kCLOCK_SysPll2Out, kCLOCK_SysPll1Div5}, /* M4 1 */ \ {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll3Out, kCLOCK_SysPll1Div5, kCLOCK_SysPll2Out, kCLOCK_SysPll2Pfd3}, /* BUS 2 */ \ @@ -976,92 +870,91 @@ typedef enum _clock_name {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll3Out, kCLOCK_SysPll3Pfd1, kCLOCK_VideoPllOut}, /* CSI 76 */ \ {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Pfd2, kCLOCK_SysPll2Out, kCLOCK_SysPll3Pfd1, kCLOCK_SysPll1Div5}, /* CKO1 77 */ \ {kCLOCK_OscRc48MDiv2, kCLOCK_Osc24MOut, kCLOCK_OscRc400M, kCLOCK_OscRc16M, kCLOCK_SysPll2Pfd3, kCLOCK_OscRc48M, kCLOCK_SysPll3Pfd1, kCLOCK_AudioPllOut} /* CKO2 78 */ \ - } - - +}; +/* clang-format on */ /* Root clock index */ typedef enum _clock_root { - kCLOCK_Root_M7 = 0, - kCLOCK_Root_M4 = 1, - kCLOCK_Root_Bus = 2, - kCLOCK_Root_Bus_Lpsr = 3, - kCLOCK_Root_Semc = 4, - kCLOCK_Root_Cssys = 5, - kCLOCK_Root_Cstrace = 6, - kCLOCK_Root_M4_Systick = 7, - kCLOCK_Root_M7_Systick = 8, - kCLOCK_Root_Adc1 = 9, - kCLOCK_Root_Adc2 = 10, - kCLOCK_Root_Acmp = 11, - kCLOCK_Root_Flexio1 = 12, - kCLOCK_Root_Flexio2 = 13, - kCLOCK_Root_Gpt1 = 14, - kCLOCK_Root_Gpt2 = 15, - kCLOCK_Root_Gpt3 = 16, - kCLOCK_Root_Gpt4 = 17, - kCLOCK_Root_Gpt5 = 18, - kCLOCK_Root_Gpt6 = 19, - kCLOCK_Root_Flexspi1 = 20, - kCLOCK_Root_Flexspi2 = 21, - kCLOCK_Root_Can1 = 22, - kCLOCK_Root_Can2 = 23, - kCLOCK_Root_Can3 = 24, - kCLOCK_Root_Lpuart1 = 25, - kCLOCK_Root_Lpuart2 = 26, - kCLOCK_Root_Lpuart3 = 27, - kCLOCK_Root_Lpuart4 = 28, - kCLOCK_Root_Lpuart5 = 29, - kCLOCK_Root_Lpuart6 = 30, - kCLOCK_Root_Lpuart7 = 31, - kCLOCK_Root_Lpuart8 = 32, - kCLOCK_Root_Lpuart9 = 33, - kCLOCK_Root_Lpuart10 = 34, - kCLOCK_Root_Lpuart11 = 35, - kCLOCK_Root_Lpuart12 = 36, - kCLOCK_Root_Lpi2c1 = 37, - kCLOCK_Root_Lpi2c2 = 38, - kCLOCK_Root_Lpi2c3 = 39, - kCLOCK_Root_Lpi2c4 = 40, - kCLOCK_Root_Lpi2c5 = 41, - kCLOCK_Root_Lpi2c6 = 42, - kCLOCK_Root_Lpspi1 = 43, - kCLOCK_Root_Lpspi2 = 44, - kCLOCK_Root_Lpspi3 = 45, - kCLOCK_Root_Lpspi4 = 46, - kCLOCK_Root_Lpspi5 = 47, - kCLOCK_Root_Lpspi6 = 48, - kCLOCK_Root_Emv1 = 49, - kCLOCK_Root_Emv2 = 50, - kCLOCK_Root_Enet1 = 51, - kCLOCK_Root_Enet2 = 52, - kCLOCK_Root_Enet_Qos = 53, - kCLOCK_Root_Enet_25m = 54, + kCLOCK_Root_M7 = 0, + kCLOCK_Root_M4 = 1, + kCLOCK_Root_Bus = 2, + kCLOCK_Root_Bus_Lpsr = 3, + kCLOCK_Root_Semc = 4, + kCLOCK_Root_Cssys = 5, + kCLOCK_Root_Cstrace = 6, + kCLOCK_Root_M4_Systick = 7, + kCLOCK_Root_M7_Systick = 8, + kCLOCK_Root_Adc1 = 9, + kCLOCK_Root_Adc2 = 10, + kCLOCK_Root_Acmp = 11, + kCLOCK_Root_Flexio1 = 12, + kCLOCK_Root_Flexio2 = 13, + kCLOCK_Root_Gpt1 = 14, + kCLOCK_Root_Gpt2 = 15, + kCLOCK_Root_Gpt3 = 16, + kCLOCK_Root_Gpt4 = 17, + kCLOCK_Root_Gpt5 = 18, + kCLOCK_Root_Gpt6 = 19, + kCLOCK_Root_Flexspi1 = 20, + kCLOCK_Root_Flexspi2 = 21, + kCLOCK_Root_Can1 = 22, + kCLOCK_Root_Can2 = 23, + kCLOCK_Root_Can3 = 24, + kCLOCK_Root_Lpuart1 = 25, + kCLOCK_Root_Lpuart2 = 26, + kCLOCK_Root_Lpuart3 = 27, + kCLOCK_Root_Lpuart4 = 28, + kCLOCK_Root_Lpuart5 = 29, + kCLOCK_Root_Lpuart6 = 30, + kCLOCK_Root_Lpuart7 = 31, + kCLOCK_Root_Lpuart8 = 32, + kCLOCK_Root_Lpuart9 = 33, + kCLOCK_Root_Lpuart10 = 34, + kCLOCK_Root_Lpuart11 = 35, + kCLOCK_Root_Lpuart12 = 36, + kCLOCK_Root_Lpi2c1 = 37, + kCLOCK_Root_Lpi2c2 = 38, + kCLOCK_Root_Lpi2c3 = 39, + kCLOCK_Root_Lpi2c4 = 40, + kCLOCK_Root_Lpi2c5 = 41, + kCLOCK_Root_Lpi2c6 = 42, + kCLOCK_Root_Lpspi1 = 43, + kCLOCK_Root_Lpspi2 = 44, + kCLOCK_Root_Lpspi3 = 45, + kCLOCK_Root_Lpspi4 = 46, + kCLOCK_Root_Lpspi5 = 47, + kCLOCK_Root_Lpspi6 = 48, + kCLOCK_Root_Emv1 = 49, + kCLOCK_Root_Emv2 = 50, + kCLOCK_Root_Enet1 = 51, + kCLOCK_Root_Enet2 = 52, + kCLOCK_Root_Enet_Qos = 53, + kCLOCK_Root_Enet_25m = 54, kCLOCK_Root_Enet_Timer1 = 55, kCLOCK_Root_Enet_Timer2 = 56, kCLOCK_Root_Enet_Timer3 = 57, - kCLOCK_Root_Usdhc1 = 58, - kCLOCK_Root_Usdhc2 = 59, - kCLOCK_Root_Asrc = 60, - kCLOCK_Root_Mqs = 61, - kCLOCK_Root_Mic = 62, - kCLOCK_Root_Spdif = 63, - kCLOCK_Root_Sai1 = 64, - kCLOCK_Root_Sai2 = 65, - kCLOCK_Root_Sai3 = 66, - kCLOCK_Root_Sai4 = 67, - kCLOCK_Root_Gc355 = 68, - kCLOCK_Root_Lcdif = 69, - kCLOCK_Root_Lcdifv2 = 70, - kCLOCK_Root_Mipi_Ref = 71, - kCLOCK_Root_Mipi_Esc = 72, - kCLOCK_Root_Csi2 = 73, - kCLOCK_Root_Csi2_Esc = 74, - kCLOCK_Root_Csi2_Ui = 75, - kCLOCK_Root_Csi = 76, - kCLOCK_Root_Cko1 = 77, - kCLOCK_Root_Cko2 = 78, + kCLOCK_Root_Usdhc1 = 58, + kCLOCK_Root_Usdhc2 = 59, + kCLOCK_Root_Asrc = 60, + kCLOCK_Root_Mqs = 61, + kCLOCK_Root_Mic = 62, + kCLOCK_Root_Spdif = 63, + kCLOCK_Root_Sai1 = 64, + kCLOCK_Root_Sai2 = 65, + kCLOCK_Root_Sai3 = 66, + kCLOCK_Root_Sai4 = 67, + kCLOCK_Root_Gc355 = 68, + kCLOCK_Root_Lcdif = 69, + kCLOCK_Root_Lcdifv2 = 70, + kCLOCK_Root_Mipi_Ref = 71, + kCLOCK_Root_Mipi_Esc = 72, + kCLOCK_Root_Csi2 = 73, + kCLOCK_Root_Csi2_Esc = 74, + kCLOCK_Root_Csi2_Ui = 75, + kCLOCK_Root_Csi = 76, + kCLOCK_Root_Cko1 = 77, + kCLOCK_Root_Cko2 = 78, } clock_root_t; /*! @@ -1071,871 +964,793 @@ typedef enum _clock_root_mux_source { /* M7 */ kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_M7_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_M7_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_M7_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_M7_ClockRoot_MuxArmPllOut = 4U, - kCLOCK_M7_ClockRoot_MuxSysPll1Out = 5U, - kCLOCK_M7_ClockRoot_MuxSysPll3Out = 6U, - kCLOCK_M7_ClockRoot_MuxVideoPllOut = 7U, - + kCLOCK_M7_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_M7_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_M7_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_M7_ClockRoot_MuxArmPllOut = 4U, + kCLOCK_M7_ClockRoot_MuxSysPll1Out = 5U, + kCLOCK_M7_ClockRoot_MuxSysPll3Out = 6U, + kCLOCK_M7_ClockRoot_MuxVideoPllOut = 7U, /* M4 */ kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_M4_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_M4_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_M4_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3 = 4U, - kCLOCK_M4_ClockRoot_MuxSysPll3Out = 5U, - kCLOCK_M4_ClockRoot_MuxSysPll2Out = 6U, - kCLOCK_M4_ClockRoot_MuxSysPll1Div5 = 7U, - + kCLOCK_M4_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_M4_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_M4_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3 = 4U, + kCLOCK_M4_ClockRoot_MuxSysPll3Out = 5U, + kCLOCK_M4_ClockRoot_MuxSysPll2Out = 6U, + kCLOCK_M4_ClockRoot_MuxSysPll1Div5 = 7U, /* BUS */ kCLOCK_BUS_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_BUS_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_BUS_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_BUS_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_BUS_ClockRoot_MuxSysPll3Out = 4U, - kCLOCK_BUS_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_BUS_ClockRoot_MuxSysPll2Out = 6U, - kCLOCK_BUS_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_BUS_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_BUS_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_BUS_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_BUS_ClockRoot_MuxSysPll3Out = 4U, + kCLOCK_BUS_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_BUS_ClockRoot_MuxSysPll2Out = 6U, + kCLOCK_BUS_ClockRoot_MuxSysPll2Pfd3 = 7U, /* BUS_LPSR */ kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_BUS_LPSR_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Pfd3 = 4U, - kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out = 5U, - kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll2Out = 6U, - kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll1Div5 = 7U, - + kCLOCK_BUS_LPSR_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Pfd3 = 4U, + kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out = 5U, + kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll2Out = 6U, + kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll1Div5 = 7U, /* SEMC */ kCLOCK_SEMC_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_SEMC_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_SEMC_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_SEMC_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_SEMC_ClockRoot_MuxSysPll1Div5 = 4U, - kCLOCK_SEMC_ClockRoot_MuxSysPll2Out = 5U, - kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd1 = 6U, - kCLOCK_SEMC_ClockRoot_MuxSysPll3Pfd0 = 7U, - + kCLOCK_SEMC_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_SEMC_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_SEMC_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_SEMC_ClockRoot_MuxSysPll1Div5 = 4U, + kCLOCK_SEMC_ClockRoot_MuxSysPll2Out = 5U, + kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd1 = 6U, + kCLOCK_SEMC_ClockRoot_MuxSysPll3Pfd0 = 7U, /* CSSYS */ kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_CSSYS_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_CSSYS_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_CSSYS_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_CSSYS_ClockRoot_MuxSysPll3Div2 = 4U, - kCLOCK_CSSYS_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_CSSYS_ClockRoot_MuxSysPll2Out = 6U, - kCLOCK_CSSYS_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_CSSYS_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_CSSYS_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_CSSYS_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_CSSYS_ClockRoot_MuxSysPll3Div2 = 4U, + kCLOCK_CSSYS_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_CSSYS_ClockRoot_MuxSysPll2Out = 6U, + kCLOCK_CSSYS_ClockRoot_MuxSysPll2Pfd3 = 7U, /* CSTRACE */ kCLOCK_CSTRACE_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_CSTRACE_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_CSTRACE_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_CSTRACE_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_CSTRACE_ClockRoot_MuxSysPll3Div2 = 4U, - kCLOCK_CSTRACE_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Pfd1 = 6U, - kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out = 7U, - + kCLOCK_CSTRACE_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_CSTRACE_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_CSTRACE_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_CSTRACE_ClockRoot_MuxSysPll3Div2 = 4U, + kCLOCK_CSTRACE_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Pfd1 = 6U, + kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out = 7U, /* M4_SYSTICK */ kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_M4_SYSTICK_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll3Pfd3 = 4U, - kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll3Out = 5U, - kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll2Pfd0 = 6U, - kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll1Div5 = 7U, - + kCLOCK_M4_SYSTICK_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll3Pfd3 = 4U, + kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll3Out = 5U, + kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll2Pfd0 = 6U, + kCLOCK_M4_SYSTICK_ClockRoot_MuxSysPll1Div5 = 7U, /* M7_SYSTICK */ kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_M7_SYSTICK_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll2Out = 4U, - kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll3Div2 = 5U, - kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll1Div5 = 6U, - kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll2Pfd0 = 7U, - + kCLOCK_M7_SYSTICK_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll2Out = 4U, + kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll3Div2 = 5U, + kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll1Div5 = 6U, + kCLOCK_M7_SYSTICK_ClockRoot_MuxSysPll2Pfd0 = 7U, /* ADC1 */ kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_ADC1_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_ADC1_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_ADC1_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_ADC1_ClockRoot_MuxSysPll3Div2 = 4U, - kCLOCK_ADC1_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_ADC1_ClockRoot_MuxSysPll2Out = 6U, - kCLOCK_ADC1_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_ADC1_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_ADC1_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_ADC1_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_ADC1_ClockRoot_MuxSysPll3Div2 = 4U, + kCLOCK_ADC1_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_ADC1_ClockRoot_MuxSysPll2Out = 6U, + kCLOCK_ADC1_ClockRoot_MuxSysPll2Pfd3 = 7U, /* ADC2 */ kCLOCK_ADC2_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_ADC2_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_ADC2_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_ADC2_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_ADC2_ClockRoot_MuxSysPll3Div2 = 4U, - kCLOCK_ADC2_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_ADC2_ClockRoot_MuxSysPll2Out = 6U, - kCLOCK_ADC2_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_ADC2_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_ADC2_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_ADC2_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_ADC2_ClockRoot_MuxSysPll3Div2 = 4U, + kCLOCK_ADC2_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_ADC2_ClockRoot_MuxSysPll2Out = 6U, + kCLOCK_ADC2_ClockRoot_MuxSysPll2Pfd3 = 7U, /* ACMP */ kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_ACMP_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_ACMP_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_ACMP_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_ACMP_ClockRoot_MuxSysPll3Out = 4U, - kCLOCK_ACMP_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_ACMP_ClockRoot_MuxAudioPllOut = 6U, - kCLOCK_ACMP_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_ACMP_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_ACMP_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_ACMP_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_ACMP_ClockRoot_MuxSysPll3Out = 4U, + kCLOCK_ACMP_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_ACMP_ClockRoot_MuxAudioPllOut = 6U, + kCLOCK_ACMP_ClockRoot_MuxSysPll2Pfd3 = 7U, /* FLEXIO1 */ kCLOCK_FLEXIO1_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_FLEXIO1_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_FLEXIO1_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_FLEXIO1_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_FLEXIO1_ClockRoot_MuxSysPll3Div2 = 4U, - kCLOCK_FLEXIO1_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_FLEXIO1_ClockRoot_MuxSysPll2Out = 6U, - kCLOCK_FLEXIO1_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_FLEXIO1_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_FLEXIO1_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_FLEXIO1_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_FLEXIO1_ClockRoot_MuxSysPll3Div2 = 4U, + kCLOCK_FLEXIO1_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_FLEXIO1_ClockRoot_MuxSysPll2Out = 6U, + kCLOCK_FLEXIO1_ClockRoot_MuxSysPll2Pfd3 = 7U, /* FLEXIO2 */ kCLOCK_FLEXIO2_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_FLEXIO2_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_FLEXIO2_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_FLEXIO2_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_FLEXIO2_ClockRoot_MuxSysPll3Div2 = 4U, - kCLOCK_FLEXIO2_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_FLEXIO2_ClockRoot_MuxSysPll2Out = 6U, - kCLOCK_FLEXIO2_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_FLEXIO2_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_FLEXIO2_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_FLEXIO2_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_FLEXIO2_ClockRoot_MuxSysPll3Div2 = 4U, + kCLOCK_FLEXIO2_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_FLEXIO2_ClockRoot_MuxSysPll2Out = 6U, + kCLOCK_FLEXIO2_ClockRoot_MuxSysPll2Pfd3 = 7U, /* GPT1 */ kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_GPT1_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_GPT1_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_GPT1_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_GPT1_ClockRoot_MuxSysPll3Div2 = 4U, - kCLOCK_GPT1_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_GPT1_ClockRoot_MuxSysPll3Pfd2 = 6U, - kCLOCK_GPT1_ClockRoot_MuxSysPll3Pfd3 = 7U, - + kCLOCK_GPT1_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_GPT1_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_GPT1_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_GPT1_ClockRoot_MuxSysPll3Div2 = 4U, + kCLOCK_GPT1_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_GPT1_ClockRoot_MuxSysPll3Pfd2 = 6U, + kCLOCK_GPT1_ClockRoot_MuxSysPll3Pfd3 = 7U, /* GPT2 */ kCLOCK_GPT2_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_GPT2_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_GPT2_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_GPT2_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_GPT2_ClockRoot_MuxSysPll3Div2 = 4U, - kCLOCK_GPT2_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_GPT2_ClockRoot_MuxAudioPllOut = 6U, - kCLOCK_GPT2_ClockRoot_MuxVideoPllOut = 7U, - + kCLOCK_GPT2_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_GPT2_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_GPT2_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_GPT2_ClockRoot_MuxSysPll3Div2 = 4U, + kCLOCK_GPT2_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_GPT2_ClockRoot_MuxAudioPllOut = 6U, + kCLOCK_GPT2_ClockRoot_MuxVideoPllOut = 7U, /* GPT3 */ kCLOCK_GPT3_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_GPT3_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_GPT3_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_GPT3_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_GPT3_ClockRoot_MuxSysPll3Div2 = 4U, - kCLOCK_GPT3_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_GPT3_ClockRoot_MuxAudioPllOut = 6U, - kCLOCK_GPT3_ClockRoot_MuxVideoPllOut = 7U, - + kCLOCK_GPT3_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_GPT3_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_GPT3_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_GPT3_ClockRoot_MuxSysPll3Div2 = 4U, + kCLOCK_GPT3_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_GPT3_ClockRoot_MuxAudioPllOut = 6U, + kCLOCK_GPT3_ClockRoot_MuxVideoPllOut = 7U, /* GPT4 */ kCLOCK_GPT4_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_GPT4_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_GPT4_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_GPT4_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_GPT4_ClockRoot_MuxSysPll3Div2 = 4U, - kCLOCK_GPT4_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_GPT4_ClockRoot_MuxSysPll3Pfd2 = 6U, - kCLOCK_GPT4_ClockRoot_MuxSysPll3Pfd3 = 7U, - + kCLOCK_GPT4_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_GPT4_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_GPT4_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_GPT4_ClockRoot_MuxSysPll3Div2 = 4U, + kCLOCK_GPT4_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_GPT4_ClockRoot_MuxSysPll3Pfd2 = 6U, + kCLOCK_GPT4_ClockRoot_MuxSysPll3Pfd3 = 7U, /* GPT5 */ kCLOCK_GPT5_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_GPT5_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_GPT5_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_GPT5_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_GPT5_ClockRoot_MuxSysPll3Div2 = 4U, - kCLOCK_GPT5_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_GPT5_ClockRoot_MuxSysPll3Pfd2 = 6U, - kCLOCK_GPT5_ClockRoot_MuxSysPll3Pfd3 = 7U, - + kCLOCK_GPT5_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_GPT5_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_GPT5_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_GPT5_ClockRoot_MuxSysPll3Div2 = 4U, + kCLOCK_GPT5_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_GPT5_ClockRoot_MuxSysPll3Pfd2 = 6U, + kCLOCK_GPT5_ClockRoot_MuxSysPll3Pfd3 = 7U, /* GPT6 */ kCLOCK_GPT6_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_GPT6_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_GPT6_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_GPT6_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_GPT6_ClockRoot_MuxSysPll3Div2 = 4U, - kCLOCK_GPT6_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_GPT6_ClockRoot_MuxSysPll3Pfd2 = 6U, - kCLOCK_GPT6_ClockRoot_MuxSysPll3Pfd3 = 7U, - + kCLOCK_GPT6_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_GPT6_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_GPT6_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_GPT6_ClockRoot_MuxSysPll3Div2 = 4U, + kCLOCK_GPT6_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_GPT6_ClockRoot_MuxSysPll3Pfd2 = 6U, + kCLOCK_GPT6_ClockRoot_MuxSysPll3Pfd3 = 7U, /* FLEXSPI1 */ kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_FLEXSPI1_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Pfd0 = 4U, - kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll2Out = 5U, - kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll2Pfd2 = 6U, - kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Out = 7U, - + kCLOCK_FLEXSPI1_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Pfd0 = 4U, + kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll2Out = 5U, + kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll2Pfd2 = 6U, + kCLOCK_FLEXSPI1_ClockRoot_MuxSysPll3Out = 7U, /* FLEXSPI2 */ kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_FLEXSPI2_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Pfd0 = 4U, - kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll2Out = 5U, - kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll2Pfd2 = 6U, - kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Out = 7U, - + kCLOCK_FLEXSPI2_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Pfd0 = 4U, + kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll2Out = 5U, + kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll2Pfd2 = 6U, + kCLOCK_FLEXSPI2_ClockRoot_MuxSysPll3Out = 7U, /* CAN1 */ kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_CAN1_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_CAN1_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_CAN1_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_CAN1_ClockRoot_MuxSysPll3Div2 = 4U, - kCLOCK_CAN1_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_CAN1_ClockRoot_MuxSysPll2Out = 6U, - kCLOCK_CAN1_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_CAN1_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_CAN1_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_CAN1_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_CAN1_ClockRoot_MuxSysPll3Div2 = 4U, + kCLOCK_CAN1_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_CAN1_ClockRoot_MuxSysPll2Out = 6U, + kCLOCK_CAN1_ClockRoot_MuxSysPll2Pfd3 = 7U, /* CAN2 */ kCLOCK_CAN2_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_CAN2_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_CAN2_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_CAN2_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_CAN2_ClockRoot_MuxSysPll3Div2 = 4U, - kCLOCK_CAN2_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_CAN2_ClockRoot_MuxSysPll2Out = 6U, - kCLOCK_CAN2_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_CAN2_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_CAN2_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_CAN2_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_CAN2_ClockRoot_MuxSysPll3Div2 = 4U, + kCLOCK_CAN2_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_CAN2_ClockRoot_MuxSysPll2Out = 6U, + kCLOCK_CAN2_ClockRoot_MuxSysPll2Pfd3 = 7U, /* CAN3 */ kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_CAN3_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_CAN3_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_CAN3_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_CAN3_ClockRoot_MuxSysPll3Pfd3 = 4U, - kCLOCK_CAN3_ClockRoot_MuxSysPll3Out = 5U, - kCLOCK_CAN3_ClockRoot_MuxSysPll2Pfd3 = 6U, - kCLOCK_CAN3_ClockRoot_MuxSysPll1Div5 = 7U, - + kCLOCK_CAN3_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_CAN3_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_CAN3_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_CAN3_ClockRoot_MuxSysPll3Pfd3 = 4U, + kCLOCK_CAN3_ClockRoot_MuxSysPll3Out = 5U, + kCLOCK_CAN3_ClockRoot_MuxSysPll2Pfd3 = 6U, + kCLOCK_CAN3_ClockRoot_MuxSysPll1Div5 = 7U, /* LPUART1 */ kCLOCK_LPUART1_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_LPUART1_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_LPUART1_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_LPUART1_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_LPUART1_ClockRoot_MuxSysPll3Div2 = 4U, - kCLOCK_LPUART1_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out = 6U, - kCLOCK_LPUART1_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_LPUART1_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_LPUART1_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_LPUART1_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_LPUART1_ClockRoot_MuxSysPll3Div2 = 4U, + kCLOCK_LPUART1_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out = 6U, + kCLOCK_LPUART1_ClockRoot_MuxSysPll2Pfd3 = 7U, /* LPUART2 */ kCLOCK_LPUART2_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_LPUART2_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_LPUART2_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_LPUART2_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_LPUART2_ClockRoot_MuxSysPll3Div2 = 4U, - kCLOCK_LPUART2_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out = 6U, - kCLOCK_LPUART2_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_LPUART2_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_LPUART2_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_LPUART2_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_LPUART2_ClockRoot_MuxSysPll3Div2 = 4U, + kCLOCK_LPUART2_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out = 6U, + kCLOCK_LPUART2_ClockRoot_MuxSysPll2Pfd3 = 7U, /* LPUART3 */ kCLOCK_LPUART3_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_LPUART3_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_LPUART3_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_LPUART3_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_LPUART3_ClockRoot_MuxSysPll3Div2 = 4U, - kCLOCK_LPUART3_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_LPUART3_ClockRoot_MuxSysPll2Out = 6U, - kCLOCK_LPUART3_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_LPUART3_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_LPUART3_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_LPUART3_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_LPUART3_ClockRoot_MuxSysPll3Div2 = 4U, + kCLOCK_LPUART3_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_LPUART3_ClockRoot_MuxSysPll2Out = 6U, + kCLOCK_LPUART3_ClockRoot_MuxSysPll2Pfd3 = 7U, /* LPUART4 */ kCLOCK_LPUART4_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_LPUART4_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_LPUART4_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_LPUART4_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_LPUART4_ClockRoot_MuxSysPll3Div2 = 4U, - kCLOCK_LPUART4_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_LPUART4_ClockRoot_MuxSysPll2Out = 6U, - kCLOCK_LPUART4_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_LPUART4_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_LPUART4_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_LPUART4_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_LPUART4_ClockRoot_MuxSysPll3Div2 = 4U, + kCLOCK_LPUART4_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_LPUART4_ClockRoot_MuxSysPll2Out = 6U, + kCLOCK_LPUART4_ClockRoot_MuxSysPll2Pfd3 = 7U, /* LPUART5 */ kCLOCK_LPUART5_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_LPUART5_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_LPUART5_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_LPUART5_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_LPUART5_ClockRoot_MuxSysPll3Div2 = 4U, - kCLOCK_LPUART5_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_LPUART5_ClockRoot_MuxSysPll2Out = 6U, - kCLOCK_LPUART5_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_LPUART5_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_LPUART5_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_LPUART5_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_LPUART5_ClockRoot_MuxSysPll3Div2 = 4U, + kCLOCK_LPUART5_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_LPUART5_ClockRoot_MuxSysPll2Out = 6U, + kCLOCK_LPUART5_ClockRoot_MuxSysPll2Pfd3 = 7U, /* LPUART6 */ kCLOCK_LPUART6_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_LPUART6_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_LPUART6_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_LPUART6_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_LPUART6_ClockRoot_MuxSysPll3Div2 = 4U, - kCLOCK_LPUART6_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_LPUART6_ClockRoot_MuxSysPll2Out = 6U, - kCLOCK_LPUART6_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_LPUART6_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_LPUART6_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_LPUART6_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_LPUART6_ClockRoot_MuxSysPll3Div2 = 4U, + kCLOCK_LPUART6_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_LPUART6_ClockRoot_MuxSysPll2Out = 6U, + kCLOCK_LPUART6_ClockRoot_MuxSysPll2Pfd3 = 7U, /* LPUART7 */ kCLOCK_LPUART7_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_LPUART7_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_LPUART7_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_LPUART7_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_LPUART7_ClockRoot_MuxSysPll3Div2 = 4U, - kCLOCK_LPUART7_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_LPUART7_ClockRoot_MuxSysPll2Out = 6U, - kCLOCK_LPUART7_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_LPUART7_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_LPUART7_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_LPUART7_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_LPUART7_ClockRoot_MuxSysPll3Div2 = 4U, + kCLOCK_LPUART7_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_LPUART7_ClockRoot_MuxSysPll2Out = 6U, + kCLOCK_LPUART7_ClockRoot_MuxSysPll2Pfd3 = 7U, /* LPUART8 */ kCLOCK_LPUART8_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_LPUART8_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_LPUART8_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_LPUART8_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_LPUART8_ClockRoot_MuxSysPll3Div2 = 4U, - kCLOCK_LPUART8_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_LPUART8_ClockRoot_MuxSysPll2Out = 6U, - kCLOCK_LPUART8_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_LPUART8_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_LPUART8_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_LPUART8_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_LPUART8_ClockRoot_MuxSysPll3Div2 = 4U, + kCLOCK_LPUART8_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_LPUART8_ClockRoot_MuxSysPll2Out = 6U, + kCLOCK_LPUART8_ClockRoot_MuxSysPll2Pfd3 = 7U, /* LPUART9 */ kCLOCK_LPUART9_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_LPUART9_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_LPUART9_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_LPUART9_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_LPUART9_ClockRoot_MuxSysPll3Div2 = 4U, - kCLOCK_LPUART9_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_LPUART9_ClockRoot_MuxSysPll2Out = 6U, - kCLOCK_LPUART9_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_LPUART9_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_LPUART9_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_LPUART9_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_LPUART9_ClockRoot_MuxSysPll3Div2 = 4U, + kCLOCK_LPUART9_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_LPUART9_ClockRoot_MuxSysPll2Out = 6U, + kCLOCK_LPUART9_ClockRoot_MuxSysPll2Pfd3 = 7U, /* LPUART10 */ kCLOCK_LPUART10_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_LPUART10_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_LPUART10_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_LPUART10_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_LPUART10_ClockRoot_MuxSysPll3Div2 = 4U, - kCLOCK_LPUART10_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_LPUART10_ClockRoot_MuxSysPll2Out = 6U, - kCLOCK_LPUART10_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_LPUART10_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_LPUART10_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_LPUART10_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_LPUART10_ClockRoot_MuxSysPll3Div2 = 4U, + kCLOCK_LPUART10_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_LPUART10_ClockRoot_MuxSysPll2Out = 6U, + kCLOCK_LPUART10_ClockRoot_MuxSysPll2Pfd3 = 7U, /* LPUART11 */ kCLOCK_LPUART11_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_LPUART11_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_LPUART11_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_LPUART11_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_LPUART11_ClockRoot_MuxSysPll3Pfd3 = 4U, - kCLOCK_LPUART11_ClockRoot_MuxSysPll3Out = 5U, - kCLOCK_LPUART11_ClockRoot_MuxSysPll2Pfd3 = 6U, - kCLOCK_LPUART11_ClockRoot_MuxSysPll1Div5 = 7U, - + kCLOCK_LPUART11_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_LPUART11_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_LPUART11_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_LPUART11_ClockRoot_MuxSysPll3Pfd3 = 4U, + kCLOCK_LPUART11_ClockRoot_MuxSysPll3Out = 5U, + kCLOCK_LPUART11_ClockRoot_MuxSysPll2Pfd3 = 6U, + kCLOCK_LPUART11_ClockRoot_MuxSysPll1Div5 = 7U, /* LPUART12 */ kCLOCK_LPUART12_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_LPUART12_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_LPUART12_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_LPUART12_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_LPUART12_ClockRoot_MuxSysPll3Pfd3 = 4U, - kCLOCK_LPUART12_ClockRoot_MuxSysPll3Out = 5U, - kCLOCK_LPUART12_ClockRoot_MuxSysPll2Pfd3 = 6U, - kCLOCK_LPUART12_ClockRoot_MuxSysPll1Div5 = 7U, - + kCLOCK_LPUART12_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_LPUART12_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_LPUART12_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_LPUART12_ClockRoot_MuxSysPll3Pfd3 = 4U, + kCLOCK_LPUART12_ClockRoot_MuxSysPll3Out = 5U, + kCLOCK_LPUART12_ClockRoot_MuxSysPll2Pfd3 = 6U, + kCLOCK_LPUART12_ClockRoot_MuxSysPll1Div5 = 7U, /* LPI2C1 */ kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_LPI2C1_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_LPI2C1_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_LPI2C1_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_LPI2C1_ClockRoot_MuxSysPll3Div2 = 4U, - kCLOCK_LPI2C1_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_LPI2C1_ClockRoot_MuxSysPll2Out = 6U, - kCLOCK_LPI2C1_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_LPI2C1_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_LPI2C1_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_LPI2C1_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_LPI2C1_ClockRoot_MuxSysPll3Div2 = 4U, + kCLOCK_LPI2C1_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_LPI2C1_ClockRoot_MuxSysPll2Out = 6U, + kCLOCK_LPI2C1_ClockRoot_MuxSysPll2Pfd3 = 7U, /* LPI2C2 */ kCLOCK_LPI2C2_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_LPI2C2_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_LPI2C2_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_LPI2C2_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_LPI2C2_ClockRoot_MuxSysPll3Div2 = 4U, - kCLOCK_LPI2C2_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_LPI2C2_ClockRoot_MuxSysPll2Out = 6U, - kCLOCK_LPI2C2_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_LPI2C2_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_LPI2C2_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_LPI2C2_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_LPI2C2_ClockRoot_MuxSysPll3Div2 = 4U, + kCLOCK_LPI2C2_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_LPI2C2_ClockRoot_MuxSysPll2Out = 6U, + kCLOCK_LPI2C2_ClockRoot_MuxSysPll2Pfd3 = 7U, /* LPI2C3 */ kCLOCK_LPI2C3_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_LPI2C3_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_LPI2C3_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_LPI2C3_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_LPI2C3_ClockRoot_MuxSysPll3Div2 = 4U, - kCLOCK_LPI2C3_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_LPI2C3_ClockRoot_MuxSysPll2Out = 6U, - kCLOCK_LPI2C3_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_LPI2C3_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_LPI2C3_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_LPI2C3_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_LPI2C3_ClockRoot_MuxSysPll3Div2 = 4U, + kCLOCK_LPI2C3_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_LPI2C3_ClockRoot_MuxSysPll2Out = 6U, + kCLOCK_LPI2C3_ClockRoot_MuxSysPll2Pfd3 = 7U, /* LPI2C4 */ kCLOCK_LPI2C4_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_LPI2C4_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_LPI2C4_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_LPI2C4_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_LPI2C4_ClockRoot_MuxSysPll3Div2 = 4U, - kCLOCK_LPI2C4_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_LPI2C4_ClockRoot_MuxSysPll2Out = 6U, - kCLOCK_LPI2C4_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_LPI2C4_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_LPI2C4_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_LPI2C4_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_LPI2C4_ClockRoot_MuxSysPll3Div2 = 4U, + kCLOCK_LPI2C4_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_LPI2C4_ClockRoot_MuxSysPll2Out = 6U, + kCLOCK_LPI2C4_ClockRoot_MuxSysPll2Pfd3 = 7U, /* LPI2C5 */ kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_LPI2C5_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_LPI2C5_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_LPI2C5_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_LPI2C5_ClockRoot_MuxSysPll3Pfd3 = 4U, - kCLOCK_LPI2C5_ClockRoot_MuxSysPll3Out = 5U, - kCLOCK_LPI2C5_ClockRoot_MuxSysPll2Pfd3 = 6U, - kCLOCK_LPI2C5_ClockRoot_MuxSysPll1Div5 = 7U, - + kCLOCK_LPI2C5_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_LPI2C5_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_LPI2C5_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_LPI2C5_ClockRoot_MuxSysPll3Pfd3 = 4U, + kCLOCK_LPI2C5_ClockRoot_MuxSysPll3Out = 5U, + kCLOCK_LPI2C5_ClockRoot_MuxSysPll2Pfd3 = 6U, + kCLOCK_LPI2C5_ClockRoot_MuxSysPll1Div5 = 7U, /* LPI2C6 */ kCLOCK_LPI2C6_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_LPI2C6_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_LPI2C6_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_LPI2C6_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_LPI2C6_ClockRoot_MuxSysPll3Pfd3 = 4U, - kCLOCK_LPI2C6_ClockRoot_MuxSysPll3Out = 5U, - kCLOCK_LPI2C6_ClockRoot_MuxSysPll2Pfd3 = 6U, - kCLOCK_LPI2C6_ClockRoot_MuxSysPll1Div5 = 7U, - + kCLOCK_LPI2C6_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_LPI2C6_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_LPI2C6_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_LPI2C6_ClockRoot_MuxSysPll3Pfd3 = 4U, + kCLOCK_LPI2C6_ClockRoot_MuxSysPll3Out = 5U, + kCLOCK_LPI2C6_ClockRoot_MuxSysPll2Pfd3 = 6U, + kCLOCK_LPI2C6_ClockRoot_MuxSysPll1Div5 = 7U, /* LPSPI1 */ kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_LPSPI1_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_LPSPI1_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_LPSPI1_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_LPSPI1_ClockRoot_MuxSysPll3Pfd2 = 4U, - kCLOCK_LPSPI1_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_LPSPI1_ClockRoot_MuxSysPll2Out = 6U, - kCLOCK_LPSPI1_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_LPSPI1_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_LPSPI1_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_LPSPI1_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_LPSPI1_ClockRoot_MuxSysPll3Pfd2 = 4U, + kCLOCK_LPSPI1_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_LPSPI1_ClockRoot_MuxSysPll2Out = 6U, + kCLOCK_LPSPI1_ClockRoot_MuxSysPll2Pfd3 = 7U, /* LPSPI2 */ kCLOCK_LPSPI2_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_LPSPI2_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_LPSPI2_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_LPSPI2_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_LPSPI2_ClockRoot_MuxSysPll3Pfd2 = 4U, - kCLOCK_LPSPI2_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_LPSPI2_ClockRoot_MuxSysPll2Out = 6U, - kCLOCK_LPSPI2_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_LPSPI2_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_LPSPI2_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_LPSPI2_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_LPSPI2_ClockRoot_MuxSysPll3Pfd2 = 4U, + kCLOCK_LPSPI2_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_LPSPI2_ClockRoot_MuxSysPll2Out = 6U, + kCLOCK_LPSPI2_ClockRoot_MuxSysPll2Pfd3 = 7U, /* LPSPI3 */ kCLOCK_LPSPI3_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_LPSPI3_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_LPSPI3_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_LPSPI3_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_LPSPI3_ClockRoot_MuxSysPll3Pfd2 = 4U, - kCLOCK_LPSPI3_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_LPSPI3_ClockRoot_MuxSysPll2Out = 6U, - kCLOCK_LPSPI3_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_LPSPI3_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_LPSPI3_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_LPSPI3_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_LPSPI3_ClockRoot_MuxSysPll3Pfd2 = 4U, + kCLOCK_LPSPI3_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_LPSPI3_ClockRoot_MuxSysPll2Out = 6U, + kCLOCK_LPSPI3_ClockRoot_MuxSysPll2Pfd3 = 7U, /* LPSPI4 */ kCLOCK_LPSPI4_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_LPSPI4_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_LPSPI4_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_LPSPI4_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_LPSPI4_ClockRoot_MuxSysPll3Pfd2 = 4U, - kCLOCK_LPSPI4_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_LPSPI4_ClockRoot_MuxSysPll2Out = 6U, - kCLOCK_LPSPI4_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_LPSPI4_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_LPSPI4_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_LPSPI4_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_LPSPI4_ClockRoot_MuxSysPll3Pfd2 = 4U, + kCLOCK_LPSPI4_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_LPSPI4_ClockRoot_MuxSysPll2Out = 6U, + kCLOCK_LPSPI4_ClockRoot_MuxSysPll2Pfd3 = 7U, /* LPSPI5 */ kCLOCK_LPSPI5_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_LPSPI5_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_LPSPI5_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_LPSPI5_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Pfd3 = 4U, - kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Out = 5U, - kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Pfd2 = 6U, - kCLOCK_LPSPI5_ClockRoot_MuxSysPll1Div5 = 7U, - + kCLOCK_LPSPI5_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_LPSPI5_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_LPSPI5_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Pfd3 = 4U, + kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Out = 5U, + kCLOCK_LPSPI5_ClockRoot_MuxSysPll3Pfd2 = 6U, + kCLOCK_LPSPI5_ClockRoot_MuxSysPll1Div5 = 7U, /* LPSPI6 */ kCLOCK_LPSPI6_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_LPSPI6_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_LPSPI6_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_LPSPI6_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Pfd3 = 4U, - kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Out = 5U, - kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Pfd2 = 6U, - kCLOCK_LPSPI6_ClockRoot_MuxSysPll1Div5 = 7U, - + kCLOCK_LPSPI6_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_LPSPI6_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_LPSPI6_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Pfd3 = 4U, + kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Out = 5U, + kCLOCK_LPSPI6_ClockRoot_MuxSysPll3Pfd2 = 6U, + kCLOCK_LPSPI6_ClockRoot_MuxSysPll1Div5 = 7U, /* EMV1 */ kCLOCK_EMV1_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_EMV1_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_EMV1_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_EMV1_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_EMV1_ClockRoot_MuxSysPll3Div2 = 4U, - kCLOCK_EMV1_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_EMV1_ClockRoot_MuxSysPll2Out = 6U, - kCLOCK_EMV1_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_EMV1_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_EMV1_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_EMV1_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_EMV1_ClockRoot_MuxSysPll3Div2 = 4U, + kCLOCK_EMV1_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_EMV1_ClockRoot_MuxSysPll2Out = 6U, + kCLOCK_EMV1_ClockRoot_MuxSysPll2Pfd3 = 7U, /* EMV2 */ kCLOCK_EMV2_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_EMV2_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_EMV2_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_EMV2_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_EMV2_ClockRoot_MuxSysPll3Div2 = 4U, - kCLOCK_EMV2_ClockRoot_MuxSysPll1Div5 = 5U, - kCLOCK_EMV2_ClockRoot_MuxSysPll2Out = 6U, - kCLOCK_EMV2_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_EMV2_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_EMV2_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_EMV2_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_EMV2_ClockRoot_MuxSysPll3Div2 = 4U, + kCLOCK_EMV2_ClockRoot_MuxSysPll1Div5 = 5U, + kCLOCK_EMV2_ClockRoot_MuxSysPll2Out = 6U, + kCLOCK_EMV2_ClockRoot_MuxSysPll2Pfd3 = 7U, /* ENET1 */ kCLOCK_ENET1_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_ENET1_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_ENET1_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_ENET1_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_ENET1_ClockRoot_MuxSysPll1Div2 = 4U, - kCLOCK_ENET1_ClockRoot_MuxAudioPllOut = 5U, - kCLOCK_ENET1_ClockRoot_MuxSysPll1Div5 = 6U, - kCLOCK_ENET1_ClockRoot_MuxSysPll2Pfd1 = 7U, - + kCLOCK_ENET1_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_ENET1_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_ENET1_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_ENET1_ClockRoot_MuxSysPll1Div2 = 4U, + kCLOCK_ENET1_ClockRoot_MuxAudioPllOut = 5U, + kCLOCK_ENET1_ClockRoot_MuxSysPll1Div5 = 6U, + kCLOCK_ENET1_ClockRoot_MuxSysPll2Pfd1 = 7U, /* ENET2 */ kCLOCK_ENET2_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_ENET2_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_ENET2_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_ENET2_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_ENET2_ClockRoot_MuxSysPll1Div2 = 4U, - kCLOCK_ENET2_ClockRoot_MuxAudioPllOut = 5U, - kCLOCK_ENET2_ClockRoot_MuxSysPll1Div5 = 6U, - kCLOCK_ENET2_ClockRoot_MuxSysPll2Pfd1 = 7U, - + kCLOCK_ENET2_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_ENET2_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_ENET2_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_ENET2_ClockRoot_MuxSysPll1Div2 = 4U, + kCLOCK_ENET2_ClockRoot_MuxAudioPllOut = 5U, + kCLOCK_ENET2_ClockRoot_MuxSysPll1Div5 = 6U, + kCLOCK_ENET2_ClockRoot_MuxSysPll2Pfd1 = 7U, /* ENET_QOS */ kCLOCK_ENET_QOS_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_ENET_QOS_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_ENET_QOS_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_ENET_QOS_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_ENET_QOS_ClockRoot_MuxSysPll1Div2 = 4U, - kCLOCK_ENET_QOS_ClockRoot_MuxAudioPllOut = 5U, - kCLOCK_ENET_QOS_ClockRoot_MuxSysPll1Div5 = 6U, - kCLOCK_ENET_QOS_ClockRoot_MuxSysPll2Pfd1 = 7U, - + kCLOCK_ENET_QOS_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_ENET_QOS_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_ENET_QOS_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_ENET_QOS_ClockRoot_MuxSysPll1Div2 = 4U, + kCLOCK_ENET_QOS_ClockRoot_MuxAudioPllOut = 5U, + kCLOCK_ENET_QOS_ClockRoot_MuxSysPll1Div5 = 6U, + kCLOCK_ENET_QOS_ClockRoot_MuxSysPll2Pfd1 = 7U, /* ENET_25M */ kCLOCK_ENET_25M_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_ENET_25M_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_ENET_25M_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_ENET_25M_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_ENET_25M_ClockRoot_MuxSysPll1Div2 = 4U, - kCLOCK_ENET_25M_ClockRoot_MuxAudioPllOut = 5U, - kCLOCK_ENET_25M_ClockRoot_MuxSysPll1Div5 = 6U, - kCLOCK_ENET_25M_ClockRoot_MuxSysPll2Pfd1 = 7U, - + kCLOCK_ENET_25M_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_ENET_25M_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_ENET_25M_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_ENET_25M_ClockRoot_MuxSysPll1Div2 = 4U, + kCLOCK_ENET_25M_ClockRoot_MuxAudioPllOut = 5U, + kCLOCK_ENET_25M_ClockRoot_MuxSysPll1Div5 = 6U, + kCLOCK_ENET_25M_ClockRoot_MuxSysPll2Pfd1 = 7U, /* ENET_TIMER1 */ kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_ENET_TIMER1_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll1Div2 = 4U, - kCLOCK_ENET_TIMER1_ClockRoot_MuxAudioPllOut = 5U, - kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll1Div5 = 6U, - kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll2Pfd1 = 7U, - + kCLOCK_ENET_TIMER1_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll1Div2 = 4U, + kCLOCK_ENET_TIMER1_ClockRoot_MuxAudioPllOut = 5U, + kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll1Div5 = 6U, + kCLOCK_ENET_TIMER1_ClockRoot_MuxSysPll2Pfd1 = 7U, /* ENET_TIMER2 */ kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_ENET_TIMER2_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll1Div2 = 4U, - kCLOCK_ENET_TIMER2_ClockRoot_MuxAudioPllOut = 5U, - kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll1Div5 = 6U, - kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll2Pfd1 = 7U, - + kCLOCK_ENET_TIMER2_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll1Div2 = 4U, + kCLOCK_ENET_TIMER2_ClockRoot_MuxAudioPllOut = 5U, + kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll1Div5 = 6U, + kCLOCK_ENET_TIMER2_ClockRoot_MuxSysPll2Pfd1 = 7U, /* ENET_TIMER3 */ kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_ENET_TIMER3_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_ENET_TIMER3_ClockRoot_MuxSysPll1Div2 = 4U, - kCLOCK_ENET_TIMER3_ClockRoot_MuxAudioPllOut = 5U, - kCLOCK_ENET_TIMER3_ClockRoot_MuxSysPll1Div5 = 6U, - kCLOCK_ENET_TIMER3_ClockRoot_MuxSysPll2Pfd1 = 7U, - + kCLOCK_ENET_TIMER3_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_ENET_TIMER3_ClockRoot_MuxSysPll1Div2 = 4U, + kCLOCK_ENET_TIMER3_ClockRoot_MuxAudioPllOut = 5U, + kCLOCK_ENET_TIMER3_ClockRoot_MuxSysPll1Div5 = 6U, + kCLOCK_ENET_TIMER3_ClockRoot_MuxSysPll2Pfd1 = 7U, /* USDHC1 */ kCLOCK_USDHC1_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_USDHC1_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_USDHC1_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_USDHC1_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd2 = 4U, - kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd0 = 5U, - kCLOCK_USDHC1_ClockRoot_MuxSysPll1Div5 = 6U, - kCLOCK_USDHC1_ClockRoot_MuxArmPllOut = 7U, - + kCLOCK_USDHC1_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_USDHC1_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_USDHC1_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd2 = 4U, + kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd0 = 5U, + kCLOCK_USDHC1_ClockRoot_MuxSysPll1Div5 = 6U, + kCLOCK_USDHC1_ClockRoot_MuxArmPllOut = 7U, /* USDHC2 */ kCLOCK_USDHC2_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_USDHC2_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_USDHC2_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_USDHC2_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd2 = 4U, - kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd0 = 5U, - kCLOCK_USDHC2_ClockRoot_MuxSysPll1Div5 = 6U, - kCLOCK_USDHC2_ClockRoot_MuxArmPllOut = 7U, - + kCLOCK_USDHC2_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_USDHC2_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_USDHC2_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd2 = 4U, + kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd0 = 5U, + kCLOCK_USDHC2_ClockRoot_MuxSysPll1Div5 = 6U, + kCLOCK_USDHC2_ClockRoot_MuxArmPllOut = 7U, /* ASRC */ kCLOCK_ASRC_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_ASRC_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_ASRC_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_ASRC_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_ASRC_ClockRoot_MuxSysPll1Div5 = 4U, - kCLOCK_ASRC_ClockRoot_MuxSysPll3Div2 = 5U, - kCLOCK_ASRC_ClockRoot_MuxAudioPllOut = 6U, - kCLOCK_ASRC_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_ASRC_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_ASRC_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_ASRC_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_ASRC_ClockRoot_MuxSysPll1Div5 = 4U, + kCLOCK_ASRC_ClockRoot_MuxSysPll3Div2 = 5U, + kCLOCK_ASRC_ClockRoot_MuxAudioPllOut = 6U, + kCLOCK_ASRC_ClockRoot_MuxSysPll2Pfd3 = 7U, /* MQS */ kCLOCK_MQS_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_MQS_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_MQS_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_MQS_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_MQS_ClockRoot_MuxSysPll1Div5 = 4U, - kCLOCK_MQS_ClockRoot_MuxSysPll3Div2 = 5U, - kCLOCK_MQS_ClockRoot_MuxAudioPllOut = 6U, - kCLOCK_MQS_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_MQS_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_MQS_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_MQS_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_MQS_ClockRoot_MuxSysPll1Div5 = 4U, + kCLOCK_MQS_ClockRoot_MuxSysPll3Div2 = 5U, + kCLOCK_MQS_ClockRoot_MuxAudioPllOut = 6U, + kCLOCK_MQS_ClockRoot_MuxSysPll2Pfd3 = 7U, /* MIC */ kCLOCK_MIC_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_MIC_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_MIC_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_MIC_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_MIC_ClockRoot_MuxSysPll3Pfd3 = 4U, - kCLOCK_MIC_ClockRoot_MuxSysPll3Out = 5U, - kCLOCK_MIC_ClockRoot_MuxAudioPllOut = 6U, - kCLOCK_MIC_ClockRoot_MuxSysPll1Div5 = 7U, - + kCLOCK_MIC_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_MIC_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_MIC_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_MIC_ClockRoot_MuxSysPll3Pfd3 = 4U, + kCLOCK_MIC_ClockRoot_MuxSysPll3Out = 5U, + kCLOCK_MIC_ClockRoot_MuxAudioPllOut = 6U, + kCLOCK_MIC_ClockRoot_MuxSysPll1Div5 = 7U, /* SPDIF */ kCLOCK_SPDIF_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_SPDIF_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_SPDIF_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_SPDIF_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_SPDIF_ClockRoot_MuxAudioPllOut = 4U, - kCLOCK_SPDIF_ClockRoot_MuxSysPll3Out = 5U, - kCLOCK_SPDIF_ClockRoot_MuxSysPll3Pfd2 = 6U, - kCLOCK_SPDIF_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_SPDIF_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_SPDIF_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_SPDIF_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_SPDIF_ClockRoot_MuxAudioPllOut = 4U, + kCLOCK_SPDIF_ClockRoot_MuxSysPll3Out = 5U, + kCLOCK_SPDIF_ClockRoot_MuxSysPll3Pfd2 = 6U, + kCLOCK_SPDIF_ClockRoot_MuxSysPll2Pfd3 = 7U, /* SAI1 */ kCLOCK_SAI1_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_SAI1_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_SAI1_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_SAI1_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_SAI1_ClockRoot_MuxAudioPllOut = 4U, - kCLOCK_SAI1_ClockRoot_MuxSysPll3Pfd2 = 5U, - kCLOCK_SAI1_ClockRoot_MuxSysPll1Div5 = 6U, - kCLOCK_SAI1_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_SAI1_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_SAI1_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_SAI1_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_SAI1_ClockRoot_MuxAudioPllOut = 4U, + kCLOCK_SAI1_ClockRoot_MuxSysPll3Pfd2 = 5U, + kCLOCK_SAI1_ClockRoot_MuxSysPll1Div5 = 6U, + kCLOCK_SAI1_ClockRoot_MuxSysPll2Pfd3 = 7U, /* SAI2 */ kCLOCK_SAI2_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_SAI2_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_SAI2_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_SAI2_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_SAI2_ClockRoot_MuxAudioPllOut = 4U, - kCLOCK_SAI2_ClockRoot_MuxSysPll3Pfd2 = 5U, - kCLOCK_SAI2_ClockRoot_MuxSysPll1Div5 = 6U, - kCLOCK_SAI2_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_SAI2_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_SAI2_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_SAI2_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_SAI2_ClockRoot_MuxAudioPllOut = 4U, + kCLOCK_SAI2_ClockRoot_MuxSysPll3Pfd2 = 5U, + kCLOCK_SAI2_ClockRoot_MuxSysPll1Div5 = 6U, + kCLOCK_SAI2_ClockRoot_MuxSysPll2Pfd3 = 7U, /* SAI3 */ kCLOCK_SAI3_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_SAI3_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_SAI3_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_SAI3_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_SAI3_ClockRoot_MuxAudioPllOut = 4U, - kCLOCK_SAI3_ClockRoot_MuxSysPll3Pfd2 = 5U, - kCLOCK_SAI3_ClockRoot_MuxSysPll1Div5 = 6U, - kCLOCK_SAI3_ClockRoot_MuxSysPll2Pfd3 = 7U, - + kCLOCK_SAI3_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_SAI3_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_SAI3_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_SAI3_ClockRoot_MuxAudioPllOut = 4U, + kCLOCK_SAI3_ClockRoot_MuxSysPll3Pfd2 = 5U, + kCLOCK_SAI3_ClockRoot_MuxSysPll1Div5 = 6U, + kCLOCK_SAI3_ClockRoot_MuxSysPll2Pfd3 = 7U, /* SAI4 */ kCLOCK_SAI4_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_SAI4_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_SAI4_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_SAI4_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_SAI4_ClockRoot_MuxSysPll3Pfd3 = 4U, - kCLOCK_SAI4_ClockRoot_MuxSysPll3Out = 5U, - kCLOCK_SAI4_ClockRoot_MuxAudioPllOut = 6U, - kCLOCK_SAI4_ClockRoot_MuxSysPll1Div5 = 7U, - + kCLOCK_SAI4_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_SAI4_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_SAI4_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_SAI4_ClockRoot_MuxSysPll3Pfd3 = 4U, + kCLOCK_SAI4_ClockRoot_MuxSysPll3Out = 5U, + kCLOCK_SAI4_ClockRoot_MuxAudioPllOut = 6U, + kCLOCK_SAI4_ClockRoot_MuxSysPll1Div5 = 7U, /* GC355 */ kCLOCK_GC355_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_GC355_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_GC355_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_GC355_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_GC355_ClockRoot_MuxSysPll2Out = 4U, - kCLOCK_GC355_ClockRoot_MuxSysPll2Pfd1 = 5U, - kCLOCK_GC355_ClockRoot_MuxSysPll3Out = 6U, - kCLOCK_GC355_ClockRoot_MuxVideoPllOut = 7U, - + kCLOCK_GC355_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_GC355_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_GC355_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_GC355_ClockRoot_MuxSysPll2Out = 4U, + kCLOCK_GC355_ClockRoot_MuxSysPll2Pfd1 = 5U, + kCLOCK_GC355_ClockRoot_MuxSysPll3Out = 6U, + kCLOCK_GC355_ClockRoot_MuxVideoPllOut = 7U, /* LCDIF */ kCLOCK_LCDIF_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_LCDIF_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_LCDIF_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_LCDIF_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_LCDIF_ClockRoot_MuxSysPll2Out = 4U, - kCLOCK_LCDIF_ClockRoot_MuxSysPll2Pfd2 = 5U, - kCLOCK_LCDIF_ClockRoot_MuxSysPll3Pfd0 = 6U, - kCLOCK_LCDIF_ClockRoot_MuxVideoPllOut = 7U, - + kCLOCK_LCDIF_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_LCDIF_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_LCDIF_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_LCDIF_ClockRoot_MuxSysPll2Out = 4U, + kCLOCK_LCDIF_ClockRoot_MuxSysPll2Pfd2 = 5U, + kCLOCK_LCDIF_ClockRoot_MuxSysPll3Pfd0 = 6U, + kCLOCK_LCDIF_ClockRoot_MuxVideoPllOut = 7U, /* LCDIFV2 */ kCLOCK_LCDIFV2_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_LCDIFV2_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_LCDIFV2_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_LCDIFV2_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_LCDIFV2_ClockRoot_MuxSysPll2Out = 4U, - kCLOCK_LCDIFV2_ClockRoot_MuxSysPll2Pfd2 = 5U, - kCLOCK_LCDIFV2_ClockRoot_MuxSysPll3Pfd0 = 6U, - kCLOCK_LCDIFV2_ClockRoot_MuxVideoPllOut = 7U, - + kCLOCK_LCDIFV2_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_LCDIFV2_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_LCDIFV2_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_LCDIFV2_ClockRoot_MuxSysPll2Out = 4U, + kCLOCK_LCDIFV2_ClockRoot_MuxSysPll2Pfd2 = 5U, + kCLOCK_LCDIFV2_ClockRoot_MuxSysPll3Pfd0 = 6U, + kCLOCK_LCDIFV2_ClockRoot_MuxVideoPllOut = 7U, /* MIPI_REF */ kCLOCK_MIPI_REF_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_MIPI_REF_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_MIPI_REF_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_MIPI_REF_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_MIPI_REF_ClockRoot_MuxSysPll2Out = 4U, - kCLOCK_MIPI_REF_ClockRoot_MuxSysPll2Pfd0 = 5U, - kCLOCK_MIPI_REF_ClockRoot_MuxSysPll3Pfd0 = 6U, - kCLOCK_MIPI_REF_ClockRoot_MuxVideoPllOut = 7U, - + kCLOCK_MIPI_REF_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_MIPI_REF_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_MIPI_REF_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_MIPI_REF_ClockRoot_MuxSysPll2Out = 4U, + kCLOCK_MIPI_REF_ClockRoot_MuxSysPll2Pfd0 = 5U, + kCLOCK_MIPI_REF_ClockRoot_MuxSysPll3Pfd0 = 6U, + kCLOCK_MIPI_REF_ClockRoot_MuxVideoPllOut = 7U, /* MIPI_ESC */ kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_MIPI_ESC_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll2Out = 4U, - kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll2Pfd0 = 5U, - kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll3Pfd0 = 6U, - kCLOCK_MIPI_ESC_ClockRoot_MuxVideoPllOut = 7U, - + kCLOCK_MIPI_ESC_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll2Out = 4U, + kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll2Pfd0 = 5U, + kCLOCK_MIPI_ESC_ClockRoot_MuxSysPll3Pfd0 = 6U, + kCLOCK_MIPI_ESC_ClockRoot_MuxVideoPllOut = 7U, /* CSI2 */ kCLOCK_CSI2_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_CSI2_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_CSI2_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_CSI2_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_CSI2_ClockRoot_MuxSysPll2Pfd2 = 4U, - kCLOCK_CSI2_ClockRoot_MuxSysPll3Out = 5U, - kCLOCK_CSI2_ClockRoot_MuxSysPll2Pfd0 = 6U, - kCLOCK_CSI2_ClockRoot_MuxVideoPllOut = 7U, - + kCLOCK_CSI2_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_CSI2_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_CSI2_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_CSI2_ClockRoot_MuxSysPll2Pfd2 = 4U, + kCLOCK_CSI2_ClockRoot_MuxSysPll3Out = 5U, + kCLOCK_CSI2_ClockRoot_MuxSysPll2Pfd0 = 6U, + kCLOCK_CSI2_ClockRoot_MuxVideoPllOut = 7U, /* CSI2_ESC */ kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_CSI2_ESC_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll2Pfd2 = 4U, - kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll3Out = 5U, - kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll2Pfd0 = 6U, - kCLOCK_CSI2_ESC_ClockRoot_MuxVideoPllOut = 7U, - + kCLOCK_CSI2_ESC_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll2Pfd2 = 4U, + kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll3Out = 5U, + kCLOCK_CSI2_ESC_ClockRoot_MuxSysPll2Pfd0 = 6U, + kCLOCK_CSI2_ESC_ClockRoot_MuxVideoPllOut = 7U, /* CSI2_UI */ kCLOCK_CSI2_UI_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_CSI2_UI_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_CSI2_UI_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_CSI2_UI_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_CSI2_UI_ClockRoot_MuxSysPll2Pfd2 = 4U, - kCLOCK_CSI2_UI_ClockRoot_MuxSysPll3Out = 5U, - kCLOCK_CSI2_UI_ClockRoot_MuxSysPll2Pfd0 = 6U, - kCLOCK_CSI2_UI_ClockRoot_MuxVideoPllOut = 7U, - + kCLOCK_CSI2_UI_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_CSI2_UI_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_CSI2_UI_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_CSI2_UI_ClockRoot_MuxSysPll2Pfd2 = 4U, + kCLOCK_CSI2_UI_ClockRoot_MuxSysPll3Out = 5U, + kCLOCK_CSI2_UI_ClockRoot_MuxSysPll2Pfd0 = 6U, + kCLOCK_CSI2_UI_ClockRoot_MuxVideoPllOut = 7U, /* CSI */ kCLOCK_CSI_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_CSI_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_CSI_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_CSI_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_CSI_ClockRoot_MuxSysPll2Pfd2 = 4U, - kCLOCK_CSI_ClockRoot_MuxSysPll3Out = 5U, - kCLOCK_CSI_ClockRoot_MuxSysPll3Pfd1 = 6U, - kCLOCK_CSI_ClockRoot_MuxVideoPllOut = 7U, - + kCLOCK_CSI_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_CSI_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_CSI_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_CSI_ClockRoot_MuxSysPll2Pfd2 = 4U, + kCLOCK_CSI_ClockRoot_MuxSysPll3Out = 5U, + kCLOCK_CSI_ClockRoot_MuxSysPll3Pfd1 = 6U, + kCLOCK_CSI_ClockRoot_MuxVideoPllOut = 7U, /* CKO1 */ kCLOCK_CKO1_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_CKO1_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_CKO1_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_CKO1_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_CKO1_ClockRoot_MuxSysPll2Pfd2 = 4U, - kCLOCK_CKO1_ClockRoot_MuxSysPll2Out = 5U, - kCLOCK_CKO1_ClockRoot_MuxSysPll3Pfd1 = 6U, - kCLOCK_CKO1_ClockRoot_MuxSysPll1Div5 = 7U, - + kCLOCK_CKO1_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_CKO1_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_CKO1_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_CKO1_ClockRoot_MuxSysPll2Pfd2 = 4U, + kCLOCK_CKO1_ClockRoot_MuxSysPll2Out = 5U, + kCLOCK_CKO1_ClockRoot_MuxSysPll3Pfd1 = 6U, + kCLOCK_CKO1_ClockRoot_MuxSysPll1Div5 = 7U, /* CKO2 */ kCLOCK_CKO2_ClockRoot_MuxOscRc48MDiv2 = 0U, - kCLOCK_CKO2_ClockRoot_MuxOsc24MOut = 1U, - kCLOCK_CKO2_ClockRoot_MuxOscRc400M = 2U, - kCLOCK_CKO2_ClockRoot_MuxOscRc16M = 3U, - kCLOCK_CKO2_ClockRoot_MuxSysPll2Pfd3 = 4U, - kCLOCK_CKO2_ClockRoot_MuxOscRc48M = 5U, - kCLOCK_CKO2_ClockRoot_MuxSysPll3Pfd1 = 6U, - kCLOCK_CKO2_ClockRoot_MuxAudioPllOut = 7U, + kCLOCK_CKO2_ClockRoot_MuxOsc24MOut = 1U, + kCLOCK_CKO2_ClockRoot_MuxOscRc400M = 2U, + kCLOCK_CKO2_ClockRoot_MuxOscRc16M = 3U, + kCLOCK_CKO2_ClockRoot_MuxSysPll2Pfd3 = 4U, + kCLOCK_CKO2_ClockRoot_MuxOscRc48M = 5U, + kCLOCK_CKO2_ClockRoot_MuxSysPll3Pfd1 = 6U, + kCLOCK_CKO2_ClockRoot_MuxAudioPllOut = 7U, } clock_root_mux_source_t; typedef enum _clock_group @@ -1945,23 +1760,11 @@ typedef enum _clock_group kCLOCK_Group_Last, } clock_group_t; - typedef struct _clock_group_config { - bool clockOff; /*!< Turn off the clock. */ + bool clockOff; /*!< Turn off the clock. */ uint16_t resetDiv; /*!< resetDiv + 1 should be common multiple of all dividers, valid range 0 ~ 255. */ - uint8_t div0 ; /*!< Divide root clock by div0 + 1, valid range: 0 ~ 15. */ - uint8_t div1 ; /*!< Divide root clock by div1 + 1, valid range: 0 ~ 15. */ - uint8_t div2 ; /*!< Divide root clock by div2 + 1, valid range: 0 ~ 15. */ - uint8_t div3 ; /*!< Divide root clock by div3 + 1, valid range: 0 ~ 15. */ - uint8_t div4 ; /*!< Divide root clock by div4 + 1, valid range: 0 ~ 15. */ - uint8_t div5 ; /*!< Divide root clock by div5 + 1, valid range: 0 ~ 15. */ - uint8_t div6 ; /*!< Divide root clock by div6 + 1, valid range: 0 ~ 15. */ - uint8_t div7 ; /*!< Divide root clock by div7 + 1, valid range: 0 ~ 15. */ - uint8_t div8 ; /*!< Divide root clock by div8 + 1, valid range: 0 ~ 15. */ - uint8_t div9 ; /*!< Divide root clock by div9 + 1, valid range: 0 ~ 15. */ - uint8_t div10; /*!< Divide root clock by div10 + 1, valid range: 0 ~ 15. */ - uint8_t div11; /*!< Divide root clock by div11 + 1, valid range: 0 ~ 15. */ + uint8_t div0; /*!< Divide root clock by div0 + 1, valid range: 0 ~ 15. */ } clock_group_config_t; #define clock_ip_name_t clock_lpcg_t @@ -1980,21 +1783,21 @@ typedef struct _clock_group_config /*! @brief OSC 24M sorce select */ typedef enum _clock_osc { - kCLOCK_RcOsc = 0U, /*!< On chip OSC. */ + kCLOCK_RcOsc = 0U, /*!< On chip OSC. */ kCLOCK_XtalOsc = 1U, /*!< 24M Xtal OSC */ } clock_osc_t; /*! @brief Clock gate value */ typedef enum _clock_gate_value { - kCLOCK_Off = (int)~CCM_LPCG_DIRECT_ON_MASK, /*!< Clock is off. */ - kCLOCK_On = CCM_LPCG_DIRECT_ON_MASK, /*!< Clock is on*/ + kCLOCK_Off = (int)~CCM_LPCG_DIRECT_ON_MASK, /*!< Clock is off. */ + kCLOCK_On = CCM_LPCG_DIRECT_ON_MASK, /*!< Clock is on*/ } clock_gate_value_t; /*! @brief System clock mode */ typedef enum _clock_mode_t { - kCLOCK_ModeRun = 0U, /*!< Remain in run mode. */ + kCLOCK_ModeRun = 0U, /*!< Remain in run mode. */ kCLOCK_ModeWait = 1U, /*!< Transfer to wait mode. */ kCLOCK_ModeStop = 2U, /*!< Transfer to stop mode. */ } clock_mode_t; @@ -2002,7 +1805,7 @@ typedef enum _clock_mode_t /*! @brief USB clock source definition. */ typedef enum _clock_usb_src { - kCLOCK_Usb480M = 0, /*!< Use 480M. */ + kCLOCK_Usb480M = 0, /*!< Use 480M. */ kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, /*!< Used when the function does not care the clock source. */ } clock_usb_src_t; @@ -2017,7 +1820,7 @@ typedef enum _clock_usb_phy_src enum _clock_pll_clk_src { kCLOCK_PllClkSrc24M = 0U, /*!< Pll clock source 24M */ - kCLOCK_PllSrcClkPN = 1U, /*!< Pll clock source CLK1_P and CLK1_N */ + kCLOCK_PllSrcClkPN = 1U, /*!< Pll clock source CLK1_P and CLK1_N */ }; typedef enum _clock_pll_post_div @@ -2040,7 +1843,7 @@ typedef enum _clock_pll_post_div typedef struct _clock_arm_pll_config { clock_pll_post_div_t postDivider; /*!< Post divider. */ - uint32_t loopDivider; /*!< PLL loop divider. Valid range: 104-208. */ + uint32_t loopDivider; /*!< PLL loop divider. Valid range: 104-208. */ } clock_arm_pll_config_t; /*! @brief PLL configuration for USB */ @@ -2053,40 +1856,58 @@ typedef struct _clock_usb_pll_config } clock_usb_pll_config_t; -typedef struct _clock_sys_pll3_config +/*! @brief Spread specturm configure Pll */ +typedef struct _clock_pll_ss_config { - uint32_t divSelect; -} clock_sys_pll3_config_t; + uint16_t stop; /*!< Spread spectrum stop value to get frequency change. */ + uint16_t step; /*!< Spread spectrum step value to get frequency change step. */ +} clock_pll_ss_config_t; -/*! @brief PLL configuration for System */ -typedef struct _clock_sys_pll_config +/*! @brief PLL configure for Sys Pll2 */ +typedef struct _clock_sys_pll2_config { - uint8_t loopDivider; /*!< PLL loop divider. Intended to be 1 (528M). - 0 - Fout=Fref*20; - 1 - Fout=Fref*22 */ - uint32_t mfn; /*!< 30 bit mfn of fractional loop divider.*/ - uint32_t mfi; /*!< 30 bit of fractional loop divider */ - uint16_t ss_stop; /*!< Stop value to get frequency change. */ - uint8_t ss_enable; /*!< Enable spread spectrum modulation */ - uint16_t ss_step; /*!< Step value to get frequency change step. */ -} clock_sys_pll_config_t; + uint32_t mfd; /*!< Denominator of spread spectrum */ + clock_pll_ss_config_t *ss; /*!< Spread spectrum parameter, + it can be NULL, if ssEnable is set to false */ + bool ssEnable; /*!< Enable spread spectrum flag */ +} clock_sys_pll2_config_t; /*! @brief PLL configure for Sys Pll1 */ typedef struct _clock_sys_pll1_config { - bool pllDiv2En; /*!< Enable Sys Pll1 divide-by-2 clock or not. */ - bool pllDiv5En; /*!< Enable Sys Pll1 divide-by-5 clock or not. */ + bool pllDiv2En; /*!< Enable Sys Pll1 divide-by-2 clock or not. */ + bool pllDiv5En; /*!< Enable Sys Pll1 divide-by-5 clock or not. */ + clock_pll_ss_config_t *ss; /*!< Spread spectrum parameter, + it can be NULL, if ssEnable is set to false */ + bool ssEnable; /*!< Enable spread spectrum flag */ } clock_sys_pll1_config_t; /*! @brief PLL configuration for AUDIO and VIDEO */ typedef struct _clock_audio_pll_config { - uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */ - uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16, 32. */ - uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ - uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */ + uint8_t postDivider; /*!< Divider after the PLL, 0x0=divided by 1, 0x1=divided by 2, 0x2=divided by 4, + 0x3=divided by 8, 0x4=divided by 16, 0x5=divided by 32.*/ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + clock_pll_ss_config_t *ss; /*!< Spread spectrum parameter, + it can be NULL, if ssEnable is set to false */ + bool ssEnable; /*!< Enable spread spectrum flag */ } clock_av_pll_config_t, clock_audio_pll_config_t, clock_video_pll_config_t; +/*! + * @brief PLL configuration fro AUDIO PLL, SYSTEM PLL1 and VIDEO PLL. + */ +typedef struct _clock_audio_pll_gpc_config +{ + uint8_t loopDivider; /*!< PLL loop divider. */ + uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/ + uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */ + clock_pll_ss_config_t *ss; /*!< Spread spectrum parameter, + it can be NULL, if ssEnable is set to false */ + bool ssEnable; /*!< Enable spread spectrum flag */ +} clock_audio_pll_gpc_config_t, clock_video_pll_gpc_config_t, clock_sys_pll1_gpc_config_t; + /*! @brief PLL configuration for ENET */ typedef struct _clock_enet_pll_config { @@ -2106,15 +1927,23 @@ typedef struct _clock_enet_pll_config b11 125MHz */ } clock_enet_pll_config_t; +/*! @brief Clock root configuration */ typedef struct _clock_root_config_t { bool clockOff; - uint8_t mfn; - uint8_t mfd; - uint8_t mux; /*!< See #clock_root_mux_source_t for details. */ - uint8_t div; /*!< it's the actual divider */ + uint8_t mux; /*!< See #clock_root_mux_source_t for details. */ + uint8_t div; /*!< it's the actual divider */ } clock_root_config_t; +/*! @brief Clock root configuration in SetPoint Mode */ +typedef struct _clock_root_setpoint_config_t +{ + uint8_t grade; /*!< Indicate speed grade for each SetPoint */ + bool clockOff; + uint8_t mux; /*!< See #clock_root_mux_source_t for details. */ + uint8_t div; /*!< it's the actual divider */ +} clock_root_setpoint_config_t; + /*! @brief PLL name */ typedef enum _clock_pll { @@ -2137,6 +1966,59 @@ typedef enum _clock_pfd kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */ } clock_pfd_t; +/*! + * @brief The enumeration of control mode. + * + */ +typedef enum _clock_control_mode +{ + kCLOCK_SoftwareMode = 0U, /*!< Software control mode. */ + kCLOCK_GpcMode, /*!< GPC control mode. */ +} clock_control_mode_t; + +/*! + * @brief The enumeration of 24MHz crystal oscillator mode. + */ +typedef enum _clock_24MOsc_mode +{ + kCLOCK_24MOscHighGainMode = 0U, /*!< 24MHz crystal oscillator work as high gain mode. */ + kCLOCK_24MOscBypassMode = 1U, /*!< 24MHz crystal oscillator work as bypass mode. */ + kCLOCK_24MOscLowPowerMode = 2U, /*!< 24MHz crystal oscillator work as low power mode. */ +} clock_24MOsc_mode_t; + +/*! + * @brief The enumeration of 16MHz RC oscillator clock source. + */ +typedef enum _clock_16MOsc_source +{ + kCLOCK_16MOscSourceFrom16MOsc = 0U, /*!< Source from 16MHz RC oscialltor. */ + kCLOCK_16MOscSourceFrom24MOsc = 1U, /*!< Source from 24MHz crystal oscillator. */ +} clock_16MOsc_source_t; + +/*! + * @brief The enumeration of 1MHz output clock behavior, including disabling 1MHz output, + * enabling locked 1MHz clock output, and enabling free-running 1MHz clock output. + */ +typedef enum _clock_1MHzOut_behavior +{ + kCLOCK_1MHzOutDisable = 0U, /*!< Disable 1MHz output clock. */ + kCLOCK_1MHzOutEnableLocked1Mhz = 1U, /*!< Enable 1MHz output clock, and select locked 1MHz to output. */ + kCLOCK_1MHzOutEnableFreeRunning1Mhz = 2U, /*!< Enable 1MHZ output clock, + and select free-running 1MHz to output. */ +} clock_1MHzOut_behavior_t; + +/*! + * @breif The clock dependence level. + */ +typedef enum _clock_level +{ + kCLOCK_Level0 = 0x0UL, /*!< Not needed in any mode. */ + kCLOCK_Level1 = 0x1UL, /*!< Needed in RUN mode. */ + kCLOCK_Level2 = 0x2UL, /*!< Needed in RUN and WAIT mode. */ + kCLOCK_Level3 = 0x3UL, /*!< Needed in RUN, WAIT and STOP mode. */ + kCLOCK_Level4 = 0x4UL, /*!< Always on in any mode. */ +} clock_level_t; + /******************************************************************************* * API ******************************************************************************/ @@ -2153,10 +2035,9 @@ extern "C" { */ static inline void CLOCK_SetRootClockMux(clock_root_t root, uint8_t src) { - assert(src < 8); + assert(src < 8U); CCM->CLOCK_ROOT[root].CONTROL = - (CCM->CLOCK_ROOT[root].CONTROL & ~(CCM_CLOCK_ROOT_CONTROL_MUX_MASK)) - | CCM_CLOCK_ROOT_CONTROL_MUX(src); + (CCM->CLOCK_ROOT[root].CONTROL & ~(CCM_CLOCK_ROOT_CONTROL_MUX_MASK)) | CCM_CLOCK_ROOT_CONTROL_MUX(src); __DSB(); __ISB(); #if __CORTEX_M == 4 @@ -2184,7 +2065,6 @@ static inline uint32_t CLOCK_GetRootClockMux(clock_root_t root) */ static inline clock_name_t CLOCK_GetRootClockSource(clock_root_t root, uint32_t src) { - const clock_name_t source[][8] = ROOT_CLOCK_SOURCES; return source[root][src]; } @@ -2197,9 +2077,8 @@ static inline clock_name_t CLOCK_GetRootClockSource(clock_root_t root, uint32_t static inline void CLOCK_SetRootClockDiv(clock_root_t root, uint8_t div) { assert(div); - CCM->CLOCK_ROOT[root].CONTROL = - (CCM->CLOCK_ROOT[root].CONTROL & ~CCM_CLOCK_ROOT_CONTROL_DIV_MASK) - | CCM_CLOCK_ROOT_CONTROL_DIV(div - 1); + CCM->CLOCK_ROOT[root].CONTROL = (CCM->CLOCK_ROOT[root].CONTROL & ~CCM_CLOCK_ROOT_CONTROL_DIV_MASK) | + CCM_CLOCK_ROOT_CONTROL_DIV((uint32_t)div - 1UL); __DSB(); __ISB(); #if __CORTEX_M == 4 @@ -2215,8 +2094,8 @@ static inline void CLOCK_SetRootClockDiv(clock_root_t root, uint8_t div) */ static inline uint32_t CLOCK_GetRootClockDiv(clock_root_t root) { - return ((CCM->CLOCK_ROOT[root].CONTROL - & CCM_CLOCK_ROOT_CONTROL_DIV_MASK) >> CCM_CLOCK_ROOT_CONTROL_DIV_SHIFT) + 1; + return ((CCM->CLOCK_ROOT[root].CONTROL & CCM_CLOCK_ROOT_CONTROL_DIV_MASK) >> CCM_CLOCK_ROOT_CONTROL_DIV_SHIFT) + + 1UL; } /*! @@ -2226,7 +2105,7 @@ static inline uint32_t CLOCK_GetRootClockDiv(clock_root_t root) */ static inline void CLOCK_PowerOffRootClock(clock_root_t root) { - if (!(CCM->CLOCK_ROOT[root].CONTROL & CCM_CLOCK_ROOT_CONTROL_OFF_MASK)) + if (0UL == (CCM->CLOCK_ROOT[root].CONTROL & CCM_CLOCK_ROOT_CONTROL_OFF_MASK)) { CCM->CLOCK_ROOT[root].CONTROL_SET = CCM_CLOCK_ROOT_CONTROL_OFF_MASK; __DSB(); @@ -2252,26 +2131,6 @@ static inline void CLOCK_PowerOnRootClock(clock_root_t root) #endif } -/*! - * @brief Set MFN and MFD Root Clock - * - * @param root Which root clock node to set, see \ref clock_root_t. - * @param mfn MFN value - * @param mfd MFD value - */ -static inline void CLOCK_SetRootClockMFx(clock_root_t root, uint32_t mfn, uint32_t mfd) -{ - CCM->CLOCK_ROOT[root].CONTROL = - (CCM->CLOCK_ROOT[root].CONTROL & - ~(CCM_CLOCK_ROOT_CONTROL_MFN_MASK | CCM_CLOCK_ROOT_CONTROL_MFD_MASK)) - | (CCM_CLOCK_ROOT_CONTROL_MFN(mfn) | CCM_CLOCK_ROOT_CONTROL_MFD(mfd)); - __DSB(); - __ISB(); -#if __CORTEX_M == 4 - (void)CCM->CLOCK_ROOT[root].CONTROL; -#endif -} - /*! * @brief Configure Root Clock * @@ -2281,11 +2140,9 @@ static inline void CLOCK_SetRootClockMFx(clock_root_t root, uint32_t mfn, uint32 static inline void CLOCK_SetRootClock(clock_root_t root, const clock_root_config_t *config) { assert(config); - CCM->CLOCK_ROOT[root].CONTROL = CCM_CLOCK_ROOT_CONTROL_MFN(config->mfn) - | CCM_CLOCK_ROOT_CONTROL_MFD(config->mfd) - | CCM_CLOCK_ROOT_CONTROL_MUX(config->mux) - | CCM_CLOCK_ROOT_CONTROL_DIV(config->div - 1) - | (config->clockOff ? CCM_CLOCK_ROOT_CONTROL_OFF(config->clockOff) : 0); + CCM->CLOCK_ROOT[root].CONTROL = CCM_CLOCK_ROOT_CONTROL_MUX(config->mux) | + CCM_CLOCK_ROOT_CONTROL_DIV((uint32_t)config->div - 1UL) | + (config->clockOff ? CCM_CLOCK_ROOT_CONTROL_OFF(config->clockOff) : 0UL); __DSB(); __ISB(); #if __CORTEX_M == 4 @@ -2296,14 +2153,16 @@ static inline void CLOCK_SetRootClock(clock_root_t root, const clock_root_config /*! * @brief Control the clock gate for specific IP. * + * @note This API will not have any effect when this clock is in CPULPM or SetPoint Mode + * * @param name Which clock to enable, see \ref clock_ip_name_t. * @param value Clock gate value to set, see \ref clock_gate_value_t. */ static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value) { - if ((value & CCM_LPCG_DIRECT_ON_MASK) != (CCM->LPCG[name].DIRECT & CCM_LPCG_DIRECT_ON_MASK)) + if (((uint32_t)value & CCM_LPCG_DIRECT_ON_MASK) != (CCM->LPCG[name].DIRECT & CCM_LPCG_DIRECT_ON_MASK)) { - CCM->LPCG[name].DIRECT = (value & CCM_LPCG_DIRECT_ON_MASK); + CCM->LPCG[name].DIRECT = ((uint32_t)value & CCM_LPCG_DIRECT_ON_MASK); __DSB(); __ISB(); #if __CORTEX_M == 4 @@ -2340,15 +2199,6 @@ static inline void CLOCK_DisableClock(clock_ip_name_t name) */ void CLOCK_SetGroupConfig(clock_group_t group, const clock_group_config_t *config); -/*! - * @brief Setting the low power mode that system will enter on next assertion of dsm_request signal. - * - * @param mode Which mode to enter, see \ref clock_mode_t. - */ -static inline void CLOCK_SetMode(clock_mode_t mode) -{ -} - /*! * @brief Gets the clock frequency for a specific clock name. * @@ -2372,8 +2222,7 @@ uint32_t CLOCK_GetFreq(clock_name_t name); static inline uint32_t CLOCK_GetRootClockFreq(clock_root_t root) { uint32_t freq, mux; - const clock_name_t source[][8] = ROOT_CLOCK_SOURCES; - mux = CLOCK_GetRootClockMux(root); + mux = CLOCK_GetRootClockMux(root); freq = CLOCK_GetFreq(source[root][mux]) / (CLOCK_GetRootClockDiv(root)); assert(freq); return freq; @@ -2399,6 +2248,68 @@ static inline uint32_t CLOCK_GetM4Freq(void) return CLOCK_GetRootClockFreq(kCLOCK_Root_M4); } +/*! + * @brief Check if PLL is bypassed + * + * @param base CCM_ANALOG base pointer. + * @param pll PLL control name (see @ref clock_pll_t enumeration) + * @return PLL bypass status. + * - true: The PLL is bypassed. + * - false: The PLL is not bypassed. + */ +static inline bool CLOCK_IsPllBypassed(clock_pll_t pll) +{ + switch (pll) + { + case kCLOCK_PllArm: + return (bool)((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK) >> + ANADIG_PLL_ARM_PLL_CTRL_BYPASS_SHIFT); + case kCLOCK_PllSys2: + return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK) >> + ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_SHIFT); + case kCLOCK_PllSys3: + return (bool)((ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK) >> + ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_SHIFT); + default: + return false; + } +} + +/*! + * @brief Check if PLL is enabled + * + * @param pll PLL control name (see @ref clock_pll_t enumeration) + * @return PLL bypass status. + * - true: The PLL is enabled. + * - false: The PLL is not enabled. + */ +static inline bool CLOCK_IsPllEnabled(clock_pll_t pll) +{ + switch (pll) + { + case kCLOCK_PllArm: + return (bool)((ANADIG_PLL->ARM_PLL_CTRL & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK) >> + ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_SHIFT); + case kCLOCK_PllSys2: + return (bool)((ANADIG_PLL->SYS_PLL2_CTRL & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK) >> + ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_SHIFT); + case kCLOCK_PllSys3: + return (bool)((ANADIG_PLL->SYS_PLL3_CTRL & ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK) >> + ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_SHIFT); + case kCLOCK_PllSys1: + return (bool)((ANADIG_PLL->SYS_PLL1_CTRL & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK) >> + ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_SHIFT); + case kCLOCK_PllAudio: + return (bool)((ANADIG_PLL->PLL_AUDIO_CTRL & ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK) >> + ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_SHIFT); + case kCLOCK_PllVideo: + return (bool)((ANADIG_PLL->PLL_VIDEO_CTRL & ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK) >> + ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_SHIFT); + default: + return false; + } +} + /*! * @name OSC operations * @{ @@ -2450,52 +2361,296 @@ static inline uint32_t CLOCK_GetRtcFreq(void) } /*! - * @brief Initialize the RC oscillator 24MHz clock. + * @brief Set the control mode of 48MHz RC oscillator. + * + * @param controlMode The control mode to be set, please refer to @ref clock_control_mode_t. */ -void CLOCK_InitRcOsc24M(void); +static inline void CLOCK_OSC_SetOsc48MControlMode(clock_control_mode_t controlMode) +{ + ANADIG_OSC->OSC_48M_CTRL = (ANADIG_OSC->OSC_48M_CTRL & ~(ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_MASK)) | + ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE(controlMode); +} /*! - * @brief Power down the RCOSC 24M clock. + * @brief Enable/disable 48MHz RC oscillator. + * + * @param enable Used to enable or disable the 48MHz RC oscillator. + * - \b true Enable the 48MHz RC oscillator. + * - \b false Dissable the 48MHz RC oscillator. */ -void CLOCK_DeinitRcOsc24M(void); -/* @} */ +static inline void CLOCK_OSC_EnableOsc48M(bool enable) +{ + if (enable) + { + ANADIG_OSC->OSC_48M_CTRL |= ANADIG_OSC_OSC_48M_CTRL_TEN_MASK; + } + else + { + ANADIG_OSC->OSC_48M_CTRL &= ~ANADIG_OSC_OSC_48M_CTRL_TEN_MASK; + } +} -/*! @brief Enable USB HS clock. - * - * This function only enables the access to USB HS prepheral, upper layer - * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY - * clock to use USB HS. +/*! + * @brief Set the control mode of the 24MHz clock sourced from 48MHz RC oscillator. * - * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. - * @param freq USB HS does not care about the clock source, so this parameter is ignored. - * @retval true The clock is set successfully. - * @retval false The clock source is invalid to get proper USB HS clock. + * @param controlMode The control mode to be set, please refer to @ref clock_control_mode_t. */ -bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq); +static inline void CLOCK_OSC_SetOsc48MDiv2ControlMode(clock_control_mode_t controlMode) +{ + ANADIG_OSC->OSC_48M_CTRL = (ANADIG_OSC->OSC_48M_CTRL & ~(ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_MASK)) | + ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE(controlMode); +} -/*! @brief Enable USB HS clock. +/*! + * @brief Enable/disable the 24MHz clock sourced from 48MHz RC oscillator. * - * This function only enables the access to USB HS prepheral, upper layer - * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY - * clock to use USB HS. + * @note The 48MHz RC oscillator must be enabled before enabling this 24MHz clock. * - * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused. - * @param freq USB HS does not care about the clock source, so this parameter is ignored. - * @retval true The clock is set successfully. - * @retval false The clock source is invalid to get proper USB HS clock. + * @param enable Used to enable/disable the 24MHz clock sourced from 48MHz RC oscillator. + * - \b true Enable the 24MHz clock sourced from 48MHz. + * - \b false Disable the 24MHz clock sourced from 48MHz. */ -bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq); +static inline void CLOCK_OSC_EnableOsc48MDiv2(bool enable) +{ + if (enable) + { + ANADIG_OSC->OSC_48M_CTRL |= ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK; + } + else + { + ANADIG_OSC->OSC_48M_CTRL &= ~ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK; + } +} -/*! @brief Disable USB HS PHY PLL clock. +/*! + * @brief Set the control mode of 24MHz crystal oscillator. * - * This function disables USB HS PHY PLL clock. + * @param controlMode The control mode to be set, please refer to @ref clock_control_mode_t. */ -void CLOCK_DisableUsbhs1PhyPllClock(void); +static inline void CLOCK_OSC_SetOsc24MControlMode(clock_control_mode_t controlMode) +{ + ANADIG_OSC->OSC_24M_CTRL = (ANADIG_OSC->OSC_24M_CTRL & ~(ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_MASK)) | + ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE(controlMode); +} -/* @} */ +/*! @brief Enable OSC 24Mhz + * + * This function enables OSC 24Mhz. + */ +void CLOCK_OSC_EnableOsc24M(void); /*! - * @brief Initialize the ARM PLL. + * @brief Gate/ungate the 24MHz crystal oscillator output. + * + * @note Gating the 24MHz crystal oscillator can save power. + * + * @param enableGate Used to gate/ungate the 24MHz crystal oscillator. + * - \b true Gate the 24MHz crystal oscillator to save power. + * - \b false Ungate the 24MHz crystal oscillator. + */ +static inline void CLOCK_OSC_GateOsc24M(bool enableGate) +{ + if (enableGate) + { + ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK; + } + else + { + ANADIG_OSC->OSC_24M_CTRL &= ~ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK; + } +} + +/*! + * @brief Set the work mode of 24MHz crystal oscillator, the available modes are high gian mode, low power mode, and + * bypass mode. + * + * @param workMode The work mode of 24MHz crystal oscillator, please refer to @ref clock_24MOsc_mode_t for details. + */ +void CLOCK_OSC_SetOsc24MWorkMode(clock_24MOsc_mode_t workMode); + +/*! + * @brief Set the control mode of 400MHz RC oscillator. + * + * @param controlMode The control mode to be set, please refer to @ref clock_control_mode_t. + */ +static inline void CLOCK_OSC_SetOscRc400MControlMode(clock_control_mode_t controlMode) +{ + ANADIG_OSC->OSC_400M_CTRL1 = (ANADIG_OSC->OSC_400M_CTRL1 & (~ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_MASK)) | + ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE(controlMode); +} + +/*! @brief Enable OSC RC 400Mhz + * + * This function enables OSC RC 400Mhz. + */ +void CLOCK_OSC_EnableOscRc400M(void); + +/*! + * @brief Gate/ungate 400MHz RC oscillator. + * + * @param enableGate Used to gate/ungate 400MHz RC oscillator. + * - \b true Gate the 400MHz RC oscillator. + * - \b false Ungate the 400MHz RC oscillator. + */ +static inline void CLOCK_OSC_GateOscRc400M(bool enableGate) +{ + if (enableGate) + { + ANADIG_OSC->OSC_400M_CTRL1 |= ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK; + } + else + { + ANADIG_OSC->OSC_400M_CTRL1 &= ~ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK; + } +} + +/*! + * @brief Trims OSC RC 400MHz. + * + * @param enable Used to enable trim function. + * @param bypass Bypass the trim function. + * @param trim Trim value. + */ +void CLOCK_OSC_TrimOscRc400M(bool enable, bool bypass, uint16_t trim); + +/*! + * @brief Set the divide value for ref_clk to generate slow clock. + * + * @note slow_clk = ref_clk / (divValue + 1), and the recommand divide value is 24. + * + * @param divValue The divide value to be set, the available range is 0~63. + */ +void CLOCK_OSC_SetOscRc400MRefClkDiv(uint8_t divValue); + +/*! + * @brief Set the target count for the fast clock. + * + * @param targetCount The desired target for the fast clock, should be the number of clock cycles of the fast_clk per + * divided ref_clk. + */ +void CLOCK_OSC_SetOscRc400MFastClkCount(uint16_t targetCount); + +/*! + * @brief Set the negative and positive hysteresis value for the tuned clock. + * + * @note The hysteresis value should be set after the clock is tuned. + * + * @param negHysteresis The negative hysteresis value for the turned clock, this value in number of clock cycles of the + * fast clock + * @param posHysteresis The positive hysteresis value for the turned clock, this value in number of clock cycles of the + * fast clock + */ +void CLOCK_OSC_SetOscRc400MHysteresisValue(uint8_t negHysteresis, uint8_t posHysteresis); + +/*! + * @brief Bypass/un-bypass the tune logic + * + * @param enableBypass Used to control whether to bypass the turn logic. + * - \b true Bypass the tune logic and use the programmed oscillator frequency to run the oscillator. + * Function CLOCK_OSC_SetOscRc400MTuneValue() can be used to set oscillator frequency. + * - \b false Use the output of tune logic to run the oscillator. + */ +void CLOCK_OSC_BypassOscRc400MTuneLogic(bool enableBypass); + +/*! + * @brief Start/Stop the tune logic. + * + * @param enable Used to start or stop the tune logic. + * - \b true Start tuning + * - \b false Stop tuning and reset the tuning logic. + */ +void CLOCK_OSC_EnableOscRc400MTuneLogic(bool enable); + +/*! + * @brief Freeze/Unfreeze the tuning value. + * + * @param enableFreeze Used to control whether to freeze the tune value. + * - \b true Freeze the tune at the current tuned value and the oscillator runs at tje frozen tune value. + * - \b false Unfreezes and continues the tune operation. + */ +void CLOCK_OSC_FreezeOscRc400MTuneValue(bool enableFreeze); + +/*! + * @brief Set the 400MHz RC oscillator tune value when the tune logic is disabled. + * + * @param tuneValue The tune value to determine the frequency of Oscillator. + */ +void CLOCK_OSC_SetOscRc400MTuneValue(uint8_t tuneValue); + +/*! + * @brief Set the behavior of the 1MHz output clock, such as disable the 1MHz clock output, + * enable the free-running 1MHz clock output, enable the locked 1MHz clock output. + * + * @note The 1MHz clock is divided from 400M RC Oscillator. + * + * @param behavior The behavior of 1MHz output clock, please refer to @ref clock_1MHzOut_behavior_t for details. + */ +void CLOCK_OSC_Set1MHzOutputBehavior(clock_1MHzOut_behavior_t behavior); + +/*! + * @brief Set the count for the locked 1MHz clock out. + * + * @param count Used to set the desired target for the locked 1MHz clock out, the value in number of clock cycles of the + * fast clock per divided ref_clk. + */ +void CLOCK_OSC_SetLocked1MHzCount(uint16_t count); + +/*! + * @brief Check the error flag for locked 1MHz clock out. + * + * @return The error flag for locked 1MHz clock out. + * - \b true The count value has been reached within one diviced ref clock period + * - \b false No effect. + */ +bool CLOCK_OSC_CheckLocked1MHzErrorFlag(void); + +/*! + * @brief Clear the error flag for locked 1MHz clock out. + */ +void CLOCK_OSC_ClearLocked1MHzErrorFlag(void); + +/*! + * @brief Get current count for the fast clock during the tune process. + * + * @return The current count for the fast clock. + */ +uint16_t CLOCK_OSC_GetCurrentOscRc400MFastClockCount(void); + +/*! + * @brief Get current tune value used by oscillator during tune process. + * + * @return The current tune value. + */ +uint8_t CLOCK_OSC_GetCurrentOscRc400MTuneValue(void); + +/*! + * @brief Set the control mode of 16MHz crystal oscillator. + * + * @param controlMode The control mode to be set, please refer to @ref clock_control_mode_t. + */ +static inline void CLOCK_OSC_SetOsc16MControlMode(clock_control_mode_t controlMode) +{ + ANADIG_OSC->OSC_16M_CTRL = (ANADIG_OSC->OSC_16M_CTRL & (~ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_MASK)) | + ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE(controlMode); +} + +/*! + * @brief Configure the 16MHz oscillator. + * + * @param source Used to select the source for 16MHz RC oscillator, please refer to @ref clock_16MOsc_source_t. + * @param enablePowerSave Enable/disable power save mode function at 16MHz OSC. + * - \b true Enable power save mode function at 16MHz osc. + * - \b false Disable power save mode function at 16MHz osc. + * @param enableClockOut Enable/Disable clock output for 16MHz RCOSC. + * - \b true Enable clock output for 16MHz RCOSC. + * - \b false Disable clock output for 16MHz RCOSC. + */ +void CLOCK_OSC_SetOsc16MConfig(clock_16MOsc_source_t source, bool enablePowerSave, bool enableClockOut); + +/* @} */ + +/*! + * @brief Initialize the ARM PLL. * * This function initialize the ARM PLL with specific settings * @@ -2508,10 +2663,10 @@ void CLOCK_InitArmPll(const clock_arm_pll_config_t *config); * * This function calculates config valudes per given frequency for Arm PLL * - * @param cfg pll config structure + * @param config pll config structure * @param freqInMhz target frequency */ -status_t CLOCK_CalcArmPllFreq(clock_arm_pll_config_t *cfg, uint32_t freqInMhz); +status_t CLOCK_CalcArmPllFreq(clock_arm_pll_config_t *config, uint32_t freqInMhz); /*! * @brief Initializes the Arm PLL with Specific Frequency (in Mhz). @@ -2527,6 +2682,21 @@ status_t CLOCK_InitArmPllWithFreq(uint32_t freqInMhz); */ void CLOCK_DeinitArmPll(void); +/*! + * @brief Calculate spread spectrum step and stop. + * + * This function calculate spread spectrum step and stop according to given + * parameters. For integer PLL (syspll2) the factor is mfd, while for other + * fractional PLLs (audio/video/syspll1), the factor is denominator. + * + * @param factor factor to calculate step/stop + * @param range spread spectrum range + * @param mod spread spectrum modulation frequency + * @param ss calculated spread spectrum values + * + */ +void CLOCK_CalcPllSpreadSpectrum(uint32_t factor, uint32_t range, uint32_t mod, clock_pll_ss_config_t *ss); + /*! * @brief Initialize the System PLL1. * @@ -2541,14 +2711,22 @@ void CLOCK_InitSysPll1(const clock_sys_pll1_config_t *config); */ void CLOCK_DeinitSysPll1(void); +/*! + * @brief Set System PLL1 output frequency in GPC mode. + * + * @param config Pointer to @ref clock_sys_pll1_gpc_config_t. + */ +void CLOCK_GPC_SetSysPll1OutputFreq(const clock_sys_pll1_gpc_config_t *config); + /*! * @brief Initialize the System PLL2. * * This function initializes the System PLL2 with specific settings * - * @param config Configuration to set to PLL2. + * @param config Configuration to configure spread spectrum. This parameter can + * be NULL, if no need to enabled spread spectrum */ -void CLOCK_InitSysPll2(const clock_sys_pll_config_t *config); +void CLOCK_InitSysPll2(const clock_sys_pll2_config_t *config); /*! * @brief De-initialize the System PLL2. @@ -2560,25 +2738,38 @@ void CLOCK_DeinitSysPll2(void); * * This function initializes the System PLL3 with specific settings * - * @param config Configuration to set to PLL3. */ -void CLOCK_InitSysPll3(const clock_sys_pll3_config_t *config); +void CLOCK_InitSysPll3(void); /*! * @brief De-initialize the System PLL3. */ void CLOCK_DeinitSysPll3(void); +/*! + * @name PLL/PFD operations + * @{ + */ +/*! + * @brief PLL bypass setting + * + * @param pll PLL control name (see @ref clock_pll_t enumeration) + * @param bypass Bypass the PLL. + * - true: Bypass the PLL. + * - false:Not bypass the PLL. + */ +void CLOCK_SetPllBypass(clock_pll_t pll, bool bypass); + /*! * @brief Calculate corresponding config values per given frequency * * This function calculates config valudes per given frequency for Audio/Video * PLL. * - * @param cfg pll config structure + * @param config pll config structure * @param freqInMhz target frequency */ -status_t CLOCK_CalcAvPllFreq(clock_av_pll_config_t *cfg, uint32_t freqInMhz); +status_t CLOCK_CalcAvPllFreq(clock_av_pll_config_t *config, uint32_t freqInMhz); /*! * @brief Initializes the Audio PLL with Specific Frequency (in Mhz). @@ -2586,8 +2777,11 @@ status_t CLOCK_CalcAvPllFreq(clock_av_pll_config_t *cfg, uint32_t freqInMhz); * This function initializes the Audio PLL with specific frequency * * @param freqInMhz target frequency + * @param ssEnable enable spread spectrum or not + * @param ssRange range spread spectrum range + * @param ssMod spread spectrum modulation frequency */ -status_t CLOCK_InitAudioPllWithFreq(uint32_t freqInMhz); +status_t CLOCK_InitAudioPllWithFreq(uint32_t freqInMhz, bool ssEnable, uint32_t ssRange, uint32_t ssMod); /*! * @brief Initializes the Audio PLL. @@ -2595,6 +2789,7 @@ status_t CLOCK_InitAudioPllWithFreq(uint32_t freqInMhz); * This function initializes the Audio PLL with specific settings * * @param config Configuration to set to PLL. + * @param ss Configuration to set spread spectrum */ void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config); @@ -2603,14 +2798,24 @@ void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config); */ void CLOCK_DeinitAudioPll(void); +/*! + * @brief Set Audio PLL output frequency in GPC mode. + * + * @param config Pointer to @ref clock_audio_pll_gpc_config_t. + */ +void CLOCK_GPC_SetAudioPllOutputFreq(const clock_audio_pll_gpc_config_t *config); + /*! * @brief Initializes the Video PLL with Specific Frequency (in Mhz). * * This function initializes the Video PLL with specific frequency * * @param freqInMhz target frequency + * @param ssEnable enable spread spectrum or not + * @param ssRange range spread spectrum range + * @param ssMod spread spectrum modulation frequency */ -status_t CLOCK_InitVideoPllWithFreq(uint32_t freqInMhz); +status_t CLOCK_InitVideoPllWithFreq(uint32_t freqInMhz, bool ssEnable, uint32_t ssRange, uint32_t ssMod); /*! * @brief Initialize the video PLL. @@ -2626,6 +2831,12 @@ void CLOCK_InitVideoPll(const clock_video_pll_config_t *config); */ void CLOCK_DeinitVideoPll(void); +/*! + * @brief Set Video PLL output frequency in GPC mode. + * + * @param config Pointer to @ref clock_audio_pll_gpc_config_t. + */ +void CLOCK_GPC_SetVideoPllOutputFreq(const clock_video_pll_gpc_config_t *config); /*! * @brief Get current PLL output frequency. * @@ -2649,16 +2860,6 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll); */ void CLOCK_InitPfd(clock_pll_t pll, clock_pfd_t pfd, uint8_t frac); -/*! - * @brief De-initialize the System PLL PFD. - * - * This function disables the System PLL PFD. - * - * @param pll Which PLL of targeting PFD to be operated. - * @param pfd Which PFD clock to disable. - */ -void CLOCK_DeinitPfd(clock_pll_t pll, clock_pfd_t pfd); - /*! * @brief Get current PFD output frequency. * @@ -2672,25 +2873,6 @@ uint32_t CLOCK_GetPfdFreq(clock_pll_t pll, clock_pfd_t pfd); uint32_t CLOCK_GetFreqFromObs(uint32_t obsSigIndex, uint32_t obsIndex); -/*! @brief Enable OSC 24Mhz - * - * This function enables OSC 24Mhz. - */ -void CLOCK_EnableOsc24M(void); - -/*! @brief Enable PLL LDO - * - * This function enables PLL LDO. - * - */ -void CLOCK_EnablePllLdo(void); - -/*! @brief Enable OSC RC 400Mhz - * - * This function enables OSC RC 400Mhz. - */ -void CLOCK_EnableOscRc400M(void); - /*! @brief Enable USB HS clock. * * This function only enables the access to USB HS prepheral, upper layer @@ -2716,6 +2898,7 @@ bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq); * @retval false The clock source is invalid to get proper USB HS clock. */ bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq); + /*! @brief Enable USB HS PHY PLL clock. * * This function enables the internal 480MHz USB PHY PLL clock. @@ -2750,6 +2933,377 @@ bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq); */ void CLOCK_DisableUsbhs1PhyPllClock(void); +/*! + * @brief Lock low power and access control mode for this clock. + * + * @note When this bit is set, bits 16-20 can not be changed until next system reset. + * + * @param name Clock source name, see \ref clock_name_t. + */ +static inline void CLOCK_OSCPLL_LockControlMode(clock_name_t name) +{ + CCM->OSCPLL[name].AUTHEN |= CCM_OSCPLL_AUTHEN_LOCK_MODE_MASK; +} + +/*! + * @brief Lock the value of Domain ID white list for this clock. + * + * @note Once locked, this bit and domain ID white list can not be changed until next system reset. + * + * @param name Clock source name, see \ref clock_name_t. + */ +static inline void CLOCK_OSCPLL_LockWhiteList(clock_name_t name) +{ + CCM->OSCPLL[name].AUTHEN |= CCM_OSCPLL_AUTHEN_LOCK_LIST_MASK; +} + +/*! + * @brief Set domain ID that can change this clock. + * + * @note If LOCK_LIST bit is set, domain ID white list can not be changed until next system reset. + * + * @param name Clock source name, see \ref clock_name_t. + * @param domainId Domains that on the whitelist can change this clock. + */ +static inline void CLOCK_OSCPLL_SetWhiteList(clock_name_t name, uint8_t domainId) +{ + CCM->OSCPLL[name].AUTHEN = + (CCM->OSCPLL[name].AUTHEN & ~CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK) | CCM_OSCPLL_AUTHEN_WHITE_LIST(domainId); +} + +/*! + * @brief Check whether this clock implement SetPoint control scheme. + * + * @param name Clock source name, see \ref clock_name_t. + * @return Clock source SetPoint implement status. + * - true: SetPoint is implemented. + * - false: SetPoint is not implemented. + */ +static inline bool CLOCK_OSCPLL_IsSetPointImplemented(clock_name_t name) +{ + return ((CCM->OSCPLL[name].CONFIG & CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_MASK) >> + CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_SHIFT); +} + +/*! + * @brief Set this clock works in Unassigned Mode. + * + * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset. + * + * @param name Clock source name, see \ref clock_name_t. + */ +static inline void CLOCK_OSCPLL_ControlByUnassignedMode(clock_name_t name) +{ + CCM->OSCPLL[name].AUTHEN &= + ~(CCM_OSCPLL_AUTHEN_CPULPM_MASK | CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK | CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK); +} + +/*! + * @brief Set this clock works in SetPoint control Mode. + * + * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset. + * + * @param name Clock source name, see \ref clock_name_t. + * @param spValue Bit0~Bit15 hold value for Setpoint 0~16 respectively. + * A bitfield value of 0 implies clock will be shutdown in this Setpoint. + * A bitfield value of 1 implies clock will be turn on in this Setpoint. + * @param stbyValue Bit0~Bit15 hold value for Setpoint 0~16 standby. + * A bitfield value of 0 implies clock will be shutdown during standby. + * A bitfield value of 1 represent clock will keep Setpoint setting during standby. + */ +void CLOCK_OSCPLL_ControlBySetPointMode(clock_name_t name, uint16_t spValue, uint16_t stbyValue); + +/*! + * @brief Set this clock works in CPU Low Power Mode. + * + * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset. + * + * @param name Clock source name, see \ref clock_name_t. + * @param domainId Domains that on the whitelist can change this clock. + * @param level0,level1 Depend level of this clock. + */ +void CLOCK_OSCPLL_ControlByCpuLowPowerMode(clock_name_t name, + uint8_t domainId, + clock_level_t level0, + clock_level_t level1); + +/*! + * @brief Set clock depend level for current accessing domain. + * + * @note This setting only take effects in CPU Low Power Mode. + * + * @param name Clock source name, see \ref clock_name_t. + * @param level Depend level of this clock. + */ +static inline void CLOCK_OSCPLL_SetCurrentClockLevel(clock_name_t name, clock_level_t level) +{ + CCM->OSCPLL[name].DOMAINr = + (CCM->OSCPLL[name].DOMAINr & ~CCM_OSCPLL_DOMAIN_LEVEL_MASK) | CCM_OSCPLL_DOMAIN_LEVEL(level); +} + +/*! + * @brief Set this clock works in Domain Mode. + * + * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset. + * + * @param name Clock source name, see \ref clock_name_t. + * @param domainId Domains that on the whitelist can change this clock. + */ +static inline void CLOCK_OSCPLL_ControlByDomainMode(clock_name_t name, uint8_t domainId) +{ + CCM->OSCPLL[name].AUTHEN = + (CCM->OSCPLL[name].AUTHEN & + ~(CCM_OSCPLL_AUTHEN_CPULPM_MASK | CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK | CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK)) | + CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK | CCM_OSCPLL_AUTHEN_WHITE_LIST(domainId); +} + +/*! + * @brief Lock low power and access control mode for this clock. + * + * @note When this bit is set, bits 16-20 can not be changed until next system reset. + * + * @param name Clock root name, see \ref clock_root_t. + */ +static inline void CLOCK_ROOT_LockControlMode(clock_root_t name) +{ + CCM->CLOCK_ROOT[name].AUTHEN |= CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_MASK; +} + +/*! + * @brief Lock the value of Domain ID white list for this clock. + * + * @note Once locked, this bit and domain ID white list can not be changed until next system reset. + * + * @param name Clock root name, see \ref clock_root_t. + */ +static inline void CLOCK_ROOT_LockWhiteList(clock_root_t name) +{ + CCM->CLOCK_ROOT[name].AUTHEN |= CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_MASK; +} + +/*! + * @brief Set domain ID that can change this clock. + * + * @note If LOCK_LIST bit is set, domain ID white list can not be changed until next system reset. + * + * @param name Clock root name, see \ref clock_root_t. + * @param domainId Domains that on the whitelist can change this clock. + */ +static inline void CLOCK_ROOT_SetWhiteList(clock_root_t name, uint8_t domainId) +{ + CCM->CLOCK_ROOT[name].AUTHEN = (CCM->CLOCK_ROOT[name].AUTHEN & ~CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_MASK) | + CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST(domainId); +} + +/*! + * @brief Check whether this clock implement SetPoint control scheme. + * + * @param name Clock root name, see \ref clock_root_t. + * @return Clock root SetPoint implement status. + * - true: SetPoint is implemented. + * - false: SetPoint is not implemented. + */ +static inline bool CLOCK_ROOT_IsSetPointImplemented(clock_root_t name) +{ + return ((CCM->CLOCK_ROOT[name].CONFIG & CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_MASK) >> + CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_SHIFT); +} + +/*! + * @brief Set this clock works in Unassigned Mode. + * + * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset. + * + * @param name Clock root name, see \ref clock_root_t. + */ +static inline void CLOCK_ROOT_ControlByUnassignedMode(clock_root_t name) +{ + CCM->CLOCK_ROOT[name].AUTHEN &= + ~(CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_MASK | CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_MASK); +} + +/*! + * @brief Configure one SetPoint for this clock. + * + * @note SetPoint value could only be changed in Unassigend Mode. + * + * @param name Which clock root to set, see \ref clock_root_t. + * @param spIndex Which SetPoint of this clock root to set. + * @param config SetPoint config, see \ref clock_root_setpoint_config_t + */ +static inline void CLOCK_ROOT_ConfigSetPoint(clock_root_t name, + uint16_t spIndex, + const clock_root_setpoint_config_t *config) +{ + assert(config); + CCM->CLOCK_ROOT[name].SETPOINT[spIndex] = + CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE(config->grade) | + CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX(config->mux) | + CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV((uint32_t)config->div - 1UL) | + CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF(config->clockOff); +} + +/*! + * @brief Enable SetPoint control for this clock root. + * + * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset. + * + * @param name Clock root name, see \ref clock_root_t. + */ +static inline void CLOCK_ROOT_EnableSetPointControl(clock_root_t name) +{ + CCM->CLOCK_ROOT[name].AUTHEN = (CCM->CLOCK_ROOT[name].AUTHEN & ~CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_MASK) | + CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_MASK; +} + +/*! + * @brief Set this clock works in SetPoint controlled Mode. + * + * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset. + * + * @param name Clock root name, see \ref clock_root_t. + * @param spTable Point to the array that stores clock root settings for each setpoint. Note that the pointed array must + * have 16 elements. + */ +void CLOCK_ROOT_ControlBySetPointMode(clock_root_t name, const clock_root_setpoint_config_t *spTable); + +/*! + * @brief Set this clock works in CPU Low Power Mode. + * + * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset. + * + * @param name Clock root name, see \ref clock_root_t. + * @param domainId Domains that on the whitelist can change this clock. + */ +static inline void CLOCK_ROOT_ControlByDomainMode(clock_root_t name, uint8_t domainId) +{ + CCM->CLOCK_ROOT[name].AUTHEN = (CCM->CLOCK_ROOT[name].AUTHEN & ~(CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_MASK | + CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_MASK)) | + CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_MASK | CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST(domainId); +} + +/*! + * @brief Lock low power and access control mode for this clock. + * + * @note When this bit is set, bits 16-20 can not be changed until next system reset. + * + * @param name Clock gate name, see \ref clock_lpcg_t. + */ +static inline void CLOCK_LPCG_LockControlMode(clock_lpcg_t name) +{ + CCM->LPCG[name].AUTHEN |= CCM_LPCG_AUTHEN_LOCK_MODE_MASK; +} + +/*! + * @brief Lock the value of Domain ID white list for this clock. + * + * @note Once locked, this bit and domain ID white list can not be changed until next system reset. + * + * @param name Clock gate name, see \ref clock_lpcg_t. + */ +static inline void CLOCK_LPCG_LockWhiteList(clock_lpcg_t name) +{ + CCM->LPCG[name].AUTHEN |= CCM_LPCG_AUTHEN_LOCK_LIST_MASK; +} + +/*! + * @brief Set domain ID that can change this clock. + * + * @note If LOCK_LIST bit is set, domain ID white list can not be changed until next system reset. + * + * @param name Clock gate name, see \ref clock_lpcg_t. + * @param domainId Domains that on the whitelist can change this clock. + */ +static inline void CLOCK_LPCG_SetWhiteList(clock_lpcg_t name, uint8_t domainId) +{ + CCM->LPCG[name].AUTHEN = + (CCM->LPCG[name].AUTHEN & ~CCM_LPCG_AUTHEN_WHITE_LIST_MASK) | CCM_LPCG_AUTHEN_WHITE_LIST(domainId); +} + +/*! + * @brief Check whether this clock implement SetPoint control scheme. + * + * @param name Clock gate name, see \ref clock_lpcg_t. + * @return Clock gate SetPoint implement status. + * - true: SetPoint is implemented. + * - false: SetPoint is not implemented. + */ +static inline bool CLOCK_LPCG_IsSetPointImplemented(clock_lpcg_t name) +{ + return ((CCM->LPCG[name].CONFIG & CCM_LPCG_CONFIG_SETPOINT_PRESENT_MASK) >> CCM_LPCG_CONFIG_SETPOINT_PRESENT_SHIFT); +} + +/*! + * @brief Set this clock works in Unassigned Mode. + * + * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset. + * + * @param name Clock gate name, see \ref clock_lpcg_t. + */ +static inline void CLOCK_LPCG_ControlByUnassignedMode(clock_lpcg_t name) +{ + CCM->LPCG[name].AUTHEN &= + ~(CCM_LPCG_AUTHEN_CPULPM_MASK | CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK | CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK); +} + +/*! + * @brief Set this clock works in SetPoint control Mode. + * + * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset. + * + * @param name Clock gate name, see \ref clock_lpcg_t. + * @param spValue Bit0~Bit15 hold value for Setpoint 0~16 respectively. + * A bitfield value of 0 implies clock will be shutdown in this Setpoint. + * A bitfield value of 1 implies clock will be turn on in this Setpoint. + * @param stbyValue Bit0~Bit15 hold value for Setpoint 0~16 standby. + * A bitfield value of 0 implies clock will be shutdown during standby. + * A bitfield value of 1 represent clock will keep Setpoint setting during standby. + */ +void CLOCK_LPCG_ControlBySetPointMode(clock_lpcg_t name, uint16_t spValue, uint16_t stbyValue); + +/*! + * @brief Set this clock works in CPU Low Power Mode. + * + * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset. + * + * @param name Clock gate name, see \ref clock_lpcg_t. + * @param domainId Domains that on the whitelist can change this clock. + * @param level0,level1 Depend level of this clock. + */ +void CLOCK_LPCG_ControlByCpuLowPowerMode(clock_lpcg_t name, + uint8_t domainId, + clock_level_t level0, + clock_level_t level1); + +/*! + * @brief Set clock depend level for current accessing domain. + * + * @note This setting only take effects in CPU Low Power Mode. + * + * @param name Clock gate name, see \ref clock_lpcg_t. + * @param level Depend level of this clock. + */ +static inline void CLOCK_LPCG_SetCurrentClockLevel(clock_lpcg_t name, clock_level_t level) +{ + CCM->LPCG[name].DOMAINr = (CCM->LPCG[name].DOMAINr & ~CCM_LPCG_DOMAIN_LEVEL_MASK) | CCM_LPCG_DOMAIN_LEVEL(level); +} + +/*! + * @brief Set this clock works in Domain Mode. + * + * @note When LOCK_MODE bit is set, control mode can not be changed until next system reset. + * + * @param name Clock gate name, see \ref clock_lpcg_t. + * @param domainId Domains that on the whitelist can change this clock. + */ +static inline void CLOCK_LPCG_ControlByDomainMode(clock_lpcg_t name, uint8_t domainId) +{ + CCM->LPCG[name].AUTHEN = + (CCM->LPCG[name].AUTHEN & + ~(CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK | CCM_LPCG_AUTHEN_CPULPM_MASK | CCM_LPCG_AUTHEN_WHITE_LIST_MASK)) | + CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK | CCM_LPCG_AUTHEN_WHITE_LIST(domainId); +} + /* @} */ #if defined(__cplusplus) diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_common.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_common.c index 748a6c97f56..ec52acbfac6 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_common.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_common.c @@ -24,17 +24,16 @@ typedef struct _mem_align_control_block #if defined(ENABLE_RAM_VECTOR_TABLE) uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) { +#ifdef __VECTOR_TABLE +#undef __VECTOR_TABLE +#endif + /* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */ #if defined(__CC_ARM) || defined(__ARMCC_VERSION) extern uint32_t Image$$VECTOR_ROM$$Base[]; extern uint32_t Image$$VECTOR_RAM$$Base[]; extern uint32_t Image$$RW_m_data$$Base[]; -/* Undef __VECTOR_TABLE to avoid duplicate definition in cmsis_clang.h*/ -#ifdef __VECTOR_TABLE -#undef __VECTOR_TABLE -#endif - #define __VECTOR_TABLE Image$$VECTOR_ROM$$Base #define __VECTOR_RAM Image$$VECTOR_RAM$$Base #define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base)) @@ -64,9 +63,9 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) SCB->VTOR = (uint32_t)__VECTOR_RAM; } - ret = __VECTOR_RAM[irq + 16]; + ret = __VECTOR_RAM[(int32_t)irq + 16]; /* make sure the __VECTOR_RAM is noncachable */ - __VECTOR_RAM[irq + 16] = irqHandler; + __VECTOR_RAM[(int32_t)irq + 16] = irqHandler; EnableGlobalIRQ(irqMaskValue); SDK_ISR_EXIT_BARRIER; @@ -77,6 +76,17 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler) #endif /* __GIC_PRIO_BITS. */ #if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + +/* + * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, + * powerlib should be used instead of these functions. + */ +#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) + +/* + * When the SYSCON STARTER registers are discontinuous, these functions are + * implemented in fsl_power.c. + */ #if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) void EnableDeepSleepIRQ(IRQn_Type interrupt) @@ -91,15 +101,15 @@ void EnableDeepSleepIRQ(IRQn_Type interrupt) intNumber -= 32u; } - SYSCON->STARTERSET[index] = 1u << intNumber; - EnableIRQ(interrupt); /* also enable interrupt at NVIC */ + SYSCON->STARTERSET[index] = 1UL << intNumber; + (void)EnableIRQ(interrupt); /* also enable interrupt at NVIC */ } void DisableDeepSleepIRQ(IRQn_Type interrupt) { uint32_t intNumber = (uint32_t)interrupt; - DisableIRQ(interrupt); /* also disable interrupt at NVIC */ + (void)DisableIRQ(interrupt); /* also disable interrupt at NVIC */ uint32_t index = 0; while (intNumber >= 32u) @@ -108,15 +118,31 @@ void DisableDeepSleepIRQ(IRQn_Type interrupt) intNumber -= 32u; } - SYSCON->STARTERCLR[index] = 1u << intNumber; + SYSCON->STARTERCLR[index] = 1UL << intNumber; } #endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */ +#endif /* FSL_FEATURE_POWERLIB_EXTEND */ #endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ void *SDK_Malloc(size_t size, size_t alignbytes) { mem_align_cb_t *p_cb = NULL; - uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t); + uint32_t alignedsize; + + /* Check overflow. */ + alignedsize = SDK_SIZEALIGN(size, alignbytes); + if (alignedsize < size) + { + return NULL; + } + + if (alignedsize > SIZE_MAX - alignbytes - sizeof(mem_align_cb_t)) + { + return NULL; + } + + alignedsize += alignbytes + sizeof(mem_align_cb_t); + union { void *pointer_value; @@ -165,7 +191,7 @@ void SDK_Free(void *ptr) * @param count Counts of loop needed for dalay. */ #if defined(SDK_DELAY_USE_DWT) && defined(DWT) -void enableCpuCycleCounter(void) +static void enableCpuCycleCounter(void) { /* Make sure the DWT trace fucntion is enabled. */ if (CoreDebug_DEMCR_TRCENA_Msk != (CoreDebug_DEMCR_TRCENA_Msk & CoreDebug->DEMCR)) @@ -183,18 +209,18 @@ void enableCpuCycleCounter(void) } } -uint32_t getCpuCycleCount(void) +static uint32_t getCpuCycleCount(void) { return DWT->CYCCNT; } #elif defined __XCC__ extern uint32_t xthal_get_ccount(void); -void enableCpuCycleCounter(void) +static void enableCpuCycleCounter(void) { /* do nothing */ } -uint32_t getCpuCycleCount(void) +static uint32_t getCpuCycleCount(void) { return xthal_get_ccount(); } @@ -236,17 +262,17 @@ static void DelayLoop(uint32_t count) /*! * @brief Delay at least for some time. * Please note that, if not uses DWT, this API will use while loop for delay, different run-time environments have - * effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delay_us and - * coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delay_us only supports + * effect on the delay time. If precise delay is needed, please enable DWT delay. The two parmeters delayTime_us and + * coreClock_Hz have limitation. For example, in the platform with 1GHz coreClock_Hz, the delayTime_us only supports * up to 4294967 in current code. If long time delay is needed, please implement a new delay function. * - * @param delay_us Delay time in unit of microsecond. + * @param delayTime_us Delay time in unit of microsecond. * @param coreClock_Hz Core clock frequency with Hz. */ -void SDK_DelayAtLeastUs(uint32_t delay_us, uint32_t coreClock_Hz) +void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz) { - assert(0U != delay_us); - uint64_t count = USEC_TO_COUNT(delay_us, coreClock_Hz); + assert(0U != delayTime_us); + uint64_t count = USEC_TO_COUNT(delayTime_us, coreClock_Hz); assert(count <= UINT32_MAX); #if defined(SDK_DELAY_USE_DWT) && defined(DWT) || (defined __XCC__) /* Use DWT for better accuracy */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_common.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_common.h index 02cdaefb532..9f93513a919 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_common.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_common.h @@ -15,7 +15,7 @@ #include #include -#if defined(__ICCARM__) +#if defined(__ICCARM__) || (defined(__CC_ARM) || defined(__ARMCC_VERSION)) || defined(__GNUC__) #include #endif @@ -48,7 +48,7 @@ /*! @name Driver version */ /*@{*/ /*! @brief common driver version. */ -#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 2, 8)) +#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 2, 9)) /*@}*/ /* Debug console type definition. */ @@ -389,13 +389,13 @@ _Pragma("diag_suppress=Pm120") /* @{ */ #if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE #if (defined(__ICCARM__)) -#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess" +#define AT_QUICKACCESS_SECTION_CODE(func) __ramfunc func #define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess" #elif(defined(__CC_ARM) || defined(__ARMCC_VERSION)) -#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func #define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func #elif(defined(__GNUC__)) -#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func +#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func #define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func #else #error Toolchain not supported. @@ -754,7 +754,7 @@ void DefaultISR(void); } #if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) - else if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) { status = kStatus_Fail; } @@ -798,7 +798,7 @@ void DefaultISR(void); } #if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0) - else if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) + else if ((int32_t)interrupt >= (int32_t)FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) { status = kStatus_Fail; } @@ -879,6 +879,12 @@ void DefaultISR(void); #endif /* ENABLE_RAM_VECTOR_TABLE. */ #if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) + + /* + * When FSL_FEATURE_POWERLIB_EXTEND is defined to non-zero value, + * powerlib should be used instead of these functions. + */ +#if !(defined(FSL_FEATURE_POWERLIB_EXTEND) && (FSL_FEATURE_POWERLIB_EXTEND != 0)) /*! * @brief Enable specific interrupt for wake-up from deep-sleep mode. * @@ -908,6 +914,7 @@ void DefaultISR(void); * @param interrupt The IRQ number. */ void DisableDeepSleepIRQ(IRQn_Type interrupt); +#endif /* FSL_FEATURE_POWERLIB_EXTEND */ #endif /* FSL_FEATURE_SOC_SYSCON_COUNT */ /*! @@ -933,10 +940,10 @@ void DefaultISR(void); * Please note that, this API uses while loop for delay, different run-time environments make the time not precise, * if precise delay count was needed, please implement a new delay function with hardware timer. * - * @param delay_us Delay time in unit of microsecond. + * @param delayTime_us Delay time in unit of microsecond. * @param coreClock_Hz Core clock frequency with Hz. */ - void SDK_DelayAtLeastUs(uint32_t delay_us, uint32_t coreClock_Hz); + void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz); #if defined(__cplusplus) } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_dcdc.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_dcdc.c index 3058d6d6661..aa41b5072de 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_dcdc.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_dcdc.c @@ -69,11 +69,11 @@ static uint32_t DCDC_ConvertByteArrayToWord(uint8_t *ptrArray) assert(ptrArray != NULL); uint32_t temp32 = 0UL; - uint8_t index; + uint32_t index; for (index = 0U; index < 4U; index++) { - temp32 |= ptrArray[index] << ((index % 4U) * 8U); + temp32 |= (uint32_t)ptrArray[index] << ((index % 4UL) * 8UL); } return temp32; @@ -162,8 +162,7 @@ void DCDC_GetDefaultConfig(dcdc_config_t *config) * config->powerDownOverCurrentDetection = true; * config->powerDownPeakCurrentDetection = true; * config->powerDownZeroCrossDetection = true; - * config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0; - * config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0; + * config->PeakCurrentThreshold = kDCDC_PeakCurrentRunMode250mALPMode1P5A; * endcode * * param config Pointer to configuration structure. See to "dcdc_detection_config_t" @@ -182,8 +181,7 @@ void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config) config->powerDownOverCurrentDetection = true; config->powerDownPeakCurrentDetection = true; config->powerDownZeroCrossDetection = true; - config->OverCurrentThreshold = kDCDC_OverCurrentThresholdAlt0; - config->PeakCurrentThreshold = kDCDC_PeakCurrentThresholdAlt0; + config->PeakCurrentThreshold = kDCDC_PeakCurrentRunMode250mALPMode1P5A; } /*! @@ -201,10 +199,9 @@ void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *con tmp32 = base->REG0 & ~(DCDC_REG0_XTALOK_DISABLE_MASK | DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK | DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK | DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK | DCDC_REG0_PWD_OVERCUR_DET_MASK | DCDC_REG0_PWD_CUR_SNS_CMP_MASK | - DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_CUR_SNS_THRSH_MASK | DCDC_REG0_OVERCUR_TRIG_ADJ_MASK); + DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_CUR_SNS_THRSH_MASK); - tmp32 |= DCDC_REG0_CUR_SNS_THRSH(config->PeakCurrentThreshold) | - DCDC_REG0_OVERCUR_TRIG_ADJ(config->OverCurrentThreshold); + tmp32 |= DCDC_REG0_CUR_SNS_THRSH(config->PeakCurrentThreshold); if (false == config->enableXtalokDetection) { tmp32 |= DCDC_REG0_XTALOK_DISABLE_MASK; @@ -275,10 +272,7 @@ void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource) * The default configuration are set according to responding registers' setting when powered on. * They are: * code - * config->enableOverloadDetection = true; * config->enableAdjustHystereticValue = false; - * config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle; - * config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32; * endcode * * param config Pointer to configuration structure. See to "dcdc_low_power_config_t" @@ -290,8 +284,6 @@ void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config) /* Initializes the configure structure to zero. */ (void)memset(config, 0, sizeof(*config)); config->enableAdjustHystereticValue = false; - config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle; - config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32; } /*! @@ -306,10 +298,8 @@ void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *conf uint32_t tmp32; /* Configure the DCDC_REG0 register. */ - tmp32 = base->REG0 & - ~(DCDC_REG0_LP_HIGH_HYS_MASK | DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK | DCDC_REG0_LP_OVERLOAD_THRSH_MASK); - tmp32 |= DCDC_REG0_LP_OVERLOAD_FREQ_SEL(config->countChargingTimePeriod) | - DCDC_REG0_LP_OVERLOAD_THRSH(config->countChargingTimeThreshold); + tmp32 = base->REG0 & ~(DCDC_REG0_LP_HIGH_HYS_MASK); + if (config->enableAdjustHystereticValue) { tmp32 |= DCDC_REG0_LP_HIGH_HYS_MASK; @@ -440,14 +430,6 @@ void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regula tmp32 = base->REG3 & ~DCDC_REG3_REG_FBK_SEL_MASK; tmp32 |= DCDC_REG3_REG_FBK_SEL(config->feedbackPoint); base->REG3 = tmp32; - - tmp32 = base->REG1 & ~DCDC_REG1_REG_RLOAD_SW_MASK; - - if (config->enableLoadResistor) - { - tmp32 |= DCDC_REG1_REG_RLOAD_SW_MASK; - } - base->REG1 = tmp32; } /*! @@ -503,6 +485,7 @@ void DCDC_SetPointInit(DCDC_Type *base, const dcdc_setpoint_config_t *config) * brief Boots DCDC into DCM(discontinous conduction mode). * * pwd_zcd=0x0; + * DM_CTRL = 1'b1; * pwd_cmp_offset=0x0; * dcdc_loopctrl_en_rcscale=0x3 or 0x5; * DCM_set_ctrl=1'b1; @@ -512,8 +495,10 @@ void DCDC_SetPointInit(DCDC_Type *base, const dcdc_setpoint_config_t *config) void DCDC_BootIntoDCM(DCDC_Type *base) { base->REG0 &= ~(DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_PWD_CMP_OFFSET_MASK); - base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x4U); + base->REG1 |= DCDC_REG1_DM_CTRL_MASK; + base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x5U); base->REG3 &= ~(DCDC_REG3_DISABLE_IDLE_SKIP_MASK | DCDC_REG3_DISABLE_PULSE_SKIP_MASK); + base->REG3 |= DCDC_REG3_ENABLE_FF_MASK; } /*! diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_dcdc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_dcdc.h index 17e2f3ae022..45947679fee 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_dcdc.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_dcdc.h @@ -20,7 +20,7 @@ * Definitions ******************************************************************************/ /*! @brief DCDC driver version. */ -#define FSL_DCDC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +#define FSL_DCDC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */ /*! @brief The array of VDD1P0 target voltage in standby mode. */ #define STANDBY_MODE_VDD1P0_TARGET_VOLTAGE \ @@ -298,50 +298,21 @@ typedef enum _dcdc_comparator_current_bias kDCDC_ComparatorCurrentBias400nA = 3U, /*!< The current bias of low power comparator is 400nA. */ } dcdc_comparator_current_bias_t; -/*! - * @brief The threshold of over current detection. - */ -typedef enum _dcdc_over_current_threshold -{ - kDCDC_OverCurrentThresholdAlt0 = 0U, /*!< 1A in the run mode, 0.25A in the power save mode. */ - kDCDC_OverCurrentThresholdAlt1 = 1U, /*!< 2A in the run mode, 0.25A in the power save mode. */ - kDCDC_OverCurrentThresholdAlt2 = 2U, /*!< 1A in the run mode, 0.2A in the power save mode. */ - kDCDC_OverCurrentThresholdAlt3 = 3U, /*!< 2A in the run mode, 0.2A in the power save mode. */ -} dcdc_over_current_threshold_t; - /*! * @brief The threshold if peak current detection. */ typedef enum _dcdc_peak_current_threshold { - kDCDC_PeakCurrentThresholdAlt0 = 0U, /*!< 150mA peak current threshold. */ - kDCDC_PeakCurrentThresholdAlt1 = 1U, /*!< 250mA peak current threshold. */ - kDCDC_PeakCurrentThresholdAlt2 = 2U, /*!< 350mA peak current threshold. */ - kDCDC_PeakCurrentThresholdAlt3 = 3U, /*!< 450mA peak current threshold. */ - kDCDC_PeakCurrentThresholdAlt4 = 4U, /*!< 550mA peak current threshold. */ - kDCDC_PeakCurrentThresholdAlt5 = 5U, /*!< 650mA peak current threshold. */ + kDCDC_PeakCurrentRunMode250mALPMode1P5A = 0U, /*!< Over peak current threshold in low power mode is 250mA, + in run mode is 1.5A */ + kDCDC_PeakCurrentRunMode200mALPMode1P5A, /*!< Over peak current threshold in low power mode is 200mA, + in run mode is 1.5A */ + kDCDC_PeakCurrentRunMode250mALPMode2A, /*!< Over peak current threshold in low power mode is 250mA, + in run mode is 2A */ + kDCDC_PeakCurrentRunMode200mALPMode2A, /*!< Over peak current threshold in low power mode is 200mA, + in run mode is 2A */ } dcdc_peak_current_threshold_t; -/*! - * @brief The period of counting the charging times in power save mode. - */ -typedef enum _dcdc_count_charging_time_period -{ - kDCDC_CountChargingTimePeriod8Cycle = 0U, /*!< Eight 32k cycle. */ - kDCDC_CountChargingTimePeriod16Cycle = 1U, /*!< Sixteen 32k cycle. */ -} dcdc_count_charging_time_period_t; - -/*! - * @brief The threshold of the counting number of charging times - */ -typedef enum _dcdc_count_charging_time_threshold -{ - kDCDC_CountChargingTimeThreshold32 = 0U, /*!< 0x0: 32. */ - kDCDC_CountChargingTimeThreshold64 = 1U, /*!< 0x1: 64. */ - kDCDC_CountChargingTimeThreshold16 = 2U, /*!< 0x2: 16. */ - kDCDC_CountChargingTimeThreshold8 = 3U, /*!< 0x3: 8. */ -} dcdc_count_charging_time_threshold_t; - /*! * @brief Oscillator clock option. */ @@ -393,7 +364,6 @@ typedef struct _dcdc_detection_config bool powerDownPeakCurrentDetection; /*!< Power down peak-current detection. */ bool powerDownZeroCrossDetection; /*!< Power down the zero cross detection function for discontinuous conductor mode. */ - dcdc_over_current_threshold_t OverCurrentThreshold; /*!< The threshold of over current detection. */ dcdc_peak_current_threshold_t PeakCurrentThreshold; /*!< The threshold of peak current detection. */ } dcdc_detection_config_t; @@ -431,10 +401,7 @@ typedef struct _dcdc_loop_control_config */ typedef struct _dcdc_internal_regulator_config { - bool enableLoadResistor; /*!< control the load resistor of the internal regulator of DCDC, the load resistor is - connected as default "true", and need set to "false" to disconnect the load - resistor. */ - uint32_t feedbackPoint; /*!< Available range is 0~3. Select the feedback point of the internal regulator. */ + uint32_t feedbackPoint; /*!< Available range is 0~3. Select the feedback point of the internal regulator. */ } dcdc_internal_regulator_config_t; /*! @@ -442,15 +409,7 @@ typedef struct _dcdc_internal_regulator_config */ typedef struct _dcdc_low_power_config { - bool enableOverloadDetection; /*!< Enable the overload detection in power save mode, if current is larger than the - overloading threshold (typical value is 50 mA), DCDC will switch to the run mode - automatically. */ bool enableAdjustHystereticValue; /*!< Adjust hysteretic value in low power from 12.5mV to 25mV. */ - dcdc_count_charging_time_period_t countChargingTimePeriod; /*!< The period of counting the charging times - in power save mode. */ - dcdc_count_charging_time_threshold_t countChargingTimeThreshold; /*!< the threshold of the counting number of - charging times during the period that - lp_overload_freq_sel sets in power save mode. */ } dcdc_low_power_config_t; /*! @@ -624,7 +583,7 @@ static inline void DCDC_SetVDD1P0StandbyModeTargetVoltage(DCDC_Type *base, static inline uint16_t DCDC_GetVDD1P0StandbyModeTargetVoltage(DCDC_Type *base) { const uint16_t vdd1P0TargetVoltage[] = STANDBY_MODE_VDD1P0_TARGET_VOLTAGE; - uint8_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK) >> DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT; + uint32_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK) >> DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT; return vdd1P0TargetVoltage[voltageValue]; } @@ -656,7 +615,7 @@ static inline void DCDC_SetVDD1P8StandbyModeTargetVoltage(DCDC_Type *base, static inline uint16_t DCDC_GetVDD1P8StandbyModeTargetVoltage(DCDC_Type *base) { const uint16_t vdd1P8TargetVoltage[] = STANDBY_MODE_VDD1P8_TARGET_VOLTAGE; - uint8_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK) >> DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT; + uint32_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK) >> DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT; return vdd1P8TargetVoltage[voltageValue]; } @@ -670,7 +629,7 @@ static inline uint16_t DCDC_GetVDD1P8StandbyModeTargetVoltage(DCDC_Type *base) static inline void DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC_Type *base, dcdc_buck_mode_1P0_target_vol_t targetVoltage) { base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; - base->CTRL1 |= ((base->CTRL1 & (~DCDC_CTRL1_VDD1P0CTRL_TRG_MASK)) | DCDC_CTRL1_VDD1P0CTRL_TRG(targetVoltage)); + base->CTRL1 = ((base->CTRL1 & (~DCDC_CTRL1_VDD1P0CTRL_TRG_MASK)) | DCDC_CTRL1_VDD1P0CTRL_TRG(targetVoltage)); while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) { } @@ -686,7 +645,7 @@ static inline void DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC_Type *base, dcdc_buc static inline uint16_t DCDC_GetVDD1P0BuckModeTargetVoltage(DCDC_Type *base) { const uint16_t vdd1P0TargetVoltage[] = BUCK_MODE_VDD1P0_TARGET_VOLTAGE; - uint8_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P0CTRL_TRG_MASK) >> DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT; + uint32_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P0CTRL_TRG_MASK) >> DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT; return vdd1P0TargetVoltage[voltageValue]; } @@ -700,7 +659,7 @@ static inline uint16_t DCDC_GetVDD1P0BuckModeTargetVoltage(DCDC_Type *base) static inline void DCDC_SetVDD1P8BuckModeTargetVoltage(DCDC_Type *base, dcdc_buck_mode_1P8_target_vol_t targetVoltage) { base->REG3 &= ~DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK; - base->CTRL1 |= ((base->CTRL1 & (~DCDC_CTRL1_VDD1P8CTRL_TRG_MASK)) | DCDC_CTRL1_VDD1P8CTRL_TRG(targetVoltage)); + base->CTRL1 = ((base->CTRL1 & (~DCDC_CTRL1_VDD1P8CTRL_TRG_MASK)) | DCDC_CTRL1_VDD1P8CTRL_TRG(targetVoltage)); while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & base->REG0)) { } @@ -716,7 +675,7 @@ static inline void DCDC_SetVDD1P8BuckModeTargetVoltage(DCDC_Type *base, dcdc_buc static inline uint16_t DCDC_GetVDD1P8BuckModeTargetVoltage(DCDC_Type *base) { const uint16_t vdd1P8TargetVoltage[] = BUCK_MODE_VDD1P8_TARGET_VOLTAGE; - uint8_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P8CTRL_TRG_MASK) >> DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT; + uint32_t voltageValue = (base->CTRL1 & DCDC_CTRL1_VDD1P8CTRL_TRG_MASK) >> DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT; return vdd1P8TargetVoltage[voltageValue]; } @@ -842,10 +801,7 @@ void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource); * The default configuration are set according to responding registers' setting when powered on. * They are: * @code - * config->enableOverloadDetection = true; * config->enableAdjustHystereticValue = false; - * config->countChargingTimePeriod = kDCDC_CountChargingTimePeriod8Cycle; - * config->countChargingTimeThreshold = kDCDC_CountChargingTimeThreshold32; * @endcode * * @param config Pointer to configuration structure. See to @ref dcdc_low_power_config_t. @@ -1025,6 +981,7 @@ static inline uint32_t DCDC_GetStatusFlags(DCDC_Type *base) * * @code * pwd_zcd=0x0; + * DM_CTRL = 1'b1; * pwd_cmp_offset=0x0; * dcdc_loopctrl_en_rcscale=0x3 or 0x5; * DCM_set_ctrl=1'b1; diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_flexspi.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_flexspi.c index 24c049be78d..068e676b80d 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_flexspi.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_flexspi.c @@ -39,8 +39,8 @@ enum FLEXSPI_STS2_BREFLOCK_MASK, /* Flash B sample clock reference delay line locked. */ }; -/*! @brief Common sets of flags used by the driver. */ -enum _flexspi_flag_constants +/*! @brief Common sets of flags used by the driver, _flexspi_flag_constants. */ +enum { /*! IRQ sources enabled by the non-blocking transactional API. */ kIrqFlags = kFLEXSPI_IpTxFifoWatermarkEmptyFlag | kFLEXSPI_IpRxFifoWatermarkAvailableFlag | @@ -52,7 +52,8 @@ enum _flexspi_flag_constants kFLEXSPI_IpCommandGrantTimeoutFlag, }; -enum _flexspi_transfer_state +/* FLEXSPI transfer state, _flexspi_transfer_state. */ +enum { kFLEXSPI_Idle = 0x0U, /*!< Transfer is done. */ kFLEXSPI_BusyWrite = 0x1U, /*!< FLEXSPI is busy write transfer. */ @@ -65,12 +66,7 @@ typedef void (*flexspi_isr_t)(FLEXSPI_Type *base, flexspi_handle_t *handle); /******************************************************************************* * Prototypes ******************************************************************************/ -/*! - * @brief Get the instance number for FLEXSPI. - * - * @param base FLEXSPI base pointer. - */ -uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base); +static void FLEXSPI_Memset(void *src, uint8_t value, size_t length); /*! * @brief Calculate flash A/B sample clock DLL. @@ -78,15 +74,7 @@ uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base); * @param base FLEXSPI base pointer. * @param config Flash configuration parameters. */ -static uint32_t FLEXSPI_CalculateDll(FLEXSPI_Type *base, flexspi_device_config_t *config); - -/*! - * @brief Check and clear IP command execution errors. - * - * @param base FLEXSPI base pointer. - * @param status interrupt status. - */ -status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status); +AT_QUICKACCESS_SECTION_CODE(static uint32_t FLEXSPI_CalculateDll(FLEXSPI_Type *base, flexspi_device_config_t *config)); /******************************************************************************* * Variables @@ -119,6 +107,18 @@ static flexspi_isr_t s_flexspiIsr; /******************************************************************************* * Code ******************************************************************************/ +AT_QUICKACCESS_SECTION_CODE(static void FLEXSPI_Memset(void *src, uint8_t value, size_t length)) +{ + assert(src != NULL); + uint8_t *p = src; + + /* Keyword volatile is to avoid compiler opitimizing this API into memset() in library. */ + for (volatile uint32_t i = 0U; i < length; i++) + { + *p = value; + p++; + } +} uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base) { @@ -362,7 +362,7 @@ void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config) void FLEXSPI_GetDefaultConfig(flexspi_config_t *config) { /* Initializes the configure structure to zero. */ - (void)memset(config, 0, sizeof(*config)); + (void)flexspi_memset(config, 0, sizeof(*config)); config->rxSampleClock = kFLEXSPI_ReadSampleClkLoopbackInternally; config->enableSckFreeRunning = false; @@ -384,7 +384,7 @@ void FLEXSPI_GetDefaultConfig(flexspi_config_t *config) config->ahbConfig.ahbGrantTimeoutCycle = 0xFFU; config->ahbConfig.ahbBusTimeoutCycle = 0xFFFFU; config->ahbConfig.resumeWaitCycle = 0x20U; - (void)memset(config->ahbConfig.buffer, 0, sizeof(config->ahbConfig.buffer)); + (void)flexspi_memset(config->ahbConfig.buffer, 0, sizeof(config->ahbConfig.buffer)); /* Use invalid master ID 0xF and buffer size 0 for the first several buffers. */ for (uint8_t i = 0; i < ((uint8_t)FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 2U); i++) { @@ -548,6 +548,11 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, /* Exit stop mode. */ base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; + + /* Wait for bus to be idle before use it access to external flash. */ + while (!FLEXSPI_GetBusIdleStatus(base)) + { + } } /*! brief Updates the LUT table. @@ -654,7 +659,7 @@ status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size } else { - for (i = 0U; i < (size / 4U + 1U); i++) + for (i = 0U; i < ((size + 3U) / 4U); i++) { base->TFDR[i] = *buffer++; } @@ -1078,7 +1083,7 @@ void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle) } else { - for (i = 0; i < (handle->dataSize / 4U + 1U); i++) + for (i = 0; i < (handle->dataSize + 3U) / 4U; i++) { base->TFDR[i] = *handle->data++; } @@ -1103,6 +1108,7 @@ void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle) #if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ #if defined(FLEXSPI) +void FLEXSPI_DriverIRQHandler(void); void FLEXSPI_DriverIRQHandler(void) { s_flexspiIsr(FLEXSPI, s_flexspiHandle[0]); @@ -1111,6 +1117,7 @@ void FLEXSPI_DriverIRQHandler(void) #endif #if defined(FLEXSPI0) +void FLEXSPI0_DriverIRQHandler(void); void FLEXSPI0_DriverIRQHandler(void) { s_flexspiIsr(FLEXSPI0, s_flexspiHandle[0]); @@ -1118,6 +1125,7 @@ void FLEXSPI0_DriverIRQHandler(void) } #endif #if defined(FLEXSPI1) +void FLEXSPI1_DriverIRQHandler(void); void FLEXSPI1_DriverIRQHandler(void) { s_flexspiIsr(FLEXSPI1, s_flexspiHandle[1]); @@ -1126,6 +1134,7 @@ void FLEXSPI1_DriverIRQHandler(void) #endif #if defined(LSIO__FLEXSPI0) +void LSIO_OCTASPI0_INT_DriverIRQHandler(void); void LSIO_OCTASPI0_INT_DriverIRQHandler(void) { s_flexspiIsr(LSIO__FLEXSPI0, s_flexspiHandle[0]); @@ -1133,6 +1142,7 @@ void LSIO_OCTASPI0_INT_DriverIRQHandler(void) } #endif #if defined(LSIO__FLEXSPI1) +void LSIO_OCTASPI1_INT_DriverIRQHandler(void); void LSIO_OCTASPI1_INT_DriverIRQHandler(void) { s_flexspiIsr(LSIO__FLEXSPI1, s_flexspiHandle[1]); @@ -1142,6 +1152,7 @@ void LSIO_OCTASPI1_INT_DriverIRQHandler(void) #if defined(FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_FLEXSPI_HAS_SHARED_IRQ0_IRQ1 +void FLEXSPI0_FLEXSPI1_DriverIRQHandler(void); void FLEXSPI0_FLEXSPI1_DriverIRQHandler(void) { /* If handle is registered, treat the transfer function is enabled. */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_flexspi.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_flexspi.h index 1995d45af76..6e7787158ba 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_flexspi.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_flexspi.h @@ -24,8 +24,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief FLEXSPI driver version 2.3.0. */ -#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 0)) +/*! @brief FLEXSPI driver version 2.3.3. */ +#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 3, 3)) /*@}*/ #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0) @@ -334,10 +334,34 @@ struct _flexspi_handle extern "C" { #endif /*_cplusplus. */ +/** + * @brief Set bytes in memory. If put this code in SRAM, Make sure this code + * does not call functions in Flash. + * + * @return pointer to start of buffer + */ +extern void *flexspi_memset(void *buf, int c, size_t n); + /*! * @name Initialization and deinitialization * @{ */ + +/*! + * @brief Get the instance number for FLEXSPI. + * + * @param base FLEXSPI base pointer. + */ +uint32_t FLEXSPI_GetInstance(FLEXSPI_Type *base); + +/*! + * @brief Check and clear IP command execution errors. + * + * @param base FLEXSPI base pointer. + * @param status interrupt status. + */ +AT_QUICKACCESS_SECTION_CODE(status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status)); + /*! * @brief Initializes the FLEXSPI module and internal state. * @@ -347,14 +371,14 @@ extern "C" { * @param base FLEXSPI peripheral base address. * @param config FLEXSPI configure structure. */ -void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config); +AT_QUICKACCESS_SECTION_CODE(void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)); /*! * @brief Gets default settings for FLEXSPI. * * @param config FLEXSPI configuration structure. */ -void FLEXSPI_GetDefaultConfig(flexspi_config_t *config); +AT_QUICKACCESS_SECTION_CODE(void FLEXSPI_GetDefaultConfig(flexspi_config_t *config)); /*! * @brief Deinitializes the FLEXSPI module. @@ -384,7 +408,7 @@ void FLEXSPI_UpdateDllValue(FLEXSPI_Type *base, flexspi_device_config_t *config, * @param config Flash configuration parameters. * @param port FLEXSPI Operation port. */ -void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port); +AT_QUICKACCESS_SECTION_CODE(void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, flexspi_port_t port)); /*! * @brief Software reset for the FLEXSPI logic. @@ -394,7 +418,7 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config, * * @param base FLEXSPI peripheral base address. */ -static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base) +AT_QUICKACCESS_SECTION_CODE(static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base)) { base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; while (0U != (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK)) @@ -408,7 +432,7 @@ static inline void FLEXSPI_SoftwareReset(FLEXSPI_Type *base) * @param base FLEXSPI peripheral base address. * @param enable True means enable FLEXSPI, false means disable. */ -static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable) +AT_QUICKACCESS_SECTION_CODE(static inline void FLEXSPI_Enable(FLEXSPI_Type *base, bool enable)) { if (enable) { @@ -578,7 +602,7 @@ static inline uint32_t FLEXSPI_GetInterruptStatusFlags(FLEXSPI_Type *base) * @param base FLEXSPI peripheral base address. * @param mask FLEXSPI interrupt source. */ -static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask) +AT_QUICKACCESS_SECTION_CODE(static inline void FLEXSPI_ClearInterruptStatusFlags(FLEXSPI_Type *base, uint32_t mask)) { base->INTR |= mask; } @@ -647,7 +671,7 @@ static inline flexspi_ahb_error_code_t FLEXSPI_GetAHBCommandErrorCode(FLEXSPI_Ty * @retval true Bus is idle. * @retval false Bus is busy. */ -static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base) +AT_QUICKACCESS_SECTION_CODE(static inline bool FLEXSPI_GetBusIdleStatus(FLEXSPI_Type *base)) { return (0U != (base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK)) && (0U != (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK)); } @@ -708,7 +732,7 @@ static inline void FLEXSPI_EnableAHBParallelMode(FLEXSPI_Type *base, bool enable * @param cmd Command sequence array. * @param count Number of sequences. */ -void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count); +AT_QUICKACCESS_SECTION_CODE(void FLEXSPI_UpdateLUT(FLEXSPI_Type *base, uint32_t index, const uint32_t *cmd, uint32_t count)); /*! * @brief Writes data into FIFO. @@ -745,7 +769,7 @@ static inline uint32_t FLEXSPI_ReadData(FLEXSPI_Type *base, uint8_t fifoIndex) * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected */ -status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size); +AT_QUICKACCESS_SECTION_CODE(status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size)); /*! * @brief Receives a buffer of data bytes using a blocking method. @@ -758,7 +782,7 @@ status_t FLEXSPI_WriteBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequencen error detected * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected */ -status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size); +AT_QUICKACCESS_SECTION_CODE(status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size)); /*! * @brief Execute command to transfer a buffer data bytes using a blocking method. @@ -769,7 +793,7 @@ status_t FLEXSPI_ReadBlocking(FLEXSPI_Type *base, uint32_t *buffer, size_t size) * @retval kStatus_FLEXSPI_IpCommandSequenceError IP command sequence error detected * @retval kStatus_FLEXSPI_IpCommandGrantTimeout IP command grant timeout detected */ -status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer); +AT_QUICKACCESS_SECTION_CODE(status_t FLEXSPI_TransferBlocking(FLEXSPI_Type *base, flexspi_transfer_t *xfer)); /*! @} */ /*! diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_flexspi_nor_boot.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_flexspi_nor_boot.c index 0e7de072bfd..b081facbc24 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_flexspi_nor_boot.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_flexspi_nor_boot.c @@ -1,5 +1,5 @@ /* - * Copyright 2019-2020 NXP + * Copyright 2019-2021 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -27,7 +27,7 @@ const ivt image_vector_table = { IVT_RSVD, /* Reserved = 0 */ (uint32_t)DCD_ADDRESS, /* Address where DCD information is stored */ (uint32_t)BOOT_DATA_ADDRESS, /* Address where BOOT Data Structure is stored */ - (uint32_t)&image_vector_table, /* Pointer to IVT Self (absolute address */ + (uint32_t)IVT_ADDRESS, /* Pointer to IVT Self (absolute address) */ (uint32_t)CSF_ADDRESS, /* Address where CSF file is stored */ IVT_RSVD /* Reserved = 0 */ }; @@ -41,9 +41,9 @@ __attribute__((section(".boot_hdr.boot_data"), used)) * Boot Data *************************************/ const BOOT_DATA_T boot_data = { - FLASH_BASE, /* boot start location */ - FLASH_SIZE, /* size */ + BOOT_IMAGE_BASE, /* boot start location */ + BOOT_IMAGE_SIZE, /* size */ PLUGIN_FLAG, /* Plugin flag*/ - 0xFFFFFFFF /* empty - extra data word */ + 0xFFFFFFFFU /* empty - extra data word */ }; -#endif +#endif \ No newline at end of file diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_flexspi_nor_boot.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_flexspi_nor_boot.h index ef209e106ac..9122e1fd2bc 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_flexspi_nor_boot.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_flexspi_nor_boot.h @@ -1,5 +1,5 @@ /* - * Copyright 2019-2020 NXP + * Copyright 2019-2021 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -9,13 +9,14 @@ #define __FLEXSPI_NOR_BOOT_H__ #include +#include "fsl_common.h" /*! @name Driver version */ /*@{*/ -/*! @brief XIP_DEVICE driver version 2.0.1. */ -#define FSL_XIP_DEVICE_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*! @brief XIP_DEVICE driver version 2.0.2. */ +#define FSL_XIP_DEVICE_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*@}*/ - +#define BOARD_FLASH_SIZE (0x1000000U) /************************************* * IVT Data *************************************/ @@ -65,33 +66,45 @@ typedef struct _ivt_ /* Set resume entry */ #if defined(__CC_ARM) || defined(__ARMCC_VERSION) extern uint32_t Reset_Handler[]; -extern uint32_t Image$$RW_m_config_text$$Base[]; #define IMAGE_ENTRY_ADDRESS ((uint32_t)Reset_Handler) -#define FLASH_BASE ((uint32_t)Image$$RW_m_config_text$$Base - 0x400) +#define BOOT_IMAGE_BASE ((uint32_t)FLASH_BASE) +#define BOOT_IMAGE_SIZE ((uint32_t)FLASH_SIZE) +#define BOOT_DATA_ADDRESS &boot_data +#define IVT_ADDRESS &image_vector_table #elif defined(__MCUXPRESSO) extern uint32_t ResetISR[]; extern uint32_t __boot_hdr_start__[]; +extern uint32_t __boot_hdr_ivt_loadaddr__[]; +extern uint32_t __boot_hdr_boot_data_loadaddr__[]; +extern uint32_t _boot_loadaddr[]; +extern uint32_t _boot_size[]; #define IMAGE_ENTRY_ADDRESS ((uint32_t)ResetISR) -#define FLASH_BASE ((uint32_t)__boot_hdr_start__ - 0x400) +#define BOOT_IMAGE_BASE ((uint32_t)_boot_loadaddr) +#define BOOT_IMAGE_SIZE ((uint32_t)_boot_size) +#define BOOT_DATA_ADDRESS ((uint32_t)__boot_hdr_boot_data_loadaddr__) +#define IVT_ADDRESS ((uint32_t)__boot_hdr_ivt_loadaddr__) #elif defined(__ICCARM__) extern uint32_t Reset_Handler[]; -extern uint32_t m_boot_hdr_conf_start[]; #define IMAGE_ENTRY_ADDRESS ((uint32_t)Reset_Handler) -#define FLASH_BASE ((uint32_t)m_boot_hdr_conf_start - 0x400) +#define BOOT_IMAGE_BASE ((uint32_t)FLASH_BASE) +#define BOOT_IMAGE_SIZE ((uint32_t)FLASH_SIZE) +#define BOOT_DATA_ADDRESS &boot_data +#define IVT_ADDRESS &image_vector_table #elif defined(__GNUC__) extern uint32_t Reset_Handler[]; -extern uint32_t __FLASH_BASE[]; #define IMAGE_ENTRY_ADDRESS ((uint32_t)Reset_Handler) -#define FLASH_BASE ((uint32_t)__FLASH_BASE - 0x400) +#define BOOT_IMAGE_BASE ((uint32_t)FLASH_BASE) +#define BOOT_IMAGE_SIZE ((uint32_t)FLASH_SIZE) +#define BOOT_DATA_ADDRESS &boot_data +#define IVT_ADDRESS &image_vector_table #endif #if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1) -#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1) +#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (1 == XIP_BOOT_HEADER_DCD_ENABLE) #define DCD_ADDRESS dcd_data #else #define DCD_ADDRESS 0 #endif #endif -#define BOOT_DATA_ADDRESS &boot_data #define CSF_ADDRESS 0 #define IVT_RSVD (uint32_t)(0x00000000) @@ -106,7 +119,17 @@ typedef struct _boot_data_ uint32_t placeholder; /* placehoder to make even 0x10 size */ } BOOT_DATA_T; -#define FLASH_SIZE 0x1000000U +#if __CORTEX_M == 7 +#define FLASH_BASE FlexSPI1_AMBA_BASE +#elif __CORTEX_M == 4 +#define FLASH_BASE FlexSPI1_ALIAS_BASE +#endif + +#if defined(BOARD_FLASH_SIZE) +#define FLASH_SIZE BOARD_FLASH_SIZE +#else +#error "Please define macro BOARD_FLASH_SIZE" +#endif #define PLUGIN_FLAG (uint32_t)0 /* External Variables */ @@ -115,4 +138,4 @@ const BOOT_DATA_T boot_data; extern const uint8_t dcd_data[]; #endif -#endif /* __FLEXSPI_NOR_BOOT_H__ */ +#endif /* __FLEXSPI_NOR_BOOT_H__ */ \ No newline at end of file diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_gpio.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_gpio.c index a3f864defcf..d643cf11f59 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_gpio.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_gpio.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2017, 2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -77,7 +77,7 @@ void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config /* If The clock IP is valid, enable the clock gate. */ if ((instance < ARRAY_SIZE(s_gpioClock)) && (kCLOCK_IpInvalid != s_gpioClock[instance])) { - CLOCK_EnableClock(s_gpioClock[instance]); + (void)CLOCK_EnableClock(s_gpioClock[instance]); } #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ @@ -113,11 +113,19 @@ void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output) assert(pin < 32U); if (output == 0U) { +#if (defined(FSL_FEATURE_IGPIO_HAS_DR_CLEAR) && FSL_FEATURE_IGPIO_HAS_DR_CLEAR) + base->DR_CLEAR = (1UL << pin); +#else base->DR &= ~(1UL << pin); /* Set pin output to low level.*/ +#endif } else { +#if (defined(FSL_FEATURE_IGPIO_HAS_DR_SET) && FSL_FEATURE_IGPIO_HAS_DR_SET) + base->DR_SET = (1UL << pin); +#else base->DR |= (1UL << pin); /* Set pin output to high level.*/ +#endif } } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_gpio.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_gpio.h index 81bccca50f5..bfbda252204 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_gpio.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_gpio.h @@ -22,8 +22,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief GPIO driver version 2.0.3. */ -#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) +/*! @brief GPIO driver version. */ +#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) /*@}*/ /*! @brief GPIO direction definition. */ @@ -161,6 +161,8 @@ static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask) { #if (defined(FSL_FEATURE_IGPIO_HAS_DR_TOGGLE) && (FSL_FEATURE_IGPIO_HAS_DR_TOGGLE == 1)) base->DR_TOGGLE = mask; +#else + base->DR ^= mask; #endif /* FSL_FEATURE_IGPIO_HAS_DR_TOGGLE */ } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_iomuxc.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_iomuxc.h index c501b0bc00b..bebffa42f83 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_iomuxc.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_iomuxc.h @@ -28,8 +28,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief IOMUXC driver version 2.0.1. */ -#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) +/*! @brief IOMUXC driver version 2.0.2. */ +#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*@}*/ /*! @@ -38,6 +38,196 @@ * * @{ */ +#define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x40C08000U, 0x0U, 0, 0, 0x40C08040U +#define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x40C08000U, 0x1U, 0, 0, 0x40C08040U +#define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x40C08000U, 0x2U, 0, 0, 0x40C08040U +#define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x40C08000U, 0x3U, 0, 0, 0x40C08040U +#define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x40C08000U, 0x5U, 0, 0, 0x40C08040U +#define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x40C08000U, 0x6U, 0x40C080B0U, 0x0U, 0x40C08040U +#define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x40C08000U, 0x7U, 0x40C080C8U, 0x0U, 0x40C08040U +#define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x40C08000U, 0xAU, 0, 0, 0x40C08040U + +#define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x40C08004U, 0x0U, 0x40C08080U, 0x0U, 0x40C08044U +#define IOMUXC_GPIO_LPSR_01_MIC_BITSTREAM0 0x40C08004U, 0x1U, 0x40C080B4U, 0x0U, 0x40C08044U +#define IOMUXC_GPIO_LPSR_01_MQS_LEFT 0x40C08004U, 0x2U, 0, 0, 0x40C08044U +#define IOMUXC_GPIO_LPSR_01_ARM_CM4_EVENTI 0x40C08004U, 0x3U, 0, 0, 0x40C08044U +#define IOMUXC_GPIO_LPSR_01_GPIO_MUX6_IO01 0x40C08004U, 0x5U, 0, 0, 0x40C08044U +#define IOMUXC_GPIO_LPSR_01_LPUART12_RXD 0x40C08004U, 0x6U, 0x40C080ACU, 0x0U, 0x40C08044U +#define IOMUXC_GPIO_LPSR_01_GPIO12_IO01 0x40C08004U, 0xAU, 0, 0, 0x40C08044U + +#define IOMUXC_GPIO_LPSR_02_GPIO12_IO02 0x40C08008U, 0xAU, 0, 0, 0x40C08048U +#define IOMUXC_GPIO_LPSR_02_SRC_BOOT_MODE00 0x40C08008U, 0x0U, 0, 0, 0x40C08048U +#define IOMUXC_GPIO_LPSR_02_LPSPI5_SCK 0x40C08008U, 0x1U, 0x40C08098U, 0x0U, 0x40C08048U +#define IOMUXC_GPIO_LPSR_02_SAI4_TX_DATA 0x40C08008U, 0x2U, 0, 0, 0x40C08048U +#define IOMUXC_GPIO_LPSR_02_MQS_RIGHT 0x40C08008U, 0x3U, 0, 0, 0x40C08048U +#define IOMUXC_GPIO_LPSR_02_GPIO_MUX6_IO02 0x40C08008U, 0x5U, 0, 0, 0x40C08048U + +#define IOMUXC_GPIO_LPSR_03_SRC_BOOT_MODE01 0x40C0800CU, 0x0U, 0, 0, 0x40C0804CU +#define IOMUXC_GPIO_LPSR_03_LPSPI5_PCS0 0x40C0800CU, 0x1U, 0x40C08094U, 0x0U, 0x40C0804CU +#define IOMUXC_GPIO_LPSR_03_SAI4_TX_SYNC 0x40C0800CU, 0x2U, 0x40C080DCU, 0x0U, 0x40C0804CU +#define IOMUXC_GPIO_LPSR_03_MQS_LEFT 0x40C0800CU, 0x3U, 0, 0, 0x40C0804CU +#define IOMUXC_GPIO_LPSR_03_GPIO_MUX6_IO03 0x40C0800CU, 0x5U, 0, 0, 0x40C0804CU +#define IOMUXC_GPIO_LPSR_03_GPIO12_IO03 0x40C0800CU, 0xAU, 0, 0, 0x40C0804CU + +#define IOMUXC_GPIO_LPSR_04_LPI2C5_SDA 0x40C08010U, 0x0U, 0x40C08088U, 0x0U, 0x40C08050U +#define IOMUXC_GPIO_LPSR_04_LPSPI5_SOUT 0x40C08010U, 0x1U, 0x40C080A0U, 0x0U, 0x40C08050U +#define IOMUXC_GPIO_LPSR_04_SAI4_TX_BCLK 0x40C08010U, 0x2U, 0x40C080D8U, 0x0U, 0x40C08050U +#define IOMUXC_GPIO_LPSR_04_LPUART12_RTS_B 0x40C08010U, 0x3U, 0, 0, 0x40C08050U +#define IOMUXC_GPIO_LPSR_04_GPIO_MUX6_IO04 0x40C08010U, 0x5U, 0, 0, 0x40C08050U +#define IOMUXC_GPIO_LPSR_04_LPUART11_TXD 0x40C08010U, 0x6U, 0x40C080A8U, 0x0U, 0x40C08050U +#define IOMUXC_GPIO_LPSR_04_GPIO12_IO04 0x40C08010U, 0xAU, 0, 0, 0x40C08050U + +#define IOMUXC_GPIO_LPSR_05_GPIO12_IO05 0x40C08014U, 0xAU, 0, 0, 0x40C08054U +#define IOMUXC_GPIO_LPSR_05_LPI2C5_SCL 0x40C08014U, 0x0U, 0x40C08084U, 0x0U, 0x40C08054U +#define IOMUXC_GPIO_LPSR_05_LPSPI5_SIN 0x40C08014U, 0x1U, 0x40C0809CU, 0x0U, 0x40C08054U +#define IOMUXC_GPIO_LPSR_05_SAI4_MCLK 0x40C08014U, 0x2U, 0x40C080C8U, 0x1U, 0x40C08054U +#define IOMUXC_GPIO_LPSR_05_LPUART12_CTS_B 0x40C08014U, 0x3U, 0, 0, 0x40C08054U +#define IOMUXC_GPIO_LPSR_05_GPIO_MUX6_IO05 0x40C08014U, 0x5U, 0, 0, 0x40C08054U +#define IOMUXC_GPIO_LPSR_05_LPUART11_RXD 0x40C08014U, 0x6U, 0x40C080A4U, 0x0U, 0x40C08054U +#define IOMUXC_GPIO_LPSR_05_NMI_GLUE_NMI 0x40C08014U, 0x7U, 0x40C080C4U, 0x0U, 0x40C08054U + +#define IOMUXC_GPIO_LPSR_06_LPI2C6_SDA 0x40C08018U, 0x0U, 0x40C08090U, 0x0U, 0x40C08058U +#define IOMUXC_GPIO_LPSR_06_SAI4_RX_DATA 0x40C08018U, 0x2U, 0x40C080D0U, 0x0U, 0x40C08058U +#define IOMUXC_GPIO_LPSR_06_LPUART12_TXD 0x40C08018U, 0x3U, 0x40C080B0U, 0x1U, 0x40C08058U +#define IOMUXC_GPIO_LPSR_06_LPSPI6_PCS3 0x40C08018U, 0x4U, 0, 0, 0x40C08058U +#define IOMUXC_GPIO_LPSR_06_GPIO_MUX6_IO06 0x40C08018U, 0x5U, 0, 0, 0x40C08058U +#define IOMUXC_GPIO_LPSR_06_FLEXCAN3_TX 0x40C08018U, 0x6U, 0, 0, 0x40C08058U +#define IOMUXC_GPIO_LPSR_06_PIT2_TRIGGER3 0x40C08018U, 0x7U, 0, 0, 0x40C08058U +#define IOMUXC_GPIO_LPSR_06_LPSPI5_PCS1 0x40C08018U, 0x8U, 0, 0, 0x40C08058U +#define IOMUXC_GPIO_LPSR_06_GPIO12_IO06 0x40C08018U, 0xAU, 0, 0, 0x40C08058U + +#define IOMUXC_GPIO_LPSR_07_LPI2C6_SCL 0x40C0801CU, 0x0U, 0x40C0808CU, 0x0U, 0x40C0805CU +#define IOMUXC_GPIO_LPSR_07_SAI4_RX_BCLK 0x40C0801CU, 0x2U, 0x40C080CCU, 0x0U, 0x40C0805CU +#define IOMUXC_GPIO_LPSR_07_LPUART12_RXD 0x40C0801CU, 0x3U, 0x40C080ACU, 0x1U, 0x40C0805CU +#define IOMUXC_GPIO_LPSR_07_LPSPI6_PCS2 0x40C0801CU, 0x4U, 0, 0, 0x40C0805CU +#define IOMUXC_GPIO_LPSR_07_GPIO_MUX6_IO07 0x40C0801CU, 0x5U, 0, 0, 0x40C0805CU +#define IOMUXC_GPIO_LPSR_07_FLEXCAN3_RX 0x40C0801CU, 0x6U, 0x40C08080U, 0x1U, 0x40C0805CU +#define IOMUXC_GPIO_LPSR_07_PIT2_TRIGGER2 0x40C0801CU, 0x7U, 0, 0, 0x40C0805CU +#define IOMUXC_GPIO_LPSR_07_LPSPI5_PCS2 0x40C0801CU, 0x8U, 0, 0, 0x40C0805CU +#define IOMUXC_GPIO_LPSR_07_GPIO12_IO07 0x40C0801CU, 0xAU, 0, 0, 0x40C0805CU + +#define IOMUXC_GPIO_LPSR_08_GPIO12_IO08 0x40C08020U, 0xAU, 0, 0, 0x40C08060U +#define IOMUXC_GPIO_LPSR_08_LPUART11_TXD 0x40C08020U, 0x0U, 0x40C080A8U, 0x1U, 0x40C08060U +#define IOMUXC_GPIO_LPSR_08_FLEXCAN3_TX 0x40C08020U, 0x1U, 0, 0, 0x40C08060U +#define IOMUXC_GPIO_LPSR_08_SAI4_RX_SYNC 0x40C08020U, 0x2U, 0x40C080D4U, 0x0U, 0x40C08060U +#define IOMUXC_GPIO_LPSR_08_MIC_CLK 0x40C08020U, 0x3U, 0, 0, 0x40C08060U +#define IOMUXC_GPIO_LPSR_08_LPSPI6_PCS1 0x40C08020U, 0x4U, 0, 0, 0x40C08060U +#define IOMUXC_GPIO_LPSR_08_GPIO_MUX6_IO08 0x40C08020U, 0x5U, 0, 0, 0x40C08060U +#define IOMUXC_GPIO_LPSR_08_LPI2C5_SDA 0x40C08020U, 0x6U, 0x40C08088U, 0x1U, 0x40C08060U +#define IOMUXC_GPIO_LPSR_08_PIT2_TRIGGER1 0x40C08020U, 0x7U, 0, 0, 0x40C08060U +#define IOMUXC_GPIO_LPSR_08_LPSPI5_PCS3 0x40C08020U, 0x8U, 0, 0, 0x40C08060U + +#define IOMUXC_GPIO_LPSR_09_GPIO12_IO09 0x40C08024U, 0xAU, 0, 0, 0x40C08064U +#define IOMUXC_GPIO_LPSR_09_LPUART11_RXD 0x40C08024U, 0x0U, 0x40C080A4U, 0x1U, 0x40C08064U +#define IOMUXC_GPIO_LPSR_09_FLEXCAN3_RX 0x40C08024U, 0x1U, 0x40C08080U, 0x2U, 0x40C08064U +#define IOMUXC_GPIO_LPSR_09_PIT2_TRIGGER0 0x40C08024U, 0x2U, 0, 0, 0x40C08064U +#define IOMUXC_GPIO_LPSR_09_MIC_BITSTREAM0 0x40C08024U, 0x3U, 0x40C080B4U, 0x1U, 0x40C08064U +#define IOMUXC_GPIO_LPSR_09_LPSPI6_PCS0 0x40C08024U, 0x4U, 0, 0, 0x40C08064U +#define IOMUXC_GPIO_LPSR_09_GPIO_MUX6_IO09 0x40C08024U, 0x5U, 0, 0, 0x40C08064U +#define IOMUXC_GPIO_LPSR_09_LPI2C5_SCL 0x40C08024U, 0x6U, 0x40C08084U, 0x1U, 0x40C08064U +#define IOMUXC_GPIO_LPSR_09_SAI4_TX_DATA 0x40C08024U, 0x7U, 0, 0, 0x40C08064U + +#define IOMUXC_GPIO_LPSR_10_GPIO12_IO10 0x40C08028U, 0xAU, 0, 0, 0x40C08068U +#define IOMUXC_GPIO_LPSR_10_JTAG_MUX_TRSTB 0x40C08028U, 0x0U, 0, 0, 0x40C08068U +#define IOMUXC_GPIO_LPSR_10_LPUART11_CTS_B 0x40C08028U, 0x1U, 0, 0, 0x40C08068U +#define IOMUXC_GPIO_LPSR_10_LPI2C6_SDA 0x40C08028U, 0x2U, 0x40C08090U, 0x1U, 0x40C08068U +#define IOMUXC_GPIO_LPSR_10_MIC_BITSTREAM1 0x40C08028U, 0x3U, 0x40C080B8U, 0x0U, 0x40C08068U +#define IOMUXC_GPIO_LPSR_10_LPSPI6_SCK 0x40C08028U, 0x4U, 0, 0, 0x40C08068U +#define IOMUXC_GPIO_LPSR_10_GPIO_MUX6_IO10 0x40C08028U, 0x5U, 0, 0, 0x40C08068U +#define IOMUXC_GPIO_LPSR_10_LPI2C5_SCLS 0x40C08028U, 0x6U, 0, 0, 0x40C08068U +#define IOMUXC_GPIO_LPSR_10_SAI4_TX_SYNC 0x40C08028U, 0x7U, 0x40C080DCU, 0x1U, 0x40C08068U +#define IOMUXC_GPIO_LPSR_10_LPUART12_TXD 0x40C08028U, 0x8U, 0x40C080B0U, 0x2U, 0x40C08068U + +#define IOMUXC_GPIO_LPSR_11_JTAG_MUX_TDO 0x40C0802CU, 0x0U, 0, 0, 0x40C0806CU +#define IOMUXC_GPIO_LPSR_11_LPUART11_RTS_B 0x40C0802CU, 0x1U, 0, 0, 0x40C0806CU +#define IOMUXC_GPIO_LPSR_11_LPI2C6_SCL 0x40C0802CU, 0x2U, 0x40C0808CU, 0x1U, 0x40C0806CU +#define IOMUXC_GPIO_LPSR_11_MIC_BITSTREAM2 0x40C0802CU, 0x3U, 0x40C080BCU, 0x0U, 0x40C0806CU +#define IOMUXC_GPIO_LPSR_11_LPSPI6_SOUT 0x40C0802CU, 0x4U, 0, 0, 0x40C0806CU +#define IOMUXC_GPIO_LPSR_11_GPIO_MUX6_IO11 0x40C0802CU, 0x5U, 0, 0, 0x40C0806CU +#define IOMUXC_GPIO_LPSR_11_LPI2C5_SDAS 0x40C0802CU, 0x6U, 0, 0, 0x40C0806CU +#define IOMUXC_GPIO_LPSR_11_ARM_TRACE_SWO 0x40C0802CU, 0x7U, 0, 0, 0x40C0806CU +#define IOMUXC_GPIO_LPSR_11_LPUART12_RXD 0x40C0802CU, 0x8U, 0x40C080ACU, 0x2U, 0x40C0806CU +#define IOMUXC_GPIO_LPSR_11_GPIO12_IO11 0x40C0802CU, 0xAU, 0, 0, 0x40C0806CU + +#define IOMUXC_GPIO_LPSR_12_GPIO12_IO12 0x40C08030U, 0xAU, 0, 0, 0x40C08070U +#define IOMUXC_GPIO_LPSR_12_JTAG_MUX_TDI 0x40C08030U, 0x0U, 0, 0, 0x40C08070U +#define IOMUXC_GPIO_LPSR_12_PIT2_TRIGGER0 0x40C08030U, 0x1U, 0, 0, 0x40C08070U +#define IOMUXC_GPIO_LPSR_12_MIC_BITSTREAM3 0x40C08030U, 0x3U, 0x40C080C0U, 0x0U, 0x40C08070U +#define IOMUXC_GPIO_LPSR_12_LPSPI6_SIN 0x40C08030U, 0x4U, 0, 0, 0x40C08070U +#define IOMUXC_GPIO_LPSR_12_GPIO_MUX6_IO12 0x40C08030U, 0x5U, 0, 0, 0x40C08070U +#define IOMUXC_GPIO_LPSR_12_LPI2C5_HREQ 0x40C08030U, 0x6U, 0, 0, 0x40C08070U +#define IOMUXC_GPIO_LPSR_12_SAI4_TX_BCLK 0x40C08030U, 0x7U, 0x40C080D8U, 0x1U, 0x40C08070U +#define IOMUXC_GPIO_LPSR_12_LPSPI5_SCK 0x40C08030U, 0x8U, 0x40C08098U, 0x1U, 0x40C08070U + +#define IOMUXC_GPIO_LPSR_13_GPIO12_IO13 0x40C08034U, 0xAU, 0, 0, 0x40C08074U +#define IOMUXC_GPIO_LPSR_13_JTAG_MUX_MOD 0x40C08034U, 0x0U, 0, 0, 0x40C08074U +#define IOMUXC_GPIO_LPSR_13_MIC_BITSTREAM1 0x40C08034U, 0x1U, 0x40C080B8U, 0x1U, 0x40C08074U +#define IOMUXC_GPIO_LPSR_13_PIT2_TRIGGER1 0x40C08034U, 0x2U, 0, 0, 0x40C08074U +#define IOMUXC_GPIO_LPSR_13_GPIO_MUX6_IO13 0x40C08034U, 0x5U, 0, 0, 0x40C08074U +#define IOMUXC_GPIO_LPSR_13_SAI4_RX_DATA 0x40C08034U, 0x7U, 0x40C080D0U, 0x1U, 0x40C08074U +#define IOMUXC_GPIO_LPSR_13_LPSPI5_PCS0 0x40C08034U, 0x8U, 0x40C08094U, 0x1U, 0x40C08074U + +#define IOMUXC_GPIO_LPSR_14_JTAG_MUX_TCK 0x40C08038U, 0x0U, 0, 0, 0x40C08078U +#define IOMUXC_GPIO_LPSR_14_MIC_BITSTREAM2 0x40C08038U, 0x1U, 0x40C080BCU, 0x1U, 0x40C08078U +#define IOMUXC_GPIO_LPSR_14_PIT2_TRIGGER2 0x40C08038U, 0x2U, 0, 0, 0x40C08078U +#define IOMUXC_GPIO_LPSR_14_GPIO_MUX6_IO14 0x40C08038U, 0x5U, 0, 0, 0x40C08078U +#define IOMUXC_GPIO_LPSR_14_SAI4_RX_BCLK 0x40C08038U, 0x7U, 0x40C080CCU, 0x1U, 0x40C08078U +#define IOMUXC_GPIO_LPSR_14_LPSPI5_SOUT 0x40C08038U, 0x8U, 0x40C080A0U, 0x1U, 0x40C08078U +#define IOMUXC_GPIO_LPSR_14_GPIO12_IO14 0x40C08038U, 0xAU, 0, 0, 0x40C08078U + +#define IOMUXC_GPIO_LPSR_15_GPIO12_IO15 0x40C0803CU, 0xAU, 0, 0, 0x40C0807CU +#define IOMUXC_GPIO_LPSR_15_JTAG_MUX_TMS 0x40C0803CU, 0x0U, 0, 0, 0x40C0807CU +#define IOMUXC_GPIO_LPSR_15_MIC_BITSTREAM3 0x40C0803CU, 0x1U, 0x40C080C0U, 0x1U, 0x40C0807CU +#define IOMUXC_GPIO_LPSR_15_PIT2_TRIGGER3 0x40C0803CU, 0x2U, 0, 0, 0x40C0807CU +#define IOMUXC_GPIO_LPSR_15_GPIO_MUX6_IO15 0x40C0803CU, 0x5U, 0, 0, 0x40C0807CU +#define IOMUXC_GPIO_LPSR_15_SAI4_RX_SYNC 0x40C0803CU, 0x7U, 0x40C080D4U, 0x1U, 0x40C0807CU +#define IOMUXC_GPIO_LPSR_15_LPSPI5_SIN 0x40C0803CU, 0x8U, 0x40C0809CU, 0x1U, 0x40C0807CU + +#define IOMUXC_WAKEUP_DIG_GPIO13_IO00 0x40C94000U, 0x5U, 0, 0, 0x40C94040U +#define IOMUXC_WAKEUP_DIG_NMI_GLUE_NMI 0x40C94000U, 0x7U, 0x40C080C4U, 0x1U, 0x40C94040U + +#define IOMUXC_PMIC_ON_REQ_DIG_SNVS_LP_PMIC_ON_REQ 0x40C94004U, 0x0U, 0, 0, 0x40C94044U +#define IOMUXC_PMIC_ON_REQ_DIG_GPIO13_IO01 0x40C94004U, 0x5U, 0, 0, 0x40C94044U + +#define IOMUXC_PMIC_STBY_REQ_DIG_CCM_PMIC_VSTBY_REQ 0x40C94008U, 0x0U, 0, 0, 0x40C94048U +#define IOMUXC_PMIC_STBY_REQ_DIG_GPIO13_IO02 0x40C94008U, 0x5U, 0, 0, 0x40C94048U + +#define IOMUXC_GPIO_SNVS_00_DIG_SNVS_TAMPER0 0x40C9400CU, 0x0U, 0, 0, 0x40C9404CU +#define IOMUXC_GPIO_SNVS_00_DIG_GPIO13_IO03 0x40C9400CU, 0x5U, 0, 0, 0x40C9404CU + +#define IOMUXC_GPIO_SNVS_01_DIG_SNVS_TAMPER1 0x40C94010U, 0x0U, 0, 0, 0x40C94050U +#define IOMUXC_GPIO_SNVS_01_DIG_GPIO13_IO04 0x40C94010U, 0x5U, 0, 0, 0x40C94050U + +#define IOMUXC_GPIO_SNVS_02_DIG_SNVS_TAMPER2 0x40C94014U, 0x0U, 0, 0, 0x40C94054U +#define IOMUXC_GPIO_SNVS_02_DIG_GPIO13_IO05 0x40C94014U, 0x5U, 0, 0, 0x40C94054U + +#define IOMUXC_GPIO_SNVS_03_DIG_SNVS_TAMPER3 0x40C94018U, 0x0U, 0, 0, 0x40C94058U +#define IOMUXC_GPIO_SNVS_03_DIG_GPIO13_IO06 0x40C94018U, 0x5U, 0, 0, 0x40C94058U + +#define IOMUXC_GPIO_SNVS_04_DIG_SNVS_TAMPER4 0x40C9401CU, 0x0U, 0, 0, 0x40C9405CU +#define IOMUXC_GPIO_SNVS_04_DIG_GPIO13_IO07 0x40C9401CU, 0x5U, 0, 0, 0x40C9405CU + +#define IOMUXC_GPIO_SNVS_05_DIG_SNVS_TAMPER5 0x40C94020U, 0x0U, 0, 0, 0x40C94060U +#define IOMUXC_GPIO_SNVS_05_DIG_GPIO13_IO08 0x40C94020U, 0x5U, 0, 0, 0x40C94060U + +#define IOMUXC_GPIO_SNVS_06_DIG_SNVS_TAMPER6 0x40C94024U, 0x0U, 0, 0, 0x40C94064U +#define IOMUXC_GPIO_SNVS_06_DIG_GPIO13_IO09 0x40C94024U, 0x5U, 0, 0, 0x40C94064U + +#define IOMUXC_GPIO_SNVS_07_DIG_SNVS_TAMPER7 0x40C94028U, 0x0U, 0, 0, 0x40C94068U +#define IOMUXC_GPIO_SNVS_07_DIG_GPIO13_IO10 0x40C94028U, 0x5U, 0, 0, 0x40C94068U + +#define IOMUXC_GPIO_SNVS_08_DIG_SNVS_TAMPER8 0x40C9402CU, 0x0U, 0, 0, 0x40C9406CU +#define IOMUXC_GPIO_SNVS_08_DIG_GPIO13_IO11 0x40C9402CU, 0x5U, 0, 0, 0x40C9406CU + +#define IOMUXC_GPIO_SNVS_09_DIG_SNVS_TAMPER9 0x40C94030U, 0x0U, 0, 0, 0x40C94070U +#define IOMUXC_GPIO_SNVS_09_DIG_GPIO13_IO12 0x40C94030U, 0x5U, 0, 0, 0x40C94070U + +#define IOMUXC_TEST_MODE_DIG 0, 0, 0, 0, 0x40C94034U + +#define IOMUXC_POR_B_DIG 0, 0, 0, 0, 0x40C94038U + +#define IOMUXC_ONOFF_DIG 0, 0, 0, 0, 0x40C9403CU + #define IOMUXC_GPIO_EMC_B1_00_SEMC_DATA00 0x400E8010U, 0x0U, 0, 0, 0x400E8254U #define IOMUXC_GPIO_EMC_B1_00_FLEXPWM4_PWM0_A 0x400E8010U, 0x1U, 0, 0, 0x400E8254U #define IOMUXC_GPIO_EMC_B1_00_GPIO_MUX1_IO00 0x400E8010U, 0x5U, 0, 0, 0x400E8254U @@ -524,7 +714,7 @@ #define IOMUXC_GPIO_EMC_B2_19_SEMC_CLKX00 0x400E8104U, 0x0U, 0, 0, 0x400E8348U #define IOMUXC_GPIO_EMC_B2_19_ENET_MDC 0x400E8104U, 0x1U, 0, 0, 0x400E8348U #define IOMUXC_GPIO_EMC_B2_19_ENET_1G_MDC 0x400E8104U, 0x2U, 0, 0, 0x400E8348U -#define IOMUXC_GPIO_EMC_B2_19_ENET_1G_REF_CLK1 0x400E8104U, 0x3U, 0x400E84C4U, 0x0U, 0x400E8348U +#define IOMUXC_GPIO_EMC_B2_19_ENET_1G_REF_CLK 0x400E8104U, 0x3U, 0x400E84C4U, 0x0U, 0x400E8348U #define IOMUXC_GPIO_EMC_B2_19_FLEXSPI2_A_DATA06 0x400E8104U, 0x4U, 0, 0, 0x400E8348U #define IOMUXC_GPIO_EMC_B2_19_GPIO_MUX2_IO29 0x400E8104U, 0x5U, 0, 0, 0x400E8348U #define IOMUXC_GPIO_EMC_B2_19_ENET_QOS_MDC 0x400E8104U, 0x8U, 0, 0, 0x400E8348U @@ -534,7 +724,7 @@ #define IOMUXC_GPIO_EMC_B2_20_SEMC_CLKX01 0x400E8108U, 0x0U, 0, 0, 0x400E834CU #define IOMUXC_GPIO_EMC_B2_20_ENET_MDIO 0x400E8108U, 0x1U, 0x400E84ACU, 0x0U, 0x400E834CU #define IOMUXC_GPIO_EMC_B2_20_ENET_1G_MDIO 0x400E8108U, 0x2U, 0x400E84C8U, 0x1U, 0x400E834CU -#define IOMUXC_GPIO_EMC_B2_20_ENET_QOS_REF_CLK1 0x400E8108U, 0x3U, 0x400E84A0U, 0x0U, 0x400E834CU +#define IOMUXC_GPIO_EMC_B2_20_ENET_QOS_REF_CLK 0x400E8108U, 0x3U, 0x400E84A0U, 0x0U, 0x400E834CU #define IOMUXC_GPIO_EMC_B2_20_FLEXSPI2_A_DATA07 0x400E8108U, 0x4U, 0, 0, 0x400E834CU #define IOMUXC_GPIO_EMC_B2_20_GPIO_MUX2_IO30 0x400E8108U, 0x5U, 0, 0, 0x400E834CU #define IOMUXC_GPIO_EMC_B2_20_ENET_QOS_MDIO 0x400E8108U, 0x8U, 0x400E84ECU, 0x0U, 0x400E834CU @@ -872,7 +1062,7 @@ #define IOMUXC_GPIO_AD_29_LPSPI1_PCS0 0x400E8180U, 0x0U, 0x400E85CCU, 0x1U, 0x400E83C4U #define IOMUXC_GPIO_AD_29_LPUART5_RXD 0x400E8180U, 0x1U, 0, 0, 0x400E83C4U -#define IOMUXC_GPIO_AD_29_ENET_REF_CLK1 0x400E8180U, 0x2U, 0x400E84A8U, 0x0U, 0x400E83C4U +#define IOMUXC_GPIO_AD_29_ENET_REF_CLK 0x400E8180U, 0x2U, 0x400E84A8U, 0x0U, 0x400E83C4U #define IOMUXC_GPIO_AD_29_ENET_TX_CLK 0x400E8180U, 0x3U, 0x400E84C0U, 0x0U, 0x400E83C4U #define IOMUXC_GPIO_AD_29_FLEXPWM2_PWM2_B 0x400E8180U, 0x4U, 0x400E852CU, 0x1U, 0x400E83C4U #define IOMUXC_GPIO_AD_29_GPIO_MUX3_IO28 0x400E8180U, 0x5U, 0, 0, 0x400E83C4U @@ -890,7 +1080,7 @@ #define IOMUXC_GPIO_AD_30_GPIO_MUX3_IO29 0x400E8184U, 0x5U, 0, 0, 0x400E83C8U #define IOMUXC_GPIO_AD_30_KPP_ROW02 0x400E8184U, 0x6U, 0, 0, 0x400E83C8U #define IOMUXC_GPIO_AD_30_FLEXIO2_D30 0x400E8184U, 0x8U, 0, 0, 0x400E83C8U -#define IOMUXC_GPIO_AD_30_WDOG2_RST_B_DEB 0x400E8184U, 0x9U, 0, 0, 0x400E83C8U +#define IOMUXC_GPIO_AD_30_WDOG2_RESET_B_DEB 0x400E8184U, 0x9U, 0, 0, 0x400E83C8U #define IOMUXC_GPIO_AD_30_GPIO9_IO29 0x400E8184U, 0xAU, 0, 0, 0x400E83C8U #define IOMUXC_GPIO_AD_31_LPSPI1_SIN 0x400E8188U, 0x0U, 0x400E85D4U, 0x1U, 0x400E83CCU @@ -901,7 +1091,7 @@ #define IOMUXC_GPIO_AD_31_GPIO_MUX3_IO30 0x400E8188U, 0x5U, 0, 0, 0x400E83CCU #define IOMUXC_GPIO_AD_31_KPP_COL02 0x400E8188U, 0x6U, 0, 0, 0x400E83CCU #define IOMUXC_GPIO_AD_31_FLEXIO2_D31 0x400E8188U, 0x8U, 0, 0, 0x400E83CCU -#define IOMUXC_GPIO_AD_31_WDOG1_RST_B_DEB 0x400E8188U, 0x9U, 0, 0, 0x400E83CCU +#define IOMUXC_GPIO_AD_31_WDOG1_RESET_B_DEB 0x400E8188U, 0x9U, 0, 0, 0x400E83CCU #define IOMUXC_GPIO_AD_31_GPIO9_IO30 0x400E8188U, 0xAU, 0, 0, 0x400E83CCU #define IOMUXC_GPIO_AD_32_GPIO9_IO31 0x400E818CU, 0xAU, 0, 0, 0x400E83D0U @@ -951,7 +1141,6 @@ #define IOMUXC_GPIO_SD_B1_00_USDHC1_CMD 0x400E819CU, 0x0U, 0, 0, 0x400E83E0U #define IOMUXC_GPIO_SD_B1_00_XBAR1_INOUT20 0x400E819CU, 0x2U, 0x400E86D8U, 0x1U, 0x400E83E0U #define IOMUXC_GPIO_SD_B1_00_GPT4_CAPTURE1 0x400E819CU, 0x3U, 0, 0, 0x400E83E0U -#define IOMUXC_GPIO_SD_B1_00_SDIO_SLV_CMD 0x400E819CU, 0x4U, 0x400E8688U, 0x0U, 0x400E83E0U #define IOMUXC_GPIO_SD_B1_00_GPIO_MUX4_IO03 0x400E819CU, 0x5U, 0, 0, 0x400E83E0U #define IOMUXC_GPIO_SD_B1_00_FLEXSPI2_A_SS0_B 0x400E819CU, 0x6U, 0, 0, 0x400E83E0U #define IOMUXC_GPIO_SD_B1_00_KPP_ROW07 0x400E819CU, 0x8U, 0x400E85A8U, 0x1U, 0x400E83E0U @@ -960,7 +1149,6 @@ #define IOMUXC_GPIO_SD_B1_01_USDHC1_CLK 0x400E81A0U, 0x0U, 0, 0, 0x400E83E4U #define IOMUXC_GPIO_SD_B1_01_XBAR1_INOUT21 0x400E81A0U, 0x2U, 0x400E86DCU, 0x1U, 0x400E83E4U #define IOMUXC_GPIO_SD_B1_01_GPT4_CAPTURE2 0x400E81A0U, 0x3U, 0, 0, 0x400E83E4U -#define IOMUXC_GPIO_SD_B1_01_SDIO_SLV_CLK 0x400E81A0U, 0x4U, 0x400E8684U, 0x0U, 0x400E83E4U #define IOMUXC_GPIO_SD_B1_01_GPIO_MUX4_IO04 0x400E81A0U, 0x5U, 0, 0, 0x400E83E4U #define IOMUXC_GPIO_SD_B1_01_FLEXSPI2_A_SCLK 0x400E81A0U, 0x6U, 0x400E858CU, 0x1U, 0x400E83E4U #define IOMUXC_GPIO_SD_B1_01_KPP_COL07 0x400E81A0U, 0x8U, 0x400E85A0U, 0x1U, 0x400E83E4U @@ -970,7 +1158,6 @@ #define IOMUXC_GPIO_SD_B1_02_USDHC1_DATA0 0x400E81A4U, 0x0U, 0, 0, 0x400E83E8U #define IOMUXC_GPIO_SD_B1_02_XBAR1_INOUT22 0x400E81A4U, 0x2U, 0x400E86E0U, 0x1U, 0x400E83E8U #define IOMUXC_GPIO_SD_B1_02_GPT4_COMPARE1 0x400E81A4U, 0x3U, 0, 0, 0x400E83E8U -#define IOMUXC_GPIO_SD_B1_02_SDIO_SLV_DATA0 0x400E81A4U, 0x4U, 0x400E868CU, 0x0U, 0x400E83E8U #define IOMUXC_GPIO_SD_B1_02_GPIO_MUX4_IO05 0x400E81A4U, 0x5U, 0, 0, 0x400E83E8U #define IOMUXC_GPIO_SD_B1_02_FLEXSPI2_A_DATA00 0x400E81A4U, 0x6U, 0x400E857CU, 0x1U, 0x400E83E8U #define IOMUXC_GPIO_SD_B1_02_KPP_ROW06 0x400E81A4U, 0x8U, 0x400E85A4U, 0x1U, 0x400E83E8U @@ -979,7 +1166,6 @@ #define IOMUXC_GPIO_SD_B1_03_USDHC1_DATA1 0x400E81A8U, 0x0U, 0, 0, 0x400E83ECU #define IOMUXC_GPIO_SD_B1_03_XBAR1_INOUT23 0x400E81A8U, 0x2U, 0x400E86E4U, 0x1U, 0x400E83ECU #define IOMUXC_GPIO_SD_B1_03_GPT4_COMPARE2 0x400E81A8U, 0x3U, 0, 0, 0x400E83ECU -#define IOMUXC_GPIO_SD_B1_03_SDIO_SLV_DATA1 0x400E81A8U, 0x4U, 0x400E8690U, 0x0U, 0x400E83ECU #define IOMUXC_GPIO_SD_B1_03_GPIO_MUX4_IO06 0x400E81A8U, 0x5U, 0, 0, 0x400E83ECU #define IOMUXC_GPIO_SD_B1_03_FLEXSPI2_A_DATA01 0x400E81A8U, 0x6U, 0x400E8580U, 0x1U, 0x400E83ECU #define IOMUXC_GPIO_SD_B1_03_KPP_COL06 0x400E81A8U, 0x8U, 0x400E859CU, 0x1U, 0x400E83ECU @@ -989,7 +1175,6 @@ #define IOMUXC_GPIO_SD_B1_04_USDHC1_DATA2 0x400E81ACU, 0x0U, 0, 0, 0x400E83F0U #define IOMUXC_GPIO_SD_B1_04_XBAR1_INOUT24 0x400E81ACU, 0x2U, 0x400E86E8U, 0x1U, 0x400E83F0U #define IOMUXC_GPIO_SD_B1_04_GPT4_COMPARE3 0x400E81ACU, 0x3U, 0, 0, 0x400E83F0U -#define IOMUXC_GPIO_SD_B1_04_SDIO_SLV_DATA2 0x400E81ACU, 0x4U, 0x400E8694U, 0x0U, 0x400E83F0U #define IOMUXC_GPIO_SD_B1_04_GPIO_MUX4_IO07 0x400E81ACU, 0x5U, 0, 0, 0x400E83F0U #define IOMUXC_GPIO_SD_B1_04_FLEXSPI2_A_DATA02 0x400E81ACU, 0x6U, 0x400E8584U, 0x1U, 0x400E83F0U #define IOMUXC_GPIO_SD_B1_04_FLEXSPI1_B_SS0_B 0x400E81ACU, 0x8U, 0, 0, 0x400E83F0U @@ -1000,7 +1185,6 @@ #define IOMUXC_GPIO_SD_B1_05_USDHC1_DATA3 0x400E81B0U, 0x0U, 0, 0, 0x400E83F4U #define IOMUXC_GPIO_SD_B1_05_XBAR1_INOUT25 0x400E81B0U, 0x2U, 0x400E86ECU, 0x1U, 0x400E83F4U #define IOMUXC_GPIO_SD_B1_05_GPT4_CLK 0x400E81B0U, 0x3U, 0, 0, 0x400E83F4U -#define IOMUXC_GPIO_SD_B1_05_SDIO_SLV_DATA3 0x400E81B0U, 0x4U, 0x400E8698U, 0x0U, 0x400E83F4U #define IOMUXC_GPIO_SD_B1_05_GPIO_MUX4_IO08 0x400E81B0U, 0x5U, 0, 0, 0x400E83F4U #define IOMUXC_GPIO_SD_B1_05_FLEXSPI2_A_DATA03 0x400E81B0U, 0x6U, 0x400E8588U, 0x1U, 0x400E83F4U #define IOMUXC_GPIO_SD_B1_05_FLEXSPI1_B_DQS 0x400E81B0U, 0x8U, 0, 0, 0x400E83F4U @@ -1070,7 +1254,7 @@ #define IOMUXC_GPIO_SD_B2_07_GPIO_MUX4_IO16 0x400E81D0U, 0x5U, 0, 0, 0x400E8414U #define IOMUXC_GPIO_SD_B2_07_LPSPI2_SCK 0x400E81D0U, 0x6U, 0x400E85E4U, 0x1U, 0x400E8414U #define IOMUXC_GPIO_SD_B2_07_ENET_TX_ER 0x400E81D0U, 0x8U, 0, 0, 0x400E8414U -#define IOMUXC_GPIO_SD_B2_07_ENET_QOS_REF_CLK1 0x400E81D0U, 0x9U, 0x400E84A0U, 0x1U, 0x400E8414U +#define IOMUXC_GPIO_SD_B2_07_ENET_QOS_REF_CLK 0x400E81D0U, 0x9U, 0x400E84A0U, 0x1U, 0x400E8414U #define IOMUXC_GPIO_SD_B2_07_GPIO10_IO16 0x400E81D0U, 0xAU, 0, 0, 0x400E8414U #define IOMUXC_GPIO_SD_B2_08_GPIO10_IO17 0x400E81D4U, 0xAU, 0, 0, 0x400E8418U @@ -1103,7 +1287,7 @@ #define IOMUXC_GPIO_SD_B2_11_USDHC2_DATA7 0x400E81E0U, 0x0U, 0, 0, 0x400E8424U #define IOMUXC_GPIO_SD_B2_11_FLEXSPI1_A_DATA03 0x400E81E0U, 0x1U, 0x400E8560U, 0x1U, 0x400E8424U #define IOMUXC_GPIO_SD_B2_11_ENET_1G_TX_CLK_IO 0x400E81E0U, 0x2U, 0x400E84E8U, 0x1U, 0x400E8424U -#define IOMUXC_GPIO_SD_B2_11_ENET_1G_REF_CLK1 0x400E81E0U, 0x3U, 0x400E84C4U, 0x1U, 0x400E8424U +#define IOMUXC_GPIO_SD_B2_11_ENET_1G_REF_CLK 0x400E81E0U, 0x3U, 0x400E84C4U, 0x1U, 0x400E8424U #define IOMUXC_GPIO_SD_B2_11_GPT6_CLK 0x400E81E0U, 0x4U, 0, 0, 0x400E8424U #define IOMUXC_GPIO_SD_B2_11_GPIO_MUX4_IO20 0x400E81E0U, 0x5U, 0, 0, 0x400E8424U #define IOMUXC_GPIO_SD_B2_11_LPSPI2_PCS1 0x400E81E0U, 0x6U, 0x400E85E0U, 0x1U, 0x400E8424U @@ -1114,7 +1298,6 @@ #define IOMUXC_GPIO_DISP_B1_00_TMR1_TIMER0 0x400E81E4U, 0x3U, 0x400E863CU, 0x2U, 0x400E8428U #define IOMUXC_GPIO_DISP_B1_00_XBAR1_INOUT26 0x400E81E4U, 0x4U, 0x400E86F0U, 0x1U, 0x400E8428U #define IOMUXC_GPIO_DISP_B1_00_GPIO_MUX4_IO21 0x400E81E4U, 0x5U, 0, 0, 0x400E8428U -#define IOMUXC_GPIO_DISP_B1_00_SDIO_SLV_CMD 0x400E81E4U, 0x6U, 0x400E8688U, 0x1U, 0x400E8428U #define IOMUXC_GPIO_DISP_B1_00_ENET_QOS_RX_EN 0x400E81E4U, 0x8U, 0x400E84F8U, 0x0U, 0x400E8428U #define IOMUXC_GPIO_DISP_B1_00_GPIO10_IO21 0x400E81E4U, 0xAU, 0, 0, 0x400E8428U @@ -1124,7 +1307,6 @@ #define IOMUXC_GPIO_DISP_B1_01_TMR1_TIMER1 0x400E81E8U, 0x3U, 0x400E8640U, 0x2U, 0x400E842CU #define IOMUXC_GPIO_DISP_B1_01_XBAR1_INOUT27 0x400E81E8U, 0x4U, 0x400E86F4U, 0x1U, 0x400E842CU #define IOMUXC_GPIO_DISP_B1_01_GPIO_MUX4_IO22 0x400E81E8U, 0x5U, 0, 0, 0x400E842CU -#define IOMUXC_GPIO_DISP_B1_01_SDIO_SLV_CLK 0x400E81E8U, 0x6U, 0x400E8684U, 0x1U, 0x400E842CU #define IOMUXC_GPIO_DISP_B1_01_ENET_QOS_RX_CLK 0x400E81E8U, 0x8U, 0, 0, 0x400E842CU #define IOMUXC_GPIO_DISP_B1_01_ENET_QOS_RX_ER 0x400E81E8U, 0x9U, 0x400E84FCU, 0x0U, 0x400E842CU #define IOMUXC_GPIO_DISP_B1_01_GPIO10_IO22 0x400E81E8U, 0xAU, 0, 0, 0x400E842CU @@ -1136,7 +1318,6 @@ #define IOMUXC_GPIO_DISP_B1_02_TMR1_TIMER2 0x400E81ECU, 0x3U, 0x400E8644U, 0x1U, 0x400E8430U #define IOMUXC_GPIO_DISP_B1_02_XBAR1_INOUT28 0x400E81ECU, 0x4U, 0x400E86F8U, 0x1U, 0x400E8430U #define IOMUXC_GPIO_DISP_B1_02_GPIO_MUX4_IO23 0x400E81ECU, 0x5U, 0, 0, 0x400E8430U -#define IOMUXC_GPIO_DISP_B1_02_SDIO_SLV_DATA0 0x400E81ECU, 0x6U, 0x400E868CU, 0x1U, 0x400E8430U #define IOMUXC_GPIO_DISP_B1_02_ENET_QOS_RX_DATA00 0x400E81ECU, 0x8U, 0x400E84F0U, 0x0U, 0x400E8430U #define IOMUXC_GPIO_DISP_B1_02_LPUART1_TXD 0x400E81ECU, 0x9U, 0x400E8620U, 0x1U, 0x400E8430U @@ -1146,7 +1327,6 @@ #define IOMUXC_GPIO_DISP_B1_03_TMR2_TIMER0 0x400E81F0U, 0x3U, 0x400E8648U, 0x2U, 0x400E8434U #define IOMUXC_GPIO_DISP_B1_03_XBAR1_INOUT29 0x400E81F0U, 0x4U, 0x400E86FCU, 0x1U, 0x400E8434U #define IOMUXC_GPIO_DISP_B1_03_GPIO_MUX4_IO24 0x400E81F0U, 0x5U, 0, 0, 0x400E8434U -#define IOMUXC_GPIO_DISP_B1_03_SDIO_SLV_DATA1 0x400E81F0U, 0x6U, 0x400E8690U, 0x1U, 0x400E8434U #define IOMUXC_GPIO_DISP_B1_03_ENET_QOS_RX_DATA01 0x400E81F0U, 0x8U, 0x400E84F4U, 0x0U, 0x400E8434U #define IOMUXC_GPIO_DISP_B1_03_LPUART1_RXD 0x400E81F0U, 0x9U, 0x400E861CU, 0x1U, 0x400E8434U #define IOMUXC_GPIO_DISP_B1_03_GPIO10_IO24 0x400E81F0U, 0xAU, 0, 0, 0x400E8434U @@ -1157,7 +1337,6 @@ #define IOMUXC_GPIO_DISP_B1_04_TMR2_TIMER1 0x400E81F4U, 0x3U, 0x400E864CU, 0x2U, 0x400E8438U #define IOMUXC_GPIO_DISP_B1_04_XBAR1_INOUT30 0x400E81F4U, 0x4U, 0x400E8700U, 0x1U, 0x400E8438U #define IOMUXC_GPIO_DISP_B1_04_GPIO_MUX4_IO25 0x400E81F4U, 0x5U, 0, 0, 0x400E8438U -#define IOMUXC_GPIO_DISP_B1_04_SDIO_SLV_DATA2 0x400E81F4U, 0x6U, 0x400E8694U, 0x1U, 0x400E8438U #define IOMUXC_GPIO_DISP_B1_04_ENET_QOS_RX_DATA02 0x400E81F4U, 0x8U, 0, 0, 0x400E8438U #define IOMUXC_GPIO_DISP_B1_04_LPSPI3_SCK 0x400E81F4U, 0x9U, 0x400E8600U, 0x1U, 0x400E8438U #define IOMUXC_GPIO_DISP_B1_04_GPIO10_IO25 0x400E81F4U, 0xAU, 0, 0, 0x400E8438U @@ -1169,7 +1348,6 @@ #define IOMUXC_GPIO_DISP_B1_05_TMR2_TIMER2 0x400E81F8U, 0x3U, 0x400E8650U, 0x1U, 0x400E843CU #define IOMUXC_GPIO_DISP_B1_05_XBAR1_INOUT31 0x400E81F8U, 0x4U, 0x400E8704U, 0x1U, 0x400E843CU #define IOMUXC_GPIO_DISP_B1_05_GPIO_MUX4_IO26 0x400E81F8U, 0x5U, 0, 0, 0x400E843CU -#define IOMUXC_GPIO_DISP_B1_05_SDIO_SLV_DATA3 0x400E81F8U, 0x6U, 0x400E8698U, 0x1U, 0x400E843CU #define IOMUXC_GPIO_DISP_B1_05_ENET_QOS_RX_DATA03 0x400E81F8U, 0x8U, 0, 0, 0x400E843CU #define IOMUXC_GPIO_DISP_B1_05_LPSPI3_SIN 0x400E81F8U, 0x9U, 0x400E8604U, 0x1U, 0x400E843CU @@ -1230,13 +1408,13 @@ #define IOMUXC_GPIO_DISP_B1_11_VIDEO_MUX_LCDIF_DATA07 0x400E8210U, 0x0U, 0, 0, 0x400E8454U #define IOMUXC_GPIO_DISP_B1_11_ENET_1G_TX_CLK_IO 0x400E8210U, 0x1U, 0x400E84E8U, 0x2U, 0x400E8454U -#define IOMUXC_GPIO_DISP_B1_11_ENET_1G_REF_CLK1 0x400E8210U, 0x2U, 0x400E84C4U, 0x2U, 0x400E8454U +#define IOMUXC_GPIO_DISP_B1_11_ENET_1G_REF_CLK 0x400E8210U, 0x2U, 0x400E84C4U, 0x2U, 0x400E8454U #define IOMUXC_GPIO_DISP_B1_11_TMR4_TIMER2 0x400E8210U, 0x3U, 0x400E8668U, 0x1U, 0x400E8454U #define IOMUXC_GPIO_DISP_B1_11_XBAR1_INOUT37 0x400E8210U, 0x4U, 0, 0, 0x400E8454U #define IOMUXC_GPIO_DISP_B1_11_GPIO_MUX5_IO00 0x400E8210U, 0x5U, 0, 0, 0x400E8454U #define IOMUXC_GPIO_DISP_B1_11_SRC_BT_CFG05 0x400E8210U, 0x6U, 0, 0, 0x400E8454U #define IOMUXC_GPIO_DISP_B1_11_ENET_QOS_TX_CLK 0x400E8210U, 0x8U, 0x400E84A4U, 0x0U, 0x400E8454U -#define IOMUXC_GPIO_DISP_B1_11_ENET_QOS_REF_CLK1 0x400E8210U, 0x9U, 0x400E84A0U, 0x2U, 0x400E8454U +#define IOMUXC_GPIO_DISP_B1_11_ENET_QOS_REF_CLK 0x400E8210U, 0x9U, 0x400E84A0U, 0x2U, 0x400E8454U #define IOMUXC_GPIO_DISP_B1_11_GPIO11_IO00 0x400E8210U, 0xAU, 0, 0, 0x400E8454U #define IOMUXC_GPIO_DISP_B2_00_GPIO11_IO01 0x400E8214U, 0xAU, 0, 0, 0x400E8458U @@ -1264,6 +1442,7 @@ #define IOMUXC_GPIO_DISP_B2_02_VIDEO_MUX_LCDIF_DATA10 0x400E821CU, 0x0U, 0, 0, 0x400E8460U #define IOMUXC_GPIO_DISP_B2_02_ENET_TX_DATA00 0x400E821CU, 0x1U, 0, 0, 0x400E8460U #define IOMUXC_GPIO_DISP_B2_02_PIT1_TRIGGER3 0x400E821CU, 0x2U, 0, 0, 0x400E8460U +#define IOMUXC_GPIO_DISP_B2_02_ARM_TRACE00 0x400E821CU, 0x3U, 0, 0, 0x400E8460U #define IOMUXC_GPIO_DISP_B2_02_SAI1_TX_DATA01 0x400E821CU, 0x4U, 0, 0, 0x400E8460U #define IOMUXC_GPIO_DISP_B2_02_GPIO_MUX5_IO03 0x400E821CU, 0x5U, 0, 0, 0x400E8460U #define IOMUXC_GPIO_DISP_B2_02_SRC_BT_CFG08 0x400E821CU, 0x6U, 0, 0, 0x400E8460U @@ -1273,6 +1452,7 @@ #define IOMUXC_GPIO_DISP_B2_03_VIDEO_MUX_LCDIF_DATA11 0x400E8220U, 0x0U, 0, 0, 0x400E8464U #define IOMUXC_GPIO_DISP_B2_03_ENET_TX_DATA01 0x400E8220U, 0x1U, 0, 0, 0x400E8464U #define IOMUXC_GPIO_DISP_B2_03_PIT1_TRIGGER2 0x400E8220U, 0x2U, 0, 0, 0x400E8464U +#define IOMUXC_GPIO_DISP_B2_03_ARM_TRACE01 0x400E8220U, 0x3U, 0, 0, 0x400E8464U #define IOMUXC_GPIO_DISP_B2_03_SAI1_MCLK 0x400E8220U, 0x4U, 0x400E866CU, 0x1U, 0x400E8464U #define IOMUXC_GPIO_DISP_B2_03_GPIO_MUX5_IO04 0x400E8220U, 0x5U, 0, 0, 0x400E8464U #define IOMUXC_GPIO_DISP_B2_03_SRC_BT_CFG09 0x400E8220U, 0x6U, 0, 0, 0x400E8464U @@ -1281,6 +1461,7 @@ #define IOMUXC_GPIO_DISP_B2_04_VIDEO_MUX_LCDIF_DATA12 0x400E8224U, 0x0U, 0, 0, 0x400E8468U #define IOMUXC_GPIO_DISP_B2_04_ENET_TX_EN 0x400E8224U, 0x1U, 0, 0, 0x400E8468U #define IOMUXC_GPIO_DISP_B2_04_PIT1_TRIGGER1 0x400E8224U, 0x2U, 0, 0, 0x400E8468U +#define IOMUXC_GPIO_DISP_B2_04_ARM_TRACE02 0x400E8224U, 0x3U, 0, 0, 0x400E8468U #define IOMUXC_GPIO_DISP_B2_04_SAI1_RX_SYNC 0x400E8224U, 0x4U, 0x400E8678U, 0x1U, 0x400E8468U #define IOMUXC_GPIO_DISP_B2_04_GPIO_MUX5_IO05 0x400E8224U, 0x5U, 0, 0, 0x400E8468U #define IOMUXC_GPIO_DISP_B2_04_SRC_BT_CFG10 0x400E8224U, 0x6U, 0, 0, 0x400E8468U @@ -1290,7 +1471,8 @@ #define IOMUXC_GPIO_DISP_B2_05_GPIO11_IO06 0x400E8228U, 0xAU, 0, 0, 0x400E846CU #define IOMUXC_GPIO_DISP_B2_05_VIDEO_MUX_LCDIF_DATA13 0x400E8228U, 0x0U, 0, 0, 0x400E846CU #define IOMUXC_GPIO_DISP_B2_05_ENET_TX_CLK 0x400E8228U, 0x1U, 0x400E84C0U, 0x1U, 0x400E846CU -#define IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK1 0x400E8228U, 0x2U, 0x400E84A8U, 0x1U, 0x400E846CU +#define IOMUXC_GPIO_DISP_B2_05_ENET_REF_CLK 0x400E8228U, 0x2U, 0x400E84A8U, 0x1U, 0x400E846CU +#define IOMUXC_GPIO_DISP_B2_05_ARM_TRACE03 0x400E8228U, 0x3U, 0, 0, 0x400E846CU #define IOMUXC_GPIO_DISP_B2_05_SAI1_RX_BCLK 0x400E8228U, 0x4U, 0x400E8670U, 0x1U, 0x400E846CU #define IOMUXC_GPIO_DISP_B2_05_GPIO_MUX5_IO06 0x400E8228U, 0x5U, 0, 0, 0x400E846CU #define IOMUXC_GPIO_DISP_B2_05_SRC_BT_CFG11 0x400E8228U, 0x6U, 0, 0, 0x400E846CU @@ -1300,6 +1482,7 @@ #define IOMUXC_GPIO_DISP_B2_06_VIDEO_MUX_LCDIF_DATA14 0x400E822CU, 0x0U, 0, 0, 0x400E8470U #define IOMUXC_GPIO_DISP_B2_06_ENET_RX_DATA00 0x400E822CU, 0x1U, 0x400E84B0U, 0x1U, 0x400E8470U #define IOMUXC_GPIO_DISP_B2_06_LPUART7_TXD 0x400E822CU, 0x2U, 0x400E8630U, 0x1U, 0x400E8470U +#define IOMUXC_GPIO_DISP_B2_06_ARM_TRACE_CLK 0x400E822CU, 0x3U, 0, 0, 0x400E8470U #define IOMUXC_GPIO_DISP_B2_06_SAI1_RX_DATA00 0x400E822CU, 0x4U, 0x400E8674U, 0x1U, 0x400E8470U #define IOMUXC_GPIO_DISP_B2_06_GPIO_MUX5_IO07 0x400E822CU, 0x5U, 0, 0, 0x400E8470U #define IOMUXC_GPIO_DISP_B2_06_ENET_QOS_RX_DATA00 0x400E822CU, 0x8U, 0x400E84F0U, 0x1U, 0x400E8470U @@ -1307,13 +1490,13 @@ #define IOMUXC_GPIO_DISP_B2_07_VIDEO_MUX_LCDIF_DATA15 0x400E8230U, 0x0U, 0, 0, 0x400E8474U #define IOMUXC_GPIO_DISP_B2_07_ENET_RX_DATA01 0x400E8230U, 0x1U, 0x400E84B4U, 0x1U, 0x400E8474U #define IOMUXC_GPIO_DISP_B2_07_LPUART7_RXD 0x400E8230U, 0x2U, 0x400E862CU, 0x1U, 0x400E8474U +#define IOMUXC_GPIO_DISP_B2_07_ARM_TRACE_SWO 0x400E8230U, 0x3U, 0, 0, 0x400E8474U #define IOMUXC_GPIO_DISP_B2_07_SAI1_TX_DATA00 0x400E8230U, 0x4U, 0, 0, 0x400E8474U #define IOMUXC_GPIO_DISP_B2_07_GPIO_MUX5_IO08 0x400E8230U, 0x5U, 0, 0, 0x400E8474U #define IOMUXC_GPIO_DISP_B2_07_ENET_QOS_RX_DATA01 0x400E8230U, 0x8U, 0x400E84F4U, 0x1U, 0x400E8474U #define IOMUXC_GPIO_DISP_B2_07_GPIO11_IO08 0x400E8230U, 0xAU, 0, 0, 0x400E8474U #define IOMUXC_GPIO_DISP_B2_08_GPIO11_IO09 0x400E8234U, 0xAU, 0, 0, 0x400E8478U -#define IOMUXC_GPIO_DISP_B2_08_SDIO_SLV_DATA0 0x400E8234U, 0xBU, 0x400E868CU, 0x2U, 0x400E8478U #define IOMUXC_GPIO_DISP_B2_08_VIDEO_MUX_LCDIF_DATA16 0x400E8234U, 0x0U, 0, 0, 0x400E8478U #define IOMUXC_GPIO_DISP_B2_08_ENET_RX_EN 0x400E8234U, 0x1U, 0x400E84B8U, 0x1U, 0x400E8478U #define IOMUXC_GPIO_DISP_B2_08_LPUART8_TXD 0x400E8234U, 0x2U, 0x400E8638U, 0x1U, 0x400E8478U @@ -1324,7 +1507,6 @@ #define IOMUXC_GPIO_DISP_B2_08_LPUART1_TXD 0x400E8234U, 0x9U, 0x400E8620U, 0x2U, 0x400E8478U #define IOMUXC_GPIO_DISP_B2_09_GPIO11_IO10 0x400E8238U, 0xAU, 0, 0, 0x400E847CU -#define IOMUXC_GPIO_DISP_B2_09_SDIO_SLV_DATA1 0x400E8238U, 0xBU, 0x400E8690U, 0x2U, 0x400E847CU #define IOMUXC_GPIO_DISP_B2_09_VIDEO_MUX_LCDIF_DATA17 0x400E8238U, 0x0U, 0, 0, 0x400E847CU #define IOMUXC_GPIO_DISP_B2_09_ENET_RX_ER 0x400E8238U, 0x1U, 0x400E84BCU, 0x1U, 0x400E847CU #define IOMUXC_GPIO_DISP_B2_09_LPUART8_RXD 0x400E8238U, 0x2U, 0x400E8634U, 0x1U, 0x400E847CU @@ -1335,11 +1517,10 @@ #define IOMUXC_GPIO_DISP_B2_09_LPUART1_RXD 0x400E8238U, 0x9U, 0x400E861CU, 0x2U, 0x400E847CU #define IOMUXC_GPIO_DISP_B2_10_GPIO11_IO11 0x400E823CU, 0xAU, 0, 0, 0x400E8480U -#define IOMUXC_GPIO_DISP_B2_10_SDIO_SLV_DATA2 0x400E823CU, 0xBU, 0x400E8694U, 0x2U, 0x400E8480U #define IOMUXC_GPIO_DISP_B2_10_VIDEO_MUX_LCDIF_DATA18 0x400E823CU, 0x0U, 0, 0, 0x400E8480U #define IOMUXC_GPIO_DISP_B2_10_EMVSIM2_IO 0x400E823CU, 0x1U, 0x400E86A8U, 0x1U, 0x400E8480U #define IOMUXC_GPIO_DISP_B2_10_LPUART2_TXD 0x400E823CU, 0x2U, 0, 0, 0x400E8480U -#define IOMUXC_GPIO_DISP_B2_10_WDOG2_RST_B_DEB 0x400E823CU, 0x3U, 0, 0, 0x400E8480U +#define IOMUXC_GPIO_DISP_B2_10_WDOG2_RESET_B_DEB 0x400E823CU, 0x3U, 0, 0, 0x400E8480U #define IOMUXC_GPIO_DISP_B2_10_XBAR1_INOUT38 0x400E823CU, 0x4U, 0, 0, 0x400E8480U #define IOMUXC_GPIO_DISP_B2_10_GPIO_MUX5_IO11 0x400E823CU, 0x5U, 0, 0, 0x400E8480U #define IOMUXC_GPIO_DISP_B2_10_LPI2C3_SCL 0x400E823CU, 0x6U, 0x400E85BCU, 0x1U, 0x400E8480U @@ -1349,17 +1530,15 @@ #define IOMUXC_GPIO_DISP_B2_11_VIDEO_MUX_LCDIF_DATA19 0x400E8240U, 0x0U, 0, 0, 0x400E8484U #define IOMUXC_GPIO_DISP_B2_11_EMVSIM2_CLK 0x400E8240U, 0x1U, 0, 0, 0x400E8484U #define IOMUXC_GPIO_DISP_B2_11_LPUART2_RXD 0x400E8240U, 0x2U, 0, 0, 0x400E8484U -#define IOMUXC_GPIO_DISP_B2_11_WDOG1_RST_B_DEB 0x400E8240U, 0x3U, 0, 0, 0x400E8484U +#define IOMUXC_GPIO_DISP_B2_11_WDOG1_RESET_B_DEB 0x400E8240U, 0x3U, 0, 0, 0x400E8484U #define IOMUXC_GPIO_DISP_B2_11_XBAR1_INOUT39 0x400E8240U, 0x4U, 0, 0, 0x400E8484U #define IOMUXC_GPIO_DISP_B2_11_GPIO_MUX5_IO12 0x400E8240U, 0x5U, 0, 0, 0x400E8484U #define IOMUXC_GPIO_DISP_B2_11_LPI2C3_SDA 0x400E8240U, 0x6U, 0x400E85C0U, 0x1U, 0x400E8484U #define IOMUXC_GPIO_DISP_B2_11_ENET_QOS_CRS 0x400E8240U, 0x8U, 0, 0, 0x400E8484U #define IOMUXC_GPIO_DISP_B2_11_SPDIF_OUT 0x400E8240U, 0x9U, 0, 0, 0x400E8484U #define IOMUXC_GPIO_DISP_B2_11_GPIO11_IO12 0x400E8240U, 0xAU, 0, 0, 0x400E8484U -#define IOMUXC_GPIO_DISP_B2_11_SDIO_SLV_DATA3 0x400E8240U, 0xBU, 0x400E8698U, 0x2U, 0x400E8484U #define IOMUXC_GPIO_DISP_B2_12_GPIO11_IO13 0x400E8244U, 0xAU, 0, 0, 0x400E8488U -#define IOMUXC_GPIO_DISP_B2_12_SDIO_SLV_CMD 0x400E8244U, 0xBU, 0x400E8688U, 0x2U, 0x400E8488U #define IOMUXC_GPIO_DISP_B2_12_VIDEO_MUX_LCDIF_DATA20 0x400E8244U, 0x0U, 0, 0, 0x400E8488U #define IOMUXC_GPIO_DISP_B2_12_EMVSIM2_RST 0x400E8244U, 0x1U, 0, 0, 0x400E8488U #define IOMUXC_GPIO_DISP_B2_12_FLEXCAN1_TX 0x400E8244U, 0x2U, 0, 0, 0x400E8488U @@ -1371,12 +1550,11 @@ #define IOMUXC_GPIO_DISP_B2_12_LPSPI4_SCK 0x400E8244U, 0x9U, 0x400E8610U, 0x1U, 0x400E8488U #define IOMUXC_GPIO_DISP_B2_13_GPIO11_IO14 0x400E8248U, 0xAU, 0, 0, 0x400E848CU -#define IOMUXC_GPIO_DISP_B2_13_SDIO_SLV_CLK 0x400E8248U, 0xBU, 0x400E8684U, 0x2U, 0x400E848CU #define IOMUXC_GPIO_DISP_B2_13_VIDEO_MUX_LCDIF_DATA21 0x400E8248U, 0x0U, 0, 0, 0x400E848CU #define IOMUXC_GPIO_DISP_B2_13_EMVSIM2_SVEN 0x400E8248U, 0x1U, 0, 0, 0x400E848CU #define IOMUXC_GPIO_DISP_B2_13_FLEXCAN1_RX 0x400E8248U, 0x2U, 0x400E8498U, 0x1U, 0x400E848CU #define IOMUXC_GPIO_DISP_B2_13_LPUART2_RTS_B 0x400E8248U, 0x3U, 0, 0, 0x400E848CU -#define IOMUXC_GPIO_DISP_B2_13_ENET_REF_CLK1 0x400E8248U, 0x4U, 0x400E84A8U, 0x2U, 0x400E848CU +#define IOMUXC_GPIO_DISP_B2_13_ENET_REF_CLK 0x400E8248U, 0x4U, 0x400E84A8U, 0x2U, 0x400E848CU #define IOMUXC_GPIO_DISP_B2_13_GPIO_MUX5_IO14 0x400E8248U, 0x5U, 0, 0, 0x400E848CU #define IOMUXC_GPIO_DISP_B2_13_LPI2C4_SDA 0x400E8248U, 0x6U, 0x400E85C8U, 0x1U, 0x400E848CU #define IOMUXC_GPIO_DISP_B2_13_ENET_QOS_1588_EVENT0_OUT 0x400E8248U, 0x8U, 0, 0, 0x400E848CU @@ -1391,7 +1569,7 @@ #define IOMUXC_GPIO_DISP_B2_14_EMVSIM2_PD 0x400E824CU, 0x1U, 0x400E86ACU, 0x1U, 0x400E8490U #define IOMUXC_GPIO_DISP_B2_14_WDOG2_B 0x400E824CU, 0x2U, 0, 0, 0x400E8490U #define IOMUXC_GPIO_DISP_B2_14_VIDEO_MUX_EXT_DCIC1 0x400E824CU, 0x3U, 0, 0, 0x400E8490U -#define IOMUXC_GPIO_DISP_B2_14_ENET_1G_REF_CLK1 0x400E824CU, 0x4U, 0x400E84C4U, 0x3U, 0x400E8490U +#define IOMUXC_GPIO_DISP_B2_14_ENET_1G_REF_CLK 0x400E824CU, 0x4U, 0x400E84C4U, 0x3U, 0x400E8490U #define IOMUXC_GPIO_DISP_B2_15_VIDEO_MUX_LCDIF_DATA23 0x400E8250U, 0x0U, 0, 0, 0x400E8494U #define IOMUXC_GPIO_DISP_B2_15_EMVSIM2_POWER_FAIL 0x400E8250U, 0x1U, 0x400E86B0U, 0x1U, 0x400E8494U @@ -1404,196 +1582,6 @@ #define IOMUXC_GPIO_DISP_B2_15_LPSPI4_PCS0 0x400E8250U, 0x9U, 0x400E860CU, 0x1U, 0x400E8494U #define IOMUXC_GPIO_DISP_B2_15_GPIO11_IO16 0x400E8250U, 0xAU, 0, 0, 0x400E8494U -#define IOMUXC_WAKEUP_DIG_GPIO13_IO00 0x40C94000U, 0x5U, 0, 0, 0x40C94040U -#define IOMUXC_WAKEUP_DIG_NMI_GLUE_NMI 0x40C94000U, 0x7U, 0x40C080C4U, 0x1U, 0x40C94040U - -#define IOMUXC_PMIC_ON_REQ_DIG_SNVS_LP_PMIC_ON_REQ 0x40C94004U, 0x0U, 0, 0, 0x40C94044U -#define IOMUXC_PMIC_ON_REQ_DIG_GPIO13_IO01 0x40C94004U, 0x5U, 0, 0, 0x40C94044U - -#define IOMUXC_PMIC_STBY_REQ_DIG_CCM_PMIC_VSTBY_REQ 0x40C94008U, 0x0U, 0, 0, 0x40C94048U -#define IOMUXC_PMIC_STBY_REQ_DIG_GPIO13_IO02 0x40C94008U, 0x5U, 0, 0, 0x40C94048U - -#define IOMUXC_GPIO_SNVS_00_DIG_SNVS_TAMPER0 0x40C9400CU, 0x0U, 0, 0, 0x40C9404CU -#define IOMUXC_GPIO_SNVS_00_DIG_GPIO13_IO03 0x40C9400CU, 0x5U, 0, 0, 0x40C9404CU - -#define IOMUXC_GPIO_SNVS_01_DIG_SNVS_TAMPER1 0x40C94010U, 0x0U, 0, 0, 0x40C94050U -#define IOMUXC_GPIO_SNVS_01_DIG_GPIO13_IO04 0x40C94010U, 0x5U, 0, 0, 0x40C94050U - -#define IOMUXC_GPIO_SNVS_02_DIG_SNVS_TAMPER2 0x40C94014U, 0x0U, 0, 0, 0x40C94054U -#define IOMUXC_GPIO_SNVS_02_DIG_GPIO13_IO05 0x40C94014U, 0x5U, 0, 0, 0x40C94054U - -#define IOMUXC_GPIO_SNVS_03_DIG_SNVS_TAMPER3 0x40C94018U, 0x0U, 0, 0, 0x40C94058U -#define IOMUXC_GPIO_SNVS_03_DIG_GPIO13_IO06 0x40C94018U, 0x5U, 0, 0, 0x40C94058U - -#define IOMUXC_GPIO_SNVS_04_DIG_SNVS_TAMPER4 0x40C9401CU, 0x0U, 0, 0, 0x40C9405CU -#define IOMUXC_GPIO_SNVS_04_DIG_GPIO13_IO07 0x40C9401CU, 0x5U, 0, 0, 0x40C9405CU - -#define IOMUXC_GPIO_SNVS_05_DIG_SNVS_TAMPER5 0x40C94020U, 0x0U, 0, 0, 0x40C94060U -#define IOMUXC_GPIO_SNVS_05_DIG_GPIO13_IO08 0x40C94020U, 0x5U, 0, 0, 0x40C94060U - -#define IOMUXC_GPIO_SNVS_06_DIG_SNVS_TAMPER6 0x40C94024U, 0x0U, 0, 0, 0x40C94064U -#define IOMUXC_GPIO_SNVS_06_DIG_GPIO13_IO09 0x40C94024U, 0x5U, 0, 0, 0x40C94064U - -#define IOMUXC_GPIO_SNVS_07_DIG_SNVS_TAMPER7 0x40C94028U, 0x0U, 0, 0, 0x40C94068U -#define IOMUXC_GPIO_SNVS_07_DIG_GPIO13_IO10 0x40C94028U, 0x5U, 0, 0, 0x40C94068U - -#define IOMUXC_GPIO_SNVS_08_DIG_SNVS_TAMPER8 0x40C9402CU, 0x0U, 0, 0, 0x40C9406CU -#define IOMUXC_GPIO_SNVS_08_DIG_GPIO13_IO11 0x40C9402CU, 0x5U, 0, 0, 0x40C9406CU - -#define IOMUXC_GPIO_SNVS_09_DIG_SNVS_TAMPER9 0x40C94030U, 0x0U, 0, 0, 0x40C94070U -#define IOMUXC_GPIO_SNVS_09_DIG_GPIO13_IO12 0x40C94030U, 0x5U, 0, 0, 0x40C94070U - -#define IOMUXC_TEST_MODE_DIG 0, 0, 0, 0, 0x40C94034U - -#define IOMUXC_POR_B_DIG 0, 0, 0, 0, 0x40C94038U - -#define IOMUXC_ONOFF_DIG 0, 0, 0, 0, 0x40C9403CU - -#define IOMUXC_GPIO_LPSR_00_FLEXCAN3_TX 0x40C08000U, 0x0U, 0, 0, 0x40C08040U -#define IOMUXC_GPIO_LPSR_00_MIC_CLK 0x40C08000U, 0x1U, 0, 0, 0x40C08040U -#define IOMUXC_GPIO_LPSR_00_MQS_RIGHT 0x40C08000U, 0x2U, 0, 0, 0x40C08040U -#define IOMUXC_GPIO_LPSR_00_ARM_CM4_EVENTO 0x40C08000U, 0x3U, 0, 0, 0x40C08040U -#define IOMUXC_GPIO_LPSR_00_GPIO_MUX6_IO00 0x40C08000U, 0x5U, 0, 0, 0x40C08040U -#define IOMUXC_GPIO_LPSR_00_LPUART12_TXD 0x40C08000U, 0x6U, 0x40C080B0U, 0x0U, 0x40C08040U -#define IOMUXC_GPIO_LPSR_00_SAI4_MCLK 0x40C08000U, 0x7U, 0x40C080C8U, 0x0U, 0x40C08040U -#define IOMUXC_GPIO_LPSR_00_GPIO12_IO00 0x40C08000U, 0xAU, 0, 0, 0x40C08040U - -#define IOMUXC_GPIO_LPSR_01_FLEXCAN3_RX 0x40C08004U, 0x0U, 0x40C08080U, 0x0U, 0x40C08044U -#define IOMUXC_GPIO_LPSR_01_MIC_BITSTREAM0 0x40C08004U, 0x1U, 0x40C080B4U, 0x0U, 0x40C08044U -#define IOMUXC_GPIO_LPSR_01_MQS_LEFT 0x40C08004U, 0x2U, 0, 0, 0x40C08044U -#define IOMUXC_GPIO_LPSR_01_ARM_CM4_EVENTI 0x40C08004U, 0x3U, 0, 0, 0x40C08044U -#define IOMUXC_GPIO_LPSR_01_GPIO_MUX6_IO01 0x40C08004U, 0x5U, 0, 0, 0x40C08044U -#define IOMUXC_GPIO_LPSR_01_LPUART12_RXD 0x40C08004U, 0x6U, 0x40C080ACU, 0x0U, 0x40C08044U -#define IOMUXC_GPIO_LPSR_01_GPIO12_IO01 0x40C08004U, 0xAU, 0, 0, 0x40C08044U - -#define IOMUXC_GPIO_LPSR_02_GPIO12_IO02 0x40C08008U, 0xAU, 0, 0, 0x40C08048U -#define IOMUXC_GPIO_LPSR_02_SRC_BOOT_MODE00 0x40C08008U, 0x0U, 0, 0, 0x40C08048U -#define IOMUXC_GPIO_LPSR_02_LPSPI5_SCK 0x40C08008U, 0x1U, 0x40C08098U, 0x0U, 0x40C08048U -#define IOMUXC_GPIO_LPSR_02_SAI4_TX_DATA 0x40C08008U, 0x2U, 0, 0, 0x40C08048U -#define IOMUXC_GPIO_LPSR_02_MQS_RIGHT 0x40C08008U, 0x3U, 0, 0, 0x40C08048U -#define IOMUXC_GPIO_LPSR_02_GPIO_MUX6_IO02 0x40C08008U, 0x5U, 0, 0, 0x40C08048U - -#define IOMUXC_GPIO_LPSR_03_SRC_BOOT_MODE01 0x40C0800CU, 0x0U, 0, 0, 0x40C0804CU -#define IOMUXC_GPIO_LPSR_03_LPSPI5_PCS0 0x40C0800CU, 0x1U, 0x40C08094U, 0x0U, 0x40C0804CU -#define IOMUXC_GPIO_LPSR_03_SAI4_TX_SYNC 0x40C0800CU, 0x2U, 0x40C080DCU, 0x0U, 0x40C0804CU -#define IOMUXC_GPIO_LPSR_03_MQS_LEFT 0x40C0800CU, 0x3U, 0, 0, 0x40C0804CU -#define IOMUXC_GPIO_LPSR_03_GPIO_MUX6_IO03 0x40C0800CU, 0x5U, 0, 0, 0x40C0804CU -#define IOMUXC_GPIO_LPSR_03_GPIO12_IO03 0x40C0800CU, 0xAU, 0, 0, 0x40C0804CU - -#define IOMUXC_GPIO_LPSR_04_LPI2C5_SDA 0x40C08010U, 0x0U, 0x40C08088U, 0x0U, 0x40C08050U -#define IOMUXC_GPIO_LPSR_04_LPSPI5_SOUT 0x40C08010U, 0x1U, 0x40C080A0U, 0x0U, 0x40C08050U -#define IOMUXC_GPIO_LPSR_04_SAI4_TX_BCLK 0x40C08010U, 0x2U, 0x40C080D8U, 0x0U, 0x40C08050U -#define IOMUXC_GPIO_LPSR_04_LPUART12_RTS_B 0x40C08010U, 0x3U, 0, 0, 0x40C08050U -#define IOMUXC_GPIO_LPSR_04_GPIO_MUX6_IO04 0x40C08010U, 0x5U, 0, 0, 0x40C08050U -#define IOMUXC_GPIO_LPSR_04_LPUART11_TXD 0x40C08010U, 0x6U, 0x40C080A8U, 0x0U, 0x40C08050U -#define IOMUXC_GPIO_LPSR_04_GPIO12_IO04 0x40C08010U, 0xAU, 0, 0, 0x40C08050U - -#define IOMUXC_GPIO_LPSR_05_GPIO12_IO05 0x40C08014U, 0xAU, 0, 0, 0x40C08054U -#define IOMUXC_GPIO_LPSR_05_LPI2C5_SCL 0x40C08014U, 0x0U, 0x40C08084U, 0x0U, 0x40C08054U -#define IOMUXC_GPIO_LPSR_05_LPSPI5_SIN 0x40C08014U, 0x1U, 0x40C0809CU, 0x0U, 0x40C08054U -#define IOMUXC_GPIO_LPSR_05_SAI4_MCLK 0x40C08014U, 0x2U, 0x40C080C8U, 0x1U, 0x40C08054U -#define IOMUXC_GPIO_LPSR_05_LPUART12_CTS_B 0x40C08014U, 0x3U, 0, 0, 0x40C08054U -#define IOMUXC_GPIO_LPSR_05_GPIO_MUX6_IO05 0x40C08014U, 0x5U, 0, 0, 0x40C08054U -#define IOMUXC_GPIO_LPSR_05_LPUART11_RXD 0x40C08014U, 0x6U, 0x40C080A4U, 0x0U, 0x40C08054U -#define IOMUXC_GPIO_LPSR_05_NMI_GLUE_NMI 0x40C08014U, 0x7U, 0x40C080C4U, 0x0U, 0x40C08054U - -#define IOMUXC_GPIO_LPSR_06_LPI2C6_SDA 0x40C08018U, 0x0U, 0x40C08090U, 0x0U, 0x40C08058U -#define IOMUXC_GPIO_LPSR_06_SAI4_RX_DATA 0x40C08018U, 0x2U, 0x40C080D0U, 0x0U, 0x40C08058U -#define IOMUXC_GPIO_LPSR_06_LPUART12_TXD 0x40C08018U, 0x3U, 0x40C080B0U, 0x1U, 0x40C08058U -#define IOMUXC_GPIO_LPSR_06_LPSPI6_PCS3 0x40C08018U, 0x4U, 0, 0, 0x40C08058U -#define IOMUXC_GPIO_LPSR_06_GPIO_MUX6_IO06 0x40C08018U, 0x5U, 0, 0, 0x40C08058U -#define IOMUXC_GPIO_LPSR_06_FLEXCAN3_TX 0x40C08018U, 0x6U, 0, 0, 0x40C08058U -#define IOMUXC_GPIO_LPSR_06_PIT2_TRIGGER3 0x40C08018U, 0x7U, 0, 0, 0x40C08058U -#define IOMUXC_GPIO_LPSR_06_LPSPI5_PCS1 0x40C08018U, 0x8U, 0, 0, 0x40C08058U -#define IOMUXC_GPIO_LPSR_06_GPIO12_IO06 0x40C08018U, 0xAU, 0, 0, 0x40C08058U - -#define IOMUXC_GPIO_LPSR_07_LPI2C6_SCL 0x40C0801CU, 0x0U, 0x40C0808CU, 0x0U, 0x40C0805CU -#define IOMUXC_GPIO_LPSR_07_SAI4_RX_BCLK 0x40C0801CU, 0x2U, 0x40C080CCU, 0x0U, 0x40C0805CU -#define IOMUXC_GPIO_LPSR_07_LPUART12_RXD 0x40C0801CU, 0x3U, 0x40C080ACU, 0x1U, 0x40C0805CU -#define IOMUXC_GPIO_LPSR_07_LPSPI6_PCS2 0x40C0801CU, 0x4U, 0, 0, 0x40C0805CU -#define IOMUXC_GPIO_LPSR_07_GPIO_MUX6_IO07 0x40C0801CU, 0x5U, 0, 0, 0x40C0805CU -#define IOMUXC_GPIO_LPSR_07_FLEXCAN3_RX 0x40C0801CU, 0x6U, 0x40C08080U, 0x1U, 0x40C0805CU -#define IOMUXC_GPIO_LPSR_07_PIT2_TRIGGER2 0x40C0801CU, 0x7U, 0, 0, 0x40C0805CU -#define IOMUXC_GPIO_LPSR_07_LPSPI5_PCS2 0x40C0801CU, 0x8U, 0, 0, 0x40C0805CU -#define IOMUXC_GPIO_LPSR_07_GPIO12_IO07 0x40C0801CU, 0xAU, 0, 0, 0x40C0805CU - -#define IOMUXC_GPIO_LPSR_08_GPIO12_IO08 0x40C08020U, 0xAU, 0, 0, 0x40C08060U -#define IOMUXC_GPIO_LPSR_08_LPUART11_TXD 0x40C08020U, 0x0U, 0x40C080A8U, 0x1U, 0x40C08060U -#define IOMUXC_GPIO_LPSR_08_FLEXCAN3_TX 0x40C08020U, 0x1U, 0, 0, 0x40C08060U -#define IOMUXC_GPIO_LPSR_08_SAI4_RX_SYNC 0x40C08020U, 0x2U, 0x40C080D4U, 0x0U, 0x40C08060U -#define IOMUXC_GPIO_LPSR_08_MIC_CLK 0x40C08020U, 0x3U, 0, 0, 0x40C08060U -#define IOMUXC_GPIO_LPSR_08_LPSPI6_PCS1 0x40C08020U, 0x4U, 0, 0, 0x40C08060U -#define IOMUXC_GPIO_LPSR_08_GPIO_MUX6_IO08 0x40C08020U, 0x5U, 0, 0, 0x40C08060U -#define IOMUXC_GPIO_LPSR_08_LPI2C5_SDA 0x40C08020U, 0x6U, 0x40C08088U, 0x1U, 0x40C08060U -#define IOMUXC_GPIO_LPSR_08_PIT2_TRIGGER1 0x40C08020U, 0x7U, 0, 0, 0x40C08060U -#define IOMUXC_GPIO_LPSR_08_LPSPI5_PCS3 0x40C08020U, 0x8U, 0, 0, 0x40C08060U - -#define IOMUXC_GPIO_LPSR_09_GPIO12_IO09 0x40C08024U, 0xAU, 0, 0, 0x40C08064U -#define IOMUXC_GPIO_LPSR_09_LPUART11_RXD 0x40C08024U, 0x0U, 0x40C080A4U, 0x1U, 0x40C08064U -#define IOMUXC_GPIO_LPSR_09_FLEXCAN3_RX 0x40C08024U, 0x1U, 0x40C08080U, 0x2U, 0x40C08064U -#define IOMUXC_GPIO_LPSR_09_PIT2_TRIGGER0 0x40C08024U, 0x2U, 0, 0, 0x40C08064U -#define IOMUXC_GPIO_LPSR_09_MIC_BITSTREAM0 0x40C08024U, 0x3U, 0x40C080B4U, 0x1U, 0x40C08064U -#define IOMUXC_GPIO_LPSR_09_LPSPI6_PCS0 0x40C08024U, 0x4U, 0, 0, 0x40C08064U -#define IOMUXC_GPIO_LPSR_09_GPIO_MUX6_IO09 0x40C08024U, 0x5U, 0, 0, 0x40C08064U -#define IOMUXC_GPIO_LPSR_09_LPI2C5_SCL 0x40C08024U, 0x6U, 0x40C08084U, 0x1U, 0x40C08064U -#define IOMUXC_GPIO_LPSR_09_SAI4_TX_DATA 0x40C08024U, 0x7U, 0, 0, 0x40C08064U - -#define IOMUXC_GPIO_LPSR_10_GPIO12_IO10 0x40C08028U, 0xAU, 0, 0, 0x40C08068U -#define IOMUXC_GPIO_LPSR_10_JTAG_MUX_TRSTB 0x40C08028U, 0x0U, 0, 0, 0x40C08068U -#define IOMUXC_GPIO_LPSR_10_LPUART11_CTS_B 0x40C08028U, 0x1U, 0, 0, 0x40C08068U -#define IOMUXC_GPIO_LPSR_10_LPI2C6_SDA 0x40C08028U, 0x2U, 0x40C08090U, 0x1U, 0x40C08068U -#define IOMUXC_GPIO_LPSR_10_MIC_BITSTREAM1 0x40C08028U, 0x3U, 0x40C080B8U, 0x0U, 0x40C08068U -#define IOMUXC_GPIO_LPSR_10_LPSPI6_SCK 0x40C08028U, 0x4U, 0, 0, 0x40C08068U -#define IOMUXC_GPIO_LPSR_10_GPIO_MUX6_IO10 0x40C08028U, 0x5U, 0, 0, 0x40C08068U -#define IOMUXC_GPIO_LPSR_10_LPI2C5_SCLS 0x40C08028U, 0x6U, 0, 0, 0x40C08068U -#define IOMUXC_GPIO_LPSR_10_SAI4_TX_SYNC 0x40C08028U, 0x7U, 0x40C080DCU, 0x1U, 0x40C08068U -#define IOMUXC_GPIO_LPSR_10_LPUART12_TXD 0x40C08028U, 0x8U, 0x40C080B0U, 0x2U, 0x40C08068U - -#define IOMUXC_GPIO_LPSR_11_JTAG_MUX_TDO 0x40C0802CU, 0x0U, 0, 0, 0x40C0806CU -#define IOMUXC_GPIO_LPSR_11_LPUART11_RTS_B 0x40C0802CU, 0x1U, 0, 0, 0x40C0806CU -#define IOMUXC_GPIO_LPSR_11_LPI2C6_SCL 0x40C0802CU, 0x2U, 0x40C0808CU, 0x1U, 0x40C0806CU -#define IOMUXC_GPIO_LPSR_11_MIC_BITSTREAM2 0x40C0802CU, 0x3U, 0x40C080BCU, 0x0U, 0x40C0806CU -#define IOMUXC_GPIO_LPSR_11_LPSPI6_SOUT 0x40C0802CU, 0x4U, 0, 0, 0x40C0806CU -#define IOMUXC_GPIO_LPSR_11_GPIO_MUX6_IO11 0x40C0802CU, 0x5U, 0, 0, 0x40C0806CU -#define IOMUXC_GPIO_LPSR_11_LPI2C5_SDAS 0x40C0802CU, 0x6U, 0, 0, 0x40C0806CU -#define IOMUXC_GPIO_LPSR_11_ARM_TRACE_SWO 0x40C0802CU, 0x7U, 0, 0, 0x40C0806CU -#define IOMUXC_GPIO_LPSR_11_LPUART12_RXD 0x40C0802CU, 0x8U, 0x40C080ACU, 0x2U, 0x40C0806CU -#define IOMUXC_GPIO_LPSR_11_GPIO12_IO11 0x40C0802CU, 0xAU, 0, 0, 0x40C0806CU - -#define IOMUXC_GPIO_LPSR_12_GPIO12_IO12 0x40C08030U, 0xAU, 0, 0, 0x40C08070U -#define IOMUXC_GPIO_LPSR_12_JTAG_MUX_TDI 0x40C08030U, 0x0U, 0, 0, 0x40C08070U -#define IOMUXC_GPIO_LPSR_12_PIT2_TRIGGER0 0x40C08030U, 0x1U, 0, 0, 0x40C08070U -#define IOMUXC_GPIO_LPSR_12_MIC_BITSTREAM3 0x40C08030U, 0x3U, 0x40C080C0U, 0x0U, 0x40C08070U -#define IOMUXC_GPIO_LPSR_12_LPSPI6_SIN 0x40C08030U, 0x4U, 0, 0, 0x40C08070U -#define IOMUXC_GPIO_LPSR_12_GPIO_MUX6_IO12 0x40C08030U, 0x5U, 0, 0, 0x40C08070U -#define IOMUXC_GPIO_LPSR_12_LPI2C5_HREQ 0x40C08030U, 0x6U, 0, 0, 0x40C08070U -#define IOMUXC_GPIO_LPSR_12_SAI4_TX_BCLK 0x40C08030U, 0x7U, 0x40C080D8U, 0x1U, 0x40C08070U -#define IOMUXC_GPIO_LPSR_12_LPSPI5_SCK 0x40C08030U, 0x8U, 0x40C08098U, 0x1U, 0x40C08070U - -#define IOMUXC_GPIO_LPSR_13_GPIO12_IO13 0x40C08034U, 0xAU, 0, 0, 0x40C08074U -#define IOMUXC_GPIO_LPSR_13_JTAG_MUX_MOD 0x40C08034U, 0x0U, 0, 0, 0x40C08074U -#define IOMUXC_GPIO_LPSR_13_MIC_BITSTREAM1 0x40C08034U, 0x1U, 0x40C080B8U, 0x1U, 0x40C08074U -#define IOMUXC_GPIO_LPSR_13_PIT2_TRIGGER1 0x40C08034U, 0x2U, 0, 0, 0x40C08074U -#define IOMUXC_GPIO_LPSR_13_GPIO_MUX6_IO13 0x40C08034U, 0x5U, 0, 0, 0x40C08074U -#define IOMUXC_GPIO_LPSR_13_SAI4_RX_DATA 0x40C08034U, 0x7U, 0x40C080D0U, 0x1U, 0x40C08074U -#define IOMUXC_GPIO_LPSR_13_LPSPI5_PCS0 0x40C08034U, 0x8U, 0x40C08094U, 0x1U, 0x40C08074U - -#define IOMUXC_GPIO_LPSR_14_JTAG_MUX_TCK 0x40C08038U, 0x0U, 0, 0, 0x40C08078U -#define IOMUXC_GPIO_LPSR_14_MIC_BITSTREAM2 0x40C08038U, 0x1U, 0x40C080BCU, 0x1U, 0x40C08078U -#define IOMUXC_GPIO_LPSR_14_PIT2_TRIGGER2 0x40C08038U, 0x2U, 0, 0, 0x40C08078U -#define IOMUXC_GPIO_LPSR_14_GPIO_MUX6_IO14 0x40C08038U, 0x5U, 0, 0, 0x40C08078U -#define IOMUXC_GPIO_LPSR_14_SAI4_RX_BCLK 0x40C08038U, 0x7U, 0x40C080CCU, 0x1U, 0x40C08078U -#define IOMUXC_GPIO_LPSR_14_LPSPI5_SOUT 0x40C08038U, 0x8U, 0x40C080A0U, 0x1U, 0x40C08078U -#define IOMUXC_GPIO_LPSR_14_GPIO12_IO14 0x40C08038U, 0xAU, 0, 0, 0x40C08078U - -#define IOMUXC_GPIO_LPSR_15_GPIO12_IO15 0x40C0803CU, 0xAU, 0, 0, 0x40C0807CU -#define IOMUXC_GPIO_LPSR_15_JTAG_MUX_TMS 0x40C0803CU, 0x0U, 0, 0, 0x40C0807CU -#define IOMUXC_GPIO_LPSR_15_MIC_BITSTREAM3 0x40C0803CU, 0x1U, 0x40C080C0U, 0x1U, 0x40C0807CU -#define IOMUXC_GPIO_LPSR_15_PIT2_TRIGGER3 0x40C0803CU, 0x2U, 0, 0, 0x40C0807CU -#define IOMUXC_GPIO_LPSR_15_GPIO_MUX6_IO15 0x40C0803CU, 0x5U, 0, 0, 0x40C0807CU -#define IOMUXC_GPIO_LPSR_15_SAI4_RX_SYNC 0x40C0803CU, 0x7U, 0x40C080D4U, 0x1U, 0x40C0807CU -#define IOMUXC_GPIO_LPSR_15_LPSPI5_SIN 0x40C0803CU, 0x8U, 0x40C0809CU, 0x1U, 0x40C0807CU - /*@}*/ #define IOMUXC_GPR_SAIMCLK_LOWBITMASK (0x7U) @@ -1652,7 +1640,7 @@ static inline void IOMUXC_SetPinMux(uint32_t muxRegister, *((volatile uint32_t *)muxRegister) = IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); - if (inputRegister) + if (inputRegister != 0UL) { *((volatile uint32_t *)inputRegister) = inputDaisy; } @@ -1681,7 +1669,7 @@ static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, uint32_t configRegister, uint32_t configValue) { - if (configRegister) + if (configRegister != 0UL) { *((volatile uint32_t *)configRegister) = configValue; } @@ -1701,22 +1689,22 @@ static inline void IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR_Type *base, iomuxc_gp if (mclk > kIOMUXC_GPR_SAI2MClk3Sel) { gpr = base->GPR2 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK); - base->GPR2 = (clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) | gpr; + base->GPR2 = ((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) | gpr; } else if (mclk > kIOMUXC_GPR_SAI1MClk3Sel) { gpr = base->GPR1 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK); - base->GPR1 = (clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) | gpr; + base->GPR1 = ((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) | gpr; } else if (mclk > kIOMUXC_GPR_SAI1MClk2Sel) { - gpr = base->GPR0 & ~(IOMUXC_GPR_SAIMCLK_HIGHBITMASK << mclk); - base->GPR0 = ((clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << mclk) | gpr; + gpr = base->GPR0 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_HIGHBITMASK << (uint32_t)mclk); + base->GPR0 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << (uint32_t)mclk) | gpr; } else { - gpr = base->GPR0 & ~(IOMUXC_GPR_SAIMCLK_LOWBITMASK << mclk); - base->GPR0 = ((clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << mclk) | gpr; + gpr = base->GPR0 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_LOWBITMASK << (uint32_t)mclk); + base->GPR0 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << (uint32_t)mclk) | gpr; } } diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_lpi2c.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_lpi2c.c index c90cc000a00..7e67a34ec16 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_lpi2c.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_lpi2c.c @@ -19,36 +19,6 @@ #define FSL_COMPONENT_ID "platform.drivers.lpi2c" #endif -/*! @brief Common sets of flags used by the driver. */ -enum -{ - /*! All flags which are cleared by the driver upon starting a transfer. */ - kMasterClearFlags = kLPI2C_MasterEndOfPacketFlag | kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag | - kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterFifoErrFlag | kLPI2C_MasterPinLowTimeoutFlag | - kLPI2C_MasterDataMatchFlag, - - /*! IRQ sources enabled by the non-blocking transactional API. */ - kMasterIrqFlags = kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterTxReadyFlag | kLPI2C_MasterRxReadyFlag | - kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag | kLPI2C_MasterPinLowTimeoutFlag | - kLPI2C_MasterFifoErrFlag, - - /*! Errors to check for. */ - kMasterErrorFlags = kLPI2C_MasterNackDetectFlag | kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterFifoErrFlag | - kLPI2C_MasterPinLowTimeoutFlag, - - /*! All flags which are cleared by the driver upon starting a transfer. */ - kSlaveClearFlags = kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveBitErrFlag | - kLPI2C_SlaveFifoErrFlag, - - /*! IRQ sources enabled by the non-blocking transactional API. */ - kSlaveIrqFlags = kLPI2C_SlaveTxReadyFlag | kLPI2C_SlaveRxReadyFlag | kLPI2C_SlaveStopDetectFlag | - kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag | - kLPI2C_SlaveTransmitAckFlag | kLPI2C_SlaveAddressValidFlag, - - /*! Errors to check for. */ - kSlaveErrorFlags = kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag, -}; - /* ! @brief LPI2C master fifo commands. */ enum { @@ -220,7 +190,7 @@ status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status) /* Check for error. These errors cause a stop to automatically be sent. We must */ /* clear the errors before a new transfer can start. */ - status &= (uint32_t)kMasterErrorFlags; + status &= (uint32_t)kLPI2C_MasterErrorFlags; if (0U != status) { /* Select the correct error code. Ordered by severity, with bus issues first. */ @@ -275,7 +245,7 @@ static status_t LPI2C_MasterWaitForTxReady(LPI2C_Type *base) size_t txCount; size_t txFifoSize = (size_t)FSL_FEATURE_LPI2C_FIFO_SIZEn(base); -#if I2C_RETRY_TIMES +#if I2C_RETRY_TIMES != 0U uint32_t waitTimes = I2C_RETRY_TIMES; #endif do @@ -291,8 +261,9 @@ static status_t LPI2C_MasterWaitForTxReady(LPI2C_Type *base) { break; } -#if I2C_RETRY_TIMES - } while ((0U == txCount) && (0U != --waitTimes)); +#if I2C_RETRY_TIMES != 0U + waitTimes--; + } while ((0U == txCount) && (0U != waitTimes)); if (0U == waitTimes) { @@ -397,7 +368,7 @@ void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfi uint32_t instance = LPI2C_GetInstance(base); /* Ungate the clock. */ - CLOCK_EnableClock(kLpi2cClocks[instance]); + (void)CLOCK_EnableClock(kLpi2cClocks[instance]); #if defined(LPI2C_PERIPH_CLOCKS) /* Ungate the functional clock in initialize function. */ CLOCK_EnableClock(kLpi2cPeriphClocks[instance]); @@ -428,8 +399,6 @@ void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfi LPI2C_MasterSetWatermarks(base, (size_t)kDefaultTxWatermark, (size_t)kDefaultRxWatermark); - LPI2C_MasterSetBaudRate(base, sourceClock_Hz, masterConfig->baudRate_Hz); - /* Configure glitch filters and bus idle and pin low timeouts. */ prescaler = (base->MCFGR1 & LPI2C_MCFGR1_PRESCALE_MASK) >> LPI2C_MCFGR1_PRESCALE_SHIFT; cfgr2 = base->MCFGR2; @@ -455,6 +424,10 @@ void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfi cfgr2 |= LPI2C_MCFGR2_FILTSCL(cycles); } base->MCFGR2 = cfgr2; + /* Configure baudrate after the SDA/SCL glitch filter setting, + since the baudrate calculation needs them as parameter. */ + LPI2C_MasterSetBaudRate(base, sourceClock_Hz, masterConfig->baudRate_Hz); + if (0U != masterConfig->pinLowTimeout_ns) { cycles = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->pinLowTimeout_ns / 256U, @@ -483,7 +456,7 @@ void LPI2C_MasterDeinit(LPI2C_Type *base) uint32_t instance = LPI2C_GetInstance(base); /* Gate clock. */ - CLOCK_DisableClock(kLpi2cClocks[instance]); + (void)CLOCK_DisableClock(kLpi2cClocks[instance]); #if defined(LPI2C_PERIPH_CLOCKS) /* Gate the functional clock. */ CLOCK_DisableClock(kLpi2cPeriphClocks[instance]); @@ -496,17 +469,17 @@ void LPI2C_MasterDeinit(LPI2C_Type *base) * brief Configures LPI2C master data match feature. * * param base The LPI2C peripheral base address. - * param config Settings for the data match feature. + * param matchConfig Settings for the data match feature. */ -void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *config) +void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *matchConfig) { /* Disable master mode. */ bool wasEnabled = (0U != ((base->MCR & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT)); LPI2C_MasterEnable(base, false); - base->MCFGR1 = (base->MCFGR1 & ~LPI2C_MCFGR1_MATCFG_MASK) | LPI2C_MCFGR1_MATCFG(config->matchMode); - base->MCFGR0 = (base->MCFGR0 & ~LPI2C_MCFGR0_RDMO_MASK) | LPI2C_MCFGR0_RDMO(config->rxDataMatchOnly); - base->MDMR = LPI2C_MDMR_MATCH0(config->match0) | LPI2C_MDMR_MATCH1(config->match1); + base->MCFGR1 = (base->MCFGR1 & ~LPI2C_MCFGR1_MATCFG_MASK) | LPI2C_MCFGR1_MATCFG(matchConfig->matchMode); + base->MCFGR0 = (base->MCFGR0 & ~LPI2C_MCFGR0_RDMO_MASK) | LPI2C_MCFGR0_RDMO(matchConfig->rxDataMatchOnly); + base->MDMR = LPI2C_MDMR_MATCH0(matchConfig->match0) | LPI2C_MDMR_MATCH1(matchConfig->match1); /* Restore master mode. */ if (wasEnabled) @@ -531,81 +504,119 @@ void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_con */ void LPI2C_MasterSetBaudRate(LPI2C_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Hz) { - uint32_t prescale = 0U; - uint32_t bestPre = 0U; - uint32_t bestClkHi = 0U; + bool wasEnabled; + uint8_t filtScl = (uint8_t)((base->MCFGR2 & LPI2C_MCFGR2_FILTSCL_MASK) >> LPI2C_MCFGR2_FILTSCL_SHIFT); + + uint8_t divider = 1U; + uint8_t bestDivider = 1U; + uint8_t prescale = 0U; + uint8_t bestPre = 0U; + + uint8_t clkCycle; + uint8_t bestclkCycle = 0U; + uint32_t absError = 0U; uint32_t bestError = 0xffffffffu; - uint32_t value; - uint32_t clkHiCycle; uint32_t computedRate; - uint32_t i; - bool wasEnabled; + + uint32_t tmpReg = 0U; /* Disable master mode. */ wasEnabled = (0U != ((base->MCR & LPI2C_MCR_MEN_MASK) >> LPI2C_MCR_MEN_SHIFT)); LPI2C_MasterEnable(base, false); - /* Baud rate = (sourceClock_Hz/2^prescale)/(CLKLO+1+CLKHI+1 + ROUNDDOWN((2+FILTSCL)/2^prescale) */ - /* Assume CLKLO = 2*CLKHI, SETHOLD = CLKHI, DATAVD = CLKHI/2. */ - for (prescale = 1U; prescale <= 128U; prescale = 2U * prescale) + /* Baud rate = (sourceClock_Hz / 2 ^ prescale) / (CLKLO + 1 + CLKHI + 1 + SCL_LATENCY) + * SCL_LATENCY = ROUNDDOWN((2 + FILTSCL) / (2 ^ prescale)) + */ + for (prescale = 0U; prescale <= 7U; prescale++) { - if (bestError == 0U) + /* Calculate the clkCycle, clkCycle = CLKLO + CLKHI, divider = 2 ^ prescale */ + clkCycle = (uint8_t)((10U * sourceClock_Hz / divider / baudRate_Hz + 5U) / 10U - (2U + filtScl) / divider - 2U); + /* According to register description, The max value for CLKLO and CLKHI is 63. + however to meet the I2C specification of tBUF, CLKHI should be less than + clkCycle - 0.52 x sourceClock_Hz / baudRate_Hz / divider + 1U. Refer to the comment of the tmpHigh's + calculation for details. So we have: + CLKHI < clkCycle - 0.52 x sourceClock_Hz / baudRate_Hz / divider + 1U, + clkCycle = CLKHI + CLKLO and + sourceClock_Hz / baudRate_Hz / divider = clkCycle + 2 + ROUNDDOWN((2 + FILTSCL) / divider), + we can come up with: CLKHI < 0.92 x CLKLO - ROUNDDOWN(2 + FILTSCL) / divider + so the max boundary of CLKHI should be 0.92 x 63 - ROUNDDOWN(2 + FILTSCL) / divider, + and the max boundary of clkCycle is 1.92 x 63 - ROUNDDOWN(2 + FILTSCL) / divider. */ + if (clkCycle > (120U - (2U + filtScl) / divider)) { - break; + divider *= 2U; + continue; } - - for (clkHiCycle = 1U; clkHiCycle < 32U; clkHiCycle++) + /* Calculate the computed baudrate and compare it with the desired baudrate */ + computedRate = (sourceClock_Hz / (uint32_t)divider) / + ((uint32_t)clkCycle + 2U + (2U + (uint32_t)filtScl) / (uint32_t)divider); + absError = baudRate_Hz > computedRate ? baudRate_Hz - computedRate : computedRate - baudRate_Hz; + if (absError < bestError) { - if (clkHiCycle == 1U) - { - computedRate = (sourceClock_Hz / prescale) / (1U + 3U + 2U + 2U / prescale); - } - else - { - computedRate = (sourceClock_Hz / prescale) / (3U * clkHiCycle + 2U + 2U / prescale); - } - - absError = baudRate_Hz > computedRate ? baudRate_Hz - computedRate : computedRate - baudRate_Hz; + bestPre = prescale; + bestDivider = divider; + bestclkCycle = clkCycle; + bestError = absError; - if (absError < bestError) + /* If the error is 0, then we can stop searching because we won't find a better match. */ + if (absError == 0U) { - bestPre = prescale; - bestClkHi = clkHiCycle; - bestError = absError; - - /* If the error is 0, then we can stop searching because we won't find a better match. */ - if (absError == 0U) - { - break; - } + break; } } + divider *= 2U; } - /* Standard, fast, fast mode plus and ultra-fast transfers. */ - value = LPI2C_MCCR0_CLKHI(bestClkHi); - - if (bestClkHi < 2U) + /* SCL low time tLO should be larger than or equal to SCL high time tHI: + tLO = ((CLKLO + 1) x (2 ^ PRESCALE)) >= tHI = ((CLKHI + 1 + SCL_LATENCY) x (2 ^ PRESCALE)), + which is CLKLO >= CLKHI + (2U + filtScl) / bestDivider. + Also since bestclkCycle = CLKLO + CLKHI, bestDivider = 2 ^ PRESCALE + which makes CLKHI <= (bestclkCycle - (2U + filtScl) / bestDivider) / 2U. + + The max tBUF should be at least 0.52 times of the SCL clock cycle: + tBUF = ((CLKLO + 1) x (2 ^ PRESCALE) / sourceClock_Hz) > (0.52 / baudRate_Hz), + plus bestDivider = 2 ^ PRESCALE, bestclkCycle = CLKLO + CLKHI we can come up with + CLKHI <= (bestclkCycle - 0.52 x sourceClock_Hz / baudRate_Hz / bestDivider + 1U). + In this case to get a safe CLKHI calculation, we can assume: + */ + uint8_t tmpHigh = (bestclkCycle - (2U + filtScl) / bestDivider) / 2U; + while (tmpHigh > (bestclkCycle - 52U * sourceClock_Hz / baudRate_Hz / bestDivider / 100U + 1U)) { - value |= (uint32_t)(LPI2C_MCCR0_CLKLO(3UL) | LPI2C_MCCR0_SETHOLD(2UL) | LPI2C_MCCR0_DATAVD(1UL)); + tmpHigh = tmpHigh - 1U; } - else - { - value |= - LPI2C_MCCR0_CLKLO(2UL * bestClkHi) | LPI2C_MCCR0_SETHOLD(bestClkHi) | LPI2C_MCCR0_DATAVD(bestClkHi / 2UL); - } - - base->MCCR0 = value; - for (i = 0U; i < 8U; i++) + /* Calculate DATAVD and SETHOLD. + To meet the timing requirement of I2C spec for standard mode, fast mode and fast mode plus: */ + /* The min tHD:STA/tSU:STA/tSU:STO should be at least 0.4 times of the SCL clock cycle, use 0.5 to be safe: + tHD:STA = ((SETHOLD + 1) x (2 ^ PRESCALE) / sourceClock_Hz) > (0.5 / baudRate_Hz), bestDivider = 2 ^ PRESCALE */ + uint8_t tmpHold = (uint8_t)(sourceClock_Hz / baudRate_Hz / bestDivider / 2U) - 1U; + + /* The max tVD:DAT/tVD:ACK/tHD:DAT should be at most 0.345 times of the SCL clock cycle, use 0.25 to be safe: + tVD:DAT = ((DATAVD + 1) x (2 ^ PRESCALE) / sourceClock_Hz) < (0.25 / baudRate_Hz), bestDivider = 2 ^ PRESCALE */ + uint8_t tmpDataVd = (uint8_t)(sourceClock_Hz / baudRate_Hz / bestDivider / 4U) - 1U; + + /* The min tSU:DAT should be at least 0.05 times of the SCL clock cycle: + tSU:DAT = ((2 + FILTSDA + 2 ^ PRESCALE) / sourceClock_Hz) >= (0.05 / baud), + plus bestDivider = 2 ^ PRESCALE, we can come up with: + FILTSDA >= (0.05 x sourceClock_Hz / baudRate_Hz - bestDivider - 2) */ + if ((sourceClock_Hz / baudRate_Hz / 20U) > (bestDivider + 2U)) { - if (bestPre == (1UL << i)) + /* Read out the FILTSDA configuration, if it is smaller than expected, change the setting. */ + uint8_t filtSda = (uint8_t)((base->MCFGR2 & LPI2C_MCFGR2_FILTSDA_MASK) >> LPI2C_MCFGR2_FILTSDA_SHIFT); + if (filtSda < (sourceClock_Hz / baudRate_Hz / 20U - bestDivider - 2U)) { - bestPre = i; - break; + filtSda = (uint8_t)(sourceClock_Hz / baudRate_Hz / 20U) - bestDivider - 2U; } + base->MCFGR2 = (base->MCFGR2 & ~LPI2C_MCFGR2_FILTSDA_MASK) | LPI2C_MCFGR2_FILTSDA(filtSda); } + + /* Set CLKHI, CLKLO, SETHOLD, DATAVD value. */ + tmpReg = LPI2C_MCCR0_CLKHI((uint32_t)tmpHigh) | + LPI2C_MCCR0_CLKLO((uint32_t)((uint32_t)bestclkCycle - (uint32_t)tmpHigh)) | + LPI2C_MCCR0_SETHOLD((uint32_t)tmpHold) | LPI2C_MCCR0_DATAVD((uint32_t)tmpDataVd); + base->MCCR0 = tmpReg; + + /* Set PRESCALE value. */ base->MCFGR1 = (base->MCFGR1 & ~LPI2C_MCFGR1_PRESCALE_MASK) | LPI2C_MCFGR1_PRESCALE(bestPre); /* Restore master mode. */ @@ -637,7 +648,7 @@ status_t LPI2C_MasterStart(LPI2C_Type *base, uint8_t address, lpi2c_direction_t if (kStatus_Success == result) { /* Clear all flags. */ - LPI2C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + LPI2C_MasterClearStatusFlags(base, (uint32_t)kLPI2C_MasterClearFlags); /* Turn off auto-stop option. */ base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK; @@ -678,16 +689,18 @@ status_t LPI2C_MasterStop(LPI2C_Type *base) /* Wait for the stop detected flag to set, indicating the transfer has completed on the bus. */ /* Also check for errors while waiting. */ -#if I2C_RETRY_TIMES +#if I2C_RETRY_TIMES != 0U uint32_t waitTimes = I2C_RETRY_TIMES; #endif -#if I2C_RETRY_TIMES - while ((result == kStatus_Success) && (0U != --waitTimes)) +#if I2C_RETRY_TIMES != 0U + while ((result == kStatus_Success) && (0U != waitTimes)) + { + waitTimes--; #else while (result == kStatus_Success) -#endif { +#endif uint32_t status = LPI2C_MasterGetStatusFlags(base); /* Check for error flags. */ @@ -702,7 +715,7 @@ status_t LPI2C_MasterStop(LPI2C_Type *base) } } -#if I2C_RETRY_TIMES +#if I2C_RETRY_TIMES != 0U if (0U == waitTimes) { result = kStatus_LPI2C_Timeout; @@ -730,7 +743,7 @@ status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize) { status_t result = kStatus_Success; uint8_t *buf; -#if I2C_RETRY_TIMES +#if I2C_RETRY_TIMES != 0U uint32_t waitTimes; #endif @@ -750,7 +763,7 @@ status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize) buf = (uint8_t *)rxBuff; while (0U != (rxSize--)) { -#if I2C_RETRY_TIMES +#if I2C_RETRY_TIMES != 0U waitTimes = I2C_RETRY_TIMES; #endif /* Read LPI2C receive fifo register. The register includes a flag to indicate whether */ @@ -767,8 +780,9 @@ status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize) } value = base->MRDR; -#if I2C_RETRY_TIMES - } while ((0U != (value & LPI2C_MRDR_RXEMPTY_MASK)) && (0U != --waitTimes)); +#if I2C_RETRY_TIMES != 0U + waitTimes--; + } while ((0U != (value & LPI2C_MRDR_RXEMPTY_MASK)) && (0U != waitTimes)); if (0U == waitTimes) { result = kStatus_LPI2C_Timeout; @@ -859,7 +873,7 @@ status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t if (kStatus_Success == result) { /* Clear all flags. */ - LPI2C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + LPI2C_MasterClearStatusFlags(base, (uint32_t)kLPI2C_MasterClearFlags); /* Turn off auto-stop option. */ base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK; @@ -982,7 +996,7 @@ void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base, s_lpi2cMasterIsr = LPI2C_MasterTransferHandleIRQ; /* Clear internal IRQ enables and enable NVIC IRQ. */ - LPI2C_MasterDisableInterrupts(base, (uint32_t)kMasterIrqFlags); + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags); /* Enable NVIC IRQ, this only enables the IRQ directly connected to the NVIC. In some cases the LPI2C IRQ is configured through INTMUX, user needs to enable @@ -1276,7 +1290,7 @@ status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base, if ((status_t)kStatus_Success == result) { /* Disable LPI2C IRQ sources while we configure stuff. */ - LPI2C_MasterDisableInterrupts(base, (uint32_t)kMasterIrqFlags); + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags); /* Reset FIFO in case there are data. */ base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; @@ -1288,13 +1302,13 @@ status_t LPI2C_MasterTransferNonBlocking(LPI2C_Type *base, LPI2C_InitTransferStateMachine(handle); /* Clear all flags. */ - LPI2C_MasterClearStatusFlags(base, (uint32_t)kMasterClearFlags); + LPI2C_MasterClearStatusFlags(base, (uint32_t)kLPI2C_MasterClearFlags); /* Turn off auto-stop option. */ base->MCFGR1 &= ~LPI2C_MCFGR1_AUTOSTOP_MASK; /* Enable LPI2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ - LPI2C_MasterEnableInterrupts(base, (uint32_t)kMasterIrqFlags); + LPI2C_MasterEnableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags); } return result; @@ -1381,7 +1395,7 @@ void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle) if (handle->state != (uint8_t)kIdleState) { /* Disable internal IRQ enables. */ - LPI2C_MasterDisableInterrupts(base, (uint32_t)kMasterIrqFlags); + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags); /* Reset fifos. */ base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK; @@ -1434,7 +1448,7 @@ void LPI2C_MasterTransferHandleIRQ(LPI2C_Type *base, lpi2c_master_handle_t *hand base->MTDR = (uint32_t)kStopCmd; } /* Disable internal IRQ enables. */ - LPI2C_MasterDisableInterrupts(base, (uint32_t)kMasterIrqFlags); + LPI2C_MasterDisableInterrupts(base, (uint32_t)kLPI2C_MasterIrqFlags); /* Set handle to idle state. */ handle->state = (uint8_t)kIdleState; @@ -1525,7 +1539,7 @@ void LPI2C_SlaveInit(LPI2C_Type *base, const lpi2c_slave_config_t *slaveConfig, uint32_t instance = LPI2C_GetInstance(base); /* Ungate the clock. */ - CLOCK_EnableClock(kLpi2cClocks[instance]); + (void)CLOCK_EnableClock(kLpi2cClocks[instance]); #if defined(LPI2C_PERIPH_CLOCKS) /* Ungate the functional clock in initialize function. */ CLOCK_EnableClock(kLpi2cPeriphClocks[instance]); @@ -1581,7 +1595,7 @@ void LPI2C_SlaveDeinit(LPI2C_Type *base) uint32_t instance = LPI2C_GetInstance(base); /* Gate the clock. */ - CLOCK_DisableClock(kLpi2cClocks[instance]); + (void)CLOCK_DisableClock(kLpi2cClocks[instance]); #if defined(LPI2C_PERIPH_CLOCKS) /* Gate the functional clock. */ @@ -1603,7 +1617,7 @@ static status_t LPI2C_SlaveCheckAndClearError(LPI2C_Type *base, uint32_t flags) { status_t result = kStatus_Success; - flags &= (uint32_t)kSlaveErrorFlags; + flags &= (uint32_t)kLPI2C_SlaveErrorFlags; if (0U != flags) { if (0U != (flags & (uint32_t)kLPI2C_SlaveBitErrFlag)) @@ -1647,7 +1661,7 @@ status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t * assert(NULL != txBuff); -#if I2C_RETRY_TIMES +#if I2C_RETRY_TIMES != 0U uint32_t waitTimes = I2C_RETRY_TIMES; #endif @@ -1673,10 +1687,11 @@ status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t * } break; } -#if I2C_RETRY_TIMES +#if I2C_RETRY_TIMES != 0U + waitTimes--; } while ((0U == (flags & ((uint32_t)kLPI2C_SlaveTxReadyFlag | (uint32_t)kLPI2C_SlaveStopDetectFlag | (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag))) && - (0U != --waitTimes)); + (0U != waitTimes)); if (0U == waitTimes) { result = kStatus_LPI2C_Timeout; @@ -1733,7 +1748,7 @@ status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_ assert(NULL != rxBuff); -#if I2C_RETRY_TIMES +#if I2C_RETRY_TIMES != 0U uint32_t waitTimes = I2C_RETRY_TIMES; #endif @@ -1759,10 +1774,11 @@ status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_ } break; } -#if I2C_RETRY_TIMES +#if I2C_RETRY_TIMES != 0U + waitTimes--; } while ((0U == (flags & ((uint32_t)kLPI2C_SlaveRxReadyFlag | (uint32_t)kLPI2C_SlaveStopDetectFlag | (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag))) && - (0U != --waitTimes)); + (0U != waitTimes)); if (0U == waitTimes) { result = kStatus_LPI2C_Timeout; @@ -1844,7 +1860,7 @@ void LPI2C_SlaveTransferCreateHandle(LPI2C_Type *base, s_lpi2cSlaveIsr = LPI2C_SlaveTransferHandleIRQ; /* Clear internal IRQ enables and enable NVIC IRQ. */ - LPI2C_SlaveDisableInterrupts(base, (uint32_t)kSlaveIrqFlags); + LPI2C_SlaveDisableInterrupts(base, (uint32_t)kLPI2C_SlaveIrqFlags); (void)EnableIRQ(kLpi2cIrqs[instance]); /* Nack by default. */ @@ -1899,7 +1915,7 @@ status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t * if ((status_t)kStatus_Success == result) { /* Disable LPI2C IRQ sources while we configure stuff. */ - LPI2C_SlaveDisableInterrupts(base, (uint32_t)kSlaveIrqFlags); + LPI2C_SlaveDisableInterrupts(base, (uint32_t)kLPI2C_SlaveIrqFlags); /* Clear transfer in handle. */ (void)memset(&handle->transfer, 0, sizeof(handle->transfer)); @@ -1914,10 +1930,10 @@ status_t LPI2C_SlaveTransferNonBlocking(LPI2C_Type *base, lpi2c_slave_handle_t * base->STAR = 0U; /* Clear all flags. */ - LPI2C_SlaveClearStatusFlags(base, (uint32_t)kSlaveClearFlags); + LPI2C_SlaveClearStatusFlags(base, (uint32_t)kLPI2C_SlaveClearFlags); /* Enable LPI2C internal IRQ sources. NVIC IRQ was enabled in CreateHandle() */ - LPI2C_SlaveEnableInterrupts(base, (uint32_t)kSlaveIrqFlags); + LPI2C_SlaveEnableInterrupts(base, (uint32_t)kLPI2C_SlaveIrqFlags); } return result; @@ -1975,7 +1991,7 @@ void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle) if (handle->isBusy) { /* Disable LPI2C IRQ sources. */ - LPI2C_SlaveDisableInterrupts(base, (uint32_t)kSlaveIrqFlags); + LPI2C_SlaveDisableInterrupts(base, (uint32_t)kLPI2C_SlaveIrqFlags); /* Nack by default. */ base->STAR = LPI2C_STAR_TXNACK_MASK; @@ -2171,6 +2187,7 @@ static void LPI2C_CommonIRQHandler(LPI2C_Type *base, uint32_t instance) #if defined(LPI2C0) /* Implementation of LPI2C0 handler named in startup code. */ +void LPI2C0_DriverIRQHandler(void); void LPI2C0_DriverIRQHandler(void) { LPI2C_CommonIRQHandler(LPI2C0, 0U); @@ -2179,6 +2196,7 @@ void LPI2C0_DriverIRQHandler(void) #if defined(LPI2C1) /* Implementation of LPI2C1 handler named in startup code. */ +void LPI2C1_DriverIRQHandler(void); void LPI2C1_DriverIRQHandler(void) { LPI2C_CommonIRQHandler(LPI2C1, 1U); @@ -2187,6 +2205,7 @@ void LPI2C1_DriverIRQHandler(void) #if defined(LPI2C2) /* Implementation of LPI2C2 handler named in startup code. */ +void LPI2C2_DriverIRQHandler(void); void LPI2C2_DriverIRQHandler(void) { LPI2C_CommonIRQHandler(LPI2C2, 2U); @@ -2195,6 +2214,7 @@ void LPI2C2_DriverIRQHandler(void) #if defined(LPI2C3) /* Implementation of LPI2C3 handler named in startup code. */ +void LPI2C3_DriverIRQHandler(void); void LPI2C3_DriverIRQHandler(void) { LPI2C_CommonIRQHandler(LPI2C3, 3U); @@ -2203,6 +2223,7 @@ void LPI2C3_DriverIRQHandler(void) #if defined(LPI2C4) /* Implementation of LPI2C4 handler named in startup code. */ +void LPI2C4_DriverIRQHandler(void); void LPI2C4_DriverIRQHandler(void) { LPI2C_CommonIRQHandler(LPI2C4, 4U); @@ -2211,6 +2232,7 @@ void LPI2C4_DriverIRQHandler(void) #if defined(LPI2C5) /* Implementation of LPI2C5 handler named in startup code. */ +void LPI2C5_DriverIRQHandler(void); void LPI2C5_DriverIRQHandler(void) { LPI2C_CommonIRQHandler(LPI2C5, 5U); @@ -2219,6 +2241,7 @@ void LPI2C5_DriverIRQHandler(void) #if defined(LPI2C6) /* Implementation of LPI2C6 handler named in startup code. */ +void LPI2C6_DriverIRQHandler(void); void LPI2C6_DriverIRQHandler(void) { LPI2C_CommonIRQHandler(LPI2C6, 6U); @@ -2227,6 +2250,7 @@ void LPI2C6_DriverIRQHandler(void) #if defined(CM4_0__LPI2C) /* Implementation of CM4_0__LPI2C handler named in startup code. */ +void M4_0_LPI2C_DriverIRQHandler(void); void M4_0_LPI2C_DriverIRQHandler(void) { LPI2C_CommonIRQHandler(CM4_0__LPI2C, LPI2C_GetInstance(CM4_0__LPI2C)); @@ -2235,6 +2259,7 @@ void M4_0_LPI2C_DriverIRQHandler(void) #if defined(CM4__LPI2C) /* Implementation of CM4__LPI2C handler named in startup code. */ +void M4_LPI2C_DriverIRQHandler(void); void M4_LPI2C_DriverIRQHandler(void) { LPI2C_CommonIRQHandler(CM4__LPI2C, LPI2C_GetInstance(CM4__LPI2C)); @@ -2243,6 +2268,7 @@ void M4_LPI2C_DriverIRQHandler(void) #if defined(CM4_1__LPI2C) /* Implementation of CM4_1__LPI2C handler named in startup code. */ +void M4_1_LPI2C_DriverIRQHandler(void); void M4_1_LPI2C_DriverIRQHandler(void) { LPI2C_CommonIRQHandler(CM4_1__LPI2C, LPI2C_GetInstance(CM4_1__LPI2C)); @@ -2251,6 +2277,7 @@ void M4_1_LPI2C_DriverIRQHandler(void) #if defined(DMA__LPI2C0) /* Implementation of DMA__LPI2C0 handler named in startup code. */ +void DMA_I2C0_INT_DriverIRQHandler(void); void DMA_I2C0_INT_DriverIRQHandler(void) { LPI2C_CommonIRQHandler(DMA__LPI2C0, LPI2C_GetInstance(DMA__LPI2C0)); @@ -2259,6 +2286,7 @@ void DMA_I2C0_INT_DriverIRQHandler(void) #if defined(DMA__LPI2C1) /* Implementation of DMA__LPI2C1 handler named in startup code. */ +void DMA_I2C1_INT_DriverIRQHandler(void); void DMA_I2C1_INT_DriverIRQHandler(void) { LPI2C_CommonIRQHandler(DMA__LPI2C1, LPI2C_GetInstance(DMA__LPI2C1)); @@ -2267,6 +2295,7 @@ void DMA_I2C1_INT_DriverIRQHandler(void) #if defined(DMA__LPI2C2) /* Implementation of DMA__LPI2C2 handler named in startup code. */ +void DMA_I2C2_INT_DriverIRQHandler(void); void DMA_I2C2_INT_DriverIRQHandler(void) { LPI2C_CommonIRQHandler(DMA__LPI2C2, LPI2C_GetInstance(DMA__LPI2C2)); @@ -2275,6 +2304,7 @@ void DMA_I2C2_INT_DriverIRQHandler(void) #if defined(DMA__LPI2C3) /* Implementation of DMA__LPI2C3 handler named in startup code. */ +void DMA_I2C3_INT_DriverIRQHandler(void); void DMA_I2C3_INT_DriverIRQHandler(void) { LPI2C_CommonIRQHandler(DMA__LPI2C3, LPI2C_GetInstance(DMA__LPI2C3)); @@ -2283,6 +2313,7 @@ void DMA_I2C3_INT_DriverIRQHandler(void) #if defined(DMA__LPI2C4) /* Implementation of DMA__LPI2C3 handler named in startup code. */ +void DMA_I2C4_INT_DriverIRQHandler(void); void DMA_I2C4_INT_DriverIRQHandler(void) { LPI2C_CommonIRQHandler(DMA__LPI2C4, LPI2C_GetInstance(DMA__LPI2C4)); @@ -2291,6 +2322,7 @@ void DMA_I2C4_INT_DriverIRQHandler(void) #if defined(ADMA__LPI2C0) /* Implementation of DMA__LPI2C0 handler named in startup code. */ +void ADMA_I2C0_INT_DriverIRQHandler(void); void ADMA_I2C0_INT_DriverIRQHandler(void) { LPI2C_CommonIRQHandler(ADMA__LPI2C0, LPI2C_GetInstance(ADMA__LPI2C0)); @@ -2299,6 +2331,7 @@ void ADMA_I2C0_INT_DriverIRQHandler(void) #if defined(ADMA__LPI2C1) /* Implementation of DMA__LPI2C1 handler named in startup code. */ +void ADMA_I2C1_INT_DriverIRQHandler(void); void ADMA_I2C1_INT_DriverIRQHandler(void) { LPI2C_CommonIRQHandler(ADMA__LPI2C1, LPI2C_GetInstance(ADMA__LPI2C1)); @@ -2307,6 +2340,7 @@ void ADMA_I2C1_INT_DriverIRQHandler(void) #if defined(ADMA__LPI2C2) /* Implementation of DMA__LPI2C2 handler named in startup code. */ +void ADMA_I2C2_INT_DriverIRQHandler(void); void ADMA_I2C2_INT_DriverIRQHandler(void) { LPI2C_CommonIRQHandler(ADMA__LPI2C2, LPI2C_GetInstance(ADMA__LPI2C2)); @@ -2315,6 +2349,7 @@ void ADMA_I2C2_INT_DriverIRQHandler(void) #if defined(ADMA__LPI2C3) /* Implementation of DMA__LPI2C3 handler named in startup code. */ +void ADMA_I2C3_INT_DriverIRQHandler(void); void ADMA_I2C3_INT_DriverIRQHandler(void) { LPI2C_CommonIRQHandler(ADMA__LPI2C3, LPI2C_GetInstance(ADMA__LPI2C3)); @@ -2323,6 +2358,7 @@ void ADMA_I2C3_INT_DriverIRQHandler(void) #if defined(ADMA__LPI2C4) /* Implementation of DMA__LPI2C3 handler named in startup code. */ +void ADMA_I2C4_INT_DriverIRQHandler(void); void ADMA_I2C4_INT_DriverIRQHandler(void) { LPI2C_CommonIRQHandler(ADMA__LPI2C4, LPI2C_GetInstance(ADMA__LPI2C4)); diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_lpi2c.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_lpi2c.h index 01da7f2748b..885f0979d48 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_lpi2c.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_lpi2c.h @@ -23,8 +23,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief LPI2C driver version 2.1.12. */ -#define FSL_LPI2C_DRIVER_VERSION (MAKE_VERSION(2, 1, 12)) +/*! @brief LPI2C driver version. */ +#define FSL_LPI2C_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) /*@}*/ /*! @brief Retry times for waiting flag. */ @@ -73,7 +73,7 @@ enum * * @note These enums are meant to be OR'd together to form a bit mask. */ -enum +enum _lpi2c_master_flags { kLPI2C_MasterTxReadyFlag = LPI2C_MSR_TDF_MASK, /*!< Transmit data flag */ kLPI2C_MasterRxReadyFlag = LPI2C_MSR_RDF_MASK, /*!< Receive data flag */ @@ -85,7 +85,19 @@ enum kLPI2C_MasterPinLowTimeoutFlag = LPI2C_MSR_PLTF_MASK, /*!< Pin low timeout flag */ kLPI2C_MasterDataMatchFlag = LPI2C_MSR_DMF_MASK, /*!< Data match flag */ kLPI2C_MasterBusyFlag = LPI2C_MSR_MBF_MASK, /*!< Master busy flag */ - kLPI2C_MasterBusBusyFlag = LPI2C_MSR_BBF_MASK /*!< Bus busy flag */ + kLPI2C_MasterBusBusyFlag = LPI2C_MSR_BBF_MASK, /*!< Bus busy flag */ + + /*! All flags which are cleared by the driver upon starting a transfer. */ + kLPI2C_MasterClearFlags = kLPI2C_MasterEndOfPacketFlag | kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag | + kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterFifoErrFlag | + kLPI2C_MasterPinLowTimeoutFlag | kLPI2C_MasterDataMatchFlag, + /*! IRQ sources enabled by the non-blocking transactional API. */ + kLPI2C_MasterIrqFlags = kLPI2C_MasterArbitrationLostFlag | kLPI2C_MasterTxReadyFlag | kLPI2C_MasterRxReadyFlag | + kLPI2C_MasterStopDetectFlag | kLPI2C_MasterNackDetectFlag | kLPI2C_MasterPinLowTimeoutFlag | + kLPI2C_MasterFifoErrFlag, + /*! Errors to check for. */ + kLPI2C_MasterErrorFlags = kLPI2C_MasterNackDetectFlag | kLPI2C_MasterArbitrationLostFlag | + kLPI2C_MasterFifoErrFlag | kLPI2C_MasterPinLowTimeoutFlag }; /*! @brief Direction of master and slave transfers. */ @@ -280,6 +292,15 @@ enum _lpi2c_slave_flags kLPI2C_SlaveGeneralCallFlag = LPI2C_SSR_GCF_MASK, /*!< General call flag */ kLPI2C_SlaveBusyFlag = LPI2C_SSR_SBF_MASK, /*!< Master busy flag */ kLPI2C_SlaveBusBusyFlag = LPI2C_SSR_BBF_MASK, /*!< Bus busy flag */ + /*! All flags which are cleared by the driver upon starting a transfer. */ + kLPI2C_SlaveClearFlags = kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveStopDetectFlag | kLPI2C_SlaveBitErrFlag | + kLPI2C_SlaveFifoErrFlag, + /*! IRQ sources enabled by the non-blocking transactional API. */ + kLPI2C_SlaveIrqFlags = kLPI2C_SlaveTxReadyFlag | kLPI2C_SlaveRxReadyFlag | kLPI2C_SlaveStopDetectFlag | + kLPI2C_SlaveRepeatedStartDetectFlag | kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag | + kLPI2C_SlaveTransmitAckFlag | kLPI2C_SlaveAddressValidFlag, + /*! Errors to check for. */ + kLPI2C_SlaveErrorFlags = kLPI2C_SlaveFifoErrFlag | kLPI2C_SlaveBitErrFlag }; /*! @brief LPI2C slave address match options. */ @@ -471,9 +492,9 @@ void LPI2C_MasterDeinit(LPI2C_Type *base); * @brief Configures LPI2C master data match feature. * * @param base The LPI2C peripheral base address. - * @param config Settings for the data match feature. + * @param matchConfig Settings for the data match feature. */ -void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *config); +void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *matchConfig); /* Not static so it can be used from fsl_lpi2c_edma.c. */ status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status); diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_lpspi.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_lpspi.c index 4917a01c9e8..f1ef13ba82d 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_lpspi.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_lpspi.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2019 NXP + * Copyright 2016-2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -185,7 +185,7 @@ void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData) */ void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz) { - assert(masterConfig); + assert(masterConfig != NULL); uint32_t tcrPrescaleValue = 0; @@ -248,7 +248,7 @@ void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfi */ void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig) { - assert(masterConfig); + assert(masterConfig != NULL); /* Initializes the configure structure to zero. */ (void)memset(masterConfig, 0, sizeof(*masterConfig)); @@ -278,7 +278,7 @@ void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig) */ void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig) { - assert(slaveConfig); + assert(slaveConfig != NULL); #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) @@ -325,7 +325,7 @@ void LPSPI_SlaveInit(LPSPI_Type *base, const lpspi_slave_config_t *slaveConfig) */ void LPSPI_SlaveGetDefaultConfig(lpspi_slave_config_t *slaveConfig) { - assert(slaveConfig); + assert(slaveConfig != NULL); /* Initializes the configure structure to zero. */ (void)memset(slaveConfig, 0, sizeof(*slaveConfig)); @@ -422,7 +422,7 @@ uint32_t LPSPI_MasterSetBaudRate(LPSPI_Type *base, uint32_t srcClock_Hz, uint32_t *tcrPrescaleValue) { - assert(tcrPrescaleValue); + assert(tcrPrescaleValue != NULL); /* For master mode configuration only, if slave mode detected, return 0. * Also, the LPSPI module needs to be disabled first, if enabled, return 0 @@ -700,7 +700,7 @@ void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base, lpspi_master_transfer_callback_t callback, void *userData) { - assert(handle); + assert(handle != NULL); /* Zero the handle. */ (void)memset(handle, 0, sizeof(*handle)); @@ -724,7 +724,7 @@ void LPSPI_MasterTransferCreateHandle(LPSPI_Type *base, */ bool LPSPI_CheckTransferArgument(lpspi_transfer_t *transfer, uint32_t bitsPerFrame, uint32_t bytesPerFrame) { - assert(transfer); + assert(transfer != NULL); /* If the transfer count is zero, then return immediately.*/ if (transfer->dataSize == 0U) @@ -790,7 +790,7 @@ bool LPSPI_CheckTransferArgument(lpspi_transfer_t *transfer, uint32_t bitsPerFra */ status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transfer) { - assert(transfer); + assert(transfer != NULL); uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1U; uint32_t bytesPerFrame = (bitsPerFrame + 7U) / 8U; @@ -1035,8 +1035,8 @@ status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transf */ status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t *handle, lpspi_transfer_t *transfer) { - assert(handle); - assert(transfer); + assert(handle != NULL); + assert(transfer != NULL); uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1U; uint32_t bytesPerFrame = (bitsPerFrame + 7U) / 8U; @@ -1056,6 +1056,26 @@ status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t return kStatus_LPSPI_Busy; } + LPSPI_Enable(base, false); + /*Transfers will stall when transmit FIFO is empty or receive FIFO is full. */ + base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); + /* Check if using 3-wire mode and the txData is NULL, set the output pin to tristated. */ + temp = base->CFGR1; + temp &= LPSPI_CFGR1_PINCFG_MASK; + if ((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut))) + { + if (NULL == handle->txData) + { + base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK; + } + /* The 3-wire mode can't send and receive data at the same time. */ + if ((NULL != handle->txData) && (NULL != handle->rxData)) + { + return kStatus_InvalidArgument; + } + } + LPSPI_Enable(base, true); + handle->state = (uint8_t)kLPSPI_Busy; bool isRxMask = false; @@ -1099,26 +1119,6 @@ status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t LPSPI_SetFifoWatermarks(base, txWatermark, handle->rxWatermark); - LPSPI_Enable(base, false); - /*Transfers will stall when transmit FIFO is empty or receive FIFO is full. */ - base->CFGR1 &= (~LPSPI_CFGR1_NOSTALL_MASK); - /* Check if using 3-wire mode and the txData is NULL, set the output pin to tristated. */ - temp = base->CFGR1; - temp &= LPSPI_CFGR1_PINCFG_MASK; - if ((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut))) - { - if (NULL == handle->txData) - { - base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK; - } - /* The 3-wire mode can't send and receive data at the same time. */ - if ((NULL != handle->txData) && (NULL != handle->rxData)) - { - return kStatus_InvalidArgument; - } - } - LPSPI_Enable(base, true); - /*Flush FIFO , clear status , disable all the inerrupts.*/ LPSPI_FlushFifo(base, true, true); LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_AllStatusFlag); @@ -1199,7 +1199,7 @@ status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t static void LPSPI_MasterTransferFillUpTxFifo(LPSPI_Type *base, lpspi_master_handle_t *handle) { - assert(handle); + assert(handle != NULL); uint32_t wordToSend = 0; uint8_t fifoSize = handle->fifoSize; @@ -1267,7 +1267,7 @@ static void LPSPI_MasterTransferFillUpTxFifo(LPSPI_Type *base, lpspi_master_hand static void LPSPI_MasterTransferComplete(LPSPI_Type *base, lpspi_master_handle_t *handle) { - assert(handle); + assert(handle != NULL); /* Disable interrupt requests*/ LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_AllInterruptEnable); @@ -1292,7 +1292,7 @@ static void LPSPI_MasterTransferComplete(LPSPI_Type *base, lpspi_master_handle_t */ status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *handle, size_t *count) { - assert(handle); + assert(handle != NULL); if (NULL == count) { @@ -1332,7 +1332,7 @@ status_t LPSPI_MasterTransferGetCount(LPSPI_Type *base, lpspi_master_handle_t *h */ void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle) { - assert(handle); + assert(handle != NULL); /* Disable interrupt requests*/ LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_AllInterruptEnable); @@ -1354,7 +1354,7 @@ void LPSPI_MasterTransferAbort(LPSPI_Type *base, lpspi_master_handle_t *handle) */ void LPSPI_MasterTransferHandleIRQ(LPSPI_Type *base, lpspi_master_handle_t *handle) { - assert(handle); + assert(handle != NULL); uint32_t readData; uint8_t bytesEachRead = handle->bytesEachRead; @@ -1471,7 +1471,7 @@ void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base, lpspi_slave_transfer_callback_t callback, void *userData) { - assert(handle); + assert(handle != NULL); /* Zero the handle. */ (void)memset(handle, 0, sizeof(*handle)); @@ -1505,8 +1505,8 @@ void LPSPI_SlaveTransferCreateHandle(LPSPI_Type *base, */ status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t *handle, lpspi_transfer_t *transfer) { - assert(handle); - assert(transfer); + assert(handle != NULL); + assert(transfer != NULL); uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1U; uint32_t bytesPerFrame = (bitsPerFrame + 7U) / 8U; @@ -1523,6 +1523,25 @@ status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t * { return kStatus_LPSPI_Busy; } + + /* Check if using 3-wire mode and the txData is NULL, set the output pin to tristated. */ + temp = base->CFGR1; + temp &= LPSPI_CFGR1_PINCFG_MASK; + if ((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut))) + { + if (NULL == handle->txData) + { + LPSPI_Enable(base, false); + base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK; + LPSPI_Enable(base, true); + } + /* The 3-wire mode can't send and receive data at the same time. */ + if ((handle->txData != NULL) && (handle->rxData != NULL)) + { + return kStatus_InvalidArgument; + } + } + handle->state = (uint8_t)kLPSPI_Busy; bool isRxMask = false; @@ -1558,24 +1577,6 @@ status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t * } LPSPI_SetFifoWatermarks(base, txWatermark, handle->rxWatermark); - /* Check if using 3-wire mode and the txData is NULL, set the output pin to tristated. */ - temp = base->CFGR1; - temp &= LPSPI_CFGR1_PINCFG_MASK; - if ((temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdiInSdiOut)) || (temp == LPSPI_CFGR1_PINCFG(kLPSPI_SdoInSdoOut))) - { - if (NULL == handle->txData) - { - LPSPI_Enable(base, false); - base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK; - LPSPI_Enable(base, true); - } - /* The 3-wire mode can't send and receive data at the same time. */ - if ((handle->txData != NULL) && (handle->rxData != NULL)) - { - return kStatus_InvalidArgument; - } - } - /*Flush FIFO , clear status , disable all the inerrupts.*/ LPSPI_FlushFifo(base, true, true); LPSPI_ClearStatusFlags(base, (uint32_t)kLPSPI_AllStatusFlag); @@ -1678,7 +1679,7 @@ status_t LPSPI_SlaveTransferNonBlocking(LPSPI_Type *base, lpspi_slave_handle_t * static void LPSPI_SlaveTransferFillUpTxFifo(LPSPI_Type *base, lpspi_slave_handle_t *handle) { - assert(handle); + assert(handle != NULL); uint32_t wordToSend = 0U; uint8_t bytesEachWrite = handle->bytesEachWrite; @@ -1710,7 +1711,7 @@ static void LPSPI_SlaveTransferFillUpTxFifo(LPSPI_Type *base, lpspi_slave_handle static void LPSPI_SlaveTransferComplete(LPSPI_Type *base, lpspi_slave_handle_t *handle) { - assert(handle); + assert(handle != NULL); status_t status = kStatus_Success; @@ -1786,7 +1787,7 @@ status_t LPSPI_SlaveTransferGetCount(LPSPI_Type *base, lpspi_slave_handle_t *han */ void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle) { - assert(handle); + assert(handle != NULL); /* Disable interrupt requests*/ LPSPI_DisableInterrupts(base, (uint32_t)kLPSPI_TxInterruptEnable | (uint32_t)kLPSPI_RxInterruptEnable); @@ -1808,13 +1809,11 @@ void LPSPI_SlaveTransferAbort(LPSPI_Type *base, lpspi_slave_handle_t *handle) */ void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle) { - assert(handle); + assert(handle != NULL); - uint32_t readData; /* variable to store word read from RX FIFO */ - uint32_t wordToSend; /* variable to store word to write to TX FIFO */ - uint8_t bytesEachRead = handle->bytesEachRead; - uint8_t bytesEachWrite = handle->bytesEachWrite; - bool isByteSwap = handle->isByteSwap; + uint32_t readData; /* variable to store word read from RX FIFO */ + uint8_t bytesEachRead = handle->bytesEachRead; + bool isByteSwap = handle->isByteSwap; uint32_t readRegRemainingTimes; if (handle->rxData != NULL) @@ -1843,20 +1842,7 @@ void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle if ((handle->txRemainingByteCount > 0U) && (handle->txData != NULL)) { - if (handle->txRemainingByteCount < (size_t)bytesEachWrite) - { - handle->bytesEachWrite = (uint8_t)handle->txRemainingByteCount; - bytesEachWrite = handle->bytesEachWrite; - } - - wordToSend = LPSPI_CombineWriteData(handle->txData, bytesEachWrite, isByteSwap); - handle->txData += bytesEachWrite; - - /*Decrease the remaining TX byte count.*/ - handle->txRemainingByteCount -= (size_t)bytesEachWrite; - - /*Write the word to TX register*/ - LPSPI_WriteData(base, wordToSend); + LPSPI_SlaveTransferFillUpTxFifo(base, handle); } if (handle->rxRemainingByteCount == 0U) @@ -2019,7 +2005,7 @@ static uint32_t LPSPI_CombineWriteData(uint8_t *txData, uint8_t bytesEachWrite, static void LPSPI_SeparateReadData(uint8_t *rxData, uint32_t readData, uint8_t bytesEachRead, bool isByteSwap) { - assert(rxData); + assert(rxData != NULL); switch (bytesEachRead) { @@ -2111,6 +2097,7 @@ static void LPSPI_CommonIRQHandler(LPSPI_Type *base, void *param) } #if defined(LPSPI0) +void LPSPI0_DriverIRQHandler(void); void LPSPI0_DriverIRQHandler(void) { assert(s_lpspiHandle[0]); @@ -2119,103 +2106,116 @@ void LPSPI0_DriverIRQHandler(void) #endif #if defined(LPSPI1) +void LPSPI1_DriverIRQHandler(void); void LPSPI1_DriverIRQHandler(void) { - assert(s_lpspiHandle[1]); + assert(s_lpspiHandle[1] != NULL); LPSPI_CommonIRQHandler(LPSPI1, s_lpspiHandle[1]); } #endif #if defined(LPSPI2) +void LPSPI2_DriverIRQHandler(void); void LPSPI2_DriverIRQHandler(void) { - assert(s_lpspiHandle[2]); + assert(s_lpspiHandle[2] != NULL); LPSPI_CommonIRQHandler(LPSPI2, s_lpspiHandle[2]); } #endif #if defined(LPSPI3) +void LPSPI3_DriverIRQHandler(void); void LPSPI3_DriverIRQHandler(void) { - assert(s_lpspiHandle[3]); + assert(s_lpspiHandle[3] != NULL); LPSPI_CommonIRQHandler(LPSPI3, s_lpspiHandle[3]); } #endif #if defined(LPSPI4) +void LPSPI4_DriverIRQHandler(void); void LPSPI4_DriverIRQHandler(void) { - assert(s_lpspiHandle[4]); + assert(s_lpspiHandle[4] != NULL); LPSPI_CommonIRQHandler(LPSPI4, s_lpspiHandle[4]); } #endif #if defined(LPSPI5) +void LPSPI5_DriverIRQHandler(void); void LPSPI5_DriverIRQHandler(void) { - assert(s_lpspiHandle[5]); + assert(s_lpspiHandle[5] != NULL); LPSPI_CommonIRQHandler(LPSPI5, s_lpspiHandle[5]); } #endif #if defined(DMA__LPSPI0) +void DMA_SPI0_INT_DriverIRQHandler(void); void DMA_SPI0_INT_DriverIRQHandler(void) { - assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI0)]); + assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI0)] != NULL); LPSPI_CommonIRQHandler(DMA__LPSPI0, s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI0)]); } #endif #if defined(DMA__LPSPI1) +void DMA_SPI1_INT_DriverIRQHandler(void); void DMA_SPI1_INT_DriverIRQHandler(void) { - assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI1)]); + assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI1)] != NULL); LPSPI_CommonIRQHandler(DMA__LPSPI1, s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI1)]); } #endif #if defined(DMA__LPSPI2) +void DMA_SPI2_INT_DriverIRQHandler(void); void DMA_SPI2_INT_DriverIRQHandler(void) { - assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI2)]); + assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI2)] != NULL); LPSPI_CommonIRQHandler(DMA__LPSPI2, s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI2)]); } #endif #if defined(DMA__LPSPI3) +void DMA_SPI3_INT_DriverIRQHandler(void); void DMA_SPI3_INT_DriverIRQHandler(void) { - assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI3)]); + assert(s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI3)] != NULL); LPSPI_CommonIRQHandler(DMA__LPSPI3, s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI3)]); } #endif #if defined(ADMA__LPSPI0) +void ADMA_SPI0_INT_DriverIRQHandler(void); void ADMA_SPI0_INT_DriverIRQHandler(void) { - assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI0)]); + assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI0)] != NULL); LPSPI_CommonIRQHandler(ADMA__LPSPI0, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI0)]); } #endif #if defined(ADMA__LPSPI1) +void ADMA_SPI1_INT_DriverIRQHandler(void); void ADMA_SPI1_INT_DriverIRQHandler(void) { - assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI1)]); + assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI1)] != NULL); LPSPI_CommonIRQHandler(ADMA__LPSPI1, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI1)]); } #endif #if defined(ADMA__LPSPI2) +void ADMA_SPI2_INT_DriverIRQHandler(void); void ADMA_SPI2_INT_DriverIRQHandler(void) { - assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI2)]); + assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI2)] != NULL); LPSPI_CommonIRQHandler(ADMA__LPSPI2, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI2)]); } #endif #if defined(ADMA__LPSPI3) +void ADMA_SPI3_INT_DriverIRQHandler(void); void ADMA_SPI3_INT_DriverIRQHandler(void) { - assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI3)]); + assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI3)] != NULL); LPSPI_CommonIRQHandler(ADMA__LPSPI3, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI3)]); } #endif diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_lpspi.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_lpspi.h index bbb0cda7abf..628877d06fc 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_lpspi.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_lpspi.h @@ -21,8 +21,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief LPSPI driver version 2.0.5. */ -#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 5)) +/*! @brief LPSPI driver version. */ +#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*@}*/ #ifndef LPSPI_DUMMY_DATA @@ -734,6 +734,40 @@ static inline void LPSPI_SetMasterSlaveMode(LPSPI_Type *base, lpspi_master_slave base->CFGR1 = (base->CFGR1 & (~LPSPI_CFGR1_MASTER_MASK)) | LPSPI_CFGR1_MASTER(mode); } +/*! + * @brief Configures the peripheral chip select used for the transfer. + * + * @param base LPSPI peripheral address. + * @param select LPSPI Peripheral Chip Select (PCS) configuration. + */ +static inline void LPSPI_SelectTransferPCS(LPSPI_Type *base, lpspi_which_pcs_t select) +{ + base->TCR = (base->TCR & (~LPSPI_TCR_PCS_MASK)) | LPSPI_TCR_PCS((uint8_t)select); +} + +/*! + * @brief Set the PCS signal to continuous or uncontinuous mode. + * + * @note In master mode, continuous transfer will keep the PCS asserted at the end of the frame size, until a command + * word is received that starts a new frame. So PCS must be set back to uncontinuous when transfer finishes. + * In slave mode, when continuous transfer is enabled, the LPSPI will only transmit the first frame size bits, after + * that the LPSPI will transmit received data back (assuming a 32-bit shift register). + * + * @param base LPSPI peripheral address. + * @param IsContinous True to set the transfer PCS to continuous mode, false to set to uncontinuous mode. + */ +static inline void LPSPI_SetPCSContinous(LPSPI_Type *base, bool IsContinous) +{ + if (IsContinous) + { + base->TCR |= LPSPI_TCR_CONT_MASK; + } + else + { + base->TCR &= LPSPI_TCR_CONT_MASK; + } +} + /*! * @brief Returns whether the LPSPI module is in master mode. * diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_lpuart.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_lpuart.c index fa214550f33..c015d0312af 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_lpuart.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_lpuart.c @@ -300,9 +300,9 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t uint32_t instance = LPUART_GetInstance(base); /* Enable lpuart clock */ - CLOCK_EnableClock(s_lpuartClock[instance]); + (void)CLOCK_EnableClock(s_lpuartClock[instance]); #if defined(LPUART_PERIPH_CLOCKS) - CLOCK_EnableClock(s_lpuartPeriphClocks[instance]); + (void)CLOCK_EnableClock(s_lpuartPeriphClocks[instance]); #endif #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ @@ -488,10 +488,10 @@ void LPUART_Deinit(LPUART_Type *base) uint32_t instance = LPUART_GetInstance(base); /* Disable lpuart clock */ - CLOCK_DisableClock(s_lpuartClock[instance]); + (void)CLOCK_DisableClock(s_lpuartClock[instance]); #if defined(LPUART_PERIPH_CLOCKS) - CLOCK_DisableClock(s_lpuartPeriphClocks[instance]); + (void)CLOCK_DisableClock(s_lpuartPeriphClocks[instance]); #endif #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ @@ -1729,83 +1729,46 @@ void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, lpuart_handle_t *handle) } #if defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART0_LPUART1_RX_DriverIRQHandler(void); void LPUART0_LPUART1_RX_DriverIRQHandler(void) { - uint32_t stat = 0U; - uint32_t ctrl = 0U; - - if (CLOCK_isEnabledClock(s_lpuartClock[0])) + /* If handle is registered, treat the transfer function is enabled. */ + if (NULL != s_lpuartHandle[0]) { - stat = LPUART0->STAT; - ctrl = LPUART0->CTRL; - if ((LPUART_STAT_OR_MASK & stat) || ((LPUART_STAT_RDRF_MASK & stat) && (LPUART_CTRL_RIE_MASK & ctrl))) - { - s_lpuartIsr(LPUART0, s_lpuartHandle[0]); - } + s_lpuartIsr(LPUART0, s_lpuartHandle[0]); } - if (CLOCK_isEnabledClock(s_lpuartClock[1])) + if (NULL != s_lpuartHandle[1]) { - stat = LPUART1->STAT; - ctrl = LPUART1->CTRL; - if ((LPUART_STAT_OR_MASK & stat) || ((LPUART_STAT_RDRF_MASK & stat) && (LPUART_CTRL_RIE_MASK & ctrl))) - { - s_lpuartIsr(LPUART1, s_lpuartHandle[1]); - } + s_lpuartIsr(LPUART1, s_lpuartHandle[1]); } SDK_ISR_EXIT_BARRIER; } +void LPUART0_LPUART1_TX_DriverIRQHandler(void); void LPUART0_LPUART1_TX_DriverIRQHandler(void) { - uint32_t stat = 0U; - uint32_t ctrl = 0U; - - if (CLOCK_isEnabledClock(s_lpuartClock[0])) + /* If handle is registered, treat the transfer function is enabled. */ + if (NULL != s_lpuartHandle[0]) { - stat = LPUART0->STAT; - ctrl = LPUART0->CTRL; - if ((LPUART_STAT_OR_MASK & stat) || ((stat & LPUART_STAT_TDRE_MASK) && (ctrl & LPUART_CTRL_TIE_MASK))) - { - s_lpuartIsr(LPUART0, s_lpuartHandle[0]); - } + s_lpuartIsr(LPUART0, s_lpuartHandle[0]); } - if (CLOCK_isEnabledClock(s_lpuartClock[1])) + if (NULL != s_lpuartHandle[1]) { - stat = LPUART1->STAT; - ctrl = LPUART1->CTRL; - if ((LPUART_STAT_OR_MASK & stat) || ((stat & LPUART_STAT_TDRE_MASK) && (ctrl & LPUART_CTRL_TIE_MASK))) - { - s_lpuartIsr(LPUART1, s_lpuartHandle[1]); - } + s_lpuartIsr(LPUART1, s_lpuartHandle[1]); } SDK_ISR_EXIT_BARRIER; } #else +void LPUART0_LPUART1_DriverIRQHandler(void); void LPUART0_LPUART1_DriverIRQHandler(void) { - uint32_t stat = 0U; - uint32_t ctrl = 0U; - - if (CLOCK_isEnabledClock(s_lpuartClock[0])) + /* If handle is registered, treat the transfer function is enabled. */ + if (NULL != s_lpuartHandle[0]) { - stat = LPUART0->STAT; - ctrl = LPUART0->CTRL; - if ((0U != (LPUART_STAT_OR_MASK & stat)) || - ((0U != (LPUART_STAT_RDRF_MASK & stat)) && (0U != (LPUART_CTRL_RIE_MASK & ctrl))) || - ((0U != (stat & LPUART_STAT_TDRE_MASK)) && (0U != (ctrl & LPUART_CTRL_TIE_MASK)))) - { - s_lpuartIsr(LPUART0, s_lpuartHandle[0]); - } + s_lpuartIsr(LPUART0, s_lpuartHandle[0]); } - if (CLOCK_isEnabledClock(s_lpuartClock[1])) + if (NULL != s_lpuartHandle[1]) { - stat = LPUART1->STAT; - ctrl = LPUART1->CTRL; - if ((0U != (LPUART_STAT_OR_MASK & stat)) || - ((0U != (LPUART_STAT_RDRF_MASK & stat)) && (0U != (LPUART_CTRL_RIE_MASK & ctrl))) || - ((0U != (stat & LPUART_STAT_TDRE_MASK)) && (0U != (ctrl & LPUART_CTRL_TIE_MASK)))) - { - s_lpuartIsr(LPUART1, s_lpuartHandle[1]); - } + s_lpuartIsr(LPUART1, s_lpuartHandle[1]); } SDK_ISR_EXIT_BARRIER; } @@ -1815,17 +1778,20 @@ void LPUART0_LPUART1_DriverIRQHandler(void) #if defined(LPUART0) #if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART0_TX_DriverIRQHandler(void); void LPUART0_TX_DriverIRQHandler(void) { s_lpuartIsr(LPUART0, s_lpuartHandle[0]); SDK_ISR_EXIT_BARRIER; } +void LPUART0_RX_DriverIRQHandler(void); void LPUART0_RX_DriverIRQHandler(void) { s_lpuartIsr(LPUART0, s_lpuartHandle[0]); SDK_ISR_EXIT_BARRIER; } #else +void LPUART0_DriverIRQHandler(void); void LPUART0_DriverIRQHandler(void) { s_lpuartIsr(LPUART0, s_lpuartHandle[0]); @@ -1838,17 +1804,20 @@ void LPUART0_DriverIRQHandler(void) #if defined(LPUART1) #if !(defined(FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) && FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1) #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART1_TX_DriverIRQHandler(void); void LPUART1_TX_DriverIRQHandler(void) { s_lpuartIsr(LPUART1, s_lpuartHandle[1]); SDK_ISR_EXIT_BARRIER; } +void LPUART1_RX_DriverIRQHandler(void); void LPUART1_RX_DriverIRQHandler(void) { s_lpuartIsr(LPUART1, s_lpuartHandle[1]); SDK_ISR_EXIT_BARRIER; } #else +void LPUART1_DriverIRQHandler(void); void LPUART1_DriverIRQHandler(void) { s_lpuartIsr(LPUART1, s_lpuartHandle[1]); @@ -1860,17 +1829,20 @@ void LPUART1_DriverIRQHandler(void) #if defined(LPUART2) #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART2_TX_DriverIRQHandler(void); void LPUART2_TX_DriverIRQHandler(void) { s_lpuartIsr(LPUART2, s_lpuartHandle[2]); SDK_ISR_EXIT_BARRIER; } +void LPUART2_RX_DriverIRQHandler(void); void LPUART2_RX_DriverIRQHandler(void) { s_lpuartIsr(LPUART2, s_lpuartHandle[2]); SDK_ISR_EXIT_BARRIER; } #else +void LPUART2_DriverIRQHandler(void); void LPUART2_DriverIRQHandler(void) { s_lpuartIsr(LPUART2, s_lpuartHandle[2]); @@ -1881,17 +1853,20 @@ void LPUART2_DriverIRQHandler(void) #if defined(LPUART3) #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART3_TX_DriverIRQHandler(void); void LPUART3_TX_DriverIRQHandler(void) { s_lpuartIsr(LPUART3, s_lpuartHandle[3]); SDK_ISR_EXIT_BARRIER; } +void LPUART3_RX_DriverIRQHandler(void); void LPUART3_RX_DriverIRQHandler(void) { s_lpuartIsr(LPUART3, s_lpuartHandle[3]); SDK_ISR_EXIT_BARRIER; } #else +void LPUART3_DriverIRQHandler(void); void LPUART3_DriverIRQHandler(void) { s_lpuartIsr(LPUART3, s_lpuartHandle[3]); @@ -1902,17 +1877,20 @@ void LPUART3_DriverIRQHandler(void) #if defined(LPUART4) #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART4_TX_DriverIRQHandler(void); void LPUART4_TX_DriverIRQHandler(void) { s_lpuartIsr(LPUART4, s_lpuartHandle[4]); SDK_ISR_EXIT_BARRIER; } +void LPUART4_RX_DriverIRQHandler(void); void LPUART4_RX_DriverIRQHandler(void) { s_lpuartIsr(LPUART4, s_lpuartHandle[4]); SDK_ISR_EXIT_BARRIER; } #else +void LPUART4_DriverIRQHandler(void); void LPUART4_DriverIRQHandler(void) { s_lpuartIsr(LPUART4, s_lpuartHandle[4]); @@ -1923,17 +1901,20 @@ void LPUART4_DriverIRQHandler(void) #if defined(LPUART5) #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART5_TX_DriverIRQHandler(void); void LPUART5_TX_DriverIRQHandler(void) { s_lpuartIsr(LPUART5, s_lpuartHandle[5]); SDK_ISR_EXIT_BARRIER; } +void LPUART5_RX_DriverIRQHandler(void); void LPUART5_RX_DriverIRQHandler(void) { s_lpuartIsr(LPUART5, s_lpuartHandle[5]); SDK_ISR_EXIT_BARRIER; } #else +void LPUART5_DriverIRQHandler(void); void LPUART5_DriverIRQHandler(void) { s_lpuartIsr(LPUART5, s_lpuartHandle[5]); @@ -1944,17 +1925,20 @@ void LPUART5_DriverIRQHandler(void) #if defined(LPUART6) #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART6_TX_DriverIRQHandler(void); void LPUART6_TX_DriverIRQHandler(void) { s_lpuartIsr(LPUART6, s_lpuartHandle[6]); SDK_ISR_EXIT_BARRIER; } +void LPUART6_RX_DriverIRQHandler(void); void LPUART6_RX_DriverIRQHandler(void) { s_lpuartIsr(LPUART6, s_lpuartHandle[6]); SDK_ISR_EXIT_BARRIER; } #else +void LPUART6_DriverIRQHandler(void); void LPUART6_DriverIRQHandler(void) { s_lpuartIsr(LPUART6, s_lpuartHandle[6]); @@ -1965,17 +1949,20 @@ void LPUART6_DriverIRQHandler(void) #if defined(LPUART7) #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART7_TX_DriverIRQHandler(void); void LPUART7_TX_DriverIRQHandler(void) { s_lpuartIsr(LPUART7, s_lpuartHandle[7]); SDK_ISR_EXIT_BARRIER; } +void LPUART7_RX_DriverIRQHandler(void); void LPUART7_RX_DriverIRQHandler(void) { s_lpuartIsr(LPUART7, s_lpuartHandle[7]); SDK_ISR_EXIT_BARRIER; } #else +void LPUART7_DriverIRQHandler(void); void LPUART7_DriverIRQHandler(void) { s_lpuartIsr(LPUART7, s_lpuartHandle[7]); @@ -1986,17 +1973,20 @@ void LPUART7_DriverIRQHandler(void) #if defined(LPUART8) #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART8_TX_DriverIRQHandler(void); void LPUART8_TX_DriverIRQHandler(void) { s_lpuartIsr(LPUART8, s_lpuartHandle[8]); SDK_ISR_EXIT_BARRIER; } +void LPUART8_RX_DriverIRQHandler(void); void LPUART8_RX_DriverIRQHandler(void) { s_lpuartIsr(LPUART8, s_lpuartHandle[8]); SDK_ISR_EXIT_BARRIER; } #else +void LPUART8_DriverIRQHandler(void); void LPUART8_DriverIRQHandler(void) { s_lpuartIsr(LPUART8, s_lpuartHandle[8]); @@ -2007,17 +1997,20 @@ void LPUART8_DriverIRQHandler(void) #if defined(LPUART9) #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART9_TX_DriverIRQHandler(void); void LPUART9_TX_DriverIRQHandler(void) { s_lpuartIsr(LPUART9, s_lpuartHandle[9]); SDK_ISR_EXIT_BARRIER; } +void LPUART9_RX_DriverIRQHandler(void); void LPUART9_RX_DriverIRQHandler(void) { s_lpuartIsr(LPUART9, s_lpuartHandle[9]); SDK_ISR_EXIT_BARRIER; } #else +void LPUART9_DriverIRQHandler(void); void LPUART9_DriverIRQHandler(void) { s_lpuartIsr(LPUART9, s_lpuartHandle[9]); @@ -2028,17 +2021,20 @@ void LPUART9_DriverIRQHandler(void) #if defined(LPUART10) #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART10_TX_DriverIRQHandler(void); void LPUART10_TX_DriverIRQHandler(void) { s_lpuartIsr(LPUART10, s_lpuartHandle[10]); SDK_ISR_EXIT_BARRIER; } +void LPUART10_RX_DriverIRQHandler(void); void LPUART10_RX_DriverIRQHandler(void) { s_lpuartIsr(LPUART10, s_lpuartHandle[10]); SDK_ISR_EXIT_BARRIER; } #else +void LPUART10_DriverIRQHandler(void); void LPUART10_DriverIRQHandler(void) { s_lpuartIsr(LPUART10, s_lpuartHandle[10]); @@ -2049,17 +2045,20 @@ void LPUART10_DriverIRQHandler(void) #if defined(LPUART11) #if defined(FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ) && FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ +void LPUART11_TX_DriverIRQHandler(void); void LPUART11_TX_DriverIRQHandler(void) { s_lpuartIsr(LPUART11, s_lpuartHandle[11]); SDK_ISR_EXIT_BARRIER; } +void LPUART11_RX_DriverIRQHandler(void); void LPUART11_RX_DriverIRQHandler(void) { s_lpuartIsr(LPUART11, s_lpuartHandle[11]); SDK_ISR_EXIT_BARRIER; } #else +void LPUART11_DriverIRQHandler(void); void LPUART11_DriverIRQHandler(void) { s_lpuartIsr(LPUART11, s_lpuartHandle[11]); @@ -2069,6 +2068,7 @@ void LPUART11_DriverIRQHandler(void) #endif #if defined(CM4_0__LPUART) +void M4_0_LPUART_DriverIRQHandler(void); void M4_0_LPUART_DriverIRQHandler(void) { s_lpuartIsr(CM4_0__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4_0__LPUART)]); @@ -2077,6 +2077,7 @@ void M4_0_LPUART_DriverIRQHandler(void) #endif #if defined(CM4_1__LPUART) +void M4_1_LPUART_DriverIRQHandler(void); void M4_1_LPUART_DriverIRQHandler(void) { s_lpuartIsr(CM4_1__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4_1__LPUART)]); @@ -2085,6 +2086,7 @@ void M4_1_LPUART_DriverIRQHandler(void) #endif #if defined(CM4__LPUART) +void M4_LPUART_DriverIRQHandler(void); void M4_LPUART_DriverIRQHandler(void) { s_lpuartIsr(CM4__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4__LPUART)]); @@ -2093,6 +2095,7 @@ void M4_LPUART_DriverIRQHandler(void) #endif #if defined(DMA__LPUART0) +void DMA_UART0_INT_DriverIRQHandler(void); void DMA_UART0_INT_DriverIRQHandler(void) { s_lpuartIsr(DMA__LPUART0, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART0)]); @@ -2101,6 +2104,7 @@ void DMA_UART0_INT_DriverIRQHandler(void) #endif #if defined(DMA__LPUART1) +void DMA_UART1_INT_DriverIRQHandler(void); void DMA_UART1_INT_DriverIRQHandler(void) { s_lpuartIsr(DMA__LPUART1, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART1)]); @@ -2109,6 +2113,7 @@ void DMA_UART1_INT_DriverIRQHandler(void) #endif #if defined(DMA__LPUART2) +void DMA_UART2_INT_DriverIRQHandler(void); void DMA_UART2_INT_DriverIRQHandler(void) { s_lpuartIsr(DMA__LPUART2, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART2)]); @@ -2117,6 +2122,7 @@ void DMA_UART2_INT_DriverIRQHandler(void) #endif #if defined(DMA__LPUART3) +void DMA_UART3_INT_DriverIRQHandler(void); void DMA_UART3_INT_DriverIRQHandler(void) { s_lpuartIsr(DMA__LPUART3, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART3)]); @@ -2125,6 +2131,7 @@ void DMA_UART3_INT_DriverIRQHandler(void) #endif #if defined(DMA__LPUART4) +void DMA_UART4_INT_DriverIRQHandler(void); void DMA_UART4_INT_DriverIRQHandler(void) { s_lpuartIsr(DMA__LPUART4, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART4)]); @@ -2133,6 +2140,7 @@ void DMA_UART4_INT_DriverIRQHandler(void) #endif #if defined(ADMA__LPUART0) +void ADMA_UART0_INT_DriverIRQHandler(void); void ADMA_UART0_INT_DriverIRQHandler(void) { s_lpuartIsr(ADMA__LPUART0, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART0)]); @@ -2141,6 +2149,7 @@ void ADMA_UART0_INT_DriverIRQHandler(void) #endif #if defined(ADMA__LPUART1) +void ADMA_UART1_INT_DriverIRQHandler(void); void ADMA_UART1_INT_DriverIRQHandler(void) { s_lpuartIsr(ADMA__LPUART1, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART1)]); @@ -2149,6 +2158,7 @@ void ADMA_UART1_INT_DriverIRQHandler(void) #endif #if defined(ADMA__LPUART2) +void ADMA_UART2_INT_DriverIRQHandler(void); void ADMA_UART2_INT_DriverIRQHandler(void) { s_lpuartIsr(ADMA__LPUART2, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART2)]); @@ -2157,6 +2167,7 @@ void ADMA_UART2_INT_DriverIRQHandler(void) #endif #if defined(ADMA__LPUART3) +void ADMA_UART3_INT_DriverIRQHandler(void); void ADMA_UART3_INT_DriverIRQHandler(void) { s_lpuartIsr(ADMA__LPUART3, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART3)]); diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_lpuart.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_lpuart.h index de224e11fd5..062b8994dc3 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_lpuart.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_lpuart.h @@ -21,8 +21,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief LPUART driver version 2.4.0. */ -#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 4, 0)) +/*! @brief LPUART driver version. */ +#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 4, 1)) /*@}*/ /*! @brief Retry times for waiting flag. */ diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_pit.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_pit.h index 1de4984358f..2b035d41adc 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_pit.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_pit.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2015, Freescale Semiconductor, Inc. - * Copyright 2016-2017 NXP + * Copyright 2016-2020 NXP * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -21,8 +21,8 @@ /*! @name Driver version */ /*@{*/ -/*! @brief PIT Driver Version 2.0.2 */ -#define FSL_PIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) +/*! @brief PIT Driver Version 2.0.4 */ +#define FSL_PIT_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) /*@}*/ /*! @@ -245,7 +245,9 @@ static inline void PIT_ClearStatusFlags(PIT_Type *base, pit_chnl_t channel, uint */ static inline void PIT_SetTimerPeriod(PIT_Type *base, pit_chnl_t channel, uint32_t count) { - base->CHANNEL[channel].LDVAL = count; + assert(count != 0U); + /* According to RM, the LDVAL trigger = clock ticks -1 */ + base->CHANNEL[channel].LDVAL = count - 1U; } /*! diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_pmu.c b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_pmu.c index 838f4f95609..60ccc7ff30d 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_pmu.c +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_pmu.c @@ -21,43 +21,7 @@ #define PMU_POWER_DETECT_CTRL_REGISTER (ANADIG_PMU->PMU_POWER_DETECT_CTRL) -#define PMU_BANDGAP_ANALOG_CTRL0_REGISTER_ADDRESS (0x00U) - -#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_PWD_MASK (0x1U) - -#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_PWD_OPTION_MASK (0x7U) -#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_PWD_OPTION_SHIFT (0U) -#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_PWD_OPTION(x) \ - (((uint32_t)(((uint32_t)(x)) << PMU_BANDGAP_ANALOG_CTRL0_REFTOP_PWD_OPTION_SHIFT)) & \ - PMU_BANDGAP_ANALOG_CTRL0_REFTOP_PWD_OPTION_MASK) - -#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_LOWPOWER_MASK (0x8U) -#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_LOWPOWER_SHIFT (3U) -#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_LOWPOWER(x) \ - (((uint32_t)(((uint32_t)(x)) << PMU_BANDGAP_ANALOG_CTRL0_REFTOP_LOWPOWER_SHIFT)) & \ - PMU_BANDGAP_ANALOG_CTRL0_REFTOP_LOWPOWER_MASK) - -#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_SELFBIASOFF_MASK (0x10U) -#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_SELFBIASOFF_SHIFT (4U) -#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_SELFBIASOFF(x) \ - (((uint32_t)(((uint32_t)(x)) << PMU_BANDGAP_ANALOG_CTRL0_REFTOP_SELFBIASOFF_SHIFT)) & \ - PMU_BANDGAP_ANALOG_CTRL0_REFTOP_SELFBIASOFF_MASK) - -#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_VBGADJ_MASK (0xE0U) -#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_VBGADJ_SHIFT (5U) -#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_VBGADJ(x) \ - (((uint32_t)(((uint32_t)(x)) << PMU_BANDGAP_ANALOG_CTRL0_REFTOP_VBGADJ_SHIFT)) & \ - PMU_BANDGAP_ANALOG_CTRL0_REFTOP_VBGADJ_MASK) - -#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_IBZTCADJ_MASK (0x1C00U) -#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_IBZTCADJ_SHIFT (10U) -#define PMU_BANDGAP_ANALOG_CTRL0_REFTOP_IBZTCADJ(x) \ - (((uint32_t)(((uint32_t)(x)) << PMU_BANDGAP_ANALOG_CTRL0_REFTOP_IBZTCADJ_SHIFT)) & \ - PMU_BANDGAP_ANALOG_CTRL0_REFTOP_IBZTCADJ_MASK) - -#define PMU_BANDGAP_ANALOG_STATUS_REGISTER_ADDRESS (0x50U) - -#define PMU_BANDGAP_ANALOG_STATUS_REFTOP_VBGUP_MASK (0x01U) +#define PMU_BIAS_CTRL_WB_CFG_1P8_WELL_SELECT_MASK (0x1U) #define PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD_MASK (0x2U) #define PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD_SHIFT 1U @@ -77,57 +41,65 @@ (((uint32_t)(((uint32_t)(x)) << PMU_BIAS_CTRL_WB_CFG_1P8_OSCILLATOR_FREQ_SHIFT)) & \ PMU_BIAS_CTRL_WB_CFG_1P8_OSCILLATOR_FREQ_MASK) -#define PMU_LDO_ENABLE_SETPOINT_REGISTERS \ - { \ - (uint32_t)(&ANADIG_PMU->LDO_PLL_ENABLE_SP), (uint32_t)(&ANADIG_PMU->LDO_LPSR_ANA_ENABLE_SP), \ - (uint32_t)(&ANADIG_PMU->LDO_LPSR_DIG_ENABLE_SP), 0UL \ +#define PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(member) \ + ((uint32_t)((ANADIG_PMU_BASE) + (uint32_t)offsetof(ANADIG_PMU_Type, member))) + +#define PMU_LDO_ENABLE_SETPOINT_REGISTERS \ + { \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_PLL_ENABLE_SP), \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_ANA_ENABLE_SP), \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_ENABLE_SP), 0UL \ } -#define PMU_LDO_LP_MODE_EN_SETPOINT_REGISTERS \ - { \ - 0UL, (uint32_t)(&ANADIG_PMU->LDO_LPSR_ANA_LP_MODE_SP), (uint32_t)(&ANADIG_PMU->LDO_LPSR_DIG_LP_MODE_SP), 0UL \ +#define PMU_LDO_LP_MODE_EN_SETPOINT_REGISTERS \ + { \ + 0UL, PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_ANA_LP_MODE_SP), \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_LP_MODE_SP), 0UL \ } -#define PMU_LDO_TRACKING_EN_SETPOINT_REGISTERS \ - { \ - 0UL, (uint32_t)(&ANADIG_PMU->LDO_LPSR_ANA_TRACKING_EN_SP), \ - (uint32_t)(&ANADIG_PMU->LDO_LPSR_DIG_TRACKING_EN_SP), 0UL \ +#define PMU_LDO_TRACKING_EN_SETPOINT_REGISTERS \ + { \ + 0UL, PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_ANA_TRACKING_EN_SP), \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_TRACKING_EN_SP), 0UL \ } -#define PMU_LDO_BYPASS_EN_SETPOINT_REGISTERS \ - { \ - 0UL, (uint32_t)(&ANADIG_PMU->LDO_LPSR_ANA_BYPASS_EN_SP), (uint32_t)(&ANADIG_PMU->LDO_LPSR_DIG_BYPASS_EN_SP), \ - 0UL \ +#define PMU_LDO_BYPASS_EN_SETPOINT_REGISTERS \ + { \ + 0UL, PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_ANA_BYPASS_EN_SP), \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_BYPASS_EN_SP), 0UL \ } -#define PMU_LDO_STBY_EN_REGISTERS \ - { \ - (uint32_t)(&ANADIG_PMU->PLL_LDO_STBY_EN_SP), (uint32_t)(&ANADIG_PMU->LDO_LPSR_ANA_STBY_EN_SP), \ - (uint32_t)(&ANADIG_PMU->LDO_LPSR_DIG_STBY_EN_SP), 0UL \ +#define PMU_LDO_STBY_EN_REGISTERS \ + { \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(PLL_LDO_STBY_EN_SP), \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_ANA_STBY_EN_SP), \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_STBY_EN_SP), 0UL \ } -#define PMU_LPSR_DIG_TRG_REGISTERS \ - { \ - (uint32_t)(&ANADIG_PMU->LDO_LPSR_DIG_TRG_SP0), (uint32_t)(&ANADIG_PMU->LDO_LPSR_DIG_TRG_SP1), \ - (uint32_t)(&ANADIG_PMU->LDO_LPSR_DIG_TRG_SP2), (uint32_t)(&ANADIG_PMU->LDO_LPSR_DIG_TRG_SP3) \ +#define PMU_LPSR_DIG_TRG_REGISTERS \ + { \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_TRG_SP0), \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_TRG_SP1), \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_TRG_SP2), \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(LDO_LPSR_DIG_TRG_SP3) \ } -#define PMU_BODY_BIAS_ENABLE_REGISTERS \ - { \ - (uint32_t)(&ANADIG_PMU->FBB_M7_ENABLE_SP), (uint32_t)(&ANADIG_PMU->RBB_SOC_ENABLE_SP), \ - (uint32_t)(&ANADIG_PMU->RBB_LPSR_ENABLE_SP) \ +#define PMU_BODY_BIAS_ENABLE_REGISTERS \ + { \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(FBB_M7_ENABLE_SP), PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_SOC_ENABLE_SP), \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_LPSR_ENABLE_SP) \ } -#define PMU_BODY_BIAS_STBY_EN_REGISTERS \ - { \ - (uint32_t)(&ANADIG_PMU->FBB_M7_STBY_EN_SP), (uint32_t)(&ANADIG_PMU->RBB_SOC_STBY_EN_SP), \ - (uint32_t)(&ANADIG_PMU->RBB_LPSR_STBY_EN_SP) \ +#define PMU_BODY_BIAS_STBY_EN_REGISTERS \ + { \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(FBB_M7_STBY_EN_SP), PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_SOC_STBY_EN_SP), \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_LPSR_STBY_EN_SP) \ } -#define PMU_BODY_BIAS_CONFIGURE_REGISTERS \ - { \ - (uint32_t)(&ANADIG_PMU->FBB_M7_CONFIGURE), (uint32_t)(&ANADIG_PMU->RBB_SOC_CONFIGURE), \ - (uint32_t)(&ANADIG_PMU->RBB_LPSR_CONFIGURE) \ +#define PMU_BODY_BIAS_CONFIGURE_REGISTERS \ + { \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(FBB_M7_CONFIGURE), PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_SOC_CONFIGURE), \ + PMU_GET_ANADIG_PMU_MEMBER_ADDRESS(RBB_LPSR_CONFIGURE) \ } /******************************************************************************* @@ -146,7 +118,7 @@ * brief Selects the control mode of the PLL LDO. * * param base PMU peripheral base address. - * param mode The control mode of the PLL LDO. Please refer to @ref pmu_control_mode_t. + * param mode The control mode of the PLL LDO. Please refer to pmu_control_mode_t. */ void PMU_SetPllLdoControlMode(ANADIG_PMU_Type *base, pmu_control_mode_t mode) { @@ -186,11 +158,14 @@ void PMU_StaticEnablePllLdo(ANADIG_PMU_Type *base) { uint32_t temp32; - temp32 = ANATOP_AI_Read(kAI_Itf_Ldo, 0U); + temp32 = ANATOP_AI_Read(kAI_Itf_Ldo, kAI_PHY_LDO_CTRL0); - if (temp32 != 0x105UL) + if (temp32 != + (AI_PHY_LDO_CTRL0_OUTPUT_TRG(0x10) | AI_PHY_LDO_CTRL0_LINREG_EN_MASK | AI_PHY_LDO_CTRL0_LIMIT_EN_MASK)) { - ANATOP_AI_Write(kAI_Itf_Ldo, 0U, 0x105UL); + ANATOP_AI_Write( + kAI_Itf_Ldo, kAI_PHY_LDO_CTRL0, + (AI_PHY_LDO_CTRL0_OUTPUT_TRG(0x10) | AI_PHY_LDO_CTRL0_LINREG_EN_MASK | AI_PHY_LDO_CTRL0_LIMIT_EN_MASK)); SDK_DelayAtLeastUs(1, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* Enable Voltage Reference for PLLs before those PLLs were enabled. */ @@ -205,14 +180,14 @@ void PMU_StaticEnablePllLdo(ANADIG_PMU_Type *base) */ void PMU_StaticDisablePllLdo(void) { - ANATOP_AI_Write(kAI_Itf_Ldo, 0U, 0UL); + ANATOP_AI_Write(kAI_Itf_Ldo, kAI_PHY_LDO_CTRL0, 0UL); } /*! * brief Selects the control mode of the LPSR ANA LDO. * * param base PMU peripheral base address. - * param mode The control mode of the LPSR ANA LDO. Please refer to @ref pmu_control_mode_t. + * param mode The control mode of the LPSR ANA LDO. Please refer to pmu_control_mode_t. */ void PMU_SetLpsrAnaLdoControlMode(ANADIG_LDO_SNVS_Type *base, pmu_control_mode_t mode) { @@ -230,13 +205,13 @@ void PMU_SetLpsrAnaLdoControlMode(ANADIG_LDO_SNVS_Type *base, pmu_control_mode_t * brief Sets the Bypass mode of the LPSR ANA LDO. * * param base ANADIG_LDO_SNVS peripheral base address. - * param bypassMode The Bypass mode of LPSR ANA LDO. Please refer to @ref pmu_lpsr_ana_ldo_bypass_mode_t. + * param enable Enable/Disable bypass mode. + * - \b true Enable LPSR ANA Bypass mode. + * - \b false Disable LPSR ANA Bypass mode. */ -void PMU_StaticSetLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS_Type *base, pmu_lpsr_ana_ldo_bypass_mode_t bypassMode) +void PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS_Type *base, bool enable) { - uint32_t temp32; - - if (bypassMode == kPMU_LpsrAnaLdoBypassModeDisable) + if (enable == false) { /* Enable LPSR ANA LDO and HP mode. */ base->PMU_LDO_LPSR_ANA &= @@ -244,8 +219,7 @@ void PMU_StaticSetLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS_Type *base, pmu_lpsr_ana_ SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* Clear Bypass. */ - base->PMU_LDO_LPSR_ANA &= ~(ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK | - ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_CFG_MASK); + base->PMU_LDO_LPSR_ANA &= ~(ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK); SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* Disable Tracking mode. */ @@ -261,12 +235,8 @@ void PMU_StaticSetLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS_Type *base, pmu_lpsr_ana_ base->PMU_LDO_LPSR_ANA |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_MASK; SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - /* Enabled Bypass and set bypass mode. */ - temp32 = base->PMU_LDO_LPSR_ANA; - temp32 &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_CFG_MASK; - temp32 |= (ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_CFG(bypassMode) | - ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK); - base->PMU_LDO_LPSR_ANA = temp32; + /* Enabled Bypass. */ + base->PMU_LDO_LPSR_ANA |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK; SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* Disable LPSR ANA LDO. */ @@ -299,15 +269,11 @@ void PMU_StaticGetLpsrAnaLdoDefaultConfig(pmu_static_lpsr_ana_ldo_config_t *conf (void)memset(config, 0, sizeof(*config)); - config->mode = kPMU_HighPowerMode; - config->enable2mALoad = true; - config->enable20uALoad = false; - config->enable4mALoad = true; - config->enableStandbyMode = false; - config->driverStrength = kPMU_LpsrAnaLdoDriverStrength0; - config->brownOutDetectorConfig = kPMU_LpsrAnaLdoBrownOutDetectorDisable; - config->chargePumpCurrent = kPMU_LpsrAnaChargePump300nA; - config->outputRange = kPMU_LpsrAnaLdoOutputFrom1P77To1P83; + config->mode = kPMU_HighPowerMode; + config->enable2mALoad = true; + config->enable20uALoad = false; + config->enable4mALoad = true; + config->enableStandbyMode = false; } /*! @@ -326,10 +292,7 @@ void PMU_StaticLpsrAnaLdoInit(ANADIG_LDO_SNVS_Type *base, const pmu_static_lpsr_ regValue &= ~(ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_MASK | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_MASK | - ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_MASK | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_MASK | - ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_PRECHRG_CURRENT_CFG_MASK | - ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ICP_TRIM_SNVS_MASK | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRIM_MASK | - ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BO_EN_MASK | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BO_OFFSET_MASK); + ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_MASK | ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_MASK); if ((config->mode) == kPMU_LowPowerMode) { @@ -339,14 +302,7 @@ void PMU_StaticLpsrAnaLdoInit(ANADIG_LDO_SNVS_Type *base, const pmu_static_lpsr_ regValue |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN(config->enable4mALoad); regValue |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN(config->enable20uALoad); regValue |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN(config->enableStandbyMode); - regValue |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_PRECHRG_CURRENT_CFG(config->driverStrength); - regValue |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ICP_TRIM_SNVS(config->chargePumpCurrent); - regValue |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRIM(config->outputRange); - if (config->brownOutDetectorConfig != kPMU_LpsrAnaLdoBrownOutDetectorDisable) - { - regValue |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BO_EN_MASK | - ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BO_OFFSET(config->brownOutDetectorConfig); - } + base->PMU_LDO_LPSR_ANA = regValue; /* Enable LPSR ANA DIG. */ @@ -368,7 +324,7 @@ void PMU_StaticLpsrAnaLdoDeinit(ANADIG_LDO_SNVS_Type *base) * brief Selects the control mode of the LPSR DIG LDO. * * param base ANADIG_LDO_SNVS peripheral base address. - * param mode The control mode of the LPSR DIG LDO. Please refer to @ref pmu_control_mode_t. + * param mode The control mode of the LPSR DIG LDO. Please refer to pmu_control_mode_t. */ void PMU_SetLpsrDigLdoControlMode(ANADIG_LDO_SNVS_Type *base, pmu_control_mode_t mode) { @@ -394,10 +350,6 @@ void PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS_Type *base, bool enabl { if (enable) { - /* HP mode */ - base->PMU_LDO_LPSR_DIG |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_HP_EN_MASK; - SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); - /* tracking */ base->PMU_LDO_LPSR_DIG |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_MASK; SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); @@ -412,8 +364,7 @@ void PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS_Type *base, bool enabl else { /* Enable LPSR DIG LDO and HP mode */ - base->PMU_LDO_LPSR_DIG |= - (ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK | ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_HP_EN_MASK); + base->PMU_LDO_LPSR_DIG |= (ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK); SDK_DelayAtLeastUs(1000, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); /* Clear BYPASS */ @@ -437,11 +388,8 @@ void PMU_StaticGetLpsrDigLdoDefaultConfig(pmu_static_lpsr_dig_config_t *config) (void)memset(config, 0, sizeof(*config)); - config->enableStableDetect = false; - config->voltageStepTime = kPMU_LpsrDigVoltageStepInc50us; - config->brownOutConfig = kPMU_LpsrDigBrownOutDisable; - config->targetVoltage = kPMU_LpsrDigTargetStableVoltage1P0V; - config->mode = kPMU_HighPowerMode; + config->voltageStepTime = kPMU_LpsrDigVoltageStepInc50us; + config->targetVoltage = kPMU_LpsrDigTargetStableVoltage1P0V; } /*! @@ -457,18 +405,8 @@ void PMU_StaticLpsrDigLdoInit(ANADIG_LDO_SNVS_Type *base, const pmu_static_lpsr_ uint32_t temp32 = base->PMU_LDO_LPSR_DIG; - temp32 &= ~(ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TEST_OVERRIDE_MASK | ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BO_OFFSET_MASK | - ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_RBB_STABLE_DETECT_MASK | ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRIM_MASK | - ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_HP_EN_MASK); - - if (config->brownOutConfig != kPMU_LpsrDigBrownOutDisable) - { - temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TEST_OVERRIDE_MASK; - temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BO_OFFSET(config->brownOutConfig); - } - temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_RBB_STABLE_DETECT(config->enableStableDetect); - temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRIM(config->targetVoltage); - temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_HP_EN(config->mode); + temp32 &= ~ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_MASK; + temp32 |= ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT(config->targetVoltage); base->PMU_LDO_LPSR_DIG = temp32; temp32 = base->PMU_LDO_LPSR_DIG_2; @@ -503,8 +441,8 @@ void PMU_StaticLpsrDigLdoDeinit(ANADIG_LDO_SNVS_Type *base) */ void PMU_GPCSetLpsrDigLdoTargetVoltage(uint32_t setpointMap, pmu_lpsr_dig_target_output_voltage_t voltageValue) { - uint32_t regValue = 0UL; - uint32_t lpsrDigTrgRegArray[] = PMU_LPSR_DIG_TRG_REGISTERS; + uint32_t regValue = 0UL; + const uint32_t lpsrDigTrgRegArray[] = PMU_LPSR_DIG_TRG_REGISTERS; uint8_t regIndex; uint8_t temp8; uint32_t i; @@ -520,7 +458,7 @@ void PMU_GPCSetLpsrDigLdoTargetVoltage(uint32_t setpointMap, pmu_lpsr_dig_target if (((temp8 >> (1U * i)) & 0x1U) != 0U) { regValue &= ~(0xFFUL << (PMU_LDO_LPSR_DIG_TRG_SPX_VOLTAGE_SETPOINTX_BIT_WIDTH * i)); - regValue |= voltageValue << (PMU_LDO_LPSR_DIG_TRG_SPX_VOLTAGE_SETPOINTX_BIT_WIDTH * i); + regValue |= (uint32_t)voltageValue << (PMU_LDO_LPSR_DIG_TRG_SPX_VOLTAGE_SETPOINTX_BIT_WIDTH * i); } } (*(volatile uint32_t *)lpsrDigTrgRegArray[regIndex]) = regValue; @@ -541,7 +479,7 @@ void PMU_GPCSetLpsrDigLdoTargetVoltage(uint32_t setpointMap, pmu_lpsr_dig_target * config->enableLdoStable = false; * endcode * - * param config Pointer to the structure pmu_snvs_dig_config_t. Please refer to @ref pmu_snvs_dig_config_t. + * param config Pointer to the structure pmu_snvs_dig_config_t. Please refer to pmu_snvs_dig_config_t. */ void PMU_GetSnvsDigLdoDefaultConfig(pmu_snvs_dig_config_t *config) { @@ -561,66 +499,44 @@ void PMU_GetSnvsDigLdoDefaultConfig(pmu_snvs_dig_config_t *config) * brief Initialize the SNVS DIG LDO. * * param base LDO SNVS DIG peripheral base address. - * param config Pointer to the structure pmu_snvs_dig_config_t. Please refer to @ref pmu_snvs_dig_config_t. + * param mode Used to control LDO power mode, please refer to pmu_ldo_operate_mode_t. */ -void PMU_SnvsDigLdoInit(ANADIG_LDO_SNVS_DIG_Type *base, const pmu_snvs_dig_config_t *config) +void PMU_SnvsDigLdoInit(ANADIG_LDO_SNVS_DIG_Type *base, pmu_ldo_operate_mode_t mode) { - assert(config != NULL); - uint32_t temp32 = base->PMU_LDO_SNVS_DIG; - temp32 &= - ~(ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_ENB_PULLDOWN_MASK | ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_MASK | - ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_CP_CONFIG_MASK | ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_RES_CONFIG_MASK | - ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TRIM_MASK | ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_STABLE_MASK); + temp32 &= ~(ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_MASK); - if (!(config->enablePullDown)) - { - temp32 |= ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_ENB_PULLDOWN_MASK; - } - temp32 |= ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN(config->mode); - temp32 |= ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_CP_CONFIG(config->chargePumpCurrent); - temp32 |= ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_RES_CONFIG(config->dischargeResistorValue); - temp32 |= ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TRIM(config->trimValue); - temp32 |= ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_STABLE(config->enableLdoStable); - base->PMU_LDO_SNVS_DIG = temp32; + temp32 |= (ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN(mode) | ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_MASK); - /* Enable SNVS DIG LDO. */ - base->PMU_LDO_SNVS_DIG |= ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_MASK; + base->PMU_LDO_SNVS_DIG = temp32; } /*! * brief Controls the ON/OFF of the selected LDO in the certain setpoints with GPC mode. * * param name The name of the selected ldo. Please see the enumeration pmu_ldo_name_t for details. - * param setpointMap The map of setpoints should be the OR'ed Value of _pmu_setpoint_map. - * param enable Turn on/off the LDO. - * true - Turn on the selected LDO in the certain setpoints. - * false - Turn off the selected LDO in the certain setpoints. + * param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map, 1b'1 + * means enable specific ldo in that setpoint. + * For example, the code PMU_GPCEnableLdo(kPMU_PllLdo, 0x1U) means enable PLL LDO in setpoint 0, disable + * PLL LDO in other setpoint. */ -void PMU_GPCEnableLdo(pmu_ldo_name_t name, uint32_t setpointMap, bool enable) +void PMU_GPCEnableLdo(pmu_ldo_name_t name, uint32_t setpointMap) { assert((name == kPMU_PllLdo) || (name > kPMU_PllLdo)); assert(name < kPMU_SnvsDigLdo); uint32_t ldoEnableRegArray[] = PMU_LDO_ENABLE_SETPOINT_REGISTERS; - if (enable) - { - (*(volatile uint32_t *)ldoEnableRegArray[(uint8_t)name]) &= ~setpointMap; - } - else - { - (*(volatile uint32_t *)ldoEnableRegArray[(uint8_t)name]) |= setpointMap; - } + (*(volatile uint32_t *)ldoEnableRegArray[(uint8_t)name]) = ~setpointMap; } /*! * brief Sets the operating mode of the selected LDO in the certain setpoints with GPC mode. * - * param name The name of the selected ldo. Please see the enumeration @ref pmu_ldo_name_t for details. + * param name The name of the selected ldo. Please see the enumeration pmu_ldo_name_t for details. * param setpointMap The map of setpoints should be the OR'ed Value of _pmu_setpoint_map. - * param mode The operating mode of the selected ldo. Please refer to the enumeration @ref pmu_ldo_operate_mode_t for + * param mode The operating mode of the selected ldo. Please refer to the enumeration pmu_ldo_operate_mode_t for * details. */ void PMU_GPCSetLdoOperateMode(pmu_ldo_name_t name, uint32_t setpointMap, pmu_ldo_operate_mode_t mode) @@ -643,86 +559,59 @@ void PMU_GPCSetLdoOperateMode(pmu_ldo_name_t name, uint32_t setpointMap, pmu_ldo /*! * brief Controls the ON/OFF of the selected LDOs' Tracking mode in the certain setpoints with GPC mode. * - * param name The name of the selected ldo. Please see the enumeration @ref pmu_ldo_name_t for details. - * param setpointMap The map of setpoints should be the OR'ed Value of _pmu_setpoint_map. - * param enable Turn on/off the LDOs' Tracking mode. - * true - Turn on the selected LDO's tracking mode in the certain setpoints. - * false - Turn off the selected LDO's tracking mode in the certain setpoints. + * param name The name of the selected ldo. Please see the enumeration pmu_ldo_name_t for details. + * param setpointMap The map of setpoints that the LDO tracking mode will be enabled in those setpoints, this value + * should be the OR'ed Value of @ref _pmu_setpoint_map. */ -void PMU_GPCEnableLdoTrackingMode(pmu_ldo_name_t name, uint32_t setpointMap, bool enable) +void PMU_GPCEnableLdoTrackingMode(pmu_ldo_name_t name, uint32_t setpointMap) { assert(name > kPMU_PllLdo); assert(name < kPMU_SnvsDigLdo); uint32_t ldoTrackingEnableRegArray[] = PMU_LDO_TRACKING_EN_SETPOINT_REGISTERS; - if (enable) - { - (*(volatile uint32_t *)ldoTrackingEnableRegArray[(uint8_t)name]) |= setpointMap; - } - else - { - (*(volatile uint32_t *)ldoTrackingEnableRegArray[(uint8_t)name]) &= ~setpointMap; - } + (*(volatile uint32_t *)ldoTrackingEnableRegArray[(uint8_t)name]) = setpointMap; } /*! * brief Controls the ON/OFF of the selected LDOs' Bypass mode in the certain setpoints with GPC mode. * - * param name The name of the selected ldo. Please see the enumeration @ref pmu_ldo_name_t for details. - * param setpointMap The map of setpoints should be the OR'ed Value of _pmu_setpoint_map. - * param enable Turn on/off the LDOs' Bypass mode. - * true - Turn on the selected LDO's Bypass mode in the certain setpoints. - * false - Turn off the selected LDO's Bypass mode in the certain setpoints. + * param name The name of the selected ldo. Please see the enumeration pmu_ldo_name_t for details. + * param setpointMap The map of setpoints that the LDO bypass mode will be enabled in those setpoints, this value + * should be the OR'ed Value of @ref _pmu_setpoint_map. */ -void PMU_GPCEnableLdoBypassMode(pmu_ldo_name_t name, uint32_t setpointMap, bool enable) +void PMU_GPCEnableLdoBypassMode(pmu_ldo_name_t name, uint32_t setpointMap) { assert(name > kPMU_PllLdo); assert(name < kPMU_SnvsDigLdo); uint32_t ldoBypassEnableRegArray[] = PMU_LDO_BYPASS_EN_SETPOINT_REGISTERS; - if (enable) - { - (*(volatile uint32_t *)ldoBypassEnableRegArray[(uint8_t)name]) |= setpointMap; - } - else - { - (*(volatile uint32_t *)ldoBypassEnableRegArray[(uint8_t)name]) &= ~setpointMap; - } + (*(volatile uint32_t *)ldoBypassEnableRegArray[(uint8_t)name]) = setpointMap; } /*! * brief Controls the ON/OFF of the selected LDOs' Standby mode in the certain setpoints with GPC mode. * - * param name The name of the selected ldo. Please see the enumeration @ref pmu_ldo_name_t for details. - * param setpointMap The map of setpoints should be the OR'ed Value of _pmu_setpoint_map. - * param enable Turn on/off the LDOs' Standby mode. - * true - Turn on the selected LDO's Standby mode in the certain setpoints. - * false - Turn off the selected LDO's Standby mode in the certain setpoints. + * param name The name of the selected ldo. Please see the enumeration pmu_ldo_name_t for details. + * param setpointMap The map of setpoints that the LDO Standby mode will be enabled in those setpoints, this value + * should be the OR'ed Value of @ref _pmu_setpoint_map. */ -void PMU_GPCEnableLdoStandbyMode(pmu_ldo_name_t name, uint32_t setpointMap, bool enable) +void PMU_GPCEnableLdoStandbyMode(pmu_ldo_name_t name, uint32_t setpointMap) { assert((name == kPMU_PllLdo) || (name > kPMU_PllLdo)); assert(name < kPMU_SnvsDigLdo); uint32_t ldoStandbyEnableRegArray[] = PMU_LDO_STBY_EN_REGISTERS; - if (enable) - { - (*(volatile uint32_t *)ldoStandbyEnableRegArray[(uint8_t)name]) |= setpointMap; - } - else - { - (*(volatile uint32_t *)ldoStandbyEnableRegArray[(uint8_t)name]) &= ~setpointMap; - } + (*(volatile uint32_t *)ldoStandbyEnableRegArray[(uint8_t)name]) = setpointMap; } /*! * brief Selects the control mode of the Bandgap Reference. * * param base PMU peripheral base address. - * param mode The control mode of the Bandgap Reference. Please refer to @ref pmu_control_mode_t. + * param mode The control mode of the Bandgap Reference. Please refer to pmu_control_mode_t. */ void PMU_SetBandgapControlMode(ANADIG_PMU_Type *base, pmu_control_mode_t mode) { @@ -768,13 +657,13 @@ void PMU_DisableBandgapSelfBiasAfterPowerUp(void) /* Wait Bandgap stable. */ do { - regValue = ANATOP_AI_Read(kAI_Itf_Bandgap, PMU_BANDGAP_ANALOG_STATUS_REGISTER_ADDRESS); - } while ((regValue & PMU_BANDGAP_ANALOG_STATUS_REFTOP_VBGUP_MASK) == 0UL); + regValue = ANATOP_AI_Read(kAI_Itf_Bandgap, kAI_BANDGAP_STAT0); + } while ((regValue & AI_BANDGAP_STAT0_REFTOP_VBGUP_MASK) == 0UL); /* Disable Bandgap self bias for best noise performance. */ - temp32 = ANATOP_AI_Read(kAI_Itf_Bandgap, PMU_BANDGAP_ANALOG_CTRL0_REGISTER_ADDRESS); - temp32 |= PMU_BANDGAP_ANALOG_CTRL0_REFTOP_SELFBIASOFF_MASK; - ANATOP_AI_Write(kAI_Itf_Bandgap, PMU_BANDGAP_ANALOG_CTRL0_REGISTER_ADDRESS, temp32); + temp32 = ANATOP_AI_Read(kAI_Itf_Bandgap, kAI_BANDGAP_CTRL0); + temp32 |= AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK; + ANATOP_AI_Write(kAI_Itf_Bandgap, kAI_BANDGAP_CTRL0, temp32); } /*! @@ -787,15 +676,15 @@ void PMU_EnableBandgapSelfBiasBeforePowerDown(void) { uint32_t temp32; - temp32 = ANATOP_AI_Read(kAI_Itf_Bandgap, PMU_BANDGAP_ANALOG_CTRL0_REGISTER_ADDRESS); - temp32 &= ~PMU_BANDGAP_ANALOG_CTRL0_REFTOP_SELFBIASOFF_MASK; - ANATOP_AI_Write(kAI_Itf_Bandgap, PMU_BANDGAP_ANALOG_CTRL0_REGISTER_ADDRESS, temp32); + temp32 = ANATOP_AI_Read(kAI_Itf_Bandgap, kAI_BANDGAP_CTRL0); + temp32 &= ~AI_BANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK; + ANATOP_AI_Write(kAI_Itf_Bandgap, kAI_BANDGAP_CTRL0, temp32); } /*! * brief Init Bandgap. * - * param config. Pointer to the structure pmu_static_bandgap_config_t. Please refer to @ref pmu_static_bandgap_config_t. + * param config. Pointer to the structure pmu_static_bandgap_config_t. Please refer to pmu_static_bandgap_config_t. */ void PMU_StaticBandgapInit(const pmu_static_bandgap_config_t *config) { @@ -803,23 +692,69 @@ void PMU_StaticBandgapInit(const pmu_static_bandgap_config_t *config) uint32_t temp32; - temp32 = ANATOP_AI_Read(kAI_Itf_Bandgap, PMU_BANDGAP_ANALOG_CTRL0_REGISTER_ADDRESS); - temp32 &= ~(PMU_BANDGAP_ANALOG_CTRL0_REFTOP_PWD_OPTION_MASK | PMU_BANDGAP_ANALOG_CTRL0_REFTOP_LOWPOWER_MASK | - PMU_BANDGAP_ANALOG_CTRL0_REFTOP_VBGADJ_MASK | PMU_BANDGAP_ANALOG_CTRL0_REFTOP_IBZTCADJ_MASK); - temp32 |= PMU_BANDGAP_ANALOG_CTRL0_REFTOP_PWD_OPTION(config->powerDownOption); - temp32 |= PMU_BANDGAP_ANALOG_CTRL0_REFTOP_LOWPOWER(config->enableLowPowerMode); - temp32 |= PMU_BANDGAP_ANALOG_CTRL0_REFTOP_VBGADJ(config->outputVoltage); - temp32 |= PMU_BANDGAP_ANALOG_CTRL0_REFTOP_IBZTCADJ(config->outputCurrent); + temp32 = ANATOP_AI_Read(kAI_Itf_Bandgap, kAI_BANDGAP_CTRL0); + temp32 &= ~(AI_BANDGAP_CTRL0_REFTOP_PWD_MASK | AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK | + AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK | AI_BANDGAP_CTRL0_REFTOP_LOWPOWER_MASK | + AI_BANDGAP_CTRL0_REFTOP_VBGADJ_MASK | AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ_MASK); + temp32 |= ((uint32_t)(config->powerDownOption) & + (AI_BANDGAP_CTRL0_REFTOP_PWD_MASK | AI_BANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK | + AI_BANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK)); + temp32 |= AI_BANDGAP_CTRL0_REFTOP_LOWPOWER(config->enableLowPowerMode); + temp32 |= AI_BANDGAP_CTRL0_REFTOP_VBGADJ(config->outputVoltage); + temp32 |= AI_BANDGAP_CTRL0_REFTOP_IBZTCADJ(config->outputCurrent); + + ANATOP_AI_Write(kAI_Itf_Bandgap, kAI_BANDGAP_CTRL0, temp32); +} + +/*! + * brief Configures Well bias, such as power source, clock source and so on. + * + * param base PMU peripheral base address. + * param config Pointer to the pmu_well_bias_config_t structure. + */ +void PMU_WellBiasInit(ANADIG_PMU_Type *base, const pmu_well_bias_config_t *config) +{ + assert(config != NULL); - ANATOP_AI_Write(kAI_Itf_Bandgap, PMU_BANDGAP_ANALOG_CTRL0_REGISTER_ADDRESS, temp32); + uint32_t tmp32; + + tmp32 = base->PMU_BIAS_CTRL; + tmp32 &= ~(ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK | ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_MASK); + tmp32 |= ((uint32_t)config->wellBiasOption.wellBiasData & + (ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK | ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_MASK)); + base->PMU_BIAS_CTRL = tmp32; + + tmp32 = base->PMU_BIAS_CTRL2; + tmp32 &= ~ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_MASK; + tmp32 |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8(config->adjustment); + base->PMU_BIAS_CTRL2 = tmp32; +} + +/*! + * brief Enables/disables the selected body bias. + * + * param base PMU peripheral base address. + * param name The name of the body bias to be turned on/off, please refer to pmu_body_bias_name_t. + * param enable Used to turn on/off the specific body bias. + * - \b true Enable the selected body bias. + * - \b false Disable the selected body bias. + */ +void PMU_GetWellBiasDefaultConfig(pmu_well_bias_config_t *config) +{ + assert(config != NULL); + + (void)memset(config, 0, sizeof(*config)); + + config->wellBiasOption.wellBiasData = 0U; + config->adjustment = kPMU_Cref0fFCspl0fFDeltaC0fF; } /*! * brief Selects the control mode of the Body Bias. * * param base PMU peripheral base address. - * param name The name of the body bias. Please refer to @ref pmu_body_bias_name_t. - * param mode The control mode of the Body Bias. Please refer to @ref pmu_control_mode_t. + * param name The name of the body bias. Please refer to pmu_body_bias_name_t. + * param mode The control mode of the Body Bias. Please refer to pmu_control_mode_t. */ void PMU_SetBodyBiasControlMode(ANADIG_PMU_Type *base, pmu_body_bias_name_t name, pmu_control_mode_t mode) { @@ -852,199 +787,113 @@ void PMU_SetBodyBiasControlMode(ANADIG_PMU_Type *base, pmu_body_bias_name_t name break; } default: - assert(false); + /* This branch should never be hit. */ break; } } -/*! - * brief Gets the default config of CM7 Forward Body Bias in static mode. - * - * param config Pointer to the structure pmu_static_body_bias_config_t. Please refer to @ref - * pmu_static_body_bias_config_t. - */ -void PMU_StaticGetCm7FBBDefaultConfig(pmu_static_body_bias_config_t *config) -{ - assert(config != NULL); - - (void)memset(config, 0, sizeof(*config)); - - config->voltageLevel = kPMU_BodyBiasWellRegulateTo0P6V; - config->driveStrength = 0x3U; - config->oscillatorFreq = 0xFU; -} - -/*! - * brief Initialize CM7 Forward Body Bias in Static/Software Mode. - * - * param base PMU peripheral base address. - * param config Pointer to the structure pmu_static_body_bias_config_t. Please refer to @ref - * pmu_static_body_bias_config_t. - */ -void PMU_StaticCm7FBBInit(ANADIG_PMU_Type *base, const pmu_static_body_bias_config_t *config) -{ - assert(config != NULL); - - uint32_t temp32; - uint32_t wellBiasConfig; - - base->PMU_BIAS_CTRL &= ~ANADIG_PMU_PMU_BIAS_CTRL_WB_NW_LVL_1P8_MASK; - base->PMU_BIAS_CTRL |= ANADIG_PMU_PMU_BIAS_CTRL_WB_NW_LVL_1P8(config->voltageLevel); - base->PMU_BIAS_CTRL &= ~ANADIG_PMU_PMU_BIAS_CTRL_WB_PW_LVL_1P8_MASK; - base->PMU_BIAS_CTRL |= ANADIG_PMU_PMU_BIAS_CTRL_WB_PW_LVL_1P8(config->voltageLevel); - temp32 = base->PMU_BIAS_CTRL; - temp32 &= ~ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK; - wellBiasConfig = PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD_MASK | - PMU_BIAS_CTRL_WB_CFG_1P8_DRIVE_STRENGTH(config->driveStrength) | - PMU_BIAS_CTRL_WB_CFG_1P8_OSCILLATOR_FREQ(config->oscillatorFreq); - temp32 |= ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8(wellBiasConfig); - base->PMU_BIAS_CTRL = temp32; - base->PMU_BIAS_CTRL2 &= ~ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK; - base->PMU_BIAS_CTRL2 |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(0x1U); - base->PMU_BIAS_CTRL2 |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK; - SDK_DelayAtLeastUs(100, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); -} - -/*! - * brief Gets the default config of LPSR Reverse Body Bias in Static/Software mode. - * - * param config Pointer to the structure pmu_static_body_bias_config_t. Please refer to @ref - * pmu_static_body_bias_config_t. - */ -void PMU_StaticLpsrRBBDefaultConfig(pmu_static_body_bias_config_t *config) -{ - assert(config != NULL); - - config->voltageLevel = kPMU_BodyBiasWellRegulateTo1P0V; - config->driveStrength = 0x5U; - config->oscillatorFreq = 0xFU; -} - -/*! - * brief Initialize LPSR Reverse Body Bias in Static/Software Mode. - * - * param base PMU peripheral base address. - * param config Pointer to the structure pmu_static_body_bias_config_t. Please refer to @ref - * pmu_static_body_bias_config_t. - */ -void PMU_StaticLpsrRBBInit(ANADIG_PMU_Type *base, const pmu_static_body_bias_config_t *config) -{ - assert(config != NULL); - - uint32_t temp32; - uint32_t wellBiasConfig; - - base->PMU_BIAS_CTRL &= ~ANADIG_PMU_PMU_BIAS_CTRL_WB_NW_LVL_1P8_MASK; - base->PMU_BIAS_CTRL |= ANADIG_PMU_PMU_BIAS_CTRL_WB_NW_LVL_1P8(config->voltageLevel); - base->PMU_BIAS_CTRL &= ~ANADIG_PMU_PMU_BIAS_CTRL_WB_PW_LVL_1P8_MASK; - base->PMU_BIAS_CTRL |= ANADIG_PMU_PMU_BIAS_CTRL_WB_PW_LVL_1P8(config->voltageLevel); - temp32 = base->PMU_BIAS_CTRL; - temp32 &= ~ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK; - wellBiasConfig = PMU_BIAS_CTRL_WB_CFG_1P8_DRIVE_STRENGTH(config->driveStrength) | - PMU_BIAS_CTRL_WB_CFG_1P8_OSCILLATOR_FREQ(config->oscillatorFreq); - temp32 |= ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8(wellBiasConfig); - base->PMU_BIAS_CTRL = temp32; - base->PMU_BIAS_CTRL2 &= ~ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK; - base->PMU_BIAS_CTRL2 |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(0x2U); - base->PMU_BIAS_CTRL2 |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK; - SDK_DelayAtLeastUs(100, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); -} - -/*! - * brief Gets the default config of SOC Reverse Body Bias in Static/Software mode. - * - * param config Pointer to the structure pmu_static_body_bias_config_t. Please refer to @ref - * pmu_static_body_bias_config_t. - */ -void PMU_StaticSocRBBDefaultConfig(pmu_static_body_bias_config_t *config) -{ - assert(config != NULL); - - config->voltageLevel = kPMU_BodyBiasWellRegulateTo1P0V; - config->driveStrength = 0x1U; - config->oscillatorFreq = 0xFU; -} - -/*! - * brief Initialize SOC Reverse Body Bias in Static/Software Mode. - * - * param base PMU peripheral base address. - * param config Pointer to the structure pmu_static_body_bias_config_t. Please refer to @ref - * pmu_static_body_bias_config_t. - */ -void PMU_StaticSocRBBInit(ANADIG_PMU_Type *base, const pmu_static_body_bias_config_t *config) +void PMU_EnableBodyBias(ANADIG_PMU_Type *base, pmu_body_bias_name_t name, bool enable) { - assert(config != NULL); + uint32_t tmp32; - uint32_t temp32; - uint32_t wellBiasConfig; - - base->PMU_BIAS_CTRL &= ~ANADIG_PMU_PMU_BIAS_CTRL_WB_NW_LVL_1P8_MASK; - base->PMU_BIAS_CTRL |= ANADIG_PMU_PMU_BIAS_CTRL_WB_NW_LVL_1P8(config->voltageLevel); - base->PMU_BIAS_CTRL &= ~ANADIG_PMU_PMU_BIAS_CTRL_WB_PW_LVL_1P8_MASK; - base->PMU_BIAS_CTRL |= ANADIG_PMU_PMU_BIAS_CTRL_WB_PW_LVL_1P8(config->voltageLevel); - temp32 = base->PMU_BIAS_CTRL; - temp32 &= ~ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK; - wellBiasConfig = PMU_BIAS_CTRL_WB_CFG_1P8_DRIVE_STRENGTH(config->driveStrength) | - PMU_BIAS_CTRL_WB_CFG_1P8_OSCILLATOR_FREQ(config->oscillatorFreq); - temp32 |= ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8(wellBiasConfig); - base->PMU_BIAS_CTRL = temp32; - base->PMU_BIAS_CTRL2 &= ~ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK; - base->PMU_BIAS_CTRL2 |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(0x4U); - base->PMU_BIAS_CTRL2 |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK; - SDK_DelayAtLeastUs(100, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY); + if (enable) + { + switch (name) + { + case kPMU_FBB_CM7: + { + tmp32 = base->PMU_BIAS_CTRL; + tmp32 &= ~PMU_BIAS_CTRL_WB_CFG_1P8_WELL_SELECT_MASK; + tmp32 |= PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD_MASK; + base->PMU_BIAS_CTRL = tmp32; + + tmp32 = base->PMU_BIAS_CTRL2; + tmp32 &= ~(ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK); + tmp32 |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(1U) | ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK; + base->PMU_BIAS_CTRL2 = tmp32; + + while ((base->PMU_BIAS_CTRL2 & ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK) != + ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK) + { + } + break; + } + case kPMU_RBB_SOC: + { + tmp32 = base->PMU_BIAS_CTRL; + tmp32 &= ~(PMU_BIAS_CTRL_WB_CFG_1P8_WELL_SELECT_MASK | PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD_MASK); + base->PMU_BIAS_CTRL = tmp32; + + tmp32 = base->PMU_BIAS_CTRL2; + tmp32 &= ~(ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK); + tmp32 |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(2U) | ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK; + base->PMU_BIAS_CTRL2 = tmp32; + while ((base->PMU_BIAS_CTRL2 & ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK) != + ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK) + { + } + break; + } + case kPMU_RBB_LPSR: + { + tmp32 = base->PMU_BIAS_CTRL; + tmp32 &= ~(PMU_BIAS_CTRL_WB_CFG_1P8_WELL_SELECT_MASK | PMU_BIAS_CTRL_WB_CFG_1P8_VOLTAGE_THRESHOLD_MASK); + base->PMU_BIAS_CTRL = tmp32; + + tmp32 = base->PMU_BIAS_CTRL2; + tmp32 &= ~(ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK); + tmp32 |= ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(4U) | ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK; + base->PMU_BIAS_CTRL2 = tmp32; + while ((base->PMU_BIAS_CTRL2 & ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK) != + ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK) + { + } + break; + } + default: + /* This branch should never be hit. */ + break; + } + } + else + { + base->PMU_BIAS_CTRL2 &= + ~(ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK | ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK); + } } /*! * brief Controls the ON/OFF of the selected body bias in the certain setpoints with GPC mode. * - * param name The name of the selected body bias. Please see the enumeration @ref pmu_body_bias_name_t for details. - * param setpointMap The map of setpoints should be the OR'ed Value of _pmu_setpoint_map. - * param enable Turn on/off the LDO. - * true - Turn on the selected body bias in the certain setpoints. - * false - Turn off the selected body bias in the certain setpoints. + * param name The name of the selected body bias. Please see the enumeration pmu_body_bias_name_t for details. + * param setpointMap The map of setpoints that the specific body bias will be enabled in those setpoints, this value + * should be the OR'ed Value of _pmu_setpoint_map. */ -void PMU_GPCEnableBodyBias(pmu_body_bias_name_t name, uint32_t setpointMap, bool enable) +void PMU_GPCEnableBodyBias(pmu_body_bias_name_t name, uint32_t setpointMap) { uint32_t bodyBiasEnableRegArray[] = PMU_BODY_BIAS_ENABLE_REGISTERS; - if (enable) - { - (*(volatile uint32_t *)bodyBiasEnableRegArray[(uint8_t)name]) &= ~setpointMap; - } - else - { - (*(volatile uint32_t *)bodyBiasEnableRegArray[(uint8_t)name]) |= setpointMap; - } + (*(volatile uint32_t *)bodyBiasEnableRegArray[(uint8_t)name]) = ~setpointMap; } /*! * brief Controls the ON/OFF of the selected Body Bias' Standby mode in the certain setpoints with GPC mode. * - * param name The name of the selected body bias. Please see the enumeration @ref pmu_body_bias_name_t for details. - * param setpointMap The map of setpoints should be the OR'ed Value of _pmu_setpoint_map. - * param enable Turn on/off the body bias' Standby mode. - * true - Turn on the selected body bias' Standby mode in the certain setpoints. - * false - Turn off the selected body bias' Standby mode in the certain setpoints. + * param name The name of the selected body bias. Please see the enumeration pmu_body_bias_name_t for details. + * param setpointMap The map of setpoints that the specific body bias standby mode will be enabled in those + * setpoints, this value should be the OR'ed Value of @ref _pmu_setpoint_map. */ -void PMU_GPCEnableBodyBiasStandbyMode(pmu_body_bias_name_t name, uint32_t setpointMap, bool enable) +void PMU_GPCEnableBodyBiasStandbyMode(pmu_body_bias_name_t name, uint32_t setpointMap) { uint32_t BBStandbyEnableRegArray[] = PMU_BODY_BIAS_STBY_EN_REGISTERS; - if (enable) - { - (*(volatile uint32_t *)BBStandbyEnableRegArray[(uint8_t)name]) |= setpointMap; - } - else - { - (*(volatile uint32_t *)BBStandbyEnableRegArray[(uint8_t)name]) &= ~setpointMap; - } + (*(volatile uint32_t *)BBStandbyEnableRegArray[(uint8_t)name]) = setpointMap; } /*! * brief Gets the default config of body bias in GPC mode. * - * param config Pointer to the structure @ref pmu_gpc_body_bias_config_t. + * param config Pointer to the structure pmu_gpc_body_bias_config_t. */ void PMU_GPCGetBodyBiasDefaultConfig(pmu_gpc_body_bias_config_t *config) { @@ -1059,8 +908,8 @@ void PMU_GPCGetBodyBiasDefaultConfig(pmu_gpc_body_bias_config_t *config) /*! * brief Sets the config of the selected Body Bias in GPC mode. * - * param name The name of the selected body bias. Please see the enumeration @ref pmu_body_bias_name_t for details. - * param config Pointer to the structure @ref pmu_gpc_body_bias_config_t. + * param name The name of the selected body bias. Please see the enumeration pmu_body_bias_name_t for details. + * param config Pointer to the structure pmu_gpc_body_bias_config_t. */ void PMU_GPCSetBodyBiasConfig(pmu_body_bias_name_t name, const pmu_gpc_body_bias_config_t *config) { diff --git a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_pmu.h b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_pmu.h index f718f7474ad..df631d4265d 100644 --- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_pmu.h +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1170/drivers/fsl_pmu.h @@ -24,7 +24,7 @@ */ /*! @brief PMU driver version */ -#define FSL_PMU_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */ +#define FSL_PMU_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) /*!< Version 2.1.0. */ /*! * @} @@ -92,17 +92,6 @@ typedef enum _pmu_ldo_operate_mode kPMU_HighPowerMode = 0x1U, /*!< LDOs operate in High power mode. */ } pmu_ldo_operate_mode_t; -/*! - * @brief The enumeration of LPSR ANA LDO's driver strength. - */ -typedef enum _pmu_lpsr_ana_ldo_driver_strength -{ - kPMU_LpsrAnaLdoDriverStrength0 = 0U, /*!< Driver strength0 of LPSR ANA LDO. */ - kPMU_LpsrAnaLdoDriverStrength1 = 1U, /*!< Driver strength1 of LPSR ANA LDO. */ - kPMU_LpsrAnaLdoDriverStrength2 = 2U, /*!< Driver strength2 of LPSR ANA LDO. */ - kPMU_LpsrAnaLdoDriverStrength3 = 3U, /*!< Driver strength3 of LPSR ANA LDO. */ -} pmu_lpsr_ana_ldo_driver_strength_t; - /*! * @brief The enumeration of LPSR ANA LDO's charge pump current. */ @@ -114,18 +103,6 @@ typedef enum _pmu_lpsr_ana_ldo_charge_pump_current kPMU_LpsrAnaChargePump600nA = 3U, /*!< The current of the charge pump is selected as 600nA. */ } pmu_lpsr_ana_ldo_charge_pump_current_t; -/*! - * @brief The enumeration of LPSR ANA LDO's brown out config. - */ -typedef enum _pmu_lpsr_ana_ldo_brown_out_detector_config -{ - kPMU_LpsrAnaLdoBrownOutDetectorDisable = 4U, /*!< Disable brown out. */ - kPMU_LpsrAnaLdoBrownOutDetectorOffset25mV = 0U, /*!< Enable brown out and the offset is 25mV. */ - kPMU_LpsrAnaLdoBrownOutDetectorOffset50mV = 1U, /*!< Enable brown out and the offset is 50mV. */ - kPMU_LpsrAnaLdoBrownOutDetectorOffset75mV = 2U, /*!< Enable brown out and the offset is 75mV. */ - kPMU_LpsrAnaLdoBrownOutDetectorOffset100mV = 3U, /*!< Enable brown out and the offset is 100mV. */ -} pmu_lpsr_ana_ldo_brown_out_detector_config_t; - /*! * @brief The enumeration of LPSR ANA LDO's output range. */ @@ -136,16 +113,6 @@ typedef enum _pmu_lpsr_ana_ldo_output_range kPMU_LpsrAnaLdoOutputFrom1P82To1P88 = 2U, /*!< The output voltage varies from 1.82V to 1.88V. */ } pmu_lpsr_ana_ldo_output_range_t; -/*! - * @brief The enumeration of LPSR ANA LDO's bypass mode. - */ -typedef enum _pmu_lpsr_ana_ldo_bypass_mode -{ - kPMU_LpsrAnaLdoBypassModeDisable = 0U, /*!< Disable LPSR ANA LDO Bypass Mode. */ - kPMU_LpsrAnaLdoBypassMode1 = 1U, /*!< Select LPSR ANA LDO Bypass Mode1. */ - kPMU_LpsrAnaLdoBypassMode2 = 2U, /*!< Select LPSR ANA LDO Bypass Mode2. */ -} pmu_lpsr_ana_ldo_bypass_mode_t; - /*! * @brief The enumeration of voltage step time for LPSR DIG LDO. */ @@ -157,23 +124,15 @@ typedef enum _pmu_lpsr_dig_voltage_step_time kPMU_LpsrDigVoltageStepInc100us = 0x3U, /*!< LPSR DIG LDO voltage step time selected as 100us. */ } pmu_lpsr_dig_voltage_step_time_t; -/*! - * @brief The enumeration of LPSR DIG LDO's brown out config. - */ -typedef enum _pmu_lpsr_dig_brown_out_config -{ - kPMU_LpsrDigBrownOutDisable = 0x4U, /*!< Disable brown out. */ - kPMU_LpsrDigBrownOutEnableOffset19mV = 0x0U, /*!< Enable brown out and the offset is 19mV. */ - kPMU_LpsrDigBrownOutEnableOffset39mV = 0x1U, /*!< Enable brown out and the offset is 39mV. */ - kPMU_LpsrDigBrownOutEnableOffset58mV = 0x2U, /*!< Enable brown out and the offset is 58mV. */ - kPMU_LpsrDigBrownOutEnableOffset78mV = 0x3U, /*!< Enable brown out and the offset is 78mV. */ -} pmu_lpsr_dig_brown_out_config_t; - /*! * @brief The target output voltage of LPSR DIG LDO. */ typedef enum _pmu_lpsr_dig_target_output_voltage { + kPMU_LpsrDigTargetStableVoltage0P631V = 0x0U, /*!< The target voltage selected as 0.631V */ + kPMU_LpsrDigTargetStableVoltage0P65V = 0x1U, /*!< The target voltage selected as 0.65V */ + kPMU_LpsrDigTargetStableVoltage0P67V = 0x2U, /*!< The target voltage selected as 0.67V */ + kPMU_LpsrDigTargetStableVoltage0P689V = 0x3U, /*!< The target voltage selected as 0.689V */ kPMU_LpsrDigTargetStableVoltage0P709V = 0x4U, /*!< The target voltage selected as 0.709V */ kPMU_LpsrDigTargetStableVoltage0P728V = 0x5U, /*!< The target voltage selected as 0.728V */ kPMU_LpsrDigTargetStableVoltage0P748V = 0x6U, /*!< The target voltage selected as 0.748V */ @@ -197,6 +156,11 @@ typedef enum _pmu_lpsr_dig_target_output_voltage kPMU_LpsrDigTargetStableVoltage1P097V = 0x18U, /*!< The target voltage selected as 1.097V */ kPMU_LpsrDigTargetStableVoltage1P117V = 0x19U, /*!< The target voltage selected as 1.117V */ kPMU_LpsrDigTargetStableVoltage1P136V = 0x1AU, /*!< The target voltage selected as 1.136V */ + kPMU_LpsrDigTargetStableVoltage1P155V = 0x1BU, /*!< The target voltage selected as 1.155V */ + kPMU_LpsrDigTargetStableVoltage1P175V = 0x1CU, /*!< The target voltage selected as 1.175V */ + kPMU_LpsrDigTargetStableVoltage1P194V = 0x1DU, /*!< The target voltage selected as 1.194V */ + kPMU_LpsrDigTargetStableVoltage1P214V = 0x1EU, /*!< The target voltage selected as 1.214V */ + kPMU_LpsrDigTargetStableVoltage1P233V = 0x1FU, /*!< The target voltage selected as 1.233V */ } pmu_lpsr_dig_target_output_voltage_t; /*! @@ -224,11 +188,11 @@ typedef enum _pmu_snvs_dig_discharge_resistor_value */ enum _pmu_static_bandgap_power_down_option { - kPMU_PowerDownBandgapFully = 1U << 0U, /*!< Fully power down the bandgap module. */ - kPMU_PowerDownVoltageReferenceOutputOnly = 1U << 1U, - /*!< Power down only the reference output section of the bandgap */ - kPMU_PowerDownBandgapVBGUPDetector = 1U << 2U, /*!< Power down the VBGUP detector of the bandgap without - affecting any additional functionality. */ + kPMU_PowerDownBandgapFully = 1U << 0U, /*!< Fully power down the bandgap module. */ + kPMU_PowerDownVoltageReferenceOutputOnly = 1U << 1U, /*!< Power down only the reference output + section of the bandgap */ + kPMU_PowerDownBandgapVBGUPDetector = 1U << 2U, /*!< Power down the VBGUP detector of the bandgap without + affecting any additional functionality. */ }; /*! @@ -261,44 +225,103 @@ typedef enum _pmu_bandgap_output_current_value } pmu_bandgap_output_current_value_t; /*! - * @brief The enumeration of the body_bias_well's voltage level in static mode. + * @brief The enumerator of well bias power source. */ -typedef enum _pmu_body_bias_well_voltage_level +typedef enum _pmu_well_bias_power_source { - kPMU_BodyBiasWellRegulateTo0P5V = 0x0U, /*!< Body Bias Well regulated to 0.5V. */ - kPMU_BodyBiasWellRegulateTo0P6V = 0x1U, /*!< Body Bias Well regulated to 0.6V. */ - kPMU_BodyBiasWellRegulateTo0P7V = 0x2U, /*!< Body Bias Well regulated to 0.7V. */ - kPMU_BodyBiasWellRegulateTo0P8V = 0x3U, /*!< Body Bias Well regulated to 0.8V. */ - kPMU_BodyBiasWellRegulateTo0P9V = 0x4U, /*!< Body Bias Well regulated to 0.9V. */ - kPMU_BodyBiasWellRegulateTo1P0V = 0x5U, /*!< Body Bias Well regulated to 1.0V. */ - kPMU_BodyBiasWellRegulateTo1P1V = 0x6U, /*!< Body Bias Well regulated to 1.1V. */ - kPMU_BodyBiasWellRegulateTo1P2V = 0x7U, /*!< Body Bias Well regulated to 1.2V. */ - kPMU_BodyBiasWellRegulateTo1P3V = 0x8U, /*!< Body Bias Well regulated to 1.3V. */ -} pmu_body_bias_well_voltage_level_t; + kPMU_WellBiasPowerFromLpsrDigLdo = 0U, /*!< LPSR Dig LDO supplies the power stage and NWELL sampler. */ + kPMU_WellBiasPowerFromDCDC, /*!< DCDC supplies the power stage and NWELL sampler. */ +} pmu_well_bias_power_source_t; + +/*! + * @brief The enumerator of bias area size. + */ +typedef enum _pmu_bias_area_size +{ + kPMU_180uA_6mm2At125C = 0U, /*!< Imax = 180uA; Areamax-RVT = 6.00mm2 at 125C */ + kPMU_150uA_5mm2At125C, /*!< Imax = 150uA; Areamax-RVT = 5.00mm2 at 125C */ + kPMU_120uA_4mm2At125C, /*!< Imax = 120uA; Areamax-RVT = 4.00mm2 at 125C */ + kPMU_90uA_3mm2At125C, /*!< Imax = 90uA; Areamax-RVT = 3.00mm2 at 125C */ + kPMU_60uA_2mm2At125C, /*!< Imax = 60uA; Areamax-RVT = 2.00mm2 at 125C */ + kPMU_45uA_1P5mm2At125C, /*!< Imax = 45uA; Areamax-RVT = 1P5mm2 at 125C */ + kPMU_30uA_1mm2At125C, /*!< Imax = 30uA; Areamax-RVT = 1.00mm2 at 125C */ + kPMU_15uA_0P5mm2At125C, /*!< Imax = 15uA; Areamax-RVT = 0.50mm2 at 125C */ +} pmu_bias_area_size_t; + +/*! + * @brief The enumerator of well bias typical frequency. + */ +typedef enum _pmu_well_bias_typical_freq +{ + kPMU_OscFreqDiv128 = 0U, /*!< Typical frequency = osc_freq / 128. */ + kPMU_OscFreqDiv64 = 1U, /*!< Typical frequency = osc_freq / 64. */ + kPMU_OscFreqDiv32 = 2U, /*!< Typical frequency = osc_freq / 32. */ + kPMU_OscFreqDiv16 = 3U, /*!< Typical frequency = osc_freq / 16. */ + kPMU_OscFreqDiv8 = 4U, /*!< Typical frequency = osc_freq / 8. */ + kPMU_OscFreqDiv2 = 6U, /*!< Typical frequency = osc_freq / 2. */ + kPMU_OscFreq = 7U, /*!< Typical frequency = oscillator frequency. */ +} pmu_well_bias_typical_freq_t; + +/*! + * @brief The enumerator of well bias adaptive clock source. + */ +typedef enum _pmu_adaptive_clock_source +{ + kPMU_AdaptiveClkSourceOscClk = 0U, /*!< The adaptive clock source is oscillator clock. */ + kPMU_AdaptiveClkSourceChargePumpClk, /*!< The adaptive clock source is charge pump clock. */ +} pmu_adaptive_clock_source_t; + +/*! + * @brief The enumerator of frequency reduction due to cap increment. + */ +typedef enum _pmu_freq_reduction +{ + kPMU_FreqReductionNone = 0U, /*!< No frequency reduction. */ + kPMU_FreqReduction30PCT, /*!< 30% frequency reduction due to cap increment. */ + kPMU_FreqReduction40PCT, /*!< 40% frequency reduction due to cap increment. */ + kPMU_FreqReduction50PCT, /*!< 50% frequency reduction due to cap increment. */ +} pmu_freq_reduction_t; + +/*! + * @brief The enumerator of well bias 1P8 adjustment. + */ +typedef enum _pmu_well_bias_1P8_adjustment +{ + kPMU_Cref0fFCspl0fFDeltaC0fF = 0U, /*!< Cref = 0fF, Cspl = 0fF, DeltaC = 0fF. */ + kPMU_Cref0fFCspl30fFDeltaCN30fF, /*!< Cref = 0fF, Cspl = 30fF, DeltaC = -30fF. */ + kPMU_Cref0fFCspl43fFDeltaCN43fF, /*!< Cref = 0fF, Cspl = 43fF, DeltaC = -43fF. */ + kPMU_Cref0fFCspl62fFDeltaCN62fF, /*!< Cref = 0fF, Cspl = 62fF, DeltaC = -62fF. */ + kPMU_Cref0fFCspl105fFDeltaCN105fF, /*!< Cref = 0fF, Cspl = 105fF, DeltaC = -105fF. */ + kPMU_Cref30fFCspl0fFDeltaC30fF, /*!< Cref = 30fF, Cspl = 0fF, DeltaC = 30fF. */ + kPMU_Cref30fFCspl43fFDeltaCN12fF, /*!< Cref = 30fF, Cspl = 43fF, DeltaC = -12fF. */ + kPMU_Cref30fFCspl105fFDeltaCN75fF, /*!< Cref = 30fF, Cspl = 105fF, DeltaC = -75fF. */ + kPMU_Cref43fFCspl0fFDeltaC43fF, /*!< Cref = 43fF, Cspl = 0fF, DeltaC = 43fF. */ + kPMU_Cref43fFCspl30fFDeltaC13fF, /*!< Cref = 43fF, Cspl = 30fF, DeltaC = 13fF. */ + kPMU_Cref43fFCspl62fFDeltaCN19fF, /*!< Cref = 43fF, Cspl = 62fF, DeltaC = -19fF. */ + kPMU_Cref62fFCspl0fFDeltaC62fF, /*!< Cref = 62fF, Cspl = 0fF, DeltaC = 62fF. */ + kPMU_Cref62fFCspl43fFDeltaC19fF, /*!< Cref = 62fF, Cspl = 43fF, DeltaC = 19fF. */ + kPMU_Cref105fFCspl0fFDeltaC105fF, /*!< Cref = 105fF, Cspl = 0fF, DeltaC = 105fF. */ + kPMU_Cref105fFCspl30fFDeltaC75fF, /*!< Cref = 105fF, Cspl = 30fF, DeltaC = 75fF. */ +} pmu_well_bias_1P8_adjustment_t; /*! * @brief LPSR ANA LDO config. */ typedef struct _pmu_static_lpsr_ana_ldo_config { - pmu_ldo_operate_mode_t mode; /*!< The operate mode of LPSR ANA LDO. */ - bool enable2mALoad; /*!< Enable/Disable 2mA load. - - @b true Enables 2mA loading to prevent overshoot; - - @b false Disables 2mA loading.*/ - bool enable4mALoad; /*!< Enable/Disable 4mA load. - - @b true Enables 4mA loading to prevent dramatic voltage drop; - - @b false Disables 4mA load. */ - bool enable20uALoad; /*!< Enable/Disable 20uA load. - - @b true Enables 20uA loading to prevent overshoot; - - @b false Disables 20uA load. */ - bool enableStandbyMode; /*!< Enable/Disable Standby Mode. - - @b true Enables Standby mode; - - @b false Disables Standby mode. */ - pmu_lpsr_ana_ldo_driver_strength_t driverStrength; /*!< The drive strength of LPSR ANA LDO's power switch. */ - pmu_lpsr_ana_ldo_charge_pump_current_t chargePumpCurrent; /*!< The current of LPSR ANA LDO's charge pump. */ - pmu_lpsr_ana_ldo_brown_out_detector_config_t - brownOutDetectorConfig; /*!< The configuration of LPSR ANA LDO's brown out. */ - pmu_lpsr_ana_ldo_output_range_t outputRange; /*!< The output range of LPSR ANA LDO. */ + pmu_ldo_operate_mode_t mode; /*!< The operate mode of LPSR ANA LDO. */ + bool enable2mALoad; /*!< Enable/Disable 2mA load. + - \b true Enables 2mA loading to prevent overshoot; + - \b false Disables 2mA loading.*/ + bool enable4mALoad; /*!< Enable/Disable 4mA load. + - \b true Enables 4mA loading to prevent dramatic voltage drop; + - \b false Disables 4mA load. */ + bool enable20uALoad; /*!< Enable/Disable 20uA load. + - \b true Enables 20uA loading to prevent overshoot; + - \b false Disables 20uA load. */ + bool enableStandbyMode; /*!< Enable/Disable Standby Mode. + - \b true Enables Standby mode; + - \b false Disables Standby mode. */ } pmu_static_lpsr_ana_ldo_config_t; /*! @@ -307,12 +330,10 @@ typedef struct _pmu_static_lpsr_ana_ldo_config typedef struct _pmu_static_lpsr_dig_config { bool enableStableDetect; /*!< Enable/Disable Stable Detect. - - @b true Enables Stable Detect. - - @b false Disables Stable Detect. */ + - \b true Enables Stable Detect. + - \b false Disables Stable Detect. */ pmu_lpsr_dig_voltage_step_time_t voltageStepTime; /*!< Step time. */ - pmu_lpsr_dig_brown_out_config_t brownOutConfig; /*!< The configuration of LPSR DIG LDO's brown out. */ pmu_lpsr_dig_target_output_voltage_t targetVoltage; /*!< The target output voltage. */ - pmu_ldo_operate_mode_t mode; /*!< The operate mode of the LPSR DIG LDO. */ } pmu_static_lpsr_dig_config_t; /*! @@ -322,13 +343,13 @@ typedef struct _pmu_snvs_dig_config { pmu_ldo_operate_mode_t mode; /*!< The operate mode the SNVS DIG LDO. */ pmu_snvs_dig_charge_pump_current_t chargePumpCurrent; /*!< The current of SNVS DIG LDO's charge pump current. */ - pmu_snvs_dig_discharge_resistor_value_t - dischargeResistorValue; /*!< The value of SNVS DIG LDO's Discharge Resistor. */ - uint8_t trimValue; /*!< The trim value. */ - bool enablePullDown; /*!< Enable/Disable Pull down. - - @b true Enables the feature of using 1M ohm resistor to discharge the LDO output. - - @b false Disables the feature of using 1M ohm resistor to discharge the LDO output. */ - bool enableLdoStable; /*!< Enable/Disable SNVS DIG LDO Stable. */ + pmu_snvs_dig_discharge_resistor_value_t dischargeResistorValue; /*!< The value of SNVS DIG LDO's + Discharge Resistor. */ + uint8_t trimValue; /*!< The trim value. */ + bool enablePullDown; /*!< Enable/Disable Pull down. + - \b true Enables the feature of using 1M ohm resistor to discharge the LDO output. + - \b false Disables the feature of using 1M ohm resistor to discharge the LDO output. */ + bool enableLdoStable; /*!< Enable/Disable SNVS DIG LDO Stable. */ } pmu_snvs_dig_config_t; /*! @@ -339,22 +360,52 @@ typedef struct _pmu_static_bandgap_config uint8_t powerDownOption; /*!< The OR'ed value of @ref _pmu_static_bandgap_power_down_option. Please refer to @ref _pmu_static_bandgap_power_down_option. */ bool enableLowPowerMode; /*!< Turn on/off the Low power mode. - - @b true Turns on the low power operation of the bandgap. - - @b false Turns off the low power operation of the bandgap. */ + - \b true Turns on the low power operation of the bandgap. + - \b false Turns off the low power operation of the bandgap. */ pmu_bandgap_output_VBG_voltage_value_t outputVoltage; /*!< The output VBG voltage of Bandgap. */ - pmu_bandgap_output_current_value_t - outputCurrent; /*!< The output current from the bandgap to the temperature sensors. */ + pmu_bandgap_output_current_value_t outputCurrent; /*!< The output current from the bandgap to + the temperature sensors. */ } pmu_static_bandgap_config_t; /*! - * @brief The config of body bias in Static/Software Mode. + * @brief The union of well bias basic options, such as clock source, power source and so on. */ -typedef struct _pmu_static_body_bias_config_t +typedef union _pmu_well_bias_option +{ + uint16_t wellBiasData; /*!< well bias configuration data. */ + struct + { + uint16_t enablePWellOnly : 1U; /*!< Turn on both PWELL and NWELL, or only trun on PWELL. + - \b 1b0 PWELL and NEWLL are both turned on. + - \b 1b1 PWELL is turned on only. */ + uint16_t reserved1 : 1U; /*!< Reserved. */ + uint16_t biasAreaSize : 3U; /*!< Select size of bias area, please refer to @ref pmu_bias_area_size_t */ + uint16_t disableAdaptiveFreq : 1U; /*!< Enable/Disable adaptive frequency. + - \b 1b0 Frequency change after each half cycle minimum frequency + determined by typical frequency. + - \b 1b1 Adaptive frequency disabled. Frequency determined by typical + frequency. */ + uint16_t wellBiasFreq : 3U; /*!< Set well bias typical frequency, please refer to @ref + pmu_well_bias_typical_freq_t. */ + uint16_t clkSource : 1U; /*!< Config the adaptive clock source, please @ref pmu_adaptive_clock_source_t. */ + uint16_t freqReduction : 2U; /*!< Config the percent of frequency reduction due to cap increment, + please refer to @ref pmu_freq_reduction_t. */ + uint16_t enablePowerDownOption : 1U; /*!< Enable/Disable pull down option. + - \b false Pull down option is disabled. + - \b true Pull down option is enabled. */ + uint16_t reserved2 : 1U; /*!< Reserved. */ + uint16_t powerSource : 1U; /*!< Set power source, please refer to @ref pmu_well_bias_power_source_t. */ + uint16_t reserved3 : 1U; /*!< Reserved. */ + } wellBiasStruct; +} pmu_well_bias_option_t; + +typedef struct _pmu_well_bias_config { - pmu_body_bias_well_voltage_level_t voltageLevel; /*!< The voltage level of body bias well. */ - uint8_t driveStrength; /*!< The value of drive Strength */ - uint8_t oscillatorFreq; /*!< The frequency of Oscillator. */ -} pmu_static_body_bias_config_t; + pmu_well_bias_option_t wellBiasOption; /*!< Well bias basic function, please + refer to @ref pmu_well_bias_option_t. */ + pmu_well_bias_1P8_adjustment_t adjustment; /*!< Well bias adjustment 1P8, please + refer to @ref pmu_well_bias_1P8_adjustment_t. */ +} pmu_well_bias_config_t; /*! * @brief The stucture of body bias config in GPC mode. @@ -375,7 +426,7 @@ extern "C" { #endif /*! - * @name LDOs control related APIs + * @name LDOs Control APIs * @{ */ @@ -420,9 +471,24 @@ void PMU_SetLpsrAnaLdoControlMode(ANADIG_LDO_SNVS_Type *base, pmu_control_mode_t * @brief Sets the Bypass mode of the LPSR ANA LDO. * * @param base ANADIG_LDO_SNVS peripheral base address. - * @param bypassMode The Bypass mode of LPSR ANA LDO. Please refer to @ref pmu_lpsr_ana_ldo_bypass_mode_t. + * @param enable Enable/Disable bypass mode. + * - \b true Enable LPSR ANA Bypass mode. + * - \b false Disable LPSR ANA Bypass mode. + */ +void PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS_Type *base, bool enable); + +/*! + * @brief Checks whether the LPSR ANA LDO is in bypass mode. + * + * @param base ANADIG_LDO_SNVS peripheral base address. + * @return The result used to indicates whether the LPSR ANA LDO is in bypass mode. + * - \b true The LPSR ANA LDO is in bypass mode. + * - \b false The LPSR ANA LDO not in bypass mode. */ -void PMU_StaticSetLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS_Type *base, pmu_lpsr_ana_ldo_bypass_mode_t bypassMode); +static inline bool PMU_StaticCheckLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS_Type *base) +{ + return ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK) != 0UL); +} /*! * @brief Fill the LPSR ANA LDO configuration structure with default settings. @@ -472,11 +538,24 @@ void PMU_SetLpsrDigLdoControlMode(ANADIG_LDO_SNVS_Type *base, pmu_control_mode_t * * @param base ANADIG_LDO_SNVS peripheral base address. * @param enable - * - @b true Turns on Bypass mode of the LPSR DIG LDO. - * - @b false Turns off Bypass mode of the LPSR DIG LDO. + * - \b true Turns on Bypass mode of the LPSR DIG LDO. + * - \b false Turns off Bypass mode of the LPSR DIG LDO. */ void PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS_Type *base, bool enable); +/*! + * @brief Checks whether the LPSR DIG LDO is in bypass mode. + * + * @param base PMU peripheral base address. + * @return The result used to indicates whether the LPSR DIG LDO is in bypass mode. + * - \b true The LPSR DIG LDO is in bypass mode. + * - \b false The LPSR DIG LDO not in bypass mode. + */ +static inline bool PMU_StaticCheckLpsrDigLdoBypassMode(ANADIG_LDO_SNVS_Type *base) +{ + return ((ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK) != 0UL); +} + /*! * @brief Gets the default configuration of LPSR DIG LDO. * @@ -538,9 +617,9 @@ void PMU_GetSnvsDigLdoDefaultConfig(pmu_snvs_dig_config_t *config); * @brief Initialize the SNVS DIG LDO. * * @param base LDO SNVS DIG peripheral base address. - * @param config Pointer to structure @ref pmu_snvs_dig_config_t. + * @param mode Used to control LDO power mode, please refer to @ref pmu_ldo_operate_mode_t. */ -void PMU_SnvsDigLdoInit(ANADIG_LDO_SNVS_DIG_Type *base, const pmu_snvs_dig_config_t *config); +void PMU_SnvsDigLdoInit(ANADIG_LDO_SNVS_DIG_Type *base, pmu_ldo_operate_mode_t mode); /*! * @brief Disable SNVS DIG LDO. @@ -554,12 +633,12 @@ static inline void PMU_SnvsDigLdoDeinit(ANADIG_LDO_SNVS_DIG_Type *base) * @brief Controls the ON/OFF of the selected LDO in certain setpoints with GPC mode. * * @param name The name of the selected ldo. Please see enumeration @ref pmu_ldo_name_t for details. - * @param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map. - * @param enable Turn on/off the LDO. - * - @b true Turns on the selected LDO in certain setpoints. - * - @b false Turns off the selected LDO in certain setpoints. + * @param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map, 1b'1 + * means enable specific ldo in that setpoint. + * For example, the code PMU_GPCEnableLdo(kPMU_PllLdo, 0x1U) means to enable PLL LDO in setpoint 0 and disable + * PLL LDO in other setpoint. */ -void PMU_GPCEnableLdo(pmu_ldo_name_t name, uint32_t setpointMap, bool enable); +void PMU_GPCEnableLdo(pmu_ldo_name_t name, uint32_t setpointMap); /*! * @brief Sets the operating mode of the selected LDO in certain setpoints with GPC mode. @@ -575,41 +654,35 @@ void PMU_GPCSetLdoOperateMode(pmu_ldo_name_t name, uint32_t setpointMap, pmu_ldo * @brief Controls the ON/OFF of the selected LDOs' Tracking mode in certain setpoints with GPC mode. * * @param name The name of the selected ldo. Please see enumeration @ref pmu_ldo_name_t for details. - * @param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map. - * @param enable Turn on/off the LDOs' Tracking mode. - * - @b true Turns on the selected LDO's tracking mode in certain setpoints. - * - @b false Turns off the selected LDO's tracking mode in certain setpoints. + * @param setpointMap The map of setpoints that the LDO tracking mode will be enabled in those setpoints, this value + * should be the OR'ed Value of @ref _pmu_setpoint_map. */ -void PMU_GPCEnableLdoTrackingMode(pmu_ldo_name_t name, uint32_t setpointMap, bool enable); +void PMU_GPCEnableLdoTrackingMode(pmu_ldo_name_t name, uint32_t setpointMap); /*! * @brief Controls the ON/OFF of the selected LDOs' Bypass mode in certain setpoints with GPC mode. * * @param name The name of the selected ldo. Please see enumeration @ref pmu_ldo_name_t for details. - * @param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map. - * @param enable Turn on/off the LDOs' Bypass mode. - * - @b true Turns on the selected LDO's Bypass mode in certain setpoints. - * - @b false Turns off the selected LDO's Bypass mode in certain setpoints. + * @param setpointMap The map of setpoints that the LDO bypass mode will be enabled in those setpoints, this value + * should be the OR'ed Value of @ref _pmu_setpoint_map. */ -void PMU_GPCEnableLdoBypassMode(pmu_ldo_name_t name, uint32_t setpointMap, bool enable); +void PMU_GPCEnableLdoBypassMode(pmu_ldo_name_t name, uint32_t setpointMap); /*! * @brief Controls the ON/OFF of the selected LDOs' Standby mode in certain setpoints with GPC mode. * * @param name The name of the selected ldo. Please see enumeration @ref pmu_ldo_name_t for details. - * @param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map. - * @param enable Turn on/off the LDOs' Standby mode. - * - @b true Turns on the selected LDO's Standby mode in the certain setpoints. - * - @b false Turns off the selected LDO's Standby mode in the certain setpoints. + * @param setpointMap The map of setpoints that the LDO Standby mode will be enabled in those setpoints, this value + * should be the OR'ed Value of @ref _pmu_setpoint_map. */ -void PMU_GPCEnableLdoStandbyMode(pmu_ldo_name_t name, uint32_t setpointMap, bool enable); +void PMU_GPCEnableLdoStandbyMode(pmu_ldo_name_t name, uint32_t setpointMap); /*! * @} */ /*! - * @name Bandgap control related APIs + * @name Bandgap Control APIs * @{ */ @@ -655,43 +728,28 @@ void PMU_StaticBandgapInit(const pmu_static_bandgap_config_t *config); /*! * @brief Controls the ON/OFF of the Bandgap in certain setpoints with GPC mode. * + * For example, the code PMU_GPCEnableBandgap(PMU, kPMU_SetPoint0 | kPMU_SetPoint1); means enable bandgap in + * setpoint0 and setpoint1 and disable bandgap in other setpoints. + * * @param base PMU peripheral base address. - * @param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map. - * @param enable Turn on/off the Bandgap. - * - @b true Turns on the Bandgap in certain setpoints. - * - @b false Turns off the Bandgap in certain setpoints. + * @param setpointMap The map of setpoints that the bandgap will be enabled in those setpoints, this parameter + * should be the OR'ed Value of @ref _pmu_setpoint_map. */ -static inline void PMU_GPCEnableBandgap(ANADIG_PMU_Type *base, uint32_t setpointMap, bool enable) +static inline void PMU_GPCEnableBandgap(ANADIG_PMU_Type *base, uint32_t setpointMap) { - if (enable) - { - base->BANDGAP_ENABLE_SP &= ~setpointMap; - } - else - { - base->BANDGAP_ENABLE_SP |= setpointMap; - } + base->BANDGAP_ENABLE_SP = ~setpointMap; } /*! * @brief Controls the ON/OFF of the Bandgap's Standby mode in certain setpoints with GPC mode. * * @param base PMU peripheral base address. - * @param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map. - * @param enable Turn on/off the Bandgap's Standby mode. - * - @b true Turns on the Bandgap's Standby mode in certain setpoints. - * - @b false Turns off the Bandgap's Standby mode in certain setpoints. + * @param setpointMap The map of setpoints that the bandgap standby mode will be enabled in those setpoints, this value + * should be the OR'ed Value of @ref _pmu_setpoint_map. */ -static inline void PMU_GPCEnableBandgapStandbyMode(ANADIG_PMU_Type *base, uint32_t setpointMap, bool enable) +static inline void PMU_GPCEnableBandgapStandbyMode(ANADIG_PMU_Type *base, uint32_t setpointMap) { - if (enable) - { - base->BANDGAP_STBY_EN_SP |= setpointMap; - } - else - { - base->BANDGAP_STBY_EN_SP &= ~setpointMap; - } + base->BANDGAP_STBY_EN_SP = setpointMap; } /*! @@ -699,85 +757,62 @@ static inline void PMU_GPCEnableBandgapStandbyMode(ANADIG_PMU_Type *base, uint32 */ /*! - * @name Body Bias control + * @name Body Bias Control APIs * @{ */ /*! - * @brief Selects the control mode of the Body Bias. + * @brief Configures Well bias, such as power source, clock source and so on. * * @param base PMU peripheral base address. - * @param name The name of the body bias. Please refer to @ref pmu_body_bias_name_t. - * @param mode The control mode of the Body Bias. Please refer to @ref pmu_control_mode_t. - */ -void PMU_SetBodyBiasControlMode(ANADIG_PMU_Type *base, pmu_body_bias_name_t name, pmu_control_mode_t mode); - -/*! - * @brief Gets the default config of CM7 Forward Body Bias in Static/Software mode. - * - * @param config Pointer to the structure @ref pmu_static_body_bias_config_t. - */ -void PMU_StaticGetCm7FBBDefaultConfig(pmu_static_body_bias_config_t *config); - -/*! - * @brief Initialize CM7 Forward Body Bias in Static/Software Mode. - * - * @param base PMU peripheral base address. - * @param config Pointer to the structure @ref pmu_static_body_bias_config_t. + * @param config Pointer to the @ref pmu_well_bias_config_t structure. */ -void PMU_StaticCm7FBBInit(ANADIG_PMU_Type *base, const pmu_static_body_bias_config_t *config); +void PMU_WellBiasInit(ANADIG_PMU_Type *base, const pmu_well_bias_config_t *config); /*! - * @brief Gets the default config of LPSR Reverse Body Bias in Static/Software mode. + * @brief Gets the default configuration of well bias. * - * @param config Pointer to the structure @ref pmu_static_body_bias_config_t. + * @param config The pointer to the @ref pmu_well_bias_config_t structure. */ -void PMU_StaticLpsrRBBDefaultConfig(pmu_static_body_bias_config_t *config); +void PMU_GetWellBiasDefaultConfig(pmu_well_bias_config_t *config); /*! - * @brief Initialize LPSR Reverse Body Bias in Static/Software Mode. + * @brief Selects the control mode of the Body Bias. * * @param base PMU peripheral base address. - * @param config Pointer to the structure @ref pmu_static_body_bias_config_t. - */ -void PMU_StaticLpsrRBBInit(ANADIG_PMU_Type *base, const pmu_static_body_bias_config_t *config); - -/*! - * @brief Gets the default config of SOC Reverse Body Bias in Static/Software mode. - * - * @param config Pointer to the structure @ref pmu_static_body_bias_config_t. + * @param name The name of the body bias. Please refer to @ref pmu_body_bias_name_t. + * @param mode The control mode of the Body Bias. Please refer to @ref pmu_control_mode_t. */ -void PMU_StaticSocRBBDefaultConfig(pmu_static_body_bias_config_t *config); +void PMU_SetBodyBiasControlMode(ANADIG_PMU_Type *base, pmu_body_bias_name_t name, pmu_control_mode_t mode); /*! - * @brief Initialize SOC Reverse Body Bias in Static/Software Mode. + * @brief Enables/disables the selected body bias. * * @param base PMU peripheral base address. - * @param config Pointer to the structure @ref pmu_static_body_bias_config_t. + * @param name The name of the body bias to be turned on/off, please refer to @ref pmu_body_bias_name_t. + * @param enable Used to turn on/off the specific body bias. + * - \b true Enable the selected body bias. + * - \b false Disable the selected body bias. */ -void PMU_StaticSocRBBInit(ANADIG_PMU_Type *base, const pmu_static_body_bias_config_t *config); +void PMU_EnableBodyBias(ANADIG_PMU_Type *base, pmu_body_bias_name_t name, bool enable); /*! * @brief Controls the ON/OFF of the selected body bias in certain setpoints with GPC mode. * * @param name The name of the selected body bias. Please see enumeration @ref pmu_body_bias_name_t for details. - * @param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map. - * @param enable Turn on/off the body bias. - * - @b true Turns on the selected body bias in certain setpoints. - * - @b false Turns off the selected body bias in certain setpoints. + * @param setpointMap The map of setpoints that the specific body bias will be enabled in those setpoints, this value + * should be the OR'ed Value of _pmu_setpoint_map. */ -void PMU_GPCEnableBodyBias(pmu_body_bias_name_t name, uint32_t setpointMap, bool enable); +void PMU_GPCEnableBodyBias(pmu_body_bias_name_t name, uint32_t setpointMap); /*! * @brief Controls the ON/OFF of the selected Body Bias' Standby mode in certain setpoints with GPC mode. * * @param name The name of the selected body bias. Please see the enumeration @ref pmu_body_bias_name_t for details. - * @param setpointMap The map of setpoints should be the OR'ed Value of @ref _pmu_setpoint_map. - * @param enable Turn on/off the body bias' Standby mode. - * - @b true Turns on the selected body bias' Standby mode in certain setpoints. - * - @b false Turns off the selected body bias' Standby mode in certain setpoints. + * @param setpointMap The map of setpoints that the specific body bias will be enabled in those setpoints, this value + * should be the OR'ed Value of @ref _pmu_setpoint_map. */ -void PMU_GPCEnableBodyBiasStandbyMode(pmu_body_bias_name_t name, uint32_t setpointMap, bool enable); +void PMU_GPCEnableBodyBiasStandbyMode(pmu_body_bias_name_t name, uint32_t setpointMap); /*! * @brief Gets the default config of body bias in GPC mode.