diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/system_stm32f4xx.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/system_stm32f4xx.c
index 82b3265504a..c8a7fa8909a 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/system_stm32f4xx.c
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/system_stm32f4xx.c
@@ -38,7 +38,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2015 STMicroelectronics
+ * © COPYRIGHT 2017 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -735,11 +735,13 @@ void SystemInit_ExtMemCtl(void)
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
-/*-- FMC/FSMC Configuration --------------------------------------------------*/
+/*-- FMC/FSMC Configuration --------------------------------------------------*/
/* Enable the FMC/FSMC interface clock */
RCC->AHB3ENR |= 0x00000001;
-
-#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
+
+#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
+ /* Delay after an RCC peripheral clock enabling */
+ tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
/* Configure and enable Bank1_SRAM2 */
FMC_Bank1->BTCR[2] = 0x00001011;
FMC_Bank1->BTCR[3] = 0x00000201;
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/system_stm32f4xx.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/system_stm32f4xx.c
index 8394e8823e3..362a3ac7955 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/system_stm32f4xx.c
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/system_stm32f4xx.c
@@ -38,7 +38,7 @@
******************************************************************************
* @attention
*
- * © COPYRIGHT 2016 STMicroelectronics
+ * © COPYRIGHT 2017 STMicroelectronics
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -188,10 +188,6 @@ void SetSysClock(void);
*/
void SystemInit(void)
{
- /* FPU settings ------------------------------------------------------------*/
- #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
- #endif
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
@@ -215,13 +211,6 @@ void SystemInit(void)
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
- /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
- SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
- SCB->VTOR = NVIC_FLASH_VECTOR_ADDRESS; /* Vector Table Relocation in Internal FLASH */
-#endif
-
/* Configure the Cube driver */
SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
HAL_Init();
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f429xx.s b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f429xx.s
index c175588c0da..98fa2ebd32e 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f429xx.s
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f429xx.s
@@ -197,9 +197,15 @@ __Vectors_Size EQU __Vectors_End - __Vectors
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInitPre
+ IMPORT HAL_InitPre
IMPORT SystemInit
IMPORT __main
+ LDR R0, =SystemInitPre
+ BLX R0
+ LDR R0, =HAL_InitPre
+ BLX R0
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_STD/startup_stm32f429xx.s b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_STD/startup_stm32f429xx.s
index ad3a376725c..2acea79cfa4 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_STD/startup_stm32f429xx.s
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_STD/startup_stm32f429xx.s
@@ -170,9 +170,15 @@ __Vectors_Size EQU __Vectors_End - __Vectors
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInitPre
+ IMPORT HAL_InitPre
IMPORT SystemInit
IMPORT __main
+ LDR R0, =SystemInitPre
+ BLX R0
+ LDR R0, =HAL_InitPre
+ BLX R0
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_IAR/startup_stm32f429xx.S b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_IAR/startup_stm32f429xx.S
index 6c829d34a11..6d95580872e 100644
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_IAR/startup_stm32f429xx.S
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_IAR/startup_stm32f429xx.S
@@ -63,6 +63,8 @@
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
+ EXTERN SystemInitPre
+ EXTERN HAL_InitPre
EXTERN SystemInit
PUBLIC __vector_table
@@ -188,6 +190,10 @@ __vector_table
SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
+ LDR R0, =SystemInitPre
+ BLX R0
+ LDR R0, =HAL_InitPre
+ BLX R0
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start