diff --git a/TESTS/mbed_hal/qspi/flash_configs/flash_configs.h b/TESTS/mbed_hal/qspi/flash_configs/flash_configs.h index 180a3d3bd72..215c75caf7e 100644 --- a/TESTS/mbed_hal/qspi/flash_configs/flash_configs.h +++ b/TESTS/mbed_hal/qspi/flash_configs/flash_configs.h @@ -69,7 +69,8 @@ defined(TARGET_CY8CPROTO_062S2_43012) || \ defined(TARGET_CY8CPROTO_062S3_4343W) || \ defined(TARGET_CYW943012P6EVB_01) || \ - defined(TARGET_CYW9P62S1_43438EVB_01)) + defined(TARGET_CYW9P62S1_43438EVB_01) || \ + defined(TARGET_CYSBSYSKIT_01)) #include "S25FL512S_config.h" #elif defined(TARGET_CYW9P62S1_43012EVB_01) diff --git a/TESTS/mbed_hal_fpga_ci_test_shield/uart/main.cpp b/TESTS/mbed_hal_fpga_ci_test_shield/uart/main.cpp index 56c94347af4..1ee96b95b78 100644 --- a/TESTS/mbed_hal_fpga_ci_test_shield/uart/main.cpp +++ b/TESTS/mbed_hal_fpga_ci_test_shield/uart/main.cpp @@ -133,6 +133,9 @@ static void uart_test_common(int baudrate, int data_bits, SerialParity parity, i serial_set_flow_control_direct(&serial, FlowControlRTSCTS, &pinmap); #else //skip this test case if static pinmap is not supported + // Cleanup uart to be able execute next test case + serial_free(&serial); + tester.reset(); return; #endif } else { diff --git a/features/FEATURE_BLE/targets/TARGET_Cypress/COMPONENT_CYW43XXX/firmware/COMPONENT_43012/w_bt_firmware_controller.c b/features/FEATURE_BLE/targets/TARGET_Cypress/COMPONENT_CYW43XXX/firmware/COMPONENT_43012/w_bt_firmware_controller.c index 621771321d0..577a49f78c1 100644 --- a/features/FEATURE_BLE/targets/TARGET_Cypress/COMPONENT_CYW43XXX/firmware/COMPONENT_43012/w_bt_firmware_controller.c +++ b/features/FEATURE_BLE/targets/TARGET_Cypress/COMPONENT_CYW43XXX/firmware/COMPONENT_43012/w_bt_firmware_controller.c @@ -2,6 +2,7 @@ /* labelling: appname-(chipname)(stepping)-frequency-(headset GIT SHA)-(generating SDK version)- * Wiced-release.hcd */ +#ifndef TARGET_CYW9P62S1_43012EVB_01 const char brcm_patch_version[] = "CYW43012C0_003.001.015.0128.0000_Generic_UART_37_4MHz_wlcsp_ref3_sLNA"; const uint8_t brcm_patchram_format = 0x01; /* Configuration Data Records (Write_RAM) */ @@ -4061,3 +4062,4 @@ const uint8_t brcm_patchram_buf[] = { }; const int brcm_patch_ram_length = sizeof(brcm_patchram_buf); +#endif diff --git a/features/FEATURE_BLE/targets/TARGET_Cypress/COMPONENT_CYW43XXX/firmware/TARGET_CYW9P62S1_43012EVB_01/w_bt_firmware_controller.c b/features/FEATURE_BLE/targets/TARGET_Cypress/COMPONENT_CYW43XXX/firmware/TARGET_CYW9P62S1_43012EVB_01/w_bt_firmware_controller.c new file mode 100644 index 00000000000..cfddd7f547d --- /dev/null +++ b/features/FEATURE_BLE/targets/TARGET_Cypress/COMPONENT_CYW43XXX/firmware/TARGET_CYW9P62S1_43012EVB_01/w_bt_firmware_controller.c @@ -0,0 +1,4222 @@ +#include + +/* labelling: appname-(chipname)(stepping)-frequency-(headset GIT SHA)-(generating SDK version)- + * Wiced-release.hcd */ +const char brcm_patch_version[] = " CYW43012C0_003.001.015.0144.0000_Generic_UART_37_4MHz_wlbga_ref3_sLNA_USI"; +const uint8_t brcm_patchram_format = 0x01; +/* Configuration Data Records (Write_RAM) */ +const uint8_t brcm_patchram_buf[71349] = { + 76, 252, 70, 0, 0, 34, 0, 66, 82, 67, 77, 99, 102, 103, 83, 0, 0, 0, + 0, 50, 0, 0, 0, 1, 1, 4, 24, 146, 0, 0, 0, 3, 6, 172, 31, 0, 44, 1, + 67, 0, 1, 28, 66, 0, 34, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 254, 0, 0, 76, 252, 204, 66, 0, 34, 0, + 66, 82, 67, 77, 99, 102, 103, 68, 0, 0, 0, 0, 230, 12, 1, 0, 3, 3, 31, + 67, 89, 87, 52, 51, 48, 49, 50, 67, 48, 32, 85, 65, 82, 84, 32, 87, + 76, 66, 71, 65, 32, 115, 76, 78, 65, 32, 85, 83, 73, 0, 22, 3, 2, 144, + 0, 3, 1, 8, 112, 158, 32, 0, 0, 0, 0, 0, 3, 1, 5, 52, 210, 33, 0, 0, + 3, 1, 5, 208, 196, 32, 0, 1, 3, 1, 5, 209, 196, 32, 0, 1, 0, 7, 4, 31, + 0, 0, 0, 1, 7, 158, 4, 0, 6, 10, 35, 60, 90, 110, 125, 5, 101, 3, 134, + 3, 162, 3, 182, 3, 177, 3, 196, 3, 233, 3, 2, 4, 52, 4, 16, 4, 232, + 3, 242, 3, 21, 4, 71, 4, 26, 4, 66, 4, 94, 4, 112, 4, 124, 4, 117, 4, + 165, 4, 202, 4, 213, 4, 3, 5, 4, 5, 228, 4, 254, 4, 227, 4, 61, 5, 23, + 5, 20, 255, 20, 255, 20, 255, 20, 255, 20, 255, 20, 255, 100, 4, 17, + 4, 151, 5, 198, 4, 201, 4, 15, 5, 9, 5, 82, 5, 64, 5, 76, 252, 204, + 10, 1, 34, 0, 91, 5, 65, 5, 55, 5, 130, 5, 170, 5, 150, 5, 175, 5, 182, + 5, 236, 5, 234, 5, 29, 6, 185, 5, 192, 5, 236, 5, 4, 6, 40, 6, 190, + 5, 187, 5, 251, 5, 10, 6, 45, 6, 20, 255, 20, 255, 20, 255, 20, 255, + 20, 255, 20, 255, 7, 1, 0, 0, 96, 0, 5, 156, 2, 255, 160, 2, 255, 164, + 2, 255, 168, 2, 255, 172, 2, 255, 0, 0, 96, 0, 5, 200, 2, 255, 204, + 2, 255, 208, 2, 255, 212, 2, 255, 216, 2, 255, 0, 0, 96, 0, 5, 188, + 4, 255, 192, 4, 255, 196, 4, 255, 200, 4, 255, 204, 4, 255, 0, 0, 96, + 0, 5, 132, 11, 255, 120, 8, 255, 72, 11, 255, 248, 4, 255, 252, 4, 255, + 0, 0, 96, 0, 5, 0, 5, 255, 4, 5, 255, 8, 5, 255, 12, 5, 255, 16, 5, + 255, 0, 0, 96, 0, 5, 20, 5, 255, 24, 5, 255, 28, 5, 255, 224, 9, 255, + 128, 10, 255, 0, 0, 96, 0, 5, 228, 4, 255, 232, 4, 255, 236, 4, 255, + 240, 4, 255, 244, 4, 255, 0, 0, 65, 0, 76, 252, 204, 210, 1, 34, 0, + 2, 128, 3, 255, 255, 136, 4, 255, 255, 78, 76, 78, 85, 86, 76, 74, 75, + 80, 83, 124, 124, 124, 124, 124, 0, 10, 34, 101, 101, 101, 101, 101, + 105, 105, 105, 105, 105, 165, 68, 89, 89, 89, 89, 89, 96, 92, 95, 103, + 105, 95, 92, 93, 99, 103, 124, 124, 124, 124, 124, 0, 9, 34, 101, 101, + 101, 101, 101, 87, 87, 87, 87, 87, 165, 68, 90, 90, 90, 90, 90, 118, + 114, 117, 127, 129, 115, 112, 113, 120, 125, 124, 124, 124, 124, 124, + 0, 8, 34, 101, 101, 101, 101, 101, 87, 87, 87, 87, 87, 165, 68, 90, + 90, 90, 90, 90, 143, 138, 142, 154, 156, 142, 139, 140, 149, 155, 124, + 124, 124, 124, 124, 0, 8, 34, 101, 101, 101, 101, 101, 87, 87, 87, 87, + 87, 165, 68, 90, 90, 90, 90, 90, 165, 159, 163, 177, 180, 163, 159, + 160, 170, 177, 124, 124, 124, 124, 124, 0, 7, 34, 101, 101, 101, 101, + 101, 87, 87, 87, 87, 87, 165, 68, 90, 90, 90, 90, 90, 193, 186, 191, + 207, 210, 189, 184, 186, 197, 205, 124, 124, 124, 124, 124, 7, 76, 252, + 204, 154, 2, 34, 0, 6, 82, 105, 105, 105, 105, 105, 105, 105, 105, 105, + 105, 165, 68, 90, 90, 90, 90, 90, 219, 19, 0, 4, 222, 19, 0, 4, 222, + 19, 0, 4, 222, 19, 0, 4, 222, 19, 0, 4, 222, 19, 0, 4, 2, 7, 127, 2, + 6, 5, 197, 3, 192, 3, 202, 3, 217, 3, 222, 3, 46, 4, 41, 4, 46, 4, 91, + 4, 66, 4, 86, 4, 51, 4, 66, 4, 111, 4, 76, 4, 186, 4, 166, 4, 161, 4, + 166, 4, 171, 4, 40, 5, 25, 5, 10, 5, 50, 5, 65, 5, 110, 5, 80, 5, 25, + 5, 110, 5, 85, 5, 20, 255, 20, 255, 20, 255, 20, 255, 20, 255, 20, 255, + 1, 0, 0, 0, 96, 0, 5, 156, 2, 255, 160, 2, 255, 164, 2, 255, 168, 2, + 255, 172, 2, 255, 30, 30, 31, 31, 33, 49, 50, 51, 51, 56, 134, 134, + 134, 134, 134, 100, 100, 99, 103, 113, 154, 149, 151, 161, 181, 200, + 197, 202, 219, 218, 2, 7, 127, 0, 6, 5, 197, 3, 192, 3, 202, 3, 217, + 3, 222, 3, 46, 4, 41, 4, 46, 4, 91, 4, 66, 4, 86, 76, 252, 204, 98, + 3, 34, 0, 4, 51, 4, 66, 4, 111, 4, 76, 4, 186, 4, 166, 4, 161, 4, 166, + 4, 171, 4, 40, 5, 25, 5, 10, 5, 50, 5, 65, 5, 110, 5, 80, 5, 25, 5, + 110, 5, 85, 5, 20, 255, 20, 255, 20, 255, 20, 255, 20, 255, 20, 255, + 1, 0, 0, 0, 96, 0, 5, 156, 2, 255, 160, 2, 255, 164, 2, 255, 168, 2, + 255, 172, 2, 255, 78, 76, 78, 85, 86, 96, 92, 95, 103, 105, 118, 114, + 117, 127, 129, 143, 138, 142, 154, 156, 165, 159, 163, 177, 180, 193, + 186, 191, 207, 210, 2, 1, 160, 23, 12, 0, 65, 0, 255, 255, 255, 255, + 84, 64, 0, 0, 24, 0, 65, 0, 255, 255, 255, 255, 7, 126, 0, 0, 136, 0, + 65, 0, 255, 255, 255, 255, 0, 0, 0, 0, 192, 0, 65, 0, 255, 255, 255, + 255, 129, 1, 0, 0, 60, 1, 65, 0, 255, 255, 255, 255, 42, 5, 0, 0, 68, + 1, 65, 0, 255, 255, 255, 255, 12, 9, 0, 0, 72, 1, 65, 0, 255, 255, 255, + 255, 46, 3, 0, 0, 96, 1, 65, 0, 255, 255, 255, 255, 10, 76, 252, 204, + 42, 4, 34, 0, 9, 0, 0, 112, 1, 65, 0, 255, 255, 255, 255, 222, 23, 0, + 0, 124, 1, 65, 0, 255, 255, 255, 255, 42, 5, 0, 0, 128, 3, 65, 0, 255, + 255, 255, 255, 222, 19, 0, 0, 132, 3, 65, 0, 255, 255, 255, 255, 215, + 206, 0, 0, 136, 3, 65, 0, 255, 255, 255, 255, 249, 63, 0, 0, 140, 3, + 65, 0, 255, 255, 255, 255, 133, 172, 0, 0, 144, 3, 65, 0, 255, 255, + 255, 255, 93, 28, 0, 0, 232, 3, 65, 0, 255, 255, 255, 255, 28, 0, 0, + 0, 148, 4, 65, 0, 255, 255, 255, 255, 108, 2, 0, 0, 192, 4, 65, 0, 255, + 255, 255, 255, 0, 128, 0, 0, 28, 6, 65, 0, 255, 255, 255, 255, 47, 64, + 0, 0, 32, 6, 65, 0, 255, 255, 255, 255, 37, 64, 0, 0, 36, 6, 65, 0, + 255, 255, 255, 255, 20, 64, 0, 0, 40, 6, 65, 0, 255, 255, 255, 255, + 163, 67, 0, 0, 44, 6, 65, 0, 255, 255, 255, 255, 82, 64, 0, 0, 52, 7, + 65, 0, 255, 255, 255, 255, 33, 98, 0, 0, 240, 7, 65, 0, 255, 76, 252, + 204, 242, 4, 34, 0, 255, 255, 255, 49, 128, 0, 0, 160, 8, 65, 0, 255, + 255, 255, 255, 49, 1, 0, 0, 168, 8, 65, 0, 255, 255, 255, 255, 80, 3, + 0, 0, 164, 8, 65, 0, 255, 255, 255, 255, 83, 1, 0, 0, 160, 8, 65, 0, + 255, 255, 255, 255, 55, 1, 0, 0, 156, 8, 65, 0, 255, 255, 255, 255, + 0, 1, 0, 0, 8, 0, 96, 0, 255, 255, 255, 255, 5, 0, 0, 0, 52, 0, 96, + 0, 255, 255, 255, 255, 15, 0, 0, 0, 36, 1, 96, 0, 255, 255, 255, 255, + 57, 0, 0, 0, 40, 1, 96, 0, 255, 255, 255, 255, 63, 0, 0, 0, 44, 1, 96, + 0, 255, 255, 255, 255, 86, 0, 0, 0, 48, 1, 96, 0, 255, 255, 255, 255, + 32, 0, 0, 0, 80, 1, 96, 0, 255, 255, 255, 255, 1, 0, 0, 0, 52, 1, 96, + 0, 255, 255, 255, 255, 9, 0, 0, 0, 88, 1, 96, 0, 255, 255, 255, 255, + 33, 0, 0, 0, 220, 1, 96, 0, 255, 255, 255, 255, 133, 0, 0, 0, 224, 1, + 96, 0, 255, 255, 255, 255, 37, 0, 0, 0, 228, 76, 252, 204, 186, 5, 34, + 0, 1, 96, 0, 255, 255, 255, 255, 62, 0, 0, 0, 232, 1, 96, 0, 255, 255, + 255, 255, 38, 0, 0, 0, 236, 1, 96, 0, 255, 255, 255, 255, 100, 0, 0, + 0, 244, 1, 96, 0, 255, 255, 255, 255, 156, 0, 0, 0, 156, 2, 96, 0, 255, + 255, 255, 255, 80, 0, 0, 0, 160, 2, 96, 0, 255, 255, 255, 255, 80, 0, + 0, 0, 164, 2, 96, 0, 255, 255, 255, 255, 80, 0, 0, 0, 168, 2, 96, 0, + 255, 255, 255, 255, 80, 0, 0, 0, 172, 2, 96, 0, 255, 255, 255, 255, + 80, 0, 0, 0, 200, 2, 96, 0, 255, 255, 255, 255, 80, 0, 0, 0, 204, 2, + 96, 0, 255, 255, 255, 255, 80, 0, 0, 0, 208, 2, 96, 0, 255, 255, 255, + 255, 80, 0, 0, 0, 212, 2, 96, 0, 255, 255, 255, 255, 80, 0, 0, 0, 216, + 2, 96, 0, 255, 255, 255, 255, 80, 0, 0, 0, 24, 3, 96, 0, 255, 255, 255, + 255, 80, 0, 0, 0, 28, 3, 96, 0, 255, 255, 255, 255, 80, 0, 0, 0, 32, + 3, 96, 0, 255, 255, 255, 255, 80, 76, 252, 204, 130, 6, 34, 0, 0, 0, + 0, 36, 3, 96, 0, 255, 255, 255, 255, 80, 0, 0, 0, 76, 3, 96, 0, 255, + 255, 255, 255, 97, 0, 0, 0, 80, 3, 96, 0, 255, 255, 255, 255, 97, 0, + 0, 0, 84, 3, 96, 0, 255, 255, 255, 255, 97, 0, 0, 0, 88, 3, 96, 0, 255, + 255, 255, 255, 97, 0, 0, 0, 92, 3, 96, 0, 255, 255, 255, 255, 97, 0, + 0, 0, 116, 2, 96, 0, 255, 255, 255, 255, 63, 0, 0, 0, 128, 3, 96, 0, + 255, 255, 255, 255, 4, 0, 0, 0, 156, 3, 96, 0, 255, 255, 255, 255, 0, + 0, 0, 0, 160, 3, 96, 0, 255, 255, 255, 255, 0, 0, 0, 0, 164, 3, 96, + 0, 255, 255, 255, 255, 0, 0, 0, 0, 168, 3, 96, 0, 255, 255, 255, 255, + 0, 0, 0, 0, 176, 3, 96, 0, 255, 255, 255, 255, 80, 0, 0, 0, 180, 3, + 96, 0, 255, 255, 255, 255, 80, 0, 0, 0, 184, 3, 96, 0, 255, 255, 255, + 255, 80, 0, 0, 0, 188, 3, 96, 0, 255, 255, 255, 255, 80, 0, 0, 0, 216, + 3, 96, 0, 255, 76, 252, 204, 74, 7, 34, 0, 255, 255, 255, 136, 0, 0, + 0, 244, 3, 96, 0, 255, 255, 255, 255, 64, 0, 0, 0, 168, 4, 96, 0, 255, + 255, 255, 255, 119, 0, 0, 0, 172, 4, 96, 0, 255, 255, 255, 255, 119, + 0, 0, 0, 176, 4, 96, 0, 255, 255, 255, 255, 119, 0, 0, 0, 180, 4, 96, + 0, 255, 255, 255, 255, 119, 0, 0, 0, 184, 4, 96, 0, 255, 255, 255, 255, + 119, 0, 0, 0, 188, 4, 96, 0, 255, 255, 255, 255, 111, 0, 0, 0, 192, + 4, 96, 0, 255, 255, 255, 255, 111, 0, 0, 0, 196, 4, 96, 0, 255, 255, + 255, 255, 111, 0, 0, 0, 200, 4, 96, 0, 255, 255, 255, 255, 111, 0, 0, + 0, 204, 4, 96, 0, 255, 255, 255, 255, 111, 0, 0, 0, 208, 4, 96, 0, 255, + 255, 255, 255, 87, 0, 0, 0, 212, 4, 96, 0, 255, 255, 255, 255, 87, 0, + 0, 0, 216, 4, 96, 0, 255, 255, 255, 255, 87, 0, 0, 0, 220, 4, 96, 0, + 255, 255, 255, 255, 87, 0, 0, 0, 224, 4, 96, 0, 255, 255, 255, 255, + 87, 0, 0, 0, 228, 76, 252, 204, 18, 8, 34, 0, 4, 96, 0, 255, 255, 255, + 255, 87, 0, 0, 0, 232, 4, 96, 0, 255, 255, 255, 255, 87, 0, 0, 0, 236, + 4, 96, 0, 255, 255, 255, 255, 87, 0, 0, 0, 240, 4, 96, 0, 255, 255, + 255, 255, 87, 0, 0, 0, 244, 4, 96, 0, 255, 255, 255, 255, 87, 0, 0, + 0, 248, 4, 96, 0, 255, 255, 255, 255, 101, 0, 0, 0, 252, 4, 96, 0, 255, + 255, 255, 255, 101, 0, 0, 0, 0, 5, 96, 0, 255, 255, 255, 255, 101, 0, + 0, 0, 4, 5, 96, 0, 255, 255, 255, 255, 101, 0, 0, 0, 8, 5, 96, 0, 255, + 255, 255, 255, 101, 0, 0, 0, 12, 5, 96, 0, 255, 255, 255, 255, 101, + 0, 0, 0, 16, 5, 96, 0, 255, 255, 255, 255, 101, 0, 0, 0, 20, 5, 96, + 0, 255, 255, 255, 255, 101, 0, 0, 0, 24, 5, 96, 0, 255, 255, 255, 255, + 101, 0, 0, 0, 28, 5, 96, 0, 255, 255, 255, 255, 101, 0, 0, 0, 56, 5, + 96, 0, 255, 255, 255, 255, 14, 0, 0, 0, 112, 5, 96, 0, 255, 255, 255, + 255, 31, 76, 252, 204, 218, 8, 34, 0, 0, 0, 0, 160, 5, 96, 0, 255, 255, + 255, 255, 38, 0, 0, 0, 168, 5, 96, 0, 255, 255, 255, 255, 150, 0, 0, + 0, 4, 6, 96, 0, 255, 255, 255, 255, 31, 0, 0, 0, 52, 6, 96, 0, 255, + 255, 255, 255, 38, 0, 0, 0, 60, 6, 96, 0, 255, 255, 255, 255, 150, 0, + 0, 0, 168, 6, 96, 0, 255, 255, 255, 255, 125, 0, 0, 0, 172, 6, 96, 0, + 255, 255, 255, 255, 127, 0, 0, 0, 176, 6, 96, 0, 255, 255, 255, 255, + 132, 0, 0, 0, 180, 6, 96, 0, 255, 255, 255, 255, 142, 0, 0, 0, 184, + 6, 96, 0, 255, 255, 255, 255, 152, 0, 0, 0, 188, 6, 96, 0, 255, 255, + 255, 255, 158, 0, 0, 0, 192, 6, 96, 0, 255, 255, 255, 255, 168, 0, 0, + 0, 196, 6, 96, 0, 255, 255, 255, 255, 180, 0, 0, 0, 200, 6, 96, 0, 255, + 255, 255, 255, 199, 0, 0, 0, 204, 6, 96, 0, 255, 255, 255, 255, 64, + 0, 0, 0, 208, 6, 96, 0, 255, 255, 255, 255, 67, 0, 0, 0, 212, 6, 96, + 0, 255, 76, 252, 204, 162, 9, 34, 0, 255, 255, 255, 71, 0, 0, 0, 216, + 6, 96, 0, 255, 255, 255, 255, 74, 0, 0, 0, 220, 6, 96, 0, 255, 255, + 255, 255, 80, 0, 0, 0, 224, 6, 96, 0, 255, 255, 255, 255, 85, 0, 0, + 0, 228, 6, 96, 0, 255, 255, 255, 255, 89, 0, 0, 0, 232, 6, 96, 0, 255, + 255, 255, 255, 95, 0, 0, 0, 236, 6, 96, 0, 255, 255, 255, 255, 102, + 0, 0, 0, 160, 7, 96, 0, 255, 255, 255, 255, 25, 0, 0, 0, 152, 7, 96, + 0, 255, 255, 255, 255, 24, 0, 0, 0, 72, 7, 96, 0, 255, 255, 255, 255, + 63, 0, 0, 0, 124, 7, 96, 0, 255, 255, 255, 255, 42, 0, 0, 0, 184, 7, + 96, 0, 255, 255, 255, 255, 80, 0, 0, 0, 192, 7, 96, 0, 255, 255, 255, + 255, 80, 0, 0, 0, 200, 7, 96, 0, 255, 255, 255, 255, 80, 0, 0, 0, 208, + 7, 96, 0, 255, 255, 255, 255, 80, 0, 0, 0, 216, 7, 96, 0, 255, 255, + 255, 255, 80, 0, 0, 0, 236, 7, 96, 0, 255, 255, 255, 255, 47, 0, 0, + 0, 240, 76, 252, 204, 106, 10, 34, 0, 7, 96, 0, 255, 255, 255, 255, + 47, 0, 0, 0, 244, 7, 96, 0, 255, 255, 255, 255, 47, 0, 0, 0, 224, 9, + 96, 0, 255, 255, 255, 255, 165, 0, 0, 0, 12, 8, 96, 0, 255, 255, 255, + 255, 108, 0, 0, 0, 28, 8, 96, 0, 255, 255, 255, 255, 144, 0, 0, 0, 48, + 8, 96, 0, 255, 255, 255, 255, 76, 0, 0, 0, 100, 8, 96, 0, 255, 255, + 255, 255, 12, 0, 0, 0, 116, 8, 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brcm_patch_ram_length = sizeof(brcm_patchram_buf); diff --git a/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.cpp b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.cpp new file mode 100644 index 00000000000..5a17077efbb --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.cpp @@ -0,0 +1,328 @@ +/* + * Copyright 2018-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include "SclSTAInterface.h" +#include "nsapi.h" +#include "lwipopts.h" +#include "lwip/etharp.h" +#include "lwip/ethip6.h" +#include "rtos.h" +#include "scl_emac.h" +#include "scl_ipc.h" +#include "mbed_wait_api.h" + + +/** @file + * Provides SCL interface functions to be used with WiFiInterface or NetworkInterface Objects + */ + +struct scl_tx_nw_credentials { + nsapi_security_t network_security_type; + int ssid_len; + int pass_len; + const char *network_ssid; + const char *network_passphrase; +} scl_tx_nw_credentials_t; + +network_params_t network_parameter; + +int scl_toerror(scl_result_t res) +{ + switch (res) { + case SCL_SUCCESS: + return NSAPI_ERROR_OK; + case SCL_UNSUPPORTED: + return NSAPI_ERROR_UNSUPPORTED; + case SCL_BADARG: + return NSAPI_ERROR_PARAMETER; + case SCL_INVALID_JOIN_STATUS: + return NSAPI_ERROR_NO_CONNECTION; + case SCL_BUFFER_UNAVAILABLE_PERMANENT: + case SCL_BUFFER_UNAVAILABLE_TEMPORARY: + case SCL_RX_BUFFER_ALLOC_FAIL: + case SCL_BUFFER_ALLOC_FAIL: + case SCL_MALLOC_FAILURE: + return NSAPI_ERROR_NO_MEMORY; + case SCL_ACCESS_POINT_NOT_FOUND: + case SCL_NETWORK_NOT_FOUND: + return NSAPI_ERROR_NO_SSID; + case SCL_NOT_AUTHENTICATED: + case SCL_INVALID_KEY: + case SCL_NOT_KEYED: + return NSAPI_ERROR_AUTH_FAILURE; + case SCL_PENDING: + case SCL_JOIN_IN_PROGRESS: + return NSAPI_ERROR_IN_PROGRESS; + case SCL_CONNECTION_LOST: + return NSAPI_ERROR_CONNECTION_LOST; + case SCL_TIMEOUT: + case SCL_EAPOL_KEY_PACKET_M1_TIMEOUT: + case SCL_EAPOL_KEY_PACKET_M3_TIMEOUT: + case SCL_EAPOL_KEY_PACKET_G1_TIMEOUT: + return NSAPI_ERROR_CONNECTION_TIMEOUT; + default: + return -res; + } +} + +nsapi_security_t scl_tosecurity(scl_security_t sec) +{ + switch (sec) { + case SCL_SECURITY_OPEN: + return NSAPI_SECURITY_NONE; + case SCL_SECURITY_WEP_PSK: + case SCL_SECURITY_WEP_SHARED: + return NSAPI_SECURITY_WEP; + case SCL_SECURITY_WPA_TKIP_PSK: + case SCL_SECURITY_WPA_TKIP_ENT: + return NSAPI_SECURITY_WPA; + case SCL_SECURITY_WPA2_MIXED_PSK: + return NSAPI_SECURITY_WPA_WPA2; + case SCL_SECURITY_WPA2_AES_PSK: + case SCL_SECURITY_WPA2_AES_ENT: + case SCL_SECURITY_WPA2_FBT_PSK: + case SCL_SECURITY_WPA2_FBT_ENT: + return NSAPI_SECURITY_WPA2; + default: + return NSAPI_SECURITY_UNKNOWN; + } +} + +scl_security_t scl_fromsecurity(nsapi_security_t sec) +{ + switch (sec) { + case NSAPI_SECURITY_NONE: + return SCL_SECURITY_OPEN; + case NSAPI_SECURITY_WEP: + return SCL_SECURITY_WEP_PSK; + case NSAPI_SECURITY_WPA: + return SCL_SECURITY_WPA_MIXED_PSK; + case NSAPI_SECURITY_WPA2: + return SCL_SECURITY_WPA2_AES_PSK; + case NSAPI_SECURITY_WPA_WPA2: + return SCL_SECURITY_WPA2_MIXED_PSK; + default: + return SCL_SECURITY_UNKNOWN; + } +} + +SclSTAInterface::SclSTAInterface(SCL_EMAC &emac, OnboardNetworkStack &stack) + : EMACInterface(emac, stack), + _ssid("\0"), + _pass("\0"), + _security(NSAPI_SECURITY_NONE), + _scl_emac(emac) +{ +} + +nsapi_error_t SclSTAInterface::connect(const char *ssid, const char *pass, nsapi_security_t security, uint8_t channel) +{ + int err = set_channel(channel); + if (err) { + return err; + } + + err = set_credentials(ssid, pass, security); + if (err) { + return err; + } + + return connect(); +} + +nsapi_error_t SclSTAInterface::set_credentials(const char *ssid, const char *pass, nsapi_security_t security) +{ + if ((ssid == NULL) || + (strlen(ssid) == 0) || + (pass == NULL && (security != NSAPI_SECURITY_NONE)) || + (strlen(pass) == 0 && (security != NSAPI_SECURITY_NONE)) || + (strlen(pass) > 63 && (security == NSAPI_SECURITY_WPA2 || security == NSAPI_SECURITY_WPA || security == NSAPI_SECURITY_WPA_WPA2)) + ) { + return NSAPI_ERROR_PARAMETER; + } + + memset(_ssid, 0, sizeof(_ssid)); + strncpy(_ssid, ssid, sizeof(_ssid)); + + memset(_pass, 0, sizeof(_pass)); + strncpy(_pass, pass, sizeof(_pass)); + + _security = security; + + return NSAPI_ERROR_OK; +} + +nsapi_error_t SclSTAInterface::connect() +{ + + uint32_t delay_timeout = 0; + scl_result_t ret_val; + nsapi_error_t interface_status; + uint32_t connection_status = 0; + + scl_tx_nw_credentials_t.network_ssid = _ssid; + if (strlen(_ssid) < MAX_SSID_LENGTH) { + scl_tx_nw_credentials_t.ssid_len = strlen(_ssid); + } + scl_tx_nw_credentials_t.network_passphrase = _pass; + if (strlen(_pass) < MAX_PASSWORD_LENGTH) { + scl_tx_nw_credentials_t.pass_len = strlen(_pass); + } + scl_tx_nw_credentials_t.network_security_type = _security; + + ret_val = scl_send_data(SCL_TX_CONNECT, (char *)&scl_tx_nw_credentials_t, TIMER_DEFAULT_VALUE); + + if (ret_val == SCL_SUCCESS) { + SCL_LOG(("wifi provisioning in progress")); + } + + network_parameter.connection_status = NSAPI_STATUS_DISCONNECTED; + + + //Get the network parameter from NP + while ((network_parameter.connection_status != NSAPI_STATUS_GLOBAL_UP) && delay_timeout < NW_CONNECT_TIMEOUT) { + ret_val = scl_get_nw_parameters(&network_parameter); + wait_us(NW_DELAY_TIME_US); + delay_timeout++; + } + + if (delay_timeout >= NW_CONNECT_TIMEOUT || ret_val != SCL_SUCCESS) { + return NSAPI_ERROR_NO_CONNECTION; + } + + if (!_scl_emac.powered_up) { + _scl_emac.power_up(); + } + + if (!_interface) { + nsapi_error_t err = _stack.add_ethernet_interface(_emac, true, &_interface); + if (err != NSAPI_ERROR_OK) { + _interface = NULL; + return err; + } + _interface->attach(_connection_status_cb); + } + + if (!scl_wifi_is_ready_to_transceive()) { + scl_emac_wifi_link_state_changed(true); + } + + interface_status = _interface->bringup(false, + network_parameter.ip_address, + network_parameter.netmask, + network_parameter.gateway, + DEFAULT_STACK); + + scl_send_data(SCL_TX_CONNECTION_STATUS, (char *)&connection_status, TIMER_DEFAULT_VALUE); + + return interface_status; +} + +void SclSTAInterface::wifi_on() +{ + if (!_scl_emac.powered_up) { + _scl_emac.power_up(); + } +} + +nsapi_error_t SclSTAInterface::disconnect() +{ + scl_result_t ret_val; + nsapi_error_t disconnect_status; + ret_val = scl_send_data(SCL_TX_DISCONNECT, (char *)&disconnect_status, TIMER_DEFAULT_VALUE); + + if (ret_val == SCL_ERROR) { + return NSAPI_ERROR_TIMEOUT; + } + + if (!_interface) { + return NSAPI_STATUS_DISCONNECTED; + } + + // bring down + int err = _interface->bringdown(); + if (err) { + return err; + } + + scl_emac_wifi_link_state_changed(false); + + return NSAPI_ERROR_OK; +} + +int SclSTAInterface::scan(WiFiAccessPoint *res, unsigned count) +{ + /* To Do */ + return NSAPI_ERROR_UNSUPPORTED; +} + +int8_t SclSTAInterface::get_rssi() +{ + int32_t rssi; + scl_result_t res; + + if (!_scl_emac.powered_up) { + _scl_emac.power_up(); + } + + res = (scl_result_t) scl_wifi_get_rssi(&rssi); + if (res == SCL_ERROR) { + return SCL_ERROR; + } + + return (int8_t)rssi; +} + +int SclSTAInterface::is_interface_connected(void) +{ + if (scl_wifi_is_ready_to_transceive() == SCL_SUCCESS) { + return SCL_SUCCESS; + } else { + return SCL_CONNECTION_LOST; + } +} + +int SclSTAInterface::get_bssid(uint8_t *bssid) +{ + scl_mac_t ap_mac; + scl_result_t res = SCL_SUCCESS; + + if (bssid == NULL) { + return SCL_BADARG; + } + + memset(&ap_mac, 0, sizeof(ap_mac)); + if (scl_wifi_is_ready_to_transceive() == SCL_SUCCESS) { + res = (scl_result_t) scl_wifi_get_bssid(&ap_mac); + if (res == SCL_SUCCESS) { + memcpy(bssid, ap_mac.octet, sizeof(ap_mac.octet)); + } + } else { + return SCL_CONNECTION_LOST; + } + return res; +} + +int SclSTAInterface::wifi_set_up(void) +{ + int res = SCL_SUCCESS; + res = scl_wifi_set_up(); + return res; +} diff --git a/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.h b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.h new file mode 100644 index 00000000000..801a9a5dfc7 --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/SclSTAInterface.h @@ -0,0 +1,165 @@ +/* + * Copyright 2018-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef SCL_STA_INTERFACE_H +#define SCL_STA_INTERFACE_H + + +/** @file + * Provides SCL interface functions to be used with WiFiInterface or NetworkInterface Objects + */ + +#include "netsocket/WiFiInterface.h" +#include "netsocket/EMACInterface.h" +#include "netsocket/OnboardNetworkStack.h" +#include "scl_emac.h" +#include "scl_wifi_api.h" +#include "scl_types.h" +#define MAX_SSID_LENGTH (33) /**< Maximum ssid length */ +#define MAX_PASSWORD_LENGTH (64) /**< Maximum password length */ + +/** SclSTAInterface class + * Implementation of the Network Stack for the SCL + */ +class SclSTAInterface : public WiFiInterface, public EMACInterface { +public: + + SclSTAInterface( + SCL_EMAC &emac = SCL_EMAC::get_instance(), + OnboardNetworkStack &stack = OnboardNetworkStack::get_default_instance()); + + /** Gets the current instance of the SclSTAInterface + * + * @return Pointer to the object of class SclSTAInterface. + */ + static SclSTAInterface *get_default_instance(); + + /** Turns on the Wi-Fi device + * + * @return void + */ + void wifi_on(); + + /** Starts the interface + * + * Attempts to connect to a Wi-Fi network. Requires ssid and passphrase to be set. + * If passphrase is invalid, NSAPI_ERROR_AUTH_ERROR is returned. + * + * @return 0 on success, negative error code on failure. + */ + nsapi_error_t connect(); + + /** Starts the interface + * + * Attempts to connect to a Wi-Fi network. + * + * @param ssid Name of the network to connect to. + * @param pass Security passphrase to connect to the network. + * @param security Type of encryption for connection (Default: NSAPI_SECURITY_NONE). + * @param channel This parameter is not supported, setting it to a value other than 0 will result in NSAPI_ERROR_UNSUPPORTED. + * @return 0 on success, negative error code on failure. + */ + nsapi_error_t connect(const char *ssid, const char *pass, nsapi_security_t security = NSAPI_SECURITY_NONE, uint8_t channel = 0); + + /** Disconnects the interface + * + * @return 0 on success, negative error code on failure. + */ + nsapi_error_t disconnect(); + + /** Set the Wi-Fi network credentials + * + * @param ssid Name of the network to connect to. + * @param pass Security passphrase to connect to the network. + * @param security Type of encryption for connection. + * (defaults to NSAPI_SECURITY_NONE) + * @return 0 on success, negative error code on failure. + */ + nsapi_error_t set_credentials(const char *ssid, const char *pass, nsapi_security_t security = NSAPI_SECURITY_NONE); + + /** Sets the Wi-Fi network channel - NOT SUPPORTED + * + * This function is not supported and will return NSAPI_ERROR_UNSUPPORTED. + * + * @param channel Channel on which the connection is to be made (Default: 0). + * @return Not supported, returns NSAPI_ERROR_UNSUPPORTED. + */ + nsapi_error_t set_channel(uint8_t channel) + { + if (channel != 0) { + return NSAPI_ERROR_UNSUPPORTED; + } + return 0; + } + + /** Set blocking status of interface. + * Nonblocking mode is not supported. + * + * @param blocking True if connect is blocking + * @return 0 on success, negative error code on failure + */ + nsapi_error_t set_blocking(bool blocking) + { + if (blocking) { + _blocking = blocking; + return NSAPI_ERROR_OK; + } else { + return NSAPI_ERROR_UNSUPPORTED; + } + } + /** Gets the current radio signal strength for active connection + * + * @return Connection strength in dBm (negative value). + */ + int8_t get_rssi(); + + /** Scans for available networks - NOT SUPPORTED + * + * @return NSAPI_ERROR_UNSUPPORTED + */ + int scan(WiFiAccessPoint *res, unsigned count); + + /** This function is used to indicate if the device is connected to the network. + * + * @return SCL_SUCCESS if device is connected. + */ + int is_interface_connected(); + + /** Gets the BSSID (MAC address of device connected to). + * + * @param bssid Pointer to the BSSID value. + * @return SCL_SUCCESS if BSSID is obtained successfully. + * @return SCL_BADARG if input parameter is NULL. + * @return SCL_ERROR if unable to fetch BSSID. + */ + int get_bssid(uint8_t *bssid); + + /** This function is used to set up the Wi-Fi interface. + * This function should be used after the wifi_on. + * + * @return SCL_SUCCESS if the Wi-Fi interface is set up successfully. + */ + int wifi_set_up(void); + +private: + + char _ssid[MAX_SSID_LENGTH]; /**< The longest possible name (defined in 802.11) +1 for the \0 */ + char _pass[MAX_PASSWORD_LENGTH]; /**< The longest allowed passphrase + 1 */ + nsapi_security_t _security; /**< Security type */ + SCL_EMAC &_scl_emac; /**< SCL_EMAC object */ +}; +#endif /* ifndef SCL_STA_INTERFACE_H */ diff --git a/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/default_wifi_interface.cpp b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/default_wifi_interface.cpp new file mode 100644 index 00000000000..59cb5ef0ab0 --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/default_wifi_interface.cpp @@ -0,0 +1,35 @@ +/* + * Copyright 2018-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "SclSTAInterface.h" + +/** @file +* Provides function definition to override get_target_default_intance of WiFiInterface and NetworkInterface classes +*/ + +/** + * Returns the WiFiInterface Object + * This function can be called using WiFiInterface or NetworkInterface objects + * + * @return pointer to WiFiInterface object. + */ + +WiFiInterface *WiFiInterface::get_target_default_instance() +{ + static SclSTAInterface wifi; + return &wifi; +} diff --git a/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/scl_emac.cpp b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/scl_emac.cpp new file mode 100644 index 00000000000..d7a276858ef --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/scl_emac.cpp @@ -0,0 +1,203 @@ +/* + * Copyright 2018-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include + +#include "cmsis_os.h" +#include "scl_emac.h" +#include "lwip/etharp.h" +#include "lwip/ethip6.h" +#include "mbed_shared_queues.h" +#include "scl_buffer_api.h" +#include "cy_result.h" +#include "cy_pdl.h" +#include "scl_ipc.h" + +/** @file + * Provides EMAC interface functions to be used with the SCL_EMAC object + */ + +SCL_EMAC::SCL_EMAC(scl_interface_role_t role) + : interface_type(role) +{ +} + +SCL_EMAC::SCL_EMAC() + : interface_type(SCL_STA_ROLE) +{ +} + +SCL_EMAC &SCL_EMAC::get_instance() +{ + return get_instance(SCL_STA_ROLE); +} + +SCL_EMAC &SCL_EMAC::get_instance(scl_interface_role_t role) +{ + static SCL_EMAC emac_sta(SCL_STA_ROLE); + static SCL_EMAC emac_ap(SCL_AP_ROLE); + return role == SCL_AP_ROLE ? emac_ap : emac_sta; +} + +uint32_t SCL_EMAC::get_mtu_size() const +{ + return SCL_PAYLOAD_MTU; +} + +uint32_t SCL_EMAC::get_align_preference() const +{ + return 0; +} + +void SCL_EMAC::add_multicast_group(const uint8_t *addr) +{ + memcpy(multicast_addr.octet, addr, sizeof(multicast_addr.octet)); + scl_wifi_register_multicast_address(&multicast_addr); +} + +void SCL_EMAC::remove_multicast_group(const uint8_t *address) +{ + /* To Do */ +} +void SCL_EMAC::set_all_multicast(bool all) +{ + /* No-op at this stage */ +} + +void SCL_EMAC::power_down() +{ + /* No-op at this stage */ +} + +bool SCL_EMAC::power_up() +{ + if (!powered_up) { + if (scl_wifi_on() != true) { + SCL_LOG(("returning False in scl_wifi_on()\n")); + return false; + } + powered_up = true; + if (link_state && emac_link_state_cb) { + emac_link_state_cb(link_state); + } + } + return true; +} + +bool SCL_EMAC::get_hwaddr(uint8_t *addr) const +{ + scl_mac_t mac; + scl_result_t res = scl_wifi_get_mac_address(&mac); + if (res == SCL_SUCCESS) { + memcpy(addr, mac.octet, sizeof(mac.octet)); + return true; + } else { + SCL_LOG(("return False in SCL_EMAC::gethwaddr\n")); + return false; + } + +} + +void SCL_EMAC::set_hwaddr(const uint8_t *addr) +{ + /* No-op at this stage */ +} + +uint8_t SCL_EMAC::get_hwaddr_size() const +{ + scl_mac_t mac; + return sizeof(mac.octet); +} + +void SCL_EMAC::set_link_input_cb(emac_link_input_cb_t input_cb) +{ + emac_link_input_cb = input_cb; +} + +void SCL_EMAC::set_link_state_cb(emac_link_state_change_cb_t state_cb) +{ + emac_link_state_cb = state_cb; +} + +void SCL_EMAC::set_memory_manager(EMACMemoryManager &mem_mngr) +{ + memory_manager = &mem_mngr; +} + +bool SCL_EMAC::link_out(emac_mem_buf_t *buf) +{ + scl_result_t retval; + scl_tx_buf_t scl_tx_data; + scl_tx_data.size = memory_manager->get_total_len(buf); + scl_tx_data.buffer = buf; + if (buf == NULL) { + return false; + } + retval = scl_network_send_ethernet_data(scl_tx_data); + if (retval != SCL_SUCCESS) { + return false; + } + memory_manager->free(buf); + return true; +} + +void SCL_EMAC::get_ifname(char *name, uint8_t size) const +{ + if (name != NULL) { + memcpy(name, "scl", size); + } +} + +void SCL_EMAC::set_activity_cb(mbed::Callback cb) +{ + activity_cb = cb; +} + +extern "C" +{ + void scl_network_process_ethernet_data(scl_buffer_t buffer) + { + emac_mem_buf_t *mem_buf = NULL; + + SCL_EMAC &emac = SCL_EMAC::get_instance(SCL_STA_ROLE); + + if (!emac.powered_up && !emac.emac_link_input_cb) { + scl_buffer_release(buffer, SCL_NETWORK_RX); + return; + } + mem_buf = buffer; + if (emac.activity_cb) { + emac.activity_cb(false); + } + emac.emac_link_input_cb(mem_buf); + } + + void scl_emac_wifi_link_state_changed(bool state_up) + { + SCL_EMAC &emac = SCL_EMAC::get_instance(SCL_STA_ROLE); + + emac.link_state = state_up; + if (emac.emac_link_state_cb) { + emac.emac_link_state_cb(state_up); + } + } +} // extern "C" + + diff --git a/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/scl_emac.h b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/scl_emac.h new file mode 100644 index 00000000000..e6e3ecd8a97 --- /dev/null +++ b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_SCL/interface/scl_emac.h @@ -0,0 +1,189 @@ +/* + * Copyright 2018-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef SCL_EMAC_H_ +#define SCL_EMAC_H_ + +/** @file + * Provides EMAC interface functions to be used with the SCL_EMAC object + * + */ +#include "EMAC.h" +#include "EMACInterface.h" +#include "WiFiInterface.h" +#include "scl_common.h" +#include "rtos/Semaphore.h" +#include "rtos/Mutex.h" +#include "scl_wifi_api.h" +class SCL_EMAC : public EMAC { +public: + SCL_EMAC(); + SCL_EMAC(scl_interface_role_t itype); + + /** + * Get the EMAC instance + * + * @return Reference to SCL_EMAC object. + */ + static SCL_EMAC &get_instance(); + + /** + * Get the EMAC instance + * + * @param role Interface type. + * + * @return Reference to SCL_EMAC object. + */ + static SCL_EMAC &get_instance(scl_interface_role_t role); + + /** + * Returns the maximum transmission unit + * + * @return MTU in bytes. + */ + virtual uint32_t get_mtu_size() const; + + /** + * Gets the memory buffer alignment preference + * + * Gets the preferred memory buffer alignment of the EMAC device. IP stack may or may not + * align with the link out memory buffer chains using the alignment. + * + * @return Memory alignment requirement in bytes. + */ + virtual uint32_t get_align_preference() const; + + /** + * Returns the interface name + * + * @param name Pointer to the location where the name should be written. + * @param size Maximum number of characters to copy. + */ + virtual void get_ifname(char *name, uint8_t size) const; + + /** + * Returns the size of the underlying interface HW address size. + * + * @return HW address size in bytes. + */ + virtual uint8_t get_hwaddr_size() const; + + /** + * Returns the interface supplied HW address + * Copies the HW address to the provided memory + * @param addr HW address of the underlying interface. It must be of correct size. See @a get_hwaddr_size. + * @return True if HW address is available. + */ + virtual bool get_hwaddr(uint8_t *addr) const; + + /** + * Set HW address for the interface + * + * Provided address must be of correct size. See @a get_hwaddr_size. + * + * Called to set the MAC address to be used - if @a get_hwaddr is provided + * the stack would normally use that, but it could be overridden for test + * purposes. + * + * @param addr Address to be set + */ + virtual void set_hwaddr(const uint8_t *addr); + + /** + * Sends the packet over the link + * + * This cannot be called from an interrupt context. + * + * @param buf Packet to be sent. + * @return True if the packet was sent successfully. False otherwise. + */ + virtual bool link_out(emac_mem_buf_t *buf); + + /** + * Initializes the HW + * + * @return True on success. False in case of an error. + */ + virtual bool power_up(); + + /** + * De-initializes the HW + */ + virtual void power_down(); + + /** + * Sets a callback that is called for packets received for a given interface + * + * @param input_cb Function to be registered as a callback. + */ + virtual void set_link_input_cb(emac_link_input_cb_t input_cb); + + /** + * Sets a callback that is called on changes in the link status for a given interface + * + * @param state_cb Function to be registered as a callback. + */ + virtual void set_link_state_cb(emac_link_state_change_cb_t state_cb); + + /** Adds a device to a multicast group + * + * @param address A multicast group hardware address. + */ + virtual void add_multicast_group(const uint8_t *address); + + /** Removes a device from a multicast group + * + * @param address A multicast group hardware address. + */ + virtual void remove_multicast_group(const uint8_t *address); + + /** Requests reception of all multicast packets + * + * @param all True to receive all multicasts. + * False to receive only multicasts addressed to specified groups. + */ + virtual void set_all_multicast(bool all); + + /** Sets memory manager used to handle memory buffers + * + * @param mem_mngr Pointer to memory manager. + */ + virtual void set_memory_manager(EMACMemoryManager &mem_mngr); + + /** Sets callback to receive EMAC activity events + * + * @param activity_cb The callback for activity events. + */ + virtual void set_activity_cb(mbed::Callback activity_cb); + + emac_link_input_cb_t emac_link_input_cb = NULL; /**< Callback for incoming data */ + emac_link_state_change_cb_t emac_link_state_cb = NULL; /**< Callback for network connection status */ + EMACMemoryManager *memory_manager; /**< Pointer to hold memory manager object */ + bool powered_up = false; /**< Flag for Wi-Fi power on status */ + bool link_state = false; /**< Flag for network connection status */ + scl_interface_role_t interface_type; /**< Type of the interface */ + scl_mac_t multicast_addr; /**< Multicast address */ + mbed::Callback activity_cb; /**< Callback for activity on network */ + +}; +/** Sends the change in network connection state to network stack +* +* @param state_up Connection status. +*/ +extern "C" void scl_emac_wifi_link_state_changed(bool state_up); + +#endif /* SCL_EMAC_H_ */ diff --git a/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_WHD/interface/WhdSTAInterface.cpp b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_WHD/interface/WhdSTAInterface.cpp index de4ffdfbd69..0995b10145e 100644 --- a/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_WHD/interface/WhdSTAInterface.cpp +++ b/features/netsocket/emac-drivers/TARGET_Cypress/COMPONENT_WHD/interface/WhdSTAInterface.cpp @@ -250,7 +250,9 @@ nsapi_error_t WhdSTAInterface::connect() // initialize wiced, this is noop if already init if (!_whd_emac.powered_up) { - _whd_emac.power_up(); + if(!_whd_emac.power_up()) { + return NSAPI_ERROR_DEVICE_ERROR; + } } res = whd_management_set_event_handler(_whd_emac.ifp, sta_link_change_events, @@ -322,7 +324,9 @@ nsapi_error_t WhdSTAInterface::connect() void WhdSTAInterface::wifi_on() { if (!_whd_emac.powered_up) { - _whd_emac.power_up(); + if(!_whd_emac.power_up()) { + CY_ASSERT(false); + } } } @@ -375,11 +379,14 @@ int8_t WhdSTAInterface::get_rssi() // initialize wiced, this is noop if already init if (!_whd_emac.powered_up) { - _whd_emac.power_up(); + if(!_whd_emac.power_up()) { + CY_ASSERT(false); + } } res = (whd_result_t)whd_wifi_get_rssi(_whd_emac.ifp, &rssi); if (res != 0) { + CY_ASSERT(false); return 0; } @@ -454,7 +461,9 @@ int WhdSTAInterface::internal_scan(WiFiAccessPoint *aps, unsigned count, scan_re // initialize wiced, this is noop if already init if (!_whd_emac.powered_up) { - _whd_emac.power_up(); + if(!_whd_emac.power_up()) { + return NSAPI_ERROR_DEVICE_ERROR; + } } interal_scan_data.sema = new Semaphore(); @@ -467,7 +476,6 @@ int WhdSTAInterface::internal_scan(WiFiAccessPoint *aps, unsigned count, scan_re whd_result_t whd_res; int res; - whd_res = (whd_result_t)whd_wifi_scan(_whd_emac.ifp, WHD_SCAN_TYPE_ACTIVE, WHD_BSS_TYPE_ANY, NULL, NULL, NULL, NULL, whd_scan_handler, &internal_scan_result, &interal_scan_data); if (whd_res != WHD_SUCCESS) { diff --git a/features/netsocket/ppp/mbed_lib.json b/features/netsocket/ppp/mbed_lib.json index 33bdb3df99e..a95bfd25bb4 100644 --- a/features/netsocket/ppp/mbed_lib.json +++ b/features/netsocket/ppp/mbed_lib.json @@ -47,6 +47,9 @@ }, "CY8CKIT_062S2_43012": { "thread-stacksize": 896 + }, + "CYSBSYSKIT_01": { + "thread-stacksize": 896 } } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/generated_mac_address.txt b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/generated_mac_address.txt new file mode 100644 index 00000000000..cba1ab86257 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/generated_mac_address.txt @@ -0,0 +1,9 @@ +/* + * This file is used to set the MAC address in NVRAM. + * The MAC address of the Wi-Fi device may be configured in OTP and/or in NVRAM. + * If both OTP and NVRAM contains the MAC address then OTP programmed MAC address will be used. + * PSOC boards are usually programmed with OTP MAC address. + * MAC address is printed during SCL power up + */ + +#define NVRAM_GENERATED_MAC_ADDRESS "macaddr=00:A0:50:45:2e:c8" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_common.h b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_common.h new file mode 100644 index 00000000000..42e0b1c02d9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_common.h @@ -0,0 +1,211 @@ +/* + * Copyright 2018-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file scl_common.h + * Defines common data types used in SCL + */ + +#include +#include "cy_result.h" + +#ifndef INCLUDED_SCL_COMMON_H_ +#define INCLUDED_SCL_COMMON_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/****************************************************** +* Constants +******************************************************/ + +#define SCL_LOG_ENABLE false /**< Flag to enable SCL debug logs */ +#define SCL_LOG(x) if (SCL_LOG_ENABLE) \ + { printf x; } /**< SCL log interface */ +#define CHECK_BUFFER_NULL(buf) if (buf == NULL)\ + { SCL_LOG(("Buffer pointer is null\n")); \ + return SCL_BADARG; } /**< Helper macro to check if the input buffer pointer is null */ + +#define MODULE_BASE_CODE (0x0080U) /**< Base code for the SCL error status */ +#define SCL_RESULT_TYPE (0) /**< SCL Result type */ + +/* + * scl_result_t Error code format + * |31-18 (14 bit) for module id|17-16 (2 bit) for result type|15-0 for SCL Error code| + * for example, for Error code 1026, the result of SCL_RESULT_CREATE is 33555458. + */ +#define SCL_RESULT_CREATE(x) CY_RSLT_CREATE(SCL_RESULT_TYPE, MODULE_BASE_CODE, (x) ) /**< Create a result value from the specified type, module, and result code */ + +#define SCL_SUCCESS (0) /**< IPC success */ +#define SCL_ERROR (100) /**< IPC error */ +#define SCL_PENDING SCL_RESULT_CREATE(1) /**< IPC Pending */ +#define SCL_TIMEOUT SCL_RESULT_CREATE(2) /**< Timeout */ +#define SCL_BADARG SCL_RESULT_CREATE(5) /**< Bad Arguments */ +#define SCL_UNFINISHED SCL_RESULT_CREATE(10) /**< Operation not finished yet (maybe aborted) */ +#define SCL_PARTIAL_RESULTS SCL_RESULT_CREATE(1003) /**< Partial results */ +#define SCL_INVALID_KEY SCL_RESULT_CREATE(1004) /**< Invalid key */ +#define SCL_DOES_NOT_EXIST SCL_RESULT_CREATE(1005) /**< Does not exist */ +#define SCL_NOT_AUTHENTICATED SCL_RESULT_CREATE(1006) /**< Not authenticated */ +#define SCL_NOT_KEYED SCL_RESULT_CREATE(1007) /**< Not keyed */ +#define SCL_IOCTL_FAIL SCL_RESULT_CREATE(1008) /**< IOCTL fail */ +#define SCL_BUFFER_UNAVAILABLE_TEMPORARY SCL_RESULT_CREATE(1009) /**< Buffer unavailable temporarily */ +#define SCL_BUFFER_UNAVAILABLE_PERMANENT SCL_RESULT_CREATE(1010) /**< Buffer unavailable permanently */ +#define SCL_CONNECTION_LOST SCL_RESULT_CREATE(1012) /**< Connection lost */ +#define SCL_OUT_OF_EVENT_HANDLER_SPACE SCL_RESULT_CREATE(1013) /**< Cannot add extra event handler */ +#define SCL_SEMAPHORE_ERROR SCL_RESULT_CREATE(1014) /**< Error manipulating a semaphore */ +#define SCL_FLOW_CONTROLLED SCL_RESULT_CREATE(1015) /**< Packet retrieval cancelled due to flow control */ +#define SCL_NO_CREDITS SCL_RESULT_CREATE(1016) /**< Packet retrieval cancelled due to lack of bus credits */ +#define SCL_NO_PACKET_TO_SEND SCL_RESULT_CREATE(1017) /**< Packet retrieval cancelled due to no pending packets */ +#define SCL_CORE_CLOCK_NOT_ENABLED SCL_RESULT_CREATE(1018) /**< Core disabled due to no clock */ +#define SCL_CORE_IN_RESET SCL_RESULT_CREATE(1019) /**< Core disabled - in reset */ +#define SCL_UNSUPPORTED SCL_RESULT_CREATE(1020) /**< Unsupported function */ +#define SCL_BUS_WRITE_REGISTER_ERROR SCL_RESULT_CREATE(1021) /**< Error writing to WLAN register */ +#define SCL_SDIO_BUS_UP_FAIL SCL_RESULT_CREATE(1022) /**< SDIO bus failed to come up */ +#define SCL_JOIN_IN_PROGRESS SCL_RESULT_CREATE(1023) /**< Join not finished yet */ +#define SCL_NETWORK_NOT_FOUND SCL_RESULT_CREATE(1024) /**< Specified network was not found */ +#define SCL_INVALID_JOIN_STATUS SCL_RESULT_CREATE(1025) /**< Join status error */ +#define SCL_UNKNOWN_INTERFACE SCL_RESULT_CREATE(1026) /**< Unknown interface specified */ +#define SCL_SDIO_RX_FAIL SCL_RESULT_CREATE(1027) /**< Error during SDIO receive */ +#define SCL_HWTAG_MISMATCH SCL_RESULT_CREATE(1028) /**< Hardware tag header corrupt */ +#define SCL_RX_BUFFER_ALLOC_FAIL SCL_RESULT_CREATE(1029) /**< Failed to allocate a buffer to receive into */ +#define SCL_BUS_READ_REGISTER_ERROR SCL_RESULT_CREATE(1030) /**< Error reading a bus hardware register */ +#define SCL_THREAD_CREATE_FAILED SCL_RESULT_CREATE(1031) /**< Failed to create a new thread */ +#define SCL_QUEUE_ERROR SCL_RESULT_CREATE(1032) /**< Error manipulating a queue */ +#define SCL_BUFFER_POINTER_MOVE_ERROR SCL_RESULT_CREATE(1033) /**< Error moving the current pointer of a packet buffer */ +#define SCL_BUFFER_SIZE_SET_ERROR SCL_RESULT_CREATE(1034) /**< Error setting size of packet buffer */ +#define SCL_THREAD_STACK_NULL SCL_RESULT_CREATE(1035) /**< Null stack pointer passed when non null was required */ +#define SCL_THREAD_DELETE_FAIL SCL_RESULT_CREATE(1036) /**< Error deleting a thread */ +#define SCL_SLEEP_ERROR SCL_RESULT_CREATE(1037) /**< Error sleeping a thread */ +#define SCL_BUFFER_ALLOC_FAIL SCL_RESULT_CREATE(1038) /**< Failed to allocate a packet buffer */ +#define SCL_NO_PACKET_TO_RECEIVE SCL_RESULT_CREATE(1039) /**< No Packets waiting to be received */ +#define SCL_INTERFACE_NOT_UP SCL_RESULT_CREATE(1040) /**< Requested interface is not active */ +#define SCL_DELAY_TOO_LONG SCL_RESULT_CREATE(1041) /**< Requested delay is too long */ +#define SCL_INVALID_DUTY_CYCLE SCL_RESULT_CREATE(1042) /**< Duty cycle is outside limit 0 to 100 */ +#define SCL_PMK_WRONG_LENGTH SCL_RESULT_CREATE(1043) /**< Returned pmk was the wrong length */ +#define SCL_UNKNOWN_SECURITY_TYPE SCL_RESULT_CREATE(1044) /**< AP security type was unknown */ +#define SCL_WEP_NOT_ALLOWED SCL_RESULT_CREATE(1045) /**< AP not allowed to use WEP - it is not secure - use Open instead */ +#define SCL_WPA_KEYLEN_BAD SCL_RESULT_CREATE(1046) /**< WPA / WPA2 key length must be between 8 & 64 bytes */ +#define SCL_FILTER_NOT_FOUND SCL_RESULT_CREATE(1047) /**< Specified filter id not found */ +#define SCL_SPI_ID_READ_FAIL SCL_RESULT_CREATE(1048) /**< Failed to read 0xfeedbead SPI id from chip */ +#define SCL_SPI_SIZE_MISMATCH SCL_RESULT_CREATE(1049) /**< Mismatch in sizes between SPI header and SDPCM header */ +#define SCL_ADDRESS_ALREADY_REGISTERED SCL_RESULT_CREATE(1050) /**< Attempt to register a multicast address twice */ +#define SCL_SDIO_RETRIES_EXCEEDED SCL_RESULT_CREATE(1051) /**< SDIO transfer failed too many times. */ +#define SCL_NULL_PTR_ARG SCL_RESULT_CREATE(1052) /**< Null Pointer argument passed to function. */ +#define SCL_THREAD_FINISH_FAIL SCL_RESULT_CREATE(1053) /**< Error deleting a thread */ +#define SCL_WAIT_ABORTED SCL_RESULT_CREATE(1054) /**< Semaphore/mutex wait has been aborted */ +#define SCL_SET_BLOCK_ACK_WINDOW_FAIL SCL_RESULT_CREATE(1055) /**< Failed to set block ack window */ +#define SCL_DELAY_TOO_SHORT SCL_RESULT_CREATE(1056) /**< Requested delay is too short */ +#define SCL_INVALID_INTERFACE SCL_RESULT_CREATE(1057) /**< Invalid interface provided */ +#define SCL_WEP_KEYLEN_BAD SCL_RESULT_CREATE(1058) /**< WEP / WEP_SHARED key length must be 5 or 13 bytes */ +#define SCL_HANDLER_ALREADY_REGISTERED SCL_RESULT_CREATE(1059) /**< EAPOL handler already registered */ +#define SCL_AP_ALREADY_UP SCL_RESULT_CREATE(1060) /**< Soft AP or P2P group owner already up */ +#define SCL_EAPOL_KEY_PACKET_M1_TIMEOUT SCL_RESULT_CREATE(1061) /**< Timeout occurred while waiting for EAPOL packet M1 from AP */ +#define SCL_EAPOL_KEY_PACKET_M3_TIMEOUT SCL_RESULT_CREATE(1062) /**< Timeout occurred while waiting for EAPOL packet M3 from AP which may indicate incorrect WPA2/WPA passphrase */ +#define SCL_EAPOL_KEY_PACKET_G1_TIMEOUT SCL_RESULT_CREATE(1063) /**< Timeout occurred while waiting for EAPOL packet G1 from AP */ +#define SCL_EAPOL_KEY_FAILURE SCL_RESULT_CREATE(1064) /**< Unknown failure occurred during the EAPOL key handshake */ +#define SCL_MALLOC_FAILURE SCL_RESULT_CREATE(1065) /**< Memory allocation failure */ +#define SCL_ACCESS_POINT_NOT_FOUND SCL_RESULT_CREATE(1066) /**< Access point not found */ +#define SCL_RTOS_ERROR SCL_RESULT_CREATE(1067) /**< RTOS operation failed */ +#define SCL_CLM_BLOB_DLOAD_ERROR SCL_RESULT_CREATE(1068) /**< CLM blob download failed */ +#define SCL_HAL_ERROR SCL_RESULT_CREATE(1069) /**< SCL HAL Error */ +#define SCL_RTOS_STATIC_MEM_LIMIT SCL_RESULT_CREATE(1070) /**< Exceeding the RTOS static objects memory */ + +/* Application uses the following constants to allocate the buffer pool: */ + +#define BDC_HEADER_WITH_PAD 6 /**< BDC Header with padding 4 + 2 */ + +#define SCL_PAYLOAD_MTU (1500) /**< The maximum size, in bytes, of the data part of an Ethernet frame */ + +/****************************************************** +* Type Definitions +******************************************************/ +/** + * Typedef for SCL buffer pointer + */ +typedef void *scl_buffer_t; + +/** + * Typedef for SCL result + */ +typedef uint32_t scl_result_t; + +/****************************************************** +* Structures and Enumerations +******************************************************/ + +/** + * Typedef for SCL boolean flags + */ +typedef enum { + SCL_FALSE = 0, /**< Boolean False */ + SCL_TRUE = 1 /**< Boolean True */ +} scl_bool_t; + +/** + * Typedef for SCL interface roles + */ +typedef enum { + SCL_INVALID_ROLE = 0, /**< Invalid role */ + SCL_STA_ROLE = 1, /**< STA or Client Interface */ + SCL_AP_ROLE = 2, /**< softAP Interface */ + SCL_P2P_ROLE = 3 /**< P2P Interface */ +} scl_interface_role_t; + +/** + * Typedef for SCL IPC receive index + */ +typedef enum { + SCL_RX_DATA = 0, /**< Received buffer */ + SCL_RX_TEST_MSG = 1, /**< Test message */ + SCL_RX_GET_BUFFER = 2, /**< Get the buffer */ + SCL_RX_GET_CONNECTION_STATUS = 3 /**< Get the connection status */ +} scl_ipc_rx_t; + +/** + * Typedef for SCL IPC transmit index + */ +typedef enum { + SCL_TX_TEST_MSG = 1, /**< Test Message */ + SCL_TX_WIFI_INIT = 2, /**< Initialize Wi-Fi */ + SCL_TX_CONFIG_PARAMETERS = 3, /**< Configuration parameters */ + SCL_TX_GET_MAC = 4, /**< Get MAC address */ + SCL_TX_REGISTER_MULTICAST_ADDRESS = 5, /**< Register multicast address */ + SCL_TX_SEND_OUT = 6, /**< Transmit buffer */ + SCL_TX_TRANSCEIVE_READY = 7, /**< Wi-Fi transmit/receive ready */ + SCL_TX_WIFI_ON = 8, /**< Wi-Fi on */ + SCL_TX_WIFI_SET_UP = 9, /**< Wi-Fi setup */ + SCL_TX_WIFI_NW_PARAM = 10, /**< Get network parameters */ + SCL_TX_WIFI_GET_RSSI = 11, /**< Get RSSI */ + SCL_TX_WIFI_GET_BSSID = 12, /**< Get BSSID */ + SCL_TX_CONNECT = 13, /**< Wi-Fi connect */ + SCL_TX_DISCONNECT = 14, /**< Wi-Fi disconnect */ + SCL_TX_CONNECTION_STATUS = 15 /**< Transmit connection status */ +} scl_ipc_tx_t; + + +/** + * Structure for storing a MAC address (Wi-Fi Media Access Control address). + */ +typedef struct { + uint8_t octet[6]; /**< Unique 6-byte MAC address */ +} scl_mac_t; + +#ifdef __cplusplus +} /* extern "C" */ +#endif +#endif /* ifndef INCLUDED_SCL_COMMON_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_ipc.h b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_ipc.h new file mode 100644 index 00000000000..a9d3e237000 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_ipc.h @@ -0,0 +1,120 @@ +/* + * Copyright 2018-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides SCL functionality to communicate with Network Processor + */ + +#include "scl_common.h" +#include "cy_device.h" +#include "cy_sysint.h" +#include "cy_ipc_drv.h" +#include "scl_wifi_api.h" +#include "ip4_addr.h" + +#ifndef INCLUDED_SCL_IPC_H +#define INCLUDED_SCL_IPC_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/****************************************************** + * Macros + ******************************************************/ +/** + * Hardware address of IPC_DATA0 register + */ +#define REG_IPC_STRUCT_DATA0(base) (((IPC_STRUCT_V2_Type*)(base))->DATA0) +/** + * Default timeout value (in ms) for SCL operations + */ +#define TIMER_DEFAULT_VALUE (100) +/** + * Default timeout value (in ms) for Wi-Fi on + */ +#define WIFI_ON_TIMEOUT (5000) +/** + * Default timeout value (in seconds) for Wi-Fi connection + */ +#define NW_CONNECT_TIMEOUT (30) +/** + * Default interval (in micro seconds) for polling the Network Processor + */ +#define NW_DELAY_TIME_US (3000000) +/** + * Default parameter length + */ +#define PARAM_LEN (20) + +/****************************************************** +* Variables +******************************************************/ +/** + * Network parameters structure. + */ +typedef struct network_params { + char ip_address[PARAM_LEN]; /**< IP address */ + char netmask[PARAM_LEN]; /**< Netmask */ + char gateway[PARAM_LEN]; /**< Gateway */ + int connection_status; /**< Connection status */ +} network_params_t; + +/****************************************************** +* Function Declarations +******************************************************/ + +/** @addtogroup communication SCL communication API + * APIs for communicating with Network Processor + * @{ + */ + +/** Initializes the SCL thread and necessary artifacts + * + * @return SCL_SUCCESS on successful initialization or SCL_ERROR otherwise + */ +extern scl_result_t scl_init(void); + +/** Sends the SCL data and respective command to Network Processor + * + * @param index Index of the command. + * @param buffer Data to be sent. + * @param timeout The maximum time (in ms) to wait for the Network Processor to release IPC channel. + * + * @return SCL_SUCCESS on successful communication within SCL timeout duration or SCL_ERROR + */ +extern scl_result_t scl_send_data(int index, char *buffer, uint32_t timeout); + +/** Terminates the SCL thread and disables the interrupts + * + * @return SCL_SUCCESS on successful termination of SCL thread and disabling of interrupts or SCL_ERROR on timeout + */ +extern scl_result_t scl_end(void); + +/** Gets the network parameters like IP Address, Netmask, and Gateway from Network Processor + * + * @param nw_param structure pointer of type @a network_params_t + * + * @return SCL_SUCCESS on successful communication or SCL_ERROR + */ +extern scl_result_t scl_get_nw_parameters(network_params_t *nw_param); + +#ifdef __cplusplus +} /* extern "C" */ +#endif +#endif /* ifndef INCLUDED_SCL_IPC_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_types.h new file mode 100644 index 00000000000..bda316cb796 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_types.h @@ -0,0 +1,115 @@ +/* + * Copyright 2018-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file scl_types.h + * Defines common data types used in SCL + * + */ + +#include +#include "cy_result.h" + +#ifndef INCLUDED_SCL_TYPES_H_ +#define INCLUDED_SCL_TYPES_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif +/****************************************************** +* Macros +******************************************************/ +#define SSID_NAME_SIZE (32) /**< SSID Length */ + +#define WEP_ENABLED 0x0001 /**< Flag to enable WEP Security */ +#define TKIP_ENABLED 0x0002 /**< Flag to enable TKIP Encryption */ +#define AES_ENABLED 0x0004 /**< Flag to enable AES Encryption */ +#define SHARED_ENABLED 0x00008000 /**< Flag to enable Shared key Security */ +#define WPA_SECURITY 0x00200000 /**< Flag to enable WPA Security */ +#define WPA2_SECURITY 0x00400000 /**< Flag to enable WPA2 Security */ +#define WPA3_SECURITY 0x01000000 /**< Flag to enable WPA3 PSK Security */ + +#define ENTERPRISE_ENABLED 0x02000000 /**< Flag to enable Enterprise Security */ +#define WPS_ENABLED 0x10000000 /**< Flag to enable WPS Security */ +#define IBSS_ENABLED 0x20000000 /**< Flag to enable IBSS mode */ +#define FBT_ENABLED 0x40000000 /**< Flag to enable FBT */ + +#define NO_POWERSAVE_MODE (0) /**< No Power save mode */ +#define PM1_POWERSAVE_MODE (1) /**< Power save mode on specified interface without regard for throughput reduction */ +#define PM2_POWERSAVE_MODE (2) /**< Power save mode on specified interface with High throughput */ + +/** + * Suppresses unused parameter warning + */ +#define UNUSED_PARAMETER(x) ( (void)(x) ) + +/** + * Suppresses unused variable warning + */ +#define UNUSED_VARIABLE(x) ( (void)(x) ) + +/** + * Suppresses unused variable warning that occurs due to an assert being disabled in release mode + */ +#define REFERENCE_DEBUG_ONLY_VARIABLE(x) ( (void)(x) ) + +/****************************************************** +* Constants +******************************************************/ + +/****************************************************** +* Structures and Enumerations +******************************************************/ + +/** + * Enumeration of Wi-Fi security modes + */ +typedef enum { + SCL_SECURITY_OPEN = 0, /**< Open security */ + SCL_SECURITY_WEP_PSK = WEP_ENABLED, /**< WEP PSK Security with open authentication */ + SCL_SECURITY_WEP_SHARED = (WEP_ENABLED | SHARED_ENABLED), /**< WEP PSK Security with shared authentication */ + SCL_SECURITY_WPA_TKIP_PSK = (WPA_SECURITY | TKIP_ENABLED), /**< WPA PSK Security with TKIP */ + SCL_SECURITY_WPA_AES_PSK = (WPA_SECURITY | AES_ENABLED), /**< WPA PSK Security with AES */ + SCL_SECURITY_WPA_MIXED_PSK = (WPA_SECURITY | AES_ENABLED | TKIP_ENABLED), /**< WPA PSK Security with AES & TKIP */ + SCL_SECURITY_WPA2_AES_PSK = (WPA2_SECURITY | AES_ENABLED), /**< WPA2 PSK Security with AES */ + SCL_SECURITY_WPA2_TKIP_PSK = (WPA2_SECURITY | TKIP_ENABLED), /**< WPA2 PSK Security with TKIP */ + SCL_SECURITY_WPA2_MIXED_PSK = (WPA2_SECURITY | AES_ENABLED | TKIP_ENABLED), /**< WPA2 PSK Security with AES & TKIP */ + SCL_SECURITY_WPA2_FBT_PSK = (WPA2_SECURITY | AES_ENABLED | FBT_ENABLED), /**< WPA2 FBT PSK Security with AES & TKIP */ + SCL_SECURITY_WPA3_SAE = (WPA3_SECURITY | AES_ENABLED), /**< WPA3 Security with AES */ + SCL_SECURITY_WPA3_WPA2_PSK = (WPA3_SECURITY | WPA2_SECURITY | AES_ENABLED), /**< WPA3 WPA2 PSK Security with AES */ + + SCL_SECURITY_WPA_TKIP_ENT = (ENTERPRISE_ENABLED | WPA_SECURITY | TKIP_ENABLED), /**< WPA Enterprise Security with TKIP */ + SCL_SECURITY_WPA_AES_ENT = (ENTERPRISE_ENABLED | WPA_SECURITY | AES_ENABLED), /**< WPA Enterprise Security with AES */ + SCL_SECURITY_WPA_MIXED_ENT = (ENTERPRISE_ENABLED | WPA_SECURITY | AES_ENABLED | TKIP_ENABLED), /**< WPA Enterprise Security with AES & TKIP */ + SCL_SECURITY_WPA2_TKIP_ENT = (ENTERPRISE_ENABLED | WPA2_SECURITY | TKIP_ENABLED), /**< WPA2 Enterprise Security with TKIP */ + SCL_SECURITY_WPA2_AES_ENT = (ENTERPRISE_ENABLED | WPA2_SECURITY | AES_ENABLED), /**< WPA2 Enterprise Security with AES */ + SCL_SECURITY_WPA2_MIXED_ENT = (ENTERPRISE_ENABLED | WPA2_SECURITY | AES_ENABLED | TKIP_ENABLED), /**< WPA2 Enterprise Security with AES & TKIP */ + SCL_SECURITY_WPA2_FBT_ENT = (ENTERPRISE_ENABLED | WPA2_SECURITY | AES_ENABLED | FBT_ENABLED), /**< WPA2 Enterprise Security with AES & FBT */ + + SCL_SECURITY_IBSS_OPEN = (IBSS_ENABLED), /**< Open security on IBSS ad-hoc network */ + SCL_SECURITY_WPS_OPEN = (WPS_ENABLED), /**< WPS with open security */ + SCL_SECURITY_WPS_SECURE = (WPS_ENABLED | AES_ENABLED), /**< WPS with AES security */ + + SCL_SECURITY_UNKNOWN = -1, /**< Returned by scan function if security is unknown. Do not pass this to the join function! */ + + SCL_SECURITY_FORCE_32_BIT = 0x7fffffff /**< Exists only to force scl_security_t type to 32 bits */ +} scl_security_t; + +#ifdef __cplusplus +} /* extern "C" */ +#endif +#endif /* ifndef INCLUDED_SCL_TYPES_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_wifi_api.h b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_wifi_api.h new file mode 100644 index 00000000000..f880559a52b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/inc/scl_wifi_api.h @@ -0,0 +1,151 @@ +/* + * Copyright 2018-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Prototypes of functions for controlling the Wi-Fi system + * + * This file provides prototypes for end-user functions, which allow + * actions such as scanning for Wi-Fi networks, joining Wi-Fi + * networks, getting the MAC address, and so on. + * + */ + +#include +#include "scl_common.h" +#ifndef INCLUDED_SCL_WIFI_API_H +#define INCLUDED_SCL_WIFI_API_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * SCL transmit buffer structure + */ +typedef struct scl_tx_buf { + scl_buffer_t buffer; /**< pointer to the buffer */ + uint32_t size; /**< size of the buffer */ +} scl_tx_buf_t; + +/****************************************************** +* Function Declarations +******************************************************/ + +/** @addtogroup wifi SCL Wi-Fi API + * APIs for controlling the Wi-Fi system + * @{ + */ + +/** Turn on the Wi-Fi device + * + * @note This API should be called before using any SCL Wi-Fi API. + * + * @return True if initialization is successful, False otherwise. + */ +extern bool scl_wifi_on(void); + +/** Brings up the Wi-Fi core + * + * @return SCL_SUCCESS or Error code. + */ +extern scl_result_t scl_wifi_set_up(void); + +/** Retrieves the current Media Access Control (MAC) address + * (or Ethernet hardware address) of the 802.11 device + * + * @param mac Pointer to a variable to which the current MAC address will be written. + * + * @return SCL_SUCCESS or Error code. + */ +extern scl_result_t scl_wifi_get_mac_address(scl_mac_t *mac); + +/** Gets the BSSID of the interface + * + * @note This API should be used after the device is connected to a network. + * + * @param bssid Returns the BSSID address (mac address), if associated. + * + * @return SCL_SUCCESS or Error code. + */ +extern scl_result_t scl_wifi_get_bssid(scl_mac_t *bssid); + +/** Registers interest in a multicast address + * + * Once a multicast address has been registered, all packets detected on the + * medium destined for that address are forwarded to the host. + * Otherwise, the packets are ignored. + * + * @param mac Ethernet MAC address. + * + * @return SCL_SUCCESS If the address was registered successfully or Error code. + */ +extern scl_result_t scl_wifi_register_multicast_address(scl_mac_t *mac); + +/** Determines if an interface is ready to transmit/receive ethernet packets. + * + * @note This function must be called after the connection is established; otherwise, it returns Error code. + * + * @return SCL_SUCCESS If the interface is ready to transmit/receive ethernet packets. + * SCL_NOTFOUND If no AP with a matching SSID was found. + * SCL_NOT_AUTHENTICATED If matching AP was found, but it does not let you authenticate. + * @note This can occur if the device is in the blocklist of the AP. + * SCL_NOT_KEYED If the device has authenticated and associated but has not completed the key exchange. + * @note This can occur if the passphrase is incorrect. + * Error code If the interface is not ready to transmit/receive ethernet packets. + */ +extern scl_result_t scl_wifi_is_ready_to_transceive(void); + +/** Sends an ethernet frame to SCL (called by the Network Stack) + * + * This function takes ethernet data from the network stack and transmits over the wireless network. + * This function returns immediately after the packet has been queued for transmission, + * NOT after it has been transmitted. Packet buffers passed to the SCL + * are released inside the SCL once they have been transmitted. + * + * @param buffer Handle of the packet buffer to be sent. + * + * @return SCL_SUCCESS or Error code. + */ +extern scl_result_t scl_network_send_ethernet_data(scl_tx_buf_t buffer); + +/** Retrieves the latest RSSI value + * + * @note This API must be called after the device is connected to a network. + * + * @param rssi Location where the RSSI value will be stored. + * + * @return SCL_SUCCESS If the RSSI was successfully retrieved or Error code. + */ +extern scl_result_t scl_wifi_get_rssi(int32_t *rssi); + +/** Retrieves the RX data packet + * + * @param buffer Pointer to RX buffer. + */ +extern void scl_network_process_ethernet_data(scl_buffer_t buffer); + +/** Notifies network stack about the change in network connection state + * + * @param state_up Connection state. + */ +extern void scl_emac_wifi_link_state_changed(bool state_up); + +#ifdef __cplusplus +} /* extern "C" */ +#endif +#endif /* ifndef INCLUDED_SCL_WIFI_API_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/IPC/scl_ipc.c b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/IPC/scl_ipc.c new file mode 100644 index 00000000000..f3d462f5583 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/IPC/scl_ipc.c @@ -0,0 +1,293 @@ +/* + * Copyright 2018-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides SCL functionality to communicate with Network Processor + */ +#include "scl_ipc.h" +#include "scl_buffer_api.h" +#include "cyabs_rtos.h" +#include "mbed_wait_api.h" +#include "string.h" +#include "nsapi_types.h" +/****************************************************** + ** Macros + *******************************************************/ +#define SCL_THREAD_STACK_SIZE (1000) +#define SCL_THREAD_PRIORITY (CY_RTOS_PRIORITY_HIGH) +#define SCL_INTR_SRC (cpuss_interrupts_ipc_4_IRQn) +#define SCL_INTR_PRI (1) +#define SCL_RX_CHANNEL (4) +#define SCL_CHANNEL_NOTIFY_INTR ((1 << SCL_RX_CHANNEL) << 16) +#define SCL_NOTIFY (1 << SCL_TX_CHANNEL) +#define SCL_LOCK_ACQUIRE_STATUS (0x80000000) +#define SCL_TX_CHANNEL (3) +#define SCL_RELEASE (0) +#define DELAY_TIME (1000) +#define SEMAPHORE_MAXCOUNT (1) +#define SEMAPHORE_INITCOUNT (0) +/****************************************************** + ** Function Declarations + *******************************************************/ +static void scl_isr(void); +static void scl_config(void); +static void scl_rx_handler(void); +static scl_result_t scl_thread_init(void); +scl_result_t scl_get_nw_parameters(network_params_t *nw_param); +scl_result_t scl_send_data(int index, char *buffer, uint32_t timeout); +scl_result_t scl_end(void); +scl_result_t scl_init(void); +/****************************************************** + * Variables Definitions + *****************************************************/ +/* Structure of SCL thread info + * scl_thread_quit_flag: flag used to determine if thread is to be quit + * scl_inited: flag used to determine if thread is started + * scl_thread: variable for thread handle + * scl_thread_stack_start: pointer to start of thread stack + * scl_thread_stack_size: size of thread stack + * scl_thread_priority: priority of thread + * scl_rx_ready: semaphore for blocking the thread + */ +struct scl_thread_info_t { + volatile scl_bool_t scl_inited; + volatile scl_bool_t scl_thread_quit_flag; + void *scl_thread_stack_start; + cy_thread_t scl_thread; + cy_semaphore_t scl_rx_ready; + uint32_t scl_thread_stack_size; + cy_thread_priority_t scl_thread_priority; +}; +struct scl_thread_info_t g_scl_thread_info; + +/****************************************************** + * Function Definitions + ******************************************************/ + +/** ISR for the IPC receiver channel interrupt + */ +static void scl_isr(void) +{ + IPC_INTR_STRUCT_Type *scl_rx_intr = NULL; + scl_rx_intr = Cy_IPC_Drv_GetIntrBaseAddr(SCL_RX_CHANNEL); + + if (REG_IPC_INTR_STRUCT_INTR_MASKED(scl_rx_intr) & SCL_CHANNEL_NOTIFY_INTR) { + REG_IPC_INTR_STRUCT_INTR(scl_rx_intr) |= SCL_CHANNEL_NOTIFY_INTR; + if (g_scl_thread_info.scl_inited == SCL_TRUE) { + cy_rtos_set_semaphore(&g_scl_thread_info.scl_rx_ready, true); + } + } +} +/** Configures the IPC interrupt channel + */ +static void scl_config(void) +{ + IPC_INTR_STRUCT_Type *scl_rx_intr = NULL; + cy_stc_sysint_t intrCfg = { + .intrSrc = SCL_INTR_SRC, + .intrPriority = SCL_INTR_PRI + }; + + scl_rx_intr = Cy_IPC_Drv_GetIntrBaseAddr(SCL_RX_CHANNEL); + REG_IPC_INTR_STRUCT_INTR_MASK(scl_rx_intr) |= SCL_CHANNEL_NOTIFY_INTR; + Cy_SysInt_Init(&intrCfg, &scl_isr); + NVIC_EnableIRQ(intrCfg.intrSrc); +} +/** Create the SCL thread and initialize the semaphore for handling the events from Network Processor + * + * @return SCL_SUCCESS on successful initialization of thread or SCL_ERROR on failure + */ +static scl_result_t scl_thread_init(void) +{ + cy_rslt_t retval, tmp = 0; + memset(&g_scl_thread_info, 0, sizeof(g_scl_thread_info)); + g_scl_thread_info.scl_thread_stack_start = (uint8_t *) malloc(SCL_THREAD_STACK_SIZE);; + g_scl_thread_info.scl_thread_stack_size = (uint32_t) SCL_THREAD_STACK_SIZE; + g_scl_thread_info.scl_thread_priority = (cy_thread_priority_t) SCL_THREAD_PRIORITY; + + if (g_scl_thread_info.scl_inited != SCL_TRUE) { + retval = cy_rtos_init_semaphore(&g_scl_thread_info.scl_rx_ready, SEMAPHORE_MAXCOUNT, SEMAPHORE_INITCOUNT); + if (retval != SCL_SUCCESS) { + return SCL_ERROR; + } + retval = cy_rtos_create_thread(&g_scl_thread_info.scl_thread, (cy_thread_entry_fn_t) scl_rx_handler, + "SCL_thread", g_scl_thread_info.scl_thread_stack_start, + g_scl_thread_info.scl_thread_stack_size, + g_scl_thread_info.scl_thread_priority, (uint32_t) tmp); + if (retval != SCL_SUCCESS) { + return SCL_ERROR; + } + g_scl_thread_info.scl_inited = SCL_TRUE; + } else { + return SCL_ERROR; + } + return SCL_SUCCESS; +} + +scl_result_t scl_init(void) +{ + scl_result_t retval = SCL_SUCCESS; + uint32_t configuration_parameters = 0; +#ifdef MBED_CONF_TARGET_NP_CLOUD_DISABLE + configuration_parameters = (MBED_CONF_TARGET_NP_CLOUD_DISABLE << 1); +#else + configuration_parameters = (false << 1); +#endif +#ifdef MBED_CONF_TARGET_NP_WIFI_ENABLE + configuration_parameters |= MBED_CONF_TARGET_NP_WIFI_ENABLE; +#else + configuration_parameters |= false; +#endif + //SCL_LOG("configuration_parameters = %lu\n", configuration_parameters); + scl_config(); + if (g_scl_thread_info.scl_inited != SCL_TRUE) { + retval = scl_thread_init(); + if (retval != SCL_SUCCESS) { + SCL_LOG(("Thread init failed\n")); + return SCL_ERROR; + } else { + retval = scl_send_data(SCL_TX_CONFIG_PARAMETERS, (char *) &configuration_parameters, TIMER_DEFAULT_VALUE); + return retval; + } + } + return SCL_SUCCESS; +} + +scl_result_t scl_send_data(int index, char *buffer, uint32_t timeout) +{ + uint32_t acquire_state; + IPC_STRUCT_Type *scl_send = NULL; + uint32_t delay_timeout; + + SCL_LOG(("scl_send_data index = %d\n", index)); + scl_send = Cy_IPC_Drv_GetIpcBaseAddress(SCL_TX_CHANNEL); + CHECK_BUFFER_NULL(buffer); + if (!(REG_IPC_STRUCT_LOCK_STATUS(scl_send) & SCL_LOCK_ACQUIRE_STATUS)) { + acquire_state = REG_IPC_STRUCT_ACQUIRE(scl_send); + if (!(acquire_state & SCL_LOCK_ACQUIRE_STATUS)) { + SCL_LOG(("IPC Channel 3 Acquired Failed\r\n")); + return SCL_ERROR; + } + REG_IPC_STRUCT_DATA0(scl_send) = index; + REG_IPC_STRUCT_DATA1(scl_send) = (uint32_t) buffer; + REG_IPC_STRUCT_NOTIFY(scl_send) = SCL_NOTIFY; + delay_timeout = 0; + while ((REG_IPC_STRUCT_LOCK_STATUS(scl_send) & SCL_LOCK_ACQUIRE_STATUS) && delay_timeout <= timeout) { + wait_us(DELAY_TIME); + delay_timeout++; + } + if (delay_timeout > timeout) { + REG_IPC_STRUCT_RELEASE(scl_send) = SCL_RELEASE; + delay_timeout = 0; + return SCL_ERROR; + } else { + return SCL_SUCCESS; + } + } else { + SCL_LOG(("unable to acquire lock\n")); + return SCL_ERROR; + } +} + +scl_result_t scl_end(void) +{ + scl_result_t retval = SCL_SUCCESS; + if (g_scl_thread_info.scl_inited == SCL_TRUE) { + retval = (scl_result_t) cy_rtos_terminate_thread(&g_scl_thread_info.scl_thread); + if (retval == SCL_SUCCESS) { + retval = (scl_result_t) cy_rtos_join_thread(&g_scl_thread_info.scl_thread); + if (retval == SCL_SUCCESS) { + retval = (scl_result_t) cy_rtos_deinit_semaphore(&g_scl_thread_info.scl_rx_ready); + if (retval == SCL_SUCCESS) { + g_scl_thread_info.scl_inited = SCL_FALSE; + } + } + } + } + return retval; +} + +/** Thread to handle the received buffer + */ +static void scl_rx_handler(void) +{ + char *buffer = NULL; + nsapi_connection_status_t connection_status; + uint32_t index; + IPC_STRUCT_Type *scl_receive = NULL; + scl_buffer_t cp_buffer; + scl_buffer_t scl_buffer; + uint32_t rx_ipc_size; + struct rx_ipc_info { + uint32_t size; + int *buf_alloc; + }*rx_cp = NULL; + + SCL_LOG(("Starting CP Rx thread\r\n")); + scl_receive = Cy_IPC_Drv_GetIpcBaseAddress(SCL_RX_CHANNEL); + + while (SCL_TRUE) { + cy_rtos_get_semaphore(&g_scl_thread_info.scl_rx_ready, CY_RTOS_NEVER_TIMEOUT, SCL_FALSE); + index = (uint32_t)REG_IPC_STRUCT_DATA0(scl_receive); + SCL_LOG(("scl_rx_handler index = %lu\n", index)); + switch (index) { + case SCL_RX_DATA: { + rx_cp = (struct rx_ipc_info *) REG_IPC_STRUCT_DATA1(scl_receive); + scl_buffer = rx_cp->buf_alloc; + REG_IPC_STRUCT_RELEASE(scl_receive) = SCL_RELEASE; + SCL_LOG(("scl_buffer = %p\n", scl_buffer)); + scl_network_process_ethernet_data(scl_buffer); + break; + } + case SCL_RX_TEST_MSG: { + buffer = (char *) REG_IPC_STRUCT_DATA1(scl_receive); + SCL_LOG(("%s\r\n", (char *) buffer)); + REG_IPC_STRUCT_RELEASE(scl_receive) = SCL_RELEASE; + break; + } + case SCL_RX_GET_BUFFER: { + rx_ipc_size = (uint32_t) REG_IPC_STRUCT_DATA1(scl_receive); + scl_host_buffer_get(&cp_buffer, SCL_NETWORK_RX, rx_ipc_size, SCL_FALSE); + REG_IPC_STRUCT_DATA1(scl_receive) = (uint32_t)cp_buffer; + REG_IPC_STRUCT_RELEASE(scl_receive) = SCL_RELEASE; + break; + } + case SCL_RX_GET_CONNECTION_STATUS: { + connection_status = (nsapi_connection_status_t) REG_IPC_STRUCT_DATA1(scl_receive); + if (connection_status == NSAPI_STATUS_GLOBAL_UP) { + scl_emac_wifi_link_state_changed(true); + } else { + scl_emac_wifi_link_state_changed(false); + } + SCL_LOG(("connection status = %d\n", connection_status)); + break; + } + default: { + SCL_LOG(("incorrect IPC from Network Processor\n")); + REG_IPC_STRUCT_RELEASE(scl_receive) = SCL_RELEASE; + break; + } + } + } +} + +scl_result_t scl_get_nw_parameters(network_params_t *nw_param) +{ + scl_result_t status = SCL_ERROR; + status = scl_send_data(SCL_TX_WIFI_NW_PARAM, (char *)nw_param, TIMER_DEFAULT_VALUE); + return status; +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/include/scl_buffer_api.h b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/include/scl_buffer_api.h new file mode 100644 index 00000000000..7a188ce9d2f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/include/scl_buffer_api.h @@ -0,0 +1,113 @@ +/* + * Copyright 2018-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** @file + * Provides declarations for buffer management functionality + */ +#ifndef _SCL_INTERNAL_BUFFER_API_H_ +#define _SCL_INTERNAL_BUFFER_API_H_ + +#include "scl_types.h" +#include "scl_common.h" +#include +#include "cy_utils.h" +#include "memp.h" +#include "pbuf.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/****************************************************** +* Constants +******************************************************/ +/** + * Size of the SDIO block + */ +#define SDIO_BLOCK_SIZE (64U) + +/****************************************************** +* Macros +******************************************************/ + +/****************************************************** +* Structures and Enumerations +******************************************************/ +/** + * Indicates the transmit/receive direction that the buffer has + * been used for. This is needed if transmit/receive pools are separate. + */ +typedef enum { + SCL_NETWORK_TX = 0, /**< Transmit direction */ + SCL_NETWORK_RX = 1 /**< Receive direction */ +} scl_buffer_dir_t; + +/****************************************************** +* Function Prototypes +******************************************************/ +/** Allocates the SCL buffer. + * + * Attempts to allocate a buffer of the requested size. A buffer + * is either allocated from a static pool of memory or allocated dynamically. + * + * @param buffer A pointer which receives the allocated buffer. + * @param direction Indicates transmit/receive direction that the buffer is + * used for. This may be needed if transmit/receive pools are separate. + * @param size The number of bytes to allocate. + * @param wait Time to wait for a buffer to be available in milli-seconds. + * + * @return SCL_SUCCESS or Error code + * + */ +scl_result_t scl_host_buffer_get(scl_buffer_t *buffer, scl_buffer_dir_t direction, + uint16_t size, uint32_t wait); + +/** Releases the SCL buffer. + * + * This function is used by SCL to indicate that it no longer requires + * the buffer. The buffer can then be released back into a pool for + * reuse or the dynamically allocated memory can be freed. + * + * @param buffer The buffer to be released. + * @param direction Indicates the transmit/receive direction that the buffer has + * been used for. This might be needed if transmit/receive pools are separate. + * + */ +void scl_buffer_release(scl_buffer_t buffer, scl_buffer_dir_t direction); + +/** Retrieves the pointer to the payload of the buffer. + * + * @param buffer The buffer whose payload pointer is to be retrieved. + * + * @return Pointer to the payload. + */ +uint8_t *scl_buffer_get_current_piece_data_pointer(scl_buffer_t buffer); + +/** Retrieves the size of the buffer. + * + * @param buffer The buffer whose size is to be retrieved. + * + * @return The size of the buffer. + */ +uint16_t scl_buffer_get_current_piece_size(scl_buffer_t buffer); + +#ifdef __cplusplus +} /*extern "C" */ +#endif + +#endif /* ifndef _SCL_INTERNAL_BUFFER_API_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/scl_buffer_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/scl_buffer_api.c new file mode 100644 index 00000000000..ec4d33a412f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/scl_buffer_api.c @@ -0,0 +1,82 @@ +/* + * Copyright 2018-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "scl_buffer_api.h" + +/****************************************************** +** @cond Constants +*******************************************************/ + +/****************************************************** +** Enumerations +*******************************************************/ + +/****************************************************** +** Function Declarations +*******************************************************/ + +/****************************************************** + * Variables Definitions + *****************************************************/ + +/****************************************************** +* Function Definitions +******************************************************/ + +scl_result_t scl_host_buffer_get(scl_buffer_t *buffer, scl_buffer_dir_t direction, + uint16_t size, uint32_t wait) +{ + UNUSED_PARAMETER(direction); + struct pbuf *p = NULL; + if ((direction == SCL_NETWORK_TX) && (size <= PBUF_POOL_BUFSIZE)) { + p = pbuf_alloc(PBUF_RAW, size, PBUF_POOL); + } else { + p = pbuf_alloc(PBUF_RAW, size + SDIO_BLOCK_SIZE, PBUF_RAM); + if (p != NULL) { + p->len = size; + p->tot_len -= SDIO_BLOCK_SIZE; + } + } + if (p != NULL) { + *buffer = p; + return SCL_SUCCESS; + } else { + return SCL_BUFFER_ALLOC_FAIL; + } + +} + +void scl_buffer_release(scl_buffer_t buffer, scl_buffer_dir_t direction) +{ + UNUSED_PARAMETER(direction); + (void) pbuf_free((struct pbuf *)buffer); +} + +uint8_t *scl_buffer_get_current_piece_data_pointer(scl_buffer_t buffer) +{ + CY_ASSERT(buffer != NULL); + struct pbuf *pbuffer = (struct pbuf *) buffer; + return (uint8_t *) pbuffer->payload; +} + +uint16_t scl_buffer_get_current_piece_size(scl_buffer_t buffer) +{ + CY_ASSERT(buffer != NULL); + struct pbuf *pbuffer = (struct pbuf *) buffer; + return (uint16_t) pbuffer->len; +} + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/scl_wifi_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/scl_wifi_api.c new file mode 100644 index 00000000000..92b7e43d8d8 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/COMPONENT_SCL/src/scl_wifi_api.c @@ -0,0 +1,160 @@ +/* + * Copyright 2018-2020 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "scl_wifi_api.h" +#include "scl_ipc.h" + +/****************************************************** + * Variables Definitions + *****************************************************/ + +typedef struct { + scl_mac_t *mac; + uint32_t retval; +} scl_mac; + +/****************************************************** + * Function Definitions + ******************************************************/ + +scl_result_t scl_wifi_is_ready_to_transceive(void) +{ + scl_result_t result = SCL_SUCCESS; + scl_result_t retval = SCL_SUCCESS; + + result = scl_send_data(SCL_TX_TRANSCEIVE_READY, (char *)&retval, TIMER_DEFAULT_VALUE); + if (result == SCL_ERROR) { + SCL_LOG(("Ready to tranceive error\n")); + return SCL_ERROR; + } else { + return retval; + } +} + +bool scl_wifi_on(void) +{ + bool retval = false; + scl_result_t result = SCL_SUCCESS; + result = scl_send_data(SCL_TX_WIFI_ON, (char *)&retval, WIFI_ON_TIMEOUT); + if (result == SCL_ERROR) { + SCL_LOG(("wifi_on Error\n")); + return false; + } else { + return retval; + } +} + +scl_result_t scl_wifi_set_up(void) +{ + scl_result_t retval = SCL_SUCCESS; + scl_result_t result = SCL_SUCCESS; + result = scl_send_data(SCL_TX_WIFI_SET_UP, (char *)&retval, TIMER_DEFAULT_VALUE); + if (result == SCL_SUCCESS) { + return retval; + } else { + SCL_LOG(("Wifi set up error\n")); + return SCL_ERROR; + } +} + +scl_result_t scl_wifi_get_mac_address(scl_mac_t *mac) +{ + scl_mac scl_mac_data; + scl_result_t scl_retval = SCL_SUCCESS; + scl_mac_data.mac = mac; + scl_mac_data.retval = SCL_SUCCESS; + + if (mac == NULL) { + return SCL_BADARG; + } + scl_retval = scl_send_data(SCL_TX_GET_MAC, (char *)&scl_mac_data, TIMER_DEFAULT_VALUE); + if (scl_retval == SCL_SUCCESS) { + return scl_mac_data.retval; + } else { + SCL_LOG(("Get MAC address error\n")); + return SCL_ERROR; + } +} + +scl_result_t scl_wifi_get_bssid(scl_mac_t *bssid) +{ + struct scl_bssid { + scl_mac_t *bssid; + uint32_t retval; + } scl_bssid_t; + scl_result_t scl_retval = SCL_SUCCESS; + scl_bssid_t.bssid = bssid; + scl_bssid_t.retval = 0; + if (bssid == NULL) { + return SCL_BADARG; + } + scl_retval = scl_send_data(SCL_TX_WIFI_GET_BSSID, (char *)&scl_bssid_t, TIMER_DEFAULT_VALUE); + if (scl_retval == SCL_SUCCESS) { + return scl_bssid_t.retval; + } else { + SCL_LOG(("get bssid error\n")); + return SCL_ERROR; + } +} + +scl_result_t scl_wifi_register_multicast_address(scl_mac_t *mac) +{ + scl_mac scl_mac_t; + scl_mac_t.mac = mac; + scl_mac_t.retval = 0; + scl_result_t scl_retval = SCL_SUCCESS; + if (mac == NULL) { + return SCL_BADARG; + } + scl_retval = scl_send_data(SCL_TX_REGISTER_MULTICAST_ADDRESS, (char *)&scl_mac_t, TIMER_DEFAULT_VALUE); + if (scl_retval != SCL_SUCCESS) { + SCL_LOG(("Register Multicast Address IPC Error")); + return SCL_ERROR; + } + return (scl_mac_t.retval); +} + +scl_result_t scl_network_send_ethernet_data(scl_tx_buf_t scl_buffer) +{ + scl_result_t retval = SCL_SUCCESS; + if (scl_buffer.buffer == NULL) { + return SCL_BADARG; + } + retval = scl_send_data(SCL_TX_SEND_OUT, (char *)&scl_buffer, TIMER_DEFAULT_VALUE); + return retval; +} + +scl_result_t scl_wifi_get_rssi(int32_t *rssi) +{ + struct tx_param { + uint32_t retval; + int32_t *get_rssi; + } tx_param_t; + scl_result_t scl_retval = SCL_SUCCESS; + + if (rssi == NULL) { + return SCL_BADARG; + } + tx_param_t.get_rssi = rssi; + scl_retval = scl_send_data(SCL_TX_WIFI_GET_RSSI, (char *) &tx_param_t, TIMER_DEFAULT_VALUE); + if (scl_retval == SCL_SUCCESS) { + return tx_param_t.retval; + } else { + SCL_LOG(("get rssi error\n")); + return SCL_ERROR; + } +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/PeripheralPins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/PeripheralPins.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/PeripheralPins.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/PeripheralPins.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/system_psoc6_cm0plus.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM0P/system_psoc6_cm0plus.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM0P/system_psoc6_cm0plus.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/system_psoc6_cm4.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/COMPONENT_CM4/system_psoc6_cm4.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/COMPONENT_CM4/system_psoc6_cm4.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/system_psoc6.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S2_43012/device/system_psoc6.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062S2_43012/device/system_psoc6.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.c index 6c8154e78d5..4e48631123a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.c @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -111,7 +111,7 @@ cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t *para CY_UNUSED_PARAMETER(params); cy_en_syspm_status_t status = CY_SYSPM_FAIL; - switch (mode) + switch (mode) { case CY_SYSPM_CHECK_READY: case CY_SYSPM_CHECK_FAIL: @@ -656,7 +656,7 @@ en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd) cy_rslt_t result; /* Initialize the semaphore. This is not done in init because init is called - * in interrupt thread. cy_rtos_init_semaphore call is prohibited in + * in interrupt thread. cy_rtos_init_semaphore call is prohibited in * interrupt thread. */ if(!sema_initialized) @@ -770,16 +770,16 @@ en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd) #ifdef CY_RTOS_AWARE /* Wait for the transfer to finish. - * Acquire semaphore and wait until it will be released + * Acquire semaphore and wait until it will be released * in SDIO_IRQ: - * 1. sdio_transfer_finished_semaphore count is equal to - * zero. cy_rtos_get_semaphore waits until semaphore - * count is increased by cy_rtos_set_semaphore() in + * 1. sdio_transfer_finished_semaphore count is equal to + * zero. cy_rtos_get_semaphore waits until semaphore + * count is increased by cy_rtos_set_semaphore() in * SDIO_IRQ. - * 2. The cy_rtos_set_semaphore() increases + * 2. The cy_rtos_set_semaphore() increases * sdio_transfer_finished_semaphore count. - * 3. The cy_rtos_get_semaphore() function decreases - * sdio_transfer_finished_semaphore back to zero + * 3. The cy_rtos_get_semaphore() function decreases + * sdio_transfer_finished_semaphore back to zero * and exit. Or timeout occurs */ result = cy_rtos_get_semaphore( &sdio_transfer_finished_semaphore, 10, false ); @@ -1080,7 +1080,12 @@ void SDIO_DisableSdClk(void) void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz) { uint16_t u16Div; - u16Div = Cy_SysClk_ClkPeriGetFrequency() / u32SdClkFreqHz; + /* + * The UDB SDIO implemenation has a extra divider internally that divides the input clock to the UDB + * by 2. The desired clock frequency is hence intentionally multiplied by 2 in order to get the required + * SDIO operating frequency. + */ + u16Div = Cy_SysClk_ClkPeriGetFrequency() / (2 * u32SdClkFreqHz); Cy_SysClk_PeriphSetDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM, (u16Div-1)); } @@ -1247,10 +1252,10 @@ void SDIO_IRQ(void) { pfnCardInt_count++; } - + /* Execute card interrupt callback if neccesary */ if (0 != pfnCardInt_count) - { + { if (NULL != gstcInternalData.pstcCallBacks.pfnCardIntCb) { gstcInternalData.pstcCallBacks.pfnCardIntCb(); @@ -1277,7 +1282,7 @@ void SDIO_IRQ(void) /* CRC was bad, set the flag */ gstcInternalData.stcEvents.u8CRCError++; } - + /* Set the done flag */ #ifdef CY_RTOS_AWARE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.h index b821eb9a461..06edc747bc9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST.h @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.c index 94e533da700..a2808d37c04 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.c @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.h index bed87f55bf0..39febda5730 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_WIFI_BT/SDIO_HOST/SDIO_HOST_cfg.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/PeripheralNames.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/PeripheralNames.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/PeripheralNames.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/PeripheralNames.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/PeripheralPins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/PeripheralPins.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/PeripheralPins.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/PeripheralPins.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xx5_cm0plus.sct diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_03_cm0plus.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm0plus.ld diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm0plus.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm0plus.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm0plus.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xx5_cm0plus.icf diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_03_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_03_cm0plus.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_03_cm0plus.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_03_cm0plus.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xx5_cm4_dual.sct diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_03_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_03_cm4.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_03_cm4.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_03_cm4.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xx5_cm4_dual.ld diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_03_cm4.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xx5_cm4_dual.icf diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_03_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_03_cm4.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_03_cm4.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_03_cm4.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/system_psoc6.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062S3_4343W/device/system_psoc6.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062S3_4343W/device/system_psoc6.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/PeripheralPins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/PeripheralPins.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/PeripheralPins.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/PeripheralPins.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/cy8c6xxa_cm0plus.sct diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_ARM/startup_psoc6_02_cm0plus.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm0plus.ld diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm0plus.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/cy8c6xxa_cm0plus.icf diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/TOOLCHAIN_IAR/startup_psoc6_02_cm0plus.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM0P/system_psoc6_cm0plus.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/COMPONENT_CM4/system_psoc6_cm4.c diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/system_psoc6.h similarity index 100% rename from targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CMOD_062_4343W/device/system_psoc6.h rename to targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CPROTO_062_4343W/device/system_psoc6.h diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c new file mode 100644 index 00000000000..54662185ade --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -0,0 +1,33 @@ +/******************************************************************************* +* File Name: cycfg.c +* +* Description: +* Wrapper function to initialize all generated code. +* This file was automatically generated and should not be modified. +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.3.1.1499 +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg.h" + +void init_cycfg_all(void) +{ + init_cycfg_routing(); + init_cycfg_pins(); +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h new file mode 100644 index 00000000000..6ceb622e4f4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -0,0 +1,47 @@ +/******************************************************************************* +* File Name: cycfg.h +* +* Description: +* Simple wrapper header containing all generated files. +* This file was automatically generated and should not be modified. +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.3.1.1499 +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_H) +#define CYCFG_H + +#if defined(__cplusplus) +extern "C" { +#endif + +#include "cycfg_notices.h" +#include "cycfg_system.h" +#include "cycfg_routing.h" +#include "cycfg_pins.h" + +void init_cycfg_all(void); + + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp new file mode 100644 index 00000000000..8619de15427 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -0,0 +1,26 @@ +/******************************************************************************* +* File Name: cycfg.timestamp +* +* Description: +* Sentinel file for determining if generated source is up to date. +* This file was automatically generated and should not be modified. +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.3.1.1499 +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h new file mode 100644 index 00000000000..3587d0e5f0e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -0,0 +1,32 @@ +/******************************************************************************* +* File Name: cycfg_notices.h +* +* Description: +* Contains warnings and errors that occurred while generating code for the +* design. +* This file was automatically generated and should not be modified. +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.3.1.1499 +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_NOTICES_H) +#define CYCFG_NOTICES_H + + +#endif /* CYCFG_NOTICES_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c new file mode 100644 index 00000000000..41daa132b46 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -0,0 +1,177 @@ +/******************************************************************************* +* File Name: cycfg_pins.c +* +* Description: +* Pin configuration +* This file was automatically generated and should not be modified. +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.3.1.1499 +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_pins.h" + +const cy_stc_gpio_pin_config_t CYBSP_SW1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_ANALOG, + .hsiom = CYBSP_SW1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_SW1_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_SW1_PORT_NUM, + .channel_num = CYBSP_SW1_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_LED1_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_LED1_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_LED1_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_LED1_PORT_NUM, + .channel_num = CYBSP_LED1_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_SWO_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_STRONG_IN_OFF, + .hsiom = CYBSP_SWO_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_SWO_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_SWO_PORT_NUM, + .channel_num = CYBSP_SWO_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLUP, + .hsiom = CYBSP_SWDIO_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_SWDIO_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_SWDIO_PORT_NUM, + .channel_num = CYBSP_SWDIO_PIN, + }; +#endif //defined (CY_USING_HAL) +const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config = +{ + .outVal = 1, + .driveMode = CY_GPIO_DM_PULLDOWN, + .hsiom = CYBSP_SWDCK_HSIOM, + .intEdge = CY_GPIO_INTR_DISABLE, + .intMask = 0UL, + .vtrip = CY_GPIO_VTRIP_CMOS, + .slewRate = CY_GPIO_SLEW_FAST, + .driveSel = CY_GPIO_DRIVE_1_2, + .vregEn = 0UL, + .ibufMode = 0UL, + .vtripSel = 0UL, + .vrefSel = 0UL, + .vohSel = 0UL, +}; +#if defined (CY_USING_HAL) + const cyhal_resource_inst_t CYBSP_SWDCK_obj = + { + .type = CYHAL_RSC_GPIO, + .block_num = CYBSP_SWDCK_PORT_NUM, + .channel_num = CYBSP_SWDCK_PIN, + }; +#endif //defined (CY_USING_HAL) + + +void init_cycfg_pins(void) +{ + Cy_GPIO_Pin_Init(CYBSP_SW1_PORT, CYBSP_SW1_PIN, &CYBSP_SW1_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_SW1_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_LED1_PORT, CYBSP_LED1_PIN, &CYBSP_LED1_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_LED1_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_SWO_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_SWDIO_PORT, CYBSP_SWDIO_PIN, &CYBSP_SWDIO_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_SWDIO_obj); +#endif //defined (CY_USING_HAL) + + Cy_GPIO_Pin_Init(CYBSP_SWDCK_PORT, CYBSP_SWDCK_PIN, &CYBSP_SWDCK_config); +#if defined (CY_USING_HAL) + cyhal_hwmgr_reserve(&CYBSP_SWDCK_obj); +#endif //defined (CY_USING_HAL) +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h new file mode 100644 index 00000000000..4aacaaa8d37 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -0,0 +1,190 @@ +/******************************************************************************* +* File Name: cycfg_pins.h +* +* Description: +* Pin configuration +* This file was automatically generated and should not be modified. +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.3.1.1499 +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_PINS_H) +#define CYCFG_PINS_H + +#include "cycfg_notices.h" +#include "cy_gpio.h" +#if defined (CY_USING_HAL) + #include "cyhal_hwmgr.h" +#endif //defined (CY_USING_HAL) +#include "cycfg_routing.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define CYBSP_SW1_ENABLED 1U +#define CYBSP_SW1_PORT GPIO_PRT0 +#define CYBSP_SW1_PORT_NUM 0U +#define CYBSP_SW1_PIN 4U +#define CYBSP_SW1_NUM 4U +#define CYBSP_SW1_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_SW1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_0_pin_4_HSIOM + #define ioss_0_port_0_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SW1_HSIOM ioss_0_port_0_pin_4_HSIOM +#define CYBSP_SW1_IRQ ioss_interrupts_gpio_0_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_SW1_HAL_PORT_PIN P0_4 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SW1_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SW1_HAL_DIR CYHAL_GPIO_DIR_INPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SW1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG +#endif //defined (CY_USING_HAL) +#define CYBSP_LED1_ENABLED 1U +#define CYBSP_LED1_PORT GPIO_PRT11 +#define CYBSP_LED1_PORT_NUM 11U +#define CYBSP_LED1_PIN 1U +#define CYBSP_LED1_NUM 1U +#define CYBSP_LED1_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_LED1_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_11_pin_1_HSIOM + #define ioss_0_port_11_pin_1_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_LED1_HSIOM ioss_0_port_11_pin_1_HSIOM +#define CYBSP_LED1_IRQ ioss_interrupts_gpio_11_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_LED1_HAL_PORT_PIN P11_1 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_LED1_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_LED1_HAL_DIR CYHAL_GPIO_DIR_OUTPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_LED1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG +#endif //defined (CY_USING_HAL) +#define CYBSP_SWO_ENABLED 1U +#define CYBSP_SWO_PORT GPIO_PRT6 +#define CYBSP_SWO_PORT_NUM 6U +#define CYBSP_SWO_PIN 4U +#define CYBSP_SWO_NUM 4U +#define CYBSP_SWO_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF +#define CYBSP_SWO_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_4_HSIOM + #define ioss_0_port_6_pin_4_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SWO_HSIOM ioss_0_port_6_pin_4_HSIOM +#define CYBSP_SWO_IRQ ioss_interrupts_gpio_6_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_SWO_HAL_PORT_PIN P6_4 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWO_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWO_HAL_DIR CYHAL_GPIO_DIR_OUTPUT +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_STRONG +#endif //defined (CY_USING_HAL) +#define CYBSP_SWDIO_ENABLED 1U +#define CYBSP_SWDIO_PORT GPIO_PRT6 +#define CYBSP_SWDIO_PORT_NUM 6U +#define CYBSP_SWDIO_PIN 6U +#define CYBSP_SWDIO_NUM 6U +#define CYBSP_SWDIO_DRIVEMODE CY_GPIO_DM_PULLUP +#define CYBSP_SWDIO_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_6_HSIOM + #define ioss_0_port_6_pin_6_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SWDIO_HSIOM ioss_0_port_6_pin_6_HSIOM +#define CYBSP_SWDIO_IRQ ioss_interrupts_gpio_6_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_SWDIO_HAL_PORT_PIN P6_6 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDIO_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDIO_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDIO_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLUP +#endif //defined (CY_USING_HAL) +#define CYBSP_SWDCK_ENABLED 1U +#define CYBSP_SWDCK_PORT GPIO_PRT6 +#define CYBSP_SWDCK_PORT_NUM 6U +#define CYBSP_SWDCK_PIN 7U +#define CYBSP_SWDCK_NUM 7U +#define CYBSP_SWDCK_DRIVEMODE CY_GPIO_DM_PULLDOWN +#define CYBSP_SWDCK_INIT_DRIVESTATE 1 +#ifndef ioss_0_port_6_pin_7_HSIOM + #define ioss_0_port_6_pin_7_HSIOM HSIOM_SEL_GPIO +#endif +#define CYBSP_SWDCK_HSIOM ioss_0_port_6_pin_7_HSIOM +#define CYBSP_SWDCK_IRQ ioss_interrupts_gpio_6_IRQn +#if defined (CY_USING_HAL) + #define CYBSP_SWDCK_HAL_PORT_PIN P6_7 +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDCK_HAL_IRQ CYHAL_GPIO_IRQ_NONE +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDCK_HAL_DIR CYHAL_GPIO_DIR_BIDIRECTIONAL +#endif //defined (CY_USING_HAL) +#if defined (CY_USING_HAL) + #define CYBSP_SWDCK_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_PULLDOWN +#endif //defined (CY_USING_HAL) + +extern const cy_stc_gpio_pin_config_t CYBSP_SW1_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_SW1_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_LED1_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_LED1_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_SWO_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_SWDIO_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_SWDIO_obj; +#endif //defined (CY_USING_HAL) +extern const cy_stc_gpio_pin_config_t CYBSP_SWDCK_config; +#if defined (CY_USING_HAL) + extern const cyhal_resource_inst_t CYBSP_SWDCK_obj; +#endif //defined (CY_USING_HAL) + +void init_cycfg_pins(void); + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_PINS_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c new file mode 100644 index 00000000000..92d57a03ff9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.c @@ -0,0 +1,266 @@ +/******************************************************************************* +* File Name: cycfg_qspi_memslot.c +* +* Description: +* Provides definitions of the SMIF-driver memory configuration. +* This file was automatically generated and should not be modified. +* QSPI Configurator: 2.0.0.1483 +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_qspi_memslot.h" + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0xEBU, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_QUAD, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0x01U, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_QUAD, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 4U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_QUAD +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x06U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x04U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0xD8U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x60U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x38U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_QUAD, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_QUAD +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x35U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x05U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd = +{ + /* The 8-bit command. 1 x I/O read command. */ + .command = 0x01U, + /* The width of the command transfer. */ + .cmdWidth = CY_SMIF_WIDTH_SINGLE, + /* The width of the address transfer. */ + .addrWidth = CY_SMIF_WIDTH_SINGLE, + /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */ + .mode = 0xFFFFFFFFU, + /* The width of the mode command transfer. */ + .modeWidth = CY_SMIF_WIDTH_SINGLE, + /* The number of dummy cycles. A zero value suggests no dummy cycles. */ + .dummyCycles = 0U, + /* The width of the data transfer. */ + .dataWidth = CY_SMIF_WIDTH_SINGLE +}; + +const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0 = +{ + /* Specifies the number of address bytes used by the memory slave device. */ + .numOfAddrBytes = 0x03U, + /* The size of the memory. */ + .memSize = 0x04000000U, + /* Specifies the Read command. */ + .readCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readCmd, + /* Specifies the Write Enable command. */ + .writeEnCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeEnCmd, + /* Specifies the Write Disable command. */ + .writeDisCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeDisCmd, + /* Specifies the Erase command. */ + .eraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_eraseCmd, + /* Specifies the sector size of each erase. */ + .eraseSize = 0x00040000U, + /* Specifies the Chip Erase command. */ + .chipEraseCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_chipEraseCmd, + /* Specifies the Program command. */ + .programCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_programCmd, + /* Specifies the page size for programming. */ + .programSize = 0x00000200U, + /* Specifies the command to read the QE-containing status register. */ + .readStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegQeCmd, + /* Specifies the command to read the WIP-containing status register. */ + .readStsRegWipCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_readStsRegWipCmd, + /* Specifies the command to write into the QE-containing status register. */ + .writeStsRegQeCmd = (cy_stc_smif_mem_cmd_t*)&S25FL512S_SlaveSlot_0_writeStsRegQeCmd, + /* The mask for the status register. */ + .stsRegBusyMask = 0x01U, + /* The mask for the status register. */ + .stsRegQuadEnableMask = 0x02U, + /* The max time for the erase type-1 cycle-time in ms. */ + .eraseTime = 2600U, + /* The max time for the chip-erase cycle-time in ms. */ + .chipEraseTime = 460000U, + /* The max time for the page-program cycle-time in us. */ + .programTime = 1300U +}; + +const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0 = +{ + /* Determines the slot number where the memory device is placed. */ + .slaveSelect = CY_SMIF_SLAVE_SELECT_0, + /* Flags. */ + .flags = CY_SMIF_FLAG_WR_EN, + /* The data-line selection options for a slave device. */ + .dataSelect = CY_SMIF_DATA_SEL0, + /* The base address the memory slave is mapped to in the PSoC memory map. + Valid when the memory-mapped mode is enabled. */ + .baseAddress = 0x18000000U, + /* The size allocated in the PSoC memory map, for the memory slave device. + The size is allocated from the base address. Valid when the memory mapped mode is enabled. */ + .memMappedSize = 0x10000U, + /* If this memory device is one of the devices in the dual quad SPI configuration. + Valid when the memory mapped mode is enabled. */ + .dualQuadSlots = 0, + /* The configuration of the device. */ + .deviceCfg = (cy_stc_smif_mem_device_cfg_t*)&deviceCfg_S25FL512S_SlaveSlot_0 +}; + +const cy_stc_smif_mem_config_t* const smifMemConfigs[] = { + &S25FL512S_SlaveSlot_0 +}; + +const cy_stc_smif_block_config_t smifBlockConfig = +{ + /* The number of SMIF memories defined. */ + .memCount = CY_SMIF_DEVICE_NUM, + /* The pointer to the array of memory config structures of size memCount. */ + .memConfig = (cy_stc_smif_mem_config_t**)smifMemConfigs, + /* The version of the SMIF driver. */ + .majorVersion = CY_SMIF_DRV_VERSION_MAJOR, + /* The version of the SMIF driver. */ + .minorVersion = CY_SMIF_DRV_VERSION_MINOR +}; + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h new file mode 100644 index 00000000000..c313452c105 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_qspi_memslot.h @@ -0,0 +1,51 @@ +/******************************************************************************* +* File Name: cycfg_qspi_memslot.h +* +* Description: +* Provides declarations of the SMIF-driver memory configuration. +* This file was automatically generated and should not be modified. +* QSPI Configurator: 2.0.0.1483 +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#ifndef CYCFG_QSPI_MEMSLOT_H +#define CYCFG_QSPI_MEMSLOT_H +#include "cy_smif_memslot.h" + +#define CY_SMIF_DEVICE_NUM 1 + +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeEnCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeDisCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_eraseCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_chipEraseCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_programCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegQeCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_readStsRegWipCmd; +extern const cy_stc_smif_mem_cmd_t S25FL512S_SlaveSlot_0_writeStsRegQeCmd; + +extern const cy_stc_smif_mem_device_cfg_t deviceCfg_S25FL512S_SlaveSlot_0; + +extern const cy_stc_smif_mem_config_t S25FL512S_SlaveSlot_0; +extern const cy_stc_smif_mem_config_t* const smifMemConfigs[CY_SMIF_DEVICE_NUM]; + +extern const cy_stc_smif_block_config_t smifBlockConfig; + + +#endif /*CY_SMIF_MEMCONFIG_H*/ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c new file mode 100644 index 00000000000..a8de1e3d5fa --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c @@ -0,0 +1,31 @@ +/******************************************************************************* +* File Name: cycfg_routing.c +* +* Description: +* Establishes all necessary connections between hardware elements. +* This file was automatically generated and should not be modified. +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.3.1.1499 +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_routing.h" + +void init_cycfg_routing(void) +{ +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h new file mode 100644 index 00000000000..645fc6902db --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -0,0 +1,46 @@ +/******************************************************************************* +* File Name: cycfg_routing.h +* +* Description: +* Establishes all necessary connections between hardware elements. +* This file was automatically generated and should not be modified. +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.3.1.1499 +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_ROUTING_H) +#define CYCFG_ROUTING_H + +#if defined(__cplusplus) +extern "C" { +#endif + +#include "cycfg_notices.h" +void init_cycfg_routing(void); +#define init_cycfg_connectivity() init_cycfg_routing() +#define ioss_0_port_6_pin_4_HSIOM P6_4_CPUSS_SWJ_SWO_TDO +#define ioss_0_port_6_pin_6_HSIOM P6_6_CPUSS_SWJ_SWDIO_TMS +#define ioss_0_port_6_pin_7_HSIOM P6_7_CPUSS_SWJ_SWCLK_TCLK + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_ROUTING_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c new file mode 100644 index 00000000000..d06a4b5f862 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -0,0 +1,28 @@ +/******************************************************************************* +* File Name: cycfg_system.c +* +* Description: +* System configuration +* This file was automatically generated and should not be modified. +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.3.1.1499 +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_system.h" + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h new file mode 100644 index 00000000000..106e61a459f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -0,0 +1,43 @@ +/******************************************************************************* +* File Name: cycfg_system.h +* +* Description: +* System configuration +* This file was automatically generated and should not be modified. +* Device Configurator: 2.0.0.1483 +* Device Support Library (../../../psoc6pdl): 1.3.1.1499 +* +******************************************************************************** +* Copyright 2017-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_SYSTEM_H) +#define CYCFG_SYSTEM_H + +#include "cycfg_notices.h" +#if defined(__cplusplus) +extern "C" { +#endif + +#define cpuss_0_dap_0_ENABLED 1U + + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_SYSTEM_H */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg new file mode 100644 index 00000000000..a561643dcf1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/qspi_config.cfg @@ -0,0 +1,2 @@ +set SMIF_BANKS { +} diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list new file mode 100644 index 00000000000..edb189b2e25 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/cyreservedresources.list @@ -0,0 +1,99 @@ +[Device=CY8C624AFNI-D43] + +[Blocks] +# WIFI +# CYBSP_WIFI_SDIO +sdhc[0] +# CYBSP_WIFI_SDIO_D0 +ioss[0].port[2].pin[0] +# CYBSP_WIFI_SDIO_D1 +ioss[0].port[2].pin[1] +# CYBSP_WIFI_SDIO_D2 +ioss[0].port[2].pin[2] +# CYBSP_WIFI_SDIO_D3 +ioss[0].port[2].pin[3] +# CYBSP_WIFI_SDIO_CMD +ioss[0].port[2].pin[4] +# CYBSP_WIFI_SDIO_CLK +ioss[0].port[2].pin[5] +# CYBSP_WIFI_WL_REG_ON +ioss[0].port[2].pin[6] +# CYBSP_WIFI_DEVICE_WAKE +ioss[0].port[2].pin[7] +# CYBSP_WIFI_HOST_WAKE +ioss[0].port[1].pin[4] + +# BT UART +# CYBSP_BT_UART +scb[12] +# CYBSP_BT_POWER +ioss[0].port[12].pin[0] +# CYBSP_BT_DEVICE_WAKE +ioss[0].port[12].pin[2] +# CYBSP_BT_HOST_WAKE +ioss[0].port[12].pin[3] +# CYBSP_BT_UART_RX +ioss[0].port[13].pin[4] +# CYBSP_BT_UART_TX +ioss[0].port[13].pin[5] +# CYBSP_BT_UART_RTS +ioss[0].port[13].pin[6] +# CYBSP_BT_UART_CTS +ioss[0].port[13].pin[7] +# CYBSP_BT_UART_CLK_DIV +peri[0].div_16[1] + +# UART +# CYBSP_DEBUG_UART +scb[10] +# CYBSP_DEBUG_UART_RX +ioss[0].port[5].pin[4] +# CYBSP_DEBUG_UART_TX +ioss[0].port[5].pin[5] +# CYBSP_DEBUG_UART_CLK_DIV +peri[0].div_16[0] + +# POWER +srss[0].power[0] + +# SYSTEM CLOCK +srss[0].clock[0] +# CLK_ALT_SYS_TICK +srss[0].clock[0].altsystickclk[0] +# CLK_BAK +srss[0].clock[0].bakclk[0] +# CLK_FAST +srss[0].clock[0].fastclk[0] +# CLK_HF0 +srss[0].clock[0].hfclk[0] +# CLK_HF2 +srss[0].clock[0].hfclk[2] +# CLK_HF4 +srss[0].clock[0].hfclk[4] +# CLK_ILO +srss[0].clock[0].ilo[0] +# CLK_IMO +srss[0].clock[0].imo[0] +# CLK_LF +srss[0].clock[0].lfclk[0] +# PATH_MUX0 +srss[0].clock[0].pathmux[0] +# PATH_MUX1 +srss[0].clock[0].pathmux[1] +# CLK_PERI +srss[0].clock[0].periclk[0] +# CLK_PLL0 +srss[0].clock[0].pll[0] +# CLK_SLOW +srss[0].clock[0].slowclk[0] +# CLK_TIMER +srss[0].clock[0].timerclk[0] + +# RTC +srss[0].rtc[0] + +# CM0(NP) I2C +# CYBSP_I2C_SCL +ioss[0].port[8].pin[0] +# CYBSP_I2C_SDA +ioss[0].port[8].pin[1] diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense new file mode 100644 index 00000000000..a31d15e2933 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.cycapsense @@ -0,0 +1,71 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi new file mode 100644 index 00000000000..f0610e10677 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.cyqspi @@ -0,0 +1,63 @@ + + + + PSoC 6.xml + + + 0 + S25FL512S + false + None + 0x18000000 + 0x10000 + 0x1800FFFF + true + false + QUAD_SPI_DATA_0_3 + S25FL512S + true + + + 1 + Not used + false + None + 0x18010000 + 0x10000 + 0x1801FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + false + + + 2 + Not used + false + None + 0x18020000 + 0x10000 + 0x1802FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + false + + + 3 + Not used + false + None + 0x18030000 + 0x10000 + 0x1803FFFF + false + false + SPI_MOSI_MISO_DATA_0_1 + default_memory.xml + false + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.modus b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.modus new file mode 100644 index 00000000000..120837b1b13 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -0,0 +1,106 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/PeripheralPins.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/PeripheralPins.c new file mode 100644 index 00000000000..57eb8a28a67 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/PeripheralPins.c @@ -0,0 +1,427 @@ +/* + * mbed Microcontroller Library + * Copyright (c) 2017-2018 Future Electronics + * Copyright (c) 2019 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "PeripheralNames.h" +#include "PeripheralPins.h" +#include "pinmap.h" + +#if DEVICE_SERIAL +//*** SERIAL *** +const PinMap PinMap_UART_RX[] = { + {P0_2, UART_0, CYHAL_PIN_IN_FUNCTION(P0_2_SCB0_UART_RX)}, + {P1_0, UART_7, CYHAL_PIN_IN_FUNCTION(P1_0_SCB7_UART_RX)}, + {P2_0, UART_1, CYHAL_PIN_IN_FUNCTION(P2_0_SCB1_UART_RX)}, + {P2_4, UART_9, CYHAL_PIN_IN_FUNCTION(P2_4_SCB9_UART_RX)}, + {P5_0, UART_5, CYHAL_PIN_IN_FUNCTION(P5_0_SCB5_UART_RX)}, + {P5_4, UART_10, CYHAL_PIN_IN_FUNCTION(P5_4_SCB10_UART_RX)}, + {P6_0, UART_3, CYHAL_PIN_IN_FUNCTION(P6_0_SCB3_UART_RX)}, + {P6_4, UART_6, CYHAL_PIN_IN_FUNCTION(P6_4_SCB6_UART_RX)}, + {P7_0, UART_4, CYHAL_PIN_IN_FUNCTION(P7_0_SCB4_UART_RX)}, + {P8_0, UART_4, CYHAL_PIN_IN_FUNCTION(P8_0_SCB4_UART_RX)}, + {P8_4, UART_11, CYHAL_PIN_IN_FUNCTION(P8_4_SCB11_UART_RX)}, + {P9_0, UART_2, CYHAL_PIN_IN_FUNCTION(P9_0_SCB2_UART_RX)}, + {P10_0, UART_1, CYHAL_PIN_IN_FUNCTION(P10_0_SCB1_UART_RX)}, + {P11_0, UART_5, CYHAL_PIN_IN_FUNCTION(P11_0_SCB5_UART_RX)}, + {P12_0, UART_6, CYHAL_PIN_IN_FUNCTION(P12_0_SCB6_UART_RX)}, + {P13_0, UART_6, CYHAL_PIN_IN_FUNCTION(P13_0_SCB6_UART_RX)}, + {P13_4, UART_12, CYHAL_PIN_IN_FUNCTION(P13_4_SCB12_UART_RX)}, + {NC, NC, 0} +}; +const PinMap PinMap_UART_TX[] = { + {P0_3, UART_0, CYHAL_PIN_OUT_FUNCTION(P0_3_SCB0_UART_TX)}, + {P1_1, UART_7, CYHAL_PIN_OUT_FUNCTION(P1_1_SCB7_UART_TX)}, + {P2_1, UART_1, CYHAL_PIN_OUT_FUNCTION(P2_1_SCB1_UART_TX)}, + {P2_5, UART_9, CYHAL_PIN_OUT_FUNCTION(P2_5_SCB9_UART_TX)}, + {P5_1, UART_5, CYHAL_PIN_OUT_FUNCTION(P5_1_SCB5_UART_TX)}, + {P5_5, UART_10, CYHAL_PIN_OUT_FUNCTION(P5_5_SCB10_UART_TX)}, + {P6_1, UART_3, CYHAL_PIN_OUT_FUNCTION(P6_1_SCB3_UART_TX)}, + {P6_5, UART_6, CYHAL_PIN_OUT_FUNCTION(P6_5_SCB6_UART_TX)}, + {P7_1, UART_4, CYHAL_PIN_OUT_FUNCTION(P7_1_SCB4_UART_TX)}, + {P8_1, UART_4, CYHAL_PIN_OUT_FUNCTION(P8_1_SCB4_UART_TX)}, + {P9_1, UART_2, CYHAL_PIN_OUT_FUNCTION(P9_1_SCB2_UART_TX)}, + {P10_1, UART_1, CYHAL_PIN_OUT_FUNCTION(P10_1_SCB1_UART_TX)}, + {P11_1, UART_5, CYHAL_PIN_OUT_FUNCTION(P11_1_SCB5_UART_TX)}, + {P12_1, UART_6, CYHAL_PIN_OUT_FUNCTION(P12_1_SCB6_UART_TX)}, + {P13_1, UART_6, CYHAL_PIN_OUT_FUNCTION(P13_1_SCB6_UART_TX)}, + {P13_5, UART_12, CYHAL_PIN_OUT_FUNCTION(P13_5_SCB12_UART_TX)}, + {NC, NC, 0} +}; +const PinMap PinMap_UART_RTS[] = { + {P0_4, UART_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_UART_RTS)}, + {P2_2, UART_1, CYHAL_PIN_OUT_FUNCTION(P2_2_SCB1_UART_RTS)}, + {P2_6, UART_9, CYHAL_PIN_OUT_FUNCTION(P2_6_SCB9_UART_RTS)}, + {P5_2, UART_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_UART_RTS)}, + {P5_6, UART_10, CYHAL_PIN_OUT_FUNCTION(P5_6_SCB10_UART_RTS)}, + {P6_2, UART_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_UART_RTS)}, + {P6_6, UART_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_UART_RTS)}, + {P7_2, UART_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_UART_RTS)}, + {P8_2, UART_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_UART_RTS)}, + {P9_2, UART_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_UART_RTS)}, + {P10_2, UART_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_UART_RTS)}, + {P11_2, UART_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_UART_RTS)}, + {P12_2, UART_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_UART_RTS)}, + {P13_2, UART_6, CYHAL_PIN_OUT_FUNCTION(P13_2_SCB6_UART_RTS)}, + {P13_6, UART_12, CYHAL_PIN_OUT_FUNCTION(P13_6_SCB12_UART_RTS)}, + {NC, NC, 0} +}; +const PinMap PinMap_UART_CTS[] = { + {P0_5, UART_0, CYHAL_PIN_IN_FUNCTION(P0_5_SCB0_UART_CTS)}, + {P2_3, UART_1, CYHAL_PIN_IN_FUNCTION(P2_3_SCB1_UART_CTS)}, + {P2_7, UART_9, CYHAL_PIN_IN_FUNCTION(P2_7_SCB9_UART_CTS)}, + {P5_3, UART_5, CYHAL_PIN_IN_FUNCTION(P5_3_SCB5_UART_CTS)}, + {P5_7, UART_10, CYHAL_PIN_IN_FUNCTION(P5_7_SCB10_UART_CTS)}, + {P6_3, UART_3, CYHAL_PIN_IN_FUNCTION(P6_3_SCB3_UART_CTS)}, + {P6_7, UART_6, CYHAL_PIN_IN_FUNCTION(P6_7_SCB6_UART_CTS)}, + {P7_3, UART_4, CYHAL_PIN_IN_FUNCTION(P7_3_SCB4_UART_CTS)}, + {P8_3, UART_4, CYHAL_PIN_IN_FUNCTION(P8_3_SCB4_UART_CTS)}, + {P9_3, UART_2, CYHAL_PIN_IN_FUNCTION(P9_3_SCB2_UART_CTS)}, + {P10_3, UART_1, CYHAL_PIN_IN_FUNCTION(P10_3_SCB1_UART_CTS)}, + {P11_3, UART_5, CYHAL_PIN_IN_FUNCTION(P11_3_SCB5_UART_CTS)}, + {P12_3, UART_6, CYHAL_PIN_IN_FUNCTION(P12_3_SCB6_UART_CTS)}, + {P13_3, UART_6, CYHAL_PIN_IN_FUNCTION(P13_3_SCB6_UART_CTS)}, + {P13_7, UART_12, CYHAL_PIN_IN_FUNCTION(P13_7_SCB12_UART_CTS)}, + {NC, NC, 0} +}; +#endif // DEVICE_SERIAL + + +#if DEVICE_I2C +//*** I2C *** +const PinMap PinMap_I2C_SCL[] = { + {P0_2, I2C_0, CYHAL_PIN_OD_FUNCTION(P0_2_SCB0_I2C_SCL)}, + {P1_0, I2C_7, CYHAL_PIN_OD_FUNCTION(P1_0_SCB7_I2C_SCL)}, + {P2_0, I2C_1, CYHAL_PIN_OD_FUNCTION(P2_0_SCB1_I2C_SCL)}, + {P2_4, I2C_9, CYHAL_PIN_OD_FUNCTION(P2_4_SCB9_I2C_SCL)}, + {P5_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_0_SCB5_I2C_SCL)}, + {P5_4, I2C_10, CYHAL_PIN_OD_FUNCTION(P5_4_SCB10_I2C_SCL)}, + {P6_0, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_0_SCB3_I2C_SCL)}, + {P6_4, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_4_SCB6_I2C_SCL)}, + {P7_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_0_SCB4_I2C_SCL)}, + {P8_0, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_0_SCB4_I2C_SCL)}, + {P8_4, I2C_11, CYHAL_PIN_OD_FUNCTION(P8_4_SCB11_I2C_SCL)}, + {P9_0, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_0_SCB2_I2C_SCL)}, + {P10_0, I2C_1, CYHAL_PIN_OD_FUNCTION(P10_0_SCB1_I2C_SCL)}, + {P11_0, I2C_5, CYHAL_PIN_OD_FUNCTION(P11_0_SCB5_I2C_SCL)}, + {P12_0, I2C_6, CYHAL_PIN_OD_FUNCTION(P12_0_SCB6_I2C_SCL)}, + {P13_0, I2C_6, CYHAL_PIN_OD_FUNCTION(P13_0_SCB6_I2C_SCL)}, + {P13_4, I2C_12, CYHAL_PIN_OD_FUNCTION(P13_4_SCB12_I2C_SCL)}, + {NC, NC, 0} +}; +const PinMap PinMap_I2C_SDA[] = { + {P0_3, I2C_0, CYHAL_PIN_OD_FUNCTION(P0_3_SCB0_I2C_SDA)}, + {P1_1, I2C_7, CYHAL_PIN_OD_FUNCTION(P1_1_SCB7_I2C_SDA)}, + {P2_1, I2C_1, CYHAL_PIN_OD_FUNCTION(P2_1_SCB1_I2C_SDA)}, + {P2_5, I2C_9, CYHAL_PIN_OD_FUNCTION(P2_5_SCB9_I2C_SDA)}, + {P5_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P5_1_SCB5_I2C_SDA)}, + {P5_5, I2C_10, CYHAL_PIN_OD_FUNCTION(P5_5_SCB10_I2C_SDA)}, + {P6_1, I2C_3, CYHAL_PIN_OD_FUNCTION(P6_1_SCB3_I2C_SDA)}, + {P6_5, I2C_6, CYHAL_PIN_OD_FUNCTION(P6_5_SCB6_I2C_SDA)}, + {P7_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P7_1_SCB4_I2C_SDA)}, + {P8_1, I2C_4, CYHAL_PIN_OD_FUNCTION(P8_1_SCB4_I2C_SDA)}, + {P9_1, I2C_2, CYHAL_PIN_OD_FUNCTION(P9_1_SCB2_I2C_SDA)}, + {P10_1, I2C_1, CYHAL_PIN_OD_FUNCTION(P10_1_SCB1_I2C_SDA)}, + {P11_1, I2C_5, CYHAL_PIN_OD_FUNCTION(P11_1_SCB5_I2C_SDA)}, + {P12_1, I2C_6, CYHAL_PIN_OD_FUNCTION(P12_1_SCB6_I2C_SDA)}, + {P13_1, I2C_6, CYHAL_PIN_OD_FUNCTION(P13_1_SCB6_I2C_SDA)}, + {P13_5, I2C_12, CYHAL_PIN_OD_FUNCTION(P13_5_SCB12_I2C_SDA)}, + {NC, NC, 0} +}; +#endif // DEVICE_I2C + +#if DEVICE_SPI +//*** SPI *** +const PinMap PinMap_SPI_MOSI[] = { + {P0_2, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_2_SCB0_SPI_MOSI)}, + {P1_0, SPI_7, CYHAL_PIN_OUT_FUNCTION(P1_0_SCB7_SPI_MOSI)}, + {P2_0, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_0_SCB1_SPI_MOSI)}, + {P5_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_0_SCB5_SPI_MOSI)}, + {P6_0, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_0_SCB3_SPI_MOSI)}, + {P6_4, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_4_SCB6_SPI_MOSI)}, + {P7_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_0_SCB4_SPI_MOSI)}, + {P8_0, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_0_SCB4_SPI_MOSI)}, + {P9_0, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_0_SCB2_SPI_MOSI)}, + {P10_0, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_0_SCB1_SPI_MOSI)}, + {P11_0, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_0_SCB5_SPI_MOSI)}, + {P12_0, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_0_SCB6_SPI_MOSI)}, + {P13_0, SPI_6, CYHAL_PIN_OUT_FUNCTION(P13_0_SCB6_SPI_MOSI)}, + {NC, NC, 0} +}; +const PinMap PinMap_SPI_MISO[] = { + {P0_3, SPI_0, CYHAL_PIN_IN_FUNCTION(P0_3_SCB0_SPI_MISO)}, + {P1_1, SPI_7, CYHAL_PIN_IN_FUNCTION(P1_1_SCB7_SPI_MISO)}, + {P2_1, SPI_1, CYHAL_PIN_IN_FUNCTION(P2_1_SCB1_SPI_MISO)}, + {P5_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P5_1_SCB5_SPI_MISO)}, + {P6_1, SPI_3, CYHAL_PIN_IN_FUNCTION(P6_1_SCB3_SPI_MISO)}, + {P6_5, SPI_6, CYHAL_PIN_IN_FUNCTION(P6_5_SCB6_SPI_MISO)}, + {P7_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P7_1_SCB4_SPI_MISO)}, + {P8_1, SPI_4, CYHAL_PIN_IN_FUNCTION(P8_1_SCB4_SPI_MISO)}, + {P9_1, SPI_2, CYHAL_PIN_IN_FUNCTION(P9_1_SCB2_SPI_MISO)}, + {P10_1, SPI_1, CYHAL_PIN_IN_FUNCTION(P10_1_SCB1_SPI_MISO)}, + {P11_1, SPI_5, CYHAL_PIN_IN_FUNCTION(P11_1_SCB5_SPI_MISO)}, + {P12_1, SPI_6, CYHAL_PIN_IN_FUNCTION(P12_1_SCB6_SPI_MISO)}, + {P13_1, SPI_6, CYHAL_PIN_IN_FUNCTION(P13_1_SCB6_SPI_MISO)}, + {NC, NC, 0} +}; +const PinMap PinMap_SPI_SCLK[] = { + {P0_4, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_4_SCB0_SPI_CLK)}, + {P2_2, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_2_SCB1_SPI_CLK)}, + {P5_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_2_SCB5_SPI_CLK)}, + {P6_2, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_2_SCB3_SPI_CLK)}, + {P6_6, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_6_SCB6_SPI_CLK)}, + {P7_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_2_SCB4_SPI_CLK)}, + {P8_2, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_2_SCB4_SPI_CLK)}, + {P9_2, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_2_SCB2_SPI_CLK)}, + {P10_2, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_2_SCB1_SPI_CLK)}, + {P11_2, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_2_SCB5_SPI_CLK)}, + {P12_2, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_2_SCB6_SPI_CLK)}, + {P13_2, SPI_6, CYHAL_PIN_OUT_FUNCTION(P13_2_SCB6_SPI_CLK)}, + {NC, NC, 0} +}; +const PinMap PinMap_SPI_SSEL[] = { + {P0_5, SPI_0, CYHAL_PIN_OUT_FUNCTION(P0_5_SCB0_SPI_SELECT0)}, + {P2_3, SPI_1, CYHAL_PIN_OUT_FUNCTION(P2_3_SCB1_SPI_SELECT0)}, + {P5_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P5_3_SCB5_SPI_SELECT0)}, + {P6_3, SPI_3, CYHAL_PIN_OUT_FUNCTION(P6_3_SCB3_SPI_SELECT0)}, + {P6_7, SPI_6, CYHAL_PIN_OUT_FUNCTION(P6_7_SCB6_SPI_SELECT0)}, + {P7_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P7_3_SCB4_SPI_SELECT0)}, + {P8_3, SPI_4, CYHAL_PIN_OUT_FUNCTION(P8_3_SCB4_SPI_SELECT0)}, + {P9_3, SPI_2, CYHAL_PIN_OUT_FUNCTION(P9_3_SCB2_SPI_SELECT0)}, + {P10_3, SPI_1, CYHAL_PIN_OUT_FUNCTION(P10_3_SCB1_SPI_SELECT0)}, + {P11_3, SPI_5, CYHAL_PIN_OUT_FUNCTION(P11_3_SCB5_SPI_SELECT0)}, + {P12_3, SPI_6, CYHAL_PIN_OUT_FUNCTION(P12_3_SCB6_SPI_SELECT0)}, + {P13_3, SPI_6, CYHAL_PIN_OUT_FUNCTION(P13_3_SCB6_SPI_SELECT0)}, + {NC, NC, 0} +}; +#endif // DEVICE_SPI + +#if DEVICE_PWMOUT +//*** PWM *** +const PinMap PinMap_PWM_OUT[] = { + // 16-bit PWM outputs + {P0_0, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM1_LINE0)}, + {P0_2, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM1_LINE1)}, + {P0_4, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM1_LINE2)}, + {P1_0, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM1_LINE3)}, + {P1_4, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM1_LINE13)}, + {P2_0, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P2_0_TCPWM1_LINE15)}, + {P2_2, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P2_2_TCPWM1_LINE16)}, + {P2_4, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P2_4_TCPWM1_LINE17)}, + {P2_6, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P2_6_TCPWM1_LINE18)}, + {P5_0, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM1_LINE4)}, + {P5_2, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM1_LINE5)}, + {P5_4, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM1_LINE6)}, + {P5_6, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM1_LINE7)}, + {P6_0, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM1_LINE8)}, + {P6_2, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM1_LINE9)}, + {P6_4, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM1_LINE10)}, + {P6_6, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM1_LINE11)}, + {P7_0, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM1_LINE12)}, + {P7_2, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM1_LINE13)}, + {P8_0, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM1_LINE16)}, + {P8_2, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM1_LINE17)}, + {P8_4, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM1_LINE18)}, + {P9_0, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM1_LINE20)}, + {P9_2, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM1_LINE21)}, + {P9_4, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM1_LINE0)}, + {P10_0, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM1_LINE22)}, + {P10_2, PWM_16b_23, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM1_LINE23)}, + {P10_4, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM1_LINE0)}, + {P10_6, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM1_LINE2)}, + {P11_0, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM1_LINE1)}, + {P11_2, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM1_LINE2)}, + {P11_4, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM1_LINE3)}, + {P12_0, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM1_LINE4)}, + {P12_2, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM1_LINE5)}, + {P12_4, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM1_LINE6)}, + {P12_6, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM1_LINE7)}, + {P13_0, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM1_LINE8)}, + {P13_2, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P13_2_TCPWM1_LINE9)}, + {P13_4, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P13_4_TCPWM1_LINE10)}, + {P13_6, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P13_6_TCPWM1_LINE11)}, + // 16-bit PWM inverted outputs + {P0_1, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM1_LINE_COMPL0)}, + {P0_3, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM1_LINE_COMPL1)}, + {P0_5, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM1_LINE_COMPL2)}, + {P1_1, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM1_LINE_COMPL3)}, + {P1_5, PWM_16b_14, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM1_LINE_COMPL14)}, + {P2_1, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P2_1_TCPWM1_LINE_COMPL15)}, + {P2_3, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P2_3_TCPWM1_LINE_COMPL16)}, + {P2_5, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P2_5_TCPWM1_LINE_COMPL17)}, + {P2_7, PWM_16b_18, CYHAL_PIN_OUT_FUNCTION(P2_7_TCPWM1_LINE_COMPL18)}, + {P5_1, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM1_LINE_COMPL4)}, + {P5_3, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM1_LINE_COMPL5)}, + {P5_5, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM1_LINE_COMPL6)}, + {P5_7, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM1_LINE_COMPL7)}, + {P6_1, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM1_LINE_COMPL8)}, + {P6_3, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM1_LINE_COMPL9)}, + {P6_5, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM1_LINE_COMPL10)}, + {P6_7, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM1_LINE_COMPL11)}, + {P7_1, PWM_16b_12, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM1_LINE_COMPL12)}, + {P7_3, PWM_16b_13, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM1_LINE_COMPL13)}, + {P7_7, PWM_16b_15, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM1_LINE_COMPL15)}, + {P8_1, PWM_16b_16, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM1_LINE_COMPL16)}, + {P8_3, PWM_16b_17, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM1_LINE_COMPL17)}, + {P9_1, PWM_16b_20, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM1_LINE_COMPL20)}, + {P9_3, PWM_16b_21, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM1_LINE_COMPL21)}, + {P9_7, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM1_LINE_COMPL1)}, + {P10_1, PWM_16b_22, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM1_LINE_COMPL22)}, + {P10_3, PWM_16b_23, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM1_LINE_COMPL23)}, + {P10_5, PWM_16b_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM1_LINE_COMPL0)}, + {P10_7, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P10_7_TCPWM1_LINE_COMPL2)}, + {P11_1, PWM_16b_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM1_LINE_COMPL1)}, + {P11_3, PWM_16b_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM1_LINE_COMPL2)}, + {P11_5, PWM_16b_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM1_LINE_COMPL3)}, + {P12_1, PWM_16b_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM1_LINE_COMPL4)}, + {P12_3, PWM_16b_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM1_LINE_COMPL5)}, + {P12_5, PWM_16b_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM1_LINE_COMPL6)}, + {P12_7, PWM_16b_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM1_LINE_COMPL7)}, + {P13_1, PWM_16b_8, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM1_LINE_COMPL8)}, + {P13_3, PWM_16b_9, CYHAL_PIN_OUT_FUNCTION(P13_3_TCPWM1_LINE_COMPL9)}, + {P13_5, PWM_16b_10, CYHAL_PIN_OUT_FUNCTION(P13_5_TCPWM1_LINE_COMPL10)}, + {P13_7, PWM_16b_11, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM1_LINE_COMPL11)}, + // 32-bit PWM outputs + {P0_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P0_0_TCPWM0_LINE0)}, + {P0_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P0_2_TCPWM0_LINE1)}, + {P0_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P0_4_TCPWM0_LINE2)}, + {P1_0, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P1_0_TCPWM0_LINE3)}, + {P1_4, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P1_4_TCPWM0_LINE5)}, + {P2_0, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P2_0_TCPWM0_LINE6)}, + {P2_2, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P2_2_TCPWM0_LINE7)}, + {P2_4, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P2_4_TCPWM0_LINE0)}, + {P2_6, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P2_6_TCPWM0_LINE1)}, + {P5_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P5_0_TCPWM0_LINE4)}, + {P5_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P5_2_TCPWM0_LINE5)}, + {P5_4, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P5_4_TCPWM0_LINE6)}, + {P5_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P5_6_TCPWM0_LINE7)}, + {P6_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P6_0_TCPWM0_LINE0)}, + {P6_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P6_2_TCPWM0_LINE1)}, + {P6_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P6_4_TCPWM0_LINE2)}, + {P6_6, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P6_6_TCPWM0_LINE3)}, + {P7_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P7_0_TCPWM0_LINE4)}, + {P7_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P7_2_TCPWM0_LINE5)}, + {P8_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P8_0_TCPWM0_LINE0)}, + {P8_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P8_2_TCPWM0_LINE1)}, + {P8_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P8_4_TCPWM0_LINE2)}, + {P9_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P9_0_TCPWM0_LINE4)}, + {P9_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P9_2_TCPWM0_LINE5)}, + {P9_4, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P9_4_TCPWM0_LINE7)}, + {P10_0, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P10_0_TCPWM0_LINE6)}, + {P10_2, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P10_2_TCPWM0_LINE7)}, + {P10_4, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P10_4_TCPWM0_LINE0)}, + {P10_6, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P10_6_TCPWM0_LINE1)}, + {P11_0, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P11_0_TCPWM0_LINE1)}, + {P11_2, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P11_2_TCPWM0_LINE2)}, + {P11_4, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P11_4_TCPWM0_LINE3)}, + {P12_0, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P12_0_TCPWM0_LINE4)}, + {P12_2, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P12_2_TCPWM0_LINE5)}, + {P12_4, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P12_4_TCPWM0_LINE6)}, + {P12_6, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P12_6_TCPWM0_LINE7)}, + {P13_0, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P13_0_TCPWM0_LINE0)}, + {P13_2, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P13_2_TCPWM0_LINE1)}, + {P13_4, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P13_4_TCPWM0_LINE2)}, + {P13_6, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P13_6_TCPWM0_LINE3)}, + // 32-bit PWM inverted outputs + {P0_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P0_1_TCPWM0_LINE_COMPL0)}, + {P0_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P0_3_TCPWM0_LINE_COMPL1)}, + {P0_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P0_5_TCPWM0_LINE_COMPL2)}, + {P1_1, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P1_1_TCPWM0_LINE_COMPL3)}, + {P1_5, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P1_5_TCPWM0_LINE_COMPL5)}, + {P2_1, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P2_1_TCPWM0_LINE_COMPL6)}, + {P2_3, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P2_3_TCPWM0_LINE_COMPL7)}, + {P2_5, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P2_5_TCPWM0_LINE_COMPL0)}, + {P2_7, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P2_7_TCPWM0_LINE_COMPL1)}, + {P5_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P5_1_TCPWM0_LINE_COMPL4)}, + {P5_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P5_3_TCPWM0_LINE_COMPL5)}, + {P5_5, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P5_5_TCPWM0_LINE_COMPL6)}, + {P5_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P5_7_TCPWM0_LINE_COMPL7)}, + {P6_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P6_1_TCPWM0_LINE_COMPL0)}, + {P6_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P6_3_TCPWM0_LINE_COMPL1)}, + {P6_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P6_5_TCPWM0_LINE_COMPL2)}, + {P6_7, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P6_7_TCPWM0_LINE_COMPL3)}, + {P7_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P7_1_TCPWM0_LINE_COMPL4)}, + {P7_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P7_3_TCPWM0_LINE_COMPL5)}, + {P7_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P7_7_TCPWM0_LINE_COMPL7)}, + {P8_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P8_1_TCPWM0_LINE_COMPL0)}, + {P8_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P8_3_TCPWM0_LINE_COMPL1)}, + {P9_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P9_1_TCPWM0_LINE_COMPL4)}, + {P9_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P9_3_TCPWM0_LINE_COMPL5)}, + {P9_7, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P9_7_TCPWM0_LINE_COMPL0)}, + {P10_1, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P10_1_TCPWM0_LINE_COMPL6)}, + {P10_3, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P10_3_TCPWM0_LINE_COMPL7)}, + {P10_5, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P10_5_TCPWM0_LINE_COMPL0)}, + {P10_7, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P10_7_TCPWM0_LINE_COMPL1)}, + {P11_1, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P11_1_TCPWM0_LINE_COMPL1)}, + {P11_3, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P11_3_TCPWM0_LINE_COMPL2)}, + {P11_5, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P11_5_TCPWM0_LINE_COMPL3)}, + {P12_1, PWM_32b_4, CYHAL_PIN_OUT_FUNCTION(P12_1_TCPWM0_LINE_COMPL4)}, + {P12_3, PWM_32b_5, CYHAL_PIN_OUT_FUNCTION(P12_3_TCPWM0_LINE_COMPL5)}, + {P12_5, PWM_32b_6, CYHAL_PIN_OUT_FUNCTION(P12_5_TCPWM0_LINE_COMPL6)}, + {P12_7, PWM_32b_7, CYHAL_PIN_OUT_FUNCTION(P12_7_TCPWM0_LINE_COMPL7)}, + {P13_1, PWM_32b_0, CYHAL_PIN_OUT_FUNCTION(P13_1_TCPWM0_LINE_COMPL0)}, + {P13_3, PWM_32b_1, CYHAL_PIN_OUT_FUNCTION(P13_3_TCPWM0_LINE_COMPL1)}, + {P13_5, PWM_32b_2, CYHAL_PIN_OUT_FUNCTION(P13_5_TCPWM0_LINE_COMPL2)}, + {P13_7, PWM_32b_3, CYHAL_PIN_OUT_FUNCTION(P13_7_TCPWM0_LINE_COMPL3)}, + {NC, NC, 0} +}; +#endif // DEVICE_PWMOUT + +#if DEVICE_ANALOGIN +const PinMap PinMap_ADC[] = { + {P9_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_0 pin through the AMUXA bus + {P9_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_1 pin through the AMUXA bus + {P9_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_2 pin through the AMUXA bus + {P9_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input connects to the P9_4 pin through the AMUXA bus + {P10_0, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_0 pin + {P10_1, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_1 pin + {P10_2, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_2 pin + {P10_3, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_3 pin + {P10_4, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_4 pin + {P10_5, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_5 pin + {P10_6, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_6 pin + {P10_7, ADC_0, CYHAL_PIN_ANALOG_FUNCTION(HSIOM_SEL_GPIO)}, // The SAR ADC Vplus input has the direct connection to the P10_7 pin + {NC, NC, 0} +}; +#endif // DEVICE_ANALOGIN + +#if DEVICE_QSPI +const PinMap PinMap_QSPI_SCLK[] = { + {P11_7, QSPI_0, CY_GPIO_CFG_CREATE(P11_7_SMIF_SPI_CLK, CY_GPIO_DM_STRONG_IN_OFF)}, + {NC, NC, 0}, +}; +const PinMap PinMap_QSPI_SSEL[] = { + {P11_2, QSPI_0, CY_GPIO_CFG_CREATE(P11_2_SMIF_SPI_SELECT0, CY_GPIO_DM_STRONG_IN_OFF)}, + {NC, NC, 0}, +}; +const PinMap PinMap_QSPI_DATA0[] = { + {P11_6, QSPI_0, CY_GPIO_CFG_CREATE(P11_6_SMIF_SPI_DATA0, CY_GPIO_DM_STRONG)}, + {NC, NC, 0}, +}; +const PinMap PinMap_QSPI_DATA1[] = { + {P11_5, QSPI_0, CY_GPIO_CFG_CREATE(P11_5_SMIF_SPI_DATA1, CY_GPIO_DM_STRONG)}, + {NC, NC, 0}, +}; +const PinMap PinMap_QSPI_DATA2[] = { + {P11_4, QSPI_0, CY_GPIO_CFG_CREATE(P11_4_SMIF_SPI_DATA2, CY_GPIO_DM_STRONG)}, + {NC, NC, 0}, +}; +const PinMap PinMap_QSPI_DATA3[] = { + {P11_3, QSPI_0, CY_GPIO_CFG_CREATE(P11_3_SMIF_SPI_DATA3, CY_GPIO_DM_STRONG)}, + {NC, NC, 0}, +}; +#endif // DEVICE_QSPI diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.c new file mode 100644 index 00000000000..a935ed999be --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.c @@ -0,0 +1,115 @@ +/***************************************************************************//** +* \file cybsp.c +* +* Description: +* Provides initialization code for starting up the hardware contained on the +* Cypress board. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "cy_syspm.h" +#include "cy_sysclk.h" +#include "cybsp.h" +#if defined(CY_USING_HAL) +#include "cyhal_hwmgr.h" +#endif + +#if !defined (CY_CFG_PWR_SYS_IDLE_MODE) +#include "mbed_power_mgmt.h" +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +/* The sysclk deep sleep callback is recommended to be the last callback that +* is executed before entry into deep sleep mode and the first one upon +* exit the deep sleep mode. +* Doing so minimizes the time spent on low power mode entry and exit. +*/ +#ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER + #define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u) +#endif + +#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) +static cyhal_sdio_t sdio_obj; + +cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void) +{ + return &sdio_obj; +} +#endif + +/** + * Registers a power management callback that prepares the clock system + * for entering deep sleep mode and restore the clocks upon wakeup from deep sleep. + * NOTE: This is called automatically as part of \ref cybsp_init + */ +static cy_rslt_t cybsp_register_sysclk_pm_callback(void) +{ + cy_rslt_t result = CY_RSLT_SUCCESS; + static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL}; + static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = { + .callback = &Cy_SysClk_DeepSleepCallback, + .type = CY_SYSPM_DEEPSLEEP, + .callbackParams = &cybsp_sysclk_pm_callback_param, + .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER + }; + + if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback)) + { + result = CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK; + } + return result; +} + +cy_rslt_t cybsp_init(void) +{ + /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ +#if defined(CY_USING_HAL) + cy_rslt_t result = cyhal_hwmgr_init(); +#else + cy_rslt_t result = CY_RSLT_SUCCESS; +#endif + +#if defined(COMPONENT_BSP_DESIGN_MODUS) + init_cycfg_all(); +#endif + + if (CY_RSLT_SUCCESS == result) + { + result = cybsp_register_sysclk_pm_callback(); + } + +#if !defined(CY_CFG_PWR_SYS_IDLE_MODE) + /* Disable deep-sleep. */ + sleep_manager_lock_deep_sleep(); +#endif + + /* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by + * user previously. Please review the Device Configurator (design.modus) and the BSP reservation list + * (cyreservedresources.list) to make sure no resources are reserved by both. + */ + return result; +} + +#if defined(__cplusplus) +} +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.h new file mode 100644 index 00000000000..7d15280e71e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp.h @@ -0,0 +1,76 @@ +/***************************************************************************//** +* \file cybsp.h +* +* \brief +* Basic API for setting up boards containing a Cypress MCU. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#pragma once + +#include "cy_result.h" +#include "cybsp_types.h" +#if defined(COMPONENT_BSP_DESIGN_MODUS) +#include "cycfg.h" +#endif +#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) +#include "cyhal_sdio.h" +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +/** +* \addtogroup group_bsp_macros Macros +* \{ +*/ + +/** Failed to configure sysclk power management callback */ +#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0)) + +/** \} group_bsp_macros */ + +/** +* \addtogroup group_bsp_functions Functions +* \{ +*/ + +/** + * \brief Initialize all hardware on the board + * \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is + * a problem initializing any hardware it returns an error code specific + * to the hardware module that had a problem. + */ +cy_rslt_t cybsp_init(void); + +#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) +/** + * \brief Get the initialized sdio object used for communicating with the WiFi Chip. + * \note This function should only be called after cybsp_init(); + * \returns The initialized sdio object. + */ +cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void); +#endif /* defined(CYBSP_WIFI_CAPABLE) */ + +/** \} group_bsp_functions */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp_types.h new file mode 100644 index 00000000000..64ef452d659 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/cybsp_types.h @@ -0,0 +1,194 @@ +/***************************************************************************//** +* \file CYSBSYSKIT_01/cybsp_types.h +* +* Description: +* Provides APIs for interacting with the hardware contained on the Cypress +* CYSBSYSKIT_01 kit. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#pragma once + +#if defined(CY_USING_HAL) +#include "cyhal_pin_package.h" +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +#ifndef CY_CFG_SYSCLK_CLKLF_FREQ_HZ +#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ (32000U) +#endif + +/** +* \addtogroup group_bsp_settings BSP Settings +* \{ +* +*
Peripheral Default HAL Settings:
+* | Resource | Parameter | Value | Remarks | +* | :------: | :-------: | :---: | :------ | +* | ADC | VREF | 1.2 V | | +* | ^ | Measurement type | Single Ended | | +* | ^ | Input voltage range | 0 to 2.4 V (0 to 2*VREF) | | +* | ^ | Output range | 0x000 to 0x7FF | | +* | DAC | Reference source | VDDA | | +* | ^ | Input range | 0x000 to 0xFFF | | +* | ^ | Output range | 0 to VDDA | | +* | ^ | Output type | Unbuffered output | | +* | I2C | Role | Master | Configurable to slave mode through HAL function | +* | ^ | Data rate | 100 kbps | Configurable through HAL function | +* | ^ | Drive mode of SCL & SDA pins | Open Drain (drives low) | External pull-up resistors are required | +* | LpTimer | Uses WCO (32.768 kHz) as clock source & MCWDT as counter. 1 count = 1/32768 second or 32768 counts = 1 second. ||| +* | SPI | Data rate | 100 kpbs | Configurable through HAL function | +* | ^ | Slave select polarity | Active low | | +* | UART | Flow control | No flow control | Configurable through HAL function | +* | ^ | Data format | 8N1 | Configurable through HAL function | +* | ^ | Baud rate | 115200 | Configurable through HAL function | +*/ +/** \} group_bsp_settings */ + +/** +* \addtogroup group_bsp_pin_state Pin States +* \{ +*/ + +/** Pin state for the LED on. */ +#define CYBSP_LED_STATE_ON (0U) +/** Pin state for the LED off. */ +#define CYBSP_LED_STATE_OFF (1U) + +/** Pin state for when a button is pressed. */ +#define CYBSP_BTN_PRESSED (0U) +/** Pin state for when a button is released. */ +#define CYBSP_BTN_OFF (1U) + +/** \} group_bsp_pin_state */ + +#if defined(CY_USING_HAL) + +/** +* \addtogroup group_bsp_pins Pin Mappings +* \{ +*/ + +/** +* \addtogroup group_bsp_pins_led LED Pins +* \{ +*/ + +/** BSP user LED1 reference designator to pin mapping */ +#define CYBSP_USER_LED1 (P11_1) + +/** \} group_bsp_pins_led */ + +/** +* \addtogroup group_bsp_pins_btn Button Pins +* \{ +*/ + +/** BSP user button reference designator to pin mapping */ +#define CYBSP_USER_BTN (P0_4) + +/** \} group_bsp_pins_btn */ + +/** +* \addtogroup group_bsp_pins_comm Communication Pins +* \{ +*/ + +/** Pin: WIFI SDIO D0 */ +#define CYBSP_WIFI_SDIO_D0 (P2_0) +/** Pin: WIFI SDIO D1 */ +#define CYBSP_WIFI_SDIO_D1 (P2_1) +/** Pin: WIFI SDIO D2 */ +#define CYBSP_WIFI_SDIO_D2 (P2_2) +/** Pin: WIFI SDIO D3 */ +#define CYBSP_WIFI_SDIO_D3 (P2_3) +/** Pin: WIFI SDIO CMD */ +#define CYBSP_WIFI_SDIO_CMD (P2_4) +/** Pin: WIFI SDIO CLK */ +#define CYBSP_WIFI_SDIO_CLK (P2_5) +/** Pin: WIFI ON */ +#define CYBSP_WIFI_WL_REG_ON (P2_6) +/** Pin: WIFI Host Wakeup */ +#define CYBSP_WIFI_HOST_WAKE (P1_4) + +/** Host-wake GPIO drive mode */ +#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG) +/** Host-wake IRQ event */ +#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE) +/** Pin: BT UART RX */ +#define CYBSP_BT_UART_RX (P13_4) +/** Pin: BT UART TX */ +#define CYBSP_BT_UART_TX (P13_5) +/** Pin: BT UART RTS */ +#define CYBSP_BT_UART_RTS (P13_6) +/** Pin: BT UART CTS */ +#define CYBSP_BT_UART_CTS (P13_7) + +/** Pin: BT Power */ +#define CYBSP_BT_POWER (P12_0) +/** Pin: BT Host Wakeup */ +#define CYBSP_BT_HOST_WAKE (P12_3) +/** Pin: BT Device Wakeup */ +#define CYBSP_BT_DEVICE_WAKE (P12_2) + +/** Pin: UART RX */ +#define CYBSP_DEBUG_UART_RX (P5_4) +/** Pin: UART TX */ +#define CYBSP_DEBUG_UART_TX (P5_5) + +/** Pin: SWO */ +#define CYBSP_SWO (P6_4) +/** Pin: SWDIO */ +#define CYBSP_SWDIO (P6_6) +/** Pin: SWDCK */ +#define CYBSP_SWDCK (P6_7) + +/** Pin: QUAD SPI SS */ +#define CYBSP_QSPI_SS (P11_2) +/** Pin: QUAD SPI D3 */ +#define CYBSP_QSPI_D3 (P11_3) +/** Pin: QUAD SPI D2 */ +#define CYBSP_QSPI_D2 (P11_4) +/** Pin: QUAD SPI D1 */ +#define CYBSP_QSPI_D1 (P11_5) +/** Pin: QUAD SPI D0 */ +#define CYBSP_QSPI_D0 (P11_6) +/** Pin: QUAD SPI SCK */ +#define CYBSP_QSPI_SCK (P11_7) + +/** Pin: I2C SCL */ +#define CYBSP_I2C_SCL (P6_0) +/** Pin: I2C SDA */ +#define CYBSP_I2C_SDA (P6_1) + +/** \} group_bsp_pins_comm */ + +/** \} group_bsp_pins */ + + + + +#endif /* defined(CY_USING_HAL) */ + +#if defined(__cplusplus) +} +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct new file mode 100644 index 00000000000..ea1cfaefe9a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct @@ -0,0 +1,298 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************* +;* \file cy8c6xxa_cm4_dual.sct +;* \version 2.60 +;* +;* Linker file for the ARMCC. +;* +;* The main purpose of the linker script is to describe how the sections in the +;* input files should be mapped into the output file, and to control the memory +;* layout of the output file. +;* +;* \note The entry point location is fixed and starts at 0x10000000. The valid +;* application image should be placed there. +;* +;* \note The linker files included with the PDL template projects must be +;* generic and handle all common use cases. Your project may not use every +;* section defined in the linker files. In that case you may see the warnings +;* during the build process: L6314W (no section matches pattern) and/or L6329W +;* (pattern only matches removed unused sections). In your project, you can +;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +;* the linker, simply comment out or remove the relevant code in the linker +;* file. +;* +;******************************************************************************* +;* \copyright +;* Copyright 2016-2019 Cypress Semiconductor Corporation +;* SPDX-License-Identifier: Apache-2.0 +;* +;* Licensed under the Apache License, Version 2.0 (the "License"); +;* you may not use this file except in compliance with the License. +;* You may obtain a copy of the License at +;* +;* http://www.apache.org/licenses/LICENSE-2.0 +;* +;* Unless required by applicable law or agreed to in writing, software +;* distributed under the License is distributed on an "AS IS" BASIS, +;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;* See the License for the specific language governing permissions and +;* limitations under the License. +;******************************************************************************/ + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10180000 +#endif + +;* MBED_APP_START is being used by the bootloader build script and +;* will be calculate by the system. In case if MBED_APP_START address is +;* customized by the bootloader config, the application image should not +;* include CM0p prebuilt image. +;* + +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +;* MBED_APP_SIZE is being used by the bootloader build script and +;* will be calculate by the system. +;* +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE (MBED_ROM_SIZE) +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08080000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x7F800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +; Size of the stack section at the end of CM4 SRAM +#define STACK_SIZE MBED_BOOT_STACK_SIZE + +; The defines below describe the location and size of blocks of memory in the target. +; Use these defines to specify the memory regions available for allocation. + +; The following defines control RAM and flash memory allocation for the CM4 core. +; You can change the memory allocation by editing RAM and Flash defines. +; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. +; Using this memory region for other purposes will lead to unexpected behavior. +; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat', +; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'. +; RAM +#define RAM_START MBED_RAM_START +#define RAM_SIZE MBED_RAM_SIZE +; Flash +#define FLASH_START MBED_APP_START +#define FLASH_SIZE MBED_APP_SIZE + +; The following defines describe a 32K flash region used for EEPROM emulation. +; This region can also be used as the general purpose flash. +; You can assign sections to this memory region for only one of the cores. +; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. +; Therefore, repurposing this memory region will prevent such middleware from operation. +#define EM_EEPROM_START 0x14000000 +#define EM_EEPROM_SIZE 0x8000 + +; The following defines describe device specific memory regions and must not be changed. +; Supervisory flash: User data +#define SFLASH_USER_DATA_START 0x16000800 +#define SFLASH_USER_DATA_SIZE 0x00000800 + +; Supervisory flash: Normal Access Restrictions (NAR) +#define SFLASH_NAR_START 0x16001A00 +#define SFLASH_NAR_SIZE 0x00000200 + +; Supervisory flash: Public Key +#define SFLASH_PUBLIC_KEY_START 0x16005A00 +#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00 + +; Supervisory flash: Table of Content # 2 +#define SFLASH_TOC_2_START 0x16007C00 +#define SFLASH_TOC_2_SIZE 0x00000200 + +; Supervisory flash: Table of Content # 2 Copy +#define SFLASH_RTOC_2_START 0x16007E00 +#define SFLASH_RTOC_2_SIZE 0x00000200 + +; External memory +#define XIP_START 0x18000000 +#define XIP_SIZE 0x08000000 + +; eFuse +#define EFUSE_START 0x90700000 +#define EFUSE_SIZE 0x100000 + +; Cortex-M4 application flash area +LR_IROM1 FLASH_START FLASH_SIZE +{ + ER_FLASH_VECTORS +0 + { + * (RESET, +FIRST) + } + + ER_FLASH_CODE +0 FIXED + { + * (InRoot$$Sections) + * (+RO) + } + + ER_RAM_VECTORS RAM_START UNINIT + { + * (RESET_RAM, +FIRST) + } + + RW_RAM_DATA +0 + { + * (.cy_ramfunc) + * (+RW, +ZI) + } + + ; Place variables in the section that should not be initialized during the + ; device startup. + RW_IRAM1 +0 UNINIT + { + * (.noinit) + } + + ; Application heap area (HEAP) + ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) + { + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + { + } + + ; Used for the digital signature of the secure application and the + ; Bootloader SDK application. The size of the section depends on the required + ; data size. + .cy_app_signature (MBED_ROM_START + MBED_ROM_SIZE - 256) 256 + { + * (.cy_app_signature) + } +} + + +; Emulated EEPROM Flash area +LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE +{ + .cy_em_eeprom +0 + { + * (.cy_em_eeprom) + } +} + +; Supervisory flash: User data +LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE +{ + .cy_sflash_user_data +0 + { + * (.cy_sflash_user_data) + } +} + +; Supervisory flash: Normal Access Restrictions (NAR) +LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE +{ + .cy_sflash_nar +0 + { + * (.cy_sflash_nar) + } +} + +; Supervisory flash: Public Key +LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE +{ + .cy_sflash_public_key +0 + { + * (.cy_sflash_public_key) + } +} + +; Supervisory flash: Table of Content # 2 +LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE +{ + .cy_toc_part2 +0 + { + * (.cy_toc_part2) + } +} + +; Supervisory flash: Table of Content # 2 Copy +LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE +{ + .cy_rtoc_part2 +0 + { + * (.cy_rtoc_part2) + } +} + + +; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details. +LR_EROM XIP_START XIP_SIZE +{ + .cy_xip +0 + { + * (.cy_xip) + } +} + + +; eFuse +LR_EFUSE EFUSE_START EFUSE_SIZE +{ + .cy_efuse +0 + { + * (.cy_efuse) + } +} + + +; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +#define __cy_memory_0_start 0x10000000 +#define __cy_memory_0_length 0x00200000 +#define __cy_memory_0_row_size 0x200 + +/* Emulated EEPROM Flash area */ +#define __cy_memory_1_start 0x14000000 +#define __cy_memory_1_length 0x8000 +#define __cy_memory_1_row_size 0x200 + +/* Supervisory Flash */ +#define __cy_memory_2_start 0x16000000 +#define __cy_memory_2_length 0x8000 +#define __cy_memory_2_row_size 0x200 + +/* XIP */ +#define __cy_memory_3_start 0x18000000 +#define __cy_memory_3_length 0x08000000 +#define __cy_memory_3_row_size 0x200 + +/* eFuse */ +#define __cy_memory_4_start 0x90700000 +#define __cy_memory_4_length 0x100000 +#define __cy_memory_4_row_size 1 + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S new file mode 100644 index 00000000000..88eb1f471d6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_ARM/startup_psoc6_02_cm4.S @@ -0,0 +1,703 @@ +;/**************************************************************************//** +; * @file startup_psoc6_02_cm4.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 02. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD 0x0000000D ; NMI Handler located at ROM code + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD scb_9_interrupt_IRQHandler ; Serial Communication Block #9 + DCD scb_10_interrupt_IRQHandler ; Serial Communication Block #10 + DCD scb_11_interrupt_IRQHandler ; Serial Communication Block #11 + DCD scb_12_interrupt_IRQHandler ; Serial Communication Block #12 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0 + DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1 + DCD cpuss_interrupts_dmac_2_IRQHandler ; CPUSS DMAC, Channel #2 + DCD cpuss_interrupts_dmac_3_IRQHandler ; CPUSS DMAC, Channel #3 + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16 + DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17 + DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18 + DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19 + DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20 + DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21 + DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22 + DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23 + DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24 + DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25 + DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26 + DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27 + DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16 + DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17 + DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18 + DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19 + DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20 + DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21 + DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22 + DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23 + DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24 + DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25 + DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26 + DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27 + DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_0_interrupt_i2s_IRQHandler ; I2S0 Audio interrupt + DCD audioss_0_interrupt_pdm_IRQHandler ; PDM0/PCM0 Audio interrupt + DCD audioss_1_interrupt_i2s_IRQHandler ; I2S1 Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD sdhc_0_interrupt_wakeup_IRQHandler ; SDIO wakeup interrupt for mxsdhc + DCD sdhc_0_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else + DCD sdhc_1_interrupt_wakeup_IRQHandler ; EEMC wakeup interrupt for mxsdhc, not used + DCD sdhc_1_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + EXPORT __ramVectors + AREA RESET_RAM, READWRITE, NOINIT +__ramVectors SPACE __Vectors_Size + + + AREA |.text|, CODE, READONLY + + +; Weak function for startup customization +; +; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +; because this function is executed as the first instruction in the ResetHandler. +; The PDL is also not initialized to use the proper register offsets. +; The user of this function is responsible for initializing the PDL and resources before using them. +; +Cy_OnResetUser PROC + EXPORT Cy_OnResetUser [WEAK] + BX LR + ENDP + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT Cy_SystemInitFpuEnable + IMPORT __main + + ; Define strong function for startup customization + BL Cy_OnResetUser + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__Vectors + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +Vectors_Copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE Vectors_Copy + + ; Update Vector Table Offset Register. */ + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb 0xF + + ; Enable the FPU if used + LDR R0, =Cy_SystemInitFpuEnable + BLX R0 + + LDR R0, =__main + BLX R0 + + ; Should never get here + B . + + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +Cy_SysLib_FaultHandler PROC + EXPORT Cy_SysLib_FaultHandler [WEAK] + B . + ENDP +HardFault_Wrapper\ + PROC + EXPORT HardFault_Wrapper [WEAK] + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + bl L_API_call +L_MSP + mrs r0, MSP +L_API_call + bl Cy_SysLib_FaultHandler + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B HardFault_Wrapper + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B HardFault_Wrapper + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT Default_Handler [WEAK] + EXPORT ioss_interrupts_gpio_0_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_1_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_2_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_3_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_4_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_5_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_6_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_7_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_8_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_9_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_10_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_11_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_12_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_13_IRQHandler [WEAK] + EXPORT ioss_interrupts_gpio_14_IRQHandler [WEAK] + EXPORT ioss_interrupt_gpio_IRQHandler [WEAK] + EXPORT ioss_interrupt_vdd_IRQHandler [WEAK] + EXPORT lpcomp_interrupt_IRQHandler [WEAK] + EXPORT scb_8_interrupt_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_0_IRQHandler [WEAK] + EXPORT srss_interrupt_mcwdt_1_IRQHandler [WEAK] + EXPORT srss_interrupt_backup_IRQHandler [WEAK] + EXPORT srss_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_ipc_15_IRQHandler [WEAK] + EXPORT scb_0_interrupt_IRQHandler [WEAK] + EXPORT scb_1_interrupt_IRQHandler [WEAK] + EXPORT scb_2_interrupt_IRQHandler [WEAK] + EXPORT scb_3_interrupt_IRQHandler [WEAK] + EXPORT scb_4_interrupt_IRQHandler [WEAK] + EXPORT scb_5_interrupt_IRQHandler [WEAK] + EXPORT scb_6_interrupt_IRQHandler [WEAK] + EXPORT scb_7_interrupt_IRQHandler [WEAK] + EXPORT scb_9_interrupt_IRQHandler [WEAK] + EXPORT scb_10_interrupt_IRQHandler [WEAK] + EXPORT scb_11_interrupt_IRQHandler [WEAK] + EXPORT scb_12_interrupt_IRQHandler [WEAK] + EXPORT csd_interrupt_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dmac_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_16_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_17_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_18_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_19_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_20_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_21_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_22_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_23_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_24_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_25_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_26_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_27_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw0_28_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_2_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_3_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_4_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_5_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_6_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_7_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_8_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_9_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_10_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_11_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_12_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_13_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_14_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_15_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_16_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_17_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_18_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_19_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_20_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_21_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_22_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_23_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_24_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_25_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_26_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_27_IRQHandler [WEAK] + EXPORT cpuss_interrupts_dw1_28_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_fault_1_IRQHandler [WEAK] + EXPORT cpuss_interrupt_crypto_IRQHandler [WEAK] + EXPORT cpuss_interrupt_fm_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_fp_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm0_cti_1_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_0_IRQHandler [WEAK] + EXPORT cpuss_interrupts_cm4_cti_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_0_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_0_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_1_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_2_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_3_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_4_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_5_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_6_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_7_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_8_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_9_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_10_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_11_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_12_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_13_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_14_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_15_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_16_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_17_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_18_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_19_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_20_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_21_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_22_IRQHandler [WEAK] + EXPORT tcpwm_1_interrupts_23_IRQHandler [WEAK] + EXPORT pass_interrupt_sar_IRQHandler [WEAK] + EXPORT audioss_0_interrupt_i2s_IRQHandler [WEAK] + EXPORT audioss_0_interrupt_pdm_IRQHandler [WEAK] + EXPORT audioss_1_interrupt_i2s_IRQHandler [WEAK] + EXPORT profile_interrupt_IRQHandler [WEAK] + EXPORT smif_interrupt_IRQHandler [WEAK] + EXPORT usb_interrupt_hi_IRQHandler [WEAK] + EXPORT usb_interrupt_med_IRQHandler [WEAK] + EXPORT usb_interrupt_lo_IRQHandler [WEAK] + EXPORT sdhc_0_interrupt_wakeup_IRQHandler [WEAK] + EXPORT sdhc_0_interrupt_general_IRQHandler [WEAK] + EXPORT sdhc_1_interrupt_wakeup_IRQHandler [WEAK] + EXPORT sdhc_1_interrupt_general_IRQHandler [WEAK] + +ioss_interrupts_gpio_0_IRQHandler +ioss_interrupts_gpio_1_IRQHandler +ioss_interrupts_gpio_2_IRQHandler +ioss_interrupts_gpio_3_IRQHandler +ioss_interrupts_gpio_4_IRQHandler +ioss_interrupts_gpio_5_IRQHandler +ioss_interrupts_gpio_6_IRQHandler +ioss_interrupts_gpio_7_IRQHandler +ioss_interrupts_gpio_8_IRQHandler +ioss_interrupts_gpio_9_IRQHandler +ioss_interrupts_gpio_10_IRQHandler +ioss_interrupts_gpio_11_IRQHandler +ioss_interrupts_gpio_12_IRQHandler +ioss_interrupts_gpio_13_IRQHandler +ioss_interrupts_gpio_14_IRQHandler +ioss_interrupt_gpio_IRQHandler +ioss_interrupt_vdd_IRQHandler +lpcomp_interrupt_IRQHandler +scb_8_interrupt_IRQHandler +srss_interrupt_mcwdt_0_IRQHandler +srss_interrupt_mcwdt_1_IRQHandler +srss_interrupt_backup_IRQHandler +srss_interrupt_IRQHandler +cpuss_interrupts_ipc_0_IRQHandler +cpuss_interrupts_ipc_1_IRQHandler +cpuss_interrupts_ipc_2_IRQHandler +cpuss_interrupts_ipc_3_IRQHandler +cpuss_interrupts_ipc_4_IRQHandler +cpuss_interrupts_ipc_5_IRQHandler +cpuss_interrupts_ipc_6_IRQHandler +cpuss_interrupts_ipc_7_IRQHandler +cpuss_interrupts_ipc_8_IRQHandler +cpuss_interrupts_ipc_9_IRQHandler +cpuss_interrupts_ipc_10_IRQHandler +cpuss_interrupts_ipc_11_IRQHandler +cpuss_interrupts_ipc_12_IRQHandler +cpuss_interrupts_ipc_13_IRQHandler +cpuss_interrupts_ipc_14_IRQHandler +cpuss_interrupts_ipc_15_IRQHandler +scb_0_interrupt_IRQHandler +scb_1_interrupt_IRQHandler +scb_2_interrupt_IRQHandler +scb_3_interrupt_IRQHandler +scb_4_interrupt_IRQHandler +scb_5_interrupt_IRQHandler +scb_6_interrupt_IRQHandler +scb_7_interrupt_IRQHandler +scb_9_interrupt_IRQHandler +scb_10_interrupt_IRQHandler +scb_11_interrupt_IRQHandler +scb_12_interrupt_IRQHandler +csd_interrupt_IRQHandler +cpuss_interrupts_dmac_0_IRQHandler +cpuss_interrupts_dmac_1_IRQHandler +cpuss_interrupts_dmac_2_IRQHandler +cpuss_interrupts_dmac_3_IRQHandler +cpuss_interrupts_dw0_0_IRQHandler +cpuss_interrupts_dw0_1_IRQHandler +cpuss_interrupts_dw0_2_IRQHandler +cpuss_interrupts_dw0_3_IRQHandler +cpuss_interrupts_dw0_4_IRQHandler +cpuss_interrupts_dw0_5_IRQHandler +cpuss_interrupts_dw0_6_IRQHandler +cpuss_interrupts_dw0_7_IRQHandler +cpuss_interrupts_dw0_8_IRQHandler +cpuss_interrupts_dw0_9_IRQHandler +cpuss_interrupts_dw0_10_IRQHandler +cpuss_interrupts_dw0_11_IRQHandler +cpuss_interrupts_dw0_12_IRQHandler +cpuss_interrupts_dw0_13_IRQHandler +cpuss_interrupts_dw0_14_IRQHandler +cpuss_interrupts_dw0_15_IRQHandler +cpuss_interrupts_dw0_16_IRQHandler +cpuss_interrupts_dw0_17_IRQHandler +cpuss_interrupts_dw0_18_IRQHandler +cpuss_interrupts_dw0_19_IRQHandler +cpuss_interrupts_dw0_20_IRQHandler +cpuss_interrupts_dw0_21_IRQHandler +cpuss_interrupts_dw0_22_IRQHandler +cpuss_interrupts_dw0_23_IRQHandler +cpuss_interrupts_dw0_24_IRQHandler +cpuss_interrupts_dw0_25_IRQHandler +cpuss_interrupts_dw0_26_IRQHandler +cpuss_interrupts_dw0_27_IRQHandler +cpuss_interrupts_dw0_28_IRQHandler +cpuss_interrupts_dw1_0_IRQHandler +cpuss_interrupts_dw1_1_IRQHandler +cpuss_interrupts_dw1_2_IRQHandler +cpuss_interrupts_dw1_3_IRQHandler +cpuss_interrupts_dw1_4_IRQHandler +cpuss_interrupts_dw1_5_IRQHandler +cpuss_interrupts_dw1_6_IRQHandler +cpuss_interrupts_dw1_7_IRQHandler +cpuss_interrupts_dw1_8_IRQHandler +cpuss_interrupts_dw1_9_IRQHandler +cpuss_interrupts_dw1_10_IRQHandler +cpuss_interrupts_dw1_11_IRQHandler +cpuss_interrupts_dw1_12_IRQHandler +cpuss_interrupts_dw1_13_IRQHandler +cpuss_interrupts_dw1_14_IRQHandler +cpuss_interrupts_dw1_15_IRQHandler +cpuss_interrupts_dw1_16_IRQHandler +cpuss_interrupts_dw1_17_IRQHandler +cpuss_interrupts_dw1_18_IRQHandler +cpuss_interrupts_dw1_19_IRQHandler +cpuss_interrupts_dw1_20_IRQHandler +cpuss_interrupts_dw1_21_IRQHandler +cpuss_interrupts_dw1_22_IRQHandler +cpuss_interrupts_dw1_23_IRQHandler +cpuss_interrupts_dw1_24_IRQHandler +cpuss_interrupts_dw1_25_IRQHandler +cpuss_interrupts_dw1_26_IRQHandler +cpuss_interrupts_dw1_27_IRQHandler +cpuss_interrupts_dw1_28_IRQHandler +cpuss_interrupts_fault_0_IRQHandler +cpuss_interrupts_fault_1_IRQHandler +cpuss_interrupt_crypto_IRQHandler +cpuss_interrupt_fm_IRQHandler +cpuss_interrupts_cm4_fp_IRQHandler +cpuss_interrupts_cm0_cti_0_IRQHandler +cpuss_interrupts_cm0_cti_1_IRQHandler +cpuss_interrupts_cm4_cti_0_IRQHandler +cpuss_interrupts_cm4_cti_1_IRQHandler +tcpwm_0_interrupts_0_IRQHandler +tcpwm_0_interrupts_1_IRQHandler +tcpwm_0_interrupts_2_IRQHandler +tcpwm_0_interrupts_3_IRQHandler +tcpwm_0_interrupts_4_IRQHandler +tcpwm_0_interrupts_5_IRQHandler +tcpwm_0_interrupts_6_IRQHandler +tcpwm_0_interrupts_7_IRQHandler +tcpwm_1_interrupts_0_IRQHandler +tcpwm_1_interrupts_1_IRQHandler +tcpwm_1_interrupts_2_IRQHandler +tcpwm_1_interrupts_3_IRQHandler +tcpwm_1_interrupts_4_IRQHandler +tcpwm_1_interrupts_5_IRQHandler +tcpwm_1_interrupts_6_IRQHandler +tcpwm_1_interrupts_7_IRQHandler +tcpwm_1_interrupts_8_IRQHandler +tcpwm_1_interrupts_9_IRQHandler +tcpwm_1_interrupts_10_IRQHandler +tcpwm_1_interrupts_11_IRQHandler +tcpwm_1_interrupts_12_IRQHandler +tcpwm_1_interrupts_13_IRQHandler +tcpwm_1_interrupts_14_IRQHandler +tcpwm_1_interrupts_15_IRQHandler +tcpwm_1_interrupts_16_IRQHandler +tcpwm_1_interrupts_17_IRQHandler +tcpwm_1_interrupts_18_IRQHandler +tcpwm_1_interrupts_19_IRQHandler +tcpwm_1_interrupts_20_IRQHandler +tcpwm_1_interrupts_21_IRQHandler +tcpwm_1_interrupts_22_IRQHandler +tcpwm_1_interrupts_23_IRQHandler +pass_interrupt_sar_IRQHandler +audioss_0_interrupt_i2s_IRQHandler +audioss_0_interrupt_pdm_IRQHandler +audioss_1_interrupt_i2s_IRQHandler +profile_interrupt_IRQHandler +smif_interrupt_IRQHandler +usb_interrupt_hi_IRQHandler +usb_interrupt_med_IRQHandler +usb_interrupt_lo_IRQHandler +sdhc_0_interrupt_wakeup_IRQHandler +sdhc_0_interrupt_general_IRQHandler +sdhc_1_interrupt_wakeup_IRQHandler +sdhc_1_interrupt_general_IRQHandler + + B . + ENDP + + ALIGN + + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld new file mode 100644 index 00000000000..8f5a345f18f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld @@ -0,0 +1,448 @@ +/***************************************************************************//** +* \file cy8c6xxa_cm4_dual.ld +* \version 2.60 +* +* Linker file for the GNU C compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point location is fixed and starts at 0x10000000. The valid +* application image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) +ENTRY(Reset_Handler) + +#if !defined(MBED_ROM_START) + #define MBED_ROM_START 0x10180000 +#endif + +/* MBED_APP_START is being used by the bootloader build script and +* will be calculate by the system. In case if MBED_APP_START address is +* customized by the bootloader config, the application image should not +* include CM0p prebuilt image. +*/ +#if !defined(MBED_APP_START) + #define MBED_APP_START (MBED_ROM_START) +#endif + +#if !defined(MBED_ROM_SIZE) + #define MBED_ROM_SIZE 0x80000 +#endif + +/* MBED_APP_SIZE is being used by the bootloader build script and +* will be calculate by the system. +*/ +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE MBED_ROM_SIZE +#endif + +#if !defined(MBED_RAM_START) + #define MBED_RAM_START 0x08080000 +#endif + +#if !defined(MBED_RAM_SIZE) + #define MBED_RAM_SIZE 0x7F800 +#endif + +#if !defined(MBED_BOOT_STACK_SIZE) + #define MBED_BOOT_STACK_SIZE 0x400 +#endif + +/* Size of the stack section at the end of CM4 SRAM */ +STACK_SIZE = MBED_BOOT_STACK_SIZE; + +/* Force symbol to be entered in the output file as an undefined symbol. Doing +* this may, for example, trigger linking of additional modules from standard +* libraries. You may list several symbols for each EXTERN, and you may use +* EXTERN multiple times. This command has the same effect as the -u command-line +* option. +*/ +EXTERN(Reset_Handler) + +/* The MEMORY section below describes the location and size of blocks of memory in the target. +* Use this section to specify the memory regions available for allocation. +*/ +MEMORY +{ + /* The ram and flash regions control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing the 'ram' and 'flash' regions. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding memory regions for CM0+ core in 'xx_cm0plus.ld', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.ld'. + */ + ram (rwx) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE + flash (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE + + /* This is a 32K flash region used for EEPROM emulation. This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ + em_eeprom (rx) : ORIGIN = 0x14000000, LENGTH = 0x8000 /* 32 KB */ + + /* The following regions define device specific memory regions and must not be changed. */ + sflash_user_data (rx) : ORIGIN = 0x16000800, LENGTH = 0x800 /* Supervisory flash: User data */ + sflash_nar (rx) : ORIGIN = 0x16001A00, LENGTH = 0x200 /* Supervisory flash: Normal Access Restrictions (NAR) */ + sflash_public_key (rx) : ORIGIN = 0x16005A00, LENGTH = 0xC00 /* Supervisory flash: Public Key */ + sflash_toc_2 (rx) : ORIGIN = 0x16007C00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 */ + sflash_rtoc_2 (rx) : ORIGIN = 0x16007E00, LENGTH = 0x200 /* Supervisory flash: Table of Content # 2 Copy */ + xip (rx) : ORIGIN = 0x18000000, LENGTH = 0x8000000 /* 128 MB */ + efuse (r) : ORIGIN = 0x90700000, LENGTH = 0x100000 /* 1 MB */ +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ + + +SECTIONS +{ + /* Cortex-M4 application flash area */ + .text ORIGIN(flash) : + { + . = ALIGN(4); + __Vectors = . ; + KEEP(*(.vectors)) + . = ALIGN(4); + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + . = ALIGN(4); + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* Read-only code (constants). */ + *(.rodata .rodata.* .constdata .constdata.* .conststring .conststring.*) + + KEEP(*(.eh_frame*)) + } > flash + + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + __exidx_start = .; + + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_psoc6_02_cm4.S */ + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + + /* Copy interrupt vectors from flash to RAM */ + LONG (__Vectors) /* From */ + LONG (__ram_vectors_start__) /* To */ + LONG (__Vectors_End - __Vectors) /* Size */ + + /* Copy data section to RAM */ + LONG (__etext) /* From */ + LONG (__data_start__) /* To */ + LONG (__data_end__ - __data_start__) /* Size */ + + __copy_table_end__ = .; + } > flash + + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_psoc6_02_cm4.S */ + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + __zero_table_end__ = .; + } > flash + + __etext = . ; + + + .ramVectors (NOLOAD) : ALIGN(8) + { + __ram_vectors_start__ = .; + KEEP(*(.ram_vectors)) + __ram_vectors_end__ = .; + } > ram + + + .data __ram_vectors_end__ : AT (__etext) + { + __data_start__ = .; + + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + KEEP(*(.cy_ramfunc*)) + . = ALIGN(4); + + __data_end__ = .; + + } > ram + + + /* Place variables in the section that should not be initialized during the + * device startup. + */ + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } > ram + + + /* The uninitialized global or static variables are placed in this section. + * + * The NOLOAD attribute tells linker that .bss section does not consume + * any space in the image. The NOLOAD attribute changes the .bss type to + * NOBITS, and that makes linker to A) not allocate section in memory, and + * A) put information to clear the section with all zeros during application + * loading. + * + * Without the NOLOAD attribute, the .bss section might get PROGBITS type. + * This makes linker to A) allocate zeroed section in memory, and B) copy + * this section to RAM during application loading. + */ + .bss (NOLOAD): + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > ram + + + .heap (NOLOAD): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + __HeapLimit = .; + } > ram + + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(ram) + LENGTH(ram); + __StackLimit = __StackTop - STACK_SIZE; + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + + + /* Used for the digital signature of the secure application and the Bootloader SDK application. + * The size of the section depends on the required data size. */ + .cy_app_signature ORIGIN(flash) + LENGTH(flash) - 256 : + { + KEEP(*(.cy_app_signature)) + } > flash + + + /* Emulated EEPROM Flash area */ + .cy_em_eeprom : + { + KEEP(*(.cy_em_eeprom)) + } > em_eeprom + + + /* Supervisory Flash: User data */ + .cy_sflash_user_data : + { + KEEP(*(.cy_sflash_user_data)) + } > sflash_user_data + + + /* Supervisory Flash: Normal Access Restrictions (NAR) */ + .cy_sflash_nar : + { + KEEP(*(.cy_sflash_nar)) + } > sflash_nar + + + /* Supervisory Flash: Public Key */ + .cy_sflash_public_key : + { + KEEP(*(.cy_sflash_public_key)) + } > sflash_public_key + + + /* Supervisory Flash: Table of Content # 2 */ + .cy_toc_part2 : + { + KEEP(*(.cy_toc_part2)) + } > sflash_toc_2 + + + /* Supervisory Flash: Table of Content # 2 Copy */ + .cy_rtoc_part2 : + { + KEEP(*(.cy_rtoc_part2)) + } > sflash_rtoc_2 + + + /* Places the code in the Execute in Place (XIP) section. See the smif driver + * documentation for details. + */ + .cy_xip : + { + KEEP(*(.cy_xip)) + } > xip + + + /* eFuse */ + .cy_efuse : + { + KEEP(*(.cy_efuse)) + } > efuse + + + /* These sections are used for additional metadata (silicon revision, + * Silicon/JTAG ID, etc.) storage. + */ + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE +} + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +__cy_memory_0_start = 0x10000000; +__cy_memory_0_length = 0x00200000; +__cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +__cy_memory_1_start = 0x14000000; +__cy_memory_1_length = 0x8000; +__cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +__cy_memory_2_start = 0x16000000; +__cy_memory_2_length = 0x8000; +__cy_memory_2_row_size = 0x200; + +/* XIP */ +__cy_memory_3_start = 0x18000000; +__cy_memory_3_length = 0x08000000; +__cy_memory_3_row_size = 0x200; + +/* eFuse */ +__cy_memory_4_start = 0x90700000; +__cy_memory_4_length = 0x100000; +__cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S new file mode 100644 index 00000000000..1ebcac39f8f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/startup_psoc6_02_cm4.S @@ -0,0 +1,673 @@ +/**************************************************************************//** + * @file startup_psoc6_02_cm4.S + * @brief CMSIS Core Device Startup File for + * ARMCM4 Device Series + * @version V5.00 + * @date 02. March 2016 + ******************************************************************************/ +/* + * Copyright (c) 2009-2016 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + /* Address of the NMI handler */ + #define CY_NMI_HANLDER_ADDR 0x0000000D + + /* The CPU VTOR register */ + #define CY_CPU_VTOR_ADDR 0xE000ED08 + + /* Copy flash vectors and data section to RAM */ + #define __STARTUP_COPY_MULTIPLE + + /* Clear single BSS section */ + #define __STARTUP_CLEAR_BSS + + .syntax unified + .arch armv7-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + .equ Heap_Size, 0x00000400 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + .section .vectors + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long CY_NMI_HANLDER_ADDR /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External interrupts Description */ + .long ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + .long ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + .long ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + .long ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + .long ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + .long ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + .long ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + .long ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + .long ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + .long ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + .long ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + .long ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + .long ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + .long ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + .long ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + .long ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + .long ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + .long lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + .long scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + .long srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + .long srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + .long srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + .long cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + .long cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + .long cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + .long cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + .long cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + .long cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + .long cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + .long cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + .long cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + .long cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + .long cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + .long cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + .long cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + .long cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + .long cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + .long cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + .long scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + .long scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + .long scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + .long scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + .long scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + .long scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + .long scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + .long scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + .long scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */ + .long scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */ + .long scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */ + .long scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */ + .long csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + .long cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + .long cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + .long cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */ + .long cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */ + .long cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + .long cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + .long cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + .long cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + .long cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + .long cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + .long cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + .long cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + .long cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + .long cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + .long cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + .long cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + .long cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + .long cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + .long cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + .long cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + .long cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + .long cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + .long cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + .long cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + .long cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + .long cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + .long cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + .long cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + .long cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + .long cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + .long cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + .long cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + .long cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + .long cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + .long cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + .long cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + .long cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + .long cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + .long cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + .long cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + .long cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + .long cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + .long cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + .long cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + .long cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + .long cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + .long cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + .long cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + .long cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + .long cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + .long cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + .long cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + .long cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + .long cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + .long cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + .long cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + .long cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + .long cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + .long cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + .long cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + .long cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + .long cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + .long cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + .long cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + .long cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + .long cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + .long cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + .long cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + .long cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + .long cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + .long cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + .long tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + .long tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + .long tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + .long tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + .long tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + .long tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + .long tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + .long tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + .long tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + .long tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + .long tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + .long tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + .long tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + .long tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + .long tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + .long tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + .long tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + .long tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + .long tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + .long tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + .long tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + .long tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + .long tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + .long tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + .long tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + .long tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + .long tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + .long tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + .long tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + .long tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + .long tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + .long tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + .long pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + .long audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */ + .long audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */ + .long audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */ + .long profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + .long smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + .long usb_interrupt_hi_IRQHandler /* USB Interrupt */ + .long usb_interrupt_med_IRQHandler /* USB Interrupt */ + .long usb_interrupt_lo_IRQHandler /* USB Interrupt */ + .long sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ + .long sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + .long sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */ + .long sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + + + .size __Vectors, . - __Vectors + .equ __VectorsSize, . - __Vectors + + .section .ram_vectors + .align 2 + .globl __ramVectors +__ramVectors: + .space __VectorsSize + .size __ramVectors, . - __ramVectors + + + .text + .thumb + .thumb_func + .align 2 + + /* + * Device startup customization + * + * Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) + * because this function is executed as the first instruction in the ResetHandler. + * The PDL is also not initialized to use the proper register offsets. + * The user of this function is responsible for initializing the PDL and resources before using them. + */ + .weak Cy_OnResetUser + .func Cy_OnResetUser, Cy_OnResetUser + .type Cy_OnResetUser, %function + +Cy_OnResetUser: + bx lr + .size Cy_OnResetUser, . - Cy_OnResetUser + .endfunc + + /* Reset handler */ + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: + bl Cy_OnResetUser + cpsid i + +/* Firstly it copies data from read only memory to RAM. There are two schemes + * to copy. One can copy more than one sections. Another can only copy + * one section. The former scheme needs more instructions and read-only + * data to implement than the latter. + * Macro __STARTUP_COPY_MULTIPLE is used to choose between two schemes. */ + +#ifdef __STARTUP_COPY_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of triplets, each of which specify: + * offset 0: LMA of start of a section to copy from + * offset 4: VMA of start of a section to copy to + * offset 8: size of the section to copy. Must be multiply of 4 + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r4, =__copy_table_start__ + ldr r5, =__copy_table_end__ + +.L_loop0: + cmp r4, r5 + bge .L_loop0_done + ldr r1, [r4] + ldr r2, [r4, #4] + ldr r3, [r4, #8] + +.L_loop0_0: + subs r3, #4 + ittt ge + ldrge r0, [r1, r3] + strge r0, [r2, r3] + bge .L_loop0_0 + + adds r4, #12 + b .L_loop0 + +.L_loop0_done: +#else +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +.L_loop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .L_loop1 +#endif /*__STARTUP_COPY_MULTIPLE */ + +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * There are two schemes too. One can clear multiple BSS sections. Another + * can only clear one section. The former is more size expensive than the + * latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +#ifdef __STARTUP_CLEAR_BSS_MULTIPLE +/* Multiple sections scheme. + * + * Between symbol address __copy_table_start__ and __copy_table_end__, + * there are array of tuples specifying: + * offset 0: Start of a BSS section + * offset 4: Size of this BSS section. Must be multiply of 4 + */ + ldr r3, =__zero_table_start__ + ldr r4, =__zero_table_end__ + +.L_loop2: + cmp r3, r4 + bge .L_loop2_done + ldr r1, [r3] + ldr r2, [r3, #4] + movs r0, 0 + +.L_loop2_0: + subs r2, #4 + itt ge + strge r0, [r1, r2] + bge .L_loop2_0 + + adds r3, #8 + b .L_loop2 +.L_loop2_done: +#elif defined (__STARTUP_CLEAR_BSS) +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.L_loop3: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .L_loop3 +#endif /* __STARTUP_CLEAR_BSS_MULTIPLE || __STARTUP_CLEAR_BSS */ + + /* Update Vector Table Offset Register. */ + ldr r0, =__ramVectors + ldr r1, =CY_CPU_VTOR_ADDR + str r0, [r1] + dsb 0xF + + /* Enable the FPU if used */ + bl Cy_SystemInitFpuEnable + + bl _start + + /* Should never get here */ + b . + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak Default_Handler + .type Default_Handler, %function + +Default_Handler: + b . + .size Default_Handler, . - Default_Handler + + + .weak Cy_SysLib_FaultHandler + .type Cy_SysLib_FaultHandler, %function + +Cy_SysLib_FaultHandler: + b . + .size Cy_SysLib_FaultHandler, . - Cy_SysLib_FaultHandler + .type Fault_Handler, %function + +Fault_Handler: + /* Storing LR content for Creator call stack trace */ + push {LR} + movs r0, #4 + mov r1, LR + tst r0, r1 + beq .L_MSP + mrs r0, PSP + b .L_API_call +.L_MSP: + mrs r0, MSP +.L_API_call: + /* Compensation of stack pointer address due to pushing 4 bytes of LR */ + adds r0, r0, #4 + bl Cy_SysLib_FaultHandler + b . + .size Fault_Handler, . - Fault_Handler + +.macro def_fault_Handler fault_handler_name + .weak \fault_handler_name + .set \fault_handler_name, Fault_Handler + .endm + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + + def_irq_handler NMI_Handler + + def_fault_Handler HardFault_Handler + def_fault_Handler MemManage_Handler + def_fault_Handler BusFault_Handler + def_fault_Handler UsageFault_Handler + + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + + def_irq_handler ioss_interrupts_gpio_0_IRQHandler /* GPIO Port Interrupt #0 */ + def_irq_handler ioss_interrupts_gpio_1_IRQHandler /* GPIO Port Interrupt #1 */ + def_irq_handler ioss_interrupts_gpio_2_IRQHandler /* GPIO Port Interrupt #2 */ + def_irq_handler ioss_interrupts_gpio_3_IRQHandler /* GPIO Port Interrupt #3 */ + def_irq_handler ioss_interrupts_gpio_4_IRQHandler /* GPIO Port Interrupt #4 */ + def_irq_handler ioss_interrupts_gpio_5_IRQHandler /* GPIO Port Interrupt #5 */ + def_irq_handler ioss_interrupts_gpio_6_IRQHandler /* GPIO Port Interrupt #6 */ + def_irq_handler ioss_interrupts_gpio_7_IRQHandler /* GPIO Port Interrupt #7 */ + def_irq_handler ioss_interrupts_gpio_8_IRQHandler /* GPIO Port Interrupt #8 */ + def_irq_handler ioss_interrupts_gpio_9_IRQHandler /* GPIO Port Interrupt #9 */ + def_irq_handler ioss_interrupts_gpio_10_IRQHandler /* GPIO Port Interrupt #10 */ + def_irq_handler ioss_interrupts_gpio_11_IRQHandler /* GPIO Port Interrupt #11 */ + def_irq_handler ioss_interrupts_gpio_12_IRQHandler /* GPIO Port Interrupt #12 */ + def_irq_handler ioss_interrupts_gpio_13_IRQHandler /* GPIO Port Interrupt #13 */ + def_irq_handler ioss_interrupts_gpio_14_IRQHandler /* GPIO Port Interrupt #14 */ + def_irq_handler ioss_interrupt_gpio_IRQHandler /* GPIO All Ports */ + def_irq_handler ioss_interrupt_vdd_IRQHandler /* GPIO Supply Detect Interrupt */ + def_irq_handler lpcomp_interrupt_IRQHandler /* Low Power Comparator Interrupt */ + def_irq_handler scb_8_interrupt_IRQHandler /* Serial Communication Block #8 (DeepSleep capable) */ + def_irq_handler srss_interrupt_mcwdt_0_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_mcwdt_1_IRQHandler /* Multi Counter Watchdog Timer interrupt */ + def_irq_handler srss_interrupt_backup_IRQHandler /* Backup domain interrupt */ + def_irq_handler srss_interrupt_IRQHandler /* Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + def_irq_handler cpuss_interrupts_ipc_0_IRQHandler /* CPUSS Inter Process Communication Interrupt #0 */ + def_irq_handler cpuss_interrupts_ipc_1_IRQHandler /* CPUSS Inter Process Communication Interrupt #1 */ + def_irq_handler cpuss_interrupts_ipc_2_IRQHandler /* CPUSS Inter Process Communication Interrupt #2 */ + def_irq_handler cpuss_interrupts_ipc_3_IRQHandler /* CPUSS Inter Process Communication Interrupt #3 */ + def_irq_handler cpuss_interrupts_ipc_4_IRQHandler /* CPUSS Inter Process Communication Interrupt #4 */ + def_irq_handler cpuss_interrupts_ipc_5_IRQHandler /* CPUSS Inter Process Communication Interrupt #5 */ + def_irq_handler cpuss_interrupts_ipc_6_IRQHandler /* CPUSS Inter Process Communication Interrupt #6 */ + def_irq_handler cpuss_interrupts_ipc_7_IRQHandler /* CPUSS Inter Process Communication Interrupt #7 */ + def_irq_handler cpuss_interrupts_ipc_8_IRQHandler /* CPUSS Inter Process Communication Interrupt #8 */ + def_irq_handler cpuss_interrupts_ipc_9_IRQHandler /* CPUSS Inter Process Communication Interrupt #9 */ + def_irq_handler cpuss_interrupts_ipc_10_IRQHandler /* CPUSS Inter Process Communication Interrupt #10 */ + def_irq_handler cpuss_interrupts_ipc_11_IRQHandler /* CPUSS Inter Process Communication Interrupt #11 */ + def_irq_handler cpuss_interrupts_ipc_12_IRQHandler /* CPUSS Inter Process Communication Interrupt #12 */ + def_irq_handler cpuss_interrupts_ipc_13_IRQHandler /* CPUSS Inter Process Communication Interrupt #13 */ + def_irq_handler cpuss_interrupts_ipc_14_IRQHandler /* CPUSS Inter Process Communication Interrupt #14 */ + def_irq_handler cpuss_interrupts_ipc_15_IRQHandler /* CPUSS Inter Process Communication Interrupt #15 */ + def_irq_handler scb_0_interrupt_IRQHandler /* Serial Communication Block #0 */ + def_irq_handler scb_1_interrupt_IRQHandler /* Serial Communication Block #1 */ + def_irq_handler scb_2_interrupt_IRQHandler /* Serial Communication Block #2 */ + def_irq_handler scb_3_interrupt_IRQHandler /* Serial Communication Block #3 */ + def_irq_handler scb_4_interrupt_IRQHandler /* Serial Communication Block #4 */ + def_irq_handler scb_5_interrupt_IRQHandler /* Serial Communication Block #5 */ + def_irq_handler scb_6_interrupt_IRQHandler /* Serial Communication Block #6 */ + def_irq_handler scb_7_interrupt_IRQHandler /* Serial Communication Block #7 */ + def_irq_handler scb_9_interrupt_IRQHandler /* Serial Communication Block #9 */ + def_irq_handler scb_10_interrupt_IRQHandler /* Serial Communication Block #10 */ + def_irq_handler scb_11_interrupt_IRQHandler /* Serial Communication Block #11 */ + def_irq_handler scb_12_interrupt_IRQHandler /* Serial Communication Block #12 */ + def_irq_handler csd_interrupt_IRQHandler /* CSD (Capsense) interrupt */ + def_irq_handler cpuss_interrupts_dmac_0_IRQHandler /* CPUSS DMAC, Channel #0 */ + def_irq_handler cpuss_interrupts_dmac_1_IRQHandler /* CPUSS DMAC, Channel #1 */ + def_irq_handler cpuss_interrupts_dmac_2_IRQHandler /* CPUSS DMAC, Channel #2 */ + def_irq_handler cpuss_interrupts_dmac_3_IRQHandler /* CPUSS DMAC, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_0_IRQHandler /* CPUSS DataWire #0, Channel #0 */ + def_irq_handler cpuss_interrupts_dw0_1_IRQHandler /* CPUSS DataWire #0, Channel #1 */ + def_irq_handler cpuss_interrupts_dw0_2_IRQHandler /* CPUSS DataWire #0, Channel #2 */ + def_irq_handler cpuss_interrupts_dw0_3_IRQHandler /* CPUSS DataWire #0, Channel #3 */ + def_irq_handler cpuss_interrupts_dw0_4_IRQHandler /* CPUSS DataWire #0, Channel #4 */ + def_irq_handler cpuss_interrupts_dw0_5_IRQHandler /* CPUSS DataWire #0, Channel #5 */ + def_irq_handler cpuss_interrupts_dw0_6_IRQHandler /* CPUSS DataWire #0, Channel #6 */ + def_irq_handler cpuss_interrupts_dw0_7_IRQHandler /* CPUSS DataWire #0, Channel #7 */ + def_irq_handler cpuss_interrupts_dw0_8_IRQHandler /* CPUSS DataWire #0, Channel #8 */ + def_irq_handler cpuss_interrupts_dw0_9_IRQHandler /* CPUSS DataWire #0, Channel #9 */ + def_irq_handler cpuss_interrupts_dw0_10_IRQHandler /* CPUSS DataWire #0, Channel #10 */ + def_irq_handler cpuss_interrupts_dw0_11_IRQHandler /* CPUSS DataWire #0, Channel #11 */ + def_irq_handler cpuss_interrupts_dw0_12_IRQHandler /* CPUSS DataWire #0, Channel #12 */ + def_irq_handler cpuss_interrupts_dw0_13_IRQHandler /* CPUSS DataWire #0, Channel #13 */ + def_irq_handler cpuss_interrupts_dw0_14_IRQHandler /* CPUSS DataWire #0, Channel #14 */ + def_irq_handler cpuss_interrupts_dw0_15_IRQHandler /* CPUSS DataWire #0, Channel #15 */ + def_irq_handler cpuss_interrupts_dw0_16_IRQHandler /* CPUSS DataWire #0, Channel #16 */ + def_irq_handler cpuss_interrupts_dw0_17_IRQHandler /* CPUSS DataWire #0, Channel #17 */ + def_irq_handler cpuss_interrupts_dw0_18_IRQHandler /* CPUSS DataWire #0, Channel #18 */ + def_irq_handler cpuss_interrupts_dw0_19_IRQHandler /* CPUSS DataWire #0, Channel #19 */ + def_irq_handler cpuss_interrupts_dw0_20_IRQHandler /* CPUSS DataWire #0, Channel #20 */ + def_irq_handler cpuss_interrupts_dw0_21_IRQHandler /* CPUSS DataWire #0, Channel #21 */ + def_irq_handler cpuss_interrupts_dw0_22_IRQHandler /* CPUSS DataWire #0, Channel #22 */ + def_irq_handler cpuss_interrupts_dw0_23_IRQHandler /* CPUSS DataWire #0, Channel #23 */ + def_irq_handler cpuss_interrupts_dw0_24_IRQHandler /* CPUSS DataWire #0, Channel #24 */ + def_irq_handler cpuss_interrupts_dw0_25_IRQHandler /* CPUSS DataWire #0, Channel #25 */ + def_irq_handler cpuss_interrupts_dw0_26_IRQHandler /* CPUSS DataWire #0, Channel #26 */ + def_irq_handler cpuss_interrupts_dw0_27_IRQHandler /* CPUSS DataWire #0, Channel #27 */ + def_irq_handler cpuss_interrupts_dw0_28_IRQHandler /* CPUSS DataWire #0, Channel #28 */ + def_irq_handler cpuss_interrupts_dw1_0_IRQHandler /* CPUSS DataWire #1, Channel #0 */ + def_irq_handler cpuss_interrupts_dw1_1_IRQHandler /* CPUSS DataWire #1, Channel #1 */ + def_irq_handler cpuss_interrupts_dw1_2_IRQHandler /* CPUSS DataWire #1, Channel #2 */ + def_irq_handler cpuss_interrupts_dw1_3_IRQHandler /* CPUSS DataWire #1, Channel #3 */ + def_irq_handler cpuss_interrupts_dw1_4_IRQHandler /* CPUSS DataWire #1, Channel #4 */ + def_irq_handler cpuss_interrupts_dw1_5_IRQHandler /* CPUSS DataWire #1, Channel #5 */ + def_irq_handler cpuss_interrupts_dw1_6_IRQHandler /* CPUSS DataWire #1, Channel #6 */ + def_irq_handler cpuss_interrupts_dw1_7_IRQHandler /* CPUSS DataWire #1, Channel #7 */ + def_irq_handler cpuss_interrupts_dw1_8_IRQHandler /* CPUSS DataWire #1, Channel #8 */ + def_irq_handler cpuss_interrupts_dw1_9_IRQHandler /* CPUSS DataWire #1, Channel #9 */ + def_irq_handler cpuss_interrupts_dw1_10_IRQHandler /* CPUSS DataWire #1, Channel #10 */ + def_irq_handler cpuss_interrupts_dw1_11_IRQHandler /* CPUSS DataWire #1, Channel #11 */ + def_irq_handler cpuss_interrupts_dw1_12_IRQHandler /* CPUSS DataWire #1, Channel #12 */ + def_irq_handler cpuss_interrupts_dw1_13_IRQHandler /* CPUSS DataWire #1, Channel #13 */ + def_irq_handler cpuss_interrupts_dw1_14_IRQHandler /* CPUSS DataWire #1, Channel #14 */ + def_irq_handler cpuss_interrupts_dw1_15_IRQHandler /* CPUSS DataWire #1, Channel #15 */ + def_irq_handler cpuss_interrupts_dw1_16_IRQHandler /* CPUSS DataWire #1, Channel #16 */ + def_irq_handler cpuss_interrupts_dw1_17_IRQHandler /* CPUSS DataWire #1, Channel #17 */ + def_irq_handler cpuss_interrupts_dw1_18_IRQHandler /* CPUSS DataWire #1, Channel #18 */ + def_irq_handler cpuss_interrupts_dw1_19_IRQHandler /* CPUSS DataWire #1, Channel #19 */ + def_irq_handler cpuss_interrupts_dw1_20_IRQHandler /* CPUSS DataWire #1, Channel #20 */ + def_irq_handler cpuss_interrupts_dw1_21_IRQHandler /* CPUSS DataWire #1, Channel #21 */ + def_irq_handler cpuss_interrupts_dw1_22_IRQHandler /* CPUSS DataWire #1, Channel #22 */ + def_irq_handler cpuss_interrupts_dw1_23_IRQHandler /* CPUSS DataWire #1, Channel #23 */ + def_irq_handler cpuss_interrupts_dw1_24_IRQHandler /* CPUSS DataWire #1, Channel #24 */ + def_irq_handler cpuss_interrupts_dw1_25_IRQHandler /* CPUSS DataWire #1, Channel #25 */ + def_irq_handler cpuss_interrupts_dw1_26_IRQHandler /* CPUSS DataWire #1, Channel #26 */ + def_irq_handler cpuss_interrupts_dw1_27_IRQHandler /* CPUSS DataWire #1, Channel #27 */ + def_irq_handler cpuss_interrupts_dw1_28_IRQHandler /* CPUSS DataWire #1, Channel #28 */ + def_irq_handler cpuss_interrupts_fault_0_IRQHandler /* CPUSS Fault Structure Interrupt #0 */ + def_irq_handler cpuss_interrupts_fault_1_IRQHandler /* CPUSS Fault Structure Interrupt #1 */ + def_irq_handler cpuss_interrupt_crypto_IRQHandler /* CRYPTO Accelerator Interrupt */ + def_irq_handler cpuss_interrupt_fm_IRQHandler /* FLASH Macro Interrupt */ + def_irq_handler cpuss_interrupts_cm4_fp_IRQHandler /* Floating Point operation fault */ + def_irq_handler cpuss_interrupts_cm0_cti_0_IRQHandler /* CM0+ CTI #0 */ + def_irq_handler cpuss_interrupts_cm0_cti_1_IRQHandler /* CM0+ CTI #1 */ + def_irq_handler cpuss_interrupts_cm4_cti_0_IRQHandler /* CM4 CTI #0 */ + def_irq_handler cpuss_interrupts_cm4_cti_1_IRQHandler /* CM4 CTI #1 */ + def_irq_handler tcpwm_0_interrupts_0_IRQHandler /* TCPWM #0, Counter #0 */ + def_irq_handler tcpwm_0_interrupts_1_IRQHandler /* TCPWM #0, Counter #1 */ + def_irq_handler tcpwm_0_interrupts_2_IRQHandler /* TCPWM #0, Counter #2 */ + def_irq_handler tcpwm_0_interrupts_3_IRQHandler /* TCPWM #0, Counter #3 */ + def_irq_handler tcpwm_0_interrupts_4_IRQHandler /* TCPWM #0, Counter #4 */ + def_irq_handler tcpwm_0_interrupts_5_IRQHandler /* TCPWM #0, Counter #5 */ + def_irq_handler tcpwm_0_interrupts_6_IRQHandler /* TCPWM #0, Counter #6 */ + def_irq_handler tcpwm_0_interrupts_7_IRQHandler /* TCPWM #0, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_0_IRQHandler /* TCPWM #1, Counter #0 */ + def_irq_handler tcpwm_1_interrupts_1_IRQHandler /* TCPWM #1, Counter #1 */ + def_irq_handler tcpwm_1_interrupts_2_IRQHandler /* TCPWM #1, Counter #2 */ + def_irq_handler tcpwm_1_interrupts_3_IRQHandler /* TCPWM #1, Counter #3 */ + def_irq_handler tcpwm_1_interrupts_4_IRQHandler /* TCPWM #1, Counter #4 */ + def_irq_handler tcpwm_1_interrupts_5_IRQHandler /* TCPWM #1, Counter #5 */ + def_irq_handler tcpwm_1_interrupts_6_IRQHandler /* TCPWM #1, Counter #6 */ + def_irq_handler tcpwm_1_interrupts_7_IRQHandler /* TCPWM #1, Counter #7 */ + def_irq_handler tcpwm_1_interrupts_8_IRQHandler /* TCPWM #1, Counter #8 */ + def_irq_handler tcpwm_1_interrupts_9_IRQHandler /* TCPWM #1, Counter #9 */ + def_irq_handler tcpwm_1_interrupts_10_IRQHandler /* TCPWM #1, Counter #10 */ + def_irq_handler tcpwm_1_interrupts_11_IRQHandler /* TCPWM #1, Counter #11 */ + def_irq_handler tcpwm_1_interrupts_12_IRQHandler /* TCPWM #1, Counter #12 */ + def_irq_handler tcpwm_1_interrupts_13_IRQHandler /* TCPWM #1, Counter #13 */ + def_irq_handler tcpwm_1_interrupts_14_IRQHandler /* TCPWM #1, Counter #14 */ + def_irq_handler tcpwm_1_interrupts_15_IRQHandler /* TCPWM #1, Counter #15 */ + def_irq_handler tcpwm_1_interrupts_16_IRQHandler /* TCPWM #1, Counter #16 */ + def_irq_handler tcpwm_1_interrupts_17_IRQHandler /* TCPWM #1, Counter #17 */ + def_irq_handler tcpwm_1_interrupts_18_IRQHandler /* TCPWM #1, Counter #18 */ + def_irq_handler tcpwm_1_interrupts_19_IRQHandler /* TCPWM #1, Counter #19 */ + def_irq_handler tcpwm_1_interrupts_20_IRQHandler /* TCPWM #1, Counter #20 */ + def_irq_handler tcpwm_1_interrupts_21_IRQHandler /* TCPWM #1, Counter #21 */ + def_irq_handler tcpwm_1_interrupts_22_IRQHandler /* TCPWM #1, Counter #22 */ + def_irq_handler tcpwm_1_interrupts_23_IRQHandler /* TCPWM #1, Counter #23 */ + def_irq_handler pass_interrupt_sar_IRQHandler /* SAR ADC interrupt */ + def_irq_handler audioss_0_interrupt_i2s_IRQHandler /* I2S0 Audio interrupt */ + def_irq_handler audioss_0_interrupt_pdm_IRQHandler /* PDM0/PCM0 Audio interrupt */ + def_irq_handler audioss_1_interrupt_i2s_IRQHandler /* I2S1 Audio interrupt */ + def_irq_handler profile_interrupt_IRQHandler /* Energy Profiler interrupt */ + def_irq_handler smif_interrupt_IRQHandler /* Serial Memory Interface interrupt */ + def_irq_handler usb_interrupt_hi_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_med_IRQHandler /* USB Interrupt */ + def_irq_handler usb_interrupt_lo_IRQHandler /* USB Interrupt */ + def_irq_handler sdhc_0_interrupt_wakeup_IRQHandler /* SDIO wakeup interrupt for mxsdhc */ + def_irq_handler sdhc_0_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + def_irq_handler sdhc_1_interrupt_wakeup_IRQHandler /* EEMC wakeup interrupt for mxsdhc, not used */ + def_irq_handler sdhc_1_interrupt_general_IRQHandler /* Consolidated interrupt for mxsdhc for everything else */ + + .end + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf new file mode 100644 index 00000000000..019967a0c12 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf @@ -0,0 +1,274 @@ +/***************************************************************************//** +* \file cy8c6xxa_cm4_dual.icf +* \version 2.60 +* +* Linker file for the IAR compiler. +* +* The main purpose of the linker script is to describe how the sections in the +* input files should be mapped into the output file, and to control the memory +* layout of the output file. +* +* \note The entry point is fixed and starts at 0x10000000. The valid application +* image should be placed there. +* +* \note The linker files included with the PDL template projects must be generic +* and handle all common use cases. Your project may not use every section +* defined in the linker files. In that case you may see warnings during the +* build process. In your project, you can simply comment out or remove the +* relevant code in the linker file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; + +if (!isdefinedsymbol(MBED_ROM_START)) { + define symbol MBED_ROM_START = 0x10180000; +} + +/* MBED_APP_START is being used by the bootloader build script and + * will be calculate by the system. In case if MBED_APP_START address is + * customized by the bootloader config, the application image should not + * include CM0p prebuilt image. + */ +if (!isdefinedsymbol(MBED_APP_START)) { + define symbol MBED_APP_START = (MBED_ROM_START); +} + +if (!isdefinedsymbol(MBED_ROM_SIZE)) { + define symbol MBED_ROM_SIZE = 0x80000; +} + +/* MBED_APP_SIZE is being used by the bootloader build script and + * will be calculate by the system. + */ +if (!isdefinedsymbol(MBED_APP_SIZE)) { + define symbol MBED_APP_SIZE = (MBED_ROM_SIZE); +} + +if (!isdefinedsymbol(MBED_RAM_START)) { + define symbol MBED_RAM_START = 0x08080000; +} + +if (!isdefinedsymbol(MBED_RAM_SIZE)) { + define symbol MBED_RAM_SIZE = 0x7F800; +} + +if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { + + if (!isdefinedsymbol(__STACK_SIZE)) { + define symbol MBED_BOOT_STACK_SIZE = 0x0400; + } else { + define symbol MBED_BOOT_STACK_SIZE = __STACK_SIZE; + } +} + +define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; + +/* The symbols below define the location and size of blocks of memory in the target. + * Use these symbols to specify the memory regions available for allocation. + */ + +/* The following symbols control RAM and flash memory allocation for the CM4 core. + * You can change the memory allocation by editing RAM and Flash symbols. + * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use. + * Using this memory region for other purposes will lead to unexpected behavior. + * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf', + * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'. + */ +/* RAM */ +define symbol __ICFEDIT_region_IRAM1_start__ = MBED_RAM_START; +define symbol __ICFEDIT_region_IRAM1_end__ = (MBED_RAM_START + MBED_RAM_SIZE); +/* Flash */ +define symbol __ICFEDIT_region_IROM1_start__ = MBED_APP_START; +define symbol __ICFEDIT_region_IROM1_end__ = (MBED_APP_START + MBED_APP_SIZE); + +/* The following symbols define a 32K flash region used for EEPROM emulation. + * This region can also be used as the general purpose flash. + * You can assign sections to this memory region for only one of the cores. + * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region. + * Therefore, repurposing this memory region will prevent such middleware from operation. + */ +define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x14007FFF; + +/* The following symbols define device specific memory regions and must not be changed. */ +/* Supervisory FLASH - User Data */ +define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800; +define symbol __ICFEDIT_region_IROM3_end__ = 0x160007FF; + +/* Supervisory FLASH - Normal Access Restrictions (NAR) */ +define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00; +define symbol __ICFEDIT_region_IROM4_end__ = 0x16001BFF; + +/* Supervisory FLASH - Public Key */ +define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00; +define symbol __ICFEDIT_region_IROM5_end__ = 0x160065FF; + +/* Supervisory FLASH - Table of Content # 2 */ +define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00; +define symbol __ICFEDIT_region_IROM6_end__ = 0x16007DFF; + +/* Supervisory FLASH - Table of Content # 2 Copy */ +define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00; +define symbol __ICFEDIT_region_IROM7_end__ = 0x16007FFF; + +/* eFuse */ +define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000; +define symbol __ICFEDIT_region_IROM8_end__ = 0x907FFFFF; + +/* XIP */ +define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000; +define symbol __ICFEDIT_region_EROM1_end__ = 0x1FFFFFFF; + +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; + + +define symbol __ICFEDIT_region_IRAM2_start__ = 0x0; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; +/*-Sizes-*/ +/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ +if (!isdefinedsymbol(__HEAP_SIZE)) { + define symbol __ICFEDIT_size_heap__ = 0x0400; +} else { + define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE; +} +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__]; +define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__]; +define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__]; +define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__]; +define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__]; +define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__]; +define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__]; +define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__]; + +define block RAM_DATA {readwrite section .data}; +define block RAM_OTHER {readwrite section * }; +define block RAM_NOINIT {readwrite section .noinit}; +define block RAM_BSS {readwrite section .bss}; +define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NOINIT, block RAM_BSS}; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { }; + +define block RO {first section .intvec, readonly}; + +/*-Initializations-*/ +initialize by copy { readwrite }; +do not initialize { section .noinit, section .intvec_ram }; + +/*-Placement-*/ + +/* Flash - Cortex-M4 application */ +place at start of IROM1_region { block RO }; + +/* Used for the digital signature of the secure application and the Bootloader SDK application. */ +".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature }; + +/* Emulated EEPROM Flash area */ +".cy_em_eeprom" : place at start of IROM2_region { section .cy_em_eeprom }; + +/* Supervisory Flash - User Data */ +".cy_sflash_user_data" : place at start of IROM3_region { section .cy_sflash_user_data }; + +/* Supervisory Flash - NAR */ +".cy_sflash_nar" : place at start of IROM4_region { section .cy_sflash_nar }; + +/* Supervisory Flash - Public Key */ +".cy_sflash_public_key" : place at start of IROM5_region { section .cy_sflash_public_key }; + +/* Supervisory Flash - TOC2 */ +".cy_toc_part2" : place at start of IROM6_region { section .cy_toc_part2 }; + +/* Supervisory Flash - RTOC2 */ +".cy_rtoc_part2" : place at start of IROM7_region { section .cy_rtoc_part2 }; + +/* eFuse */ +".cy_efuse" : place at start of IROM8_region { section .cy_efuse }; + +/* Execute in Place (XIP). See the smif driver documentation for details. */ +".cy_xip" : place at start of EROM1_region { section .cy_xip }; + +/* RAM */ +place at start of IRAM1_region { readwrite section .intvec_ram}; +place in IRAM1_region { block RAM}; +place in IRAM1_region { block HEAP}; +place at end of IRAM1_region { block CSTACK }; + +/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */ +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +keep { section .cy_app_signature, + section .cy_em_eeprom, + section .cy_sflash_user_data, + section .cy_sflash_nar, + section .cy_sflash_public_key, + section .cy_toc_part2, + section .cy_rtoc_part2, + section .cy_efuse, + section .cy_xip, + section .cymeta, + }; + + +/* The following symbols used by the cymcuelftool. */ +/* Flash */ +define exported symbol __cy_memory_0_start = 0x10000000; +define exported symbol __cy_memory_0_length = 0x00200000; +define exported symbol __cy_memory_0_row_size = 0x200; + +/* Emulated EEPROM Flash area */ +define exported symbol __cy_memory_1_start = 0x14000000; +define exported symbol __cy_memory_1_length = 0x8000; +define exported symbol __cy_memory_1_row_size = 0x200; + +/* Supervisory Flash */ +define exported symbol __cy_memory_2_start = 0x16000000; +define exported symbol __cy_memory_2_length = 0x8000; +define exported symbol __cy_memory_2_row_size = 0x200; + +/* XIP */ +define exported symbol __cy_memory_3_start = 0x18000000; +define exported symbol __cy_memory_3_length = 0x08000000; +define exported symbol __cy_memory_3_row_size = 0x200; + +/* eFuse */ +define exported symbol __cy_memory_4_start = 0x90700000; +define exported symbol __cy_memory_4_length = 0x100000; +define exported symbol __cy_memory_4_row_size = 1; + +/* EOF */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S new file mode 100644 index 00000000000..3257b6f20c9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/TOOLCHAIN_IAR/startup_psoc6_02_cm4.S @@ -0,0 +1,1263 @@ +;/**************************************************************************//** +; * @file startup_psoc6_02_cm4.S +; * @brief CMSIS Core Device Startup File for +; * ARMCM4 Device Series +; * @version V5.00 +; * @date 08. March 2016 +; ******************************************************************************/ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + SECTION .intvec_ram:DATA:NOROOT(2) + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN Cy_SystemInitFpuEnable + EXTERN __iar_data_init3 + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + PUBLIC __ramVectors + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD 0x0000000D ; NMI_Handler is defined in ROM code + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External interrupts Description + DCD ioss_interrupts_gpio_0_IRQHandler ; GPIO Port Interrupt #0 + DCD ioss_interrupts_gpio_1_IRQHandler ; GPIO Port Interrupt #1 + DCD ioss_interrupts_gpio_2_IRQHandler ; GPIO Port Interrupt #2 + DCD ioss_interrupts_gpio_3_IRQHandler ; GPIO Port Interrupt #3 + DCD ioss_interrupts_gpio_4_IRQHandler ; GPIO Port Interrupt #4 + DCD ioss_interrupts_gpio_5_IRQHandler ; GPIO Port Interrupt #5 + DCD ioss_interrupts_gpio_6_IRQHandler ; GPIO Port Interrupt #6 + DCD ioss_interrupts_gpio_7_IRQHandler ; GPIO Port Interrupt #7 + DCD ioss_interrupts_gpio_8_IRQHandler ; GPIO Port Interrupt #8 + DCD ioss_interrupts_gpio_9_IRQHandler ; GPIO Port Interrupt #9 + DCD ioss_interrupts_gpio_10_IRQHandler ; GPIO Port Interrupt #10 + DCD ioss_interrupts_gpio_11_IRQHandler ; GPIO Port Interrupt #11 + DCD ioss_interrupts_gpio_12_IRQHandler ; GPIO Port Interrupt #12 + DCD ioss_interrupts_gpio_13_IRQHandler ; GPIO Port Interrupt #13 + DCD ioss_interrupts_gpio_14_IRQHandler ; GPIO Port Interrupt #14 + DCD ioss_interrupt_gpio_IRQHandler ; GPIO All Ports + DCD ioss_interrupt_vdd_IRQHandler ; GPIO Supply Detect Interrupt + DCD lpcomp_interrupt_IRQHandler ; Low Power Comparator Interrupt + DCD scb_8_interrupt_IRQHandler ; Serial Communication Block #8 (DeepSleep capable) + DCD srss_interrupt_mcwdt_0_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_mcwdt_1_IRQHandler ; Multi Counter Watchdog Timer interrupt + DCD srss_interrupt_backup_IRQHandler ; Backup domain interrupt + DCD srss_interrupt_IRQHandler ; Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) + DCD cpuss_interrupts_ipc_0_IRQHandler ; CPUSS Inter Process Communication Interrupt #0 + DCD cpuss_interrupts_ipc_1_IRQHandler ; CPUSS Inter Process Communication Interrupt #1 + DCD cpuss_interrupts_ipc_2_IRQHandler ; CPUSS Inter Process Communication Interrupt #2 + DCD cpuss_interrupts_ipc_3_IRQHandler ; CPUSS Inter Process Communication Interrupt #3 + DCD cpuss_interrupts_ipc_4_IRQHandler ; CPUSS Inter Process Communication Interrupt #4 + DCD cpuss_interrupts_ipc_5_IRQHandler ; CPUSS Inter Process Communication Interrupt #5 + DCD cpuss_interrupts_ipc_6_IRQHandler ; CPUSS Inter Process Communication Interrupt #6 + DCD cpuss_interrupts_ipc_7_IRQHandler ; CPUSS Inter Process Communication Interrupt #7 + DCD cpuss_interrupts_ipc_8_IRQHandler ; CPUSS Inter Process Communication Interrupt #8 + DCD cpuss_interrupts_ipc_9_IRQHandler ; CPUSS Inter Process Communication Interrupt #9 + DCD cpuss_interrupts_ipc_10_IRQHandler ; CPUSS Inter Process Communication Interrupt #10 + DCD cpuss_interrupts_ipc_11_IRQHandler ; CPUSS Inter Process Communication Interrupt #11 + DCD cpuss_interrupts_ipc_12_IRQHandler ; CPUSS Inter Process Communication Interrupt #12 + DCD cpuss_interrupts_ipc_13_IRQHandler ; CPUSS Inter Process Communication Interrupt #13 + DCD cpuss_interrupts_ipc_14_IRQHandler ; CPUSS Inter Process Communication Interrupt #14 + DCD cpuss_interrupts_ipc_15_IRQHandler ; CPUSS Inter Process Communication Interrupt #15 + DCD scb_0_interrupt_IRQHandler ; Serial Communication Block #0 + DCD scb_1_interrupt_IRQHandler ; Serial Communication Block #1 + DCD scb_2_interrupt_IRQHandler ; Serial Communication Block #2 + DCD scb_3_interrupt_IRQHandler ; Serial Communication Block #3 + DCD scb_4_interrupt_IRQHandler ; Serial Communication Block #4 + DCD scb_5_interrupt_IRQHandler ; Serial Communication Block #5 + DCD scb_6_interrupt_IRQHandler ; Serial Communication Block #6 + DCD scb_7_interrupt_IRQHandler ; Serial Communication Block #7 + DCD scb_9_interrupt_IRQHandler ; Serial Communication Block #9 + DCD scb_10_interrupt_IRQHandler ; Serial Communication Block #10 + DCD scb_11_interrupt_IRQHandler ; Serial Communication Block #11 + DCD scb_12_interrupt_IRQHandler ; Serial Communication Block #12 + DCD csd_interrupt_IRQHandler ; CSD (Capsense) interrupt + DCD cpuss_interrupts_dmac_0_IRQHandler ; CPUSS DMAC, Channel #0 + DCD cpuss_interrupts_dmac_1_IRQHandler ; CPUSS DMAC, Channel #1 + DCD cpuss_interrupts_dmac_2_IRQHandler ; CPUSS DMAC, Channel #2 + DCD cpuss_interrupts_dmac_3_IRQHandler ; CPUSS DMAC, Channel #3 + DCD cpuss_interrupts_dw0_0_IRQHandler ; CPUSS DataWire #0, Channel #0 + DCD cpuss_interrupts_dw0_1_IRQHandler ; CPUSS DataWire #0, Channel #1 + DCD cpuss_interrupts_dw0_2_IRQHandler ; CPUSS DataWire #0, Channel #2 + DCD cpuss_interrupts_dw0_3_IRQHandler ; CPUSS DataWire #0, Channel #3 + DCD cpuss_interrupts_dw0_4_IRQHandler ; CPUSS DataWire #0, Channel #4 + DCD cpuss_interrupts_dw0_5_IRQHandler ; CPUSS DataWire #0, Channel #5 + DCD cpuss_interrupts_dw0_6_IRQHandler ; CPUSS DataWire #0, Channel #6 + DCD cpuss_interrupts_dw0_7_IRQHandler ; CPUSS DataWire #0, Channel #7 + DCD cpuss_interrupts_dw0_8_IRQHandler ; CPUSS DataWire #0, Channel #8 + DCD cpuss_interrupts_dw0_9_IRQHandler ; CPUSS DataWire #0, Channel #9 + DCD cpuss_interrupts_dw0_10_IRQHandler ; CPUSS DataWire #0, Channel #10 + DCD cpuss_interrupts_dw0_11_IRQHandler ; CPUSS DataWire #0, Channel #11 + DCD cpuss_interrupts_dw0_12_IRQHandler ; CPUSS DataWire #0, Channel #12 + DCD cpuss_interrupts_dw0_13_IRQHandler ; CPUSS DataWire #0, Channel #13 + DCD cpuss_interrupts_dw0_14_IRQHandler ; CPUSS DataWire #0, Channel #14 + DCD cpuss_interrupts_dw0_15_IRQHandler ; CPUSS DataWire #0, Channel #15 + DCD cpuss_interrupts_dw0_16_IRQHandler ; CPUSS DataWire #0, Channel #16 + DCD cpuss_interrupts_dw0_17_IRQHandler ; CPUSS DataWire #0, Channel #17 + DCD cpuss_interrupts_dw0_18_IRQHandler ; CPUSS DataWire #0, Channel #18 + DCD cpuss_interrupts_dw0_19_IRQHandler ; CPUSS DataWire #0, Channel #19 + DCD cpuss_interrupts_dw0_20_IRQHandler ; CPUSS DataWire #0, Channel #20 + DCD cpuss_interrupts_dw0_21_IRQHandler ; CPUSS DataWire #0, Channel #21 + DCD cpuss_interrupts_dw0_22_IRQHandler ; CPUSS DataWire #0, Channel #22 + DCD cpuss_interrupts_dw0_23_IRQHandler ; CPUSS DataWire #0, Channel #23 + DCD cpuss_interrupts_dw0_24_IRQHandler ; CPUSS DataWire #0, Channel #24 + DCD cpuss_interrupts_dw0_25_IRQHandler ; CPUSS DataWire #0, Channel #25 + DCD cpuss_interrupts_dw0_26_IRQHandler ; CPUSS DataWire #0, Channel #26 + DCD cpuss_interrupts_dw0_27_IRQHandler ; CPUSS DataWire #0, Channel #27 + DCD cpuss_interrupts_dw0_28_IRQHandler ; CPUSS DataWire #0, Channel #28 + DCD cpuss_interrupts_dw1_0_IRQHandler ; CPUSS DataWire #1, Channel #0 + DCD cpuss_interrupts_dw1_1_IRQHandler ; CPUSS DataWire #1, Channel #1 + DCD cpuss_interrupts_dw1_2_IRQHandler ; CPUSS DataWire #1, Channel #2 + DCD cpuss_interrupts_dw1_3_IRQHandler ; CPUSS DataWire #1, Channel #3 + DCD cpuss_interrupts_dw1_4_IRQHandler ; CPUSS DataWire #1, Channel #4 + DCD cpuss_interrupts_dw1_5_IRQHandler ; CPUSS DataWire #1, Channel #5 + DCD cpuss_interrupts_dw1_6_IRQHandler ; CPUSS DataWire #1, Channel #6 + DCD cpuss_interrupts_dw1_7_IRQHandler ; CPUSS DataWire #1, Channel #7 + DCD cpuss_interrupts_dw1_8_IRQHandler ; CPUSS DataWire #1, Channel #8 + DCD cpuss_interrupts_dw1_9_IRQHandler ; CPUSS DataWire #1, Channel #9 + DCD cpuss_interrupts_dw1_10_IRQHandler ; CPUSS DataWire #1, Channel #10 + DCD cpuss_interrupts_dw1_11_IRQHandler ; CPUSS DataWire #1, Channel #11 + DCD cpuss_interrupts_dw1_12_IRQHandler ; CPUSS DataWire #1, Channel #12 + DCD cpuss_interrupts_dw1_13_IRQHandler ; CPUSS DataWire #1, Channel #13 + DCD cpuss_interrupts_dw1_14_IRQHandler ; CPUSS DataWire #1, Channel #14 + DCD cpuss_interrupts_dw1_15_IRQHandler ; CPUSS DataWire #1, Channel #15 + DCD cpuss_interrupts_dw1_16_IRQHandler ; CPUSS DataWire #1, Channel #16 + DCD cpuss_interrupts_dw1_17_IRQHandler ; CPUSS DataWire #1, Channel #17 + DCD cpuss_interrupts_dw1_18_IRQHandler ; CPUSS DataWire #1, Channel #18 + DCD cpuss_interrupts_dw1_19_IRQHandler ; CPUSS DataWire #1, Channel #19 + DCD cpuss_interrupts_dw1_20_IRQHandler ; CPUSS DataWire #1, Channel #20 + DCD cpuss_interrupts_dw1_21_IRQHandler ; CPUSS DataWire #1, Channel #21 + DCD cpuss_interrupts_dw1_22_IRQHandler ; CPUSS DataWire #1, Channel #22 + DCD cpuss_interrupts_dw1_23_IRQHandler ; CPUSS DataWire #1, Channel #23 + DCD cpuss_interrupts_dw1_24_IRQHandler ; CPUSS DataWire #1, Channel #24 + DCD cpuss_interrupts_dw1_25_IRQHandler ; CPUSS DataWire #1, Channel #25 + DCD cpuss_interrupts_dw1_26_IRQHandler ; CPUSS DataWire #1, Channel #26 + DCD cpuss_interrupts_dw1_27_IRQHandler ; CPUSS DataWire #1, Channel #27 + DCD cpuss_interrupts_dw1_28_IRQHandler ; CPUSS DataWire #1, Channel #28 + DCD cpuss_interrupts_fault_0_IRQHandler ; CPUSS Fault Structure Interrupt #0 + DCD cpuss_interrupts_fault_1_IRQHandler ; CPUSS Fault Structure Interrupt #1 + DCD cpuss_interrupt_crypto_IRQHandler ; CRYPTO Accelerator Interrupt + DCD cpuss_interrupt_fm_IRQHandler ; FLASH Macro Interrupt + DCD cpuss_interrupts_cm4_fp_IRQHandler ; Floating Point operation fault + DCD cpuss_interrupts_cm0_cti_0_IRQHandler ; CM0+ CTI #0 + DCD cpuss_interrupts_cm0_cti_1_IRQHandler ; CM0+ CTI #1 + DCD cpuss_interrupts_cm4_cti_0_IRQHandler ; CM4 CTI #0 + DCD cpuss_interrupts_cm4_cti_1_IRQHandler ; CM4 CTI #1 + DCD tcpwm_0_interrupts_0_IRQHandler ; TCPWM #0, Counter #0 + DCD tcpwm_0_interrupts_1_IRQHandler ; TCPWM #0, Counter #1 + DCD tcpwm_0_interrupts_2_IRQHandler ; TCPWM #0, Counter #2 + DCD tcpwm_0_interrupts_3_IRQHandler ; TCPWM #0, Counter #3 + DCD tcpwm_0_interrupts_4_IRQHandler ; TCPWM #0, Counter #4 + DCD tcpwm_0_interrupts_5_IRQHandler ; TCPWM #0, Counter #5 + DCD tcpwm_0_interrupts_6_IRQHandler ; TCPWM #0, Counter #6 + DCD tcpwm_0_interrupts_7_IRQHandler ; TCPWM #0, Counter #7 + DCD tcpwm_1_interrupts_0_IRQHandler ; TCPWM #1, Counter #0 + DCD tcpwm_1_interrupts_1_IRQHandler ; TCPWM #1, Counter #1 + DCD tcpwm_1_interrupts_2_IRQHandler ; TCPWM #1, Counter #2 + DCD tcpwm_1_interrupts_3_IRQHandler ; TCPWM #1, Counter #3 + DCD tcpwm_1_interrupts_4_IRQHandler ; TCPWM #1, Counter #4 + DCD tcpwm_1_interrupts_5_IRQHandler ; TCPWM #1, Counter #5 + DCD tcpwm_1_interrupts_6_IRQHandler ; TCPWM #1, Counter #6 + DCD tcpwm_1_interrupts_7_IRQHandler ; TCPWM #1, Counter #7 + DCD tcpwm_1_interrupts_8_IRQHandler ; TCPWM #1, Counter #8 + DCD tcpwm_1_interrupts_9_IRQHandler ; TCPWM #1, Counter #9 + DCD tcpwm_1_interrupts_10_IRQHandler ; TCPWM #1, Counter #10 + DCD tcpwm_1_interrupts_11_IRQHandler ; TCPWM #1, Counter #11 + DCD tcpwm_1_interrupts_12_IRQHandler ; TCPWM #1, Counter #12 + DCD tcpwm_1_interrupts_13_IRQHandler ; TCPWM #1, Counter #13 + DCD tcpwm_1_interrupts_14_IRQHandler ; TCPWM #1, Counter #14 + DCD tcpwm_1_interrupts_15_IRQHandler ; TCPWM #1, Counter #15 + DCD tcpwm_1_interrupts_16_IRQHandler ; TCPWM #1, Counter #16 + DCD tcpwm_1_interrupts_17_IRQHandler ; TCPWM #1, Counter #17 + DCD tcpwm_1_interrupts_18_IRQHandler ; TCPWM #1, Counter #18 + DCD tcpwm_1_interrupts_19_IRQHandler ; TCPWM #1, Counter #19 + DCD tcpwm_1_interrupts_20_IRQHandler ; TCPWM #1, Counter #20 + DCD tcpwm_1_interrupts_21_IRQHandler ; TCPWM #1, Counter #21 + DCD tcpwm_1_interrupts_22_IRQHandler ; TCPWM #1, Counter #22 + DCD tcpwm_1_interrupts_23_IRQHandler ; TCPWM #1, Counter #23 + DCD pass_interrupt_sar_IRQHandler ; SAR ADC interrupt + DCD audioss_0_interrupt_i2s_IRQHandler ; I2S0 Audio interrupt + DCD audioss_0_interrupt_pdm_IRQHandler ; PDM0/PCM0 Audio interrupt + DCD audioss_1_interrupt_i2s_IRQHandler ; I2S1 Audio interrupt + DCD profile_interrupt_IRQHandler ; Energy Profiler interrupt + DCD smif_interrupt_IRQHandler ; Serial Memory Interface interrupt + DCD usb_interrupt_hi_IRQHandler ; USB Interrupt + DCD usb_interrupt_med_IRQHandler ; USB Interrupt + DCD usb_interrupt_lo_IRQHandler ; USB Interrupt + DCD sdhc_0_interrupt_wakeup_IRQHandler ; SDIO wakeup interrupt for mxsdhc + DCD sdhc_0_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else + DCD sdhc_1_interrupt_wakeup_IRQHandler ; EEMC wakeup interrupt for mxsdhc, not used + DCD sdhc_1_interrupt_general_IRQHandler ; Consolidated interrupt for mxsdhc for everything else + +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + SECTION .intvec_ram:DATA:REORDER:NOROOT(2) +__ramVectors + DS32 __Vectors_Size + + + THUMB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default handlers +;; + PUBWEAK Default_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Default_Handler + B Default_Handler + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Weak function for startup customization +;; +;; Note. The global resources are not yet initialized (for example global variables, peripherals, clocks) +;; because this function is executed as the first instruction in the ResetHandler. +;; The PDL is also not initialized to use the proper register offsets. +;; The user of this function is responsible for initializing the PDL and resources before using them. +;; + PUBWEAK Cy_OnResetUser + SECTION .text:CODE:REORDER:NOROOT(2) +Cy_OnResetUser + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Define strong version to return zero for +;; __iar_program_start to skip data sections +;; initialization. +;; + PUBLIC __low_level_init + SECTION .text:CODE:REORDER:NOROOT(2) +__low_level_init + MOVS R0, #0 + BX LR + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + ; Define strong function for startup customization + LDR R0, =Cy_OnResetUser + BLX R0 + + ; Disable global interrupts + CPSID I + + ; Copy vectors from ROM to RAM + LDR r1, =__vector_table + LDR r0, =__ramVectors + LDR r2, =__Vectors_Size +intvec_copy + LDR r3, [r1] + STR r3, [r0] + ADDS r0, r0, #4 + ADDS r1, r1, #4 + SUBS r2, r2, #1 + CMP r2, #0 + BNE intvec_copy + + ; Update Vector Table Offset Register + LDR r0, =__ramVectors + LDR r1, =0xE000ED08 + STR r0, [r1] + dsb + + ; Initialize data sections + LDR R0, =__iar_data_init3 + BLX R0 + + LDR R0, =SystemInit + BLX R0 + + LDR R0, =__iar_program_start + BLX R0 + +; Should never get here +Cy_Main_Exited + B Cy_Main_Exited + + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + + PUBWEAK Cy_SysLib_FaultHandler + SECTION .text:CODE:REORDER:NOROOT(1) +Cy_SysLib_FaultHandler + B Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Wrapper + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Wrapper + IMPORT Cy_SysLib_FaultHandler + movs r0, #4 + mov r1, LR + tst r0, r1 + beq L_MSP + mrs r0, PSP + b L_API_call +L_MSP + mrs r0, MSP +L_API_call + ; Storing LR content for Creator call stack trace + push {LR} + bl Cy_SysLib_FaultHandler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Wrapper + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B HardFault_Wrapper + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B HardFault_Wrapper + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B HardFault_Wrapper + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + ; External interrupts + PUBWEAK ioss_interrupts_gpio_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_0_IRQHandler + B ioss_interrupts_gpio_0_IRQHandler + + PUBWEAK ioss_interrupts_gpio_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_1_IRQHandler + B ioss_interrupts_gpio_1_IRQHandler + + PUBWEAK ioss_interrupts_gpio_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_2_IRQHandler + B ioss_interrupts_gpio_2_IRQHandler + + PUBWEAK ioss_interrupts_gpio_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_3_IRQHandler + B ioss_interrupts_gpio_3_IRQHandler + + PUBWEAK ioss_interrupts_gpio_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_4_IRQHandler + B ioss_interrupts_gpio_4_IRQHandler + + PUBWEAK ioss_interrupts_gpio_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_5_IRQHandler + B ioss_interrupts_gpio_5_IRQHandler + + PUBWEAK ioss_interrupts_gpio_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_6_IRQHandler + B ioss_interrupts_gpio_6_IRQHandler + + PUBWEAK ioss_interrupts_gpio_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_7_IRQHandler + B ioss_interrupts_gpio_7_IRQHandler + + PUBWEAK ioss_interrupts_gpio_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_8_IRQHandler + B ioss_interrupts_gpio_8_IRQHandler + + PUBWEAK ioss_interrupts_gpio_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_9_IRQHandler + B ioss_interrupts_gpio_9_IRQHandler + + PUBWEAK ioss_interrupts_gpio_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_10_IRQHandler + B ioss_interrupts_gpio_10_IRQHandler + + PUBWEAK ioss_interrupts_gpio_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_11_IRQHandler + B ioss_interrupts_gpio_11_IRQHandler + + PUBWEAK ioss_interrupts_gpio_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_12_IRQHandler + B ioss_interrupts_gpio_12_IRQHandler + + PUBWEAK ioss_interrupts_gpio_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_13_IRQHandler + B ioss_interrupts_gpio_13_IRQHandler + + PUBWEAK ioss_interrupts_gpio_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupts_gpio_14_IRQHandler + B ioss_interrupts_gpio_14_IRQHandler + + PUBWEAK ioss_interrupt_gpio_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_gpio_IRQHandler + B ioss_interrupt_gpio_IRQHandler + + PUBWEAK ioss_interrupt_vdd_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ioss_interrupt_vdd_IRQHandler + B ioss_interrupt_vdd_IRQHandler + + PUBWEAK lpcomp_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +lpcomp_interrupt_IRQHandler + B lpcomp_interrupt_IRQHandler + + PUBWEAK scb_8_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_8_interrupt_IRQHandler + B scb_8_interrupt_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_0_IRQHandler + B srss_interrupt_mcwdt_0_IRQHandler + + PUBWEAK srss_interrupt_mcwdt_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_mcwdt_1_IRQHandler + B srss_interrupt_mcwdt_1_IRQHandler + + PUBWEAK srss_interrupt_backup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_backup_IRQHandler + B srss_interrupt_backup_IRQHandler + + PUBWEAK srss_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +srss_interrupt_IRQHandler + B srss_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_0_IRQHandler + B cpuss_interrupts_ipc_0_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_1_IRQHandler + B cpuss_interrupts_ipc_1_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_2_IRQHandler + B cpuss_interrupts_ipc_2_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_3_IRQHandler + B cpuss_interrupts_ipc_3_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_4_IRQHandler + B cpuss_interrupts_ipc_4_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_5_IRQHandler + B cpuss_interrupts_ipc_5_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_6_IRQHandler + B cpuss_interrupts_ipc_6_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_7_IRQHandler + B cpuss_interrupts_ipc_7_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_8_IRQHandler + B cpuss_interrupts_ipc_8_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_9_IRQHandler + B cpuss_interrupts_ipc_9_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_10_IRQHandler + B cpuss_interrupts_ipc_10_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_11_IRQHandler + B cpuss_interrupts_ipc_11_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_12_IRQHandler + B cpuss_interrupts_ipc_12_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_13_IRQHandler + B cpuss_interrupts_ipc_13_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_14_IRQHandler + B cpuss_interrupts_ipc_14_IRQHandler + + PUBWEAK cpuss_interrupts_ipc_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_ipc_15_IRQHandler + B cpuss_interrupts_ipc_15_IRQHandler + + PUBWEAK scb_0_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_0_interrupt_IRQHandler + B scb_0_interrupt_IRQHandler + + PUBWEAK scb_1_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_1_interrupt_IRQHandler + B scb_1_interrupt_IRQHandler + + PUBWEAK scb_2_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_2_interrupt_IRQHandler + B scb_2_interrupt_IRQHandler + + PUBWEAK scb_3_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_3_interrupt_IRQHandler + B scb_3_interrupt_IRQHandler + + PUBWEAK scb_4_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_4_interrupt_IRQHandler + B scb_4_interrupt_IRQHandler + + PUBWEAK scb_5_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_5_interrupt_IRQHandler + B scb_5_interrupt_IRQHandler + + PUBWEAK scb_6_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_6_interrupt_IRQHandler + B scb_6_interrupt_IRQHandler + + PUBWEAK scb_7_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_7_interrupt_IRQHandler + B scb_7_interrupt_IRQHandler + + PUBWEAK scb_9_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_9_interrupt_IRQHandler + B scb_9_interrupt_IRQHandler + + PUBWEAK scb_10_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_10_interrupt_IRQHandler + B scb_10_interrupt_IRQHandler + + PUBWEAK scb_11_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_11_interrupt_IRQHandler + B scb_11_interrupt_IRQHandler + + PUBWEAK scb_12_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +scb_12_interrupt_IRQHandler + B scb_12_interrupt_IRQHandler + + PUBWEAK csd_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +csd_interrupt_IRQHandler + B csd_interrupt_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_0_IRQHandler + B cpuss_interrupts_dmac_0_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_1_IRQHandler + B cpuss_interrupts_dmac_1_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_2_IRQHandler + B cpuss_interrupts_dmac_2_IRQHandler + + PUBWEAK cpuss_interrupts_dmac_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dmac_3_IRQHandler + B cpuss_interrupts_dmac_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_0_IRQHandler + B cpuss_interrupts_dw0_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_1_IRQHandler + B cpuss_interrupts_dw0_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_2_IRQHandler + B cpuss_interrupts_dw0_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_3_IRQHandler + B cpuss_interrupts_dw0_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_4_IRQHandler + B cpuss_interrupts_dw0_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_5_IRQHandler + B cpuss_interrupts_dw0_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_6_IRQHandler + B cpuss_interrupts_dw0_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_7_IRQHandler + B cpuss_interrupts_dw0_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_8_IRQHandler + B cpuss_interrupts_dw0_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_9_IRQHandler + B cpuss_interrupts_dw0_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_10_IRQHandler + B cpuss_interrupts_dw0_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_11_IRQHandler + B cpuss_interrupts_dw0_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_12_IRQHandler + B cpuss_interrupts_dw0_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_13_IRQHandler + B cpuss_interrupts_dw0_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_14_IRQHandler + B cpuss_interrupts_dw0_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_15_IRQHandler + B cpuss_interrupts_dw0_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_16_IRQHandler + B cpuss_interrupts_dw0_16_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_17_IRQHandler + B cpuss_interrupts_dw0_17_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_18_IRQHandler + B cpuss_interrupts_dw0_18_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_19_IRQHandler + B cpuss_interrupts_dw0_19_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_20_IRQHandler + B cpuss_interrupts_dw0_20_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_21_IRQHandler + B cpuss_interrupts_dw0_21_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_22_IRQHandler + B cpuss_interrupts_dw0_22_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_23_IRQHandler + B cpuss_interrupts_dw0_23_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_24_IRQHandler + B cpuss_interrupts_dw0_24_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_25_IRQHandler + B cpuss_interrupts_dw0_25_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_26_IRQHandler + B cpuss_interrupts_dw0_26_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_27_IRQHandler + B cpuss_interrupts_dw0_27_IRQHandler + + PUBWEAK cpuss_interrupts_dw0_28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw0_28_IRQHandler + B cpuss_interrupts_dw0_28_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_0_IRQHandler + B cpuss_interrupts_dw1_0_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_1_IRQHandler + B cpuss_interrupts_dw1_1_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_2_IRQHandler + B cpuss_interrupts_dw1_2_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_3_IRQHandler + B cpuss_interrupts_dw1_3_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_4_IRQHandler + B cpuss_interrupts_dw1_4_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_5_IRQHandler + B cpuss_interrupts_dw1_5_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_6_IRQHandler + B cpuss_interrupts_dw1_6_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_7_IRQHandler + B cpuss_interrupts_dw1_7_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_8_IRQHandler + B cpuss_interrupts_dw1_8_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_9_IRQHandler + B cpuss_interrupts_dw1_9_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_10_IRQHandler + B cpuss_interrupts_dw1_10_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_11_IRQHandler + B cpuss_interrupts_dw1_11_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_12_IRQHandler + B cpuss_interrupts_dw1_12_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_13_IRQHandler + B cpuss_interrupts_dw1_13_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_14_IRQHandler + B cpuss_interrupts_dw1_14_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_15_IRQHandler + B cpuss_interrupts_dw1_15_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_16_IRQHandler + B cpuss_interrupts_dw1_16_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_17_IRQHandler + B cpuss_interrupts_dw1_17_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_18_IRQHandler + B cpuss_interrupts_dw1_18_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_19_IRQHandler + B cpuss_interrupts_dw1_19_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_20_IRQHandler + B cpuss_interrupts_dw1_20_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_21_IRQHandler + B cpuss_interrupts_dw1_21_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_22_IRQHandler + B cpuss_interrupts_dw1_22_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_23_IRQHandler + B cpuss_interrupts_dw1_23_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_24_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_24_IRQHandler + B cpuss_interrupts_dw1_24_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_25_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_25_IRQHandler + B cpuss_interrupts_dw1_25_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_26_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_26_IRQHandler + B cpuss_interrupts_dw1_26_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_27_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_27_IRQHandler + B cpuss_interrupts_dw1_27_IRQHandler + + PUBWEAK cpuss_interrupts_dw1_28_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_dw1_28_IRQHandler + B cpuss_interrupts_dw1_28_IRQHandler + + PUBWEAK cpuss_interrupts_fault_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_0_IRQHandler + B cpuss_interrupts_fault_0_IRQHandler + + PUBWEAK cpuss_interrupts_fault_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_fault_1_IRQHandler + B cpuss_interrupts_fault_1_IRQHandler + + PUBWEAK cpuss_interrupt_crypto_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_crypto_IRQHandler + B cpuss_interrupt_crypto_IRQHandler + + PUBWEAK cpuss_interrupt_fm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupt_fm_IRQHandler + B cpuss_interrupt_fm_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_fp_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_fp_IRQHandler + B cpuss_interrupts_cm4_fp_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_0_IRQHandler + B cpuss_interrupts_cm0_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm0_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm0_cti_1_IRQHandler + B cpuss_interrupts_cm0_cti_1_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_0_IRQHandler + B cpuss_interrupts_cm4_cti_0_IRQHandler + + PUBWEAK cpuss_interrupts_cm4_cti_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +cpuss_interrupts_cm4_cti_1_IRQHandler + B cpuss_interrupts_cm4_cti_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_0_IRQHandler + B tcpwm_0_interrupts_0_IRQHandler + + PUBWEAK tcpwm_0_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_1_IRQHandler + B tcpwm_0_interrupts_1_IRQHandler + + PUBWEAK tcpwm_0_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_2_IRQHandler + B tcpwm_0_interrupts_2_IRQHandler + + PUBWEAK tcpwm_0_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_3_IRQHandler + B tcpwm_0_interrupts_3_IRQHandler + + PUBWEAK tcpwm_0_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_4_IRQHandler + B tcpwm_0_interrupts_4_IRQHandler + + PUBWEAK tcpwm_0_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_5_IRQHandler + B tcpwm_0_interrupts_5_IRQHandler + + PUBWEAK tcpwm_0_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_6_IRQHandler + B tcpwm_0_interrupts_6_IRQHandler + + PUBWEAK tcpwm_0_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_0_interrupts_7_IRQHandler + B tcpwm_0_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_0_IRQHandler + B tcpwm_1_interrupts_0_IRQHandler + + PUBWEAK tcpwm_1_interrupts_1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_1_IRQHandler + B tcpwm_1_interrupts_1_IRQHandler + + PUBWEAK tcpwm_1_interrupts_2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_2_IRQHandler + B tcpwm_1_interrupts_2_IRQHandler + + PUBWEAK tcpwm_1_interrupts_3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_3_IRQHandler + B tcpwm_1_interrupts_3_IRQHandler + + PUBWEAK tcpwm_1_interrupts_4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_4_IRQHandler + B tcpwm_1_interrupts_4_IRQHandler + + PUBWEAK tcpwm_1_interrupts_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_5_IRQHandler + B tcpwm_1_interrupts_5_IRQHandler + + PUBWEAK tcpwm_1_interrupts_6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_6_IRQHandler + B tcpwm_1_interrupts_6_IRQHandler + + PUBWEAK tcpwm_1_interrupts_7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_7_IRQHandler + B tcpwm_1_interrupts_7_IRQHandler + + PUBWEAK tcpwm_1_interrupts_8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_8_IRQHandler + B tcpwm_1_interrupts_8_IRQHandler + + PUBWEAK tcpwm_1_interrupts_9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_9_IRQHandler + B tcpwm_1_interrupts_9_IRQHandler + + PUBWEAK tcpwm_1_interrupts_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_10_IRQHandler + B tcpwm_1_interrupts_10_IRQHandler + + PUBWEAK tcpwm_1_interrupts_11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_11_IRQHandler + B tcpwm_1_interrupts_11_IRQHandler + + PUBWEAK tcpwm_1_interrupts_12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_12_IRQHandler + B tcpwm_1_interrupts_12_IRQHandler + + PUBWEAK tcpwm_1_interrupts_13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_13_IRQHandler + B tcpwm_1_interrupts_13_IRQHandler + + PUBWEAK tcpwm_1_interrupts_14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_14_IRQHandler + B tcpwm_1_interrupts_14_IRQHandler + + PUBWEAK tcpwm_1_interrupts_15_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_15_IRQHandler + B tcpwm_1_interrupts_15_IRQHandler + + PUBWEAK tcpwm_1_interrupts_16_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_16_IRQHandler + B tcpwm_1_interrupts_16_IRQHandler + + PUBWEAK tcpwm_1_interrupts_17_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_17_IRQHandler + B tcpwm_1_interrupts_17_IRQHandler + + PUBWEAK tcpwm_1_interrupts_18_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_18_IRQHandler + B tcpwm_1_interrupts_18_IRQHandler + + PUBWEAK tcpwm_1_interrupts_19_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_19_IRQHandler + B tcpwm_1_interrupts_19_IRQHandler + + PUBWEAK tcpwm_1_interrupts_20_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_20_IRQHandler + B tcpwm_1_interrupts_20_IRQHandler + + PUBWEAK tcpwm_1_interrupts_21_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_21_IRQHandler + B tcpwm_1_interrupts_21_IRQHandler + + PUBWEAK tcpwm_1_interrupts_22_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_22_IRQHandler + B tcpwm_1_interrupts_22_IRQHandler + + PUBWEAK tcpwm_1_interrupts_23_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +tcpwm_1_interrupts_23_IRQHandler + B tcpwm_1_interrupts_23_IRQHandler + + PUBWEAK pass_interrupt_sar_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +pass_interrupt_sar_IRQHandler + B pass_interrupt_sar_IRQHandler + + PUBWEAK audioss_0_interrupt_i2s_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_0_interrupt_i2s_IRQHandler + B audioss_0_interrupt_i2s_IRQHandler + + PUBWEAK audioss_0_interrupt_pdm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_0_interrupt_pdm_IRQHandler + B audioss_0_interrupt_pdm_IRQHandler + + PUBWEAK audioss_1_interrupt_i2s_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +audioss_1_interrupt_i2s_IRQHandler + B audioss_1_interrupt_i2s_IRQHandler + + PUBWEAK profile_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +profile_interrupt_IRQHandler + B profile_interrupt_IRQHandler + + PUBWEAK smif_interrupt_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +smif_interrupt_IRQHandler + B smif_interrupt_IRQHandler + + PUBWEAK usb_interrupt_hi_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_hi_IRQHandler + B usb_interrupt_hi_IRQHandler + + PUBWEAK usb_interrupt_med_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_med_IRQHandler + B usb_interrupt_med_IRQHandler + + PUBWEAK usb_interrupt_lo_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +usb_interrupt_lo_IRQHandler + B usb_interrupt_lo_IRQHandler + + PUBWEAK sdhc_0_interrupt_wakeup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +sdhc_0_interrupt_wakeup_IRQHandler + B sdhc_0_interrupt_wakeup_IRQHandler + + PUBWEAK sdhc_0_interrupt_general_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +sdhc_0_interrupt_general_IRQHandler + B sdhc_0_interrupt_general_IRQHandler + + PUBWEAK sdhc_1_interrupt_wakeup_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +sdhc_1_interrupt_wakeup_IRQHandler + B sdhc_1_interrupt_wakeup_IRQHandler + + PUBWEAK sdhc_1_interrupt_general_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +sdhc_1_interrupt_general_IRQHandler + B sdhc_1_interrupt_general_IRQHandler + + + END + + +; [] END OF FILE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/system_psoc6_cm4.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/system_psoc6_cm4.c new file mode 100644 index 00000000000..0a18f50a4d4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/COMPONENT_CM4/system_psoc6_cm4.c @@ -0,0 +1,552 @@ +/***************************************************************************//** +* \file system_psoc6_cm4.c +* \version 2.60 +* +* The device system-source file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "system_psoc6.h" +#include "cy_device.h" +#include "cy_device_headers.h" +#include "cy_syslib.h" +#include "cy_wdt.h" + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + #include "cy_ipc_sema.h" + #include "cy_ipc_pipe.h" + #include "cy_ipc_drv.h" + + #if defined(CY_DEVICE_PSOC6ABLE2) + #include "cy_flash.h" + #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ + + +/******************************************************************************* +* SystemCoreClockUpdate() +*******************************************************************************/ + +/** Default HFClk frequency in Hz */ +#define CY_CLK_HFCLK0_FREQ_HZ_DEFAULT (8000000UL) + +/** Default PeriClk frequency in Hz */ +#define CY_CLK_PERICLK_FREQ_HZ_DEFAULT (4000000UL) + +/** Default SlowClk system core frequency in Hz */ +#define CY_CLK_SYSTEM_FREQ_HZ_DEFAULT (8000000UL) + +/** IMO frequency in Hz */ +#define CY_CLK_IMO_FREQ_HZ (8000000UL) + +/** HVILO frequency in Hz */ +#define CY_CLK_HVILO_FREQ_HZ (32000UL) + +/** PILO frequency in Hz */ +#define CY_CLK_PILO_FREQ_HZ (32768UL) + +/** WCO frequency in Hz */ +#define CY_CLK_WCO_FREQ_HZ (32768UL) + +/** ALTLF frequency in Hz */ +#define CY_CLK_ALTLF_FREQ_HZ (32768UL) + + +/** +* Holds the SlowClk (Cortex-M0+) or FastClk (Cortex-M4) system core clock, +* which is the system clock frequency supplied to the SysTick timer and the +* processor core clock. +* This variable implements CMSIS Core global variable. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* This variable can be used by debuggers to query the frequency +* of the debug timer or to configure the trace clock speed. +* +* \attention Compilers must be configured to avoid removing this variable in case +* the application program is not using it. Debugging systems require the variable +* to be physically present in memory so that it can be examined to configure the debugger. */ +uint32_t SystemCoreClock = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +/** Holds the HFClk0 clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_Hfclk0FreqHz = CY_CLK_HFCLK0_FREQ_HZ_DEFAULT; + +/** Holds the PeriClk clock frequency. Updated by \ref SystemCoreClockUpdate(). */ +uint32_t cy_PeriClkFreqHz = CY_CLK_PERICLK_FREQ_HZ_DEFAULT; + +/** Holds the Alternate high frequency clock in Hz. Updated by \ref SystemCoreClockUpdate(). */ +#if (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) + uint32_t cy_BleEcoClockFreqHz = CY_CLK_ALTHF_FREQ_HZ; +#endif /* (defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL)) || defined (CY_DOXYGEN) */ + +/* SCB->CPACR */ +#define SCB_CPACR_CP10_CP11_ENABLE (0xFUL << 20u) + + +/******************************************************************************* +* SystemInit() +*******************************************************************************/ + +/* CLK_FLL_CONFIG default values */ +#define CY_FB_CLK_FLL_CONFIG_VALUE (0x01000000u) +#define CY_FB_CLK_FLL_CONFIG2_VALUE (0x00020001u) +#define CY_FB_CLK_FLL_CONFIG3_VALUE (0x00002800u) +#define CY_FB_CLK_FLL_CONFIG4_VALUE (0x000000FFu) + + +/******************************************************************************* +* SystemCoreClockUpdate (void) +*******************************************************************************/ + +/* Do not use these definitions directly in your application */ +#define CY_DELAY_MS_OVERFLOW_THRESHOLD (0x8000u) +#define CY_DELAY_1K_THRESHOLD (1000u) +#define CY_DELAY_1K_MINUS_1_THRESHOLD (CY_DELAY_1K_THRESHOLD - 1u) +#define CY_DELAY_1M_THRESHOLD (1000000u) +#define CY_DELAY_1M_MINUS_1_THRESHOLD (CY_DELAY_1M_THRESHOLD - 1u) +uint32_t cy_delayFreqHz = CY_CLK_SYSTEM_FREQ_HZ_DEFAULT; + +uint32_t cy_delayFreqKhz = (CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / + CY_DELAY_1K_THRESHOLD; + +uint8_t cy_delayFreqMhz = (uint8_t)((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1M_MINUS_1_THRESHOLD) / + CY_DELAY_1M_THRESHOLD); + +uint32_t cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * + ((CY_CLK_SYSTEM_FREQ_HZ_DEFAULT + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD); + +#define CY_ROOT_PATH_SRC_IMO (0UL) +#define CY_ROOT_PATH_SRC_EXT (1UL) +#if (SRSS_ECO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ECO (2UL) +#endif /* (SRSS_ECO_PRESENT == 1U) */ +#if (SRSS_ALTHF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_ALTHF (3UL) +#endif /* (SRSS_ALTHF_PRESENT == 1U) */ +#define CY_ROOT_PATH_SRC_DSI_MUX (4UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_HVILO (16UL) +#define CY_ROOT_PATH_SRC_DSI_MUX_WCO (17UL) +#if (SRSS_ALTLF_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_ALTLF (18UL) +#endif /* (SRSS_ALTLF_PRESENT == 1U) */ +#if (SRSS_PILO_PRESENT == 1U) + #define CY_ROOT_PATH_SRC_DSI_MUX_PILO (19UL) +#endif /* (SRSS_PILO_PRESENT == 1U) */ + + +/******************************************************************************* +* Function Name: SystemInit +****************************************************************************//** +* \cond +* Initializes the system: +* - Restores FLL registers to the default state for single core devices. +* - Unlocks and disables WDT. +* - Calls Cy_PDL_Init() function to define the driver library. +* - Calls the Cy_SystemInit() function, if compiled from PSoC Creator. +* - Calls \ref SystemCoreClockUpdate(). +* \endcond +*******************************************************************************/ +void SystemInit(void) +{ + Cy_PDL_Init(CY_DEVICE_CFG); + +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Restore FLL registers to the default state as they are not restored by the ROM code */ + uint32_t copy = SRSS->CLK_FLL_CONFIG; + copy &= ~SRSS_CLK_FLL_CONFIG_FLL_ENABLE_Msk; + SRSS->CLK_FLL_CONFIG = copy; + + copy = SRSS->CLK_ROOT_SELECT[0u]; + copy &= ~SRSS_CLK_ROOT_SELECT_ROOT_DIV_Msk; /* Set ROOT_DIV = 0*/ + SRSS->CLK_ROOT_SELECT[0u] = copy; + + SRSS->CLK_FLL_CONFIG = CY_FB_CLK_FLL_CONFIG_VALUE; + SRSS->CLK_FLL_CONFIG2 = CY_FB_CLK_FLL_CONFIG2_VALUE; + SRSS->CLK_FLL_CONFIG3 = CY_FB_CLK_FLL_CONFIG3_VALUE; + SRSS->CLK_FLL_CONFIG4 = CY_FB_CLK_FLL_CONFIG4_VALUE; + + /* Unlock and disable WDT */ + Cy_WDT_Unlock(); + Cy_WDT_Disable(); + #endif /* (__CM0P_PRESENT == 0) */ +#endif /* __CM0P_PRESENT */ + + Cy_SystemInit(); + SystemCoreClockUpdate(); + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) + +#ifdef __CM0P_PRESENT + #if (__CM0P_PRESENT == 0) + /* Allocate and initialize semaphores for the system operations. */ + static uint32_t ipcSemaArray[CY_IPC_SEMA_COUNT / CY_IPC_SEMA_PER_WORD]; + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, CY_IPC_SEMA_COUNT, ipcSemaArray); + #else + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); + #endif /* (__CM0P_PRESENT) */ +#else + (void) Cy_IPC_Sema_Init(CY_IPC_CHAN_SEMA, 0ul, NULL); +#endif /* __CM0P_PRESENT */ + + + /******************************************************************************** + * + * Initializes the system pipes. The system pipes are used by BLE and Flash. + * + * If the default startup file is not used, or SystemInit() is not called in your + * project, call the following three functions prior to executing any flash or + * EmEEPROM write or erase operation: + * -# Cy_IPC_Sema_Init() + * -# Cy_IPC_Pipe_Config() + * -# Cy_IPC_Pipe_Init() + * -# Cy_Flash_Init() + * + *******************************************************************************/ + /* Create an array of endpoint structures */ + static cy_stc_ipc_pipe_ep_t systemIpcPipeEpArray[CY_IPC_MAX_ENDPOINTS]; + + Cy_IPC_Pipe_Config(systemIpcPipeEpArray); + + static cy_ipc_pipe_callback_ptr_t systemIpcPipeSysCbArray[CY_SYS_CYPIPE_CLIENT_CNT]; + + static const cy_stc_ipc_pipe_config_t systemIpcPipeConfigCm4 = + { + /* .ep0ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP0, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP0, + /* .ipcNotifierMuxNumber */ CY_SYS_INTR_CYPIPE_MUX_EP0, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM0_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP0 + }, + /* .ep1ConfigData */ + { + /* .ipcNotifierNumber */ CY_IPC_INTR_CYPIPE_EP1, + /* .ipcNotifierPriority */ CY_SYS_INTR_CYPIPE_PRIOR_EP1, + /* .ipcNotifierMuxNumber */ 0u, + /* .epAddress */ CY_IPC_EP_CYPIPE_CM4_ADDR, + /* .epConfig */ CY_SYS_CYPIPE_CONFIG_EP1 + }, + /* .endpointClientsCount */ CY_SYS_CYPIPE_CLIENT_CNT, + /* .endpointsCallbacksArray */ systemIpcPipeSysCbArray, + /* .userPipeIsrHandler */ &Cy_SysIpcPipeIsrCm4 + }; + + if (cy_device->flashPipeRequired != 0u) + { + Cy_IPC_Pipe_Init(&systemIpcPipeConfigCm4); + } + +#if defined(CY_DEVICE_PSOC6ABLE2) + Cy_Flash_Init(); +#endif /* defined(CY_DEVICE_PSOC6ABLE2) */ + +#endif /* !defined(CY_IPC_DEFAULT_CFG_DISABLE) */ +} + + +/******************************************************************************* +* Function Name: Cy_SystemInit +****************************************************************************//** +* +* The function is called during device startup. Once project compiled as part of +* the PSoC Creator project, the Cy_SystemInit() function is generated by the +* PSoC Creator. +* +* The function generated by PSoC Creator performs all of the necessary device +* configuration based on the design settings. This includes settings from the +* Design Wide Resources (DWR) such as Clocks and Pins as well as any component +* configuration that is necessary. +* +*******************************************************************************/ +__WEAK void Cy_SystemInit(void) +{ + /* Empty weak function. The actual implementation to be in the PSoC Creator + * generated strong function. + */ +} + + +/******************************************************************************* +* Function Name: SystemCoreClockUpdate +****************************************************************************//** +* +* Gets core clock frequency and updates \ref SystemCoreClock, \ref +* cy_Hfclk0FreqHz, and \ref cy_PeriClkFreqHz. +* +* Updates global variables used by the \ref Cy_SysLib_Delay(), \ref +* Cy_SysLib_DelayUs(), and \ref Cy_SysLib_DelayCycles(). +* +*******************************************************************************/ +void SystemCoreClockUpdate (void) +{ + uint32_t srcFreqHz; + uint32_t pathFreqHz; + uint32_t fastClkDiv; + uint32_t periClkDiv; + uint32_t rootPath; + uint32_t srcClk; + + /* Get root path clock for the high-frequency clock # 0 */ + rootPath = _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_MUX, SRSS->CLK_ROOT_SELECT[0u]); + + /* Get source of the root path clock */ + srcClk = _FLD2VAL(SRSS_CLK_PATH_SELECT_PATH_MUX, SRSS->CLK_PATH_SELECT[rootPath]); + + /* Get frequency of the source */ + switch (srcClk) + { + case CY_ROOT_PATH_SRC_IMO: + srcFreqHz = CY_CLK_IMO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_EXT: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + + #if (SRSS_ECO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ECO: + srcFreqHz = CY_CLK_ECO_FREQ_HZ; + break; + #endif /* (SRSS_ECO_PRESENT == 1U) */ + +#if defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_ALTHF: + srcFreqHz = cy_BleEcoClockFreqHz; + break; +#endif /* defined (CY_IP_MXBLESS) && (CY_IP_MXBLESS == 1UL) && (SRSS_ALTHF_PRESENT == 1U) */ + + case CY_ROOT_PATH_SRC_DSI_MUX: + { + uint32_t dsi_src; + dsi_src = _FLD2VAL(SRSS_CLK_DSI_SELECT_DSI_MUX, SRSS->CLK_DSI_SELECT[rootPath]); + switch (dsi_src) + { + case CY_ROOT_PATH_SRC_DSI_MUX_HVILO: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + + case CY_ROOT_PATH_SRC_DSI_MUX_WCO: + srcFreqHz = CY_CLK_WCO_FREQ_HZ; + break; + + #if (SRSS_ALTLF_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_ALTLF: + srcFreqHz = CY_CLK_ALTLF_FREQ_HZ; + break; + #endif /* (SRSS_ALTLF_PRESENT == 1U) */ + + #if (SRSS_PILO_PRESENT == 1U) + case CY_ROOT_PATH_SRC_DSI_MUX_PILO: + srcFreqHz = CY_CLK_PILO_FREQ_HZ; + break; + #endif /* (SRSS_PILO_PRESENT == 1U) */ + + default: + srcFreqHz = CY_CLK_HVILO_FREQ_HZ; + break; + } + } + break; + + default: + srcFreqHz = CY_CLK_EXT_FREQ_HZ; + break; + } + + if (rootPath == 0UL) + { + /* FLL */ + bool fllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_FLL_STATUS_LOCKED, SRSS->CLK_FLL_STATUS)); + bool fllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)); + bool fllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3)) || + (1UL == _FLD2VAL(SRSS_CLK_FLL_CONFIG3_BYPASS_SEL, SRSS->CLK_FLL_CONFIG3))); + if ((fllOutputAuto && fllLocked) || fllOutputOutput) + { + uint32_t fllMult; + uint32_t refDiv; + uint32_t outputDiv; + + fllMult = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_MULT, SRSS->CLK_FLL_CONFIG); + refDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG2_FLL_REF_DIV, SRSS->CLK_FLL_CONFIG2); + outputDiv = _FLD2VAL(SRSS_CLK_FLL_CONFIG_FLL_OUTPUT_DIV, SRSS->CLK_FLL_CONFIG) + 1UL; + + pathFreqHz = ((srcFreqHz / refDiv) * fllMult) / outputDiv; + } + else + { + pathFreqHz = srcFreqHz; + } + } + else if ((rootPath == 1UL) || (rootPath == 2UL)) + { + /* PLL */ + bool pllLocked = ( 0UL != _FLD2VAL(SRSS_CLK_PLL_STATUS_LOCKED, SRSS->CLK_PLL_STATUS[rootPath - 1UL])); + bool pllOutputOutput = ( 3UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])); + bool pllOutputAuto = ((0UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL])) || + (1UL == _FLD2VAL(SRSS_CLK_PLL_CONFIG_BYPASS_SEL, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]))); + if ((pllOutputAuto && pllLocked) || pllOutputOutput) + { + uint32_t feedbackDiv; + uint32_t referenceDiv; + uint32_t outputDiv; + + feedbackDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_FEEDBACK_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); + referenceDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_REFERENCE_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); + outputDiv = _FLD2VAL(SRSS_CLK_PLL_CONFIG_OUTPUT_DIV, SRSS->CLK_PLL_CONFIG[rootPath - 1UL]); + + pathFreqHz = ((srcFreqHz * feedbackDiv) / referenceDiv) / outputDiv; + + } + else + { + pathFreqHz = srcFreqHz; + } + } + else + { + /* Direct */ + pathFreqHz = srcFreqHz; + } + + /* Get frequency after hf_clk pre-divider */ + pathFreqHz = pathFreqHz >> _FLD2VAL(SRSS_CLK_ROOT_SELECT_ROOT_DIV, SRSS->CLK_ROOT_SELECT[0u]); + cy_Hfclk0FreqHz = pathFreqHz; + + /* Fast Clock Divider */ + fastClkDiv = 1u + _FLD2VAL(CPUSS_CM4_CLOCK_CTL_FAST_INT_DIV, CPUSS->CM4_CLOCK_CTL); + + /* Peripheral Clock Divider */ + periClkDiv = 1u + _FLD2VAL(CPUSS_CM0_CLOCK_CTL_PERI_INT_DIV, CPUSS->CM0_CLOCK_CTL); + cy_PeriClkFreqHz = pathFreqHz / periClkDiv; + + pathFreqHz = pathFreqHz / fastClkDiv; + SystemCoreClock = pathFreqHz; + + /* Sets clock frequency for Delay API */ + cy_delayFreqHz = SystemCoreClock; + cy_delayFreqMhz = (uint8_t)((cy_delayFreqHz + CY_DELAY_1M_MINUS_1_THRESHOLD) / CY_DELAY_1M_THRESHOLD); + cy_delayFreqKhz = (cy_delayFreqHz + CY_DELAY_1K_MINUS_1_THRESHOLD) / CY_DELAY_1K_THRESHOLD; + cy_delay32kMs = CY_DELAY_MS_OVERFLOW_THRESHOLD * cy_delayFreqKhz; +} + + +/******************************************************************************* +* Function Name: Cy_SystemInitFpuEnable +****************************************************************************//** +* +* Enables the FPU if it is used. The function is called from the startup file. +* +*******************************************************************************/ +void Cy_SystemInitFpuEnable(void) +{ + #if defined (__FPU_USED) && (__FPU_USED == 1U) + uint32_t interruptState; + interruptState = Cy_SysLib_EnterCriticalSection(); + SCB->CPACR |= SCB_CPACR_CP10_CP11_ENABLE; + __DSB(); + __ISB(); + Cy_SysLib_ExitCriticalSection(interruptState); + #endif /* (__FPU_USED) && (__FPU_USED == 1U) */ +} + + +#if !defined(CY_IPC_DEFAULT_CFG_DISABLE) +/******************************************************************************* +* Function Name: Cy_SysIpcPipeIsrCm4 +****************************************************************************//** +* +* This is the interrupt service routine for the system pipe. +* +*******************************************************************************/ +void Cy_SysIpcPipeIsrCm4(void) +{ + Cy_IPC_Pipe_ExecuteCallback(CY_IPC_EP_CYPIPE_CM4_ADDR); +} +#endif + + +/******************************************************************************* +* Function Name: Cy_MemorySymbols +****************************************************************************//** +* +* The intention of the function is to declare boundaries of the memories for the +* MDK compilers. For the rest of the supported compilers, this is done using +* linker configuration files. The following symbols used by the cymcuelftool. +* +*******************************************************************************/ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) +__asm void Cy_MemorySymbols(void) +{ + /* Flash */ + EXPORT __cy_memory_0_start + EXPORT __cy_memory_0_length + EXPORT __cy_memory_0_row_size + + /* Working Flash */ + EXPORT __cy_memory_1_start + EXPORT __cy_memory_1_length + EXPORT __cy_memory_1_row_size + + /* Supervisory Flash */ + EXPORT __cy_memory_2_start + EXPORT __cy_memory_2_length + EXPORT __cy_memory_2_row_size + + /* XIP */ + EXPORT __cy_memory_3_start + EXPORT __cy_memory_3_length + EXPORT __cy_memory_3_row_size + + /* eFuse */ + EXPORT __cy_memory_4_start + EXPORT __cy_memory_4_length + EXPORT __cy_memory_4_row_size + + /* Flash */ +__cy_memory_0_start EQU __cpp(CY_FLASH_BASE) +__cy_memory_0_length EQU __cpp(CY_FLASH_SIZE) +__cy_memory_0_row_size EQU 0x200 + + /* Flash region for EEPROM emulation */ +__cy_memory_1_start EQU __cpp(CY_EM_EEPROM_BASE) +__cy_memory_1_length EQU __cpp(CY_EM_EEPROM_SIZE) +__cy_memory_1_row_size EQU 0x200 + + /* Supervisory Flash */ +__cy_memory_2_start EQU __cpp(CY_SFLASH_BASE) +__cy_memory_2_length EQU __cpp(CY_SFLASH_SIZE) +__cy_memory_2_row_size EQU 0x200 + + /* XIP */ +__cy_memory_3_start EQU __cpp(CY_XIP_BASE) +__cy_memory_3_length EQU __cpp(CY_XIP_SIZE) +__cy_memory_3_row_size EQU 0x200 + + /* eFuse */ +__cy_memory_4_start EQU __cpp(0x90700000) +__cy_memory_4_length EQU __cpp(0x100000) +__cy_memory_4_row_size EQU __cpp(1) +} +#endif /* defined (__ARMCC_VERSION) && (__ARMCC_VERSION < 6010050) */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/system_psoc6.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/system_psoc6.h new file mode 100644 index 00000000000..423361f58ab --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYSBSYSKIT_01/device/system_psoc6.h @@ -0,0 +1,680 @@ +/***************************************************************************//** +* \file system_psoc6.h +* \version 2.60 +* +* \brief Device system header file. +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + + +#ifndef _SYSTEM_PSOC6_H_ +#define _SYSTEM_PSOC6_H_ + +/** +* \addtogroup group_system_config +* \{ +* Provides device startup, system configuration, and linker script files. +* The system startup provides the followings features: +* - See \ref group_system_config_device_initialization for the: +* * \ref group_system_config_dual_core_device_initialization +* * \ref group_system_config_single_core_device_initialization +* - \ref group_system_config_device_memory_definition +* - \ref group_system_config_heap_stack_config +* - \ref group_system_config_merge_apps +* - \ref group_system_config_default_handlers +* - \ref group_system_config_device_vector_table +* - \ref group_system_config_cm4_functions +* +* \section group_system_config_configuration Configuration Considerations +* +* \subsection group_system_config_device_memory_definition Device Memory Definition +* The flash and RAM allocation for each CPU is defined by the linker scripts. +* For dual-core devices, the physical flash and RAM memory is shared between the CPU cores. +* 2 KB of RAM (allocated at the end of RAM) are reserved for system use. +* For Single-Core devices the system reserves additional 80 bytes of RAM. +* Using the reserved memory area for other purposes will lead to unexpected behavior. +* +* \note The linker files provided with the PDL are generic and handle all common +* use cases. Your project may not use every section defined in the linker files. +* In that case you may see warnings during the build process. To eliminate build +* warnings in your project, you can simply comment out or remove the relevant +* code in the linker file. +* +* ARM GCC\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.ld', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.ld' and 'cy8c6xx7_cm4_dual.ld'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the +* Cy_SysEnableCM4() function call. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.ld', where 'xx' is the device group: +* \code +* flash (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 +* ram (rwx) : ORIGIN = 0x08000000, LENGTH = 0x00024000 +* \endcode +* - 'xx_cm4_dual.ld', where 'xx' is the device group: +* \code +* flash (rx) : ORIGIN = 0x10080000, LENGTH = 0x00080000 +* ram (rwx) : ORIGIN = 0x08024000, LENGTH = 0x00023800 +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the rom ORIGIN's +* value in the 'xx_cm4_dual.ld' file, where 'xx' is the device group. Do this +* by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* ARM MDK\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.scat', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.scat' and 'cy8c6xx7_cm4_dual.scat'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref +* Cy_SysEnableCM4() function call. +* +* \note The linker files provided with the PDL are generic and handle all common +* use cases. Your project may not use every section defined in the linker files. +* In that case you may see the warnings during the build process: +* L6314W (no section matches pattern) and/or L6329W +* (pattern only matches removed unused sections). In your project, you can +* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to +* the linker. You can also comment out or remove the relevant code in the linker +* file. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.scat', where 'xx' is the device group: +* \code +* #define FLASH_START 0x10000000 +* #define FLASH_SIZE 0x00080000 +* #define RAM_START 0x08000000 +* #define RAM_SIZE 0x00024000 +* \endcode +* - 'xx_cm4_dual.scat', where 'xx' is the device group: +* \code +* #define FLASH_START 0x10080000 +* #define FLASH_SIZE 0x00080000 +* #define RAM_START 0x08024000 +* #define RAM_SIZE 0x00023800 +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the FLASH_START +* value in the 'xx_cm4_dual.scat' file, +* where 'xx' is the device group. Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* IAR\n +* The flash and RAM sections for the CPU are defined in the linker files: +* 'xx_yy.icf', where 'xx' is the device group, and 'yy' is the target CPU; for example, +* 'cy8c6xx7_cm0plus.icf' and 'cy8c6xx7_cm4_dual.icf'. +* \note If the start of the Cortex-M4 application image is changed, the value +* of the of the \ref CY_CORTEX_M4_APPL_ADDR should also be changed. The +* \ref CY_CORTEX_M4_APPL_ADDR macro should be used as the parameter for the \ref +* Cy_SysEnableCM4() function call. +* +* Change the flash and RAM sizes by editing the macros value in the +* linker files for both CPUs: +* - 'xx_cm0plus.icf', where 'xx' is the device group: +* \code +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10080000; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08024000; +* \endcode +* - 'xx_cm4_dual.icf', where 'xx' is the device group: +* \code +* define symbol __ICFEDIT_region_IROM1_start__ = 0x10080000; +* define symbol __ICFEDIT_region_IROM1_end__ = 0x10100000; +* define symbol __ICFEDIT_region_IRAM1_start__ = 0x08024000; +* define symbol __ICFEDIT_region_IRAM1_end__ = 0x08047800; +* \endcode +* +* Change the value of the \ref CY_CORTEX_M4_APPL_ADDR macro to the +* __ICFEDIT_region_IROM1_start__ value in the 'xx_cm4_dual.icf' file, where 'xx' +* is the device group. Do this by either: +* - Passing the following commands to the compiler:\n +* \code -D CY_CORTEX_M4_APPL_ADDR=0x10080000 \endcode +* - Editing the \ref CY_CORTEX_M4_APPL_ADDR value in the 'system_xx.h', where +* 'xx' is device family:\n +* \code #define CY_CORTEX_M4_APPL_ADDR (0x10080000u) \endcode +* +* \subsection group_system_config_device_initialization Device Initialization +* After a power-on-reset (POR), the boot process is handled by the boot code +* from the on-chip ROM that is always executed by the Cortex-M0+ core. The boot +* code passes the control to the Cortex-M0+ startup code located in flash. +* +* \subsubsection group_system_config_dual_core_device_initialization Dual-Core Devices +* The Cortex-M0+ startup code performs the device initialization by a call to +* SystemInit() and then calls the main() function. The Cortex-M4 core is disabled +* by default. Enable the core using the \ref Cy_SysEnableCM4() function. +* See \ref group_system_config_cm4_functions for more details. +* \note Startup code executes SystemInit() function for the both Cortex-M0+ and Cortex-M4 cores. +* The function has a separate implementation on each core. +* Both function implementations unlock and disable the WDT. +* Therefore enable the WDT after both cores have been initialized. +* +* \subsubsection group_system_config_single_core_device_initialization Single-Core Devices +* The Cortex-M0+ core is not user-accessible on these devices. In this case the +* Flash Boot handles setup of the CM0+ core and starts the Cortex-M4 core. +* +* \subsection group_system_config_heap_stack_config Heap and Stack Configuration +* There are two ways to adjust heap and stack configurations: +* -# Editing source code files +* -# Specifying via command line +* +* By default, the stack size is set to 0x00001000 and the heap size is set to 0x00000400. +* +* \subsubsection group_system_config_heap_stack_config_gcc ARM GCC +* - Editing source code files\n +* The heap and stack sizes are defined in the assembler startup files +* (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). +* Change the heap and stack sizes by modifying the following lines:\n +* \code .equ Stack_Size, 0x00001000 \endcode +* \code .equ Heap_Size, 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the compiler:\n +* \code -D __STACK_SIZE=0x000000400 \endcode +* \code -D __HEAP_SIZE=0x000000100 \endcode +* +* \subsubsection group_system_config_heap_stack_config_mdk ARM MDK +* - Editing source code files\n +* The heap and stack sizes are defined in the assembler startup files +* (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* Change the heap and stack sizes by modifying the following lines:\n +* \code Stack_Size EQU 0x00001000 \endcode +* \code Heap_Size EQU 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the assembler:\n +* \code "--predefine=___STACK_SIZE SETA 0x000000400" \endcode +* \code "--predefine=__HEAP_SIZE SETA 0x000000100" \endcode +* +* \subsubsection group_system_config_heap_stack_config_iar IAR +* - Editing source code files\n +* The heap and stack sizes are defined in the linker scatter files: 'xx_yy.icf', +* where 'xx' is the device family, and 'yy' is the target CPU; for example, +* cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. +* Change the heap and stack sizes by modifying the following lines:\n +* \code Stack_Size EQU 0x00001000 \endcode +* \code Heap_Size EQU 0x00000400 \endcode +* +* - Specifying via command line\n +* Change the heap and stack sizes passing the following commands to the +* linker (including quotation marks):\n +* \code --define_symbol __STACK_SIZE=0x000000400 \endcode +* \code --define_symbol __HEAP_SIZE=0x000000100 \endcode +* +* \subsection group_system_config_merge_apps Merging CM0+ and CM4 Executables +* The CM0+ project and linker script build the CM0+ application image. Similarly, +* the CM4 linker script builds the CM4 application image. Each specifies +* locations, sizes, and contents of sections in memory. See +* \ref group_system_config_device_memory_definition for the symbols and default +* values. +* +* The cymcuelftool is invoked by a post-build command. The precise project +* setting is IDE-specific. +* +* The cymcuelftool combines the two executables. The tool examines the +* executables to ensure that memory regions either do not overlap, or contain +* identical bytes (shared). If there are no problems, it creates a new ELF file +* with the merged image, without changing any of the addresses or data. +* +* \subsection group_system_config_default_handlers Default Interrupt Handlers Definition +* The default interrupt handler functions are defined as weak functions to a dummy +* handler in the startup file. The naming convention for the interrupt handler names +* is \_IRQHandler. A default interrupt handler can be overwritten in +* user code by defining the handler function using the same name. For example: +* \code +* void scb_0_interrupt_IRQHandler(void) +*{ +* ... +*} +* \endcode +* +* \subsection group_system_config_device_vector_table Vectors Table Copy from Flash to RAM +* This process uses memory sections defined in the linker script. The startup +* code actually defines the contents of the vector table and performs the copy. +* \subsubsection group_system_config_device_vector_table_gcc ARM GCC +* The linker script file is 'xx_yy.ld', where 'xx' is the device family, and +* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.ld and cy8c6xx7_cm4_dual.ld. +* It defines sections and locations in memory.\n +* Copy interrupt vectors from flash to RAM: \n +* From: \code LONG (__Vectors) \endcode +* To: \code LONG (__ram_vectors_start__) \endcode +* Size: \code LONG (__Vectors_End - __Vectors) \endcode +* The vector table address (and the vector table itself) are defined in the +* assembler startup files (e.g. startup_psoc6_01_cm0plus.S and startup_psoc6_01_cm4.S). +* The code in these files copies the vector table from Flash to RAM. +* \subsubsection group_system_config_device_vector_table_mdk ARM MDK +* The linker script file is 'xx_yy.scat', where 'xx' is the device family, +* and 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.scat and +* cy8c6xx7_cm4_dual.scat. The linker script specifies that the vector table +* (RESET_RAM) shall be first in the RAM section.\n +* RESET_RAM represents the vector table. It is defined in the assembler startup +* files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* The code in these files copies the vector table from Flash to RAM. +* +* \subsubsection group_system_config_device_vector_table_iar IAR +* The linker script file is 'xx_yy.icf', where 'xx' is the device family, and +* 'yy' is the target CPU; for example, cy8c6xx7_cm0plus.icf and cy8c6xx7_cm4_dual.icf. +* This file defines the .intvec_ram section and its location. +* \code place at start of IRAM1_region { readwrite section .intvec_ram}; \endcode +* The vector table address (and the vector table itself) are defined in the +* assembler startup files (e.g. startup_psoc6_01_cm0plus.s and startup_psoc6_01_cm4.s). +* The code in these files copies the vector table from Flash to RAM. +* +* \section group_system_config_more_information More Information +* Refer to the PDL User Guide for the +* more details. +* +* \section group_system_config_MISRA MISRA Compliance +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
2.3RThe character sequence // shall not be used within a comment.The comments provide a useful WEB link to the documentation.
+* +* \section group_system_config_changelog Changelog +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +* +*
VersionChangesReason for Change
2.60Updated linker scripts.Provided support for new devices, updated usage of CM0p prebuilt image.
2.50Updated assembler files, C files, linker scripts.Dynamic allocated HEAP size for Arm Compiler 6, IAR 8.
2.40Updated assembler files, C files, linker scripts.Added Arm Compiler 6 support.
2.30Added assembler files, linker scripts for Mbed OS.Added Arm Mbed OS embedded operating system support.
Updated linker scripts to extend the Flash and Ram memories size available for the CM4 core.Enhanced PDL usability.
2.20Moved the Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit() functions implementation from IPC to Startup.Changed the IPC driver configuration method from compile time to run time.
2.10Added constructor attribute to SystemInit() function declaration for ARM MDK compiler. \n +* Removed $Sub$$main symbol for ARM MDK compiler. +* uVision Debugger support.
Updated description of the Startup behavior for Single-Core Devices. \n +* Added note about WDT disabling by SystemInit() function. +* Documentation improvement.
2.0Added restoring of FLL registers to the default state in SystemInit() API for single core devices. +* Single core device support. +*
Added Normal Access Restrictions, Public Key, TOC part2 and TOC part2 copy to Supervisory flash linker memory regions. \n +* Renamed 'wflash' memory region to 'em_eeprom'. +* Linker scripts usability improvement.
Added Cy_IPC_SystemSemaInit(), Cy_IPC_SystemPipeInit(), Cy_Flash_Init() functions call to SystemInit() API.Reserved system resources for internal operations.
Added clearing and releasing of IPC structure #7 (reserved for the Deep-Sleep operations) to SystemInit() API.To avoid deadlocks in case of SW or WDT reset during Deep-Sleep entering.
1.0Initial version
+* +* +* \defgroup group_system_config_macro Macro +* \{ +* \defgroup group_system_config_system_macro System +* \defgroup group_system_config_cm4_status_macro Cortex-M4 Status +* \defgroup group_system_config_user_settings_macro User Settings +* \} +* \defgroup group_system_config_functions Functions +* \{ +* \defgroup group_system_config_system_functions System +* \defgroup group_system_config_cm4_functions Cortex-M4 Control +* \} +* \defgroup group_system_config_globals Global Variables +* +* \} +*/ + +/** +* \addtogroup group_system_config_system_functions +* \{ +* \details +* The following system functions implement CMSIS Core functions. +* Refer to the [CMSIS documentation] +* (http://www.keil.com/pack/doc/CMSIS/Core/html/group__system__init__gr.html "System and Clock Configuration") +* for more details. +* \} +*/ + +#ifdef __cplusplus +extern "C" { +#endif + + +/******************************************************************************* +* Include files +*******************************************************************************/ +#include + + +/******************************************************************************* +* Global preprocessor symbols/macros ('define') +*******************************************************************************/ +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined (__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3))) + #define CY_SYSTEM_CPU_CM0P 1UL +#else + #define CY_SYSTEM_CPU_CM0P 0UL +#endif + +#if defined (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) + #include "cyfitter.h" +#endif /* (CY_PSOC_CREATOR_USED) && (CY_PSOC_CREATOR_USED == 1U) */ + + + + +/******************************************************************************* +* +* START OF USER SETTINGS HERE +* =========================== +* +* All lines with '<<<' can be set by user. +* +*******************************************************************************/ + +/** +* \addtogroup group_system_config_user_settings_macro +* \{ +*/ + +#if defined (CYDEV_CLK_EXTCLK__HZ) + #define CY_CLK_EXT_FREQ_HZ (CYDEV_CLK_EXTCLK__HZ) +#else + /***************************************************************************//** + * External Clock Frequency (in Hz, [value]UL). If compiled within + * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. + * Otherwise, edit the value below. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_EXT_FREQ_HZ (24000000UL) /* <<< 24 MHz */ +#endif /* (CYDEV_CLK_EXTCLK__HZ) */ + + +#if defined (CYDEV_CLK_ECO__HZ) + #define CY_CLK_ECO_FREQ_HZ (CYDEV_CLK_ECO__HZ) +#else + /***************************************************************************//** + * \brief External crystal oscillator frequency (in Hz, [value]UL). If compiled + * within PSoC Creator and the clock is enabled in the DWR, the value from DWR + * used. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_ECO_FREQ_HZ (24000000UL) /* <<< 24 MHz */ +#endif /* (CYDEV_CLK_ECO__HZ) */ + + +#if defined (CYDEV_CLK_ALTHF__HZ) + #define CY_CLK_ALTHF_FREQ_HZ (CYDEV_CLK_ALTHF__HZ) +#else + /***************************************************************************//** + * \brief Alternate high frequency (in Hz, [value]UL). If compiled within + * PSoC Creator and the clock is enabled in the DWR, the value from DWR used. + * Otherwise, edit the value below. + * (USER SETTING) + *******************************************************************************/ + #define CY_CLK_ALTHF_FREQ_HZ (32000000UL) /* <<< 32 MHz */ +#endif /* (CYDEV_CLK_ALTHF__HZ) */ + + +/***************************************************************************//** +* \brief Start address of the Cortex-M4 application ([address]UL) +* (USER SETTING) +*******************************************************************************/ +#if !defined (CY_CORTEX_M4_APPL_ADDR) + #define CY_CORTEX_M4_APPL_ADDR (CY_FLASH_BASE + 0x2000U) /* <<< 8 kB of flash is reserved for the Cortex-M0+ application */ +#endif /* (CY_CORTEX_M4_APPL_ADDR) */ + + +/***************************************************************************//** +* \brief IPC Semaphores allocation ([value]UL). +* (USER SETTING) +*******************************************************************************/ +#define CY_IPC_SEMA_COUNT (128UL) /* <<< This will allow 128 (4*32) semaphores */ + + +/***************************************************************************//** +* \brief IPC Pipe definitions ([value]UL). +* (USER SETTING) +*******************************************************************************/ +#define CY_IPC_MAX_ENDPOINTS (8UL) /* <<< 8 endpoints */ + + +/******************************************************************************* +* +* END OF USER SETTINGS HERE +* ========================= +* +*******************************************************************************/ + +/** \} group_system_config_user_settings_macro */ + + +/** +* \addtogroup group_system_config_system_macro +* \{ +*/ + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) + /** The Cortex-M0+ startup driver identifier */ + #define CY_STARTUP_M0P_ID ((uint32_t)((uint32_t)((0x0EU) & 0x3FFFU) << 18U)) +#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ + +#if (CY_SYSTEM_CPU_CM0P != 1UL) || defined(CY_DOXYGEN) + /** The Cortex-M4 startup driver identifier */ + #define CY_STARTUP_M4_ID ((uint32_t)((uint32_t)((0x0FU) & 0x3FFFU) << 18U)) +#endif /* (CY_SYSTEM_CPU_CM0P != 1UL) */ + +/** \} group_system_config_system_macro */ + + +/** +* \addtogroup group_system_config_system_functions +* \{ +*/ +extern void SystemInit(void); + +extern void SystemCoreClockUpdate(void); +/** \} group_system_config_system_functions */ + + +/** +* \addtogroup group_system_config_cm4_functions +* \{ +*/ +extern uint32_t Cy_SysGetCM4Status(void); +extern void Cy_SysEnableCM4(uint32_t vectorTableOffset); +extern void Cy_SysDisableCM4(void); +extern void Cy_SysRetainCM4(void); +extern void Cy_SysResetCM4(void); +/** \} group_system_config_cm4_functions */ + + +/** \cond */ +extern void Default_Handler (void); + +void Cy_SysIpcPipeIsrCm0(void); +void Cy_SysIpcPipeIsrCm4(void); + +extern void Cy_SystemInit(void); +extern void Cy_SystemInitFpuEnable(void); + +extern uint32_t cy_delayFreqHz; +extern uint32_t cy_delayFreqKhz; +extern uint8_t cy_delayFreqMhz; +extern uint32_t cy_delay32kMs; +/** \endcond */ + + +#if (CY_SYSTEM_CPU_CM0P == 1UL) || defined(CY_DOXYGEN) +/** +* \addtogroup group_system_config_cm4_status_macro +* \{ +*/ +#define CY_SYS_CM4_STATUS_ENABLED (3U) /**< The Cortex-M4 core is enabled: power on, clock on, no isolate, no reset and no retain. */ +#define CY_SYS_CM4_STATUS_DISABLED (0U) /**< The Cortex-M4 core is disabled: power off, clock off, isolate, reset and no retain. */ +#define CY_SYS_CM4_STATUS_RETAINED (2U) /**< The Cortex-M4 core is retained. power off, clock off, isolate, no reset and retain. */ +#define CY_SYS_CM4_STATUS_RESET (1U) /**< The Cortex-M4 core is in the Reset mode: clock off, no isolated, no retain and reset. */ +/** \} group_system_config_cm4_status_macro */ + +#endif /* (CY_SYSTEM_CPU_CM0P == 1UL) */ + + +/******************************************************************************* +* IPC Configuration +* ========================= +*******************************************************************************/ +/* IPC CY_PIPE default configuration */ +#define CY_SYS_CYPIPE_CLIENT_CNT (8UL) + +#define CY_SYS_INTR_CYPIPE_MUX_EP0 (1UL) /* IPC CYPRESS PIPE */ +#define CY_SYS_INTR_CYPIPE_PRIOR_EP0 (1UL) /* Notifier Priority */ +#define CY_SYS_INTR_CYPIPE_PRIOR_EP1 (1UL) /* Notifier Priority */ + +#define CY_SYS_CYPIPE_CHAN_MASK_EP0 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP0) +#define CY_SYS_CYPIPE_CHAN_MASK_EP1 (0x0001UL << CY_IPC_CHAN_CYPIPE_EP1) + + +/******************************************************************************/ +/* + * The System pipe configuration defines the IPC channel number, interrupt + * number, and the pipe interrupt mask for the endpoint. + * + * The format of the endPoint configuration + * Bits[31:16] Interrupt Mask + * Bits[15:8 ] IPC interrupt + * Bits[ 7:0 ] IPC channel + */ + +/* System Pipe addresses */ +/* CyPipe defines */ + +#define CY_SYS_CYPIPE_INTR_MASK ( CY_SYS_CYPIPE_CHAN_MASK_EP0 | CY_SYS_CYPIPE_CHAN_MASK_EP1 ) + +#define CY_SYS_CYPIPE_CONFIG_EP0 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_CYPIPE_EP0 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP0) +#define CY_SYS_CYPIPE_CONFIG_EP1 ( (CY_SYS_CYPIPE_INTR_MASK << CY_IPC_PIPE_CFG_IMASK_Pos) \ + | (CY_IPC_INTR_CYPIPE_EP1 << CY_IPC_PIPE_CFG_INTR_Pos) \ + | CY_IPC_CHAN_CYPIPE_EP1) + +/******************************************************************************/ + + +/** \addtogroup group_system_config_globals +* \{ +*/ + +extern uint32_t SystemCoreClock; +extern uint32_t cy_BleEcoClockFreqHz; +extern uint32_t cy_Hfclk0FreqHz; +extern uint32_t cy_PeriClkFreqHz; + +/** \} group_system_config_globals */ + + + +/** \cond INTERNAL */ +/******************************************************************************* +* Backward compatibility macro. The following code is DEPRECATED and must +* not be used in new projects +*******************************************************************************/ + +/* BWC defines for functions related to enter/exit critical section */ +#define Cy_SaveIRQ Cy_SysLib_EnterCriticalSection +#define Cy_RestoreIRQ Cy_SysLib_ExitCriticalSection +#define CY_SYS_INTR_CYPIPE_EP0 (CY_IPC_INTR_CYPIPE_EP0) +#define CY_SYS_INTR_CYPIPE_EP1 (CY_IPC_INTR_CYPIPE_EP1) + +/** \endcond */ + +#ifdef __cplusplus +} +#endif + +#endif /* _SYSTEM_PSOC6_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.c index 6c8154e78d5..4e48631123a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.c @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -111,7 +111,7 @@ cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t *para CY_UNUSED_PARAMETER(params); cy_en_syspm_status_t status = CY_SYSPM_FAIL; - switch (mode) + switch (mode) { case CY_SYSPM_CHECK_READY: case CY_SYSPM_CHECK_FAIL: @@ -656,7 +656,7 @@ en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd) cy_rslt_t result; /* Initialize the semaphore. This is not done in init because init is called - * in interrupt thread. cy_rtos_init_semaphore call is prohibited in + * in interrupt thread. cy_rtos_init_semaphore call is prohibited in * interrupt thread. */ if(!sema_initialized) @@ -770,16 +770,16 @@ en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd) #ifdef CY_RTOS_AWARE /* Wait for the transfer to finish. - * Acquire semaphore and wait until it will be released + * Acquire semaphore and wait until it will be released * in SDIO_IRQ: - * 1. sdio_transfer_finished_semaphore count is equal to - * zero. cy_rtos_get_semaphore waits until semaphore - * count is increased by cy_rtos_set_semaphore() in + * 1. sdio_transfer_finished_semaphore count is equal to + * zero. cy_rtos_get_semaphore waits until semaphore + * count is increased by cy_rtos_set_semaphore() in * SDIO_IRQ. - * 2. The cy_rtos_set_semaphore() increases + * 2. The cy_rtos_set_semaphore() increases * sdio_transfer_finished_semaphore count. - * 3. The cy_rtos_get_semaphore() function decreases - * sdio_transfer_finished_semaphore back to zero + * 3. The cy_rtos_get_semaphore() function decreases + * sdio_transfer_finished_semaphore back to zero * and exit. Or timeout occurs */ result = cy_rtos_get_semaphore( &sdio_transfer_finished_semaphore, 10, false ); @@ -1080,7 +1080,12 @@ void SDIO_DisableSdClk(void) void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz) { uint16_t u16Div; - u16Div = Cy_SysClk_ClkPeriGetFrequency() / u32SdClkFreqHz; + /* + * The UDB SDIO implemenation has a extra divider internally that divides the input clock to the UDB + * by 2. The desired clock frequency is hence intentionally multiplied by 2 in order to get the required + * SDIO operating frequency. + */ + u16Div = Cy_SysClk_ClkPeriGetFrequency() / (2 * u32SdClkFreqHz); Cy_SysClk_PeriphSetDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM, (u16Div-1)); } @@ -1247,10 +1252,10 @@ void SDIO_IRQ(void) { pfnCardInt_count++; } - + /* Execute card interrupt callback if neccesary */ if (0 != pfnCardInt_count) - { + { if (NULL != gstcInternalData.pstcCallBacks.pfnCardIntCb) { gstcInternalData.pstcCallBacks.pfnCardIntCb(); @@ -1277,7 +1282,7 @@ void SDIO_IRQ(void) /* CRC was bad, set the flag */ gstcInternalData.stcEvents.u8CRCError++; } - + /* Set the done flag */ #ifdef CY_RTOS_AWARE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.h index b821eb9a461..06edc747bc9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST.h @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.c index 94e533da700..a2808d37c04 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.c @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.h index bed87f55bf0..39febda5730 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW943012P6EVB_01/SDIO_HOST/SDIO_HOST_cfg.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.c index 6c8154e78d5..4e48631123a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.c @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -111,7 +111,7 @@ cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t *para CY_UNUSED_PARAMETER(params); cy_en_syspm_status_t status = CY_SYSPM_FAIL; - switch (mode) + switch (mode) { case CY_SYSPM_CHECK_READY: case CY_SYSPM_CHECK_FAIL: @@ -656,7 +656,7 @@ en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd) cy_rslt_t result; /* Initialize the semaphore. This is not done in init because init is called - * in interrupt thread. cy_rtos_init_semaphore call is prohibited in + * in interrupt thread. cy_rtos_init_semaphore call is prohibited in * interrupt thread. */ if(!sema_initialized) @@ -770,16 +770,16 @@ en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd) #ifdef CY_RTOS_AWARE /* Wait for the transfer to finish. - * Acquire semaphore and wait until it will be released + * Acquire semaphore and wait until it will be released * in SDIO_IRQ: - * 1. sdio_transfer_finished_semaphore count is equal to - * zero. cy_rtos_get_semaphore waits until semaphore - * count is increased by cy_rtos_set_semaphore() in + * 1. sdio_transfer_finished_semaphore count is equal to + * zero. cy_rtos_get_semaphore waits until semaphore + * count is increased by cy_rtos_set_semaphore() in * SDIO_IRQ. - * 2. The cy_rtos_set_semaphore() increases + * 2. The cy_rtos_set_semaphore() increases * sdio_transfer_finished_semaphore count. - * 3. The cy_rtos_get_semaphore() function decreases - * sdio_transfer_finished_semaphore back to zero + * 3. The cy_rtos_get_semaphore() function decreases + * sdio_transfer_finished_semaphore back to zero * and exit. Or timeout occurs */ result = cy_rtos_get_semaphore( &sdio_transfer_finished_semaphore, 10, false ); @@ -1080,7 +1080,12 @@ void SDIO_DisableSdClk(void) void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz) { uint16_t u16Div; - u16Div = Cy_SysClk_ClkPeriGetFrequency() / u32SdClkFreqHz; + /* + * The UDB SDIO implemenation has a extra divider internally that divides the input clock to the UDB + * by 2. The desired clock frequency is hence intentionally multiplied by 2 in order to get the required + * SDIO operating frequency. + */ + u16Div = Cy_SysClk_ClkPeriGetFrequency() / (2 * u32SdClkFreqHz); Cy_SysClk_PeriphSetDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM, (u16Div-1)); } @@ -1247,10 +1252,10 @@ void SDIO_IRQ(void) { pfnCardInt_count++; } - + /* Execute card interrupt callback if neccesary */ if (0 != pfnCardInt_count) - { + { if (NULL != gstcInternalData.pstcCallBacks.pfnCardIntCb) { gstcInternalData.pstcCallBacks.pfnCardIntCb(); @@ -1277,7 +1282,7 @@ void SDIO_IRQ(void) /* CRC was bad, set the flag */ gstcInternalData.stcEvents.u8CRCError++; } - + /* Set the done flag */ #ifdef CY_RTOS_AWARE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.h index b821eb9a461..06edc747bc9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST.h @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.c index 5232ed1701e..e89c7c74b5a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.c @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.h index ff5671844ca..60ab730b5de 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43012EVB_01/SDIO_HOST/SDIO_HOST_cfg.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST.c index 6c8154e78d5..4e48631123a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST.c @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -111,7 +111,7 @@ cy_en_syspm_status_t SDIO_DeepSleepCallback(cy_stc_syspm_callback_params_t *para CY_UNUSED_PARAMETER(params); cy_en_syspm_status_t status = CY_SYSPM_FAIL; - switch (mode) + switch (mode) { case CY_SYSPM_CHECK_READY: case CY_SYSPM_CHECK_FAIL: @@ -656,7 +656,7 @@ en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd) cy_rslt_t result; /* Initialize the semaphore. This is not done in init because init is called - * in interrupt thread. cy_rtos_init_semaphore call is prohibited in + * in interrupt thread. cy_rtos_init_semaphore call is prohibited in * interrupt thread. */ if(!sema_initialized) @@ -770,16 +770,16 @@ en_sdio_result_t SDIO_SendCommandAndWait(stc_sdio_cmd_t *pstcCmd) #ifdef CY_RTOS_AWARE /* Wait for the transfer to finish. - * Acquire semaphore and wait until it will be released + * Acquire semaphore and wait until it will be released * in SDIO_IRQ: - * 1. sdio_transfer_finished_semaphore count is equal to - * zero. cy_rtos_get_semaphore waits until semaphore - * count is increased by cy_rtos_set_semaphore() in + * 1. sdio_transfer_finished_semaphore count is equal to + * zero. cy_rtos_get_semaphore waits until semaphore + * count is increased by cy_rtos_set_semaphore() in * SDIO_IRQ. - * 2. The cy_rtos_set_semaphore() increases + * 2. The cy_rtos_set_semaphore() increases * sdio_transfer_finished_semaphore count. - * 3. The cy_rtos_get_semaphore() function decreases - * sdio_transfer_finished_semaphore back to zero + * 3. The cy_rtos_get_semaphore() function decreases + * sdio_transfer_finished_semaphore back to zero * and exit. Or timeout occurs */ result = cy_rtos_get_semaphore( &sdio_transfer_finished_semaphore, 10, false ); @@ -1080,7 +1080,12 @@ void SDIO_DisableSdClk(void) void SDIO_SetSdClkFrequency(uint32_t u32SdClkFreqHz) { uint16_t u16Div; - u16Div = Cy_SysClk_ClkPeriGetFrequency() / u32SdClkFreqHz; + /* + * The UDB SDIO implemenation has a extra divider internally that divides the input clock to the UDB + * by 2. The desired clock frequency is hence intentionally multiplied by 2 in order to get the required + * SDIO operating frequency. + */ + u16Div = Cy_SysClk_ClkPeriGetFrequency() / (2 * u32SdClkFreqHz); Cy_SysClk_PeriphSetDivider(SDIO_HOST_Internal_Clock_DIV_TYPE, SDIO_HOST_Internal_Clock_DIV_NUM, (u16Div-1)); } @@ -1247,10 +1252,10 @@ void SDIO_IRQ(void) { pfnCardInt_count++; } - + /* Execute card interrupt callback if neccesary */ if (0 != pfnCardInt_count) - { + { if (NULL != gstcInternalData.pstcCallBacks.pfnCardIntCb) { gstcInternalData.pstcCallBacks.pfnCardIntCb(); @@ -1277,7 +1282,7 @@ void SDIO_IRQ(void) /* CRC was bad, set the flag */ gstcInternalData.stcEvents.u8CRCError++; } - + /* Set the done flag */ #ifdef CY_RTOS_AWARE diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST.h index b821eb9a461..06edc747bc9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST.h @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST_cfg.c b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST_cfg.c index 94e533da700..a2808d37c04 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST_cfg.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST_cfg.c @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST_cfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST_cfg.h index bed87f55bf0..39febda5730 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST_cfg.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYW9P62S1_43438EVB_01/SDIO_HOST/SDIO_HOST_cfg.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_lp_ticker_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_lp_ticker_api.c index ac20ec6d165..eba20492214 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_lp_ticker_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_lp_ticker_api.c @@ -62,11 +62,8 @@ uint32_t lp_ticker_read(void) void lp_ticker_set_interrupt(timestamp_t timestamp) { - uint32_t delay; - delay = (uint32_t)timestamp - cyhal_lptimer_read(&cy_lptimer0); - - if (CY_RSLT_SUCCESS != cyhal_lptimer_set_match(&cy_lptimer0, delay)) { - MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_lptimer_set_time"); + if (CY_RSLT_SUCCESS != cyhal_lptimer_set_match(&cy_lptimer0, (uint32_t)timestamp)) { + MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER, MBED_ERROR_CODE_FAILED_OPERATION), "cyhal_lptimer_set_match"); } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_port_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_port_api.c index a75bf716f77..d89ccfadb57 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_port_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_port_api.c @@ -41,7 +41,7 @@ void port_init(port_t *obj, PortName port, int mask, PinDirection dir) void port_mode(port_t *obj, PinMode mode) { - gpio_t gpio = {.pin = 0, .direction = obj->direction, .drive_mode = obj->drive_mode}; + gpio_t gpio = {.direction = obj->direction, .drive_mode = obj->drive_mode}; for (uint8_t pin = 0; pin < 8; pin++) { if ((1 << pin) & obj->mask) { gpio.pin = port_pin(obj->port, pin); @@ -52,7 +52,7 @@ void port_mode(port_t *obj, PinMode mode) void port_dir(port_t *obj, PinDirection dir) { - gpio_t gpio = {.pin = 0, .direction = obj->direction, .drive_mode = obj->drive_mode}; + gpio_t gpio = {.direction = obj->direction, .drive_mode = obj->drive_mode}; for (uint8_t pin = 0; pin < 8; pin++) { if ((1 << pin) & obj->mask) { gpio.pin = port_pin(obj->port, pin); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_qspi_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_qspi_api.c index 3404dcc75d0..f747eb0f821 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_qspi_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_qspi_api.c @@ -38,7 +38,8 @@ qspi_status_t qspi_free(qspi_t *obj) qspi_status_t qspi_frequency(qspi_t *obj, int hz) { - return CY_RSLT_SUCCESS == cyhal_qspi_set_frequency(&(obj->hal_qspi), (uint32_t)hz) ? QSPI_STATUS_OK : QSPI_STATUS_ERROR; + /* Return OK since this API is not implemented in cy_hal */ + return QSPI_STATUS_OK; } static inline cyhal_qspi_bus_width_t cyhal_qspi_convert_width(qspi_bus_width_t width) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_serial_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_serial_api.c index ee9f2536cfa..820f4b43ae6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_serial_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_serial_api.c @@ -125,7 +125,6 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b break; default: MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SERIAL, MBED_ERROR_CODE_UNSUPPORTED), "Unsupported parity"); - return; } cyhal_uart_cfg_t cfg = { .data_bits = data_bits, @@ -152,11 +151,11 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) static const cyhal_uart_event_t interrupt_mask = (cyhal_uart_event_t) (CYHAL_UART_IRQ_RX_DONE | CYHAL_UART_IRQ_RX_ERROR | CYHAL_UART_IRQ_RX_NOT_EMPTY); ser->rx_event_mask = enable - ? (ser->rx_event_mask | interrupt_mask) - : (ser->rx_event_mask & ~interrupt_mask); + ? (cyhal_uart_event_t)(ser->rx_event_mask | interrupt_mask) + : (cyhal_uart_event_t)(ser->rx_event_mask & ~interrupt_mask); cyhal_uart_enable_event(&(ser->hal_obj), interrupt_mask, CYHAL_ISR_PRIORITY_DEFAULT, (bool)enable); } else if (irq == TxIrq) { - static const cyhal_uart_event_t interrupt_mask = CYHAL_UART_IRQ_TX_DONE | CYHAL_UART_IRQ_TX_ERROR | CYHAL_UART_IRQ_TX_EMPTY; + static const cyhal_uart_event_t interrupt_mask = (cyhal_uart_event_t)(CYHAL_UART_IRQ_TX_DONE | CYHAL_UART_IRQ_TX_ERROR | CYHAL_UART_IRQ_TX_EMPTY); ser->tx_event_mask = enable ? (cyhal_uart_event_t)(ser->tx_event_mask | interrupt_mask) : (cyhal_uart_event_t)(ser->tx_event_mask & ~interrupt_mask); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/cy_spi_api.c b/targets/TARGET_Cypress/TARGET_PSOC6/cy_spi_api.c index 522d9a6ec0e..f6bff0799a9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/cy_spi_api.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/cy_spi_api.c @@ -45,7 +45,6 @@ SPIName spi_get_peripheral_name(PinName mosi, PinName miso, PinName mclk) return (SPIName)CYHAL_SCB_BASE_ADDRESSES[map->inst->block_num]; } MBED_ERROR(MBED_MAKE_ERROR(MBED_MODULE_DRIVER_SPI, MBED_ERROR_CODE_FAILED_OPERATION), "SPI not found"); - return (SPIName)0; } static void cy_spi_irq_handler_internal(void *handler_arg, cyhal_spi_event_t event) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_BLESS/psoc6_cm0p_bless.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_BLESS/psoc6_cm0p_bless.c index e1f4b05da45..0e0db96a84a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_BLESS/psoc6_cm0p_bless.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_BLESS/psoc6_cm0p_bless.c @@ -41,45 +41,45 @@ const uint8_t cy_m0p_image[] = { 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0x60u, 0x05u, 0x00u, 0x08u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x3cu, 0x53u, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, + 0x00u, 0x00u, 0x00u, 0x00u, 0xb4u, 0x53u, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x64u, 0x05u, 0x00u, 0x08u, 0x3cu, 0x53u, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, + 0x64u, 0x05u, 0x00u, 0x08u, 0xb4u, 0x53u, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, 0x02u, 0x38u, 0xfcu, 0xd1u, 0xc0u, 0x46u, 0xc0u, 0x46u, 0x70u, 0x47u, 0xefu, 0xf3u, 0x10u, 0x80u, 0x72u, 0xb6u, 0x70u, 0x47u, 0x80u, 0xf3u, 0x10u, 0x88u, 0x70u, 0x47u, 0x70u, 0x47u, 0xffu, 0xf7u, 0xfdu, 0xffu, 0x72u, 0xb6u, 0x0fu, 0x4cu, 0x10u, 0x4du, 0xacu, 0x42u, 0x09u, 0xdau, 0x21u, 0x68u, 0x62u, 0x68u, 0xa3u, 0x68u, 0x04u, 0x3bu, 0x02u, 0xdbu, 0xc8u, 0x58u, 0xd0u, 0x50u, 0xfau, 0xe7u, 0x0cu, 0x34u, 0xf3u, 0xe7u, 0x0au, 0x49u, 0x0bu, 0x4au, 0x00u, 0x20u, 0x52u, 0x1au, 0x02u, 0xddu, 0x04u, 0x3au, 0x88u, 0x50u, 0xfcu, 0xdcu, 0x08u, 0x48u, 0x09u, 0x49u, - 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x02u, 0xf0u, 0x6du, 0xfcu, 0x02u, 0xf0u, 0xf9u, 0xfbu, 0xfeu, 0xe7u, - 0xb0u, 0xa1u, 0x01u, 0x10u, 0xc8u, 0xa1u, 0x01u, 0x10u, 0x60u, 0x05u, 0x00u, 0x08u, 0xc8u, 0x12u, 0x00u, 0x08u, + 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x02u, 0xf0u, 0xa9u, 0xfcu, 0x02u, 0xf0u, 0x35u, 0xfcu, 0xfeu, 0xe7u, + 0x28u, 0xa2u, 0x01u, 0x10u, 0x40u, 0xa2u, 0x01u, 0x10u, 0x60u, 0x05u, 0x00u, 0x08u, 0xccu, 0x12u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x08u, 0x08u, 0xedu, 0x00u, 0xe0u, 0xfeu, 0xe7u, 0xfeu, 0xe7u, 0x00u, 0xb5u, 0x04u, 0x20u, 0x71u, 0x46u, 0x08u, 0x42u, 0x02u, 0xd0u, 0xefu, 0xf3u, 0x09u, 0x80u, 0x01u, 0xe0u, 0xefu, 0xf3u, 0x08u, 0x80u, - 0x04u, 0x30u, 0x01u, 0xf0u, 0xfbu, 0xfeu, 0xfeu, 0xe7u, 0x10u, 0xb5u, 0x00u, 0xf0u, 0x5fu, 0xf8u, 0x10u, 0xbdu, + 0x04u, 0x30u, 0x01u, 0xf0u, 0x11u, 0xffu, 0xfeu, 0xe7u, 0x10u, 0xb5u, 0x00u, 0xf0u, 0x5fu, 0xf8u, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x00u, 0xf0u, 0x2bu, 0xfcu, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x00u, 0xf0u, 0xbfu, 0xf8u, 0x10u, 0xbdu, - 0x10u, 0xb5u, 0x06u, 0xf0u, 0x6du, 0xffu, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x0du, 0xf0u, 0x41u, 0xfdu, 0x10u, 0xbdu, - 0x10u, 0xb5u, 0x06u, 0xf0u, 0x7du, 0xffu, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x05u, 0xf0u, 0x97u, 0xf9u, 0x10u, 0xbdu, + 0x10u, 0xb5u, 0x06u, 0xf0u, 0xa9u, 0xffu, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x0du, 0xf0u, 0x7du, 0xfdu, 0x10u, 0xbdu, + 0x10u, 0xb5u, 0x06u, 0xf0u, 0xb9u, 0xffu, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x05u, 0xf0u, 0xd3u, 0xf9u, 0x10u, 0xbdu, 0xf8u, 0xb5u, 0x0fu, 0x00u, 0x01u, 0x29u, 0x03u, 0xd0u, 0x08u, 0x29u, 0x34u, 0xd0u, 0x1cu, 0x48u, 0x17u, 0xe0u, 0x03u, 0x20u, 0x01u, 0xf0u, 0xb9u, 0xfbu, 0x1bu, 0x4bu, 0x98u, 0x42u, 0xf7u, 0xd0u, 0x00u, 0xf0u, 0x3cu, 0xfbu, 0x01u, 0x28u, 0xf3u, 0xd0u, 0x02u, 0x20u, 0xffu, 0xf7u, 0xe7u, 0xffu, 0x06u, 0x00u, 0xffu, 0xf7u, 0x85u, 0xffu, - 0x15u, 0x4du, 0x28u, 0x60u, 0x05u, 0xf0u, 0x7eu, 0xf9u, 0x04u, 0x00u, 0x06u, 0x28u, 0x01u, 0xd1u, 0x00u, 0x20u, + 0x15u, 0x4du, 0x28u, 0x60u, 0x05u, 0xf0u, 0xbau, 0xf9u, 0x04u, 0x00u, 0x06u, 0x28u, 0x01u, 0xd1u, 0x00u, 0x20u, 0xf8u, 0xbdu, 0x02u, 0x2eu, 0x0du, 0xd1u, 0x03u, 0x3cu, 0xb4u, 0x43u, 0x30u, 0x00u, 0xe4u, 0xb2u, 0xffu, 0xf7u, 0xc7u, 0xffu, 0x00u, 0x2cu, 0x01u, 0xd1u, 0x00u, 0x28u, 0xf1u, 0xd0u, 0x28u, 0x68u, 0xffu, 0xf7u, 0x71u, 0xffu, 0xd4u, 0xe7u, 0x38u, 0x00u, 0xffu, 0xf7u, 0xbcu, 0xffu, 0x02u, 0x2cu, 0xf6u, 0xd0u, 0x00u, 0x28u, 0xf4u, 0xd1u, - 0x02u, 0xf0u, 0x92u, 0xf8u, 0xf1u, 0xe7u, 0x04u, 0x4bu, 0x18u, 0x68u, 0xffu, 0xf7u, 0x62u, 0xffu, 0xdeu, 0xe7u, + 0x02u, 0xf0u, 0xdau, 0xf8u, 0xf1u, 0xe7u, 0x04u, 0x4bu, 0x18u, 0x68u, 0xffu, 0xf7u, 0x62u, 0xffu, 0xdeu, 0xe7u, 0xffu, 0x00u, 0x42u, 0x00u, 0x01u, 0x01u, 0x88u, 0x00u, 0x88u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x00u, 0x28u, 0x05u, 0xd0u, 0x04u, 0x4bu, 0x18u, 0x60u, 0x00u, 0xf0u, 0x0bu, 0xfcu, 0x00u, 0x20u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x84u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x16u, 0x00u, 0x70u, 0xb5u, 0x28u, 0x4du, 0x94u, 0xb0u, 0x2eu, 0x68u, 0x00u, 0x2eu, 0x48u, 0xd0u, 0x01u, 0xacu, 0x4cu, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, - 0x04u, 0xf0u, 0xbeu, 0xf9u, 0x0au, 0x21u, 0x33u, 0x68u, 0x69u, 0x44u, 0x9au, 0x8au, 0xa2u, 0x81u, 0x5au, 0x89u, + 0x04u, 0xf0u, 0xfau, 0xf9u, 0x0au, 0x21u, 0x33u, 0x68u, 0x69u, 0x44u, 0x9au, 0x8au, 0xa2u, 0x81u, 0x5au, 0x89u, 0x22u, 0x83u, 0x9au, 0x89u, 0x62u, 0x83u, 0x1fu, 0x4au, 0xa2u, 0x83u, 0x1au, 0x89u, 0xcau, 0x87u, 0x59u, 0x1cu, 0xc8u, 0x7fu, 0x13u, 0xa9u, 0x08u, 0x70u, 0x69u, 0x46u, 0x98u, 0x7fu, 0x05u, 0x31u, 0xc8u, 0x77u, 0x69u, 0x46u, 0xd8u, 0x7fu, 0x06u, 0x31u, 0xc8u, 0x77u, 0x5bu, 0x7fu, 0xe3u, 0x77u, 0xd3u, 0x07u, 0x01u, 0xd5u, 0x05u, 0xf0u, - 0xf5u, 0xf8u, 0x2bu, 0x68u, 0x1bu, 0x68u, 0x1bu, 0x89u, 0x9bu, 0x07u, 0x01u, 0xd5u, 0x05u, 0xf0u, 0xf6u, 0xf8u, - 0x2bu, 0x68u, 0x1bu, 0x68u, 0x1bu, 0x89u, 0x1bu, 0x07u, 0x01u, 0xd5u, 0x05u, 0xf0u, 0xebu, 0xf8u, 0x07u, 0xa8u, - 0x05u, 0xf0u, 0x38u, 0xf9u, 0x00u, 0x28u, 0x0eu, 0xd1u, 0x2bu, 0x68u, 0x1bu, 0x68u, 0x9au, 0x69u, 0x59u, 0x68u, - 0x62u, 0x60u, 0x00u, 0x29u, 0x04u, 0xd0u, 0x26u, 0x30u, 0x22u, 0x22u, 0x68u, 0x44u, 0x04u, 0xf0u, 0x77u, 0xf9u, - 0x20u, 0x00u, 0x05u, 0xf0u, 0xfbu, 0xf8u, 0x14u, 0xb0u, 0x70u, 0xbdu, 0x03u, 0x48u, 0xfbu, 0xe7u, 0xc0u, 0x46u, + 0x31u, 0xf9u, 0x2bu, 0x68u, 0x1bu, 0x68u, 0x1bu, 0x89u, 0x9bu, 0x07u, 0x01u, 0xd5u, 0x05u, 0xf0u, 0x32u, 0xf9u, + 0x2bu, 0x68u, 0x1bu, 0x68u, 0x1bu, 0x89u, 0x1bu, 0x07u, 0x01u, 0xd5u, 0x05u, 0xf0u, 0x27u, 0xf9u, 0x07u, 0xa8u, + 0x05u, 0xf0u, 0x74u, 0xf9u, 0x00u, 0x28u, 0x0eu, 0xd1u, 0x2bu, 0x68u, 0x1bu, 0x68u, 0x9au, 0x69u, 0x59u, 0x68u, + 0x62u, 0x60u, 0x00u, 0x29u, 0x04u, 0xd0u, 0x26u, 0x30u, 0x22u, 0x22u, 0x68u, 0x44u, 0x04u, 0xf0u, 0xb3u, 0xf9u, + 0x20u, 0x00u, 0x05u, 0xf0u, 0x37u, 0xf9u, 0x14u, 0xb0u, 0x70u, 0xbdu, 0x03u, 0x48u, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0x84u, 0x05u, 0x00u, 0x08u, 0x03u, 0x04u, 0x00u, 0x00u, 0xffu, 0x00u, 0x16u, 0x00u, 0x10u, 0xb5u, 0x02u, 0x48u, - 0x01u, 0xf0u, 0x88u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xc0u, 0x00u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x52u, 0x4eu, + 0x01u, 0xf0u, 0xd0u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xc0u, 0x00u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x52u, 0x4eu, 0x33u, 0x68u, 0x00u, 0x2bu, 0x7du, 0xd0u, 0x9au, 0x68u, 0x00u, 0x2au, 0x7au, 0xd0u, 0x02u, 0x24u, 0x22u, 0x42u, 0x6au, 0xd1u, 0x01u, 0x21u, 0x4du, 0x4du, 0x4eu, 0x4bu, 0xecu, 0x58u, 0x0cu, 0x40u, 0x04u, 0xd0u, 0x14u, 0x00u, 0x7fu, 0x31u, 0x0cu, 0x40u, 0x00u, 0xd0u, 0x0cu, 0x00u, 0xe9u, 0x58u, 0x89u, 0x07u, 0x03u, 0xd5u, 0x04u, 0x21u, @@ -99,17 +99,17 @@ const uint8_t cy_m0p_image[] = { 0xf2u, 0xd1u, 0x70u, 0xbdu, 0xdcu, 0x60u, 0x64u, 0x24u, 0x17u, 0x4bu, 0x31u, 0x68u, 0x1au, 0x68u, 0x08u, 0x7cu, 0x13u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u, 0x43u, 0x43u, 0x10u, 0x6au, 0xb0u, 0x32u, 0x12u, 0x68u, 0x1bu, 0x18u, 0x9au, 0x18u, 0x12u, 0x68u, 0x00u, 0x2au, 0x06u, 0xdau, 0x00u, 0x2cu, 0xeau, 0xd0u, 0x01u, 0x20u, 0x01u, 0xf0u, - 0x7bu, 0xfdu, 0x01u, 0x3cu, 0xe8u, 0xe7u, 0x00u, 0x2cu, 0xe3u, 0xd0u, 0x80u, 0x22u, 0x49u, 0x7cu, 0x52u, 0x02u, + 0x91u, 0xfdu, 0x01u, 0x3cu, 0xe8u, 0xe7u, 0x00u, 0x2cu, 0xe3u, 0xd0u, 0x80u, 0x22u, 0x49u, 0x7cu, 0x52u, 0x02u, 0x8au, 0x40u, 0x12u, 0x0cu, 0x9au, 0x60u, 0xdcu, 0xe7u, 0x9cu, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x3cu, 0x40u, 0x68u, 0xf0u, 0x01u, 0x00u, 0x08u, 0x10u, 0x00u, 0x00u, 0xa8u, 0x10u, 0x00u, 0x00u, 0x34u, 0x11u, 0x00u, 0x00u, - 0x38u, 0x10u, 0x00u, 0x00u, 0x94u, 0x05u, 0x00u, 0x08u, 0xc4u, 0x12u, 0x00u, 0x08u, 0x10u, 0xb5u, 0xffu, 0xf7u, + 0x38u, 0x10u, 0x00u, 0x00u, 0x94u, 0x05u, 0x00u, 0x08u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0x83u, 0xfeu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x02u, 0xd0u, 0x00u, 0x28u, 0x00u, 0xd0u, 0x98u, 0x47u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x8cu, 0x05u, 0x00u, 0x08u, 0x00u, 0x28u, 0x05u, 0xdbu, 0x1fu, 0x23u, 0x18u, 0x40u, 0x1eu, 0x3bu, 0x83u, 0x40u, 0x01u, 0x4au, 0x13u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0x10u, 0xb5u, 0x02u, 0x4bu, 0x1bu, 0x68u, 0x98u, 0x47u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x90u, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x1eu, 0x08u, 0xd0u, 0x0cu, 0x4bu, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x45u, 0x78u, 0x01u, 0x2du, 0x02u, 0xd0u, 0xffu, 0x2du, 0x09u, 0xd0u, 0x70u, 0xbdu, 0x82u, 0x68u, 0x1au, 0x60u, 0x02u, 0xf0u, - 0x4fu, 0xfau, 0xffu, 0xf7u, 0xb3u, 0xfeu, 0x25u, 0x71u, 0xa0u, 0x60u, 0xf5u, 0xe7u, 0x03u, 0x4bu, 0x18u, 0x60u, + 0x8bu, 0xfau, 0xffu, 0xf7u, 0xb3u, 0xfeu, 0x25u, 0x71u, 0xa0u, 0x60u, 0xf5u, 0xe7u, 0x03u, 0x4bu, 0x18u, 0x60u, 0x01u, 0x23u, 0x03u, 0x71u, 0xf0u, 0xe7u, 0xc0u, 0x46u, 0x98u, 0x05u, 0x00u, 0x08u, 0x9cu, 0x05u, 0x00u, 0x08u, 0x1fu, 0x23u, 0x18u, 0x40u, 0x1eu, 0x3bu, 0x83u, 0x40u, 0x03u, 0x4au, 0xd3u, 0x67u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0xbfu, 0xf3u, 0x6fu, 0x8fu, 0x70u, 0x47u, 0xc0u, 0x46u, 0x04u, 0xe1u, 0x00u, 0xe0u, 0x10u, 0xb5u, 0x00u, 0xf0u, @@ -125,20 +125,20 @@ const uint8_t cy_m0p_image[] = { 0x98u, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x91u, 0x4cu, 0xa5u, 0x44u, 0x0bu, 0x93u, 0x90u, 0x4bu, 0x08u, 0x90u, 0x0cu, 0x00u, 0x0au, 0x92u, 0x99u, 0x42u, 0x00u, 0xd8u, 0x11u, 0xe1u, 0x80u, 0x22u, 0x8du, 0x4bu, 0xd2u, 0x05u, 0x5du, 0x69u, 0x06u, 0x93u, 0x15u, 0x40u, 0x10u, 0xd0u, 0x07u, 0x22u, 0x5bu, 0x69u, 0x13u, 0x40u, 0x02u, 0x2bu, - 0x22u, 0xd1u, 0x05u, 0x20u, 0x01u, 0xf0u, 0x5cu, 0xffu, 0x87u, 0x4bu, 0x05u, 0x00u, 0x98u, 0x42u, 0xf8u, 0xd0u, + 0x22u, 0xd1u, 0x05u, 0x20u, 0x01u, 0xf0u, 0xa4u, 0xffu, 0x87u, 0x4bu, 0x05u, 0x00u, 0x98u, 0x42u, 0xf8u, 0xd0u, 0x01u, 0x23u, 0x04u, 0x93u, 0xdbu, 0x18u, 0x03u, 0x93u, 0x1bu, 0xe0u, 0x06u, 0x9au, 0x83u, 0x4bu, 0xb0u, 0x21u, 0xd3u, 0x58u, 0xe8u, 0x22u, 0x49u, 0x05u, 0xd2u, 0x00u, 0x8au, 0x5cu, 0x1fu, 0x21u, 0x0bu, 0x40u, 0x93u, 0x42u, - 0x36u, 0xd1u, 0x01u, 0x20u, 0x01u, 0xf0u, 0x8cu, 0xffu, 0x7bu, 0x4bu, 0x05u, 0x00u, 0x98u, 0x42u, 0xf8u, 0xd0u, + 0x36u, 0xd1u, 0x01u, 0x20u, 0x01u, 0xf0u, 0xceu, 0xffu, 0x7bu, 0x4bu, 0x05u, 0x00u, 0x98u, 0x42u, 0xf8u, 0xd0u, 0x00u, 0x23u, 0x04u, 0x93u, 0x05u, 0x33u, 0xe6u, 0xe7u, 0xdbu, 0xb2u, 0x03u, 0x93u, 0x01u, 0x23u, 0x00u, 0x25u, 0x04u, 0x93u, 0xf0u, 0x23u, 0x1bu, 0x06u, 0xe3u, 0x18u, 0x5eu, 0x0au, 0x09u, 0x93u, 0x76u, 0x02u, 0x00u, 0x21u, 0x03u, 0x20u, 0x01u, 0xf0u, 0xfdu, 0xf8u, 0x00u, 0x28u, 0xf9u, 0xd1u, 0x0cu, 0xabu, 0x9bu, 0x1bu, 0x02u, 0x93u, 0x05u, 0x90u, 0x02u, 0x00u, 0x00u, 0x90u, 0x04u, 0x00u, 0x00u, 0x2du, 0x42u, 0xd0u, 0x00u, 0x2au, 0x01u, 0xd0u, - 0x01u, 0xf0u, 0x74u, 0xfcu, 0x00u, 0x21u, 0x03u, 0x20u, 0x01u, 0xf0u, 0x24u, 0xf9u, 0x00u, 0x28u, 0xf9u, 0xd1u, + 0x01u, 0xf0u, 0x8au, 0xfcu, 0x00u, 0x21u, 0x03u, 0x20u, 0x01u, 0xf0u, 0x24u, 0xf9u, 0x00u, 0x28u, 0xf9u, 0xd1u, 0x00u, 0x2du, 0x00u, 0xd1u, 0x8eu, 0xe0u, 0x66u, 0x48u, 0x8du, 0x23u, 0x9bu, 0x00u, 0x9du, 0x44u, 0xf0u, 0xbdu, 0x01u, 0x23u, 0x04u, 0x93u, 0x04u, 0x33u, 0xb6u, 0xe7u, 0x80u, 0x23u, 0x5bu, 0x05u, 0xf3u, 0x18u, 0x1bu, 0x78u, 0x02u, 0x99u, 0x8bu, 0x55u, 0x4du, 0xe0u, 0x5fu, 0x4bu, 0x9cu, 0x42u, 0x00u, 0xd0u, 0xa9u, 0xe0u, 0x00u, 0xf0u, 0x43u, 0xfeu, 0x5du, 0x4bu, 0x04u, 0x00u, 0x98u, 0x42u, 0xf9u, 0xd0u, 0x00u, 0x28u, 0x62u, 0xd1u, 0xc8u, 0x27u, - 0x0cu, 0xa9u, 0x30u, 0x00u, 0x00u, 0xf0u, 0x3cu, 0xfeu, 0x04u, 0x00u, 0x01u, 0x20u, 0x01u, 0xf0u, 0x3cu, 0xfcu, + 0x0cu, 0xa9u, 0x30u, 0x00u, 0x00u, 0xf0u, 0x3cu, 0xfeu, 0x04u, 0x00u, 0x01u, 0x20u, 0x01u, 0xf0u, 0x52u, 0xfcu, 0xa4u, 0x23u, 0xa4u, 0x22u, 0xdbu, 0x03u, 0x23u, 0x40u, 0xd2u, 0x03u, 0x93u, 0x42u, 0x52u, 0xd1u, 0x01u, 0x3fu, 0x00u, 0x2fu, 0xedu, 0xd1u, 0x51u, 0x4au, 0x02u, 0x9bu, 0x94u, 0x46u, 0x07u, 0x9eu, 0x63u, 0x44u, 0x01u, 0x9au, 0x02u, 0x93u, 0x00u, 0x2cu, 0xbau, 0xd1u, 0x00u, 0x9bu, 0x0au, 0x99u, 0x8bu, 0x42u, 0xb6u, 0xd2u, 0x80u, 0x23u, @@ -148,14 +148,14 @@ const uint8_t cy_m0p_image[] = { 0x1bu, 0x78u, 0x5bu, 0x1au, 0x59u, 0x1eu, 0x8bu, 0x41u, 0xdbu, 0xb2u, 0x01u, 0x93u, 0x00u, 0x9bu, 0x01u, 0x33u, 0x00u, 0x93u, 0x07u, 0x9bu, 0x01u, 0x36u, 0xb3u, 0x42u, 0xdeu, 0xd1u, 0x01u, 0x9bu, 0x00u, 0x2bu, 0x27u, 0xd0u, 0x05u, 0x9bu, 0x37u, 0x4au, 0x9eu, 0x18u, 0x07u, 0x9bu, 0xf6u, 0x18u, 0x0bu, 0x9bu, 0x00u, 0x2bu, 0x19u, 0xd1u, - 0xc8u, 0x27u, 0x30u, 0x00u, 0x00u, 0xf0u, 0x74u, 0xfdu, 0x04u, 0x00u, 0x01u, 0x20u, 0x01u, 0xf0u, 0xecu, 0xfbu, + 0xc8u, 0x27u, 0x30u, 0x00u, 0x00u, 0xf0u, 0x74u, 0xfdu, 0x04u, 0x00u, 0x01u, 0x20u, 0x01u, 0xf0u, 0x02u, 0xfcu, 0xa4u, 0x23u, 0xa4u, 0x22u, 0xdbu, 0x03u, 0x23u, 0x40u, 0xd2u, 0x03u, 0x93u, 0x42u, 0x93u, 0xd1u, 0x01u, 0x3fu, 0x00u, 0x2fu, 0xeeu, 0xd1u, 0x27u, 0x4bu, 0x9cu, 0x42u, 0xacu, 0xd1u, 0x00u, 0xf0u, 0xd5u, 0xfdu, 0x26u, 0x4bu, 0x04u, 0x00u, 0xf8u, 0xe7u, 0x0cu, 0xa9u, 0x30u, 0x00u, 0x00u, 0xf0u, 0x98u, 0xfdu, 0x04u, 0x00u, 0xa1u, 0xe7u, 0x01u, 0x92u, 0x9fu, 0xe7u, 0x06u, 0x9bu, 0x5bu, 0x69u, 0x5bu, 0x00u, 0x09u, 0xd5u, 0x03u, 0x9bu, 0x02u, 0x2bu, - 0x06u, 0xd1u, 0x02u, 0x20u, 0x01u, 0xf0u, 0x7cu, 0xfeu, 0x17u, 0x4bu, 0x05u, 0x00u, 0x98u, 0x42u, 0xf8u, 0xd0u, + 0x06u, 0xd1u, 0x02u, 0x20u, 0x01u, 0xf0u, 0xc4u, 0xfeu, 0x17u, 0x4bu, 0x05u, 0x00u, 0x98u, 0x42u, 0xf8u, 0xd0u, 0x06u, 0x9bu, 0x1bu, 0x68u, 0x1bu, 0x02u, 0x09u, 0xd4u, 0x04u, 0x9bu, 0x00u, 0x2bu, 0x06u, 0xd1u, 0x00u, 0x20u, - 0x01u, 0xf0u, 0xb6u, 0xfeu, 0x10u, 0x4bu, 0x05u, 0x00u, 0x98u, 0x42u, 0xf8u, 0xd0u, 0x00u, 0x2du, 0x00u, 0xd0u, + 0x01u, 0xf0u, 0xf8u, 0xfeu, 0x10u, 0x4bu, 0x05u, 0x00u, 0x98u, 0x42u, 0xf8u, 0xd0u, 0x00u, 0x2du, 0x00u, 0xd0u, 0x51u, 0xe7u, 0x14u, 0x4bu, 0x9cu, 0x42u, 0x0au, 0xd0u, 0x13u, 0x4bu, 0x9cu, 0x42u, 0x07u, 0xd0u, 0x60u, 0x42u, 0x60u, 0x41u, 0x12u, 0x4cu, 0x40u, 0x42u, 0x12u, 0x4bu, 0x20u, 0x40u, 0xc0u, 0x18u, 0x44u, 0xe7u, 0x11u, 0x48u, 0x42u, 0xe7u, 0x00u, 0x2cu, 0x00u, 0xd0u, 0x6du, 0xe7u, 0x59u, 0xe7u, 0xc0u, 0x46u, 0xccu, 0xfdu, 0xffu, 0xffu, @@ -164,37 +164,37 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0xfeu, 0xffu, 0x0fu, 0x02u, 0x00u, 0x52u, 0x00u, 0x06u, 0x00u, 0x52u, 0x00u, 0xedu, 0xffu, 0xe9u, 0xffu, 0x13u, 0x00u, 0x16u, 0x00u, 0x01u, 0x00u, 0x16u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x24u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x3au, 0x33u, 0x1bu, 0x78u, 0xa3u, 0x42u, 0x01u, 0xd8u, 0x00u, 0x20u, 0x10u, 0xbdu, 0x20u, 0x00u, 0x01u, 0xf0u, - 0xa1u, 0xf8u, 0x03u, 0x28u, 0x01u, 0xd0u, 0x01u, 0x34u, 0xf0u, 0xe7u, 0x01u, 0x20u, 0xf5u, 0xe7u, 0xc0u, 0x46u, - 0xc4u, 0x12u, 0x00u, 0x08u, 0x01u, 0x4bu, 0x18u, 0x68u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xecu, 0x00u, 0x00u, 0x08u, + 0xadu, 0xf8u, 0x03u, 0x28u, 0x01u, 0xd0u, 0x01u, 0x34u, 0xf0u, 0xe7u, 0x01u, 0x20u, 0xf5u, 0xe7u, 0xc0u, 0x46u, + 0xc8u, 0x12u, 0x00u, 0x08u, 0x01u, 0x4bu, 0x18u, 0x68u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x34u, 0x06u, 0x00u, 0x08u, 0xa0u, 0x23u, 0x03u, 0x4au, 0xdbu, 0x00u, 0xd0u, 0x58u, 0x01u, 0x23u, 0x18u, 0x40u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0xa0u, 0x23u, 0x03u, 0x4au, 0xdbu, 0x00u, 0xd0u, 0x58u, 0x03u, 0x23u, 0x18u, 0x40u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0x02u, 0x4au, 0x03u, 0x4bu, 0xd0u, 0x58u, 0xc0u, 0x0fu, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0x1cu, 0x05u, 0x00u, 0x00u, 0x10u, 0xb5u, 0x01u, 0xf0u, - 0x97u, 0xf9u, 0x10u, 0xbdu, 0x70u, 0xb5u, 0x04u, 0x00u, 0x03u, 0x20u, 0x0du, 0x00u, 0x16u, 0x00u, 0x01u, 0xf0u, + 0x45u, 0xfau, 0x10u, 0xbdu, 0x70u, 0xb5u, 0x04u, 0x00u, 0x03u, 0x20u, 0x0du, 0x00u, 0x16u, 0x00u, 0x01u, 0xf0u, 0x33u, 0xf8u, 0x05u, 0x4bu, 0x98u, 0x42u, 0x05u, 0xd0u, 0x32u, 0x00u, 0x29u, 0x00u, 0x20u, 0x00u, 0x01u, 0xf0u, - 0xd1u, 0xf8u, 0x70u, 0xbdu, 0x01u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x01u, 0x88u, 0x00u, 0x03u, 0x00u, 0x4au, 0x00u, + 0x7fu, 0xf9u, 0x70u, 0xbdu, 0x01u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x01u, 0x88u, 0x00u, 0x03u, 0x00u, 0x4au, 0x00u, 0xf8u, 0xb5u, 0x0bu, 0x00u, 0x11u, 0x00u, 0xc2u, 0x1au, 0xd5u, 0x17u, 0x54u, 0x19u, 0x6cu, 0x40u, 0x8cu, 0x42u, 0x21u, 0xd3u, 0x12u, 0x4eu, 0x12u, 0x4du, 0x4fu, 0x08u, 0x74u, 0x59u, 0xa4u, 0x05u, 0xa4u, 0x0du, 0x98u, 0x42u, - 0x0fu, 0xd9u, 0xd0u, 0x19u, 0x02u, 0xf0u, 0x20u, 0xf9u, 0x20u, 0x1au, 0xc3u, 0x43u, 0xdbu, 0x17u, 0x18u, 0x40u, + 0x0fu, 0xd9u, 0xd0u, 0x19u, 0x02u, 0xf0u, 0x5cu, 0xf9u, 0x20u, 0x1au, 0xc3u, 0x43u, 0xdbu, 0x17u, 0x18u, 0x40u, 0x73u, 0x59u, 0x82u, 0x05u, 0x9bu, 0x0au, 0x9bu, 0x02u, 0x92u, 0x0du, 0x13u, 0x43u, 0x73u, 0x51u, 0x20u, 0x1au, - 0xf8u, 0xbdu, 0xdbu, 0x19u, 0x18u, 0x1au, 0x02u, 0xf0u, 0x0fu, 0xf9u, 0x06u, 0x4bu, 0x00u, 0x19u, 0x98u, 0x42u, + 0xf8u, 0xbdu, 0xdbu, 0x19u, 0x18u, 0x1au, 0x02u, 0xf0u, 0x4bu, 0xf9u, 0x06u, 0x4bu, 0x00u, 0x19u, 0x98u, 0x42u, 0xeeu, 0xd9u, 0x18u, 0x00u, 0xecu, 0xe7u, 0x00u, 0x24u, 0x20u, 0x00u, 0xf0u, 0xe7u, 0x00u, 0x00u, 0x26u, 0x40u, 0x3cu, 0x05u, 0x00u, 0x00u, 0xffu, 0x03u, 0x00u, 0x00u, 0x80u, 0x21u, 0x10u, 0xb5u, 0x02u, 0x4bu, 0x09u, 0x02u, 0x1au, 0x68u, 0xffu, 0xf7u, 0xc5u, 0xffu, 0x10u, 0xbdu, 0xdcu, 0x00u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x01u, 0xf0u, - 0xebu, 0xfau, 0x10u, 0xbdu, 0x06u, 0x4bu, 0x10u, 0xb5u, 0x1bu, 0x68u, 0x5bu, 0x68u, 0x00u, 0x2bu, 0x06u, 0xd0u, + 0x01u, 0xfbu, 0x10u, 0xbdu, 0x06u, 0x4bu, 0x10u, 0xb5u, 0x1bu, 0x68u, 0x5bu, 0x68u, 0x00u, 0x2bu, 0x06u, 0xd0u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x00u, 0x20u, 0x18u, 0x5eu, 0xffu, 0xf7u, 0x8du, 0xfdu, 0x10u, 0xbdu, 0x98u, 0x05u, 0x00u, 0x08u, 0x07u, 0x4bu, 0x10u, 0xb5u, 0x1bu, 0x68u, 0x5bu, 0x68u, 0x00u, 0x2bu, 0x08u, 0xd0u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x05u, 0xd0u, 0x00u, 0x20u, 0x18u, 0x5eu, 0x00u, 0x28u, 0x01u, 0xdbu, 0xffu, 0xf7u, 0xafu, 0xfdu, 0x10u, 0xbdu, 0x98u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0x96u, 0xfbu, 0x10u, 0xbdu, - 0x10u, 0xb5u, 0xffu, 0xf7u, 0x96u, 0xfbu, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x01u, 0xf0u, 0xbdu, 0xfcu, 0x10u, 0xbdu, - 0x10u, 0xb5u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x08u, 0xfcu, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x03u, 0x22u, + 0x10u, 0xb5u, 0xffu, 0xf7u, 0x96u, 0xfbu, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x01u, 0xf0u, 0x05u, 0xfdu, 0x10u, 0xbdu, + 0x10u, 0xb5u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x50u, 0xfcu, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x03u, 0x22u, 0x05u, 0x49u, 0x00u, 0x20u, 0x00u, 0xf0u, 0x38u, 0xfeu, 0x43u, 0x1eu, 0x98u, 0x41u, 0x03u, 0x4bu, 0x40u, 0x42u, 0x18u, 0x40u, 0x03u, 0x4bu, 0xc0u, 0x18u, 0x10u, 0xbdu, 0x01u, 0x05u, 0x00u, 0x10u, 0xfeu, 0xffu, 0xe9u, 0xffu, 0x02u, 0x00u, 0x16u, 0x00u, 0x10u, 0xb5u, 0x0au, 0x00u, 0x00u, 0x28u, 0x09u, 0xd0u, 0xfau, 0x23u, 0xffu, 0x33u, 0x99u, 0x42u, 0x05u, 0xd8u, 0xf9u, 0x3bu, 0xffu, 0x3bu, 0x02u, 0x49u, 0xffu, 0xf7u, 0xd3u, 0xfdu, 0x10u, 0xbdu, 0x01u, 0x48u, 0xfcu, 0xe7u, 0x07u, 0x08u, 0x00u, 0x16u, 0x01u, 0x00u, 0x16u, 0x00u, 0x10u, 0xb5u, 0x0au, 0x00u, 0x00u, 0x28u, 0x08u, 0xd0u, 0xfau, 0x23u, 0xffu, 0x33u, 0x99u, 0x42u, 0x04u, 0xd8u, 0x03u, 0x49u, 0x03u, 0xf0u, - 0xceu, 0xfdu, 0x00u, 0x20u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x07u, 0x08u, 0x00u, 0x16u, + 0x0au, 0xfeu, 0x00u, 0x20u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x07u, 0x08u, 0x00u, 0x16u, 0x01u, 0x00u, 0x16u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x20u, 0x00u, 0xf0u, 0x84u, 0xfeu, 0x10u, 0xbdu, 0x00u, 0x00u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x98u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x00u, 0x20u, 0x00u, 0xf0u, 0x5eu, 0xfeu, 0x10u, 0xbdu, 0x00u, 0x00u, 0x07u, 0x4bu, 0x10u, 0xb5u, 0x01u, 0x22u, 0x19u, 0x60u, @@ -203,55 +203,55 @@ const uint8_t cy_m0p_image[] = { 0x70u, 0xb5u, 0x0bu, 0x00u, 0x15u, 0x00u, 0x00u, 0x21u, 0x02u, 0x00u, 0x01u, 0x20u, 0x00u, 0xf0u, 0xa4u, 0xfdu, 0x04u, 0x1eu, 0x03u, 0xd0u, 0x29u, 0x00u, 0x00u, 0x20u, 0x00u, 0xf0u, 0xe2u, 0xfdu, 0x20u, 0x00u, 0x70u, 0xbdu, 0x03u, 0x88u, 0xaeu, 0x20u, 0x58u, 0x43u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0xc0u, 0x18u, 0x0cu, 0x00u, 0x0au, 0x21u, - 0x02u, 0xf0u, 0x42u, 0xf8u, 0x20u, 0x80u, 0x10u, 0xbdu, 0x91u, 0xfcu, 0xffu, 0xffu, 0x00u, 0x22u, 0x83u, 0x5eu, - 0x04u, 0x48u, 0x10u, 0xb5u, 0x58u, 0x43u, 0x0cu, 0x00u, 0x03u, 0x49u, 0x02u, 0xf0u, 0xbfu, 0xf8u, 0xbdu, 0x30u, + 0x02u, 0xf0u, 0x7eu, 0xf8u, 0x20u, 0x80u, 0x10u, 0xbdu, 0x91u, 0xfcu, 0xffu, 0xffu, 0x00u, 0x22u, 0x83u, 0x5eu, + 0x04u, 0x48u, 0x10u, 0xb5u, 0x58u, 0x43u, 0x0cu, 0x00u, 0x03u, 0x49u, 0x02u, 0xf0u, 0xfbu, 0xf8u, 0xbdu, 0x30u, 0x20u, 0x80u, 0x10u, 0xbdu, 0xb5u, 0xd7u, 0xffu, 0xffu, 0x10u, 0x27u, 0x00u, 0x00u, 0xf8u, 0xb5u, 0x80u, 0x23u, 0xfau, 0x27u, 0x0eu, 0x00u, 0x01u, 0x25u, 0x1bu, 0x02u, 0x18u, 0x43u, 0x0cu, 0x4cu, 0x00u, 0x04u, 0xe0u, 0x61u, 0xbfu, 0x00u, 0x23u, 0x6cu, 0x2bu, 0x42u, 0x08u, 0xd1u, 0x00u, 0x2fu, 0x01u, 0xd1u, 0x08u, 0x48u, 0x0cu, 0xe0u, - 0x28u, 0x00u, 0x01u, 0x3fu, 0x01u, 0xf0u, 0x10u, 0xfau, 0xf3u, 0xe7u, 0x00u, 0x2fu, 0xf6u, 0xd0u, 0x00u, 0x20u, + 0x28u, 0x00u, 0x01u, 0x3fu, 0x01u, 0xf0u, 0x26u, 0xfau, 0xf3u, 0xe7u, 0x00u, 0x2fu, 0xf6u, 0xd0u, 0x00u, 0x20u, 0x23u, 0x6cu, 0x1du, 0x43u, 0x25u, 0x64u, 0xe3u, 0x6au, 0x33u, 0x80u, 0xf8u, 0xbdu, 0x00u, 0x00u, 0x3cu, 0x40u, 0x04u, 0x00u, 0x16u, 0x00u, 0x70u, 0xb5u, 0xfau, 0x26u, 0x01u, 0x25u, 0x00u, 0x04u, 0x0bu, 0x4cu, 0x01u, 0x43u, 0xe1u, 0x61u, 0xb6u, 0x00u, 0x23u, 0x6cu, 0x2bu, 0x42u, 0x08u, 0xd1u, 0x00u, 0x2eu, 0x01u, 0xd1u, 0x08u, 0x48u, - 0x0au, 0xe0u, 0x28u, 0x00u, 0x01u, 0x3eu, 0x01u, 0xf0u, 0xefu, 0xf9u, 0xf3u, 0xe7u, 0x00u, 0x2eu, 0xf6u, 0xd0u, + 0x0au, 0xe0u, 0x28u, 0x00u, 0x01u, 0x3eu, 0x01u, 0xf0u, 0x05u, 0xfau, 0xf3u, 0xe7u, 0x00u, 0x2eu, 0xf6u, 0xd0u, 0x00u, 0x20u, 0x23u, 0x6cu, 0x1du, 0x43u, 0x25u, 0x64u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x3cu, 0x40u, 0x04u, 0x00u, 0x16u, 0x00u, 0x10u, 0x23u, 0x04u, 0x49u, 0x04u, 0x4au, 0x88u, 0x58u, 0x03u, 0x43u, 0x8bu, 0x50u, 0x00u, 0x22u, 0x03u, 0x4bu, 0x1au, 0x60u, 0x70u, 0x47u, 0x00u, 0x00u, 0x3cu, 0x40u, 0x70u, 0xf0u, 0x01u, 0x00u, - 0xecu, 0x00u, 0x00u, 0x08u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0xedu, 0xffu, 0x10u, 0xbdu, 0xf0u, 0xb5u, 0x1bu, 0x4bu, + 0x34u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0xedu, 0xffu, 0x10u, 0xbdu, 0xf0u, 0xb5u, 0x1bu, 0x4bu, 0x9du, 0xb0u, 0x01u, 0xa9u, 0x0au, 0x00u, 0x18u, 0x00u, 0x70u, 0xc8u, 0x70u, 0xc2u, 0x70u, 0xc8u, 0x70u, 0xc2u, 0x70u, 0xc8u, 0x70u, 0xc2u, 0x0au, 0xacu, 0x1au, 0x00u, 0x20u, 0x00u, 0x24u, 0x32u, 0xe0u, 0xcau, 0xe0u, 0xc0u, 0xe0u, 0xcau, 0xe0u, 0xc0u, 0xe0u, 0xcau, 0xe0u, 0xc0u, 0x13u, 0xadu, 0x2au, 0x00u, 0x48u, 0x33u, 0xc1u, 0xcbu, 0xc1u, 0xc2u, 0xc1u, 0xcbu, 0xc1u, 0xc2u, 0xc1u, 0xcbu, 0xc1u, 0xc2u, 0x0du, 0x4eu, 0x33u, 0x68u, 0x98u, 0x69u, 0x01u, 0x30u, 0xffu, 0x30u, 0x00u, 0xf0u, 0x02u, 0xfcu, 0x33u, 0x68u, 0x21u, 0x00u, 0x98u, 0x69u, 0x81u, 0x30u, 0xffu, 0x30u, 0x00u, 0xf0u, 0xfbu, 0xfbu, 0x33u, 0x68u, 0x29u, 0x00u, 0x98u, 0x69u, 0x80u, 0x23u, 0x9bu, 0x00u, - 0xc0u, 0x18u, 0x00u, 0xf0u, 0xf3u, 0xfbu, 0x1du, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x68u, 0x46u, 0x00u, 0x10u, - 0xc4u, 0x12u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x89u, 0xb0u, 0x02u, 0x93u, 0x0eu, 0xabu, 0x1bu, 0x78u, 0x03u, 0x90u, + 0xc0u, 0x18u, 0x00u, 0xf0u, 0xf3u, 0xfbu, 0x1du, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x46u, 0x00u, 0x10u, + 0xc8u, 0x12u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x89u, 0xb0u, 0x02u, 0x93u, 0x0eu, 0xabu, 0x1bu, 0x78u, 0x03u, 0x90u, 0x00u, 0x91u, 0x04u, 0x92u, 0x05u, 0x93u, 0x01u, 0x28u, 0x00u, 0xd9u, 0x49u, 0xe1u, 0x03u, 0x29u, 0x00u, 0xd9u, 0x46u, 0xe1u, 0x02u, 0x9bu, 0x0cu, 0x3bu, 0x87u, 0x2bu, 0x00u, 0xd9u, 0x41u, 0xe1u, 0xfbu, 0x2au, 0x00u, 0xd9u, - 0x3eu, 0xe1u, 0xa2u, 0x4cu, 0x63u, 0x68u, 0x9bu, 0x03u, 0x01u, 0xd5u, 0x01u, 0xf0u, 0xafu, 0xfbu, 0x01u, 0x22u, + 0x3eu, 0xe1u, 0xa2u, 0x4cu, 0x63u, 0x68u, 0x9bu, 0x03u, 0x01u, 0xd5u, 0x01u, 0xf0u, 0xf7u, 0xfbu, 0x01u, 0x22u, 0x9fu, 0x4bu, 0xa0u, 0x49u, 0x1eu, 0x00u, 0x58u, 0x58u, 0x01u, 0x91u, 0x10u, 0x42u, 0x04u, 0xd0u, 0x9eu, 0x49u, 0x5bu, 0x58u, 0x13u, 0x42u, 0x00u, 0xd0u, 0x2du, 0xe1u, 0xffu, 0xf7u, 0x98u, 0xffu, 0x9bu, 0x4bu, 0x9cu, 0x4au, 0xf2u, 0x50u, 0xa0u, 0x23u, 0x02u, 0x9au, 0x1bu, 0x03u, 0x13u, 0x43u, 0x9au, 0x4au, 0xb3u, 0x50u, 0x9au, 0x4bu, 0x9au, 0x4au, 0xf2u, 0x50u, 0x9au, 0x4bu, 0x5au, 0x68u, 0x01u, 0x23u, 0x1au, 0x42u, 0x00u, 0xd0u, 0x1bu, 0xe1u, 0x98u, 0x4au, 0xb0u, 0x58u, 0x08u, 0x22u, 0x10u, 0x40u, 0x4bu, 0xd0u, 0x18u, 0x00u, 0x32u, 0x68u, 0x96u, 0x4bu, - 0x40u, 0x03u, 0x18u, 0x43u, 0x80u, 0x25u, 0x10u, 0x43u, 0x30u, 0x60u, 0x63u, 0x69u, 0xedu, 0x05u, 0x2bu, 0x42u, - 0x5bu, 0xd0u, 0x05u, 0x9bu, 0x00u, 0x2bu, 0x58u, 0xd1u, 0x01u, 0x21u, 0x03u, 0x20u, 0x01u, 0xf0u, 0x8cu, 0xfau, + 0x40u, 0x03u, 0x18u, 0x43u, 0x80u, 0x25u, 0x02u, 0x43u, 0x32u, 0x60u, 0x63u, 0x69u, 0xedu, 0x05u, 0x2bu, 0x42u, + 0x5bu, 0xd0u, 0x05u, 0x9bu, 0x00u, 0x2bu, 0x58u, 0xd1u, 0x01u, 0x21u, 0x03u, 0x20u, 0x01u, 0xf0u, 0xd4u, 0xfau, 0x8eu, 0x4bu, 0x62u, 0x69u, 0x1bu, 0x68u, 0x42u, 0x33u, 0x1bu, 0x78u, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x2au, 0x42u, 0x02u, 0xd0u, 0xa3u, 0x69u, 0x1du, 0x43u, 0xa5u, 0x61u, 0x01u, 0x9bu, 0x01u, 0x9au, 0xf7u, 0x58u, 0x88u, 0x4bu, - 0x40u, 0x20u, 0x3bu, 0x43u, 0xb3u, 0x50u, 0x01u, 0xf0u, 0x27u, 0xf9u, 0x01u, 0x23u, 0x85u, 0x4cu, 0x32u, 0x59u, - 0x1au, 0x42u, 0x08u, 0xd1u, 0x33u, 0x51u, 0x40u, 0x20u, 0x01u, 0xf0u, 0x1eu, 0xf9u, 0x03u, 0x23u, 0x40u, 0x20u, - 0x33u, 0x51u, 0x01u, 0xf0u, 0x19u, 0xf9u, 0xfau, 0x25u, 0x7fu, 0x4bu, 0x80u, 0x4cu, 0x1fu, 0x40u, 0x01u, 0x9bu, + 0x40u, 0x20u, 0x3bu, 0x43u, 0xb3u, 0x50u, 0x01u, 0xf0u, 0x3du, 0xf9u, 0x01u, 0x23u, 0x85u, 0x4cu, 0x32u, 0x59u, + 0x1au, 0x42u, 0x08u, 0xd1u, 0x33u, 0x51u, 0x40u, 0x20u, 0x01u, 0xf0u, 0x34u, 0xf9u, 0x03u, 0x23u, 0x40u, 0x20u, + 0x33u, 0x51u, 0x01u, 0xf0u, 0x2fu, 0xf9u, 0xfau, 0x25u, 0x7fu, 0x4bu, 0x80u, 0x4cu, 0x1fu, 0x40u, 0x01u, 0x9bu, 0x3cu, 0x43u, 0xf4u, 0x50u, 0xedu, 0x00u, 0x79u, 0x4bu, 0x1bu, 0x68u, 0x9au, 0x69u, 0x7cu, 0x4bu, 0xd3u, 0x58u, 0x10u, 0x22u, 0x13u, 0x42u, 0x2cu, 0xd1u, 0x00u, 0x2du, 0x25u, 0xd1u, 0x7au, 0x4cu, 0x20u, 0x00u, 0x09u, 0xb0u, - 0xf0u, 0xbdu, 0x00u, 0xf0u, 0xadu, 0xffu, 0x71u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x1du, 0xd2u, 0x6fu, 0x1bu, 0x68u, - 0x9bu, 0x18u, 0x19u, 0x68u, 0x09u, 0x0eu, 0x01u, 0x31u, 0x4bu, 0x08u, 0x18u, 0x18u, 0x01u, 0xf0u, 0xfcu, 0xfeu, - 0x71u, 0x49u, 0x88u, 0x42u, 0x02u, 0xd8u, 0x32u, 0x68u, 0x70u, 0x48u, 0xa3u, 0xe7u, 0x01u, 0xf0u, 0xf4u, 0xfeu, + 0xf0u, 0xbdu, 0x01u, 0xf0u, 0x5bu, 0xf8u, 0x71u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x1du, 0xd2u, 0x6fu, 0x1bu, 0x68u, + 0x9bu, 0x18u, 0x19u, 0x68u, 0x09u, 0x0eu, 0x01u, 0x31u, 0x4bu, 0x08u, 0x18u, 0x18u, 0x01u, 0xf0u, 0x38u, 0xffu, + 0x71u, 0x49u, 0x88u, 0x42u, 0x02u, 0xd8u, 0x32u, 0x68u, 0x70u, 0x48u, 0xa3u, 0xe7u, 0x01u, 0xf0u, 0x30u, 0xffu, 0x01u, 0x38u, 0x32u, 0x68u, 0x00u, 0x28u, 0xf7u, 0xd0u, 0x99u, 0xe7u, 0x03u, 0x23u, 0x6cu, 0x4au, 0xb1u, 0x58u, - 0x0bu, 0x43u, 0xb3u, 0x50u, 0xb0u, 0xe7u, 0x01u, 0x20u, 0x01u, 0x3du, 0x01u, 0xf0u, 0xddu, 0xf8u, 0xcau, 0xe7u, + 0x0bu, 0x43u, 0xb3u, 0x50u, 0xb0u, 0xe7u, 0x01u, 0x20u, 0x01u, 0x3du, 0x01u, 0xf0u, 0xf3u, 0xf8u, 0xcau, 0xe7u, 0x00u, 0x2du, 0xd2u, 0xd0u, 0x08u, 0x23u, 0x67u, 0x4au, 0x01u, 0x20u, 0xb1u, 0x58u, 0x0bu, 0x43u, 0xb3u, 0x50u, - 0x01u, 0xf0u, 0x06u, 0xfau, 0x00u, 0x28u, 0x02u, 0xd0u, 0x05u, 0x9bu, 0x01u, 0x2bu, 0x01u, 0xd1u, 0x62u, 0x4cu, + 0x01u, 0xf0u, 0x4eu, 0xfau, 0x00u, 0x28u, 0x02u, 0xd0u, 0x05u, 0x9bu, 0x01u, 0x2bu, 0x01u, 0xd1u, 0x62u, 0x4cu, 0x3cu, 0x43u, 0x62u, 0x4bu, 0x01u, 0x9au, 0x23u, 0x40u, 0x01u, 0x24u, 0x61u, 0x4du, 0x23u, 0x43u, 0xb3u, 0x50u, 0x49u, 0x4bu, 0xf3u, 0x58u, 0x23u, 0x42u, 0x00u, 0xd0u, 0xceu, 0xe0u, 0x00u, 0x2du, 0xb5u, 0xd0u, 0x20u, 0x00u, - 0x01u, 0x3du, 0x01u, 0xf0u, 0xb9u, 0xf8u, 0xf3u, 0xe7u, 0x01u, 0x3du, 0x00u, 0x28u, 0x00u, 0xd0u, 0xdau, 0xe0u, + 0x01u, 0x3du, 0x01u, 0xf0u, 0xcfu, 0xf8u, 0xf3u, 0xe7u, 0x01u, 0x3du, 0x00u, 0x28u, 0x00u, 0xd0u, 0xdau, 0xe0u, 0x06u, 0xabu, 0xdbu, 0x88u, 0xbbu, 0x42u, 0x00u, 0xd0u, 0xc4u, 0xe0u, 0x06u, 0xabu, 0x99u, 0x1du, 0x55u, 0x48u, 0xffu, 0xf7u, 0x84u, 0xfeu, 0x04u, 0x1eu, 0x00u, 0xd0u, 0xcdu, 0xe0u, 0x06u, 0xabu, 0xdau, 0x88u, 0x80u, 0x23u, 0xdbu, 0x00u, 0x1au, 0x42u, 0x1bu, 0xd1u, 0x0au, 0x25u, 0x01u, 0x93u, 0x80u, 0x21u, 0x4du, 0x48u, 0xc9u, 0x00u, @@ -270,12 +270,12 @@ const uint8_t cy_m0p_image[] = { 0x22u, 0x4cu, 0x33u, 0xe7u, 0x22u, 0x4cu, 0x31u, 0xe7u, 0x22u, 0x4cu, 0x2fu, 0xe7u, 0x00u, 0x00u, 0x26u, 0x40u, 0x00u, 0x00u, 0x3cu, 0x40u, 0xa0u, 0xf0u, 0x01u, 0x00u, 0xb4u, 0xf0u, 0x01u, 0x00u, 0xa4u, 0xf0u, 0x01u, 0x00u, 0x06u, 0x00u, 0x00u, 0x01u, 0xa8u, 0xf0u, 0x01u, 0x00u, 0xacu, 0xf0u, 0x01u, 0x00u, 0x01u, 0x00u, 0x01u, 0x00u, - 0xfcu, 0x00u, 0x3cu, 0x40u, 0x70u, 0xf0u, 0x01u, 0x00u, 0x04u, 0x1au, 0x00u, 0x80u, 0xc4u, 0x12u, 0x00u, 0x08u, + 0xfcu, 0x00u, 0x3cu, 0x40u, 0x70u, 0xf0u, 0x01u, 0x00u, 0x04u, 0x1au, 0x00u, 0x80u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x30u, 0x00u, 0x03u, 0x00u, 0xb0u, 0xf0u, 0x01u, 0x00u, 0xefu, 0xffu, 0xfeu, 0xffu, 0x20u, 0x00u, 0x02u, 0x00u, 0x10u, 0x40u, 0x00u, 0x00u, 0x04u, 0x00u, 0x16u, 0x00u, 0x00u, 0x09u, 0x3du, 0x00u, 0x04u, 0x0au, 0x00u, 0x80u, 0xc4u, 0xf0u, 0x01u, 0x00u, 0x68u, 0xf0u, 0x01u, 0x00u, 0x28u, 0x00u, 0x02u, 0x00u, 0xffu, 0xffu, 0xfbu, 0xffu, 0xf0u, 0x7eu, 0x0eu, 0x00u, 0x03u, 0x1eu, 0x00u, 0x00u, 0x09u, 0x1eu, 0x00u, 0x00u, 0x00u, 0x48u, 0xe8u, 0x01u, - 0xecu, 0x00u, 0x00u, 0x08u, 0x64u, 0xf0u, 0x01u, 0x00u, 0x00u, 0x24u, 0xf4u, 0x00u, 0x01u, 0x00u, 0x16u, 0x00u, + 0x34u, 0x06u, 0x00u, 0x08u, 0x64u, 0xf0u, 0x01u, 0x00u, 0x00u, 0x24u, 0xf4u, 0x00u, 0x01u, 0x00u, 0x16u, 0x00u, 0x03u, 0x00u, 0x16u, 0x00u, 0x02u, 0x00u, 0x16u, 0x00u, 0x00u, 0x2du, 0x00u, 0xd1u, 0xe5u, 0xe6u, 0xc0u, 0x27u, 0x0au, 0x25u, 0x7fu, 0x01u, 0xc0u, 0x21u, 0x3bu, 0x48u, 0x49u, 0x01u, 0xffu, 0xf7u, 0xe3u, 0xfdu, 0x04u, 0x1eu, 0x6cu, 0xd1u, 0x06u, 0xabu, 0x99u, 0x1du, 0x37u, 0x48u, 0xffu, 0xf7u, 0xb8u, 0xfdu, 0x04u, 0x00u, 0x00u, 0x2du, @@ -291,15 +291,15 @@ const uint8_t cy_m0p_image[] = { 0x93u, 0x43u, 0x19u, 0x43u, 0x31u, 0x80u, 0xffu, 0xf7u, 0x8du, 0xfdu, 0x04u, 0x00u, 0x00u, 0x2cu, 0x00u, 0xd0u, 0x84u, 0xe6u, 0x04u, 0x9bu, 0x12u, 0x49u, 0x5bu, 0x00u, 0x19u, 0x43u, 0x89u, 0xb2u, 0x11u, 0x48u, 0xffu, 0xf7u, 0x81u, 0xfdu, 0x04u, 0x1eu, 0x04u, 0xd1u, 0x10u, 0x49u, 0x10u, 0x48u, 0xffu, 0xf7u, 0x7bu, 0xfdu, 0x04u, 0x00u, - 0x02u, 0x9bu, 0x58u, 0x01u, 0x80u, 0xb2u, 0x00u, 0xf0u, 0x77u, 0xffu, 0x6fu, 0xe6u, 0x00u, 0x2du, 0x99u, 0xd0u, + 0x02u, 0x9bu, 0x58u, 0x01u, 0x80u, 0xb2u, 0x00u, 0xf0u, 0x8du, 0xffu, 0x6fu, 0xe6u, 0x00u, 0x2du, 0x99u, 0xd0u, 0x99u, 0xe7u, 0xc0u, 0x46u, 0x02u, 0x1eu, 0x00u, 0x00u, 0x04u, 0x00u, 0x16u, 0x00u, 0x16u, 0x18u, 0x00u, 0x00u, 0x07u, 0x1eu, 0x00u, 0x00u, 0x7fu, 0xf5u, 0xffu, 0xffu, 0xffu, 0xe7u, 0xffu, 0xffu, 0x06u, 0x1eu, 0x00u, 0x00u, 0x01u, 0x10u, 0x00u, 0x00u, 0x08u, 0x1eu, 0x00u, 0x00u, 0x37u, 0x68u, 0x00u, 0x00u, 0x0fu, 0x1eu, 0x00u, 0x00u, 0x13u, 0xb5u, 0x00u, 0x28u, 0x08u, 0xd0u, 0x00u, 0x24u, 0x03u, 0x78u, 0x42u, 0x78u, 0xc1u, 0x78u, 0x80u, 0x78u, 0x00u, 0x94u, 0xffu, 0xf7u, 0xbfu, 0xfdu, 0x16u, 0xbdu, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x00u, 0x16u, 0x00u, - 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xc4u, 0x12u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, + 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, 0x50u, 0x43u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, - 0xc4u, 0x12u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, 0x40u, 0x28u, 0x2fu, 0xd0u, + 0xc8u, 0x12u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, 0x40u, 0x28u, 0x2fu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x30u, 0xd0u, 0x10u, 0x28u, 0x28u, 0xd0u, 0x19u, 0x48u, 0x1eu, 0xe0u, 0x80u, 0x28u, 0x28u, 0xd0u, 0x80u, 0x23u, 0x5bu, 0x00u, 0x98u, 0x42u, 0xf7u, 0xd1u, 0x14u, 0x48u, 0x16u, 0xe0u, 0x15u, 0x4bu, 0x98u, 0x42u, 0x14u, 0xd0u, 0x08u, 0xd8u, 0xa0u, 0x23u, 0x1bu, 0x06u, 0x98u, 0x42u, 0x1cu, 0xd0u, 0x12u, 0x4bu, @@ -310,78 +310,78 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0x00u, 0x52u, 0x00u, 0x01u, 0x00u, 0x00u, 0xf0u, 0x09u, 0x00u, 0x00u, 0xa0u, 0x04u, 0x00u, 0x00u, 0xf0u, 0x05u, 0x00u, 0x00u, 0xf0u, 0x03u, 0x00u, 0x00u, 0xf0u, 0x01u, 0x00u, 0x52u, 0x00u, 0x02u, 0x00u, 0x52u, 0x00u, 0x03u, 0x00u, 0x52u, 0x00u, 0x01u, 0x00u, 0x50u, 0x00u, 0x02u, 0x00u, 0x50u, 0x00u, 0x05u, 0x00u, 0x52u, 0x00u, - 0x10u, 0xb5u, 0x00u, 0x20u, 0x00u, 0xf0u, 0x8cu, 0xfdu, 0x0bu, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x1du, 0xd2u, 0x6fu, + 0x10u, 0xb5u, 0x00u, 0x20u, 0x00u, 0xf0u, 0x3au, 0xfeu, 0x0bu, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x1du, 0xd2u, 0x6fu, 0x1bu, 0x68u, 0x9bu, 0x18u, 0x19u, 0x68u, 0x1cu, 0x68u, 0x09u, 0x0eu, 0x01u, 0x31u, 0x4bu, 0x08u, 0x18u, 0x18u, - 0x01u, 0xf0u, 0xdau, 0xfcu, 0x24u, 0x0au, 0xe4u, 0xb2u, 0x01u, 0x34u, 0x63u, 0x08u, 0xc0u, 0x18u, 0x21u, 0x00u, - 0x01u, 0xf0u, 0xd2u, 0xfcu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xc4u, 0x12u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x00u, 0x20u, + 0x01u, 0xf0u, 0x16u, 0xfdu, 0x24u, 0x0au, 0xe4u, 0xb2u, 0x01u, 0x34u, 0x63u, 0x08u, 0xc0u, 0x18u, 0x21u, 0x00u, + 0x01u, 0xf0u, 0x0eu, 0xfdu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x7cu, 0xffu, 0x0au, 0x4bu, 0x1cu, 0x68u, 0x23u, 0x00u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x0au, 0xdbu, 0x07u, 0x4bu, 0x18u, 0x68u, 0xffu, 0xf7u, 0x7bu, 0xffu, 0x01u, 0x22u, 0x63u, 0x68u, 0x9au, 0x60u, 0x9au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, - 0xc4u, 0x12u, 0x00u, 0x08u, 0xa0u, 0x05u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x0du, 0x4bu, 0x10u, 0xb5u, + 0xc8u, 0x12u, 0x00u, 0x08u, 0xa0u, 0x05u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x0du, 0x4bu, 0x10u, 0xb5u, 0x18u, 0x60u, 0x00u, 0x28u, 0x04u, 0xd0u, 0xfeu, 0x23u, 0x5bu, 0x42u, 0x03u, 0x80u, 0x00u, 0x23u, 0x43u, 0x80u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0x4cu, 0x32u, 0x12u, 0x78u, 0x00u, 0x2au, 0x08u, 0xd0u, 0x4du, 0x33u, 0x1bu, 0x78u, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x02u, 0x22u, 0x04u, 0x49u, 0x00u, 0x20u, 0x00u, 0xf0u, 0x14u, 0xfau, - 0x10u, 0xbdu, 0xc0u, 0x46u, 0xb0u, 0x05u, 0x00u, 0x08u, 0xc4u, 0x12u, 0x00u, 0x08u, 0xb1u, 0x02u, 0x00u, 0x08u, + 0x10u, 0xbdu, 0xc0u, 0x46u, 0xb0u, 0x05u, 0x00u, 0x08u, 0xc8u, 0x12u, 0x00u, 0x08u, 0xadu, 0x02u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x02u, 0x48u, 0xffu, 0xf7u, 0xdau, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x05u, 0x00u, 0x08u, - 0x10u, 0xb5u, 0xc3u, 0x05u, 0x04u, 0x00u, 0x00u, 0x2bu, 0x29u, 0xd1u, 0x01u, 0xf0u, 0x99u, 0xfbu, 0xe0u, 0x22u, + 0x10u, 0xb5u, 0xc3u, 0x05u, 0x04u, 0x00u, 0x00u, 0x2bu, 0x29u, 0xd1u, 0x01u, 0xf0u, 0xd5u, 0xfbu, 0xe0u, 0x22u, 0x14u, 0x4bu, 0x52u, 0x05u, 0x1au, 0x60u, 0x14u, 0x4au, 0x12u, 0x78u, 0x00u, 0x2au, 0x04u, 0xd0u, 0x80u, 0x22u, 0x19u, 0x68u, 0x52u, 0x00u, 0x0au, 0x43u, 0x1au, 0x60u, 0x5cu, 0x60u, 0x00u, 0x24u, 0x9cu, 0x60u, 0xdcu, 0x60u, 0x0eu, 0x4bu, 0x1bu, 0x68u, 0x50u, 0x33u, 0x18u, 0x78u, 0x01u, 0x00u, 0xa0u, 0x42u, 0x0cu, 0xd0u, 0xffu, 0xf7u, - 0x77u, 0xffu, 0xfau, 0x21u, 0x89u, 0x00u, 0x01u, 0xf0u, 0x5fu, 0xfcu, 0x01u, 0x00u, 0x08u, 0x48u, 0x01u, 0xf0u, - 0x5bu, 0xfcu, 0x08u, 0x4bu, 0xc1u, 0x18u, 0x20u, 0x00u, 0x03u, 0xf0u, 0xb6u, 0xf9u, 0x10u, 0xbdu, 0x06u, 0x48u, - 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xa0u, 0x05u, 0x00u, 0x08u, 0x0bu, 0x00u, 0x00u, 0x16u, 0xc4u, 0x12u, 0x00u, 0x08u, + 0x77u, 0xffu, 0xfau, 0x21u, 0x89u, 0x00u, 0x01u, 0xf0u, 0x9bu, 0xfcu, 0x01u, 0x00u, 0x08u, 0x48u, 0x01u, 0xf0u, + 0x97u, 0xfcu, 0x08u, 0x4bu, 0xc1u, 0x18u, 0x20u, 0x00u, 0x03u, 0xf0u, 0xfau, 0xf9u, 0x10u, 0xbdu, 0x06u, 0x48u, + 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xa0u, 0x05u, 0x00u, 0x08u, 0x0bu, 0x00u, 0x00u, 0x16u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x60u, 0xf5u, 0x90u, 0x00u, 0x98u, 0x08u, 0x00u, 0x00u, 0x06u, 0x00u, 0x52u, 0x00u, 0x70u, 0xb5u, 0xc4u, 0x05u, - 0x06u, 0x00u, 0x0du, 0x00u, 0xe4u, 0x0du, 0x20u, 0xd1u, 0x00u, 0x29u, 0x1eu, 0xd0u, 0x01u, 0xf0u, 0x58u, 0xfbu, + 0x06u, 0x00u, 0x0du, 0x00u, 0xe4u, 0x0du, 0x20u, 0xd1u, 0x00u, 0x29u, 0x1eu, 0xd0u, 0x01u, 0xf0u, 0x94u, 0xfbu, 0x0fu, 0x4bu, 0x10u, 0x4au, 0x1au, 0x60u, 0x5cu, 0x60u, 0x9eu, 0x60u, 0xddu, 0x60u, 0x0eu, 0x4bu, 0x1bu, 0x68u, 0x4eu, 0x33u, 0x19u, 0x78u, 0x00u, 0x29u, 0x0bu, 0xd0u, 0xffu, 0xf7u, 0x42u, 0xffu, 0xfau, 0x21u, 0x89u, 0x00u, - 0x01u, 0xf0u, 0x2au, 0xfcu, 0x01u, 0x00u, 0x09u, 0x48u, 0x01u, 0xf0u, 0x26u, 0xfcu, 0x08u, 0x4bu, 0xc1u, 0x18u, - 0x80u, 0x20u, 0x40u, 0x00u, 0x03u, 0xf0u, 0x80u, 0xf9u, 0x70u, 0xbdu, 0x06u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, - 0xa0u, 0x05u, 0x00u, 0x08u, 0x00u, 0x01u, 0x00u, 0x05u, 0xc4u, 0x12u, 0x00u, 0x08u, 0xc0u, 0xeau, 0x21u, 0x01u, + 0x01u, 0xf0u, 0x66u, 0xfcu, 0x01u, 0x00u, 0x09u, 0x48u, 0x01u, 0xf0u, 0x62u, 0xfcu, 0x08u, 0x4bu, 0xc1u, 0x18u, + 0x80u, 0x20u, 0x40u, 0x00u, 0x03u, 0xf0u, 0xc4u, 0xf9u, 0x70u, 0xbdu, 0x06u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, + 0xa0u, 0x05u, 0x00u, 0x08u, 0x00u, 0x01u, 0x00u, 0x05u, 0xc8u, 0x12u, 0x00u, 0x08u, 0xc0u, 0xeau, 0x21u, 0x01u, 0x48u, 0x26u, 0x00u, 0x00u, 0x06u, 0x00u, 0x52u, 0x00u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0x3fu, 0xffu, 0x10u, 0xbdu, 0x70u, 0xb5u, 0xc3u, 0x05u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x00u, 0x2bu, 0x2au, 0xd1u, 0x00u, 0x29u, 0x28u, 0xd0u, - 0x01u, 0xf0u, 0x1eu, 0xfbu, 0xc0u, 0x22u, 0x80u, 0x21u, 0x13u, 0x4bu, 0xd2u, 0x04u, 0x1au, 0x60u, 0x13u, 0x4au, + 0x01u, 0xf0u, 0x5au, 0xfbu, 0xc0u, 0x22u, 0x80u, 0x21u, 0x13u, 0x4bu, 0xd2u, 0x04u, 0x1au, 0x60u, 0x13u, 0x4au, 0x49u, 0x00u, 0x12u, 0x78u, 0x00u, 0x2au, 0x02u, 0xd0u, 0x1au, 0x68u, 0x0au, 0x43u, 0x1au, 0x60u, 0x59u, 0x60u, 0x9du, 0x60u, 0xdcu, 0x60u, 0x0eu, 0x4bu, 0x1bu, 0x68u, 0x4fu, 0x33u, 0x18u, 0x78u, 0x01u, 0x1eu, 0x0du, 0xd0u, - 0xffu, 0xf7u, 0xfeu, 0xfeu, 0xfau, 0x21u, 0x89u, 0x00u, 0x01u, 0xf0u, 0xe6u, 0xfbu, 0x01u, 0x00u, 0x09u, 0x48u, - 0x01u, 0xf0u, 0xe2u, 0xfbu, 0xe1u, 0x23u, 0x9bu, 0x00u, 0xc1u, 0x18u, 0x00u, 0x20u, 0x03u, 0xf0u, 0x3cu, 0xf9u, + 0xffu, 0xf7u, 0xfeu, 0xfeu, 0xfau, 0x21u, 0x89u, 0x00u, 0x01u, 0xf0u, 0x22u, 0xfcu, 0x01u, 0x00u, 0x09u, 0x48u, + 0x01u, 0xf0u, 0x1eu, 0xfcu, 0xe1u, 0x23u, 0x9bu, 0x00u, 0xc1u, 0x18u, 0x00u, 0x20u, 0x03u, 0xf0u, 0x80u, 0xf9u, 0x70u, 0xbdu, 0x05u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xa0u, 0x05u, 0x00u, 0x08u, 0x0bu, 0x00u, 0x00u, 0x16u, - 0xc4u, 0x12u, 0x00u, 0x08u, 0x80u, 0x8du, 0x5bu, 0x00u, 0x06u, 0x00u, 0x52u, 0x00u, 0x0eu, 0x4bu, 0x10u, 0xb5u, + 0xc8u, 0x12u, 0x00u, 0x08u, 0x80u, 0x8du, 0x5bu, 0x00u, 0x06u, 0x00u, 0x52u, 0x00u, 0x0eu, 0x4bu, 0x10u, 0xb5u, 0x1bu, 0x68u, 0x9cu, 0x69u, 0x5bu, 0x69u, 0x00u, 0x1bu, 0xc0u, 0x09u, 0x00u, 0x01u, 0xc0u, 0x18u, 0x1fu, 0x23u, 0x1au, 0x40u, 0x03u, 0x29u, 0x07u, 0xd8u, 0xc9u, 0x00u, 0x8bu, 0x40u, 0x8au, 0x40u, 0x04u, 0x68u, 0x9cu, 0x43u, 0x22u, 0x43u, 0x02u, 0x60u, 0x10u, 0xbdu, 0x04u, 0x39u, 0xc9u, 0x00u, 0x8bu, 0x40u, 0x8au, 0x40u, 0x44u, 0x68u, - 0x9cu, 0x43u, 0x22u, 0x43u, 0x42u, 0x60u, 0xf5u, 0xe7u, 0xc4u, 0x12u, 0x00u, 0x08u, 0x30u, 0xb5u, 0x00u, 0x28u, + 0x9cu, 0x43u, 0x22u, 0x43u, 0x42u, 0x60u, 0xf5u, 0xe7u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x30u, 0xb5u, 0x00u, 0x28u, 0x30u, 0xd0u, 0x00u, 0x29u, 0x2eu, 0xd0u, 0x18u, 0x4bu, 0xcdu, 0x68u, 0x1au, 0x68u, 0x93u, 0x69u, 0x54u, 0x69u, 0xc3u, 0x1au, 0xdbu, 0x09u, 0x1bu, 0x01u, 0x1bu, 0x19u, 0x0cu, 0x68u, 0x04u, 0x60u, 0x14u, 0x00u, 0x79u, 0x34u, 0x24u, 0x78u, 0x24u, 0x18u, 0x25u, 0x60u, 0x14u, 0x00u, 0x7au, 0x34u, 0x24u, 0x78u, 0x0du, 0x69u, 0x24u, 0x18u, 0x25u, 0x60u, 0x14u, 0x00u, 0x7bu, 0x34u, 0x24u, 0x78u, 0x4du, 0x69u, 0x24u, 0x18u, 0x25u, 0x60u, 0x14u, 0x00u, 0x78u, 0x34u, 0x24u, 0x78u, 0x8du, 0x68u, 0x24u, 0x18u, 0x25u, 0x60u, 0x4cu, 0x68u, 0x7cu, 0x32u, 0x84u, 0x61u, 0x12u, 0x78u, 0x10u, 0x18u, 0x8au, 0x69u, 0x02u, 0x60u, 0x00u, 0x20u, 0xcau, 0x69u, 0x1au, 0x60u, 0x0au, 0x6au, - 0x5au, 0x60u, 0x30u, 0xbdu, 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc4u, 0x12u, 0x00u, 0x08u, 0x01u, 0x00u, 0x5au, 0x00u, + 0x5au, 0x60u, 0x30u, 0xbdu, 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x01u, 0x00u, 0x5au, 0x00u, 0xf7u, 0xb5u, 0x01u, 0x26u, 0x37u, 0x00u, 0x8fu, 0x40u, 0x33u, 0x40u, 0x8bu, 0x40u, 0x05u, 0x68u, 0x14u, 0x00u, 0xbdu, 0x43u, 0x0fu, 0x27u, 0x2bu, 0x43u, 0x03u, 0x60u, 0x0au, 0x4bu, 0x08u, 0xaau, 0x12u, 0x78u, 0x1bu, 0x68u, 0x01u, 0x92u, 0x79u, 0x33u, 0x1du, 0x78u, 0x8eu, 0x00u, 0x45u, 0x19u, 0x2bu, 0x68u, 0x3cu, 0x40u, 0x1au, 0x00u, 0x3bu, 0x00u, 0xb3u, 0x40u, 0xb4u, 0x40u, 0x9au, 0x43u, 0x14u, 0x43u, 0x2cu, 0x60u, 0x01u, 0x9au, 0xffu, 0xf7u, - 0x85u, 0xffu, 0xf7u, 0xbdu, 0xc4u, 0x12u, 0x00u, 0x08u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, + 0x85u, 0xffu, 0xf7u, 0xbdu, 0xc8u, 0x12u, 0x00u, 0x08u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0x89u, 0xb2u, 0x41u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, - 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc4u, 0x12u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, + 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u, 0xc2u, 0x60u, 0x81u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x00u, 0x8au, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, - 0xc4u, 0x12u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, + 0xc8u, 0x12u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x18u, 0x60u, 0x70u, 0x47u, 0xb4u, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x15u, 0x4cu, 0x1fu, 0x00u, 0x24u, 0x68u, 0x1du, 0x0au, 0x20u, 0x18u, 0xffu, 0x24u, 0x25u, 0x40u, 0x27u, 0x40u, 0x12u, 0x4cu, 0x1bu, 0x0cu, 0x26u, 0x68u, 0x07u, 0x60u, 0x34u, 0x6au, 0x45u, 0x60u, 0x83u, 0x60u, 0xacu, 0x36u, 0x36u, 0x88u, 0x77u, 0x43u, 0x3fu, 0x19u, 0x07u, 0x61u, 0x2fu, 0x00u, 0x80u, 0x37u, 0x6du, 0x01u, 0x7fu, 0x01u, 0xe7u, 0x19u, 0x64u, 0x19u, 0x0au, 0x4du, 0x47u, 0x61u, 0x1fu, 0x04u, 0x3bu, 0x43u, 0x64u, 0x19u, 0x23u, 0x60u, 0x00u, 0x23u, 0x83u, 0x61u, 0x05u, 0x9bu, 0xc2u, 0x61u, 0x01u, 0x62u, 0x00u, 0x2bu, 0x01u, 0xd0u, 0x1bu, 0x88u, 0x83u, 0x81u, - 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xb4u, 0x05u, 0x00u, 0x08u, 0xc4u, 0x12u, 0x00u, 0x08u, 0x08u, 0x10u, 0x00u, 0x00u, + 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xb4u, 0x05u, 0x00u, 0x08u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x08u, 0x10u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x83u, 0x68u, 0x85u, 0xb0u, 0x02u, 0xadu, 0x2bu, 0x80u, 0x15u, 0x4bu, 0x02u, 0x68u, 0x1bu, 0x68u, 0x06u, 0x6au, 0x9bu, 0x8eu, 0x47u, 0x6au, 0x9bu, 0x18u, 0xabu, 0x70u, 0x43u, 0x68u, 0x00u, 0x95u, 0x82u, 0x6au, 0xc1u, 0x6au, 0x04u, 0x00u, 0x03u, 0x93u, 0x03u, 0x69u, 0xc0u, 0x68u, 0xffu, 0xf7u, 0xb5u, 0xffu, 0x00u, 0x21u, 0x3bu, 0x00u, 0x0au, 0x00u, 0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xaeu, 0xffu, 0x21u, 0x6bu, 0x28u, 0x00u, - 0x00u, 0xf0u, 0x56u, 0xfcu, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, + 0x00u, 0xf0u, 0x6cu, 0xfcu, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0xc4u, 0x12u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, + 0xc8u, 0x12u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, 0x26u, 0x68u, 0x69u, 0x43u, 0x34u, 0x18u, 0x25u, 0x69u, 0x01u, 0x93u, 0x71u, 0x18u, 0x00u, 0x2du, 0x19u, 0xd0u, 0x88u, 0x69u, 0x00u, 0x28u, 0x18u, 0xd1u, 0x2eu, 0x68u, 0x00u, 0x2eu, 0x15u, 0xdau, 0x67u, 0x68u, 0x01u, 0x24u, 0x26u, 0x00u, 0x4bu, 0x68u, 0x9eu, 0x40u, 0xb4u, 0x46u, 0x13u, 0x68u, 0x9eu, 0xb2u, 0x63u, 0x46u, 0x1bu, 0x04u, @@ -399,7 +399,7 @@ const uint8_t cy_m0p_image[] = { 0x98u, 0x47u, 0x31u, 0x00u, 0x20u, 0x69u, 0xffu, 0xf7u, 0xe7u, 0xfeu, 0xadu, 0xb2u, 0x00u, 0x2du, 0x09u, 0xd0u, 0x63u, 0x69u, 0x1du, 0x60u, 0x00u, 0x25u, 0x1bu, 0x68u, 0x63u, 0x6au, 0xabu, 0x42u, 0x05u, 0xd0u, 0x98u, 0x47u, 0x65u, 0x62u, 0xa5u, 0x61u, 0x63u, 0x69u, 0x1bu, 0x68u, 0x73u, 0xbdu, 0xa3u, 0x6au, 0x00u, 0x2bu, 0xf8u, 0xd0u, - 0x98u, 0x47u, 0xf6u, 0xe7u, 0xc4u, 0x12u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, + 0x98u, 0x47u, 0xf6u, 0xe7u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, 0x10u, 0x68u, 0xc0u, 0x18u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xb4u, 0x05u, 0x00u, 0x08u, 0x2cu, 0x22u, 0x0au, 0x4bu, 0x50u, 0x43u, 0x1bu, 0x68u, 0x18u, 0x18u, 0x0cu, 0x22u, 0x83u, 0x5eu, 0x00u, 0x2bu, 0x0au, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x04u, 0x4au, 0xd3u, 0x67u, @@ -410,15 +410,15 @@ const uint8_t cy_m0p_image[] = { 0xf8u, 0xb5u, 0x19u, 0x4bu, 0x0fu, 0x00u, 0x1bu, 0x68u, 0x1au, 0x00u, 0x2eu, 0x32u, 0x12u, 0x78u, 0x82u, 0x42u, 0x27u, 0xd9u, 0x00u, 0x29u, 0x25u, 0xd0u, 0x1fu, 0x25u, 0x0au, 0x68u, 0x15u, 0x40u, 0x21u, 0xd1u, 0x19u, 0x00u, 0xacu, 0x31u, 0x0cu, 0x88u, 0x11u, 0x4eu, 0x60u, 0x43u, 0x1cu, 0x6au, 0xd2u, 0x08u, 0x04u, 0x19u, 0x29u, 0x00u, - 0x78u, 0x68u, 0x34u, 0x60u, 0x02u, 0xf0u, 0x14u, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x74u, 0xfeu, + 0x78u, 0x68u, 0x34u, 0x60u, 0x02u, 0xf0u, 0x50u, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x74u, 0xfeu, 0x3au, 0x00u, 0x29u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0x81u, 0xfeu, 0x04u, 0x1eu, 0x07u, 0xd1u, 0x01u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0x69u, 0xfeu, 0x03u, 0x00u, 0x20u, 0x00u, 0x00u, 0x2bu, 0x00u, 0xd0u, 0x04u, 0x48u, - 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xc4u, 0x12u, 0x00u, 0x08u, 0xb8u, 0x05u, 0x00u, 0x08u, + 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xc8u, 0x12u, 0x00u, 0x08u, 0xb8u, 0x05u, 0x00u, 0x08u, 0x01u, 0x01u, 0x8au, 0x00u, 0x03u, 0x01u, 0x8au, 0x00u, 0x10u, 0xb5u, 0x00u, 0x2au, 0x0du, 0xd1u, 0x00u, 0x29u, 0x14u, 0xd1u, 0x0bu, 0x4bu, 0x1au, 0x68u, 0x13u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u, 0x58u, 0x43u, 0x13u, 0x6au, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x18u, 0x60u, 0x08u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x29u, 0x06u, 0xd0u, 0x06u, 0x4bu, 0x19u, 0x60u, 0x19u, 0x00u, 0x5au, 0x60u, 0xffu, 0xf7u, 0xabu, 0xffu, 0xf5u, 0xe7u, 0x03u, 0x48u, 0xf3u, 0xe7u, - 0xc4u, 0x12u, 0x00u, 0x08u, 0xb8u, 0x05u, 0x00u, 0x08u, 0x24u, 0x05u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, + 0xc8u, 0x12u, 0x00u, 0x08u, 0xb8u, 0x05u, 0x00u, 0x08u, 0x24u, 0x05u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, 0xf7u, 0xb5u, 0x18u, 0x4fu, 0x04u, 0x00u, 0x3bu, 0x68u, 0x01u, 0x91u, 0xdeu, 0x68u, 0x33u, 0x68u, 0x83u, 0x42u, 0x26u, 0xd9u, 0x00u, 0x25u, 0xa9u, 0x42u, 0x02u, 0xd1u, 0xfeu, 0xf7u, 0x3fu, 0xfcu, 0x05u, 0x00u, 0x38u, 0x68u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x1au, 0xdau, 0x1fu, 0x22u, 0x01u, 0x23u, 0x22u, 0x40u, 0x93u, 0x40u, 0x64u, 0x09u, @@ -438,144 +438,153 @@ const uint8_t cy_m0p_image[] = { 0x92u, 0x00u, 0x50u, 0x58u, 0x18u, 0x40u, 0x43u, 0x1eu, 0x98u, 0x41u, 0x03u, 0x4bu, 0xc0u, 0x18u, 0x70u, 0x47u, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xb8u, 0x05u, 0x00u, 0x08u, 0x00u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0x04u, 0x4bu, 0x10u, 0x30u, 0x1bu, 0x68u, 0x80u, 0x02u, 0x1bu, 0x69u, 0xc0u, 0x58u, 0x0fu, 0x23u, 0x18u, 0x40u, - 0x70u, 0x47u, 0xc0u, 0x46u, 0xc4u, 0x12u, 0x00u, 0x08u, 0xa6u, 0x22u, 0x05u, 0x49u, 0xd2u, 0x00u, 0x8bu, 0x58u, + 0x70u, 0x47u, 0xc0u, 0x46u, 0xc8u, 0x12u, 0x00u, 0x08u, 0xa6u, 0x22u, 0x05u, 0x49u, 0xd2u, 0x00u, 0x8bu, 0x58u, 0x02u, 0x20u, 0xdbu, 0x43u, 0x9bu, 0x07u, 0x02u, 0xd0u, 0x01u, 0x23u, 0x88u, 0x58u, 0x18u, 0x40u, 0x70u, 0x47u, - 0x00u, 0x00u, 0x26u, 0x40u, 0x09u, 0x4au, 0x83u, 0x00u, 0x9bu, 0x18u, 0xd0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, - 0x07u, 0x22u, 0x10u, 0x40u, 0x04u, 0x28u, 0x07u, 0xd1u, 0xc0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x1fu, 0x23u, - 0x03u, 0x40u, 0x80u, 0x20u, 0x40u, 0x00u, 0x18u, 0x43u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, - 0xb0u, 0x23u, 0x15u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x10u, 0xb5u, 0x99u, 0x03u, 0xdbu, 0x01u, 0xdbu, 0x0fu, - 0x89u, 0x0bu, 0xc3u, 0x71u, 0x11u, 0x4bu, 0x01u, 0x60u, 0xd3u, 0x58u, 0x0fu, 0x24u, 0xd9u, 0x04u, 0xdbu, 0x01u, - 0xdbu, 0x0du, 0x03u, 0x81u, 0xb1u, 0x23u, 0xdbu, 0x00u, 0xd3u, 0x58u, 0xc9u, 0x0cu, 0x81u, 0x80u, 0x19u, 0x00u, - 0x21u, 0x40u, 0x81u, 0x72u, 0x19u, 0x09u, 0x21u, 0x40u, 0xc1u, 0x72u, 0xd9u, 0x02u, 0x9bu, 0x00u, 0x9bu, 0x0fu, - 0x83u, 0x73u, 0x07u, 0x4bu, 0xc9u, 0x0cu, 0xd3u, 0x58u, 0x81u, 0x81u, 0x5au, 0x05u, 0xdbu, 0x01u, 0x52u, 0x0fu, - 0xdbu, 0x0du, 0x82u, 0x71u, 0x03u, 0x82u, 0x10u, 0xbdu, 0x00u, 0x00u, 0x26u, 0x40u, 0x84u, 0x05u, 0x00u, 0x00u, - 0x8cu, 0x05u, 0x00u, 0x00u, 0x10u, 0xb5u, 0x10u, 0x4bu, 0x42u, 0x1eu, 0x1bu, 0x68u, 0x3bu, 0x33u, 0x1bu, 0x78u, - 0x93u, 0x42u, 0x16u, 0xd9u, 0x7fu, 0x22u, 0x1fu, 0x24u, 0x80u, 0x30u, 0xffu, 0x30u, 0x0bu, 0x4bu, 0x80u, 0x00u, - 0xc3u, 0x58u, 0x1au, 0x40u, 0x0au, 0x70u, 0x1au, 0x0cu, 0x22u, 0x40u, 0x18u, 0x0au, 0x8au, 0x70u, 0x1au, 0x01u, - 0x20u, 0x40u, 0xe2u, 0x40u, 0x48u, 0x70u, 0x00u, 0x20u, 0x9bu, 0x00u, 0x9bu, 0x0fu, 0xcau, 0x70u, 0x0bu, 0x71u, - 0x10u, 0xbdu, 0x03u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xc4u, 0x12u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, - 0x01u, 0x00u, 0x4au, 0x00u, 0xf7u, 0xb5u, 0x48u, 0x4bu, 0x00u, 0x91u, 0x15u, 0x00u, 0x98u, 0x42u, 0x00u, 0xd9u, - 0x87u, 0xe0u, 0x9au, 0x42u, 0x00u, 0xd9u, 0x84u, 0xe0u, 0x44u, 0x4bu, 0x99u, 0x42u, 0x00u, 0xd9u, 0x80u, 0xe0u, - 0x01u, 0x22u, 0x43u, 0x4bu, 0x1au, 0x70u, 0xffu, 0x28u, 0x45u, 0xd8u, 0x0fu, 0x23u, 0x07u, 0x26u, 0x1cu, 0x00u, - 0x18u, 0x40u, 0xffu, 0x2du, 0x58u, 0xd8u, 0xffu, 0x22u, 0x2du, 0x01u, 0x15u, 0x40u, 0x28u, 0x43u, 0xf0u, 0x25u, - 0xe0u, 0x22u, 0x2cu, 0x43u, 0xf0u, 0x25u, 0xd2u, 0x02u, 0x32u, 0x43u, 0x2du, 0x03u, 0x2bu, 0x43u, 0x39u, 0x4du, - 0x07u, 0x26u, 0x2fu, 0x68u, 0x3du, 0x00u, 0xacu, 0x35u, 0x2du, 0x88u, 0x6eu, 0x43u, 0x35u, 0x00u, 0x01u, 0x96u, - 0x3eu, 0x6au, 0xadu, 0x19u, 0x2eu, 0x68u, 0x00u, 0x2eu, 0xfcu, 0xdau, 0x33u, 0x4du, 0x2eu, 0x78u, 0x33u, 0x4du, - 0x00u, 0x2eu, 0x03u, 0xd0u, 0x32u, 0x4eu, 0xaeu, 0x59u, 0x00u, 0x2eu, 0x50u, 0xdau, 0x31u, 0x4eu, 0x32u, 0x49u, - 0x31u, 0x60u, 0x32u, 0x4eu, 0x32u, 0x49u, 0x31u, 0x60u, 0xa3u, 0x21u, 0xc9u, 0x00u, 0x6eu, 0x58u, 0xa6u, 0x43u, - 0x06u, 0x43u, 0x30u, 0x4cu, 0x6eu, 0x50u, 0x28u, 0x59u, 0x98u, 0x43u, 0x02u, 0x43u, 0x00u, 0x20u, 0x2au, 0x51u, - 0x2du, 0x4bu, 0x00u, 0x9au, 0x1au, 0x60u, 0x26u, 0x4bu, 0xeau, 0x50u, 0x3bu, 0x6au, 0x01u, 0x9au, 0xd3u, 0x18u, - 0x00u, 0x22u, 0x5au, 0x60u, 0xfeu, 0xbdu, 0x29u, 0x4bu, 0x98u, 0x42u, 0x05u, 0xd8u, 0x0fu, 0x23u, 0x18u, 0x40u, - 0x06u, 0x00u, 0x00u, 0x24u, 0x20u, 0x00u, 0xb4u, 0xe7u, 0x25u, 0x4bu, 0x06u, 0x0au, 0x98u, 0x42u, 0x04u, 0xd8u, - 0xffu, 0x23u, 0x04u, 0x01u, 0x1cu, 0x40u, 0x26u, 0x43u, 0xf3u, 0xe7u, 0xf0u, 0x23u, 0x00u, 0x02u, 0x1bu, 0x01u, - 0x18u, 0x40u, 0x06u, 0x43u, 0x1fu, 0x4bu, 0xecu, 0xe7u, 0x1cu, 0x4au, 0x95u, 0x42u, 0x05u, 0xd8u, 0x2au, 0x04u, - 0xf0u, 0x25u, 0x2du, 0x03u, 0x2au, 0x40u, 0x32u, 0x43u, 0xa8u, 0xe7u, 0x2au, 0x0au, 0x12u, 0x04u, 0x32u, 0x43u, - 0x17u, 0x4eu, 0xb5u, 0x42u, 0x07u, 0xd8u, 0xf0u, 0x26u, 0x2du, 0x05u, 0x36u, 0x04u, 0x35u, 0x40u, 0x2au, 0x43u, - 0xffu, 0x25u, 0x2du, 0x04u, 0x9au, 0xe7u, 0x2du, 0x06u, 0x2au, 0x43u, 0x13u, 0x4du, 0x96u, 0xe7u, 0x13u, 0x48u, - 0xc3u, 0xe7u, 0x12u, 0x48u, 0xc6u, 0xe7u, 0xc0u, 0x46u, 0x0fu, 0x06u, 0x00u, 0x00u, 0xffu, 0xffu, 0xffu, 0x00u, - 0xc0u, 0x05u, 0x00u, 0x08u, 0xc4u, 0x12u, 0x00u, 0x08u, 0xccu, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, - 0x1cu, 0x05u, 0x00u, 0x00u, 0x08u, 0x01u, 0x26u, 0x40u, 0x1fu, 0x1fu, 0x00u, 0x00u, 0x04u, 0x01u, 0x26u, 0x40u, - 0x3du, 0x3du, 0x00u, 0x00u, 0x14u, 0x05u, 0x00u, 0x00u, 0xbcu, 0x05u, 0x00u, 0x08u, 0xffu, 0x04u, 0x00u, 0x00u, - 0xffu, 0x05u, 0x00u, 0x00u, 0x0fu, 0x0fu, 0x00u, 0x00u, 0x00u, 0x00u, 0x0fu, 0x0fu, 0x01u, 0x00u, 0x4au, 0x00u, - 0x00u, 0x22u, 0xf8u, 0xb5u, 0x22u, 0x4bu, 0x1au, 0x70u, 0x22u, 0x4bu, 0x1au, 0x68u, 0x13u, 0x00u, 0xacu, 0x33u, - 0x1cu, 0x88u, 0x07u, 0x23u, 0x63u, 0x43u, 0x12u, 0x6au, 0x9bu, 0x18u, 0x1au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xdau, - 0x1du, 0x4au, 0x00u, 0x24u, 0x15u, 0x68u, 0x1du, 0x4au, 0x95u, 0x42u, 0x05u, 0xd1u, 0x1cu, 0x4au, 0x1du, 0x4cu, - 0x12u, 0x68u, 0x12u, 0x19u, 0x54u, 0x42u, 0x54u, 0x41u, 0xa4u, 0x22u, 0x1bu, 0x4du, 0xd2u, 0x00u, 0xafu, 0x58u, - 0x00u, 0x25u, 0x5du, 0x60u, 0xacu, 0x42u, 0x15u, 0xd0u, 0x3fu, 0x02u, 0x3eu, 0x0au, 0xaeu, 0x42u, 0x11u, 0xd0u, - 0x16u, 0x4bu, 0x1cu, 0x68u, 0xa8u, 0x42u, 0x0fu, 0xd1u, 0x22u, 0x00u, 0x2bu, 0x00u, 0x08u, 0x00u, 0x29u, 0x00u, - 0x01u, 0xf0u, 0x18u, 0xf9u, 0x2bu, 0x00u, 0x7au, 0x0au, 0x80u, 0x18u, 0x59u, 0x41u, 0x32u, 0x00u, 0x01u, 0xf0u, - 0xf1u, 0xf8u, 0x05u, 0x00u, 0x28u, 0x00u, 0xf8u, 0xbdu, 0x0au, 0x00u, 0x2bu, 0x00u, 0x30u, 0x00u, 0x29u, 0x00u, - 0x01u, 0xf0u, 0x08u, 0xf9u, 0x2bu, 0x00u, 0x62u, 0x08u, 0x80u, 0x18u, 0x59u, 0x41u, 0x22u, 0x00u, 0xeeu, 0xe7u, - 0xc0u, 0x05u, 0x00u, 0x08u, 0xc4u, 0x12u, 0x00u, 0x08u, 0x08u, 0x01u, 0x26u, 0x40u, 0x1fu, 0x1fu, 0x00u, 0x00u, - 0x04u, 0x01u, 0x26u, 0x40u, 0xc3u, 0xc2u, 0xffu, 0xffu, 0x00u, 0x00u, 0x26u, 0x40u, 0xbcu, 0x05u, 0x00u, 0x08u, - 0xe0u, 0x22u, 0x01u, 0x21u, 0x4du, 0x4bu, 0x80u, 0x00u, 0xc0u, 0x18u, 0x92u, 0x00u, 0x83u, 0x58u, 0xf0u, 0xb5u, - 0x9bu, 0x06u, 0x9bu, 0x0fu, 0x99u, 0x40u, 0x0fu, 0x23u, 0x84u, 0x58u, 0x89u, 0xb0u, 0x1cu, 0x40u, 0x20u, 0x00u, - 0x01u, 0x91u, 0xffu, 0xf7u, 0x6fu, 0xfeu, 0x03u, 0x28u, 0x54u, 0xd0u, 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0x5bu, 0x00u, 0x98u, 0x42u, 0x0du, 0xd1u, + 0x13u, 0x68u, 0x11u, 0x49u, 0x1au, 0x00u, 0x94u, 0x32u, 0x12u, 0x68u, 0x1bu, 0x68u, 0x9bu, 0x18u, 0x1au, 0x68u, + 0x11u, 0x40u, 0xc0u, 0x22u, 0xd2u, 0x01u, 0x0au, 0x43u, 0x1au, 0x60u, 0x10u, 0xbdu, 0xb0u, 0x21u, 0x12u, 0x68u, + 0x0au, 0x4bu, 0x49u, 0x05u, 0xcbu, 0x58u, 0x11u, 0x00u, 0x09u, 0x48u, 0x94u, 0x31u, 0x03u, 0x40u, 0xc0u, 0x20u, + 0x09u, 0x68u, 0x12u, 0x68u, 0x80u, 0x00u, 0x52u, 0x18u, 0x11u, 0x68u, 0x01u, 0x40u, 0x0bu, 0x43u, 0x13u, 0x60u, + 0xebu, 0xe7u, 0xc0u, 0x46u, 0xc8u, 0x12u, 0x00u, 0x08u, 0xffu, 0x8fu, 0xffu, 0xffu, 0x1cu, 0x18u, 0x00u, 0x00u, + 0xffu, 0xfcu, 0xffu, 0xffu, 0x70u, 0xb5u, 0xffu, 0xf7u, 0x3fu, 0xffu, 0x80u, 0x23u, 0x15u, 0x4au, 0x5bu, 0x00u, + 0x98u, 0x42u, 0x0du, 0xd1u, 0x13u, 0x68u, 0x14u, 0x49u, 0x1au, 0x00u, 0x94u, 0x32u, 0x12u, 0x68u, 0x1bu, 0x68u, + 0x9bu, 0x18u, 0x1au, 0x68u, 0x11u, 0x40u, 0x80u, 0x22u, 0xd2u, 0x01u, 0x0au, 0x43u, 0x1au, 0x60u, 0x70u, 0xbdu, 0xb0u, 0x24u, 0x12u, 0x68u, 0x0du, 0x4bu, 0x11u, 0x00u, 0x64u, 0x05u, 0xe3u, 0x58u, 0x0cu, 0x4du, 0x94u, 0x31u, 0x2bu, 0x40u, 0xc0u, 0x25u, 0x10u, 0x68u, 0x09u, 0x68u, 0xadu, 0x00u, 0x41u, 0x18u, 0x08u, 0x68u, 0x28u, 0x40u, - 0x03u, 0x43u, 0x0bu, 0x60u, 0x11u, 0x00u, 0x98u, 0x31u, 0x13u, 0x68u, 0x0au, 0x68u, 0x9bu, 0x18u, 0xc1u, 0x22u, - 0x52u, 0x01u, 0xa2u, 0x58u, 0xe2u, 0xe7u, 0xc0u, 0x46u, 0xc4u, 0x12u, 0x00u, 0x08u, 0x24u, 0x18u, 0x00u, 0x00u, - 0xffu, 0xfcu, 0xffu, 0xffu, 0x10u, 0xb5u, 0xffu, 0xf7u, 0x71u, 0xffu, 0x80u, 0x23u, 0x12u, 0x4au, 0x5bu, 0x00u, - 0x98u, 0x42u, 0x0du, 0xd1u, 0x13u, 0x68u, 0x11u, 0x49u, 0x1au, 0x00u, 0x94u, 0x32u, 0x12u, 0x68u, 0x1bu, 0x68u, - 0x9bu, 0x18u, 0x1au, 0x68u, 0x11u, 0x40u, 0xc0u, 0x22u, 0xd2u, 0x01u, 0x0au, 0x43u, 0x1au, 0x60u, 0x10u, 0xbdu, - 0xb0u, 0x21u, 0x12u, 0x68u, 0x0au, 0x4bu, 0x49u, 0x05u, 0xcbu, 0x58u, 0x11u, 0x00u, 0x09u, 0x48u, 0x94u, 0x31u, - 0x03u, 0x40u, 0xc0u, 0x20u, 0x09u, 0x68u, 0x12u, 0x68u, 0x80u, 0x00u, 0x52u, 0x18u, 0x11u, 0x68u, 0x01u, 0x40u, - 0x0bu, 0x43u, 0x13u, 0x60u, 0xebu, 0xe7u, 0xc0u, 0x46u, 0xc4u, 0x12u, 0x00u, 0x08u, 0xffu, 0x8fu, 0xffu, 0xffu, - 0x1cu, 0x18u, 0x00u, 0x00u, 0xffu, 0xfcu, 0xffu, 0xffu, 0x70u, 0xb5u, 0xffu, 0xf7u, 0x3fu, 0xffu, 0x80u, 0x23u, - 0x15u, 0x4au, 0x5bu, 0x00u, 0x98u, 0x42u, 0x0du, 0xd1u, 0x13u, 0x68u, 0x14u, 0x49u, 0x1au, 0x00u, 0x94u, 0x32u, - 0x12u, 0x68u, 0x1bu, 0x68u, 0x9bu, 0x18u, 0x1au, 0x68u, 0x11u, 0x40u, 0x80u, 0x22u, 0xd2u, 0x01u, 0x0au, 0x43u, - 0x1au, 0x60u, 0x70u, 0xbdu, 0xb0u, 0x24u, 0x12u, 0x68u, 0x0du, 0x4bu, 0x11u, 0x00u, 0x64u, 0x05u, 0xe3u, 0x58u, - 0x0cu, 0x4du, 0x94u, 0x31u, 0x2bu, 0x40u, 0xc0u, 0x25u, 0x10u, 0x68u, 0x09u, 0x68u, 0xadu, 0x00u, 0x41u, 0x18u, - 0x08u, 0x68u, 0x28u, 0x40u, 0x03u, 0x43u, 0x0bu, 0x60u, 0x11u, 0x00u, 0x98u, 0x31u, 0x13u, 0x68u, 0x0au, 0x68u, - 0x9bu, 0x18u, 0x05u, 0x4au, 0xa2u, 0x58u, 0xe3u, 0xe7u, 0xc4u, 0x12u, 0x00u, 0x08u, 0xffu, 0x8fu, 0xffu, 0xffu, - 0x50u, 0x18u, 0x00u, 0x00u, 0xffu, 0xfcu, 0xffu, 0xffu, 0x4cu, 0x18u, 0x00u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x20u, - 0xffu, 0xf7u, 0xeeu, 0xfbu, 0xb0u, 0x23u, 0x5bu, 0x05u, 0x5au, 0x78u, 0x00u, 0x2au, 0x03u, 0xd0u, 0x5au, 0x78u, - 0x01u, 0x23u, 0x22u, 0x2au, 0x01u, 0xd8u, 0x43u, 0x42u, 0x43u, 0x41u, 0x18u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x00u, + 0x03u, 0x43u, 0x0bu, 0x60u, 0x11u, 0x00u, 0x98u, 0x31u, 0x13u, 0x68u, 0x0au, 0x68u, 0x9bu, 0x18u, 0x05u, 0x4au, + 0xa2u, 0x58u, 0xe3u, 0xe7u, 0xc8u, 0x12u, 0x00u, 0x08u, 0xffu, 0x8fu, 0xffu, 0xffu, 0x50u, 0x18u, 0x00u, 0x00u, + 0xffu, 0xfcu, 0xffu, 0xffu, 0x4cu, 0x18u, 0x00u, 0x00u, 0xf8u, 0xb5u, 0x1fu, 0x4fu, 0xc0u, 0x25u, 0x3bu, 0x68u, + 0x2du, 0x01u, 0x1au, 0x00u, 0x94u, 0x32u, 0x1bu, 0x68u, 0x12u, 0x68u, 0x9bu, 0x18u, 0x1eu, 0x68u, 0xffu, 0xf7u, + 0xfbu, 0xfeu, 0x34u, 0x00u, 0x80u, 0x23u, 0x2cu, 0x40u, 0x5bu, 0x00u, 0x98u, 0x42u, 0x0fu, 0xd1u, 0x00u, 0x20u, + 0xffu, 0xf7u, 0xc6u, 0xfbu, 0xb0u, 0x23u, 0x5bu, 0x05u, 0x5au, 0x78u, 0x00u, 0x2au, 0x03u, 0xd0u, 0x5au, 0x78u, + 0x01u, 0x23u, 0x22u, 0x2au, 0x01u, 0xd8u, 0x43u, 0x42u, 0x43u, 0x41u, 0x18u, 0x00u, 0xf8u, 0xbdu, 0x3bu, 0x68u, + 0x0eu, 0x4fu, 0x19u, 0x00u, 0x94u, 0x31u, 0x1au, 0x68u, 0x08u, 0x68u, 0x12u, 0x18u, 0x10u, 0x68u, 0x38u, 0x40u, + 0x10u, 0x60u, 0x1au, 0x68u, 0x08u, 0x68u, 0x12u, 0x18u, 0x28u, 0x00u, 0x17u, 0x68u, 0xb0u, 0x43u, 0x38u, 0x43u, + 0x10u, 0x60u, 0x1bu, 0x68u, 0x0au, 0x68u, 0x9bu, 0x18u, 0x18u, 0x68u, 0x28u, 0x40u, 0x00u, 0x1bu, 0x43u, 0x1eu, + 0x98u, 0x41u, 0xc0u, 0xb2u, 0xe2u, 0xe7u, 0xc0u, 0x46u, 0xc8u, 0x12u, 0x00u, 0x08u, 0xffu, 0xf3u, 0xffu, 0xffu, 0x02u, 0x00u, 0x00u, 0x20u, 0x82u, 0x42u, 0x02u, 0xd1u, 0x09u, 0x4bu, 0x58u, 0x69u, 0xc0u, 0x0fu, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x42u, 0x33u, 0x1bu, 0x78u, 0x00u, 0x2bu, 0x09u, 0xd0u, 0x01u, 0x2au, 0x07u, 0xd1u, 0x04u, 0x4bu, 0x10u, 0x00u, 0x99u, 0x69u, 0x49u, 0x00u, 0x01u, 0xd4u, 0x98u, 0x69u, 0xc0u, 0x0fu, 0x10u, 0x40u, 0x70u, 0x47u, - 0x00u, 0x00u, 0x26u, 0x40u, 0xc4u, 0x12u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0cu, 0x4bu, 0x1bu, 0x68u, 0x42u, 0x33u, + 0x00u, 0x00u, 0x26u, 0x40u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0cu, 0x4bu, 0x1bu, 0x68u, 0x42u, 0x33u, 0x1bu, 0x78u, 0x00u, 0x2bu, 0x11u, 0xd0u, 0x07u, 0x22u, 0x09u, 0x4du, 0xacu, 0x69u, 0x14u, 0x40u, 0xa0u, 0x42u, 0x0bu, 0xd0u, 0xabu, 0x69u, 0x93u, 0x43u, 0x02u, 0x40u, 0x13u, 0x43u, 0xabu, 0x61u, 0x00u, 0x29u, 0x04u, 0xd0u, - 0xa0u, 0x42u, 0x02u, 0xd9u, 0xc8u, 0x20u, 0xffu, 0xf7u, 0x97u, 0xfeu, 0x70u, 0xbdu, 0xc4u, 0x12u, 0x00u, 0x08u, + 0xa0u, 0x42u, 0x02u, 0xd9u, 0xc8u, 0x20u, 0xffu, 0xf7u, 0x65u, 0xfeu, 0x70u, 0xbdu, 0xc8u, 0x12u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, 0x70u, 0xb5u, 0x03u, 0x1eu, 0x1bu, 0xd0u, 0xc0u, 0x68u, 0x00u, 0x28u, 0x18u, 0xd0u, 0x18u, 0x68u, 0x00u, 0x28u, 0x15u, 0xd0u, 0x1cu, 0x79u, 0x16u, 0x4du, 0xa4u, 0x00u, 0x62u, 0x59u, 0x11u, 0x1eu, 0x09u, 0xd1u, 0x63u, 0x51u, 0x5au, 0x61u, 0x1au, 0x61u, 0x19u, 0xe0u, 0x06u, 0x7eu, 0x1au, 0x7eu, 0x96u, 0x42u, @@ -595,6194 +604,6193 @@ const uint8_t cy_m0p_image[] = { 0x29u, 0x00u, 0x1au, 0x68u, 0x5bu, 0x68u, 0x02u, 0x92u, 0x01u, 0x93u, 0x03u, 0x93u, 0x02u, 0xa8u, 0x23u, 0x68u, 0x98u, 0x47u, 0x24u, 0x69u, 0xeeu, 0xe7u, 0xc0u, 0x46u, 0x10u, 0x06u, 0x00u, 0x08u, 0x0cu, 0x06u, 0x00u, 0x08u, 0xffu, 0x00u, 0x42u, 0x00u, 0xf8u, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x19u, 0x4cu, 0x06u, 0x00u, 0x23u, 0x68u, - 0x00u, 0x2bu, 0x1au, 0xd1u, 0xfdu, 0xf7u, 0xc9u, 0xfeu, 0x23u, 0x68u, 0x05u, 0x00u, 0x00u, 0x2bu, 0x20u, 0xd1u, + 0x00u, 0x2bu, 0x1au, 0xd1u, 0xfdu, 0xf7u, 0x81u, 0xfeu, 0x23u, 0x68u, 0x05u, 0x00u, 0x00u, 0x2bu, 0x20u, 0xd1u, 0x04u, 0x21u, 0x14u, 0x4au, 0x13u, 0x69u, 0x8bu, 0x43u, 0x13u, 0x61u, 0x01u, 0x2eu, 0x1eu, 0xd0u, 0x30u, 0xbfu, - 0x28u, 0x00u, 0xfdu, 0xf7u, 0xbeu, 0xfeu, 0x23u, 0x68u, 0x00u, 0x24u, 0xa3u, 0x42u, 0x03u, 0xd0u, 0x08u, 0x21u, + 0x28u, 0x00u, 0xfdu, 0xf7u, 0x76u, 0xfeu, 0x23u, 0x68u, 0x00u, 0x24u, 0xa3u, 0x42u, 0x03u, 0xd0u, 0x08u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x89u, 0xffu, 0x20u, 0x00u, 0x70u, 0xbdu, 0x01u, 0x21u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x83u, 0xffu, 0x00u, 0x28u, 0xdeu, 0xd0u, 0x02u, 0x21u, 0x00u, 0x20u, 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0x23u, 0x25u, 0x4au, + 0x19u, 0x00u, 0x12u, 0x68u, 0x01u, 0x20u, 0x00u, 0xf0u, 0xa7u, 0xf8u, 0x00u, 0x25u, 0xa8u, 0x42u, 0xecu, 0xd1u, + 0x00u, 0x20u, 0x00u, 0xf0u, 0x99u, 0xf8u, 0x1eu, 0x4au, 0x1fu, 0x4bu, 0x90u, 0x42u, 0x03u, 0xd0u, 0x9du, 0x42u, + 0xe3u, 0xd0u, 0x01u, 0x35u, 0xf4u, 0xe7u, 0x9du, 0x42u, 0xb9u, 0xd1u, 0xdeu, 0xe7u, 0x17u, 0x4cu, 0x03u, 0x2fu, + 0x05u, 0xd1u, 0x01u, 0x21u, 0x00u, 0x20u, 0x00u, 0xf0u, 0xafu, 0xf8u, 0x00u, 0x28u, 0xf9u, 0xd1u, 0x28u, 0x00u, + 0x00u, 0xf0u, 0x92u, 0xf8u, 0xd2u, 0xe7u, 0x15u, 0x4cu, 0xf1u, 0xe7u, 0x00u, 0xf0u, 0x6du, 0xf8u, 0x0eu, 0x4au, + 0x05u, 0x00u, 0x01u, 0x21u, 0x30u, 0x00u, 0x00u, 0xf0u, 0x6fu, 0xf8u, 0x00u, 0x28u, 0x09u, 0xd1u, 0x00u, 0x9bu, + 0x00u, 0x2bu, 0x08u, 0xd0u, 0x23u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x00u, 0xf0u, 0x8du, 0xf8u, 0x04u, 0x00u, + 0xe5u, 0xe7u, 0x06u, 0x4cu, 0xe3u, 0xe7u, 0x09u, 0x4cu, 0xe1u, 0xe7u, 0xc0u, 0x46u, 0xc8u, 0x12u, 0x00u, 0x08u, + 0x00u, 0x00u, 0x26u, 0x40u, 0x1cu, 0x05u, 0x00u, 0x00u, 0xa0u, 0x05u, 0x00u, 0x08u, 0x05u, 0x00u, 0x52u, 0x00u, + 0x01u, 0x01u, 0x88u, 0x00u, 0xb0u, 0x05u, 0x00u, 0x08u, 0xf0u, 0x49u, 0x02u, 0x00u, 0x01u, 0x00u, 0x50u, 0x00u, + 0x18u, 0x4bu, 0xf7u, 0xb5u, 0x1bu, 0x68u, 0x18u, 0x4au, 0x5cu, 0x68u, 0x04u, 0x23u, 0x11u, 0x69u, 0x0bu, 0x43u, + 0x13u, 0x61u, 0x01u, 0x28u, 0x24u, 0xd0u, 0x30u, 0xbfu, 0x23u, 0x00u, 0xfcu, 0x33u, 0x1bu, 0x69u, 0x00u, 0x2bu, + 0x1du, 0xd1u, 0xa3u, 0x20u, 0x11u, 0x4bu, 0x12u, 0x49u, 0x12u, 0x4au, 0xc0u, 0x00u, 0x0fu, 0x68u, 0x1eu, 0x58u, + 0x15u, 0x68u, 0x01u, 0x95u, 0x10u, 0x4du, 0x0du, 0x60u, 0x06u, 0x25u, 0x1du, 0x50u, 0x3eu, 0x20u, 0x10u, 0x60u, + 0x0eu, 0x48u, 0x3eu, 0x35u, 0x1du, 0x50u, 0x1du, 0x58u, 0x00u, 0x2du, 0xfcu, 0xdau, 0x0cu, 0x48u, 0xfcu, 0x34u, + 0x20u, 0x61u, 0x0fu, 0x60u, 0xa3u, 0x21u, 0xc9u, 0x00u, 0x5eu, 0x50u, 0x01u, 0x9bu, 0x13u, 0x60u, 0xf7u, 0xbdu, + 0x20u, 0xbfu, 0xd9u, 0xe7u, 0xc8u, 0x12u, 0x00u, 0x08u, 0x00u, 0xedu, 0x00u, 0xe0u, 0x00u, 0x00u, 0x26u, 0x40u, + 0x08u, 0x01u, 0x26u, 0x40u, 0x04u, 0x01u, 0x26u, 0x40u, 0x1eu, 0x1fu, 0x00u, 0x00u, 0x1cu, 0x05u, 0x00u, 0x00u, + 0xaau, 0xaau, 0xaau, 0xaau, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, + 0x60u, 0x47u, 0x00u, 0xbfu, 0x1bu, 0x01u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, + 0x60u, 0x47u, 0x00u, 0xbfu, 0x0du, 0x15u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, + 0x60u, 0x47u, 0x00u, 0xbfu, 0x69u, 0x19u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, + 0x60u, 0x47u, 0x00u, 0xbfu, 0x29u, 0x16u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, + 0x60u, 0x47u, 0x00u, 0xbfu, 0x23u, 0x01u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, + 0x60u, 0x47u, 0x00u, 0xbfu, 0x69u, 0x2bu, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, + 0x60u, 0x47u, 0x00u, 0xbfu, 0xedu, 0x11u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, + 0x60u, 0x47u, 0x00u, 0xbfu, 0xf5u, 0x18u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, + 0x60u, 0x47u, 0x00u, 0xbfu, 0xedu, 0x10u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, }; #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_01_cm0p_crypto.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_01_cm0p_crypto.c index f1e46b784b1..29bc9223106 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_01_cm0p_crypto.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_01_cm0p_crypto.c @@ -40,35 +40,35 @@ const uint8_t cy_m0p_image[] = { 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u, - 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0x00u, 0x04u, 0x00u, 0x08u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x08u, 0x7fu, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, + 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0xf8u, 0x03u, 0x00u, 0x08u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x30u, 0x7fu, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x04u, 0x04u, 0x00u, 0x08u, 0x08u, 0x7fu, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, + 0xfcu, 0x03u, 0x00u, 0x08u, 0x30u, 0x7fu, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, 0x02u, 0x38u, 0xfcu, 0xd1u, 0xc0u, 0x46u, 0xc0u, 0x46u, 0x70u, 0x47u, 0xefu, 0xf3u, 0x10u, 0x80u, 0x72u, 0xb6u, 0x70u, 0x47u, 0x80u, 0xf3u, 0x10u, 0x88u, 0x70u, 0x47u, 0x70u, 0x47u, 0xffu, 0xf7u, 0xfdu, 0xffu, 0x72u, 0xb6u, 0x0fu, 0x4cu, 0x10u, 0x4du, 0xacu, 0x42u, 0x09u, 0xdau, 0x21u, 0x68u, 0x62u, 0x68u, 0xa3u, 0x68u, 0x04u, 0x3bu, 0x02u, 0xdbu, 0xc8u, 0x58u, 0xd0u, 0x50u, 0xfau, 0xe7u, 0x0cu, 0x34u, 0xf3u, 0xe7u, 0x0au, 0x49u, 0x0bu, 0x4au, 0x00u, 0x20u, 0x52u, 0x1au, 0x02u, 0xddu, 0x04u, 0x3au, 0x88u, 0x50u, 0xfcu, 0xdcu, 0x08u, 0x48u, 0x09u, 0x49u, - 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x06u, 0xf0u, 0xb1u, 0xfdu, 0x06u, 0xf0u, 0x51u, 0xfdu, 0xfeu, 0xe7u, - 0x14u, 0x7fu, 0x00u, 0x10u, 0x2cu, 0x7fu, 0x00u, 0x10u, 0x00u, 0x04u, 0x00u, 0x08u, 0x5cu, 0x06u, 0x00u, 0x08u, + 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x06u, 0xf0u, 0xc7u, 0xfdu, 0x06u, 0xf0u, 0x67u, 0xfdu, 0xfeu, 0xe7u, + 0x3cu, 0x7fu, 0x00u, 0x10u, 0x54u, 0x7fu, 0x00u, 0x10u, 0xf8u, 0x03u, 0x00u, 0x08u, 0x58u, 0x06u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x08u, 0x08u, 0xedu, 0x00u, 0xe0u, 0xfeu, 0xe7u, 0xfeu, 0xe7u, 0x00u, 0xb5u, 0x04u, 0x20u, 0x71u, 0x46u, 0x08u, 0x42u, 0x02u, 0xd0u, 0xefu, 0xf3u, 0x09u, 0x80u, 0x01u, 0xe0u, 0xefu, 0xf3u, 0x08u, 0x80u, - 0x04u, 0x30u, 0x06u, 0xf0u, 0x43u, 0xfbu, 0xfeu, 0xe7u, 0xf7u, 0xb5u, 0x03u, 0x27u, 0x11u, 0x4eu, 0x14u, 0x00u, + 0x04u, 0x30u, 0x06u, 0xf0u, 0x59u, 0xfbu, 0xfeu, 0xe7u, 0xf7u, 0xb5u, 0x03u, 0x27u, 0x11u, 0x4eu, 0x14u, 0x00u, 0x32u, 0x68u, 0x05u, 0x00u, 0x52u, 0x69u, 0x82u, 0x18u, 0x08u, 0x78u, 0x49u, 0x68u, 0x38u, 0x40u, 0x10u, 0x60u, 0x01u, 0x2cu, 0x00u, 0xd1u, 0x20u, 0x31u, 0x28u, 0x00u, 0x08u, 0x9au, 0x01u, 0x3cu, 0x03u, 0xf0u, 0x72u, 0xfdu, 0x0cu, 0x23u, 0x61u, 0x42u, 0x61u, 0x41u, 0x00u, 0x93u, 0x28u, 0x00u, 0x08u, 0x3bu, 0x44u, 0x31u, 0x00u, 0x22u, 0x03u, 0xf0u, 0xd0u, 0xfdu, 0x33u, 0x68u, 0x1bu, 0x68u, 0xedu, 0x18u, 0x01u, 0x23u, 0x2au, 0x68u, 0x1au, 0x42u, - 0xfcu, 0xd1u, 0xf7u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0x73u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x03u, 0x26u, + 0xfcu, 0xd1u, 0xf7u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x73u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x03u, 0x26u, 0x0eu, 0x4du, 0x19u, 0x00u, 0x2bu, 0x68u, 0x00u, 0x78u, 0x5bu, 0x69u, 0x30u, 0x40u, 0xe3u, 0x18u, 0x18u, 0x60u, 0x13u, 0x00u, 0x20u, 0x00u, 0x06u, 0x9au, 0x03u, 0xf0u, 0x4du, 0xfdu, 0x08u, 0x23u, 0x20u, 0x00u, 0x00u, 0x93u, 0x00u, 0x22u, 0x04u, 0x3bu, 0x48u, 0x21u, 0x03u, 0xf0u, 0xadu, 0xfdu, 0x2bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, - 0x01u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x73u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, + 0x01u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x73u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x1du, 0x00u, 0x1au, 0x70u, 0x04u, 0x9bu, 0x02u, 0x32u, 0x6bu, 0x60u, 0xd3u, 0x00u, 0x0au, 0x00u, 0x04u, 0x99u, 0x04u, 0x00u, 0x03u, 0xf0u, 0xceu, 0xfdu, 0x03u, 0x21u, 0x0du, 0x4eu, 0x2au, 0x78u, 0x33u, 0x68u, 0x0au, 0x40u, 0x5bu, 0x69u, 0x69u, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0x0au, 0x00u, 0x20u, 0x00u, 0x20u, 0x32u, 0x03u, 0xf0u, 0x06u, 0xfdu, 0x08u, 0x23u, 0x20u, 0x00u, 0x00u, 0x22u, 0x46u, 0x21u, 0x03u, 0xf0u, 0x6cu, 0xfdu, 0x33u, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x01u, 0x23u, 0x20u, 0x68u, 0x18u, 0x40u, 0xfcu, 0xd1u, 0x70u, 0xbdu, - 0x20u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x16u, 0x00u, 0x1au, 0x00u, 0x0au, 0x9bu, 0x05u, 0x00u, + 0x18u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x16u, 0x00u, 0x1au, 0x00u, 0x0au, 0x9bu, 0x05u, 0x00u, 0x5cu, 0x68u, 0x03u, 0x91u, 0x27u, 0x00u, 0x40u, 0x37u, 0x39u, 0x00u, 0x50u, 0x34u, 0x10u, 0x23u, 0x03u, 0xf0u, 0xa1u, 0xfdu, 0x23u, 0x00u, 0x03u, 0x9au, 0x0au, 0x99u, 0x28u, 0x00u, 0x00u, 0x97u, 0xffu, 0xf7u, 0x74u, 0xffu, 0x28u, 0x00u, 0x10u, 0x23u, 0x22u, 0x00u, 0x31u, 0x00u, 0x03u, 0xf0u, 0x94u, 0xfdu, 0x00u, 0x20u, 0x05u, 0xb0u, @@ -99,7 +99,7 @@ const uint8_t cy_m0p_image[] = { 0xd3u, 0xfeu, 0x10u, 0x23u, 0x2au, 0x00u, 0x07u, 0x99u, 0x30u, 0x00u, 0x03u, 0xf0u, 0xcbu, 0xfcu, 0x10u, 0x3cu, 0xcfu, 0xe7u, 0x01u, 0x48u, 0xdfu, 0xe7u, 0xc0u, 0x46u, 0x02u, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x91u, 0xb0u, 0x19u, 0x9du, 0x04u, 0x00u, 0x06u, 0x91u, 0x0bu, 0x92u, 0x00u, 0x21u, 0x10u, 0x22u, 0x0cu, 0xa8u, 0x07u, 0x93u, - 0x06u, 0xf0u, 0xafu, 0xfeu, 0x6bu, 0x68u, 0x0cu, 0xa9u, 0x1au, 0x00u, 0x40u, 0x32u, 0x03u, 0x92u, 0x60u, 0x33u, + 0x06u, 0xf0u, 0xc5u, 0xfeu, 0x6bu, 0x68u, 0x0cu, 0xa9u, 0x1au, 0x00u, 0x40u, 0x32u, 0x03u, 0x92u, 0x60u, 0x33u, 0x10u, 0x32u, 0x04u, 0x92u, 0x05u, 0x93u, 0x07u, 0x9au, 0x10u, 0x23u, 0x20u, 0x00u, 0x03u, 0xf0u, 0xaau, 0xfcu, 0x0fu, 0x9bu, 0x1bu, 0xbau, 0x08u, 0x93u, 0x06u, 0x9bu, 0x08u, 0x9eu, 0x1bu, 0x09u, 0x0au, 0x93u, 0x0eu, 0x9bu, 0x1fu, 0xbau, 0x08u, 0x9bu, 0x17u, 0x99u, 0xf3u, 0x1au, 0x1au, 0x01u, 0x89u, 0x18u, 0x09u, 0x91u, 0x18u, 0x99u, @@ -111,32 +111,32 @@ const uint8_t cy_m0p_image[] = { 0x0eu, 0x92u, 0x00u, 0x93u, 0x04u, 0x9au, 0x03u, 0x9bu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x6cu, 0xfeu, 0x10u, 0x23u, 0x04u, 0x9au, 0x09u, 0x99u, 0x20u, 0x00u, 0x03u, 0xf0u, 0x64u, 0xfcu, 0xc1u, 0xe7u, 0x00u, 0x00u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, - 0xfcu, 0xd1u, 0x70u, 0x47u, 0x20u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x17u, 0x00u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, + 0xfcu, 0xd1u, 0x70u, 0x47u, 0x18u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x17u, 0x00u, 0x1eu, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x08u, 0x2du, 0x04u, 0xd0u, 0x0cu, 0x4au, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x04u, 0xe0u, 0x86u, 0x22u, 0x52u, 0x01u, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0xe2u, 0x21u, 0x08u, 0x4bu, 0xc9u, 0x05u, 0x1bu, 0x68u, 0x0du, 0x43u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x15u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x26u, 0x60u, - 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x10u, 0x00u, 0x00u, 0x20u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x07u, 0x00u, + 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x10u, 0x00u, 0x00u, 0x18u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x07u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, 0x1du, 0x00u, 0x38u, 0x00u, 0xffu, 0xf7u, 0xbau, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x24u, 0x03u, 0x1bu, 0x68u, 0x2du, 0x04u, 0xd8u, 0x68u, 0x80u, 0x23u, 0xdbu, 0x05u, 0x1eu, 0x43u, - 0x34u, 0x43u, 0x38u, 0x18u, 0x2cu, 0x43u, 0x04u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, + 0x34u, 0x43u, 0x38u, 0x18u, 0x2cu, 0x43u, 0x04u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0xa1u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x24u, 0x02u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xedu, 0x18u, 0xd0u, 0x23u, 0xdbu, 0x05u, - 0x1eu, 0x43u, 0x34u, 0x43u, 0x2cu, 0x60u, 0x70u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, + 0x1eu, 0x43u, 0x34u, 0x43u, 0x2cu, 0x60u, 0x70u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x8du, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, - 0xe4u, 0x18u, 0xa0u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, + 0xe4u, 0x18u, 0xa0u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7bu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0xa2u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x67u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x06u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, - 0x20u, 0x04u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x78u, 0x4au, 0x68u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x78u, 0x4au, 0x68u, 0x02u, 0x34u, 0xe4u, 0x00u, 0x23u, 0x00u, 0x0eu, 0x00u, 0x08u, 0x21u, 0xffu, 0xf7u, 0x5du, 0xffu, 0x10u, 0x23u, 0x08u, 0x22u, 0x04u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x81u, 0xffu, 0x23u, 0x00u, 0x10u, 0x3bu, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x08u, 0x22u, 0x05u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x78u, 0xffu, 0x03u, 0x21u, 0x05u, 0x4bu, 0x32u, 0x78u, 0x1bu, 0x68u, 0x0au, 0x40u, 0x5bu, 0x69u, 0x28u, 0x00u, 0xebu, 0x18u, 0x1au, 0x60u, 0xffu, 0xf7u, - 0x39u, 0xffu, 0x70u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0bu, 0x78u, 0x02u, 0x33u, + 0x39u, 0xffu, 0x70u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0bu, 0x78u, 0x02u, 0x33u, 0xdcu, 0x00u, 0xffu, 0xf7u, 0xd1u, 0xffu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x90u, 0xffu, 0x10u, 0x23u, 0x06u, 0x22u, 0x04u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x5au, 0xffu, 0x23u, 0x00u, 0x10u, 0x3bu, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x07u, 0x22u, 0x05u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x51u, 0xffu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x1au, 0xffu, @@ -164,7 +164,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x21u, 0xffu, 0xf7u, 0xa3u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe2u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x5fu, 0xfeu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x08u, 0x4bu, 0x09u, 0x4au, 0x1bu, 0x68u, 0x02u, 0x21u, 0xdbu, 0x68u, 0x20u, 0x00u, 0xe3u, 0x18u, 0x1au, 0x60u, 0x10u, 0x23u, 0x00u, 0x22u, 0xffu, 0xf7u, 0x8fu, 0xfeu, 0x10u, 0x3du, - 0xdfu, 0xe7u, 0x04u, 0x48u, 0xbfu, 0xe7u, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, + 0xdfu, 0xe7u, 0x04u, 0x48u, 0xbfu, 0xe7u, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, 0x21u, 0xc0u, 0x10u, 0x41u, 0x02u, 0x00u, 0x32u, 0x00u, 0xf7u, 0xb5u, 0x0fu, 0x26u, 0x04u, 0x00u, 0x01u, 0x91u, 0x15u, 0x00u, 0x1fu, 0x00u, 0x16u, 0x40u, 0x5eu, 0xd1u, 0x0au, 0x99u, 0xffu, 0xf7u, 0xe5u, 0xfeu, 0x10u, 0x23u, 0x3au, 0x00u, 0x09u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x47u, 0xfeu, 0x10u, 0x23u, 0x09u, 0x22u, 0x31u, 0x00u, @@ -178,7 +178,7 @@ const uint8_t cy_m0p_image[] = { 0x1au, 0x60u, 0x10u, 0x23u, 0x00u, 0x22u, 0xffu, 0xf7u, 0x31u, 0xfeu, 0x10u, 0x3du, 0x00u, 0x2du, 0xe8u, 0xd1u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf7u, 0xfdu, 0x10u, 0x22u, 0x39u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, 0x10u, 0x23u, 0x00u, 0x22u, 0x0cu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x20u, 0xfeu, 0x20u, 0x00u, 0xffu, 0xf7u, - 0xe9u, 0xfdu, 0x00u, 0x20u, 0xfeu, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, + 0xe9u, 0xfdu, 0x00u, 0x20u, 0xfeu, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x01u, 0xc0u, 0x10u, 0x41u, 0x18u, 0x00u, 0x10u, 0x41u, 0x02u, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x1du, 0x00u, 0x8bu, 0xb0u, 0x04u, 0x92u, 0x6au, 0x78u, 0x1bu, 0x78u, 0x12u, 0x02u, 0x1au, 0x43u, 0xabu, 0x78u, 0x04u, 0x00u, 0x1bu, 0x04u, 0x1au, 0x43u, 0xebu, 0x78u, 0x2eu, 0x7au, 0x1bu, 0x06u, 0x13u, 0x43u, 0x6au, 0x79u, 0x06u, 0x93u, @@ -203,7 +203,7 @@ const uint8_t cy_m0p_image[] = { 0xf2u, 0xb2u, 0x0fu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x83u, 0xfdu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x28u, 0xfdu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x08u, 0x4bu, 0x09u, 0x4au, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1du, 0xfdu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x03u, 0x4bu, 0x04u, 0x4au, 0x1bu, 0x68u, - 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0xb3u, 0xe7u, 0x20u, 0x04u, 0x00u, 0x08u, 0x10u, 0x10u, 0x00u, 0x66u, + 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0xb3u, 0xe7u, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0x10u, 0x00u, 0x66u, 0x10u, 0x10u, 0x00u, 0x67u, 0x02u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x0fu, 0x32u, 0x44u, 0x1eu, 0x11u, 0x78u, 0x01u, 0x3au, 0x49u, 0x00u, 0x0bu, 0x43u, 0x53u, 0x70u, 0x1bu, 0x0au, 0x94u, 0x42u, 0xf7u, 0xd1u, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x79u, 0x23u, 0xc2u, 0x7bu, 0x5bu, 0x42u, 0x53u, 0x40u, 0xc3u, 0x73u, 0x10u, 0xbdu, 0xf7u, 0xb5u, @@ -230,34 +230,34 @@ const uint8_t cy_m0p_image[] = { 0xa0u, 0x36u, 0x80u, 0x33u, 0x33u, 0x60u, 0x03u, 0x9bu, 0x90u, 0x34u, 0x73u, 0x60u, 0x32u, 0x00u, 0x0cu, 0x99u, 0x28u, 0x00u, 0xb4u, 0x60u, 0xffu, 0xf7u, 0x53u, 0xffu, 0x02u, 0x9bu, 0x32u, 0x00u, 0x0cu, 0x99u, 0x28u, 0x00u, 0x00u, 0x97u, 0xffu, 0xf7u, 0x61u, 0xffu, 0x28u, 0x00u, 0x0bu, 0x9bu, 0x32u, 0x00u, 0x0cu, 0x99u, 0xffu, 0xf7u, - 0x8du, 0xffu, 0x00u, 0x20u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, - 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, 0x20u, 0x04u, 0x00u, 0x08u, + 0x8du, 0xffu, 0x00u, 0x20u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, + 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf1u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0xa0u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x02u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x0fu, 0x32u, 0x44u, 0x1eu, 0x11u, 0x78u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x02u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x0fu, 0x32u, 0x44u, 0x1eu, 0x11u, 0x78u, 0x01u, 0x3au, 0x49u, 0x00u, 0x0bu, 0x43u, 0x53u, 0x70u, 0x1bu, 0x0au, 0x94u, 0x42u, 0xf7u, 0xd1u, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x79u, 0x23u, 0xc2u, 0x7bu, 0x5bu, 0x42u, 0x53u, 0x40u, 0xc3u, 0x73u, 0x10u, 0xbdu, 0x00u, 0x00u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc7u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x86u, 0x22u, 0x52u, 0x01u, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x06u, 0x4bu, 0x07u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, - 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, + 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa8u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x07u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, - 0x15u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x10u, 0x23u, 0x23u, 0x60u, 0x70u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, + 0x15u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x10u, 0x23u, 0x23u, 0x60u, 0x70u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x00u, 0x23u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x0bu, 0x60u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x8cu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x14u, 0x4du, 0x15u, 0x4au, 0x2bu, 0x68u, 0x20u, 0x00u, 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0xffu, 0xf7u, 0x8bu, 0xffu, 0x71u, 0x68u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcfu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x2au, 0x68u, 0x0du, 0x49u, 0xd3u, 0x68u, 0xe3u, 0x18u, 0x19u, 0x60u, 0x13u, 0x68u, 0xe3u, 0x18u, 0x1au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u, 0x70u, 0x68u, 0xffu, 0xf7u, 0x87u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x68u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, - 0x2bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x04u, 0x4bu, 0x23u, 0x60u, 0x70u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, + 0x2bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x04u, 0x4bu, 0x23u, 0x60u, 0x70u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x00u, 0x00u, 0x10u, 0x41u, 0x01u, 0xc0u, 0x10u, 0x40u, 0x11u, 0x10u, 0x10u, 0x41u, 0x70u, 0xb5u, 0x0eu, 0x00u, 0x11u, 0x00u, 0x32u, 0x68u, 0x05u, 0x00u, 0x9cu, 0x18u, 0x1au, 0x00u, 0xffu, 0xf7u, 0x81u, 0xffu, 0x10u, 0x2cu, 0x01u, 0xd8u, 0x34u, 0x60u, 0x70u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x48u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x28u, 0x00u, 0xdbu, 0x68u, 0x10u, 0x3cu, 0xebu, 0x18u, 0x1au, 0x60u, - 0xffu, 0xf7u, 0x46u, 0xffu, 0xebu, 0xe7u, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, + 0xffu, 0xf7u, 0x46u, 0xffu, 0xebu, 0xe7u, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, 0xf0u, 0xb5u, 0x10u, 0x25u, 0x87u, 0xb0u, 0x0fu, 0x00u, 0x04u, 0x00u, 0x01u, 0x92u, 0x00u, 0x21u, 0x2au, 0x00u, - 0x02u, 0xa8u, 0x06u, 0xf0u, 0xbeu, 0xf9u, 0x80u, 0x23u, 0x7eu, 0x68u, 0x3fu, 0x68u, 0x02u, 0xaau, 0x13u, 0x70u, + 0x02u, 0xa8u, 0x06u, 0xf0u, 0xd4u, 0xf9u, 0x80u, 0x23u, 0x7eu, 0x68u, 0x3fu, 0x68u, 0x02u, 0xaau, 0x13u, 0x70u, 0x02u, 0xa9u, 0xeau, 0x1bu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x53u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x18u, 0x4du, 0x19u, 0x4au, 0x2bu, 0x68u, 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0x0fu, 0x2fu, 0x02u, 0xd8u, 0x30u, 0x00u, 0xffu, 0xf7u, 0x2du, 0xffu, 0x10u, 0x22u, 0x31u, 0x00u, 0x20u, 0x00u, @@ -265,10 +265,10 @@ const uint8_t cy_m0p_image[] = { 0x0fu, 0x4au, 0xdbu, 0x68u, 0x20u, 0x00u, 0xe3u, 0x18u, 0x1au, 0x60u, 0xffu, 0xf7u, 0x09u, 0xffu, 0x01u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4du, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf8u, 0xfeu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x2au, 0x68u, 0x08u, 0x49u, 0xd3u, 0x68u, 0xe3u, 0x18u, 0x19u, 0x60u, 0x13u, 0x68u, 0xe4u, 0x18u, 0x23u, 0x68u, - 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, + 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, 0x08u, 0x00u, 0x10u, 0x41u, 0x01u, 0xc0u, 0x10u, 0x40u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x1eu, 0x00u, 0xa7u, 0xb0u, 0x2cu, 0xabu, 0x0au, 0xadu, 0x1fu, 0x78u, 0x02u, 0x91u, 0x03u, 0x92u, 0x00u, 0x21u, 0x70u, 0x22u, 0x28u, 0x00u, - 0x06u, 0xf0u, 0x67u, 0xf9u, 0x18u, 0x22u, 0x00u, 0x21u, 0x04u, 0xa8u, 0x06u, 0xf0u, 0x62u, 0xf9u, 0x3au, 0x00u, + 0x06u, 0xf0u, 0x7du, 0xf9u, 0x18u, 0x22u, 0x00u, 0x21u, 0x04u, 0xa8u, 0x06u, 0xf0u, 0x78u, 0xf9u, 0x3au, 0x00u, 0x2eu, 0x9bu, 0x31u, 0x00u, 0x00u, 0x95u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf3u, 0xfbu, 0x2eu, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xaau, 0xfbu, 0x06u, 0xabu, 0x04u, 0xa9u, 0x20u, 0x00u, 0x05u, 0x93u, 0xffu, 0xf7u, 0x2au, 0xffu, 0x03u, 0x9bu, 0x02u, 0x9au, 0x04u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x60u, 0xffu, 0x20u, 0x00u, 0x2du, 0x9au, @@ -276,30 +276,30 @@ const uint8_t cy_m0p_image[] = { 0x0cu, 0x4cu, 0x7fu, 0x00u, 0x25u, 0x68u, 0xdbu, 0xb2u, 0x2cu, 0x6au, 0x06u, 0x19u, 0x05u, 0x9cu, 0x24u, 0x02u, 0x3cu, 0x40u, 0xffu, 0x3fu, 0x3au, 0x40u, 0x22u, 0x43u, 0x32u, 0x60u, 0x6au, 0x6au, 0x82u, 0x18u, 0x13u, 0x60u, 0xabu, 0x6au, 0xc3u, 0x18u, 0x19u, 0x60u, 0xebu, 0x6au, 0xc0u, 0x18u, 0x06u, 0x9bu, 0x03u, 0x60u, 0x00u, 0x20u, - 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0du, 0x00u, 0x11u, 0x00u, 0x86u, 0x22u, + 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0du, 0x00u, 0x11u, 0x00u, 0x86u, 0x22u, 0x04u, 0x00u, 0x04u, 0x98u, 0xd2u, 0x00u, 0xa0u, 0x50u, 0x1au, 0x00u, 0x20u, 0x00u, 0x02u, 0xf0u, 0x68u, 0xfeu, 0x04u, 0x23u, 0x00u, 0x22u, 0x58u, 0x21u, 0x20u, 0x00u, 0x02u, 0xf0u, 0xceu, 0xfeu, 0x08u, 0x21u, 0x06u, 0x4bu, 0x1au, 0x68u, 0x13u, 0x68u, 0xe3u, 0x18u, 0x18u, 0x68u, 0x08u, 0x40u, 0xfcu, 0xd1u, 0x13u, 0x6bu, 0xe4u, 0x18u, - 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, - 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x20u, 0x04u, 0x00u, 0x08u, + 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, + 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0fu, 0x26u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x9cu, 0x68u, 0x05u, 0x19u, 0x2cu, 0x68u, 0x34u, 0x40u, 0x04u, 0x2cu, 0xfbu, 0xd8u, 0xdcu, 0x68u, 0x06u, 0x4du, 0x04u, 0x19u, 0x25u, 0x60u, 0xdcu, 0x68u, 0x04u, 0x19u, - 0x21u, 0x60u, 0xdbu, 0x68u, 0xc0u, 0x18u, 0x02u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, + 0x21u, 0x60u, 0xdbu, 0x68u, 0xc0u, 0x18u, 0x02u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x70u, 0x10u, 0xb5u, 0x0fu, 0x24u, 0x06u, 0x4bu, 0x19u, 0x68u, 0x8bu, 0x68u, 0xc2u, 0x18u, 0x13u, 0x68u, 0x23u, 0x40u, 0x06u, 0x2bu, 0xfbu, 0xd8u, 0xcbu, 0x68u, 0xc0u, 0x18u, 0xb0u, 0x23u, 0xdbu, 0x05u, - 0x03u, 0x60u, 0x10u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x80u, 0x27u, 0x0cu, 0x4cu, 0x7fu, 0x00u, + 0x03u, 0x60u, 0x10u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x80u, 0x27u, 0x0cu, 0x4cu, 0x7fu, 0x00u, 0x25u, 0x68u, 0xdbu, 0xb2u, 0x2cu, 0x6au, 0x06u, 0x19u, 0x05u, 0x9cu, 0x24u, 0x02u, 0x3cu, 0x40u, 0xffu, 0x3fu, 0x3au, 0x40u, 0x22u, 0x43u, 0x32u, 0x60u, 0x6au, 0x6au, 0x82u, 0x18u, 0x13u, 0x60u, 0xabu, 0x6au, 0xc3u, 0x18u, 0x19u, 0x60u, 0xebu, 0x6au, 0xc0u, 0x18u, 0x06u, 0x9bu, 0x03u, 0x60u, 0x00u, 0x20u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0du, 0x00u, 0x11u, 0x00u, 0x1au, 0x00u, 0x04u, 0x00u, 0xffu, 0xf7u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x0du, 0x00u, 0x11u, 0x00u, 0x1au, 0x00u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xafu, 0xffu, 0x8cu, 0x23u, 0x04u, 0x9au, 0x5bu, 0x01u, 0xe2u, 0x50u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc2u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x9bu, 0xffu, 0x04u, 0x4bu, 0x00u, 0x20u, 0x1bu, 0x68u, 0x1bu, 0x6bu, 0xe4u, 0x18u, - 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, 0x7fu, 0xb5u, 0x0du, 0x00u, + 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x7fu, 0xb5u, 0x0du, 0x00u, 0x19u, 0x00u, 0x0eu, 0x4bu, 0x16u, 0x00u, 0x03u, 0x93u, 0x09u, 0x9au, 0x08u, 0x9bu, 0x04u, 0x00u, 0x02u, 0xf0u, 0xf1u, 0xfdu, 0x03u, 0xabu, 0x69u, 0x00u, 0x59u, 0x18u, 0x08u, 0x23u, 0x89u, 0x5du, 0x20u, 0x00u, 0x00u, 0x93u, 0x00u, 0x22u, 0x04u, 0x3bu, 0x02u, 0xf0u, 0x4eu, 0xfeu, 0x05u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x02u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x7fu, 0xbdu, 0xc0u, 0x46u, 0x70u, 0x71u, 0x72u, 0x73u, - 0x20u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x05u, 0x93u, 0x20u, 0x4bu, 0x05u, 0x00u, 0x1bu, 0x68u, + 0x18u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x05u, 0x93u, 0x20u, 0x4bu, 0x05u, 0x00u, 0x1bu, 0x68u, 0x04u, 0x91u, 0x03u, 0x92u, 0x1fu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1fu, 0x68u, 0x00u, 0x26u, 0x1bu, 0x4bu, 0xf2u, 0x00u, 0xd2u, 0x18u, 0x03u, 0x99u, 0x08u, 0x23u, 0x28u, 0x00u, 0x02u, 0xf0u, 0x9cu, 0xfeu, 0x44u, 0x1eu, 0xa0u, 0x41u, 0x44u, 0x42u, 0x17u, 0x48u, 0x17u, 0x4bu, 0x04u, 0x40u, 0x01u, 0x36u, 0xe4u, 0x18u, @@ -307,8 +307,8 @@ const uint8_t cy_m0p_image[] = { 0x03u, 0x9au, 0x02u, 0x99u, 0x28u, 0x00u, 0x08u, 0x23u, 0x02u, 0xf0u, 0x4cu, 0xfeu, 0x08u, 0x36u, 0x0cu, 0x9au, 0x39u, 0x00u, 0x28u, 0x00u, 0x08u, 0x23u, 0x02u, 0xf0u, 0x45u, 0xfeu, 0x02u, 0x9bu, 0x04u, 0x9au, 0x28u, 0x00u, 0x01u, 0x97u, 0x00u, 0x96u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa1u, 0xffu, 0x28u, 0x00u, 0x08u, 0x23u, 0x32u, 0x00u, - 0x05u, 0x99u, 0x02u, 0xf0u, 0x37u, 0xfeu, 0x20u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, - 0x20u, 0x72u, 0x00u, 0x10u, 0xfdu, 0xffu, 0xceu, 0xffu, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x89u, 0xb0u, + 0x05u, 0x99u, 0x02u, 0xf0u, 0x37u, 0xfeu, 0x20u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, + 0x48u, 0x72u, 0x00u, 0x10u, 0xfdu, 0xffu, 0xceu, 0xffu, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x89u, 0xb0u, 0x07u, 0x93u, 0x25u, 0x4bu, 0x04u, 0x00u, 0x1bu, 0x68u, 0x06u, 0x91u, 0x04u, 0x92u, 0x03u, 0x93u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x03u, 0x93u, 0x00u, 0x27u, 0x1fu, 0x4bu, 0x04u, 0x9du, 0xfeu, 0x00u, 0xf6u, 0x18u, 0x2bu, 0x00u, 0x10u, 0x33u, 0x05u, 0x93u, 0x08u, 0x23u, 0x32u, 0x00u, 0x29u, 0x00u, @@ -318,20 +318,20 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x08u, 0x23u, 0x02u, 0xf0u, 0xf6u, 0xfdu, 0x03u, 0x9fu, 0x03u, 0x9bu, 0x08u, 0x37u, 0x01u, 0x93u, 0x06u, 0x9au, 0x33u, 0x00u, 0x20u, 0x00u, 0x00u, 0x97u, 0x01u, 0x21u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x3au, 0x00u, 0x07u, 0x99u, 0x02u, 0xf0u, 0xe5u, 0xfdu, 0x28u, 0x00u, 0x09u, 0xb0u, 0xf0u, 0xbdu, - 0x08u, 0x35u, 0xcau, 0xe7u, 0x02u, 0x4du, 0xd4u, 0xe7u, 0x20u, 0x04u, 0x00u, 0x08u, 0x20u, 0x72u, 0x00u, 0x10u, + 0x08u, 0x35u, 0xcau, 0xe7u, 0x02u, 0x4du, 0xd4u, 0xe7u, 0x18u, 0x04u, 0x00u, 0x08u, 0x48u, 0x72u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, 0x70u, 0xb5u, 0x0fu, 0x26u, 0x0bu, 0x4bu, 0x1bu, 0x68u, 0x9cu, 0x68u, 0x05u, 0x19u, 0x2cu, 0x68u, 0x34u, 0x40u, 0x04u, 0x2cu, 0xfbu, 0xd8u, 0x86u, 0x25u, 0x6du, 0x01u, 0x44u, 0x59u, 0x00u, 0x2cu, 0xfcu, 0xdbu, 0xdcu, 0x68u, 0x05u, 0x4du, 0x04u, 0x19u, 0x25u, 0x60u, 0xdcu, 0x68u, 0x04u, 0x19u, 0x21u, 0x60u, - 0xdbu, 0x68u, 0xc0u, 0x18u, 0x02u, 0x60u, 0x70u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, + 0xdbu, 0x68u, 0xc0u, 0x18u, 0x02u, 0x60u, 0x70u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, 0x30u, 0xb5u, 0x0fu, 0x25u, 0x06u, 0x4bu, 0x1cu, 0x68u, 0xa3u, 0x68u, 0xc2u, 0x18u, 0x13u, 0x68u, 0x2bu, 0x40u, 0x06u, 0x2bu, 0xfbu, 0xd8u, 0xe3u, 0x68u, 0x09u, 0x06u, 0xc0u, 0x18u, 0x01u, 0x60u, 0x30u, 0xbdu, 0xc0u, 0x46u, - 0x20u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x0fu, 0x27u, 0x09u, 0x4cu, 0x26u, 0x68u, 0xb4u, 0x68u, 0x05u, 0x19u, + 0x18u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x0fu, 0x27u, 0x09u, 0x4cu, 0x26u, 0x68u, 0xb4u, 0x68u, 0x05u, 0x19u, 0x2cu, 0x68u, 0x3cu, 0x40u, 0x06u, 0x2cu, 0xfbu, 0xd8u, 0xf4u, 0x68u, 0x09u, 0x03u, 0x00u, 0x19u, 0x80u, 0x24u, 0xe4u, 0x05u, 0x22u, 0x43u, 0x11u, 0x43u, 0x1bu, 0x04u, 0x19u, 0x43u, 0x01u, 0x60u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x30u, 0xb5u, 0x0fu, 0x25u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x9au, 0x68u, 0x84u, 0x18u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x30u, 0xb5u, 0x0fu, 0x25u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x9au, 0x68u, 0x84u, 0x18u, 0x22u, 0x68u, 0x2au, 0x40u, 0x04u, 0x2au, 0xfbu, 0xd8u, 0xdau, 0x68u, 0x06u, 0x4cu, 0x82u, 0x18u, 0x14u, 0x60u, 0xdau, 0x68u, 0x82u, 0x18u, 0x11u, 0x60u, 0xdbu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x23u, 0x03u, 0x60u, 0x30u, 0xbdu, - 0x20u, 0x04u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x16u, 0x00u, 0x1fu, 0x00u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x16u, 0x00u, 0x1fu, 0x00u, 0x00u, 0x25u, 0x01u, 0x91u, 0x1cu, 0x4bu, 0xeau, 0x00u, 0xd2u, 0x18u, 0x31u, 0x00u, 0x08u, 0x23u, 0x20u, 0x00u, 0x02u, 0xf0u, 0xb2u, 0xfeu, 0x00u, 0x28u, 0x2cu, 0xd0u, 0x01u, 0x35u, 0x10u, 0x2du, 0xf2u, 0xd1u, 0x00u, 0x25u, 0x31u, 0x00u, 0x20u, 0x00u, 0x08u, 0x22u, 0xffu, 0xf7u, 0x85u, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, @@ -339,7 +339,7 @@ const uint8_t cy_m0p_image[] = { 0x39u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbeu, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa0u, 0xffu, 0x01u, 0x99u, 0x20u, 0x00u, 0x4bu, 0x1eu, 0x99u, 0x41u, 0x52u, 0x31u, 0xffu, 0xf7u, 0x87u, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x01u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0x93u, 0xffu, 0x28u, 0x00u, - 0xfeu, 0xbdu, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xc0u, 0x46u, 0xa0u, 0x72u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, + 0xfeu, 0xbdu, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xc0u, 0x46u, 0xc8u, 0x72u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x27u, 0x85u, 0xb0u, 0x02u, 0x91u, 0x00u, 0x92u, 0x03u, 0x93u, 0x26u, 0x4bu, 0x00u, 0x9du, 0xfeu, 0x00u, 0xf6u, 0x18u, 0x2bu, 0x00u, 0x10u, 0x33u, 0x01u, 0x93u, 0x08u, 0x23u, 0x32u, 0x00u, 0x29u, 0x00u, 0x20u, 0x00u, 0x02u, 0xf0u, 0x68u, 0xfeu, 0x00u, 0x28u, 0x04u, 0xd0u, 0x01u, 0x9bu, 0x9du, 0x42u, @@ -350,15 +350,15 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0xffu, 0xf7u, 0x67u, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x49u, 0xffu, 0x02u, 0x99u, 0x20u, 0x00u, 0x4bu, 0x1eu, 0x99u, 0x41u, 0x54u, 0x31u, 0xffu, 0xf7u, 0x30u, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x01u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0x3cu, 0xffu, 0x28u, 0x00u, 0x05u, 0xb0u, - 0xf0u, 0xbdu, 0x08u, 0x35u, 0xbau, 0xe7u, 0xc0u, 0x46u, 0xa0u, 0x72u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, + 0xf0u, 0xbdu, 0x08u, 0x35u, 0xbau, 0xe7u, 0xc0u, 0x46u, 0xc8u, 0x72u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, 0x42u, 0x1eu, 0x03u, 0x00u, 0x00u, 0x20u, 0x04u, 0x2au, 0x03u, 0xd8u, 0x28u, 0x30u, 0x58u, 0x43u, 0x01u, 0x4bu, - 0xc0u, 0x18u, 0x70u, 0x47u, 0x20u, 0x73u, 0x00u, 0x10u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, + 0xc0u, 0x18u, 0x70u, 0x47u, 0x48u, 0x73u, 0x00u, 0x10u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xf2u, 0xf9u, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, - 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xdfu, 0xf9u, 0x10u, 0xbdu, 0x2cu, 0x06u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xdfu, 0xf9u, 0x10u, 0xbdu, 0x28u, 0x06u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0xadu, 0xb0u, 0x04u, 0x00u, 0x04u, 0x91u, 0x05u, 0x92u, 0x03u, 0x93u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x15u, 0xe1u, 0x03u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x11u, 0xe1u, 0x32u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x0du, 0xe1u, 0x33u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x09u, 0xe1u, 0x32u, 0x9bu, 0x58u, 0x78u, 0xffu, 0xf7u, @@ -396,7 +396,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x28u, 0x00u, 0xd0u, 0x71u, 0xe7u, 0x03u, 0x9bu, 0xe9u, 0x1du, 0xc9u, 0x08u, 0x59u, 0x18u, 0x0au, 0x22u, 0x2bu, 0x00u, 0x20u, 0x00u, 0x04u, 0xf0u, 0xc4u, 0xf8u, 0x68u, 0xe7u, 0x08u, 0x4eu, 0x6bu, 0xe7u, 0x07u, 0x4eu, 0x6eu, 0xe7u, 0x07u, 0x4eu, 0x6cu, 0xe7u, 0xc0u, 0x46u, 0x09u, 0x80u, 0x00u, 0x00u, 0x01u, 0x00u, 0x32u, 0x00u, - 0x2cu, 0x06u, 0x00u, 0x08u, 0xb0u, 0xb0u, 0x00u, 0x00u, 0x0bu, 0x80u, 0x00u, 0x00u, 0x0bu, 0x00u, 0x32u, 0x00u, + 0x28u, 0x06u, 0x00u, 0x08u, 0xb0u, 0xb0u, 0x00u, 0x00u, 0x0bu, 0x80u, 0x00u, 0x00u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x0au, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x04u, 0x00u, 0x0fu, 0x1eu, 0x04u, 0x92u, 0x03u, 0x93u, 0x00u, 0xd1u, 0x8bu, 0xe1u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x88u, 0xe1u, 0x0cu, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x84u, 0xe1u, 0x0du, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x80u, 0xe1u, 0x58u, 0x78u, 0xffu, 0xf7u, 0x78u, 0xfeu, @@ -448,11 +448,11 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x21u, 0x20u, 0x00u, 0x03u, 0xf0u, 0x7au, 0xffu, 0x00u, 0x28u, 0x09u, 0xd0u, 0x01u, 0x23u, 0x0cu, 0x9au, 0x13u, 0x70u, 0x0eu, 0x49u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x27u, 0xfdu, 0x38u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x0cu, 0x9bu, 0x18u, 0x70u, 0xf5u, 0xe7u, 0x04u, 0x4fu, 0x09u, 0x49u, 0xf3u, 0xe7u, 0x02u, 0x4fu, 0xf4u, 0xe7u, - 0x08u, 0x4fu, 0xf2u, 0xe7u, 0xf5u, 0xffu, 0xcdu, 0xffu, 0x0bu, 0x00u, 0x32u, 0x00u, 0x2cu, 0x06u, 0x00u, 0x08u, + 0x08u, 0x4fu, 0xf2u, 0xe7u, 0xf5u, 0xffu, 0xcdu, 0xffu, 0x0bu, 0x00u, 0x32u, 0x00u, 0x28u, 0x06u, 0x00u, 0x08u, 0x80u, 0x80u, 0x00u, 0x00u, 0x08u, 0x60u, 0x00u, 0x00u, 0x06u, 0x80u, 0x00u, 0x00u, 0xf1u, 0x7eu, 0x00u, 0x00u, 0x30u, 0x60u, 0x00u, 0x00u, 0x0au, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, - 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xefu, 0xfeu, 0x10u, 0xbdu, 0x2cu, 0x06u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xefu, 0xfeu, 0x10u, 0xbdu, 0x28u, 0x06u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x85u, 0xb0u, 0x08u, 0x00u, 0x02u, 0x91u, 0x03u, 0x92u, 0x1eu, 0x00u, 0xffu, 0xf7u, 0xc7u, 0xfcu, 0x07u, 0x1eu, 0x00u, 0xd1u, 0x7bu, 0xe0u, 0x03u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x77u, 0xe0u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0x74u, 0xe0u, 0x73u, 0x68u, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x70u, 0xe0u, 0xb3u, 0x68u, @@ -476,25 +476,25 @@ const uint8_t cy_m0p_image[] = { 0x12u, 0x01u, 0x13u, 0x43u, 0x09u, 0x03u, 0x0bu, 0x43u, 0x36u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x44u, 0xfeu, 0x10u, 0xbdu, 0x00u, 0x00u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, - 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, - 0x2cu, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x02u, 0x4bu, 0x1bu, 0x68u, - 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x20u, 0x68u, 0x10u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0au, 0x4bu, + 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, + 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x02u, 0x4bu, 0x1bu, 0x68u, + 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x20u, 0x68u, 0x10u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0au, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u, 0x25u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x0fu, 0xfeu, 0x10u, 0xbdu, 0x0fu, 0x23u, 0x13u, 0x43u, - 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, + 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x05u, 0xd8u, 0x05u, 0x4bu, 0x21u, 0x22u, 0x00u, 0x21u, - 0x01u, 0xf0u, 0xfau, 0xfdu, 0x10u, 0xbdu, 0x03u, 0x4bu, 0xf8u, 0xe7u, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, + 0x01u, 0xf0u, 0xfau, 0xfdu, 0x10u, 0xbdu, 0x03u, 0x4bu, 0xf8u, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0xc0u, 0xc0u, 0x00u, 0x00u, 0xcfu, 0xc0u, 0x00u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x10u, 0x22u, 0x19u, 0x00u, 0x01u, 0xf0u, 0xeau, 0xfdu, 0x10u, 0xbdu, 0x09u, 0x03u, 0x0bu, 0x00u, 0x13u, 0x43u, 0x00u, 0x22u, 0x10u, 0xb5u, 0x11u, 0x00u, 0x01u, 0xf0u, 0xe1u, 0xfdu, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, - 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xcfu, 0xfdu, 0x10u, 0xbdu, 0x2cu, 0x06u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xcfu, 0xfdu, 0x10u, 0xbdu, 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, - 0x01u, 0xf0u, 0xbau, 0xfdu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x14u, 0x00u, + 0x01u, 0xf0u, 0xbau, 0xfdu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x14u, 0x00u, 0x07u, 0x4au, 0x15u, 0x68u, 0x24u, 0x22u, 0x29u, 0x35u, 0x2du, 0x78u, 0x1fu, 0x2du, 0x00u, 0xd9u, 0x01u, 0x3au, 0x24u, 0x01u, 0x23u, 0x43u, 0x09u, 0x03u, 0x0bu, 0x43u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xa5u, 0xfdu, 0x70u, 0xbdu, - 0x2cu, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x9cu, 0xfdu, + 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x9cu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x23u, 0x10u, 0xb5u, 0x11u, 0x22u, 0x19u, 0x00u, 0x01u, 0xf0u, 0x95u, 0xfdu, 0x10u, 0xbdu, 0x70u, 0xb5u, 0x04u, 0x00u, 0x1bu, 0x4du, 0xffu, 0xf7u, 0x9fu, 0xffu, 0x20u, 0x00u, 0x01u, 0x22u, 0x02u, 0x21u, 0xffu, 0xf7u, 0xa1u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x03u, 0x21u, 0xffu, 0xf7u, 0x9cu, 0xffu, 0x2au, 0x00u, @@ -527,7 +527,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x70u, 0xfeu, 0x94u, 0x4bu, 0x1bu, 0x78u, 0x00u, 0x2bu, 0x0bu, 0xd0u, 0x01u, 0x2bu, 0x01u, 0xd1u, 0x00u, 0xf0u, 0x35u, 0xfdu, 0x0eu, 0x9bu, 0x00u, 0x22u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x50u, 0xffu, 0x00u, 0xf0u, 0x24u, 0xfdu, 0x8du, 0x4bu, 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0x01u, 0xd9u, 0x00u, 0xf0u, - 0x1du, 0xfdu, 0x04u, 0xf0u, 0x79u, 0xffu, 0x05u, 0x00u, 0x89u, 0x00u, 0x25u, 0x01u, 0x73u, 0x03u, 0x18u, 0x05u, + 0x1du, 0xfdu, 0x04u, 0xf0u, 0x8fu, 0xffu, 0x05u, 0x00u, 0x89u, 0x00u, 0x25u, 0x01u, 0x73u, 0x03u, 0x18u, 0x05u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa1u, 0xfeu, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa3u, 0xfeu, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x9eu, 0xfeu, 0x80u, 0x22u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa2u, 0xfeu, 0xc0u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x9du, 0xfeu, 0xc0u, 0x22u, @@ -561,7 +561,7 @@ const uint8_t cy_m0p_image[] = { 0x43u, 0xfdu, 0x16u, 0x4bu, 0x36u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x9du, 0xfbu, 0x03u, 0x23u, 0x02u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4au, 0xfdu, 0x09u, 0x4bu, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x01u, 0xf0u, 0x91u, 0xfbu, 0x00u, 0x21u, 0x06u, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x01u, 0xf0u, - 0x8bu, 0xfbu, 0x0eu, 0x21u, 0x70u, 0xe7u, 0xc0u, 0x46u, 0xc0u, 0x00u, 0x00u, 0x08u, 0x1cu, 0x04u, 0x00u, 0x08u, + 0x8bu, 0xfbu, 0x0eu, 0x21u, 0x70u, 0xe7u, 0xc0u, 0x46u, 0xc0u, 0x00u, 0x00u, 0x08u, 0x14u, 0x04u, 0x00u, 0x08u, 0x4eu, 0x00u, 0x40u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, 0x20u, 0x30u, 0x00u, 0x00u, 0x23u, 0x20u, 0x00u, 0x00u, 0x10u, 0x20u, 0x00u, 0x00u, 0x2eu, 0x00u, 0x40u, 0x00u, 0x2eu, 0x20u, 0x30u, 0x00u, 0x2eu, 0x20u, 0x40u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x81u, 0xfdu, 0x01u, 0x22u, 0x0au, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x83u, 0xfdu, @@ -692,7 +692,7 @@ const uint8_t cy_m0p_image[] = { 0x8bu, 0xffu, 0x00u, 0x21u, 0x44u, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x85u, 0xffu, 0xe0u, 0x21u, 0x49u, 0x00u, 0xffu, 0xf7u, 0x69u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xeau, 0xf9u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd8u, 0xf9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xdcu, 0xf9u, 0x09u, 0xb0u, 0xf0u, 0xbdu, 0x42u, 0x4bu, - 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0xf1u, 0xd8u, 0x04u, 0xf0u, 0x44u, 0xfau, 0x05u, 0x00u, 0x84u, 0x00u, + 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0xf1u, 0xd8u, 0x04u, 0xf0u, 0x5au, 0xfau, 0x05u, 0x00u, 0x84u, 0x00u, 0xd1u, 0x00u, 0xc7u, 0x01u, 0xedu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x76u, 0xf9u, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x78u, 0xf9u, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x73u, 0xf9u, 0x02u, 0x22u, 0x00u, 0x21u, 0xffu, 0x32u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x76u, 0xf9u, 0x80u, 0x22u, 0x01u, 0x21u, @@ -708,7 +708,7 @@ const uint8_t cy_m0p_image[] = { 0x0bu, 0xffu, 0x00u, 0x21u, 0x0eu, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x05u, 0xffu, 0x03u, 0x21u, 0xffu, 0xf7u, 0xeau, 0xfau, 0x9eu, 0x00u, 0x40u, 0x00u, 0x9eu, 0x90u, 0x30u, 0x00u, 0x82u, 0x70u, 0x00u, 0x00u, 0x73u, 0x70u, 0x00u, 0x00u, 0x9eu, 0x90u, 0x40u, 0x00u, 0x72u, 0x70u, 0x00u, 0x00u, 0x70u, 0x70u, 0x00u, 0x00u, - 0x71u, 0x70u, 0x00u, 0x00u, 0x60u, 0x70u, 0x00u, 0x00u, 0x1cu, 0x04u, 0x00u, 0x08u, 0x12u, 0x10u, 0x00u, 0x00u, + 0x71u, 0x70u, 0x00u, 0x00u, 0x60u, 0x70u, 0x00u, 0x00u, 0x14u, 0x04u, 0x00u, 0x08u, 0x12u, 0x10u, 0x00u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf7u, 0xf8u, 0x20u, 0x00u, 0x01u, 0x22u, 0x04u, 0x21u, 0xffu, 0xf7u, 0xf9u, 0xf8u, 0x20u, 0x00u, 0x00u, 0x22u, 0x05u, 0x21u, 0xffu, 0xf7u, 0xf4u, 0xf8u, 0x42u, 0x22u, 0x20u, 0x00u, 0xffu, 0x32u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xf7u, 0xf8u, 0xa0u, 0x22u, 0x20u, 0x00u, 0x52u, 0x00u, @@ -719,7 +719,7 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0xb0u, 0xfeu, 0x00u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0x01u, 0x23u, 0xffu, 0xf7u, 0x5du, 0xf8u, 0x20u, 0x00u, 0x03u, 0x23u, 0x00u, 0x22u, 0x01u, 0x21u, 0xffu, 0xf7u, 0xeeu, 0xf8u, 0x01u, 0x23u, 0x00u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x3eu, 0xf8u, 0x7fu, 0xe7u, 0x1cu, 0x22u, - 0xb3u, 0x49u, 0x01u, 0xa8u, 0x04u, 0xf0u, 0x44u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa5u, 0xf8u, 0x01u, 0x22u, + 0xb3u, 0x49u, 0x01u, 0xa8u, 0x04u, 0xf0u, 0x5au, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa5u, 0xf8u, 0x01u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa7u, 0xf8u, 0x00u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa2u, 0xf8u, 0xe0u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa6u, 0xf8u, 0xf0u, 0x22u, 0x00u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa0u, 0xf8u, 0x80u, 0x22u, 0x01u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, @@ -750,7 +750,7 @@ const uint8_t cy_m0p_image[] = { 0x03u, 0x23u, 0x00u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x69u, 0xffu, 0x3eu, 0x23u, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xb0u, 0xfdu, 0x00u, 0x21u, 0x3eu, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xaau, 0xfdu, 0x23u, 0x21u, 0xffu, 0xf7u, 0x8fu, 0xf9u, 0x39u, 0x49u, 0x11u, 0x22u, 0x1cu, 0x31u, - 0x01u, 0xa8u, 0x04u, 0xf0u, 0x4du, 0xfau, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xaeu, 0xffu, 0x01u, 0x22u, 0x04u, 0x21u, + 0x01u, 0xa8u, 0x04u, 0xf0u, 0x63u, 0xfau, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xaeu, 0xffu, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xb0u, 0xffu, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xabu, 0xffu, 0x31u, 0x4au, 0x00u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xafu, 0xffu, 0xf0u, 0x22u, 0x01u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xa9u, 0xffu, 0x81u, 0x22u, 0x06u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xa4u, 0xffu, @@ -764,7 +764,7 @@ const uint8_t cy_m0p_image[] = { 0x4bu, 0xfdu, 0x04u, 0x23u, 0x00u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xf8u, 0xfeu, 0x4eu, 0x23u, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x3fu, 0xfdu, 0x00u, 0x21u, 0x07u, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x39u, 0xfdu, 0x43u, 0x21u, 0xffu, 0xf7u, 0x1eu, 0xf9u, 0x12u, 0x10u, 0x00u, 0x00u, - 0x15u, 0x79u, 0x00u, 0x10u, 0x3eu, 0x30u, 0x30u, 0x00u, 0x01u, 0x02u, 0x00u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, + 0x3du, 0x79u, 0x00u, 0x10u, 0x3eu, 0x30u, 0x30u, 0x00u, 0x01u, 0x02u, 0x00u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, 0x70u, 0xb5u, 0x0cu, 0x00u, 0x05u, 0x00u, 0xfeu, 0xf7u, 0xdau, 0xfeu, 0x09u, 0x4bu, 0x26u, 0x01u, 0x33u, 0x43u, 0x28u, 0x00u, 0x3du, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0x1fu, 0xfdu, 0x24u, 0x03u, 0x05u, 0x4bu, 0x34u, 0x43u, 0x28u, 0x00u, 0x23u, 0x43u, 0x37u, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0x16u, 0xfdu, 0x70u, 0xbdu, 0xc0u, 0x46u, @@ -776,7 +776,7 @@ const uint8_t cy_m0p_image[] = { 0xebu, 0xfcu, 0x0bu, 0x4bu, 0x2du, 0x03u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x07u, 0xd8u, 0x2bu, 0x00u, 0x26u, 0x22u, 0x3bu, 0x43u, 0x30u, 0x00u, 0x00u, 0x21u, 0x00u, 0xf0u, 0xddu, 0xfcu, 0xf8u, 0xbdu, 0x0fu, 0x23u, 0x2bu, 0x43u, 0x3bu, 0x43u, 0x25u, 0x22u, 0xf5u, 0xe7u, 0xc0u, 0x46u, 0x0eu, 0x00u, 0x80u, 0x00u, - 0x2cu, 0x06u, 0x00u, 0x08u, 0x07u, 0xb5u, 0x00u, 0x93u, 0x13u, 0x00u, 0xfeu, 0xf7u, 0xf5u, 0xffu, 0x07u, 0xbdu, + 0x28u, 0x06u, 0x00u, 0x08u, 0x07u, 0xb5u, 0x00u, 0x93u, 0x13u, 0x00u, 0xfeu, 0xf7u, 0xf5u, 0xffu, 0x07u, 0xbdu, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x17u, 0x00u, 0x1eu, 0x00u, 0x0du, 0x00u, 0xfeu, 0xf7u, 0xd5u, 0xfeu, 0x3au, 0x00u, 0x07u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xd7u, 0xfeu, 0x32u, 0x00u, 0x08u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xd2u, 0xfeu, 0x2au, 0x00u, 0x0bu, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xcdu, 0xfeu, 0x06u, 0x9au, 0x09u, 0x21u, @@ -871,16 +871,16 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x90u, 0x08u, 0x22u, 0x00u, 0x97u, 0x07u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd0u, 0xfeu, 0x01u, 0x22u, 0x05u, 0x9bu, 0x13u, 0x42u, 0x0au, 0xd0u, 0x0bu, 0x23u, 0x01u, 0x93u, 0x01u, 0x3bu, 0x00u, 0x93u, 0x02u, 0x97u, 0x01u, 0x3bu, 0x07u, 0x32u, 0x07u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x0eu, 0xfeu, 0x01u, 0x35u, 0xcdu, 0xe7u, - 0x2cu, 0x06u, 0x00u, 0x08u, 0xc5u, 0x60u, 0x00u, 0x00u, 0xc6u, 0xc0u, 0x00u, 0x00u, 0x20u, 0x04u, 0x00u, 0x08u, + 0x28u, 0x06u, 0x00u, 0x08u, 0xc5u, 0x60u, 0x00u, 0x00u, 0xc6u, 0xc0u, 0x00u, 0x00u, 0x18u, 0x04u, 0x00u, 0x08u, 0x80u, 0x22u, 0x0du, 0x4bu, 0x52u, 0x00u, 0x90u, 0x42u, 0x11u, 0xd0u, 0x07u, 0xd8u, 0x01u, 0x22u, 0xc0u, 0x28u, 0x0eu, 0xd0u, 0x02u, 0x22u, 0xe0u, 0x28u, 0x0bu, 0xd0u, 0x00u, 0x22u, 0x09u, 0xe0u, 0xc0u, 0x22u, 0x52u, 0x00u, 0x90u, 0x42u, 0x07u, 0xd0u, 0x05u, 0x4au, 0x90u, 0x42u, 0xf6u, 0xd1u, 0x05u, 0x22u, 0x00u, 0xe0u, 0x03u, 0x22u, - 0x1au, 0x70u, 0x70u, 0x47u, 0x04u, 0x22u, 0xfbu, 0xe7u, 0x1cu, 0x04u, 0x00u, 0x08u, 0x09u, 0x02u, 0x00u, 0x00u, + 0x1au, 0x70u, 0x70u, 0x47u, 0x04u, 0x22u, 0xfbu, 0xe7u, 0x14u, 0x04u, 0x00u, 0x08u, 0x09u, 0x02u, 0x00u, 0x00u, 0x01u, 0x4bu, 0x18u, 0x70u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xc0u, 0x00u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x05u, 0x98u, 0x00u, 0x90u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x2fu, 0xffu, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x62u, 0xfbu, 0x13u, 0xbdu, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x93u, 0xb0u, 0x05u, 0x93u, 0x1au, 0xabu, 0x1cu, 0x78u, 0x65u, 0x4bu, 0x05u, 0x00u, 0x1bu, 0x68u, 0x03u, 0x91u, 0x04u, 0x92u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, - 0x1eu, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x06u, 0xa8u, 0x03u, 0xf0u, 0x43u, 0xfeu, 0x33u, 0x00u, 0x81u, 0x33u, + 0x1eu, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x06u, 0xa8u, 0x03u, 0xf0u, 0x59u, 0xfeu, 0x33u, 0x00u, 0x81u, 0x33u, 0x22u, 0x00u, 0xffu, 0x33u, 0x06u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0xfcu, 0xfbu, 0x04u, 0x1eu, 0x00u, 0xd0u, 0x86u, 0xe0u, 0x33u, 0x00u, 0x80u, 0x33u, 0x01u, 0x93u, 0x98u, 0x23u, 0x01u, 0x9au, 0xdbu, 0x00u, 0x77u, 0x1cu, 0xf6u, 0x50u, 0xffu, 0x37u, 0xf3u, 0x18u, 0x5au, 0x60u, 0x9fu, 0x60u, 0x19u, 0x9au, 0x09u, 0x9bu, 0x9au, 0x42u, @@ -904,10 +904,10 @@ const uint8_t cy_m0p_image[] = { 0x28u, 0x00u, 0x00u, 0xf0u, 0xa7u, 0xfbu, 0x02u, 0x9au, 0x09u, 0x9bu, 0x9bu, 0x1au, 0x19u, 0x9au, 0x9bu, 0xb2u, 0xb9u, 0x18u, 0x89u, 0xe7u, 0x02u, 0x9bu, 0x18u, 0x9au, 0x39u, 0x00u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x9au, 0xfbu, 0x86u, 0xe7u, 0xfau, 0x5cu, 0x01u, 0x9cu, 0x4au, 0x40u, 0xf2u, 0x54u, 0xfau, 0x5cu, 0x42u, 0x40u, 0xe2u, 0x54u, - 0x01u, 0x33u, 0x80u, 0xe7u, 0x20u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x66u, 0x4cu, 0x05u, 0x00u, 0xa5u, 0x44u, + 0x01u, 0x33u, 0x80u, 0xe7u, 0x18u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x66u, 0x4cu, 0x05u, 0x00u, 0xa5u, 0x44u, 0x04u, 0x92u, 0x93u, 0x22u, 0x05u, 0x93u, 0x13u, 0xaeu, 0xaeu, 0xabu, 0x1cu, 0x78u, 0x03u, 0x91u, 0x92u, 0x00u, - 0x00u, 0x21u, 0x30u, 0x00u, 0x03u, 0xf0u, 0x75u, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x07u, 0xa8u, 0x03u, 0xf0u, - 0x70u, 0xfdu, 0x22u, 0x00u, 0x73u, 0xabu, 0x07u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x77u, 0xfdu, 0x04u, 0x1eu, + 0x00u, 0x21u, 0x30u, 0x00u, 0x03u, 0xf0u, 0x8bu, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x07u, 0xa8u, 0x03u, 0xf0u, + 0x86u, 0xfdu, 0x22u, 0x00u, 0x73u, 0xabu, 0x07u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x77u, 0xfdu, 0x04u, 0x1eu, 0x3bu, 0xd1u, 0x90u, 0x23u, 0x9bu, 0x00u, 0xf6u, 0x50u, 0x33u, 0xaau, 0x04u, 0x33u, 0xf2u, 0x50u, 0x0au, 0x9fu, 0x04u, 0x33u, 0x53u, 0xaau, 0xf2u, 0x50u, 0x10u, 0x9bu, 0xbeu, 0xb2u, 0x01u, 0x93u, 0x02u, 0x00u, 0x33u, 0x00u, 0x53u, 0xa9u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x6eu, 0xfcu, 0xadu, 0x9bu, 0xbbu, 0x42u, 0x2eu, 0xd9u, 0x07u, 0xa9u, @@ -937,10 +937,10 @@ const uint8_t cy_m0p_image[] = { 0x13u, 0x43u, 0x33u, 0x60u, 0x00u, 0x2du, 0x01u, 0xd1u, 0x00u, 0x29u, 0x12u, 0xd0u, 0x80u, 0x22u, 0xa3u, 0x68u, 0x52u, 0x02u, 0xc3u, 0x18u, 0x19u, 0x68u, 0x11u, 0x42u, 0xfcu, 0xd0u, 0x23u, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, - 0xfcu, 0xd1u, 0xf7u, 0xbdu, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0x20u, 0x04u, 0x00u, 0x08u, - 0x2cu, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, + 0xfcu, 0xd1u, 0xf7u, 0xbdu, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0x18u, 0x04u, 0x00u, 0x08u, + 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, - 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xb0u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xb0u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x22u, 0x0eu, 0x21u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0du, 0x21u, 0xffu, 0xf7u, 0xdfu, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0xdau, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0bu, 0x21u, 0xffu, 0xf7u, 0xd5u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0au, 0x21u, @@ -951,10 +951,10 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x00u, 0x22u, 0x03u, 0x21u, 0xffu, 0xf7u, 0xadu, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x02u, 0x21u, 0xffu, 0xf7u, 0xa8u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x01u, 0x21u, 0xffu, 0xf7u, 0xa3u, 0xffu, 0x00u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x9eu, 0xffu, 0x03u, 0x4bu, 0x0fu, 0x21u, 0x1au, 0x68u, 0x20u, 0x00u, - 0x92u, 0x08u, 0xffu, 0xf7u, 0x97u, 0xffu, 0x10u, 0xbdu, 0x24u, 0x04u, 0x00u, 0x08u, 0x05u, 0x4bu, 0x1bu, 0x68u, + 0x92u, 0x08u, 0xffu, 0xf7u, 0x97u, 0xffu, 0x10u, 0xbdu, 0x1cu, 0x04u, 0x00u, 0x08u, 0x05u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x04u, 0x4bu, 0x1fu, 0x2au, 0x00u, 0xd9u, 0x04u, 0x4bu, 0x04u, 0x4au, 0x13u, 0x60u, - 0x70u, 0x47u, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x44u, 0x79u, 0x00u, 0x10u, 0x98u, 0x79u, 0x00u, 0x10u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x2fu, 0x4bu, 0x70u, 0xb5u, 0x14u, 0x00u, 0x1au, 0x68u, 0x00u, 0x2au, 0x2cu, 0xd0u, + 0x70u, 0x47u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x6cu, 0x79u, 0x00u, 0x10u, 0xc0u, 0x79u, 0x00u, 0x10u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x2fu, 0x4bu, 0x70u, 0xb5u, 0x14u, 0x00u, 0x1au, 0x68u, 0x00u, 0x2au, 0x2cu, 0xd0u, 0x00u, 0x29u, 0x09u, 0xd1u, 0x00u, 0x2cu, 0x28u, 0xd1u, 0x13u, 0x6du, 0xc1u, 0x18u, 0x2au, 0x4bu, 0x1bu, 0x68u, 0x9cu, 0x6cu, 0x00u, 0x29u, 0x21u, 0xd0u, 0xa4u, 0x00u, 0x28u, 0x4bu, 0x65u, 0x1eu, 0x9du, 0x42u, 0x1cu, 0xd8u, 0x80u, 0x23u, 0x1bu, 0x01u, 0x9cu, 0x42u, 0x3eu, 0xd0u, 0x0du, 0xd8u, 0x80u, 0x23u, 0x9bu, 0x00u, 0x9cu, 0x42u, @@ -966,8 +966,8 @@ const uint8_t cy_m0p_image[] = { 0xebu, 0xd1u, 0x1fu, 0x2eu, 0x02u, 0xd9u, 0x10u, 0x4du, 0x1bu, 0x02u, 0x43u, 0x51u, 0x93u, 0x6bu, 0xa2u, 0x08u, 0xc3u, 0x18u, 0x19u, 0x60u, 0x0fu, 0x21u, 0xffu, 0xf7u, 0x2du, 0xffu, 0x00u, 0x20u, 0x0bu, 0x4bu, 0x1cu, 0x60u, 0x70u, 0xbdu, 0x7cu, 0x23u, 0xe4u, 0xe7u, 0x78u, 0x23u, 0xe2u, 0xe7u, 0x60u, 0x23u, 0xe0u, 0xe7u, 0x40u, 0x23u, - 0xdeu, 0xe7u, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, 0x2cu, 0x06u, 0x00u, 0x08u, 0xffu, 0x7fu, 0x00u, 0x00u, - 0x0bu, 0x00u, 0x32u, 0x00u, 0xffu, 0x3fu, 0x00u, 0x00u, 0x88u, 0x14u, 0x00u, 0x00u, 0x24u, 0x04u, 0x00u, 0x08u, + 0xdeu, 0xe7u, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x28u, 0x06u, 0x00u, 0x08u, 0xffu, 0x7fu, 0x00u, 0x00u, + 0x0bu, 0x00u, 0x32u, 0x00u, 0xffu, 0x3fu, 0x00u, 0x00u, 0x88u, 0x14u, 0x00u, 0x00u, 0x1cu, 0x04u, 0x00u, 0x08u, 0x20u, 0x4bu, 0x21u, 0x49u, 0x1bu, 0x68u, 0x09u, 0x68u, 0x9au, 0x6cu, 0x92u, 0x00u, 0x00u, 0x29u, 0x1cu, 0xd0u, 0x1eu, 0x49u, 0x09u, 0x68u, 0x00u, 0x29u, 0x18u, 0xd0u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x2fu, 0xd9u, 0x1bu, 0x4bu, 0xc3u, 0x58u, 0x5bu, 0x04u, 0x5bu, 0x0eu, 0x70u, 0x2bu, 0x1du, 0xd0u, 0x08u, 0xd8u, 0x40u, 0x2bu, @@ -976,89 +976,89 @@ const uint8_t cy_m0p_image[] = { 0x13u, 0xd0u, 0x7fu, 0x2bu, 0xf9u, 0xd1u, 0x80u, 0x22u, 0x52u, 0x00u, 0xf6u, 0xe7u, 0x80u, 0x22u, 0xd2u, 0x01u, 0xf3u, 0xe7u, 0x80u, 0x22u, 0x92u, 0x01u, 0xf0u, 0xe7u, 0x80u, 0x22u, 0x52u, 0x01u, 0xedu, 0xe7u, 0x80u, 0x22u, 0x12u, 0x01u, 0xeau, 0xe7u, 0x80u, 0x22u, 0xd2u, 0x00u, 0xe7u, 0xe7u, 0x80u, 0x22u, 0x92u, 0x00u, 0xe4u, 0xe7u, - 0x0au, 0x00u, 0xe2u, 0xe7u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x20u, 0x04u, 0x00u, 0x08u, 0x24u, 0x04u, 0x00u, 0x08u, + 0x0au, 0x00u, 0xe2u, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, 0x18u, 0x04u, 0x00u, 0x08u, 0x1cu, 0x04u, 0x00u, 0x08u, 0x88u, 0x14u, 0x00u, 0x00u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0x30u, 0xffu, 0x17u, 0x4au, 0x18u, 0x49u, 0x13u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x17u, 0xd8u, 0x16u, 0x4bu, 0x23u, 0x60u, 0x01u, 0x20u, 0x09u, 0x68u, 0x4bu, 0x6bu, 0xe3u, 0x18u, 0x18u, 0x60u, 0x13u, 0x4bu, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x13u, 0x68u, 0x09u, 0x6du, 0x9au, 0x6cu, 0x61u, 0x18u, 0x92u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x2au, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbdu, 0xfeu, 0x00u, 0x20u, 0x10u, 0xbdu, 0x23u, 0x68u, 0x0bu, 0x48u, 0x03u, 0x40u, 0x23u, 0x60u, 0x0bu, 0x68u, 0x0au, 0x48u, 0x5bu, 0x68u, 0xe3u, 0x18u, 0x18u, 0x60u, 0x80u, 0x23u, 0x20u, 0x68u, - 0x1bu, 0x06u, 0x03u, 0x43u, 0x23u, 0x60u, 0x03u, 0x23u, 0xa3u, 0x60u, 0xd8u, 0xe7u, 0x2cu, 0x06u, 0x00u, 0x08u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x03u, 0x00u, 0x00u, 0x80u, 0x24u, 0x04u, 0x00u, 0x08u, 0xffu, 0xffu, 0xfeu, 0x7fu, + 0x1bu, 0x06u, 0x03u, 0x43u, 0x23u, 0x60u, 0x03u, 0x23u, 0xa3u, 0x60u, 0xd8u, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x03u, 0x00u, 0x00u, 0x80u, 0x1cu, 0x04u, 0x00u, 0x08u, 0xffu, 0xffu, 0xfeu, 0x7fu, 0x01u, 0x00u, 0x02u, 0x00u, 0x03u, 0x23u, 0x03u, 0x70u, 0x00u, 0x20u, 0x70u, 0x47u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x00u, 0x23u, 0x03u, 0x60u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x20u, 0x03u, 0x4bu, - 0x18u, 0x60u, 0x70u, 0x47u, 0x83u, 0x60u, 0xf9u, 0xe7u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x24u, 0x04u, 0x00u, 0x08u, + 0x18u, 0x60u, 0x70u, 0x47u, 0x83u, 0x60u, 0xf9u, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, 0x1cu, 0x04u, 0x00u, 0x08u, 0x30u, 0xb5u, 0x01u, 0x29u, 0x0bu, 0xd9u, 0x01u, 0x22u, 0x0au, 0x40u, 0x54u, 0x42u, 0x62u, 0x41u, 0xcbu, 0x0fu, 0x5bu, 0x18u, 0x5bu, 0x10u, 0x9bu, 0x1au, 0x02u, 0x00u, 0x01u, 0x39u, 0x8bu, 0x42u, 0x00u, 0xdbu, 0x30u, 0xbdu, 0x14u, 0x78u, 0x45u, 0x5cu, 0x15u, 0x70u, 0x44u, 0x54u, 0x01u, 0x32u, 0x01u, 0x39u, 0xf5u, 0xe7u, 0x00u, 0x00u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf0u, 0xffu, + 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf0u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x80u, 0x21u, 0x05u, 0x4bu, 0xc9u, 0x05u, 0x1au, 0x68u, 0xd3u, 0x68u, 0xe3u, 0x18u, - 0x19u, 0x60u, 0xd3u, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, + 0x19u, 0x60u, 0xd3u, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd9u, 0xffu, 0x05u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x06u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, - 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, + 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0x00u, 0x00u, 0x41u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u, 0x1du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbeu, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x07u, 0x4bu, 0x08u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, - 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0xf8u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0x10u, 0x02u, 0x00u, 0x42u, + 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0xf8u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0x02u, 0x00u, 0x42u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u, 0x1du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa0u, 0xffu, 0x03u, 0x28u, 0xfau, 0xd8u, 0x09u, 0x4bu, 0x0au, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, - 0x15u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x06u, 0x9bu, 0x23u, 0x60u, 0xf8u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, + 0x15u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x06u, 0x9bu, 0x23u, 0x60u, 0xf8u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0x32u, 0x00u, 0x43u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x80u, 0xffu, 0x07u, 0x28u, 0xfau, 0xd8u, 0x03u, 0x4bu, 0x2du, 0x06u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, - 0x70u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x1eu, 0x00u, + 0x70u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x1eu, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x6du, 0xffu, 0x07u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x24u, 0x06u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xedu, 0x18u, 0x01u, 0x23u, 0xb3u, 0x40u, 0x1cu, 0x43u, 0x2cu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, - 0x20u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x07u, 0x00u, 0x0cu, 0x00u, 0x1du, 0x00u, 0x06u, 0xabu, 0x1eu, 0x78u, + 0x18u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x07u, 0x00u, 0x0cu, 0x00u, 0x1du, 0x00u, 0x06u, 0xabu, 0x1eu, 0x78u, 0x38u, 0x00u, 0xffu, 0xf7u, 0x55u, 0xffu, 0x07u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x02u, 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0x20u, 0x00u, 0x00u, 0x93u, 0x00u, 0x22u, 0x04u, 0x3bu, 0x50u, 0x21u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, - 0x10u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, + 0x10u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x10u, 0x00u, 0x1au, 0x1eu, 0x13u, 0xd0u, 0x03u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x39u, 0xffu, 0x0cu, 0x23u, 0x20u, 0x00u, 0x00u, 0x93u, 0x00u, 0x22u, 0x04u, 0x3bu, 0x51u, 0x21u, 0xffu, 0xf7u, 0x99u, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x10u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, - 0xfcu, 0xd1u, 0x13u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x01u, 0x20u, 0x00u, 0x2bu, + 0xfcu, 0xd1u, 0x13u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x01u, 0x20u, 0x00u, 0x2bu, 0x15u, 0xd0u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xffu, 0x08u, 0x23u, 0x00u, 0x22u, 0x00u, 0x93u, 0x52u, 0x21u, 0x04u, 0x3bu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7eu, 0xffu, 0x10u, 0x22u, 0x05u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe3u, 0x18u, 0x19u, 0x68u, 0x11u, 0x42u, 0xfcu, 0xd1u, 0xc0u, 0x23u, 0x5bu, 0x00u, 0xe0u, 0x58u, 0x16u, 0xbdu, - 0x20u, 0x04u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x11u, 0x00u, 0x1au, 0x00u, 0x04u, 0xabu, + 0x18u, 0x04u, 0x00u, 0x08u, 0x13u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x00u, 0x11u, 0x00u, 0x1au, 0x00u, 0x04u, 0xabu, 0x1bu, 0x88u, 0x00u, 0x2bu, 0x15u, 0xd0u, 0x00u, 0x90u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xffu, 0x0cu, 0x23u, 0x01u, 0x93u, 0x04u, 0x3bu, 0x00u, 0x93u, 0x20u, 0x00u, 0x04u, 0x3bu, 0x00u, 0x22u, 0x53u, 0x21u, 0xffu, 0xf7u, 0x73u, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x10u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, - 0xfcu, 0xd1u, 0x13u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, - 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, 0x20u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, - 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x20u, 0x04u, 0x00u, 0x08u, + 0xfcu, 0xd1u, 0x13u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, + 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, 0x18u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, + 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x18u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x17u, 0x00u, 0x1eu, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x08u, 0x2du, 0x04u, 0xd0u, 0x0cu, 0x4au, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x04u, 0xe0u, 0x86u, 0x22u, 0x52u, 0x01u, 0xa3u, 0x58u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0xe2u, 0x21u, 0x08u, 0x4bu, 0xc9u, 0x05u, 0x1bu, 0x68u, 0x0du, 0x43u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x15u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x26u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x10u, 0x00u, 0x00u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0eu, 0x00u, 0x15u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbbu, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0x06u, 0x4bu, 0x06u, 0x49u, 0x1bu, 0x68u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x11u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, - 0x20u, 0x04u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x1eu, 0x1eu, + 0x18u, 0x04u, 0x00u, 0x08u, 0x0cu, 0x00u, 0x00u, 0x70u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x1eu, 0x1eu, 0x22u, 0xd0u, 0x08u, 0x21u, 0xffu, 0xf7u, 0xb4u, 0xffu, 0x21u, 0x00u, 0x32u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0xd9u, 0xffu, 0x34u, 0x00u, 0x0fu, 0x2cu, 0x18u, 0xd8u, 0x10u, 0x24u, 0x33u, 0x09u, 0x64u, 0x42u, 0x5cu, 0x43u, 0xa4u, 0x19u, 0xa4u, 0xb2u, 0x00u, 0x2cu, 0x0cu, 0xd0u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x8du, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x0du, 0x4bu, 0x0du, 0x4au, 0x1bu, 0x68u, 0x24u, 0x04u, 0xdbu, 0x68u, 0x14u, 0x43u, 0xebu, 0x18u, 0x1cu, 0x60u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x8au, 0xffu, 0x70u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x7cu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x10u, 0x3cu, 0xdbu, 0x68u, 0xa4u, 0xb2u, - 0xebu, 0x18u, 0x1au, 0x60u, 0xd6u, 0xe7u, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, 0x08u, 0xc0u, 0x00u, 0x40u, + 0xebu, 0x18u, 0x1au, 0x60u, 0xd6u, 0xe7u, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x08u, 0xc0u, 0x00u, 0x40u, 0x08u, 0xc0u, 0x10u, 0x40u, 0xf8u, 0xb5u, 0x05u, 0x00u, 0x16u, 0x00u, 0x1fu, 0x1eu, 0x1eu, 0xd0u, 0x1au, 0x00u, 0xffu, 0xf7u, 0xa0u, 0xffu, 0x3cu, 0x00u, 0x0fu, 0x2cu, 0x19u, 0xd8u, 0x10u, 0x24u, 0x3bu, 0x09u, 0x64u, 0x42u, 0x5cu, 0x43u, 0xe4u, 0x19u, 0xa4u, 0xb2u, 0x00u, 0x2cu, 0x0du, 0xd0u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x54u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x0du, 0x4bu, 0x0eu, 0x4au, 0x1bu, 0x68u, 0x32u, 0x43u, 0xdbu, 0x68u, 0x24u, 0x04u, 0xebu, 0x18u, 0x14u, 0x43u, 0x1cu, 0x60u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x50u, 0xffu, 0xf8u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x42u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x32u, 0x43u, - 0xdbu, 0x68u, 0x10u, 0x3cu, 0xebu, 0x18u, 0x1au, 0x60u, 0xa4u, 0xb2u, 0xd4u, 0xe7u, 0x20u, 0x04u, 0x00u, 0x08u, + 0xdbu, 0x68u, 0x10u, 0x3cu, 0xebu, 0x18u, 0x1au, 0x60u, 0xa4u, 0xb2u, 0xd4u, 0xe7u, 0x18u, 0x04u, 0x00u, 0x08u, 0x00u, 0xc0u, 0x00u, 0x42u, 0x00u, 0xc0u, 0x10u, 0x42u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x14u, 0x00u, 0x1eu, 0x00u, 0x01u, 0x20u, 0x00u, 0x2bu, 0x2du, 0xd0u, 0x8cu, 0x23u, 0x00u, 0x22u, 0x5bu, 0x01u, 0xeau, 0x50u, 0x28u, 0x00u, 0x0au, 0x00u, 0x33u, 0x00u, 0x08u, 0x21u, 0xffu, 0xf7u, 0x33u, 0xffu, 0x22u, 0x00u, 0x33u, 0x00u, 0x09u, 0x21u, @@ -1068,7 +1068,7 @@ const uint8_t cy_m0p_image[] = { 0x14u, 0x43u, 0xebu, 0x18u, 0x1cu, 0x60u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x08u, 0xffu, 0x8cu, 0x23u, 0x5bu, 0x01u, 0xe8u, 0x58u, 0x70u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0xf7u, 0xfeu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x05u, 0x4au, 0x1bu, 0x68u, 0x10u, 0x3cu, 0xdbu, 0x68u, 0xa4u, 0xb2u, 0xebu, 0x18u, 0x1au, 0x60u, 0xd3u, 0xe7u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x98u, 0x00u, 0x00u, 0x43u, 0x98u, 0x00u, 0x10u, 0x43u, 0xf8u, 0xb5u, 0x1fu, 0x00u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x98u, 0x00u, 0x00u, 0x43u, 0x98u, 0x00u, 0x10u, 0x43u, 0xf8u, 0xb5u, 0x1fu, 0x00u, 0x06u, 0xabu, 0x1eu, 0x88u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x00u, 0x2eu, 0x29u, 0xd0u, 0x33u, 0x00u, 0x08u, 0x21u, 0xffu, 0xf7u, 0xeeu, 0xfeu, 0x33u, 0x00u, 0x3au, 0x00u, 0x09u, 0x21u, 0x28u, 0x00u, 0xffu, 0xf7u, 0xe8u, 0xfeu, 0x21u, 0x00u, 0x32u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x0du, 0xffu, 0x34u, 0x00u, 0x0fu, 0x2cu, 0x18u, 0xd8u, @@ -1077,37 +1077,37 @@ const uint8_t cy_m0p_image[] = { 0x24u, 0x04u, 0xdbu, 0x68u, 0x14u, 0x43u, 0xebu, 0x18u, 0x1cu, 0x60u, 0x28u, 0x00u, 0xffu, 0xf7u, 0xbeu, 0xfeu, 0xf8u, 0xbdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0xb0u, 0xfeu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x10u, 0x3cu, 0xdbu, 0x68u, 0xa4u, 0xb2u, 0xebu, 0x18u, 0x1au, 0x60u, 0xd6u, 0xe7u, 0xc0u, 0x46u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x98u, 0xc0u, 0x00u, 0x41u, 0x98u, 0xc0u, 0x10u, 0x41u, 0x10u, 0xb5u, 0x80u, 0x24u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x98u, 0xc0u, 0x00u, 0x41u, 0x98u, 0xc0u, 0x10u, 0x41u, 0x10u, 0xb5u, 0x80u, 0x24u, 0xa4u, 0x00u, 0x01u, 0x51u, 0x81u, 0x21u, 0x52u, 0x00u, 0x52u, 0x08u, 0x89u, 0x00u, 0x42u, 0x50u, 0x82u, 0x22u, 0xdbu, 0x00u, 0xdbu, 0x08u, 0x92u, 0x00u, 0x83u, 0x50u, 0x00u, 0x20u, 0x10u, 0xbdu, 0x70u, 0xb5u, 0x04u, 0x00u, 0x15u, 0x00u, 0xffu, 0xf7u, 0x3fu, 0xfdu, 0x00u, 0x22u, 0x5cu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xaau, 0xfdu, 0x20u, 0x21u, 0x06u, 0x4bu, 0x1au, 0x68u, 0x13u, 0x68u, 0xe3u, 0x18u, 0x18u, 0x68u, 0x08u, 0x40u, 0xfcu, 0xd1u, - 0x93u, 0x69u, 0xe4u, 0x18u, 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, + 0x93u, 0x69u, 0xe4u, 0x18u, 0x23u, 0x68u, 0x2bu, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x80u, 0x24u, 0xa4u, 0x00u, 0x01u, 0x51u, 0x81u, 0x21u, 0x52u, 0x00u, 0x52u, 0x08u, 0x89u, 0x00u, 0x42u, 0x50u, 0x82u, 0x22u, 0xdbu, 0x00u, 0xdbu, 0x08u, 0x92u, 0x00u, 0x83u, 0x50u, 0x00u, 0x20u, 0x10u, 0xbdu, 0x83u, 0x23u, 0x9bu, 0x00u, 0x10u, 0xb5u, 0xc1u, 0x50u, 0x01u, 0x21u, 0x04u, 0x33u, 0xc1u, 0x50u, 0x06u, 0x4bu, 0x19u, 0x68u, 0x0bu, 0x68u, 0xc3u, 0x18u, 0x1cu, 0x68u, 0x00u, 0x2cu, 0xfcu, 0xdbu, 0x8bu, 0x69u, 0xc0u, 0x18u, - 0x03u, 0x68u, 0x00u, 0x20u, 0x13u, 0x60u, 0x10u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, + 0x03u, 0x68u, 0x00u, 0x20u, 0x13u, 0x60u, 0x10u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x24u, 0x68u, 0x29u, 0x34u, 0x24u, 0x78u, 0x1fu, 0x2cu, 0x02u, 0xd8u, 0xffu, 0xf7u, 0x05u, 0xfeu, 0x10u, 0xbdu, - 0xffu, 0xf7u, 0x12u, 0xffu, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, + 0xffu, 0xf7u, 0x12u, 0xffu, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, - 0xfau, 0xe7u, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, + 0xfau, 0xe7u, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u, 0x29u, 0x34u, 0x22u, 0x78u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x22u, 0xffu, 0xf7u, - 0xbfu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x22u, 0xffu, 0xf7u, 0xadu, 0xfeu, 0xfau, 0xe7u, 0x2cu, 0x06u, 0x00u, 0x08u, + 0xbfu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x22u, 0xffu, 0xf7u, 0xadu, 0xfeu, 0xfau, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x03u, 0x34u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xd6u, 0xfau, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x0au, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u, 0x25u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xc5u, 0xfau, 0x10u, 0xbdu, - 0x0fu, 0x23u, 0x13u, 0x43u, 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, + 0x0fu, 0x23u, 0x13u, 0x43u, 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x09u, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u, 0x0bu, 0x43u, 0x21u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xadu, 0xfau, 0x10u, 0xbdu, - 0x0fu, 0x23u, 0x13u, 0x43u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, + 0x0fu, 0x23u, 0x13u, 0x43u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa0u, 0xfau, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x8du, 0xfau, 0x10u, 0xbdu, - 0x2cu, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, + 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, - 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x78u, 0xfau, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x78u, 0xfau, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x1du, 0x00u, 0x5eu, 0x1cu, 0x01u, 0x92u, 0x0fu, 0x00u, 0x32u, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xccu, 0xffu, 0x32u, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc7u, 0xffu, 0x32u, 0x00u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc2u, 0xffu, 0x2au, 0x00u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, @@ -1120,7 +1120,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x2au, 0xfau, 0x0du, 0x4bu, 0x03u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x24u, 0xfau, 0x33u, 0x00u, 0x3au, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xfau, 0x00u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x5du, 0xffu, 0x02u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x40u, 0xffu, - 0x01u, 0x3du, 0xd9u, 0xe7u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x02u, 0x00u, 0x30u, 0x00u, 0x01u, 0x00u, 0x30u, 0x00u, + 0x01u, 0x3du, 0xd9u, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, 0x02u, 0x00u, 0x30u, 0x00u, 0x01u, 0x00u, 0x30u, 0x00u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x9eu, 0x00u, 0x91u, 0x15u, 0x00u, 0x01u, 0x21u, 0x72u, 0x1cu, 0x77u, 0x00u, 0x01u, 0x93u, 0xffu, 0xf7u, 0x63u, 0xffu, 0x3au, 0x00u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x5eu, 0xffu, 0x3au, 0x00u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x59u, 0xffu, 0x32u, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, @@ -1142,7 +1142,7 @@ const uint8_t cy_m0p_image[] = { 0x7bu, 0xf9u, 0x20u, 0x00u, 0x10u, 0x4bu, 0x03u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x75u, 0xf9u, 0x00u, 0x9bu, 0x20u, 0x00u, 0x1au, 0x03u, 0x02u, 0x23u, 0x00u, 0x21u, 0x13u, 0x43u, 0x30u, 0x22u, 0xffu, 0xf7u, 0x6cu, 0xf9u, 0x0eu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc2u, 0xfeu, 0xf7u, 0xbdu, 0xc0u, 0x46u, 0x3au, 0x10u, 0x00u, 0x00u, - 0x18u, 0x20u, 0x00u, 0x00u, 0x23u, 0x20u, 0x00u, 0x00u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x20u, 0x20u, 0x00u, 0x00u, + 0x18u, 0x20u, 0x00u, 0x00u, 0x23u, 0x20u, 0x00u, 0x00u, 0x28u, 0x06u, 0x00u, 0x08u, 0x20u, 0x20u, 0x00u, 0x00u, 0x10u, 0x10u, 0x00u, 0x00u, 0x21u, 0x30u, 0x00u, 0x00u, 0x23u, 0x00u, 0x30u, 0x00u, 0x28u, 0x30u, 0x00u, 0x00u, 0xf7u, 0xb5u, 0x06u, 0x00u, 0x1cu, 0x00u, 0x09u, 0x9bu, 0x01u, 0x91u, 0x5fu, 0x00u, 0x15u, 0x00u, 0x02u, 0x21u, 0x3au, 0x00u, 0xffu, 0xf7u, 0xabu, 0xfeu, 0x3au, 0x00u, 0x03u, 0x21u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xa6u, 0xfeu, @@ -1160,7 +1160,7 @@ const uint8_t cy_m0p_image[] = { 0xebu, 0xf8u, 0x01u, 0x9bu, 0x30u, 0x00u, 0x1cu, 0x03u, 0x0du, 0x4bu, 0x30u, 0x22u, 0x23u, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xe2u, 0xf8u, 0xc0u, 0x23u, 0x9bu, 0x03u, 0x30u, 0x00u, 0x23u, 0x43u, 0x30u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xdau, 0xf8u, 0x30u, 0x00u, 0x03u, 0x21u, 0xffu, 0xf7u, 0x30u, 0xfeu, 0xf7u, 0xbdu, 0xc0u, 0x46u, - 0x2cu, 0x06u, 0x00u, 0x08u, 0x20u, 0x30u, 0x00u, 0x00u, 0x30u, 0x20u, 0x00u, 0x00u, 0x10u, 0x00u, 0x40u, 0x00u, + 0x28u, 0x06u, 0x00u, 0x08u, 0x20u, 0x30u, 0x00u, 0x00u, 0x30u, 0x20u, 0x00u, 0x00u, 0x10u, 0x00u, 0x40u, 0x00u, 0x01u, 0x00u, 0x40u, 0x00u, 0xf8u, 0xb5u, 0x1du, 0x00u, 0x00u, 0x23u, 0x16u, 0x00u, 0x0fu, 0x00u, 0x10u, 0x22u, 0x19u, 0x00u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xc0u, 0xf8u, 0xe0u, 0x23u, 0x00u, 0x22u, 0x1bu, 0x02u, 0x11u, 0x00u, 0x3bu, 0x43u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb8u, 0xf8u, 0x90u, 0x23u, 0x00u, 0x22u, 0x1bu, 0x02u, 0x33u, 0x43u, @@ -1183,8 +1183,8 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x5cu, 0xfdu, 0x33u, 0x68u, 0x2cu, 0x22u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x00u, 0xd9u, 0x04u, 0x3au, 0x0eu, 0x4bu, 0xa8u, 0xe7u, 0x0eu, 0x4bu, 0x25u, 0x22u, 0xeau, 0xe7u, 0xe0u, 0x21u, 0x20u, 0x00u, 0x89u, 0x01u, 0xffu, 0xf7u, 0x79u, 0xfdu, 0x00u, 0x23u, 0x11u, 0x22u, 0x19u, 0x00u, - 0x20u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xf8u, 0xf8u, 0xbdu, 0x2cu, 0x06u, 0x00u, 0x08u, 0x0au, 0xb0u, 0x00u, 0x00u, - 0x09u, 0xc0u, 0x00u, 0x00u, 0x20u, 0x04u, 0x00u, 0x08u, 0xdcu, 0xd0u, 0x00u, 0x00u, 0xd0u, 0xd0u, 0x00u, 0x00u, + 0x20u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xf8u, 0xf8u, 0xbdu, 0x28u, 0x06u, 0x00u, 0x08u, 0x0au, 0xb0u, 0x00u, 0x00u, + 0x09u, 0xc0u, 0x00u, 0x00u, 0x18u, 0x04u, 0x00u, 0x08u, 0xdcu, 0xd0u, 0x00u, 0x00u, 0xd0u, 0xd0u, 0x00u, 0x00u, 0x0au, 0xe0u, 0x00u, 0x00u, 0xdfu, 0xd0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x06u, 0x00u, 0x0fu, 0x00u, 0x02u, 0x93u, 0x0au, 0x9du, 0x0bu, 0x98u, 0x06u, 0x2au, 0x37u, 0xd8u, 0x21u, 0x4bu, 0x91u, 0x00u, 0xc9u, 0x58u, 0x20u, 0x4cu, 0x21u, 0x4bu, 0xa4u, 0x5cu, 0x9bu, 0x5cu, 0x01u, 0x22u, 0x3au, 0x70u, 0x1au, 0x19u, 0x0bu, 0x32u, @@ -1195,7 +1195,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x28u, 0x12u, 0xd1u, 0x00u, 0x9au, 0xa3u, 0xb2u, 0xaau, 0x18u, 0x02u, 0x99u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb5u, 0xfcu, 0x00u, 0x28u, 0x09u, 0xd1u, 0x38u, 0x70u, 0x07u, 0xe0u, 0x00u, 0x24u, 0x23u, 0x00u, 0x21u, 0x00u, 0xcau, 0xe7u, 0x01u, 0x30u, 0x42u, 0x78u, 0xffu, 0x2au, 0xe0u, 0xd0u, 0x00u, 0x20u, 0x05u, 0xb0u, 0xf0u, 0xbdu, - 0xecu, 0x79u, 0x00u, 0x10u, 0x0fu, 0x7au, 0x00u, 0x10u, 0x08u, 0x7au, 0x00u, 0x10u, 0xf0u, 0xb5u, 0x8bu, 0xb0u, + 0x14u, 0x7au, 0x00u, 0x10u, 0x37u, 0x7au, 0x00u, 0x10u, 0x30u, 0x7au, 0x00u, 0x10u, 0xf0u, 0xb5u, 0x8bu, 0xb0u, 0x09u, 0x93u, 0x8bu, 0x68u, 0x04u, 0x00u, 0x05u, 0x93u, 0xcbu, 0x68u, 0x08u, 0x92u, 0x06u, 0x93u, 0x0bu, 0x68u, 0x4fu, 0x68u, 0x07u, 0x93u, 0x0bu, 0x69u, 0x8du, 0x69u, 0x03u, 0x93u, 0x4bu, 0x69u, 0x04u, 0x93u, 0xb3u, 0x4bu, 0x1bu, 0x68u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1eu, 0x68u, 0x20u, 0x00u, 0xffu, 0xf7u, @@ -1242,10 +1242,10 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x4eu, 0xfcu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x51u, 0xfbu, 0x0du, 0x23u, 0x00u, 0x97u, 0x1au, 0x00u, 0x19u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x44u, 0xfcu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x47u, 0xfbu, 0x01u, 0x3du, 0x93u, 0xe7u, 0x0du, 0x23u, 0x05u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x39u, 0xfcu, 0x20u, 0x00u, - 0xffu, 0xf7u, 0x3cu, 0xfbu, 0x00u, 0x97u, 0x05u, 0x23u, 0xe9u, 0xe7u, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, + 0xffu, 0xf7u, 0x3cu, 0xfbu, 0x00u, 0x97u, 0x05u, 0x23u, 0xe9u, 0xe7u, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x06u, 0x60u, 0x00u, 0x00u, 0x05u, 0x50u, 0x00u, 0x00u, 0x07u, 0x70u, 0x00u, 0x00u, 0x08u, 0x80u, 0x00u, 0x00u, 0x09u, 0xa0u, 0x00u, 0x00u, 0x0au, 0xc0u, 0x00u, 0x00u, 0x0bu, 0x50u, 0x00u, 0x00u, 0x07u, 0xb0u, 0x00u, 0x00u, - 0x2cu, 0x06u, 0x00u, 0x08u, 0xb9u, 0xe0u, 0x00u, 0x00u, 0xbeu, 0xb0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x0bu, 0x69u, + 0x28u, 0x06u, 0x00u, 0x08u, 0xb9u, 0xe0u, 0x00u, 0x00u, 0xbeu, 0xb0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x0bu, 0x69u, 0x87u, 0xb0u, 0x03u, 0x93u, 0x4bu, 0x69u, 0x04u, 0x00u, 0x04u, 0x93u, 0x8bu, 0x69u, 0x0fu, 0x68u, 0x05u, 0x93u, 0x34u, 0x4bu, 0x4du, 0x68u, 0x1bu, 0x68u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1eu, 0x68u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x3du, 0xffu, 0x31u, 0x00u, 0x82u, 0xb2u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xfbu, @@ -1260,13 +1260,13 @@ const uint8_t cy_m0p_image[] = { 0x0eu, 0x22u, 0x00u, 0xf0u, 0xcdu, 0xfdu, 0x2bu, 0x00u, 0x32u, 0x00u, 0x20u, 0x00u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0xf9u, 0xfcu, 0x2bu, 0x00u, 0x0cu, 0x22u, 0x04u, 0x99u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xc1u, 0xfdu, 0xf0u, 0x21u, 0x20u, 0x00u, 0xc9u, 0x01u, 0xffu, 0xf7u, 0x12u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xafu, 0xfau, 0x00u, 0x20u, - 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0x0bu, 0x00u, 0x13u, 0xb5u, 0x11u, 0x00u, 0x07u, 0x22u, + 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x0bu, 0x00u, 0x13u, 0xb5u, 0x11u, 0x00u, 0x07u, 0x22u, 0x04u, 0x00u, 0x58u, 0x68u, 0x02u, 0x40u, 0xc0u, 0x20u, 0x80u, 0x00u, 0x22u, 0x50u, 0x1au, 0x69u, 0x20u, 0x00u, 0x00u, 0x92u, 0x9bu, 0x69u, 0xfeu, 0xf7u, 0xdcu, 0xffu, 0x0cu, 0x23u, 0x01u, 0x93u, 0x04u, 0x3bu, 0x00u, 0x93u, 0x20u, 0x00u, 0x04u, 0x3bu, 0x00u, 0x22u, 0x4cu, 0x21u, 0xffu, 0xf7u, 0x36u, 0xf8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x04u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xc0u, 0x46u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, 0x00u, 0xd9u, 0x80u, 0xe0u, 0x10u, 0x00u, 0x8bu, 0x60u, - 0x1au, 0x00u, 0x02u, 0xf0u, 0x4du, 0xf8u, 0x04u, 0x16u, 0x29u, 0x3au, 0x4du, 0x6cu, 0x5cu, 0x00u, 0x54u, 0x33u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, 0x00u, 0xd9u, 0x80u, 0xe0u, 0x10u, 0x00u, 0x8bu, 0x60u, + 0x1au, 0x00u, 0x02u, 0xf0u, 0x63u, 0xf8u, 0x04u, 0x16u, 0x29u, 0x3au, 0x4du, 0x6cu, 0x5cu, 0x00u, 0x54u, 0x33u, 0x8bu, 0x61u, 0x3cu, 0x4bu, 0x00u, 0x20u, 0xcbu, 0x62u, 0x40u, 0x23u, 0xcbu, 0x60u, 0x2cu, 0x3bu, 0x4bu, 0x61u, 0x4bu, 0x62u, 0x2du, 0x33u, 0x40u, 0x32u, 0xffu, 0x33u, 0x0au, 0x61u, 0x08u, 0x60u, 0x48u, 0x60u, 0xcbu, 0x61u, 0x00u, 0xbdu, 0x60u, 0x33u, 0x8bu, 0x61u, 0x01u, 0x23u, 0x0bu, 0x60u, 0x4bu, 0x60u, 0x32u, 0x4bu, 0x40u, 0x32u, @@ -1282,8 +1282,8 @@ const uint8_t cy_m0p_image[] = { 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x0au, 0x61u, 0x24u, 0x3bu, 0xdcu, 0xe7u, 0xc0u, 0x33u, 0x8bu, 0x61u, 0x05u, 0x23u, 0x0bu, 0x60u, 0x03u, 0x3bu, 0x4bu, 0x60u, 0x0cu, 0x4bu, 0x80u, 0x32u, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x0au, 0x61u, 0x20u, 0x3bu, 0xccu, 0xe7u, 0x08u, 0x48u, - 0x96u, 0xe7u, 0xc0u, 0x46u, 0x98u, 0x7au, 0x00u, 0x10u, 0xacu, 0x7au, 0x00u, 0x10u, 0xccu, 0x7au, 0x00u, 0x10u, - 0xecu, 0x7au, 0x00u, 0x10u, 0x2cu, 0x7bu, 0x00u, 0x10u, 0x6cu, 0x7bu, 0x00u, 0x10u, 0xacu, 0x7bu, 0x00u, 0x10u, + 0x96u, 0xe7u, 0xc0u, 0x46u, 0xc0u, 0x7au, 0x00u, 0x10u, 0xd4u, 0x7au, 0x00u, 0x10u, 0xf4u, 0x7au, 0x00u, 0x10u, + 0x14u, 0x7bu, 0x00u, 0x10u, 0x54u, 0x7bu, 0x00u, 0x10u, 0x94u, 0x7bu, 0x00u, 0x10u, 0xd4u, 0x7bu, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, 0x10u, 0xbdu, 0x00u, 0x24u, 0x4bu, 0x69u, 0x8cu, 0x62u, 0x0cu, 0x62u, 0xa3u, 0x42u, 0xf7u, 0xd0u, 0xcau, 0x6au, 0x9bu, 0xb2u, 0x09u, 0x69u, 0xfeu, 0xf7u, 0xa0u, 0xffu, 0x20u, 0x00u, 0xf1u, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf7u, 0xb5u, 0x07u, 0x00u, @@ -1313,33 +1313,33 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x20u, 0x70u, 0xbdu, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x8fu, 0xb0u, 0x01u, 0x93u, 0x14u, 0xabu, 0x1fu, 0x78u, 0x19u, 0x4bu, 0x04u, 0x00u, 0x1bu, 0x68u, 0x00u, 0x91u, 0x16u, 0x00u, 0x1du, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1du, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, - 0x02u, 0xf0u, 0xbfu, 0xf8u, 0x2bu, 0x00u, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, + 0x02u, 0xf0u, 0xd5u, 0xf8u, 0x2bu, 0x00u, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, 0x00u, 0x28u, 0x18u, 0xd1u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x0cu, 0xffu, 0x00u, 0x28u, 0x12u, 0xd1u, 0x33u, 0x00u, 0x00u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x18u, 0xffu, 0x00u, 0x28u, 0x0au, 0xd1u, 0x01u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x00u, 0x28u, 0x03u, 0xd1u, 0x02u, 0xa9u, - 0x20u, 0x00u, 0xffu, 0xf7u, 0xadu, 0xffu, 0x0fu, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, + 0x20u, 0x00u, 0xffu, 0xf7u, 0xadu, 0xffu, 0x0fu, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x9bu, 0x68u, 0xc0u, 0x18u, 0x0fu, 0x23u, 0x00u, 0x68u, 0x18u, 0x40u, 0x70u, 0x47u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, - 0xfcu, 0xd1u, 0x70u, 0x47u, 0x20u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x03u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, + 0xfcu, 0xd1u, 0x70u, 0x47u, 0x18u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x0fu, 0x00u, 0x16u, 0x00u, 0x1du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x04u, 0x28u, 0xfau, 0xd8u, 0xe0u, 0x21u, 0x07u, 0x4bu, 0xc9u, 0x05u, 0x1bu, 0x68u, 0x0fu, 0x43u, 0xdau, 0x68u, 0xa2u, 0x18u, 0x17u, 0x60u, 0xdau, 0x68u, 0xa2u, 0x18u, - 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, + 0x16u, 0x60u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0xf8u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcau, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x03u, 0x4bu, 0x2du, 0x06u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x25u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb9u, 0xffu, 0x06u, 0x28u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb9u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0xc8u, 0x23u, 0xdbu, 0x05u, 0x23u, 0x60u, - 0x10u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, + 0x10u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa7u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0xcau, 0x23u, - 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, + 0xdbu, 0x05u, 0x23u, 0x60u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x93u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x24u, 0x02u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xedu, 0x18u, 0xccu, 0x23u, 0xdbu, 0x05u, 0x1eu, 0x43u, 0x34u, 0x43u, - 0x2cu, 0x60u, 0x70u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, + 0x2cu, 0x60u, 0x70u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x05u, 0x00u, 0x0cu, 0x00u, 0x16u, 0x00u, 0x28u, 0x00u, 0xffu, 0xf7u, 0x7du, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x05u, 0x4bu, 0x24u, 0x02u, 0x1bu, 0x68u, 0xdbu, 0x68u, 0xedu, 0x18u, 0xd0u, 0x23u, 0xdbu, 0x05u, 0x1eu, 0x43u, 0x34u, 0x43u, 0x2cu, 0x60u, 0x70u, 0xbdu, - 0x20u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x68u, 0xffu, + 0x18u, 0x04u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x68u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0xceu, 0x21u, 0x04u, 0x4bu, 0xc9u, 0x05u, 0x1bu, 0x68u, 0x29u, 0x43u, 0xdbu, 0x68u, - 0xe4u, 0x18u, 0x21u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, - 0x68u, 0xd8u, 0x10u, 0x00u, 0x8bu, 0x60u, 0x01u, 0xf0u, 0x03u, 0xfeu, 0x04u, 0x1fu, 0x12u, 0x3bu, 0x2fu, 0x49u, + 0xe4u, 0x18u, 0x21u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, + 0x68u, 0xd8u, 0x10u, 0x00u, 0x8bu, 0x60u, 0x01u, 0xf0u, 0x19u, 0xfeu, 0x04u, 0x1fu, 0x12u, 0x3bu, 0x2fu, 0x49u, 0x57u, 0x00u, 0x40u, 0x33u, 0x0bu, 0x61u, 0x69u, 0x23u, 0x4bu, 0x60u, 0x2fu, 0x4bu, 0x00u, 0x20u, 0xcbu, 0x62u, 0x40u, 0x23u, 0xcbu, 0x60u, 0x2cu, 0x3bu, 0x08u, 0x60u, 0x4bu, 0x61u, 0x4bu, 0x62u, 0x00u, 0xbdu, 0x40u, 0x33u, 0x0bu, 0x61u, 0x02u, 0x23u, 0x0bu, 0x60u, 0x68u, 0x33u, 0x4bu, 0x60u, 0x28u, 0x4bu, 0xcbu, 0x62u, 0x40u, 0x23u, @@ -1352,9 +1352,9 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x23u, 0x0bu, 0x60u, 0x66u, 0x33u, 0x4bu, 0x60u, 0x10u, 0x4bu, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x20u, 0x3bu, 0xd4u, 0xe7u, 0x80u, 0x33u, 0x0bu, 0x61u, 0x06u, 0x23u, 0x0bu, 0x60u, 0x65u, 0x33u, 0x4bu, 0x60u, 0x0au, 0x4bu, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, - 0x24u, 0x3bu, 0xc6u, 0xe7u, 0x07u, 0x48u, 0xa9u, 0xe7u, 0xecu, 0x7bu, 0x00u, 0x10u, 0x20u, 0x7cu, 0x00u, 0x10u, - 0x00u, 0x7cu, 0x00u, 0x10u, 0x80u, 0x7cu, 0x00u, 0x10u, 0x40u, 0x7cu, 0x00u, 0x10u, 0x00u, 0x7du, 0x00u, 0x10u, - 0xc0u, 0x7cu, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, + 0x24u, 0x3bu, 0xc6u, 0xe7u, 0x07u, 0x48u, 0xa9u, 0xe7u, 0x14u, 0x7cu, 0x00u, 0x10u, 0x48u, 0x7cu, 0x00u, 0x10u, + 0x28u, 0x7cu, 0x00u, 0x10u, 0xa8u, 0x7cu, 0x00u, 0x10u, 0x68u, 0x7cu, 0x00u, 0x10u, 0x28u, 0x7du, 0x00u, 0x10u, + 0xe8u, 0x7cu, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, 0x10u, 0xbdu, 0x00u, 0x24u, 0x4bu, 0x69u, 0x8cu, 0x62u, 0x0cu, 0x62u, 0xa3u, 0x42u, 0xf7u, 0xd0u, 0xcau, 0x6au, 0x9bu, 0xb2u, 0x09u, 0x69u, 0xfeu, 0xf7u, 0x40u, 0xfeu, 0x20u, 0x00u, 0xf1u, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x04u, 0x00u, 0x0du, 0x1eu, 0x03u, 0x92u, 0x01u, 0x93u, 0x00u, 0xd1u, 0x95u, 0xe0u, @@ -1377,7 +1377,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x92u, 0xfeu, 0x00u, 0x27u, 0x38u, 0x00u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x02u, 0x9bu, 0x31u, 0x00u, 0x9fu, 0x1bu, 0x3au, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x99u, 0xfeu, 0x69u, 0x68u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x5fu, 0xfeu, 0x01u, 0x9bu, 0x00u, 0x26u, 0xdbu, 0x1bu, 0x01u, 0x93u, 0xb8u, 0xe7u, 0x02u, 0x4fu, 0xeau, 0xe7u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x08u, 0x00u, 0x00u, 0x71u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x04u, 0x00u, 0x0du, 0x1eu, 0x02u, 0x92u, 0x00u, 0xd1u, 0x7bu, 0xe0u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x78u, 0xe0u, 0x8bu, 0x6au, 0x0au, 0x6au, 0x00u, 0x93u, 0x53u, 0x0fu, 0x03u, 0x93u, 0x70u, 0x23u, 0xceu, 0x68u, 0xd7u, 0x00u, 0x01u, 0x93u, 0x80u, 0x2eu, 0x01u, 0xd0u, 0x38u, 0x3bu, 0x01u, 0x93u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4au, 0xfeu, @@ -1401,7 +1401,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0xc0u, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x85u, 0xfdu, 0x00u, 0x20u, 0x70u, 0xbdu, 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0xbfu, 0xb0u, 0x01u, 0x93u, 0x44u, 0xabu, 0x1fu, 0x78u, 0x0du, 0x00u, 0x16u, 0x00u, 0x00u, 0x21u, 0xc0u, 0x22u, 0x0eu, 0xa8u, 0x01u, 0xf0u, - 0x00u, 0xfeu, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, 0x01u, 0xf0u, 0xfbu, 0xfdu, 0x0eu, 0xabu, 0x3au, 0x00u, + 0x16u, 0xfeu, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, 0x01u, 0xf0u, 0x11u, 0xfeu, 0x0eu, 0xabu, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x02u, 0xfeu, 0x00u, 0x28u, 0x18u, 0xd1u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, 0x00u, 0x28u, 0x12u, 0xd1u, 0x33u, 0x00u, 0x2au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x86u, 0xfeu, 0x00u, 0x28u, 0x0au, 0xd1u, 0x01u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, @@ -1413,7 +1413,7 @@ const uint8_t cy_m0p_image[] = { 0x60u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x5eu, 0xfbu, 0x40u, 0x21u, 0x0au, 0x4bu, 0x1au, 0x68u, 0x13u, 0x68u, 0xe3u, 0x18u, 0x18u, 0x68u, 0x08u, 0x40u, 0xfcu, 0xd1u, 0xd3u, 0x69u, 0xe3u, 0x18u, 0x1au, 0x68u, 0x04u, 0x9bu, 0x1au, 0x60u, 0xa1u, 0x23u, 0x9bu, 0x00u, 0xe0u, 0x50u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x03u, 0x31u, - 0x01u, 0x00u, 0x01u, 0x00u, 0x20u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0xa0u, 0x20u, 0x1cu, 0x4du, + 0x01u, 0x00u, 0x01u, 0x00u, 0x18u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0xa0u, 0x20u, 0x1cu, 0x4du, 0x80u, 0x00u, 0x25u, 0x50u, 0x3fu, 0x25u, 0x04u, 0x30u, 0xb0u, 0x26u, 0x25u, 0x50u, 0x00u, 0x25u, 0xb6u, 0x00u, 0xa5u, 0x51u, 0x08u, 0x36u, 0xa5u, 0x51u, 0x17u, 0x4fu, 0x08u, 0x36u, 0x01u, 0x35u, 0xa5u, 0x51u, 0x10u, 0x36u, 0xa7u, 0x51u, 0x40u, 0x3eu, 0xa1u, 0x51u, 0xa9u, 0x21u, 0x89u, 0x00u, 0x62u, 0x50u, 0xa2u, 0x22u, 0x92u, 0x00u, @@ -1421,20 +1421,20 @@ const uint8_t cy_m0p_image[] = { 0x0du, 0x4bu, 0x1du, 0x68u, 0x2bu, 0x68u, 0xe1u, 0x18u, 0x03u, 0x00u, 0x08u, 0x68u, 0xe6u, 0x58u, 0x16u, 0x42u, 0x07u, 0xd0u, 0xc0u, 0x0fu, 0xf9u, 0xd1u, 0xebu, 0x69u, 0xe3u, 0x18u, 0x1au, 0x68u, 0x05u, 0x9bu, 0x1au, 0x60u, 0x00u, 0xe0u, 0x06u, 0x48u, 0xa1u, 0x23u, 0x00u, 0x22u, 0x9bu, 0x00u, 0xe2u, 0x50u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0x00u, 0x00u, 0x03u, 0x31u, 0x01u, 0x00u, 0x01u, 0x00u, 0x20u, 0x04u, 0x00u, 0x08u, 0x01u, 0x00u, 0x32u, 0x00u, + 0x00u, 0x00u, 0x03u, 0x31u, 0x01u, 0x00u, 0x01u, 0x00u, 0x18u, 0x04u, 0x00u, 0x08u, 0x01u, 0x00u, 0x32u, 0x00u, 0x07u, 0x4bu, 0x89u, 0x00u, 0x1au, 0x68u, 0x93u, 0x6bu, 0x12u, 0x69u, 0xc3u, 0x18u, 0x89u, 0x18u, 0x08u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x68u, 0x80u, 0x00u, 0x80u, 0x0cu, 0x80u, 0x00u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x24u, 0x68u, 0x29u, 0x34u, 0x24u, 0x78u, 0x1fu, 0x2cu, + 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x24u, 0x68u, 0x29u, 0x34u, 0x24u, 0x78u, 0x1fu, 0x2cu, 0x02u, 0xd8u, 0xfeu, 0xf7u, 0x47u, 0xfbu, 0x10u, 0xbdu, 0xfeu, 0xf7u, 0x16u, 0xfcu, 0xfbu, 0xe7u, 0xc0u, 0x46u, - 0x2cu, 0x06u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x1fu, 0x24u, 0x95u, 0x00u, 0x13u, 0x05u, 0x09u, 0x4au, 0xadu, 0x0cu, + 0x28u, 0x06u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x1fu, 0x24u, 0x95u, 0x00u, 0x13u, 0x05u, 0x09u, 0x4au, 0xadu, 0x0cu, 0x12u, 0x68u, 0x89u, 0x06u, 0x29u, 0x32u, 0x12u, 0x78u, 0x1bu, 0x0du, 0x94u, 0x42u, 0xa4u, 0x41u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa5u, 0x40u, 0x0bu, 0x43u, 0x2bu, 0x43u, 0x80u, 0x22u, 0x00u, 0x21u, 0xfeu, 0xf7u, 0x6cu, 0xf8u, - 0x70u, 0xbdu, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, + 0x70u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x28u, 0x06u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u, 0x29u, 0x34u, 0x22u, 0x78u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x22u, 0xfeu, 0xf7u, 0x21u, 0xfbu, 0x10u, 0xbdu, - 0x00u, 0x22u, 0xfeu, 0xf7u, 0x0fu, 0xfcu, 0xfau, 0xe7u, 0x2cu, 0x06u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u, + 0x00u, 0x22u, 0xfeu, 0xf7u, 0x0fu, 0xfcu, 0xfau, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x93u, 0x0eu, 0x00u, 0x01u, 0x92u, 0xffu, 0xf7u, 0xcfu, 0xffu, 0x1bu, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x2du, 0xd8u, 0x19u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x69u, 0xe3u, 0x18u, 0x1fu, 0x68u, 0x5du, 0x68u, 0x31u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x83u, 0xffu, 0x06u, 0x00u, 0x00u, 0x9au, 0x01u, 0x00u, @@ -1442,48 +1442,48 @@ const uint8_t cy_m0p_image[] = { 0x01u, 0x9au, 0x07u, 0x33u, 0xdbu, 0x08u, 0x9bu, 0xb2u, 0x31u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x82u, 0xffu, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x09u, 0xd8u, 0x3au, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x87u, 0xffu, 0x2au, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x82u, 0xffu, - 0xf7u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xd4u, 0xe7u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x20u, 0x04u, 0x00u, 0x08u, + 0xf7u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xd4u, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, 0x18u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x03u, 0x93u, 0x04u, 0x00u, 0x01u, 0x91u, 0x02u, 0x92u, 0xffu, 0xf7u, 0x8cu, 0xffu, 0x16u, 0x4eu, 0x33u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x23u, 0xd8u, 0x14u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x69u, 0xe3u, 0x18u, 0x1fu, 0x68u, 0x5du, 0x68u, 0x02u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x40u, 0xffu, 0x03u, 0x9bu, 0x02u, 0x00u, 0x07u, 0x33u, 0xdbu, 0x08u, 0x9bu, 0xb2u, 0x01u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x49u, 0xffu, 0x33u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x09u, 0xd8u, 0x3au, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x2au, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4au, 0xffu, - 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xdeu, 0xe7u, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x0bu, 0x00u, 0x3fu, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u, + 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xdeu, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x0bu, 0x00u, 0x3fu, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u, 0xbbu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x50u, 0xffu, 0x03u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x6bu, 0xe4u, 0x18u, - 0x20u, 0x68u, 0x40u, 0x07u, 0xc0u, 0x0fu, 0x10u, 0xbdu, 0x20u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, + 0x20u, 0x68u, 0x40u, 0x07u, 0xc0u, 0x0fu, 0x10u, 0xbdu, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x13u, 0x01u, 0x0bu, 0x43u, 0x3du, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u, 0xa6u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x3bu, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x20u, 0x68u, 0x40u, 0x07u, 0xc0u, 0x0fu, - 0x10u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x13u, 0x01u, 0x0bu, 0x43u, + 0x10u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x13u, 0x01u, 0x0bu, 0x43u, 0x3du, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u, 0x90u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x25u, 0xffu, 0x04u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x01u, 0x23u, 0x20u, 0x68u, 0x18u, 0x40u, 0x10u, 0xbdu, 0xc0u, 0x46u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x08u, 0x4bu, 0x10u, 0xb5u, 0x1au, 0x68u, 0x8bu, 0x00u, 0x12u, 0x69u, 0x9bu, 0x18u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x08u, 0x4bu, 0x10u, 0xb5u, 0x1au, 0x68u, 0x8bu, 0x00u, 0x12u, 0x69u, 0x9bu, 0x18u, 0xc3u, 0x18u, 0x1cu, 0x68u, 0xffu, 0xf7u, 0xd4u, 0xfeu, 0xe1u, 0x04u, 0xc9u, 0x0cu, 0x08u, 0x31u, 0xc9u, 0x08u, - 0xfeu, 0xf7u, 0x3eu, 0xf9u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x20u, 0x04u, 0x00u, 0x08u, 0x00u, 0x28u, 0x07u, 0xdbu, + 0xfeu, 0xf7u, 0x3eu, 0xf9u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x18u, 0x04u, 0x00u, 0x08u, 0x00u, 0x28u, 0x07u, 0xdbu, 0x1fu, 0x23u, 0xc0u, 0x22u, 0x18u, 0x40u, 0x1eu, 0x3bu, 0x83u, 0x40u, 0x02u, 0x49u, 0x52u, 0x00u, 0x8bu, 0x50u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0x30u, 0xb5u, 0xf8u, 0x25u, 0x0fu, 0x4bu, 0x10u, 0x4au, 0x18u, 0x68u, 0x14u, 0x68u, 0x43u, 0x6au, 0x22u, 0x6cu, 0x6du, 0x03u, 0x9au, 0x18u, 0x11u, 0x68u, 0x29u, 0x40u, 0x10u, 0xd0u, 0x11u, 0x60u, 0x22u, 0x6cu, 0x9bu, 0x18u, 0x1bu, 0x68u, 0x0au, 0x4bu, 0x1au, 0x68u, 0x53u, 0x1cu, 0xd9u, 0x7fu, 0x00u, 0x29u, 0x07u, 0xd1u, 0x41u, 0x6au, 0x08u, 0x6au, 0x49u, 0x6au, 0x50u, 0x62u, 0x91u, 0x62u, - 0x01u, 0x22u, 0xdau, 0x77u, 0x30u, 0xbdu, 0x00u, 0x22u, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, - 0x20u, 0x04u, 0x00u, 0x08u, 0x2cu, 0x04u, 0x00u, 0x08u, 0x00u, 0x22u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x03u, 0x68u, + 0x01u, 0x22u, 0xdau, 0x77u, 0x30u, 0xbdu, 0x00u, 0x22u, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, + 0x18u, 0x04u, 0x00u, 0x08u, 0x24u, 0x04u, 0x00u, 0x08u, 0x00u, 0x22u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x03u, 0x68u, 0x0du, 0x00u, 0x0bu, 0x60u, 0x43u, 0x68u, 0x4bu, 0x60u, 0x83u, 0x69u, 0x8bu, 0x60u, 0xc3u, 0x69u, 0xcbu, 0x60u, 0x4bu, 0x1cu, 0xdau, 0x77u, 0x03u, 0x8cu, 0x0bu, 0x82u, 0x03u, 0x8du, 0x0bu, 0x83u, 0xfdu, 0xf7u, 0xceu, 0xffu, - 0xa1u, 0x69u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x20u, 0x49u, 0x20u, 0x00u, 0x20u, 0x30u, 0x00u, 0xf0u, 0xaau, 0xfeu, + 0xa1u, 0x69u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x20u, 0x49u, 0x20u, 0x00u, 0x20u, 0x30u, 0x00u, 0xf0u, 0xc0u, 0xfeu, 0x20u, 0x22u, 0xa3u, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x1au, 0x4au, 0x13u, 0x60u, 0x80u, 0x22u, 0x21u, 0x68u, 0x52u, 0x02u, 0x8au, 0x40u, 0x18u, 0x4eu, 0x61u, 0x68u, 0x33u, 0x68u, 0x49u, 0x01u, 0x1bu, 0x6au, 0x5bu, 0x18u, 0x16u, 0x49u, 0x5bu, 0x18u, 0xe1u, 0x69u, - 0x1au, 0x60u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x14u, 0x49u, 0x20u, 0x00u, 0x28u, 0x30u, 0x00u, 0xf0u, 0x8au, 0xfeu, + 0x1au, 0x60u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x14u, 0x49u, 0x20u, 0x00u, 0x28u, 0x30u, 0x00u, 0xf0u, 0xa0u, 0xfeu, 0x28u, 0x23u, 0xe0u, 0x5eu, 0xffu, 0xf7u, 0x8au, 0xffu, 0x28u, 0x22u, 0xa3u, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x08u, 0x4au, 0x13u, 0x60u, 0x0bu, 0x4au, 0x33u, 0x68u, 0x12u, 0x68u, 0x5bu, 0x6au, 0x92u, 0x6cu, 0x00u, 0x20u, 0x9bu, 0x18u, 0xf8u, 0x22u, 0x52u, 0x03u, 0x1au, 0x60u, 0x07u, 0x4bu, 0x1du, 0x60u, 0x70u, 0xbdu, 0x25u, 0x5fu, 0x00u, 0x10u, 0x00u, 0xe1u, 0x00u, 0xe0u, - 0x2cu, 0x06u, 0x00u, 0x08u, 0x08u, 0x10u, 0x00u, 0x00u, 0xb9u, 0x59u, 0x00u, 0x10u, 0x20u, 0x04u, 0x00u, 0x08u, - 0x2cu, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x06u, 0x4bu, + 0x28u, 0x06u, 0x00u, 0x08u, 0x08u, 0x10u, 0x00u, 0x00u, 0xb9u, 0x59u, 0x00u, 0x10u, 0x18u, 0x04u, 0x00u, 0x08u, + 0x24u, 0x04u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x06u, 0x4bu, 0x1fu, 0x2au, 0x04u, 0xd8u, 0x05u, 0x4au, 0x1au, 0x60u, 0xffu, 0xf7u, 0x8eu, 0xffu, 0x10u, 0xbdu, 0x04u, 0x4au, - 0xf9u, 0xe7u, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x28u, 0x04u, 0x00u, 0x08u, 0x40u, 0x7du, 0x00u, 0x10u, - 0x98u, 0x7du, 0x00u, 0x10u, 0xf0u, 0xb5u, 0xb4u, 0x4bu, 0x85u, 0xb0u, 0x1cu, 0x68u, 0x00u, 0x2cu, 0x1eu, 0xd0u, + 0xf9u, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x20u, 0x04u, 0x00u, 0x08u, 0x68u, 0x7du, 0x00u, 0x10u, + 0xc0u, 0x7du, 0x00u, 0x10u, 0xf0u, 0xb5u, 0xb4u, 0x4bu, 0x85u, 0xb0u, 0x1cu, 0x68u, 0x00u, 0x2cu, 0x1eu, 0xd0u, 0xb2u, 0x4bu, 0xb3u, 0x4du, 0x63u, 0x60u, 0x2bu, 0x68u, 0x5fu, 0x6au, 0x23u, 0x78u, 0x01u, 0x2bu, 0x18u, 0xd1u, 0x38u, 0x00u, 0xfeu, 0xf7u, 0x1fu, 0xf8u, 0x60u, 0x60u, 0x00u, 0x23u, 0xabu, 0x4au, 0xe1u, 0x69u, 0x13u, 0x60u, 0x2bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x10u, 0x88u, 0x22u, 0x69u, 0x1bu, 0x6au, 0x50u, 0x43u, 0xc0u, 0x18u, @@ -1528,9 +1528,9 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x93u, 0xd3u, 0x69u, 0x40u, 0x6au, 0x52u, 0x69u, 0xb0u, 0x47u, 0x99u, 0xe7u, 0x96u, 0x69u, 0xedu, 0xe7u, 0xd6u, 0x69u, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0xedu, 0xe6u, 0xa1u, 0x6au, 0x03u, 0x91u, 0x8bu, 0x6au, 0x02u, 0x93u, 0x4bu, 0x6au, 0x01u, 0x93u, 0x0bu, 0x6au, 0x00u, 0x93u, 0xcbu, 0x69u, 0x8au, 0x69u, 0x40u, 0x6au, - 0x49u, 0x69u, 0xb0u, 0x47u, 0x84u, 0xe7u, 0xc0u, 0x46u, 0x30u, 0x04u, 0x00u, 0x08u, 0x09u, 0x00u, 0x32u, 0x00u, - 0x2cu, 0x06u, 0x00u, 0x08u, 0x20u, 0x04u, 0x00u, 0x08u, 0x0au, 0x00u, 0x32u, 0x00u, 0x28u, 0x04u, 0x00u, 0x08u, - 0x2cu, 0x04u, 0x00u, 0x08u, 0x01u, 0x00u, 0x32u, 0x00u, 0x56u, 0x6au, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, + 0x49u, 0x69u, 0xb0u, 0x47u, 0x84u, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x09u, 0x00u, 0x32u, 0x00u, + 0x28u, 0x06u, 0x00u, 0x08u, 0x18u, 0x04u, 0x00u, 0x08u, 0x0au, 0x00u, 0x32u, 0x00u, 0x20u, 0x04u, 0x00u, 0x08u, + 0x24u, 0x04u, 0x00u, 0x08u, 0x01u, 0x00u, 0x32u, 0x00u, 0x56u, 0x6au, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0xc9u, 0xe6u, 0xa1u, 0x6au, 0x0bu, 0x7bu, 0x00u, 0x93u, 0x8bu, 0x68u, 0x4au, 0x68u, 0x40u, 0x6au, 0x09u, 0x68u, 0xb0u, 0x47u, 0x65u, 0xe7u, 0x96u, 0x6au, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0xbbu, 0xe6u, 0xa1u, 0x6au, 0x0bu, 0x7bu, 0x02u, 0x93u, 0x4bu, 0x69u, 0x01u, 0x93u, 0x0bu, 0x69u, 0x00u, 0x93u, 0x4bu, 0x68u, 0x0au, 0x68u, @@ -1554,10 +1554,10 @@ const uint8_t cy_m0p_image[] = { 0x36u, 0x0cu, 0x91u, 0x40u, 0xb1u, 0x42u, 0x13u, 0xd1u, 0x80u, 0x26u, 0x09u, 0x04u, 0x76u, 0x01u, 0x99u, 0x51u, 0xacu, 0x35u, 0x9bu, 0x59u, 0x2bu, 0x88u, 0x0au, 0x49u, 0x5au, 0x43u, 0x10u, 0x18u, 0x00u, 0xf0u, 0xe2u, 0xf8u, 0x00u, 0x28u, 0x05u, 0xd1u, 0x23u, 0x68u, 0x9bu, 0x68u, 0x00u, 0x2bu, 0x01u, 0xd1u, 0xffu, 0xf7u, 0xcau, 0xfdu, - 0x70u, 0xbdu, 0xc0u, 0x46u, 0x2cu, 0x04u, 0x00u, 0x08u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x0cu, 0x10u, 0x00u, 0x00u, - 0x30u, 0x04u, 0x00u, 0x08u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, + 0x70u, 0xbdu, 0xc0u, 0x46u, 0x24u, 0x04u, 0x00u, 0x08u, 0x28u, 0x06u, 0x00u, 0x08u, 0x0cu, 0x10u, 0x00u, 0x00u, + 0x28u, 0x04u, 0x00u, 0x08u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, 0x50u, 0x43u, 0xc0u, 0x18u, - 0x70u, 0x47u, 0xc0u, 0x46u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, + 0x70u, 0x47u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, 0x40u, 0x28u, 0x2fu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x30u, 0xd0u, 0x10u, 0x28u, 0x28u, 0xd0u, 0x19u, 0x48u, 0x1eu, 0xe0u, 0x80u, 0x28u, 0x28u, 0xd0u, 0x80u, 0x23u, 0x5bu, 0x00u, 0x98u, 0x42u, 0xf7u, 0xd1u, 0x14u, 0x48u, 0x16u, 0xe0u, 0x15u, 0x4bu, 0x98u, 0x42u, 0x14u, 0xd0u, 0x08u, 0xd8u, 0xa0u, 0x23u, 0x1bu, 0x06u, 0x98u, 0x42u, @@ -1571,41 +1571,41 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x00u, 0x52u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x9au, 0xffu, 0x0au, 0x4bu, 0x1cu, 0x68u, 0x23u, 0x00u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x0au, 0xdbu, 0x07u, 0x4bu, 0x18u, 0x68u, 0xffu, 0xf7u, 0x99u, 0xffu, 0x01u, 0x22u, 0x63u, 0x68u, 0x9au, 0x60u, 0x9au, 0x68u, 0x00u, 0x2au, - 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x34u, 0x04u, 0x00u, 0x08u, + 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, 0x2cu, 0x04u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x0du, 0x4bu, 0x10u, 0xb5u, 0x18u, 0x60u, 0x00u, 0x28u, 0x04u, 0xd0u, 0xfeu, 0x23u, 0x5bu, 0x42u, 0x03u, 0x80u, 0x00u, 0x23u, 0x43u, 0x80u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0x4cu, 0x32u, 0x12u, 0x78u, 0x00u, 0x2au, 0x08u, 0xd0u, 0x4du, 0x33u, 0x1bu, 0x78u, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x02u, 0x22u, - 0x04u, 0x49u, 0x00u, 0x20u, 0x00u, 0xf0u, 0xe0u, 0xf8u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x44u, 0x04u, 0x00u, 0x08u, - 0x2cu, 0x06u, 0x00u, 0x08u, 0x4du, 0x01u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x02u, 0x48u, 0xffu, 0xf7u, 0xdau, 0xffu, - 0x10u, 0xbdu, 0xc0u, 0x46u, 0xc0u, 0x03u, 0x00u, 0x08u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, + 0x04u, 0x49u, 0x00u, 0x20u, 0x00u, 0xf0u, 0xe0u, 0xf8u, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x3cu, 0x04u, 0x00u, 0x08u, + 0x28u, 0x06u, 0x00u, 0x08u, 0x49u, 0x01u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x02u, 0x48u, 0xffu, 0xf7u, 0xdau, 0xffu, + 0x10u, 0xbdu, 0xc0u, 0x46u, 0xb8u, 0x03u, 0x00u, 0x08u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0x89u, 0xb2u, 0x41u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, - 0x01u, 0x48u, 0xfcu, 0xe7u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, + 0x01u, 0x48u, 0xfcu, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u, 0xc2u, 0x60u, 0x81u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x00u, 0x8au, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, - 0x2cu, 0x06u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, - 0x18u, 0x60u, 0x70u, 0x47u, 0x48u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x15u, 0x4cu, + 0x28u, 0x06u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, + 0x18u, 0x60u, 0x70u, 0x47u, 0x40u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x15u, 0x4cu, 0x1fu, 0x00u, 0x24u, 0x68u, 0x1du, 0x0au, 0x20u, 0x18u, 0xffu, 0x24u, 0x25u, 0x40u, 0x27u, 0x40u, 0x12u, 0x4cu, 0x1bu, 0x0cu, 0x26u, 0x68u, 0x07u, 0x60u, 0x34u, 0x6au, 0x45u, 0x60u, 0x83u, 0x60u, 0xacu, 0x36u, 0x36u, 0x88u, 0x77u, 0x43u, 0x3fu, 0x19u, 0x07u, 0x61u, 0x2fu, 0x00u, 0x80u, 0x37u, 0x6du, 0x01u, 0x7fu, 0x01u, 0xe7u, 0x19u, 0x64u, 0x19u, 0x0au, 0x4du, 0x47u, 0x61u, 0x1fu, 0x04u, 0x3bu, 0x43u, 0x64u, 0x19u, 0x23u, 0x60u, 0x00u, 0x23u, 0x83u, 0x61u, 0x05u, 0x9bu, 0xc2u, 0x61u, 0x01u, 0x62u, 0x00u, 0x2bu, 0x01u, 0xd0u, 0x1bu, 0x88u, 0x83u, 0x81u, - 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x48u, 0x04u, 0x00u, 0x08u, 0x2cu, 0x06u, 0x00u, 0x08u, 0x08u, 0x10u, 0x00u, 0x00u, + 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x40u, 0x04u, 0x00u, 0x08u, 0x28u, 0x06u, 0x00u, 0x08u, 0x08u, 0x10u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x83u, 0x68u, 0x85u, 0xb0u, 0x02u, 0xadu, 0x2bu, 0x80u, 0x15u, 0x4bu, 0x02u, 0x68u, 0x1bu, 0x68u, 0x06u, 0x6au, 0x9bu, 0x8eu, 0x47u, 0x6au, 0x9bu, 0x18u, 0xabu, 0x70u, 0x43u, 0x68u, 0x00u, 0x95u, 0x82u, 0x6au, 0xc1u, 0x6au, 0x04u, 0x00u, 0x03u, 0x93u, 0x03u, 0x69u, 0xc0u, 0x68u, 0xffu, 0xf7u, 0xb5u, 0xffu, 0x00u, 0x21u, 0x3bu, 0x00u, 0x0au, 0x00u, 0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xaeu, 0xffu, 0x21u, 0x6bu, 0x28u, 0x00u, - 0x00u, 0xf0u, 0xc8u, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, + 0x00u, 0xf0u, 0xdeu, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0x2cu, 0x06u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, + 0x28u, 0x06u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, 0x26u, 0x68u, 0x69u, 0x43u, 0x34u, 0x18u, 0x25u, 0x69u, 0x01u, 0x93u, 0x71u, 0x18u, 0x00u, 0x2du, 0x19u, 0xd0u, 0x88u, 0x69u, 0x00u, 0x28u, 0x18u, 0xd1u, 0x2eu, 0x68u, 0x00u, 0x2eu, 0x15u, 0xdau, 0x67u, 0x68u, 0x01u, 0x24u, 0x26u, 0x00u, 0x4bu, 0x68u, 0x9eu, 0x40u, 0xb4u, 0x46u, 0x13u, 0x68u, 0x9eu, 0xb2u, 0x63u, 0x46u, 0x1bu, 0x04u, 0x1eu, 0x43u, 0x16u, 0x60u, 0xeau, 0x60u, 0x8cu, 0x61u, 0xbcu, 0x40u, 0x01u, 0x9bu, 0xa4u, 0xb2u, 0x4bu, 0x62u, - 0xacu, 0x60u, 0xfeu, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x02u, 0x48u, 0xfau, 0xe7u, 0x48u, 0x04u, 0x00u, 0x08u, + 0xacu, 0x60u, 0xfeu, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x02u, 0x48u, 0xfau, 0xe7u, 0x40u, 0x04u, 0x00u, 0x08u, 0x04u, 0x02u, 0x8au, 0x00u, 0x07u, 0x02u, 0x8au, 0x00u, 0x2cu, 0x23u, 0x43u, 0x43u, 0x06u, 0x48u, 0x00u, 0x68u, 0xc0u, 0x18u, 0xc3u, 0x69u, 0x93u, 0x42u, 0x04u, 0xd9u, 0x03u, 0x6au, 0x00u, 0x20u, 0x92u, 0x00u, 0xd1u, 0x50u, - 0x70u, 0x47u, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x48u, 0x04u, 0x00u, 0x08u, 0x0au, 0x02u, 0x8au, 0x00u, + 0x70u, 0x47u, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x40u, 0x04u, 0x00u, 0x08u, 0x0au, 0x02u, 0x8au, 0x00u, 0x73u, 0xb5u, 0x00u, 0x26u, 0x42u, 0x69u, 0x04u, 0x00u, 0xd5u, 0x68u, 0x01u, 0x96u, 0x2bu, 0x0cu, 0xb3u, 0x42u, 0x21u, 0xd0u, 0x1bu, 0x04u, 0x13u, 0x60u, 0x13u, 0x68u, 0x19u, 0x4bu, 0x00u, 0x69u, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0xb3u, 0x42u, 0x15u, 0xdau, 0x01u, 0xa9u, 0xffu, 0xf7u, 0x22u, 0xffu, @@ -1614,503 +1614,505 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x69u, 0xffu, 0xf7u, 0xf1u, 0xfeu, 0xadu, 0xb2u, 0x00u, 0x2du, 0x09u, 0xd0u, 0x63u, 0x69u, 0x1du, 0x60u, 0x00u, 0x25u, 0x1bu, 0x68u, 0x63u, 0x6au, 0xabu, 0x42u, 0x05u, 0xd0u, 0x98u, 0x47u, 0x65u, 0x62u, 0xa5u, 0x61u, 0x63u, 0x69u, 0x1bu, 0x68u, 0x73u, 0xbdu, 0xa3u, 0x6au, 0x00u, 0x2bu, 0xf8u, 0xd0u, 0x98u, 0x47u, 0xf6u, 0xe7u, - 0x2cu, 0x06u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, 0x10u, 0x68u, 0xc0u, 0x18u, - 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x48u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x19u, 0x4bu, + 0x28u, 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0xe7u, 0x9du, 0x42u, 0xb9u, 0xd1u, 0xdeu, 0xe7u, 0x17u, 0x4cu, 0x03u, 0x2fu, + 0x05u, 0xd1u, 0x01u, 0x21u, 0x00u, 0x20u, 0x00u, 0xf0u, 0x9du, 0xf8u, 0x00u, 0x28u, 0xf9u, 0xd1u, 0x28u, 0x00u, + 0x00u, 0xf0u, 0x78u, 0xf8u, 0xd2u, 0xe7u, 0x15u, 0x4cu, 0xf1u, 0xe7u, 0x00u, 0xf0u, 0x8bu, 0xf8u, 0x0eu, 0x4au, + 0x05u, 0x00u, 0x01u, 0x21u, 0x30u, 0x00u, 0x00u, 0xf0u, 0x9du, 0xf8u, 0x00u, 0x28u, 0x09u, 0xd1u, 0x00u, 0x9bu, + 0x00u, 0x2bu, 0x08u, 0xd0u, 0x23u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x00u, 0xf0u, 0x8bu, 0xf8u, 0x04u, 0x00u, + 0xe5u, 0xe7u, 0x06u, 0x4cu, 0xe3u, 0xe7u, 0x09u, 0x4cu, 0xe1u, 0xe7u, 0xc0u, 0x46u, 0x28u, 0x06u, 0x00u, 0x08u, + 0x00u, 0x00u, 0x26u, 0x40u, 0x1cu, 0x05u, 0x00u, 0x00u, 0x2cu, 0x04u, 0x00u, 0x08u, 0x05u, 0x00u, 0x52u, 0x00u, + 0x01u, 0x01u, 0x88u, 0x00u, 0x3cu, 0x04u, 0x00u, 0x08u, 0xf0u, 0x49u, 0x02u, 0x00u, 0x01u, 0x00u, 0x50u, 0x00u, + 0x18u, 0x4bu, 0xf7u, 0xb5u, 0x1bu, 0x68u, 0x18u, 0x4au, 0x5cu, 0x68u, 0x04u, 0x23u, 0x11u, 0x69u, 0x0bu, 0x43u, + 0x13u, 0x61u, 0x01u, 0x28u, 0x24u, 0xd0u, 0x30u, 0xbfu, 0x23u, 0x00u, 0xfcu, 0x33u, 0x1bu, 0x69u, 0x00u, 0x2bu, + 0x1du, 0xd1u, 0xa3u, 0x20u, 0x11u, 0x4bu, 0x12u, 0x49u, 0x12u, 0x4au, 0xc0u, 0x00u, 0x0fu, 0x68u, 0x1eu, 0x58u, + 0x15u, 0x68u, 0x01u, 0x95u, 0x10u, 0x4du, 0x0du, 0x60u, 0x06u, 0x25u, 0x1du, 0x50u, 0x3eu, 0x20u, 0x10u, 0x60u, + 0x0eu, 0x48u, 0x3eu, 0x35u, 0x1du, 0x50u, 0x1du, 0x58u, 0x00u, 0x2du, 0xfcu, 0xdau, 0x0cu, 0x48u, 0xfcu, 0x34u, + 0x20u, 0x61u, 0x0fu, 0x60u, 0xa3u, 0x21u, 0xc9u, 0x00u, 0x5eu, 0x50u, 0x01u, 0x9bu, 0x13u, 0x60u, 0xf7u, 0xbdu, + 0x20u, 0xbfu, 0xd9u, 0xe7u, 0x28u, 0x06u, 0x00u, 0x08u, 0x00u, 0xedu, 0x00u, 0xe0u, 0x00u, 0x00u, 0x26u, 0x40u, + 0x08u, 0x01u, 0x26u, 0x40u, 0x04u, 0x01u, 0x26u, 0x40u, 0x1eu, 0x1fu, 0x00u, 0x00u, 0x1cu, 0x05u, 0x00u, 0x00u, + 0xaau, 0xaau, 0xaau, 0xaau, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x81u, 0x64u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x23u, 0x01u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x29u, 0x62u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, - 0x0du, 0x64u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0xa5u, 0x6du, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x1bu, 0x01u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, - 0x79u, 0x6du, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x0du, 0x64u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x55u, 0x60u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x0du, 0x61u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x91u, 0x5fu, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, }; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_02_cm0p_crypto.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_02_cm0p_crypto.c index f608dc4d33e..96de7c86bb2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_02_cm0p_crypto.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_02_cm0p_crypto.c @@ -37,19 +37,19 @@ const uint8_t cy_m0p_image[] = { 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0xb0u, 0x03u, 0x00u, 0x08u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x20u, 0x7eu, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x48u, 0x7eu, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xb4u, 0x03u, 0x00u, 0x08u, 0x20u, 0x7eu, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, + 0xb4u, 0x03u, 0x00u, 0x08u, 0x48u, 0x7eu, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, 0x02u, 0x38u, 0xfcu, 0xd1u, 0xc0u, 0x46u, 0xc0u, 0x46u, 0x70u, 0x47u, 0xefu, 0xf3u, 0x10u, 0x80u, 0x72u, 0xb6u, 0x70u, 0x47u, 0x80u, 0xf3u, 0x10u, 0x88u, 0x70u, 0x47u, 0x70u, 0x47u, 0xffu, 0xf7u, 0xfdu, 0xffu, 0x72u, 0xb6u, 0x0fu, 0x4cu, 0x10u, 0x4du, 0xacu, 0x42u, 0x09u, 0xdau, 0x21u, 0x68u, 0x62u, 0x68u, 0xa3u, 0x68u, 0x04u, 0x3bu, 0x02u, 0xdbu, 0xc8u, 0x58u, 0xd0u, 0x50u, 0xfau, 0xe7u, 0x0cu, 0x34u, 0xf3u, 0xe7u, 0x0au, 0x49u, 0x0bu, 0x4au, 0x00u, 0x20u, 0x52u, 0x1au, 0x02u, 0xddu, 0x04u, 0x3au, 0x88u, 0x50u, 0xfcu, 0xdcu, 0x08u, 0x48u, 0x09u, 0x49u, - 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x06u, 0xf0u, 0x63u, 0xfdu, 0x06u, 0xf0u, 0x03u, 0xfdu, 0xfeu, 0xe7u, - 0x2cu, 0x7eu, 0x00u, 0x10u, 0x44u, 0x7eu, 0x00u, 0x10u, 0xb0u, 0x03u, 0x00u, 0x08u, 0x10u, 0x06u, 0x00u, 0x08u, + 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x06u, 0xf0u, 0x75u, 0xfdu, 0x06u, 0xf0u, 0x15u, 0xfdu, 0xfeu, 0xe7u, + 0x54u, 0x7eu, 0x00u, 0x10u, 0x6cu, 0x7eu, 0x00u, 0x10u, 0xb0u, 0x03u, 0x00u, 0x08u, 0x0cu, 0x06u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x08u, 0x08u, 0xedu, 0x00u, 0xe0u, 0xfeu, 0xe7u, 0xfeu, 0xe7u, 0x00u, 0xb5u, 0x04u, 0x20u, 0x71u, 0x46u, 0x08u, 0x42u, 0x02u, 0xd0u, 0xefu, 0xf3u, 0x09u, 0x80u, 0x01u, 0xe0u, 0xefu, 0xf3u, 0x08u, 0x80u, - 0x04u, 0x30u, 0x06u, 0xf0u, 0xf5u, 0xfau, 0xfeu, 0xe7u, 0xf7u, 0xb5u, 0x03u, 0x27u, 0x11u, 0x4eu, 0x14u, 0x00u, + 0x04u, 0x30u, 0x06u, 0xf0u, 0x07u, 0xfbu, 0xfeu, 0xe7u, 0xf7u, 0xb5u, 0x03u, 0x27u, 0x11u, 0x4eu, 0x14u, 0x00u, 0x32u, 0x68u, 0x05u, 0x00u, 0x52u, 0x69u, 0x82u, 0x18u, 0x08u, 0x78u, 0x49u, 0x68u, 0x38u, 0x40u, 0x10u, 0x60u, 0x01u, 0x2cu, 0x00u, 0xd1u, 0x20u, 0x31u, 0x28u, 0x00u, 0x08u, 0x9au, 0x01u, 0x3cu, 0x03u, 0xf0u, 0x72u, 0xfdu, 0x0cu, 0x23u, 0x61u, 0x42u, 0x61u, 0x41u, 0x00u, 0x93u, 0x28u, 0x00u, 0x08u, 0x3bu, 0x44u, 0x31u, 0x00u, 0x22u, @@ -95,7 +95,7 @@ const uint8_t cy_m0p_image[] = { 0xd3u, 0xfeu, 0x10u, 0x23u, 0x2au, 0x00u, 0x07u, 0x99u, 0x30u, 0x00u, 0x03u, 0xf0u, 0xcbu, 0xfcu, 0x10u, 0x3cu, 0xcfu, 0xe7u, 0x01u, 0x48u, 0xdfu, 0xe7u, 0xc0u, 0x46u, 0x02u, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x91u, 0xb0u, 0x19u, 0x9du, 0x04u, 0x00u, 0x06u, 0x91u, 0x0bu, 0x92u, 0x00u, 0x21u, 0x10u, 0x22u, 0x0cu, 0xa8u, 0x07u, 0x93u, - 0x06u, 0xf0u, 0x5du, 0xfeu, 0x6bu, 0x68u, 0x0cu, 0xa9u, 0x1au, 0x00u, 0x40u, 0x32u, 0x03u, 0x92u, 0x60u, 0x33u, + 0x06u, 0xf0u, 0x6fu, 0xfeu, 0x6bu, 0x68u, 0x0cu, 0xa9u, 0x1au, 0x00u, 0x40u, 0x32u, 0x03u, 0x92u, 0x60u, 0x33u, 0x10u, 0x32u, 0x04u, 0x92u, 0x05u, 0x93u, 0x07u, 0x9au, 0x10u, 0x23u, 0x20u, 0x00u, 0x03u, 0xf0u, 0xaau, 0xfcu, 0x0fu, 0x9bu, 0x1bu, 0xbau, 0x08u, 0x93u, 0x06u, 0x9bu, 0x08u, 0x9eu, 0x1bu, 0x09u, 0x0au, 0x93u, 0x0eu, 0x9bu, 0x1fu, 0xbau, 0x08u, 0x9bu, 0x17u, 0x99u, 0xf3u, 0x1au, 0x1au, 0x01u, 0x89u, 0x18u, 0x09u, 0x91u, 0x18u, 0x99u, @@ -253,7 +253,7 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x28u, 0x00u, 0xdbu, 0x68u, 0x10u, 0x3cu, 0xebu, 0x18u, 0x1au, 0x60u, 0xffu, 0xf7u, 0x46u, 0xffu, 0xebu, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, 0xf0u, 0xb5u, 0x10u, 0x25u, 0x87u, 0xb0u, 0x0fu, 0x00u, 0x04u, 0x00u, 0x01u, 0x92u, 0x00u, 0x21u, 0x2au, 0x00u, - 0x02u, 0xa8u, 0x06u, 0xf0u, 0x6cu, 0xf9u, 0x80u, 0x23u, 0x7eu, 0x68u, 0x3fu, 0x68u, 0x02u, 0xaau, 0x13u, 0x70u, + 0x02u, 0xa8u, 0x06u, 0xf0u, 0x7eu, 0xf9u, 0x80u, 0x23u, 0x7eu, 0x68u, 0x3fu, 0x68u, 0x02u, 0xaau, 0x13u, 0x70u, 0x02u, 0xa9u, 0xeau, 0x1bu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x53u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x18u, 0x4du, 0x19u, 0x4au, 0x2bu, 0x68u, 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0x0fu, 0x2fu, 0x02u, 0xd8u, 0x30u, 0x00u, 0xffu, 0xf7u, 0x2du, 0xffu, 0x10u, 0x22u, 0x31u, 0x00u, 0x20u, 0x00u, @@ -264,7 +264,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, 0x08u, 0x00u, 0x10u, 0x41u, 0x01u, 0xc0u, 0x10u, 0x40u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x1eu, 0x00u, 0xa7u, 0xb0u, 0x2cu, 0xabu, 0x0au, 0xadu, 0x1fu, 0x78u, 0x02u, 0x91u, 0x03u, 0x92u, 0x00u, 0x21u, 0x70u, 0x22u, 0x28u, 0x00u, - 0x06u, 0xf0u, 0x15u, 0xf9u, 0x18u, 0x22u, 0x00u, 0x21u, 0x04u, 0xa8u, 0x06u, 0xf0u, 0x10u, 0xf9u, 0x3au, 0x00u, + 0x06u, 0xf0u, 0x27u, 0xf9u, 0x18u, 0x22u, 0x00u, 0x21u, 0x04u, 0xa8u, 0x06u, 0xf0u, 0x22u, 0xf9u, 0x3au, 0x00u, 0x2eu, 0x9bu, 0x31u, 0x00u, 0x00u, 0x95u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf3u, 0xfbu, 0x2eu, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xaau, 0xfbu, 0x06u, 0xabu, 0x04u, 0xa9u, 0x20u, 0x00u, 0x05u, 0x93u, 0xffu, 0xf7u, 0x2au, 0xffu, 0x03u, 0x9bu, 0x02u, 0x9au, 0x04u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x60u, 0xffu, 0x20u, 0x00u, 0x2du, 0x9au, @@ -304,7 +304,7 @@ const uint8_t cy_m0p_image[] = { 0x39u, 0x00u, 0x28u, 0x00u, 0x08u, 0x23u, 0x02u, 0xf0u, 0x45u, 0xfeu, 0x02u, 0x9bu, 0x04u, 0x9au, 0x28u, 0x00u, 0x01u, 0x97u, 0x00u, 0x96u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa1u, 0xffu, 0x28u, 0x00u, 0x08u, 0x23u, 0x32u, 0x00u, 0x05u, 0x99u, 0x02u, 0xf0u, 0x37u, 0xfeu, 0x20u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, - 0x38u, 0x71u, 0x00u, 0x10u, 0xfdu, 0xffu, 0xceu, 0xffu, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x89u, 0xb0u, + 0x60u, 0x71u, 0x00u, 0x10u, 0xfdu, 0xffu, 0xceu, 0xffu, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x89u, 0xb0u, 0x07u, 0x93u, 0x25u, 0x4bu, 0x04u, 0x00u, 0x1bu, 0x68u, 0x06u, 0x91u, 0x04u, 0x92u, 0x03u, 0x93u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x03u, 0x93u, 0x00u, 0x27u, 0x1fu, 0x4bu, 0x04u, 0x9du, 0xfeu, 0x00u, 0xf6u, 0x18u, 0x2bu, 0x00u, 0x10u, 0x33u, 0x05u, 0x93u, 0x08u, 0x23u, 0x32u, 0x00u, 0x29u, 0x00u, @@ -314,7 +314,7 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x08u, 0x23u, 0x02u, 0xf0u, 0xf6u, 0xfdu, 0x03u, 0x9fu, 0x03u, 0x9bu, 0x08u, 0x37u, 0x01u, 0x93u, 0x06u, 0x9au, 0x33u, 0x00u, 0x20u, 0x00u, 0x00u, 0x97u, 0x01u, 0x21u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x3au, 0x00u, 0x07u, 0x99u, 0x02u, 0xf0u, 0xe5u, 0xfdu, 0x28u, 0x00u, 0x09u, 0xb0u, 0xf0u, 0xbdu, - 0x08u, 0x35u, 0xcau, 0xe7u, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x38u, 0x71u, 0x00u, 0x10u, + 0x08u, 0x35u, 0xcau, 0xe7u, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x60u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, 0x70u, 0xb5u, 0x0fu, 0x26u, 0x0bu, 0x4bu, 0x1bu, 0x68u, 0x9cu, 0x68u, 0x05u, 0x19u, 0x2cu, 0x68u, 0x34u, 0x40u, 0x04u, 0x2cu, 0xfbu, 0xd8u, 0x86u, 0x25u, 0x6du, 0x01u, 0x44u, 0x59u, 0x00u, 0x2cu, 0xfcu, 0xdbu, 0xdcu, 0x68u, 0x05u, 0x4du, 0x04u, 0x19u, 0x25u, 0x60u, 0xdcu, 0x68u, 0x04u, 0x19u, 0x21u, 0x60u, @@ -335,7 +335,7 @@ const uint8_t cy_m0p_image[] = { 0x39u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbeu, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa0u, 0xffu, 0x01u, 0x99u, 0x20u, 0x00u, 0x4bu, 0x1eu, 0x99u, 0x41u, 0x52u, 0x31u, 0xffu, 0xf7u, 0x87u, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x01u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0x93u, 0xffu, 0x28u, 0x00u, - 0xfeu, 0xbdu, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xc0u, 0x46u, 0xb8u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, + 0xfeu, 0xbdu, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x27u, 0x85u, 0xb0u, 0x02u, 0x91u, 0x00u, 0x92u, 0x03u, 0x93u, 0x26u, 0x4bu, 0x00u, 0x9du, 0xfeu, 0x00u, 0xf6u, 0x18u, 0x2bu, 0x00u, 0x10u, 0x33u, 0x01u, 0x93u, 0x08u, 0x23u, 0x32u, 0x00u, 0x29u, 0x00u, 0x20u, 0x00u, 0x02u, 0xf0u, 0x68u, 0xfeu, 0x00u, 0x28u, 0x04u, 0xd0u, 0x01u, 0x9bu, 0x9du, 0x42u, @@ -346,15 +346,15 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0xffu, 0xf7u, 0x67u, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x49u, 0xffu, 0x02u, 0x99u, 0x20u, 0x00u, 0x4bu, 0x1eu, 0x99u, 0x41u, 0x54u, 0x31u, 0xffu, 0xf7u, 0x30u, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x01u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0x3cu, 0xffu, 0x28u, 0x00u, 0x05u, 0xb0u, - 0xf0u, 0xbdu, 0x08u, 0x35u, 0xbau, 0xe7u, 0xc0u, 0x46u, 0xb8u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, + 0xf0u, 0xbdu, 0x08u, 0x35u, 0xbau, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, 0x42u, 0x1eu, 0x03u, 0x00u, 0x00u, 0x20u, 0x04u, 0x2au, 0x03u, 0xd8u, 0x28u, 0x30u, 0x58u, 0x43u, 0x01u, 0x4bu, - 0xc0u, 0x18u, 0x70u, 0x47u, 0x38u, 0x72u, 0x00u, 0x10u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, + 0xc0u, 0x18u, 0x70u, 0x47u, 0x60u, 0x72u, 0x00u, 0x10u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, + 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xf2u, 0xf9u, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, - 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xdfu, 0xf9u, 0x10u, 0xbdu, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xdfu, 0xf9u, 0x10u, 0xbdu, 0xdcu, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0xadu, 0xb0u, 0x04u, 0x00u, 0x04u, 0x91u, 0x05u, 0x92u, 0x03u, 0x93u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x15u, 0xe1u, 0x03u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x11u, 0xe1u, 0x32u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x0du, 0xe1u, 0x33u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x09u, 0xe1u, 0x32u, 0x9bu, 0x58u, 0x78u, 0xffu, 0xf7u, @@ -392,7 +392,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x28u, 0x00u, 0xd0u, 0x71u, 0xe7u, 0x03u, 0x9bu, 0xe9u, 0x1du, 0xc9u, 0x08u, 0x59u, 0x18u, 0x0au, 0x22u, 0x2bu, 0x00u, 0x20u, 0x00u, 0x04u, 0xf0u, 0xc4u, 0xf8u, 0x68u, 0xe7u, 0x08u, 0x4eu, 0x6bu, 0xe7u, 0x07u, 0x4eu, 0x6eu, 0xe7u, 0x07u, 0x4eu, 0x6cu, 0xe7u, 0xc0u, 0x46u, 0x09u, 0x80u, 0x00u, 0x00u, 0x01u, 0x00u, 0x32u, 0x00u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0xb0u, 0xb0u, 0x00u, 0x00u, 0x0bu, 0x80u, 0x00u, 0x00u, 0x0bu, 0x00u, 0x32u, 0x00u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0xb0u, 0xb0u, 0x00u, 0x00u, 0x0bu, 0x80u, 0x00u, 0x00u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x0au, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x04u, 0x00u, 0x0fu, 0x1eu, 0x04u, 0x92u, 0x03u, 0x93u, 0x00u, 0xd1u, 0x8bu, 0xe1u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x88u, 0xe1u, 0x0cu, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x84u, 0xe1u, 0x0du, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x80u, 0xe1u, 0x58u, 0x78u, 0xffu, 0xf7u, 0x78u, 0xfeu, @@ -444,11 +444,11 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x21u, 0x20u, 0x00u, 0x03u, 0xf0u, 0x7au, 0xffu, 0x00u, 0x28u, 0x09u, 0xd0u, 0x01u, 0x23u, 0x0cu, 0x9au, 0x13u, 0x70u, 0x0eu, 0x49u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x27u, 0xfdu, 0x38u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x0cu, 0x9bu, 0x18u, 0x70u, 0xf5u, 0xe7u, 0x04u, 0x4fu, 0x09u, 0x49u, 0xf3u, 0xe7u, 0x02u, 0x4fu, 0xf4u, 0xe7u, - 0x08u, 0x4fu, 0xf2u, 0xe7u, 0xf5u, 0xffu, 0xcdu, 0xffu, 0x0bu, 0x00u, 0x32u, 0x00u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x08u, 0x4fu, 0xf2u, 0xe7u, 0xf5u, 0xffu, 0xcdu, 0xffu, 0x0bu, 0x00u, 0x32u, 0x00u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x80u, 0x80u, 0x00u, 0x00u, 0x08u, 0x60u, 0x00u, 0x00u, 0x06u, 0x80u, 0x00u, 0x00u, 0xf1u, 0x7eu, 0x00u, 0x00u, 0x30u, 0x60u, 0x00u, 0x00u, 0x0au, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, - 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xefu, 0xfeu, 0x10u, 0xbdu, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xefu, 0xfeu, 0x10u, 0xbdu, 0xdcu, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x85u, 0xb0u, 0x08u, 0x00u, 0x02u, 0x91u, 0x03u, 0x92u, 0x1eu, 0x00u, 0xffu, 0xf7u, 0xc7u, 0xfcu, 0x07u, 0x1eu, 0x00u, 0xd1u, 0x7bu, 0xe0u, 0x03u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x77u, 0xe0u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0x74u, 0xe0u, 0x73u, 0x68u, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x70u, 0xe0u, 0xb3u, 0x68u, @@ -473,24 +473,24 @@ const uint8_t cy_m0p_image[] = { 0x10u, 0xbdu, 0x00u, 0x00u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x02u, 0x4bu, 0x1bu, 0x68u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x02u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x20u, 0x68u, 0x10u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0au, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u, 0x25u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x0fu, 0xfeu, 0x10u, 0xbdu, 0x0fu, 0x23u, 0x13u, 0x43u, - 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, + 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x05u, 0xd8u, 0x05u, 0x4bu, 0x21u, 0x22u, 0x00u, 0x21u, - 0x01u, 0xf0u, 0xfau, 0xfdu, 0x10u, 0xbdu, 0x03u, 0x4bu, 0xf8u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x01u, 0xf0u, 0xfau, 0xfdu, 0x10u, 0xbdu, 0x03u, 0x4bu, 0xf8u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xc0u, 0xc0u, 0x00u, 0x00u, 0xcfu, 0xc0u, 0x00u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x10u, 0x22u, 0x19u, 0x00u, 0x01u, 0xf0u, 0xeau, 0xfdu, 0x10u, 0xbdu, 0x09u, 0x03u, 0x0bu, 0x00u, 0x13u, 0x43u, 0x00u, 0x22u, 0x10u, 0xb5u, 0x11u, 0x00u, 0x01u, 0xf0u, 0xe1u, 0xfdu, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, - 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xcfu, 0xfdu, 0x10u, 0xbdu, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xcfu, 0xfdu, 0x10u, 0xbdu, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, - 0x01u, 0xf0u, 0xbau, 0xfdu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x14u, 0x00u, + 0x01u, 0xf0u, 0xbau, 0xfdu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x14u, 0x00u, 0x07u, 0x4au, 0x15u, 0x68u, 0x24u, 0x22u, 0x29u, 0x35u, 0x2du, 0x78u, 0x1fu, 0x2du, 0x00u, 0xd9u, 0x01u, 0x3au, 0x24u, 0x01u, 0x23u, 0x43u, 0x09u, 0x03u, 0x0bu, 0x43u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xa5u, 0xfdu, 0x70u, 0xbdu, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x9cu, 0xfdu, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x9cu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x23u, 0x10u, 0xb5u, 0x11u, 0x22u, 0x19u, 0x00u, 0x01u, 0xf0u, 0x95u, 0xfdu, 0x10u, 0xbdu, 0x70u, 0xb5u, 0x04u, 0x00u, 0x1bu, 0x4du, 0xffu, 0xf7u, 0x9fu, 0xffu, 0x20u, 0x00u, 0x01u, 0x22u, 0x02u, 0x21u, 0xffu, 0xf7u, 0xa1u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x03u, 0x21u, 0xffu, 0xf7u, 0x9cu, 0xffu, 0x2au, 0x00u, @@ -523,7 +523,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x70u, 0xfeu, 0x94u, 0x4bu, 0x1bu, 0x78u, 0x00u, 0x2bu, 0x0bu, 0xd0u, 0x01u, 0x2bu, 0x01u, 0xd1u, 0x00u, 0xf0u, 0x35u, 0xfdu, 0x0eu, 0x9bu, 0x00u, 0x22u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x50u, 0xffu, 0x00u, 0xf0u, 0x24u, 0xfdu, 0x8du, 0x4bu, 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0x01u, 0xd9u, 0x00u, 0xf0u, - 0x1du, 0xfdu, 0x04u, 0xf0u, 0x27u, 0xffu, 0x05u, 0x00u, 0x89u, 0x00u, 0x25u, 0x01u, 0x73u, 0x03u, 0x18u, 0x05u, + 0x1du, 0xfdu, 0x04u, 0xf0u, 0x39u, 0xffu, 0x05u, 0x00u, 0x89u, 0x00u, 0x25u, 0x01u, 0x73u, 0x03u, 0x18u, 0x05u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa1u, 0xfeu, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa3u, 0xfeu, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x9eu, 0xfeu, 0x80u, 0x22u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa2u, 0xfeu, 0xc0u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x9du, 0xfeu, 0xc0u, 0x22u, @@ -688,7 +688,7 @@ const uint8_t cy_m0p_image[] = { 0x8bu, 0xffu, 0x00u, 0x21u, 0x44u, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x85u, 0xffu, 0xe0u, 0x21u, 0x49u, 0x00u, 0xffu, 0xf7u, 0x69u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xeau, 0xf9u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd8u, 0xf9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xdcu, 0xf9u, 0x09u, 0xb0u, 0xf0u, 0xbdu, 0x42u, 0x4bu, - 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0xf1u, 0xd8u, 0x04u, 0xf0u, 0xf2u, 0xf9u, 0x05u, 0x00u, 0x84u, 0x00u, + 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0xf1u, 0xd8u, 0x04u, 0xf0u, 0x04u, 0xfau, 0x05u, 0x00u, 0x84u, 0x00u, 0xd1u, 0x00u, 0xc7u, 0x01u, 0xedu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x76u, 0xf9u, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x78u, 0xf9u, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x73u, 0xf9u, 0x02u, 0x22u, 0x00u, 0x21u, 0xffu, 0x32u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x76u, 0xf9u, 0x80u, 0x22u, 0x01u, 0x21u, @@ -715,7 +715,7 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0xb0u, 0xfeu, 0x00u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0x01u, 0x23u, 0xffu, 0xf7u, 0x5du, 0xf8u, 0x20u, 0x00u, 0x03u, 0x23u, 0x00u, 0x22u, 0x01u, 0x21u, 0xffu, 0xf7u, 0xeeu, 0xf8u, 0x01u, 0x23u, 0x00u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x3eu, 0xf8u, 0x7fu, 0xe7u, 0x1cu, 0x22u, - 0xb3u, 0x49u, 0x01u, 0xa8u, 0x04u, 0xf0u, 0xf2u, 0xfau, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa5u, 0xf8u, 0x01u, 0x22u, + 0xb3u, 0x49u, 0x01u, 0xa8u, 0x04u, 0xf0u, 0x04u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa5u, 0xf8u, 0x01u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa7u, 0xf8u, 0x00u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa2u, 0xf8u, 0xe0u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa6u, 0xf8u, 0xf0u, 0x22u, 0x00u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa0u, 0xf8u, 0x80u, 0x22u, 0x01u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, @@ -746,7 +746,7 @@ const uint8_t cy_m0p_image[] = { 0x03u, 0x23u, 0x00u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x69u, 0xffu, 0x3eu, 0x23u, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xb0u, 0xfdu, 0x00u, 0x21u, 0x3eu, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xaau, 0xfdu, 0x23u, 0x21u, 0xffu, 0xf7u, 0x8fu, 0xf9u, 0x39u, 0x49u, 0x11u, 0x22u, 0x1cu, 0x31u, - 0x01u, 0xa8u, 0x04u, 0xf0u, 0xfbu, 0xf9u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xaeu, 0xffu, 0x01u, 0x22u, 0x04u, 0x21u, + 0x01u, 0xa8u, 0x04u, 0xf0u, 0x0du, 0xfau, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xaeu, 0xffu, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xb0u, 0xffu, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xabu, 0xffu, 0x31u, 0x4au, 0x00u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xafu, 0xffu, 0xf0u, 0x22u, 0x01u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xa9u, 0xffu, 0x81u, 0x22u, 0x06u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xa4u, 0xffu, @@ -760,7 +760,7 @@ const uint8_t cy_m0p_image[] = { 0x4bu, 0xfdu, 0x04u, 0x23u, 0x00u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xf8u, 0xfeu, 0x4eu, 0x23u, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x3fu, 0xfdu, 0x00u, 0x21u, 0x07u, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x39u, 0xfdu, 0x43u, 0x21u, 0xffu, 0xf7u, 0x1eu, 0xf9u, 0x12u, 0x10u, 0x00u, 0x00u, - 0x2du, 0x78u, 0x00u, 0x10u, 0x3eu, 0x30u, 0x30u, 0x00u, 0x01u, 0x02u, 0x00u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, + 0x55u, 0x78u, 0x00u, 0x10u, 0x3eu, 0x30u, 0x30u, 0x00u, 0x01u, 0x02u, 0x00u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, 0x70u, 0xb5u, 0x0cu, 0x00u, 0x05u, 0x00u, 0xfeu, 0xf7u, 0xdau, 0xfeu, 0x09u, 0x4bu, 0x26u, 0x01u, 0x33u, 0x43u, 0x28u, 0x00u, 0x3du, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0x1fu, 0xfdu, 0x24u, 0x03u, 0x05u, 0x4bu, 0x34u, 0x43u, 0x28u, 0x00u, 0x23u, 0x43u, 0x37u, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0x16u, 0xfdu, 0x70u, 0xbdu, 0xc0u, 0x46u, @@ -772,7 +772,7 @@ const uint8_t cy_m0p_image[] = { 0xebu, 0xfcu, 0x0bu, 0x4bu, 0x2du, 0x03u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x07u, 0xd8u, 0x2bu, 0x00u, 0x26u, 0x22u, 0x3bu, 0x43u, 0x30u, 0x00u, 0x00u, 0x21u, 0x00u, 0xf0u, 0xddu, 0xfcu, 0xf8u, 0xbdu, 0x0fu, 0x23u, 0x2bu, 0x43u, 0x3bu, 0x43u, 0x25u, 0x22u, 0xf5u, 0xe7u, 0xc0u, 0x46u, 0x0eu, 0x00u, 0x80u, 0x00u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x07u, 0xb5u, 0x00u, 0x93u, 0x13u, 0x00u, 0xfeu, 0xf7u, 0xf5u, 0xffu, 0x07u, 0xbdu, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x07u, 0xb5u, 0x00u, 0x93u, 0x13u, 0x00u, 0xfeu, 0xf7u, 0xf5u, 0xffu, 0x07u, 0xbdu, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x17u, 0x00u, 0x1eu, 0x00u, 0x0du, 0x00u, 0xfeu, 0xf7u, 0xd5u, 0xfeu, 0x3au, 0x00u, 0x07u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xd7u, 0xfeu, 0x32u, 0x00u, 0x08u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xd2u, 0xfeu, 0x2au, 0x00u, 0x0bu, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xcdu, 0xfeu, 0x06u, 0x9au, 0x09u, 0x21u, @@ -867,7 +867,7 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x90u, 0x08u, 0x22u, 0x00u, 0x97u, 0x07u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd0u, 0xfeu, 0x01u, 0x22u, 0x05u, 0x9bu, 0x13u, 0x42u, 0x0au, 0xd0u, 0x0bu, 0x23u, 0x01u, 0x93u, 0x01u, 0x3bu, 0x00u, 0x93u, 0x02u, 0x97u, 0x01u, 0x3bu, 0x07u, 0x32u, 0x07u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x0eu, 0xfeu, 0x01u, 0x35u, 0xcdu, 0xe7u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0xc5u, 0x60u, 0x00u, 0x00u, 0xc6u, 0xc0u, 0x00u, 0x00u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0xc5u, 0x60u, 0x00u, 0x00u, 0xc6u, 0xc0u, 0x00u, 0x00u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x80u, 0x22u, 0x0du, 0x4bu, 0x52u, 0x00u, 0x90u, 0x42u, 0x11u, 0xd0u, 0x07u, 0xd8u, 0x01u, 0x22u, 0xc0u, 0x28u, 0x0eu, 0xd0u, 0x02u, 0x22u, 0xe0u, 0x28u, 0x0bu, 0xd0u, 0x00u, 0x22u, 0x09u, 0xe0u, 0xc0u, 0x22u, 0x52u, 0x00u, 0x90u, 0x42u, 0x07u, 0xd0u, 0x05u, 0x4au, 0x90u, 0x42u, 0xf6u, 0xd1u, 0x05u, 0x22u, 0x00u, 0xe0u, 0x03u, 0x22u, @@ -876,7 +876,7 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x98u, 0x00u, 0x90u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x2fu, 0xffu, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x62u, 0xfbu, 0x13u, 0xbdu, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x93u, 0xb0u, 0x05u, 0x93u, 0x1au, 0xabu, 0x1cu, 0x78u, 0x65u, 0x4bu, 0x05u, 0x00u, 0x1bu, 0x68u, 0x03u, 0x91u, 0x04u, 0x92u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, - 0x1eu, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x06u, 0xa8u, 0x03u, 0xf0u, 0xf1u, 0xfdu, 0x33u, 0x00u, 0x81u, 0x33u, + 0x1eu, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x06u, 0xa8u, 0x03u, 0xf0u, 0x03u, 0xfeu, 0x33u, 0x00u, 0x81u, 0x33u, 0x22u, 0x00u, 0xffu, 0x33u, 0x06u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0xfcu, 0xfbu, 0x04u, 0x1eu, 0x00u, 0xd0u, 0x86u, 0xe0u, 0x33u, 0x00u, 0x80u, 0x33u, 0x01u, 0x93u, 0x98u, 0x23u, 0x01u, 0x9au, 0xdbu, 0x00u, 0x77u, 0x1cu, 0xf6u, 0x50u, 0xffu, 0x37u, 0xf3u, 0x18u, 0x5au, 0x60u, 0x9fu, 0x60u, 0x19u, 0x9au, 0x09u, 0x9bu, 0x9au, 0x42u, @@ -902,8 +902,8 @@ const uint8_t cy_m0p_image[] = { 0x86u, 0xe7u, 0xfau, 0x5cu, 0x01u, 0x9cu, 0x4au, 0x40u, 0xf2u, 0x54u, 0xfau, 0x5cu, 0x42u, 0x40u, 0xe2u, 0x54u, 0x01u, 0x33u, 0x80u, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x66u, 0x4cu, 0x05u, 0x00u, 0xa5u, 0x44u, 0x04u, 0x92u, 0x93u, 0x22u, 0x05u, 0x93u, 0x13u, 0xaeu, 0xaeu, 0xabu, 0x1cu, 0x78u, 0x03u, 0x91u, 0x92u, 0x00u, - 0x00u, 0x21u, 0x30u, 0x00u, 0x03u, 0xf0u, 0x23u, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x07u, 0xa8u, 0x03u, 0xf0u, - 0x1eu, 0xfdu, 0x22u, 0x00u, 0x73u, 0xabu, 0x07u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x77u, 0xfdu, 0x04u, 0x1eu, + 0x00u, 0x21u, 0x30u, 0x00u, 0x03u, 0xf0u, 0x35u, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x07u, 0xa8u, 0x03u, 0xf0u, + 0x30u, 0xfdu, 0x22u, 0x00u, 0x73u, 0xabu, 0x07u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x77u, 0xfdu, 0x04u, 0x1eu, 0x3bu, 0xd1u, 0x90u, 0x23u, 0x9bu, 0x00u, 0xf6u, 0x50u, 0x33u, 0xaau, 0x04u, 0x33u, 0xf2u, 0x50u, 0x0au, 0x9fu, 0x04u, 0x33u, 0x53u, 0xaau, 0xf2u, 0x50u, 0x10u, 0x9bu, 0xbeu, 0xb2u, 0x01u, 0x93u, 0x02u, 0x00u, 0x33u, 0x00u, 0x53u, 0xa9u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x6eu, 0xfcu, 0xadu, 0x9bu, 0xbbu, 0x42u, 0x2eu, 0xd9u, 0x07u, 0xa9u, @@ -934,9 +934,9 @@ const uint8_t cy_m0p_image[] = { 0x52u, 0x02u, 0xc3u, 0x18u, 0x19u, 0x68u, 0x11u, 0x42u, 0xfcu, 0xd0u, 0x23u, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0xf7u, 0xbdu, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, - 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xb0u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xb0u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x22u, 0x0eu, 0x21u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0du, 0x21u, 0xffu, 0xf7u, 0xdfu, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0xdau, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0bu, 0x21u, 0xffu, 0xf7u, 0xd5u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0au, 0x21u, @@ -949,7 +949,7 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x9eu, 0xffu, 0x03u, 0x4bu, 0x0fu, 0x21u, 0x1au, 0x68u, 0x20u, 0x00u, 0x92u, 0x08u, 0xffu, 0xf7u, 0x97u, 0xffu, 0x10u, 0xbdu, 0xd4u, 0x03u, 0x00u, 0x08u, 0x05u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x04u, 0x4bu, 0x1fu, 0x2au, 0x00u, 0xd9u, 0x04u, 0x4bu, 0x04u, 0x4au, 0x13u, 0x60u, - 0x70u, 0x47u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x5cu, 0x78u, 0x00u, 0x10u, 0xb0u, 0x78u, 0x00u, 0x10u, + 0x70u, 0x47u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x84u, 0x78u, 0x00u, 0x10u, 0xd8u, 0x78u, 0x00u, 0x10u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x2fu, 0x4bu, 0x70u, 0xb5u, 0x14u, 0x00u, 0x1au, 0x68u, 0x00u, 0x2au, 0x2cu, 0xd0u, 0x00u, 0x29u, 0x09u, 0xd1u, 0x00u, 0x2cu, 0x28u, 0xd1u, 0x13u, 0x6du, 0xc1u, 0x18u, 0x2au, 0x4bu, 0x1bu, 0x68u, 0x9cu, 0x6cu, 0x00u, 0x29u, 0x21u, 0xd0u, 0xa4u, 0x00u, 0x28u, 0x4bu, 0x65u, 0x1eu, 0x9du, 0x42u, 0x1cu, 0xd8u, @@ -962,7 +962,7 @@ const uint8_t cy_m0p_image[] = { 0xebu, 0xd1u, 0x1fu, 0x2eu, 0x02u, 0xd9u, 0x10u, 0x4du, 0x1bu, 0x02u, 0x43u, 0x51u, 0x93u, 0x6bu, 0xa2u, 0x08u, 0xc3u, 0x18u, 0x19u, 0x60u, 0x0fu, 0x21u, 0xffu, 0xf7u, 0x2du, 0xffu, 0x00u, 0x20u, 0x0bu, 0x4bu, 0x1cu, 0x60u, 0x70u, 0xbdu, 0x7cu, 0x23u, 0xe4u, 0xe7u, 0x78u, 0x23u, 0xe2u, 0xe7u, 0x60u, 0x23u, 0xe0u, 0xe7u, 0x40u, 0x23u, - 0xdeu, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xffu, 0x7fu, 0x00u, 0x00u, + 0xdeu, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xffu, 0x7fu, 0x00u, 0x00u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xffu, 0x3fu, 0x00u, 0x00u, 0x88u, 0x14u, 0x00u, 0x00u, 0xd4u, 0x03u, 0x00u, 0x08u, 0x20u, 0x4bu, 0x21u, 0x49u, 0x1bu, 0x68u, 0x09u, 0x68u, 0x9au, 0x6cu, 0x92u, 0x00u, 0x00u, 0x29u, 0x1cu, 0xd0u, 0x1eu, 0x49u, 0x09u, 0x68u, 0x00u, 0x29u, 0x18u, 0xd0u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x2fu, 0xd9u, @@ -972,18 +972,18 @@ const uint8_t cy_m0p_image[] = { 0x13u, 0xd0u, 0x7fu, 0x2bu, 0xf9u, 0xd1u, 0x80u, 0x22u, 0x52u, 0x00u, 0xf6u, 0xe7u, 0x80u, 0x22u, 0xd2u, 0x01u, 0xf3u, 0xe7u, 0x80u, 0x22u, 0x92u, 0x01u, 0xf0u, 0xe7u, 0x80u, 0x22u, 0x52u, 0x01u, 0xedu, 0xe7u, 0x80u, 0x22u, 0x12u, 0x01u, 0xeau, 0xe7u, 0x80u, 0x22u, 0xd2u, 0x00u, 0xe7u, 0xe7u, 0x80u, 0x22u, 0x92u, 0x00u, 0xe4u, 0xe7u, - 0x0au, 0x00u, 0xe2u, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xd4u, 0x03u, 0x00u, 0x08u, + 0x0au, 0x00u, 0xe2u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xd4u, 0x03u, 0x00u, 0x08u, 0x88u, 0x14u, 0x00u, 0x00u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0x30u, 0xffu, 0x17u, 0x4au, 0x18u, 0x49u, 0x13u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x17u, 0xd8u, 0x16u, 0x4bu, 0x23u, 0x60u, 0x01u, 0x20u, 0x09u, 0x68u, 0x4bu, 0x6bu, 0xe3u, 0x18u, 0x18u, 0x60u, 0x13u, 0x4bu, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x13u, 0x68u, 0x09u, 0x6du, 0x9au, 0x6cu, 0x61u, 0x18u, 0x92u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x2au, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbdu, 0xfeu, 0x00u, 0x20u, 0x10u, 0xbdu, 0x23u, 0x68u, 0x0bu, 0x48u, 0x03u, 0x40u, 0x23u, 0x60u, 0x0bu, 0x68u, 0x0au, 0x48u, 0x5bu, 0x68u, 0xe3u, 0x18u, 0x18u, 0x60u, 0x80u, 0x23u, 0x20u, 0x68u, - 0x1bu, 0x06u, 0x03u, 0x43u, 0x23u, 0x60u, 0x03u, 0x23u, 0xa3u, 0x60u, 0xd8u, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x1bu, 0x06u, 0x03u, 0x43u, 0x23u, 0x60u, 0x03u, 0x23u, 0xa3u, 0x60u, 0xd8u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x00u, 0x00u, 0x80u, 0xd4u, 0x03u, 0x00u, 0x08u, 0xffu, 0xffu, 0xfeu, 0x7fu, 0x01u, 0x00u, 0x02u, 0x00u, 0x03u, 0x23u, 0x03u, 0x70u, 0x00u, 0x20u, 0x70u, 0x47u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x00u, 0x23u, 0x03u, 0x60u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x20u, 0x03u, 0x4bu, - 0x18u, 0x60u, 0x70u, 0x47u, 0x83u, 0x60u, 0xf9u, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xd4u, 0x03u, 0x00u, 0x08u, + 0x18u, 0x60u, 0x70u, 0x47u, 0x83u, 0x60u, 0xf9u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd4u, 0x03u, 0x00u, 0x08u, 0x30u, 0xb5u, 0x01u, 0x29u, 0x0bu, 0xd9u, 0x01u, 0x22u, 0x0au, 0x40u, 0x54u, 0x42u, 0x62u, 0x41u, 0xcbu, 0x0fu, 0x5bu, 0x18u, 0x5bu, 0x10u, 0x9bu, 0x1au, 0x02u, 0x00u, 0x01u, 0x39u, 0x8bu, 0x42u, 0x00u, 0xdbu, 0x30u, 0xbdu, 0x14u, 0x78u, 0x45u, 0x5cu, 0x15u, 0x70u, 0x44u, 0x54u, 0x01u, 0x32u, 0x01u, 0x39u, 0xf5u, 0xe7u, 0x00u, 0x00u, @@ -1085,25 +1085,25 @@ const uint8_t cy_m0p_image[] = { 0x19u, 0x68u, 0x0bu, 0x68u, 0xc3u, 0x18u, 0x1cu, 0x68u, 0x00u, 0x2cu, 0xfcu, 0xdbu, 0x8bu, 0x69u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x20u, 0x13u, 0x60u, 0x10u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x24u, 0x68u, 0x29u, 0x34u, 0x24u, 0x78u, 0x1fu, 0x2cu, 0x02u, 0xd8u, 0xffu, 0xf7u, 0x05u, 0xfeu, 0x10u, 0xbdu, - 0xffu, 0xf7u, 0x12u, 0xffu, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, + 0xffu, 0xf7u, 0x12u, 0xffu, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, - 0xfau, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, + 0xfau, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u, 0x29u, 0x34u, 0x22u, 0x78u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x22u, 0xffu, 0xf7u, - 0xbfu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x22u, 0xffu, 0xf7u, 0xadu, 0xfeu, 0xfau, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0xbfu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x22u, 0xffu, 0xf7u, 0xadu, 0xfeu, 0xfau, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x03u, 0x34u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xd6u, 0xfau, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x0au, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u, 0x25u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xc5u, 0xfau, 0x10u, 0xbdu, - 0x0fu, 0x23u, 0x13u, 0x43u, 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x0fu, 0x23u, 0x13u, 0x43u, 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x09u, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u, 0x0bu, 0x43u, 0x21u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xadu, 0xfau, 0x10u, 0xbdu, - 0x0fu, 0x23u, 0x13u, 0x43u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, + 0x0fu, 0x23u, 0x13u, 0x43u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa0u, 0xfau, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x8du, 0xfau, 0x10u, 0xbdu, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, - 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x78u, 0xfau, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x78u, 0xfau, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x1du, 0x00u, 0x5eu, 0x1cu, 0x01u, 0x92u, 0x0fu, 0x00u, 0x32u, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xccu, 0xffu, 0x32u, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc7u, 0xffu, 0x32u, 0x00u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc2u, 0xffu, 0x2au, 0x00u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, @@ -1116,7 +1116,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x2au, 0xfau, 0x0du, 0x4bu, 0x03u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x24u, 0xfau, 0x33u, 0x00u, 0x3au, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xfau, 0x00u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x5du, 0xffu, 0x02u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x40u, 0xffu, - 0x01u, 0x3du, 0xd9u, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x02u, 0x00u, 0x30u, 0x00u, 0x01u, 0x00u, 0x30u, 0x00u, + 0x01u, 0x3du, 0xd9u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x02u, 0x00u, 0x30u, 0x00u, 0x01u, 0x00u, 0x30u, 0x00u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x9eu, 0x00u, 0x91u, 0x15u, 0x00u, 0x01u, 0x21u, 0x72u, 0x1cu, 0x77u, 0x00u, 0x01u, 0x93u, 0xffu, 0xf7u, 0x63u, 0xffu, 0x3au, 0x00u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x5eu, 0xffu, 0x3au, 0x00u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x59u, 0xffu, 0x32u, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, @@ -1138,7 +1138,7 @@ const uint8_t cy_m0p_image[] = { 0x7bu, 0xf9u, 0x20u, 0x00u, 0x10u, 0x4bu, 0x03u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x75u, 0xf9u, 0x00u, 0x9bu, 0x20u, 0x00u, 0x1au, 0x03u, 0x02u, 0x23u, 0x00u, 0x21u, 0x13u, 0x43u, 0x30u, 0x22u, 0xffu, 0xf7u, 0x6cu, 0xf9u, 0x0eu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc2u, 0xfeu, 0xf7u, 0xbdu, 0xc0u, 0x46u, 0x3au, 0x10u, 0x00u, 0x00u, - 0x18u, 0x20u, 0x00u, 0x00u, 0x23u, 0x20u, 0x00u, 0x00u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x20u, 0x20u, 0x00u, 0x00u, + 0x18u, 0x20u, 0x00u, 0x00u, 0x23u, 0x20u, 0x00u, 0x00u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x20u, 0x20u, 0x00u, 0x00u, 0x10u, 0x10u, 0x00u, 0x00u, 0x21u, 0x30u, 0x00u, 0x00u, 0x23u, 0x00u, 0x30u, 0x00u, 0x28u, 0x30u, 0x00u, 0x00u, 0xf7u, 0xb5u, 0x06u, 0x00u, 0x1cu, 0x00u, 0x09u, 0x9bu, 0x01u, 0x91u, 0x5fu, 0x00u, 0x15u, 0x00u, 0x02u, 0x21u, 0x3au, 0x00u, 0xffu, 0xf7u, 0xabu, 0xfeu, 0x3au, 0x00u, 0x03u, 0x21u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xa6u, 0xfeu, @@ -1156,7 +1156,7 @@ const uint8_t cy_m0p_image[] = { 0xebu, 0xf8u, 0x01u, 0x9bu, 0x30u, 0x00u, 0x1cu, 0x03u, 0x0du, 0x4bu, 0x30u, 0x22u, 0x23u, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xe2u, 0xf8u, 0xc0u, 0x23u, 0x9bu, 0x03u, 0x30u, 0x00u, 0x23u, 0x43u, 0x30u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xdau, 0xf8u, 0x30u, 0x00u, 0x03u, 0x21u, 0xffu, 0xf7u, 0x30u, 0xfeu, 0xf7u, 0xbdu, 0xc0u, 0x46u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x20u, 0x30u, 0x00u, 0x00u, 0x30u, 0x20u, 0x00u, 0x00u, 0x10u, 0x00u, 0x40u, 0x00u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x20u, 0x30u, 0x00u, 0x00u, 0x30u, 0x20u, 0x00u, 0x00u, 0x10u, 0x00u, 0x40u, 0x00u, 0x01u, 0x00u, 0x40u, 0x00u, 0xf8u, 0xb5u, 0x1du, 0x00u, 0x00u, 0x23u, 0x16u, 0x00u, 0x0fu, 0x00u, 0x10u, 0x22u, 0x19u, 0x00u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xc0u, 0xf8u, 0xe0u, 0x23u, 0x00u, 0x22u, 0x1bu, 0x02u, 0x11u, 0x00u, 0x3bu, 0x43u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb8u, 0xf8u, 0x90u, 0x23u, 0x00u, 0x22u, 0x1bu, 0x02u, 0x33u, 0x43u, @@ -1179,7 +1179,7 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x5cu, 0xfdu, 0x33u, 0x68u, 0x2cu, 0x22u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x00u, 0xd9u, 0x04u, 0x3au, 0x0eu, 0x4bu, 0xa8u, 0xe7u, 0x0eu, 0x4bu, 0x25u, 0x22u, 0xeau, 0xe7u, 0xe0u, 0x21u, 0x20u, 0x00u, 0x89u, 0x01u, 0xffu, 0xf7u, 0x79u, 0xfdu, 0x00u, 0x23u, 0x11u, 0x22u, 0x19u, 0x00u, - 0x20u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xf8u, 0xf8u, 0xbdu, 0xe0u, 0x05u, 0x00u, 0x08u, 0x0au, 0xb0u, 0x00u, 0x00u, + 0x20u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xf8u, 0xf8u, 0xbdu, 0xdcu, 0x05u, 0x00u, 0x08u, 0x0au, 0xb0u, 0x00u, 0x00u, 0x09u, 0xc0u, 0x00u, 0x00u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0xd0u, 0x00u, 0x00u, 0xd0u, 0xd0u, 0x00u, 0x00u, 0x0au, 0xe0u, 0x00u, 0x00u, 0xdfu, 0xd0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x06u, 0x00u, 0x0fu, 0x00u, 0x02u, 0x93u, 0x0au, 0x9du, 0x0bu, 0x98u, 0x06u, 0x2au, 0x37u, 0xd8u, 0x21u, 0x4bu, 0x91u, 0x00u, 0xc9u, 0x58u, @@ -1191,7 +1191,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x28u, 0x12u, 0xd1u, 0x00u, 0x9au, 0xa3u, 0xb2u, 0xaau, 0x18u, 0x02u, 0x99u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb5u, 0xfcu, 0x00u, 0x28u, 0x09u, 0xd1u, 0x38u, 0x70u, 0x07u, 0xe0u, 0x00u, 0x24u, 0x23u, 0x00u, 0x21u, 0x00u, 0xcau, 0xe7u, 0x01u, 0x30u, 0x42u, 0x78u, 0xffu, 0x2au, 0xe0u, 0xd0u, 0x00u, 0x20u, 0x05u, 0xb0u, 0xf0u, 0xbdu, - 0x04u, 0x79u, 0x00u, 0x10u, 0x27u, 0x79u, 0x00u, 0x10u, 0x20u, 0x79u, 0x00u, 0x10u, 0xf0u, 0xb5u, 0x8bu, 0xb0u, + 0x2cu, 0x79u, 0x00u, 0x10u, 0x4fu, 0x79u, 0x00u, 0x10u, 0x48u, 0x79u, 0x00u, 0x10u, 0xf0u, 0xb5u, 0x8bu, 0xb0u, 0x09u, 0x93u, 0x8bu, 0x68u, 0x04u, 0x00u, 0x05u, 0x93u, 0xcbu, 0x68u, 0x08u, 0x92u, 0x06u, 0x93u, 0x0bu, 0x68u, 0x4fu, 0x68u, 0x07u, 0x93u, 0x0bu, 0x69u, 0x8du, 0x69u, 0x03u, 0x93u, 0x4bu, 0x69u, 0x04u, 0x93u, 0xb3u, 0x4bu, 0x1bu, 0x68u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1eu, 0x68u, 0x20u, 0x00u, 0xffu, 0xf7u, @@ -1241,7 +1241,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x3cu, 0xfbu, 0x00u, 0x97u, 0x05u, 0x23u, 0xe9u, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x06u, 0x60u, 0x00u, 0x00u, 0x05u, 0x50u, 0x00u, 0x00u, 0x07u, 0x70u, 0x00u, 0x00u, 0x08u, 0x80u, 0x00u, 0x00u, 0x09u, 0xa0u, 0x00u, 0x00u, 0x0au, 0xc0u, 0x00u, 0x00u, 0x0bu, 0x50u, 0x00u, 0x00u, 0x07u, 0xb0u, 0x00u, 0x00u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0xb9u, 0xe0u, 0x00u, 0x00u, 0xbeu, 0xb0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x0bu, 0x69u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0xb9u, 0xe0u, 0x00u, 0x00u, 0xbeu, 0xb0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x0bu, 0x69u, 0x87u, 0xb0u, 0x03u, 0x93u, 0x4bu, 0x69u, 0x04u, 0x00u, 0x04u, 0x93u, 0x8bu, 0x69u, 0x0fu, 0x68u, 0x05u, 0x93u, 0x34u, 0x4bu, 0x4du, 0x68u, 0x1bu, 0x68u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1eu, 0x68u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x3du, 0xffu, 0x31u, 0x00u, 0x82u, 0xb2u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xfbu, @@ -1262,7 +1262,7 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x04u, 0x3bu, 0x00u, 0x22u, 0x4cu, 0x21u, 0xffu, 0xf7u, 0x36u, 0xf8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x04u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, 0x00u, 0xd9u, 0x80u, 0xe0u, 0x10u, 0x00u, 0x8bu, 0x60u, - 0x1au, 0x00u, 0x01u, 0xf0u, 0xfbu, 0xffu, 0x04u, 0x16u, 0x29u, 0x3au, 0x4du, 0x6cu, 0x5cu, 0x00u, 0x54u, 0x33u, + 0x1au, 0x00u, 0x02u, 0xf0u, 0x0du, 0xf8u, 0x04u, 0x16u, 0x29u, 0x3au, 0x4du, 0x6cu, 0x5cu, 0x00u, 0x54u, 0x33u, 0x8bu, 0x61u, 0x3cu, 0x4bu, 0x00u, 0x20u, 0xcbu, 0x62u, 0x40u, 0x23u, 0xcbu, 0x60u, 0x2cu, 0x3bu, 0x4bu, 0x61u, 0x4bu, 0x62u, 0x2du, 0x33u, 0x40u, 0x32u, 0xffu, 0x33u, 0x0au, 0x61u, 0x08u, 0x60u, 0x48u, 0x60u, 0xcbu, 0x61u, 0x00u, 0xbdu, 0x60u, 0x33u, 0x8bu, 0x61u, 0x01u, 0x23u, 0x0bu, 0x60u, 0x4bu, 0x60u, 0x32u, 0x4bu, 0x40u, 0x32u, @@ -1278,8 +1278,8 @@ const uint8_t cy_m0p_image[] = { 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x0au, 0x61u, 0x24u, 0x3bu, 0xdcu, 0xe7u, 0xc0u, 0x33u, 0x8bu, 0x61u, 0x05u, 0x23u, 0x0bu, 0x60u, 0x03u, 0x3bu, 0x4bu, 0x60u, 0x0cu, 0x4bu, 0x80u, 0x32u, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x0au, 0x61u, 0x20u, 0x3bu, 0xccu, 0xe7u, 0x08u, 0x48u, - 0x96u, 0xe7u, 0xc0u, 0x46u, 0xb0u, 0x79u, 0x00u, 0x10u, 0xc4u, 0x79u, 0x00u, 0x10u, 0xe4u, 0x79u, 0x00u, 0x10u, - 0x04u, 0x7au, 0x00u, 0x10u, 0x44u, 0x7au, 0x00u, 0x10u, 0x84u, 0x7au, 0x00u, 0x10u, 0xc4u, 0x7au, 0x00u, 0x10u, + 0x96u, 0xe7u, 0xc0u, 0x46u, 0xd8u, 0x79u, 0x00u, 0x10u, 0xecu, 0x79u, 0x00u, 0x10u, 0x0cu, 0x7au, 0x00u, 0x10u, + 0x2cu, 0x7au, 0x00u, 0x10u, 0x6cu, 0x7au, 0x00u, 0x10u, 0xacu, 0x7au, 0x00u, 0x10u, 0xecu, 0x7au, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, 0x10u, 0xbdu, 0x00u, 0x24u, 0x4bu, 0x69u, 0x8cu, 0x62u, 0x0cu, 0x62u, 0xa3u, 0x42u, 0xf7u, 0xd0u, 0xcau, 0x6au, 0x9bu, 0xb2u, 0x09u, 0x69u, 0xfeu, 0xf7u, 0xa0u, 0xffu, 0x20u, 0x00u, 0xf1u, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf7u, 0xb5u, 0x07u, 0x00u, @@ -1309,7 +1309,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x20u, 0x70u, 0xbdu, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x8fu, 0xb0u, 0x01u, 0x93u, 0x14u, 0xabu, 0x1fu, 0x78u, 0x19u, 0x4bu, 0x04u, 0x00u, 0x1bu, 0x68u, 0x00u, 0x91u, 0x16u, 0x00u, 0x1du, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1du, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, - 0x02u, 0xf0u, 0x6du, 0xf8u, 0x2bu, 0x00u, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, + 0x02u, 0xf0u, 0x7fu, 0xf8u, 0x2bu, 0x00u, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, 0x00u, 0x28u, 0x18u, 0xd1u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x0cu, 0xffu, 0x00u, 0x28u, 0x12u, 0xd1u, 0x33u, 0x00u, 0x00u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x18u, 0xffu, 0x00u, 0x28u, 0x0au, 0xd1u, 0x01u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x00u, 0x28u, 0x03u, 0xd1u, 0x02u, 0xa9u, @@ -1335,7 +1335,7 @@ const uint8_t cy_m0p_image[] = { 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x68u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0xceu, 0x21u, 0x04u, 0x4bu, 0xc9u, 0x05u, 0x1bu, 0x68u, 0x29u, 0x43u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x21u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, - 0x68u, 0xd8u, 0x10u, 0x00u, 0x8bu, 0x60u, 0x01u, 0xf0u, 0xb1u, 0xfdu, 0x04u, 0x1fu, 0x12u, 0x3bu, 0x2fu, 0x49u, + 0x68u, 0xd8u, 0x10u, 0x00u, 0x8bu, 0x60u, 0x01u, 0xf0u, 0xc3u, 0xfdu, 0x04u, 0x1fu, 0x12u, 0x3bu, 0x2fu, 0x49u, 0x57u, 0x00u, 0x40u, 0x33u, 0x0bu, 0x61u, 0x69u, 0x23u, 0x4bu, 0x60u, 0x2fu, 0x4bu, 0x00u, 0x20u, 0xcbu, 0x62u, 0x40u, 0x23u, 0xcbu, 0x60u, 0x2cu, 0x3bu, 0x08u, 0x60u, 0x4bu, 0x61u, 0x4bu, 0x62u, 0x00u, 0xbdu, 0x40u, 0x33u, 0x0bu, 0x61u, 0x02u, 0x23u, 0x0bu, 0x60u, 0x68u, 0x33u, 0x4bu, 0x60u, 0x28u, 0x4bu, 0xcbu, 0x62u, 0x40u, 0x23u, @@ -1348,9 +1348,9 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x23u, 0x0bu, 0x60u, 0x66u, 0x33u, 0x4bu, 0x60u, 0x10u, 0x4bu, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x20u, 0x3bu, 0xd4u, 0xe7u, 0x80u, 0x33u, 0x0bu, 0x61u, 0x06u, 0x23u, 0x0bu, 0x60u, 0x65u, 0x33u, 0x4bu, 0x60u, 0x0au, 0x4bu, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, - 0x24u, 0x3bu, 0xc6u, 0xe7u, 0x07u, 0x48u, 0xa9u, 0xe7u, 0x04u, 0x7bu, 0x00u, 0x10u, 0x38u, 0x7bu, 0x00u, 0x10u, - 0x18u, 0x7bu, 0x00u, 0x10u, 0x98u, 0x7bu, 0x00u, 0x10u, 0x58u, 0x7bu, 0x00u, 0x10u, 0x18u, 0x7cu, 0x00u, 0x10u, - 0xd8u, 0x7bu, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, + 0x24u, 0x3bu, 0xc6u, 0xe7u, 0x07u, 0x48u, 0xa9u, 0xe7u, 0x2cu, 0x7bu, 0x00u, 0x10u, 0x60u, 0x7bu, 0x00u, 0x10u, + 0x40u, 0x7bu, 0x00u, 0x10u, 0xc0u, 0x7bu, 0x00u, 0x10u, 0x80u, 0x7bu, 0x00u, 0x10u, 0x40u, 0x7cu, 0x00u, 0x10u, + 0x00u, 0x7cu, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, 0x10u, 0xbdu, 0x00u, 0x24u, 0x4bu, 0x69u, 0x8cu, 0x62u, 0x0cu, 0x62u, 0xa3u, 0x42u, 0xf7u, 0xd0u, 0xcau, 0x6au, 0x9bu, 0xb2u, 0x09u, 0x69u, 0xfeu, 0xf7u, 0x40u, 0xfeu, 0x20u, 0x00u, 0xf1u, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x04u, 0x00u, 0x0du, 0x1eu, 0x03u, 0x92u, 0x01u, 0x93u, 0x00u, 0xd1u, 0x95u, 0xe0u, @@ -1397,7 +1397,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0xc0u, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x85u, 0xfdu, 0x00u, 0x20u, 0x70u, 0xbdu, 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0xbfu, 0xb0u, 0x01u, 0x93u, 0x44u, 0xabu, 0x1fu, 0x78u, 0x0du, 0x00u, 0x16u, 0x00u, 0x00u, 0x21u, 0xc0u, 0x22u, 0x0eu, 0xa8u, 0x01u, 0xf0u, - 0xaeu, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, 0x01u, 0xf0u, 0xa9u, 0xfdu, 0x0eu, 0xabu, 0x3au, 0x00u, + 0xc0u, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, 0x01u, 0xf0u, 0xbbu, 0xfdu, 0x0eu, 0xabu, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x02u, 0xfeu, 0x00u, 0x28u, 0x18u, 0xd1u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, 0x00u, 0x28u, 0x12u, 0xd1u, 0x33u, 0x00u, 0x2au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x86u, 0xfeu, 0x00u, 0x28u, 0x0au, 0xd1u, 0x01u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, @@ -1422,15 +1422,15 @@ const uint8_t cy_m0p_image[] = { 0x1bu, 0x68u, 0x00u, 0x68u, 0x80u, 0x00u, 0x80u, 0x0cu, 0x80u, 0x00u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x24u, 0x68u, 0x29u, 0x34u, 0x24u, 0x78u, 0x1fu, 0x2cu, 0x02u, 0xd8u, 0xfeu, 0xf7u, 0x47u, 0xfbu, 0x10u, 0xbdu, 0xfeu, 0xf7u, 0x16u, 0xfcu, 0xfbu, 0xe7u, 0xc0u, 0x46u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x1fu, 0x24u, 0x95u, 0x00u, 0x13u, 0x05u, 0x09u, 0x4au, 0xadu, 0x0cu, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x1fu, 0x24u, 0x95u, 0x00u, 0x13u, 0x05u, 0x09u, 0x4au, 0xadu, 0x0cu, 0x12u, 0x68u, 0x89u, 0x06u, 0x29u, 0x32u, 0x12u, 0x78u, 0x1bu, 0x0du, 0x94u, 0x42u, 0xa4u, 0x41u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa5u, 0x40u, 0x0bu, 0x43u, 0x2bu, 0x43u, 0x80u, 0x22u, 0x00u, 0x21u, 0xfeu, 0xf7u, 0x6cu, 0xf8u, - 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, + 0x70u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u, + 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u, 0x29u, 0x34u, 0x22u, 0x78u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x22u, 0xfeu, 0xf7u, 0x21u, 0xfbu, 0x10u, 0xbdu, - 0x00u, 0x22u, 0xfeu, 0xf7u, 0x0fu, 0xfcu, 0xfau, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u, + 0x00u, 0x22u, 0xfeu, 0xf7u, 0x0fu, 0xfcu, 0xfau, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x93u, 0x0eu, 0x00u, 0x01u, 0x92u, 0xffu, 0xf7u, 0xcfu, 0xffu, 0x1bu, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x2du, 0xd8u, 0x19u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x69u, 0xe3u, 0x18u, 0x1fu, 0x68u, 0x5du, 0x68u, 0x31u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x83u, 0xffu, 0x06u, 0x00u, 0x00u, 0x9au, 0x01u, 0x00u, @@ -1438,14 +1438,14 @@ const uint8_t cy_m0p_image[] = { 0x01u, 0x9au, 0x07u, 0x33u, 0xdbu, 0x08u, 0x9bu, 0xb2u, 0x31u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x82u, 0xffu, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x09u, 0xd8u, 0x3au, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x87u, 0xffu, 0x2au, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x82u, 0xffu, - 0xf7u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xd4u, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xf7u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xd4u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x03u, 0x93u, 0x04u, 0x00u, 0x01u, 0x91u, 0x02u, 0x92u, 0xffu, 0xf7u, 0x8cu, 0xffu, 0x16u, 0x4eu, 0x33u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x23u, 0xd8u, 0x14u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x69u, 0xe3u, 0x18u, 0x1fu, 0x68u, 0x5du, 0x68u, 0x02u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x40u, 0xffu, 0x03u, 0x9bu, 0x02u, 0x00u, 0x07u, 0x33u, 0xdbu, 0x08u, 0x9bu, 0xb2u, 0x01u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x49u, 0xffu, 0x33u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x09u, 0xd8u, 0x3au, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x2au, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4au, 0xffu, - 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xdeu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xdeu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x0bu, 0x00u, 0x3fu, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u, 0xbbu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x50u, 0xffu, 0x03u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x20u, 0x68u, 0x40u, 0x07u, 0xc0u, 0x0fu, 0x10u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, @@ -1462,23 +1462,23 @@ const uint8_t cy_m0p_image[] = { 0x18u, 0x68u, 0x14u, 0x68u, 0x43u, 0x6au, 0x22u, 0x6cu, 0x6du, 0x03u, 0x9au, 0x18u, 0x11u, 0x68u, 0x29u, 0x40u, 0x10u, 0xd0u, 0x11u, 0x60u, 0x22u, 0x6cu, 0x9bu, 0x18u, 0x1bu, 0x68u, 0x0au, 0x4bu, 0x1au, 0x68u, 0x53u, 0x1cu, 0xd9u, 0x7fu, 0x00u, 0x29u, 0x07u, 0xd1u, 0x41u, 0x6au, 0x08u, 0x6au, 0x49u, 0x6au, 0x50u, 0x62u, 0x91u, 0x62u, - 0x01u, 0x22u, 0xdau, 0x77u, 0x30u, 0xbdu, 0x00u, 0x22u, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x01u, 0x22u, 0xdau, 0x77u, 0x30u, 0xbdu, 0x00u, 0x22u, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x03u, 0x00u, 0x08u, 0x00u, 0x22u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x03u, 0x68u, 0x0du, 0x00u, 0x0bu, 0x60u, 0x43u, 0x68u, 0x4bu, 0x60u, 0x83u, 0x69u, 0x8bu, 0x60u, 0xc3u, 0x69u, 0xcbu, 0x60u, 0x4bu, 0x1cu, 0xdau, 0x77u, 0x03u, 0x8cu, 0x0bu, 0x82u, 0x03u, 0x8du, 0x0bu, 0x83u, 0xfdu, 0xf7u, 0xceu, 0xffu, - 0xa1u, 0x69u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x20u, 0x49u, 0x20u, 0x00u, 0x20u, 0x30u, 0x00u, 0xf0u, 0x5cu, 0xfeu, + 0xa1u, 0x69u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x20u, 0x49u, 0x20u, 0x00u, 0x20u, 0x30u, 0x00u, 0xf0u, 0x6eu, 0xfeu, 0x20u, 0x22u, 0xa3u, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x1au, 0x4au, 0x13u, 0x60u, 0x1au, 0x4eu, 0x63u, 0x68u, 0x32u, 0x68u, 0x80u, 0x33u, 0x12u, 0x6au, 0x5bu, 0x01u, 0x9bu, 0x18u, 0x80u, 0x22u, 0x21u, 0x68u, 0x52u, 0x02u, 0x8au, 0x40u, 0xe1u, 0x69u, 0x9au, 0x60u, - 0x00u, 0x29u, 0x00u, 0xd1u, 0x13u, 0x49u, 0x20u, 0x00u, 0x28u, 0x30u, 0x00u, 0xf0u, 0x3du, 0xfeu, 0x28u, 0x23u, + 0x00u, 0x29u, 0x00u, 0xd1u, 0x13u, 0x49u, 0x20u, 0x00u, 0x28u, 0x30u, 0x00u, 0xf0u, 0x4fu, 0xfeu, 0x28u, 0x23u, 0xe0u, 0x5eu, 0xffu, 0xf7u, 0x8bu, 0xffu, 0x28u, 0x22u, 0xa3u, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x08u, 0x4au, 0x13u, 0x60u, 0x0au, 0x4au, 0x33u, 0x68u, 0x12u, 0x68u, 0x5bu, 0x6au, 0x92u, 0x6cu, 0x00u, 0x20u, 0x9bu, 0x18u, 0xf8u, 0x22u, 0x52u, 0x03u, 0x1au, 0x60u, 0x06u, 0x4bu, 0x1du, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe1u, 0x5eu, 0x00u, 0x10u, 0x00u, 0xe1u, 0x00u, 0xe0u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x79u, 0x59u, 0x00u, 0x10u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x03u, 0x00u, 0x08u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x79u, 0x59u, 0x00u, 0x10u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x06u, 0x4bu, 0x1fu, 0x2au, 0x04u, 0xd8u, 0x05u, 0x4au, 0x1au, 0x60u, 0xffu, 0xf7u, 0x90u, 0xffu, 0x10u, 0xbdu, 0x04u, 0x4au, 0xf9u, 0xe7u, 0xc0u, 0x46u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0xd8u, 0x03u, 0x00u, 0x08u, 0x58u, 0x7cu, 0x00u, 0x10u, 0xb0u, 0x7cu, 0x00u, 0x10u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0xd8u, 0x03u, 0x00u, 0x08u, 0x80u, 0x7cu, 0x00u, 0x10u, 0xd8u, 0x7cu, 0x00u, 0x10u, 0xf0u, 0xb5u, 0xb4u, 0x4bu, 0x85u, 0xb0u, 0x1cu, 0x68u, 0x00u, 0x2cu, 0x1eu, 0xd0u, 0xb2u, 0x4bu, 0xb3u, 0x4du, 0x63u, 0x60u, 0x2bu, 0x68u, 0x5fu, 0x6au, 0x23u, 0x78u, 0x01u, 0x2bu, 0x18u, 0xd1u, 0x38u, 0x00u, 0xfeu, 0xf7u, 0x21u, 0xf8u, 0x60u, 0x60u, 0x00u, 0x23u, 0xabu, 0x4au, 0xe1u, 0x69u, 0x13u, 0x60u, 0x2bu, 0x68u, 0x1au, 0x00u, @@ -1524,7 +1524,7 @@ const uint8_t cy_m0p_image[] = { 0x40u, 0x6au, 0x52u, 0x69u, 0xb0u, 0x47u, 0x99u, 0xe7u, 0x96u, 0x69u, 0xedu, 0xe7u, 0xd6u, 0x69u, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0xedu, 0xe6u, 0xa1u, 0x6au, 0x03u, 0x91u, 0x8bu, 0x6au, 0x02u, 0x93u, 0x4bu, 0x6au, 0x01u, 0x93u, 0x0bu, 0x6au, 0x00u, 0x93u, 0xcbu, 0x69u, 0x8au, 0x69u, 0x40u, 0x6au, 0x49u, 0x69u, 0xb0u, 0x47u, - 0x84u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x09u, 0x00u, 0x32u, 0x00u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x84u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x09u, 0x00u, 0x32u, 0x00u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x0au, 0x00u, 0x32u, 0x00u, 0xd8u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x03u, 0x00u, 0x08u, 0x01u, 0x00u, 0x32u, 0x00u, 0x56u, 0x6au, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0xc9u, 0xe6u, 0xa1u, 0x6au, 0x0bu, 0x7bu, 0x00u, 0x93u, 0x8bu, 0x68u, 0x4au, 0x68u, 0x40u, 0x6au, 0x09u, 0x68u, 0xb0u, 0x47u, 0x65u, 0xe7u, @@ -1549,10 +1549,10 @@ const uint8_t cy_m0p_image[] = { 0x29u, 0x6au, 0x80u, 0x33u, 0x5bu, 0x01u, 0xcbu, 0x18u, 0xdeu, 0x68u, 0x82u, 0x40u, 0x36u, 0x0cu, 0xb2u, 0x42u, 0x11u, 0xd1u, 0x12u, 0x04u, 0x1au, 0x60u, 0xacu, 0x35u, 0x1bu, 0x68u, 0x2bu, 0x88u, 0x58u, 0x43u, 0x40u, 0x18u, 0x07u, 0x49u, 0x00u, 0xf0u, 0xb5u, 0xf8u, 0x00u, 0x28u, 0x05u, 0xd1u, 0x23u, 0x68u, 0x9bu, 0x68u, 0x00u, 0x2bu, - 0x01u, 0xd1u, 0xffu, 0xf7u, 0xcdu, 0xfdu, 0x70u, 0xbdu, 0xdcu, 0x03u, 0x00u, 0x08u, 0xe0u, 0x05u, 0x00u, 0x08u, - 0xe0u, 0x03u, 0x00u, 0x08u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x01u, 0xd1u, 0xffu, 0xf7u, 0xcdu, 0xfdu, 0x70u, 0xbdu, 0xdcu, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, 0x50u, 0x43u, 0xc0u, 0x18u, - 0x70u, 0x47u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, + 0x70u, 0x47u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, 0x40u, 0x28u, 0x2fu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x30u, 0xd0u, 0x10u, 0x28u, 0x28u, 0xd0u, 0x19u, 0x48u, 0x1eu, 0xe0u, 0x80u, 0x28u, 0x28u, 0xd0u, 0x80u, 0x23u, 0x5bu, 0x00u, 0x98u, 0x42u, 0xf7u, 0xd1u, 0x14u, 0x48u, 0x16u, 0xe0u, 0x15u, 0x4bu, 0x98u, 0x42u, 0x14u, 0xd0u, 0x08u, 0xd8u, 0xa0u, 0x23u, 0x1bu, 0x06u, 0x98u, 0x42u, @@ -1566,26 +1566,26 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x00u, 0x52u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x9au, 0xffu, 0x0au, 0x4bu, 0x1cu, 0x68u, 0x23u, 0x00u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x0au, 0xdbu, 0x07u, 0x4bu, 0x18u, 0x68u, 0xffu, 0xf7u, 0x99u, 0xffu, 0x01u, 0x22u, 0x63u, 0x68u, 0x9au, 0x60u, 0x9au, 0x68u, 0x00u, 0x2au, - 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, + 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0x89u, 0xb2u, 0x41u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u, 0xc2u, 0x60u, 0x81u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x00u, 0x8au, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, - 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x18u, 0x60u, 0x70u, 0x47u, 0xf8u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x12u, 0x4cu, 0x1fu, 0x00u, 0x24u, 0x68u, 0x1eu, 0x0au, 0x20u, 0x18u, 0xffu, 0x24u, 0x27u, 0x40u, 0x34u, 0x40u, 0x0fu, 0x4eu, 0x1bu, 0x0cu, 0x35u, 0x68u, 0x07u, 0x60u, 0x2eu, 0x6au, 0x44u, 0x60u, 0x83u, 0x60u, 0xacu, 0x35u, 0x2du, 0x88u, 0x80u, 0x34u, 0x6fu, 0x43u, 0x64u, 0x01u, 0x34u, 0x19u, 0xbfu, 0x19u, 0x1eu, 0x04u, 0x33u, 0x43u, 0x07u, 0x61u, 0x44u, 0x61u, 0xa3u, 0x60u, 0x00u, 0x23u, 0x83u, 0x61u, 0x05u, 0x9bu, 0xc2u, 0x61u, 0x01u, 0x62u, 0x00u, 0x2bu, 0x01u, 0xd0u, 0x1bu, 0x88u, - 0x83u, 0x81u, 0xf0u, 0xbdu, 0xf8u, 0x03u, 0x00u, 0x08u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x83u, 0x68u, + 0x83u, 0x81u, 0xf0u, 0xbdu, 0xf8u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x83u, 0x68u, 0x85u, 0xb0u, 0x02u, 0xadu, 0x2bu, 0x80u, 0x15u, 0x4bu, 0x02u, 0x68u, 0x1bu, 0x68u, 0x06u, 0x6au, 0x9bu, 0x8eu, 0x47u, 0x6au, 0x9bu, 0x18u, 0x6bu, 0x80u, 0x43u, 0x68u, 0x00u, 0x95u, 0x82u, 0x6au, 0xc1u, 0x6au, 0x04u, 0x00u, 0x03u, 0x93u, 0x03u, 0x69u, 0xc0u, 0x68u, 0xffu, 0xf7u, 0xbdu, 0xffu, 0x00u, 0x21u, 0x3bu, 0x00u, 0x0au, 0x00u, - 0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x21u, 0x6bu, 0x28u, 0x00u, 0x00u, 0xf0u, 0xb4u, 0xfau, + 0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x21u, 0x6bu, 0x28u, 0x00u, 0x00u, 0xf0u, 0xc6u, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, - 0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, 0x26u, 0x68u, 0x69u, 0x43u, 0x34u, 0x18u, 0x25u, 0x69u, 0x01u, 0x93u, 0x71u, 0x18u, 0x00u, 0x2du, 0x19u, 0xd0u, 0x88u, 0x69u, 0x00u, 0x28u, 0x18u, 0xd1u, 0x2eu, 0x68u, 0x00u, 0x2eu, 0x15u, 0xdau, 0x67u, 0x68u, 0x01u, 0x24u, 0x26u, 0x00u, 0x4bu, 0x68u, @@ -1600,20 +1600,20 @@ const uint8_t cy_m0p_image[] = { 0x98u, 0x47u, 0x31u, 0x00u, 0x20u, 0x69u, 0xffu, 0xf7u, 0x0du, 0xffu, 0xadu, 0xb2u, 0x00u, 0x2du, 0x09u, 0xd0u, 0x63u, 0x69u, 0x1du, 0x60u, 0x00u, 0x25u, 0x1bu, 0x68u, 0x63u, 0x6au, 0xabu, 0x42u, 0x05u, 0xd0u, 0x98u, 0x47u, 0x65u, 0x62u, 0xa5u, 0x61u, 0x63u, 0x69u, 0x1bu, 0x68u, 0x73u, 0xbdu, 0xa3u, 0x6au, 0x00u, 0x2bu, 0xf8u, 0xd0u, - 0x98u, 0x47u, 0xf6u, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, + 0x98u, 0x47u, 0xf6u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, 0x10u, 0x68u, 0xc0u, 0x18u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xf8u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x19u, 0x4bu, 0x0fu, 0x00u, 0x1bu, 0x68u, 0x1au, 0x00u, 0x2eu, 0x32u, 0x12u, 0x78u, 0x82u, 0x42u, 0x27u, 0xd9u, 0x00u, 0x29u, 0x25u, 0xd0u, 0x1fu, 0x25u, 0x0au, 0x68u, 0x15u, 0x40u, 0x21u, 0xd1u, 0x19u, 0x00u, 0xacu, 0x31u, 0x0cu, 0x88u, 0x11u, 0x4eu, 0x60u, 0x43u, 0x1cu, 0x6au, 0xd2u, 0x08u, 0x04u, 0x19u, 0x29u, 0x00u, - 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0x2bu, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcau, 0xfeu, + 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0x3du, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcau, 0xfeu, 0x3au, 0x00u, 0x29u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xd7u, 0xfeu, 0x04u, 0x1eu, 0x07u, 0xd1u, 0x01u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xbfu, 0xfeu, 0x03u, 0x00u, 0x20u, 0x00u, 0x00u, 0x2bu, 0x00u, 0xd0u, 0x04u, 0x48u, - 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xfcu, 0x03u, 0x00u, 0x08u, + 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xfcu, 0x03u, 0x00u, 0x08u, 0x01u, 0x01u, 0x8au, 0x00u, 0x03u, 0x01u, 0x8au, 0x00u, 0x10u, 0xb5u, 0x00u, 0x2au, 0x0du, 0xd1u, 0x00u, 0x29u, 0x14u, 0xd1u, 0x0bu, 0x4bu, 0x1au, 0x68u, 0x13u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u, 0x58u, 0x43u, 0x13u, 0x6au, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x18u, 0x60u, 0x08u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x29u, 0x06u, 0xd0u, 0x06u, 0x4bu, 0x19u, 0x60u, 0x19u, 0x00u, 0x5au, 0x60u, 0xffu, 0xf7u, 0xabu, 0xffu, 0xf5u, 0xe7u, 0x03u, 0x48u, 0xf3u, 0xe7u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0xfcu, 0x03u, 0x00u, 0x08u, 0x78u, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0xfcu, 0x03u, 0x00u, 0x08u, 0x78u, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, 0xf7u, 0xb5u, 0x18u, 0x4fu, 0x04u, 0x00u, 0x3bu, 0x68u, 0x01u, 0x91u, 0xdeu, 0x68u, 0x33u, 0x68u, 0x83u, 0x42u, 0x26u, 0xd9u, 0x00u, 0x25u, 0xa9u, 0x42u, 0x02u, 0xd1u, 0xf9u, 0xf7u, 0xc7u, 0xfeu, 0x05u, 0x00u, 0x38u, 0x68u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x1au, 0xdau, 0x1fu, 0x22u, 0x01u, 0x23u, 0x22u, 0x40u, 0x93u, 0x40u, 0x64u, 0x09u, @@ -1626,10 +1626,19 @@ const uint8_t cy_m0p_image[] = { 0x18u, 0x40u, 0x43u, 0x1eu, 0x98u, 0x41u, 0x03u, 0x4bu, 0xc0u, 0x18u, 0x70u, 0x47u, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xfcu, 0x03u, 0x00u, 0x08u, 0x00u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0xa6u, 0x22u, 0x05u, 0x49u, 0xd2u, 0x00u, 0x8bu, 0x58u, 0x02u, 0x20u, 0xdbu, 0x43u, 0x9bu, 0x07u, 0x02u, 0xd0u, 0x01u, 0x23u, 0x88u, 0x58u, - 0x18u, 0x40u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x09u, 0x4au, 0x83u, 0x00u, 0x9bu, 0x18u, 0xd0u, 0x22u, - 0x92u, 0x00u, 0x98u, 0x58u, 0x07u, 0x22u, 0x10u, 0x40u, 0x04u, 0x28u, 0x07u, 0xd1u, 0xc0u, 0x22u, 0x92u, 0x00u, - 0x98u, 0x58u, 0x1fu, 0x23u, 0x03u, 0x40u, 0x80u, 0x20u, 0x40u, 0x00u, 0x18u, 0x43u, 0x70u, 0x47u, 0xc0u, 0x46u, - 0x00u, 0x00u, 0x26u, 0x40u, 0xb0u, 0x23u, 0x15u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x10u, 0xb5u, 0x99u, 0x03u, + 0x18u, 0x40u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0xefu, 0xffu, 0x00u, 0x23u, + 0x02u, 0x28u, 0x01u, 0xd1u, 0x01u, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x04u, 0x00u, 0x08u, + 0x09u, 0x4au, 0x83u, 0x00u, 0x9bu, 0x18u, 0xd0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x07u, 0x22u, 0x10u, 0x40u, + 0x04u, 0x28u, 0x07u, 0xd1u, 0xc0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x1fu, 0x23u, 0x03u, 0x40u, 0x80u, 0x20u, + 0x40u, 0x00u, 0x18u, 0x43u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, + 0xe7u, 0xffu, 0x02u, 0x28u, 0x1cu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x14u, 0xd0u, 0x01u, 0x28u, 0x14u, 0xd0u, + 0x00u, 0x20u, 0x11u, 0xe0u, 0x12u, 0x23u, 0xffu, 0x33u, 0x98u, 0x42u, 0x14u, 0xd0u, 0x14u, 0x23u, 0xffu, 0x33u, + 0x98u, 0x42u, 0x18u, 0xd0u, 0x03u, 0x3bu, 0x98u, 0x42u, 0xf2u, 0xd1u, 0x0cu, 0x4au, 0x0cu, 0x4bu, 0xd0u, 0x58u, + 0xc0u, 0x0fu, 0xc0u, 0x03u, 0x00u, 0xe0u, 0x0bu, 0x48u, 0x10u, 0xbdu, 0x0bu, 0x4bu, 0x18u, 0x68u, 0xfbu, 0xe7u, + 0xffu, 0xf7u, 0xbau, 0xffu, 0xf8u, 0xe7u, 0x09u, 0x4bu, 0x18u, 0x69u, 0x04u, 0x23u, 0x18u, 0x40u, 0xf3u, 0xd0u, + 0x80u, 0x20u, 0x00u, 0x02u, 0xf0u, 0xe7u, 0x01u, 0x4au, 0x05u, 0x4bu, 0xe8u, 0xe7u, 0x00u, 0x00u, 0x26u, 0x40u, + 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x12u, 0x7au, 0x00u, 0x04u, 0x04u, 0x00u, 0x08u, 0x00u, 0x00u, 0x27u, 0x40u, + 0x3cu, 0x05u, 0x00u, 0x00u, 0xb0u, 0x23u, 0x15u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x10u, 0xb5u, 0x99u, 0x03u, 0xdbu, 0x01u, 0xdbu, 0x0fu, 0x89u, 0x0bu, 0xc3u, 0x71u, 0x11u, 0x4bu, 0x01u, 0x60u, 0xd3u, 0x58u, 0x0fu, 0x24u, 0xd9u, 0x04u, 0xdbu, 0x01u, 0xdbu, 0x0du, 0x03u, 0x81u, 0xb1u, 0x23u, 0xdbu, 0x00u, 0xd3u, 0x58u, 0xc9u, 0x0cu, 0x81u, 0x80u, 0x19u, 0x00u, 0x21u, 0x40u, 0x81u, 0x72u, 0x19u, 0x09u, 0x21u, 0x40u, 0xc1u, 0x72u, 0xd9u, 0x02u, @@ -1639,463 +1648,457 @@ const uint8_t cy_m0p_image[] = { 0x3bu, 0x33u, 0x1bu, 0x78u, 0x93u, 0x42u, 0x16u, 0xd9u, 0x7fu, 0x22u, 0x1fu, 0x24u, 0x80u, 0x30u, 0xffu, 0x30u, 0x0bu, 0x4bu, 0x80u, 0x00u, 0xc3u, 0x58u, 0x1au, 0x40u, 0x0au, 0x70u, 0x1au, 0x0cu, 0x22u, 0x40u, 0x18u, 0x0au, 0x8au, 0x70u, 0x1au, 0x01u, 0x20u, 0x40u, 0xe2u, 0x40u, 0x48u, 0x70u, 0x00u, 0x20u, 0x9bu, 0x00u, 0x9bu, 0x0fu, - 0xcau, 0x70u, 0x0bu, 0x71u, 0x10u, 0xbdu, 0x03u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, - 0x00u, 0x00u, 0x26u, 0x40u, 0x01u, 0x00u, 0x4au, 0x00u, 0xe0u, 0x22u, 0x01u, 0x21u, 0x4du, 0x4bu, 0x80u, 0x00u, - 0xc0u, 0x18u, 0x92u, 0x00u, 0x83u, 0x58u, 0xf0u, 0xb5u, 0x9bu, 0x06u, 0x9bu, 0x0fu, 0x99u, 0x40u, 0x0fu, 0x23u, - 0x84u, 0x58u, 0x89u, 0xb0u, 0x1cu, 0x40u, 0x20u, 0x00u, 0x01u, 0x91u, 0xffu, 0xf7u, 0x7du, 0xffu, 0x03u, 0x28u, - 0x54u, 0xd0u, 0x08u, 0xd8u, 0x01u, 0x28u, 0x13u, 0xd0u, 0x62u, 0xd9u, 0xffu, 0xf7u, 0x67u, 0xffu, 0x42u, 0x4bu, - 0x02u, 0x28u, 0x0bu, 0xd1u, 0x0du, 0xe0u, 0x12u, 0x23u, 0xffu, 0x33u, 0x98u, 0x42u, 0x50u, 0xd0u, 0x14u, 0x23u, - 0xffu, 0x33u, 0x98u, 0x42u, 0x51u, 0xd0u, 0x03u, 0x3bu, 0x98u, 0x42u, 0x41u, 0xd0u, 0x00u, 0x26u, 0x01u, 0xe0u, - 0x3au, 0x4bu, 0x1eu, 0x68u, 0x00u, 0x2cu, 0x4du, 0xd1u, 0x03u, 0xadu, 0x14u, 0x22u, 0x21u, 0x00u, 0x28u, 0x00u, - 0x00u, 0xf0u, 0xddu, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x6du, 0xffu, 0xb0u, 0x23u, 0x31u, 0x4au, 0xdbu, 0x00u, + 0xcau, 0x70u, 0x0bu, 0x71u, 0x10u, 0xbdu, 0x03u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x00u, 0x00u, 0x26u, 0x40u, 0x01u, 0x00u, 0x4au, 0x00u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x04u, 0x00u, 0xffu, 0xf7u, + 0x65u, 0xffu, 0x06u, 0x00u, 0x00u, 0x2cu, 0x34u, 0xd1u, 0x01u, 0xadu, 0x14u, 0x22u, 0x21u, 0x00u, 0x28u, 0x00u, + 0x00u, 0xf0u, 0xcfu, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x95u, 0xffu, 0xb0u, 0x23u, 0x25u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xacu, 0x7bu, 0x02u, 0x3cu, 0x63u, 0x1eu, 0x9cu, 0x41u, 0xeau, 0x79u, - 0x03u, 0x9fu, 0x53u, 0x1eu, 0x9au, 0x41u, 0xa8u, 0x88u, 0x01u, 0x32u, 0x00u, 0x2cu, 0x16u, 0xd0u, 0x00u, 0x23u, - 0x19u, 0x00u, 0x00u, 0xf0u, 0xa5u, 0xfcu, 0x00u, 0x23u, 0x0cu, 0x00u, 0x05u, 0x00u, 0x3au, 0x00u, 0x30u, 0x00u, - 0x19u, 0x00u, 0x00u, 0xf0u, 0x9du, 0xfcu, 0xe6u, 0x07u, 0x6au, 0x08u, 0x32u, 0x43u, 0x63u, 0x08u, 0x80u, 0x18u, - 0x59u, 0x41u, 0x2au, 0x00u, 0x23u, 0x00u, 0x00u, 0xf0u, 0x73u, 0xfcu, 0x06u, 0x00u, 0x01u, 0x9bu, 0x58u, 0x08u, - 0x80u, 0x19u, 0x19u, 0x00u, 0x00u, 0xf0u, 0xe0u, 0xfbu, 0x09u, 0xb0u, 0xf0u, 0xbdu, 0x1cu, 0x4bu, 0xc0u, 0xe7u, - 0x18u, 0x4au, 0x1cu, 0x4bu, 0xd3u, 0x58u, 0x00u, 0x2bu, 0xb8u, 0xdau, 0x80u, 0x26u, 0x36u, 0x02u, 0xb9u, 0xe7u, - 0x19u, 0x4bu, 0x1bu, 0x69u, 0x5bu, 0x07u, 0xf8u, 0xd4u, 0xb0u, 0xe7u, 0x12u, 0x4au, 0x17u, 0x4bu, 0xf1u, 0xe7u, - 0x17u, 0x4eu, 0xafu, 0xe7u, 0x17u, 0x4bu, 0x1bu, 0x68u, 0x3bu, 0x33u, 0x1bu, 0x78u, 0xa3u, 0x42u, 0xddu, 0xd3u, - 0x03u, 0xadu, 0x05u, 0x22u, 0x00u, 0x21u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x89u, 0xfdu, 0x20u, 0x00u, 0x29u, 0x00u, - 0x80u, 0x34u, 0xffu, 0xf7u, 0x49u, 0xffu, 0xffu, 0x34u, 0x06u, 0x4bu, 0xa4u, 0x00u, 0xe3u, 0x58u, 0x00u, 0x24u, - 0xa3u, 0x42u, 0x03u, 0xdau, 0x2cu, 0x79u, 0x02u, 0x3cu, 0x63u, 0x1eu, 0x9cu, 0x41u, 0x2fu, 0x78u, 0x68u, 0x78u, - 0xaau, 0x78u, 0xaau, 0xe7u, 0x00u, 0x00u, 0x26u, 0x40u, 0x00u, 0x04u, 0x00u, 0x08u, 0x04u, 0x04u, 0x00u, 0x08u, - 0x5cu, 0x04u, 0x00u, 0x08u, 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x00u, 0x27u, 0x40u, 0x3cu, 0x05u, 0x00u, 0x00u, - 0x00u, 0x12u, 0x7au, 0x00u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x14u, 0x4bu, 0x30u, 0xb5u, 0x1au, 0x68u, 0x07u, 0x24u, - 0x13u, 0x00u, 0x28u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x15u, 0xd8u, 0x83u, 0x08u, 0x1du, 0x00u, 0xa5u, 0x43u, - 0x2cu, 0x1eu, 0x0fu, 0xd1u, 0x03u, 0x34u, 0x20u, 0x40u, 0xa0u, 0x40u, 0x81u, 0x40u, 0x12u, 0x68u, 0x9bu, 0x00u, - 0x20u, 0x32u, 0xd3u, 0x18u, 0x0au, 0x00u, 0xffu, 0x21u, 0x81u, 0x40u, 0x1cu, 0x68u, 0x62u, 0x40u, 0x11u, 0x40u, - 0x61u, 0x40u, 0x19u, 0x60u, 0x30u, 0xbdu, 0x80u, 0x23u, 0x20u, 0x40u, 0x1bu, 0x06u, 0x18u, 0x43u, 0x80u, 0x23u, - 0x9bu, 0x01u, 0x12u, 0x68u, 0xc9u, 0x18u, 0x89u, 0x00u, 0x88u, 0x50u, 0xf3u, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, - 0x06u, 0x4bu, 0x9au, 0x68u, 0x03u, 0x00u, 0x06u, 0x48u, 0x10u, 0x33u, 0x9bu, 0x00u, 0x82u, 0x42u, 0x02u, 0xd1u, - 0x98u, 0x58u, 0x99u, 0x50u, 0x70u, 0x47u, 0x03u, 0x4au, 0xd0u, 0x58u, 0xfbu, 0xe7u, 0x00u, 0xedu, 0x00u, 0xe0u, - 0x00u, 0x00u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x10u, 0xf8u, 0xb5u, 0x06u, 0x00u, 0x0du, 0x00u, 0x00u, 0x28u, - 0x3au, 0xd0u, 0x00u, 0x23u, 0xc0u, 0x5eu, 0x00u, 0x28u, 0x28u, 0xdbu, 0x71u, 0x88u, 0xffu, 0xf7u, 0xb4u, 0xffu, - 0x00u, 0x24u, 0xffu, 0x22u, 0x03u, 0x27u, 0x94u, 0x46u, 0x00u, 0x23u, 0xf0u, 0x5eu, 0x71u, 0x68u, 0x83u, 0xb2u, - 0x1fu, 0x40u, 0xffu, 0x00u, 0x66u, 0x46u, 0xbau, 0x40u, 0x89u, 0x01u, 0x31u, 0x40u, 0xd2u, 0x43u, 0xb9u, 0x40u, - 0x00u, 0x28u, 0x15u, 0xdbu, 0x11u, 0x4eu, 0x83u, 0x08u, 0x9bu, 0x00u, 0x9bu, 0x19u, 0xc0u, 0x26u, 0xb6u, 0x00u, - 0x9fu, 0x59u, 0x3au, 0x40u, 0x11u, 0x43u, 0x99u, 0x51u, 0x0du, 0x4bu, 0x9au, 0x68u, 0x0du, 0x4bu, 0x9au, 0x42u, - 0x02u, 0xd1u, 0x29u, 0x00u, 0xffu, 0xf7u, 0xbcu, 0xffu, 0x20u, 0x00u, 0xf8u, 0xbdu, 0x0au, 0x4cu, 0xd8u, 0xe7u, - 0x0fu, 0x26u, 0x33u, 0x40u, 0x08u, 0x3bu, 0x06u, 0x4eu, 0x9bu, 0x08u, 0x9bu, 0x00u, 0x9bu, 0x19u, 0xdeu, 0x69u, - 0x32u, 0x40u, 0x11u, 0x43u, 0xd9u, 0x61u, 0xe7u, 0xe7u, 0x03u, 0x4cu, 0xedu, 0xe7u, 0x00u, 0xe1u, 0x00u, 0xe0u, - 0x00u, 0xedu, 0x00u, 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0x30u, 0x00u, 0x00u, 0xf0u, 0xbeu, 0xf8u, + 0x00u, 0x28u, 0x37u, 0xd1u, 0x01u, 0x98u, 0xffu, 0xf7u, 0x8fu, 0xffu, 0x00u, 0x9bu, 0x00u, 0x2bu, 0x3eu, 0xd0u, + 0x23u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xdbu, 0x00u, 0xf0u, 0xe9u, 0xf8u, 0x04u, 0x00u, 0x2bu, 0xe0u, 0x06u, 0x20u, + 0x00u, 0xf0u, 0xd4u, 0xf8u, 0x2bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, + 0x02u, 0xdau, 0x28u, 0x4cu, 0x20u, 0x00u, 0xfeu, 0xbdu, 0x00u, 0x20u, 0x00u, 0xf0u, 0xbfu, 0xf8u, 0x26u, 0x4bu, + 0x98u, 0x42u, 0xf6u, 0xd0u, 0x00u, 0x23u, 0x25u, 0x4au, 0x19u, 0x00u, 0x12u, 0x68u, 0x01u, 0x20u, 0x00u, 0xf0u, + 0x9du, 0xf8u, 0x00u, 0x25u, 0xa8u, 0x42u, 0xecu, 0xd1u, 0x00u, 0x20u, 0x00u, 0xf0u, 0xafu, 0xf8u, 0x1eu, 0x4au, + 0x1fu, 0x4bu, 0x90u, 0x42u, 0x03u, 0xd0u, 0x9du, 0x42u, 0xe3u, 0xd0u, 0x01u, 0x35u, 0xf4u, 0xe7u, 0x9du, 0x42u, + 0xb9u, 0xd1u, 0xdeu, 0xe7u, 0x17u, 0x4cu, 0x03u, 0x2fu, 0x05u, 0xd1u, 0x01u, 0x21u, 0x00u, 0x20u, 0x00u, 0xf0u, + 0xadu, 0xf8u, 0x00u, 0x28u, 0xf9u, 0xd1u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x88u, 0xf8u, 0xd2u, 0xe7u, 0x15u, 0x4cu, + 0xf1u, 0xe7u, 0x00u, 0xf0u, 0x6bu, 0xf8u, 0x0eu, 0x4au, 0x05u, 0x00u, 0x01u, 0x21u, 0x30u, 0x00u, 0x00u, 0xf0u, + 0x6du, 0xf8u, 0x00u, 0x28u, 0x09u, 0xd1u, 0x00u, 0x9bu, 0x00u, 0x2bu, 0x08u, 0xd0u, 0x23u, 0x68u, 0x00u, 0x2bu, + 0xfcu, 0xdbu, 0x00u, 0xf0u, 0x9bu, 0xf8u, 0x04u, 0x00u, 0xe5u, 0xe7u, 0x06u, 0x4cu, 0xe3u, 0xe7u, 0x09u, 0x4cu, + 0xe1u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, 0x1cu, 0x05u, 0x00u, 0x00u, + 0xe4u, 0x03u, 0x00u, 0x08u, 0x05u, 0x00u, 0x52u, 0x00u, 0x01u, 0x01u, 0x88u, 0x00u, 0xf4u, 0x03u, 0x00u, 0x08u, + 0xf0u, 0x49u, 0x02u, 0x00u, 0x01u, 0x00u, 0x50u, 0x00u, 0x18u, 0x4bu, 0xf7u, 0xb5u, 0x1bu, 0x68u, 0x18u, 0x4au, + 0x5cu, 0x68u, 0x04u, 0x23u, 0x11u, 0x69u, 0x0bu, 0x43u, 0x13u, 0x61u, 0x01u, 0x28u, 0x24u, 0xd0u, 0x30u, 0xbfu, + 0x23u, 0x00u, 0xfcu, 0x33u, 0x1bu, 0x69u, 0x00u, 0x2bu, 0x1du, 0xd1u, 0xa3u, 0x20u, 0x11u, 0x4bu, 0x12u, 0x49u, + 0x12u, 0x4au, 0xc0u, 0x00u, 0x0fu, 0x68u, 0x1eu, 0x58u, 0x15u, 0x68u, 0x01u, 0x95u, 0x10u, 0x4du, 0x0du, 0x60u, + 0x06u, 0x25u, 0x1du, 0x50u, 0x3eu, 0x20u, 0x10u, 0x60u, 0x0eu, 0x48u, 0x3eu, 0x35u, 0x1du, 0x50u, 0x1du, 0x58u, + 0x00u, 0x2du, 0xfcu, 0xdau, 0x0cu, 0x48u, 0xfcu, 0x34u, 0x20u, 0x61u, 0x0fu, 0x60u, 0xa3u, 0x21u, 0xc9u, 0x00u, + 0x5eu, 0x50u, 0x01u, 0x9bu, 0x13u, 0x60u, 0xf7u, 0xbdu, 0x20u, 0xbfu, 0xd9u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x00u, 0xedu, 0x00u, 0xe0u, 0x00u, 0x00u, 0x26u, 0x40u, 0x08u, 0x01u, 0x26u, 0x40u, 0x04u, 0x01u, 0x26u, 0x40u, + 0x1eu, 0x1fu, 0x00u, 0x00u, 0x1cu, 0x05u, 0x00u, 0x00u, 0xaau, 0xaau, 0xaau, 0xaau, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xdbu, 0x00u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x69u, 0x60u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x75u, 0x61u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xe3u, 0x00u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xbdu, 0x6cu, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xa5u, 0x63u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x41u, 0x5fu, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x31u, 0x63u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x05u, 0x60u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, }; #endif /* defined(CY_DEVICE_PSOC6A2M) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_03_cm0p_crypto.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_03_cm0p_crypto.c index 37fdf2d4aa8..271f5712626 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_03_cm0p_crypto.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_CRYPTO/psoc6_03_cm0p_crypto.c @@ -37,19 +37,19 @@ const uint8_t cy_m0p_image[] = { 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0xb0u, 0x03u, 0x00u, 0x08u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x20u, 0x7eu, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x48u, 0x7eu, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xb4u, 0x03u, 0x00u, 0x08u, 0x20u, 0x7eu, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, + 0xb4u, 0x03u, 0x00u, 0x08u, 0x48u, 0x7eu, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, 0x02u, 0x38u, 0xfcu, 0xd1u, 0xc0u, 0x46u, 0xc0u, 0x46u, 0x70u, 0x47u, 0xefu, 0xf3u, 0x10u, 0x80u, 0x72u, 0xb6u, 0x70u, 0x47u, 0x80u, 0xf3u, 0x10u, 0x88u, 0x70u, 0x47u, 0x70u, 0x47u, 0xffu, 0xf7u, 0xfdu, 0xffu, 0x72u, 0xb6u, 0x0fu, 0x4cu, 0x10u, 0x4du, 0xacu, 0x42u, 0x09u, 0xdau, 0x21u, 0x68u, 0x62u, 0x68u, 0xa3u, 0x68u, 0x04u, 0x3bu, 0x02u, 0xdbu, 0xc8u, 0x58u, 0xd0u, 0x50u, 0xfau, 0xe7u, 0x0cu, 0x34u, 0xf3u, 0xe7u, 0x0au, 0x49u, 0x0bu, 0x4au, 0x00u, 0x20u, 0x52u, 0x1au, 0x02u, 0xddu, 0x04u, 0x3au, 0x88u, 0x50u, 0xfcu, 0xdcu, 0x08u, 0x48u, 0x09u, 0x49u, - 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x06u, 0xf0u, 0x63u, 0xfdu, 0x06u, 0xf0u, 0x03u, 0xfdu, 0xfeu, 0xe7u, - 0x2cu, 0x7eu, 0x00u, 0x10u, 0x44u, 0x7eu, 0x00u, 0x10u, 0xb0u, 0x03u, 0x00u, 0x08u, 0x10u, 0x06u, 0x00u, 0x08u, + 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x06u, 0xf0u, 0x75u, 0xfdu, 0x06u, 0xf0u, 0x15u, 0xfdu, 0xfeu, 0xe7u, + 0x54u, 0x7eu, 0x00u, 0x10u, 0x6cu, 0x7eu, 0x00u, 0x10u, 0xb0u, 0x03u, 0x00u, 0x08u, 0x0cu, 0x06u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x08u, 0x08u, 0xedu, 0x00u, 0xe0u, 0xfeu, 0xe7u, 0xfeu, 0xe7u, 0x00u, 0xb5u, 0x04u, 0x20u, 0x71u, 0x46u, 0x08u, 0x42u, 0x02u, 0xd0u, 0xefu, 0xf3u, 0x09u, 0x80u, 0x01u, 0xe0u, 0xefu, 0xf3u, 0x08u, 0x80u, - 0x04u, 0x30u, 0x06u, 0xf0u, 0xf5u, 0xfau, 0xfeu, 0xe7u, 0xf7u, 0xb5u, 0x03u, 0x27u, 0x11u, 0x4eu, 0x14u, 0x00u, + 0x04u, 0x30u, 0x06u, 0xf0u, 0x07u, 0xfbu, 0xfeu, 0xe7u, 0xf7u, 0xb5u, 0x03u, 0x27u, 0x11u, 0x4eu, 0x14u, 0x00u, 0x32u, 0x68u, 0x05u, 0x00u, 0x52u, 0x69u, 0x82u, 0x18u, 0x08u, 0x78u, 0x49u, 0x68u, 0x38u, 0x40u, 0x10u, 0x60u, 0x01u, 0x2cu, 0x00u, 0xd1u, 0x20u, 0x31u, 0x28u, 0x00u, 0x08u, 0x9au, 0x01u, 0x3cu, 0x03u, 0xf0u, 0x72u, 0xfdu, 0x0cu, 0x23u, 0x61u, 0x42u, 0x61u, 0x41u, 0x00u, 0x93u, 0x28u, 0x00u, 0x08u, 0x3bu, 0x44u, 0x31u, 0x00u, 0x22u, @@ -95,7 +95,7 @@ const uint8_t cy_m0p_image[] = { 0xd3u, 0xfeu, 0x10u, 0x23u, 0x2au, 0x00u, 0x07u, 0x99u, 0x30u, 0x00u, 0x03u, 0xf0u, 0xcbu, 0xfcu, 0x10u, 0x3cu, 0xcfu, 0xe7u, 0x01u, 0x48u, 0xdfu, 0xe7u, 0xc0u, 0x46u, 0x02u, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x91u, 0xb0u, 0x19u, 0x9du, 0x04u, 0x00u, 0x06u, 0x91u, 0x0bu, 0x92u, 0x00u, 0x21u, 0x10u, 0x22u, 0x0cu, 0xa8u, 0x07u, 0x93u, - 0x06u, 0xf0u, 0x5du, 0xfeu, 0x6bu, 0x68u, 0x0cu, 0xa9u, 0x1au, 0x00u, 0x40u, 0x32u, 0x03u, 0x92u, 0x60u, 0x33u, + 0x06u, 0xf0u, 0x6fu, 0xfeu, 0x6bu, 0x68u, 0x0cu, 0xa9u, 0x1au, 0x00u, 0x40u, 0x32u, 0x03u, 0x92u, 0x60u, 0x33u, 0x10u, 0x32u, 0x04u, 0x92u, 0x05u, 0x93u, 0x07u, 0x9au, 0x10u, 0x23u, 0x20u, 0x00u, 0x03u, 0xf0u, 0xaau, 0xfcu, 0x0fu, 0x9bu, 0x1bu, 0xbau, 0x08u, 0x93u, 0x06u, 0x9bu, 0x08u, 0x9eu, 0x1bu, 0x09u, 0x0au, 0x93u, 0x0eu, 0x9bu, 0x1fu, 0xbau, 0x08u, 0x9bu, 0x17u, 0x99u, 0xf3u, 0x1au, 0x1au, 0x01u, 0x89u, 0x18u, 0x09u, 0x91u, 0x18u, 0x99u, @@ -253,7 +253,7 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x4bu, 0x06u, 0x4au, 0x1bu, 0x68u, 0x28u, 0x00u, 0xdbu, 0x68u, 0x10u, 0x3cu, 0xebu, 0x18u, 0x1au, 0x60u, 0xffu, 0xf7u, 0x46u, 0xffu, 0xebu, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, 0xf0u, 0xb5u, 0x10u, 0x25u, 0x87u, 0xb0u, 0x0fu, 0x00u, 0x04u, 0x00u, 0x01u, 0x92u, 0x00u, 0x21u, 0x2au, 0x00u, - 0x02u, 0xa8u, 0x06u, 0xf0u, 0x6cu, 0xf9u, 0x80u, 0x23u, 0x7eu, 0x68u, 0x3fu, 0x68u, 0x02u, 0xaau, 0x13u, 0x70u, + 0x02u, 0xa8u, 0x06u, 0xf0u, 0x7eu, 0xf9u, 0x80u, 0x23u, 0x7eu, 0x68u, 0x3fu, 0x68u, 0x02u, 0xaau, 0x13u, 0x70u, 0x02u, 0xa9u, 0xeau, 0x1bu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x53u, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0x18u, 0x4du, 0x19u, 0x4au, 0x2bu, 0x68u, 0xdbu, 0x68u, 0xe3u, 0x18u, 0x1au, 0x60u, 0x0fu, 0x2fu, 0x02u, 0xd8u, 0x30u, 0x00u, 0xffu, 0xf7u, 0x2du, 0xffu, 0x10u, 0x22u, 0x31u, 0x00u, 0x20u, 0x00u, @@ -264,7 +264,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x2bu, 0xfcu, 0xd1u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x18u, 0x00u, 0x10u, 0x41u, 0x08u, 0x00u, 0x10u, 0x41u, 0x01u, 0xc0u, 0x10u, 0x40u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x1eu, 0x00u, 0xa7u, 0xb0u, 0x2cu, 0xabu, 0x0au, 0xadu, 0x1fu, 0x78u, 0x02u, 0x91u, 0x03u, 0x92u, 0x00u, 0x21u, 0x70u, 0x22u, 0x28u, 0x00u, - 0x06u, 0xf0u, 0x15u, 0xf9u, 0x18u, 0x22u, 0x00u, 0x21u, 0x04u, 0xa8u, 0x06u, 0xf0u, 0x10u, 0xf9u, 0x3au, 0x00u, + 0x06u, 0xf0u, 0x27u, 0xf9u, 0x18u, 0x22u, 0x00u, 0x21u, 0x04u, 0xa8u, 0x06u, 0xf0u, 0x22u, 0xf9u, 0x3au, 0x00u, 0x2eu, 0x9bu, 0x31u, 0x00u, 0x00u, 0x95u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xf3u, 0xfbu, 0x2eu, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xaau, 0xfbu, 0x06u, 0xabu, 0x04u, 0xa9u, 0x20u, 0x00u, 0x05u, 0x93u, 0xffu, 0xf7u, 0x2au, 0xffu, 0x03u, 0x9bu, 0x02u, 0x9au, 0x04u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x60u, 0xffu, 0x20u, 0x00u, 0x2du, 0x9au, @@ -304,7 +304,7 @@ const uint8_t cy_m0p_image[] = { 0x39u, 0x00u, 0x28u, 0x00u, 0x08u, 0x23u, 0x02u, 0xf0u, 0x45u, 0xfeu, 0x02u, 0x9bu, 0x04u, 0x9au, 0x28u, 0x00u, 0x01u, 0x97u, 0x00u, 0x96u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa1u, 0xffu, 0x28u, 0x00u, 0x08u, 0x23u, 0x32u, 0x00u, 0x05u, 0x99u, 0x02u, 0xf0u, 0x37u, 0xfeu, 0x20u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, - 0x38u, 0x71u, 0x00u, 0x10u, 0xfdu, 0xffu, 0xceu, 0xffu, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x89u, 0xb0u, + 0x60u, 0x71u, 0x00u, 0x10u, 0xfdu, 0xffu, 0xceu, 0xffu, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x89u, 0xb0u, 0x07u, 0x93u, 0x25u, 0x4bu, 0x04u, 0x00u, 0x1bu, 0x68u, 0x06u, 0x91u, 0x04u, 0x92u, 0x03u, 0x93u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x03u, 0x93u, 0x00u, 0x27u, 0x1fu, 0x4bu, 0x04u, 0x9du, 0xfeu, 0x00u, 0xf6u, 0x18u, 0x2bu, 0x00u, 0x10u, 0x33u, 0x05u, 0x93u, 0x08u, 0x23u, 0x32u, 0x00u, 0x29u, 0x00u, @@ -314,7 +314,7 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x08u, 0x23u, 0x02u, 0xf0u, 0xf6u, 0xfdu, 0x03u, 0x9fu, 0x03u, 0x9bu, 0x08u, 0x37u, 0x01u, 0x93u, 0x06u, 0x9au, 0x33u, 0x00u, 0x20u, 0x00u, 0x00u, 0x97u, 0x01u, 0x21u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x3au, 0x00u, 0x07u, 0x99u, 0x02u, 0xf0u, 0xe5u, 0xfdu, 0x28u, 0x00u, 0x09u, 0xb0u, 0xf0u, 0xbdu, - 0x08u, 0x35u, 0xcau, 0xe7u, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x38u, 0x71u, 0x00u, 0x10u, + 0x08u, 0x35u, 0xcau, 0xe7u, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x60u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, 0x70u, 0xb5u, 0x0fu, 0x26u, 0x0bu, 0x4bu, 0x1bu, 0x68u, 0x9cu, 0x68u, 0x05u, 0x19u, 0x2cu, 0x68u, 0x34u, 0x40u, 0x04u, 0x2cu, 0xfbu, 0xd8u, 0x86u, 0x25u, 0x6du, 0x01u, 0x44u, 0x59u, 0x00u, 0x2cu, 0xfcu, 0xdbu, 0xdcu, 0x68u, 0x05u, 0x4du, 0x04u, 0x19u, 0x25u, 0x60u, 0xdcu, 0x68u, 0x04u, 0x19u, 0x21u, 0x60u, @@ -335,7 +335,7 @@ const uint8_t cy_m0p_image[] = { 0x39u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbeu, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa0u, 0xffu, 0x01u, 0x99u, 0x20u, 0x00u, 0x4bu, 0x1eu, 0x99u, 0x41u, 0x52u, 0x31u, 0xffu, 0xf7u, 0x87u, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x01u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0x93u, 0xffu, 0x28u, 0x00u, - 0xfeu, 0xbdu, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xc0u, 0x46u, 0xb8u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, + 0xfeu, 0xbdu, 0x02u, 0x4du, 0xd4u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x27u, 0x85u, 0xb0u, 0x02u, 0x91u, 0x00u, 0x92u, 0x03u, 0x93u, 0x26u, 0x4bu, 0x00u, 0x9du, 0xfeu, 0x00u, 0xf6u, 0x18u, 0x2bu, 0x00u, 0x10u, 0x33u, 0x01u, 0x93u, 0x08u, 0x23u, 0x32u, 0x00u, 0x29u, 0x00u, 0x20u, 0x00u, 0x02u, 0xf0u, 0x68u, 0xfeu, 0x00u, 0x28u, 0x04u, 0xd0u, 0x01u, 0x9bu, 0x9du, 0x42u, @@ -346,15 +346,15 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0xffu, 0xf7u, 0x67u, 0xffu, 0x08u, 0x23u, 0x20u, 0x00u, 0x1au, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x49u, 0xffu, 0x02u, 0x99u, 0x20u, 0x00u, 0x4bu, 0x1eu, 0x99u, 0x41u, 0x54u, 0x31u, 0xffu, 0xf7u, 0x30u, 0xffu, 0x20u, 0x00u, 0x08u, 0x23u, 0x01u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0x3cu, 0xffu, 0x28u, 0x00u, 0x05u, 0xb0u, - 0xf0u, 0xbdu, 0x08u, 0x35u, 0xbau, 0xe7u, 0xc0u, 0x46u, 0xb8u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, + 0xf0u, 0xbdu, 0x08u, 0x35u, 0xbau, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x71u, 0x00u, 0x10u, 0x03u, 0x00u, 0x31u, 0x00u, 0x42u, 0x1eu, 0x03u, 0x00u, 0x00u, 0x20u, 0x04u, 0x2au, 0x03u, 0xd8u, 0x28u, 0x30u, 0x58u, 0x43u, 0x01u, 0x4bu, - 0xc0u, 0x18u, 0x70u, 0x47u, 0x38u, 0x72u, 0x00u, 0x10u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, + 0xc0u, 0x18u, 0x70u, 0x47u, 0x60u, 0x72u, 0x00u, 0x10u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, + 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xf2u, 0xf9u, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, - 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xdfu, 0xf9u, 0x10u, 0xbdu, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x02u, 0xf0u, 0xdfu, 0xf9u, 0x10u, 0xbdu, 0xdcu, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0xadu, 0xb0u, 0x04u, 0x00u, 0x04u, 0x91u, 0x05u, 0x92u, 0x03u, 0x93u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x15u, 0xe1u, 0x03u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x11u, 0xe1u, 0x32u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x0du, 0xe1u, 0x33u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x09u, 0xe1u, 0x32u, 0x9bu, 0x58u, 0x78u, 0xffu, 0xf7u, @@ -392,7 +392,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x28u, 0x00u, 0xd0u, 0x71u, 0xe7u, 0x03u, 0x9bu, 0xe9u, 0x1du, 0xc9u, 0x08u, 0x59u, 0x18u, 0x0au, 0x22u, 0x2bu, 0x00u, 0x20u, 0x00u, 0x04u, 0xf0u, 0xc4u, 0xf8u, 0x68u, 0xe7u, 0x08u, 0x4eu, 0x6bu, 0xe7u, 0x07u, 0x4eu, 0x6eu, 0xe7u, 0x07u, 0x4eu, 0x6cu, 0xe7u, 0xc0u, 0x46u, 0x09u, 0x80u, 0x00u, 0x00u, 0x01u, 0x00u, 0x32u, 0x00u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0xb0u, 0xb0u, 0x00u, 0x00u, 0x0bu, 0x80u, 0x00u, 0x00u, 0x0bu, 0x00u, 0x32u, 0x00u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0xb0u, 0xb0u, 0x00u, 0x00u, 0x0bu, 0x80u, 0x00u, 0x00u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x0au, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x04u, 0x00u, 0x0fu, 0x1eu, 0x04u, 0x92u, 0x03u, 0x93u, 0x00u, 0xd1u, 0x8bu, 0xe1u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x88u, 0xe1u, 0x0cu, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x84u, 0xe1u, 0x0du, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x80u, 0xe1u, 0x58u, 0x78u, 0xffu, 0xf7u, 0x78u, 0xfeu, @@ -444,11 +444,11 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x21u, 0x20u, 0x00u, 0x03u, 0xf0u, 0x7au, 0xffu, 0x00u, 0x28u, 0x09u, 0xd0u, 0x01u, 0x23u, 0x0cu, 0x9au, 0x13u, 0x70u, 0x0eu, 0x49u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x27u, 0xfdu, 0x38u, 0x00u, 0x07u, 0xb0u, 0xf0u, 0xbdu, 0x0cu, 0x9bu, 0x18u, 0x70u, 0xf5u, 0xe7u, 0x04u, 0x4fu, 0x09u, 0x49u, 0xf3u, 0xe7u, 0x02u, 0x4fu, 0xf4u, 0xe7u, - 0x08u, 0x4fu, 0xf2u, 0xe7u, 0xf5u, 0xffu, 0xcdu, 0xffu, 0x0bu, 0x00u, 0x32u, 0x00u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x08u, 0x4fu, 0xf2u, 0xe7u, 0xf5u, 0xffu, 0xcdu, 0xffu, 0x0bu, 0x00u, 0x32u, 0x00u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x80u, 0x80u, 0x00u, 0x00u, 0x08u, 0x60u, 0x00u, 0x00u, 0x06u, 0x80u, 0x00u, 0x00u, 0xf1u, 0x7eu, 0x00u, 0x00u, 0x30u, 0x60u, 0x00u, 0x00u, 0x0au, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, - 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xefu, 0xfeu, 0x10u, 0xbdu, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xefu, 0xfeu, 0x10u, 0xbdu, 0xdcu, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0x85u, 0xb0u, 0x08u, 0x00u, 0x02u, 0x91u, 0x03u, 0x92u, 0x1eu, 0x00u, 0xffu, 0xf7u, 0xc7u, 0xfcu, 0x07u, 0x1eu, 0x00u, 0xd1u, 0x7bu, 0xe0u, 0x03u, 0x9bu, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x77u, 0xe0u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0x74u, 0xe0u, 0x73u, 0x68u, 0x00u, 0x2bu, 0x00u, 0xd1u, 0x70u, 0xe0u, 0xb3u, 0x68u, @@ -473,24 +473,24 @@ const uint8_t cy_m0p_image[] = { 0x10u, 0xbdu, 0x00u, 0x00u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x02u, 0x4bu, 0x1bu, 0x68u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x02u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x20u, 0x68u, 0x10u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0au, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u, 0x25u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x0fu, 0xfeu, 0x10u, 0xbdu, 0x0fu, 0x23u, 0x13u, 0x43u, - 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, + 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x05u, 0xd8u, 0x05u, 0x4bu, 0x21u, 0x22u, 0x00u, 0x21u, - 0x01u, 0xf0u, 0xfau, 0xfdu, 0x10u, 0xbdu, 0x03u, 0x4bu, 0xf8u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x01u, 0xf0u, 0xfau, 0xfdu, 0x10u, 0xbdu, 0x03u, 0x4bu, 0xf8u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xc0u, 0xc0u, 0x00u, 0x00u, 0xcfu, 0xc0u, 0x00u, 0x00u, 0x00u, 0x23u, 0x10u, 0xb5u, 0x10u, 0x22u, 0x19u, 0x00u, 0x01u, 0xf0u, 0xeau, 0xfdu, 0x10u, 0xbdu, 0x09u, 0x03u, 0x0bu, 0x00u, 0x13u, 0x43u, 0x00u, 0x22u, 0x10u, 0xb5u, 0x11u, 0x00u, 0x01u, 0xf0u, 0xe1u, 0xfdu, 0x10u, 0xbdu, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, - 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xcfu, 0xfdu, 0x10u, 0xbdu, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xcfu, 0xfdu, 0x10u, 0xbdu, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, - 0x01u, 0xf0u, 0xbau, 0xfdu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x14u, 0x00u, + 0x01u, 0xf0u, 0xbau, 0xfdu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x14u, 0x00u, 0x07u, 0x4au, 0x15u, 0x68u, 0x24u, 0x22u, 0x29u, 0x35u, 0x2du, 0x78u, 0x1fu, 0x2du, 0x00u, 0xd9u, 0x01u, 0x3au, 0x24u, 0x01u, 0x23u, 0x43u, 0x09u, 0x03u, 0x0bu, 0x43u, 0x00u, 0x21u, 0x01u, 0xf0u, 0xa5u, 0xfdu, 0x70u, 0xbdu, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x9cu, 0xfdu, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0x01u, 0xf0u, 0x9cu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x23u, 0x10u, 0xb5u, 0x11u, 0x22u, 0x19u, 0x00u, 0x01u, 0xf0u, 0x95u, 0xfdu, 0x10u, 0xbdu, 0x70u, 0xb5u, 0x04u, 0x00u, 0x1bu, 0x4du, 0xffu, 0xf7u, 0x9fu, 0xffu, 0x20u, 0x00u, 0x01u, 0x22u, 0x02u, 0x21u, 0xffu, 0xf7u, 0xa1u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x03u, 0x21u, 0xffu, 0xf7u, 0x9cu, 0xffu, 0x2au, 0x00u, @@ -523,7 +523,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x70u, 0xfeu, 0x94u, 0x4bu, 0x1bu, 0x78u, 0x00u, 0x2bu, 0x0bu, 0xd0u, 0x01u, 0x2bu, 0x01u, 0xd1u, 0x00u, 0xf0u, 0x35u, 0xfdu, 0x0eu, 0x9bu, 0x00u, 0x22u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x50u, 0xffu, 0x00u, 0xf0u, 0x24u, 0xfdu, 0x8du, 0x4bu, 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0x01u, 0xd9u, 0x00u, 0xf0u, - 0x1du, 0xfdu, 0x04u, 0xf0u, 0x27u, 0xffu, 0x05u, 0x00u, 0x89u, 0x00u, 0x25u, 0x01u, 0x73u, 0x03u, 0x18u, 0x05u, + 0x1du, 0xfdu, 0x04u, 0xf0u, 0x39u, 0xffu, 0x05u, 0x00u, 0x89u, 0x00u, 0x25u, 0x01u, 0x73u, 0x03u, 0x18u, 0x05u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa1u, 0xfeu, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa3u, 0xfeu, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x9eu, 0xfeu, 0x80u, 0x22u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa2u, 0xfeu, 0xc0u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x9du, 0xfeu, 0xc0u, 0x22u, @@ -688,7 +688,7 @@ const uint8_t cy_m0p_image[] = { 0x8bu, 0xffu, 0x00u, 0x21u, 0x44u, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x85u, 0xffu, 0xe0u, 0x21u, 0x49u, 0x00u, 0xffu, 0xf7u, 0x69u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xeau, 0xf9u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd8u, 0xf9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xdcu, 0xf9u, 0x09u, 0xb0u, 0xf0u, 0xbdu, 0x42u, 0x4bu, - 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0xf1u, 0xd8u, 0x04u, 0xf0u, 0xf2u, 0xf9u, 0x05u, 0x00u, 0x84u, 0x00u, + 0x18u, 0x78u, 0x01u, 0x38u, 0x04u, 0x28u, 0xf1u, 0xd8u, 0x04u, 0xf0u, 0x04u, 0xfau, 0x05u, 0x00u, 0x84u, 0x00u, 0xd1u, 0x00u, 0xc7u, 0x01u, 0xedu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x76u, 0xf9u, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x78u, 0xf9u, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x73u, 0xf9u, 0x02u, 0x22u, 0x00u, 0x21u, 0xffu, 0x32u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x76u, 0xf9u, 0x80u, 0x22u, 0x01u, 0x21u, @@ -715,7 +715,7 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0xb0u, 0xfeu, 0x00u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0x01u, 0x23u, 0xffu, 0xf7u, 0x5du, 0xf8u, 0x20u, 0x00u, 0x03u, 0x23u, 0x00u, 0x22u, 0x01u, 0x21u, 0xffu, 0xf7u, 0xeeu, 0xf8u, 0x01u, 0x23u, 0x00u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x3eu, 0xf8u, 0x7fu, 0xe7u, 0x1cu, 0x22u, - 0xb3u, 0x49u, 0x01u, 0xa8u, 0x04u, 0xf0u, 0xf2u, 0xfau, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa5u, 0xf8u, 0x01u, 0x22u, + 0xb3u, 0x49u, 0x01u, 0xa8u, 0x04u, 0xf0u, 0x04u, 0xfbu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa5u, 0xf8u, 0x01u, 0x22u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa7u, 0xf8u, 0x00u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa2u, 0xf8u, 0xe0u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa6u, 0xf8u, 0xf0u, 0x22u, 0x00u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xa0u, 0xf8u, 0x80u, 0x22u, 0x01u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, @@ -746,7 +746,7 @@ const uint8_t cy_m0p_image[] = { 0x03u, 0x23u, 0x00u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x69u, 0xffu, 0x3eu, 0x23u, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xb0u, 0xfdu, 0x00u, 0x21u, 0x3eu, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0xaau, 0xfdu, 0x23u, 0x21u, 0xffu, 0xf7u, 0x8fu, 0xf9u, 0x39u, 0x49u, 0x11u, 0x22u, 0x1cu, 0x31u, - 0x01u, 0xa8u, 0x04u, 0xf0u, 0xfbu, 0xf9u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xaeu, 0xffu, 0x01u, 0x22u, 0x04u, 0x21u, + 0x01u, 0xa8u, 0x04u, 0xf0u, 0x0du, 0xfau, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xaeu, 0xffu, 0x01u, 0x22u, 0x04u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xb0u, 0xffu, 0x00u, 0x22u, 0x05u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xabu, 0xffu, 0x31u, 0x4au, 0x00u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xafu, 0xffu, 0xf0u, 0x22u, 0x01u, 0x21u, 0x52u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xa9u, 0xffu, 0x81u, 0x22u, 0x06u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xa4u, 0xffu, @@ -760,7 +760,7 @@ const uint8_t cy_m0p_image[] = { 0x4bu, 0xfdu, 0x04u, 0x23u, 0x00u, 0x22u, 0x19u, 0x00u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xf8u, 0xfeu, 0x4eu, 0x23u, 0x3du, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x3fu, 0xfdu, 0x00u, 0x21u, 0x07u, 0x4bu, 0x37u, 0x22u, 0x20u, 0x00u, 0x00u, 0xf0u, 0x39u, 0xfdu, 0x43u, 0x21u, 0xffu, 0xf7u, 0x1eu, 0xf9u, 0x12u, 0x10u, 0x00u, 0x00u, - 0x2du, 0x78u, 0x00u, 0x10u, 0x3eu, 0x30u, 0x30u, 0x00u, 0x01u, 0x02u, 0x00u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, + 0x55u, 0x78u, 0x00u, 0x10u, 0x3eu, 0x30u, 0x30u, 0x00u, 0x01u, 0x02u, 0x00u, 0x00u, 0x4eu, 0x40u, 0x30u, 0x00u, 0x70u, 0xb5u, 0x0cu, 0x00u, 0x05u, 0x00u, 0xfeu, 0xf7u, 0xdau, 0xfeu, 0x09u, 0x4bu, 0x26u, 0x01u, 0x33u, 0x43u, 0x28u, 0x00u, 0x3du, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0x1fu, 0xfdu, 0x24u, 0x03u, 0x05u, 0x4bu, 0x34u, 0x43u, 0x28u, 0x00u, 0x23u, 0x43u, 0x37u, 0x22u, 0x00u, 0x21u, 0x00u, 0xf0u, 0x16u, 0xfdu, 0x70u, 0xbdu, 0xc0u, 0x46u, @@ -772,7 +772,7 @@ const uint8_t cy_m0p_image[] = { 0xebu, 0xfcu, 0x0bu, 0x4bu, 0x2du, 0x03u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x07u, 0xd8u, 0x2bu, 0x00u, 0x26u, 0x22u, 0x3bu, 0x43u, 0x30u, 0x00u, 0x00u, 0x21u, 0x00u, 0xf0u, 0xddu, 0xfcu, 0xf8u, 0xbdu, 0x0fu, 0x23u, 0x2bu, 0x43u, 0x3bu, 0x43u, 0x25u, 0x22u, 0xf5u, 0xe7u, 0xc0u, 0x46u, 0x0eu, 0x00u, 0x80u, 0x00u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x07u, 0xb5u, 0x00u, 0x93u, 0x13u, 0x00u, 0xfeu, 0xf7u, 0xf5u, 0xffu, 0x07u, 0xbdu, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x07u, 0xb5u, 0x00u, 0x93u, 0x13u, 0x00u, 0xfeu, 0xf7u, 0xf5u, 0xffu, 0x07u, 0xbdu, 0xf8u, 0xb5u, 0x04u, 0x00u, 0x17u, 0x00u, 0x1eu, 0x00u, 0x0du, 0x00u, 0xfeu, 0xf7u, 0xd5u, 0xfeu, 0x3au, 0x00u, 0x07u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xd7u, 0xfeu, 0x32u, 0x00u, 0x08u, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xd2u, 0xfeu, 0x2au, 0x00u, 0x0bu, 0x21u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0xcdu, 0xfeu, 0x06u, 0x9au, 0x09u, 0x21u, @@ -867,7 +867,7 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x90u, 0x08u, 0x22u, 0x00u, 0x97u, 0x07u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xd0u, 0xfeu, 0x01u, 0x22u, 0x05u, 0x9bu, 0x13u, 0x42u, 0x0au, 0xd0u, 0x0bu, 0x23u, 0x01u, 0x93u, 0x01u, 0x3bu, 0x00u, 0x93u, 0x02u, 0x97u, 0x01u, 0x3bu, 0x07u, 0x32u, 0x07u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x0eu, 0xfeu, 0x01u, 0x35u, 0xcdu, 0xe7u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0xc5u, 0x60u, 0x00u, 0x00u, 0xc6u, 0xc0u, 0x00u, 0x00u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0xc5u, 0x60u, 0x00u, 0x00u, 0xc6u, 0xc0u, 0x00u, 0x00u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x80u, 0x22u, 0x0du, 0x4bu, 0x52u, 0x00u, 0x90u, 0x42u, 0x11u, 0xd0u, 0x07u, 0xd8u, 0x01u, 0x22u, 0xc0u, 0x28u, 0x0eu, 0xd0u, 0x02u, 0x22u, 0xe0u, 0x28u, 0x0bu, 0xd0u, 0x00u, 0x22u, 0x09u, 0xe0u, 0xc0u, 0x22u, 0x52u, 0x00u, 0x90u, 0x42u, 0x07u, 0xd0u, 0x05u, 0x4au, 0x90u, 0x42u, 0xf6u, 0xd1u, 0x05u, 0x22u, 0x00u, 0xe0u, 0x03u, 0x22u, @@ -876,7 +876,7 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x98u, 0x00u, 0x90u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x2fu, 0xffu, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x62u, 0xfbu, 0x13u, 0xbdu, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x93u, 0xb0u, 0x05u, 0x93u, 0x1au, 0xabu, 0x1cu, 0x78u, 0x65u, 0x4bu, 0x05u, 0x00u, 0x1bu, 0x68u, 0x03u, 0x91u, 0x04u, 0x92u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, - 0x1eu, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x06u, 0xa8u, 0x03u, 0xf0u, 0xf1u, 0xfdu, 0x33u, 0x00u, 0x81u, 0x33u, + 0x1eu, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x06u, 0xa8u, 0x03u, 0xf0u, 0x03u, 0xfeu, 0x33u, 0x00u, 0x81u, 0x33u, 0x22u, 0x00u, 0xffu, 0x33u, 0x06u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0xfcu, 0xfbu, 0x04u, 0x1eu, 0x00u, 0xd0u, 0x86u, 0xe0u, 0x33u, 0x00u, 0x80u, 0x33u, 0x01u, 0x93u, 0x98u, 0x23u, 0x01u, 0x9au, 0xdbu, 0x00u, 0x77u, 0x1cu, 0xf6u, 0x50u, 0xffu, 0x37u, 0xf3u, 0x18u, 0x5au, 0x60u, 0x9fu, 0x60u, 0x19u, 0x9au, 0x09u, 0x9bu, 0x9au, 0x42u, @@ -902,8 +902,8 @@ const uint8_t cy_m0p_image[] = { 0x86u, 0xe7u, 0xfau, 0x5cu, 0x01u, 0x9cu, 0x4au, 0x40u, 0xf2u, 0x54u, 0xfau, 0x5cu, 0x42u, 0x40u, 0xe2u, 0x54u, 0x01u, 0x33u, 0x80u, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x66u, 0x4cu, 0x05u, 0x00u, 0xa5u, 0x44u, 0x04u, 0x92u, 0x93u, 0x22u, 0x05u, 0x93u, 0x13u, 0xaeu, 0xaeu, 0xabu, 0x1cu, 0x78u, 0x03u, 0x91u, 0x92u, 0x00u, - 0x00u, 0x21u, 0x30u, 0x00u, 0x03u, 0xf0u, 0x23u, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x07u, 0xa8u, 0x03u, 0xf0u, - 0x1eu, 0xfdu, 0x22u, 0x00u, 0x73u, 0xabu, 0x07u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x77u, 0xfdu, 0x04u, 0x1eu, + 0x00u, 0x21u, 0x30u, 0x00u, 0x03u, 0xf0u, 0x35u, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x07u, 0xa8u, 0x03u, 0xf0u, + 0x30u, 0xfdu, 0x22u, 0x00u, 0x73u, 0xabu, 0x07u, 0xa9u, 0x28u, 0x00u, 0x01u, 0xf0u, 0x77u, 0xfdu, 0x04u, 0x1eu, 0x3bu, 0xd1u, 0x90u, 0x23u, 0x9bu, 0x00u, 0xf6u, 0x50u, 0x33u, 0xaau, 0x04u, 0x33u, 0xf2u, 0x50u, 0x0au, 0x9fu, 0x04u, 0x33u, 0x53u, 0xaau, 0xf2u, 0x50u, 0x10u, 0x9bu, 0xbeu, 0xb2u, 0x01u, 0x93u, 0x02u, 0x00u, 0x33u, 0x00u, 0x53u, 0xa9u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x6eu, 0xfcu, 0xadu, 0x9bu, 0xbbu, 0x42u, 0x2eu, 0xd9u, 0x07u, 0xa9u, @@ -934,9 +934,9 @@ const uint8_t cy_m0p_image[] = { 0x52u, 0x02u, 0xc3u, 0x18u, 0x19u, 0x68u, 0x11u, 0x42u, 0xfcu, 0xd0u, 0x23u, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0xf7u, 0xbdu, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xd0u, 0x03u, 0x00u, 0x08u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, - 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xb0u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xb0u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x22u, 0x0eu, 0x21u, 0xffu, 0xf7u, 0xe4u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0du, 0x21u, 0xffu, 0xf7u, 0xdfu, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0cu, 0x21u, 0xffu, 0xf7u, 0xdau, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0bu, 0x21u, 0xffu, 0xf7u, 0xd5u, 0xffu, 0x20u, 0x00u, 0x00u, 0x22u, 0x0au, 0x21u, @@ -949,7 +949,7 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x9eu, 0xffu, 0x03u, 0x4bu, 0x0fu, 0x21u, 0x1au, 0x68u, 0x20u, 0x00u, 0x92u, 0x08u, 0xffu, 0xf7u, 0x97u, 0xffu, 0x10u, 0xbdu, 0xd4u, 0x03u, 0x00u, 0x08u, 0x05u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x04u, 0x4bu, 0x1fu, 0x2au, 0x00u, 0xd9u, 0x04u, 0x4bu, 0x04u, 0x4au, 0x13u, 0x60u, - 0x70u, 0x47u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x5cu, 0x78u, 0x00u, 0x10u, 0xb0u, 0x78u, 0x00u, 0x10u, + 0x70u, 0x47u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x84u, 0x78u, 0x00u, 0x10u, 0xd8u, 0x78u, 0x00u, 0x10u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x2fu, 0x4bu, 0x70u, 0xb5u, 0x14u, 0x00u, 0x1au, 0x68u, 0x00u, 0x2au, 0x2cu, 0xd0u, 0x00u, 0x29u, 0x09u, 0xd1u, 0x00u, 0x2cu, 0x28u, 0xd1u, 0x13u, 0x6du, 0xc1u, 0x18u, 0x2au, 0x4bu, 0x1bu, 0x68u, 0x9cu, 0x6cu, 0x00u, 0x29u, 0x21u, 0xd0u, 0xa4u, 0x00u, 0x28u, 0x4bu, 0x65u, 0x1eu, 0x9du, 0x42u, 0x1cu, 0xd8u, @@ -962,7 +962,7 @@ const uint8_t cy_m0p_image[] = { 0xebu, 0xd1u, 0x1fu, 0x2eu, 0x02u, 0xd9u, 0x10u, 0x4du, 0x1bu, 0x02u, 0x43u, 0x51u, 0x93u, 0x6bu, 0xa2u, 0x08u, 0xc3u, 0x18u, 0x19u, 0x60u, 0x0fu, 0x21u, 0xffu, 0xf7u, 0x2du, 0xffu, 0x00u, 0x20u, 0x0bu, 0x4bu, 0x1cu, 0x60u, 0x70u, 0xbdu, 0x7cu, 0x23u, 0xe4u, 0xe7u, 0x78u, 0x23u, 0xe2u, 0xe7u, 0x60u, 0x23u, 0xe0u, 0xe7u, 0x40u, 0x23u, - 0xdeu, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xffu, 0x7fu, 0x00u, 0x00u, + 0xdeu, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xffu, 0x7fu, 0x00u, 0x00u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xffu, 0x3fu, 0x00u, 0x00u, 0x88u, 0x14u, 0x00u, 0x00u, 0xd4u, 0x03u, 0x00u, 0x08u, 0x20u, 0x4bu, 0x21u, 0x49u, 0x1bu, 0x68u, 0x09u, 0x68u, 0x9au, 0x6cu, 0x92u, 0x00u, 0x00u, 0x29u, 0x1cu, 0xd0u, 0x1eu, 0x49u, 0x09u, 0x68u, 0x00u, 0x29u, 0x18u, 0xd0u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x2fu, 0xd9u, @@ -972,18 +972,18 @@ const uint8_t cy_m0p_image[] = { 0x13u, 0xd0u, 0x7fu, 0x2bu, 0xf9u, 0xd1u, 0x80u, 0x22u, 0x52u, 0x00u, 0xf6u, 0xe7u, 0x80u, 0x22u, 0xd2u, 0x01u, 0xf3u, 0xe7u, 0x80u, 0x22u, 0x92u, 0x01u, 0xf0u, 0xe7u, 0x80u, 0x22u, 0x52u, 0x01u, 0xedu, 0xe7u, 0x80u, 0x22u, 0x12u, 0x01u, 0xeau, 0xe7u, 0x80u, 0x22u, 0xd2u, 0x00u, 0xe7u, 0xe7u, 0x80u, 0x22u, 0x92u, 0x00u, 0xe4u, 0xe7u, - 0x0au, 0x00u, 0xe2u, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xd4u, 0x03u, 0x00u, 0x08u, + 0x0au, 0x00u, 0xe2u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xd4u, 0x03u, 0x00u, 0x08u, 0x88u, 0x14u, 0x00u, 0x00u, 0x10u, 0xb5u, 0x04u, 0x00u, 0xffu, 0xf7u, 0x30u, 0xffu, 0x17u, 0x4au, 0x18u, 0x49u, 0x13u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x17u, 0xd8u, 0x16u, 0x4bu, 0x23u, 0x60u, 0x01u, 0x20u, 0x09u, 0x68u, 0x4bu, 0x6bu, 0xe3u, 0x18u, 0x18u, 0x60u, 0x13u, 0x4bu, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x13u, 0x68u, 0x09u, 0x6du, 0x9au, 0x6cu, 0x61u, 0x18u, 0x92u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x2au, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0xbdu, 0xfeu, 0x00u, 0x20u, 0x10u, 0xbdu, 0x23u, 0x68u, 0x0bu, 0x48u, 0x03u, 0x40u, 0x23u, 0x60u, 0x0bu, 0x68u, 0x0au, 0x48u, 0x5bu, 0x68u, 0xe3u, 0x18u, 0x18u, 0x60u, 0x80u, 0x23u, 0x20u, 0x68u, - 0x1bu, 0x06u, 0x03u, 0x43u, 0x23u, 0x60u, 0x03u, 0x23u, 0xa3u, 0x60u, 0xd8u, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x1bu, 0x06u, 0x03u, 0x43u, 0x23u, 0x60u, 0x03u, 0x23u, 0xa3u, 0x60u, 0xd8u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x03u, 0x00u, 0x00u, 0x80u, 0xd4u, 0x03u, 0x00u, 0x08u, 0xffu, 0xffu, 0xfeu, 0x7fu, 0x01u, 0x00u, 0x02u, 0x00u, 0x03u, 0x23u, 0x03u, 0x70u, 0x00u, 0x20u, 0x70u, 0x47u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x00u, 0x23u, 0x03u, 0x60u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x20u, 0x03u, 0x4bu, - 0x18u, 0x60u, 0x70u, 0x47u, 0x83u, 0x60u, 0xf9u, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xd4u, 0x03u, 0x00u, 0x08u, + 0x18u, 0x60u, 0x70u, 0x47u, 0x83u, 0x60u, 0xf9u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd4u, 0x03u, 0x00u, 0x08u, 0x30u, 0xb5u, 0x01u, 0x29u, 0x0bu, 0xd9u, 0x01u, 0x22u, 0x0au, 0x40u, 0x54u, 0x42u, 0x62u, 0x41u, 0xcbu, 0x0fu, 0x5bu, 0x18u, 0x5bu, 0x10u, 0x9bu, 0x1au, 0x02u, 0x00u, 0x01u, 0x39u, 0x8bu, 0x42u, 0x00u, 0xdbu, 0x30u, 0xbdu, 0x14u, 0x78u, 0x45u, 0x5cu, 0x15u, 0x70u, 0x44u, 0x54u, 0x01u, 0x32u, 0x01u, 0x39u, 0xf5u, 0xe7u, 0x00u, 0x00u, @@ -1085,25 +1085,25 @@ const uint8_t cy_m0p_image[] = { 0x19u, 0x68u, 0x0bu, 0x68u, 0xc3u, 0x18u, 0x1cu, 0x68u, 0x00u, 0x2cu, 0xfcu, 0xdbu, 0x8bu, 0x69u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x20u, 0x13u, 0x60u, 0x10u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x24u, 0x68u, 0x29u, 0x34u, 0x24u, 0x78u, 0x1fu, 0x2cu, 0x02u, 0xd8u, 0xffu, 0xf7u, 0x05u, 0xfeu, 0x10u, 0xbdu, - 0xffu, 0xf7u, 0x12u, 0xffu, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, + 0xffu, 0xf7u, 0x12u, 0xffu, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, - 0xfau, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, + 0xfau, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u, 0x29u, 0x34u, 0x22u, 0x78u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x22u, 0xffu, 0xf7u, - 0xbfu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x22u, 0xffu, 0xf7u, 0xadu, 0xfeu, 0xfau, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0xbfu, 0xfdu, 0x10u, 0xbdu, 0x00u, 0x22u, 0xffu, 0xf7u, 0xadu, 0xfeu, 0xfau, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x03u, 0x34u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xd6u, 0xfau, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x0au, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u, 0x25u, 0x22u, 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xc5u, 0xfau, 0x10u, 0xbdu, - 0x0fu, 0x23u, 0x13u, 0x43u, 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x0fu, 0x23u, 0x13u, 0x43u, 0x0bu, 0x43u, 0x24u, 0x22u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x09u, 0x4bu, 0x09u, 0x03u, 0x1bu, 0x68u, 0x12u, 0x01u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x06u, 0xd8u, 0x13u, 0x00u, 0x0bu, 0x43u, 0x21u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xadu, 0xfau, 0x10u, 0xbdu, - 0x0fu, 0x23u, 0x13u, 0x43u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, + 0x0fu, 0x23u, 0x13u, 0x43u, 0xf6u, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x0bu, 0x00u, 0x13u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xa0u, 0xfau, 0x10u, 0xbdu, 0x00u, 0x00u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x07u, 0x4au, 0x12u, 0x68u, 0x29u, 0x32u, 0x14u, 0x78u, 0x0cu, 0x22u, 0x1fu, 0x2cu, 0x00u, 0xd9u, 0x04u, 0x32u, 0x91u, 0x40u, 0x01u, 0x3bu, 0x0bu, 0x43u, 0x12u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x8du, 0xfau, 0x10u, 0xbdu, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x1fu, 0x24u, 0x08u, 0x4bu, 0x89u, 0x06u, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x9cu, 0x42u, 0xa4u, 0x41u, 0x13u, 0x00u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa3u, 0x40u, 0x80u, 0x22u, - 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x78u, 0xfau, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x0bu, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x78u, 0xfau, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x1du, 0x00u, 0x5eu, 0x1cu, 0x01u, 0x92u, 0x0fu, 0x00u, 0x32u, 0x00u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xccu, 0xffu, 0x32u, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc7u, 0xffu, 0x32u, 0x00u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc2u, 0xffu, 0x2au, 0x00u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, @@ -1116,7 +1116,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x2au, 0xfau, 0x0du, 0x4bu, 0x03u, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x24u, 0xfau, 0x33u, 0x00u, 0x3au, 0x22u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xfau, 0x00u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x5du, 0xffu, 0x02u, 0x22u, 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x40u, 0xffu, - 0x01u, 0x3du, 0xd9u, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x02u, 0x00u, 0x30u, 0x00u, 0x01u, 0x00u, 0x30u, 0x00u, + 0x01u, 0x3du, 0xd9u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x02u, 0x00u, 0x30u, 0x00u, 0x01u, 0x00u, 0x30u, 0x00u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x08u, 0x9eu, 0x00u, 0x91u, 0x15u, 0x00u, 0x01u, 0x21u, 0x72u, 0x1cu, 0x77u, 0x00u, 0x01u, 0x93u, 0xffu, 0xf7u, 0x63u, 0xffu, 0x3au, 0x00u, 0x02u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x5eu, 0xffu, 0x3au, 0x00u, 0x03u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x59u, 0xffu, 0x32u, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, @@ -1138,7 +1138,7 @@ const uint8_t cy_m0p_image[] = { 0x7bu, 0xf9u, 0x20u, 0x00u, 0x10u, 0x4bu, 0x03u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0x75u, 0xf9u, 0x00u, 0x9bu, 0x20u, 0x00u, 0x1au, 0x03u, 0x02u, 0x23u, 0x00u, 0x21u, 0x13u, 0x43u, 0x30u, 0x22u, 0xffu, 0xf7u, 0x6cu, 0xf9u, 0x0eu, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xc2u, 0xfeu, 0xf7u, 0xbdu, 0xc0u, 0x46u, 0x3au, 0x10u, 0x00u, 0x00u, - 0x18u, 0x20u, 0x00u, 0x00u, 0x23u, 0x20u, 0x00u, 0x00u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x20u, 0x20u, 0x00u, 0x00u, + 0x18u, 0x20u, 0x00u, 0x00u, 0x23u, 0x20u, 0x00u, 0x00u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x20u, 0x20u, 0x00u, 0x00u, 0x10u, 0x10u, 0x00u, 0x00u, 0x21u, 0x30u, 0x00u, 0x00u, 0x23u, 0x00u, 0x30u, 0x00u, 0x28u, 0x30u, 0x00u, 0x00u, 0xf7u, 0xb5u, 0x06u, 0x00u, 0x1cu, 0x00u, 0x09u, 0x9bu, 0x01u, 0x91u, 0x5fu, 0x00u, 0x15u, 0x00u, 0x02u, 0x21u, 0x3au, 0x00u, 0xffu, 0xf7u, 0xabu, 0xfeu, 0x3au, 0x00u, 0x03u, 0x21u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xa6u, 0xfeu, @@ -1156,7 +1156,7 @@ const uint8_t cy_m0p_image[] = { 0xebu, 0xf8u, 0x01u, 0x9bu, 0x30u, 0x00u, 0x1cu, 0x03u, 0x0du, 0x4bu, 0x30u, 0x22u, 0x23u, 0x43u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xe2u, 0xf8u, 0xc0u, 0x23u, 0x9bu, 0x03u, 0x30u, 0x00u, 0x23u, 0x43u, 0x30u, 0x22u, 0x00u, 0x21u, 0xffu, 0xf7u, 0xdau, 0xf8u, 0x30u, 0x00u, 0x03u, 0x21u, 0xffu, 0xf7u, 0x30u, 0xfeu, 0xf7u, 0xbdu, 0xc0u, 0x46u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x20u, 0x30u, 0x00u, 0x00u, 0x30u, 0x20u, 0x00u, 0x00u, 0x10u, 0x00u, 0x40u, 0x00u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x20u, 0x30u, 0x00u, 0x00u, 0x30u, 0x20u, 0x00u, 0x00u, 0x10u, 0x00u, 0x40u, 0x00u, 0x01u, 0x00u, 0x40u, 0x00u, 0xf8u, 0xb5u, 0x1du, 0x00u, 0x00u, 0x23u, 0x16u, 0x00u, 0x0fu, 0x00u, 0x10u, 0x22u, 0x19u, 0x00u, 0x04u, 0x00u, 0xffu, 0xf7u, 0xc0u, 0xf8u, 0xe0u, 0x23u, 0x00u, 0x22u, 0x1bu, 0x02u, 0x11u, 0x00u, 0x3bu, 0x43u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xb8u, 0xf8u, 0x90u, 0x23u, 0x00u, 0x22u, 0x1bu, 0x02u, 0x33u, 0x43u, @@ -1179,7 +1179,7 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x11u, 0x00u, 0xffu, 0xf7u, 0x5cu, 0xfdu, 0x33u, 0x68u, 0x2cu, 0x22u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x00u, 0xd9u, 0x04u, 0x3au, 0x0eu, 0x4bu, 0xa8u, 0xe7u, 0x0eu, 0x4bu, 0x25u, 0x22u, 0xeau, 0xe7u, 0xe0u, 0x21u, 0x20u, 0x00u, 0x89u, 0x01u, 0xffu, 0xf7u, 0x79u, 0xfdu, 0x00u, 0x23u, 0x11u, 0x22u, 0x19u, 0x00u, - 0x20u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xf8u, 0xf8u, 0xbdu, 0xe0u, 0x05u, 0x00u, 0x08u, 0x0au, 0xb0u, 0x00u, 0x00u, + 0x20u, 0x00u, 0xffu, 0xf7u, 0x19u, 0xf8u, 0xf8u, 0xbdu, 0xdcu, 0x05u, 0x00u, 0x08u, 0x0au, 0xb0u, 0x00u, 0x00u, 0x09u, 0xc0u, 0x00u, 0x00u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0xd0u, 0x00u, 0x00u, 0xd0u, 0xd0u, 0x00u, 0x00u, 0x0au, 0xe0u, 0x00u, 0x00u, 0xdfu, 0xd0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x06u, 0x00u, 0x0fu, 0x00u, 0x02u, 0x93u, 0x0au, 0x9du, 0x0bu, 0x98u, 0x06u, 0x2au, 0x37u, 0xd8u, 0x21u, 0x4bu, 0x91u, 0x00u, 0xc9u, 0x58u, @@ -1191,7 +1191,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x28u, 0x12u, 0xd1u, 0x00u, 0x9au, 0xa3u, 0xb2u, 0xaau, 0x18u, 0x02u, 0x99u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb5u, 0xfcu, 0x00u, 0x28u, 0x09u, 0xd1u, 0x38u, 0x70u, 0x07u, 0xe0u, 0x00u, 0x24u, 0x23u, 0x00u, 0x21u, 0x00u, 0xcau, 0xe7u, 0x01u, 0x30u, 0x42u, 0x78u, 0xffu, 0x2au, 0xe0u, 0xd0u, 0x00u, 0x20u, 0x05u, 0xb0u, 0xf0u, 0xbdu, - 0x04u, 0x79u, 0x00u, 0x10u, 0x27u, 0x79u, 0x00u, 0x10u, 0x20u, 0x79u, 0x00u, 0x10u, 0xf0u, 0xb5u, 0x8bu, 0xb0u, + 0x2cu, 0x79u, 0x00u, 0x10u, 0x4fu, 0x79u, 0x00u, 0x10u, 0x48u, 0x79u, 0x00u, 0x10u, 0xf0u, 0xb5u, 0x8bu, 0xb0u, 0x09u, 0x93u, 0x8bu, 0x68u, 0x04u, 0x00u, 0x05u, 0x93u, 0xcbu, 0x68u, 0x08u, 0x92u, 0x06u, 0x93u, 0x0bu, 0x68u, 0x4fu, 0x68u, 0x07u, 0x93u, 0x0bu, 0x69u, 0x8du, 0x69u, 0x03u, 0x93u, 0x4bu, 0x69u, 0x04u, 0x93u, 0xb3u, 0x4bu, 0x1bu, 0x68u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1eu, 0x68u, 0x20u, 0x00u, 0xffu, 0xf7u, @@ -1241,7 +1241,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0x3cu, 0xfbu, 0x00u, 0x97u, 0x05u, 0x23u, 0xe9u, 0xe7u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x06u, 0x60u, 0x00u, 0x00u, 0x05u, 0x50u, 0x00u, 0x00u, 0x07u, 0x70u, 0x00u, 0x00u, 0x08u, 0x80u, 0x00u, 0x00u, 0x09u, 0xa0u, 0x00u, 0x00u, 0x0au, 0xc0u, 0x00u, 0x00u, 0x0bu, 0x50u, 0x00u, 0x00u, 0x07u, 0xb0u, 0x00u, 0x00u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0xb9u, 0xe0u, 0x00u, 0x00u, 0xbeu, 0xb0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x0bu, 0x69u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0xb9u, 0xe0u, 0x00u, 0x00u, 0xbeu, 0xb0u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x0bu, 0x69u, 0x87u, 0xb0u, 0x03u, 0x93u, 0x4bu, 0x69u, 0x04u, 0x00u, 0x04u, 0x93u, 0x8bu, 0x69u, 0x0fu, 0x68u, 0x05u, 0x93u, 0x34u, 0x4bu, 0x4du, 0x68u, 0x1bu, 0x68u, 0x1eu, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1eu, 0x68u, 0x20u, 0x00u, 0xfeu, 0xf7u, 0x3du, 0xffu, 0x31u, 0x00u, 0x82u, 0xb2u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x1eu, 0xfbu, @@ -1262,7 +1262,7 @@ const uint8_t cy_m0p_image[] = { 0x20u, 0x00u, 0x04u, 0x3bu, 0x00u, 0x22u, 0x4cu, 0x21u, 0xffu, 0xf7u, 0x36u, 0xf8u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xe4u, 0x18u, 0x04u, 0x23u, 0x22u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x13u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, 0x00u, 0xd9u, 0x80u, 0xe0u, 0x10u, 0x00u, 0x8bu, 0x60u, - 0x1au, 0x00u, 0x01u, 0xf0u, 0xfbu, 0xffu, 0x04u, 0x16u, 0x29u, 0x3au, 0x4du, 0x6cu, 0x5cu, 0x00u, 0x54u, 0x33u, + 0x1au, 0x00u, 0x02u, 0xf0u, 0x0du, 0xf8u, 0x04u, 0x16u, 0x29u, 0x3au, 0x4du, 0x6cu, 0x5cu, 0x00u, 0x54u, 0x33u, 0x8bu, 0x61u, 0x3cu, 0x4bu, 0x00u, 0x20u, 0xcbu, 0x62u, 0x40u, 0x23u, 0xcbu, 0x60u, 0x2cu, 0x3bu, 0x4bu, 0x61u, 0x4bu, 0x62u, 0x2du, 0x33u, 0x40u, 0x32u, 0xffu, 0x33u, 0x0au, 0x61u, 0x08u, 0x60u, 0x48u, 0x60u, 0xcbu, 0x61u, 0x00u, 0xbdu, 0x60u, 0x33u, 0x8bu, 0x61u, 0x01u, 0x23u, 0x0bu, 0x60u, 0x4bu, 0x60u, 0x32u, 0x4bu, 0x40u, 0x32u, @@ -1278,8 +1278,8 @@ const uint8_t cy_m0p_image[] = { 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x0au, 0x61u, 0x24u, 0x3bu, 0xdcu, 0xe7u, 0xc0u, 0x33u, 0x8bu, 0x61u, 0x05u, 0x23u, 0x0bu, 0x60u, 0x03u, 0x3bu, 0x4bu, 0x60u, 0x0cu, 0x4bu, 0x80u, 0x32u, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x0au, 0x61u, 0x20u, 0x3bu, 0xccu, 0xe7u, 0x08u, 0x48u, - 0x96u, 0xe7u, 0xc0u, 0x46u, 0xb0u, 0x79u, 0x00u, 0x10u, 0xc4u, 0x79u, 0x00u, 0x10u, 0xe4u, 0x79u, 0x00u, 0x10u, - 0x04u, 0x7au, 0x00u, 0x10u, 0x44u, 0x7au, 0x00u, 0x10u, 0x84u, 0x7au, 0x00u, 0x10u, 0xc4u, 0x7au, 0x00u, 0x10u, + 0x96u, 0xe7u, 0xc0u, 0x46u, 0xd8u, 0x79u, 0x00u, 0x10u, 0xecu, 0x79u, 0x00u, 0x10u, 0x0cu, 0x7au, 0x00u, 0x10u, + 0x2cu, 0x7au, 0x00u, 0x10u, 0x6cu, 0x7au, 0x00u, 0x10u, 0xacu, 0x7au, 0x00u, 0x10u, 0xecu, 0x7au, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, 0x10u, 0xbdu, 0x00u, 0x24u, 0x4bu, 0x69u, 0x8cu, 0x62u, 0x0cu, 0x62u, 0xa3u, 0x42u, 0xf7u, 0xd0u, 0xcau, 0x6au, 0x9bu, 0xb2u, 0x09u, 0x69u, 0xfeu, 0xf7u, 0xa0u, 0xffu, 0x20u, 0x00u, 0xf1u, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf7u, 0xb5u, 0x07u, 0x00u, @@ -1309,7 +1309,7 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x20u, 0x70u, 0xbdu, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x8fu, 0xb0u, 0x01u, 0x93u, 0x14u, 0xabu, 0x1fu, 0x78u, 0x19u, 0x4bu, 0x04u, 0x00u, 0x1bu, 0x68u, 0x00u, 0x91u, 0x16u, 0x00u, 0x1du, 0x1eu, 0x02u, 0xd0u, 0x9bu, 0x6bu, 0xc3u, 0x18u, 0x1du, 0x68u, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, - 0x02u, 0xf0u, 0x6du, 0xf8u, 0x2bu, 0x00u, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, + 0x02u, 0xf0u, 0x7fu, 0xf8u, 0x2bu, 0x00u, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, 0x00u, 0x28u, 0x18u, 0xd1u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x0cu, 0xffu, 0x00u, 0x28u, 0x12u, 0xd1u, 0x33u, 0x00u, 0x00u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x18u, 0xffu, 0x00u, 0x28u, 0x0au, 0xd1u, 0x01u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x00u, 0x28u, 0x03u, 0xd1u, 0x02u, 0xa9u, @@ -1335,7 +1335,7 @@ const uint8_t cy_m0p_image[] = { 0xd0u, 0x03u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x0du, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x68u, 0xffu, 0x06u, 0x28u, 0xfau, 0xd8u, 0xceu, 0x21u, 0x04u, 0x4bu, 0xc9u, 0x05u, 0x1bu, 0x68u, 0x29u, 0x43u, 0xdbu, 0x68u, 0xe4u, 0x18u, 0x21u, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x00u, 0xb5u, 0x06u, 0x2au, - 0x68u, 0xd8u, 0x10u, 0x00u, 0x8bu, 0x60u, 0x01u, 0xf0u, 0xb1u, 0xfdu, 0x04u, 0x1fu, 0x12u, 0x3bu, 0x2fu, 0x49u, + 0x68u, 0xd8u, 0x10u, 0x00u, 0x8bu, 0x60u, 0x01u, 0xf0u, 0xc3u, 0xfdu, 0x04u, 0x1fu, 0x12u, 0x3bu, 0x2fu, 0x49u, 0x57u, 0x00u, 0x40u, 0x33u, 0x0bu, 0x61u, 0x69u, 0x23u, 0x4bu, 0x60u, 0x2fu, 0x4bu, 0x00u, 0x20u, 0xcbu, 0x62u, 0x40u, 0x23u, 0xcbu, 0x60u, 0x2cu, 0x3bu, 0x08u, 0x60u, 0x4bu, 0x61u, 0x4bu, 0x62u, 0x00u, 0xbdu, 0x40u, 0x33u, 0x0bu, 0x61u, 0x02u, 0x23u, 0x0bu, 0x60u, 0x68u, 0x33u, 0x4bu, 0x60u, 0x28u, 0x4bu, 0xcbu, 0x62u, 0x40u, 0x23u, @@ -1348,9 +1348,9 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x23u, 0x0bu, 0x60u, 0x66u, 0x33u, 0x4bu, 0x60u, 0x10u, 0x4bu, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, 0x20u, 0x3bu, 0xd4u, 0xe7u, 0x80u, 0x33u, 0x0bu, 0x61u, 0x06u, 0x23u, 0x0bu, 0x60u, 0x65u, 0x33u, 0x4bu, 0x60u, 0x0au, 0x4bu, 0xcbu, 0x62u, 0x80u, 0x23u, 0xcbu, 0x60u, 0x40u, 0x3bu, 0x4bu, 0x61u, - 0x24u, 0x3bu, 0xc6u, 0xe7u, 0x07u, 0x48u, 0xa9u, 0xe7u, 0x04u, 0x7bu, 0x00u, 0x10u, 0x38u, 0x7bu, 0x00u, 0x10u, - 0x18u, 0x7bu, 0x00u, 0x10u, 0x98u, 0x7bu, 0x00u, 0x10u, 0x58u, 0x7bu, 0x00u, 0x10u, 0x18u, 0x7cu, 0x00u, 0x10u, - 0xd8u, 0x7bu, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, + 0x24u, 0x3bu, 0xc6u, 0xe7u, 0x07u, 0x48u, 0xa9u, 0xe7u, 0x2cu, 0x7bu, 0x00u, 0x10u, 0x60u, 0x7bu, 0x00u, 0x10u, + 0x40u, 0x7bu, 0x00u, 0x10u, 0xc0u, 0x7bu, 0x00u, 0x10u, 0x80u, 0x7bu, 0x00u, 0x10u, 0x40u, 0x7cu, 0x00u, 0x10u, + 0x00u, 0x7cu, 0x00u, 0x10u, 0x0bu, 0x00u, 0x32u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x29u, 0x01u, 0xd1u, 0x07u, 0x48u, 0x10u, 0xbdu, 0x00u, 0x24u, 0x4bu, 0x69u, 0x8cu, 0x62u, 0x0cu, 0x62u, 0xa3u, 0x42u, 0xf7u, 0xd0u, 0xcau, 0x6au, 0x9bu, 0xb2u, 0x09u, 0x69u, 0xfeu, 0xf7u, 0x40u, 0xfeu, 0x20u, 0x00u, 0xf1u, 0xe7u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x04u, 0x00u, 0x0du, 0x1eu, 0x03u, 0x92u, 0x01u, 0x93u, 0x00u, 0xd1u, 0x95u, 0xe0u, @@ -1397,7 +1397,7 @@ const uint8_t cy_m0p_image[] = { 0xffu, 0xf7u, 0xc0u, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x85u, 0xfdu, 0x00u, 0x20u, 0x70u, 0xbdu, 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x0bu, 0x00u, 0x32u, 0x00u, 0xf0u, 0xb5u, 0x04u, 0x00u, 0xbfu, 0xb0u, 0x01u, 0x93u, 0x44u, 0xabu, 0x1fu, 0x78u, 0x0du, 0x00u, 0x16u, 0x00u, 0x00u, 0x21u, 0xc0u, 0x22u, 0x0eu, 0xa8u, 0x01u, 0xf0u, - 0xaeu, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, 0x01u, 0xf0u, 0xa9u, 0xfdu, 0x0eu, 0xabu, 0x3au, 0x00u, + 0xc0u, 0xfdu, 0x30u, 0x22u, 0x00u, 0x21u, 0x02u, 0xa8u, 0x01u, 0xf0u, 0xbbu, 0xfdu, 0x0eu, 0xabu, 0x3au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x02u, 0xfeu, 0x00u, 0x28u, 0x18u, 0xd1u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x7au, 0xfeu, 0x00u, 0x28u, 0x12u, 0xd1u, 0x33u, 0x00u, 0x2au, 0x00u, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x86u, 0xfeu, 0x00u, 0x28u, 0x0au, 0xd1u, 0x01u, 0x9au, 0x02u, 0xa9u, 0x20u, 0x00u, 0xffu, 0xf7u, @@ -1422,15 +1422,15 @@ const uint8_t cy_m0p_image[] = { 0x1bu, 0x68u, 0x00u, 0x68u, 0x80u, 0x00u, 0x80u, 0x0cu, 0x80u, 0x00u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x24u, 0x68u, 0x29u, 0x34u, 0x24u, 0x78u, 0x1fu, 0x2cu, 0x02u, 0xd8u, 0xfeu, 0xf7u, 0x47u, 0xfbu, 0x10u, 0xbdu, 0xfeu, 0xf7u, 0x16u, 0xfcu, 0xfbu, 0xe7u, 0xc0u, 0x46u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x1fu, 0x24u, 0x95u, 0x00u, 0x13u, 0x05u, 0x09u, 0x4au, 0xadu, 0x0cu, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x70u, 0xb5u, 0x1fu, 0x24u, 0x95u, 0x00u, 0x13u, 0x05u, 0x09u, 0x4au, 0xadu, 0x0cu, 0x12u, 0x68u, 0x89u, 0x06u, 0x29u, 0x32u, 0x12u, 0x78u, 0x1bu, 0x0du, 0x94u, 0x42u, 0xa4u, 0x41u, 0x64u, 0x42u, 0x0cu, 0x34u, 0xa5u, 0x40u, 0x0bu, 0x43u, 0x2bu, 0x43u, 0x80u, 0x22u, 0x00u, 0x21u, 0xfeu, 0xf7u, 0x6cu, 0xf8u, - 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, + 0x70u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x04u, 0xd8u, 0x80u, 0x23u, 0x02u, 0x68u, 0x1au, 0x42u, 0xfcu, 0xd1u, 0x70u, 0x47u, 0x03u, 0x68u, 0x00u, 0x2bu, 0xfcu, 0xd1u, 0xfau, 0xe7u, 0xc0u, 0x46u, - 0xd0u, 0x03u, 0x00u, 0x08u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u, + 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x13u, 0x00u, 0x06u, 0x4au, 0x14u, 0x68u, 0x29u, 0x34u, 0x22u, 0x78u, 0x1fu, 0x2au, 0x03u, 0xd8u, 0x00u, 0x22u, 0xfeu, 0xf7u, 0x21u, 0xfbu, 0x10u, 0xbdu, - 0x00u, 0x22u, 0xfeu, 0xf7u, 0x0fu, 0xfcu, 0xfau, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u, + 0x00u, 0x22u, 0xfeu, 0xf7u, 0x0fu, 0xfcu, 0xfau, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xf7u, 0xb5u, 0x04u, 0x00u, 0x00u, 0x93u, 0x0eu, 0x00u, 0x01u, 0x92u, 0xffu, 0xf7u, 0xcfu, 0xffu, 0x1bu, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x2du, 0xd8u, 0x19u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x69u, 0xe3u, 0x18u, 0x1fu, 0x68u, 0x5du, 0x68u, 0x31u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x83u, 0xffu, 0x06u, 0x00u, 0x00u, 0x9au, 0x01u, 0x00u, @@ -1438,14 +1438,14 @@ const uint8_t cy_m0p_image[] = { 0x01u, 0x9au, 0x07u, 0x33u, 0xdbu, 0x08u, 0x9bu, 0xb2u, 0x31u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x82u, 0xffu, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x09u, 0xd8u, 0x3au, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x87u, 0xffu, 0x2au, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x82u, 0xffu, - 0xf7u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xd4u, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, + 0xf7u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xd4u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x85u, 0xb0u, 0x03u, 0x93u, 0x04u, 0x00u, 0x01u, 0x91u, 0x02u, 0x92u, 0xffu, 0xf7u, 0x8cu, 0xffu, 0x16u, 0x4eu, 0x33u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x23u, 0xd8u, 0x14u, 0x4bu, 0x1bu, 0x68u, 0x1bu, 0x69u, 0xe3u, 0x18u, 0x1fu, 0x68u, 0x5du, 0x68u, 0x02u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x40u, 0xffu, 0x03u, 0x9bu, 0x02u, 0x00u, 0x07u, 0x33u, 0xdbu, 0x08u, 0x9bu, 0xb2u, 0x01u, 0x99u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x49u, 0xffu, 0x33u, 0x68u, 0x29u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x09u, 0xd8u, 0x3au, 0x00u, 0x00u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4fu, 0xffu, 0x2au, 0x00u, 0x01u, 0x21u, 0x20u, 0x00u, 0xffu, 0xf7u, 0x4au, 0xffu, - 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xdeu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x05u, 0xb0u, 0xf0u, 0xbdu, 0x00u, 0x25u, 0x2fu, 0x00u, 0xdeu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, 0x0bu, 0x00u, 0x3fu, 0x22u, 0x00u, 0x21u, 0xfdu, 0xf7u, 0xbbu, 0xffu, 0x20u, 0x00u, 0xffu, 0xf7u, 0x50u, 0xffu, 0x03u, 0x4bu, 0x1bu, 0x68u, 0xdbu, 0x6bu, 0xe4u, 0x18u, 0x20u, 0x68u, 0x40u, 0x07u, 0xc0u, 0x0fu, 0x10u, 0xbdu, 0xd0u, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x04u, 0x00u, @@ -1462,23 +1462,23 @@ const uint8_t cy_m0p_image[] = { 0x18u, 0x68u, 0x14u, 0x68u, 0x43u, 0x6au, 0x22u, 0x6cu, 0x6du, 0x03u, 0x9au, 0x18u, 0x11u, 0x68u, 0x29u, 0x40u, 0x10u, 0xd0u, 0x11u, 0x60u, 0x22u, 0x6cu, 0x9bu, 0x18u, 0x1bu, 0x68u, 0x0au, 0x4bu, 0x1au, 0x68u, 0x53u, 0x1cu, 0xd9u, 0x7fu, 0x00u, 0x29u, 0x07u, 0xd1u, 0x41u, 0x6au, 0x08u, 0x6au, 0x49u, 0x6au, 0x50u, 0x62u, 0x91u, 0x62u, - 0x01u, 0x22u, 0xdau, 0x77u, 0x30u, 0xbdu, 0x00u, 0x22u, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x01u, 0x22u, 0xdau, 0x77u, 0x30u, 0xbdu, 0x00u, 0x22u, 0xfbu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x03u, 0x00u, 0x08u, 0x00u, 0x22u, 0x70u, 0xb5u, 0x04u, 0x00u, 0x03u, 0x68u, 0x0du, 0x00u, 0x0bu, 0x60u, 0x43u, 0x68u, 0x4bu, 0x60u, 0x83u, 0x69u, 0x8bu, 0x60u, 0xc3u, 0x69u, 0xcbu, 0x60u, 0x4bu, 0x1cu, 0xdau, 0x77u, 0x03u, 0x8cu, 0x0bu, 0x82u, 0x03u, 0x8du, 0x0bu, 0x83u, 0xfdu, 0xf7u, 0xceu, 0xffu, - 0xa1u, 0x69u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x20u, 0x49u, 0x20u, 0x00u, 0x20u, 0x30u, 0x00u, 0xf0u, 0x5cu, 0xfeu, + 0xa1u, 0x69u, 0x00u, 0x29u, 0x00u, 0xd1u, 0x20u, 0x49u, 0x20u, 0x00u, 0x20u, 0x30u, 0x00u, 0xf0u, 0x6eu, 0xfeu, 0x20u, 0x22u, 0xa3u, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x1au, 0x4au, 0x13u, 0x60u, 0x1au, 0x4eu, 0x63u, 0x68u, 0x32u, 0x68u, 0x80u, 0x33u, 0x12u, 0x6au, 0x5bu, 0x01u, 0x9bu, 0x18u, 0x80u, 0x22u, 0x21u, 0x68u, 0x52u, 0x02u, 0x8au, 0x40u, 0xe1u, 0x69u, 0x9au, 0x60u, - 0x00u, 0x29u, 0x00u, 0xd1u, 0x13u, 0x49u, 0x20u, 0x00u, 0x28u, 0x30u, 0x00u, 0xf0u, 0x3du, 0xfeu, 0x28u, 0x23u, + 0x00u, 0x29u, 0x00u, 0xd1u, 0x13u, 0x49u, 0x20u, 0x00u, 0x28u, 0x30u, 0x00u, 0xf0u, 0x4fu, 0xfeu, 0x28u, 0x23u, 0xe0u, 0x5eu, 0xffu, 0xf7u, 0x8bu, 0xffu, 0x28u, 0x22u, 0xa3u, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x08u, 0x4au, 0x13u, 0x60u, 0x0au, 0x4au, 0x33u, 0x68u, 0x12u, 0x68u, 0x5bu, 0x6au, 0x92u, 0x6cu, 0x00u, 0x20u, 0x9bu, 0x18u, 0xf8u, 0x22u, 0x52u, 0x03u, 0x1au, 0x60u, 0x06u, 0x4bu, 0x1du, 0x60u, 0x70u, 0xbdu, 0xc0u, 0x46u, 0xe1u, 0x5eu, 0x00u, 0x10u, 0x00u, 0xe1u, 0x00u, 0xe0u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x79u, 0x59u, 0x00u, 0x10u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x03u, 0x00u, 0x08u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x79u, 0x59u, 0x00u, 0x10u, 0xd0u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x03u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x07u, 0x4bu, 0x1bu, 0x68u, 0x29u, 0x33u, 0x1au, 0x78u, 0x06u, 0x4bu, 0x1fu, 0x2au, 0x04u, 0xd8u, 0x05u, 0x4au, 0x1au, 0x60u, 0xffu, 0xf7u, 0x90u, 0xffu, 0x10u, 0xbdu, 0x04u, 0x4au, 0xf9u, 0xe7u, 0xc0u, 0x46u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0xd8u, 0x03u, 0x00u, 0x08u, 0x58u, 0x7cu, 0x00u, 0x10u, 0xb0u, 0x7cu, 0x00u, 0x10u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0xd8u, 0x03u, 0x00u, 0x08u, 0x80u, 0x7cu, 0x00u, 0x10u, 0xd8u, 0x7cu, 0x00u, 0x10u, 0xf0u, 0xb5u, 0xb4u, 0x4bu, 0x85u, 0xb0u, 0x1cu, 0x68u, 0x00u, 0x2cu, 0x1eu, 0xd0u, 0xb2u, 0x4bu, 0xb3u, 0x4du, 0x63u, 0x60u, 0x2bu, 0x68u, 0x5fu, 0x6au, 0x23u, 0x78u, 0x01u, 0x2bu, 0x18u, 0xd1u, 0x38u, 0x00u, 0xfeu, 0xf7u, 0x21u, 0xf8u, 0x60u, 0x60u, 0x00u, 0x23u, 0xabu, 0x4au, 0xe1u, 0x69u, 0x13u, 0x60u, 0x2bu, 0x68u, 0x1au, 0x00u, @@ -1524,7 +1524,7 @@ const uint8_t cy_m0p_image[] = { 0x40u, 0x6au, 0x52u, 0x69u, 0xb0u, 0x47u, 0x99u, 0xe7u, 0x96u, 0x69u, 0xedu, 0xe7u, 0xd6u, 0x69u, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0xedu, 0xe6u, 0xa1u, 0x6au, 0x03u, 0x91u, 0x8bu, 0x6au, 0x02u, 0x93u, 0x4bu, 0x6au, 0x01u, 0x93u, 0x0bu, 0x6au, 0x00u, 0x93u, 0xcbu, 0x69u, 0x8au, 0x69u, 0x40u, 0x6au, 0x49u, 0x69u, 0xb0u, 0x47u, - 0x84u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x09u, 0x00u, 0x32u, 0x00u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x84u, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0x09u, 0x00u, 0x32u, 0x00u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xd0u, 0x03u, 0x00u, 0x08u, 0x0au, 0x00u, 0x32u, 0x00u, 0xd8u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x03u, 0x00u, 0x08u, 0x01u, 0x00u, 0x32u, 0x00u, 0x56u, 0x6au, 0x28u, 0x68u, 0x00u, 0x2eu, 0x00u, 0xd1u, 0xc9u, 0xe6u, 0xa1u, 0x6au, 0x0bu, 0x7bu, 0x00u, 0x93u, 0x8bu, 0x68u, 0x4au, 0x68u, 0x40u, 0x6au, 0x09u, 0x68u, 0xb0u, 0x47u, 0x65u, 0xe7u, @@ -1549,10 +1549,10 @@ const uint8_t cy_m0p_image[] = { 0x29u, 0x6au, 0x80u, 0x33u, 0x5bu, 0x01u, 0xcbu, 0x18u, 0xdeu, 0x68u, 0x82u, 0x40u, 0x36u, 0x0cu, 0xb2u, 0x42u, 0x11u, 0xd1u, 0x12u, 0x04u, 0x1au, 0x60u, 0xacu, 0x35u, 0x1bu, 0x68u, 0x2bu, 0x88u, 0x58u, 0x43u, 0x40u, 0x18u, 0x07u, 0x49u, 0x00u, 0xf0u, 0xb5u, 0xf8u, 0x00u, 0x28u, 0x05u, 0xd1u, 0x23u, 0x68u, 0x9bu, 0x68u, 0x00u, 0x2bu, - 0x01u, 0xd1u, 0xffu, 0xf7u, 0xcdu, 0xfdu, 0x70u, 0xbdu, 0xdcu, 0x03u, 0x00u, 0x08u, 0xe0u, 0x05u, 0x00u, 0x08u, - 0xe0u, 0x03u, 0x00u, 0x08u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x01u, 0xd1u, 0xffu, 0xf7u, 0xcdu, 0xfdu, 0x70u, 0xbdu, 0xdcu, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0xe0u, 0x03u, 0x00u, 0x08u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, 0x50u, 0x43u, 0xc0u, 0x18u, - 0x70u, 0x47u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, + 0x70u, 0x47u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, 0x40u, 0x28u, 0x2fu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x30u, 0xd0u, 0x10u, 0x28u, 0x28u, 0xd0u, 0x19u, 0x48u, 0x1eu, 0xe0u, 0x80u, 0x28u, 0x28u, 0xd0u, 0x80u, 0x23u, 0x5bu, 0x00u, 0x98u, 0x42u, 0xf7u, 0xd1u, 0x14u, 0x48u, 0x16u, 0xe0u, 0x15u, 0x4bu, 0x98u, 0x42u, 0x14u, 0xd0u, 0x08u, 0xd8u, 0xa0u, 0x23u, 0x1bu, 0x06u, 0x98u, 0x42u, @@ -1566,26 +1566,26 @@ const uint8_t cy_m0p_image[] = { 0x05u, 0x00u, 0x52u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x9au, 0xffu, 0x0au, 0x4bu, 0x1cu, 0x68u, 0x23u, 0x00u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x0au, 0xdbu, 0x07u, 0x4bu, 0x18u, 0x68u, 0xffu, 0xf7u, 0x99u, 0xffu, 0x01u, 0x22u, 0x63u, 0x68u, 0x9au, 0x60u, 0x9au, 0x68u, 0x00u, 0x2au, - 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, + 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0x89u, 0xb2u, 0x41u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u, 0xc2u, 0x60u, 0x81u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x00u, 0x8au, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, - 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x18u, 0x60u, 0x70u, 0x47u, 0xf8u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x12u, 0x4cu, 0x1fu, 0x00u, 0x24u, 0x68u, 0x1eu, 0x0au, 0x20u, 0x18u, 0xffu, 0x24u, 0x27u, 0x40u, 0x34u, 0x40u, 0x0fu, 0x4eu, 0x1bu, 0x0cu, 0x35u, 0x68u, 0x07u, 0x60u, 0x2eu, 0x6au, 0x44u, 0x60u, 0x83u, 0x60u, 0xacu, 0x35u, 0x2du, 0x88u, 0x80u, 0x34u, 0x6fu, 0x43u, 0x64u, 0x01u, 0x34u, 0x19u, 0xbfu, 0x19u, 0x1eu, 0x04u, 0x33u, 0x43u, 0x07u, 0x61u, 0x44u, 0x61u, 0xa3u, 0x60u, 0x00u, 0x23u, 0x83u, 0x61u, 0x05u, 0x9bu, 0xc2u, 0x61u, 0x01u, 0x62u, 0x00u, 0x2bu, 0x01u, 0xd0u, 0x1bu, 0x88u, - 0x83u, 0x81u, 0xf0u, 0xbdu, 0xf8u, 0x03u, 0x00u, 0x08u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x83u, 0x68u, + 0x83u, 0x81u, 0xf0u, 0xbdu, 0xf8u, 0x03u, 0x00u, 0x08u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x83u, 0x68u, 0x85u, 0xb0u, 0x02u, 0xadu, 0x2bu, 0x80u, 0x15u, 0x4bu, 0x02u, 0x68u, 0x1bu, 0x68u, 0x06u, 0x6au, 0x9bu, 0x8eu, 0x47u, 0x6au, 0x9bu, 0x18u, 0x6bu, 0x80u, 0x43u, 0x68u, 0x00u, 0x95u, 0x82u, 0x6au, 0xc1u, 0x6au, 0x04u, 0x00u, 0x03u, 0x93u, 0x03u, 0x69u, 0xc0u, 0x68u, 0xffu, 0xf7u, 0xbdu, 0xffu, 0x00u, 0x21u, 0x3bu, 0x00u, 0x0au, 0x00u, - 0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x21u, 0x6bu, 0x28u, 0x00u, 0x00u, 0xf0u, 0xb4u, 0xfau, + 0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x21u, 0x6bu, 0x28u, 0x00u, 0x00u, 0xf0u, 0xc6u, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, - 0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, + 0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, 0x26u, 0x68u, 0x69u, 0x43u, 0x34u, 0x18u, 0x25u, 0x69u, 0x01u, 0x93u, 0x71u, 0x18u, 0x00u, 0x2du, 0x19u, 0xd0u, 0x88u, 0x69u, 0x00u, 0x28u, 0x18u, 0xd1u, 0x2eu, 0x68u, 0x00u, 0x2eu, 0x15u, 0xdau, 0x67u, 0x68u, 0x01u, 0x24u, 0x26u, 0x00u, 0x4bu, 0x68u, @@ -1600,20 +1600,20 @@ const uint8_t cy_m0p_image[] = { 0x98u, 0x47u, 0x31u, 0x00u, 0x20u, 0x69u, 0xffu, 0xf7u, 0x0du, 0xffu, 0xadu, 0xb2u, 0x00u, 0x2du, 0x09u, 0xd0u, 0x63u, 0x69u, 0x1du, 0x60u, 0x00u, 0x25u, 0x1bu, 0x68u, 0x63u, 0x6au, 0xabu, 0x42u, 0x05u, 0xd0u, 0x98u, 0x47u, 0x65u, 0x62u, 0xa5u, 0x61u, 0x63u, 0x69u, 0x1bu, 0x68u, 0x73u, 0xbdu, 0xa3u, 0x6au, 0x00u, 0x2bu, 0xf8u, 0xd0u, - 0x98u, 0x47u, 0xf6u, 0xe7u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, + 0x98u, 0x47u, 0xf6u, 0xe7u, 0xdcu, 0x05u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, 0x10u, 0x68u, 0xc0u, 0x18u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xf8u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x19u, 0x4bu, 0x0fu, 0x00u, 0x1bu, 0x68u, 0x1au, 0x00u, 0x2eu, 0x32u, 0x12u, 0x78u, 0x82u, 0x42u, 0x27u, 0xd9u, 0x00u, 0x29u, 0x25u, 0xd0u, 0x1fu, 0x25u, 0x0au, 0x68u, 0x15u, 0x40u, 0x21u, 0xd1u, 0x19u, 0x00u, 0xacu, 0x31u, 0x0cu, 0x88u, 0x11u, 0x4eu, 0x60u, 0x43u, 0x1cu, 0x6au, 0xd2u, 0x08u, 0x04u, 0x19u, 0x29u, 0x00u, - 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0x2bu, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcau, 0xfeu, + 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0x3du, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcau, 0xfeu, 0x3au, 0x00u, 0x29u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xd7u, 0xfeu, 0x04u, 0x1eu, 0x07u, 0xd1u, 0x01u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xbfu, 0xfeu, 0x03u, 0x00u, 0x20u, 0x00u, 0x00u, 0x2bu, 0x00u, 0xd0u, 0x04u, 0x48u, - 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, 0xfcu, 0x03u, 0x00u, 0x08u, + 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, 0xfcu, 0x03u, 0x00u, 0x08u, 0x01u, 0x01u, 0x8au, 0x00u, 0x03u, 0x01u, 0x8au, 0x00u, 0x10u, 0xb5u, 0x00u, 0x2au, 0x0du, 0xd1u, 0x00u, 0x29u, 0x14u, 0xd1u, 0x0bu, 0x4bu, 0x1au, 0x68u, 0x13u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u, 0x58u, 0x43u, 0x13u, 0x6au, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x18u, 0x60u, 0x08u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x29u, 0x06u, 0xd0u, 0x06u, 0x4bu, 0x19u, 0x60u, 0x19u, 0x00u, 0x5au, 0x60u, 0xffu, 0xf7u, 0xabu, 0xffu, 0xf5u, 0xe7u, 0x03u, 0x48u, 0xf3u, 0xe7u, - 0xe0u, 0x05u, 0x00u, 0x08u, 0xfcu, 0x03u, 0x00u, 0x08u, 0x78u, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, + 0xdcu, 0x05u, 0x00u, 0x08u, 0xfcu, 0x03u, 0x00u, 0x08u, 0x78u, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, 0xf7u, 0xb5u, 0x18u, 0x4fu, 0x04u, 0x00u, 0x3bu, 0x68u, 0x01u, 0x91u, 0xdeu, 0x68u, 0x33u, 0x68u, 0x83u, 0x42u, 0x26u, 0xd9u, 0x00u, 0x25u, 0xa9u, 0x42u, 0x02u, 0xd1u, 0xf9u, 0xf7u, 0xc7u, 0xfeu, 0x05u, 0x00u, 0x38u, 0x68u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x1au, 0xdau, 0x1fu, 0x22u, 0x01u, 0x23u, 0x22u, 0x40u, 0x93u, 0x40u, 0x64u, 0x09u, @@ -1626,10 +1626,19 @@ const uint8_t cy_m0p_image[] = { 0x18u, 0x40u, 0x43u, 0x1eu, 0x98u, 0x41u, 0x03u, 0x4bu, 0xc0u, 0x18u, 0x70u, 0x47u, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xfcu, 0x03u, 0x00u, 0x08u, 0x00u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0xa6u, 0x22u, 0x05u, 0x49u, 0xd2u, 0x00u, 0x8bu, 0x58u, 0x02u, 0x20u, 0xdbu, 0x43u, 0x9bu, 0x07u, 0x02u, 0xd0u, 0x01u, 0x23u, 0x88u, 0x58u, - 0x18u, 0x40u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x09u, 0x4au, 0x83u, 0x00u, 0x9bu, 0x18u, 0xd0u, 0x22u, - 0x92u, 0x00u, 0x98u, 0x58u, 0x07u, 0x22u, 0x10u, 0x40u, 0x04u, 0x28u, 0x07u, 0xd1u, 0xc0u, 0x22u, 0x92u, 0x00u, - 0x98u, 0x58u, 0x1fu, 0x23u, 0x03u, 0x40u, 0x80u, 0x20u, 0x40u, 0x00u, 0x18u, 0x43u, 0x70u, 0x47u, 0xc0u, 0x46u, - 0x00u, 0x00u, 0x26u, 0x40u, 0xb0u, 0x23u, 0x15u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x10u, 0xb5u, 0x99u, 0x03u, + 0x18u, 0x40u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, 0xefu, 0xffu, 0x00u, 0x23u, + 0x02u, 0x28u, 0x01u, 0xd1u, 0x01u, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x04u, 0x00u, 0x08u, + 0x09u, 0x4au, 0x83u, 0x00u, 0x9bu, 0x18u, 0xd0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x07u, 0x22u, 0x10u, 0x40u, + 0x04u, 0x28u, 0x07u, 0xd1u, 0xc0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x1fu, 0x23u, 0x03u, 0x40u, 0x80u, 0x20u, + 0x40u, 0x00u, 0x18u, 0x43u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, + 0xe7u, 0xffu, 0x02u, 0x28u, 0x1cu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x14u, 0xd0u, 0x01u, 0x28u, 0x14u, 0xd0u, + 0x00u, 0x20u, 0x11u, 0xe0u, 0x12u, 0x23u, 0xffu, 0x33u, 0x98u, 0x42u, 0x14u, 0xd0u, 0x14u, 0x23u, 0xffu, 0x33u, + 0x98u, 0x42u, 0x18u, 0xd0u, 0x03u, 0x3bu, 0x98u, 0x42u, 0xf2u, 0xd1u, 0x0cu, 0x4au, 0x0cu, 0x4bu, 0xd0u, 0x58u, + 0xc0u, 0x0fu, 0xc0u, 0x03u, 0x00u, 0xe0u, 0x0bu, 0x48u, 0x10u, 0xbdu, 0x0bu, 0x4bu, 0x18u, 0x68u, 0xfbu, 0xe7u, + 0xffu, 0xf7u, 0xbau, 0xffu, 0xf8u, 0xe7u, 0x09u, 0x4bu, 0x18u, 0x69u, 0x04u, 0x23u, 0x18u, 0x40u, 0xf3u, 0xd0u, + 0x80u, 0x20u, 0x00u, 0x02u, 0xf0u, 0xe7u, 0x01u, 0x4au, 0x05u, 0x4bu, 0xe8u, 0xe7u, 0x00u, 0x00u, 0x26u, 0x40u, + 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x12u, 0x7au, 0x00u, 0x04u, 0x04u, 0x00u, 0x08u, 0x00u, 0x00u, 0x27u, 0x40u, + 0x3cu, 0x05u, 0x00u, 0x00u, 0xb0u, 0x23u, 0x15u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x10u, 0xb5u, 0x99u, 0x03u, 0xdbu, 0x01u, 0xdbu, 0x0fu, 0x89u, 0x0bu, 0xc3u, 0x71u, 0x11u, 0x4bu, 0x01u, 0x60u, 0xd3u, 0x58u, 0x0fu, 0x24u, 0xd9u, 0x04u, 0xdbu, 0x01u, 0xdbu, 0x0du, 0x03u, 0x81u, 0xb1u, 0x23u, 0xdbu, 0x00u, 0xd3u, 0x58u, 0xc9u, 0x0cu, 0x81u, 0x80u, 0x19u, 0x00u, 0x21u, 0x40u, 0x81u, 0x72u, 0x19u, 0x09u, 0x21u, 0x40u, 0xc1u, 0x72u, 0xd9u, 0x02u, @@ -1639,463 +1648,457 @@ const uint8_t cy_m0p_image[] = { 0x3bu, 0x33u, 0x1bu, 0x78u, 0x93u, 0x42u, 0x16u, 0xd9u, 0x7fu, 0x22u, 0x1fu, 0x24u, 0x80u, 0x30u, 0xffu, 0x30u, 0x0bu, 0x4bu, 0x80u, 0x00u, 0xc3u, 0x58u, 0x1au, 0x40u, 0x0au, 0x70u, 0x1au, 0x0cu, 0x22u, 0x40u, 0x18u, 0x0au, 0x8au, 0x70u, 0x1au, 0x01u, 0x20u, 0x40u, 0xe2u, 0x40u, 0x48u, 0x70u, 0x00u, 0x20u, 0x9bu, 0x00u, 0x9bu, 0x0fu, - 0xcau, 0x70u, 0x0bu, 0x71u, 0x10u, 0xbdu, 0x03u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xe0u, 0x05u, 0x00u, 0x08u, - 0x00u, 0x00u, 0x26u, 0x40u, 0x01u, 0x00u, 0x4au, 0x00u, 0xe0u, 0x22u, 0x01u, 0x21u, 0x4du, 0x4bu, 0x80u, 0x00u, - 0xc0u, 0x18u, 0x92u, 0x00u, 0x83u, 0x58u, 0xf0u, 0xb5u, 0x9bu, 0x06u, 0x9bu, 0x0fu, 0x99u, 0x40u, 0x0fu, 0x23u, - 0x84u, 0x58u, 0x89u, 0xb0u, 0x1cu, 0x40u, 0x20u, 0x00u, 0x01u, 0x91u, 0xffu, 0xf7u, 0x7du, 0xffu, 0x03u, 0x28u, - 0x54u, 0xd0u, 0x08u, 0xd8u, 0x01u, 0x28u, 0x13u, 0xd0u, 0x62u, 0xd9u, 0xffu, 0xf7u, 0x67u, 0xffu, 0x42u, 0x4bu, - 0x02u, 0x28u, 0x0bu, 0xd1u, 0x0du, 0xe0u, 0x12u, 0x23u, 0xffu, 0x33u, 0x98u, 0x42u, 0x50u, 0xd0u, 0x14u, 0x23u, - 0xffu, 0x33u, 0x98u, 0x42u, 0x51u, 0xd0u, 0x03u, 0x3bu, 0x98u, 0x42u, 0x41u, 0xd0u, 0x00u, 0x26u, 0x01u, 0xe0u, - 0x3au, 0x4bu, 0x1eu, 0x68u, 0x00u, 0x2cu, 0x4du, 0xd1u, 0x03u, 0xadu, 0x14u, 0x22u, 0x21u, 0x00u, 0x28u, 0x00u, - 0x00u, 0xf0u, 0xddu, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x6du, 0xffu, 0xb0u, 0x23u, 0x31u, 0x4au, 0xdbu, 0x00u, + 0xcau, 0x70u, 0x0bu, 0x71u, 0x10u, 0xbdu, 0x03u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xdcu, 0x05u, 0x00u, 0x08u, + 0x00u, 0x00u, 0x26u, 0x40u, 0x01u, 0x00u, 0x4au, 0x00u, 0xf0u, 0xb5u, 0x87u, 0xb0u, 0x04u, 0x00u, 0xffu, 0xf7u, + 0x65u, 0xffu, 0x06u, 0x00u, 0x00u, 0x2cu, 0x34u, 0xd1u, 0x01u, 0xadu, 0x14u, 0x22u, 0x21u, 0x00u, 0x28u, 0x00u, + 0x00u, 0xf0u, 0xcfu, 0xfdu, 0x28u, 0x00u, 0xffu, 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0xe7u, 0x17u, 0x4bu, 0x1bu, 0x68u, 0x3bu, 0x33u, 0x1bu, 0x78u, 0xa3u, 0x42u, 0xddu, 0xd3u, - 0x03u, 0xadu, 0x05u, 0x22u, 0x00u, 0x21u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x89u, 0xfdu, 0x20u, 0x00u, 0x29u, 0x00u, - 0x80u, 0x34u, 0xffu, 0xf7u, 0x49u, 0xffu, 0xffu, 0x34u, 0x06u, 0x4bu, 0xa4u, 0x00u, 0xe3u, 0x58u, 0x00u, 0x24u, - 0xa3u, 0x42u, 0x03u, 0xdau, 0x2cu, 0x79u, 0x02u, 0x3cu, 0x63u, 0x1eu, 0x9cu, 0x41u, 0x2fu, 0x78u, 0x68u, 0x78u, - 0xaau, 0x78u, 0xaau, 0xe7u, 0x00u, 0x00u, 0x26u, 0x40u, 0x00u, 0x04u, 0x00u, 0x08u, 0x04u, 0x04u, 0x00u, 0x08u, - 0x5cu, 0x04u, 0x00u, 0x08u, 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x00u, 0x27u, 0x40u, 0x3cu, 0x05u, 0x00u, 0x00u, - 0x00u, 0x12u, 0x7au, 0x00u, 0xe0u, 0x05u, 0x00u, 0x08u, 0x14u, 0x4bu, 0x30u, 0xb5u, 0x1au, 0x68u, 0x07u, 0x24u, - 0x13u, 0x00u, 0x28u, 0x33u, 0x1bu, 0x78u, 0x1fu, 0x2bu, 0x15u, 0xd8u, 0x83u, 0x08u, 0x1du, 0x00u, 0xa5u, 0x43u, - 0x2cu, 0x1eu, 0x0fu, 0xd1u, 0x03u, 0x34u, 0x20u, 0x40u, 0xa0u, 0x40u, 0x81u, 0x40u, 0x12u, 0x68u, 0x9bu, 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0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xe3u, 0x00u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x05u, 0x60u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xdbu, 0x00u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, }; #endif /* defined(CY_DEVICE_PSOC6A512K) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_01_cm0p_sleep.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_01_cm0p_sleep.c index 7d326e39cc6..e1204782e9b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_01_cm0p_sleep.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_01_cm0p_sleep.c @@ -41,21 +41,21 @@ const uint8_t cy_m0p_image[] = { 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x89u, 0x01u, 0x00u, 0x10u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0xf8u, 0x03u, 0x00u, 0x08u, - 0x00u, 0x00u, 0x00u, 0x00u, 0xc8u, 0x14u, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, + 0x00u, 0x00u, 0x00u, 0x00u, 0xf0u, 0x14u, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xfcu, 0x03u, 0x00u, 0x08u, 0xc8u, 0x14u, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, + 0xfcu, 0x03u, 0x00u, 0x08u, 0xf0u, 0x14u, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, 0x02u, 0x38u, 0xfcu, 0xd1u, 0xc0u, 0x46u, 0xc0u, 0x46u, 0x70u, 0x47u, 0xefu, 0xf3u, 0x10u, 0x80u, 0x72u, 0xb6u, 0x70u, 0x47u, 0x80u, 0xf3u, 0x10u, 0x88u, 0x70u, 0x47u, 0x70u, 0x47u, 0xffu, 0xf7u, 0xfdu, 0xffu, 0x72u, 0xb6u, 0x0fu, 0x4cu, 0x10u, 0x4du, 0xacu, 0x42u, 0x09u, 0xdau, 0x21u, 0x68u, 0x62u, 0x68u, 0xa3u, 0x68u, 0x04u, 0x3bu, 0x02u, 0xdbu, 0xc8u, 0x58u, 0xd0u, 0x50u, 0xfau, 0xe7u, 0x0cu, 0x34u, 0xf3u, 0xe7u, 0x0au, 0x49u, 0x0bu, 0x4au, 0x00u, 0x20u, 0x52u, 0x1au, 0x02u, 0xddu, 0x04u, 0x3au, 0x88u, 0x50u, 0xfcu, 0xdcu, 0x08u, 0x48u, 0x09u, 0x49u, - 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x00u, 0xf0u, 0xb9u, 0xfeu, 0x00u, 0xf0u, 0x63u, 0xfeu, 0xfeu, 0xe7u, - 0xd4u, 0x14u, 0x00u, 0x10u, 0xecu, 0x14u, 0x00u, 0x10u, 0xf8u, 0x03u, 0x00u, 0x08u, 0x10u, 0x06u, 0x00u, 0x08u, + 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x00u, 0xf0u, 0xcfu, 0xfeu, 0x00u, 0xf0u, 0x79u, 0xfeu, 0xfeu, 0xe7u, + 0xfcu, 0x14u, 0x00u, 0x10u, 0x14u, 0x15u, 0x00u, 0x10u, 0xf8u, 0x03u, 0x00u, 0x08u, 0x14u, 0x06u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x08u, 0x08u, 0xedu, 0x00u, 0xe0u, 0xfeu, 0xe7u, 0xfeu, 0xe7u, 0x00u, 0xb5u, 0x04u, 0x20u, 0x71u, 0x46u, 0x08u, 0x42u, 0x02u, 0xd0u, 0xefu, 0xf3u, 0x09u, 0x80u, 0x01u, 0xe0u, 0xefu, 0xf3u, 0x08u, 0x80u, - 0x04u, 0x30u, 0x00u, 0xf0u, 0x55u, 0xfcu, 0xfeu, 0xe7u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, - 0x0cu, 0x06u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, - 0x50u, 0x43u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x0cu, 0x06u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, + 0x04u, 0x30u, 0x00u, 0xf0u, 0x6bu, 0xfcu, 0xfeu, 0xe7u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, + 0x10u, 0x06u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, + 0x50u, 0x43u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x10u, 0x06u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, 0x40u, 0x28u, 0x2fu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x30u, 0xd0u, 0x10u, 0x28u, 0x28u, 0xd0u, 0x19u, 0x48u, 0x1eu, 0xe0u, 0x80u, 0x28u, 0x28u, 0xd0u, 0x80u, 0x23u, 0x5bu, 0x00u, 0x98u, 0x42u, 0xf7u, 0xd1u, 0x14u, 0x48u, 0x16u, 0xe0u, 0x15u, 0x4bu, 0x98u, 0x42u, 0x14u, 0xd0u, 0x08u, 0xd8u, 0xa0u, 0x23u, @@ -69,33 +69,33 @@ const uint8_t cy_m0p_image[] = { 0x02u, 0x00u, 0x50u, 0x00u, 0x05u, 0x00u, 0x52u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x9au, 0xffu, 0x0au, 0x4bu, 0x1cu, 0x68u, 0x23u, 0x00u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x0au, 0xdbu, 0x07u, 0x4bu, 0x18u, 0x68u, 0xffu, 0xf7u, 0x99u, 0xffu, 0x01u, 0x22u, 0x63u, 0x68u, 0x9au, 0x60u, - 0x9au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x0cu, 0x06u, 0x00u, 0x08u, + 0x9au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x10u, 0x06u, 0x00u, 0x08u, 0x14u, 0x04u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x0du, 0x4bu, 0x10u, 0xb5u, 0x18u, 0x60u, 0x00u, 0x28u, 0x04u, 0xd0u, 0xfeu, 0x23u, 0x5bu, 0x42u, 0x03u, 0x80u, 0x00u, 0x23u, 0x43u, 0x80u, 0x09u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0x4cu, 0x32u, 0x12u, 0x78u, 0x00u, 0x2au, 0x08u, 0xd0u, 0x4du, 0x33u, 0x1bu, 0x78u, 0x00u, 0x2bu, 0x04u, 0xd0u, 0x02u, 0x22u, 0x04u, 0x49u, 0x00u, 0x20u, 0x00u, 0xf0u, 0xe0u, 0xf8u, 0x10u, 0xbdu, 0xc0u, 0x46u, - 0x24u, 0x04u, 0x00u, 0x08u, 0x0cu, 0x06u, 0x00u, 0x08u, 0x49u, 0x01u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x02u, 0x48u, + 0x24u, 0x04u, 0x00u, 0x08u, 0x10u, 0x06u, 0x00u, 0x08u, 0x45u, 0x01u, 0x00u, 0x08u, 0x10u, 0xb5u, 0x02u, 0x48u, 0xffu, 0xf7u, 0xdau, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xb8u, 0x03u, 0x00u, 0x08u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0x89u, 0xb2u, 0x41u, 0x60u, - 0x00u, 0x20u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, 0x0cu, 0x06u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, + 0x00u, 0x20u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, 0x10u, 0x06u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u, 0xc2u, 0x60u, 0x81u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x00u, 0x8au, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, - 0x01u, 0x48u, 0xfcu, 0xe7u, 0x0cu, 0x06u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, + 0x01u, 0x48u, 0xfcu, 0xe7u, 0x10u, 0x06u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x18u, 0x60u, 0x70u, 0x47u, 0x28u, 0x04u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x15u, 0x4cu, 0x1fu, 0x00u, 0x24u, 0x68u, 0x1du, 0x0au, 0x20u, 0x18u, 0xffu, 0x24u, 0x25u, 0x40u, 0x27u, 0x40u, 0x12u, 0x4cu, 0x1bu, 0x0cu, 0x26u, 0x68u, 0x07u, 0x60u, 0x34u, 0x6au, 0x45u, 0x60u, 0x83u, 0x60u, 0xacu, 0x36u, 0x36u, 0x88u, 0x77u, 0x43u, 0x3fu, 0x19u, 0x07u, 0x61u, 0x2fu, 0x00u, 0x80u, 0x37u, 0x6du, 0x01u, 0x7fu, 0x01u, 0xe7u, 0x19u, 0x64u, 0x19u, 0x0au, 0x4du, 0x47u, 0x61u, 0x1fu, 0x04u, 0x3bu, 0x43u, 0x64u, 0x19u, 0x23u, 0x60u, 0x00u, 0x23u, 0x83u, 0x61u, 0x05u, 0x9bu, 0xc2u, 0x61u, 0x01u, 0x62u, 0x00u, 0x2bu, 0x01u, 0xd0u, - 0x1bu, 0x88u, 0x83u, 0x81u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x0cu, 0x06u, 0x00u, 0x08u, + 0x1bu, 0x88u, 0x83u, 0x81u, 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0x10u, 0x06u, 0x00u, 0x08u, 0x08u, 0x10u, 0x00u, 0x00u, 0xf0u, 0xb5u, 0x83u, 0x68u, 0x85u, 0xb0u, 0x02u, 0xadu, 0x2bu, 0x80u, 0x15u, 0x4bu, 0x02u, 0x68u, 0x1bu, 0x68u, 0x06u, 0x6au, 0x9bu, 0x8eu, 0x47u, 0x6au, 0x9bu, 0x18u, 0xabu, 0x70u, 0x43u, 0x68u, 0x00u, 0x95u, 0x82u, 0x6au, 0xc1u, 0x6au, 0x04u, 0x00u, 0x03u, 0x93u, 0x03u, 0x69u, 0xc0u, 0x68u, 0xffu, 0xf7u, 0xb5u, 0xffu, 0x00u, 0x21u, 0x3bu, 0x00u, 0x0au, 0x00u, 0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xaeu, 0xffu, - 0x21u, 0x6bu, 0x28u, 0x00u, 0x00u, 0xf0u, 0xc8u, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, + 0x21u, 0x6bu, 0x28u, 0x00u, 0x00u, 0xf0u, 0xdeu, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, - 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x0cu, 0x06u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, + 0xf0u, 0xbdu, 0xc0u, 0x46u, 0x10u, 0x06u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, 0x26u, 0x68u, 0x69u, 0x43u, 0x34u, 0x18u, 0x25u, 0x69u, 0x01u, 0x93u, 0x71u, 0x18u, 0x00u, 0x2du, 0x19u, 0xd0u, 0x88u, 0x69u, 0x00u, 0x28u, 0x18u, 0xd1u, 0x2eu, 0x68u, 0x00u, 0x2eu, 0x15u, 0xdau, 0x67u, 0x68u, 0x01u, 0x24u, 0x26u, 0x00u, 0x4bu, 0x68u, 0x9eu, 0x40u, 0xb4u, 0x46u, 0x13u, 0x68u, 0x9eu, 0xb2u, @@ -112,20 +112,20 @@ const uint8_t cy_m0p_image[] = { 0x98u, 0x47u, 0x31u, 0x00u, 0x20u, 0x69u, 0xffu, 0xf7u, 0xf1u, 0xfeu, 0xadu, 0xb2u, 0x00u, 0x2du, 0x09u, 0xd0u, 0x63u, 0x69u, 0x1du, 0x60u, 0x00u, 0x25u, 0x1bu, 0x68u, 0x63u, 0x6au, 0xabu, 0x42u, 0x05u, 0xd0u, 0x98u, 0x47u, 0x65u, 0x62u, 0xa5u, 0x61u, 0x63u, 0x69u, 0x1bu, 0x68u, 0x73u, 0xbdu, 0xa3u, 0x6au, 0x00u, 0x2bu, 0xf8u, 0xd0u, - 0x98u, 0x47u, 0xf6u, 0xe7u, 0x0cu, 0x06u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, + 0x98u, 0x47u, 0xf6u, 0xe7u, 0x10u, 0x06u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, 0x10u, 0x68u, 0xc0u, 0x18u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x28u, 0x04u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x19u, 0x4bu, 0x0fu, 0x00u, 0x1bu, 0x68u, 0x1au, 0x00u, 0x2eu, 0x32u, 0x12u, 0x78u, 0x82u, 0x42u, 0x27u, 0xd9u, 0x00u, 0x29u, 0x25u, 0xd0u, 0x1fu, 0x25u, 0x0au, 0x68u, 0x15u, 0x40u, 0x21u, 0xd1u, 0x19u, 0x00u, 0xacu, 0x31u, 0x0cu, 0x88u, 0x11u, 0x4eu, 0x60u, 0x43u, 0x1cu, 0x6au, 0xd2u, 0x08u, 0x04u, 0x19u, 0x29u, 0x00u, - 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0xfeu, 0xfeu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xaeu, 0xfeu, + 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0x14u, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xaeu, 0xfeu, 0x3au, 0x00u, 0x29u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xbbu, 0xfeu, 0x04u, 0x1eu, 0x07u, 0xd1u, 0x01u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xa3u, 0xfeu, 0x03u, 0x00u, 0x20u, 0x00u, 0x00u, 0x2bu, 0x00u, 0xd0u, 0x04u, 0x48u, - 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x0cu, 0x06u, 0x00u, 0x08u, 0x2cu, 0x04u, 0x00u, 0x08u, + 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x10u, 0x06u, 0x00u, 0x08u, 0x2cu, 0x04u, 0x00u, 0x08u, 0x01u, 0x01u, 0x8au, 0x00u, 0x03u, 0x01u, 0x8au, 0x00u, 0x10u, 0xb5u, 0x00u, 0x2au, 0x0du, 0xd1u, 0x00u, 0x29u, 0x14u, 0xd1u, 0x0bu, 0x4bu, 0x1au, 0x68u, 0x13u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u, 0x58u, 0x43u, 0x13u, 0x6au, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x18u, 0x60u, 0x08u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x29u, 0x06u, 0xd0u, 0x06u, 0x4bu, 0x19u, 0x60u, 0x19u, 0x00u, 0x5au, 0x60u, 0xffu, 0xf7u, 0xabu, 0xffu, 0xf5u, 0xe7u, 0x03u, 0x48u, 0xf3u, 0xe7u, - 0x0cu, 0x06u, 0x00u, 0x08u, 0x2cu, 0x04u, 0x00u, 0x08u, 0xbcu, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, + 0x10u, 0x06u, 0x00u, 0x08u, 0x2cu, 0x04u, 0x00u, 0x08u, 0xbcu, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, 0xf7u, 0xb5u, 0x18u, 0x4fu, 0x04u, 0x00u, 0x3bu, 0x68u, 0x01u, 0x91u, 0xdeu, 0x68u, 0x33u, 0x68u, 0x83u, 0x42u, 0x26u, 0xd9u, 0x00u, 0x25u, 0xa9u, 0x42u, 0x02u, 0xd1u, 0xffu, 0xf7u, 0x67u, 0xfdu, 0x05u, 0x00u, 0x38u, 0x68u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x1au, 0xdau, 0x1fu, 0x22u, 0x01u, 0x23u, 0x22u, 0x40u, 0x93u, 0x40u, 0x64u, 0x09u, @@ -138,279 +138,282 @@ const uint8_t cy_m0p_image[] = { 0x18u, 0x40u, 0x43u, 0x1eu, 0x98u, 0x41u, 0x03u, 0x4bu, 0xc0u, 0x18u, 0x70u, 0x47u, 0x02u, 0x48u, 0xfcu, 0xe7u, 0x2cu, 0x04u, 0x00u, 0x08u, 0x00u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0xa6u, 0x22u, 0x05u, 0x49u, 0xd2u, 0x00u, 0x8bu, 0x58u, 0x02u, 0x20u, 0xdbu, 0x43u, 0x9bu, 0x07u, 0x02u, 0xd0u, 0x01u, 0x23u, 0x88u, 0x58u, - 0x18u, 0x40u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x09u, 0x4au, 0x83u, 0x00u, 0x9bu, 0x18u, 0xd0u, 0x22u, - 0x92u, 0x00u, 0x98u, 0x58u, 0x07u, 0x22u, 0x10u, 0x40u, 0x04u, 0x28u, 0x07u, 0xd1u, 0xc0u, 0x22u, 0x92u, 0x00u, - 0x98u, 0x58u, 0x1fu, 0x23u, 0x03u, 0x40u, 0x80u, 0x20u, 0x40u, 0x00u, 0x18u, 0x43u, 0x70u, 0x47u, 0xc0u, 0x46u, - 0x00u, 0x00u, 0x26u, 0x40u, 0xb0u, 0x23u, 0x15u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x10u, 0xb5u, 0x99u, 0x03u, - 0xdbu, 0x01u, 0xdbu, 0x0fu, 0x89u, 0x0bu, 0xc3u, 0x71u, 0x11u, 0x4bu, 0x01u, 0x60u, 0xd3u, 0x58u, 0x0fu, 0x24u, - 0xd9u, 0x04u, 0xdbu, 0x01u, 0xdbu, 0x0du, 0x03u, 0x81u, 0xb1u, 0x23u, 0xdbu, 0x00u, 0xd3u, 0x58u, 0xc9u, 0x0cu, - 0x81u, 0x80u, 0x19u, 0x00u, 0x21u, 0x40u, 0x81u, 0x72u, 0x19u, 0x09u, 0x21u, 0x40u, 0xc1u, 0x72u, 0xd9u, 0x02u, - 0x9bu, 0x00u, 0x9bu, 0x0fu, 0x83u, 0x73u, 0x07u, 0x4bu, 0xc9u, 0x0cu, 0xd3u, 0x58u, 0x81u, 0x81u, 0x5au, 0x05u, - 0xdbu, 0x01u, 0x52u, 0x0fu, 0xdbu, 0x0du, 0x82u, 0x71u, 0x03u, 0x82u, 0x10u, 0xbdu, 0x00u, 0x00u, 0x26u, 0x40u, - 0x84u, 0x05u, 0x00u, 0x00u, 0x8cu, 0x05u, 0x00u, 0x00u, 0x10u, 0xb5u, 0x10u, 0x4bu, 0x42u, 0x1eu, 0x1bu, 0x68u, - 0x3bu, 0x33u, 0x1bu, 0x78u, 0x93u, 0x42u, 0x16u, 0xd9u, 0x7fu, 0x22u, 0x1fu, 0x24u, 0x80u, 0x30u, 0xffu, 0x30u, - 0x0bu, 0x4bu, 0x80u, 0x00u, 0xc3u, 0x58u, 0x1au, 0x40u, 0x0au, 0x70u, 0x1au, 0x0cu, 0x22u, 0x40u, 0x18u, 0x0au, - 0x8au, 0x70u, 0x1au, 0x01u, 0x20u, 0x40u, 0xe2u, 0x40u, 0x48u, 0x70u, 0x00u, 0x20u, 0x9bu, 0x00u, 0x9bu, 0x0fu, - 0xcau, 0x70u, 0x0bu, 0x71u, 0x10u, 0xbdu, 0x03u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0x0cu, 0x06u, 0x00u, 0x08u, - 0x00u, 0x00u, 0x26u, 0x40u, 0x01u, 0x00u, 0x4au, 0x00u, 0xe0u, 0x22u, 0x01u, 0x21u, 0x4du, 0x4bu, 0x80u, 0x00u, - 0xc0u, 0x18u, 0x92u, 0x00u, 0x83u, 0x58u, 0xf0u, 0xb5u, 0x9bu, 0x06u, 0x9bu, 0x0fu, 0x99u, 0x40u, 0x0fu, 0x23u, - 0x84u, 0x58u, 0x89u, 0xb0u, 0x1cu, 0x40u, 0x20u, 0x00u, 0x01u, 0x91u, 0xffu, 0xf7u, 0x7du, 0xffu, 0x03u, 0x28u, - 0x54u, 0xd0u, 0x08u, 0xd8u, 0x01u, 0x28u, 0x13u, 0xd0u, 0x62u, 0xd9u, 0xffu, 0xf7u, 0x67u, 0xffu, 0x42u, 0x4bu, - 0x02u, 0x28u, 0x0bu, 0xd1u, 0x0du, 0xe0u, 0x12u, 0x23u, 0xffu, 0x33u, 0x98u, 0x42u, 0x50u, 0xd0u, 0x14u, 0x23u, - 0xffu, 0x33u, 0x98u, 0x42u, 0x51u, 0xd0u, 0x03u, 0x3bu, 0x98u, 0x42u, 0x41u, 0xd0u, 0x00u, 0x26u, 0x01u, 0xe0u, - 0x3au, 0x4bu, 0x1eu, 0x68u, 0x00u, 0x2cu, 0x4du, 0xd1u, 0x03u, 0xadu, 0x14u, 0x22u, 0x21u, 0x00u, 0x28u, 0x00u, - 0x00u, 0xf0u, 0xb0u, 0xfdu, 0x28u, 0x00u, 0xffu, 0xf7u, 0x6du, 0xffu, 0xb0u, 0x23u, 0x31u, 0x4au, 0xdbu, 0x00u, - 0xd3u, 0x58u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xacu, 0x7bu, 0x02u, 0x3cu, 0x63u, 0x1eu, 0x9cu, 0x41u, 0xeau, 0x79u, - 0x03u, 0x9fu, 0x53u, 0x1eu, 0x9au, 0x41u, 0xa8u, 0x88u, 0x01u, 0x32u, 0x00u, 0x2cu, 0x16u, 0xd0u, 0x00u, 0x23u, - 0x19u, 0x00u, 0x00u, 0xf0u, 0x81u, 0xfcu, 0x00u, 0x23u, 0x0cu, 0x00u, 0x05u, 0x00u, 0x3au, 0x00u, 0x30u, 0x00u, - 0x19u, 0x00u, 0x00u, 0xf0u, 0x79u, 0xfcu, 0xe6u, 0x07u, 0x6au, 0x08u, 0x32u, 0x43u, 0x63u, 0x08u, 0x80u, 0x18u, - 0x59u, 0x41u, 0x2au, 0x00u, 0x23u, 0x00u, 0x00u, 0xf0u, 0x4fu, 0xfcu, 0x06u, 0x00u, 0x01u, 0x9bu, 0x58u, 0x08u, - 0x80u, 0x19u, 0x19u, 0x00u, 0x00u, 0xf0u, 0xbcu, 0xfbu, 0x09u, 0xb0u, 0xf0u, 0xbdu, 0x1cu, 0x4bu, 0xc0u, 0xe7u, - 0x18u, 0x4au, 0x1cu, 0x4bu, 0xd3u, 0x58u, 0x00u, 0x2bu, 0xb8u, 0xdau, 0x80u, 0x26u, 0x36u, 0x02u, 0xb9u, 0xe7u, - 0x19u, 0x4bu, 0x1bu, 0x69u, 0x5bu, 0x07u, 0xf8u, 0xd4u, 0xb0u, 0xe7u, 0x12u, 0x4au, 0x17u, 0x4bu, 0xf1u, 0xe7u, - 0x17u, 0x4eu, 0xafu, 0xe7u, 0x17u, 0x4bu, 0x1bu, 0x68u, 0x3bu, 0x33u, 0x1bu, 0x78u, 0xa3u, 0x42u, 0xddu, 0xd3u, - 0x03u, 0xadu, 0x05u, 0x22u, 0x00u, 0x21u, 0x28u, 0x00u, 0x00u, 0xf0u, 0x5cu, 0xfdu, 0x20u, 0x00u, 0x29u, 0x00u, - 0x80u, 0x34u, 0xffu, 0xf7u, 0x49u, 0xffu, 0xffu, 0x34u, 0x06u, 0x4bu, 0xa4u, 0x00u, 0xe3u, 0x58u, 0x00u, 0x24u, - 0xa3u, 0x42u, 0x03u, 0xdau, 0x2cu, 0x79u, 0x02u, 0x3cu, 0x63u, 0x1eu, 0x9cu, 0x41u, 0x2fu, 0x78u, 0x68u, 0x78u, - 0xaau, 0x78u, 0xaau, 0xe7u, 0x00u, 0x00u, 0x26u, 0x40u, 0x30u, 0x04u, 0x00u, 0x08u, 0x34u, 0x04u, 0x00u, 0x08u, - 0xc4u, 0x00u, 0x00u, 0x08u, 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x00u, 0x27u, 0x40u, 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0xe5u, 0xe7u, 0x06u, 0x4cu, + 0xe3u, 0xe7u, 0x09u, 0x4cu, 0xe1u, 0xe7u, 0xc0u, 0x46u, 0x10u, 0x06u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, + 0x1cu, 0x05u, 0x00u, 0x00u, 0x14u, 0x04u, 0x00u, 0x08u, 0x05u, 0x00u, 0x52u, 0x00u, 0x01u, 0x01u, 0x88u, 0x00u, + 0x24u, 0x04u, 0x00u, 0x08u, 0xf0u, 0x49u, 0x02u, 0x00u, 0x01u, 0x00u, 0x50u, 0x00u, 0x18u, 0x4bu, 0xf7u, 0xb5u, + 0x1bu, 0x68u, 0x18u, 0x4au, 0x5cu, 0x68u, 0x04u, 0x23u, 0x11u, 0x69u, 0x0bu, 0x43u, 0x13u, 0x61u, 0x01u, 0x28u, + 0x24u, 0xd0u, 0x30u, 0xbfu, 0x23u, 0x00u, 0xfcu, 0x33u, 0x1bu, 0x69u, 0x00u, 0x2bu, 0x1du, 0xd1u, 0xa3u, 0x20u, + 0x11u, 0x4bu, 0x12u, 0x49u, 0x12u, 0x4au, 0xc0u, 0x00u, 0x0fu, 0x68u, 0x1eu, 0x58u, 0x15u, 0x68u, 0x01u, 0x95u, + 0x10u, 0x4du, 0x0du, 0x60u, 0x06u, 0x25u, 0x1du, 0x50u, 0x3eu, 0x20u, 0x10u, 0x60u, 0x0eu, 0x48u, 0x3eu, 0x35u, + 0x1du, 0x50u, 0x1du, 0x58u, 0x00u, 0x2du, 0xfcu, 0xdau, 0x0cu, 0x48u, 0xfcu, 0x34u, 0x20u, 0x61u, 0x0fu, 0x60u, + 0xa3u, 0x21u, 0xc9u, 0x00u, 0x5eu, 0x50u, 0x01u, 0x9bu, 0x13u, 0x60u, 0xf7u, 0xbdu, 0x20u, 0xbfu, 0xd9u, 0xe7u, + 0x10u, 0x06u, 0x00u, 0x08u, 0x00u, 0xedu, 0x00u, 0xe0u, 0x00u, 0x00u, 0x26u, 0x40u, 0x08u, 0x01u, 0x26u, 0x40u, + 0x04u, 0x01u, 0x26u, 0x40u, 0x1eu, 0x1fu, 0x00u, 0x00u, 0x1cu, 0x05u, 0x00u, 0x00u, 0xaau, 0xaau, 0xaau, 0xaau, + 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0xa5u, 0x06u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x23u, 0x01u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x4du, 0x04u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0xb5u, 0x0fu, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x1bu, 0x01u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x31u, 0x06u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x79u, 0x02u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0x31u, 0x03u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, + 0xb5u, 0x01u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, - 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + }; #endif /* defined(CY_DEVICE_PSOC6ABLE2) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_02_cm0p_sleep.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_02_cm0p_sleep.c index 81e1bd68aa6..5ab97070c61 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_02_cm0p_sleep.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_02_cm0p_sleep.c @@ -37,21 +37,21 @@ const uint8_t cy_m0p_image[] = { 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0xb0u, 0x03u, 0x00u, 0x08u, - 0x00u, 0x00u, 0x00u, 0x00u, 0xf0u, 0x13u, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x18u, 0x14u, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xb4u, 0x03u, 0x00u, 0x08u, 0xf0u, 0x13u, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, + 0xb4u, 0x03u, 0x00u, 0x08u, 0x18u, 0x14u, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, 0x02u, 0x38u, 0xfcu, 0xd1u, 0xc0u, 0x46u, 0xc0u, 0x46u, 0x70u, 0x47u, 0xefu, 0xf3u, 0x10u, 0x80u, 0x72u, 0xb6u, 0x70u, 0x47u, 0x80u, 0xf3u, 0x10u, 0x88u, 0x70u, 0x47u, 0x70u, 0x47u, 0xffu, 0xf7u, 0xfdu, 0xffu, 0x72u, 0xb6u, 0x0fu, 0x4cu, 0x10u, 0x4du, 0xacu, 0x42u, 0x09u, 0xdau, 0x21u, 0x68u, 0x62u, 0x68u, 0xa3u, 0x68u, 0x04u, 0x3bu, 0x02u, 0xdbu, 0xc8u, 0x58u, 0xd0u, 0x50u, 0xfau, 0xe7u, 0x0cu, 0x34u, 0xf3u, 0xe7u, 0x0au, 0x49u, 0x0bu, 0x4au, 0x00u, 0x20u, 0x52u, 0x1au, 0x02u, 0xddu, 0x04u, 0x3au, 0x88u, 0x50u, 0xfcu, 0xdcu, 0x08u, 0x48u, 0x09u, 0x49u, - 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x00u, 0xf0u, 0x73u, 0xfeu, 0x00u, 0xf0u, 0x1du, 0xfeu, 0xfeu, 0xe7u, - 0xfcu, 0x13u, 0x00u, 0x10u, 0x14u, 0x14u, 0x00u, 0x10u, 0xb0u, 0x03u, 0x00u, 0x08u, 0xccu, 0x05u, 0x00u, 0x08u, + 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x00u, 0xf0u, 0x85u, 0xfeu, 0x00u, 0xf0u, 0x2fu, 0xfeu, 0xfeu, 0xe7u, + 0x24u, 0x14u, 0x00u, 0x10u, 0x3cu, 0x14u, 0x00u, 0x10u, 0xb0u, 0x03u, 0x00u, 0x08u, 0xc8u, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x08u, 0x08u, 0xedu, 0x00u, 0xe0u, 0xfeu, 0xe7u, 0xfeu, 0xe7u, 0x00u, 0xb5u, 0x04u, 0x20u, 0x71u, 0x46u, 0x08u, 0x42u, 0x02u, 0xd0u, 0xefu, 0xf3u, 0x09u, 0x80u, 0x01u, 0xe0u, 0xefu, 0xf3u, 0x08u, 0x80u, - 0x04u, 0x30u, 0x00u, 0xf0u, 0x0fu, 0xfcu, 0xfeu, 0xe7u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, - 0xc8u, 0x05u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, - 0x50u, 0x43u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xc8u, 0x05u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, + 0x04u, 0x30u, 0x00u, 0xf0u, 0x21u, 0xfcu, 0xfeu, 0xe7u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, + 0xc4u, 0x05u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, + 0x50u, 0x43u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, 0x40u, 0x28u, 0x2fu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x30u, 0xd0u, 0x10u, 0x28u, 0x28u, 0xd0u, 0x19u, 0x48u, 0x1eu, 0xe0u, 0x80u, 0x28u, 0x28u, 0xd0u, 0x80u, 0x23u, 0x5bu, 0x00u, 0x98u, 0x42u, 0xf7u, 0xd1u, 0x14u, 0x48u, 0x16u, 0xe0u, 0x15u, 0x4bu, 0x98u, 0x42u, 0x14u, 0xd0u, 0x08u, 0xd8u, 0xa0u, 0x23u, @@ -65,27 +65,27 @@ const uint8_t cy_m0p_image[] = { 0x02u, 0x00u, 0x50u, 0x00u, 0x05u, 0x00u, 0x52u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x9au, 0xffu, 0x0au, 0x4bu, 0x1cu, 0x68u, 0x23u, 0x00u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x0au, 0xdbu, 0x07u, 0x4bu, 0x18u, 0x68u, 0xffu, 0xf7u, 0x99u, 0xffu, 0x01u, 0x22u, 0x63u, 0x68u, 0x9au, 0x60u, - 0x9au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc8u, 0x05u, 0x00u, 0x08u, + 0x9au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0xccu, 0x03u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0x89u, 0xb2u, 0x41u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, - 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc8u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, + 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u, 0xc2u, 0x60u, 0x81u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x00u, 0x8au, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, - 0xc8u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, + 0xc4u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x18u, 0x60u, 0x70u, 0x47u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x12u, 0x4cu, 0x1fu, 0x00u, 0x24u, 0x68u, 0x1eu, 0x0au, 0x20u, 0x18u, 0xffu, 0x24u, 0x27u, 0x40u, 0x34u, 0x40u, 0x0fu, 0x4eu, 0x1bu, 0x0cu, 0x35u, 0x68u, 0x07u, 0x60u, 0x2eu, 0x6au, 0x44u, 0x60u, 0x83u, 0x60u, 0xacu, 0x35u, 0x2du, 0x88u, 0x80u, 0x34u, 0x6fu, 0x43u, 0x64u, 0x01u, 0x34u, 0x19u, 0xbfu, 0x19u, 0x1eu, 0x04u, 0x33u, 0x43u, 0x07u, 0x61u, 0x44u, 0x61u, 0xa3u, 0x60u, 0x00u, 0x23u, 0x83u, 0x61u, 0x05u, 0x9bu, 0xc2u, 0x61u, 0x01u, 0x62u, 0x00u, 0x2bu, - 0x01u, 0xd0u, 0x1bu, 0x88u, 0x83u, 0x81u, 0xf0u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0xc8u, 0x05u, 0x00u, 0x08u, + 0x01u, 0xd0u, 0x1bu, 0x88u, 0x83u, 0x81u, 0xf0u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0xc4u, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x83u, 0x68u, 0x85u, 0xb0u, 0x02u, 0xadu, 0x2bu, 0x80u, 0x15u, 0x4bu, 0x02u, 0x68u, 0x1bu, 0x68u, 0x06u, 0x6au, 0x9bu, 0x8eu, 0x47u, 0x6au, 0x9bu, 0x18u, 0x6bu, 0x80u, 0x43u, 0x68u, 0x00u, 0x95u, 0x82u, 0x6au, 0xc1u, 0x6au, 0x04u, 0x00u, 0x03u, 0x93u, 0x03u, 0x69u, 0xc0u, 0x68u, 0xffu, 0xf7u, 0xbdu, 0xffu, 0x00u, 0x21u, 0x3bu, 0x00u, 0x0au, 0x00u, 0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x21u, 0x6bu, 0x28u, 0x00u, - 0x00u, 0xf0u, 0xb4u, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, + 0x00u, 0xf0u, 0xc6u, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0xc8u, 0x05u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, + 0xc4u, 0x05u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, 0x26u, 0x68u, 0x69u, 0x43u, 0x34u, 0x18u, 0x25u, 0x69u, 0x01u, 0x93u, 0x71u, 0x18u, 0x00u, 0x2du, 0x19u, 0xd0u, 0x88u, 0x69u, 0x00u, 0x28u, 0x18u, 0xd1u, 0x2eu, 0x68u, 0x00u, 0x2eu, 0x15u, 0xdau, 0x67u, 0x68u, 0x01u, 0x24u, 0x26u, 0x00u, 0x4bu, 0x68u, 0x9eu, 0x40u, 0xb4u, 0x46u, 0x13u, 0x68u, 0x9eu, 0xb2u, 0x63u, 0x46u, 0x1bu, 0x04u, @@ -99,20 +99,20 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x2bu, 0x00u, 0xd0u, 0x98u, 0x47u, 0x31u, 0x00u, 0x20u, 0x69u, 0xffu, 0xf7u, 0x0du, 0xffu, 0xadu, 0xb2u, 0x00u, 0x2du, 0x09u, 0xd0u, 0x63u, 0x69u, 0x1du, 0x60u, 0x00u, 0x25u, 0x1bu, 0x68u, 0x63u, 0x6au, 0xabu, 0x42u, 0x05u, 0xd0u, 0x98u, 0x47u, 0x65u, 0x62u, 0xa5u, 0x61u, 0x63u, 0x69u, 0x1bu, 0x68u, 0x73u, 0xbdu, 0xa3u, 0x6au, - 0x00u, 0x2bu, 0xf8u, 0xd0u, 0x98u, 0x47u, 0xf6u, 0xe7u, 0xc8u, 0x05u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, + 0x00u, 0x2bu, 0xf8u, 0xd0u, 0x98u, 0x47u, 0xf6u, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, 0x10u, 0x68u, 0xc0u, 0x18u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x19u, 0x4bu, 0x0fu, 0x00u, 0x1bu, 0x68u, 0x1au, 0x00u, 0x2eu, 0x32u, 0x12u, 0x78u, 0x82u, 0x42u, 0x27u, 0xd9u, 0x00u, 0x29u, 0x25u, 0xd0u, 0x1fu, 0x25u, 0x0au, 0x68u, 0x15u, 0x40u, 0x21u, 0xd1u, 0x19u, 0x00u, 0xacu, 0x31u, 0x0cu, 0x88u, 0x11u, 0x4eu, 0x60u, 0x43u, 0x1cu, 0x6au, 0xd2u, 0x08u, - 0x04u, 0x19u, 0x29u, 0x00u, 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0xfau, 0xfeu, 0x29u, 0x00u, 0x20u, 0x00u, + 0x04u, 0x19u, 0x29u, 0x00u, 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0x0cu, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcau, 0xfeu, 0x3au, 0x00u, 0x29u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xd7u, 0xfeu, 0x04u, 0x1eu, 0x07u, 0xd1u, 0x01u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xbfu, 0xfeu, 0x03u, 0x00u, 0x20u, 0x00u, 0x00u, 0x2bu, - 0x00u, 0xd0u, 0x04u, 0x48u, 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xc8u, 0x05u, 0x00u, 0x08u, + 0x00u, 0xd0u, 0x04u, 0x48u, 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xc4u, 0x05u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x01u, 0x01u, 0x8au, 0x00u, 0x03u, 0x01u, 0x8au, 0x00u, 0x10u, 0xb5u, 0x00u, 0x2au, 0x0du, 0xd1u, 0x00u, 0x29u, 0x14u, 0xd1u, 0x0bu, 0x4bu, 0x1au, 0x68u, 0x13u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u, 0x58u, 0x43u, 0x13u, 0x6au, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x18u, 0x60u, 0x08u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x29u, 0x06u, 0xd0u, 0x06u, 0x4bu, 0x19u, 0x60u, 0x19u, 0x00u, 0x5au, 0x60u, 0xffu, 0xf7u, 0xabu, 0xffu, 0xf5u, 0xe7u, - 0x03u, 0x48u, 0xf3u, 0xe7u, 0xc8u, 0x05u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x78u, 0x03u, 0x00u, 0x08u, + 0x03u, 0x48u, 0xf3u, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x78u, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, 0xf7u, 0xb5u, 0x18u, 0x4fu, 0x04u, 0x00u, 0x3bu, 0x68u, 0x01u, 0x91u, 0xdeu, 0x68u, 0x33u, 0x68u, 0x83u, 0x42u, 0x26u, 0xd9u, 0x00u, 0x25u, 0xa9u, 0x42u, 0x02u, 0xd1u, 0xffu, 0xf7u, 0xadu, 0xfdu, 0x05u, 0x00u, 0x38u, 0x68u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x1au, 0xdau, 0x1fu, 0x22u, 0x01u, 0x23u, 0x22u, 0x40u, @@ -125,10 +125,19 @@ const uint8_t cy_m0p_image[] = { 0x92u, 0x00u, 0x50u, 0x58u, 0x18u, 0x40u, 0x43u, 0x1eu, 0x98u, 0x41u, 0x03u, 0x4bu, 0xc0u, 0x18u, 0x70u, 0x47u, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x00u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0xa6u, 0x22u, 0x05u, 0x49u, 0xd2u, 0x00u, 0x8bu, 0x58u, 0x02u, 0x20u, 0xdbu, 0x43u, 0x9bu, 0x07u, 0x02u, 0xd0u, - 0x01u, 0x23u, 0x88u, 0x58u, 0x18u, 0x40u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x09u, 0x4au, 0x83u, 0x00u, - 0x9bu, 0x18u, 0xd0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x07u, 0x22u, 0x10u, 0x40u, 0x04u, 0x28u, 0x07u, 0xd1u, - 0xc0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x1fu, 0x23u, 0x03u, 0x40u, 0x80u, 0x20u, 0x40u, 0x00u, 0x18u, 0x43u, - 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0xb0u, 0x23u, 0x15u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, + 0x01u, 0x23u, 0x88u, 0x58u, 0x18u, 0x40u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, + 0xefu, 0xffu, 0x00u, 0x23u, 0x02u, 0x28u, 0x01u, 0xd1u, 0x01u, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x00u, 0x10u, 0xbdu, + 0xe8u, 0x03u, 0x00u, 0x08u, 0x09u, 0x4au, 0x83u, 0x00u, 0x9bu, 0x18u, 0xd0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, + 0x07u, 0x22u, 0x10u, 0x40u, 0x04u, 0x28u, 0x07u, 0xd1u, 0xc0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x1fu, 0x23u, + 0x03u, 0x40u, 0x80u, 0x20u, 0x40u, 0x00u, 0x18u, 0x43u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, + 0x10u, 0xb5u, 0xffu, 0xf7u, 0xe7u, 0xffu, 0x02u, 0x28u, 0x1cu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x14u, 0xd0u, + 0x01u, 0x28u, 0x14u, 0xd0u, 0x00u, 0x20u, 0x11u, 0xe0u, 0x12u, 0x23u, 0xffu, 0x33u, 0x98u, 0x42u, 0x14u, 0xd0u, + 0x14u, 0x23u, 0xffu, 0x33u, 0x98u, 0x42u, 0x18u, 0xd0u, 0x03u, 0x3bu, 0x98u, 0x42u, 0xf2u, 0xd1u, 0x0cu, 0x4au, + 0x0cu, 0x4bu, 0xd0u, 0x58u, 0xc0u, 0x0fu, 0xc0u, 0x03u, 0x00u, 0xe0u, 0x0bu, 0x48u, 0x10u, 0xbdu, 0x0bu, 0x4bu, + 0x18u, 0x68u, 0xfbu, 0xe7u, 0xffu, 0xf7u, 0xbau, 0xffu, 0xf8u, 0xe7u, 0x09u, 0x4bu, 0x18u, 0x69u, 0x04u, 0x23u, + 0x18u, 0x40u, 0xf3u, 0xd0u, 0x80u, 0x20u, 0x00u, 0x02u, 0xf0u, 0xe7u, 0x01u, 0x4au, 0x05u, 0x4bu, 0xe8u, 0xe7u, + 0x00u, 0x00u, 0x26u, 0x40u, 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x12u, 0x7au, 0x00u, 0xecu, 0x03u, 0x00u, 0x08u, + 0x00u, 0x00u, 0x27u, 0x40u, 0x3cu, 0x05u, 0x00u, 0x00u, 0xb0u, 0x23u, 0x15u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x10u, 0xb5u, 0x99u, 0x03u, 0xdbu, 0x01u, 0xdbu, 0x0fu, 0x89u, 0x0bu, 0xc3u, 0x71u, 0x11u, 0x4bu, 0x01u, 0x60u, 0xd3u, 0x58u, 0x0fu, 0x24u, 0xd9u, 0x04u, 0xdbu, 0x01u, 0xdbu, 0x0du, 0x03u, 0x81u, 0xb1u, 0x23u, 0xdbu, 0x00u, 0xd3u, 0x58u, 0xc9u, 0x0cu, 0x81u, 0x80u, 0x19u, 0x00u, 0x21u, 0x40u, 0x81u, 0x72u, 0x19u, 0x09u, 0x21u, 0x40u, @@ -139,264 +148,258 @@ const uint8_t cy_m0p_image[] = { 0x80u, 0x30u, 0xffu, 0x30u, 0x0bu, 0x4bu, 0x80u, 0x00u, 0xc3u, 0x58u, 0x1au, 0x40u, 0x0au, 0x70u, 0x1au, 0x0cu, 0x22u, 0x40u, 0x18u, 0x0au, 0x8au, 0x70u, 0x1au, 0x01u, 0x20u, 0x40u, 0xe2u, 0x40u, 0x48u, 0x70u, 0x00u, 0x20u, 0x9bu, 0x00u, 0x9bu, 0x0fu, 0xcau, 0x70u, 0x0bu, 0x71u, 0x10u, 0xbdu, 0x03u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, - 0xc8u, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, 0x01u, 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0x02u, 0x00u, + 0x01u, 0x00u, 0x50u, 0x00u, 0x18u, 0x4bu, 0xf7u, 0xb5u, 0x1bu, 0x68u, 0x18u, 0x4au, 0x5cu, 0x68u, 0x04u, 0x23u, + 0x11u, 0x69u, 0x0bu, 0x43u, 0x13u, 0x61u, 0x01u, 0x28u, 0x24u, 0xd0u, 0x30u, 0xbfu, 0x23u, 0x00u, 0xfcu, 0x33u, + 0x1bu, 0x69u, 0x00u, 0x2bu, 0x1du, 0xd1u, 0xa3u, 0x20u, 0x11u, 0x4bu, 0x12u, 0x49u, 0x12u, 0x4au, 0xc0u, 0x00u, + 0x0fu, 0x68u, 0x1eu, 0x58u, 0x15u, 0x68u, 0x01u, 0x95u, 0x10u, 0x4du, 0x0du, 0x60u, 0x06u, 0x25u, 0x1du, 0x50u, + 0x3eu, 0x20u, 0x10u, 0x60u, 0x0eu, 0x48u, 0x3eu, 0x35u, 0x1du, 0x50u, 0x1du, 0x58u, 0x00u, 0x2du, 0xfcu, 0xdau, + 0x0cu, 0x48u, 0xfcu, 0x34u, 0x20u, 0x61u, 0x0fu, 0x60u, 0xa3u, 0x21u, 0xc9u, 0x00u, 0x5eu, 0x50u, 0x01u, 0x9bu, + 0x13u, 0x60u, 0xf7u, 0xbdu, 0x20u, 0xbfu, 0xd9u, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x00u, 0xedu, 0x00u, 0xe0u, + 0x00u, 0x00u, 0x26u, 0x40u, 0x08u, 0x01u, 0x26u, 0x40u, 0x04u, 0x01u, 0x26u, 0x40u, 0x1eu, 0x1fu, 0x00u, 0x00u, + 0x1cu, 0x05u, 0x00u, 0x00u, 0xaau, 0xaau, 0xaau, 0xaau, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xdbu, 0x00u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x9du, 0x02u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xa9u, 0x03u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xe3u, 0x00u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xddu, 0x0eu, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xd9u, 0x05u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x75u, 0x01u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x65u, 0x05u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x39u, 0x02u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, }; #endif /* defined(CY_DEVICE_PSOC6A2M) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_03_cm0p_sleep.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_03_cm0p_sleep.c index 532d2337223..de4c30d0ef1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_03_cm0p_sleep.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/COMPONENT_CM0P_SLEEP/psoc6_03_cm0p_sleep.c @@ -37,21 +37,21 @@ const uint8_t cy_m0p_image[] = { 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x49u, 0x01u, 0x00u, 0x10u, 0x10u, 0xb5u, 0x06u, 0x4cu, 0x23u, 0x78u, 0x00u, 0x2bu, 0x07u, 0xd1u, 0x05u, 0x4bu, 0x00u, 0x2bu, 0x02u, 0xd0u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x01u, 0x23u, 0x23u, 0x70u, 0x10u, 0xbdu, 0xb0u, 0x03u, 0x00u, 0x08u, - 0x00u, 0x00u, 0x00u, 0x00u, 0xf0u, 0x13u, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x18u, 0x14u, 0x00u, 0x10u, 0x04u, 0x4bu, 0x10u, 0xb5u, 0x00u, 0x2bu, 0x03u, 0xd0u, 0x03u, 0x49u, 0x04u, 0x48u, 0x00u, 0xe0u, 0x00u, 0xbfu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0x00u, 0x00u, 0x00u, 0x00u, - 0xb4u, 0x03u, 0x00u, 0x08u, 0xf0u, 0x13u, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, + 0xb4u, 0x03u, 0x00u, 0x08u, 0x18u, 0x14u, 0x00u, 0x10u, 0x02u, 0x30u, 0x80u, 0x08u, 0x03u, 0xd0u, 0x01u, 0x30u, 0x02u, 0x38u, 0xfcu, 0xd1u, 0xc0u, 0x46u, 0xc0u, 0x46u, 0x70u, 0x47u, 0xefu, 0xf3u, 0x10u, 0x80u, 0x72u, 0xb6u, 0x70u, 0x47u, 0x80u, 0xf3u, 0x10u, 0x88u, 0x70u, 0x47u, 0x70u, 0x47u, 0xffu, 0xf7u, 0xfdu, 0xffu, 0x72u, 0xb6u, 0x0fu, 0x4cu, 0x10u, 0x4du, 0xacu, 0x42u, 0x09u, 0xdau, 0x21u, 0x68u, 0x62u, 0x68u, 0xa3u, 0x68u, 0x04u, 0x3bu, 0x02u, 0xdbu, 0xc8u, 0x58u, 0xd0u, 0x50u, 0xfau, 0xe7u, 0x0cu, 0x34u, 0xf3u, 0xe7u, 0x0au, 0x49u, 0x0bu, 0x4au, 0x00u, 0x20u, 0x52u, 0x1au, 0x02u, 0xddu, 0x04u, 0x3au, 0x88u, 0x50u, 0xfcu, 0xdcu, 0x08u, 0x48u, 0x09u, 0x49u, - 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x00u, 0xf0u, 0x73u, 0xfeu, 0x00u, 0xf0u, 0x1du, 0xfeu, 0xfeu, 0xe7u, - 0xfcu, 0x13u, 0x00u, 0x10u, 0x14u, 0x14u, 0x00u, 0x10u, 0xb0u, 0x03u, 0x00u, 0x08u, 0xccu, 0x05u, 0x00u, 0x08u, + 0x08u, 0x60u, 0xbfu, 0xf3u, 0x4fu, 0x8fu, 0x00u, 0xf0u, 0x85u, 0xfeu, 0x00u, 0xf0u, 0x2fu, 0xfeu, 0xfeu, 0xe7u, + 0x24u, 0x14u, 0x00u, 0x10u, 0x3cu, 0x14u, 0x00u, 0x10u, 0xb0u, 0x03u, 0x00u, 0x08u, 0xc8u, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x08u, 0x08u, 0xedu, 0x00u, 0xe0u, 0xfeu, 0xe7u, 0xfeu, 0xe7u, 0x00u, 0xb5u, 0x04u, 0x20u, 0x71u, 0x46u, 0x08u, 0x42u, 0x02u, 0xd0u, 0xefu, 0xf3u, 0x09u, 0x80u, 0x01u, 0xe0u, 0xefu, 0xf3u, 0x08u, 0x80u, - 0x04u, 0x30u, 0x00u, 0xf0u, 0x0fu, 0xfcu, 0xfeu, 0xe7u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, - 0xc8u, 0x05u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, - 0x50u, 0x43u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xc8u, 0x05u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, + 0x04u, 0x30u, 0x00u, 0xf0u, 0x21u, 0xfcu, 0xfeu, 0xe7u, 0x01u, 0x4bu, 0x18u, 0x60u, 0x70u, 0x47u, 0xc0u, 0x46u, + 0xc4u, 0x05u, 0x00u, 0x08u, 0x04u, 0x4bu, 0x1bu, 0x68u, 0x1au, 0x00u, 0xacu, 0x32u, 0x12u, 0x88u, 0x1bu, 0x6au, + 0x50u, 0x43u, 0xc0u, 0x18u, 0x70u, 0x47u, 0xc0u, 0x46u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x1du, 0x4bu, 0x98u, 0x42u, 0x0fu, 0xd0u, 0x10u, 0xd8u, 0x40u, 0x28u, 0x2fu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x30u, 0xd0u, 0x10u, 0x28u, 0x28u, 0xd0u, 0x19u, 0x48u, 0x1eu, 0xe0u, 0x80u, 0x28u, 0x28u, 0xd0u, 0x80u, 0x23u, 0x5bu, 0x00u, 0x98u, 0x42u, 0xf7u, 0xd1u, 0x14u, 0x48u, 0x16u, 0xe0u, 0x15u, 0x4bu, 0x98u, 0x42u, 0x14u, 0xd0u, 0x08u, 0xd8u, 0xa0u, 0x23u, @@ -65,27 +65,27 @@ const uint8_t cy_m0p_image[] = { 0x02u, 0x00u, 0x50u, 0x00u, 0x05u, 0x00u, 0x52u, 0x00u, 0x10u, 0xb5u, 0x00u, 0x20u, 0xffu, 0xf7u, 0x9au, 0xffu, 0x0au, 0x4bu, 0x1cu, 0x68u, 0x23u, 0x00u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc0u, 0x18u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x0au, 0xdbu, 0x07u, 0x4bu, 0x18u, 0x68u, 0xffu, 0xf7u, 0x99u, 0xffu, 0x01u, 0x22u, 0x63u, 0x68u, 0x9au, 0x60u, - 0x9au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc8u, 0x05u, 0x00u, 0x08u, + 0x9au, 0x68u, 0x00u, 0x2au, 0xfcu, 0xd1u, 0x10u, 0xbdu, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0xccu, 0x03u, 0x00u, 0x08u, 0x02u, 0x00u, 0x50u, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0x89u, 0xb2u, 0x41u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, - 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc8u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, + 0x01u, 0x48u, 0xfcu, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x04u, 0xdau, 0x89u, 0xb2u, 0xc2u, 0x60u, 0x81u, 0x60u, 0x00u, 0x20u, 0x70u, 0x47u, 0x00u, 0x48u, 0xfcu, 0xe7u, 0x01u, 0x00u, 0x8au, 0x00u, 0x06u, 0x4bu, 0x1bu, 0x68u, 0xb0u, 0x33u, 0x1bu, 0x68u, 0xc3u, 0x18u, 0x1bu, 0x68u, 0x00u, 0x2bu, 0x03u, 0xdau, 0xc3u, 0x68u, 0x00u, 0x20u, 0x0bu, 0x60u, 0x70u, 0x47u, 0x01u, 0x48u, 0xfcu, 0xe7u, - 0xc8u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, + 0xc4u, 0x05u, 0x00u, 0x08u, 0x01u, 0x00u, 0x8au, 0x00u, 0x02u, 0x4bu, 0x1au, 0x68u, 0x00u, 0x2au, 0x00u, 0xd1u, 0x18u, 0x60u, 0x70u, 0x47u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x2cu, 0x24u, 0x60u, 0x43u, 0x12u, 0x4cu, 0x1fu, 0x00u, 0x24u, 0x68u, 0x1eu, 0x0au, 0x20u, 0x18u, 0xffu, 0x24u, 0x27u, 0x40u, 0x34u, 0x40u, 0x0fu, 0x4eu, 0x1bu, 0x0cu, 0x35u, 0x68u, 0x07u, 0x60u, 0x2eu, 0x6au, 0x44u, 0x60u, 0x83u, 0x60u, 0xacu, 0x35u, 0x2du, 0x88u, 0x80u, 0x34u, 0x6fu, 0x43u, 0x64u, 0x01u, 0x34u, 0x19u, 0xbfu, 0x19u, 0x1eu, 0x04u, 0x33u, 0x43u, 0x07u, 0x61u, 0x44u, 0x61u, 0xa3u, 0x60u, 0x00u, 0x23u, 0x83u, 0x61u, 0x05u, 0x9bu, 0xc2u, 0x61u, 0x01u, 0x62u, 0x00u, 0x2bu, - 0x01u, 0xd0u, 0x1bu, 0x88u, 0x83u, 0x81u, 0xf0u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0xc8u, 0x05u, 0x00u, 0x08u, + 0x01u, 0xd0u, 0x1bu, 0x88u, 0x83u, 0x81u, 0xf0u, 0xbdu, 0xe0u, 0x03u, 0x00u, 0x08u, 0xc4u, 0x05u, 0x00u, 0x08u, 0xf0u, 0xb5u, 0x83u, 0x68u, 0x85u, 0xb0u, 0x02u, 0xadu, 0x2bu, 0x80u, 0x15u, 0x4bu, 0x02u, 0x68u, 0x1bu, 0x68u, 0x06u, 0x6au, 0x9bu, 0x8eu, 0x47u, 0x6au, 0x9bu, 0x18u, 0x6bu, 0x80u, 0x43u, 0x68u, 0x00u, 0x95u, 0x82u, 0x6au, 0xc1u, 0x6au, 0x04u, 0x00u, 0x03u, 0x93u, 0x03u, 0x69u, 0xc0u, 0x68u, 0xffu, 0xf7u, 0xbdu, 0xffu, 0x00u, 0x21u, 0x3bu, 0x00u, 0x0au, 0x00u, 0x00u, 0x91u, 0x30u, 0x00u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x21u, 0x6bu, 0x28u, 0x00u, - 0x00u, 0xf0u, 0xb4u, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, + 0x00u, 0xf0u, 0xc6u, 0xfau, 0x00u, 0x22u, 0xabu, 0x5eu, 0x00u, 0x2bu, 0x06u, 0xdbu, 0x1fu, 0x22u, 0x13u, 0x40u, 0x1eu, 0x3au, 0x9au, 0x40u, 0x13u, 0x00u, 0x03u, 0x4au, 0x13u, 0x60u, 0x05u, 0xb0u, 0xf0u, 0xbdu, 0xc0u, 0x46u, - 0xc8u, 0x05u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, + 0xc4u, 0x05u, 0x00u, 0x08u, 0x00u, 0xe1u, 0x00u, 0xe0u, 0xf7u, 0xb5u, 0x2cu, 0x25u, 0x13u, 0x4cu, 0x68u, 0x43u, 0x26u, 0x68u, 0x69u, 0x43u, 0x34u, 0x18u, 0x25u, 0x69u, 0x01u, 0x93u, 0x71u, 0x18u, 0x00u, 0x2du, 0x19u, 0xd0u, 0x88u, 0x69u, 0x00u, 0x28u, 0x18u, 0xd1u, 0x2eu, 0x68u, 0x00u, 0x2eu, 0x15u, 0xdau, 0x67u, 0x68u, 0x01u, 0x24u, 0x26u, 0x00u, 0x4bu, 0x68u, 0x9eu, 0x40u, 0xb4u, 0x46u, 0x13u, 0x68u, 0x9eu, 0xb2u, 0x63u, 0x46u, 0x1bu, 0x04u, @@ -99,20 +99,20 @@ const uint8_t cy_m0p_image[] = { 0x00u, 0x2bu, 0x00u, 0xd0u, 0x98u, 0x47u, 0x31u, 0x00u, 0x20u, 0x69u, 0xffu, 0xf7u, 0x0du, 0xffu, 0xadu, 0xb2u, 0x00u, 0x2du, 0x09u, 0xd0u, 0x63u, 0x69u, 0x1du, 0x60u, 0x00u, 0x25u, 0x1bu, 0x68u, 0x63u, 0x6au, 0xabu, 0x42u, 0x05u, 0xd0u, 0x98u, 0x47u, 0x65u, 0x62u, 0xa5u, 0x61u, 0x63u, 0x69u, 0x1bu, 0x68u, 0x73u, 0xbdu, 0xa3u, 0x6au, - 0x00u, 0x2bu, 0xf8u, 0xd0u, 0x98u, 0x47u, 0xf6u, 0xe7u, 0xc8u, 0x05u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, + 0x00u, 0x2bu, 0xf8u, 0xd0u, 0x98u, 0x47u, 0xf6u, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x2cu, 0x23u, 0x10u, 0xb5u, 0x43u, 0x43u, 0x03u, 0x4au, 0x10u, 0x68u, 0xc0u, 0x18u, 0xffu, 0xf7u, 0xb6u, 0xffu, 0x10u, 0xbdu, 0xc0u, 0x46u, 0xe0u, 0x03u, 0x00u, 0x08u, 0xf8u, 0xb5u, 0x19u, 0x4bu, 0x0fu, 0x00u, 0x1bu, 0x68u, 0x1au, 0x00u, 0x2eu, 0x32u, 0x12u, 0x78u, 0x82u, 0x42u, 0x27u, 0xd9u, 0x00u, 0x29u, 0x25u, 0xd0u, 0x1fu, 0x25u, 0x0au, 0x68u, 0x15u, 0x40u, 0x21u, 0xd1u, 0x19u, 0x00u, 0xacu, 0x31u, 0x0cu, 0x88u, 0x11u, 0x4eu, 0x60u, 0x43u, 0x1cu, 0x6au, 0xd2u, 0x08u, - 0x04u, 0x19u, 0x29u, 0x00u, 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0xfau, 0xfeu, 0x29u, 0x00u, 0x20u, 0x00u, + 0x04u, 0x19u, 0x29u, 0x00u, 0x78u, 0x68u, 0x34u, 0x60u, 0x00u, 0xf0u, 0x0cu, 0xffu, 0x29u, 0x00u, 0x20u, 0x00u, 0xffu, 0xf7u, 0xcau, 0xfeu, 0x3au, 0x00u, 0x29u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xd7u, 0xfeu, 0x04u, 0x1eu, 0x07u, 0xd1u, 0x01u, 0x00u, 0x30u, 0x68u, 0xffu, 0xf7u, 0xbfu, 0xfeu, 0x03u, 0x00u, 0x20u, 0x00u, 0x00u, 0x2bu, - 0x00u, 0xd0u, 0x04u, 0x48u, 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xc8u, 0x05u, 0x00u, 0x08u, + 0x00u, 0xd0u, 0x04u, 0x48u, 0xf8u, 0xbdu, 0x04u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, 0xc4u, 0x05u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x01u, 0x01u, 0x8au, 0x00u, 0x03u, 0x01u, 0x8au, 0x00u, 0x10u, 0xb5u, 0x00u, 0x2au, 0x0du, 0xd1u, 0x00u, 0x29u, 0x14u, 0xd1u, 0x0bu, 0x4bu, 0x1au, 0x68u, 0x13u, 0x00u, 0xacu, 0x33u, 0x1bu, 0x88u, 0x58u, 0x43u, 0x13u, 0x6au, 0xc0u, 0x18u, 0x08u, 0x4bu, 0x18u, 0x60u, 0x08u, 0x00u, 0x10u, 0xbdu, 0x00u, 0x29u, 0x06u, 0xd0u, 0x06u, 0x4bu, 0x19u, 0x60u, 0x19u, 0x00u, 0x5au, 0x60u, 0xffu, 0xf7u, 0xabu, 0xffu, 0xf5u, 0xe7u, - 0x03u, 0x48u, 0xf3u, 0xe7u, 0xc8u, 0x05u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x78u, 0x03u, 0x00u, 0x08u, + 0x03u, 0x48u, 0xf3u, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x78u, 0x03u, 0x00u, 0x08u, 0x03u, 0x01u, 0x8au, 0x00u, 0xf7u, 0xb5u, 0x18u, 0x4fu, 0x04u, 0x00u, 0x3bu, 0x68u, 0x01u, 0x91u, 0xdeu, 0x68u, 0x33u, 0x68u, 0x83u, 0x42u, 0x26u, 0xd9u, 0x00u, 0x25u, 0xa9u, 0x42u, 0x02u, 0xd1u, 0xffu, 0xf7u, 0xadu, 0xfdu, 0x05u, 0x00u, 0x38u, 0x68u, 0x03u, 0x68u, 0x00u, 0x2bu, 0x1au, 0xdau, 0x1fu, 0x22u, 0x01u, 0x23u, 0x22u, 0x40u, @@ -125,10 +125,19 @@ const uint8_t cy_m0p_image[] = { 0x92u, 0x00u, 0x50u, 0x58u, 0x18u, 0x40u, 0x43u, 0x1eu, 0x98u, 0x41u, 0x03u, 0x4bu, 0xc0u, 0x18u, 0x70u, 0x47u, 0x02u, 0x48u, 0xfcu, 0xe7u, 0xe4u, 0x03u, 0x00u, 0x08u, 0x00u, 0x01u, 0x88u, 0x00u, 0x04u, 0x01u, 0x8au, 0x00u, 0xa6u, 0x22u, 0x05u, 0x49u, 0xd2u, 0x00u, 0x8bu, 0x58u, 0x02u, 0x20u, 0xdbu, 0x43u, 0x9bu, 0x07u, 0x02u, 0xd0u, - 0x01u, 0x23u, 0x88u, 0x58u, 0x18u, 0x40u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x09u, 0x4au, 0x83u, 0x00u, - 0x9bu, 0x18u, 0xd0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x07u, 0x22u, 0x10u, 0x40u, 0x04u, 0x28u, 0x07u, 0xd1u, - 0xc0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x1fu, 0x23u, 0x03u, 0x40u, 0x80u, 0x20u, 0x40u, 0x00u, 0x18u, 0x43u, - 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, 0xb0u, 0x23u, 0x15u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, + 0x01u, 0x23u, 0x88u, 0x58u, 0x18u, 0x40u, 0x70u, 0x47u, 0x00u, 0x00u, 0x26u, 0x40u, 0x10u, 0xb5u, 0xffu, 0xf7u, + 0xefu, 0xffu, 0x00u, 0x23u, 0x02u, 0x28u, 0x01u, 0xd1u, 0x01u, 0x4bu, 0x1bu, 0x68u, 0x18u, 0x00u, 0x10u, 0xbdu, + 0xe8u, 0x03u, 0x00u, 0x08u, 0x09u, 0x4au, 0x83u, 0x00u, 0x9bu, 0x18u, 0xd0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, + 0x07u, 0x22u, 0x10u, 0x40u, 0x04u, 0x28u, 0x07u, 0xd1u, 0xc0u, 0x22u, 0x92u, 0x00u, 0x98u, 0x58u, 0x1fu, 0x23u, + 0x03u, 0x40u, 0x80u, 0x20u, 0x40u, 0x00u, 0x18u, 0x43u, 0x70u, 0x47u, 0xc0u, 0x46u, 0x00u, 0x00u, 0x26u, 0x40u, + 0x10u, 0xb5u, 0xffu, 0xf7u, 0xe7u, 0xffu, 0x02u, 0x28u, 0x1cu, 0xd0u, 0x05u, 0xd8u, 0x00u, 0x28u, 0x14u, 0xd0u, + 0x01u, 0x28u, 0x14u, 0xd0u, 0x00u, 0x20u, 0x11u, 0xe0u, 0x12u, 0x23u, 0xffu, 0x33u, 0x98u, 0x42u, 0x14u, 0xd0u, + 0x14u, 0x23u, 0xffu, 0x33u, 0x98u, 0x42u, 0x18u, 0xd0u, 0x03u, 0x3bu, 0x98u, 0x42u, 0xf2u, 0xd1u, 0x0cu, 0x4au, + 0x0cu, 0x4bu, 0xd0u, 0x58u, 0xc0u, 0x0fu, 0xc0u, 0x03u, 0x00u, 0xe0u, 0x0bu, 0x48u, 0x10u, 0xbdu, 0x0bu, 0x4bu, + 0x18u, 0x68u, 0xfbu, 0xe7u, 0xffu, 0xf7u, 0xbau, 0xffu, 0xf8u, 0xe7u, 0x09u, 0x4bu, 0x18u, 0x69u, 0x04u, 0x23u, + 0x18u, 0x40u, 0xf3u, 0xd0u, 0x80u, 0x20u, 0x00u, 0x02u, 0xf0u, 0xe7u, 0x01u, 0x4au, 0x05u, 0x4bu, 0xe8u, 0xe7u, + 0x00u, 0x00u, 0x26u, 0x40u, 0x0cu, 0x05u, 0x00u, 0x00u, 0x00u, 0x12u, 0x7au, 0x00u, 0xecu, 0x03u, 0x00u, 0x08u, + 0x00u, 0x00u, 0x27u, 0x40u, 0x3cu, 0x05u, 0x00u, 0x00u, 0xb0u, 0x23u, 0x15u, 0x4au, 0xdbu, 0x00u, 0xd3u, 0x58u, 0x10u, 0xb5u, 0x99u, 0x03u, 0xdbu, 0x01u, 0xdbu, 0x0fu, 0x89u, 0x0bu, 0xc3u, 0x71u, 0x11u, 0x4bu, 0x01u, 0x60u, 0xd3u, 0x58u, 0x0fu, 0x24u, 0xd9u, 0x04u, 0xdbu, 0x01u, 0xdbu, 0x0du, 0x03u, 0x81u, 0xb1u, 0x23u, 0xdbu, 0x00u, 0xd3u, 0x58u, 0xc9u, 0x0cu, 0x81u, 0x80u, 0x19u, 0x00u, 0x21u, 0x40u, 0x81u, 0x72u, 0x19u, 0x09u, 0x21u, 0x40u, @@ -139,264 +148,258 @@ const uint8_t cy_m0p_image[] = { 0x80u, 0x30u, 0xffu, 0x30u, 0x0bu, 0x4bu, 0x80u, 0x00u, 0xc3u, 0x58u, 0x1au, 0x40u, 0x0au, 0x70u, 0x1au, 0x0cu, 0x22u, 0x40u, 0x18u, 0x0au, 0x8au, 0x70u, 0x1au, 0x01u, 0x20u, 0x40u, 0xe2u, 0x40u, 0x48u, 0x70u, 0x00u, 0x20u, 0x9bu, 0x00u, 0x9bu, 0x0fu, 0xcau, 0x70u, 0x0bu, 0x71u, 0x10u, 0xbdu, 0x03u, 0x48u, 0xfcu, 0xe7u, 0xc0u, 0x46u, - 0xc8u, 0x05u, 0x00u, 0x08u, 0x00u, 0x00u, 0x26u, 0x40u, 0x01u, 0x00u, 0x4au, 0x00u, 0xe0u, 0x22u, 0x01u, 0x21u, - 0x4du, 0x4bu, 0x80u, 0x00u, 0xc0u, 0x18u, 0x92u, 0x00u, 0x83u, 0x58u, 0xf0u, 0xb5u, 0x9bu, 0x06u, 0x9bu, 0x0fu, - 0x99u, 0x40u, 0x0fu, 0x23u, 0x84u, 0x58u, 0x89u, 0xb0u, 0x1cu, 0x40u, 0x20u, 0x00u, 0x01u, 0x91u, 0xffu, 0xf7u, - 0x7du, 0xffu, 0x03u, 0x28u, 0x54u, 0xd0u, 0x08u, 0xd8u, 0x01u, 0x28u, 0x13u, 0xd0u, 0x62u, 0xd9u, 0xffu, 0xf7u, - 0x67u, 0xffu, 0x42u, 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0x95u, 0x10u, 0x4du, 0x0du, 0x60u, 0x06u, 0x25u, 0x1du, 0x50u, + 0x3eu, 0x20u, 0x10u, 0x60u, 0x0eu, 0x48u, 0x3eu, 0x35u, 0x1du, 0x50u, 0x1du, 0x58u, 0x00u, 0x2du, 0xfcu, 0xdau, + 0x0cu, 0x48u, 0xfcu, 0x34u, 0x20u, 0x61u, 0x0fu, 0x60u, 0xa3u, 0x21u, 0xc9u, 0x00u, 0x5eu, 0x50u, 0x01u, 0x9bu, + 0x13u, 0x60u, 0xf7u, 0xbdu, 0x20u, 0xbfu, 0xd9u, 0xe7u, 0xc4u, 0x05u, 0x00u, 0x08u, 0x00u, 0xedu, 0x00u, 0xe0u, + 0x00u, 0x00u, 0x26u, 0x40u, 0x08u, 0x01u, 0x26u, 0x40u, 0x04u, 0x01u, 0x26u, 0x40u, 0x1eu, 0x1fu, 0x00u, 0x00u, + 0x1cu, 0x05u, 0x00u, 0x00u, 0xaau, 0xaau, 0xaau, 0xaau, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x75u, 0x01u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x9du, 0x02u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xa9u, 0x03u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x65u, 0x05u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xddu, 0x0eu, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xd9u, 0x05u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xe3u, 0x00u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0x39u, 0x02u, 0x00u, 0x10u, 0x01u, 0xb4u, 0x02u, 0x48u, + 0x84u, 0x46u, 0x01u, 0xbcu, 0x60u, 0x47u, 0x00u, 0xbfu, 0xdbu, 0x00u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, }; #endif /* defined(CY_DEVICE_PSOC6A512K) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/README.md b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/README.md index 0df7feed0bf..6f8d7eef8fe 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/README.md +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/README.md @@ -6,6 +6,11 @@ Prebuilt application images are executed on the Cortex M0+ core of the PSoC 6 du The images are provided as C arrays ready to be compiled as part of the Cortex M4 application. The Cortex M0+ application code is placed to internal flash by the Cortex M4 linker script. +Note: Each application image has a variant based on the hardware die (e.g. +psoc6_01, psoc6_02, psoc6_03, ...) it is supported on. An #ifdef at the top of +each .c file automatically controls which version is used so there is no need +to specify a particular image. + ### Images * [COMPONENT_CM0P_SLEEP](./COMPONENT_CM0P_SLEEP/README.md) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/version.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/version.xml index 39a7566b367..0f08fc2b239 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/version.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6cm0p/version.xml @@ -1 +1 @@ -1.1.0.56 +1.1.1.63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/include/cy_result.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/include/cy_result.h index f4410a6641a..83de7d44aa4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/include/cy_result.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/include/cy_result.h @@ -8,7 +8,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -69,7 +69,7 @@ typedef uint32_t cy_rslt_t; /** \cond INTERNAL */ /** Mask for the bit at position "x" */ -#define CY_BIT_MASK(x) ((1U << (x)) - 1U) +#define CY_BIT_MASK(x) ((1UL << (x)) - 1U) /** Bit position of the result type */ #define CY_RSLT_TYPE_POSITION (16U) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/include/cy_utils.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/include/cy_utils.h index ea4631b9744..7a678c5eb7f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/include/cy_utils.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/include/cy_utils.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/version.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/version.xml new file mode 100644 index 00000000000..2447c1093dc --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/core_lib/version.xml @@ -0,0 +1 @@ +1.1.1.11109 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal.h index 41b68c6f54d..e48ff7ac836 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal.h @@ -18,7 +18,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -35,7 +35,13 @@ *******************************************************************************/ /** -* \defgroup group_hal HAL Drivers +* \addtogroup group_hal HAL Drivers +* This section documents the drivers which form the stable API of the Cypress HAL. +* In order to remain portable across platforms and HAL versions, applications should +* rely only on functionality documented in this section. +* \{ +* \defgroup group_result Result Type +* \} */ #pragma once @@ -46,10 +52,12 @@ #include "cyhal_adc.h" #include "cyhal_crc.h" #include "cyhal_dac.h" +#include "cyhal_dma.h" #include "cyhal_flash.h" #include "cyhal_gpio.h" #include "cyhal_hwmgr.h" #include "cyhal_i2c.h" +#include "cyhal_ezi2c.h" #include "cyhal_interconnect.h" #include "cyhal_lptimer.h" #include "cyhal_pwm.h" diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_adc.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_adc.h index 78b836c590c..43228c9e40a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_adc.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_adc.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,8 +29,21 @@ * \addtogroup group_hal_adc ADC (Analog to Digital Converter) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress ADC. +* High level interface for interacting with the analog to digital converter (ADC). * +* Each ADC instance supports one or more selectable channels, each +* of which can perform conversions on a different pin. +* See the device datasheet for details about which pins support ADC conversion. +* +* In order to use the ADC, first call cyhal_adc_init to initialize an ADC instance. +* Then call cyhal_adc_channel_init to initialize one or more channels associated with +* that instance. +* +* All channels are single-ended. +* The values returned by the read API are relative to the ADC's voltage range, which +* is device specific. +* +* \defgroup group_hal_adc_common Common * \defgroup group_hal_adc_functions ADC Functions * \defgroup group_hal_adc_channel_functions ADC Channel Functions */ @@ -59,12 +72,6 @@ extern "C" { /** No channels available */ #define CYHAL_ADC_RSLT_NO_CHANNELS (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_ADC, 3)) - -/** -* \addtogroup group_hal_adc_functions -* \{ -*/ - /** Initialize ADC peripheral * * @param[out] obj The adc object to initialize @@ -84,13 +91,6 @@ cy_rslt_t cyhal_adc_init(cyhal_adc_t *obj, cyhal_gpio_t pin, const cyhal_clock_d */ void cyhal_adc_free(cyhal_adc_t *obj); -/** \} group_hal_adc_functions */ - -/** -* \addtogroup group_hal_adc_channel_functions -* \{ -*/ - /** Initialize a single-ended ADC channel. * * Configures the pin used by ADC. @@ -116,8 +116,6 @@ void cyhal_adc_channel_free(cyhal_adc_channel_t *obj); */ uint16_t cyhal_adc_read_u16(const cyhal_adc_channel_t *obj); -/** \} group_hal_adc_channel_functions */ - #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_analog_common.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_analog_common.h index f6a0d4c4913..6e3f78bb779 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_analog_common.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_analog_common.h @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,13 +29,13 @@ extern "C" { #endif -/** +/** * Initialize the programmable analog. This utilizes reference counting to avoid * repeatedly initializing the analog subsystem when multiple analog blocks are in use * */ void cyhal_analog_init(); -/** +/** * Uninitialize the programmable analog. This utilizes reference counting to avoid * disabling the analog subsystem until all blocks which require it have been freed. */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc.h index f464fa0da95..747f8394458 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc.h @@ -2,14 +2,14 @@ * \file cyhal_crc.h * * \brief -* Provides a high level interface for interacting with the Cypress CRC accelerator. +* Provides a high level interface for interacting with the Cypress CRC accelerator. * This interface abstracts out the chip specific details. If any chip specific * functionality is necessary, or performance is critical the low level functions * can be used directly. * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,8 +29,15 @@ * \addtogroup group_hal_crc CRC (Cyclic Redundancy Check) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress CRC. +* High level interface for interacting with the cyclic redundancy check (CRC), which provides hardware +* accelerated CRC computations. +* The CRC APIs are structured to enable usage in situations where the entire input data +* set is not available in memory at one time. Therefore, each conversion consists of three steps: +* * A single call to cyhal_crc_start, to initialize data structures for this computation +* * One or more calls to cyhal_crc_compute, to provide chunks of data. +* * A single call to cyhal_crc_finish, to finalize the computation and retrieve the result. * +* Many of the algorithm parameters can be customized; see crc_algorithm_t for more details. */ #pragma once diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc_impl.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc_impl.h index 3ab58d2ba00..0f86c272758 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc_impl.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crc_impl.h @@ -1,13 +1,13 @@ -/***************************************************************************//** +/***************************************************************************//** * \file cyhal_crc_impl.h * * Description: -* Provides a high level interface for interacting with the Cypress CRC accelerator. +* Provides a high level interface for interacting with the Cypress CRC accelerator. * This is a wrapper around the lower level PDL API. * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crypto_common.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crypto_common.h index df7bd3898db..b7f35243297 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crypto_common.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_crypto_common.h @@ -2,12 +2,12 @@ * \file cyhal_crypto_common.h * * Description: -* This file provides common defines, addresses, and functions required by drivers +* This file provides common defines, addresses, and functions required by drivers * using the Crypto block. * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dac.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dac.h index 494142e1de1..9f1e5a12e3b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dac.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dac.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,8 +29,13 @@ * \addtogroup group_hal_dac DAC (Digital to Analog Converter) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress DAC. +* High level interface for interacting with the digital to analog converter (DAC). * +* This block drives a pin with a firmware configurable voltage. See the device datasheet +* for details on which pins support DAC output. +* +* The cyhal_dac_write and cyhal_dac_read APIs are defined relative to the DAC's output +* voltage range, which is device dependent. */ #pragma once diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma.h new file mode 100644 index 00000000000..d89945d04b7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma.h @@ -0,0 +1,185 @@ +/***************************************************************************//** +* \file cyhal_dma.h +* +* \brief +* Provides a high level interface for interacting with the Cypress DMA. +* This interface abstracts out the chip specific details. If any chip specific +* functionality is necessary, or performance is critical the low level functions +* can be used directly. +* +******************************************************************************** +* \copyright +<<<<<<< HEAD +* Copyright 2018-2019 Cypress Semiconductor Corporation +======= +* Copyright 2018-2020 Cypress Semiconductor Corporation +>>>>>>> Minor consistancy cleanup for HAL documentation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_hal_dma DMA (Direct Memory Access) +* \ingroup group_hal +* \{ +* High level interface for interacting with the direct memory access (DMA). Allows the user to +* initialize and configure a DMA channel in order to trigger data transfers to +* and from memory and peripherals. The transfers occur independently of the CPU +* and are triggered in software. Multiple channels are available with +* user-selectable priority and transfer characteristics. +*/ + +#pragma once + +#include +#include +#include "cy_result.h" +#include "cyhal_hw_types.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** Invalid transfer width parameter error */ +#define CYHAL_DMA_RSLT_ERR_INVALID_TRANSFER_WIDTH (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_DMA, 0)) +/** Invalid parameter error */ +#define CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_DMA, 1)) +/** Invalid priority parameter error */ +#define CYHAL_DMA_RSLT_ERR_INVALID_PRIORITY (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_DMA, 2)) +/** Invalid src or dst addr alignment error */ +#define CYHAL_DMA_RSLT_ERR_INVALID_ALIGNMENT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_DMA, 3)) +/** Invalid burst_size paramenter error */ +#define CYHAL_DMA_RSLT_ERR_INVALID_BURST_SIZE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_DMA, 4)) +/** Channel busy error */ +#define CYHAL_DMA_RSLT_ERR_CHANNEL_BUSY (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_DMA, 5)) +/** Transfer has already been started warning */ +#define CYHAL_DMA_RSLT_WARN_TRANSFER_ALREADY_STARTED (CY_RSLT_CREATE(CY_RSLT_TYPE_WARNING, CYHAL_RSLT_MODULE_DMA, 6)) +/** Unsupported hardware error */ +#define CYHAL_DMA_RSLT_FATAL_UNSUPPORTED_HARDWARE (CY_RSLT_CREATE(CY_RSLT_TYPE_FATAL, CYHAL_RSLT_MODULE_DMA, 7)) + +/** Direction for DMA transfers. */ +typedef enum +{ + CYHAL_DMA_DIRECTION_MEM2MEM, //!< Memory to memory + CYHAL_DMA_DIRECTION_MEM2PERIPH, //!< Memory to peripheral + CYHAL_DMA_DIRECTION_PERIPH2MEM, //!< Peripheral to memory + CYHAL_DMA_DIRECTION_PERIPH2PERIPH, //!< Peripheral to peripheral +} cyhal_dma_direction_t; + +/** Flags enum of DMA events. Multiple events can be enabled. */ +typedef enum +{ + CYHAL_DMA_NO_INTR = 0, //!< No interrupt + CYHAL_DMA_TRANSFER_COMPLETE = 1 << 0, //!< Indicates that a burst or full transfer has completed + CYHAL_DMA_SRC_BUS_ERROR = 1 << 1, //!< Indicates that there is a source bus error + CYHAL_DMA_DST_BUS_ERROR = 1 << 2, //!< Indicates that there is a destination bus error + CYHAL_DMA_SRC_MISAL = 1 << 3, //!< Indicates that the source address is not aligned + CYHAL_DMA_DST_MISAL = 1 << 4, //!< Indicates that the destination address is not aligned + CYHAL_DMA_CURR_PTR_NULL = 1 << 5, //!< Indicates that the current descriptor pointer is null + CYHAL_DMA_ACTIVE_CH_DISABLED = 1 << 6, //!< Indicates that the active channel is disabled + CYHAL_DMA_DESCR_BUS_ERROR = 1 << 7, //!< Indicates that there has been a descriptor bus error +} cyhal_dma_event_t; + +/** If burst_size is used, selects whether a single trigger of the channel + * transfers a single burst of burst_size or a full transfer of size length + * (that is, every burst is triggered). This will also select when a trigger + * complete event will occur; after each burst or after the full transfer */ +typedef enum +{ + CYHAL_DMA_TRANSFER_BURST, //!< A single burst is triggered and a transfer completion event will occur after the burst + CYHAL_DMA_TRANSFER_FULL, //!< All bursts are triggered and a single transfer completion event will occur at the end of all of them +} cyhal_dma_transfer_action_t; + +/** \brief Configuration of a DMA channel. When configuring address, + * increments, and transfer width keep in mind your hardware may have more + * stringent address and data alignment requirements. */ +typedef struct +{ + uint32_t src_addr; //!< Source address + int16_t src_increment; //!< Source address auto increment amount in multiples of transfer_width + uint32_t dst_addr; //!< Destination address + int16_t dst_increment; //!< Destination address auto increment amount in multiples of transfer_width + uint8_t transfer_width; //!< Transfer width in bits. Valid values are: 8, 16, or 32 + uint32_t length; //!< Number of elements to be transferred in total + uint32_t burst_size; //!< Number of elements to be transferred per trigger. If set to 0 every element is transferred, otherwise burst_size must evenly divide length. + cyhal_dma_transfer_action_t action; //!< Sets the behavior of the channel when triggered (using start_transfer). Ignored if burst_size is not configured. +} cyhal_dma_cfg_t; + +/** Event handler for DMA interrupts */ +typedef void (*cyhal_dma_event_callback_t)(void *callback_arg, cyhal_dma_event_t event); + +/** Initialize the DMA peripheral. + * + * @param[out] obj The DMA object to initialize + * @param[in] priority The priority of this DMA operation relative to others. The number of priority levels which are supported is hardware dependent. All implementations define a CYHAL_DMA_PRIORITY_DEFAULT constant which is always valid. If supported, implementations will also define CYHAL_DMA_PRIORITY_HIGH, CYHAL_DMA_PRIORITY_MEDIUM, and CYHAL_DMA_PRIORITY_LOW. The behavior of any other value is implementation defined. See the implementation-specific DMA documentation for more details. + * @param[in] direction The direction memory is copied + * @return The status of the init request + */ +cy_rslt_t cyhal_dma_init(cyhal_dma_t *obj, uint8_t priority, cyhal_dma_direction_t direction); + +/** Free the DMA object. Freeing a DMA object while a transfer is in + progress (see @ref cyhal_dma_is_busy) is invalid. + * + * @param[in,out] obj The DMA object + */ +void cyhal_dma_free(cyhal_dma_t *obj); + +/** Setup a DMA descriptor for specified resource + * + * @param[in] obj The DMA object + * @param[in] cfg Configuration parameters for the transfer + * @return The status of the configure request + */ +cy_rslt_t cyhal_dma_configure(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg); + +/** Initiates DMA channel transfer for specified DMA object + * + * @param[in] obj The DMA object + * @return The status of the start_transfer request + */ +cy_rslt_t cyhal_dma_start_transfer(cyhal_dma_t *obj); + +/** Checks whether a transfer is pending or running on the DMA channel + * + * @param[in] obj The DMA object + * @return True if DMA channel is busy + */ +bool cyhal_dma_is_busy(cyhal_dma_t *obj); + +/** The DMA callback handler registration + * + * @param[in] obj The DMA object + * @param[in] callback The callback handler which will be invoked when an event triggers + * @param[in] callback_arg Generic argument that will be provided to the callback when called + */ +void cyhal_dma_register_callback(cyhal_dma_t *obj, cyhal_dma_event_callback_t callback, void *callback_arg); + +/** Configure DMA event enablement. + * + * @param[in] obj The DMA object + * @param[in] event The DMA event type + * @param[in] intr_priority The priority for NVIC interrupt events. The priority from the most recent call will take precedence, i.e all events will have the same priority. + * @param[in] enable True to turn on interrupts, False to turn off + */ +void cyhal_dma_enable_event(cyhal_dma_t *obj, cyhal_dma_event_t event, uint8_t intr_priority, bool enable); + +#if defined(__cplusplus) +} +#endif + +#ifdef CYHAL_DMA_IMPL_HEADER +#include CYHAL_DMA_IMPL_HEADER +#endif /* CYHAL_DMA_IMPL_HEADER */ + +/** \} group_hal_dma */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma_dmac.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma_dmac.h new file mode 100644 index 00000000000..87658a7255f --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma_dmac.h @@ -0,0 +1,94 @@ +/***************************************************************************//** +* \file cyhal_dma_dmac.h +* +* \brief +* Defines a high level interface for interacting with the Cypress DMAC. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include "cyhal_dma.h" + +/** + * \addtogroup group_hal_psoc6_dma_dmac DMAC (Direct Memory Access Controller) + * \ingroup group_hal_psoc6_dma + * \{ + * Implementation specific interface for using the DMAC DMA peripheral + */ + +#pragma once + +#ifdef CY_IP_M4CPUSS_DMAC + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** Initialize the DMAC peripheral + * + * @param[out] obj The DMA object to initialize + * @param[in] priority The priority of this DMA operation relative to others. Values must be between 0-3 with 0 being the highest priority. + * @return The status of the init request + */ +cy_rslt_t cyhal_dma_init_dmac(cyhal_dma_t *obj, uint8_t priority); + +/** Frees the DMAC specific object + * + * @param[in,out] obj The DMA object + */ +void cyhal_dma_free_dmac(cyhal_dma_t *obj); + +/** Setup a DMAC descriptor for the dma resource + * + * @param[in] obj The DMA object + * @param[in] cfg Configuration parameters for the transfer + * @return The status of the configure request + */ +cy_rslt_t cyhal_dma_configure_dmac(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg); + +/** Start a DMAC transfer + * + * Initiates DMA channel transfer for specified DMA object + * @param[in] obj The DMA object + * @return The status of the start_transfer request + */ +cy_rslt_t cyhal_dma_start_transfer_dmac(cyhal_dma_t *obj); + +/** Configure DMAC event enablement. + * + * @param[in] obj The DMA object + * @param[in] event The DMA event type + * @param[in] intrPriority The priority for NVIC interrupt events. The priority from the most recent call will take precedence, i.e all events will have the same priority. + * @param[in] enable True to turn on interrupts, False to turn off + */ +void cyhal_dma_enable_event_dmac(cyhal_dma_t *obj, cyhal_dma_event_t event, uint8_t intrPriority, bool enable); + +/** Checks whether a transfer is pending or running on the DMA channel + * + * @param[in] obj The DMA object + * @return True if DMA channel is busy + */ +bool cyhal_dma_is_busy_dmac(cyhal_dma_t *obj); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* CY_IP_M4CPUSS_DMAC */ + +/** \} group_hal_psoc6_dma_dmac */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma_dw.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma_dw.h new file mode 100644 index 00000000000..dbda5094be0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma_dw.h @@ -0,0 +1,94 @@ +/***************************************************************************//** +* \file cyhal_dma_dw.h +* +* \brief +* Defines a high level interface for interacting with the Cypress Datawire DMA. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include "cyhal_dma.h" + +/** + * \addtogroup group_hal_psoc6_dma_dw DW (Datawire) + * \ingroup group_hal_psoc6_dma + * \{ + * Implementation specific interface for using the Datawire DMA peripheral + */ + +#pragma once + +#ifdef CY_IP_M4CPUSS_DMA + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** Initialize the Datawire peripheral. + * + * @param[out] obj The DMA object to initialize + * @param[in] priority The priority of this DMA operation relative to others. Values must be between 0-3 with 0 being the highest priority. + * @return The status of the init request + */ +cy_rslt_t cyhal_dma_init_dw(cyhal_dma_t *obj, uint8_t priority); + +/** Frees the Datawire specific DMA object + * + * @param[in,out] obj The DMA object + */ +void cyhal_dma_free_dw(cyhal_dma_t *obj); + +/** Setup a Datawire descriptor for the dma resource + * + * @param[in] obj The DMA object + * @param[in] cfg Configuration prameters for the transfer + * @return The status of the configure request + */ +cy_rslt_t cyhal_dma_configure_dw(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg); + +/** Start a Datawire transfer + * + * Initiates DMA channel transfer for specified DMA object + * @param[in] obj The DMA object + * @return The status of the start_transfer request + */ +cy_rslt_t cyhal_dma_start_transfer_dw(cyhal_dma_t *obj); + +/** Configure Datawire event enablement. + * + * @param[in] obj The DMA object + * @param[in] event The DMA event type + * @param[in] intrPriority The priority for NVIC interrupt events. The priority from the most recent call will take precedence, i.e all events will have the same priority. + * @param[in] enable True to turn on interrupts, False to turn off + */ +void cyhal_dma_enable_event_dw(cyhal_dma_t *obj, cyhal_dma_event_t event, uint8_t intrPriority, bool enable); + +/** Checks whether a transfer is pending or running on the DMA channel + * + * @param[in] obj The DMA object + * @return True if DMA channel is busy + */ +bool cyhal_dma_is_busy_dw(cyhal_dma_t *obj); + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* CY_IP_M4CPUSS_DMA */ + +/** \} group_hal_psoc6_dma_dw */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma_impl.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma_impl.h new file mode 100644 index 00000000000..672d0ce6cc6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_dma_impl.h @@ -0,0 +1,73 @@ +/***************************************************************************//** +* \file cyhal_dma_impl.h +* +* \brief +* Implementation details of Cypress Datawire/DMAC DMA. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#pragma once + +#if defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M4CPUSS_DMA) + +#if defined(__cplusplus) +extern "C" { +#endif + +/** \addtogroup group_hal_psoc6_dma DMA (Direct Memory Access) + * \ingroup group_hal_psoc6 + * \{ + * DW (DataWire) is one of two DMA hardware implementations for PSOC6. DW is + * designed for low latency memory to peripheral or peripheral to memory + * transfers but can also perform memory to memory transfers and peripheral to + * peripheral transfers. + * + * DMAC (Direct Memory Access Controller) is the second of two DMA hardware + * implementations for PSOC6. DMAC is designed with high memory bandwidth for + * large memory to memory transfers but can perform peripheral to memory, + * memory to peripheral, and peripheral to peripheral transfers. + * + * Which DMA type is used is dependent on the exact hardware and number of DMA + * channels already in use. This implementation will attempt to use DMAC first + * for memory to memory transfers and Datawire otherwise but either type may be + * used. */ + +/** Default DMA channel priority */ +#define CYHAL_DMA_PRIORITY_DEFAULT CYHAL_DMA_PRIORITY_LOW +/** High DMA channel priority */ +#define CYHAL_DMA_PRIORITY_HIGH 0 +/** Medium DMA channel priority */ +#define CYHAL_DMA_PRIORITY_MEDIUM 1 +/** Low DMA channel priority */ +#define CYHAL_DMA_PRIORITY_LOW 3 + +/** \cond INTERNAL */ +/** Hal-Triggers uses bit 8 to denote a one to one trigger, whereas, the PDL + * SwTrigger function uses bit 5 to denote a one to one trigger. */ +#define HAL_TRIGGERS_1TO1_MASK (0x80) +#define PDL_TRIGGERS_1TO1_MASK (0x10) +/** \endcond */ + +/** \} group_hal_psoc6_dma */ + +#if defined(__cplusplus) +} +#endif + +#endif /* defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M4CPUSS_DMA) */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_ezi2c.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_ezi2c.h new file mode 100644 index 00000000000..b4aea5d3779 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_ezi2c.h @@ -0,0 +1,186 @@ +/***************************************************************************//** +* \file cyhal_ezi2c.h +* +* \brief +* Provides a high level interface for interacting with the Cypress EZI2C. +* This interface abstracts out the chip specific details. If any chip specific +* functionality is necessary, or performance is critical the low level functions +* can be used directly. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/****************************************************************************** +* Provides a high level Cypress EZI2C Slave interface for interacting with +* an I2C master. +* This interface abstracts out the chip specific details. If any chip specific +* functionality is necessary, or performance is critical the low level functions +* can be used directly. +* +* Cypress EZI2C emulates a common I2C EEPROM interface that acts like dual-port +* memory between the external master and your code. Once the interface is setup, +* your code can read/write freely from the specified buffer(s). +* All I2C transactions to/from the master are handled automatically. +*******************************************************************************/ + +/** +* \addtogroup group_hal_ezi2c EZI2C (Inter-Integrated Circuit) +* \ingroup group_hal +* \{ +* High level interface for interacting with the Cypress EZ Inter-Integrated Circuit (EZI2C). +*/ + +#pragma once + +#include +#include +#include "cy_result.h" +#include "cyhal_hw_types.h" +#include "cyhal_modules.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +/** The requested resource type is invalid */ +#define CYHAL_EZI2C_RSLT_ERR_INVALID_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_EZI2C, 0)) +/** Can not reach desired data rate */ +#define CYHAL_EZI2C_RSLT_ERR_CAN_NOT_REACH_DR (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_EZI2C, 1)) +/** Number of addresses is not valid */ +#define CYHAL_EZI2C_RSLT_ERR_NUM_ADDR_NOT_VALID (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_EZI2C, 2)) +/** Number of addresses is not valid */ +#define CYHAL_EZI2C_RSLT_ERR_CHECK_USER_CONFIG (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_EZI2C, 3)) + +/** Size of Sub-Address */ +typedef enum +{ + CYHAL_EZI2C_SUB_ADDR8_BITS, /**< Sub-address is 8 bits */ + CYHAL_EZI2C_SUB_ADDR16_BITS /**< Sub-address is 16 bits */ +} cyhal_ezi2c_sub_addr_size_t; + +/** Size of Sub-Address */ +typedef enum +{ + CYHAL_EZI2C_DATA_RATE_100KHZ = 100000, + CYHAL_EZI2C_DATA_RATE_400KHZ = 400000, + CYHAL_EZI2C_DATA_RATE_1MHZ = 1000000 +} cyhal_ezi2c_data_rate_t; + +/** Return codes of ezi2c */ +typedef enum +{ + /** Each EZI2C slave status is encoded in a separate bit, therefore multiple bits may be set to indicate the current status */ + CYHAL_EZI2C_STATUS_OK = 0x0UL, /**< Operation completed successfully */ + CYHAL_EZI2C_STATUS_READ1 = 0x01UL, /**< The Read transfer intended for the primary slave address is complete */ + CYHAL_EZI2C_STATUS_WRITE1 = 0x02UL, /**< The Write transfer intended for the primary slave address is complete */ + CYHAL_EZI2C_STATUS_READ2 = 0x04UL, /**< The Read transfer intended for the secondary slave address is complete */ + CYHAL_EZI2C_STATUS_WRITE2 = 0x08UL, /**< The Write transfer intended for the secondary slave address is complete */ + CYHAL_EZI2C_STATUS_BUSY = 0x10UL, /**< A transfer intended for the primary address or secondary address is in progress */ + CYHAL_EZI2C_STATUS_ERR = 0x20UL /**< An error occurred during a transfer intended for the primary or secondary slave address */ + +} cyhal_ezi2c_status_t; + +/** Enum to enable/disable/report interrupt cause flags. When an event is triggered + * the status can be obtained by calling \ref cyhal_ezi2c_get_activity_status. + * \note This is a placeholder for now. It may be extended in the future. + */ +typedef enum +{ + CYHAL_EZI2C_EVENT_NONE = 0, /* No event */ +} cyhal_ezi2c_event_t; + +/** Handler for I2C events */ +typedef void (*cyhal_ezi2c_event_callback_t)(void *callback_arg, cyhal_ezi2c_event_t event); + +/** Initial EZI2C sub configuration */ +typedef struct +{ + /** The 7-bit right justified primary slave address */ + uint8_t slave_address; + /** A pointer to the data buffer for the primary/secondary slave address */ + uint8_t *buf; + /** The size of the buffer assigned to the primary/secondary slave address */ + uint32_t buf_size; + /** The Read/Write boundary within the buffer assigned to the primary/secondary slave address. + * This specifies the number of data bytes from the beginning of the buffer with + * read and write access for the master. Data bytes at this value or greater are read + * only by the master */ + uint32_t buf_rw_boundary; +} cyhal_ezi2c_slave_cfg_t; + +/** Initial EZI2C configuration */ +typedef struct +{ + /** Number of addresses (one or two). If set "true" - use two addresses otherwise ("false") one */ + bool two_addresses; + /** When set, the slave will wake the device from Deep Sleep on an address match */ + bool enable_wake_from_sleep; + /** Maximum frequency that the I2C Slave bus runs at. Supports standard data rates of 100/400/1000 kbps */ + cyhal_ezi2c_data_rate_t data_rate; + /** Refer to cyhal_ezi2c_slave_cfg_t for details. This config structure is mandatory. */ + cyhal_ezi2c_slave_cfg_t slave1_cfg; + /** Refer to cyhal_ezi2c_slave_cfg_t for details. This config structure is optional. */ + /** Set it if user want to use dual-port addressing otherwise leave blank */ + cyhal_ezi2c_slave_cfg_t slave2_cfg; + /** The size of the sub-address, can either be 8 or 16 bits */ + cyhal_ezi2c_sub_addr_size_t sub_address_size; +} cyhal_ezi2c_cfg_t; + +/** Initialize the EZI2C (slave), and configures its specifieds pins and clock. + * + * @param[out] obj The I2C object + * @param[in] sda The sda pin + * @param[in] scl The scl pin + * @param[in] clk The clock to use can be shared, if NULL a new clock will be allocated + * @param[in] cfg The ezi2c configuration (refer to cyhal_ezi2c_cfg_t for details) + * @return The status of the init request + */ +cy_rslt_t cyhal_ezi2c_init(cyhal_ezi2c_t *obj, cyhal_gpio_t sda, cyhal_gpio_t scl, const cyhal_clock_divider_t *clk, const cyhal_ezi2c_cfg_t *cfg); + +/** Deinitialize the ezi2c object + * + * @param[in,out] obj The ezi2c object + */ +void cyhal_ezi2c_free(cyhal_ezi2c_t *obj); + +/** + * EZI2C slave get activity status + * This function returns a non-zero value if an I2C Read or Write + * cycle has occurred since the last time this function was called. + * + * @param[in] obj The EZI2C object + * + * @return The status of the EZI2C (see cyhal_ezi2c_status_t for details) + */ +cyhal_ezi2c_status_t cyhal_ezi2c_get_activity_status(cyhal_ezi2c_t *obj); + +/** The EZI2C event callback handler registration + * + * @param[in] obj The EZI2C object + * @param[in] callback The callback handler which will be invoked when an event triggers + * @param[in] callback_arg Generic argument that will be provided to the callback when called + */ +void cyhal_ezi2c_register_callback(cyhal_ezi2c_t *obj, cyhal_ezi2c_event_callback_t callback, void *callback_arg); + + + +#if defined(__cplusplus) +} +#endif + +/** \} group_hal_ezi2c */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_flash.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_flash.h index 9eefbed5148..e5d3f4a24fd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_flash.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_flash.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,7 +29,11 @@ * \addtogroup group_hal_flash Flash * \ingroup group_hal * \{ -* Flash HAL high-level description +* High level interface for interacting with internal flash memory. +* +* This driver allows data to be read from and written to flash. It also +* provides the ability to obtain information about the address and +* characteristics of the flash block(s) contained on the device. */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_gpio.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_gpio.h index eea6697e248..ecd038fc1dc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_gpio.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_gpio.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,7 +29,54 @@ * \addtogroup group_hal_gpio GPIO (General Purpose Input Output) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress GPIO. +* High level interface for configuring and interacting with general purpose input/outputs (GPIO). +* +* The GPIO driver provides functions to configure and initialize GPIO, and to read and write data to the pin. +* The driver also supports interrupt generation on GPIO signals with rising, falling or both edges. +* +* \note The APIs in this driver need not be used if a GPIO is to be used as an input or output of peripherals like I2C or PWM. +* The respective peripheral's driver will utilize the GPIO interface to configure and initialize its GPIO pins. +* +* \section subsection_gpio_features Features +* * Configurable GPIO pin direction - \ref cyhal_gpio_direction_t +* * Configurable GPIO pin drive modes - \ref cyhal_gpio_drive_mode_t +* * Configurable analog and digital characteristics +* * Configurable edge-triggered interrupts and callback assignment on GPIO events - \ref cyhal_gpio_event_t +* +* \section subsection_gpio_quickstart Quick Start +* \ref cyhal_gpio_init can be used for a simple GPIO initialization by providing the pin number (pin), pin direction (direction), +* pin drive mode (drive_mode) and the initial value on the pin (init_val). +* +* \section subsection_gpio_sample_snippets Code Snippets +* +* \subsection subsection_gpio_snippet_1 Snippet 1: Reading value from GPIO +* The following snippet initializes GPIO pin \ref P0_0 as an input with high impedance digital drive mode and initial value = false (low). A value is read +* from the pin and stored to a uint8_t variable (read_val). + +* \snippet gpio.c snippet_cyhal_gpio_read + +* \subsection subsection_gpio_snippet_2 Snippet 2: Writing value to a GPIO +* The following snippet initializes GPIO pin \ref P0_0 as an output pin with strong drive mode and initial value = false (low). +* A value = true (high) is written to the output driver. + +* \snippet gpio.c snippet_cyhal_gpio_write + +* \subsection subsection_gpio_snippet_3 Snippet 3: Reconfiguring a GPIO +* The following snippet shows how to reconfigure a GPIO pin during run-time using the firmware. The GPIO pin \ref P0_0 +* is first initialized as an output pin with strong drive mode. The pin is then reconfigured as an input with high impedance digital drive mode. +* \note \ref cyhal_gpio_configure only changes the direction and the drive_mode +* of the pin. Previously set pin value is retained. +* +* \snippet gpio.c snippet_cyhal_gpio_reconfigure + +* \subsection subsection_gpio_snippet_4 Snippet 4: Interrupts on GPIO events +* GPIO events can be mapped to an interrupt and assigned to a callback function. The callback function needs to be first registered and +* then the event needs to be enabled. +** The following snippet initializes GPIO pin \ref P0_0 as an input pin. It registers a callback function and enables detection +* of a falling edge event to trigger the callback. +* \note If no argument needs to be passed to the callback function then a NULL can be passed during registering.
+* +* \snippet gpio.c snippet_cyhal_gpio_interrupt */ #pragma once @@ -43,6 +90,7 @@ extern "C" { #endif /* __cplusplus */ + /******************************************************************************* * Defines *******************************************************************************/ @@ -70,8 +118,14 @@ typedef enum { } cyhal_gpio_direction_t; /** Pin drive mode */ + +/** \note When the drive_mode of the pin is set to CYHAL_GPIO_DRIVE_PULL_NONE , + * it is set to CYHAL_GPIO_DRIVE_STRONG if the direction + * of the pin is CYHAL_GPIO_DIR_OUTPUT or CYHAL_GPIO_DIR_BIDIRECTIONAL. + * If not, the drive_mode of the pin is set to CYHAL_GPIO_DRIVE_NONE. + */ typedef enum { - CYHAL_GPIO_DRIVE_NONE, /**< No drive; Hi-Z */ + CYHAL_GPIO_DRIVE_NONE, /**< Digital Hi-Z */ CYHAL_GPIO_DRIVE_ANALOG, /**< Analog Hi-Z */ CYHAL_GPIO_DRIVE_PULLUP, /**< Pull-up resistor */ CYHAL_GPIO_DRIVE_PULLDOWN, /**< Pull-down resistor */ @@ -89,16 +143,17 @@ typedef void (*cyhal_gpio_event_callback_t)(void *callback_arg, cyhal_gpio_event * Functions *******************************************************************************/ -/** Initialize the GPIO pin +/** Initialize the GPIO pin
+ * See \ref subsection_gpio_snippet_1. * - * @param[in] pin The GPIO pin to initialize - * @param[in] direction The pin direction - * @param[in] drvMode The pin drive mode - * @param[in] initVal Initial value on the pin + * @param[in] pin The GPIO pin to initialize + * @param[in] direction The pin direction + * @param[in] drive_mode The pin drive mode + * @param[in] init_val Initial value on the pin * * @return The status of the init request */ -cy_rslt_t cyhal_gpio_init(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cyhal_gpio_drive_mode_t drvMode, bool initVal); +cy_rslt_t cyhal_gpio_init(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cyhal_gpio_drive_mode_t drive_mode, bool init_val); /** Uninitialize the gpio peripheral and the cyhal_gpio_t object * @@ -106,7 +161,8 @@ cy_rslt_t cyhal_gpio_init(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cy */ void cyhal_gpio_free(cyhal_gpio_t pin); -/** Configure the GPIO pin +/** Configure the GPIO pin
+ * See \ref subsection_gpio_snippet_3. * * @param[in] pin The GPIO pin * @param[in] direction The pin direction @@ -116,27 +172,30 @@ void cyhal_gpio_free(cyhal_gpio_t pin); */ cy_rslt_t cyhal_gpio_configure(cyhal_gpio_t pin, cyhal_gpio_direction_t direction, cyhal_gpio_drive_mode_t drvMode); -/** Set the output value for the pin. This only works for output & in_out pins. +/** Set the output value for the pin. This only works for output & in_out pins.
+ * See \ref subsection_gpio_snippet_2. * * @param[in] pin The GPIO object * @param[in] value The value to be set (high = true, low = false) */ void cyhal_gpio_write(cyhal_gpio_t pin, bool value); -/** Read the input value. This only works for input & in_out pins. +/** Read the input value. This only works for \ref CYHAL_GPIO_DIR_INPUT & \ref CYHAL_GPIO_DIR_BIDIRECTIONAL pins.
+ * See \ref subsection_gpio_snippet_1. * * @param[in] pin The GPIO object * @return The value of the IO (true = high, false = low) */ bool cyhal_gpio_read(cyhal_gpio_t pin); -/** Toggle the output value - * +/** Toggle the output value
+ * See \ref subsection_gpio_snippet_4. * @param[in] pin The GPIO object */ void cyhal_gpio_toggle(cyhal_gpio_t pin); -/** Register/clear a callback handler for pin events +/** Register/clear a callback handler for pin events
+ * See \ref subsection_gpio_snippet_4. * * @param[in] pin The pin number * @param[in] callback The function to call when the specified event happens. Pass NULL to unregister the handler. @@ -144,17 +203,18 @@ void cyhal_gpio_toggle(cyhal_gpio_t pin); */ void cyhal_gpio_register_callback(cyhal_gpio_t pin, cyhal_gpio_event_callback_t callback, void *callback_arg); -/** Enable or Disable the specified GPIO event +/** Enable or Disable the specified GPIO event
+ * See \ref subsection_gpio_snippet_4. * * @param[in] pin The GPIO object * @param[in] event The GPIO event - * @param[in] intrPriority The priority for NVIC interrupt events + * @param[in] intr_priority The priority for NVIC interrupt events * @param[in] enable True to turn on interrupts, False to turn off */ -void cyhal_gpio_enable_event(cyhal_gpio_t pin, cyhal_gpio_event_t event, uint8_t intrPriority, bool enable); +void cyhal_gpio_enable_event(cyhal_gpio_t pin, cyhal_gpio_event_t event, uint8_t intr_priority, bool enable); /******************************************************************************* -* Backward compatibility macro. The following code is DEPRECATED and must +* Backward compatibility macro. The following code is DEPRECATED and must * not be used in new projects *******************************************************************************/ /** \cond INTERNAL */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_gpio_impl.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_gpio_impl.h index 5878cf9b2bf..5898c715b67 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_gpio_impl.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_gpio_impl.h @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_resources.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_resources.h index f5da12987ff..74733c9aa58 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_resources.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_resources.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -23,7 +23,7 @@ *******************************************************************************/ /** -* \addtogroup group_hal_psoc6_hw_types +* \addtogroup group_hal_psoc6_hw_types * \ingroup group_hal_psoc6 * \{ */ @@ -46,6 +46,7 @@ typedef enum CYHAL_RSC_CRYPTO, /*!< Crypto hardware accelerator */ CYHAL_RSC_DAC, /*!< Digital to analog converter */ CYHAL_RSC_DMA, /*!< DMA controller */ + CYHAL_RSC_DW, /*!< Datawire DMA controller */ CYHAL_RSC_GPIO, /*!< General purpose I/O pin */ CYHAL_RSC_I2S, /*!< I2S communications block */ CYHAL_RSC_LCD, /*!< Segment LCD controller */ @@ -63,8 +64,8 @@ typedef enum CYHAL_RSC_INVALID, /*!< Placeholder for invalid type */ } cyhal_resource_t; -/** - * @brief Represents a particular instance of a resource on the chip +/** + * @brief Represents a particular instance of a resource on the chip */ typedef struct { @@ -74,7 +75,7 @@ typedef struct * The channel number, if the resource type defines multiple channels * per block instance. Otherwise, 0 */ uint8_t channel_num; -} cyhal_resource_inst_t; +} cyhal_resource_inst_t; #if defined(__cplusplus) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_types.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_types.h index 5548ffc6b86..dd7bc51adac 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_types.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hw_types.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -23,10 +23,18 @@ *******************************************************************************/ /** -* \addtogroup group_hal_psoc6_hw_types Implementation-defined types -* \ingroup group_hal_psoc6 +* \addtogroup group_hal_psoc6 PSoC 6 Implementation Specific * \{ -* Aliases for types which are part of the public HAL interface but whose representations are +* This section provides details about the PSoC 6 implementation of the Cypress HAL. +* All information within this section is platform specific and is provided for reference. +* Portable application code should depend only on the APIs and types which are documented +* in the @ref group_hal section. +*/ + +/** +* \addtogroup group_hal_psoc6_hw_types PSoC6 Specific Hardware Types +* \{ +* Aliases for types which are part of the public HAL interface but whose representations * need to vary per HAL implementation */ @@ -35,6 +43,7 @@ #include "cy_pdl.h" #include "cyhal_hw_resources.h" #include "cyhal_pin_package.h" +#include "cyhal_triggers.h" #include #if defined(CYHAL_UDB_SDIO) @@ -47,7 +56,9 @@ extern "C" { #ifndef CYHAL_ISR_PRIORITY_DEFAULT -/** Default priority for interrupts */ +/** Priority that is applied by default to all drivers when initalized. Priorities can be + * overridden on each driver as part of enabling events. + */ #define CYHAL_ISR_PRIORITY_DEFAULT (7) #endif @@ -56,6 +67,7 @@ extern "C" { */ #define CYHAL_CRC_IMPL_HEADER "cyhal_crc_impl.h" //!< Implementation specific header for CRC +#define CYHAL_DMA_IMPL_HEADER "cyhal_dma_impl.h" //!< Implementation specific header for DMA #define CYHAL_GPIO_IMPL_HEADER "cyhal_gpio_impl.h" //!< Implementation specific header for GPIO #define CYHAL_PWM_IMPL_HEADER "cyhal_pwm_impl.h" //!< Implementation specific header for PWM #define CYHAL_SYSTEM_IMPL_HEADER "cyhal_system_impl.h" //!< Implementation specific header for System @@ -67,7 +79,6 @@ extern "C" { /** */ typedef uint32_t cyhal_source_t; //!< Routable signal source -typedef uint32_t cyhal_dest_t; //!< Routable signal destination /** Callbacks for Sleep and Deepsleep APIs */ #define cyhal_system_callback_t cy_stc_syspm_callback_t @@ -98,13 +109,6 @@ typedef struct { void* callback_arg; } cyhal_event_callback_data_t; -/** -* \addtogroup group_hal_psoc6_hw_types_handle Instance Handles -* \{ -* Structs which retain data which needs to persist across HAL API calls. From the perspective of the -* generic HAL interface, these are opaque; the contents are specific to this implementation. -*/ - /** @brief ADC object */ typedef struct { #ifdef CY_IP_MXS40PASS_SAR @@ -131,16 +135,6 @@ typedef struct { #endif } cyhal_adc_channel_t; -/** @brief Comparator object */ -typedef struct { -#if defined(CY_IP_MXLPCOMP_INSTANCES) || defined(PASS_NR_CTBS) - /* TODO: define */ - void * TODO_define; -#else - void *empty; -#endif -} cyhal_comp_t; - /** @brief CRC object */ typedef struct { #if defined(CY_IP_MXCRYPTO_INSTANCES) || defined(CPUSS_CRYPTO_PRESENT) @@ -163,8 +157,37 @@ typedef struct { /** @brief DMA object */ typedef struct { -#if defined(CY_IP_M4CPUSS_DMAC_INSTANCES) || defined(CY_IP_M4CPUSS_DMA_INSTANCES) - cyhal_resource_inst_t resource; +#if defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M4CPUSS_DMA) + cyhal_resource_inst_t resource; + union + { +#ifdef CY_IP_M4CPUSS_DMA + cy_stc_dma_channel_config_t dw; +#endif +#ifdef CY_IP_M4CPUSS_DMAC + cy_stc_dmac_channel_config_t dmac; +#endif + } channel_config; + union + { +#ifdef CY_IP_M4CPUSS_DMA + cy_stc_dma_descriptor_config_t dw; +#endif +#ifdef CY_IP_M4CPUSS_DMAC + cy_stc_dmac_descriptor_config_t dmac; +#endif + } descriptor_config; + union + { +#ifdef CY_IP_M4CPUSS_DMA + cy_stc_dma_descriptor_t dw; +#endif +#ifdef CY_IP_M4CPUSS_DMAC + cy_stc_dmac_descriptor_t dmac; +#endif + } descriptor; + uint32_t irq_cause; + cyhal_event_callback_data_t callback_data; #else void *empty; #endif @@ -199,53 +222,41 @@ typedef struct { #endif } cyhal_i2c_t; -/** @brief I2S object */ +/** @brief EZI2C object */ typedef struct { -#ifdef CY_IP_MXAUDIOSS_INSTANCES - /* TODO: define */ - void * TODO_define; +#ifdef CY_IP_MXSCB + CySCB_Type* base; + cyhal_resource_inst_t resource; + cyhal_gpio_t pin_sda; + cyhal_gpio_t pin_scl; + cyhal_clock_divider_t clock; + bool is_shared_clock; + cy_stc_scb_ezi2c_context_t context; + uint32_t irq_cause; + cyhal_event_callback_data_t callback_data; #else void *empty; #endif -} cyhal_i2s_t; +} cyhal_ezi2c_t; /** @brief LPTIMER object */ typedef struct { #ifdef CY_IP_MXS40SRSS_MCWDT_INSTANCES - MCWDT_STRUCT_Type *base; - cyhal_resource_inst_t resource; - cyhal_event_callback_data_t callback_data; + MCWDT_STRUCT_Type *base; + cyhal_resource_inst_t resource; + cyhal_event_callback_data_t callback_data; #else void *empty; #endif } cyhal_lptimer_t; -/** @brief OpAmp object */ -typedef struct { -#ifdef PASS_NR_CTBS - /* TODO: define */ - void * TODO_define; -#else - void *empty; -#endif -} cyhal_opamp_t; - -/** @brief PDM-PCM object */ -typedef struct { -#ifdef CY_IP_MXAUDIOSS_INSTANCES - /* TODO: define */ - void * TODO_define; -#else - void *empty; -#endif -} cyhal_pdm_pcm_t; - /** @brief PWM object */ typedef struct { #ifdef CY_IP_MXTCPWM TCPWM_Type* base; cyhal_resource_inst_t resource; cyhal_gpio_t pin; + cyhal_gpio_t pin_compl; cyhal_clock_divider_t clock; uint32_t clock_hz; bool dedicated_clock; @@ -280,12 +291,18 @@ typedef struct { #if defined(CY_IP_MXCRYPTO_INSTANCES) || defined(CPUSS_CRYPTO_PRESENT) CRYPTO_Type* base; cyhal_resource_inst_t resource; +#else + void *empty; #endif } cyhal_trng_t; /** @brief RTC object */ typedef struct { - uint8_t placeholder; +#ifdef CY_IP_MXS40SRSS_RTC + cy_stc_rtc_dst_t dst; +#else + void *empty; +#endif } cyhal_rtc_t; /** @brief SDHC object */ @@ -457,10 +474,9 @@ typedef struct { uint8_t placeholder; } cyhal_wdt_t; -/** \} group_hal_psoc6_hw_types_handles */ - #if defined(__cplusplus) } #endif /* __cplusplus */ /** \} group_hal_psoc6_hw_types */ +/** \} group_hal_psoc6 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hwmgr.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hwmgr.h index 35f076cf78f..62c5277c0cc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hwmgr.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_hwmgr.h @@ -8,7 +8,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -28,7 +28,14 @@ * \addtogroup group_hal_hwmgr HWMGR (Hardware Manager) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress Hardware Manager. +* High level interface for interacting with the Hardware Manager. +* +* This provides two related functions: +* * Allows HAL drivers (or application firmware) to mark specific hardware blocks +* as consumed, so that other firmware will not accidentally try to use the block +* for a conflicting purpose. +* * For resources which are interchangeable, such as clock dividers, provides allocation +* and reservation of an available instance (if one exists). */ #pragma once @@ -80,13 +87,6 @@ void cyhal_hwmgr_free(const cyhal_resource_inst_t* obj); */ cy_rslt_t cyhal_hwmgr_allocate(cyhal_resource_t type, cyhal_resource_inst_t* obj); -/** Allocate (pick and reserve) an DMA resource and provide a reference to it. - * - * @param[out] obj The resource object that was allocated - * @return The status of the reserve request - */ -cy_rslt_t cyhal_hwmgr_allocate_dma(cyhal_resource_inst_t* obj); - /** Allocate (pick and reserve) an Clock Divider resource and provide a reference to it. * * @param[out] obj The resource object that was allocated diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_i2c.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_i2c.h index 35e9cc32469..abfab7dd1ee 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_i2c.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_i2c.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,10 +29,63 @@ * \addtogroup group_hal_i2c I2C (Inter-Integrated Circuit) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress I2C. -* -* \defgroup group_hal_i2c_master Master -* \defgroup group_hal_i2c_slave Slave +* High level interface for interacting with the I2C resource. +* +* The I2C protocol is a synchronous serial interface protocol. This driver supports +* both master and slave mode of operation. The communication frequency and address (for slave operation) can be +* configured. +* +* \section section_i2c_features Features +* +* * Master or slave functionality +* * Configurable slave address +* * Configurable data rates +* * Configurable interrupt and callback assignment from I2C events - \ref cyhal_i2c_event_t +* +* \section section_i2c_quickstart Quick Start +* Initialize an I2C instance using the \ref cyhal_i2c_init and provide sda (I2C data) and scl (I2C clock) pins.
+* By default, this initializes the resource as an I2C master.
+* Configure the behavior (master/slave) and the interface (bus frequency, slave address) using the \ref cyhal_i2c_configure function.
+* See \ref subsection_i2c_snippet_1 for example initialization as master or slave. +* \note The clock parameter (const cyhal_clock_divider_t *clk) is optional and can be set +* to NULL to generate and use an available clock resource with a default frequency (CYHAL_I2C_MASTER_DEFAULT_FREQ). +* +* \section section_i2c_snippets Code Snippets +* +* \subsection subsection_i2c_snippet_1 Snippet 1: I2C Initialization and Configuration +* This snippet initializes an I2C resource as master or slave and assigns +* the sda and scl pins. +* +* Initializing as I2C master +* \snippet i2c.c snippet_cyhal_i2c_master_init +* +* Initializing as I2C slave +* \snippet i2c.c snippet_cyhal_i2c_slave_init +* +* \subsection subsection_i2c_snippet_2 Snippet 2: Handling events +* This snippet shows how to enable and handle I2C events using \ref cyhal_i2c_enable_event and \ref cyhal_i2c_register_callback.
+* The callback parameter of \ref cyhal_i2c_register_callback is used to pass the callback handler that will be invoked when an event occurs.
+* The event parameter of \ref cyhal_i2c_enable_event is used to pass the bitmasks of events ( \ref cyhal_i2c_event_t) to be enabled. +* +* \snippet i2c.c snippet_cyhal_handle_i2c_events +* +* \subsection subsection_i2c_snippet_3 Snippet 3: I2C Master Asynchronous Transfer +* This snippet shows how to implement asynchronous transfers using \ref cyhal_i2c_master_transfer_async.
+* \ref cyhal_i2c_abort_async is used to stop the transfer, in this case when an error occurs. +* +* \snippet i2c.c snippet_cyhal_async_transfer +* +* \section subsection_i2c_moreinformation More Information +* +* Peripheral Driver Library (PDL) +* * +PSoC 6 PDL: SCB (Serial Communication Block) +* +* Code examples (Github) +* * +PSoC 6 MCU: I2C Master +* * +PSoC 6 MCU: I2C Slave Using Callbacks */ #pragma once @@ -47,6 +100,7 @@ extern "C" { #endif + /** The requested resource type is invalid */ #define CYHAL_I2C_RSLT_ERR_INVALID_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_I2C, 0)) /** Can not reach desired data rate */ @@ -57,42 +111,48 @@ extern "C" { /** Enum to enable/disable/report interrupt cause flags. */ typedef enum { - CYHAL_I2C_EVENT_NONE = 0, /* No event */ - CYHAL_I2C_SLAVE_READ_EVENT = 1 << 1, /* Indicates that the slave was addressed and the master wants to read data. */ - CYHAL_I2C_SLAVE_WRITE_EVENT = 1 << 2, /* Indicates that the slave was addressed and the master wants to write data. */ - CYHAL_I2C_SLAVE_RD_IN_FIFO_EVENT = 1 << 3, /* All slave data from the configured Read buffer has been loaded into the TX FIFO. */ - CYHAL_I2C_SLAVE_RD_BUF_EMPTY_EVENT = 1 << 4, /* The master has read all data out of the configured Read buffer. */ - CYHAL_I2C_SLAVE_RD_CMPLT_EVENT = 1 << 5, /* Indicates the master completed reading from the slave (set by the master NAK or Stop) */ - CYHAL_I2C_SLAVE_WR_CMPLT_EVENT = 1 << 6, /* Indicates the master completed writing to the slave (set by the master Stop or Restart)*/ - CYHAL_I2C_SLAVE_ERR_EVENT = 1 << 7, /* Indicates the I2C hardware detected an error. */ - CYHAL_I2C_MASTER_WR_IN_FIFO_EVENT = 1 << 17, /* All data specified by Cy_SCB_I2C_MasterWrite has been loaded into the TX FIFO. */ - CYHAL_I2C_MASTER_WR_CMPLT_EVENT = 1 << 18, /* The master write started by Cy_SCB_I2C_MasterWrite is complete.*/ - CYHAL_I2C_MASTER_RD_CMPLT_EVENT = 1 << 19, /* The master read started by Cy_SCB_I2C_MasterRead is complete.*/ - CYHAL_I2C_MASTER_ERR_EVENT = 1 << 20, /* Indicates the I2C hardware has detected an error. */ + CYHAL_I2C_EVENT_NONE = 0, /**< No event */ + CYHAL_I2C_SLAVE_READ_EVENT = 1 << 1, /**< Indicates that the slave was addressed and the master wants to read data. */ + CYHAL_I2C_SLAVE_WRITE_EVENT = 1 << 2, /**< Indicates that the slave was addressed and the master wants to write data. */ + CYHAL_I2C_SLAVE_RD_IN_FIFO_EVENT = 1 << 3, /**< All slave data from the configured Read buffer has been loaded into the TX FIFO. */ + CYHAL_I2C_SLAVE_RD_BUF_EMPTY_EVENT = 1 << 4, /**< The master has read all data out of the configured Read buffer. */ + CYHAL_I2C_SLAVE_RD_CMPLT_EVENT = 1 << 5, /**< Indicates the master completed reading from the slave (set by the master NAK or Stop) */ + CYHAL_I2C_SLAVE_WR_CMPLT_EVENT = 1 << 6, /**< Indicates the master completed writing to the slave (set by the master Stop or Restart)*/ + CYHAL_I2C_SLAVE_ERR_EVENT = 1 << 7, /**< Indicates the I2C hardware detected an error. */ + CYHAL_I2C_MASTER_WR_IN_FIFO_EVENT = 1 << 17, /**< All data specified by cyhal_i2c_master_transfer_async has been loaded into the TX FIFO. */ + CYHAL_I2C_MASTER_WR_CMPLT_EVENT = 1 << 18, /**< The master write started by cyhal_i2c_master_transfer_async is complete.*/ + CYHAL_I2C_MASTER_RD_CMPLT_EVENT = 1 << 19, /**< The master read started by cyhal_i2c_master_transfer_async is complete.*/ + CYHAL_I2C_MASTER_ERR_EVENT = 1 << 20, /**< Indicates the I2C hardware has detected an error. */ } cyhal_i2c_event_t; + /** Handler for I2C events */ typedef void (*cyhal_i2c_event_callback_t)(void *callback_arg, cyhal_i2c_event_t event); + /** @brief Initial I2C configuration */ typedef struct { - bool is_slave; /* I2C mode, is the device a master or slave */ - uint16_t address; /* Address of this slave device (7-bit), should be set to 0 for master */ - uint32_t frequencyhal_hz; /* Frequency that the I2C bus runs at */ + bool is_slave; /**< Operates as a slave when set to (true), else as a master (false) */ + uint16_t address; /**< Address of this slave resource (7-bit), should be set to 0 for master */ + uint32_t frequencyhal_hz; /**< Frequency that the I2C bus runs at (I2C data rate in bits per second)
+ Refer to the device datasheet for the supported I2C data rates */ } cyhal_i2c_cfg_t; -/** Initialize the I2C peripheral, and configures its specifieds pins. By default - * it is setup as a Master running at 400kHz. This can be changed by calling - * cyhal_i2c_configure(). + +/** Initialize the I2C peripheral, and configures its specified pins. By default + * it is configured as a Master with a bus frequency = CYHAL_I2C_MASTER_DEFAULT_FREQ. + * Use \ref cyhal_i2c_configure() to change the default behavior.
* NOTE: Master/Slave specific functions only work when the block is configured - * to be in that mode. + * to be in that mode.
+ * See \ref subsection_i2c_snippet_1 * * @param[out] obj The I2C object * @param[in] sda The sda pin * @param[in] scl The scl pin * @param[in] clk The clock to use can be shared, if not provided a new clock will be allocated * @return The status of the init request + * */ cy_rslt_t cyhal_i2c_init(cyhal_i2c_t *obj, cyhal_gpio_t sda, cyhal_gpio_t scl, const cyhal_clock_divider_t *clk); @@ -102,27 +162,27 @@ cy_rslt_t cyhal_i2c_init(cyhal_i2c_t *obj, cyhal_gpio_t sda, cyhal_gpio_t scl, c */ void cyhal_i2c_free(cyhal_i2c_t *obj); -/** Configure the I2C block +/** Configure the I2C block. + * NOTE: Master/Slave specific functions only work when the block is configured + * to be in that mode.
+ * See \ref subsection_i2c_snippet_1 * * @param[in] obj The I2C object * @param[in] cfg Configuration settings to apply * @return The status of the configure request + * */ cy_rslt_t cyhal_i2c_configure(cyhal_i2c_t *obj, const cyhal_i2c_cfg_t *cfg); -/** -* \addtogroup group_hal_i2c_master -* \{ -*/ /** * I2C master write * * @param[in] obj The I2C object * @param[in] dev_addr device address (7-bit) - * @param[in] data i2c send data - * @param[in] size i2c send data size - * @param[in] timeout timeout in milisecond, set this value to 0 if you want to wait forever + * @param[in] data I2C send data + * @param[in] size I2C send data size + * @param[in] timeout timeout in millisecond, set this value to 0 if you want to wait forever * @param[in] send_stop whether the stop should be send, used to support repeat start conditions * * @return The status of the master_write request @@ -134,110 +194,108 @@ cy_rslt_t cyhal_i2c_master_write(cyhal_i2c_t *obj, uint16_t dev_addr, const uint * * @param[in] obj The I2C object * @param[in] dev_addr device address (7-bit) - * @param[out] data i2c receive data - * @param[in] size i2c receive data size - * @param[in] timeout timeout in milisecond, set this value to 0 if you want to wait forever + * @param[out] data I2C receive data + * @param[in] size I2C receive data size + * @param[in] timeout timeout in millisecond, set this value to 0 if you want to wait forever * @param[in] send_stop whether the stop should be send, used to support repeat start conditions * * @return The status of the master_read request */ cy_rslt_t cyhal_i2c_master_read(cyhal_i2c_t *obj, uint16_t dev_addr, uint8_t *data, uint16_t size, uint32_t timeout, bool send_stop); -/** \} group_hal_i2c_master */ - -/** -* \addtogroup group_hal_i2c_slave -* \{ -*/ - /** - * I2C slave config write buffer - * The user needs to setup a new buffer every time (i.e. call slave_send and slave_recv every time the buffer has been used up) + * The function configures the read buffer on an I2C Slave. This is the buffer from which the master reads data from. + * The user needs to setup a new buffer every time (i.e. call slave_send and slave_recv every time the buffer has been used up)
+ * See related code example: PSoC 6 MCU: I2C Master * * @param[in] obj The I2C object - * @param[in] data i2c slave send data - * @param[in] size i2c slave send data size + * @param[in] data I2C slave send data + * @param[in] size I2C slave send data size * * @return The status of the slave_config_write_buff request */ cy_rslt_t cyhal_i2c_slave_config_write_buff(cyhal_i2c_t *obj, const uint8_t *data, uint16_t size); /** - * I2C slave config read buffer - * The user needs to setup a new buffer every time (i.e. call slave_send and slave_recv every time the buffer has been used up) + * The function configures the write buffer on an I2C Slave. This is the buffer to which the master writes data to. + * The user needs to setup a new buffer every time (i.e. call slave_send and slave_recv every time the buffer has been used up)
+ * See related code example: PSoC 6 MCU: I2C Master * * @param[in] obj The I2C object - * @param[out] data i2c slave receive data - * @param[in] size i2c slave receive data size + * @param[out] data I2C slave receive data + * @param[in] size I2C slave receive data size * * @return The status of the slave_config_read_buff request */ cy_rslt_t cyhal_i2c_slave_config_read_buff(cyhal_i2c_t *obj, uint8_t *data, uint16_t size); -/** \} group_hal_i2c_slave */ -/** -* \addtogroup group_hal_i2c_master -* \{ -*/ - -/** Perform an i2c write using a block of data stored at the specified memory location +/** Perform an I2C write using a block of data stored at the specified memory location * * @param[in] obj The I2C object * @param[in] address device address (7-bit) * @param[in] mem_addr mem address to store the written data * @param[in] mem_addr_size number of bytes in the mem address - * @param[in] data i2c master send data - * @param[in] size i2c master send data size - * @param[in] timeout timeout in milisecond, set this value to 0 if you want to wait forever + * @param[in] data I2C master send data + * @param[in] size I2C master send data size + * @param[in] timeout timeout in millisecond, set this value to 0 if you want to wait forever * @return The status of the write request */ + cy_rslt_t cyhal_i2c_master_mem_write(cyhal_i2c_t *obj, uint16_t address, uint16_t mem_addr, uint16_t mem_addr_size, const uint8_t *data, uint16_t size, uint32_t timeout); -/** Perform an i2c read using a block of data stored at the specified memory location +/** Perform an I2C read using a block of data stored at the specified memory location * * @param[in] obj The I2C object * @param[in] address device address (7-bit) * @param[in] mem_addr mem address to store the written data * @param[in] mem_addr_size number of bytes in the mem address - * @param[out] data i2c master send data - * @param[in] size i2c master send data size - * @param[in] timeout timeout in milisecond, set this value to 0 if you want to wait forever + * @param[out] data I2C master send data + * @param[in] size I2C master send data size + * @param[in] timeout timeout in millisecond, set this value to 0 if you want to wait forever * @return The status of the read request */ cy_rslt_t cyhal_i2c_master_mem_read(cyhal_i2c_t *obj, uint16_t address, uint16_t mem_addr, uint16_t mem_addr_size, uint8_t *data, uint16_t size, uint32_t timeout); -/** Start I2C master asynchronous transfer +/** Initiate a non-blocking I2C master asynchronous transfer. Supports simultaneous write and read operation.
+ * Use callback handler to handle the events until data transfer is complete.
+ * If either of tx_size or rx_size is '0', the respective write or read operation is not performed. + * See \ref subsection_i2c_snippet_3 * * @param[in] obj The I2C object * @param[in] address device address (7-bit) * @param[in] tx The transmit buffer - * @param[in] tx_size The number of bytes to transmit + * @param[in] tx_size The number of bytes to transmit. Use '0' if write operation is not required. * @param[out] rx The receive buffer - * @param[in] rx_size The number of bytes to receive + * @param[in] rx_size The number of bytes to receive. Use '0' if read operation is not required. * @return The status of the master_transfer_async request + * */ cy_rslt_t cyhal_i2c_master_transfer_async(cyhal_i2c_t *obj, uint16_t address, const void *tx, size_t tx_size, void *rx, size_t rx_size); -/** \} group_hal_i2c_master */ -/** Abort asynchronous transfer +/** Abort asynchronous transfer.
+ *This function aborts the ongoing transfer by generating a stop condition.
+ * See \ref subsection_i2c_snippet_3 * - * This function does not perform any check - that should happen in upper layers. * @param[in] obj The I2C object * @return The status of the abort_async request + * */ cy_rslt_t cyhal_i2c_abort_async(cyhal_i2c_t *obj); -/** The I2C event callback handler registration +/** The I2C event callback handler registration
+ * See \ref subsection_i2c_snippet_2 * * @param[in] obj The I2C object * @param[in] callback The callback handler which will be invoked when an event triggers * @param[in] callback_arg Generic argument that will be provided to the callback when called + * */ void cyhal_i2c_register_callback(cyhal_i2c_t *obj, cyhal_i2c_event_callback_t callback, void *callback_arg); /** Configure and Enable or Disable I2C Interrupt. + * See \ref subsection_i2c_snippet_2 * * @param[in] obj The I2C object * @param[in] event The I2C event type @@ -246,8 +304,9 @@ void cyhal_i2c_register_callback(cyhal_i2c_t *obj, cyhal_i2c_event_callback_t ca */ void cyhal_i2c_enable_event(cyhal_i2c_t *obj, cyhal_i2c_event_t event, uint8_t intrPriority, bool enable); + /******************************************************************************* -* Backward compatibility macro. The following code is DEPRECATED and must +* Backward compatibility macro. The following code is DEPRECATED and must * not be used in new projects *******************************************************************************/ /** \cond INTERNAL */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_interconnect.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_interconnect.h index 390633cb5b1..c9fe16ea3fc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_interconnect.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_interconnect.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,7 +29,13 @@ * \addtogroup group_hal_interconnect INTERCONNECT (Internal digital routing) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress digital routing. +* High level interface for interacting with the digital routing. +* +* This provides limited facilities for runtime manipulation of the on chip routing. +* The following types of connections are supported: +* * Connection from a peripheral to a pin. (A dedicated connection must exist + between the pin and the peripheral; see the device datasheet for more details) +* * Experimental support for connecting between two on-chip "trigger" terminals. */ #pragma once diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_lptimer.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_lptimer.h index 5f77945d292..74ce6e360ad 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_lptimer.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_lptimer.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,7 +29,11 @@ * \addtogroup group_hal_lptimer LPTIMER (Low-Power Timer) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress LPTIMER. +* High level interface for interacting with the low-power timer (LPTIMER). +* +* This can be used to measure timing between events, or to perform +* some action the ability after a set interval. It continues to operate +* in some low power modes; see the device datasheet for details. */ #pragma once @@ -43,6 +47,10 @@ extern "C" { #endif + +/** Failed to configure power management callback */ +#define CYHAL_LPTIMER_RSLT_ERR_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_WDT, 0)) + /** LPTIMER interrupt triggers */ typedef enum { CYHAL_LPTIMER_COMPARE_MATCH, @@ -81,33 +89,38 @@ void cyhal_lptimer_free(cyhal_lptimer_t *obj); */ cy_rslt_t cyhal_lptimer_reload(cyhal_lptimer_t *obj); -/** Set timeframe between interrupts - * - * Configures the LPTIMER in free-running mode. Generates an interrupt on match. - * This function is for initial configuration. For quick updates to the match - * value, use cyhal_lptimer_set_time(). - * - * @param[in] obj The LPTIMER object - * @param[in] time The time in ticks to be set - * - * @return The status of the set_time request - */ -cy_rslt_t cyhal_lptimer_set_time(cyhal_lptimer_t *obj, uint32_t time); +/** Deprecated. Call cyhal_lptimer_set_match instead. */ +#define cyhal_lptimer_set_time cyhal_lptimer_set_match /** Update the match/compare value - * + * * Update the match value of an already configured LPTIMER set up * to generate an interrupt on match. Note that this function does not * reinitialize the counter or the associated peripheral initialization * sequence. - * + * * @param[in] obj The LPTIMER object - * @param[in] value The match value in ticks + * @param[in] value The tick value to match * * @return The status of the set_match request */ cy_rslt_t cyhal_lptimer_set_match(cyhal_lptimer_t *obj, uint32_t value); +/** Update the match/compare value + * + * Update the match value of an already configured LPTIMER set up + * to generate an interrupt on match delay from the current counter value. + * Note that this function does not reinitialize the counter or the + * associated peripheral initialization + * sequence. + * + * @param[in] obj The LPTIMER object + * @param[in] delay The ticks to wait + * + * @return The status of the set_match request + */ +cy_rslt_t cyhal_lptimer_set_delay(cyhal_lptimer_t *obj, uint32_t delay); + /** Read the current tick * * If no rollover has occurred, the seconds passed since cyhal_lptimer_init() or cyhal_lptimer_set_time() diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_modules.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_modules.h index d53cf526e97..a46eba8910d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_modules.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_modules.h @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,8 +24,9 @@ *******************************************************************************/ /** -* \ingroup group_hal +* \ingroup group_result * \{ +* Enum definition for all HAL resource modules. */ #pragma once @@ -37,6 +38,11 @@ extern "C" { #endif /** Enum to in indicate which module an errors occurred in. */ +/** + * @brief Enum to specify module IDs for @ref cy_rslt_t values returned from the HAL. + * + */ + enum cyhal_rslt_module_chip { CYHAL_RSLT_MODULE_CHIP_HWMGR = CY_RSLT_MODULE_ABSTRACTION_HAL_BASE, //!< An error occurred in hardware management module @@ -64,10 +70,11 @@ enum cyhal_rslt_module_chip CYHAL_RSLT_MODULE_UART, //!< An error occurred in UART module CYHAL_RSLT_MODULE_USB, //!< An error occurred in USB module CYHAL_RSLT_MODULE_WDT, //!< An error occurred in WDT module + CYHAL_RSLT_MODULE_EZI2C, //!< An error occurred in EZI2C module }; #if defined(__cplusplus) } #endif /* __cplusplus */ -/** \} group_hal */ +/** \} group_hal_modules */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pin_package.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pin_package.h index 1063a599d49..de733525ab0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pin_package.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pin_package.h @@ -3,10 +3,10 @@ * * Description: * Provides definitions for the pinout for each supported device. -* +* ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -37,24 +37,29 @@ extern "C" { #endif /* __cplusplus */ -/** Port names */ +/** Port definitions that individual pins can belong to. */ typedef enum { - CYHAL_PORT_0 = 0x0, - CYHAL_PORT_1 = 0x1, - CYHAL_PORT_2 = 0x2, - CYHAL_PORT_3 = 0x3, - CYHAL_PORT_4 = 0x4, - CYHAL_PORT_5 = 0x5, - CYHAL_PORT_6 = 0x6, - CYHAL_PORT_7 = 0x7, - CYHAL_PORT_8 = 0x8, - CYHAL_PORT_9 = 0x9, - CYHAL_PORT_10 = 0xA, - CYHAL_PORT_11 = 0xB, - CYHAL_PORT_12 = 0xC, - CYHAL_PORT_13 = 0xD, - CYHAL_PORT_14 = 0xE, - CYHAL_PORT_15 = 0xF, + CYHAL_PORT_0 = 0x00, + CYHAL_PORT_1 = 0x01, + CYHAL_PORT_2 = 0x02, + CYHAL_PORT_3 = 0x03, + CYHAL_PORT_4 = 0x04, + CYHAL_PORT_5 = 0x05, + CYHAL_PORT_6 = 0x06, + CYHAL_PORT_7 = 0x07, + CYHAL_PORT_8 = 0x08, + CYHAL_PORT_9 = 0x09, + CYHAL_PORT_10 = 0x0A, + CYHAL_PORT_11 = 0x0B, + CYHAL_PORT_12 = 0x0C, + CYHAL_PORT_13 = 0x0D, + CYHAL_PORT_14 = 0x0E, + CYHAL_PORT_15 = 0x0F, + CYHAL_PORT_16 = 0x10, + CYHAL_PORT_17 = 0x11, + CYHAL_PORT_18 = 0x12, + CYHAL_PORT_19 = 0x13, + CYHAL_PORT_20 = 0x14, } cyhal_port_t; /** Bitfield representing the configuration of a GPIO (hsiom selection and mode). @@ -115,6 +120,8 @@ typedef uint16_t cyhal_gpio_mapping_cfg_t; // 8bit hsiom, 8bit mode #include "pin_packages/cyhal_psoc6_03_49_wlcsp.h" #elif defined(_GPIO_PSOC6_03_68_QFN_H_) #include "pin_packages/cyhal_psoc6_03_68_qfn.h" +#elif defined(_GPIO_PLAYER_128_TQFP_H_) +#include "pin_packages/cyhal_mxs28playermcuss_128_tqfp.h" #else #error "Unhandled Device/PinPackage combination" #endif @@ -123,4 +130,4 @@ typedef uint16_t cyhal_gpio_mapping_cfg_t; // 8bit hsiom, 8bit mode } #endif /* __cplusplus */ -/** \} group_hal_adc */ +/** \} group_hal_psoc6 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm.h index b7cf1e09a05..20265effb82 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,12 +29,61 @@ * \addtogroup group_hal_pwm PWM (Pulse Width Modulator) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress PWM. + * High level interface for interacting with the pulse width modulator (PWM) hardware resource + * + * The PWM driver can be used to generate periodic digital waveforms with configurable frequency and duty cycle. + * The driver allows assigning the PWM output and an optional inverted output to supplied pins. + * The driver supports interrupt generation on PWM terminal count and capture/compare events. + * + * \section section_pwm_features Features + * * Configurable pin assignment for the PWM output + * * Optional complementary (inverted) PWM output to a second pin + * * Configurable dead time between normal and inverted PWM outputs + * * Configurable alignment: left, right or center + * * Continuous or One-shot operation + * * Option to instantiate and use a new clock or use pre-allocated clock for clock input + * * Configurable interrupt and callback assignment on PWM events: terminal count, capture/compare match or combination of both + * + * \section section_pwm_quickstart Quick Start + * + * See \ref subsection_pwm_snippet_1 for a code snippet that generates a signal with the specified frequency and duty cycle on the specified pin. + * + * \section section_pwm_snippets Code snippets + * + * \subsection subsection_pwm_snippet_1 Snippet 1: Simple PWM initialization and output to pin + * The following snippet initializes a PWM resource and assigns the output to the supplied pin using \ref cyhal_pwm_init.
+ * The clock parameter clk is optional and need not be provided (NULL), to generate and use an available clock resource with a default frequency.
+ * The clock frequency and the duty cycle is set using \ref cyhal_pwm_set_duty_cycle.
+ * \ref cyhal_pwm_start starts the PWM output on the pin. + * + * \snippet pwm.c snippet_cyhal_pwm_simple_init + * + * + * \subsection subsection_pwm_snippet_2 Snippet 2: Starting and stopping the PWM output + * \ref cyhal_pwm_start and \ref cyhal_pwm_stop functions can be used after PWM initialization to start and stop the PWM output. + * + * \snippet pwm.c snippet_cyhal_pwm_start_stop + * + * + * \subsection subsection_pwm_snippet_3 Snippet 3: Advanced PWM output to pin + * \ref cyhal_pwm_init_adv can be used to specify advanced PWM options like an additional inverted PWM output, pulse alignment + * (left, right, center) and run mode (one-shot or continuous). The following snippet initializes a left-aligned, continuous running PWM + * assigned to the supplied pin. The inverted output is assigned to a second pin (compl_pin). + * + * \snippet pwm.c snippet_cyhal_pwm_adv_init + * + * + * \subsection subsection_pwm_snippet_4 Snippet 4: Interrupts on PWM events + * PWM events like hitting the terminal count or a capture/compare event can be used to trigger a callback function.
+ * \ref cyhal_pwm_enable_event() can be used to enable one or more events to trigger the callback function. + * + * \snippet pwm.c snippet_cyhal_pwm_events */ #pragma once #include +#include #include "cy_result.h" #include "cyhal_hw_types.h" #include "cyhal_modules.h" @@ -43,6 +92,17 @@ extern "C" { #endif +/** Initialize the PWM out peripheral and configure the pin + * This is similar to the \ref cyhal_pwm_init_adv() but uses defaults for some of the + * more advanced setup options. See \ref subsection_pwm_snippet_1. + * + * @param[out] obj The PWM object to initialize + * @param[in] pin The PWM pin to initialize + * @param[in] clk An optional, pre-allocated clock to use, if NULL a new clock will be allocated + * @return The status of the init request. + */ +#define cyhal_pwm_init(obj, pin, clk) (cyhal_pwm_init_adv(obj, pin, NC, CYHAL_PWM_LEFT_ALIGN, true, 0u, (bool)(pin & 1), clk)) + /** Bad argument */ #define CYHAL_PWM_RSLT_BAD_ARGUMENT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_PWM, 0)) /** Failed to initialize PWM clock */ @@ -52,23 +112,44 @@ extern "C" { /** PWM interrupt triggers */ typedef enum { - CYHAL_PWM_IRQ_NONE = 0, - CYHAL_PWM_IRQ_TERMINAL_COUNT = 1 << 0, - CYHAL_PWM_IRQ_CAPTURE_COMPARE = 1 << 1, - CYHAL_PWM_IRQ_ALL = (1 << 2) - 1, + CYHAL_PWM_IRQ_NONE = 0, /**< No interrupts */ + CYHAL_PWM_IRQ_TERMINAL_COUNT = 1 << 0, /**< Interrupt on terminal count match event */ + CYHAL_PWM_IRQ_CAPTURE_COMPARE = 1 << 1, /**< Interrupt on capture/compare match event */ + CYHAL_PWM_IRQ_ALL = (1 << 2) - 1, /**< Interrupt on any events */ } cyhal_pwm_event_t; +/** PWM alignment */ +typedef enum { + CYHAL_PWM_LEFT_ALIGN = 0, /**< PWM is left aligned (signal starts high and goes low after capture/compare match) */ + CYHAL_PWM_RIGHT_ALIGN = 1, /**< PWM is right aligned (signal starts low and goes high after capture/compare match) */ + CYHAL_PWM_CENTER_ALIGN = 2, /**< PWM is centered aligned (signal starts and ends low with a center aligned pulse) */ +} cyhal_pwm_alignment_t; + /** Handler for PWM interrupts */ typedef void(*cyhal_pwm_event_callback_t)(void *callback_arg, cyhal_pwm_event_t event); -/** Initialize the PWM out peripheral and configure the pin +/** Initialize the PWM out peripheral and configure the pin. + * This is similar to the \ref cyhal_pwm_init() but provides additional setup options.
+ * See \ref subsection_pwm_snippet_3. * - * @param[out] obj The PWM object to initialize - * @param[in] pin The PWM pin to initialize - * @param[in] clk The clock to use can be shared, if not provided a new clock will be allocated + * @param[out] obj The PWM object to initialize. + * @param[in] pin The PWM pin to initialize. + * @param[in] compl_pin An optional, additional inverted output pin.
+ * If supplied, this must be connected to the same PWM instance as pin, for + * PSoC 6 see \ref section_psoc6_pwm_compl_pins.
+ * If this output is not needed, use \ref NC (No Connect). + * @param[in] pwm_alignment PWM alignment: left, right, or center. + * @param[in] continuous PWM run type: continuous (true) or one shot (false). + * @param[in] dead_time_us The number of micro-seconds for dead time. This is + * only meaningful if both pin and compl_pin are provided. + * @param[in] invert An option for the user to invert the PWM output + * @param[in] clk An optional, pre-allocated clock to use, if NULL a + * new clock will be allocated. * @return The status of the init request + * + * @note In some cases, it is possible to use a pin designated for non-inverting output as an inverting output and vice versa. Whether this is possible is dependent on the HAL implementation and operating mode. See the implementation specific documentation for details. */ -cy_rslt_t cyhal_pwm_init(cyhal_pwm_t *obj, cyhal_gpio_t pin, const cyhal_clock_divider_t *clk); +cy_rslt_t cyhal_pwm_init_adv(cyhal_pwm_t *obj, cyhal_gpio_t pin, cyhal_gpio_t compl_pin, cyhal_pwm_alignment_t pwm_alignment, bool continuous, uint32_t dead_time_us, bool invert, const cyhal_clock_divider_t *clk); /** Deinitialize the PWM object * @@ -85,26 +166,26 @@ void cyhal_pwm_free(cyhal_pwm_t *obj); */ cy_rslt_t cyhal_pwm_set_period(cyhal_pwm_t *obj, uint32_t period_us, uint32_t pulse_width_us); -/** Set the PWM pulsewidth specified in microseconds, keeping the period the same. +/** Set the PWM duty cycle and frequency * - * @param[in] obj The PWM object - * @param[in] duty_cycle The percentage of time the output is high - * @param[in] frequencyhal_hz The frequency of the PWM - * @return The status of the pulsewidth request + * @param[in] obj The PWM object + * @param[in] duty_cycle The percentage of time the output is high + * @param[in] frequencyhal_hz The frequency of the PWM in Hz + * @return The status of the duty cycle request */ cy_rslt_t cyhal_pwm_set_duty_cycle(cyhal_pwm_t *obj, float duty_cycle, uint32_t frequencyhal_hz); -/** Starts the PWM with the provided period and pulsewidth +/** Starts the PWM generation and outputs on pin and compl_pin. * * @param[in] obj The PWM object - * @return The status of the start request + * @return The status of the start request */ cy_rslt_t cyhal_pwm_start(cyhal_pwm_t *obj); -/** Stops the PWM from running +/** Stops the PWM generation and outputs on pin and compl_pin. * - * @param[in] obj The PWM object - * @return The status of the stop request + * @param[in] obj The PWM object + * @return The status of the stop request */ cy_rslt_t cyhal_pwm_stop(cyhal_pwm_t *obj); @@ -118,12 +199,12 @@ void cyhal_pwm_register_callback(cyhal_pwm_t *obj, cyhal_pwm_event_callback_t ca /** Configure PWM event enablement. * - * @param[in] obj The PWM object - * @param[in] event The PWM event type - * @param[in] intrPriority The priority for NVIC interrupt events - * @param[in] enable True to turn on events, False to turn off + * @param[in] obj The PWM object + * @param[in] event The PWM event type + * @param[in] intr_priority The priority for NVIC interrupt events + * @param[in] enable True to turn on events, False to turn off */ -void cyhal_pwm_enable_event(cyhal_pwm_t *obj, cyhal_pwm_event_t event, uint8_t intrPriority, bool enable); +void cyhal_pwm_enable_event(cyhal_pwm_t *obj, cyhal_pwm_event_t event, uint8_t intr_priority, bool enable); #if defined(__cplusplus) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm_impl.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm_impl.h index 957a86c9e94..e7c0a3473ff 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm_impl.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_pwm_impl.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2019 Cypress Semiconductor Corporation +* Copyright 2019-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_qspi.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_qspi.h index bf67b384527..2e69c396ffe 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_qspi.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_qspi.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,7 +29,10 @@ * \addtogroup group_hal_qspi QSPI (Quad Serial Peripheral Interface) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress Quad-SPI. +* High level interface for interacting with the Quad Serial Peripheral Interface (QSPI) interface. +* +* The QSPI block supports sending commands to and receiving commands from an +* another device (often an external memory) via single, dual, quad, or octal SPI. */ #pragma once @@ -71,12 +74,10 @@ typedef enum { } cyhal_qspi_event_t; #define CYHAL_QSPI_RSLT_ERR_BUS_WIDTH (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 0)) /**< Bus width Error. >*/ -#define CYHAL_QSPI_RSLT_ERR_SIZE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 1)) /**< Size Error. >*/ -#define CYHAL_QSPI_RSLT_ERR_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 2)) /**< Pin related Error. >*/ -#define CYHAL_QSPI_RSLT_ERR_DATA_SEL (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 3)) /**< Data select Error. >*/ -#define CYHAL_QSPI_RSLT_ERR_INSTANCE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 4)) /**< QSPI instance related Error. >*/ -#define CYHAL_QSPI_RSLT_ERR_ALT_SIZE_WIDTH_MISMATCH (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 5)) /**< Provided alt size is incompatible with provided alt width. >*/ -#define CYHAL_QSPI_RSLT_ERR_ALT_SIZE_DUMMY_CYCLES_MISMATCH (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 6)) /**< Provided alt size is incompatible with provided number of dummy cycles (due to device-specific restrictions). >*/ +#define CYHAL_QSPI_RSLT_ERR_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 1)) /**< Pin related Error. >*/ +#define CYHAL_QSPI_RSLT_ERR_DATA_SEL (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 2)) /**< Data select Error. >*/ +#define CYHAL_QSPI_RSLT_ERR_INSTANCE (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 3)) /**< QSPI instance related Error. >*/ +#define CYHAL_QSPI_RSLT_ERR_FREQUENCY (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_QSPI, 4)) /**< Clock frequency error. >*/ /** @brief QSPI command settings */ typedef struct cyhal_qspi_command { @@ -93,7 +94,7 @@ typedef struct cyhal_qspi_command { } address; struct { cyhal_qspi_bus_width_t bus_width; /**< Bus width for mode bits >*/ - uint8_t size; /**< Mode bits size >*/ + cyhal_qspi_size_t size; /**< Mode bits size >*/ uint32_t value; /**< Mode bits value >*/ bool disabled; /**< Mode bits phase skipped if disabled is set to true >*/ } mode_bits; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_rtc.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_rtc.h index e49fe882219..8e997e4179b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_rtc.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_rtc.h @@ -2,14 +2,14 @@ * \file cyhal_rtc.h * * \brief -* Provides a high level interface for interacting with the Real Time Clock on -* Cypress devices. This interface abstracts out the chip specific details. -* If any chip specific functionality is necessary, or performance is critical +* Provides a high level interface for interacting with the Real Time Clock on +* Cypress devices. This interface abstracts out the chip specific details. +* If any chip specific functionality is necessary, or performance is critical * the low level functions can be used directly. * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,7 +29,14 @@ * \addtogroup group_hal_rtc RTC (Real-Time Clock) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress RTC. +* High level interface for interacting with the real-time clock (RTC). +* +* The real time clock provides tracking of the current time and date, as +* well as the ability to trigger a callback at a specific time in the future. +* +* If a suitable clock source is available, the RTC can continue timekeeping +* operations even when the device is in a low power operating mode. See the +* device datasheet for more details. */ #pragma once @@ -43,6 +50,8 @@ /** RTC not initialized */ #define CY_RSLT_RTC_NOT_INITIALIZED CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_RTC, 0) +/** Bad argument */ +#define CY_RSLT_RTC_BAD_ARGUMENT CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_RTC, 1) #if defined(__cplusplus) extern "C" { @@ -64,6 +73,35 @@ typedef struct uint8_t en_month : 1; /** !< Enable match of month */ } cyhal_alarm_active_t; +/** Enumeration used to configure the DST format */ +typedef enum +{ + CYHAL_RTC_DST_RELATIVE, /**< Relative DST format */ + CYHAL_RTC_DST_FIXED /**< Fixed DST format */ +} cyhal_rtc_dst_format_t; + +/** +* Day Light Savings Time (DST) structure for setting when to apply. It allows to +* set the DST time and date using a fixed or relative time format. +*/ +typedef struct +{ + cyhal_rtc_dst_format_t format; /**< DST format. See /ref cyhal_rtc_dst_format_t. + Based on this value other structure elements + should be filled or could be ignored */ + uint32_t hour; /**< Hour in 24hour format, range[0-23] */ + union + { + uint32_t dayOfMonth; /**< Day of Month, range[1-31]. */ + struct /* format = CYHAL_RTC_DST_FIXED */ + { + uint32_t dayOfWeek; /**< Day of the week, starting on Sunday, range[0-6] */ + uint32_t weekOfMonth; /**< Week of month, range[0-5]. Where 5 => Last week of month */ + }; + }; + uint32_t month; /**< Month value, range[1-12]. */ +} cyhal_rtc_dst_t; + /** Handler for RTC events */ typedef void (*cyhal_rtc_event_callback_t)(void *callback_arg, cyhal_rtc_event_t event); @@ -83,7 +121,7 @@ cy_rslt_t cyhal_rtc_init(cyhal_rtc_t *obj); /** Deinitialize RTC * - * Frees resources associated with the RTC and disables CPU access. This + * Frees resources associated with the RTC and disables CPU access. This * only affects the CPU domain and not the time keeping logic. * After this function is called no other RTC functions should be called * except for rtc_init. @@ -115,6 +153,23 @@ cy_rslt_t cyhal_rtc_read(cyhal_rtc_t *obj, struct tm *time); */ cy_rslt_t cyhal_rtc_write(cyhal_rtc_t *obj, const struct tm *time); +/** Set the start and end time for Day Light Savings + * + * @param[in] obj RTC object + * @param[in] start When Day Light Savings time should start + * @param[in] stop When Day Light Savings time should end + * @return The status of the set_dst request + */ +cy_rslt_t cyhal_rtc_set_dst(cyhal_rtc_t *obj, const cyhal_rtc_dst_t *start, const cyhal_rtc_dst_t *stop); + +/** Checks to see if Day Light Savings Time is currently active. This should only be called after + * \ref cyhal_rtc_set_dst(). + * + * @param[in] obj RTC object + * @return Boolean indicating whether the current date/time is within the specified DST start/stop window. + */ +bool cyhal_rtc_is_dst(cyhal_rtc_t *obj); + /** Set an alarm for the specified time in seconds to the RTC peripheral * * @param[in] obj RTC object diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_scb_common.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_scb_common.h index e1a00765c52..4095ae7100c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_scb_common.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_scb_common.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -22,6 +22,7 @@ * limitations under the License. *******************************************************************************/ +/** \cond INTERNAL */ /** * \addtogroup group_hal_psoc6_scb_common SCB Common Functionality * \ingroup group_hal_psoc6 @@ -71,3 +72,4 @@ __STATIC_INLINE void *cyhal_scb_get_irq_obj(void) #endif /** \} group_hal_psoc6_scb_common */ +/** \endcond */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdhc.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdhc.h index 6cd2fc9eb82..87d717d8c2e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdhc.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdhc.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,7 +29,10 @@ * \addtogroup group_hal_sdhc SDHC (SD Host Controller) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress SDHC. +* High level interface for interacting with the SD Host Controller (SDHC). +* +* The SD Host Controller allows data to be read from and written to several types +* of memory cards, including SD and eMMC (see cyhal_sdhc_card_type_t for a full list). */ #pragma once @@ -44,12 +47,13 @@ extern "C" { #endif #define CYHAL_SDHC_RSLT_ERR_PIN (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDHC, 0)) /**< Pin related Error. >*/ +#define CYHAL_SDHC_RSLT_ERR_UNSUPPORTED (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SDHC, 1)) /**< Requested feature is not supported on this hardware. >*/ /** Card types */ typedef enum { CYHAL_SDHC_SD, //!< Secure Digital card - CYHAL_SDHC_SDIO, //!< CD Input Output card + CYHAL_SDHC_SDIO, //!< SD Input Output card CYHAL_SDHC_EMMC, //!< Embedded Multimedia card CYHAL_SDHC_COMBO, //!< Combo Card (SD + SDIO) CYHAL_SDHC_UNUSABLE, //!< Unusable card or unsupported type diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdio.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdio.h index d5e396eca88..c33f0ab3766 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdio.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_sdio.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,8 +29,14 @@ * \addtogroup group_hal_sdio SDIO (Secure Digital Input Output) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress SDIO interface. +* High level interface for interacting with the Secure Digital Input Output (SDIO) interface. * +* The Secure Digital Input Output (SDIO) protocol is an extension of the SD +* interface for general I/O functions. +* +* This driver allows commands to be sent over the SDIO bus; the supported commands +* can be found in cyhal_sdio_command_t. Bulk data transfer is also supported +* via cyhal_sdio_bulk_transfer(). */ #pragma once @@ -44,11 +50,6 @@ extern "C" { #endif -/** - * \addtogroup group_hal_sdio_errors Error Codes - * \{ - */ - #define CYHAL_SDIO_RET_NO_ERRORS (0x00) /**< No error*/ #define CYHAL_SDIO_RET_NO_SP_ERRORS (0x01) /**< Non-specific error code*/ #define CYHAL_SDIO_RET_CMD_CRC_ERROR (0x02) /**< There was a CRC error on the Command/Response*/ @@ -91,8 +92,6 @@ extern "C" { CYHAL_RSLT_MODULE_SDIO, \ CYHAL_SDIO_CANCELED) -/** \} group_hal_sdio_errors */ - /** Commands that can be issued */ typedef enum { @@ -115,7 +114,7 @@ typedef enum /** Types of events that could be asserted by SDIO */ typedef enum { /* Interrupt-based thread events */ - CYHAL_SDIO_CMD_COMPLETE = 0x00001, //!> Command Complete + CYHAL_SDIO_CMD_COMPLETE = 0x00001, //!> Command Complete CYHAL_SDIO_XFER_COMPLETE = 0x00002, //!> Host read/write transfer is complete CYHAL_SDIO_BGAP_EVENT = 0x00004, //!> This bit is set when both read/write transaction is stopped CYHAL_SDIO_DMA_INTERRUPT = 0x00008, //!> Host controller detects an SDMA Buffer Boundary during transfer @@ -131,11 +130,11 @@ typedef enum { CYHAL_SDIO_FX_EVENT = 0x02000, //!> This status is set when R[14] of response register is set to 1 CYHAL_SDIO_CQE_EVENT = 0x04000, //!> This status is set if Command Queuing/Crypto event has occurred CYHAL_SDIO_ERR_INTERRUPT = 0x08000, //!> If any of the bits in the Error Interrupt Status register are set - + /* Non-interrupt-based thread events */ CYHAL_SDIO_GOING_DOWN = 0x10000, //!> The interface is going away (eg: powering down for some period of time) CYHAL_SDIO_COMING_UP = 0x20000, //!> The interface is back up (eg: came back from a low power state) - + CYHAL_SDIO_ALL_INTERRUPTS = 0x0E1FF, //!> Is used to enable/disable all interrupts events } cyhal_sdio_event_t; @@ -193,9 +192,13 @@ cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t directio * @param[in,out] obj The SDIO object * @param[in] direction The direction of transfer (read/write) * @param[in] argument The argument to the command - * @param[in] data The data to send to the SDIO device. The data buffer - * should be aligned to the block size (64 bytes) if data - * size is greater that block size (64 bytes). + * @param[in] data The data to send to the SDIO device. A bulk transfer is done in block + * size (default: 64 bytes) chunks for better performance. Therefore, + * the size of the data buffer passed into this function must be at least + * `length` bytes and a multiple of the block size. For example, when + * requesting to read 100 bytes of data with a block size 64 bytes, the + * data buffer needs to be at least 128 bytes. The first 100 bytes of data + * in the buffer will be the requested data. * @param[in] length The number of bytes to send * @param[out] response The response from the SDIO device * @return The status of the configure request @@ -245,7 +248,7 @@ void cyhal_sdio_register_callback(cyhal_sdio_t *obj, cyhal_sdio_event_callback_t void cyhal_sdio_enable_event(cyhal_sdio_t *obj, cyhal_sdio_event_t event, uint8_t intrPriority, bool enable); /******************************************************************************* -* Backward compatibility macro. The following code is DEPRECATED and must +* Backward compatibility macro. The following code is DEPRECATED and must * not be used in new projects *******************************************************************************/ /** \cond INTERNAL */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_spi.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_spi.h index ca6f24a08ba..a08561ac3c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_spi.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_spi.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,7 +29,59 @@ * \addtogroup group_hal_spi SPI (Serial Peripheral Interface) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress SPI. +* High level interface for interacting with the Serial Peripheral Interface (SPI). +* +* The SPI protocol is a synchronous serial interface protocol. Devices operate +* in either master or slave mode. The master initiates the data transfer. +* +* Motorola SPI modes 0, 1, 2, and 3 are supported, with either MSB or LSB first. +* The operating mode and data frame size can be configured via \ref cyhal_spi_cfg_t. +* +* \section section_spi_features Features +* * Supports master and slave functionality. +* * Supports Motorola modes - 0, 1, 2 and 3 - \ref cyhal_spi_mode_t +* * MSb or LSb first shift direction - \ref cyhal_spi_mode_t +* * Master supports up to four slave select lines +* * Supports data frame size of 8 or 16 bits +* * Configurable interrupt and callback assignment on SPI events: +* Data transfer to FIFO complete, Transfer complete and Transmission error - \ref cyhal_spi_event_t +* * Supports changing baud rate of the transaction in run time. +* * Provides functions to send/receive a single byte or block of data. +* +* \section section_spi_quickstart Quick Start +* +* Initialise a SPI master or slave interface using \ref cyhal_spi_init() and provide the SPI pins (mosi, miso, sclk, ssel), +* number of bits per frame (data_bits) and SPI Motorola mode. The data rate can be set using \ref cyhal_spi_set_frequency().
+* See \ref section_spi_snippets for code snippets to send or receive the data. +* +* \section section_spi_snippets Code snippets +* +* \subsection subsection_spi_snippet_1 Snippet 1: SPI Master - Single byte transfer operation (Read and Write) +* The following code snippet initialises an SPI Master interface using the \ref cyhal_spi_init(). The data rate of transfer is set using \ref cyhal_spi_set_frequency(). +* The code snippet shows how to transfer a single byte of data using \ref cyhal_spi_send() and \ref cyhal_spi_recv(). +* \snippet spi.c snippet_cyhal_spi_master_byte_operation +* +* \subsection subsection_spi_snippet_2 Snippet 2: SPI Slave - Single byte transfer operation (Read and Write) +* The following code snippet initialises an SPI Slave interface using the \ref cyhal_spi_init(). The data rate of transfer is set using \ref cyhal_spi_set_frequency. +* The code snippet shows how to transfer a single byte of data using \ref cyhal_spi_send() and \ref cyhal_spi_recv. +* \snippet spi.c snippet_cyhal_spi_slave_byte_operation +* +* \subsection subsection_spi_snippet_3 Snippet 3: SPI Block Data transfer +* The following snippet sends and receives an array of data in a single SPI transaction using \ref cyhal_spi_transfer(). The example +* uses SPI master to transmit 5 bytes of data and receive 5 bytes of data in a single transaction. +* \snippet spi.c snippet_cyhal_spi_block_data_transfer +* +* \subsection subsection_spi_snippet_4 Snippet 4: Interrupts on SPI events +* SPI interrupt events ( \ref cyhal_spi_event_t) can be mapped to an interrupt and assigned to a callback function. +* The callback function needs to be first registered and then the event needs to be enabled. +* The following snippet initialises a SPI master to perform a block transfer using \ref cyhal_spi_transfer_async(). This is a non-blocking function. +* A callback function is registered using \ref cyhal_spi_register_callback to notify whenever the SPI transfer is complete. +* \snippet spi.c snippet_cyhal_spi_interrupt_callback_events + +* \section subsection_spi_moreinfor More Information +* +* * mtb-example-psoc6-spi-master: This example project demonstrates +* use of SPI (HAL) resource in PSoC® 6 MCU in Master mode to write data to an SPI slave. */ #pragma once @@ -44,7 +96,6 @@ extern "C" { #endif - /** Bad argument */ #define CYHAL_SPI_RSLT_BAD_ARGUMENT (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SPI, 0)) /** Failed to initialize SPI clock */ @@ -105,7 +156,6 @@ typedef struct bool is_slave; //!< Whether the peripheral is operating as slave or master } cyhal_spi_cfg_t; - /** Initialize the SPI peripheral * * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral @@ -232,7 +282,7 @@ void cyhal_spi_register_callback(cyhal_spi_t *obj, cyhal_spi_event_callback_t ca void cyhal_spi_enable_event(cyhal_spi_t *obj, cyhal_spi_event_t event, uint8_t intrPriority, bool enable); /******************************************************************************* -* Backward compatibility macro. The following code is DEPRECATED and must +* Backward compatibility macro. The following code is DEPRECATED and must * not be used in new projects *******************************************************************************/ /** \cond INTERNAL */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_system.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_system.h index d5f994a0190..24317fd4fd6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_system.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_system.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -26,11 +26,16 @@ *******************************************************************************/ /** -* \addtogroup group_hal_system SYSTEM (Power Management and System Clock) +* \addtogroup group_hal_system System (Power Management and System Clock) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress power management +* High level interface for interacting with the power management * and system clock configuration. +* +* This driver provides three categories of functionality: +* * Retrieval and adjustment of system clock frequencies. +* * Control over low power operating modes. +* * The ability to disable interrupts during a critical section, and to renable them afterwards. */ #pragma once @@ -56,6 +61,19 @@ extern "C" { /** An error occurred in System module */ #define CYHAL_SYSTEM_RSLT_NO_VALID_DIVIDER (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_SYSTEM , 4)) +/** Flags enum of possible system reset causes */ +typedef enum +{ + CYHAL_SYSTEM_RESET_NONE = 0, /** No cause */ + CYHAL_SYSTEM_RESET_WDT = 1 << 0, /** A watchdog timer (WDT) reset has occurred */ + CYHAL_SYSTEM_RESET_ACTIVE_FAULT = 1 << 1, /** The fault logging system requested a reset from its Active logic. */ + CYHAL_SYSTEM_RESET_DEEPSLEEP_FAULT = 1 << 2, /** The fault logging system requested a reset from its Deep-Sleep logic. */ + CYHAL_SYSTEM_RESET_SOFT = 1 << 3, /** The CPU requested a system reset through it's SYSRESETREQ. */ + CYHAL_SYSTEM_RESET_HIB_WAKEUP = 1 << 4, /** A reset has occurred due to a a wakeup from hibernate power mode. */ + CYHAL_SYSTEM_RESET_WCO_ERR = 1 << 5, /** A reset has occurred due to a watch-crystal clock error */ + CYHAL_SYSTEM_RESET_SYS_CLK_ERR = 1 << 6, /** A reset has occurred due to a system clock error */ +} cyhal_reset_reason_t; + /** Enter a critical section * * Disables interrupts and returns a value indicating whether the interrupts were previously @@ -113,6 +131,32 @@ cy_rslt_t cyhal_system_register_callback(cyhal_system_callback_t *callback); */ cy_rslt_t cyhal_system_unregister_callback(cyhal_system_callback_t const *callback); +/** + * Requests that the current operation delays for at least the specified length of time. + * If this is running in an RTOS aware environment (-DCY_RTOS_AWARE) it will attempt to + * have the RTOS suspend the current task so others can continue to run. If this is not + * run under an RTOS it will then defer to the standard system delay which is likely to + * be a busy loop. + * If this is part of an application that is build with RTOS awareness, but the delay + * should not depend on the RTOS for whatever reason, use cyhal_system_delay_us() with + * the appropriate 1000x multiplier to the delay time. + * + * @param[in] milliseconds The number of milliseconds to delay for + * @return Returns CY_RSLT_SUCCESS if the delay request was successful, otherwise error + */ +cy_rslt_t cyhal_system_delay_ms(uint32_t milliseconds); + +/** + * Requests that the current operation delay for at least the specified number of + * micro-seconds. This will generally keep the processor active in a loop for the + * specified length of time. If this is running under an RTOS, it will NOT attempt to + * run any other RTOS tasks, however if the scheduler or a high priority interrupt + * comes it they can take over anyway. + * + * @param[in] microseconds The number of micro-seconds to delay for + */ +void cyhal_system_delay_us(uint16_t microseconds); + /** Gets the specified clock's current frequency. * * @param[in] clock ID of clock to configure @@ -138,6 +182,15 @@ cy_rslt_t cyhal_system_clock_set_frequency(uint8_t clock, uint32_t frequency_hz) */ cy_rslt_t cyhal_system_clock_set_divider(cyhal_system_clock_t clock, cyhal_system_divider_t divider); +/** Gets the cause of the latest reset or resets that occured in the system. + * + * @return Returns an enum of flags with the cause of the last reset(s) + */ +cyhal_reset_reason_t cyhal_system_get_reset_reason(void); + +/** Clears the reset cause registers */ +void cyhal_system_clear_reset_reason(void); + #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_system_impl.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_system_impl.h index d7e88a65914..9e5ffc0a2cc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_system_impl.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_system_impl.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -31,7 +31,7 @@ #ifdef CY_IP_MXS40SRSS -#define cyhal_system_critical_section_enter() Cy_SysLib_EnterCriticalSection() +#define cyhal_system_critical_section_enter() Cy_SysLib_EnterCriticalSection() #define cyhal_system_critical_section_exit(x) Cy_SysLib_ExitCriticalSection(x) @@ -39,4 +39,6 @@ #define cyhal_system_deepsleep() Cy_SysPm_CpuEnterDeepSleep(CY_SYSPM_WAIT_FOR_INTERRUPT) +#define cyhal_system_delay_us(microseconds) Cy_SysLib_DelayUs(microseconds) + #endif /* CY_IP_MXS40SRSS */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_tcpwm_common.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_tcpwm_common.h index faa9d44ddbf..2990501486f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_tcpwm_common.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_tcpwm_common.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2019 Cypress Semiconductor Corporation +* Copyright 2019-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -22,6 +22,7 @@ * limitations under the License. *******************************************************************************/ +/** \cond INTERNAL */ /** * \addtogroup group_hal_psoc6_tcpwm_common TCPWM Common Functionality * \ingroup group_hal_psoc6 @@ -77,3 +78,4 @@ void cyhal_tcpwm_register_callback(cyhal_resource_inst_t *resource, cy_israddres void cyhal_tcpwm_enable_event(TCPWM_Type *type, cyhal_resource_inst_t *resource, uint32_t event, uint8_t intrPriority, bool enable); /** \} group_hal_psoc6_tcpwm_common */ +/** \endcond */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer.h index 5dcb30921ca..2e2d36291d8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -26,10 +26,57 @@ *******************************************************************************/ /** -* \addtogroup group_hal_timer TIMER (Timer/Counter) +* \addtogroup group_hal_timer Timer (Timer/Counter) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress Timer. +* High level interface for interacting with the Timer/Counter hardware resource. +* +* The timer block is commonly used to measure the time of occurrence of an event, +* to measure the time difference between two events or perform an action after +* a specified period of time. The driver also allows the user to invoke a callback function +* when a particular event occurs. +* +* Some use case scenarios of timer - +* +* * Creating a periodic interrupt for executing periodic tasks +* * Measuring time between two events +* * Triggering other system resources after a certain number of events +* * Capturing time stamps when events occur +* +* \section subsection_timer_features Features +* * Runtime configurable parameters like period and compare value - \ref cyhal_timer_cfg_t +* * Configurable counting direction - \ref cyhal_timer_direction_t +* * Interrupt on various events - \ref cyhal_timer_event_t +* * Continuous or One Shot run modes +* +* \section subsection_timer_quickstart Quick Start +* +* \ref cyhal_timer_init can be used for timer initialization by providing the timer object - \ref cyhal_timer_t, +* and shared clock source - clk (optional). The timer parameters needs to be populated in \ref cyhal_timer_cfg_t structure. +* The timer then needs to be configured by using the \ref cyhal_timer_configure function. +* +* \note A default frequency is set when an existing clock divider - clk is not provided to \ref cyhal_timer_init which is +* defined by the macro - \ref CYHAL_TIMER_DEFAULT_FREQ. +* +* \warning Currently there is no support for pin connections to Timer using this driver. So, the pin should be +* assigned as \ref NC while using the \ref cyhal_timer_init to initialize the timer. +* +* +* See \ref subsection_timer_snippet_1. +* +* \section subsection_timer_sample_snippets Code Snippets +* +* \subsection subsection_timer_snippet_1 Snippet 1: Measuring time between two events +* The following snippet initializes a Timer and measures the time between two events. +* The clk need not be provided, in which case a clock resource is assigned. +* \snippet timer.c snippet_cyhal_timer_event_measure +* +* \subsection subsection_timer_snippet_2 Snippet 2: Handling an event in a callback function +* The following snippet initializes a Timer and triggers an event after every one second. +* The clk need not be provided (NULL), in which +* case a clock resource is assigned. +* \snippet timer.c snippet_cyhal_timer_event_interrupt +* */ #pragma once @@ -44,6 +91,10 @@ extern "C" { #endif +/******************************************************************************* +* Enumerations +*******************************************************************************/ + /** Timer directions */ typedef enum { @@ -54,17 +105,21 @@ typedef enum /** Timer/counter interrupt triggers */ typedef enum { - CYHAL_TIMER_IRQ_NONE = 0, - CYHAL_TIMER_IRQ_TERMINAL_COUNT = 1 << 0, - CYHAL_TIMER_IRQ_CAPTURE_COMPARE = 1 << 1, - CYHAL_TIMER_IRQ_ALL = (1 << 2) - 1, + CYHAL_TIMER_IRQ_NONE = 0, /**< No interrupt handled **/ + CYHAL_TIMER_IRQ_TERMINAL_COUNT = 1 << 0, /**< Interrupt when terminal count is reached **/ + CYHAL_TIMER_IRQ_CAPTURE_COMPARE = 1 << 1, /**< Interrupt when Compare/Capture value is reached **/ + CYHAL_TIMER_IRQ_ALL = (1 << 2) - 1, /**< Interrupt on terminal count and Compare/Capture values **/ } cyhal_timer_event_t; +/******************************************************************************* +* Data Structures +*******************************************************************************/ + /** @brief Describes the current configuration of a timer/counter */ typedef struct { /** - * Whether the timer is set to continously run. + * Whether the timer is set to continuously run. * If true, the timer will run forever. * Otherwise, the timer will run once and stop (one shot). */ @@ -76,6 +131,10 @@ typedef struct uint32_t value; //!< Current value of the timer/counter } cyhal_timer_cfg_t; +/******************************************************************************* +* Typedefs +*******************************************************************************/ + /** Handler for timer events */ typedef void(*cyhal_timer_event_callback_t)(void *callback_arg, cyhal_timer_event_t event); @@ -91,7 +150,12 @@ typedef void(*cyhal_timer_event_callback_t)(void *callback_arg, cyhal_timer_even /** Default timer frequency, used when an existing clock divider is not provided to init */ #define CYHAL_TIMER_DEFAULT_FREQ (1000000u) -/** Initialize the timer/counter peripheral and configure the pin. +/******************************************************************************* +* Functions +*******************************************************************************/ + +/** Initialize the timer/counter peripheral and configure the pin.
+ * See \ref subsection_timer_snippet_1. * * @param[out] obj The timer/counter object to initialize * @param[in] pin optional - The timer/counter compare/capture pin to initialize @@ -107,38 +171,51 @@ cy_rslt_t cyhal_timer_init(cyhal_timer_t *obj, cyhal_gpio_t pin, const cyhal_clo */ void cyhal_timer_free(cyhal_timer_t *obj); -/** Updates the configuration of the timer/counter object - * +/** Updates the configuration of the timer/counter object
+ * See \ref subsection_timer_snippet_1. * @param[in] obj The timer/counter object * @param[in] cfg The configuration of the timer/counter * @return The status of the configure request */ cy_rslt_t cyhal_timer_configure(cyhal_timer_t *obj, const cyhal_timer_cfg_t *cfg); -/** Configures the timer frequency. This is not valid to call if a non-null clock divider - * was provided to cyhal_timer_init +/** Configures the timer frequency. + * \note This is only valid to call if a null clock divider was provided to \ref cyhal_timer_init. + * If a custom clock was provided its frequency should be adjusted directly. * + * See \ref subsection_timer_snippet_1. * @param[in] obj The timer/counter object * @param[in] hz The frequency rate in Hz * @return The status of the set_frequency request */ cy_rslt_t cyhal_timer_set_frequency(cyhal_timer_t *obj, uint32_t hz); -/** Starts the timer/counter with the pre-set configuration. +/** Starts the timer/counter with the pre-set configuration
+ * See \ref subsection_timer_snippet_1. * * @param[in] obj The timer/counter object * @return The status of the start request */ cy_rslt_t cyhal_timer_start(cyhal_timer_t *obj); -/** Stops the timer/counter. +/** Stops the timer/counter
+ * See \ref subsection_timer_snippet_1. * * @param[in] obj The timer/counter object * @return The status of the stop request */ cy_rslt_t cyhal_timer_stop(cyhal_timer_t *obj); -/** The timer/counter callback handler registration +/** Reads the current value from the timer/counter
+ * See \ref subsection_timer_snippet_1. + * + * @param[in] obj The timer/counter object + * @return The current value of the timer/counter + */ +uint32_t cyhal_timer_read(const cyhal_timer_t *obj); + +/** The timer/counter callback handler registration
+ * See \ref subsection_timer_snippet_2. * * @param[in] obj The timer/counter object * @param[in] callback The callback handler which will be invoked when the event occurs @@ -146,14 +223,15 @@ cy_rslt_t cyhal_timer_stop(cyhal_timer_t *obj); */ void cyhal_timer_register_callback(cyhal_timer_t *obj, cyhal_timer_event_callback_t callback, void *callback_arg); -/** Configure timer/counter event enablement. +/** Configure timer/counter event enablement
+ * See \ref subsection_timer_snippet_2. * * @param[in] obj The timer/counter object * @param[in] event The timer/counter event type - * @param[in] intrPriority The priority for NVIC interrupt events + * @param[in] intr_priority The priority for NVIC interrupt events * @param[in] enable True to turn on interrupts, False to turn off */ -void cyhal_timer_enable_event(cyhal_timer_t *obj, cyhal_timer_event_t event, uint8_t intrPriority, bool enable); +void cyhal_timer_enable_event(cyhal_timer_t *obj, cyhal_timer_event_t event, uint8_t intr_priority, bool enable); #if defined(__cplusplus) } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer_impl.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer_impl.h index 9693bb83910..58c27cb3df0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer_impl.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_timer_impl.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2019 Cypress Semiconductor Corporation +* Copyright 2019-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_triggers.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_triggers.h new file mode 100644 index 00000000000..6a36d592e39 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_triggers.h @@ -0,0 +1,56 @@ +/***************************************************************************//** +* \file cyhal_triggers.h +* +* Description: +* Provides definitions for the triggers for each supported device family. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** +* \addtogroup group_hal_psoc6_triggers Triggers +* \ingroup group_hal_psoc6 +* \{ +* Trigger connections for supported device families +*/ + +#pragma once + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +#include "cy_device.h" + +#ifdef CY_DEVICE_PSOC6ABLE2 +#include "triggers/cyhal_triggers_psoc6_01.h" +#endif + +#ifdef CY_DEVICE_PSOC6A2M +#include "triggers/cyhal_triggers_psoc6_02.h" +#endif + +#ifdef CY_DEVICE_PSOC6A512K +#include "triggers/cyhal_triggers_psoc6_03.h" +#endif + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +/** \} group_hal_psoc6_triggers */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng.h index aafbb18b164..4d798be7747 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,7 +29,9 @@ * \addtogroup group_hal_trng TRNG (True Random Number Generator) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress TRNG. +* High level interface for interacting with the true random number generator (TRNG). +* +* This block uses dedicated hardware to efficiently generate truly random numbers. */ #pragma once diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng_impl.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng_impl.h index a42176d991d..44b46bdfdb5 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng_impl.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_trng_impl.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_uart.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_uart.h index 4cd3f897ded..6f007d031aa 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_uart.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_uart.h @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -29,7 +29,27 @@ * \addtogroup group_hal_uart UART (Universal Asynchronous Receiver-Transmitter) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress UART. +* High level interface for interacting with the Universal Asynchronous Receiver-Transmitter (UART). +* +* The Universal Asynchronous Receiver/Transmitter (UART) protocol is an +* asynchronous serial interface protocol. UART communication is typically +* point-to-point. The UART interface consists of two signals: +* * TX: Transmitter output +* * RX: Receiver input +* +* Additionally, two side-band signals are used to implement flow control in +* UART. Note that the flow control applies only to TX functionality. +* * Clear to Send (CTS): This is an input signal to the transmitter. +* When active, it indicates that the slave is ready for the master to +* transmit data. +* * Ready to Send (RTS): This is an output signal from the receiver. When +* active, it indicates that the receiver is ready to receive data +* +* Flow control can be configured via cyhal_uart_set_flow_control() +* +* The data frame size, STOP bits, and parity can be configured via cyhal_uart_cfg_t. +* The UART contains dedicated hardware buffers for transmit and receive. Optionally, +* either these can be augmented with a software buffer. */ #pragma once diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_usb_dev.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_usb_dev.h index 839f106d65d..59195c2e663 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_usb_dev.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_usb_dev.h @@ -29,8 +29,16 @@ * \addtogroup group_hal_usb_dev USB Device * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress USB Device. -* +* High level interface for interacting with the USB Device interface. +* +* This block supports one control endpoint (EP0) and one or more data endpoints +* see the device datasheet for the number of data endpoints supported. +* +* Four transfer types are supported (cyhal_usb_dev_ep_type_t): +* * Bulk +* * Interrupt +* * Isochronous +* * Control */ #pragma once @@ -45,6 +53,10 @@ extern "C" { #endif +/** + * \addtogroup group_hal_usb_dev_common Common + * \{ + */ /** The usb error */ #define CYHAL_USB_DEV_RSLT_ERR (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_USB, 0)) @@ -54,7 +66,9 @@ extern "C" { /** The configuration of USB clock failed */ #define CYHAL_USB_DEV_RSLT_ERR_CLK_CFG (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CYHAL_RSLT_MODULE_USB, 2)) -/** +/** \} group_hal_usb_dev_common */ + +/** * \addtogroup group_hal_usb_dev_endpoint Endpoint * \{ * APIs relating to endpoint management @@ -79,6 +93,11 @@ typedef enum /** \} group_hal_usb_dev_endpoint */ +/** + * \addtogroup group_hal_usb_dev_common Common + * \{ + */ + /** Service Callback Events */ typedef enum { @@ -88,20 +107,22 @@ typedef enum CYHAL_USB_DEV_EVENT_EP0_OUT, /**< Callback hooked to endpoint 0 OUT packet interrupt */ } cyhal_usb_dev_event_t; -/** - * USB endpoint address (consists from endpoint number and direction) - * - * \ingroup group_hal_usb_dev_endpoint +/** + * USB endpoint address (consists from endpoint number and direction) + * + * \ingroup group_hal_usb_dev_endpoint */ typedef uint8_t cyhal_usb_dev_ep_t; -/** Callback handler for USB Device interrupt */ +/** + * Callback handler for USB Device interrupt + */ typedef void (*cyhal_usb_dev_irq_callback_t)(void); -/** +/** * Callback handler for the transfer completion event for data endpoints (not applicable for endpoint 0) - * - * \ingroup group_hal_usb_dev_endpoint + * + * \ingroup group_hal_usb_dev_endpoint */ typedef void (* cyhal_usb_dev_endpoint_callback_t)(cyhal_usb_dev_ep_t endpoint); @@ -190,7 +211,9 @@ typedef void (*cyhal_usb_dev_sof_callback_t)(uint32_t frame_number); */ void cyhal_usb_dev_set_address(cyhal_usb_dev_t *obj, uint8_t address); -/** +/** \} group_hal_usb_dev_common */ + +/** * \addtogroup group_hal_usb_dev_ep0 EP0 * \{ * APIs relating specifically to management of endpoint zero @@ -257,7 +280,7 @@ uint32_t cyhal_usb_dev_ep0_get_max_packet(cyhal_usb_dev_t *obj); /** \} group_hal_usb_dev_ep0 */ /** - * \addtogroup group_hal_usb_dev_endpoint + * \addtogroup group_hal_usb_dev_endpoint * \{ */ @@ -382,6 +405,11 @@ cy_rslt_t cyhal_usb_dev_endpoint_add(cyhal_usb_dev_t *obj, bool alloc, bool enab /** \} group_hal_usb_dev_endpoint */ +/** + * \addtogroup group_hal_usb_dev_common Common + * \{ + */ + /** The USB Device callback handler registration * * @param[in,out] obj The usb device object @@ -412,8 +440,8 @@ void cyhal_usb_dev_process_irq(cyhal_usb_dev_t *obj); * @param[in,out] obj The usb device object * @param[in] endpoint Endpoint to registers handler * @param[in] callback The callback handler which will be invoked when the endpoint comp - * - * \ingroup group_hal_usb_dev_endpoint + * + * \ingroup group_hal_usb_dev_endpoint */ void cyhal_usb_dev_register_endpoint_callback(cyhal_usb_dev_t *obj, cyhal_usb_dev_ep_t endpoint, cyhal_usb_dev_endpoint_callback_t callback); @@ -434,6 +462,8 @@ void cyhal_usb_dev_register_event_callback(cyhal_usb_dev_t *obj, cyhal_usb_dev_e */ void cyhal_usb_dev_register_sof_callback( cyhal_usb_dev_t *obj, cyhal_usb_dev_sof_callback_t callback); +/** \} group_hal_usb_dev_common */ + #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_utils.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_utils.h index 3f457af2fd4..b6c45d1f1f7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_utils.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_utils.h @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -22,13 +22,16 @@ * limitations under the License. *******************************************************************************/ +/** \cond INTERNAL */ /** -* \addtogroup group_hal_psoc6 PSoC 6 Implementation +* \addtogroup group_hal_psoc6 PSoC 6 Implementation Specific * \{ +* Common utility macros & functions used by multiple HAL drivers. */ #pragma once +#include "cy_result.h" #include "cyhal_hw_types.h" #include "cy_utils.h" @@ -37,16 +40,9 @@ extern "C" { #endif -/** - * \addtogroup group_hal_psoc6_interrupts Interrupts - * \{ - */ #define CYHAL_IRQN_OFFSET 16 /**< Offset for implementation-defined ISR type numbers (IRQ0 = 16) */ #define CYHAL_GET_CURRENT_IRQN() ((IRQn_Type) (__get_IPSR() - CYHAL_IRQN_OFFSET)) /**< Macro to get the IRQn of the current ISR */ -/** \} group_hal_psoc6_interrupts */ - - /** * \addtogroup group_hal_psoc6_pin_package * \{ @@ -84,21 +80,30 @@ static inline cyhal_resource_inst_t cyhal_utils_get_gpio_resource(cyhal_gpio_t p */ const cyhal_resource_pin_mapping_t *cyhal_utils_get_resource(cyhal_gpio_t pin, const cyhal_resource_pin_mapping_t* mappings, size_t count); +/** Attempts to reserve the specified pin and then initialize it to connect to the item defined by the provided mapping object. + * @param[in] pin The pin to reserve and connect + * @param[in] mapping The pin/hardware block connection mapping information + * @return CY_RSLT_SUCCESS if everything was ok, else an error. + */ +cy_rslt_t cyhal_utils_reserve_and_connect(cyhal_gpio_t pin, const cyhal_resource_pin_mapping_t *mapping); + /** Disconnects any routing for the pin from the interconnect driver and then free's the pin from the hwmgr. * * @param[in] pin The pin to disconnect and free */ void cyhal_utils_disconnect_and_free(cyhal_gpio_t pin); -/** \} group_hal_psoc6_pin_package */ +/** Checks to see if the provided pin is a no-connect (CYHAL_NC_PIN_VALUE). If not, calls + * cyhal_utils_disconnect_and_free(). + * + * @param[in] pin The pin to disconnect and free + */ +void cyhal_utils_release_if_used(cyhal_gpio_t *pin); -/** -* \addtogroup group_hal_psoc6_clocks Clocks -* \{ -*/ +/** \} group_hal_psoc6_pin_package */ /** Calculate the peri clock divider value that need to be set to reach frequency closest to the input frequency - * + * * @param[in] frequency The desired frequency * @param[in] frac_bits The number of fractional bits that the divider has * @return The calculate divider value to set, NOTE a divider value of x divide the frequency by (x+1) @@ -108,7 +113,13 @@ static inline uint32_t cyhal_divider_value(uint32_t frequency, uint32_t frac_bit return ((Cy_SysClk_ClkPeriGetFrequency() * (1 << frac_bits)) + (frequency / 2)) / frequency - 1; } -/** \} group_hal_psoc6_clocks */ +/** Determine if two resources are the same + * + * @param[in] resource1 First resource to compare + * @param[in] resource2 Second resource to compare + * @return Boolean indicating whether two resources are the same + */ +bool cyhal_utils_resources_equal(const cyhal_resource_inst_t *resource1, const cyhal_resource_inst_t *resource2); #if defined(__cplusplus) } @@ -116,3 +127,4 @@ static inline uint32_t cyhal_divider_value(uint32_t frequency, uint32_t frac_bit /** \} group_hal_psoc6_utils */ /** \} group_hal_psoc6 */ +/** \endcond */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_wdt.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_wdt.h index ea82d395505..07d85c16f3b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_wdt.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/cyhal_wdt.h @@ -29,7 +29,35 @@ * \addtogroup group_hal_wdt WDT (Watchdog Timer) * \ingroup group_hal * \{ -* High level interface for interacting with the Cypress WDT. +* High level interface to the Watchdog Timer (WDT). +* +* cyhal_wdt_init() initializes the WDT and passes a pointer to the WDT block through obj. +* The timeout_ms parameter takes in the timeout in milliseconds. +* It can be used for recovering from a CPU or firmware failure. + The watchdog timer is initialized with a timeout interval. Once the WDT is started, + if cyhal_wdt_kick() must be called at least once within the timeout interval. In case + the firmware fails to do so, it is considered to be a CPU crash or firmware failure and the device + will be reset. +* +* +*\section subsection_wdt_features Features +* WDT supports Device Reset generation if not serviced within the configured timeout interval. +* +* +* \section subsection_wdt_quickstart Quick Start +* +* \ref cyhal_wdt_init() can be used for initialization by providing the WDT object (obj) and the timeout parameter +* (timeout period in ms). +* The timeout parameter can have a minimum value of 1ms. The maximum value of the timeout +* parameter can be obtained using the cyhal_wdt_get_max_timeout_ms(). +* +* +* \section subsection_wdt_sample_use_case Sample use case +* +* \subsection subsection_wdt_use_case Use Case: Initialization and reset functionality +* The following snippet initializes the WDT and depicts the reset functionality of WDT in case of CPU or +* firmware failure. +* \snippet wdt.c snippet_cyhal_wdt_init_and_reset */ #pragma once @@ -54,6 +82,8 @@ extern "C" { * @param[out] obj The WDT object * @param[in] timeout_ms The time in milliseconds before the WDT times out (1ms - max) (see cyhal_wdt_get_max_timeout_ms()) * @return The status of the init request +* +* Returns \ref CY_RSLT_SUCCESS if the operation was successfull. */ cy_rslt_t cyhal_wdt_init(cyhal_wdt_t *obj, uint32_t timeout_ms); @@ -65,7 +95,9 @@ cy_rslt_t cyhal_wdt_init(cyhal_wdt_t *obj, uint32_t timeout_ms); * undefined. * * @param[inout] obj The WDT object +* */ + void cyhal_wdt_free(cyhal_wdt_t *obj); /** Refresh the WDT @@ -74,11 +106,13 @@ void cyhal_wdt_free(cyhal_wdt_t *obj); * In the event of a timeout, the WDT resets the system. * * @param[inout] obj The WDT object +* +* See \ref subsection_wdt_use_case */ void cyhal_wdt_kick(cyhal_wdt_t *obj); /** Start the WDT -* +* * Enables the WDT. * * @param[inout] obj The WDT object @@ -87,7 +121,7 @@ void cyhal_wdt_kick(cyhal_wdt_t *obj); void cyhal_wdt_start(cyhal_wdt_t *obj); /** Stop the WDT -* +* * Disables the WDT. * * @param[inout] obj The WDT object @@ -98,13 +132,13 @@ void cyhal_wdt_stop(cyhal_wdt_t *obj); /** Get the WDT timeout * * Gets the time in milliseconds before the WDT times out. -* +* * @param[inout] obj The WDT object * @return The time in milliseconds before the WDT times out */ uint32_t cyhal_wdt_get_timeout_ms(cyhal_wdt_t *obj); -/** Gets the maximum WDT timeout +/** Gets the maximum WDT timeout * * Gets the maximum timeout for the WDT. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble.h index c45650269f3..23d2e856c68 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO HAL header for 104-M-CSP-BLE package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21430 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,97 +30,107 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_01_104_m_csp_ble PSoC6_01 104-M-CSP-BLE + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 104-M-CSP-BLE package for the PSoC6_01 series. */ typedef enum { - NC = (int)0xFFFFFFFF, - - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), - P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), - P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), - P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), - - P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), - P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), - P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), - P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), - P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), - - P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), - P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), - P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), - P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), - P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), - P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), - P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), - P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), - - P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), - P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), - - P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), - P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), - P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), - P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), - P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), - - P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), - P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), - P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), - P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), - P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), - P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), - P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), - P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), - - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), - - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), - P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), - P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), - P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), - P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), - P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), - - P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), - P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), - P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), - P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), - P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), - P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), - P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), - P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), - - P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), - P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), - P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), - P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), - P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), - - P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), - P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), -} cyhal_gpio_t; + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin + + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 + P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 + P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 + P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 + + P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 + P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 + P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3 + P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4 + P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5 + + P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 + P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 + P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 + P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 + P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 + P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5 + P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 + P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7 + + P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 + P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 + + P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 + P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 + P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 + P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6 + P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 + + P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 + P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 + P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 + P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 + P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4 + P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), //!< Port 8 Pin 5 + P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), //!< Port 8 Pin 6 + P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), //!< Port 8 Pin 7 + + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 + + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 + P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 + P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 + P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 + P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 + P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7 + + P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 + P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 + P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 + P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 + P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 + P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 + P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 + P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 + + P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 + P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 + P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 + P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 + P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 + + P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0 + P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1 +} cyhal_gpio_psoc6_01_104_m_csp_ble_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_01_104_m_csp_ble_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -132,90 +142,171 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ +/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1]; +/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2]; +/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[1]; +/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1]; +/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1]; +/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1]; +/** List of valid pin to peripheral connections for the bless_ext_lna_rx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_lna_chip_en_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_tx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_bpktctl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_rx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_tx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_txd_rxd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_act_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_buck_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_clk_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_dig_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_isolate_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_mxd_clk_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_le signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_reset_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_ldo_ol_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_switch_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_xtal_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa0_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa1_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[4]; +/** List of valid pin to peripheral connections for the pass_ctdac_voutsw signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[14]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[12]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[13]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[9]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[8]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[6]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[12]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[14]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[14]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[13]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[9]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[8]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[6]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[11]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[10]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[12]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[12]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; +/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; +/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; +/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[68]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[68]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_01_104_M_CSP_BLE_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.h index d09252f4242..cd4fb18d4a9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO HAL header for 104-M-CSP-BLE-USB package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21430 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,99 +30,109 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_01_104_m_csp_ble_usb PSoC6_01 104-M-CSP-BLE-USB + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 104-M-CSP-BLE-USB package for the PSoC6_01 series. */ typedef enum { - NC = (int)0xFFFFFFFF, - - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), - P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), - P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), - P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), - - P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), - P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), - P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), - P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), - - P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), - P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), - P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), - P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), - P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), - P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), - P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), - P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), - - P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), - P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), - - P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), - P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), - P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), - P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), - P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), - - P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), - P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), - P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), - P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), - P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), - P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), - P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), - P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), - - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), - - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), - P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), - P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), - P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), - P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), - P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), - - P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), - P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), - P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), - P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), - P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), - P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), - P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), - P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), - - P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), - P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), - P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), - P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), - P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), - - P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), - P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), - - USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), - USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), -} cyhal_gpio_t; + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin + + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 + P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 + P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 + P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 + + P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 + P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 + P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4 + P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5 + + P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 + P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 + P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 + P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 + P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 + P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5 + P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 + P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7 + + P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 + P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 + + P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 + P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 + P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 + P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6 + P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 + + P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 + P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 + P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 + P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 + P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4 + P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), //!< Port 8 Pin 5 + P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), //!< Port 8 Pin 6 + P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), //!< Port 8 Pin 7 + + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 + + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 + P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 + P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 + P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 + P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 + P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7 + + P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 + P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 + P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 + P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 + P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 + P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 + P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 + P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 + + P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 + P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 + P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 + P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 + P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 + + P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0 + P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1 + + USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 + USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 +} cyhal_gpio_psoc6_01_104_m_csp_ble_usb_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_01_104_m_csp_ble_usb_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -134,90 +144,171 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ +/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1]; +/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2]; +/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[1]; +/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1]; +/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1]; +/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1]; +/** List of valid pin to peripheral connections for the bless_ext_lna_rx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_lna_chip_en_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_tx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_bpktctl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_rx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_tx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_txd_rxd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_act_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_buck_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_clk_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_dig_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_isolate_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_mxd_clk_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_le signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_reset_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_ldo_ol_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_switch_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_xtal_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa0_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa1_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[4]; +/** List of valid pin to peripheral connections for the pass_ctdac_voutsw signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[14]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[12]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[12]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[9]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[8]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[6]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[12]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[14]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[14]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[12]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[9]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[8]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[6]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[10]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[10]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[12]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[12]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; +/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; +/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; +/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[68]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[66]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_01_104_M_CSP_BLE_USB_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_116_bga_ble.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_116_bga_ble.h index 0dc0fa4c2d7..7fa08a272e4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_116_bga_ble.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_116_bga_ble.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO HAL header for 116-BGA-BLE package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21430 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,105 +30,115 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_01_116_bga_ble PSoC6_01 116-BGA-BLE + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 116-BGA-BLE package for the PSoC6_01 series. */ typedef enum { - NC = (int)0xFFFFFFFF, - - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), - P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), - P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), - P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), - - P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), - P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), - P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), - P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), - P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), - P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), - - P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), - P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), - P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), - P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), - P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), - P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), - P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), - - P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), - P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), - - P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), - P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), - P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), - P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), - P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), - - P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), - P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), - P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), - P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), - P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), - P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), - P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), - P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), - - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), - P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), - P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), - P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), - P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), - - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), - P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), - P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), - P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), - P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), - - P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), - P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), - P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), - P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), - P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), - P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), - P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), - P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), - - P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), - P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), - P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), - P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), - P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), - P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), - P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), - P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), - - P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), - P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), - P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), - P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), -} cyhal_gpio_t; + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin + + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 + P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 + P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 + P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 + + P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 + P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 + P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2 + P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3 + P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4 + P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5 + + P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 + P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 + P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 + P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 + P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 + P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5 + P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 + + P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 + P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 + + P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 + P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 + P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 + P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6 + P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 + + P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 + P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 + P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 + P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 + P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4 + P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), //!< Port 8 Pin 5 + P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), //!< Port 8 Pin 6 + P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), //!< Port 8 Pin 7 + + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 + P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4 + P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), //!< Port 9 Pin 5 + P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), //!< Port 9 Pin 6 + P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), //!< Port 9 Pin 7 + + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 + P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 + P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 + P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 + P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 + + P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 + P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 + P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 + P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 + P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 + P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 + P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 + P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 + + P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 + P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 + P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 + P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 + P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 + P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5 + P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 + P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 + + P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0 + P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1 + P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6 + P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7 +} cyhal_gpio_psoc6_01_116_bga_ble_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_01_116_bga_ble_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -140,90 +150,171 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ +/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1]; +/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2]; +/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2]; +/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1]; +/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1]; +/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1]; +/** List of valid pin to peripheral connections for the bless_ext_lna_rx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_lna_chip_en_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_tx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_bpktctl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_rx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_tx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_txd_rxd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_act_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_buck_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_clk_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_dig_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_isolate_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_mxd_clk_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_le signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_reset_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_ldo_ol_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_switch_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_xtal_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa0_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa1_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[8]; +/** List of valid pin to peripheral connections for the pass_ctdac_voutsw signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[7]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[14]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[13]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[13]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[10]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[10]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[8]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[13]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[14]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[14]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[13]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[10]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[10]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[8]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[11]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[11]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[12]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[12]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; +/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; +/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; +/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[78]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[74]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_01_116_BGA_BLE_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_116_bga_usb.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_116_bga_usb.h index d615df7c83c..c094b0d3d4f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_116_bga_usb.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_116_bga_usb.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO HAL header for 116-BGA-USB package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21430 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,105 +30,115 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_01_116_bga_usb PSoC6_01 116-BGA-USB + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 116-BGA-USB package for the PSoC6_01 series. */ typedef enum { - NC = (int)0xFFFFFFFF, - - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), - P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), - P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), - P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), - - P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), - P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), - P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), - - P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), - P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), - P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), - P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), - P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), - P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), - P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), - - P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), - P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), - - P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), - P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), - P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), - P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), - P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), - - P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), - P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), - P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), - P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), - P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), - P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), - P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), - P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), - - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), - P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), - P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), - P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), - P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), - - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), - P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), - P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), - P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), - P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), - - P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), - P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), - P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), - P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), - P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), - P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), - P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), - P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), - - P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), - P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), - P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), - P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), - P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), - P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), - P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), - P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), - - P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), - P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), - P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), - P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), - - USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), - USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), -} cyhal_gpio_t; + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin + + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 + P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 + P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 + P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 + + P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 + P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 + P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2 + + P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 + P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 + P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 + P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 + P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 + P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5 + P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 + + P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 + P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 + + P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 + P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 + P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 + P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6 + P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 + + P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 + P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 + P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 + P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 + P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4 + P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), //!< Port 8 Pin 5 + P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), //!< Port 8 Pin 6 + P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), //!< Port 8 Pin 7 + + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 + P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4 + P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), //!< Port 9 Pin 5 + P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), //!< Port 9 Pin 6 + P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), //!< Port 9 Pin 7 + + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 + P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 + P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 + P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 + P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 + + P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 + P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 + P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 + P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 + P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 + P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 + P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 + P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 + + P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 + P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 + P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 + P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 + P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 + P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5 + P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 + P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 + + P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0 + P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1 + P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6 + P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7 + + USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 + USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 +} cyhal_gpio_psoc6_01_116_bga_usb_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_01_116_bga_usb_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -140,90 +150,171 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ +/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1]; +/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2]; +/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2]; +/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1]; +/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1]; +/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1]; +/** List of valid pin to peripheral connections for the bless_ext_lna_rx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_lna_chip_en_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_tx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_bpktctl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_rx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_tx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_txd_rxd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_act_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_buck_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_clk_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_dig_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_isolate_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_mxd_clk_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_le signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_reset_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_ldo_ol_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_switch_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_xtal_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa0_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa1_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[8]; +/** List of valid pin to peripheral connections for the pass_ctdac_voutsw signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[7]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[14]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[13]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[12]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[9]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[9]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[8]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[13]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[14]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[14]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[12]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[9]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[9]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[8]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[10]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[11]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[12]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[12]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; +/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; +/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; +/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[76]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[70]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_01_116_BGA_USB_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_124_bga.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_124_bga.h index 55b576ad6ae..cc40e138c7a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_124_bga.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_124_bga.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO HAL header for 124-BGA package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21430 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,133 +30,143 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_01_124_bga PSoC6_01 124-BGA + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 124-BGA package for the PSoC6_01 series. */ typedef enum { - NC = (int)0xFFFFFFFF, + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin + + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 + P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 + P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 + P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), - P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), - P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), - P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), + P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 + P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 + P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2 + P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3 + P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4 + P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5 - P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), - P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), - P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), - P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), - P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), - P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), + P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 + P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 + P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 + P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 + P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4 + P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5 + P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), //!< Port 2 Pin 6 + P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), //!< Port 2 Pin 7 - P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), - P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), - P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), - P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), - P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), - P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), - P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), - P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), + P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 + P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1 + P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2), //!< Port 3 Pin 2 + P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3), //!< Port 3 Pin 3 + P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4), //!< Port 3 Pin 4 + P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5), //!< Port 3 Pin 5 - P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), - P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), - P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2), - P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3), - P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4), - P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5), + P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0), //!< Port 4 Pin 0 + P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1), //!< Port 4 Pin 1 - P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0), - P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1), + P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 + P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 + P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 + P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 + P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 + P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5 + P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 + P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7 - P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), - P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), - P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), - P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), - P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), - P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), - P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), - P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), + P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 + P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 - P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), - P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), + P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 + P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 + P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 + P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6 + P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 - P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), - P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), - P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), - P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), - P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), + P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 + P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 + P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 + P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 + P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4 + P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), //!< Port 8 Pin 5 + P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), //!< Port 8 Pin 6 + P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), //!< Port 8 Pin 7 - P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), - P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), - P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), - P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), - P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), - P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), - P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), - P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 + P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4 + P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), //!< Port 9 Pin 5 + P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), //!< Port 9 Pin 6 + P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), //!< Port 9 Pin 7 - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), - P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), - P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), - P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), - P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 + P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 + P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 + P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 + P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 + P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7 - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), - P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), - P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), - P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), - P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), - P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), + P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 + P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 + P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 + P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 + P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 + P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 + P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 + P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 - P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), - P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), - P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), - P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), - P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), - P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), - P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), - P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), + P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 + P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 + P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 + P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 + P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 + P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5 + P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 + P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 - P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), - P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), - P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), - P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), - P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), - P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), - P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), - P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), + P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0 + P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1 + P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), //!< Port 13 Pin 2 + P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), //!< Port 13 Pin 3 + P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), //!< Port 13 Pin 4 + P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), //!< Port 13 Pin 5 + P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6 + P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7 - P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), - P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), - P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), - P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), - P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), - P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), - P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), - P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), + USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 + USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 +} cyhal_gpio_psoc6_01_124_bga_t; - USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), - USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), -} cyhal_gpio_t; +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_01_124_bga_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -168,90 +178,171 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ +/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1]; +/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2]; +/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2]; +/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1]; +/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1]; +/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1]; +/** List of valid pin to peripheral connections for the bless_ext_lna_rx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_lna_chip_en_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_tx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_bpktctl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_rx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_tx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_txd_rxd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_act_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_buck_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_clk_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_dig_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_isolate_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_mxd_clk_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_le signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_reset_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_ldo_ol_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_switch_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_xtal_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa0_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa1_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[8]; +/** List of valid pin to peripheral connections for the pass_ctdac_voutsw signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[17]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[17]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[16]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[17]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[17]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[16]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[13]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[13]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[10]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[16]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[17]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[17]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[16]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[13]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[13]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[10]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[14]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[14]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[15]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[15]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; +/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; +/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; +/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[98]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[98]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_01_124_BGA_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_124_bga_sip.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_124_bga_sip.h index ab95e612f2d..29cf77d337e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_124_bga_sip.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_124_bga_sip.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO HAL header for 124-BGA-SIP package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21430 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,114 +30,124 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_01_124_bga_sip PSoC6_01 124-BGA-SIP + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 124-BGA-SIP package for the PSoC6_01 series. */ typedef enum { - NC = (int)0xFFFFFFFF, - - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), - P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), - P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), - P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), - - P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), - P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), - P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), - P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), - P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), - P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), - - P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), - P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), - P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), - P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), - P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), - P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), - P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), - P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), - - P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), - P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), - - P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), - P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), - P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), - P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), - P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), - - P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), - P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), - P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), - P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), - P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), - P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), - P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), - P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), - - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), - P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), - P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), - P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), - P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), - - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), - P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), - P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), - P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), - P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), - P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), - - P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), - P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), - P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), - P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), - P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), - P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), - P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), - P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), - - P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), - P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), - P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), - P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), - P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), - P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), - P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), - P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), - - P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), - P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), - P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), - P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), - P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), - P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), - P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), - P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), - - USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), - USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), -} cyhal_gpio_t; + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin + + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 + P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 + P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 + P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 + + P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 + P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 + P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2 + P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3 + P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4 + P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5 + + P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 + P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 + P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 + P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 + P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 + P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5 + P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 + P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7 + + P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 + P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 + + P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 + P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 + P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 + P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6 + P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 + + P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 + P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 + P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 + P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 + P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4 + P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), //!< Port 8 Pin 5 + P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), //!< Port 8 Pin 6 + P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), //!< Port 8 Pin 7 + + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 + P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4 + P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), //!< Port 9 Pin 5 + P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), //!< Port 9 Pin 6 + P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), //!< Port 9 Pin 7 + + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 + P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 + P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 + P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 + P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 + P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7 + + P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 + P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 + P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 + P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 + P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 + P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 + P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 + P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 + + P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 + P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 + P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 + P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 + P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 + P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5 + P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 + P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 + + P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0 + P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1 + P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), //!< Port 13 Pin 2 + P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), //!< Port 13 Pin 3 + P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), //!< Port 13 Pin 4 + P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), //!< Port 13 Pin 5 + P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6 + P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7 + + USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 + USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 +} cyhal_gpio_psoc6_01_124_bga_sip_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_01_124_bga_sip_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -149,90 +159,171 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ +/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1]; +/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2]; +/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2]; +/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1]; +/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1]; +/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1]; +/** List of valid pin to peripheral connections for the bless_ext_lna_rx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_lna_chip_en_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_tx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_bpktctl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_rx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_tx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_txd_rxd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_act_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_buck_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_clk_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_dig_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_isolate_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_mxd_clk_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_le signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_reset_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_ldo_ol_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_switch_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_xtal_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa0_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa1_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[8]; +/** List of valid pin to peripheral connections for the pass_ctdac_voutsw signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[14]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[11]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[11]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[9]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[14]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[14]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[14]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[14]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[11]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[11]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[9]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[12]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[12]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[12]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[12]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; +/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; +/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; +/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[82]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[82]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_01_124_BGA_SIP_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_43_smt.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_43_smt.h index 07646d2fee5..45dc91b498d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_43_smt.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_43_smt.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO HAL header for 43-SMT package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21430 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,59 +30,69 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_01_43_smt PSoC6_01 43-SMT + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 43-SMT package for the PSoC6_01 series. */ typedef enum { - NC = (int)0xFFFFFFFF, - - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), - P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), - - P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), - P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), - P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), - P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), - P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), - P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), - P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), - - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), - - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), - - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), - P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), - P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), - P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), - - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), - P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), - P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), - P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), - P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), - - P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), - P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), -} cyhal_gpio_t; + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin + + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 + P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 + + P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 + P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 + P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 + P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 + P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 + P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5 + P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 + + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 + + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 + + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 + P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4 + P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), //!< Port 9 Pin 5 + P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), //!< Port 9 Pin 6 + + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 + P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 + P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 + P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 + P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 + + P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 + P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 +} cyhal_gpio_psoc6_01_43_smt_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_01_43_smt_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -94,90 +104,171 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ +/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1]; +/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[1]; +/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[1]; +/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1]; +/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1]; +/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1]; +/** List of valid pin to peripheral connections for the bless_ext_lna_rx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_lna_chip_en_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_tx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_bpktctl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_rx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_tx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_txd_rxd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_act_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_buck_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_clk_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_dig_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_isolate_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_mxd_clk_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_le signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_reset_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_ldo_ol_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_switch_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_xtal_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa0_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa1_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[7]; +/** List of valid pin to peripheral connections for the pass_ctdac_voutsw signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[7]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[5]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[6]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[9]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[6]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[5]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[8]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[5]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[4]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[4]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[9]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[6]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[5]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[8]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[5]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[4]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[4]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[6]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[7]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[4]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[5]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; +/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; +/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; +/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[38]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[34]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_01_43_SMT_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_68_qfn_ble.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_68_qfn_ble.h index 3e3df464af1..011c6a70353 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_68_qfn_ble.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_68_qfn_ble.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO HAL header for 68-QFN-BLE package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21430 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,65 +30,75 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_01_68_qfn_ble PSoC6_01 68-QFN-BLE + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 68-QFN-BLE package for the PSoC6_01 series. */ typedef enum { - NC = (int)0xFFFFFFFF, - - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), - P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), - P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), - P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), - - P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), - P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), - - P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), - P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), - P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), - P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), - P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), - - P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), - P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), - P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), - - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), - - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - - P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), - P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), - P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), - P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), - P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), - P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), - P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), - P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), - - P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), - P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), -} cyhal_gpio_t; + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin + + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 + P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 + P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 + P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 + + P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 + P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 + + P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 + P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 + P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 + P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6 + P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 + + P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 + P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 + P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 + + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 + + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + + P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 + P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 + P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 + P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 + P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 + P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 + P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 + P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 + + P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 + P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 +} cyhal_gpio_psoc6_01_68_qfn_ble_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_01_68_qfn_ble_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -100,90 +110,171 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ +/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1]; +/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[1]; +/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[1]; +/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1]; +/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1]; +/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1]; +/** List of valid pin to peripheral connections for the bless_ext_lna_rx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_lna_chip_en_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_tx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_bpktctl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_rx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_tx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_txd_rxd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_act_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_buck_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_clk_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_dig_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_isolate_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_mxd_clk_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_le signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_reset_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_ldo_ol_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_switch_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_xtal_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa0_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa1_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[4]; +/** List of valid pin to peripheral connections for the pass_ctdac_voutsw signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[2]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[10]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[10]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[9]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[10]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[10]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[8]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[4]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[3]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[3]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[9]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[10]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[10]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[8]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[4]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[3]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[3]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[6]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[7]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[8]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[8]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; +/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; +/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; +/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[40]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[38]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_01_68_QFN_BLE_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_80_wlcsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_80_wlcsp.h index b5d10fba7f6..1460a23a72a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_80_wlcsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_01_80_wlcsp.h @@ -5,11 +5,11 @@ * PSoC6_01 device GPIO HAL header for 80-WLCSP package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21430 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,91 +30,101 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_01_80_wlcsp PSoC6_01 80-WLCSP + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 80-WLCSP package for the PSoC6_01 series. */ typedef enum { - NC = (int)0xFFFFFFFF, - - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), - P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), - P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), - P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), - - P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), - P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), - P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), - P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), - - P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), - P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), - P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), - P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), - P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), - P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), - P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), - P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), - - P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), - P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), - - P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), - P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), - - P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), - P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), - P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), - P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), - P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), - - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), - P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), - P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), - - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), - P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), - - P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), - P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), - P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), - P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), - P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), - P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), - P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), - P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), - - P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), - P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), - P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), - P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), - P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), - P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), - P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), - P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), - - USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), - USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), -} cyhal_gpio_t; + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin + + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 + P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 + P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 + P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 + + P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 + P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 + P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4 + P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5 + + P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 + P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 + P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 + P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 + P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 + P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5 + P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 + P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7 + + P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 + P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 + + P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 + P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 + + P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 + P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 + P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 + P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 + P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4 + + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 + P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4 + P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), //!< Port 9 Pin 7 + + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 + P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 + + P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 + P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 + P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 + P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 + P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 + P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 + P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 + P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 + + P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 + P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 + P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 + P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 + P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 + P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5 + P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 + P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 + + USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 + USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 +} cyhal_gpio_psoc6_01_80_wlcsp_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_01_80_wlcsp_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -126,90 +136,171 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ +/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[1]; +/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2]; +/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2]; +/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[1]; +/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[1]; +/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[1]; +/** List of valid pin to peripheral connections for the bless_ext_lna_rx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_lna_rx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_lna_chip_en_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_lna_chip_en_out[1]; +/** List of valid pin to peripheral connections for the bless_ext_pa_tx_ctl_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_ext_pa_tx_ctl_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_bpktctl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_bpktctl[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_rx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_rx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_dbus_tx_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_dbus_tx_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_act_txd_rxd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_act_txd_rxd[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_act_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_act_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_buck_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_buck_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_clk_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_clk_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_dig_ldo_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_dig_ldo_en[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_isolate_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_isolate_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_mxd_clk_out signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_mxd_clk_out[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_clk[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_data[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_rcb_le signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_rcb_le[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_reset_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_reset_n[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_ldo_ol_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_ldo_ol_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_ret_switch_hv signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_ret_switch_hv[1]; +/** List of valid pin to peripheral connections for the bless_mxd_dpslp_xtal_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_bless_mxd_dpslp_xtal_en[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa0_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa0_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_oa1_out_10x signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_oa1_out_10x[1]; +/** List of valid pin to peripheral connections for the pass_ctb_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctb_pads[6]; +/** List of valid pin to peripheral connections for the pass_ctdac_voutsw signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_ctdac_voutsw[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp0[1]; +/** List of valid pin to peripheral connections for the pass_dsi_ctb_cmp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_dsi_ctb_cmp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[4]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[13]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[13]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[11]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[13]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[13]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[11]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[9]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[6]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[4]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[11]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[13]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[13]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[11]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[9]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[6]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[4]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[9]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[9]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[11]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[11]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; +/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; +/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; +/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[60]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[60]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_01_80_WLCSP_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_100_wlcsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_100_wlcsp.h index ddfc61981e2..ce59f33cebf 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_100_wlcsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_100_wlcsp.h @@ -5,11 +5,11 @@ * PSoC6_02 device GPIO HAL header for 100-WLCSP package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21305 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,113 +30,123 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_02_100_wlcsp PSoC6_02 100-WLCSP + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 100-WLCSP package for the PSoC6_02 series. */ typedef enum { - NC = (int)0xFFFFFFFF, - - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), - P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), - P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), - P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), - - P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), - P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), - P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), - P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), - - P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), - P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), - P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), - P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), - P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), - P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), - P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), - P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), - - P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), - P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), - P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), - P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), - P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), - P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), - P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), - P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), - - P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), - P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), - - P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), - P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), - - P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), - P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), - P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), - P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), - P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), - - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), - P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), - P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), - - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), - P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), - P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), - P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), - P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), - P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), - - P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), - P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), - P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), - P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), - P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), - P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), - P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), - P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), - - P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), - P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), - P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), - P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), - P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), - P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), - P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), - P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), - - P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), - P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), - P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), - P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), - P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), - P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), - P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), - P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), - - USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), - USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), -} cyhal_gpio_t; + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin + + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 + P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 + P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 + P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 + + P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 + P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 + P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4 + P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5 + + P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 + P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 + P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 + P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 + P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4 + P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5 + P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), //!< Port 2 Pin 6 + P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), //!< Port 2 Pin 7 + + P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 + P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 + P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 + P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 + P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 + P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5 + P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 + P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7 + + P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 + P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 + + P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 + P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 + + P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 + P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 + P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 + P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 + P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4 + + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 + P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4 + P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), //!< Port 9 Pin 7 + + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 + P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 + P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 + P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 + P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 + P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7 + + P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 + P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 + P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 + P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 + P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 + P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 + P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 + P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 + + P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 + P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 + P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 + P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 + P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 + P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5 + P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 + P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 + + P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0 + P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1 + P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), //!< Port 13 Pin 2 + P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), //!< Port 13 Pin 3 + P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), //!< Port 13 Pin 4 + P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), //!< Port 13 Pin 5 + P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6 + P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7 + + USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 + USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 +} cyhal_gpio_psoc6_02_100_wlcsp_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_02_100_wlcsp_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -148,74 +158,139 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ +/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[4]; +/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2]; +/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2]; +/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[4]; +/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[3]; +/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[3]; +/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[4]; +/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[4]; +/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[4]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[19]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[18]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[15]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[15]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[14]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[11]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[8]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[7]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[14]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[15]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[15]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[14]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[11]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[8]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[7]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[15]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[15]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[17]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[16]; +/** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[2]; +/** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[8]; +/** List of valid pin to peripheral connections for the sdhc_card_dat_7to4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[4]; +/** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[2]; +/** List of valid pin to peripheral connections for the sdhc_card_emmc_reset_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_emmc_reset_n[1]; +/** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[1]; +/** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[2]; +/** List of valid pin to peripheral connections for the sdhc_clk_card signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[2]; +/** List of valid pin to peripheral connections for the sdhc_io_volt_sel signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[1]; +/** List of valid pin to peripheral connections for the sdhc_led_ctrl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_led_ctrl[1]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; +/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; +/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; +/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[80]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[80]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_02_100_WLCSP_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_124_bga.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_124_bga.h index 9ff888efd7c..61ff82afb5e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_124_bga.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_124_bga.h @@ -5,11 +5,11 @@ * PSoC6_02 device GPIO HAL header for 124-BGA package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21305 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,133 +30,143 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_02_124_bga PSoC6_02 124-BGA + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 124-BGA package for the PSoC6_02 series. */ typedef enum { - NC = (int)0xFFFFFFFF, - - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), - P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), - P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), - P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), - - P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), - P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), - P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), - P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), - P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), - P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), - - P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), - P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), - P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), - P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), - P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), - P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), - P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), - P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), - - P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), - P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), - P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2), - P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3), - P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4), - P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5), - - P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0), - P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1), - - P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), - P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), - P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), - P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), - P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), - P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), - P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), - P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), - - P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), - P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), - - P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), - P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), - P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), - P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), - P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), - - P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), - P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), - P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), - P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), - P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), - P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), - P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), - P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), - - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), - P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), - P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), - P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), - P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), - - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), - P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), - P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), - P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), - P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), - P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), - - P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), - P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), - P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), - P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), - P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), - P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), - P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), - P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), - - P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), - P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), - P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), - P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), - P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), - P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), - P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), - P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), - - P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), - P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), - P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), - P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), - P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), - P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), - P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), - P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), - - USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), - USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), -} cyhal_gpio_t; + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin + + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 + P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 + P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 + P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 + + P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 + P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 + P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2 + P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3 + P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4 + P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5 + + P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 + P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 + P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 + P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 + P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4 + P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5 + P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), //!< Port 2 Pin 6 + P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), //!< Port 2 Pin 7 + + P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 + P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1 + P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2), //!< Port 3 Pin 2 + P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3), //!< Port 3 Pin 3 + P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4), //!< Port 3 Pin 4 + P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5), //!< Port 3 Pin 5 + + P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0), //!< Port 4 Pin 0 + P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1), //!< Port 4 Pin 1 + + P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 + P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 + P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 + P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 + P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 + P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5 + P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 + P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7 + + P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 + P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 + + P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 + P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 + P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 + P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6 + P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 + + P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 + P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 + P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 + P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 + P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4 + P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), //!< Port 8 Pin 5 + P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), //!< Port 8 Pin 6 + P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), //!< Port 8 Pin 7 + + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 + P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4 + P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), //!< Port 9 Pin 5 + P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), //!< Port 9 Pin 6 + P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), //!< Port 9 Pin 7 + + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 + P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 + P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 + P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 + P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 + P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7 + + P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 + P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 + P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 + P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 + P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 + P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 + P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 + P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 + + P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 + P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 + P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 + P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 + P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 + P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5 + P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 + P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 + + P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0 + P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1 + P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), //!< Port 13 Pin 2 + P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), //!< Port 13 Pin 3 + P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), //!< Port 13 Pin 4 + P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), //!< Port 13 Pin 5 + P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6 + P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7 + + USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 + USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 +} cyhal_gpio_psoc6_02_124_bga_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_02_124_bga_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -168,74 +178,139 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ +/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[4]; +/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2]; +/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2]; +/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[4]; +/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[4]; +/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[4]; +/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[4]; +/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[4]; +/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[4]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[21]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[21]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[16]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[17]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[17]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[16]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[13]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[13]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[10]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[16]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[17]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[17]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[16]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[13]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[13]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[10]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[18]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[18]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[19]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[19]; +/** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[2]; +/** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[8]; +/** List of valid pin to peripheral connections for the sdhc_card_dat_7to4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[4]; +/** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[2]; +/** List of valid pin to peripheral connections for the sdhc_card_emmc_reset_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_emmc_reset_n[1]; +/** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[2]; +/** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[2]; +/** List of valid pin to peripheral connections for the sdhc_clk_card signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[2]; +/** List of valid pin to peripheral connections for the sdhc_io_volt_sel signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[2]; +/** List of valid pin to peripheral connections for the sdhc_led_ctrl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_led_ctrl[1]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; +/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; +/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; +/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[98]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[98]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_02_124_BGA_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_128_tqfp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_128_tqfp.h index d349f4561fc..aa69176af69 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_128_tqfp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_128_tqfp.h @@ -5,11 +5,11 @@ * PSoC6_02 device GPIO HAL header for 128-TQFP package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21305 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,135 +30,145 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_02_128_tqfp PSoC6_02 128-TQFP + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 128-TQFP package for the PSoC6_02 series. */ typedef enum { - NC = (int)0xFFFFFFFF, - - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), - P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), - P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), - P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), - - P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), - P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), - P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), - P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), - P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), - P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), - - P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), - P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), - P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), - P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), - P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), - P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), - P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), - P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), - - P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), - P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), - P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2), - P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3), - P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4), - P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5), - - P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0), - P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1), - P4_2 = CYHAL_GET_GPIO(CYHAL_PORT_4, 2), - P4_3 = CYHAL_GET_GPIO(CYHAL_PORT_4, 3), - - P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), - P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), - P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), - P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), - P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), - P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), - P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), - P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), - - P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), - P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), - - P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), - P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), - P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), - P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), - P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), - - P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), - P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), - P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), - P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), - P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), - P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), - P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), - P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), - - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), - P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), - P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), - P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), - P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), - - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), - P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), - P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), - P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), - P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), - P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), - - P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), - P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), - P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), - P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), - P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), - P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), - P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), - P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), - - P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), - P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), - P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), - P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), - P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), - P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), - P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), - P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), - - P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), - P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), - P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), - P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), - P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), - P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), - P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), - P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), - - USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), - USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), -} cyhal_gpio_t; + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin + + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 + P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 + P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 + P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 + + P1_0 = CYHAL_GET_GPIO(CYHAL_PORT_1, 0), //!< Port 1 Pin 0 + P1_1 = CYHAL_GET_GPIO(CYHAL_PORT_1, 1), //!< Port 1 Pin 1 + P1_2 = CYHAL_GET_GPIO(CYHAL_PORT_1, 2), //!< Port 1 Pin 2 + P1_3 = CYHAL_GET_GPIO(CYHAL_PORT_1, 3), //!< Port 1 Pin 3 + P1_4 = CYHAL_GET_GPIO(CYHAL_PORT_1, 4), //!< Port 1 Pin 4 + P1_5 = CYHAL_GET_GPIO(CYHAL_PORT_1, 5), //!< Port 1 Pin 5 + + P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 + P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 + P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 + P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 + P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4 + P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5 + P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), //!< Port 2 Pin 6 + P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), //!< Port 2 Pin 7 + + P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 + P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1 + P3_2 = CYHAL_GET_GPIO(CYHAL_PORT_3, 2), //!< Port 3 Pin 2 + P3_3 = CYHAL_GET_GPIO(CYHAL_PORT_3, 3), //!< Port 3 Pin 3 + P3_4 = CYHAL_GET_GPIO(CYHAL_PORT_3, 4), //!< Port 3 Pin 4 + P3_5 = CYHAL_GET_GPIO(CYHAL_PORT_3, 5), //!< Port 3 Pin 5 + + P4_0 = CYHAL_GET_GPIO(CYHAL_PORT_4, 0), //!< Port 4 Pin 0 + P4_1 = CYHAL_GET_GPIO(CYHAL_PORT_4, 1), //!< Port 4 Pin 1 + P4_2 = CYHAL_GET_GPIO(CYHAL_PORT_4, 2), //!< Port 4 Pin 2 + P4_3 = CYHAL_GET_GPIO(CYHAL_PORT_4, 3), //!< Port 4 Pin 3 + + P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 + P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 + P5_2 = CYHAL_GET_GPIO(CYHAL_PORT_5, 2), //!< Port 5 Pin 2 + P5_3 = CYHAL_GET_GPIO(CYHAL_PORT_5, 3), //!< Port 5 Pin 3 + P5_4 = CYHAL_GET_GPIO(CYHAL_PORT_5, 4), //!< Port 5 Pin 4 + P5_5 = CYHAL_GET_GPIO(CYHAL_PORT_5, 5), //!< Port 5 Pin 5 + P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 + P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7 + + P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 + P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 + + P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 + P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 + P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 + P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6 + P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 + + P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 + P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 + P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 + P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 + P8_4 = CYHAL_GET_GPIO(CYHAL_PORT_8, 4), //!< Port 8 Pin 4 + P8_5 = CYHAL_GET_GPIO(CYHAL_PORT_8, 5), //!< Port 8 Pin 5 + P8_6 = CYHAL_GET_GPIO(CYHAL_PORT_8, 6), //!< Port 8 Pin 6 + P8_7 = CYHAL_GET_GPIO(CYHAL_PORT_8, 7), //!< Port 8 Pin 7 + + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 + P9_4 = CYHAL_GET_GPIO(CYHAL_PORT_9, 4), //!< Port 9 Pin 4 + P9_5 = CYHAL_GET_GPIO(CYHAL_PORT_9, 5), //!< Port 9 Pin 5 + P9_6 = CYHAL_GET_GPIO(CYHAL_PORT_9, 6), //!< Port 9 Pin 6 + P9_7 = CYHAL_GET_GPIO(CYHAL_PORT_9, 7), //!< Port 9 Pin 7 + + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 + P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 + P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 + P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 + P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 + P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7 + + P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 + P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 + P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 + P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 + P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 + P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 + P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 + P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 + + P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 + P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 + P12_2 = CYHAL_GET_GPIO(CYHAL_PORT_12, 2), //!< Port 12 Pin 2 + P12_3 = CYHAL_GET_GPIO(CYHAL_PORT_12, 3), //!< Port 12 Pin 3 + P12_4 = CYHAL_GET_GPIO(CYHAL_PORT_12, 4), //!< Port 12 Pin 4 + P12_5 = CYHAL_GET_GPIO(CYHAL_PORT_12, 5), //!< Port 12 Pin 5 + P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 + P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 + + P13_0 = CYHAL_GET_GPIO(CYHAL_PORT_13, 0), //!< Port 13 Pin 0 + P13_1 = CYHAL_GET_GPIO(CYHAL_PORT_13, 1), //!< Port 13 Pin 1 + P13_2 = CYHAL_GET_GPIO(CYHAL_PORT_13, 2), //!< Port 13 Pin 2 + P13_3 = CYHAL_GET_GPIO(CYHAL_PORT_13, 3), //!< Port 13 Pin 3 + P13_4 = CYHAL_GET_GPIO(CYHAL_PORT_13, 4), //!< Port 13 Pin 4 + P13_5 = CYHAL_GET_GPIO(CYHAL_PORT_13, 5), //!< Port 13 Pin 5 + P13_6 = CYHAL_GET_GPIO(CYHAL_PORT_13, 6), //!< Port 13 Pin 6 + P13_7 = CYHAL_GET_GPIO(CYHAL_PORT_13, 7), //!< Port 13 Pin 7 + + USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 + USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 +} cyhal_gpio_psoc6_02_128_tqfp_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_02_128_tqfp_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -170,74 +180,139 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ +/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[4]; +/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[2]; +/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[2]; +/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[4]; +/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[4]; +/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[4]; +/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[4]; +/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[4]; +/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[4]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[21]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[21]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[17]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[17]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[17]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[17]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[13]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[13]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[10]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[17]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[17]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[17]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[17]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[13]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[13]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[10]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[19]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[19]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[19]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[19]; +/** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[2]; +/** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[8]; +/** List of valid pin to peripheral connections for the sdhc_card_dat_7to4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[4]; +/** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[2]; +/** List of valid pin to peripheral connections for the sdhc_card_emmc_reset_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_emmc_reset_n[1]; +/** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[2]; +/** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[2]; +/** List of valid pin to peripheral connections for the sdhc_clk_card signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[2]; +/** List of valid pin to peripheral connections for the sdhc_io_volt_sel signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[2]; +/** List of valid pin to peripheral connections for the sdhc_led_ctrl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_led_ctrl[1]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; +/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; +/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; +/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[100]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[100]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_02_128_TQFP_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_68_qfn.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_68_qfn.h index 03a39420971..e357bd6001c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_68_qfn.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_02_68_qfn.h @@ -5,11 +5,11 @@ * PSoC6_02 device GPIO HAL header for 68-QFN package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21305 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,83 +30,93 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_02_68_qfn PSoC6_02 68-QFN + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 68-QFN package for the PSoC6_02 series. */ typedef enum { - NC = (int)0xFFFFFFFF, - - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), - P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), - P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), - P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), - - P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), - P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), - P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), - P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), - P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), - P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), - P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), - P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), - - P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), - P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), - - P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), - P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), - P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), - P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), - - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), - - P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), - P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), - - P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), - P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), - - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), - - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), - P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), - P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), - P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), - - P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), - P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), - P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), - P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), - P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), - P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), - P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), - P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), - - P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), - P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), - - USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), - USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), -} cyhal_gpio_t; + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin + + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 + P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 + P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 + P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 + + P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 + P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 + P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 + P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 + P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4 + P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5 + P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), //!< Port 2 Pin 6 + P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), //!< Port 2 Pin 7 + + P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 + P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1 + + P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 + P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 + P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 + P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7 + + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 + + P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 + P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 + + P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 + P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 + + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 + + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 + P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 + P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 + P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 + + P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 + P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 + P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 + P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 + P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 + P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 + P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 + P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 + + P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 + P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 + + USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 + USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 +} cyhal_gpio_psoc6_02_68_qfn_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_02_68_qfn_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -118,74 +128,139 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ +/** List of valid pin to peripheral connections for the audioss_clk_i2s_if signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_clk_i2s_if[3]; +/** List of valid pin to peripheral connections for the audioss_pdm_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_clk[1]; +/** List of valid pin to peripheral connections for the audioss_pdm_data signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_pdm_data[1]; +/** List of valid pin to peripheral connections for the audioss_rx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sck[1]; +/** List of valid pin to peripheral connections for the audioss_rx_sdi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_sdi[2]; +/** List of valid pin to peripheral connections for the audioss_rx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_rx_ws[1]; +/** List of valid pin to peripheral connections for the audioss_tx_sck signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sck[3]; +/** List of valid pin to peripheral connections for the audioss_tx_sdo signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_sdo[2]; +/** List of valid pin to peripheral connections for the audioss_tx_ws signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_audioss_tx_ws[2]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[6]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[12]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[12]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[10]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[11]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[11]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[10]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[5]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[4]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[5]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[10]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[11]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[11]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[10]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[5]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[4]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[5]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[10]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[10]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[11]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[11]; +/** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[1]; +/** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[4]; +/** List of valid pin to peripheral connections for the sdhc_card_dat_7to4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_7to4[1]; +/** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[1]; +/** List of valid pin to peripheral connections for the sdhc_card_emmc_reset_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_emmc_reset_n[1]; +/** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[2]; +/** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[1]; +/** List of valid pin to peripheral connections for the sdhc_clk_card signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[1]; +/** List of valid pin to peripheral connections for the sdhc_io_volt_sel signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[2]; +/** List of valid pin to peripheral connections for the sdhc_led_ctrl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_led_ctrl[1]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_data4 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data4[1]; +/** List of valid pin to peripheral connections for the smif_spi_data5 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data5[1]; +/** List of valid pin to peripheral connections for the smif_spi_data6 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data6[1]; +/** List of valid pin to peripheral connections for the smif_spi_data7 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data7[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the smif_spi_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select3[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[50]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[52]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_02_68_QFN_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_100_tqfp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_100_tqfp.h index 3f22c20b989..1b7beec9136 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_100_tqfp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_100_tqfp.h @@ -5,11 +5,11 @@ * PSoC6_03 device GPIO HAL header for 100-TQFP package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21421 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,94 +30,104 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_03_100_tqfp PSoC6_03 100-TQFP + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 100-TQFP package for the PSoC6_03 series. */ typedef enum { - NC = (int)0xFFFFFFFF, - - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), - P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), - P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), - P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), - - P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), - P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), - P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), - P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), - P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), - P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), - P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), - P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), - - P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), - P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), - - P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), - P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), - P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), - P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), - - P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), - P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), - - P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), - P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), - P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), - P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), - P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), - - P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), - P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), - P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), - P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), - - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), - - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), - P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), - P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), - P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), - P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), - P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), - - P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), - P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), - P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), - P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), - P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), - P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), - P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), - P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), - - P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), - P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), - P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), - P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), - - USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), - USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), -} cyhal_gpio_t; + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin + + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 + P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 + P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 + P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 + + P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 + P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 + P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 + P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 + P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4 + P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5 + P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), //!< Port 2 Pin 6 + P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), //!< Port 2 Pin 7 + + P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 + P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1 + + P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 + P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 + P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 + P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7 + + P6_0 = CYHAL_GET_GPIO(CYHAL_PORT_6, 0), //!< Port 6 Pin 0 + P6_1 = CYHAL_GET_GPIO(CYHAL_PORT_6, 1), //!< Port 6 Pin 1 + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 + + P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 + P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 + P7_5 = CYHAL_GET_GPIO(CYHAL_PORT_7, 5), //!< Port 7 Pin 5 + P7_6 = CYHAL_GET_GPIO(CYHAL_PORT_7, 6), //!< Port 7 Pin 6 + P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 + + P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 + P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 + P8_2 = CYHAL_GET_GPIO(CYHAL_PORT_8, 2), //!< Port 8 Pin 2 + P8_3 = CYHAL_GET_GPIO(CYHAL_PORT_8, 3), //!< Port 8 Pin 3 + + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 + + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 + P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 + P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 + P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 + P10_6 = CYHAL_GET_GPIO(CYHAL_PORT_10, 6), //!< Port 10 Pin 6 + P10_7 = CYHAL_GET_GPIO(CYHAL_PORT_10, 7), //!< Port 10 Pin 7 + + P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 + P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 + P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 + P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 + P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 + P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 + P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 + P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 + + P12_0 = CYHAL_GET_GPIO(CYHAL_PORT_12, 0), //!< Port 12 Pin 0 + P12_1 = CYHAL_GET_GPIO(CYHAL_PORT_12, 1), //!< Port 12 Pin 1 + P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 + P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 + + USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 + USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 +} cyhal_gpio_psoc6_03_100_tqfp_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_03_100_tqfp_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -129,59 +139,109 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ -extern const cyhal_resource_pin_mapping_t cyhal_pin_map_can_ttcan_rx[1]; -extern const cyhal_resource_pin_mapping_t cyhal_pin_map_can_ttcan_tx[1]; +/** List of valid pin to peripheral connections for the canfd_ttcan_rx signal. */ +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[1]; +/** List of valid pin to peripheral connections for the canfd_ttcan_tx signal. */ +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[8]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[12]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[12]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[9]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[11]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[11]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[9]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[5]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[5]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[4]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[9]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[11]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[11]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[9]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[5]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[5]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[4]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[8]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[8]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[10]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[10]; +/** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[1]; +/** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[4]; +/** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[1]; +/** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[1]; +/** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[1]; +/** List of valid pin to peripheral connections for the sdhc_clk_card signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[1]; +/** List of valid pin to peripheral connections for the sdhc_io_volt_sel signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[1]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[64]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[64]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_03_100_TQFP_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_49_wlcsp.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_49_wlcsp.h index 91aa011c1c6..ff9574eea0c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_49_wlcsp.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_49_wlcsp.h @@ -5,11 +5,11 @@ * PSoC6_03 device GPIO HAL header for 49-WLCSP package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21421 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,61 +30,71 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_03_49_wlcsp PSoC6_03 49-WLCSP + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 50-WLCSP package for the PSoC6_03 series. */ typedef enum { - NC = (int)0xFFFFFFFF, - - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - - P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), - P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), - P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), - P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), - P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), - P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), - - P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), - P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), - - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), - - P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), - P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), - - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), - - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), - P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), - P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), - P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), - - P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), - P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), - P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), - P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), - P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), - P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), -} cyhal_gpio_t; + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin + + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + + P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 + P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 + P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 + P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 + P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4 + P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5 + + P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 + P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 + + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 + + P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 + P7_4 = CYHAL_GET_GPIO(CYHAL_PORT_7, 4), //!< Port 7 Pin 4 + + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 + + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 + P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 + P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 + P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 + + P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 + P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 + P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 + P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 + P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 + P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 +} cyhal_gpio_psoc6_03_49_wlcsp_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_03_49_wlcsp_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -96,59 +106,109 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ -extern const cyhal_resource_pin_mapping_t cyhal_pin_map_can_ttcan_rx[1]; -extern const cyhal_resource_pin_mapping_t cyhal_pin_map_can_ttcan_tx[1]; +/** List of valid pin to peripheral connections for the canfd_ttcan_rx signal. */ +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[1]; +/** List of valid pin to peripheral connections for the canfd_ttcan_tx signal. */ +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[6]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[6]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[6]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[7]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[6]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[6]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[7]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[5]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[4]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[1]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[7]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[6]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[6]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[7]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[5]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[4]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[1]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[6]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[6]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[5]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[5]; +/** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[1]; +/** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[4]; +/** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[1]; +/** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[1]; +/** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[1]; +/** List of valid pin to peripheral connections for the sdhc_clk_card signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[1]; +/** List of valid pin to peripheral connections for the sdhc_io_volt_sel signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[1]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[38]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[36]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_03_49_WLCSP_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_68_qfn.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_68_qfn.h index 685c10717d1..ee64b6d1f08 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_68_qfn.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/pin_packages/cyhal_psoc6_03_68_qfn.h @@ -5,11 +5,11 @@ * PSoC6_03 device GPIO HAL header for 68-QFN package * * \note -* Generator version: 1.4.7153.30079 +* Generator version: 1.5.7254.21421 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,83 +30,93 @@ #include "cyhal_hw_resources.h" +/** + * \addtogroup group_hal_psoc6_pin_package_psoc6_03_68_qfn PSoC6_03 68-QFN + * \ingroup group_hal_psoc6_pin_package + * \{ + */ + #if defined(__cplusplus) extern "C" { #endif /* __cplusplus */ +/** Gets a pin definition from the provided port and pin numbers */ #define CYHAL_GET_GPIO(port, pin) (((port) << 16) + (pin)) -/* Pin names */ +/** Definitions for all of the pins that are bonded out on in the 68-QFN package for the PSoC6_03 series. */ typedef enum { - NC = (int)0xFFFFFFFF, - - P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), - P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), - P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), - P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), - P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), - P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), - - P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), - P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), - P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), - P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), - P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), - P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), - P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), - P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), - - P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), - P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), - - P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), - P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), - P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), - P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), - - P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), - P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), - P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), - P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), - P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), - P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), - - P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), - P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), - P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), - P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), - P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), - - P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), - P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), - - P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), - P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), - P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), - P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), - - P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), - P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), - P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), - P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), - P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), - P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), - - P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), - P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), - P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), - P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), - P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), - P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), - P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), - P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), - - P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), - P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), - - USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), - USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), -} cyhal_gpio_t; + NC = (int)0xFFFFFFFF, //!< No Connect/Invalid Pin + + P0_0 = CYHAL_GET_GPIO(CYHAL_PORT_0, 0), //!< Port 0 Pin 0 + P0_1 = CYHAL_GET_GPIO(CYHAL_PORT_0, 1), //!< Port 0 Pin 1 + P0_2 = CYHAL_GET_GPIO(CYHAL_PORT_0, 2), //!< Port 0 Pin 2 + P0_3 = CYHAL_GET_GPIO(CYHAL_PORT_0, 3), //!< Port 0 Pin 3 + P0_4 = CYHAL_GET_GPIO(CYHAL_PORT_0, 4), //!< Port 0 Pin 4 + P0_5 = CYHAL_GET_GPIO(CYHAL_PORT_0, 5), //!< Port 0 Pin 5 + + P2_0 = CYHAL_GET_GPIO(CYHAL_PORT_2, 0), //!< Port 2 Pin 0 + P2_1 = CYHAL_GET_GPIO(CYHAL_PORT_2, 1), //!< Port 2 Pin 1 + P2_2 = CYHAL_GET_GPIO(CYHAL_PORT_2, 2), //!< Port 2 Pin 2 + P2_3 = CYHAL_GET_GPIO(CYHAL_PORT_2, 3), //!< Port 2 Pin 3 + P2_4 = CYHAL_GET_GPIO(CYHAL_PORT_2, 4), //!< Port 2 Pin 4 + P2_5 = CYHAL_GET_GPIO(CYHAL_PORT_2, 5), //!< Port 2 Pin 5 + P2_6 = CYHAL_GET_GPIO(CYHAL_PORT_2, 6), //!< Port 2 Pin 6 + P2_7 = CYHAL_GET_GPIO(CYHAL_PORT_2, 7), //!< Port 2 Pin 7 + + P3_0 = CYHAL_GET_GPIO(CYHAL_PORT_3, 0), //!< Port 3 Pin 0 + P3_1 = CYHAL_GET_GPIO(CYHAL_PORT_3, 1), //!< Port 3 Pin 1 + + P5_0 = CYHAL_GET_GPIO(CYHAL_PORT_5, 0), //!< Port 5 Pin 0 + P5_1 = CYHAL_GET_GPIO(CYHAL_PORT_5, 1), //!< Port 5 Pin 1 + P5_6 = CYHAL_GET_GPIO(CYHAL_PORT_5, 6), //!< Port 5 Pin 6 + P5_7 = CYHAL_GET_GPIO(CYHAL_PORT_5, 7), //!< Port 5 Pin 7 + + P6_2 = CYHAL_GET_GPIO(CYHAL_PORT_6, 2), //!< Port 6 Pin 2 + P6_3 = CYHAL_GET_GPIO(CYHAL_PORT_6, 3), //!< Port 6 Pin 3 + P6_4 = CYHAL_GET_GPIO(CYHAL_PORT_6, 4), //!< Port 6 Pin 4 + P6_5 = CYHAL_GET_GPIO(CYHAL_PORT_6, 5), //!< Port 6 Pin 5 + P6_6 = CYHAL_GET_GPIO(CYHAL_PORT_6, 6), //!< Port 6 Pin 6 + P6_7 = CYHAL_GET_GPIO(CYHAL_PORT_6, 7), //!< Port 6 Pin 7 + + P7_0 = CYHAL_GET_GPIO(CYHAL_PORT_7, 0), //!< Port 7 Pin 0 + P7_1 = CYHAL_GET_GPIO(CYHAL_PORT_7, 1), //!< Port 7 Pin 1 + P7_2 = CYHAL_GET_GPIO(CYHAL_PORT_7, 2), //!< Port 7 Pin 2 + P7_3 = CYHAL_GET_GPIO(CYHAL_PORT_7, 3), //!< Port 7 Pin 3 + P7_7 = CYHAL_GET_GPIO(CYHAL_PORT_7, 7), //!< Port 7 Pin 7 + + P8_0 = CYHAL_GET_GPIO(CYHAL_PORT_8, 0), //!< Port 8 Pin 0 + P8_1 = CYHAL_GET_GPIO(CYHAL_PORT_8, 1), //!< Port 8 Pin 1 + + P9_0 = CYHAL_GET_GPIO(CYHAL_PORT_9, 0), //!< Port 9 Pin 0 + P9_1 = CYHAL_GET_GPIO(CYHAL_PORT_9, 1), //!< Port 9 Pin 1 + P9_2 = CYHAL_GET_GPIO(CYHAL_PORT_9, 2), //!< Port 9 Pin 2 + P9_3 = CYHAL_GET_GPIO(CYHAL_PORT_9, 3), //!< Port 9 Pin 3 + + P10_0 = CYHAL_GET_GPIO(CYHAL_PORT_10, 0), //!< Port 10 Pin 0 + P10_1 = CYHAL_GET_GPIO(CYHAL_PORT_10, 1), //!< Port 10 Pin 1 + P10_2 = CYHAL_GET_GPIO(CYHAL_PORT_10, 2), //!< Port 10 Pin 2 + P10_3 = CYHAL_GET_GPIO(CYHAL_PORT_10, 3), //!< Port 10 Pin 3 + P10_4 = CYHAL_GET_GPIO(CYHAL_PORT_10, 4), //!< Port 10 Pin 4 + P10_5 = CYHAL_GET_GPIO(CYHAL_PORT_10, 5), //!< Port 10 Pin 5 + + P11_0 = CYHAL_GET_GPIO(CYHAL_PORT_11, 0), //!< Port 11 Pin 0 + P11_1 = CYHAL_GET_GPIO(CYHAL_PORT_11, 1), //!< Port 11 Pin 1 + P11_2 = CYHAL_GET_GPIO(CYHAL_PORT_11, 2), //!< Port 11 Pin 2 + P11_3 = CYHAL_GET_GPIO(CYHAL_PORT_11, 3), //!< Port 11 Pin 3 + P11_4 = CYHAL_GET_GPIO(CYHAL_PORT_11, 4), //!< Port 11 Pin 4 + P11_5 = CYHAL_GET_GPIO(CYHAL_PORT_11, 5), //!< Port 11 Pin 5 + P11_6 = CYHAL_GET_GPIO(CYHAL_PORT_11, 6), //!< Port 11 Pin 6 + P11_7 = CYHAL_GET_GPIO(CYHAL_PORT_11, 7), //!< Port 11 Pin 7 + + P12_6 = CYHAL_GET_GPIO(CYHAL_PORT_12, 6), //!< Port 12 Pin 6 + P12_7 = CYHAL_GET_GPIO(CYHAL_PORT_12, 7), //!< Port 12 Pin 7 + + USBDP = CYHAL_GET_GPIO(CYHAL_PORT_14, 0), //!< Port 14 Pin 0 + USBDM = CYHAL_GET_GPIO(CYHAL_PORT_14, 1), //!< Port 14 Pin 1 +} cyhal_gpio_psoc6_03_68_qfn_t; + +/** Create generic name for the series/package specific type. */ +typedef cyhal_gpio_psoc6_03_68_qfn_t cyhal_gpio_t; /* Connection type definition */ /** Represents an association between a pin and a resource */ @@ -118,59 +128,109 @@ typedef struct } cyhal_resource_pin_mapping_t; /* Pin connections */ -extern const cyhal_resource_pin_mapping_t cyhal_pin_map_can_ttcan_rx[1]; -extern const cyhal_resource_pin_mapping_t cyhal_pin_map_can_ttcan_tx[1]; +/** List of valid pin to peripheral connections for the canfd_ttcan_rx signal. */ +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_rx[1]; +/** List of valid pin to peripheral connections for the canfd_ttcan_tx signal. */ +extern const cyhal_resource_pin_mapping_t cyhal_pin_map_canfd_ttcan_tx[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_dsi_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_dsi_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inn_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inn_comp1[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp0[1]; +/** List of valid pin to peripheral connections for the lpcomp_inp_comp1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_lpcomp_inp_comp1[1]; +/** List of valid pin to peripheral connections for the pass_sarmux_pads signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_pass_sarmux_pads[6]; +/** List of valid pin to peripheral connections for the scb_i2c_scl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_scl[10]; +/** List of valid pin to peripheral connections for the scb_i2c_sda signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_i2c_sda[10]; +/** List of valid pin to peripheral connections for the scb_spi_m_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_clk[8]; +/** List of valid pin to peripheral connections for the scb_spi_m_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_miso[10]; +/** List of valid pin to peripheral connections for the scb_spi_m_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_mosi[10]; +/** List of valid pin to peripheral connections for the scb_spi_m_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select0[8]; +/** List of valid pin to peripheral connections for the scb_spi_m_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select1[4]; +/** List of valid pin to peripheral connections for the scb_spi_m_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select2[4]; +/** List of valid pin to peripheral connections for the scb_spi_m_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_m_select3[2]; +/** List of valid pin to peripheral connections for the scb_spi_s_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_clk[8]; +/** List of valid pin to peripheral connections for the scb_spi_s_miso signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_miso[10]; +/** List of valid pin to peripheral connections for the scb_spi_s_mosi signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_mosi[10]; +/** List of valid pin to peripheral connections for the scb_spi_s_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select0[8]; +/** List of valid pin to peripheral connections for the scb_spi_s_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select1[4]; +/** List of valid pin to peripheral connections for the scb_spi_s_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select2[4]; +/** List of valid pin to peripheral connections for the scb_spi_s_select3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_spi_s_select3[2]; +/** List of valid pin to peripheral connections for the scb_uart_cts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_cts[7]; +/** List of valid pin to peripheral connections for the scb_uart_rts signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rts[7]; +/** List of valid pin to peripheral connections for the scb_uart_rx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_rx[9]; +/** List of valid pin to peripheral connections for the scb_uart_tx signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_scb_uart_tx[9]; +/** List of valid pin to peripheral connections for the sdhc_card_cmd signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_cmd[1]; +/** List of valid pin to peripheral connections for the sdhc_card_dat_3to0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_dat_3to0[4]; +/** List of valid pin to peripheral connections for the sdhc_card_detect_n signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_detect_n[1]; +/** List of valid pin to peripheral connections for the sdhc_card_if_pwr_en signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_if_pwr_en[1]; +/** List of valid pin to peripheral connections for the sdhc_card_mech_write_prot signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_card_mech_write_prot[1]; +/** List of valid pin to peripheral connections for the sdhc_clk_card signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_clk_card[1]; +/** List of valid pin to peripheral connections for the sdhc_io_volt_sel signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_sdhc_io_volt_sel[1]; +/** List of valid pin to peripheral connections for the smif_spi_clk signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_clk[1]; +/** List of valid pin to peripheral connections for the smif_spi_data0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data0[1]; +/** List of valid pin to peripheral connections for the smif_spi_data1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data1[1]; +/** List of valid pin to peripheral connections for the smif_spi_data2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data2[1]; +/** List of valid pin to peripheral connections for the smif_spi_data3 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_data3[1]; +/** List of valid pin to peripheral connections for the smif_spi_select0 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select0[1]; +/** List of valid pin to peripheral connections for the smif_spi_select1 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select1[1]; +/** List of valid pin to peripheral connections for the smif_spi_select2 signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_smif_spi_select2[1]; +/** List of valid pin to peripheral connections for the tcpwm_line signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line[52]; +/** List of valid pin to peripheral connections for the tcpwm_line_compl signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_tcpwm_line_compl[54]; +/** List of valid pin to peripheral connections for the usb_usb_dm_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dm_pad[1]; +/** List of valid pin to peripheral connections for the usb_usb_dp_pad signal. */ extern const cyhal_resource_pin_mapping_t cyhal_pin_map_usb_usb_dp_pad[1]; #if defined(__cplusplus) } #endif /* __cplusplus */ +/** \} group_hal_psoc6 */ + #endif /* _CYHAL_PSOC6_03_68_QFN_H_ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/triggers/cyhal_triggers_psoc6_01.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/triggers/cyhal_triggers_psoc6_01.h new file mode 100644 index 00000000000..17ae553ad1b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/triggers/cyhal_triggers_psoc6_01.h @@ -0,0 +1,547 @@ +/***************************************************************************//** +* \file cyhal_triggers_psoc6_01.h +* +* \brief +* PSoC6_01 family HAL triggers header +* +* \note +* Generator version: 1.5.7254.19579 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYHAL_TRIGGERS_PSOC6_01_H_ +#define _CYHAL_TRIGGERS_PSOC6_01_H_ + +/** + * \addtogroup group_hal_psoc6_triggers_psoc6_01 PSOC6_01 + * \ingroup group_hal_psoc6_triggers + * \{ + * Trigger connections for psoc6_01 + */ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** @brief Name of each output trigger. */ +typedef enum +{ + TRIGGER_CPUSS_CTI_TR_IN0 = 0, //!< CPUSS Cross-Triggering-Interface trigger multiplexer (CTI) - cpuss.cti_tr_in[0] + TRIGGER_CPUSS_CTI_TR_IN1 = 1, //!< CPUSS Cross-Triggering-Interface trigger multiplexer (CTI) - cpuss.cti_tr_in[1] + TRIGGER_CPUSS_DW0_TR_IN0 = 2, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[0] + TRIGGER_CPUSS_DW0_TR_IN1 = 3, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[1] + TRIGGER_CPUSS_DW0_TR_IN2 = 4, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[2] + TRIGGER_CPUSS_DW0_TR_IN3 = 5, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[3] + TRIGGER_CPUSS_DW0_TR_IN4 = 6, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[4] + TRIGGER_CPUSS_DW0_TR_IN5 = 7, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[5] + TRIGGER_CPUSS_DW0_TR_IN6 = 8, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[6] + TRIGGER_CPUSS_DW0_TR_IN7 = 9, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[7] + TRIGGER_CPUSS_DW0_TR_IN8 = 10, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[8] + TRIGGER_CPUSS_DW0_TR_IN9 = 11, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[9] + TRIGGER_CPUSS_DW0_TR_IN10 = 12, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[10] + TRIGGER_CPUSS_DW0_TR_IN11 = 13, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[11] + TRIGGER_CPUSS_DW0_TR_IN12 = 14, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[12] + TRIGGER_CPUSS_DW0_TR_IN13 = 15, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[13] + TRIGGER_CPUSS_DW0_TR_IN14 = 16, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[14] + TRIGGER_CPUSS_DW0_TR_IN15 = 17, //!< DW0 trigger multiplexer - cpuss.dw0_tr_in[15] + TRIGGER_CPUSS_DW1_TR_IN0 = 18, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[0] + TRIGGER_CPUSS_DW1_TR_IN1 = 19, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[1] + TRIGGER_CPUSS_DW1_TR_IN2 = 20, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[2] + TRIGGER_CPUSS_DW1_TR_IN3 = 21, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[3] + TRIGGER_CPUSS_DW1_TR_IN4 = 22, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[4] + TRIGGER_CPUSS_DW1_TR_IN5 = 23, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[5] + TRIGGER_CPUSS_DW1_TR_IN6 = 24, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[6] + TRIGGER_CPUSS_DW1_TR_IN7 = 25, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[7] + TRIGGER_CPUSS_DW1_TR_IN8 = 26, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[8] + TRIGGER_CPUSS_DW1_TR_IN9 = 27, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[9] + TRIGGER_CPUSS_DW1_TR_IN10 = 28, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[10] + TRIGGER_CPUSS_DW1_TR_IN11 = 29, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[11] + TRIGGER_CPUSS_DW1_TR_IN12 = 30, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[12] + TRIGGER_CPUSS_DW1_TR_IN13 = 31, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[13] + TRIGGER_CPUSS_DW1_TR_IN14 = 32, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[14] + TRIGGER_CPUSS_DW1_TR_IN15 = 33, //!< DW1 trigger multiplexer - cpuss.dw1_tr_in[15] + TRIGGER_PASS_TR_SAR_IN = 34, //!< PASS trigger multiplexer - pass.tr_sar_in + TRIGGER_PERI_TR_IO_OUTPUT0 = 35, //!< GPIO/HSIOM trigger multiplexer - peri.tr_io_output[0] + TRIGGER_PERI_TR_IO_OUTPUT1 = 36, //!< GPIO/HSIOM trigger multiplexer - peri.tr_io_output[1] + TRIGGER_PROFILE_TR_START = 37, //!< PROFILE trigger multiplexer - profile.tr_start + TRIGGER_PROFILE_TR_STOP = 38, //!< PROFILE trigger multiplexer - profile.tr_stop + TRIGGER_TCPWM0_TR_IN0 = 39, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[0] + TRIGGER_TCPWM0_TR_IN1 = 40, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[1] + TRIGGER_TCPWM0_TR_IN2 = 41, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[2] + TRIGGER_TCPWM0_TR_IN3 = 42, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[3] + TRIGGER_TCPWM0_TR_IN4 = 43, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[4] + TRIGGER_TCPWM0_TR_IN5 = 44, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[5] + TRIGGER_TCPWM0_TR_IN6 = 45, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[6] + TRIGGER_TCPWM0_TR_IN7 = 46, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[7] + TRIGGER_TCPWM0_TR_IN8 = 47, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[8] + TRIGGER_TCPWM0_TR_IN9 = 48, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[9] + TRIGGER_TCPWM0_TR_IN10 = 49, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[10] + TRIGGER_TCPWM0_TR_IN11 = 50, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[11] + TRIGGER_TCPWM0_TR_IN12 = 51, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[12] + TRIGGER_TCPWM0_TR_IN13 = 52, //!< TCPWM0 Trigger Multiplexer - tcpwm[0].tr_in[13] + TRIGGER_TCPWM1_TR_IN0 = 53, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[0] + TRIGGER_TCPWM1_TR_IN1 = 54, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[1] + TRIGGER_TCPWM1_TR_IN2 = 55, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[2] + TRIGGER_TCPWM1_TR_IN3 = 56, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[3] + TRIGGER_TCPWM1_TR_IN4 = 57, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[4] + TRIGGER_TCPWM1_TR_IN5 = 58, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[5] + TRIGGER_TCPWM1_TR_IN6 = 59, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[6] + TRIGGER_TCPWM1_TR_IN7 = 60, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[7] + TRIGGER_TCPWM1_TR_IN8 = 61, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[8] + TRIGGER_TCPWM1_TR_IN9 = 62, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[9] + TRIGGER_TCPWM1_TR_IN10 = 63, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[10] + TRIGGER_TCPWM1_TR_IN11 = 64, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[11] + TRIGGER_TCPWM1_TR_IN12 = 65, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[12] + TRIGGER_TCPWM1_TR_IN13 = 66, //!< TCPWM1 Trigger Multiplexer - tcpwm[1].tr_in[13] + TRIGGER_TR_GROUP0_INPUT1 = 67, //!< Datawire output trigger reduction mux - tr_group[0].input[1] + TRIGGER_TR_GROUP0_INPUT2 = 68, //!< Datawire output trigger reduction mux - tr_group[0].input[2] + TRIGGER_TR_GROUP0_INPUT3 = 69, //!< Datawire output trigger reduction mux - tr_group[0].input[3] + TRIGGER_TR_GROUP0_INPUT4 = 70, //!< Datawire output trigger reduction mux - tr_group[0].input[4] + TRIGGER_TR_GROUP0_INPUT5 = 71, //!< Datawire output trigger reduction mux - tr_group[0].input[5] + TRIGGER_TR_GROUP0_INPUT6 = 72, //!< Datawire output trigger reduction mux - tr_group[0].input[6] + TRIGGER_TR_GROUP0_INPUT7 = 73, //!< Datawire output trigger reduction mux - tr_group[0].input[7] + TRIGGER_TR_GROUP0_INPUT8 = 74, //!< Datawire output trigger reduction mux - tr_group[0].input[8] + TRIGGER_TR_GROUP0_INPUT9 = 75, //!< TCPWM trigger output reduction mux - tr_group[0].input[9] + TRIGGER_TR_GROUP0_INPUT10 = 76, //!< TCPWM trigger output reduction mux - tr_group[0].input[10] + TRIGGER_TR_GROUP0_INPUT11 = 77, //!< TCPWM trigger output reduction mux - tr_group[0].input[11] + TRIGGER_TR_GROUP0_INPUT12 = 78, //!< TCPWM trigger output reduction mux - tr_group[0].input[12] + TRIGGER_TR_GROUP0_INPUT13 = 79, //!< TCPWM trigger output reduction mux - tr_group[0].input[13] + TRIGGER_TR_GROUP0_INPUT14 = 80, //!< TCPWM trigger output reduction mux - tr_group[0].input[14] + TRIGGER_TR_GROUP0_INPUT15 = 81, //!< TCPWM trigger output reduction mux - tr_group[0].input[15] + TRIGGER_TR_GROUP0_INPUT16 = 82, //!< TCPWM trigger output reduction mux - tr_group[0].input[16] + TRIGGER_TR_GROUP0_INPUT17 = 83, //!< TCPWM trigger output reduction mux - tr_group[0].input[17] + TRIGGER_TR_GROUP0_INPUT18 = 84, //!< TCPWM trigger output reduction mux - tr_group[0].input[18] + TRIGGER_TR_GROUP0_INPUT19 = 85, //!< TCPWM trigger output reduction mux - tr_group[0].input[19] + TRIGGER_TR_GROUP0_INPUT20 = 86, //!< TCPWM trigger output reduction mux - tr_group[0].input[20] + TRIGGER_TR_GROUP0_INPUT21 = 87, //!< TCPWM trigger output reduction mux - tr_group[0].input[21] + TRIGGER_TR_GROUP0_INPUT22 = 88, //!< TCPWM trigger output reduction mux - tr_group[0].input[22] + TRIGGER_TR_GROUP0_INPUT23 = 89, //!< TCPWM trigger output reduction mux - tr_group[0].input[23] + TRIGGER_TR_GROUP0_INPUT24 = 90, //!< TCPWM trigger output reduction mux - tr_group[0].input[24] + TRIGGER_TR_GROUP0_INPUT25 = 91, //!< HSIOM Pin input reduction mux - tr_group[0].input[25] + TRIGGER_TR_GROUP0_INPUT26 = 92, //!< HSIOM Pin input reduction mux - tr_group[0].input[26] + TRIGGER_TR_GROUP0_INPUT27 = 93, //!< DMA request reduction mux - tr_group[0].input[27] + TRIGGER_TR_GROUP0_INPUT28 = 94, //!< DMA request reduction mux - tr_group[0].input[28] + TRIGGER_TR_GROUP0_INPUT29 = 95, //!< DMA request reduction mux - tr_group[0].input[29] + TRIGGER_TR_GROUP0_INPUT30 = 96, //!< DMA request reduction mux - tr_group[0].input[30] + TRIGGER_TR_GROUP0_INPUT31 = 97, //!< DMA request reduction mux - tr_group[0].input[31] + TRIGGER_TR_GROUP0_INPUT32 = 98, //!< DMA request reduction mux - tr_group[0].input[32] + TRIGGER_TR_GROUP0_INPUT33 = 99, //!< DMA request reduction mux - tr_group[0].input[33] + TRIGGER_TR_GROUP0_INPUT34 = 100, //!< DMA request reduction mux - tr_group[0].input[34] + TRIGGER_TR_GROUP0_INPUT35 = 101, //!< DMA request reduction mux - tr_group[0].input[35] + TRIGGER_TR_GROUP0_INPUT36 = 102, //!< DMA request reduction mux - tr_group[0].input[36] + TRIGGER_TR_GROUP0_INPUT37 = 103, //!< DMA request reduction mux - tr_group[0].input[37] + TRIGGER_TR_GROUP0_INPUT38 = 104, //!< DMA request reduction mux - tr_group[0].input[38] + TRIGGER_TR_GROUP0_INPUT39 = 105, //!< DMA request reduction mux - tr_group[0].input[39] + TRIGGER_TR_GROUP0_INPUT40 = 106, //!< DMA request reduction mux - tr_group[0].input[40] + TRIGGER_TR_GROUP0_INPUT41 = 107, //!< DMA request reduction mux - tr_group[0].input[41] + TRIGGER_TR_GROUP0_INPUT42 = 108, //!< DMA request reduction mux - tr_group[0].input[42] + TRIGGER_TR_GROUP0_INPUT43 = 109, //!< Trigger input reduction mux - tr_group[0].input[43] + TRIGGER_TR_GROUP0_INPUT44 = 110, //!< Trigger input reduction mux - tr_group[0].input[44] + TRIGGER_TR_GROUP0_INPUT45 = 111, //!< Trigger input reduction mux - tr_group[0].input[45] + TRIGGER_TR_GROUP0_INPUT46 = 112, //!< Trigger input reduction mux - tr_group[0].input[46] + TRIGGER_TR_GROUP0_INPUT47 = 113, //!< Trigger input reduction mux - tr_group[0].input[47] + TRIGGER_TR_GROUP0_INPUT48 = 114, //!< Trigger input reduction mux - tr_group[0].input[48] + TRIGGER_TR_GROUP0_INPUT49 = 115, //!< Trigger input reduction mux - tr_group[0].input[49] + TRIGGER_TR_GROUP0_INPUT50 = 116, //!< Trigger input reduction mux - tr_group[0].input[50] + TRIGGER_TR_GROUP1_INPUT1 = 117, //!< Datawire output trigger reduction mux - tr_group[1].input[1] + TRIGGER_TR_GROUP1_INPUT2 = 118, //!< Datawire output trigger reduction mux - tr_group[1].input[2] + TRIGGER_TR_GROUP1_INPUT3 = 119, //!< Datawire output trigger reduction mux - tr_group[1].input[3] + TRIGGER_TR_GROUP1_INPUT4 = 120, //!< Datawire output trigger reduction mux - tr_group[1].input[4] + TRIGGER_TR_GROUP1_INPUT5 = 121, //!< Datawire output trigger reduction mux - tr_group[1].input[5] + TRIGGER_TR_GROUP1_INPUT6 = 122, //!< Datawire output trigger reduction mux - tr_group[1].input[6] + TRIGGER_TR_GROUP1_INPUT7 = 123, //!< Datawire output trigger reduction mux - tr_group[1].input[7] + TRIGGER_TR_GROUP1_INPUT8 = 124, //!< Datawire output trigger reduction mux - tr_group[1].input[8] + TRIGGER_TR_GROUP1_INPUT9 = 125, //!< TCPWM trigger output reduction mux - tr_group[1].input[9] + TRIGGER_TR_GROUP1_INPUT10 = 126, //!< TCPWM trigger output reduction mux - tr_group[1].input[10] + TRIGGER_TR_GROUP1_INPUT11 = 127, //!< TCPWM trigger output reduction mux - tr_group[1].input[11] + TRIGGER_TR_GROUP1_INPUT12 = 128, //!< TCPWM trigger output reduction mux - tr_group[1].input[12] + TRIGGER_TR_GROUP1_INPUT13 = 129, //!< TCPWM trigger output reduction mux - tr_group[1].input[13] + TRIGGER_TR_GROUP1_INPUT14 = 130, //!< TCPWM trigger output reduction mux - tr_group[1].input[14] + TRIGGER_TR_GROUP1_INPUT15 = 131, //!< TCPWM trigger output reduction mux - tr_group[1].input[15] + TRIGGER_TR_GROUP1_INPUT16 = 132, //!< TCPWM trigger output reduction mux - tr_group[1].input[16] + TRIGGER_TR_GROUP1_INPUT17 = 133, //!< TCPWM trigger output reduction mux - tr_group[1].input[17] + TRIGGER_TR_GROUP1_INPUT18 = 134, //!< TCPWM trigger output reduction mux - tr_group[1].input[18] + TRIGGER_TR_GROUP1_INPUT19 = 135, //!< TCPWM trigger output reduction mux - tr_group[1].input[19] + TRIGGER_TR_GROUP1_INPUT20 = 136, //!< TCPWM trigger output reduction mux - tr_group[1].input[20] + TRIGGER_TR_GROUP1_INPUT21 = 137, //!< TCPWM trigger output reduction mux - tr_group[1].input[21] + TRIGGER_TR_GROUP1_INPUT22 = 138, //!< TCPWM trigger output reduction mux - tr_group[1].input[22] + TRIGGER_TR_GROUP1_INPUT23 = 139, //!< TCPWM trigger output reduction mux - tr_group[1].input[23] + TRIGGER_TR_GROUP1_INPUT24 = 140, //!< TCPWM trigger output reduction mux - tr_group[1].input[24] + TRIGGER_TR_GROUP1_INPUT25 = 141, //!< HSIOM Pin input reduction mux - tr_group[1].input[25] + TRIGGER_TR_GROUP1_INPUT26 = 142, //!< HSIOM Pin input reduction mux - tr_group[1].input[26] + TRIGGER_TR_GROUP1_INPUT27 = 143, //!< DMA request reduction mux - tr_group[1].input[27] + TRIGGER_TR_GROUP1_INPUT28 = 144, //!< DMA request reduction mux - tr_group[1].input[28] + TRIGGER_TR_GROUP1_INPUT29 = 145, //!< DMA request reduction mux - tr_group[1].input[29] + TRIGGER_TR_GROUP1_INPUT30 = 146, //!< DMA request reduction mux - tr_group[1].input[30] + TRIGGER_TR_GROUP1_INPUT31 = 147, //!< DMA request reduction mux - tr_group[1].input[31] + TRIGGER_TR_GROUP1_INPUT32 = 148, //!< DMA request reduction mux - tr_group[1].input[32] + TRIGGER_TR_GROUP1_INPUT33 = 149, //!< DMA request reduction mux - tr_group[1].input[33] + TRIGGER_TR_GROUP1_INPUT34 = 150, //!< DMA request reduction mux - tr_group[1].input[34] + TRIGGER_TR_GROUP1_INPUT35 = 151, //!< DMA request reduction mux - tr_group[1].input[35] + TRIGGER_TR_GROUP1_INPUT36 = 152, //!< DMA request reduction mux - tr_group[1].input[36] + TRIGGER_TR_GROUP1_INPUT37 = 153, //!< DMA request reduction mux - tr_group[1].input[37] + TRIGGER_TR_GROUP1_INPUT38 = 154, //!< DMA request reduction mux - tr_group[1].input[38] + TRIGGER_TR_GROUP1_INPUT39 = 155, //!< DMA request reduction mux - tr_group[1].input[39] + TRIGGER_TR_GROUP1_INPUT40 = 156, //!< DMA request reduction mux - tr_group[1].input[40] + TRIGGER_TR_GROUP1_INPUT41 = 157, //!< DMA request reduction mux - tr_group[1].input[41] + TRIGGER_TR_GROUP1_INPUT42 = 158, //!< DMA request reduction mux - tr_group[1].input[42] + TRIGGER_TR_GROUP1_INPUT43 = 159, //!< Trigger input reduction mux - tr_group[1].input[43] + TRIGGER_TR_GROUP1_INPUT44 = 160, //!< Trigger input reduction mux - tr_group[1].input[44] + TRIGGER_TR_GROUP1_INPUT45 = 161, //!< Trigger input reduction mux - tr_group[1].input[45] + TRIGGER_TR_GROUP1_INPUT46 = 162, //!< Trigger input reduction mux - tr_group[1].input[46] + TRIGGER_TR_GROUP1_INPUT47 = 163, //!< Trigger input reduction mux - tr_group[1].input[47] + TRIGGER_TR_GROUP1_INPUT48 = 164, //!< Trigger input reduction mux - tr_group[1].input[48] + TRIGGER_TR_GROUP1_INPUT49 = 165, //!< Trigger input reduction mux - tr_group[1].input[49] + TRIGGER_TR_GROUP1_INPUT50 = 166, //!< Trigger input reduction mux - tr_group[1].input[50] + TRIGGER_TR_GROUP2_INPUT1 = 167, //!< Datawire output trigger reduction mux - tr_group[2].input[1] + TRIGGER_TR_GROUP2_INPUT2 = 168, //!< Datawire output trigger reduction mux - tr_group[2].input[2] + TRIGGER_TR_GROUP2_INPUT3 = 169, //!< Datawire output trigger reduction mux - tr_group[2].input[3] + TRIGGER_TR_GROUP2_INPUT4 = 170, //!< Datawire output trigger reduction mux - tr_group[2].input[4] + TRIGGER_TR_GROUP2_INPUT5 = 171, //!< Datawire output trigger reduction mux - tr_group[2].input[5] + TRIGGER_TR_GROUP2_INPUT6 = 172, //!< Datawire output trigger reduction mux - tr_group[2].input[6] + TRIGGER_TR_GROUP2_INPUT7 = 173, //!< Datawire output trigger reduction mux - tr_group[2].input[7] + TRIGGER_TR_GROUP2_INPUT8 = 174, //!< Datawire output trigger reduction mux - tr_group[2].input[8] + TRIGGER_TR_GROUP2_INPUT9 = 175, //!< TCPWM trigger output reduction mux - tr_group[2].input[9] + TRIGGER_TR_GROUP2_INPUT10 = 176, //!< TCPWM trigger output reduction mux - tr_group[2].input[10] + TRIGGER_TR_GROUP2_INPUT11 = 177, //!< TCPWM trigger output reduction mux - tr_group[2].input[11] + TRIGGER_TR_GROUP2_INPUT12 = 178, //!< TCPWM trigger output reduction mux - tr_group[2].input[12] + TRIGGER_TR_GROUP2_INPUT13 = 179, //!< TCPWM trigger output reduction mux - tr_group[2].input[13] + TRIGGER_TR_GROUP2_INPUT14 = 180, //!< TCPWM trigger output reduction mux - tr_group[2].input[14] + TRIGGER_TR_GROUP2_INPUT15 = 181, //!< TCPWM trigger output reduction mux - tr_group[2].input[15] + TRIGGER_TR_GROUP2_INPUT16 = 182, //!< TCPWM trigger output reduction mux - tr_group[2].input[16] + TRIGGER_TR_GROUP2_INPUT17 = 183, //!< TCPWM trigger output reduction mux - tr_group[2].input[17] + TRIGGER_TR_GROUP2_INPUT18 = 184, //!< TCPWM trigger output reduction mux - tr_group[2].input[18] + TRIGGER_TR_GROUP2_INPUT19 = 185, //!< TCPWM trigger output reduction mux - tr_group[2].input[19] + TRIGGER_TR_GROUP2_INPUT20 = 186, //!< TCPWM trigger output reduction mux - tr_group[2].input[20] + TRIGGER_TR_GROUP2_INPUT21 = 187, //!< TCPWM trigger output reduction mux - tr_group[2].input[21] + TRIGGER_TR_GROUP2_INPUT22 = 188, //!< TCPWM trigger output reduction mux - tr_group[2].input[22] + TRIGGER_TR_GROUP2_INPUT23 = 189, //!< TCPWM trigger output reduction mux - tr_group[2].input[23] + TRIGGER_TR_GROUP2_INPUT24 = 190, //!< TCPWM trigger output reduction mux - tr_group[2].input[24] + TRIGGER_TR_GROUP2_INPUT25 = 191, //!< HSIOM Pin input reduction mux - tr_group[2].input[25] + TRIGGER_TR_GROUP2_INPUT26 = 192, //!< HSIOM Pin input reduction mux - tr_group[2].input[26] + TRIGGER_TR_GROUP2_INPUT27 = 193, //!< HSIOM Pin input reduction mux - tr_group[2].input[27] + TRIGGER_TR_GROUP2_INPUT28 = 194, //!< HSIOM Pin input reduction mux - tr_group[2].input[28] + TRIGGER_TR_GROUP2_INPUT29 = 195, //!< HSIOM Pin input reduction mux - tr_group[2].input[29] + TRIGGER_TR_GROUP2_INPUT30 = 196, //!< HSIOM Pin input reduction mux - tr_group[2].input[30] + TRIGGER_TR_GROUP2_INPUT31 = 197, //!< HSIOM Pin input reduction mux - tr_group[2].input[31] + TRIGGER_TR_GROUP2_INPUT32 = 198, //!< HSIOM Pin input reduction mux - tr_group[2].input[32] + TRIGGER_TR_GROUP2_INPUT33 = 199, //!< DMA request reduction mux - tr_group[2].input[33] + TRIGGER_TR_GROUP2_INPUT34 = 200, //!< DMA request reduction mux - tr_group[2].input[34] + TRIGGER_TR_GROUP2_INPUT35 = 201, //!< Trigger input reduction mux - tr_group[2].input[35] + TRIGGER_TR_GROUP2_INPUT36 = 202, //!< Trigger input reduction mux - tr_group[2].input[36] + TRIGGER_TR_GROUP2_INPUT37 = 203, //!< Trigger input reduction mux - tr_group[2].input[37] + TRIGGER_TR_GROUP2_INPUT38 = 204, //!< Trigger input reduction mux - tr_group[2].input[38] + TRIGGER_TR_GROUP2_INPUT39 = 205, //!< Trigger input reduction mux - tr_group[2].input[39] + TRIGGER_TR_GROUP2_INPUT40 = 206, //!< Trigger input reduction mux - tr_group[2].input[40] + TRIGGER_TR_GROUP2_INPUT41 = 207, //!< Trigger input reduction mux - tr_group[2].input[41] + TRIGGER_TR_GROUP2_INPUT42 = 208, //!< Trigger input reduction mux - tr_group[2].input[42] + TRIGGER_TR_GROUP3_INPUT1 = 209, //!< Datawire output trigger reduction mux - tr_group[3].input[1] + TRIGGER_TR_GROUP3_INPUT2 = 210, //!< Datawire output trigger reduction mux - tr_group[3].input[2] + TRIGGER_TR_GROUP3_INPUT3 = 211, //!< Datawire output trigger reduction mux - tr_group[3].input[3] + TRIGGER_TR_GROUP3_INPUT4 = 212, //!< Datawire output trigger reduction mux - tr_group[3].input[4] + TRIGGER_TR_GROUP3_INPUT5 = 213, //!< Datawire output trigger reduction mux - tr_group[3].input[5] + TRIGGER_TR_GROUP3_INPUT6 = 214, //!< Datawire output trigger reduction mux - tr_group[3].input[6] + TRIGGER_TR_GROUP3_INPUT7 = 215, //!< Datawire output trigger reduction mux - tr_group[3].input[7] + TRIGGER_TR_GROUP3_INPUT8 = 216, //!< Datawire output trigger reduction mux - tr_group[3].input[8] + TRIGGER_TR_GROUP3_INPUT9 = 217, //!< TCPWM trigger output reduction mux - tr_group[3].input[9] + TRIGGER_TR_GROUP3_INPUT10 = 218, //!< TCPWM trigger output reduction mux - tr_group[3].input[10] + TRIGGER_TR_GROUP3_INPUT11 = 219, //!< TCPWM trigger output reduction mux - tr_group[3].input[11] + TRIGGER_TR_GROUP3_INPUT12 = 220, //!< TCPWM trigger output reduction mux - tr_group[3].input[12] + TRIGGER_TR_GROUP3_INPUT13 = 221, //!< TCPWM trigger output reduction mux - tr_group[3].input[13] + TRIGGER_TR_GROUP3_INPUT14 = 222, //!< TCPWM trigger output reduction mux - tr_group[3].input[14] + TRIGGER_TR_GROUP3_INPUT15 = 223, //!< TCPWM trigger output reduction mux - tr_group[3].input[15] + TRIGGER_TR_GROUP3_INPUT16 = 224, //!< TCPWM trigger output reduction mux - tr_group[3].input[16] + TRIGGER_TR_GROUP3_INPUT17 = 225, //!< TCPWM trigger output reduction mux - tr_group[3].input[17] + TRIGGER_TR_GROUP3_INPUT18 = 226, //!< TCPWM trigger output reduction mux - tr_group[3].input[18] + TRIGGER_TR_GROUP3_INPUT19 = 227, //!< TCPWM trigger output reduction mux - tr_group[3].input[19] + TRIGGER_TR_GROUP3_INPUT20 = 228, //!< TCPWM trigger output reduction mux - tr_group[3].input[20] + TRIGGER_TR_GROUP3_INPUT21 = 229, //!< TCPWM trigger output reduction mux - tr_group[3].input[21] + TRIGGER_TR_GROUP3_INPUT22 = 230, //!< TCPWM trigger output reduction mux - tr_group[3].input[22] + TRIGGER_TR_GROUP3_INPUT23 = 231, //!< TCPWM trigger output reduction mux - tr_group[3].input[23] + TRIGGER_TR_GROUP3_INPUT24 = 232, //!< TCPWM trigger output reduction mux - tr_group[3].input[24] + TRIGGER_TR_GROUP3_INPUT25 = 233, //!< HSIOM Pin input reduction mux - tr_group[3].input[25] + TRIGGER_TR_GROUP3_INPUT26 = 234, //!< HSIOM Pin input reduction mux - tr_group[3].input[26] + TRIGGER_TR_GROUP3_INPUT27 = 235, //!< HSIOM Pin input reduction mux - tr_group[3].input[27] + TRIGGER_TR_GROUP3_INPUT28 = 236, //!< HSIOM Pin input reduction mux - tr_group[3].input[28] + TRIGGER_TR_GROUP3_INPUT29 = 237, //!< HSIOM Pin input reduction mux - tr_group[3].input[29] + TRIGGER_TR_GROUP3_INPUT30 = 238, //!< HSIOM Pin input reduction mux - tr_group[3].input[30] + TRIGGER_TR_GROUP3_INPUT31 = 239, //!< HSIOM Pin input reduction mux - tr_group[3].input[31] + TRIGGER_TR_GROUP3_INPUT32 = 240, //!< HSIOM Pin input reduction mux - tr_group[3].input[32] + TRIGGER_TR_GROUP3_INPUT33 = 241, //!< DMA request reduction mux - tr_group[3].input[33] + TRIGGER_TR_GROUP3_INPUT34 = 242, //!< DMA request reduction mux - tr_group[3].input[34] + TRIGGER_TR_GROUP3_INPUT35 = 243, //!< Trigger input reduction mux - tr_group[3].input[35] + TRIGGER_TR_GROUP3_INPUT36 = 244, //!< Trigger input reduction mux - tr_group[3].input[36] + TRIGGER_TR_GROUP3_INPUT37 = 245, //!< Trigger input reduction mux - tr_group[3].input[37] + TRIGGER_TR_GROUP3_INPUT38 = 246, //!< Trigger input reduction mux - tr_group[3].input[38] + TRIGGER_TR_GROUP3_INPUT39 = 247, //!< Trigger input reduction mux - tr_group[3].input[39] + TRIGGER_TR_GROUP3_INPUT40 = 248, //!< Trigger input reduction mux - tr_group[3].input[40] + TRIGGER_TR_GROUP3_INPUT41 = 249, //!< Trigger input reduction mux - tr_group[3].input[41] + TRIGGER_TR_GROUP3_INPUT42 = 250, //!< Trigger input reduction mux - tr_group[3].input[42] + TRIGGER_TR_GROUP4_INPUT1 = 251, //!< Datawire output trigger reduction mux - tr_group[4].input[1] + TRIGGER_TR_GROUP4_INPUT2 = 252, //!< Datawire output trigger reduction mux - tr_group[4].input[2] + TRIGGER_TR_GROUP4_INPUT3 = 253, //!< Datawire output trigger reduction mux - tr_group[4].input[3] + TRIGGER_TR_GROUP4_INPUT4 = 254, //!< Datawire output trigger reduction mux - tr_group[4].input[4] + TRIGGER_TR_GROUP4_INPUT5 = 255, //!< Datawire output trigger reduction mux - tr_group[4].input[5] + TRIGGER_TR_GROUP4_INPUT6 = 256, //!< Datawire output trigger reduction mux - tr_group[4].input[6] + TRIGGER_TR_GROUP4_INPUT7 = 257, //!< Datawire output trigger reduction mux - tr_group[4].input[7] + TRIGGER_TR_GROUP4_INPUT8 = 258, //!< Datawire output trigger reduction mux - tr_group[4].input[8] + TRIGGER_TR_GROUP4_INPUT9 = 259, //!< TCPWM trigger output reduction mux - tr_group[4].input[9] + TRIGGER_TR_GROUP4_INPUT10 = 260, //!< TCPWM trigger output reduction mux - tr_group[4].input[10] + TRIGGER_TR_GROUP4_INPUT11 = 261, //!< TCPWM trigger output reduction mux - tr_group[4].input[11] + TRIGGER_TR_GROUP4_INPUT12 = 262, //!< TCPWM trigger output reduction mux - tr_group[4].input[12] + TRIGGER_TR_GROUP4_INPUT13 = 263, //!< TCPWM trigger output reduction mux - tr_group[4].input[13] + TRIGGER_TR_GROUP4_INPUT14 = 264, //!< TCPWM trigger output reduction mux - tr_group[4].input[14] + TRIGGER_TR_GROUP4_INPUT15 = 265, //!< TCPWM trigger output reduction mux - tr_group[4].input[15] + TRIGGER_TR_GROUP4_INPUT16 = 266, //!< TCPWM trigger output reduction mux - tr_group[4].input[16] + TRIGGER_TR_GROUP4_INPUT17 = 267, //!< TCPWM trigger output reduction mux - tr_group[4].input[17] + TRIGGER_TR_GROUP4_INPUT18 = 268, //!< TCPWM trigger output reduction mux - tr_group[4].input[18] + TRIGGER_TR_GROUP4_INPUT19 = 269, //!< TCPWM trigger output reduction mux - tr_group[4].input[19] + TRIGGER_TR_GROUP4_INPUT20 = 270, //!< TCPWM trigger output reduction mux - tr_group[4].input[20] + TRIGGER_TR_GROUP4_INPUT21 = 271, //!< TCPWM trigger output reduction mux - tr_group[4].input[21] + TRIGGER_TR_GROUP4_INPUT22 = 272, //!< TCPWM trigger output reduction mux - tr_group[4].input[22] + TRIGGER_TR_GROUP4_INPUT23 = 273, //!< TCPWM trigger output reduction mux - tr_group[4].input[23] + TRIGGER_TR_GROUP4_INPUT24 = 274, //!< TCPWM trigger output reduction mux - tr_group[4].input[24] + TRIGGER_TR_GROUP4_INPUT25 = 275, //!< HSIOM Pin input reduction mux - tr_group[4].input[25] + TRIGGER_TR_GROUP4_INPUT26 = 276, //!< HSIOM Pin input reduction mux - tr_group[4].input[26] + TRIGGER_TR_GROUP4_INPUT27 = 277, //!< HSIOM Pin input reduction mux - tr_group[4].input[27] + TRIGGER_TR_GROUP4_INPUT28 = 278, //!< HSIOM Pin input reduction mux - tr_group[4].input[28] + TRIGGER_TR_GROUP4_INPUT29 = 279, //!< HSIOM Pin input reduction mux - tr_group[4].input[29] + TRIGGER_TR_GROUP4_INPUT30 = 280, //!< HSIOM Pin input reduction mux - tr_group[4].input[30] + TRIGGER_TR_GROUP4_INPUT31 = 281, //!< HSIOM Pin input reduction mux - tr_group[4].input[31] + TRIGGER_TR_GROUP4_INPUT32 = 282, //!< HSIOM Pin input reduction mux - tr_group[4].input[32] + TRIGGER_TR_GROUP4_INPUT33 = 283, //!< DMA request reduction mux - tr_group[4].input[33] + TRIGGER_TR_GROUP4_INPUT34 = 284, //!< DMA request reduction mux - tr_group[4].input[34] + TRIGGER_TR_GROUP4_INPUT35 = 285, //!< Trigger input reduction mux - tr_group[4].input[35] + TRIGGER_TR_GROUP4_INPUT36 = 286, //!< Trigger input reduction mux - tr_group[4].input[36] + TRIGGER_TR_GROUP4_INPUT37 = 287, //!< Trigger input reduction mux - tr_group[4].input[37] + TRIGGER_TR_GROUP4_INPUT38 = 288, //!< Trigger input reduction mux - tr_group[4].input[38] + TRIGGER_TR_GROUP4_INPUT39 = 289, //!< Trigger input reduction mux - tr_group[4].input[39] + TRIGGER_TR_GROUP4_INPUT40 = 290, //!< Trigger input reduction mux - tr_group[4].input[40] + TRIGGER_TR_GROUP4_INPUT41 = 291, //!< Trigger input reduction mux - tr_group[4].input[41] + TRIGGER_TR_GROUP4_INPUT42 = 292, //!< Trigger input reduction mux - tr_group[4].input[42] + TRIGGER_TR_GROUP5_INPUT1 = 293, //!< Datawire output trigger reduction mux - tr_group[5].input[1] + TRIGGER_TR_GROUP5_INPUT2 = 294, //!< Datawire output trigger reduction mux - tr_group[5].input[2] + TRIGGER_TR_GROUP5_INPUT3 = 295, //!< Datawire output trigger reduction mux - tr_group[5].input[3] + TRIGGER_TR_GROUP5_INPUT4 = 296, //!< Datawire output trigger reduction mux - tr_group[5].input[4] + TRIGGER_TR_GROUP5_INPUT5 = 297, //!< Datawire output trigger reduction mux - tr_group[5].input[5] + TRIGGER_TR_GROUP5_INPUT6 = 298, //!< Datawire output trigger reduction mux - tr_group[5].input[6] + TRIGGER_TR_GROUP5_INPUT7 = 299, //!< Datawire output trigger reduction mux - tr_group[5].input[7] + TRIGGER_TR_GROUP5_INPUT8 = 300, //!< Datawire output trigger reduction mux - tr_group[5].input[8] + TRIGGER_TR_GROUP5_INPUT9 = 301, //!< TCPWM trigger output reduction mux - tr_group[5].input[9] + TRIGGER_TR_GROUP5_INPUT10 = 302, //!< TCPWM trigger output reduction mux - tr_group[5].input[10] + TRIGGER_TR_GROUP5_INPUT11 = 303, //!< TCPWM trigger output reduction mux - tr_group[5].input[11] + TRIGGER_TR_GROUP5_INPUT12 = 304, //!< TCPWM trigger output reduction mux - tr_group[5].input[12] + TRIGGER_TR_GROUP5_INPUT13 = 305, //!< TCPWM trigger output reduction mux - tr_group[5].input[13] + TRIGGER_TR_GROUP5_INPUT14 = 306, //!< TCPWM trigger output reduction mux - tr_group[5].input[14] + TRIGGER_TR_GROUP5_INPUT15 = 307, //!< TCPWM trigger output reduction mux - tr_group[5].input[15] + TRIGGER_TR_GROUP5_INPUT16 = 308, //!< TCPWM trigger output reduction mux - tr_group[5].input[16] + TRIGGER_TR_GROUP5_INPUT17 = 309, //!< TCPWM trigger output reduction mux - tr_group[5].input[17] + TRIGGER_TR_GROUP5_INPUT18 = 310, //!< TCPWM trigger output reduction mux - tr_group[5].input[18] + TRIGGER_TR_GROUP5_INPUT19 = 311, //!< TCPWM trigger output reduction mux - tr_group[5].input[19] + TRIGGER_TR_GROUP5_INPUT20 = 312, //!< TCPWM trigger output reduction mux - tr_group[5].input[20] + TRIGGER_TR_GROUP5_INPUT21 = 313, //!< TCPWM trigger output reduction mux - tr_group[5].input[21] + TRIGGER_TR_GROUP5_INPUT22 = 314, //!< TCPWM trigger output reduction mux - tr_group[5].input[22] + TRIGGER_TR_GROUP5_INPUT23 = 315, //!< TCPWM trigger output reduction mux - tr_group[5].input[23] + TRIGGER_TR_GROUP5_INPUT24 = 316, //!< TCPWM trigger output reduction mux - tr_group[5].input[24] + TRIGGER_TR_GROUP5_INPUT25 = 317, //!< HSIOM Pin input reduction mux - tr_group[5].input[25] + TRIGGER_TR_GROUP5_INPUT26 = 318, //!< HSIOM Pin input reduction mux - tr_group[5].input[26] + TRIGGER_TR_GROUP5_INPUT27 = 319, //!< HSIOM Pin input reduction mux - tr_group[5].input[27] + TRIGGER_TR_GROUP5_INPUT28 = 320, //!< HSIOM Pin input reduction mux - tr_group[5].input[28] + TRIGGER_TR_GROUP5_INPUT29 = 321, //!< HSIOM Pin input reduction mux - tr_group[5].input[29] + TRIGGER_TR_GROUP5_INPUT30 = 322, //!< HSIOM Pin input reduction mux - tr_group[5].input[30] + TRIGGER_TR_GROUP5_INPUT31 = 323, //!< HSIOM Pin input reduction mux - tr_group[5].input[31] + TRIGGER_TR_GROUP5_INPUT32 = 324, //!< HSIOM Pin input reduction mux - tr_group[5].input[32] + TRIGGER_TR_GROUP5_INPUT33 = 325, //!< DMA request reduction mux - tr_group[5].input[33] + TRIGGER_TR_GROUP5_INPUT34 = 326, //!< DMA request reduction mux - tr_group[5].input[34] + TRIGGER_TR_GROUP5_INPUT35 = 327, //!< Trigger input reduction mux - tr_group[5].input[35] + TRIGGER_TR_GROUP5_INPUT36 = 328, //!< Trigger input reduction mux - tr_group[5].input[36] + TRIGGER_TR_GROUP5_INPUT37 = 329, //!< Trigger input reduction mux - tr_group[5].input[37] + TRIGGER_TR_GROUP5_INPUT38 = 330, //!< Trigger input reduction mux - tr_group[5].input[38] + TRIGGER_TR_GROUP5_INPUT39 = 331, //!< Trigger input reduction mux - tr_group[5].input[39] + TRIGGER_TR_GROUP5_INPUT40 = 332, //!< Trigger input reduction mux - tr_group[5].input[40] + TRIGGER_TR_GROUP5_INPUT41 = 333, //!< Trigger input reduction mux - tr_group[5].input[41] + TRIGGER_TR_GROUP5_INPUT42 = 334, //!< Trigger input reduction mux - tr_group[5].input[42] + TRIGGER_TR_GROUP6_INPUT1 = 335, //!< Datawire output trigger reduction mux - tr_group[6].input[1] + TRIGGER_TR_GROUP6_INPUT2 = 336, //!< Datawire output trigger reduction mux - tr_group[6].input[2] + TRIGGER_TR_GROUP6_INPUT3 = 337, //!< Datawire output trigger reduction mux - tr_group[6].input[3] + TRIGGER_TR_GROUP6_INPUT4 = 338, //!< Datawire output trigger reduction mux - tr_group[6].input[4] + TRIGGER_TR_GROUP6_INPUT5 = 339, //!< Datawire output trigger reduction mux - tr_group[6].input[5] + TRIGGER_TR_GROUP6_INPUT6 = 340, //!< Datawire output trigger reduction mux - tr_group[6].input[6] + TRIGGER_TR_GROUP6_INPUT7 = 341, //!< Datawire output trigger reduction mux - tr_group[6].input[7] + TRIGGER_TR_GROUP6_INPUT8 = 342, //!< Datawire output trigger reduction mux - tr_group[6].input[8] + TRIGGER_TR_GROUP6_INPUT9 = 343, //!< TCPWM trigger output reduction mux - tr_group[6].input[9] + TRIGGER_TR_GROUP6_INPUT10 = 344, //!< TCPWM trigger output reduction mux - tr_group[6].input[10] + TRIGGER_TR_GROUP6_INPUT11 = 345, //!< TCPWM trigger output reduction mux - tr_group[6].input[11] + TRIGGER_TR_GROUP6_INPUT12 = 346, //!< TCPWM trigger output reduction mux - tr_group[6].input[12] + TRIGGER_TR_GROUP6_INPUT13 = 347, //!< TCPWM trigger output reduction mux - tr_group[6].input[13] + TRIGGER_TR_GROUP6_INPUT14 = 348, //!< TCPWM trigger output reduction mux - tr_group[6].input[14] + TRIGGER_TR_GROUP6_INPUT15 = 349, //!< TCPWM trigger output reduction mux - tr_group[6].input[15] + TRIGGER_TR_GROUP6_INPUT16 = 350, //!< TCPWM trigger output reduction mux - tr_group[6].input[16] + TRIGGER_TR_GROUP6_INPUT17 = 351, //!< TCPWM trigger output reduction mux - tr_group[6].input[17] + TRIGGER_TR_GROUP6_INPUT18 = 352, //!< TCPWM trigger output reduction mux - tr_group[6].input[18] + TRIGGER_TR_GROUP6_INPUT19 = 353, //!< TCPWM trigger output reduction mux - tr_group[6].input[19] + TRIGGER_TR_GROUP6_INPUT20 = 354, //!< TCPWM trigger output reduction mux - tr_group[6].input[20] + TRIGGER_TR_GROUP6_INPUT21 = 355, //!< TCPWM trigger output reduction mux - tr_group[6].input[21] + TRIGGER_TR_GROUP6_INPUT22 = 356, //!< TCPWM trigger output reduction mux - tr_group[6].input[22] + TRIGGER_TR_GROUP6_INPUT23 = 357, //!< TCPWM trigger output reduction mux - tr_group[6].input[23] + TRIGGER_TR_GROUP6_INPUT24 = 358, //!< TCPWM trigger output reduction mux - tr_group[6].input[24] + TRIGGER_TR_GROUP6_INPUT25 = 359, //!< HSIOM Pin input reduction mux - tr_group[6].input[25] + TRIGGER_TR_GROUP6_INPUT26 = 360, //!< HSIOM Pin input reduction mux - tr_group[6].input[26] + TRIGGER_TR_GROUP6_INPUT27 = 361, //!< HSIOM Pin input reduction mux - tr_group[6].input[27] + TRIGGER_TR_GROUP6_INPUT28 = 362, //!< HSIOM Pin input reduction mux - tr_group[6].input[28] + TRIGGER_TR_GROUP6_INPUT29 = 363, //!< HSIOM Pin input reduction mux - tr_group[6].input[29] + TRIGGER_TR_GROUP6_INPUT30 = 364, //!< HSIOM Pin input reduction mux - tr_group[6].input[30] + TRIGGER_TR_GROUP6_INPUT31 = 365, //!< HSIOM Pin input reduction mux - tr_group[6].input[31] + TRIGGER_TR_GROUP6_INPUT32 = 366, //!< HSIOM Pin input reduction mux - tr_group[6].input[32] + TRIGGER_TR_GROUP6_INPUT33 = 367, //!< DMA request reduction mux - tr_group[6].input[33] + TRIGGER_TR_GROUP6_INPUT34 = 368, //!< DMA request reduction mux - tr_group[6].input[34] + TRIGGER_TR_GROUP6_INPUT35 = 369, //!< Trigger input reduction mux - tr_group[6].input[35] + TRIGGER_TR_GROUP6_INPUT36 = 370, //!< Trigger input reduction mux - tr_group[6].input[36] + TRIGGER_TR_GROUP6_INPUT37 = 371, //!< Trigger input reduction mux - tr_group[6].input[37] + TRIGGER_TR_GROUP6_INPUT38 = 372, //!< Trigger input reduction mux - tr_group[6].input[38] + TRIGGER_TR_GROUP6_INPUT39 = 373, //!< Trigger input reduction mux - tr_group[6].input[39] + TRIGGER_TR_GROUP6_INPUT40 = 374, //!< Trigger input reduction mux - tr_group[6].input[40] + TRIGGER_TR_GROUP6_INPUT41 = 375, //!< Trigger input reduction mux - tr_group[6].input[41] + TRIGGER_TR_GROUP6_INPUT42 = 376, //!< Trigger input reduction mux - tr_group[6].input[42] + TRIGGER_TR_GROUP7_INPUT1 = 377, //!< Datawire output trigger reduction mux - tr_group[7].input[1] + TRIGGER_TR_GROUP7_INPUT2 = 378, //!< Datawire output trigger reduction mux - tr_group[7].input[2] + TRIGGER_TR_GROUP7_INPUT3 = 379, //!< Datawire output trigger reduction mux - tr_group[7].input[3] + TRIGGER_TR_GROUP7_INPUT4 = 380, //!< Datawire output trigger reduction mux - tr_group[7].input[4] + TRIGGER_TR_GROUP7_INPUT5 = 381, //!< Datawire output trigger reduction mux - tr_group[7].input[5] + TRIGGER_TR_GROUP7_INPUT6 = 382, //!< Datawire output trigger reduction mux - tr_group[7].input[6] + TRIGGER_TR_GROUP7_INPUT7 = 383, //!< Datawire output trigger reduction mux - tr_group[7].input[7] + TRIGGER_TR_GROUP7_INPUT8 = 384, //!< Datawire output trigger reduction mux - tr_group[7].input[8] + TRIGGER_TR_GROUP7_INPUT9 = 385, //!< TCPWM trigger output reduction mux - tr_group[7].input[9] + TRIGGER_TR_GROUP7_INPUT10 = 386, //!< TCPWM trigger output reduction mux - tr_group[7].input[10] + TRIGGER_TR_GROUP7_INPUT11 = 387, //!< TCPWM trigger output reduction mux - tr_group[7].input[11] + TRIGGER_TR_GROUP7_INPUT12 = 388, //!< TCPWM trigger output reduction mux - tr_group[7].input[12] + TRIGGER_TR_GROUP7_INPUT13 = 389, //!< TCPWM trigger output reduction mux - tr_group[7].input[13] + TRIGGER_TR_GROUP7_INPUT14 = 390, //!< TCPWM trigger output reduction mux - tr_group[7].input[14] + TRIGGER_TR_GROUP7_INPUT15 = 391, //!< TCPWM trigger output reduction mux - tr_group[7].input[15] + TRIGGER_TR_GROUP7_INPUT16 = 392, //!< TCPWM trigger output reduction mux - tr_group[7].input[16] + TRIGGER_TR_GROUP7_INPUT17 = 393, //!< TCPWM trigger output reduction mux - tr_group[7].input[17] + TRIGGER_TR_GROUP7_INPUT18 = 394, //!< TCPWM trigger output reduction mux - tr_group[7].input[18] + TRIGGER_TR_GROUP7_INPUT19 = 395, //!< TCPWM trigger output reduction mux - tr_group[7].input[19] + TRIGGER_TR_GROUP7_INPUT20 = 396, //!< TCPWM trigger output reduction mux - tr_group[7].input[20] + TRIGGER_TR_GROUP7_INPUT21 = 397, //!< TCPWM trigger output reduction mux - tr_group[7].input[21] + TRIGGER_TR_GROUP7_INPUT22 = 398, //!< TCPWM trigger output reduction mux - tr_group[7].input[22] + TRIGGER_TR_GROUP7_INPUT23 = 399, //!< TCPWM trigger output reduction mux - tr_group[7].input[23] + TRIGGER_TR_GROUP7_INPUT24 = 400, //!< TCPWM trigger output reduction mux - tr_group[7].input[24] + TRIGGER_TR_GROUP7_INPUT25 = 401, //!< HSIOM Pin input reduction mux - tr_group[7].input[25] + TRIGGER_TR_GROUP7_INPUT26 = 402, //!< HSIOM Pin input reduction mux - tr_group[7].input[26] + TRIGGER_TR_GROUP7_INPUT27 = 403, //!< HSIOM Pin input reduction mux - tr_group[7].input[27] + TRIGGER_TR_GROUP7_INPUT28 = 404, //!< HSIOM Pin input reduction mux - tr_group[7].input[28] + TRIGGER_TR_GROUP7_INPUT29 = 405, //!< HSIOM Pin input reduction mux - tr_group[7].input[29] + TRIGGER_TR_GROUP7_INPUT30 = 406, //!< HSIOM Pin input reduction mux - tr_group[7].input[30] + TRIGGER_TR_GROUP7_INPUT31 = 407, //!< HSIOM Pin input reduction mux - tr_group[7].input[31] + TRIGGER_TR_GROUP7_INPUT32 = 408, //!< HSIOM Pin input reduction mux - tr_group[7].input[32] + TRIGGER_TR_GROUP7_INPUT33 = 409, //!< DMA request reduction mux - tr_group[7].input[33] + TRIGGER_TR_GROUP7_INPUT34 = 410, //!< DMA request reduction mux - tr_group[7].input[34] + TRIGGER_TR_GROUP7_INPUT35 = 411, //!< Trigger input reduction mux - tr_group[7].input[35] + TRIGGER_TR_GROUP7_INPUT36 = 412, //!< Trigger input reduction mux - tr_group[7].input[36] + TRIGGER_TR_GROUP7_INPUT37 = 413, //!< Trigger input reduction mux - tr_group[7].input[37] + TRIGGER_TR_GROUP7_INPUT38 = 414, //!< Trigger input reduction mux - tr_group[7].input[38] + TRIGGER_TR_GROUP7_INPUT39 = 415, //!< Trigger input reduction mux - tr_group[7].input[39] + TRIGGER_TR_GROUP7_INPUT40 = 416, //!< Trigger input reduction mux - tr_group[7].input[40] + TRIGGER_TR_GROUP7_INPUT41 = 417, //!< Trigger input reduction mux - tr_group[7].input[41] + TRIGGER_TR_GROUP7_INPUT42 = 418, //!< Trigger input reduction mux - tr_group[7].input[42] + TRIGGER_TR_GROUP8_INPUT1 = 419, //!< Datawire output trigger reduction mux - tr_group[8].input[1] + TRIGGER_TR_GROUP8_INPUT2 = 420, //!< Datawire output trigger reduction mux - tr_group[8].input[2] + TRIGGER_TR_GROUP8_INPUT3 = 421, //!< Datawire output trigger reduction mux - tr_group[8].input[3] + TRIGGER_TR_GROUP8_INPUT4 = 422, //!< Datawire output trigger reduction mux - tr_group[8].input[4] + TRIGGER_TR_GROUP8_INPUT5 = 423, //!< Datawire output trigger reduction mux - tr_group[8].input[5] + TRIGGER_TR_GROUP8_INPUT6 = 424, //!< Datawire output trigger reduction mux - tr_group[8].input[6] + TRIGGER_TR_GROUP8_INPUT7 = 425, //!< Datawire output trigger reduction mux - tr_group[8].input[7] + TRIGGER_TR_GROUP8_INPUT8 = 426, //!< Datawire output trigger reduction mux - tr_group[8].input[8] + TRIGGER_TR_GROUP8_INPUT9 = 427, //!< TCPWM trigger output reduction mux - tr_group[8].input[9] + TRIGGER_TR_GROUP8_INPUT10 = 428, //!< TCPWM trigger output reduction mux - tr_group[8].input[10] + TRIGGER_TR_GROUP8_INPUT11 = 429, //!< TCPWM trigger output reduction mux - tr_group[8].input[11] + TRIGGER_TR_GROUP8_INPUT12 = 430, //!< TCPWM trigger output reduction mux - tr_group[8].input[12] + TRIGGER_TR_GROUP8_INPUT13 = 431, //!< TCPWM trigger output reduction mux - tr_group[8].input[13] + TRIGGER_TR_GROUP8_INPUT14 = 432, //!< TCPWM trigger output reduction mux - tr_group[8].input[14] + TRIGGER_TR_GROUP8_INPUT15 = 433, //!< TCPWM trigger output reduction mux - tr_group[8].input[15] + TRIGGER_TR_GROUP8_INPUT16 = 434, //!< TCPWM trigger output reduction mux - tr_group[8].input[16] + TRIGGER_TR_GROUP8_INPUT17 = 435, //!< TCPWM trigger output reduction mux - tr_group[8].input[17] + TRIGGER_TR_GROUP8_INPUT18 = 436, //!< TCPWM trigger output reduction mux - tr_group[8].input[18] + TRIGGER_TR_GROUP8_INPUT19 = 437, //!< TCPWM trigger output reduction mux - tr_group[8].input[19] + TRIGGER_TR_GROUP8_INPUT20 = 438, //!< TCPWM trigger output reduction mux - tr_group[8].input[20] + TRIGGER_TR_GROUP8_INPUT21 = 439, //!< TCPWM trigger output reduction mux - tr_group[8].input[21] + TRIGGER_TR_GROUP8_INPUT22 = 440, //!< TCPWM trigger output reduction mux - tr_group[8].input[22] + TRIGGER_TR_GROUP8_INPUT23 = 441, //!< TCPWM trigger output reduction mux - tr_group[8].input[23] + TRIGGER_TR_GROUP8_INPUT24 = 442, //!< TCPWM trigger output reduction mux - tr_group[8].input[24] + TRIGGER_TR_GROUP8_INPUT25 = 443, //!< HSIOM Pin input reduction mux - tr_group[8].input[25] + TRIGGER_TR_GROUP8_INPUT26 = 444, //!< HSIOM Pin input reduction mux - tr_group[8].input[26] + TRIGGER_TR_GROUP8_INPUT27 = 445, //!< HSIOM Pin input reduction mux - tr_group[8].input[27] + TRIGGER_TR_GROUP8_INPUT28 = 446, //!< HSIOM Pin input reduction mux - tr_group[8].input[28] + TRIGGER_TR_GROUP8_INPUT29 = 447, //!< HSIOM Pin input reduction mux - tr_group[8].input[29] + TRIGGER_TR_GROUP8_INPUT30 = 448, //!< HSIOM Pin input reduction mux - tr_group[8].input[30] + TRIGGER_TR_GROUP8_INPUT31 = 449, //!< HSIOM Pin input reduction mux - tr_group[8].input[31] + TRIGGER_TR_GROUP8_INPUT32 = 450, //!< HSIOM Pin input reduction mux - tr_group[8].input[32] + TRIGGER_TR_GROUP8_INPUT33 = 451, //!< DMA request reduction mux - tr_group[8].input[33] + TRIGGER_TR_GROUP8_INPUT34 = 452, //!< DMA request reduction mux - tr_group[8].input[34] + TRIGGER_TR_GROUP8_INPUT35 = 453, //!< Trigger input reduction mux - tr_group[8].input[35] + TRIGGER_TR_GROUP8_INPUT36 = 454, //!< Trigger input reduction mux - tr_group[8].input[36] + TRIGGER_TR_GROUP8_INPUT37 = 455, //!< Trigger input reduction mux - tr_group[8].input[37] + TRIGGER_TR_GROUP8_INPUT38 = 456, //!< Trigger input reduction mux - tr_group[8].input[38] + TRIGGER_TR_GROUP8_INPUT39 = 457, //!< Trigger input reduction mux - tr_group[8].input[39] + TRIGGER_TR_GROUP8_INPUT40 = 458, //!< Trigger input reduction mux - tr_group[8].input[40] + TRIGGER_TR_GROUP8_INPUT41 = 459, //!< Trigger input reduction mux - tr_group[8].input[41] + TRIGGER_TR_GROUP8_INPUT42 = 460, //!< Trigger input reduction mux - tr_group[8].input[42] + TRIGGER_UDB_TR_DW_ACK0 = 461, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[0] + TRIGGER_UDB_TR_DW_ACK1 = 462, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[1] + TRIGGER_UDB_TR_DW_ACK2 = 463, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[2] + TRIGGER_UDB_TR_DW_ACK3 = 464, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[3] + TRIGGER_UDB_TR_DW_ACK4 = 465, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[4] + TRIGGER_UDB_TR_DW_ACK5 = 466, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[5] + TRIGGER_UDB_TR_DW_ACK6 = 467, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[6] + TRIGGER_UDB_TR_DW_ACK7 = 468, //!< Datawire output trigger reduction mux - udb.tr_dw_ack[7] + TRIGGER_UDB_TR_IN0 = 469, //!< UDB trigger multiplexer - udb.tr_in[0] + TRIGGER_UDB_TR_IN1 = 470, //!< UDB trigger multiplexer - udb.tr_in[1] + TRIGGER_USB_DMA_BURSTEND0 = 471, //!< USB DMA burstend multiplexer - usb.dma_burstend[0] + TRIGGER_USB_DMA_BURSTEND1 = 472, //!< USB DMA burstend multiplexer - usb.dma_burstend[1] + TRIGGER_USB_DMA_BURSTEND2 = 473, //!< USB DMA burstend multiplexer - usb.dma_burstend[2] + TRIGGER_USB_DMA_BURSTEND3 = 474, //!< USB DMA burstend multiplexer - usb.dma_burstend[3] + TRIGGER_USB_DMA_BURSTEND4 = 475, //!< USB DMA burstend multiplexer - usb.dma_burstend[4] + TRIGGER_USB_DMA_BURSTEND5 = 476, //!< USB DMA burstend multiplexer - usb.dma_burstend[5] + TRIGGER_USB_DMA_BURSTEND6 = 477, //!< USB DMA burstend multiplexer - usb.dma_burstend[6] + TRIGGER_USB_DMA_BURSTEND7 = 478, //!< USB DMA burstend multiplexer - usb.dma_burstend[7] +} cyhal_trigger_dest_psoc6_01_t; + +/** Typedef from device family specific trigger dest to generic trigger dest */ +typedef cyhal_trigger_dest_psoc6_01_t cyhal_dest_t; + +/** \cond INTERNAL */ +/** Maps each cyhal_destination_t to a mux index. + * If bit 8 of the mux index is set, this denotes that the trigger is a + * one to one trigger. + */ +extern const uint8_t cyhal_dest_to_mux[479]; + +/* Maps each cyhal_destination_t to a specific output in its mux */ +extern const uint8_t cyhal_mux_dest_index[479]; +/** \endcond */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +/** \} group_hal_psoc6_triggers_psoc6_01 */ +#endif /* _CYHAL_TRIGGERS_PSOC6_01_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/triggers/cyhal_triggers_psoc6_02.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/triggers/cyhal_triggers_psoc6_02.h new file mode 100644 index 00000000000..258a8b261d4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/triggers/cyhal_triggers_psoc6_02.h @@ -0,0 +1,175 @@ +/***************************************************************************//** +* \file cyhal_triggers_psoc6_02.h +* +* \brief +* PSoC6_02 family HAL triggers header +* +* \note +* Generator version: 1.5.7254.19579 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYHAL_TRIGGERS_PSOC6_02_H_ +#define _CYHAL_TRIGGERS_PSOC6_02_H_ + +/** + * \addtogroup group_hal_psoc6_triggers_psoc6_02 PSOC6_02 + * \ingroup group_hal_psoc6_triggers + * \{ + * Trigger connections for psoc6_02 + */ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** @brief Name of each output trigger. */ +typedef enum +{ + TRIGGER_CPUSS_CTI_TR_IN0 = 0, //!< CPUSS Debug and Profiler trigger multiplexer - cpuss.cti_tr_in[0] + TRIGGER_CPUSS_CTI_TR_IN1 = 1, //!< CPUSS Debug and Profiler trigger multiplexer - cpuss.cti_tr_in[1] + TRIGGER_CPUSS_DMAC_TR_IN0 = 2, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[0] + TRIGGER_CPUSS_DMAC_TR_IN1 = 3, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[1] + TRIGGER_CPUSS_DMAC_TR_IN2 = 4, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[2] + TRIGGER_CPUSS_DMAC_TR_IN3 = 5, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[3] + TRIGGER_CPUSS_DW0_TR_IN0 = 6, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[0] + TRIGGER_CPUSS_DW0_TR_IN1 = 7, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[1] + TRIGGER_CPUSS_DW0_TR_IN2 = 8, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[2] + TRIGGER_CPUSS_DW0_TR_IN3 = 9, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[3] + TRIGGER_CPUSS_DW0_TR_IN4 = 10, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[4] + TRIGGER_CPUSS_DW0_TR_IN5 = 11, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[5] + TRIGGER_CPUSS_DW0_TR_IN6 = 12, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[6] + TRIGGER_CPUSS_DW0_TR_IN7 = 13, //!< P-DMA0 trigger multiplexer - cpuss.dw0_tr_in[7] + TRIGGER_CPUSS_DW0_TR_IN8 = 14, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[8] + TRIGGER_CPUSS_DW0_TR_IN9 = 15, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[9] + TRIGGER_CPUSS_DW0_TR_IN10 = 16, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[10] + TRIGGER_CPUSS_DW0_TR_IN11 = 17, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[11] + TRIGGER_CPUSS_DW0_TR_IN12 = 18, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[12] + TRIGGER_CPUSS_DW0_TR_IN13 = 19, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[13] + TRIGGER_CPUSS_DW0_TR_IN14 = 20, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[14] + TRIGGER_CPUSS_DW0_TR_IN15 = 21, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[15] + TRIGGER_CPUSS_DW0_TR_IN16 = 22, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[16] + TRIGGER_CPUSS_DW0_TR_IN17 = 23, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[17] + TRIGGER_CPUSS_DW0_TR_IN18 = 24, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[18] + TRIGGER_CPUSS_DW0_TR_IN19 = 25, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[19] + TRIGGER_CPUSS_DW0_TR_IN20 = 26, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[20] + TRIGGER_CPUSS_DW0_TR_IN21 = 27, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[21] + TRIGGER_CPUSS_DW0_TR_IN22 = 28, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[22] + TRIGGER_CPUSS_DW0_TR_IN23 = 29, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[23] + TRIGGER_CPUSS_DW0_TR_IN24 = 30, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[24] + TRIGGER_CPUSS_DW0_TR_IN25 = 31, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[25] + TRIGGER_CPUSS_DW0_TR_IN26 = 32, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[26] + TRIGGER_CPUSS_DW0_TR_IN27 = 33, //!< SCB DW0 Triggers - cpuss.dw0_tr_in[27] + TRIGGER_CPUSS_DW0_TR_IN28 = 34, //!< SAR to PDMA0 direct connect - cpuss.dw0_tr_in[28] + TRIGGER_CPUSS_DW1_TR_IN0 = 35, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[0] + TRIGGER_CPUSS_DW1_TR_IN1 = 36, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[1] + TRIGGER_CPUSS_DW1_TR_IN2 = 37, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[2] + TRIGGER_CPUSS_DW1_TR_IN3 = 38, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[3] + TRIGGER_CPUSS_DW1_TR_IN4 = 39, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[4] + TRIGGER_CPUSS_DW1_TR_IN5 = 40, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[5] + TRIGGER_CPUSS_DW1_TR_IN6 = 41, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[6] + TRIGGER_CPUSS_DW1_TR_IN7 = 42, //!< P-DMA1 trigger multiplexer - cpuss.dw1_tr_in[7] + TRIGGER_CPUSS_DW1_TR_IN8 = 43, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[8] + TRIGGER_CPUSS_DW1_TR_IN9 = 44, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[9] + TRIGGER_CPUSS_DW1_TR_IN10 = 45, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[10] + TRIGGER_CPUSS_DW1_TR_IN11 = 46, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[11] + TRIGGER_CPUSS_DW1_TR_IN12 = 47, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[12] + TRIGGER_CPUSS_DW1_TR_IN13 = 48, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[13] + TRIGGER_CPUSS_DW1_TR_IN14 = 49, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[14] + TRIGGER_CPUSS_DW1_TR_IN15 = 50, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[15] + TRIGGER_CPUSS_DW1_TR_IN16 = 51, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[16] + TRIGGER_CPUSS_DW1_TR_IN17 = 52, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[17] + TRIGGER_CPUSS_DW1_TR_IN18 = 53, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[18] + TRIGGER_CPUSS_DW1_TR_IN19 = 54, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[19] + TRIGGER_CPUSS_DW1_TR_IN20 = 55, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[20] + TRIGGER_CPUSS_DW1_TR_IN21 = 56, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[21] + TRIGGER_CPUSS_DW1_TR_IN22 = 57, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[22] + TRIGGER_CPUSS_DW1_TR_IN23 = 58, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[23] + TRIGGER_CPUSS_DW1_TR_IN24 = 59, //!< AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw1_tr_in[24] + TRIGGER_CPUSS_DW1_TR_IN25 = 60, //!< AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw1_tr_in[25] + TRIGGER_CPUSS_DW1_TR_IN26 = 61, //!< AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw1_tr_in[26] + TRIGGER_CPUSS_DW1_TR_IN27 = 62, //!< AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw1_tr_in[27] + TRIGGER_CPUSS_DW1_TR_IN28 = 63, //!< AUDIOSS PDMA1 triggers (I2S & PDM) - cpuss.dw1_tr_in[28] + TRIGGER_CSD_DSI_START = 64, //!< Capsense trigger multiplexer - csd.dsi_start + TRIGGER_PASS_TR_SAR_IN = 65, //!< ADC trigger multiplexer - pass.tr_sar_in + TRIGGER_PERI_TR_DBG_FREEZE = 66, //!< PERI Freeze trigger multiplexer - peri.tr_dbg_freeze + TRIGGER_PERI_TR_IO_OUTPUT0 = 67, //!< HSIOM trigger multiplexer - peri.tr_io_output[0] + TRIGGER_PERI_TR_IO_OUTPUT1 = 68, //!< HSIOM trigger multiplexer - peri.tr_io_output[1] + TRIGGER_PROFILE_TR_START = 69, //!< CPUSS Debug and Profiler trigger multiplexer - profile.tr_start + TRIGGER_PROFILE_TR_STOP = 70, //!< CPUSS Debug and Profiler trigger multiplexer - profile.tr_stop + TRIGGER_TCPWM0_TR_IN0 = 71, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[0] + TRIGGER_TCPWM0_TR_IN1 = 72, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[1] + TRIGGER_TCPWM0_TR_IN2 = 73, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[2] + TRIGGER_TCPWM0_TR_IN3 = 74, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[3] + TRIGGER_TCPWM0_TR_IN4 = 75, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[4] + TRIGGER_TCPWM0_TR_IN5 = 76, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[5] + TRIGGER_TCPWM0_TR_IN6 = 77, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[6] + TRIGGER_TCPWM0_TR_IN7 = 78, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[7] + TRIGGER_TCPWM0_TR_IN8 = 79, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[8] + TRIGGER_TCPWM0_TR_IN9 = 80, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[9] + TRIGGER_TCPWM0_TR_IN10 = 81, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[10] + TRIGGER_TCPWM0_TR_IN11 = 82, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[11] + TRIGGER_TCPWM0_TR_IN12 = 83, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[12] + TRIGGER_TCPWM0_TR_IN13 = 84, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[13] + TRIGGER_TCPWM1_TR_IN0 = 85, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[0] + TRIGGER_TCPWM1_TR_IN1 = 86, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[1] + TRIGGER_TCPWM1_TR_IN2 = 87, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[2] + TRIGGER_TCPWM1_TR_IN3 = 88, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[3] + TRIGGER_TCPWM1_TR_IN4 = 89, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[4] + TRIGGER_TCPWM1_TR_IN5 = 90, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[5] + TRIGGER_TCPWM1_TR_IN6 = 91, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[6] + TRIGGER_TCPWM1_TR_IN7 = 92, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[7] + TRIGGER_TCPWM1_TR_IN8 = 93, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[8] + TRIGGER_TCPWM1_TR_IN9 = 94, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[9] + TRIGGER_TCPWM1_TR_IN10 = 95, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[10] + TRIGGER_TCPWM1_TR_IN11 = 96, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[11] + TRIGGER_TCPWM1_TR_IN12 = 97, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[12] + TRIGGER_TCPWM1_TR_IN13 = 98, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[13] + TRIGGER_USB_DMA_BURSTEND0 = 99, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[0] + TRIGGER_USB_DMA_BURSTEND1 = 100, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[1] + TRIGGER_USB_DMA_BURSTEND2 = 101, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[2] + TRIGGER_USB_DMA_BURSTEND3 = 102, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[3] + TRIGGER_USB_DMA_BURSTEND4 = 103, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[4] + TRIGGER_USB_DMA_BURSTEND5 = 104, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[5] + TRIGGER_USB_DMA_BURSTEND6 = 105, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[6] + TRIGGER_USB_DMA_BURSTEND7 = 106, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[7] +} cyhal_trigger_dest_psoc6_02_t; + +/** Typedef from device family specific trigger dest to generic trigger dest */ +typedef cyhal_trigger_dest_psoc6_02_t cyhal_dest_t; + +/** \cond INTERNAL */ +/** Maps each cyhal_destination_t to a mux index. + * If bit 8 of the mux index is set, this denotes that the trigger is a + * one to one trigger. + */ +extern const uint8_t cyhal_dest_to_mux[107]; + +/* Maps each cyhal_destination_t to a specific output in its mux */ +extern const uint8_t cyhal_mux_dest_index[107]; +/** \endcond */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +/** \} group_hal_psoc6_triggers_psoc6_02 */ +#endif /* _CYHAL_TRIGGERS_PSOC6_02_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/triggers/cyhal_triggers_psoc6_03.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/triggers/cyhal_triggers_psoc6_03.h new file mode 100644 index 00000000000..e9504eba62c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/include/triggers/cyhal_triggers_psoc6_03.h @@ -0,0 +1,176 @@ +/***************************************************************************//** +* \file cyhal_triggers_psoc6_03.h +* +* \brief +* PSoC6_03 family HAL triggers header +* +* \note +* Generator version: 1.5.7254.19579 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYHAL_TRIGGERS_PSOC6_03_H_ +#define _CYHAL_TRIGGERS_PSOC6_03_H_ + +/** + * \addtogroup group_hal_psoc6_triggers_psoc6_03 PSOC6_03 + * \ingroup group_hal_psoc6_triggers + * \{ + * Trigger connections for psoc6_03 + */ + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +/** @brief Name of each output trigger. */ +typedef enum +{ + TRIGGER_CANFD0_TR_DBG_DMA_ACK0 = 0, //!< CAN DW0 triggers (from DW back to CAN) - canfd[0].tr_dbg_dma_ack[0] + TRIGGER_CANFD0_TR_EVT_SWT_IN0 = 1, //!< CAN TT Sync - canfd[0].tr_evt_swt_in[0] + TRIGGER_CPUSS_CTI_TR_IN0 = 2, //!< CPUSS Debug trigger multiplexer - cpuss.cti_tr_in[0] + TRIGGER_CPUSS_CTI_TR_IN1 = 3, //!< CPUSS Debug trigger multiplexer - cpuss.cti_tr_in[1] + TRIGGER_CPUSS_DMAC_TR_IN0 = 4, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[0] + TRIGGER_CPUSS_DMAC_TR_IN1 = 5, //!< MDMA trigger multiplexer - cpuss.dmac_tr_in[1] + TRIGGER_CPUSS_DW0_TR_IN0 = 6, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[0] + TRIGGER_CPUSS_DW0_TR_IN1 = 7, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[1] + TRIGGER_CPUSS_DW0_TR_IN2 = 8, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[2] + TRIGGER_CPUSS_DW0_TR_IN3 = 9, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[3] + TRIGGER_CPUSS_DW0_TR_IN4 = 10, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[4] + TRIGGER_CPUSS_DW0_TR_IN5 = 11, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[5] + TRIGGER_CPUSS_DW0_TR_IN6 = 12, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[6] + TRIGGER_CPUSS_DW0_TR_IN7 = 13, //!< PDMA0 trigger multiplexer - cpuss.dw0_tr_in[7] + TRIGGER_CPUSS_DW0_TR_IN8 = 14, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[8] + TRIGGER_CPUSS_DW0_TR_IN9 = 15, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[9] + TRIGGER_CPUSS_DW0_TR_IN10 = 16, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[10] + TRIGGER_CPUSS_DW0_TR_IN11 = 17, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[11] + TRIGGER_CPUSS_DW0_TR_IN12 = 18, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[12] + TRIGGER_CPUSS_DW0_TR_IN13 = 19, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[13] + TRIGGER_CPUSS_DW0_TR_IN14 = 20, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[14] + TRIGGER_CPUSS_DW0_TR_IN15 = 21, //!< USB PDMA0 Triggers - cpuss.dw0_tr_in[15] + TRIGGER_CPUSS_DW0_TR_IN16 = 22, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[16] + TRIGGER_CPUSS_DW0_TR_IN17 = 23, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[17] + TRIGGER_CPUSS_DW0_TR_IN18 = 24, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[18] + TRIGGER_CPUSS_DW0_TR_IN19 = 25, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[19] + TRIGGER_CPUSS_DW0_TR_IN20 = 26, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[20] + TRIGGER_CPUSS_DW0_TR_IN21 = 27, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[21] + TRIGGER_CPUSS_DW0_TR_IN22 = 28, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[22] + TRIGGER_CPUSS_DW0_TR_IN23 = 29, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[23] + TRIGGER_CPUSS_DW0_TR_IN24 = 30, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[24] + TRIGGER_CPUSS_DW0_TR_IN25 = 31, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[25] + TRIGGER_CPUSS_DW0_TR_IN26 = 32, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[26] + TRIGGER_CPUSS_DW0_TR_IN27 = 33, //!< SCB PDMA0 Triggers - cpuss.dw0_tr_in[27] + TRIGGER_CPUSS_DW0_TR_IN28 = 34, //!< SAR to PDMA1 direct connect - cpuss.dw0_tr_in[28] + TRIGGER_CPUSS_DW1_TR_IN0 = 35, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[0] + TRIGGER_CPUSS_DW1_TR_IN1 = 36, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[1] + TRIGGER_CPUSS_DW1_TR_IN2 = 37, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[2] + TRIGGER_CPUSS_DW1_TR_IN3 = 38, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[3] + TRIGGER_CPUSS_DW1_TR_IN4 = 39, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[4] + TRIGGER_CPUSS_DW1_TR_IN5 = 40, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[5] + TRIGGER_CPUSS_DW1_TR_IN6 = 41, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[6] + TRIGGER_CPUSS_DW1_TR_IN7 = 42, //!< PDMA1 trigger multiplexer - cpuss.dw1_tr_in[7] + TRIGGER_CPUSS_DW1_TR_IN8 = 43, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[8] + TRIGGER_CPUSS_DW1_TR_IN9 = 44, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[9] + TRIGGER_CPUSS_DW1_TR_IN10 = 45, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[10] + TRIGGER_CPUSS_DW1_TR_IN11 = 46, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[11] + TRIGGER_CPUSS_DW1_TR_IN12 = 47, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[12] + TRIGGER_CPUSS_DW1_TR_IN13 = 48, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[13] + TRIGGER_CPUSS_DW1_TR_IN14 = 49, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[14] + TRIGGER_CPUSS_DW1_TR_IN15 = 50, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[15] + TRIGGER_CPUSS_DW1_TR_IN16 = 51, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[16] + TRIGGER_CPUSS_DW1_TR_IN17 = 52, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[17] + TRIGGER_CPUSS_DW1_TR_IN18 = 53, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[18] + TRIGGER_CPUSS_DW1_TR_IN19 = 54, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[19] + TRIGGER_CPUSS_DW1_TR_IN20 = 55, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[20] + TRIGGER_CPUSS_DW1_TR_IN21 = 56, //!< SCB PDMA1 Triggers - cpuss.dw1_tr_in[21] + TRIGGER_CPUSS_DW1_TR_IN22 = 57, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[22] + TRIGGER_CPUSS_DW1_TR_IN23 = 58, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[23] + TRIGGER_CPUSS_DW1_TR_IN24 = 59, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[24] + TRIGGER_CPUSS_DW1_TR_IN25 = 60, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[25] + TRIGGER_CPUSS_DW1_TR_IN26 = 61, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[26] + TRIGGER_CPUSS_DW1_TR_IN27 = 62, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[27] + TRIGGER_CPUSS_DW1_TR_IN28 = 63, //!< SMIF to PDMA1 direct connect - cpuss.dw1_tr_in[28] + TRIGGER_CPUSS_DW1_TR_IN29 = 64, //!< CAN PDMA1 triggers - cpuss.dw1_tr_in[29] + TRIGGER_CPUSS_DW1_TR_IN30 = 65, //!< CAN PDMA1 triggers - cpuss.dw1_tr_in[30] + TRIGGER_CPUSS_DW1_TR_IN31 = 66, //!< CAN PDMA1 triggers - cpuss.dw1_tr_in[31] + TRIGGER_CSD_DSI_START = 67, //!< Capsense trigger multiplexer - csd.dsi_start + TRIGGER_PASS_TR_SAR_IN = 68, //!< ADC trigger multiplexer - pass.tr_sar_in + TRIGGER_PERI_TR_DBG_FREEZE = 69, //!< PERI Freeze trigger multiplexer - peri.tr_dbg_freeze + TRIGGER_PERI_TR_IO_OUTPUT0 = 70, //!< HSIOM trigger multiplexer - peri.tr_io_output[0] + TRIGGER_PERI_TR_IO_OUTPUT1 = 71, //!< HSIOM trigger multiplexer - peri.tr_io_output[1] + TRIGGER_TCPWM0_TR_IN0 = 72, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[0] + TRIGGER_TCPWM0_TR_IN1 = 73, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[1] + TRIGGER_TCPWM0_TR_IN2 = 74, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[2] + TRIGGER_TCPWM0_TR_IN3 = 75, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[3] + TRIGGER_TCPWM0_TR_IN4 = 76, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[4] + TRIGGER_TCPWM0_TR_IN5 = 77, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[5] + TRIGGER_TCPWM0_TR_IN6 = 78, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[6] + TRIGGER_TCPWM0_TR_IN7 = 79, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[7] + TRIGGER_TCPWM0_TR_IN8 = 80, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[8] + TRIGGER_TCPWM0_TR_IN9 = 81, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[9] + TRIGGER_TCPWM0_TR_IN10 = 82, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[10] + TRIGGER_TCPWM0_TR_IN11 = 83, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[11] + TRIGGER_TCPWM0_TR_IN12 = 84, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[12] + TRIGGER_TCPWM0_TR_IN13 = 85, //!< TCPWM0 trigger multiplexer - tcpwm[0].tr_in[13] + TRIGGER_TCPWM1_TR_IN0 = 86, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[0] + TRIGGER_TCPWM1_TR_IN1 = 87, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[1] + TRIGGER_TCPWM1_TR_IN2 = 88, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[2] + TRIGGER_TCPWM1_TR_IN3 = 89, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[3] + TRIGGER_TCPWM1_TR_IN4 = 90, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[4] + TRIGGER_TCPWM1_TR_IN5 = 91, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[5] + TRIGGER_TCPWM1_TR_IN6 = 92, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[6] + TRIGGER_TCPWM1_TR_IN7 = 93, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[7] + TRIGGER_TCPWM1_TR_IN8 = 94, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[8] + TRIGGER_TCPWM1_TR_IN9 = 95, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[9] + TRIGGER_TCPWM1_TR_IN10 = 96, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[10] + TRIGGER_TCPWM1_TR_IN11 = 97, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[11] + TRIGGER_TCPWM1_TR_IN12 = 98, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[12] + TRIGGER_TCPWM1_TR_IN13 = 99, //!< TCPWM1 trigger multiplexer - tcpwm[1].tr_in[13] + TRIGGER_USB_DMA_BURSTEND0 = 100, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[0] + TRIGGER_USB_DMA_BURSTEND1 = 101, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[1] + TRIGGER_USB_DMA_BURSTEND2 = 102, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[2] + TRIGGER_USB_DMA_BURSTEND3 = 103, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[3] + TRIGGER_USB_DMA_BURSTEND4 = 104, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[4] + TRIGGER_USB_DMA_BURSTEND5 = 105, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[5] + TRIGGER_USB_DMA_BURSTEND6 = 106, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[6] + TRIGGER_USB_DMA_BURSTEND7 = 107, //!< USB PDMA0 Acknowledge Triggers - usb.dma_burstend[7] +} cyhal_trigger_dest_psoc6_03_t; + +/** Typedef from device family specific trigger dest to generic trigger dest */ +typedef cyhal_trigger_dest_psoc6_03_t cyhal_dest_t; + +/** \cond INTERNAL */ +/** Maps each cyhal_destination_t to a mux index. + * If bit 8 of the mux index is set, this denotes that the trigger is a + * one to one trigger. + */ +extern const uint8_t cyhal_dest_to_mux[108]; + +/* Maps each cyhal_destination_t to a specific output in its mux */ +extern const uint8_t cyhal_mux_dest_index[108]; +/** \endcond */ + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ +/** \} group_hal_psoc6_triggers_psoc6_03 */ +#endif /* _CYHAL_TRIGGERS_PSOC6_03_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_adc.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_adc.c similarity index 98% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_adc.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_adc.c index 4072f59864d..4a7f8a9a309 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_adc.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_adc.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -185,7 +185,7 @@ cy_rslt_t cyhal_adc_init(cyhal_adc_t *obj, cyhal_gpio_t pin, const cyhal_clock_d cy_rslt_t result = CY_RSLT_SUCCESS; - if (CYHAL_NC_PIN_VALUE == pin) + if (CYHAL_NC_PIN_VALUE == pin) result = CYHAL_ADC_RSLT_BAD_ARGUMENT; if (CY_RSLT_SUCCESS == result) @@ -228,7 +228,7 @@ cy_rslt_t cyhal_adc_init(cyhal_adc_t *obj, cyhal_gpio_t pin, const cyhal_clock_d } if (CY_RSLT_SUCCESS == result) - { + { if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(pclk, obj->clock.div_type, obj->clock.div_num)) result = CYHAL_ADC_RSLT_FAILED_CLOCK; } @@ -355,7 +355,7 @@ void cyhal_adc_channel_free(cyhal_adc_channel_t *obj) Cy_SAR_SetSwitchSarSeqCtrl(obj->adc->base, mux_ctrl, CY_SAR_SWITCH_SEQ_CTRL_DISABLE); obj->adc->base->CHAN_CONFIG[obj->channel_idx] = 0; - cyhal_gpio_free(obj->pin); + cyhal_utils_release_if_used(&(obj->pin)); obj->adc = NULL; } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_analog_common.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_analog_common.c similarity index 96% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_analog_common.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_analog_common.c index 33e55ad7495..55a618fb768 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_analog_common.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_analog_common.c @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_crc.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_crc.c similarity index 97% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_crc.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_crc.c index 867c0056afd..0bcd511961b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_crc.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_crc.c @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_crypto_common.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_crypto_common.c similarity index 98% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_crypto_common.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_crypto_common.c index 2397ba0d8b3..3079c1cc912 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_crypto_common.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_crypto_common.c @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_dac.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dac.c similarity index 96% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_dac.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dac.c index f0805d15eec..4442257fcb3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_dac.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dac.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -148,11 +148,7 @@ void cyhal_dac_free(cyhal_dac_t *obj) cyhal_hwmgr_free(&obj->resource); - if(obj->pin != CYHAL_NC_PIN_VALUE) - { - cyhal_gpio_free(obj->pin); - obj->pin = CYHAL_NC_PIN_VALUE; - } + cyhal_utils_release_if_used(&(obj->pin)); obj->base = NULL; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dma.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dma.c new file mode 100644 index 00000000000..438311d7b4e --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dma.c @@ -0,0 +1,206 @@ +/***************************************************************************//** +* \file cyhal_dma.c +* +* \brief +* Implements a high level interface for interacting with the Cypress DMA. +* This implementation abstracts out the chip specific details. If any chip specific +* functionality is necessary, or performance is critical the low level functions +* can be used directly. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include "cyhal_dma_dmac.h" +#include "cyhal_dma_dw.h" +#include "cyhal_hwmgr.h" +#include "cyhal_system.h" +#include "cyhal_utils.h" + +/** +* \addtogroup group_hal_dma DMA (Direct Memory Access) +* \ingroup group_hal +* \{ +*/ + +#if defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M4CPUSS_DMA) + +#if defined(__cplusplus) +extern "C" { +#endif /* __cplusplus */ + +cy_rslt_t cyhal_dma_init(cyhal_dma_t *obj, uint8_t priority, cyhal_dma_direction_t direction) +{ + CY_ASSERT(NULL != obj); + +#if !defined(CY_IP_M4CPUSS_DMAC) && defined(CY_IP_M4CPUSS_DMA) + /* Only DW available. Ignore direction for purpose of choosing DMA type. */ + CY_UNUSED_PARAMETER(direction); + return cyhal_dma_init_dw(obj, priority); +#elif defined(CY_IP_M4CPUSS_DMAC) && !defined(CY_IP_M4CPUSS_DMA) + /* Only DMAC available. Ignore direction for purpose of choosing DMA type. */ + CY_UNUSED_PARAMETER(direction); + return cyhal_dma_init_dmac(obj, priority); +#else + /* DMAC is designed with high memory bandwidth for memory to memory + * transfers so prefer it when direction is MEM2MEM. Otherwise prefer + * Datawire as it is designed for low latency memory to peripheral or + * peripheral to memory transfers. Note: Both DMA types can handle any + * direction value so using a non-ideal DMA type is ok.*/ + cy_rslt_t rslt; + if(direction == CYHAL_DMA_DIRECTION_MEM2MEM) + { + rslt = cyhal_dma_init_dmac(obj, priority); + /* If no DMAC channels are available fall back on DW. */ + if(CYHAL_HWMGR_RSLT_ERR_NONE_FREE == rslt) + rslt = cyhal_dma_init_dw(obj, priority); + } + else + { + rslt = cyhal_dma_init_dw(obj, priority); + /* If no DW channels are available fall back on DMAC. */ + if(CYHAL_HWMGR_RSLT_ERR_NONE_FREE == rslt) + rslt = cyhal_dma_init_dmac(obj, priority); + } + return rslt; +#endif +} + +void cyhal_dma_free(cyhal_dma_t *obj) +{ + CY_ASSERT(NULL != obj); + + CY_ASSERT(!cyhal_dma_is_busy(obj)); + +#ifdef CY_IP_M4CPUSS_DMAC + if(obj->resource.type == CYHAL_RSC_DMA) + { + cyhal_dma_free_dmac(obj); + } +#endif +#ifdef CY_IP_M4CPUSS_DMA + if(obj->resource.type == CYHAL_RSC_DW) + { + cyhal_dma_free_dw(obj); + } +#endif +} + +cy_rslt_t cyhal_dma_configure(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg) +{ + CY_ASSERT(NULL != obj); + +#ifdef CY_IP_M4CPUSS_DMAC + if(obj->resource.type == CYHAL_RSC_DMA) + { + return cyhal_dma_configure_dmac(obj, cfg); + } +#endif +#ifdef CY_IP_M4CPUSS_DMA + if(obj->resource.type == CYHAL_RSC_DW) + { + return cyhal_dma_configure_dw(obj, cfg); + } +#endif + + /* Control should never reach here but return value anyway to appease + * compilers */ + CY_ASSERT(false); + return CYHAL_DMA_RSLT_FATAL_UNSUPPORTED_HARDWARE; +} + +cy_rslt_t cyhal_dma_start_transfer(cyhal_dma_t *obj) +{ + CY_ASSERT(NULL != obj); + +#ifdef CY_IP_M4CPUSS_DMAC + if(obj->resource.type == CYHAL_RSC_DMA) + { + return cyhal_dma_start_transfer_dmac(obj); + } +#endif +#ifdef CY_IP_M4CPUSS_DMA + if(obj->resource.type == CYHAL_RSC_DW) + { + return cyhal_dma_start_transfer_dw(obj); + } +#endif + + /* Control should never reach here but return value anyway to appease + * compilers */ + CY_ASSERT(false); + return CYHAL_DMA_RSLT_FATAL_UNSUPPORTED_HARDWARE; +} + +bool cyhal_dma_is_busy(cyhal_dma_t *obj) +{ + CY_ASSERT(NULL != obj); + +#ifdef CY_IP_M4CPUSS_DMAC + if(obj->resource.type == CYHAL_RSC_DMA) + { + return cyhal_dma_is_busy_dmac(obj); + } +#endif +#ifdef CY_IP_M4CPUSS_DMA + if(obj->resource.type == CYHAL_RSC_DW) + { + return cyhal_dma_is_busy_dw(obj); + } +#endif + + /* Control should never reach here but return value anyway to appease + * compilers */ + CY_ASSERT(false); + return CYHAL_DMA_RSLT_FATAL_UNSUPPORTED_HARDWARE; +} + +void cyhal_dma_register_callback(cyhal_dma_t *obj, cyhal_dma_event_callback_t callback, void *callback_arg) +{ + CY_ASSERT(NULL != obj); + + uint32_t saved_intr_status = cyhal_system_critical_section_enter(); + obj->callback_data.callback = (cy_israddress)callback; + obj->callback_data.callback_arg = callback_arg; + cyhal_system_critical_section_exit(saved_intr_status); +} + +void cyhal_dma_enable_event(cyhal_dma_t *obj, cyhal_dma_event_t event, uint8_t intrPriority, bool enable) +{ + CY_ASSERT(NULL != obj); + +#ifdef CY_IP_M4CPUSS_DMAC + if(obj->resource.type == CYHAL_RSC_DMA) + { + cyhal_dma_enable_event_dmac(obj, event, intrPriority, enable); + } +#endif +#ifdef CY_IP_M4CPUSS_DMA + if(obj->resource.type == CYHAL_RSC_DW) + { + cyhal_dma_enable_event_dw(obj, event, intrPriority, enable); + } +#endif +} + +#if defined(__cplusplus) +} +#endif /* __cplusplus */ + +#endif /* defined(CY_IP_M4CPUSS_DMAC) || defined(CY_IP_M4CPUSS_DMA) */ + +/** \} group_hal_dma */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dma_dmac.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dma_dmac.c new file mode 100644 index 00000000000..9d4923b3fd7 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dma_dmac.c @@ -0,0 +1,364 @@ +/***************************************************************************//** +* \file cyhal_dma_dmac.c +* +* \brief +* Implements a high level interface for interacting with the Cypress DMAC. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include "cyhal_dma.h" +#include "cyhal_dma_dmac.h" +#include "cyhal_dma_impl.h" +#include "cyhal_hwmgr.h" +#include "cyhal_system.h" +#include "cyhal_utils.h" +#include "cyhal_triggers.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#ifdef CY_IP_M4CPUSS_DMAC + +static cyhal_dma_t* cyhal_dmac_config_structs[CPUSS_DMAC_CH_NR]; + +/** Default dmac descriptor config */ +static const cy_stc_dmac_descriptor_config_t default_descriptor_config_dmac = +{ + .retrigger = CY_DMAC_RETRIG_IM, + .interruptType = CY_DMAC_DESCR, + .triggerOutType = CY_DMAC_DESCR_CHAIN, + .channelState = CY_DMAC_CHANNEL_ENABLED, + .triggerInType = CY_DMAC_DESCR, + .dataPrefetch = false, + .dataSize = CY_DMAC_WORD, + .srcTransferSize = CY_DMAC_TRANSFER_SIZE_DATA, + .dstTransferSize = CY_DMAC_TRANSFER_SIZE_DATA, + .descriptorType = CY_DMAC_1D_TRANSFER, + .srcAddress = 0, + .dstAddress = 0, + .srcXincrement = 1U, + .dstXincrement = 1U, + .xCount = 1UL, + .srcYincrement = 0U, + .dstYincrement = 0U, + .yCount = 1UL, + .nextDescriptor = 0, +}; + +/** Default dmac channel config */ +static const cy_stc_dmac_channel_config_t default_channel_config_dmac = +{ + .descriptor = 0, + .priority = 1, + .enable = false, + .bufferable = false, +}; + +/** Sets the dmac configuration struct */ +static inline void cyhal_dma_set_dmac_obj(cyhal_dma_t *obj) +{ + cyhal_dmac_config_structs[obj->resource.block_num * CPUSS_DMAC_CH_NR + obj->resource.channel_num] = obj; +} + +/** Zeros the dmac configuration struct */ +static inline void cyhal_dma_free_dmac_obj(cyhal_dma_t *obj) +{ + cyhal_dmac_config_structs[obj->resource.block_num * CPUSS_DMAC_CH_NR + obj->resource.channel_num] = NULL; +} + +/** Gets the dmac configuration struct from block and channel */ +static inline cyhal_dma_t* cyhal_dma_get_dmac_obj(uint8_t block, uint8_t channel) +{ + return cyhal_dmac_config_structs[block * CPUSS_DMAC_CH_NR + channel]; +} + +/** Gets the dmac block number from irq number */ +/** This should never be called from a non-dma IRQn */ +static inline uint8_t cyhal_dma_get_dmac_block_from_irqn(IRQn_Type irqn) +{ + /* Since there is only one dmac block this function always returns 0. diff + * is calculated here only to verify that this was called from a valid + * IRQn. */ + CY_UNUSED uint8_t diff = irqn - cpuss_interrupts_dmac_0_IRQn; + + CY_ASSERT(diff < CPUSS_DMAC_CH_NR); + + return 0; +} + +/** Gets the dmac channel number from irq number */ +/** This should never be called from a non-dma IRQn */ +static inline uint8_t cyhal_dma_get_dmac_channel_from_irqn(IRQn_Type irqn) +{ + uint8_t diff = irqn - cpuss_interrupts_dmac_0_IRQn; + + CY_ASSERT(diff < CPUSS_DMAC_CH_NR); + + return diff; +} + +/** Gets the irqn corresponding to a particular cyhal_dma_t config struct */ +static inline IRQn_Type cyhal_dma_get_dmac_irqn(cyhal_dma_t *obj) +{ + return (IRQn_Type)((uint8_t)cpuss_interrupts_dmac_0_IRQn + (obj->resource.block_num * CPUSS_DMAC_CH_NR + obj->resource.channel_num)); +} + +/** Gets the dmac base pointer from block number */ +static inline DMAC_Type* cyhal_dma_get_dmac_base(uint8_t block_num) +{ + return DMAC; +} + +/** Uses tables provided as part of the hal interconnect driver to determine mux + * trigger group and mux trigger index and then construct the trigger line + * input parameter to Cy_TrigMux_SwTrigger. */ +static inline uint32_t cyhal_dma_get_dmac_trigger_line(uint8_t block_num, uint8_t channel_num) +{ + /* cyhal_dest_t triggers are guaranteed to be sorted by trigger type, block + * num, then channel num, therefore, we can just directly find the proper + * trigger by calculating an offset. */ + cyhal_dest_t trigger = (cyhal_dest_t)(TRIGGER_CPUSS_DMAC_TR_IN0 + (block_num * CPUSS_DMAC_CH_NR) + channel_num); + + /* One to one triggers have bit 8 set in cyhal_dest_to_mux but + * Cy_TrigMux_SwTrigger wants the trigger group field to have bit 5 set to + * denote one to one triggers. */ + uint8_t trig_group = cyhal_dest_to_mux[trigger]; + /* If hal one to one triggers bit is set: mask it out and set pdl one to + * one bit */ + if(trig_group & HAL_TRIGGERS_1TO1_MASK) + trig_group = (trig_group & ~HAL_TRIGGERS_1TO1_MASK) | PDL_TRIGGERS_1TO1_MASK; + + /* Construct trigger line which consists of three fields packed into a + * uint32_t: + * Bits 30: Input/output bit. Set to 1 for output. + * Bits 12-8: Trigger group selection. + * Bits 7-0: Select the output trigger number in the trigger group. */ + return PERI_TR_CMD_OUT_SEL_Msk | trig_group << 8 | cyhal_mux_dest_index[trigger]; +} + +/** Convert PDL interrupt cause to hal dma event */ +static inline cyhal_dma_event_t cyhal_dma_convert_dmac_interrupt_cause(uint32_t cause) +{ + switch(cause) + { + case CY_DMAC_INTR_COMPLETION: + return CYHAL_DMA_TRANSFER_COMPLETE; + case CY_DMAC_INTR_SRC_BUS_ERROR: + return CYHAL_DMA_SRC_BUS_ERROR; + case CY_DMAC_INTR_DST_BUS_ERROR: + return CYHAL_DMA_DST_BUS_ERROR; + case CY_DMAC_INTR_SRC_MISAL: + return CYHAL_DMA_SRC_MISAL; + case CY_DMAC_INTR_DST_MISAL: + return CYHAL_DMA_DST_MISAL; + case CY_DMAC_INTR_CURR_PTR_NULL: + return CYHAL_DMA_CURR_PTR_NULL; + case CY_DMAC_INTR_ACTIVE_CH_DISABLED: + return CYHAL_DMA_ACTIVE_CH_DISABLED; + case CY_DMAC_INTR_DESCR_BUS_ERROR: + return CYHAL_DMA_DESCR_BUS_ERROR; + default: + return CYHAL_DMA_NO_INTR; + } +} + +/** DMAC irq handler */ +static void cyhal_dma_irq_handler_dmac(void) +{ + /* Use irqn to get appropriate config structure */ + uint8_t block = cyhal_dma_get_dmac_block_from_irqn(CYHAL_GET_CURRENT_IRQN()); + uint8_t channel = cyhal_dma_get_dmac_channel_from_irqn(CYHAL_GET_CURRENT_IRQN()); + cyhal_dma_t *obj = cyhal_dma_get_dmac_obj(block, channel); + + /* Get interrupt type and call users event callback if they have enabled that event */ + uint32_t cause = Cy_DMAC_Channel_GetInterruptStatusMasked(cyhal_dma_get_dmac_base(block), channel); + cyhal_dma_event_t event_type = cyhal_dma_convert_dmac_interrupt_cause(cause); + uint32_t events_to_callback = event_type && obj->irq_cause; + if(obj->callback_data.callback != NULL && events_to_callback) + { + ((cyhal_dma_event_callback_t)obj->callback_data.callback)(obj->callback_data.callback_arg, (cyhal_dma_event_t)events_to_callback); + } + + /* Clear all interrupts */ + Cy_DMAC_Channel_ClearInterrupt(cyhal_dma_get_dmac_base(block), channel, CY_DMAC_INTR_MASK); +} + +cy_rslt_t cyhal_dma_init_dmac(cyhal_dma_t *obj, uint8_t priority) +{ + if(!CY_DMAC_IS_PRIORITY_VALID(priority)) + return CYHAL_DMA_RSLT_ERR_INVALID_PRIORITY; + + cy_rslt_t rslt = cyhal_hwmgr_allocate(CYHAL_RSC_DMA, &obj->resource); + if(rslt != CY_RSLT_SUCCESS) + return rslt; + + /* Setup descriptor and channel configs */ + obj->descriptor_config.dmac = default_descriptor_config_dmac; + obj->channel_config.dmac = default_channel_config_dmac; + obj->channel_config.dmac.descriptor = &obj->descriptor.dmac; + obj->channel_config.dmac.priority = priority; + + obj->callback_data.callback = NULL; + obj->callback_data.callback_arg = NULL; + obj->irq_cause = 0; + + cyhal_dma_set_dmac_obj(obj); + + return CY_RSLT_SUCCESS; +} + +void cyhal_dma_free_dmac(cyhal_dma_t *obj) +{ + Cy_DMAC_Descriptor_DeInit(&obj->descriptor.dmac); + Cy_DMAC_Channel_DeInit(cyhal_dma_get_dmac_base(obj->resource.block_num), obj->resource.channel_num); + + NVIC_DisableIRQ(cyhal_dma_get_dmac_irqn(obj)); + + cyhal_dma_free_dmac_obj(obj); + cyhal_hwmgr_free(&obj->resource); +} + +/* Initalize descriptor, initialize channel, enable channel, enable channel + * interrupt, and enable DMAC controller */ +cy_rslt_t cyhal_dma_configure_dmac(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg) +{ + /* Do not reconfigure if transfer is pending/active already */ + if(cyhal_dma_is_busy_dmac(obj)) + return CYHAL_DMA_RSLT_ERR_CHANNEL_BUSY; + + obj->descriptor_config.dmac.srcAddress = (void*)cfg->src_addr; + obj->descriptor_config.dmac.dstAddress = (void*)cfg->dst_addr; + obj->descriptor_config.dmac.nextDescriptor = &obj->descriptor.dmac; + + if(cfg->transfer_width == 8) + obj->descriptor_config.dmac.dataSize = CY_DMAC_BYTE; + else if(cfg->transfer_width == 16) + obj->descriptor_config.dmac.dataSize = CY_DMAC_HALFWORD; + else if(cfg->transfer_width == 32) + obj->descriptor_config.dmac.dataSize = CY_DMAC_WORD; + else + return CYHAL_DMA_RSLT_ERR_INVALID_TRANSFER_WIDTH; + + /* Length must be a multiple of burst_size */ + if(cfg->burst_size != 0 && cfg->length % cfg->burst_size != 0) + return CYHAL_DMA_RSLT_ERR_INVALID_BURST_SIZE; + + /* Setup 2D transfer if burst_size is being used otherwise set up 1D + * transfer */ + if(cfg->burst_size != 0) + { + obj->descriptor_config.dmac.descriptorType = CY_DMAC_2D_TRANSFER; + obj->descriptor_config.dmac.xCount = cfg->burst_size; + obj->descriptor_config.dmac.yCount = cfg->length / cfg->burst_size; + obj->descriptor_config.dmac.srcXincrement = cfg->src_increment; + obj->descriptor_config.dmac.dstXincrement = cfg->dst_increment; + obj->descriptor_config.dmac.srcYincrement = cfg->src_increment * cfg->burst_size; + obj->descriptor_config.dmac.dstYincrement = cfg->dst_increment * cfg->burst_size; + + /* If burst action, configure trigger and interrupt actions */ + if(cfg->action == CYHAL_DMA_TRANSFER_BURST) + { + obj->descriptor_config.dmac.interruptType = CY_DMAC_X_LOOP; + obj->descriptor_config.dmac.triggerInType = CY_DMAC_X_LOOP; + } + } + else + { + obj->descriptor_config.dmac.descriptorType = CY_DMAC_1D_TRANSFER; + obj->descriptor_config.dmac.xCount = cfg->length; + obj->descriptor_config.dmac.srcXincrement = cfg->src_increment; + obj->descriptor_config.dmac.dstXincrement = cfg->dst_increment; + + obj->descriptor_config.dmac.interruptType = CY_DMAC_DESCR; + obj->descriptor_config.dmac.triggerInType = CY_DMAC_DESCR; + } + + if(CY_DMAC_SUCCESS != Cy_DMAC_Descriptor_Init(&obj->descriptor.dmac, &obj->descriptor_config.dmac)) + return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER; + + /* Setup channel and enable */ + DMAC_Type* base = cyhal_dma_get_dmac_base(obj->resource.block_num); + if(CY_DMAC_SUCCESS != Cy_DMAC_Channel_Init(base, obj->resource.channel_num, &obj->channel_config.dmac)) + return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER; + Cy_DMAC_Channel_SetDescriptor(base, obj->resource.channel_num, &obj->descriptor.dmac); + Cy_DMAC_Channel_SetPriority(base, obj->resource.channel_num, obj->channel_config.dmac.priority); + Cy_DMAC_Channel_Enable(base, obj->resource.channel_num); + Cy_DMAC_Channel_SetInterruptMask (base, obj->resource.channel_num, CY_DMAC_INTR_MASK); + + Cy_DMAC_Enable(base); + + /* src_misal and dst_misal interrupts are triggered immediately on enable + * so return those errors here */ + uint32_t status = Cy_DMAC_Channel_GetInterruptStatus(base, obj->resource.channel_num); + if((status & CY_DMAC_INTR_SRC_MISAL) || + (status & CY_DMAC_INTR_DST_MISAL)) + { + /* Clear all interrupts and return error */ + Cy_DMAC_Channel_ClearInterrupt(base, obj->resource.channel_num, CY_DMAC_INTR_MASK); + return CYHAL_DMA_RSLT_ERR_INVALID_ALIGNMENT; + } + + /* Enable interrupt for this channel */ + cy_stc_sysint_t irqCfg = { cyhal_dma_get_dmac_irqn(obj), CYHAL_ISR_PRIORITY_DEFAULT }; + if(CY_SYSINT_SUCCESS != Cy_SysInt_Init(&irqCfg, cyhal_dma_irq_handler_dmac)) + return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER; + NVIC_EnableIRQ(irqCfg.intrSrc); + + return CY_RSLT_SUCCESS; +} + +cy_rslt_t cyhal_dma_start_transfer_dmac(cyhal_dma_t *obj) +{ + /* Return warning if channel is busy */ + if(cyhal_dma_is_busy_dmac(obj)) + return CYHAL_DMA_RSLT_WARN_TRANSFER_ALREADY_STARTED; + + uint32_t trigline = cyhal_dma_get_dmac_trigger_line(obj->resource.block_num, obj->resource.channel_num); + cy_en_trigmux_status_t trig_status = Cy_TrigMux_SwTrigger(trigline, CY_TRIGGER_TWO_CYCLES); + + /* Also return warning if SW trigger is already initated but DMA hardware + * has not seen it yet */ + if(trig_status == CY_TRIGMUX_INVALID_STATE) + return CYHAL_DMA_RSLT_WARN_TRANSFER_ALREADY_STARTED; + else + return CY_RSLT_SUCCESS; +} + +void cyhal_dma_enable_event_dmac(cyhal_dma_t *obj, cyhal_dma_event_t event, uint8_t intrPriority, bool enable) +{ + if(enable) + obj->irq_cause |= event; + else + obj->irq_cause &= ~event; + + NVIC_SetPriority(cyhal_dma_get_dmac_irqn(obj), intrPriority); +} + +bool cyhal_dma_is_busy_dmac(cyhal_dma_t *obj) +{ + /* The ACTIVE register is a bit field of all pending or active channels */ + return cyhal_dma_get_dmac_base(obj->resource.block_num)->ACTIVE & (1 << obj->resource.channel_num); +} + +#endif /* CY_IP_M4CPUSS_DMAC */ + +#if defined(__cplusplus) +} +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dma_dw.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dma_dw.c new file mode 100644 index 00000000000..694ef842eb0 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_dma_dw.c @@ -0,0 +1,402 @@ +/***************************************************************************//** +* \file cyhal_dma_dw.c +* +* \brief +* Implements a high level interface for interacting with the Cypress Datawire DMA. +* +******************************************************************************** +* \copyright +* Copyright 2018-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include "cyhal_dma.h" +#include "cyhal_dma_dw.h" +#include "cyhal_dma_impl.h" +#include "cyhal_hwmgr.h" +#include "cyhal_system.h" +#include "cyhal_utils.h" +#include "cyhal_triggers.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#ifdef CY_IP_M4CPUSS_DMA + +#if (CPUSS_DW0_PRESENT==1) && (CPUSS_DW1_PRESENT==1) +#define NUM_DW_CHANNELS (CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR) +#elif (CPUSS_DW0_PRESENT==1) +#define NUM_DW_CHANNELS (CPUSS_DW0_CH_NR) +#endif + +static cyhal_dma_t* cyhal_dw_config_structs[NUM_DW_CHANNELS]; + +/** Default dw descriptor config */ +static const cy_stc_dma_descriptor_config_t default_descriptor_config_dw = +{ + .retrigger = CY_DMA_RETRIG_IM, + .interruptType = CY_DMA_DESCR, + .triggerOutType = CY_DMA_DESCR_CHAIN, + .channelState = CY_DMA_CHANNEL_ENABLED, + .triggerInType = CY_DMA_DESCR, + .dataSize = CY_DMA_WORD, + .srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA, + .descriptorType = CY_DMA_1D_TRANSFER, + .srcAddress = 0, + .dstAddress = 0, + .srcXincrement = 1U, + .dstXincrement = 1U, + .xCount = 1UL, + .srcYincrement = 0U, + .dstYincrement = 0U, + .yCount = 1UL, + .nextDescriptor = 0, +}; + +/** Default dw channel config */ +static const cy_stc_dma_channel_config_t default_channel_config_dw = +{ + .descriptor = 0, + .preemptable = false, + .priority = 1, + .enable = false, + .bufferable = false, +}; + +/** Sets the dw configuration struct */ +static inline void cyhal_dma_set_dw_obj(cyhal_dma_t *obj) +{ + cyhal_dw_config_structs[obj->resource.block_num * CPUSS_DW0_CH_NR + obj->resource.channel_num] = obj; +} + +/** Zeros the dw configuration struct */ +static inline void cyhal_dma_free_dw_obj(cyhal_dma_t *obj) +{ + cyhal_dw_config_structs[obj->resource.block_num * CPUSS_DW0_CH_NR + obj->resource.channel_num] = NULL; +} + +/** Gets the dw configuration struct from block and channel */ +static inline cyhal_dma_t* cyhal_dma_get_dw_obj(uint8_t block, uint8_t channel) +{ + return cyhal_dw_config_structs[block * CPUSS_DW0_CH_NR + channel]; +} + +/** Gets the dw block number from irq number */ +/** This should never be called from a non-dma IRQn */ +static inline uint8_t cyhal_dma_get_dw_block_from_irqn(IRQn_Type irqn) +{ + uint8_t diff = irqn - cpuss_interrupts_dw0_0_IRQn; +#if defined(CPUSS_DW0_CH_NR) && !defined(CPUSS_DW1_CH_NR) + CY_ASSERT(diff < CPUSS_DW0_CH_NR); + + if(diff < CPUSS_DW0_CH_NR) + return 0; +#elif defined(CPUSS_DW0_CH_NR) && defined(CPUSS_DW1_CH_NR) + CY_ASSERT(diff < CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR); + + if(diff < CPUSS_DW0_CH_NR) + return 0; + if(diff < CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR) + return 1; +#endif + + // Should never reach here. Just silencing compiler warnings. + CY_ASSERT(false); + return 255; +} + +/** Gets the dw channel number from irq number */ +/** This should never be called from a non-dma IRQn */ +static inline uint8_t cyhal_dma_get_dw_channel_from_irqn(IRQn_Type irqn) +{ + uint8_t diff = irqn - cpuss_interrupts_dw0_0_IRQn; +#if defined(CPUSS_DW0_CH_NR) && !defined(CPUSS_DW1_CH_NR) + CY_ASSERT(diff < CPUSS_DW0_CH_NR); + + if(diff < CPUSS_DW0_CH_NR) + return diff; +#elif defined(CPUSS_DW0_CH_NR) && defined(CPUSS_DW1_CH_NR) + CY_ASSERT(diff < CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR); + + if(diff < CPUSS_DW0_CH_NR) + return diff; + else + return diff - CPUSS_DW0_CH_NR; +#endif +} + +/** Gets the irqn corresponding to a particular cyhal_dma_t config struct */ +static inline IRQn_Type cyhal_dma_get_dw_irqn(cyhal_dma_t *obj) +{ + return (IRQn_Type)((uint8_t)cpuss_interrupts_dw0_0_IRQn + (obj->resource.block_num * CPUSS_DW0_CH_NR + obj->resource.channel_num)); +} + +/** Gets the dw base pointer from block number */ +static inline DW_Type* cyhal_dma_get_dw_base(uint8_t block_num) +{ + return block_num == 0 ? DW0 : DW1; +} + +/** Uses tables provided as part of the hal interconnect driver to determine mux + * trigger group and mux trigger index and then construct the trigger line + * input parameter to Cy_TrigMux_SwTrigger. */ +static inline uint32_t cyhal_dma_get_dw_trigger_line(uint8_t block_num, uint8_t channel_num) +{ + /* cyhal_dest_t triggers are guaranteed to be sorted by trigger type, block + * num, then channel num, therefore, we can just directly find the proper + * trigger by calculating an offset. */ + cyhal_dest_t trigger = (cyhal_dest_t)(TRIGGER_CPUSS_DW0_TR_IN0 + (block_num * CPUSS_DW0_CH_NR) + channel_num); + + /* One to one triggers have bit 8 set in cyhal_dest_to_mux but + * Cy_TrigMux_SwTrigger wants the trigger group field to have bit 5 set to + * denote one to one triggers. */ + uint8_t trig_group = cyhal_dest_to_mux[trigger]; + /* If hal one to one triggers bit is set: mask it out and set pdl one to + * one bit */ + if(trig_group & HAL_TRIGGERS_1TO1_MASK) + trig_group = (trig_group & ~HAL_TRIGGERS_1TO1_MASK) | PDL_TRIGGERS_1TO1_MASK; + + /* Construct trigger line which consists of three fields packed into a + * uint32_t: + * Bits 30: Input/output bit. Set to 1 for output. + * Bits 12-8: Trigger group selection. + * Bits 7-0: Select the output trigger number in the trigger group. */ + return PERI_TR_CMD_OUT_SEL_Msk | trig_group << 8 | cyhal_mux_dest_index[trigger]; +} + +/** Convert PDL interrupt cause to hal dma event */ +static inline cyhal_dma_event_t cyhal_dma_convert_dw_interrupt_cause(cy_en_dma_intr_cause_t cause) +{ + switch(cause) + { + case CY_DMA_INTR_CAUSE_NO_INTR: + return CYHAL_DMA_NO_INTR; + case CY_DMA_INTR_CAUSE_COMPLETION: + return CYHAL_DMA_TRANSFER_COMPLETE; + case CY_DMA_INTR_CAUSE_SRC_BUS_ERROR: + return CYHAL_DMA_SRC_BUS_ERROR; + case CY_DMA_INTR_CAUSE_DST_BUS_ERROR: + return CYHAL_DMA_DST_BUS_ERROR; + case CY_DMA_INTR_CAUSE_SRC_MISAL: + return CYHAL_DMA_SRC_MISAL; + case CY_DMA_INTR_CAUSE_DST_MISAL: + return CYHAL_DMA_DST_MISAL; + case CY_DMA_INTR_CAUSE_CURR_PTR_NULL: + return CYHAL_DMA_CURR_PTR_NULL; + case CY_DMA_INTR_CAUSE_ACTIVE_CH_DISABLED: + return CYHAL_DMA_ACTIVE_CH_DISABLED; + case CY_DMA_INTR_CAUSE_DESCR_BUS_ERROR: + return CYHAL_DMA_DESCR_BUS_ERROR; + default: + return CYHAL_DMA_NO_INTR; + } +} + +/** DW irq handler */ +static void cyhal_dma_irq_handler_dw(void) +{ + /* Use irqn to get appropriate config structure */ + uint8_t block = cyhal_dma_get_dw_block_from_irqn(CYHAL_GET_CURRENT_IRQN()); + uint8_t channel = cyhal_dma_get_dw_channel_from_irqn(CYHAL_GET_CURRENT_IRQN()); + cyhal_dma_t *obj = cyhal_dma_get_dw_obj(block, channel); + + /* Get interrupt type and call users event callback if they have enabled that event */ + cy_en_dma_intr_cause_t cause = Cy_DMA_Channel_GetStatus(cyhal_dma_get_dw_base(block), channel); + cyhal_dma_event_t event_type = cyhal_dma_convert_dw_interrupt_cause(cause); + uint32_t events_to_callback = event_type && obj->irq_cause; + if(obj->callback_data.callback != NULL && events_to_callback) + { + ((cyhal_dma_event_callback_t)obj->callback_data.callback)(obj->callback_data.callback_arg, (cyhal_dma_event_t)events_to_callback); + } + + /* Clear all interrupts */ + Cy_DMA_Channel_ClearInterrupt(cyhal_dma_get_dw_base(block), channel); +} + +cy_rslt_t cyhal_dma_init_dw(cyhal_dma_t *obj, uint8_t priority) +{ + if(!CY_DMA_IS_PRIORITY_VALID(priority)) + return CYHAL_DMA_RSLT_ERR_INVALID_PRIORITY; + + cy_rslt_t rslt = cyhal_hwmgr_allocate(CYHAL_RSC_DW, &obj->resource); + if(rslt != CY_RSLT_SUCCESS) + return rslt; + + /* Setup descriptor and channel configs */ + obj->descriptor_config.dw = default_descriptor_config_dw; + obj->channel_config.dw = default_channel_config_dw; + obj->channel_config.dw.descriptor = &obj->descriptor.dw; + obj->channel_config.dw.priority = priority; + + obj->callback_data.callback = NULL; + obj->callback_data.callback_arg = NULL; + obj->irq_cause = 0; + + cyhal_dma_set_dw_obj(obj); + + return CY_RSLT_SUCCESS; +} + +void cyhal_dma_free_dw(cyhal_dma_t *obj) +{ + Cy_DMA_Descriptor_DeInit(&obj->descriptor.dw); + Cy_DMA_Channel_DeInit(cyhal_dma_get_dw_base(obj->resource.block_num), obj->resource.channel_num); + + NVIC_DisableIRQ(cyhal_dma_get_dw_irqn(obj)); + + cyhal_dma_free_dw_obj(obj); + cyhal_hwmgr_free(&obj->resource); +} + +/* Initalize descriptor, initialize channel, enable channel, enable channel + * interrupt, and enable DW controller */ +cy_rslt_t cyhal_dma_configure_dw(cyhal_dma_t *obj, const cyhal_dma_cfg_t *cfg) +{ + /* Do not reconfigure if transfer is pending/active already */ + if(cyhal_dma_is_busy_dw(obj)) + return CYHAL_DMA_RSLT_ERR_CHANNEL_BUSY; + + obj->descriptor_config.dw.srcAddress = (void*)cfg->src_addr; + obj->descriptor_config.dw.dstAddress = (void*)cfg->dst_addr; + obj->descriptor_config.dw.nextDescriptor = &obj->descriptor.dw; + + if(cfg->transfer_width == 8) + obj->descriptor_config.dw.dataSize = CY_DMA_BYTE; + else if(cfg->transfer_width == 16) + obj->descriptor_config.dw.dataSize = CY_DMA_HALFWORD; + else if(cfg->transfer_width == 32) + obj->descriptor_config.dw.dataSize = CY_DMA_WORD; + else + return CYHAL_DMA_RSLT_ERR_INVALID_TRANSFER_WIDTH; + + /* Length must be a multiple of burst_size */ + if(cfg->burst_size != 0 && cfg->length % cfg->burst_size != 0) + return CYHAL_DMA_RSLT_ERR_INVALID_BURST_SIZE; + + /* Setup 2D transfer if burst_size is being used otherwise set up 1D + * transfer */ + if(cfg->burst_size != 0) + { + obj->descriptor_config.dw.descriptorType = CY_DMA_2D_TRANSFER; + obj->descriptor_config.dw.xCount = cfg->burst_size; + obj->descriptor_config.dw.yCount = cfg->length / cfg->burst_size; + obj->descriptor_config.dw.srcXincrement = cfg->src_increment; + obj->descriptor_config.dw.dstXincrement = cfg->dst_increment; + obj->descriptor_config.dw.srcYincrement = cfg->src_increment * cfg->burst_size; + obj->descriptor_config.dw.dstYincrement = cfg->dst_increment * cfg->burst_size; + + /* If burst action, configure trigger and interrupt actions */ + if(cfg->action == CYHAL_DMA_TRANSFER_BURST) + { + obj->descriptor_config.dw.interruptType = CY_DMA_X_LOOP; + obj->descriptor_config.dw.triggerInType = CY_DMA_X_LOOP; + } + } + else + { + obj->descriptor_config.dw.descriptorType = CY_DMA_1D_TRANSFER; + obj->descriptor_config.dw.xCount = cfg->length; + obj->descriptor_config.dw.srcXincrement = cfg->src_increment; + obj->descriptor_config.dw.dstXincrement = cfg->dst_increment; + + obj->descriptor_config.dw.interruptType = CY_DMA_DESCR; + obj->descriptor_config.dw.triggerInType = CY_DMA_DESCR; + } + + if(CY_DMA_SUCCESS != Cy_DMA_Descriptor_Init(&obj->descriptor.dw, &obj->descriptor_config.dw)) + return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER; + + /* Setup channel and enable */ + DW_Type* base = cyhal_dma_get_dw_base(obj->resource.block_num); + if(CY_DMA_SUCCESS != Cy_DMA_Channel_Init(base, obj->resource.channel_num, &obj->channel_config.dw)) + return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER; + Cy_DMA_Channel_SetDescriptor(base, obj->resource.channel_num, &obj->descriptor.dw); + Cy_DMA_Channel_SetPriority(base, obj->resource.channel_num, obj->channel_config.dw.priority); + Cy_DMA_Channel_Enable(base, obj->resource.channel_num); + Cy_DMA_Channel_SetInterruptMask (base, obj->resource.channel_num, CY_DMA_INTR_MASK); + + Cy_DMA_Enable(base); + + /* src_misal and dst_misal interrupts are triggered immediately on enable + * so return those errors here */ + uint32_t status = Cy_DMA_Channel_GetInterruptStatus(base, obj->resource.channel_num); + if((status & CY_DMA_INTR_CAUSE_SRC_MISAL) || + (status & CY_DMA_INTR_CAUSE_DST_MISAL)) + { + Cy_DMA_Channel_ClearInterrupt(base, obj->resource.channel_num); + return CYHAL_DMA_RSLT_ERR_INVALID_ALIGNMENT; + } + + /* Enable interrupt for this channel */ + cy_stc_sysint_t irqCfg = { cyhal_dma_get_dw_irqn(obj), CYHAL_ISR_PRIORITY_DEFAULT }; + if(CY_SYSINT_SUCCESS != Cy_SysInt_Init(&irqCfg, cyhal_dma_irq_handler_dw)) + return CYHAL_DMA_RSLT_ERR_INVALID_PARAMETER; + NVIC_EnableIRQ(irqCfg.intrSrc); + + return CY_RSLT_SUCCESS; +} + +cy_rslt_t cyhal_dma_start_transfer_dw(cyhal_dma_t *obj) +{ + /* Return warning if channel is busy */ + if(cyhal_dma_is_busy_dw(obj)) + return CYHAL_DMA_RSLT_WARN_TRANSFER_ALREADY_STARTED; + + uint32_t trigline = cyhal_dma_get_dw_trigger_line(obj->resource.block_num, obj->resource.channel_num); + cy_en_trigmux_status_t trig_status = Cy_TrigMux_SwTrigger(trigline, CY_TRIGGER_TWO_CYCLES); + + /* Also return warning if SW trigger is already initated but DMA hardware + * has not seen it yet */ + if(trig_status == CY_TRIGMUX_INVALID_STATE) + return CYHAL_DMA_RSLT_WARN_TRANSFER_ALREADY_STARTED; + else + return CY_RSLT_SUCCESS; +} + +void cyhal_dma_enable_event_dw(cyhal_dma_t *obj, cyhal_dma_event_t event, uint8_t intrPriority, bool enable) +{ + if(enable) + obj->irq_cause |= event; + else + obj->irq_cause &= ~event; + + NVIC_SetPriority(cyhal_dma_get_dw_irqn(obj), intrPriority); +} + +bool cyhal_dma_is_busy_dw(cyhal_dma_t *obj) +{ +#if CY_IP_M4CPUSS_DMA_VERSION == 1 + /* In DW_V1 the pending channel information is stored in the PENDING + * register of the DW block and is a bit field of all pending or active + * channels */ + return cyhal_dma_get_dw_base(obj->resource.block_num)->PENDING & (1 << obj->resource.channel_num); +#elif CY_IP_M4CPUSS_DMA_VERSION == 2 + /* In DW_V2 the pending channel information is stored in the STATUS + * register of the channel itself */ + return DW_CH_STATUS(cyhal_dma_get_dw_base(obj->resource.block_num), obj->resource.channel_num) & (1UL << DW_CH_STRUCT_V2_CH_STATUS_PENDING_Pos); +#else + // Should never reach here. Just silencing compiler warnings. + CY_ASSERT(false); + return false; +#endif +} + +#endif /* CY_IP_M4CPUSS_DMA */ + +#if defined(__cplusplus) +} +#endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_ezi2c.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_ezi2c.c new file mode 100644 index 00000000000..278e5e5b0de --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_ezi2c.c @@ -0,0 +1,289 @@ +/******************************************************************************* +* File Name: cyhal_ezi2c.c +* +* Description: +* Provides a high level interface for interacting with the Cypress I2C. This is +* a wrapper around the lower level PDL API. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include +#include "cyhal_ezi2c.h" +#include "cyhal_scb_common.h" +#include "cyhal_gpio.h" +#include "cyhal_interconnect.h" +#include "cyhal_system_impl.h" +#include "cyhal_hwmgr.h" + +#ifdef CY_IP_MXSCB + +#if defined(__cplusplus) +extern "C" +{ +#endif + +/* Peripheral clock values for different EZI2C speeds according PDL API Reference Guide */ +#define SCB_PERI_CLOCK_SLAVE_STD 8000000 +#define SCB_PERI_CLOCK_SLAVE_FST 12500000 +#define SCB_PERI_CLOCK_SLAVE_FSTP 50000000 +#define SCB_PERI_CLOCK_MASTER_STD 2000000 +#define SCB_PERI_CLOCK_MASTER_FST 8500000 +#define SCB_PERI_CLOCK_MASTER_FSTP 20000000 + +/* Implement ISR for EZI2C */ +static void cyhal_ezi2c_irq_handler(void) +{ + cyhal_ezi2c_t *obj = (cyhal_ezi2c_t*) cyhal_scb_get_irq_obj(); + Cy_SCB_EZI2C_Interrupt(obj->base, &(obj->context)); + + /* Call if registered callback here */ + cyhal_ezi2c_event_callback_t callback = (cyhal_ezi2c_event_callback_t) obj->callback_data.callback; + if (callback != NULL) + { + callback(obj->callback_data.callback_arg, CYHAL_EZI2C_EVENT_NONE); + } +} + +static uint32_t cyhal_set_peri_divider(cyhal_ezi2c_t *obj, uint32_t freq) +{ + /* Return the actual data rate on success, 0 otherwise */ + uint32_t peri_freq = 0; + if (freq == 0) + { + return 0; + } + if (freq <= CY_SCB_I2C_STD_DATA_RATE) + { + peri_freq = SCB_PERI_CLOCK_SLAVE_STD; + } + else if (freq <= CY_SCB_I2C_FST_DATA_RATE) + { + peri_freq = SCB_PERI_CLOCK_SLAVE_FST; + } + else if (freq <= CY_SCB_I2C_FSTP_DATA_RATE) + { + peri_freq = SCB_PERI_CLOCK_SLAVE_FSTP; + } + else + { + return 0; + } + + /* Connect assigned divider to be a clock source for EZI2C */ + cy_en_sysclk_status_t status = Cy_SysClk_PeriphAssignDivider((en_clk_dst_t)((uint8_t)PCLK_SCB0_CLOCK + obj->resource.block_num), obj->clock.div_type, obj->clock.div_num); + if (status == CY_SYSCLK_SUCCESS) + status = Cy_SysClk_PeriphDisableDivider(obj->clock.div_type, obj->clock.div_num); + if (status == CY_SYSCLK_SUCCESS) + status = Cy_SysClk_PeriphSetDivider (obj->clock.div_type, obj->clock.div_num, cyhal_divider_value(peri_freq, 0u)); + if (status == CY_SYSCLK_SUCCESS) + status = Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num); + CY_ASSERT(CY_SYSCLK_SUCCESS == status); + + return Cy_SCB_I2C_SetDataRate(obj->base, freq, Cy_SysClk_PeriphGetFrequency(obj->clock.div_type, obj->clock.div_num)); +} + +cy_rslt_t cyhal_ezi2c_init(cyhal_ezi2c_t *obj, cyhal_gpio_t sda, cyhal_gpio_t scl, const cyhal_clock_divider_t *clk, const cyhal_ezi2c_cfg_t *cfg) +{ + /* Validate input configuration structure */ + if ((0 == cfg->slave1_cfg.slave_address) || ((cfg->two_addresses) && (0 == cfg->slave2_cfg.slave_address))) + { + return CYHAL_EZI2C_RSLT_ERR_CHECK_USER_CONFIG; + } + + CY_ASSERT(NULL != obj); + + /* Populate configuration structure */ + const cy_stc_scb_ezi2c_config_t ezI2cConfig = + { + .numberOfAddresses = cfg->two_addresses ? CY_SCB_EZI2C_TWO_ADDRESSES : CY_SCB_EZI2C_ONE_ADDRESS, + .slaveAddress1 = cfg->slave1_cfg.slave_address, + .slaveAddress2 = cfg->slave2_cfg.slave_address, + .subAddressSize = (cy_en_scb_ezi2c_sub_addr_size_t)cfg->sub_address_size, + .enableWakeFromSleep = cfg->enable_wake_from_sleep, + }; + + /* Explicitly marked not allocated resources as invalid to prevent freeing them. */ + obj->resource.type = CYHAL_RSC_INVALID; + obj->pin_scl = CYHAL_NC_PIN_VALUE; + obj->pin_sda = CYHAL_NC_PIN_VALUE; + obj->is_shared_clock = true; + + cy_rslt_t result; + + /* Reserve the I2C */ + const cyhal_resource_pin_mapping_t *sda_map = CY_UTILS_GET_RESOURCE(sda, cyhal_pin_map_scb_i2c_sda); + const cyhal_resource_pin_mapping_t *scl_map = CY_UTILS_GET_RESOURCE(scl, cyhal_pin_map_scb_i2c_scl); + if ((NULL == sda_map) || (NULL == scl_map) || (sda_map->inst->block_num != scl_map->inst->block_num)) + { + return CYHAL_EZI2C_RSLT_ERR_INVALID_PIN; + } + + result = cyhal_hwmgr_reserve(scl_map->inst); + + /* Reserve the SDA pin */ + if (result == CY_RSLT_SUCCESS) + { + cyhal_resource_inst_t pin_rsc = cyhal_utils_get_gpio_resource(sda); + result = cyhal_hwmgr_reserve(&pin_rsc); + if (result == CY_RSLT_SUCCESS) + { + obj->pin_sda = sda; + /* Configures the HSIOM connection to the pin */ + Cy_GPIO_SetHSIOM(CYHAL_GET_PORTADDR(sda), CYHAL_GET_PIN(sda), CY_GPIO_CFG_GET_HSIOM(scl_map->cfg)); + /* Configures the pin output buffer drive mode and input buffer enable */ + Cy_GPIO_SetDrivemode(CYHAL_GET_PORTADDR(sda), CYHAL_GET_PIN(sda), CY_GPIO_DM_OD_DRIVESLOW); + } + } + + /* Reserve the SCL pin */ + if (result == CY_RSLT_SUCCESS) + { + cyhal_resource_inst_t pin_rsc = cyhal_utils_get_gpio_resource(scl); + /* Connect SCB I2C function to pins */ + cy_rslt_t result = cyhal_hwmgr_reserve(&pin_rsc); + if (result == CY_RSLT_SUCCESS) + { + obj->pin_scl = scl; + /* Configures the HSIOM connection to the pin */ + Cy_GPIO_SetHSIOM(CYHAL_GET_PORTADDR(scl), CYHAL_GET_PIN(scl), CY_GPIO_CFG_GET_HSIOM(scl_map->cfg)); + /* Configures the pin output buffer drive mode and input buffer enable */ + Cy_GPIO_SetDrivemode(CYHAL_GET_PORTADDR(scl), CYHAL_GET_PIN(scl), CY_GPIO_DM_OD_DRIVESLOW); + } + } + + if (result == CY_RSLT_SUCCESS) + { + obj->is_shared_clock = (clk != NULL); + if (clk == NULL) + { + result = cyhal_hwmgr_allocate_clock(&(obj->clock), CY_SYSCLK_DIV_16_BIT, false); + } + else + { + obj->clock = *clk; + } + } + + obj->resource = *(scl_map->inst); + obj->base = CYHAL_SCB_BASE_ADDRESSES[obj->resource.block_num]; + + if (result == CY_RSLT_SUCCESS) + { + /* Configure I2C to operate */ + result = Cy_SCB_EZI2C_Init(obj->base, &ezI2cConfig, &(obj->context)); + } + + int32_t ezi2c_freq; + switch(cfg->data_rate) + { + case CYHAL_EZI2C_DATA_RATE_100KHZ: + ezi2c_freq = 100000; + break; + case CYHAL_EZI2C_DATA_RATE_400KHZ: + ezi2c_freq = 400000; + break; + case CYHAL_EZI2C_DATA_RATE_1MHZ: + ezi2c_freq = 1000000; + break; + default: + return CYHAL_EZI2C_RSLT_ERR_CHECK_USER_CONFIG; + } + + /* Set data rate */ + int32_t dataRate = cyhal_set_peri_divider(obj, ezi2c_freq); + if (dataRate == 0) + { + /* Can not reach desired data rate */ + return CYHAL_EZI2C_RSLT_ERR_CAN_NOT_REACH_DR; + } + + if (result == CY_RSLT_SUCCESS) + { + /* Configure buffer for communication with master */ + Cy_SCB_EZI2C_SetBuffer1(obj->base, cfg->slave1_cfg.buf, cfg->slave1_cfg.buf_size, cfg->slave1_cfg.buf_rw_boundary, &(obj->context)); + /* Check if user set one or two addresses */ + if(cfg->two_addresses) + { + Cy_SCB_EZI2C_SetBuffer2(obj->base, cfg->slave2_cfg.buf, cfg->slave2_cfg.buf_size, cfg->slave2_cfg.buf_rw_boundary, &(obj->context)); + } + } + + if (result == CY_RSLT_SUCCESS) + { + obj->callback_data.callback = NULL; + obj->callback_data.callback_arg = NULL; + obj->irq_cause = 0; + cyhal_scb_config_structs[obj->resource.block_num] = obj; + + cy_stc_sysint_t irqCfg = { CYHAL_SCB_IRQ_N[obj->resource.block_num], CYHAL_ISR_PRIORITY_DEFAULT }; + Cy_SysInt_Init(&irqCfg, cyhal_ezi2c_irq_handler); + NVIC_EnableIRQ(CYHAL_SCB_IRQ_N[obj->resource.block_num]); + + /* Enable EZI2C to operate */ + (void)Cy_SCB_EZI2C_Enable(obj->base); + } + + if (result != CY_RSLT_SUCCESS) + { + cyhal_ezi2c_free(obj); + } + return result; +} + +void cyhal_ezi2c_free(cyhal_ezi2c_t *obj) +{ + CY_ASSERT(NULL != obj); + + if (CYHAL_RSC_INVALID != obj->resource.type) + { + IRQn_Type irqn = CYHAL_SCB_IRQ_N[obj->resource.block_num]; + NVIC_DisableIRQ(irqn); + + cyhal_hwmgr_free(&(obj->resource)); + obj->base = NULL; + obj->resource.type = CYHAL_RSC_INVALID; + } + + cyhal_utils_release_if_used(&(obj->pin_sda)); + cyhal_utils_release_if_used(&(obj->pin_scl)); + + if (!obj->is_shared_clock) + { + cyhal_hwmgr_free_clock(&(obj->clock)); + } +} + +cyhal_ezi2c_status_t cyhal_ezi2c_get_activity_status(cyhal_ezi2c_t *obj) +{ + return (cyhal_ezi2c_status_t)Cy_SCB_EZI2C_GetActivity(obj->base, &(obj->context)); +} + +void cyhal_ezi2c_register_callback(cyhal_ezi2c_t *obj, cyhal_ezi2c_event_callback_t callback, void *callback_arg) +{ + uint32_t savedIntrStatus = cyhal_system_critical_section_enter(); + obj->callback_data.callback = (cy_israddress) callback; + obj->callback_data.callback_arg = callback_arg; + cyhal_system_critical_section_exit(savedIntrStatus); +} + +#if defined(__cplusplus) +} +#endif + +#endif /* CY_IP_MXSCB */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_flash.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_flash.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_flash.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_flash.c index 6b0feb80d94..d901e2e3332 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_flash.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_flash.c @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_gpio.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_gpio.c similarity index 92% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_gpio.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_gpio.c index 0be8107e401..8faf937514c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_gpio.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_gpio.c @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -83,10 +83,15 @@ static uint32_t cyhal_gpio_convert_drive_mode(cyhal_gpio_drive_mode_t drive_mode uint32_t drvMode; switch (drive_mode) { + /* For DRIVE_NONE and DRIVE_ANALOG: Return immediately so drvMode is + * not modified after switch statement based on direction as direction + * does not make sense for input only drive modes */ case CYHAL_GPIO_DRIVE_NONE: - case CYHAL_GPIO_DRIVE_ANALOG: drvMode = CY_GPIO_DM_HIGHZ; - break; + return drvMode; + case CYHAL_GPIO_DRIVE_ANALOG: + drvMode = CY_GPIO_DM_ANALOG; + return drvMode; case CYHAL_GPIO_DRIVE_PULLUP: drvMode = CY_GPIO_DM_PULLUP; break; @@ -155,6 +160,8 @@ void cyhal_gpio_free(cyhal_gpio_t pin) if (pin != CYHAL_NC_PIN_VALUE) { Cy_GPIO_SetInterruptMask(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), 0); + hal_gpio_callbacks[CYHAL_GET_PORT(pin)][CYHAL_GET_PIN(pin)] = NULL; + hal_gpio_callback_args[CYHAL_GET_PORT(pin)][CYHAL_GET_PIN(pin)] = NULL; Cy_GPIO_Pin_FastInit(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), CY_GPIO_DM_ANALOG, 0UL, HSIOM_SEL_GPIO); /* Do not attempt to free the resource we don't reserve in mbed. */ @@ -183,9 +190,10 @@ void cyhal_gpio_register_callback(cyhal_gpio_t pin, cyhal_gpio_event_callback_t void cyhal_gpio_enable_event(cyhal_gpio_t pin, cyhal_gpio_event_t event, uint8_t intrPriority, bool enable) { + Cy_GPIO_ClearInterrupt(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin)); Cy_GPIO_SetInterruptEdge(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), (uint32_t)event); Cy_GPIO_SetInterruptMask(CYHAL_GET_PORTADDR(pin), CYHAL_GET_PIN(pin), (uint32_t)enable); - + /* Only enable if it's not already enabled */ IRQn_Type irqn = (IRQn_Type)(ioss_interrupts_gpio_0_IRQn + CYHAL_GET_PORT(pin)); if (NVIC_GetEnableIRQ(irqn) == 0) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_hwmgr.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_hwmgr.c similarity index 95% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_hwmgr.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_hwmgr.c index 1d66606cbab..b14629220e9 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_hwmgr.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_hwmgr.c @@ -8,7 +8,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -105,18 +105,22 @@ extern "C" #define CY_BLOCK_COUNT_DAC 0 #endif -#if defined(CY_IP_M4CPUSS_DMAC_INSTANCES) || defined(CY_IP_M4CPUSS_DMA_INSTANCES) - #ifndef CPUSS_DMAC_CH_NR - #define CPUSS_DMAC_CH_NR (0u) - #endif - - #define CY_BLOCK_COUNT_DMA 3 - #define CY_CHANNEL_COUNT_DMA (CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR + CPUSS_DMAC_CH_NR) +#if defined(CY_IP_M4CPUSS_DMAC_INSTANCES) + #define CY_BLOCK_COUNT_DMA (CY_IP_M4CPUSS_DMAC_INSTANCES) + #define CY_CHANNEL_COUNT_DMA (CPUSS_DMAC_CH_NR) #else #define CY_BLOCK_COUNT_DMA 0 #define CY_CHANNEL_COUNT_DMA 0 #endif +#if defined(CY_IP_M4CPUSS_DMA_INSTANCES) + #define CY_BLOCK_COUNT_DW (CY_IP_M4CPUSS_DMA_INSTANCES) + #define CY_CHANNEL_COUNT_DW (CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR) +#else + #define CY_BLOCK_COUNT_DW 0 + #define CY_CHANNEL_COUNT_DW 0 +#endif + #ifdef IOSS_GPIO_GPIO_PORT_NR #define CY_BLOCK_COUNT_GPIO IOSS_GPIO_GPIO_PORT_NR #define CY_CHANNEL_COUNT_GPIO (8 * IOSS_GPIO_GPIO_PORT_NR) @@ -259,7 +263,9 @@ extern "C" #define CY_SIZE_DAC CY_BLOCK_COUNT_DAC #define CY_OFFSET_DMA (CY_OFFSET_DAC + CY_SIZE_DAC) #define CY_SIZE_DMA CY_CHANNEL_COUNT_DMA -#define CY_OFFSET_GPIO (CY_OFFSET_DMA + CY_SIZE_DMA) +#define CY_OFFSET_DW (CY_OFFSET_DMA + CY_SIZE_DMA) +#define CY_SIZE_DW CY_CHANNEL_COUNT_DW +#define CY_OFFSET_GPIO (CY_OFFSET_DW + CY_SIZE_DW) #define CY_SIZE_GPIO CY_CHANNEL_COUNT_GPIO #define CY_OFFSET_I2S (CY_OFFSET_GPIO + CY_SIZE_GPIO) #define CY_SIZE_I2S CY_BLOCK_COUNT_I2S @@ -306,10 +312,14 @@ static const uint8_t cyhal_block_offsets_clock[4] = }; static const uint8_t cyhal_block_offsets_dma[] = +{ + 0, +}; + +static const uint8_t cyhal_block_offsets_dw[] = { 0, CPUSS_DW0_CH_NR, - CPUSS_DW0_CH_NR + CPUSS_DW1_CH_NR, }; static const uint8_t cyhal_block_offsets_gpio[] = @@ -415,6 +425,7 @@ static const uint16_t cyhal_resource_offsets[] = CY_OFFSET_CRYPTO, CY_OFFSET_DAC, CY_OFFSET_DMA, + CY_OFFSET_DW, CY_OFFSET_GPIO, CY_OFFSET_I2S, CY_OFFSET_LCD, @@ -435,6 +446,7 @@ static const uint32_t cyhal_has_channels = (1 << CYHAL_RSC_CAN) | (1 << CYHAL_RSC_CLOCK) | (1 << CYHAL_RSC_DMA) | + (1 << CYHAL_RSC_DW) | (1 << CYHAL_RSC_GPIO) | (1 << CYHAL_RSC_TCPWM) ; @@ -449,6 +461,9 @@ static const uint32_t cyhal_has_channels = static inline void check_array_size() __attribute__ ((deprecated)); #if __ICCARM__ #pragma diag_suppress=Pe177 +#elif __clang__ +#pragma clang diagnostic push +#pragma clang diagnostic ignored "-Wunused-function" #endif static inline void check_array_size() { @@ -457,6 +472,8 @@ static inline void check_array_size() } #if __ICCARM__ #pragma diag_default=Pe177 +#elif __clang__ +#pragma clang diagnostic pop #endif /******************************************************************************* @@ -483,6 +500,8 @@ static inline const uint8_t* cyhal_get_block_offsets(cyhal_resource_t type) return cyhal_block_offsets_clock; case CYHAL_RSC_DMA: return cyhal_block_offsets_dma; + case CYHAL_RSC_DW: + return cyhal_block_offsets_dw; case CYHAL_RSC_GPIO: return cyhal_block_offsets_gpio; case CYHAL_RSC_TCPWM: @@ -504,6 +523,8 @@ static inline uint8_t cyhal_get_block_offset_length(cyhal_resource_t type) return sizeof(cyhal_block_offsets_clock)/sizeof(cyhal_block_offsets_clock[0]); case CYHAL_RSC_DMA: return sizeof(cyhal_block_offsets_dma)/sizeof(cyhal_block_offsets_dma[0]); + case CYHAL_RSC_DW: + return sizeof(cyhal_block_offsets_dw)/sizeof(cyhal_block_offsets_dw[0]); case CYHAL_RSC_GPIO: return sizeof(cyhal_block_offsets_gpio)/sizeof(cyhal_block_offsets_gpio[0]); case CYHAL_RSC_TCPWM: @@ -708,11 +729,6 @@ void cyhal_hwmgr_free_clock(cyhal_clock_divider_t* obj) cyhal_hwmgr_free(&res); } -cy_rslt_t cyhal_hwmgr_allocate_dma(cyhal_resource_inst_t* obj) -{ - return cyhal_hwmgr_allocate(CYHAL_RSC_DMA, obj); -} - #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_i2c.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_i2c.c similarity index 95% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_i2c.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_i2c.c index 3d9d26e311c..f5ae876193c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_i2c.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_i2c.c @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -134,10 +134,14 @@ static uint32_t cyhal_set_peri_divider(cyhal_i2c_t *obj, uint32_t freq, bool is_ { return 0; } - Cy_SysClk_PeriphAssignDivider((en_clk_dst_t)((uint8_t)PCLK_SCB0_CLOCK + obj->resource.block_num), obj->clock.div_type, obj->clock.div_num); - Cy_SysClk_PeriphDisableDivider(obj->clock.div_type, obj->clock.div_num); - Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, cyhal_divider_value(peri_freq, 0u)); - Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num); + cy_en_sysclk_status_t status = Cy_SysClk_PeriphAssignDivider((en_clk_dst_t)((uint8_t)PCLK_SCB0_CLOCK + obj->resource.block_num), obj->clock.div_type, obj->clock.div_num); + if (status == CY_SYSCLK_SUCCESS) + status = Cy_SysClk_PeriphDisableDivider(obj->clock.div_type, obj->clock.div_num); + if (status == CY_SYSCLK_SUCCESS) + status = Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, cyhal_divider_value(peri_freq, 0u)); + if (status == CY_SYSCLK_SUCCESS) + status = Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num); + CY_ASSERT(CY_SYSCLK_SUCCESS == status); /* According to PDL API Reference Guide - Cy_SysClk_PeriphGetFrequency() use only for i2c master role */ if(!is_slave) @@ -148,7 +152,6 @@ static uint32_t cyhal_set_peri_divider(cyhal_i2c_t *obj, uint32_t freq, bool is_ { return Cy_SCB_I2C_GetDataRate(obj->base, Cy_SysClk_PeriphGetFrequency(obj->clock.div_type, obj->clock.div_num)); } - } /* Start API implementing */ @@ -268,16 +271,9 @@ void cyhal_i2c_free(cyhal_i2c_t *obj) obj->base = NULL; obj->resource.type = CYHAL_RSC_INVALID; } - if (CYHAL_NC_PIN_VALUE != obj->pin_sda) - { - cyhal_utils_disconnect_and_free(obj->pin_sda); - obj->pin_sda = CYHAL_NC_PIN_VALUE; - } - if (CYHAL_NC_PIN_VALUE != obj->pin_scl) - { - cyhal_utils_disconnect_and_free(obj->pin_scl); - obj->pin_scl = CYHAL_NC_PIN_VALUE; - } + + cyhal_utils_release_if_used(&(obj->pin_sda)); + cyhal_utils_release_if_used(&(obj->pin_scl)); if (!obj->is_shared_clock) { @@ -417,7 +413,7 @@ cy_rslt_t cyhal_i2c_master_mem_write(cyhal_i2c_t *obj, uint16_t address, uint16_ } cy_rslt_t status = cyhal_i2c_master_write(obj, address, mem_addr_buf, mem_addr_size, timeout, false); - + if (status == CY_RSLT_SUCCESS) { while (size > 0) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_interconnect.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_interconnect.c similarity index 97% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_interconnect.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_interconnect.c index 27c569a02f7..15800bc0f2c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_interconnect.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_interconnect.c @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_lptimer.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_lptimer.c similarity index 56% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_lptimer.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_lptimer.c index 8c3ceb70d2a..0884fe46121 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_lptimer.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_lptimer.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -26,7 +26,7 @@ *******************************************************************************/ #include "cmsis_compiler.h" -#include "cy_wdt.h" +#include "cy_mcwdt.h" #include "cy_syslib.h" #include "cy_sysint.h" #include "cyhal_lptimer.h" @@ -52,16 +52,11 @@ static MCWDT_STRUCT_Type * const CYHAL_LPTIMER_BASE_ADDRESSES[] = { #endif }; -#if !defined (CY_CFG_SYSCLK_CLKLF_FREQ_HZ) -#define CY_CFG_SYSCLK_CLKLF_FREQ_HZ 32768UL /* Default to 32K ILO */ -#endif /* CY_CFG_SYSCLK_CLKLF_FREQ_HZ */ - -#define CY_MCWDT_COUNTER0_MAX_TICKS (0xffffUL) -#define CY_MCWDT_COUNTER1_MAX_TICKS (0xffffUL) -#define CY_MCWDT_COUNTER2_MAX_TICKS (0xffffffffUL) #define CY_MCWDT_MAX_DELAY_TICKS (0xfff0ffffUL) /* ~36hours, Not set to 0xffffffff to avoid C0 and C1 both overflowing */ #define CY_MCWDT_LPTIMER_CTRL (CY_MCWDT_CTR0 | CY_MCWDT_CTR1 | CY_MCWDT_CTR2) +#define CY_MCWDT_MIN_DELAY 3 /* minimum amount of lfclk cycles of that LPTIMER can delay for. */ + #define CY_DEFAULT_MCWDT_PRIORITY 3 static const uint16_t CY_MCWDT_RESET_TIME_US = 62; @@ -95,8 +90,8 @@ cy_rslt_t cyhal_lptimer_init(cyhal_lptimer_t *obj) obj->base = CYHAL_LPTIMER_BASE_ADDRESSES[obj->resource.block_num]; const cy_stc_mcwdt_config_t cfg = { - .c0Match = CY_MCWDT_COUNTER0_MAX_TICKS, - .c1Match = CY_MCWDT_COUNTER1_MAX_TICKS, + .c0Match = 0xFFFF, + .c1Match = 0xFFFF, .c0Mode = CY_MCWDT_MODE_INT, .c1Mode = CY_MCWDT_MODE_INT, .c2Mode = CY_MCWDT_MODE_NONE, @@ -107,25 +102,28 @@ cy_rslt_t cyhal_lptimer_init(cyhal_lptimer_t *obj) .c1c2Cascade = false }; rslt = (cy_rslt_t) Cy_MCWDT_Init(obj->base, &cfg); + } + + if (CY_RSLT_SUCCESS == rslt) + { + obj->callback_data.callback = NULL; + obj->callback_data.callback_arg = NULL; + cyhal_lptimer_config_structs[obj->resource.block_num] = obj; + } + if (CY_RSLT_SUCCESS == rslt) + { + IRQn_Type irqn = (IRQn_Type) (srss_interrupt_mcwdt_0_IRQn + obj->resource.block_num); + cy_stc_sysint_t irqCfg = { irqn, CY_DEFAULT_MCWDT_PRIORITY }; + rslt = (cy_rslt_t) Cy_SysInt_Init(&irqCfg, &cyhal_lptimer_irq_handler); if (CY_RSLT_SUCCESS == rslt) { - obj->callback_data.callback = NULL; - obj->callback_data.callback_arg = NULL; - cyhal_lptimer_config_structs[obj->resource.block_num] = obj; - - IRQn_Type irqn = (IRQn_Type) (srss_interrupt_mcwdt_0_IRQn + obj->resource.block_num); - cy_stc_sysint_t irqCfg = { irqn, CY_DEFAULT_MCWDT_PRIORITY }; - rslt = (cy_rslt_t) Cy_SysInt_Init(&irqCfg, &cyhal_lptimer_irq_handler); - - if (CY_RSLT_SUCCESS == rslt) - { - NVIC_EnableIRQ(irqn); - Cy_MCWDT_Enable(obj->base, CY_MCWDT_LPTIMER_CTRL, CY_MCWDT_RESET_TIME_US); - } + NVIC_EnableIRQ(irqn); + Cy_MCWDT_Enable(obj->base, CY_MCWDT_LPTIMER_CTRL, CY_MCWDT_RESET_TIME_US); } } + if (CY_RSLT_SUCCESS != rslt) { cyhal_lptimer_free(obj); @@ -154,96 +152,74 @@ void cyhal_lptimer_free(cyhal_lptimer_t *obj) cy_rslt_t cyhal_lptimer_reload(cyhal_lptimer_t *obj) { - Cy_MCWDT_ResetCounters(obj->base, (CY_MCWDT_CTR0 | CY_MCWDT_CTR1), CY_MCWDT_RESET_TIME_US); + Cy_MCWDT_ResetCounters(obj->base, CY_MCWDT_CTR2, CY_MCWDT_RESET_TIME_US); return CY_RSLT_SUCCESS; } -cy_rslt_t cyhal_lptimer_set_time(cyhal_lptimer_t *obj, uint32_t ticks) +cy_rslt_t cyhal_lptimer_set_match(cyhal_lptimer_t *obj, uint32_t ticks) { - return cyhal_lptimer_set_match(obj, ticks); + return cyhal_lptimer_set_delay(obj, ticks - cyhal_lptimer_read(obj)); } -cy_rslt_t cyhal_lptimer_set_match(cyhal_lptimer_t *obj, uint32_t ticks) +cy_rslt_t cyhal_lptimer_set_delay(cyhal_lptimer_t *obj, uint32_t delay) { - uint16_t c0_match_ticks; - uint16_t c1_match_ticks; - uint32_t mcwdt_interrupt_mask; - uint16_t c0_current_ticks = Cy_MCWDT_GetCount(obj->base, CY_MCWDT_COUNTER0); - uint16_t c1_current_ticks = Cy_MCWDT_GetCount(obj->base, CY_MCWDT_COUNTER1); - - Cy_MCWDT_ClearInterrupt(obj->base, (CY_MCWDT_CTR0 | CY_MCWDT_CTR1)); - - /* Use MCWDT C0,C1 and C2 to implement a 32bit free running counter - C2 alone can not be used as it does not support interrupt on match feature - C2 is used to keep track of time, while C0 and C1 are used to set interrupts - To set an interrupt: - 1. delay = diff between timestamp(time in future) vs current value of C2 - 2. if delay > 2seconds (Max time that can be counted by C0) - Yes - - use both C0 and C1 - - Increment C0 by delay % (CY_MCWDT_COUNTER0_MAX_TICKS + 1) - - Increment C1 by delay / (CY_MCWDT_COUNTER1_MAX_TICKS + 1) - - Special case : In case delay is multiple of (CY_MCWDT_COUNTER0_MAX_TICKS + 1), then - delay % (CY_MCWDT_COUNTER0_MAX_TICKS + 1) will be 0, in this case - - Increment C0 by c0_current_ticks -1 - - Increment C1 by (delay / (CY_MCWDT_COUNTER1_MAX_TICKS + 1)) -1 - No - - Use only C0 - */ - if (ticks > CY_MCWDT_COUNTER0_MAX_TICKS) + /** + * 16 bit C0/C1 are cascaded to generated a 32 bit counter. + * Counter0 continues counting after reaching its match value + * Interrupt is generated on Counter1 match. + * + * Supposed T=C0=C1=0, and we need to trigger an interrupt at T=0x28000. + * We set C0_match to 0x8000 and C1 match to 1. + * At T = 0x8000, C0_value matches C0_match so C1 get incremented. C1/C0=0x18000. + * At T = 0x18000, C0_value matches C0_match again so C1 get incremented from 1 to 2. + * When C1 get incremented from 1 to 2 theinterrupt is generated. + * At T = 0x18000, C1/C0 = 0x28000. + */ + + if (delay <= CY_MCWDT_MIN_DELAY) { - uint16_t c0_increment; - uint16_t c1_increment; - - if (ticks > CY_MCWDT_MAX_DELAY_TICKS) - { - ticks = CY_MCWDT_MAX_DELAY_TICKS; - } + delay = CY_MCWDT_MIN_DELAY; + } + if (delay > CY_MCWDT_MAX_DELAY_TICKS) + { + delay = CY_MCWDT_MAX_DELAY_TICKS; + } - c0_increment = ticks % (CY_MCWDT_COUNTER0_MAX_TICKS + 1); - c0_match_ticks = (c0_current_ticks + c0_increment) % (CY_MCWDT_COUNTER0_MAX_TICKS + 1); - c1_increment = (ticks) / (CY_MCWDT_COUNTER0_MAX_TICKS + 1); - c1_match_ticks = (c1_current_ticks + c1_increment) % (CY_MCWDT_COUNTER1_MAX_TICKS + 1); + uint16_t c0_increment = (uint16_t)delay; + uint16_t c1_increment = (uint16_t)(delay >> 16); - /* Special case - ticks is multiple of (CY_MCWDT_COUNTER0_MAX_TICKS + 1) */ - if (c0_increment == 0) - { - c0_match_ticks = c0_current_ticks - 1; - c1_match_ticks = c1_match_ticks -1; - } + Cy_MCWDT_ClearInterrupt(obj->base, CY_MCWDT_CTR1); - mcwdt_interrupt_mask = CY_MCWDT_CTR1; - } - else - { - c0_match_ticks = c0_current_ticks + (uint16_t)ticks; - c1_match_ticks = CY_MCWDT_COUNTER1_MAX_TICKS; + uint16_t c0_old_match = Cy_MCWDT_GetMatch(obj->base, CY_MCWDT_COUNTER0); - /* MCWDT has internal delay of about 1.5 LF clock ticks, so this is the minimum - * that we can schedule. - */ - if (ticks < 3) - { - /* Cheating a bit here. */ - c0_match_ticks = c0_current_ticks + 3; - } + uint32_t critical_section = cyhal_system_critical_section_enter(); - mcwdt_interrupt_mask = CY_MCWDT_CTR0; - } + /* Cascading from C0 match into C1 is queued and can take 1 full LF clk cycle. + * There are 3 cases: + * Case 1: if c0 = match0 then the cascade into C1 will happen 1 cycle from now. The value c1_current_ticks is 1 lower than expected. + * Case 2: if c0 = match0 -1 then cascade may or not happen before new match value would occur. Match occurs on rising clock edge. + * Synching match value occurs on falling edge. Wait until c0 = match0 to ensure cascade occurs. + * Case 3: everything works as expected. + */ + uint16_t c0_current_ticks; + while ((c0_current_ticks = (Cy_MCWDT_GetCount(obj->base, CY_MCWDT_COUNTER0))) == c0_old_match) {} - if(c1_match_ticks == 0) + uint16_t c1_current_ticks = Cy_MCWDT_GetCount(obj->base, CY_MCWDT_COUNTER1); + if (c0_current_ticks == c0_old_match + 1) { - c1_match_ticks = 1; + c1_current_ticks++; } - - if(c0_match_ticks == 0) + if (Cy_MCWDT_GetCount(obj->base, CY_MCWDT_COUNTER0) != c0_current_ticks) { - c0_match_ticks = 1; + // Just in the very unlikely case that an increment occurred while previous instruction was running. + c1_current_ticks = Cy_MCWDT_GetCount(obj->base, CY_MCWDT_COUNTER1); } + Cy_MCWDT_SetMatch(obj->base, CY_MCWDT_COUNTER0, c0_current_ticks + c0_increment, CY_MCWDT_SETMATCH_NOWAIT_TIME_US); + Cy_MCWDT_SetMatch(obj->base, CY_MCWDT_COUNTER1, c1_current_ticks + c1_increment, CY_MCWDT_SETMATCH_NOWAIT_TIME_US); + + cyhal_system_critical_section_exit(critical_section); - Cy_MCWDT_SetMatch(obj->base, CY_MCWDT_COUNTER0, c0_match_ticks, CY_MCWDT_SETMATCH_NOWAIT_TIME_US); - Cy_MCWDT_SetMatch(obj->base, CY_MCWDT_COUNTER1, c1_match_ticks, CY_MCWDT_SETMATCH_NOWAIT_TIME_US); - Cy_MCWDT_SetInterruptMask(obj->base, mcwdt_interrupt_mask); + Cy_MCWDT_SetInterruptMask(obj->base, CY_MCWDT_CTR1); return CY_RSLT_SUCCESS; } @@ -265,8 +241,10 @@ void cyhal_lptimer_register_callback(cyhal_lptimer_t *obj, cyhal_lptimer_event_c void cyhal_lptimer_enable_event(cyhal_lptimer_t *obj, cyhal_lptimer_event_t event, uint8_t intrPriority, bool enable) { - Cy_MCWDT_SetInterruptMask(obj->base, enable ? CY_MCWDT_CTR0 : 0); - + CY_ASSERT(event == CYHAL_LPTIMER_COMPARE_MATCH); + Cy_MCWDT_ClearInterrupt(obj->base, CY_MCWDT_CTR1); + Cy_MCWDT_SetInterruptMask(obj->base, enable ? CY_MCWDT_CTR1 : 0); + IRQn_Type irqn = (IRQn_Type)(srss_interrupt_mcwdt_0_IRQn + obj->resource.block_num); NVIC_SetPriority(irqn, intrPriority); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_not_implemented.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_not_implemented.c similarity index 87% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_not_implemented.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_not_implemented.c index bedd38d6ebb..ee1b7ceb148 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_not_implemented.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_not_implemented.c @@ -10,7 +10,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -27,6 +27,8 @@ *******************************************************************************/ #include "cyhal_interconnect.h" +#include "cyhal_triggers.h" +#include "cy_utils.h" #if defined(__cplusplus) extern "C" @@ -46,12 +48,13 @@ typedef enum } cyhal_trigger_src; /* Trigger type for each output ~100b */ +/* Note: Non-fake version implemented in cyhal_triggers */ typedef enum { DEST0, DEST1, MUX_IN1, -} cyhal_trigger_dest; +} cyhal_trigger_dest_fake; // Two fake muxes. // Mux0 @@ -62,7 +65,8 @@ typedef enum // Outputs: DEST1 /* Maps each cyhal_destination_t to a mux index ~100b */ -const uint8_t cyhal_dest_to_mux[] = +/* Note: Non-fake version implemented in cyhal_triggers */ +const uint8_t cyhal_dest_to_mux_fake[] = { 0, // DEST0 1, // DEST1 @@ -70,7 +74,8 @@ const uint8_t cyhal_dest_to_mux[] = }; /* Maps each cyhal_destination_t to a specific output in its mux ~100b */ -const uint8_t cyhal_mux_dest_index[] = +/* Note: Non-fake version implemented in cyhal_triggers */ +const uint8_t cyhal_mux_dest_index_fake[] = { 0, // DEST0 0, // DEST1 @@ -87,10 +92,10 @@ const cyhal_source_t* cyhal_mux_to_sources[] = { cyhal_mux0_sources, cyhal_mux1_ /* Mapping from cyhal_source_t to cyhal_destination_t for intra mux connections ~80b*/ const cyhal_dest_t cyhal_intra_trigger_source[] = { - CYHAL_INTERCONNECT_MUX_NOT_CONTINUATION, // SRC0 - CYHAL_INTERCONNECT_MUX_NOT_CONTINUATION, // SRC1, - CYHAL_INTERCONNECT_MUX_NOT_CONTINUATION, // SRC2, - MUX_IN1 // MUX_OUT0 + (cyhal_dest_t)CYHAL_INTERCONNECT_MUX_NOT_CONTINUATION, // SRC0 + (cyhal_dest_t)CYHAL_INTERCONNECT_MUX_NOT_CONTINUATION, // SRC1, + (cyhal_dest_t)CYHAL_INTERCONNECT_MUX_NOT_CONTINUATION, // SRC2, + (cyhal_dest_t)MUX_IN1 // MUX_OUT0 }; @@ -111,7 +116,7 @@ typedef enum #define ONE_TO_ONE_IDENT 0x80 /** Determines whether a mux is one-to-one */ #define IS_1TO1(muxId) (ONE_TO_ONE_IDENT == (muxId & ONE_TO_ONE_IDENT)) -#define WRITE_REGISTER(muxIdx, sourceId, destId) /* TODO */ +#define WRITE_REGISTER(muxIdx, sourceId, destId) /* Maps each cyhal_destination_t to a mux index */ //extern uint8_t cyhal_dest_to_mux[]; @@ -126,7 +131,8 @@ typedef enum bool cyhal_has_connection(uint8_t mux, uint8_t outputIdx) { - // TODO + CY_UNUSED_PARAMETER(mux); + CY_UNUSED_PARAMETER(outputIdx); return false; } @@ -138,8 +144,8 @@ bool cyhal_has_connection(uint8_t mux, uint8_t outputIdx) */ cy_rslt_t cyhal_connect_trigger(cyhal_source_t source, cyhal_dest_t dest) { - uint8_t muxIdx = cyhal_dest_to_mux[dest]; - uint8_t destId = dest - cyhal_mux_dest_index[dest]; + uint8_t muxIdx = cyhal_dest_to_mux_fake[dest]; + uint8_t destId = dest - cyhal_mux_dest_index_fake[dest]; uint8_t sourceCount = cyhal_source_count_per_mux[muxIdx]; if (cyhal_has_connection(muxIdx, destId)) @@ -166,8 +172,8 @@ cy_rslt_t cyhal_connect_trigger(cyhal_source_t source, cyhal_dest_t dest) if (CYHAL_INTERCONNECT_MUX_NOT_CONTINUATION != intraDest) { // This destination can be driven by the output of another mux. - uint8_t upstreamMuxIdx = cyhal_dest_to_mux[intraDest]; - uint8_t intraDestId = intraDest - cyhal_mux_dest_index[intraDest]; + uint8_t upstreamMuxIdx = cyhal_dest_to_mux_fake[intraDest]; + uint8_t intraDestId = intraDest - cyhal_mux_dest_index_fake[intraDest]; uint8_t upstreamMuxSourceCount = cyhal_source_count_per_mux[upstreamMuxIdx]; cy_rslt_t result = CYHAL_CONNECT_RSLT_NO_CONNECTION; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_pwm.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_pwm.c new file mode 100644 index 00000000000..880bf464862 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_pwm.c @@ -0,0 +1,340 @@ +/***************************************************************************//** +* \file cyhal_pwm.c +* +* \brief +* Provides a high level interface for interacting with the Cypress PWM. This is +* a wrapper around the lower level PDL API. +* +******************************************************************************** +* \copyright +* Copyright 2018-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +/** + * \addtogroup group_hal_psoc6_pwm PWM (Pulse Width Modulator) + * \ingroup group_hal_psoc6 + * \{ + * \section section_psoc6_pwm_compl_pins Complementary PWM output + * The PWM HAL driver allows generation of a normal and an inverted output. PSoC 6 devices support complementary pin pairs to which the normal and + * inverted signals can be routed. To identify the complementary pin for a given pin, open the PSoC 6 device datasheet and navigate to the 'Multiple Alternate Functions' table. Each + * column represents an alternate function of the pin in the corresponding row. Find your pin and make a note of the tcpwm[X].line[Y]:Z. The + * complementary pin is found by looking up the pin against tcpwm[X].line_compl[Y]:Z from the same column. + * For example, the image below shows a pair of complementary pins (P0.0 and P0.1) identified by the tcpwm[0].line[0]:0 and tcpwm[0].line_compl[0]:0 mapping. + * These complementary pins can be supplied to \ref cyhal_pwm_init_adv using pin and compl_pin parameters in any order. + * \image html pwm_compl_pins.png "Complementary PWM pins" + * + * \} group_hal_psoc6_pwm + */ + +#include +#include "cyhal_pwm_impl.h" +#include "cyhal_gpio.h" +#include "cyhal_hwmgr.h" +#include "cyhal_interconnect.h" +#include "cyhal_utils.h" + +#ifdef CY_IP_MXTCPWM + +#if defined(__cplusplus) +extern "C" { +#endif + +#define TCPWM_MAX_WIDTH 32 +#define MAX_DEAD_TIME_CYCLES 255 +static const uint32_t US_PER_SEC = 1000000u; + +/** The configuration of PWM output signal for Center and Asymmetric alignment with overflow and underflow swapped */ +#define CY_TCPWM_PWM_MODE_CNTR_OR_ASYMM_UO_SWAPPED (_VAL2FLD(TCPWM_CNT_TR_CTRL2_CC_MATCH_MODE, CY_TCPWM_PWM_TR_CTRL2_INVERT) | \ + _VAL2FLD(TCPWM_CNT_TR_CTRL2_OVERFLOW_MODE, CY_TCPWM_PWM_TR_CTRL2_CLEAR) | \ + _VAL2FLD(TCPWM_CNT_TR_CTRL2_UNDERFLOW_MODE, CY_TCPWM_PWM_TR_CTRL2_SET)) + +static const cyhal_resource_pin_mapping_t* try_alloc_pwm(cyhal_gpio_t pin, const cyhal_resource_pin_mapping_t *pin_map, size_t count) +{ + for (uint32_t i = 0; i < count; i++) + { + if (pin == pin_map[i].pin) + { + if (CY_RSLT_SUCCESS == cyhal_hwmgr_reserve(pin_map[i].inst)) + { + return &pin_map[i]; + } + } + } + return NULL; +} + +static cy_rslt_t convert_alignment(cyhal_pwm_alignment_t hal_alignment, uint32_t *pdl_alignment, bool swapped) +{ + switch (hal_alignment) + { + case CYHAL_PWM_LEFT_ALIGN: + *pdl_alignment = (swapped) ? CY_TCPWM_PWM_RIGHT_ALIGN : CY_TCPWM_PWM_LEFT_ALIGN; + return CY_RSLT_SUCCESS; + case CYHAL_PWM_RIGHT_ALIGN: + *pdl_alignment = (swapped) ? CY_TCPWM_PWM_LEFT_ALIGN : CY_TCPWM_PWM_RIGHT_ALIGN; + return CY_RSLT_SUCCESS; + case CYHAL_PWM_CENTER_ALIGN: + *pdl_alignment = CY_TCPWM_PWM_CENTER_ALIGN; + return CY_RSLT_SUCCESS; + default: + return CYHAL_PWM_RSLT_BAD_ARGUMENT; + } +} + +cy_rslt_t cyhal_pwm_init_adv(cyhal_pwm_t *obj, cyhal_gpio_t pin, cyhal_gpio_t pin_compl, cyhal_pwm_alignment_t pwm_alignment, bool continuous, uint32_t dead_time_us, bool invert, const cyhal_clock_divider_t *clk) +{ + CY_ASSERT(NULL != obj); + + cy_rslt_t result = CY_RSLT_SUCCESS; + bool swapped = false; + + const cyhal_resource_pin_mapping_t* map = try_alloc_pwm(pin, cyhal_pin_map_tcpwm_line, sizeof(cyhal_pin_map_tcpwm_line) / sizeof(cyhal_resource_pin_mapping_t)); + if (map == NULL) + { + swapped = true; + map = try_alloc_pwm(pin, cyhal_pin_map_tcpwm_line_compl, sizeof(cyhal_pin_map_tcpwm_line_compl) / sizeof(cyhal_resource_pin_mapping_t)); + } + if (map == NULL) + { + return CYHAL_PWM_RSLT_BAD_ARGUMENT; + } + else + { + /* Explicitly marked not allocated resources as invalid to prevent freeing them. */ + obj->resource.type = CYHAL_RSC_INVALID; + obj->dedicated_clock = false; + obj->resource = *map->inst; + obj->base = CYHAL_TCPWM_DATA[obj->resource.block_num].base; + obj->pin = CYHAL_NC_PIN_VALUE; + obj->pin_compl = CYHAL_NC_PIN_VALUE; + + result = cyhal_utils_reserve_and_connect(pin, map); + if (CY_RSLT_SUCCESS == result) + { + obj->pin = pin; + } + } + + if (CY_RSLT_SUCCESS == result && NC != pin_compl) + { + const cyhal_resource_pin_mapping_t *map_compl = swapped + ? CY_UTILS_GET_RESOURCE(pin_compl, cyhal_pin_map_tcpwm_line) + : CY_UTILS_GET_RESOURCE(pin_compl, cyhal_pin_map_tcpwm_line_compl); + + if ((NULL == map_compl) || !cyhal_utils_resources_equal(map->inst, map_compl->inst)) + { + result = CYHAL_PWM_RSLT_BAD_ARGUMENT; + } + else + { + result = cyhal_utils_reserve_and_connect(pin_compl, map_compl); + if (CY_RSLT_SUCCESS == result) + { + obj->pin_compl = pin_compl; + } + } + } + + if (CY_RSLT_SUCCESS == result) + { + uint32_t source_hz = Cy_SysClk_ClkPeriGetFrequency(); + en_clk_dst_t pclk = (en_clk_dst_t)(CYHAL_TCPWM_DATA[obj->resource.block_num].clock_dst + obj->resource.channel_num); + if (NULL != clk) + { + obj->clock_hz = source_hz / (1 + Cy_SysClk_PeriphGetDivider(clk->div_type, clk->div_num)); + if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(pclk, clk->div_type, clk->div_num)) + { + result = CYHAL_PWM_RSLT_FAILED_CLOCK_INIT; + } + } + else + { + if (CY_RSLT_SUCCESS == (result = cyhal_hwmgr_allocate_clock(&(obj->clock), CY_SYSCLK_DIV_16_BIT, false))) + { + obj->dedicated_clock = true; + uint32_t div = (dead_time_us > 0) + ? (((uint64_t)source_hz * dead_time_us) / (US_PER_SEC * MAX_DEAD_TIME_CYCLES)) + 1 + : (uint32_t)(1 << (TCPWM_MAX_WIDTH - CYHAL_TCPWM_DATA[obj->resource.block_num].max_count)); + + if (0 == div || + CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, div - 1) || + CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num) || + CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(pclk, obj->clock.div_type, obj->clock.div_num)) + { + result = CYHAL_PWM_RSLT_FAILED_CLOCK_INIT; + } + else + { + obj->clock_hz = source_hz / div; + } + } + } + } + + uint32_t pdl_alignment = CY_TCPWM_PWM_LEFT_ALIGN; + if (CY_RSLT_SUCCESS == result) + { + result = convert_alignment(pwm_alignment, &pdl_alignment, swapped); + } + + if (CY_RSLT_SUCCESS == result) + { + uint8_t dead_time = dead_time_us * obj->clock_hz / US_PER_SEC; + + cy_stc_tcpwm_pwm_config_t config = + { + .pwmMode = (dead_time == 0) ? CY_TCPWM_PWM_MODE_PWM : CY_TCPWM_PWM_MODE_DEADTIME, + .clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_1, + .pwmAlignment = pdl_alignment, + .deadTimeClocks = dead_time, + .runMode = (continuous) ? CY_TCPWM_PWM_CONTINUOUS : CY_TCPWM_PWM_ONESHOT, + .period0 = 0UL, + .period1 = 0UL, + .enablePeriodSwap = false, + .compare0 = 0UL, + .compare1 = 0UL, + .enableCompareSwap = false, + .interruptSources = CY_TCPWM_INT_NONE, + .invertPWMOut = (invert) ? CY_TCPWM_PWM_INVERT_ENABLE : CY_TCPWM_PWM_INVERT_DISABLE, + .invertPWMOutN = (invert) ? CY_TCPWM_PWM_INVERT_ENABLE : CY_TCPWM_PWM_INVERT_DISABLE, + .killMode = CY_TCPWM_PWM_STOP_ON_KILL, + .swapInputMode = CY_TCPWM_INPUT_RISINGEDGE, + .swapInput = CY_TCPWM_INPUT_0, + .reloadInputMode = CY_TCPWM_INPUT_RISINGEDGE, + .reloadInput = CY_TCPWM_INPUT_0, + .startInputMode = CY_TCPWM_INPUT_RISINGEDGE, + .startInput = CY_TCPWM_INPUT_0, + .killInputMode = CY_TCPWM_INPUT_RISINGEDGE, + .killInput = CY_TCPWM_INPUT_0, + .countInputMode = CY_TCPWM_INPUT_LEVEL, + .countInput = CY_TCPWM_INPUT_1 + }; + result = Cy_TCPWM_PWM_Init(obj->base, obj->resource.channel_num, &config); + if ((swapped) && (pwm_alignment == CYHAL_PWM_CENTER_ALIGN)) + { + TCPWM_CNT_TR_CTRL2(obj->base, obj->resource.channel_num) = CY_TCPWM_PWM_MODE_CNTR_OR_ASYMM_UO_SWAPPED; + } + } + + if (CY_RSLT_SUCCESS == result) + { + cyhal_tcpwm_init_callback_data(&(obj->resource), &(obj->callback_data)); + Cy_TCPWM_PWM_Enable(obj->base, obj->resource.channel_num); + } + else + { + cyhal_pwm_free(obj); + } + + return result; +} + +void cyhal_pwm_free(cyhal_pwm_t *obj) +{ + CY_ASSERT(NULL != obj); + + IRQn_Type irqn = (IRQn_Type)(CYHAL_TCPWM_DATA[obj->resource.block_num].isr_offset + obj->resource.channel_num); + NVIC_DisableIRQ(irqn); + + cyhal_utils_release_if_used(&(obj->pin)); + cyhal_utils_release_if_used(&(obj->pin_compl)); + + if (NULL != obj->base) + { + Cy_TCPWM_PWM_Disable(obj->base, obj->resource.channel_num); + + cyhal_hwmgr_free(&(obj->resource)); + obj->base = NULL; + obj->resource.type = CYHAL_RSC_INVALID; + } + + if (obj->dedicated_clock) + { + cy_en_sysclk_status_t rslt = Cy_SysClk_PeriphDisableDivider(obj->clock.div_type, obj->clock.div_num); + CY_UNUSED_PARAMETER(rslt); /* CY_ASSERT only processes in DEBUG, ignores for others */ + CY_ASSERT(CY_SYSCLK_SUCCESS == rslt); + cyhal_hwmgr_free_clock(&(obj->clock)); + obj->dedicated_clock = false; + } +} + +static cy_rslt_t cyhal_pwm_set_period_and_compare(cyhal_pwm_t *obj, uint32_t period, uint32_t compare) +{ + if (period < 1 || period > (uint32_t)((1 << CYHAL_TCPWM_DATA[obj->resource.block_num].max_count)) - 1) + return CYHAL_PWM_RSLT_BAD_ARGUMENT; + if (compare > period) + compare = period; + + cyhal_gpio_t pin = obj->pin; + cyhal_gpio_t pin_compl = obj->pin_compl; + + Cy_TCPWM_PWM_SetCompare0(obj->base, obj->resource.channel_num, 0u); + Cy_TCPWM_PWM_SetPeriod0(obj->base, obj->resource.channel_num, period - 1u); + + bool swapped_pins = (CY_UTILS_GET_RESOURCE(pin, cyhal_pin_map_tcpwm_line_compl) != NULL) && (CY_UTILS_GET_RESOURCE(pin_compl, cyhal_pin_map_tcpwm_line) != NULL); + bool is_center_aligned = (TCPWM_CNT_TR_CTRL2(obj->base, obj->resource.channel_num) == CY_TCPWM_PWM_MODE_CNTR_OR_ASYMM) || + (TCPWM_CNT_TR_CTRL2(obj->base, obj->resource.channel_num) == CY_TCPWM_PWM_MODE_CNTR_OR_ASYMM_UO_SWAPPED); + + if ((swapped_pins) && (!is_center_aligned)) + { + Cy_TCPWM_PWM_SetCompare0(obj->base, obj->resource.channel_num, period - compare); + } + else + { + Cy_TCPWM_PWM_SetCompare0(obj->base, obj->resource.channel_num, compare); + } + + + return CY_RSLT_SUCCESS; +} + +cy_rslt_t cyhal_pwm_set_period(cyhal_pwm_t *obj, uint32_t period_us, uint32_t pulse_width_us) +{ + CY_ASSERT(NULL != obj); + uint32_t period = (uint32_t)((uint64_t)period_us * obj->clock_hz / US_PER_SEC); + uint32_t width = (uint32_t)((uint64_t)pulse_width_us * obj->clock_hz / US_PER_SEC); + return cyhal_pwm_set_period_and_compare(obj, period, width); +} + +cy_rslt_t cyhal_pwm_set_duty_cycle(cyhal_pwm_t *obj, float duty_cycle, uint32_t frequencyhal_hz) +{ + CY_ASSERT(NULL != obj); + if (duty_cycle < 0.0f || duty_cycle > 100.0f || frequencyhal_hz < 1) + return CYHAL_PWM_RSLT_BAD_ARGUMENT; + uint32_t period = obj->clock_hz / frequencyhal_hz; + uint32_t width = (uint32_t)(duty_cycle * 0.01f * period); + return cyhal_pwm_set_period_and_compare(obj, period, width); +} + +cy_rslt_t cyhal_pwm_start(cyhal_pwm_t *obj) +{ + CY_ASSERT(NULL != obj); + Cy_TCPWM_TriggerReloadOrIndex(obj->base, 1u << obj->resource.channel_num); + return CY_RSLT_SUCCESS; +} + +cy_rslt_t cyhal_pwm_stop(cyhal_pwm_t *obj) +{ + CY_ASSERT(NULL != obj); + Cy_TCPWM_TriggerStopOrKill(obj->base, 1u << obj->resource.channel_num); + return CY_RSLT_SUCCESS; +} + +#if defined(__cplusplus) +} +#endif + +#endif /* CY_IP_MXTCPWM */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_qspi.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_qspi.c similarity index 86% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_qspi.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_qspi.c index 5c4c852a6d6..8673da20f1e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_qspi.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_qspi.c @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -207,30 +207,6 @@ static cy_rslt_t make_pin_reservations(cyhal_qspi_t *obj) #endif -/* Free all QSPI pins */ -static void free_pin_connections(cyhal_qspi_t *obj) -{ - if (CYHAL_NC_PIN_VALUE != obj->pin_sclk) - { - cyhal_utils_disconnect_and_free(obj->pin_sclk); - obj->pin_sclk = CYHAL_NC_PIN_VALUE; - } - if (CYHAL_NC_PIN_VALUE != obj->pin_ssel) - { - cyhal_utils_disconnect_and_free(obj->pin_ssel); - obj->pin_ssel = CYHAL_NC_PIN_VALUE; - } - - for (uint8_t i = 0; (i < MAX_DATA_PINS); i++) - { - if (CYHAL_NC_PIN_VALUE != obj->pin_ios[i]) - { - cyhal_utils_disconnect_and_free(obj->pin_ios[i]); - obj->pin_ios[i] = CYHAL_NC_PIN_VALUE; - } - } -} - /******************************************************************************* * (Internal) QSPI Config Related Functions *******************************************************************************/ @@ -292,45 +268,16 @@ static inline uint32_t get_size(cyhal_qspi_size_t hal_size) return ((uint32_t)hal_size >> 3); /* convert bits to bytes */ } -/* cyhal_qspi_bus_width_t to number of bus lines used */ -static uint8_t get_lines(cyhal_qspi_bus_width_t hal_width) -{ - uint8_t lines; - - switch (hal_width) - { - case CYHAL_QSPI_CFG_BUS_SINGLE: - lines = 1; - break; - case CYHAL_QSPI_CFG_BUS_DUAL: - lines = 2; - break; - case CYHAL_QSPI_CFG_BUS_QUAD: - lines = 4; - break; - case CYHAL_QSPI_CFG_BUS_OCTAL: - lines = 8; - break; - default: - lines = 0; - } - - return lines; -} - /* Sends QSPI command with certain set of data */ /* Address passed through 'command' is not used, instead the value in 'addr' is used. */ static cy_rslt_t qspi_command_transfer(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, - uint32_t addr, bool endOfTransfer, uint8_t *dummy_cycles) + uint32_t addr, bool endOfTransfer) { /* max address size is 4 bytes and max mode bits size is 4 bytes */ uint8_t cmd_param[8] = {0}; uint32_t start_pos = 0; uint32_t addr_size = 0; - uint32_t mode_size = 0; - uint8_t leftover_bits = 0; - uint8_t lines = 0; - uint8_t integrated_dummy_cycles = 0; + uint32_t mode_bits_size = 0; cy_en_smif_txfr_width_t bus_width = CY_SMIF_WIDTH_SINGLE; cy_stc_smif_mem_cmd_t cyhal_cmd_config; cy_rslt_t result = CY_RSLT_SUCCESS; @@ -361,67 +308,22 @@ static cy_rslt_t qspi_command_transfer(cyhal_qspi_t *obj, const cyhal_qspi_comma if (!command->address.disabled) { addr_size = get_size(command->address.size); - if (addr_size == 0) - { - result = CYHAL_QSPI_RSLT_ERR_SIZE; - } - else - { - uint32_to_byte_array(addr, cmd_param, start_pos, addr_size); - start_pos += addr_size; - bus_width = cyhal_cmd_config.addrWidth; - } + uint32_to_byte_array(addr, cmd_param, start_pos, addr_size); + start_pos += addr_size; + bus_width = cyhal_cmd_config.addrWidth; } if (!command->mode_bits.disabled) { - // Mode size must be a multiple of the number of bus lines used (i.e. a whole number of cycles) - lines = get_lines(command->mode_bits.bus_width); - if (lines == 0) - { - result = CYHAL_QSPI_RSLT_ERR_BUS_WIDTH; - } - else if (command->mode_bits.size % lines != 0) - { - result = CYHAL_QSPI_RSLT_ERR_ALT_SIZE_WIDTH_MISMATCH; - } - else - { - // Round mode size up to nearest byte - unused parts of byte act as dummy cycles - mode_size = get_size(command->mode_bits.size - 1) + 1; - - // Unused bits in most significant byte of mode - leftover_bits = (mode_size << 3) - command->mode_bits.size; - if (leftover_bits != 0) - { - // Account for dummy cycles that will be spent in the mode portion of the command - integrated_dummy_cycles = (8 - (command->mode_bits.size % 8)) / lines; - if (*dummy_cycles < integrated_dummy_cycles) - { - // Not enough dummy cycles to account for a short mode - result = CYHAL_QSPI_RSLT_ERR_ALT_SIZE_DUMMY_CYCLES_MISMATCH; - } - else - { - *dummy_cycles -= integrated_dummy_cycles; - } - - // Align mode value to the end of the most significant byte - cyhal_cmd_config.mode <<= leftover_bits; - } - - uint32_to_byte_array(cyhal_cmd_config.mode, cmd_param, start_pos, mode_size); - bus_width = cyhal_cmd_config.modeWidth; - } + mode_bits_size = get_size(command->mode_bits.size); + uint32_to_byte_array(cyhal_cmd_config.mode, cmd_param, start_pos, mode_bits_size); + bus_width = cyhal_cmd_config.modeWidth; } - if (CY_RSLT_SUCCESS == result) - { - uint32_t cmpltTxfr = ((endOfTransfer) ? 1UL : 0UL); - result = (cy_rslt_t)Cy_SMIF_TransmitCommand(obj->base, cyhal_cmd_config.command, - cyhal_cmd_config.cmdWidth, cmd_param, (addr_size + mode_size), - bus_width, obj->slave_select, cmpltTxfr, &obj->context); - } + uint32_t cmpltTxfr = ((endOfTransfer) ? 1UL : 0UL); + result = (cy_rslt_t)Cy_SMIF_TransmitCommand(obj->base, cyhal_cmd_config.command, + cyhal_cmd_config.cmdWidth, cmd_param, (addr_size + mode_bits_size), + bus_width, obj->slave_select, cmpltTxfr, &obj->context); } return result; } @@ -817,10 +719,10 @@ cy_rslt_t cyhal_qspi_init( } } - if (CY_RSLT_SUCCESS == result) - { - result = cyhal_qspi_set_frequency(obj, hz); - } + /* cyhal_qspi_set_frequency should be called here. + Changing clock frequency is not supported on this device. + */ + (void)hz; if (CY_RSLT_SUCCESS == result) { @@ -866,15 +768,20 @@ void cyhal_qspi_free(cyhal_qspi_t *obj) obj->resource.type = CYHAL_RSC_INVALID; } - free_pin_connections(obj); + cyhal_utils_release_if_used(&(obj->pin_sclk)); + cyhal_utils_release_if_used(&(obj->pin_ssel)); + for (uint8_t i = 0; (i < MAX_DATA_PINS); i++) + { + cyhal_utils_release_if_used(&(obj->pin_ios[i])); + } } cy_rslt_t cyhal_qspi_set_frequency(cyhal_qspi_t *obj, uint32_t hz) { - /* TODO after HAL clock management implemented JIRA: BSP-510 */ + /* Changing clock frequency is not supported on this device. */ (void) obj; (void) hz; - return CY_RSLT_SUCCESS; + return CYHAL_QSPI_RSLT_ERR_FREQUENCY; } /* no restriction on the value of length. This function splits the read into multiple chunked transfers. */ @@ -884,7 +791,6 @@ cy_rslt_t cyhal_qspi_read(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command uint32_t chunk = 0; size_t read_bytes = *length; uint32_t addr = command->address.value; - uint8_t dummy_cycles = command->dummy_count; /* SMIF can read only up to 65536 bytes in one go. Split the larger read into multiple chunks */ while (read_bytes > 0) @@ -898,11 +804,11 @@ cy_rslt_t cyhal_qspi_read(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command * to create a copy of the command object. Instead of copying the object, the address is * passed separately. */ - status = qspi_command_transfer(obj, command, addr, false, &dummy_cycles); + status = qspi_command_transfer(obj, command, addr, false); if (CY_RSLT_SUCCESS == status) { - if (dummy_cycles > 0u) + if (command->dummy_count > 0u) { status = (cy_rslt_t)Cy_SMIF_SendDummyCycles(obj->base, command->dummy_count); } @@ -927,15 +833,13 @@ cy_rslt_t cyhal_qspi_read(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command cy_rslt_t cyhal_qspi_read_async(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, void *data, size_t *length) { - cy_rslt_t status = CY_RSLT_SUCCESS; - uint32_t addr = command->address.value; - uint8_t dummy_cycles = command->dummy_count; - status = qspi_command_transfer(obj, command, addr, false, &dummy_cycles); + cy_rslt_t status = qspi_command_transfer(obj, command, command->address.value, false); + if (CY_RSLT_SUCCESS == status) { if (command->dummy_count > 0u) { - status = (cy_rslt_t)Cy_SMIF_SendDummyCycles(obj->base, dummy_cycles); + status = (cy_rslt_t)Cy_SMIF_SendDummyCycles(obj->base, command->dummy_count); } if (CY_RSLT_SUCCESS == status) @@ -950,14 +854,13 @@ cy_rslt_t cyhal_qspi_read_async(cyhal_qspi_t *obj, const cyhal_qspi_command_t *c /* length can be up to 65536. */ cy_rslt_t cyhal_qspi_write(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, const void *data, size_t *length) { - uint8_t dummy_cycles = command->dummy_count; - cy_rslt_t status = qspi_command_transfer(obj, command, command->address.value, false, &dummy_cycles); + cy_rslt_t status = qspi_command_transfer(obj, command, command->address.value, false); if (CY_RSLT_SUCCESS == status) { if (command->dummy_count > 0u) { - status = (cy_rslt_t)Cy_SMIF_SendDummyCycles(obj->base, dummy_cycles); + status = (cy_rslt_t)Cy_SMIF_SendDummyCycles(obj->base, command->dummy_count); } if ((CY_SMIF_SUCCESS == status) && (*length > 0)) @@ -973,14 +876,13 @@ cy_rslt_t cyhal_qspi_write(cyhal_qspi_t *obj, const cyhal_qspi_command_t *comman /* length can be up to 65536. */ cy_rslt_t cyhal_qspi_write_async(cyhal_qspi_t *obj, const cyhal_qspi_command_t *command, const void *data, size_t *length) { - uint8_t dummy_cycles = command->dummy_count; - cy_rslt_t status = qspi_command_transfer(obj, command, command->address.value, false, &dummy_cycles); + cy_rslt_t status = qspi_command_transfer(obj, command, command->address.value, false); if (CY_RSLT_SUCCESS == status) { if (command->dummy_count > 0u) { - status = (cy_rslt_t)Cy_SMIF_SendDummyCycles(obj->base, dummy_cycles); + status = (cy_rslt_t)Cy_SMIF_SendDummyCycles(obj->base, command->dummy_count); } if ((CY_SMIF_SUCCESS == status) && (*length > 0)) @@ -1001,7 +903,7 @@ cy_rslt_t cyhal_qspi_transfer( if ((tx_data == NULL || tx_size == 0) && (rx_data == NULL || rx_size == 0)) { /* only command, no rx or tx */ - status = qspi_command_transfer(obj, command, command->address.value, true, NULL); + status = qspi_command_transfer(obj, command, command->address.value, true); } else { diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_rtc.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_rtc.c similarity index 57% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_rtc.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_rtc.c index c0042f70e22..28172f5efb0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_rtc.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_rtc.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -26,9 +26,29 @@ *******************************************************************************/ #include "cy_rtc.h" +#include "cy_utils.h" #include "cyhal_rtc.h" #include "cyhal_system.h" +/** +* \addtogroup group_hal_psoc6_rtc RTC (Real Time Clock) +* \ingroup group_hal_psoc6 +* \{ +* +* Internally the PSoC6 RTC only stores the year as a two digit BCD value +* (0-99); no century information is stored. On RTC initialization the HAL must, +* as a result, assume a default century. If cyhal_rtc_write has been called +* with a different century than the default, its value must be stored and that +* value must persist through deep sleep, hibernate, software resets, etc. PSoC6 +* hardware provides a number of BREG registers which exist in the BACKUP domain +* and will persist over these power modes and resets. The HAL uses the highest +* indexed BACKUP->BREG register to store the century for the RTC. +* +* Therefore do not use the highest indexed BACKUP->BREG register as it is +* reserved for internal HAL usage. +* \} group_hal_psoc6_wdt +*/ + #ifdef CY_IP_MXS40SRSS_RTC_INSTANCES #if defined(__cplusplus) @@ -42,28 +62,59 @@ extern "C" { #define CYHAL_RTC_INIT_CENTURY 2000 #define CYHAL_TM_YEAR_BASE 1900 +#define CYHAL_RTC_BREG (BACKUP->BREG[SRSS_BACKUP_NUM_BREG-1]) +#define CYHAL_RTC_BREG_CENTURY_Pos 0UL +#define CYHAL_RTC_BREG_CENTURY_Msk 0x0000FFFFUL +#define CYHAL_RTC_BREG_STATE_Pos 16UL +#define CYHAL_RTC_BREG_STATE_Msk 0xFFFF0000UL + /** Wrapper around the PDL Cy_RTC_DeepSleepCallback to adapt the function signature */ static cy_en_syspm_status_t cyhal_rtc_syspm_callback(cy_stc_syspm_callback_params_t *params, cy_en_syspm_callback_mode_t mode) { return Cy_RTC_DeepSleepCallback(params, mode); } +static cy_stc_rtc_dst_t *dst; static cy_stc_syspm_callback_params_t cyhal_rtc_pm_cb_params = {NULL, NULL}; static cy_stc_syspm_callback_t cyhal_rtc_pm_cb = { .callback = &cyhal_rtc_syspm_callback, .type = CY_SYSPM_DEEPSLEEP, .callbackParams = &cyhal_rtc_pm_cb_params, }; + static cyhal_rtc_event_callback_t cyhal_rtc_user_handler; static void *cyhal_rtc_handler_arg; -#define CYHAL_RTC_INITIAL_CENTURY 1900 -static uint16_t cyhal_rtc_century = CYHAL_RTC_INITIAL_CENTURY; -static uint8_t cyhal_rtc_initialized = CYHAL_RTC_STATE_UNINITIALIZED; + +/* Returns century portion of BREG register used to store century info */ +static inline uint16_t get_rtc_century() +{ + return _FLD2VAL(CYHAL_RTC_BREG_CENTURY, CYHAL_RTC_BREG); +} + +/* Sets century portion of BREG register used to store century info */ +static inline void set_rtc_century(uint16_t century) +{ + CYHAL_RTC_BREG &= CYHAL_RTC_BREG_STATE_Msk; + CYHAL_RTC_BREG |= _VAL2FLD(CYHAL_RTC_BREG_CENTURY, century); +} + +/* Returns state portion of BREG register used to store century info */ +static inline uint16_t get_rtc_state() +{ + return _FLD2VAL(CYHAL_RTC_BREG_STATE, CYHAL_RTC_BREG); +} + +/* Sets state portion of BREG register used to store century info */ +static inline void set_rtc_state(uint16_t init) +{ + CYHAL_RTC_BREG &= CYHAL_RTC_BREG_CENTURY_Msk; + CYHAL_RTC_BREG |= _VAL2FLD(CYHAL_RTC_BREG_STATE, init); +} /** Wrapper around the PDL RTC interrupt handler to adapt the function signature */ static void cyhal_rtc_internal_handler(void) { - Cy_RTC_Interrupt(NULL, false); + Cy_RTC_Interrupt(dst, NULL != dst); } void Cy_RTC_Alarm1Interrupt(void) @@ -76,63 +127,84 @@ void Cy_RTC_Alarm1Interrupt(void) void Cy_RTC_CenturyInterrupt(void) { - cyhal_rtc_century += 100; + set_rtc_century(get_rtc_century() + 100); } cy_rslt_t cyhal_rtc_init(cyhal_rtc_t *obj) { CY_ASSERT(NULL != obj); cy_rslt_t rslt = CY_RSLT_SUCCESS; - if (cyhal_rtc_initialized == CYHAL_RTC_STATE_UNINITIALIZED) + if (get_rtc_state() == CYHAL_RTC_STATE_UNINITIALIZED) { if (Cy_RTC_IsExternalResetOccurred()) { // Reset to default time static const cy_stc_rtc_config_t defaultTime = { - .dayOfWeek = CY_RTC_THURSDAY, + .dayOfWeek = CY_RTC_SATURDAY, .date = 1, .month = 1, - .year = 70 + .year = 0, }; Cy_RTC_SetDateAndTime(&defaultTime); + set_rtc_century(CYHAL_RTC_INIT_CENTURY); + } + + if (Cy_SysPm_RegisterCallback(&cyhal_rtc_pm_cb)) + { + set_rtc_state(CYHAL_RTC_STATE_ENABLED); } else { - // Time is already set (possibly after sw reset). Assume century. - cyhal_rtc_century = CYHAL_RTC_INIT_CENTURY; + rslt = CY_RSLT_RTC_NOT_INITIALIZED; } - Cy_RTC_ClearInterrupt(CY_RTC_INTR_CENTURY); - Cy_RTC_SetInterruptMask(CY_RTC_INTR_CENTURY); - static const cy_stc_sysint_t irqCfg = {.intrSrc = srss_interrupt_backup_IRQn, .intrPriority = CYHAL_RTC_DEFAULT_PRIORITY}; - Cy_SysInt_Init(&irqCfg, &cyhal_rtc_internal_handler); - Cy_SysPm_RegisterCallback(&cyhal_rtc_pm_cb); - cyhal_rtc_initialized = CYHAL_RTC_STATE_ENABLED; } - NVIC_EnableIRQ(srss_interrupt_backup_IRQn); + else if(get_rtc_state() == CYHAL_RTC_STATE_ENABLED || get_rtc_state() == CYHAL_RTC_STATE_TIME_SET) + { + if(Cy_RTC_GetInterruptStatus() & CY_RTC_INTR_CENTURY) + Cy_RTC_CenturyInterrupt(); + } + + Cy_RTC_ClearInterrupt(CY_RTC_INTR_CENTURY); + Cy_RTC_SetInterruptMask(CY_RTC_INTR_CENTURY); + static const cy_stc_sysint_t irqCfg = {.intrSrc = srss_interrupt_backup_IRQn, .intrPriority = CYHAL_RTC_DEFAULT_PRIORITY}; + Cy_SysInt_Init(&irqCfg, &cyhal_rtc_internal_handler); + + if (rslt == CY_RSLT_SUCCESS) + { + dst = NULL; + NVIC_EnableIRQ(srss_interrupt_backup_IRQn); + } + return rslt; } void cyhal_rtc_free(cyhal_rtc_t *obj) { + CY_ASSERT(NULL != obj); NVIC_DisableIRQ(srss_interrupt_backup_IRQn); Cy_RTC_SetInterruptMask(CY_RTC_INTR_CENTURY); + dst = NULL; } bool cyhal_rtc_is_enabled(cyhal_rtc_t *obj) { - return (cyhal_rtc_initialized == CYHAL_RTC_STATE_TIME_SET); + CY_ASSERT(NULL != obj); + return (get_rtc_state() == CYHAL_RTC_STATE_TIME_SET); } cy_rslt_t cyhal_rtc_read(cyhal_rtc_t *obj, struct tm *time) { + CY_ASSERT(NULL != obj); // The number of days that precede each month of the year, not including Feb 29 static const uint16_t CUMULATIVE_DAYS[] = {0, 31, 59, 90, 120, 151, 181, 212, 243, 273, 304, 334}; + cy_stc_rtc_config_t dateTime; uint32_t savedIntrStatus = cyhal_system_critical_section_enter(); Cy_RTC_GetDateAndTime(&dateTime); - int year = dateTime.year + cyhal_rtc_century; + int year = dateTime.year + get_rtc_century(); cyhal_system_critical_section_exit(savedIntrStatus); + time->tm_sec = dateTime.sec; time->tm_min = dateTime.min; time->tm_hour = dateTime.hour; @@ -143,11 +215,13 @@ cy_rslt_t cyhal_rtc_read(cyhal_rtc_t *obj, struct tm *time) time->tm_yday = CUMULATIVE_DAYS[time->tm_mon] + dateTime.date - 1u + ((dateTime.month >= 3 && Cy_RTC_IsLeapYear(year)) ? 1u : 0u); time->tm_isdst = -1; + return CY_RSLT_SUCCESS; } cy_rslt_t cyhal_rtc_write(cyhal_rtc_t *obj, const struct tm *time) { + CY_ASSERT(NULL != obj); uint32_t year2digit = time->tm_year % 100; cy_stc_rtc_config_t newtime = { .sec = time->tm_sec, @@ -159,6 +233,7 @@ cy_rslt_t cyhal_rtc_write(cyhal_rtc_t *obj, const struct tm *time) .month = time->tm_mon + 1, .year = year2digit }; + cy_rslt_t rslt; uint32_t retry = 0; static const uint32_t MAX_RETRY = 10, RETRY_DELAY_MS = 1; @@ -168,19 +243,58 @@ cy_rslt_t cyhal_rtc_write(cyhal_rtc_t *obj, const struct tm *time) uint32_t savedIntrStatus = cyhal_system_critical_section_enter(); rslt = (cy_rslt_t)Cy_RTC_SetDateAndTime(&newtime); if (rslt == CY_RSLT_SUCCESS) - cyhal_rtc_century = time->tm_year - year2digit + CYHAL_TM_YEAR_BASE; + set_rtc_century(time->tm_year - year2digit + CYHAL_TM_YEAR_BASE); cyhal_system_critical_section_exit(savedIntrStatus); ++retry; } while (rslt == CY_RTC_INVALID_STATE && retry < MAX_RETRY); + while (CY_RTC_BUSY == Cy_RTC_GetSyncStatus()) { } + if (rslt == CY_RSLT_SUCCESS) - cyhal_rtc_initialized = CYHAL_RTC_STATE_TIME_SET; + set_rtc_state(CYHAL_RTC_STATE_TIME_SET); return rslt; } +static void initialize_dst(const cyhal_rtc_dst_t *hal, cy_stc_rtc_dst_format_t *pdl) +{ + pdl->format = (hal->format == CYHAL_RTC_DST_FIXED) ? CY_RTC_DST_FIXED : CY_RTC_DST_RELATIVE; + pdl->hour = hal->hour; + pdl->dayOfMonth = (hal->format == CYHAL_RTC_DST_FIXED) ? hal->dayOfMonth : 1; + pdl->weekOfMonth = (hal->format == CYHAL_RTC_DST_FIXED) ? 1 : hal->weekOfMonth + 1; + pdl->dayOfWeek = (hal->format == CYHAL_RTC_DST_FIXED) ? 1 : hal->dayOfWeek + 1; + pdl->month = hal->month; +} + +cy_rslt_t cyhal_rtc_set_dst(cyhal_rtc_t *obj, const cyhal_rtc_dst_t *start, const cyhal_rtc_dst_t *stop) +{ + CY_ASSERT(NULL != obj); + CY_ASSERT(NULL != start); + CY_ASSERT(NULL != stop); + + initialize_dst(start, &(obj->dst.startDst)); + initialize_dst(stop, &(obj->dst.stopDst)); + + cy_stc_rtc_config_t dateTime; + Cy_RTC_GetDateAndTime(&dateTime); + cy_rslt_t rslt = Cy_RTC_EnableDstTime(&(obj->dst), &dateTime); + if (rslt == CY_RSLT_SUCCESS) + dst = &(obj->dst); + return rslt; +} + +bool cyhal_rtc_is_dst(cyhal_rtc_t *obj) +{ + CY_ASSERT(NULL != obj); + + cy_stc_rtc_config_t dateTime; + Cy_RTC_GetDateAndTime(&dateTime); + return Cy_RTC_GetDstStatus(&(obj->dst), &dateTime); +} + cy_rslt_t cyhal_rtc_set_alarm(cyhal_rtc_t *obj, const struct tm *time, cyhal_alarm_active_t active) { // Note: the hardware does not support year matching + CY_ASSERT(NULL != obj); cy_stc_rtc_alarm_t alarm = { .sec = time->tm_sec, .secEn = active.en_sec ? CY_RTC_ALARM_ENABLE : CY_RTC_ALARM_DISABLE, @@ -201,16 +315,20 @@ cy_rslt_t cyhal_rtc_set_alarm(cyhal_rtc_t *obj, const struct tm *time, cyhal_ala void cyhal_rtc_register_callback(cyhal_rtc_t *obj, cyhal_rtc_event_callback_t callback, void *callback_arg) { + CY_ASSERT(NULL != obj); uint32_t savedIntrStatus = cyhal_system_critical_section_enter(); cyhal_rtc_handler_arg = callback_arg; cyhal_rtc_user_handler = callback; cyhal_system_critical_section_exit(savedIntrStatus); } -void cyhal_rtc_enable_event(cyhal_rtc_t *obj, cyhal_rtc_event_t event, uint8_t intrPriority, bool enable) +void cyhal_rtc_enable_event(cyhal_rtc_t *obj, cyhal_rtc_event_t event, uint8_t intr_priority, bool enable) { + CY_ASSERT(NULL != obj); + CY_ASSERT(CYHAL_RTC_ALARM == event); Cy_RTC_ClearInterrupt(CY_RTC_INTR_ALARM1 | CY_RTC_INTR_ALARM2); Cy_RTC_SetInterruptMask((enable ? CY_RTC_INTR_ALARM1 : 0) | CY_RTC_INTR_CENTURY); + NVIC_SetPriority(srss_interrupt_backup_IRQn, intr_priority); } #if defined(__cplusplus) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_scb_common.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_scb_common.c similarity index 98% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_scb_common.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_scb_common.c index 2b640f5e650..ee2e994c4a2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_scb_common.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_scb_common.c @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_sdhc.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_sdhc.c similarity index 92% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_sdhc.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_sdhc.c index da2f6108f35..2671b13d2a4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_sdhc.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_sdhc.c @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -26,6 +26,7 @@ #include /* For memcpy */ #include #include "cy_pdl.h" +#include "cy_utils.h" #include "cy_result.h" #include "cyhal_sdhc.h" #include "cyhal_sdio.h" @@ -71,12 +72,9 @@ extern "C" #define BIT_MASK( x ) (( 1 << x ) - 1 ) -#define SDIO_PINS_NC ((cyhal_gpio_t) CYHAL_NC_PIN_VALUE) - /* Macro-function to calculate pin mapping number */ #define COUNT(pin_mapping) (sizeof(pin_mapping)/sizeof(cyhal_resource_pin_mapping_t)) - #if (defined(SDHC_CHIP_TOP_DATA8_PRESENT) && (SDHC_CHIP_TOP_DATA8_PRESENT)) || \ (defined(SDHC0_CHIP_TOP_DATA8_PRESENT) && (SDHC0_CHIP_TOP_DATA8_PRESENT)) || \ (defined(SDHC1_CHIP_TOP_DATA8_PRESENT) && (SDHC1_CHIP_TOP_DATA8_PRESENT)) @@ -224,20 +222,11 @@ static const uint32_t eventMap[SDHC_EVENTS_NUM][SDHC_EVENTS_MAP_NUM] = { (uint32_t)CYHAL_SDHC_ERR_INTERRUPT, (uint32_t)CY_SD_HOST_ERR_INTERRUPT }, }; -static void release_pin_if_used(cyhal_gpio_t *pin) -{ - if (CYHAL_NC_PIN_VALUE != *pin) - { - cyhal_utils_disconnect_and_free(*pin); - *pin = CYHAL_NC_PIN_VALUE; - } -} - static cy_rslt_t setup_pin(cyhal_gpio_t pin, const cyhal_resource_pin_mapping_t *pinmap, size_t count, cyhal_gpio_t *objRef) { cyhal_resource_inst_t pin_rsc = cyhal_utils_get_gpio_resource(pin); cy_rslt_t result = cyhal_hwmgr_reserve(&pin_rsc); - + if (result == CY_RSLT_SUCCESS) { const cyhal_resource_pin_mapping_t *map = cyhal_utils_get_resource(pin, pinmap, count); @@ -269,9 +258,9 @@ static cy_rslt_t setup_pin(cyhal_gpio_t pin, const cyhal_resource_pin_mapping_t static bool isTransferInProcess = false; /* Internal functions */ -static cy_en_sd_host_status_t Cy_SD_Host_PollTransferComplete(SDHC_Type *base, const uint16_t delay); -static cy_en_sd_host_status_t Cy_SD_Host_PollCmdComplete(SDHC_Type *base); -static cy_en_sd_host_status_t Cy_SD_Host_SdCardChangeClock(SDHC_Type *base, uint32_t instance_num, uint32_t frequency); +static cy_en_sd_host_status_t cyhal_sd_host_polltransfercomplete(SDHC_Type *base, const uint16_t delay); +static cy_en_sd_host_status_t cyhal_sd_host_pollcmdcomplete(SDHC_Type *base); +static cy_en_sd_host_status_t cyhal_sd_host_sdcardchangeclock(SDHC_Type *base, uint32_t instance_num, uint32_t frequency); static cy_en_sd_host_bus_width_t convert_buswidth(uint8_t stopbits); static cy_en_syspm_status_t cyhal_sdio_syspm_callback(cy_stc_syspm_callback_params_t *params, cy_en_syspm_callback_mode_t mode); @@ -363,7 +352,7 @@ static cy_en_sd_host_bus_width_t convert_buswidth(uint8_t stopbits) /******************************************************************************* -* Function Name: Cy_SD_Host_SdCardChangeClock +* Function Name: cyhal_sd_host_sdcardchangeclock ****************************************************************************//** * * Changes the Host controller SD clock. @@ -380,19 +369,19 @@ static cy_en_sd_host_bus_width_t convert_buswidth(uint8_t stopbits) * \return \ref cy_en_sd_host_status_t * *******************************************************************************/ -static cy_en_sd_host_status_t Cy_SD_Host_SdCardChangeClock(SDHC_Type *base, uint32_t instance_num, uint32_t frequency) +static cy_en_sd_host_status_t cyhal_sd_host_sdcardchangeclock(SDHC_Type *base, uint32_t instance_num, uint32_t frequency) { cy_en_sd_host_status_t ret = CY_SD_HOST_ERROR_INVALID_PARAMETER; uint32_t clockInput = 0; - - cy_rslt_t get_frequency_result = + + cy_rslt_t get_frequency_result = cyhal_system_clock_get_frequency(CYHAL_SDHC_HF_CLOCKS[instance_num], &clockInput); if ((NULL != base) && (get_frequency_result == CY_RSLT_SUCCESS) && (0U != clockInput)) { /* Update SD Host clock divider */ uint16_t clkDiv = (uint16_t) ((clockInput / frequency) >> 1UL); - + Cy_SD_Host_DisableSdClk(base); ret = Cy_SD_Host_SetSdClkDiv(base, clkDiv); Cy_SD_Host_EnableSdClk(base); @@ -424,7 +413,7 @@ static cy_en_sd_host_status_t Cy_SD_Host_SdCardChangeClock(SDHC_Type *base, uint /******************************************************************************* -* Function Name: Cy_SD_Host_PollCmdComplete +* Function Name: cyhal_sd_host_pollcmdcomplete ****************************************************************************//** * * Waits for the command complete event. @@ -435,7 +424,7 @@ static cy_en_sd_host_status_t Cy_SD_Host_SdCardChangeClock(SDHC_Type *base, uint * \return \ref cy_en_sd_host_status_t * *******************************************************************************/ -static cy_en_sd_host_status_t Cy_SD_Host_PollCmdComplete(SDHC_Type *base) +static cy_en_sd_host_status_t cyhal_sd_host_pollcmdcomplete(SDHC_Type *base) { cy_en_sd_host_status_t ret = CY_SD_HOST_ERROR_TIMEOUT; uint32_t retry = SDHC_RETRY_TIMES; @@ -461,7 +450,7 @@ static cy_en_sd_host_status_t Cy_SD_Host_PollCmdComplete(SDHC_Type *base) /******************************************************************************* -* Function Name: Cy_SD_Host_PollTransferComplete +* Function Name: cyhal_sd_host_polltransfercomplete ****************************************************************************//** * * Waits for the command complete event. @@ -477,7 +466,7 @@ static cy_en_sd_host_status_t Cy_SD_Host_PollCmdComplete(SDHC_Type *base) * If the pointer is NULL, returns error. * *******************************************************************************/ -static cy_en_sd_host_status_t Cy_SD_Host_PollTransferComplete(SDHC_Type *base, const uint16_t delay) +static cy_en_sd_host_status_t cyhal_sd_host_polltransfercomplete(SDHC_Type *base, const uint16_t delay) { cy_en_sd_host_status_t ret = CY_SD_HOST_ERROR_TIMEOUT; uint32_t retry = SDHC_RW_RETRY_CYCLES; @@ -578,9 +567,9 @@ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj, CY_ASSERT(NULL != obj); cy_rslt_t result = CY_RSLT_SUCCESS; - + obj->base = NULL; - + obj->pin_clk = CYHAL_NC_PIN_VALUE; obj->pin_cmd = CYHAL_NC_PIN_VALUE; obj->pin_data[0] = CYHAL_NC_PIN_VALUE; @@ -655,8 +644,8 @@ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj, if ((NC != cardDetect) && (CY_RSLT_SUCCESS == result)) { #if CARD_DETECT_PRESENT - result = setup_pin(cardDetect, cyhal_pin_map_sdhc_card_detect_n, - COUNT(cyhal_pin_map_sdhc_card_detect_n), &(obj->pin_cardDetect)); + result = setup_pin(cardDetect, cyhal_pin_map_sdhc_card_detect_n, + COUNT(cyhal_pin_map_sdhc_card_detect_n), &(obj->pin_cardDetect)); #else result = CYHAL_SDHC_RSLT_ERR_PIN; #endif @@ -665,8 +654,8 @@ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj, if ((NC != ioVoltSel) && (CY_RSLT_SUCCESS == result)) { #if IO_VOLT_SEL_PRESENT - result = setup_pin(ioVoltSel, cyhal_pin_map_sdhc_io_volt_sel, - COUNT(cyhal_pin_map_sdhc_io_volt_sel), &(obj->pin_ioVoltSel)); + result = setup_pin(ioVoltSel, cyhal_pin_map_sdhc_io_volt_sel, + COUNT(cyhal_pin_map_sdhc_io_volt_sel), &(obj->pin_ioVoltSel)); #else result = CYHAL_SDHC_RSLT_ERR_PIN; #endif @@ -675,8 +664,8 @@ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj, if ((NC != cardIfPwrEn) && (CY_RSLT_SUCCESS == result)) { #if CARD_IF_PWR_EN_PRESENT - result = setup_pin(cardIfPwrEn, cyhal_pin_map_sdhc_card_if_pwr_en, - COUNT(cyhal_pin_map_sdhc_card_if_pwr_en), &(obj->pin_cardIfPwrEn)); + result = setup_pin(cardIfPwrEn, cyhal_pin_map_sdhc_card_if_pwr_en, + COUNT(cyhal_pin_map_sdhc_card_if_pwr_en), &(obj->pin_cardIfPwrEn)); #else result = CYHAL_SDHC_RSLT_ERR_PIN; #endif @@ -685,8 +674,8 @@ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj, if ((NC != cardMechWriteProt) && (CY_RSLT_SUCCESS == result)) { #if CARD_WRITE_PROT_PRESENT - result = setup_pin(cardMechWriteProt, cyhal_pin_map_sdhc_card_mech_write_prot, - COUNT(cyhal_pin_map_sdhc_card_mech_write_prot), &(obj->pin_cardMechWriteProt)); + result = setup_pin(cardMechWriteProt, cyhal_pin_map_sdhc_card_mech_write_prot, + COUNT(cyhal_pin_map_sdhc_card_mech_write_prot), &(obj->pin_cardMechWriteProt)); #else result = CYHAL_SDHC_RSLT_ERR_PIN; #endif @@ -695,8 +684,8 @@ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj, if ((NC != ledCtrl) && (CY_RSLT_SUCCESS == result)) { #if LED_CTRL_PRESENT - result = setup_pin(ledCtrl, cyhal_pin_map_sdhc_led_ctrl, - COUNT(cyhal_pin_map_sdhc_led_ctrl), &(obj->pin_ledCtrl)); + result = setup_pin(ledCtrl, cyhal_pin_map_sdhc_led_ctrl, + COUNT(cyhal_pin_map_sdhc_led_ctrl), &(obj->pin_ledCtrl)); #else result = CYHAL_SDHC_RSLT_ERR_PIN; #endif @@ -705,8 +694,8 @@ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj, if ((NC != cardEmmcReset) && (CY_RSLT_SUCCESS == result)) { #if CARD_EMMC_RESET_PRESENT - result = setup_pin(cardEmmcReset, cyhal_pin_map_sdhc_card_emmc_reset_n, - COUNT(cyhal_pin_map_sdhc_card_emmc_reset_n), &(obj->pin_cardEmmcReset)); + result = setup_pin(cardEmmcReset, cyhal_pin_map_sdhc_card_emmc_reset_n, + COUNT(cyhal_pin_map_sdhc_card_emmc_reset_n), &(obj->pin_cardEmmcReset)); #else result = CYHAL_SDHC_RSLT_ERR_PIN; #endif @@ -755,7 +744,7 @@ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj, cy_stc_sysint_t irqCfg = { irqn, CYHAL_ISR_PRIORITY_DEFAULT }; Cy_SysInt_Init(&irqCfg, cyhal_sdhc_irq_handler); NVIC_EnableIRQ(irqn); - + result = (cy_rslt_t) Cy_SD_Host_Init(obj->base, &hostConfig, &obj->context); } @@ -776,11 +765,11 @@ cy_rslt_t cyhal_sdhc_init(cyhal_sdhc_t *obj, /* Initialize the card */ result = (cy_rslt_t)Cy_SD_Host_InitCard(obj->base, &stcSdcardCfg, &obj->context); - + if (result == CY_RSLT_SUCCESS) { /* Update SD Card frequency to be 25 Mhz */ - result = (cy_rslt_t) Cy_SD_Host_SdCardChangeClock(obj->base, obj->resource.block_num, CY_SD_HOST_CLK_25M); + result = (cy_rslt_t) cyhal_sd_host_sdcardchangeclock(obj->base, obj->resource.block_num, CY_SD_HOST_CLK_25M); } } } @@ -803,15 +792,15 @@ void cyhal_sdhc_free(cyhal_sdhc_t *obj) NVIC_DisableIRQ(irqn); Cy_SD_Host_DeInit(obj->base); - + cyhal_hwmgr_free(&(obj->resource)); obj->base = NULL; obj->resource.type = CYHAL_RSC_INVALID; } /* Free pins */ - release_pin_if_used(&obj->pin_cmd); - release_pin_if_used(&obj->pin_clk); + cyhal_utils_release_if_used(&(obj->pin_cmd)); + cyhal_utils_release_if_used(&(obj->pin_clk)); #if DATA8_PRESENT const uint8_t max_idx = 8; @@ -820,31 +809,31 @@ void cyhal_sdhc_free(cyhal_sdhc_t *obj) #endif for (uint8_t i = 0; i < max_idx; i++) { - release_pin_if_used(&obj->pin_data[i]); + cyhal_utils_release_if_used(&(obj->pin_data[i])); } #if CARD_DETECT_PRESENT - release_pin_if_used(&obj->pin_cardDetect); + cyhal_utils_release_if_used(&(obj->pin_cardDetect)); #endif #if IO_VOLT_SEL_PRESENT - release_pin_if_used(&obj->pin_ioVoltSel); + cyhal_utils_release_if_used(&(obj->pin_ioVoltSel)); #endif #if CARD_IF_PWR_EN_PRESENT - release_pin_if_used(&obj->pin_cardIfPwrEn); + cyhal_utils_release_if_used(&(obj->pin_cardIfPwrEn)); #endif #if CARD_WRITE_PROT_PRESENT - release_pin_if_used(&obj->pin_cardMechWriteProt); + cyhal_utils_release_if_used(&(obj->pin_cardMechWriteProt)); #endif #if LED_CTRL_PRESENT - release_pin_if_used(&obj->pin_ledCtrl); + cyhal_utils_release_if_used(&(obj->pin_ledCtrl)); #endif #if CARD_EMMC_RESET_PRESENT - release_pin_if_used(&obj->pin_cardEmmcReset); + cyhal_utils_release_if_used(&(obj->pin_cardEmmcReset)); #endif } @@ -879,14 +868,14 @@ cy_rslt_t cyhal_sdhc_read(const cyhal_sdhc_t *obj, uint32_t address, uint8_t *da } else { - driverRet = Cy_SD_Host_PollTransferComplete(obj->base, SDHC_RW_TIMEOUT_US); - + driverRet = cyhal_sd_host_polltransfercomplete(obj->base, SDHC_RW_TIMEOUT_US); + if (CY_SD_HOST_SUCCESS != driverRet) { ret = CY_RSLT_TYPE_ERROR; } } - + /* Restore interrupts after transition */ Cy_SD_Host_SetNormalInterruptMask(obj->base, regIntrSts); @@ -933,7 +922,7 @@ cy_rslt_t cyhal_sdhc_write(const cyhal_sdhc_t *obj, uint32_t address, const uint } else { - driverRet = Cy_SD_Host_PollTransferComplete(obj->base, SDHC_RW_TIMEOUT_US); + driverRet = cyhal_sd_host_polltransfercomplete(obj->base, SDHC_RW_TIMEOUT_US); if (CY_SD_HOST_SUCCESS != driverRet) { @@ -984,7 +973,7 @@ cy_rslt_t cyhal_sdhc_erase(const cyhal_sdhc_t *obj, uint32_t startAddr, size_t l } else { - driverRet = Cy_SD_Host_PollCmdComplete(obj->base); + driverRet = cyhal_sd_host_pollcmdcomplete(obj->base); } if (CY_SD_HOST_SUCCESS != driverRet) @@ -1037,15 +1026,23 @@ cy_rslt_t cyhal_sdhc_erase(const cyhal_sdhc_t *obj, uint32_t startAddr, size_t l cy_rslt_t cyhal_sdhc_read_async(const cyhal_sdhc_t *obj, uint32_t address, uint8_t *data, size_t *length) { - cy_rslt_t ret = CY_RSLT_SUCCESS; - //TODO: implement + /* Not yet implemented for this device. */ + CY_UNUSED_PARAMETER(obj); + CY_UNUSED_PARAMETER(address); + CY_UNUSED_PARAMETER(data); + CY_UNUSED_PARAMETER(length); + cy_rslt_t ret = CYHAL_SDHC_RSLT_ERR_UNSUPPORTED; return ret; } cy_rslt_t cyhal_sdhc_write_async(const cyhal_sdhc_t *obj, uint32_t address, const uint8_t *data, size_t *length) { - cy_rslt_t ret = CY_RSLT_SUCCESS; - //TODO: implement + /* Not yet implemented for this device. */ + CY_UNUSED_PARAMETER(obj); + CY_UNUSED_PARAMETER(address); + CY_UNUSED_PARAMETER(data); + CY_UNUSED_PARAMETER(length); + cy_rslt_t ret = CYHAL_SDHC_RSLT_ERR_UNSUPPORTED; return ret; } @@ -1186,37 +1183,37 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, obj->pin_data2 = CYHAL_NC_PIN_VALUE; obj->pin_data3 = CYHAL_NC_PIN_VALUE; - result = setup_pin( - cmd, cyhal_pin_map_sdhc_card_cmd, COUNT(cyhal_pin_map_sdhc_card_cmd), &(obj->pin_cmd)); + result = setup_pin(cmd, cyhal_pin_map_sdhc_card_cmd, + COUNT(cyhal_pin_map_sdhc_card_cmd), &(obj->pin_cmd)); if (CY_RSLT_SUCCESS == result) { - result = setup_pin( - clk, cyhal_pin_map_sdhc_clk_card, COUNT(cyhal_pin_map_sdhc_clk_card), &(obj->pin_clk)); + result = setup_pin(clk, cyhal_pin_map_sdhc_clk_card, + COUNT(cyhal_pin_map_sdhc_clk_card), &(obj->pin_clk)); } if (CY_RSLT_SUCCESS == result) { - result = setup_pin( - data0, cyhal_pin_map_sdhc_card_dat_3to0, COUNT(cyhal_pin_map_sdhc_card_dat_3to0), &(obj->pin_data0)); + result = setup_pin(data0, cyhal_pin_map_sdhc_card_dat_3to0, + COUNT(cyhal_pin_map_sdhc_card_dat_3to0), &(obj->pin_data0)); } - + if (CY_RSLT_SUCCESS == result) { - result = setup_pin( - data1, cyhal_pin_map_sdhc_card_dat_3to0, COUNT(cyhal_pin_map_sdhc_card_dat_3to0), &(obj->pin_data1)); + result = setup_pin(data1, cyhal_pin_map_sdhc_card_dat_3to0, + COUNT(cyhal_pin_map_sdhc_card_dat_3to0), &(obj->pin_data1)); } - + if (CY_RSLT_SUCCESS == result) { - result = setup_pin( - data2, cyhal_pin_map_sdhc_card_dat_3to0, COUNT(cyhal_pin_map_sdhc_card_dat_3to0), &(obj->pin_data2)); + result = setup_pin(data2, cyhal_pin_map_sdhc_card_dat_3to0, + COUNT(cyhal_pin_map_sdhc_card_dat_3to0), &(obj->pin_data2)); } - + if (CY_RSLT_SUCCESS == result) { - result = setup_pin( - data3, cyhal_pin_map_sdhc_card_dat_3to0, COUNT(cyhal_pin_map_sdhc_card_dat_3to0), &(obj->pin_data3)); + result = setup_pin(data3, cyhal_pin_map_sdhc_card_dat_3to0, + COUNT(cyhal_pin_map_sdhc_card_dat_3to0), &(obj->pin_data3)); } if (result == CY_RSLT_SUCCESS) @@ -1228,7 +1225,7 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, if (result == CY_RSLT_SUCCESS) { obj->resource = sdhc; - + if (result == CY_RSLT_SUCCESS) { obj->base = CYHAL_SDHC_BASE_ADDRESSES[obj->resource.block_num]; @@ -1265,9 +1262,6 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, if (result == CY_RSLT_SUCCESS) { - /* Only enable the SDMA interrupt */ - Cy_SD_Host_SetNormalInterruptMask(obj->base, CY_SD_HOST_DMA_INTERRUPT); - /* Don't enable any error interrupts for now */ Cy_SD_Host_SetErrorInterruptMask(obj->base, 0UL); @@ -1290,7 +1284,7 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, (void)Cy_SD_Host_SetHostBusWidth(obj->base, CY_SD_HOST_BUS_WIDTH_4_BIT); /* Change the host SD clock to 400 kHz */ - (void) Cy_SD_Host_SdCardChangeClock(obj->base, obj->resource.block_num, SDIO_HOST_CLK_400K); + (void) cyhal_sd_host_sdcardchangeclock(obj->base, obj->resource.block_num, SDIO_HOST_CLK_400K); obj->frequencyhal_hz = SDIO_HOST_CLK_400K; obj->block_size = SDIO_64B_BLOCK; @@ -1327,27 +1321,26 @@ void cyhal_sdio_free(cyhal_sdio_t *obj) } /* Free pins */ - release_pin_if_used(&obj->pin_clk); - release_pin_if_used(&obj->pin_cmd); - release_pin_if_used(&obj->pin_data0); - release_pin_if_used(&obj->pin_data1); - release_pin_if_used(&obj->pin_data2); - release_pin_if_used(&obj->pin_data3); + cyhal_utils_release_if_used(&obj->pin_clk); + cyhal_utils_release_if_used(&obj->pin_cmd); + cyhal_utils_release_if_used(&obj->pin_data0); + cyhal_utils_release_if_used(&obj->pin_data1); + cyhal_utils_release_if_used(&obj->pin_data2); + cyhal_utils_release_if_used(&obj->pin_data3); } - cy_rslt_t cyhal_sdio_configure(cyhal_sdio_t *obj, const cyhal_sdio_cfg_t *config) { cy_en_sd_host_status_t result = CY_SD_HOST_ERROR_TIMEOUT; - if ((NULL == obj) && (config == NULL)) + if ((NULL == obj) || (config == NULL)) { return CYHAL_SDIO_RSLT_ERR_BAD_PARAM; } if (config->frequencyhal_hz != 0U) { - result = Cy_SD_Host_SdCardChangeClock(obj->base, obj->resource.block_num, config->frequencyhal_hz); + result = cyhal_sd_host_sdcardchangeclock(obj->base, obj->resource.block_num, config->frequencyhal_hz); obj->frequencyhal_hz = config->frequencyhal_hz; } @@ -1371,6 +1364,7 @@ cy_rslt_t cyhal_sdio_configure(cyhal_sdio_t *obj, const cyhal_sdio_cfg_t *config cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t direction, \ cyhal_sdio_command_t command, uint32_t argument, uint32_t* response) { + (void)direction; if (NULL == obj) { return CYHAL_SDIO_RSLT_ERR_BAD_PARAM; @@ -1423,7 +1417,7 @@ cy_rslt_t cyhal_sdio_send_cmd(const cyhal_sdio_t *obj, cyhal_transfer_t directio if (CY_SD_HOST_SUCCESS == result) { - result = Cy_SD_Host_PollCmdComplete(obj->base); + result = cyhal_sd_host_pollcmdcomplete(obj->base); } } @@ -1480,7 +1474,7 @@ cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction *response = 0UL; } - while ((CY_SD_HOST_SUCCESS != result) && (retry-- > 0UL)) + while ((CY_SD_HOST_SUCCESS != result) && (retry > 0UL)) { /* Add SDIO Error Handling * SDIO write timeout is expected when doing first write to register @@ -1544,13 +1538,14 @@ cy_rslt_t cyhal_sdio_bulk_transfer(cyhal_sdio_t *obj, cyhal_transfer_t direction result = Cy_SD_Host_SendCommand(obj->base, &cmd); if ( CY_SD_HOST_SUCCESS == result ) { - result = Cy_SD_Host_PollCmdComplete(obj->base); + result = cyhal_sd_host_pollcmdcomplete(obj->base); if ( CY_SD_HOST_SUCCESS == result ) { - result = Cy_SD_Host_PollTransferComplete(obj->base, SDIO_RW_TIMEOUT_US); + result = cyhal_sd_host_polltransfercomplete(obj->base, SDIO_RW_TIMEOUT_US); } } + retry--; } if (response != NULL ) @@ -1621,7 +1616,7 @@ cy_rslt_t cyhal_sdio_transfer_async(cyhal_sdio_t *obj, cyhal_transfer_t directio dat.enReliableWrite = false; dat.enableDma = true; - while ((CY_SD_HOST_SUCCESS != result) && (retry-- > 0UL)) + while ((CY_SD_HOST_SUCCESS != result) && (retry > 0UL)) { /* Check if an error occurred on any previous transactions or reset after the first unsuccessful bulk transfer try */ if( (Cy_SD_Host_GetNormalInterruptStatus(obj->base) & CY_SD_HOST_ERR_INTERRUPT) || @@ -1671,6 +1666,7 @@ cy_rslt_t cyhal_sdio_transfer_async(cyhal_sdio_t *obj, cyhal_transfer_t directio (void)Cy_SD_Host_InitDataTransfer(obj->base, &dat); result = Cy_SD_Host_SendCommand(obj->base, &cmd); + retry--; } if (CY_SD_HOST_SUCCESS != result) @@ -1702,7 +1698,7 @@ bool cyhal_sdio_is_busy(const cyhal_sdio_t *obj) if (!isCmdComplete) { - result = Cy_SD_Host_PollCmdComplete(obj->base); + result = cyhal_sd_host_pollcmdcomplete(obj->base); if (CY_SD_HOST_SUCCESS == result) { @@ -1712,7 +1708,7 @@ bool cyhal_sdio_is_busy(const cyhal_sdio_t *obj) if (isCmdComplete) { - result = Cy_SD_Host_PollTransferComplete(obj->base, SDIO_RW_TIMEOUT_US); + result = cyhal_sd_host_polltransfercomplete(obj->base, SDIO_RW_TIMEOUT_US); if (CY_SD_HOST_SUCCESS == result) { @@ -1785,6 +1781,7 @@ void cyhal_sdio_enable_event(cyhal_sdio_t *obj, cyhal_sdio_irq_event_t event, ui obj->irq_cause &= ~event; } + Cy_SD_Host_ClearNormalInterruptStatus(obj->base, interruptMask); Cy_SD_Host_SetNormalInterruptMask(obj->base, interruptMask); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_spi.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_spi.c similarity index 97% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_spi.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_spi.c index c11081404b3..53e666e5ec7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_spi.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_spi.c @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -203,6 +203,7 @@ cy_rslt_t cyhal_spi_init(cyhal_spi_t *obj, cyhal_gpio_t mosi, cyhal_gpio_t miso, uint8_t bits, cyhal_spi_mode_t mode, bool is_slave) { CY_ASSERT(NULL != obj); + memset(obj, 0, sizeof(cyhal_spi_t)); cy_rslt_t result = CY_RSLT_SUCCESS; cyhal_resource_inst_t pin_rsc; @@ -436,33 +437,12 @@ void cyhal_spi_free(cyhal_spi_t *obj) cyhal_hwmgr_free(&(obj->resource)); obj->resource.type = CYHAL_RSC_INVALID; } - if (CYHAL_NC_PIN_VALUE != obj->pin_miso) - { - cyhal_utils_disconnect_and_free(obj->pin_miso); - obj->pin_miso = CYHAL_NC_PIN_VALUE; - } - if (CYHAL_NC_PIN_VALUE != obj->pin_mosi) - { - cyhal_utils_disconnect_and_free(obj->pin_mosi); - obj->pin_mosi = CYHAL_NC_PIN_VALUE; - } - if (CYHAL_NC_PIN_VALUE != obj->pin_sclk) - { - cyhal_utils_disconnect_and_free(obj->pin_sclk); - obj->pin_sclk = CYHAL_NC_PIN_VALUE; - } - if (CYHAL_NC_PIN_VALUE != obj->pin_ssel) - { - if (obj->is_slave) - { - cyhal_utils_disconnect_and_free(obj->pin_ssel); - obj->pin_ssel = CYHAL_NC_PIN_VALUE; - } - else - { - cyhal_gpio_free(obj->pin_ssel); - } - } + + cyhal_utils_release_if_used(&(obj->pin_miso)); + cyhal_utils_release_if_used(&(obj->pin_mosi)); + cyhal_utils_release_if_used(&(obj->pin_sclk)); + cyhal_utils_release_if_used(&(obj->pin_ssel)); + if (obj->alloc_clock) { cyhal_hwmgr_free_clock(&(obj->clock)); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_system.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_system.c similarity index 81% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_system.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_system.c index cdd57a5eaee..c4e95948008 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_system.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_system.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -27,6 +27,9 @@ #include "cyhal_system.h" #include "cyhal_hwmgr.h" +#ifdef CY_RTOS_AWARE +#include "cyabs_rtos.h" +#endif #ifdef CY_IP_MXS40SRSS @@ -51,6 +54,16 @@ cy_rslt_t cyhal_system_unregister_callback(cyhal_system_callback_t const *handle : CYHAL_SYSTEM_RSLT_ERROR; } +cy_rslt_t cyhal_system_delay_ms(uint32_t milliseconds) +{ +#ifdef CY_RTOS_AWARE + return cy_rtos_delay_milliseconds(milliseconds); +#else + Cy_SysLib_Delay(milliseconds); + return CY_RSLT_SUCCESS; +#endif +} + uint32_t get_src_freq(cy_en_clkpath_in_sources_t source) { /* get the frequency of the source, i.e., the path mux input */ @@ -67,7 +80,7 @@ uint32_t get_src_freq(cy_en_clkpath_in_sources_t source) } } -uint32_t get_clkpath_freq(cy_en_clkhf_in_sources_t path, uint32_t freq, uint8_t *fll_pll_used) +static uint32_t get_clkpath_freq(cy_en_clkhf_in_sources_t path, uint32_t freq, uint8_t *fll_pll_used) { *fll_pll_used = 0xff; if (path == CY_SYSCLK_CLKHF_IN_CLKPATH0) @@ -97,7 +110,7 @@ uint32_t get_clkpath_freq(cy_en_clkhf_in_sources_t path, uint32_t freq, uint8_t return freq; } -cy_rslt_t try_set_hf_divider(uint8_t clock, uint32_t input_freq, uint32_t target_freq) +static cy_rslt_t try_set_hf_divider(uint8_t clock, uint32_t input_freq, uint32_t target_freq) { bool divider_found = false; cy_en_clkhf_dividers_t divider; @@ -134,7 +147,7 @@ cy_rslt_t try_set_hf_divider(uint8_t clock, uint32_t input_freq, uint32_t target } } -cy_rslt_t try_set_fll(uint8_t clock, uint32_t target_freq) +static cy_rslt_t try_set_fll(uint8_t clock, uint32_t target_freq) { Cy_SysClk_FllDisable(); Cy_SysClk_ClkHfSetSource(clock, CY_SYSCLK_CLKHF_IN_CLKPATH0); @@ -153,7 +166,7 @@ cy_rslt_t try_set_fll(uint8_t clock, uint32_t target_freq) return rslt; } -cy_rslt_t try_set_pll(uint8_t clock, uint8_t pll, uint32_t target_freq) +static cy_rslt_t try_set_pll(uint8_t clock, uint8_t pll, uint32_t target_freq) { Cy_SysClk_PllDisable(pll); Cy_SysClk_ClkHfSetSource(clock, (cy_en_clkhf_in_sources_t)(pll)); @@ -180,7 +193,7 @@ cy_rslt_t try_set_pll(uint8_t clock, uint8_t pll, uint32_t target_freq) } /* This should be part of the PDL */ -static inline bool Cy_SysClk_ClkHfIsEnabled(uint32_t clkHf) +static inline bool cyhal_sysclk_clkhfisenabled(uint32_t clkHf) { bool retVal = false; if (clkHf < CY_SRSS_NUM_HFROOT) @@ -216,7 +229,7 @@ cy_rslt_t cyhal_system_clock_set_frequency(uint8_t clock, uint32_t frequency_hz) return rslt; } - bool enabled = Cy_SysClk_ClkHfIsEnabled(clock); + bool enabled = cyhal_sysclk_clkhfisenabled(clock); if (enabled && fll_pll_used == 0) { return try_set_fll(clock, frequency_hz); @@ -292,6 +305,39 @@ cy_rslt_t cyhal_system_clock_set_divider(cyhal_system_clock_t clock, cyhal_syste return CY_RSLT_SUCCESS; } +cyhal_reset_reason_t cyhal_system_get_reset_reason(void) +{ + uint32_t pdl_reason = Cy_SysLib_GetResetReason(); + cyhal_reset_reason_t reason = CYHAL_SYSTEM_RESET_NONE; + + if (CY_SYSLIB_RESET_ACT_FAULT & pdl_reason) + reason |= CYHAL_SYSTEM_RESET_ACTIVE_FAULT; + if (CY_SYSLIB_RESET_DPSLP_FAULT & pdl_reason) + reason |= CYHAL_SYSTEM_RESET_DEEPSLEEP_FAULT; + if (CY_SYSLIB_RESET_SOFT & pdl_reason) + reason |= CYHAL_SYSTEM_RESET_SOFT; + if (CY_SYSLIB_RESET_HIB_WAKEUP & pdl_reason) + reason |= CYHAL_SYSTEM_RESET_HIB_WAKEUP; + if ((CY_SYSLIB_RESET_HWWDT | CY_SYSLIB_RESET_SWWDT0 | CY_SYSLIB_RESET_SWWDT1 | + CY_SYSLIB_RESET_SWWDT2 | CY_SYSLIB_RESET_SWWDT3) & pdl_reason) + reason |= CYHAL_SYSTEM_RESET_WDT; +#if (SRSS_WCOCSV_PRESENT != 0U) + if (CY_SYSLIB_RESET_CSV_WCO_LOSS & pdl_reason) + reason |= CYHAL_SYSTEM_RESET_WCO_ERR; +#endif +#if (SRSS_MASK_HFCSV != 0) + if ((CY_SYSLIB_RESET_HFCLK_LOSS | CY_SYSLIB_RESET_HFCLK_ERR) & pdl_reason) + reason |= CYHAL_SYSTEM_RESET_SYS_CLK_ERR; +#endif + + return reason; +} + +void cyhal_system_clear_reset_reason(void) +{ + Cy_SysLib_ClearResetReason(); +} + #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_tcpwm_common.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_tcpwm_common.c similarity index 85% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_tcpwm_common.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_tcpwm_common.c index 26e2670f1c9..00368586ec2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_tcpwm_common.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_tcpwm_common.c @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -79,24 +79,27 @@ void cyhal_tcpwm_irq_handler() channel = irqn - CYHAL_TCPWM_DATA[block].isr_offset; break; } - else - { - CY_ASSERT(block != CY_IP_MXTCPWM_INSTANCES - 1); // IRQn should always be in one of those ranges - } } - TCPWM_Type *blockAddr = CYHAL_TCPWM_DATA[block].base; - uint32_t index = GET_ARRAY_INDEX(block, channel); + if (block < CY_IP_MXTCPWM_INSTANCES) + { + TCPWM_Type *blockAddr = CYHAL_TCPWM_DATA[block].base; + uint32_t index = GET_ARRAY_INDEX(block, channel); + + cyhal_event_callback_data_t *callback_data = cyhal_tcpwm_callback_data_structs[index]; + if (callback_data->callback != NULL) + { + cyhal_tcpwm_event_callback_t callback = (cyhal_tcpwm_event_callback_t) callback_data->callback; + /* Call registered callbacks here */ + (void) (callback) (callback_data->callback_arg, Cy_TCPWM_GetInterruptStatus(blockAddr, channel)); + } - cyhal_event_callback_data_t *callback_data = cyhal_tcpwm_callback_data_structs[index]; - if (callback_data->callback != NULL) + Cy_TCPWM_ClearInterrupt(blockAddr, channel, CY_TCPWM_INT_ON_CC_OR_TC); + } + else { - cyhal_tcpwm_event_callback_t callback = (cyhal_tcpwm_event_callback_t) callback_data->callback; - /* Call registered callbacks here */ - (void) (callback) (callback_data->callback_arg, Cy_TCPWM_GetInterruptStatus(blockAddr, channel)); + CY_HALT(); // Could not determine the block/channel for IRQn } - - Cy_TCPWM_ClearInterrupt(blockAddr, channel, CY_TCPWM_INT_ON_CC_OR_TC); } /******************************************************************************* diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_timer.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_timer.c similarity index 94% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_timer.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_timer.c index 1491d45890d..a7a755edb75 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_timer.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_timer.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -59,7 +59,7 @@ static const cy_stc_tcpwm_counter_config_t default_config = }; /** Convert timer direction from the HAL enum to the corresponding PDL constant - * + * * @param[in] direction The direction, as a HAL enum value * @return The direction, as a PDL constant */ @@ -85,7 +85,7 @@ cy_rslt_t cyhal_timer_init(cyhal_timer_t *obj, cyhal_gpio_t pin, const cyhal_clo { CY_ASSERT(NULL != obj); - //TODO: Handle Trigger mux pin assignments + // No support currently for pin connections on this device if (CYHAL_NC_PIN_VALUE != pin) return CYHAL_TIMER_RSLT_ERR_BAD_ARGUMENT; @@ -148,7 +148,7 @@ void cyhal_timer_free(cyhal_timer_t *obj) IRQn_Type irqn = (IRQn_Type)(CYHAL_TCPWM_DATA[obj->resource.block_num].isr_offset + obj->resource.channel_num); NVIC_DisableIRQ(irqn); - if (NULL != obj && NULL != obj->base) + if (NULL != obj->base) { Cy_TCPWM_Counter_Disable(obj->base, obj->resource.channel_num); @@ -159,6 +159,7 @@ void cyhal_timer_free(cyhal_timer_t *obj) if (obj->dedicated_clock) { cy_en_sysclk_status_t rslt = Cy_SysClk_PeriphDisableDivider(obj->clock.div_type, obj->clock.div_num); + CY_UNUSED_PARAMETER(rslt); /* CY_ASSERT only processes in DEBUG, ignores for others */ CY_ASSERT(CY_SYSCLK_SUCCESS == rslt); cyhal_hwmgr_free_clock(&(obj->clock)); obj->dedicated_clock = false; @@ -217,6 +218,7 @@ cy_rslt_t cyhal_timer_set_frequency(cyhal_timer_t *obj, uint32_t hz) { uint32_t div = Cy_SysClk_ClkPeriGetFrequency() / hz; if (0 == div || + CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphDisableDivider(obj->clock.div_type, obj->clock.div_num) || CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, div - 1) || CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num)) { @@ -245,6 +247,12 @@ cy_rslt_t cyhal_timer_stop(cyhal_timer_t *obj) return CY_RSLT_SUCCESS; } +uint32_t cyhal_timer_read(const cyhal_timer_t *obj) +{ + CY_ASSERT(NULL != obj); + return Cy_TCPWM_Counter_GetCounter(obj->base, obj->resource.channel_num); +} + #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_trng.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_trng.c similarity index 97% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_trng.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_trng.c index c18117eb576..6248b3d0b18 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_trng.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_trng.c @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_uart.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_uart.c similarity index 97% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_uart.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_uart.c index 8b1522aaf61..f5897ee09cc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_uart.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_uart.c @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -322,22 +322,12 @@ void cyhal_uart_free(cyhal_uart_t *obj) cyhal_hwmgr_free(&(obj->resource)); Cy_SysPm_UnregisterCallback(&(obj->pm_callback)); } - if (CYHAL_NC_PIN_VALUE != obj->pin_rx) - { - cyhal_utils_disconnect_and_free(obj->pin_rx); - } - if (CYHAL_NC_PIN_VALUE != obj->pin_tx) - { - cyhal_utils_disconnect_and_free(obj->pin_tx); - } - if (CYHAL_NC_PIN_VALUE != obj->pin_rts) - { - cyhal_utils_disconnect_and_free(obj->pin_rts); - } - if (CYHAL_NC_PIN_VALUE != obj->pin_cts) - { - cyhal_utils_disconnect_and_free(obj->pin_cts); - } + + cyhal_utils_release_if_used(&(obj->pin_rx)); + cyhal_utils_release_if_used(&(obj->pin_tx)); + cyhal_utils_release_if_used(&(obj->pin_rts)); + cyhal_utils_release_if_used(&(obj->pin_cts)); + if (!(obj->is_user_clock)) { cyhal_hwmgr_free_clock(&(obj->clock)); @@ -634,7 +624,7 @@ cy_rslt_t cyhal_uart_read_async(cyhal_uart_t *obj, void *rx, size_t length) bool cyhal_uart_is_tx_active(cyhal_uart_t *obj) { - return (0UL != (obj->context.txStatus & CY_SCB_UART_TRANSMIT_ACTIVE)) || !Cy_SCB_IsTxComplete(obj->base); + return (0UL != (obj->context.txStatus & CY_SCB_UART_TRANSMIT_ACTIVE)); } bool cyhal_uart_is_rx_active(cyhal_uart_t *obj) @@ -708,10 +698,12 @@ void cyhal_uart_enable_event(cyhal_uart_t *obj, cyhal_uart_event_t event, uint8_ obj->irq_cause |= event; if (event & CYHAL_UART_IRQ_RX_NOT_EMPTY) { + Cy_SCB_ClearRxInterrupt(obj->base, CY_SCB_RX_INTR_NOT_EMPTY); Cy_SCB_SetRxInterruptMask(obj->base, Cy_SCB_GetRxInterruptMask(obj->base) | CY_SCB_RX_INTR_NOT_EMPTY); } if (event & CYHAL_UART_IRQ_TX_EMPTY) { + Cy_SCB_ClearTxInterrupt(obj->base, CY_SCB_UART_TX_EMPTY); Cy_SCB_SetTxInterruptMask(obj->base, Cy_SCB_GetTxInterruptMask(obj->base) | CY_SCB_UART_TX_EMPTY); } } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_udb_sdio.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_udb_sdio.c similarity index 94% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_udb_sdio.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_udb_sdio.c index 5725c0c913b..9402f609aa0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_udb_sdio.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_udb_sdio.c @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,6 +24,7 @@ *******************************************************************************/ #include "cyhal_hwmgr.h" +#include "cy_utils.h" #if defined(CYHAL_UDB_SDIO) @@ -39,9 +40,6 @@ extern "C" #include "cyhal_gpio.h" #include "cyhal_interconnect.h" -/* Not connected pin define */ -#define SDIO_PINS_NC ((cyhal_gpio_t) CYHAL_NC_PIN_VALUE) - #define CY_HAL_SDIO_CLK_DIV_VALUE ((uint8_t) 0xFF) /* Not configured clock divider define*/ @@ -128,7 +126,6 @@ static const cy_stc_gpio_pin_config_t pin_clk_config = /******************************************************************************* * Internal functions *******************************************************************************/ -static void cyhal_free_pins(cyhal_sdio_t *obj); static cy_en_syspm_status_t cyhal_sdio_ds_callback(cy_stc_syspm_callback_params_t *callbackParams, cy_en_syspm_callback_mode_t mode); /****************************************************************************** @@ -235,22 +232,6 @@ static void cyhal_sdio_interrupts_dispatcher_IRQHandler(void) } } -static void cyhal_free_pins(cyhal_sdio_t *obj) -{ - cyhal_gpio_free(obj->pin_clk); - obj->pin_clk = SDIO_PINS_NC; - cyhal_gpio_free(obj->pin_cmd); - obj->pin_cmd = SDIO_PINS_NC; - cyhal_gpio_free(obj->pin_data0); - obj->pin_data0 = SDIO_PINS_NC; - cyhal_gpio_free(obj->pin_data1); - obj->pin_data1 = SDIO_PINS_NC; - cyhal_gpio_free(obj->pin_data2); - obj->pin_data2 = SDIO_PINS_NC; - cyhal_gpio_free(obj->pin_data3); - obj->pin_data3 = SDIO_PINS_NC; -} - static void cyhal_free_clocks(cyhal_sdio_t *obj) { cyhal_resource_inst_t udbClkRsc; @@ -260,10 +241,10 @@ static void cyhal_free_clocks(cyhal_sdio_t *obj) cyhal_hwmgr_free(&udbClkRsc); } -static void cyhal_free_dmas(cyhal_sdio_t *obj) +static void cyhal_free_dmas() { cyhal_resource_inst_t dmaRsc; - dmaRsc.type = CYHAL_RSC_DMA; + dmaRsc.type = CYHAL_RSC_DW; dmaRsc.block_num = 0; dmaRsc.channel_num = 0; @@ -295,12 +276,12 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, * SDIO. */ obj->resource.type = CYHAL_RSC_INVALID; - obj->pin_cmd = SDIO_PINS_NC; - obj->pin_clk = SDIO_PINS_NC; - obj->pin_data0 = SDIO_PINS_NC; - obj->pin_data1 = SDIO_PINS_NC; - obj->pin_data2 = SDIO_PINS_NC; - obj->pin_data3 = SDIO_PINS_NC; + obj->pin_cmd = CYHAL_NC_PIN_VALUE; + obj->pin_clk = CYHAL_NC_PIN_VALUE; + obj->pin_data0 = CYHAL_NC_PIN_VALUE; + obj->pin_data1 = CYHAL_NC_PIN_VALUE; + obj->pin_data2 = CYHAL_NC_PIN_VALUE; + obj->pin_data3 = CYHAL_NC_PIN_VALUE; obj->dma0Ch0.resource.type = CYHAL_RSC_INVALID; obj->dma0Ch1.resource.type = CYHAL_RSC_INVALID; obj->dma1Ch1.resource.type = CYHAL_RSC_INVALID; @@ -336,28 +317,28 @@ cy_rslt_t cyhal_sdio_init(cyhal_sdio_t *obj, cyhal_gpio_t cmd, cyhal_gpio_t clk, if (retVal == CY_RSLT_SUCCESS) { /* Reserve DMA0 CH0 */ - cyhal_resource_inst_t dmaRsc = { CYHAL_RSC_DMA, 0, 0 }; + cyhal_resource_inst_t dmaRsc = { CYHAL_RSC_DW, 0, 0 }; retVal = cyhal_hwmgr_reserve(&dmaRsc); } if (retVal == CY_RSLT_SUCCESS) { /* Reserve DMA0 CH1 */ - cyhal_resource_inst_t dmaRsc = { CYHAL_RSC_DMA, 0, 1 }; + cyhal_resource_inst_t dmaRsc = { CYHAL_RSC_DW, 0, 1 }; retVal = cyhal_hwmgr_reserve(&dmaRsc); } if (retVal == CY_RSLT_SUCCESS) { /* Reserve DMA1 CH1 */ - cyhal_resource_inst_t dmaRsc = { CYHAL_RSC_DMA, 1, 1 }; + cyhal_resource_inst_t dmaRsc = { CYHAL_RSC_DW, 1, 1 }; retVal = cyhal_hwmgr_reserve(&dmaRsc); } if (retVal == CY_RSLT_SUCCESS) { /* Reserve DMA1 CH3 */ - cyhal_resource_inst_t dmaRsc = { CYHAL_RSC_DMA, 1, 3 }; + cyhal_resource_inst_t dmaRsc = { CYHAL_RSC_DW, 1, 3 }; retVal = cyhal_hwmgr_reserve(&dmaRsc); } @@ -502,9 +483,15 @@ void cyhal_sdio_free(cyhal_sdio_t *obj) NVIC_DisableIRQ(cpuss_interrupts_dw1_1_IRQn); NVIC_DisableIRQ(cpuss_interrupts_dw1_3_IRQn); - cyhal_free_pins(obj); + cyhal_utils_release_if_used(&(obj->pin_clk)); + cyhal_utils_release_if_used(&(obj->pin_cmd)); + cyhal_utils_release_if_used(&(obj->pin_data0)); + cyhal_utils_release_if_used(&(obj->pin_data1)); + cyhal_utils_release_if_used(&(obj->pin_data2)); + cyhal_utils_release_if_used(&(obj->pin_data3)); + cyhal_free_clocks(obj); - cyhal_free_dmas(obj); + cyhal_free_dmas(); cyhal_hwmgr_free(&(obj->resource)); SDIO_Free(); @@ -675,12 +662,14 @@ cy_rslt_t cyhal_sdio_transfer_async(cyhal_sdio_t *obj, cyhal_transfer_t directio bool cyhal_sdio_is_busy(const cyhal_sdio_t *obj) { /* UDB SDIO does not support async transfers */ + CY_UNUSED_PARAMETER(obj); return false; } cy_rslt_t cyhal_sdio_abort_async(const cyhal_sdio_t *obj) { /* Reset UDB SDIO */ + CY_UNUSED_PARAMETER(obj); SDIO_Reset(); return CY_RSLT_SUCCESS; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_usb_dev.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_usb_dev.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_usb_dev.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_usb_dev.c index 884bec75c76..29a30358abd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_usb_dev.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_usb_dev.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2019 Cypress Semiconductor Corporation +* Copyright 2019-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -470,15 +470,8 @@ static void cyhal_usb_dev_free_resources(cyhal_usb_dev_t *obj) cyhal_hwmgr_free_clock(&(obj->clock)); } - if (CYHAL_NC_PIN_VALUE != obj->pin_dp) - { - cyhal_utils_disconnect_and_free(obj->pin_dp); - } - - if (CYHAL_NC_PIN_VALUE != obj->pin_dm) - { - cyhal_utils_disconnect_and_free(obj->pin_dm); - } + cyhal_utils_release_if_used(&(obj->pin_dp)); + cyhal_utils_release_if_used(&(obj->pin_dm)); } cy_rslt_t cyhal_usb_dev_init(cyhal_usb_dev_t *obj, cyhal_gpio_t dp, cyhal_gpio_t dm, const cyhal_clock_divider_t *clk) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_utils.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_utils.c similarity index 60% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_utils.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_utils.c index 2492d4952eb..adba880a49e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_utils.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_utils.c @@ -6,7 +6,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -22,10 +22,10 @@ * limitations under the License. *******************************************************************************/ -#include "cy_result.h" #include "cyhal_utils.h" #include "cyhal_hwmgr.h" #include "cyhal_interconnect.h" +#include "cyhal_gpio.h" #if defined(__cplusplus) extern "C" @@ -44,14 +44,46 @@ const cyhal_resource_pin_mapping_t *cyhal_utils_get_resource(cyhal_gpio_t pin, c return NULL; } +cy_rslt_t cyhal_utils_reserve_and_connect(cyhal_gpio_t pin, const cyhal_resource_pin_mapping_t *mapping) +{ + cyhal_resource_inst_t pinRsc = cyhal_utils_get_gpio_resource(pin); + cy_rslt_t status = cyhal_hwmgr_reserve(&pinRsc); + if (CY_RSLT_SUCCESS == status) + { + status = cyhal_connect_pin(mapping); + if (CY_RSLT_SUCCESS != status) + { + cyhal_hwmgr_free(&pinRsc); + } + } + return status; +} + void cyhal_utils_disconnect_and_free(cyhal_gpio_t pin) { cy_rslt_t rslt = cyhal_disconnect_pin(pin); + CY_UNUSED_PARAMETER(rslt); /* CY_ASSERT only processes in DEBUG, ignores for others */ CY_ASSERT(CY_RSLT_SUCCESS == rslt); cyhal_resource_inst_t rsc = cyhal_utils_get_gpio_resource(pin); cyhal_hwmgr_free(&rsc); } +void cyhal_utils_release_if_used(cyhal_gpio_t *pin) +{ + if (CYHAL_NC_PIN_VALUE != *pin) + { + cyhal_utils_disconnect_and_free(*pin); + *pin = CYHAL_NC_PIN_VALUE; + } +} + +bool cyhal_utils_resources_equal(const cyhal_resource_inst_t *resource1, const cyhal_resource_inst_t *resource2) +{ + return (resource1->type == resource2->type) && + (resource1->block_num == resource2->block_num) && + (resource1->channel_num == resource2->channel_num); +} + #if defined(__cplusplus) } #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_wdt.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_wdt.c similarity index 95% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_wdt.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_wdt.c index 731122736a2..794051fbaae 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_wdt.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/cyhal_wdt.c @@ -10,7 +10,7 @@ * ******************************************************************************** * \copyright -* Copyright 2019 Cypress Semiconductor Corporation +* Copyright 2019-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -27,8 +27,8 @@ *******************************************************************************/ /** -* \addtogroup group_hal_psoc6_wdt (WDT) Watchdog Timer -* \ingroup group_hal_psoc6 +* \addtogroup group_hal_psoc6_wdt WDT (Watchdog Timer) +* \ingroup group_hal_psoc6 * \{ * The PSoC 6 WDT is only capable of supporting certain timeout ranges below its maximum timeout of 6000ms. * As a result, any unsupported timeouts given to the HAL WDT are rounded up to the nearest supported value. @@ -87,6 +87,7 @@ #include "cyhal_wdt.h" #include "cy_wdt.h" #include "cy_lvd.h" +#include "cy_utils.h" #if defined(__cplusplus) extern "C" { @@ -187,6 +188,7 @@ cy_rslt_t cyhal_wdt_init(cyhal_wdt_t *obj, uint32_t timeout_ms) void cyhal_wdt_free(cyhal_wdt_t *obj) { + CY_UNUSED_PARAMETER(obj); cyhal_wdt_stop(obj); cyhal_wdt_initialized = false; @@ -194,11 +196,13 @@ void cyhal_wdt_free(cyhal_wdt_t *obj) void cyhal_wdt_kick(cyhal_wdt_t *obj) { + CY_UNUSED_PARAMETER(obj); Cy_WDT_ClearWatchdog(); } void cyhal_wdt_start(cyhal_wdt_t *obj) { + CY_UNUSED_PARAMETER(obj); Cy_WDT_Unlock(); Cy_WDT_Enable(); Cy_WDT_Lock(); @@ -206,12 +210,14 @@ void cyhal_wdt_start(cyhal_wdt_t *obj) void cyhal_wdt_stop(cyhal_wdt_t *obj) { + CY_UNUSED_PARAMETER(obj); Cy_WDT_Unlock(); Cy_WDT_Disable(); } uint32_t cyhal_wdt_get_timeout_ms(cyhal_wdt_t *obj) { + CY_UNUSED_PARAMETER(obj); return cyhal_wdt_initial_timeout_ms; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_104_m_csp_ble.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_104_m_csp_ble.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_104_m_csp_ble.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_104_m_csp_ble.c index aba6f0c0983..d403b9754b1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_104_m_csp_ble.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_104_m_csp_ble.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.c index 52632bfbe31..b0b16967a73 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_104_m_csp_ble_usb.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_116_bga_ble.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_116_bga_ble.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_116_bga_ble.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_116_bga_ble.c index d3739e8152e..f99c7e46e26 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_116_bga_ble.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_116_bga_ble.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_116_bga_usb.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_116_bga_usb.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_116_bga_usb.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_116_bga_usb.c index cfbe3be6e61..fd7d26cbfd8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_116_bga_usb.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_116_bga_usb.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_124_bga.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_124_bga.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_124_bga.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_124_bga.c index 5c60a3377b7..ee1079ad01f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_124_bga.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_124_bga.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_124_bga_sip.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_124_bga_sip.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_124_bga_sip.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_124_bga_sip.c index b054780a44e..f9cefebc946 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_124_bga_sip.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_124_bga_sip.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_43_smt.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_43_smt.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_43_smt.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_43_smt.c index 99139febff6..1ea1fe0099b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_43_smt.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_43_smt.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_68_qfn_ble.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_68_qfn_ble.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_68_qfn_ble.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_68_qfn_ble.c index f16ceef0711..5720e7acaf7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_68_qfn_ble.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_68_qfn_ble.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_80_wlcsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_80_wlcsp.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_80_wlcsp.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_80_wlcsp.c index 32f8410d03c..ebbe5ea36e0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_01_80_wlcsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_01_80_wlcsp.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_100_wlcsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_02_100_wlcsp.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_100_wlcsp.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_02_100_wlcsp.c index eff52802c56..10cce481542 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_100_wlcsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_02_100_wlcsp.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_124_bga.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_02_124_bga.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_124_bga.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_02_124_bga.c index 04c906e0ef6..a4e9d65f4d3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_124_bga.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_02_124_bga.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_128_tqfp.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_02_128_tqfp.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_128_tqfp.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_02_128_tqfp.c index 4a0fe2db8d8..a2003cb859b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_128_tqfp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_02_128_tqfp.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_68_qfn.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_02_68_qfn.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_68_qfn.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_02_68_qfn.c index b08ff8ecb63..1a57ede4958 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_02_68_qfn.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_02_68_qfn.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_03_100_tqfp.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_03_100_tqfp.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_03_100_tqfp.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_03_100_tqfp.c index b3dd0ba45f0..74c69f0fdbb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_03_100_tqfp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_03_100_tqfp.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_03_49_wlcsp.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_03_49_wlcsp.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_03_49_wlcsp.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_03_49_wlcsp.c index 4cc2c807926..2af3573012e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_03_49_wlcsp.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_03_49_wlcsp.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_03_68_qfn.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_03_68_qfn.c similarity index 99% rename from targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_03_68_qfn.c rename to targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_03_68_qfn.c index f9ff30a847e..27958478814 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/pin_packages/cyhal_psoc6_03_68_qfn.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/pin_packages/cyhal_psoc6_03_68_qfn.c @@ -9,7 +9,7 @@ * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/triggers/cyhal_triggers_psoc6_01.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/triggers/cyhal_triggers_psoc6_01.c new file mode 100644 index 00000000000..7953c1e6b32 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/triggers/cyhal_triggers_psoc6_01.c @@ -0,0 +1,999 @@ +/***************************************************************************//** +* \file cyhal_triggers_psoc6_01.c +* +* \brief +* PSoC6_01 family HAL triggers header +* +* \note +* Generator version: 1.5.7254.19579 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include "cy_device_headers.h" +#include "cyhal_hw_types.h" + +#ifdef CY_DEVICE_PSOC6ABLE2 +#include "triggers/cyhal_triggers_psoc6_01.h" + +const uint8_t cyhal_dest_to_mux[479] = +{ + 5, /* TRIGGER_CPUSS_CTI_TR_IN0 */ + 5, /* TRIGGER_CPUSS_CTI_TR_IN1 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN0 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN1 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN2 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN3 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN4 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN5 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN6 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN7 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN8 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN9 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN10 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN11 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN12 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN13 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN14 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN15 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN0 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN1 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN2 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN3 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN4 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN5 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN6 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN7 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN8 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN9 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN10 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN11 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN12 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN13 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN14 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN15 */ + 6, /* TRIGGER_PASS_TR_SAR_IN */ + 8, /* TRIGGER_PERI_TR_IO_OUTPUT0 */ + 8, /* TRIGGER_PERI_TR_IO_OUTPUT1 */ + 4, /* TRIGGER_PROFILE_TR_START */ + 4, /* TRIGGER_PROFILE_TR_STOP */ + 2, /* TRIGGER_TCPWM0_TR_IN0 */ + 2, /* TRIGGER_TCPWM0_TR_IN1 */ + 2, /* TRIGGER_TCPWM0_TR_IN2 */ + 2, /* TRIGGER_TCPWM0_TR_IN3 */ + 2, /* TRIGGER_TCPWM0_TR_IN4 */ + 2, /* TRIGGER_TCPWM0_TR_IN5 */ + 2, /* TRIGGER_TCPWM0_TR_IN6 */ + 2, /* TRIGGER_TCPWM0_TR_IN7 */ + 2, /* TRIGGER_TCPWM0_TR_IN8 */ + 2, /* TRIGGER_TCPWM0_TR_IN9 */ + 2, /* TRIGGER_TCPWM0_TR_IN10 */ + 2, /* TRIGGER_TCPWM0_TR_IN11 */ + 2, /* TRIGGER_TCPWM0_TR_IN12 */ + 2, /* TRIGGER_TCPWM0_TR_IN13 */ + 3, /* TRIGGER_TCPWM1_TR_IN0 */ + 3, /* TRIGGER_TCPWM1_TR_IN1 */ + 3, /* TRIGGER_TCPWM1_TR_IN2 */ + 3, /* TRIGGER_TCPWM1_TR_IN3 */ + 3, /* TRIGGER_TCPWM1_TR_IN4 */ + 3, /* TRIGGER_TCPWM1_TR_IN5 */ + 3, /* TRIGGER_TCPWM1_TR_IN6 */ + 3, /* TRIGGER_TCPWM1_TR_IN7 */ + 3, /* TRIGGER_TCPWM1_TR_IN8 */ + 3, /* TRIGGER_TCPWM1_TR_IN9 */ + 3, /* TRIGGER_TCPWM1_TR_IN10 */ + 3, /* TRIGGER_TCPWM1_TR_IN11 */ + 3, /* TRIGGER_TCPWM1_TR_IN12 */ + 3, /* TRIGGER_TCPWM1_TR_IN13 */ + 10, /* TRIGGER_TR_GROUP0_INPUT1 */ + 10, /* TRIGGER_TR_GROUP0_INPUT2 */ + 10, /* TRIGGER_TR_GROUP0_INPUT3 */ + 10, /* TRIGGER_TR_GROUP0_INPUT4 */ + 10, /* TRIGGER_TR_GROUP0_INPUT5 */ + 10, /* TRIGGER_TR_GROUP0_INPUT6 */ + 10, /* TRIGGER_TR_GROUP0_INPUT7 */ + 10, /* TRIGGER_TR_GROUP0_INPUT8 */ + 11, /* TRIGGER_TR_GROUP0_INPUT9 */ + 11, /* TRIGGER_TR_GROUP0_INPUT10 */ + 11, /* TRIGGER_TR_GROUP0_INPUT11 */ + 11, /* TRIGGER_TR_GROUP0_INPUT12 */ + 11, /* TRIGGER_TR_GROUP0_INPUT13 */ + 11, /* TRIGGER_TR_GROUP0_INPUT14 */ + 11, /* TRIGGER_TR_GROUP0_INPUT15 */ + 11, /* TRIGGER_TR_GROUP0_INPUT16 */ + 11, /* TRIGGER_TR_GROUP0_INPUT17 */ + 11, /* TRIGGER_TR_GROUP0_INPUT18 */ + 11, /* TRIGGER_TR_GROUP0_INPUT19 */ + 11, /* TRIGGER_TR_GROUP0_INPUT20 */ + 11, /* TRIGGER_TR_GROUP0_INPUT21 */ + 11, /* TRIGGER_TR_GROUP0_INPUT22 */ + 11, /* TRIGGER_TR_GROUP0_INPUT23 */ + 11, /* TRIGGER_TR_GROUP0_INPUT24 */ + 12, /* TRIGGER_TR_GROUP0_INPUT25 */ + 12, /* TRIGGER_TR_GROUP0_INPUT26 */ + 13, /* TRIGGER_TR_GROUP0_INPUT27 */ + 13, /* TRIGGER_TR_GROUP0_INPUT28 */ + 13, /* TRIGGER_TR_GROUP0_INPUT29 */ + 13, /* TRIGGER_TR_GROUP0_INPUT30 */ + 13, /* TRIGGER_TR_GROUP0_INPUT31 */ + 13, /* TRIGGER_TR_GROUP0_INPUT32 */ + 13, /* TRIGGER_TR_GROUP0_INPUT33 */ + 13, /* TRIGGER_TR_GROUP0_INPUT34 */ + 13, /* TRIGGER_TR_GROUP0_INPUT35 */ + 13, /* TRIGGER_TR_GROUP0_INPUT36 */ + 13, /* TRIGGER_TR_GROUP0_INPUT37 */ + 13, /* TRIGGER_TR_GROUP0_INPUT38 */ + 13, /* TRIGGER_TR_GROUP0_INPUT39 */ + 13, /* TRIGGER_TR_GROUP0_INPUT40 */ + 13, /* TRIGGER_TR_GROUP0_INPUT41 */ + 13, /* TRIGGER_TR_GROUP0_INPUT42 */ + 14, /* TRIGGER_TR_GROUP0_INPUT43 */ + 14, /* TRIGGER_TR_GROUP0_INPUT44 */ + 14, /* TRIGGER_TR_GROUP0_INPUT45 */ + 14, /* TRIGGER_TR_GROUP0_INPUT46 */ + 14, /* TRIGGER_TR_GROUP0_INPUT47 */ + 14, /* TRIGGER_TR_GROUP0_INPUT48 */ + 14, /* TRIGGER_TR_GROUP0_INPUT49 */ + 14, /* TRIGGER_TR_GROUP0_INPUT50 */ + 10, /* TRIGGER_TR_GROUP1_INPUT1 */ + 10, /* TRIGGER_TR_GROUP1_INPUT2 */ + 10, /* TRIGGER_TR_GROUP1_INPUT3 */ + 10, /* TRIGGER_TR_GROUP1_INPUT4 */ + 10, /* TRIGGER_TR_GROUP1_INPUT5 */ + 10, /* TRIGGER_TR_GROUP1_INPUT6 */ + 10, /* TRIGGER_TR_GROUP1_INPUT7 */ + 10, /* TRIGGER_TR_GROUP1_INPUT8 */ + 11, /* TRIGGER_TR_GROUP1_INPUT9 */ + 11, /* TRIGGER_TR_GROUP1_INPUT10 */ + 11, /* TRIGGER_TR_GROUP1_INPUT11 */ + 11, /* TRIGGER_TR_GROUP1_INPUT12 */ + 11, /* TRIGGER_TR_GROUP1_INPUT13 */ + 11, /* TRIGGER_TR_GROUP1_INPUT14 */ + 11, /* TRIGGER_TR_GROUP1_INPUT15 */ + 11, /* TRIGGER_TR_GROUP1_INPUT16 */ + 11, /* TRIGGER_TR_GROUP1_INPUT17 */ + 11, /* TRIGGER_TR_GROUP1_INPUT18 */ + 11, /* TRIGGER_TR_GROUP1_INPUT19 */ + 11, /* TRIGGER_TR_GROUP1_INPUT20 */ + 11, /* TRIGGER_TR_GROUP1_INPUT21 */ + 11, /* TRIGGER_TR_GROUP1_INPUT22 */ + 11, /* TRIGGER_TR_GROUP1_INPUT23 */ + 11, /* TRIGGER_TR_GROUP1_INPUT24 */ + 12, /* TRIGGER_TR_GROUP1_INPUT25 */ + 12, /* TRIGGER_TR_GROUP1_INPUT26 */ + 13, /* TRIGGER_TR_GROUP1_INPUT27 */ + 13, /* TRIGGER_TR_GROUP1_INPUT28 */ + 13, /* TRIGGER_TR_GROUP1_INPUT29 */ + 13, /* TRIGGER_TR_GROUP1_INPUT30 */ + 13, /* TRIGGER_TR_GROUP1_INPUT31 */ + 13, /* TRIGGER_TR_GROUP1_INPUT32 */ + 13, /* TRIGGER_TR_GROUP1_INPUT33 */ + 13, /* TRIGGER_TR_GROUP1_INPUT34 */ + 13, /* TRIGGER_TR_GROUP1_INPUT35 */ + 13, /* TRIGGER_TR_GROUP1_INPUT36 */ + 13, /* TRIGGER_TR_GROUP1_INPUT37 */ + 13, /* TRIGGER_TR_GROUP1_INPUT38 */ + 13, /* TRIGGER_TR_GROUP1_INPUT39 */ + 13, /* TRIGGER_TR_GROUP1_INPUT40 */ + 13, /* TRIGGER_TR_GROUP1_INPUT41 */ + 13, /* TRIGGER_TR_GROUP1_INPUT42 */ + 14, /* TRIGGER_TR_GROUP1_INPUT43 */ + 14, /* TRIGGER_TR_GROUP1_INPUT44 */ + 14, /* TRIGGER_TR_GROUP1_INPUT45 */ + 14, /* TRIGGER_TR_GROUP1_INPUT46 */ + 14, /* TRIGGER_TR_GROUP1_INPUT47 */ + 14, /* TRIGGER_TR_GROUP1_INPUT48 */ + 14, /* TRIGGER_TR_GROUP1_INPUT49 */ + 14, /* TRIGGER_TR_GROUP1_INPUT50 */ + 10, /* TRIGGER_TR_GROUP2_INPUT1 */ + 10, /* TRIGGER_TR_GROUP2_INPUT2 */ + 10, /* TRIGGER_TR_GROUP2_INPUT3 */ + 10, /* TRIGGER_TR_GROUP2_INPUT4 */ + 10, /* TRIGGER_TR_GROUP2_INPUT5 */ + 10, /* TRIGGER_TR_GROUP2_INPUT6 */ + 10, /* TRIGGER_TR_GROUP2_INPUT7 */ + 10, /* TRIGGER_TR_GROUP2_INPUT8 */ + 11, /* TRIGGER_TR_GROUP2_INPUT9 */ + 11, /* TRIGGER_TR_GROUP2_INPUT10 */ + 11, /* TRIGGER_TR_GROUP2_INPUT11 */ + 11, /* TRIGGER_TR_GROUP2_INPUT12 */ + 11, /* TRIGGER_TR_GROUP2_INPUT13 */ + 11, /* TRIGGER_TR_GROUP2_INPUT14 */ + 11, /* TRIGGER_TR_GROUP2_INPUT15 */ + 11, /* TRIGGER_TR_GROUP2_INPUT16 */ + 11, /* TRIGGER_TR_GROUP2_INPUT17 */ + 11, /* TRIGGER_TR_GROUP2_INPUT18 */ + 11, /* TRIGGER_TR_GROUP2_INPUT19 */ + 11, /* TRIGGER_TR_GROUP2_INPUT20 */ + 11, /* TRIGGER_TR_GROUP2_INPUT21 */ + 11, /* TRIGGER_TR_GROUP2_INPUT22 */ + 11, /* TRIGGER_TR_GROUP2_INPUT23 */ + 11, /* TRIGGER_TR_GROUP2_INPUT24 */ + 12, /* TRIGGER_TR_GROUP2_INPUT25 */ + 12, /* TRIGGER_TR_GROUP2_INPUT26 */ + 12, /* TRIGGER_TR_GROUP2_INPUT27 */ + 12, /* TRIGGER_TR_GROUP2_INPUT28 */ + 12, /* TRIGGER_TR_GROUP2_INPUT29 */ + 12, /* TRIGGER_TR_GROUP2_INPUT30 */ + 12, /* TRIGGER_TR_GROUP2_INPUT31 */ + 12, /* TRIGGER_TR_GROUP2_INPUT32 */ + 13, /* TRIGGER_TR_GROUP2_INPUT33 */ + 13, /* TRIGGER_TR_GROUP2_INPUT34 */ + 14, /* TRIGGER_TR_GROUP2_INPUT35 */ + 14, /* TRIGGER_TR_GROUP2_INPUT36 */ + 14, /* TRIGGER_TR_GROUP2_INPUT37 */ + 14, /* TRIGGER_TR_GROUP2_INPUT38 */ + 14, /* TRIGGER_TR_GROUP2_INPUT39 */ + 14, /* TRIGGER_TR_GROUP2_INPUT40 */ + 14, /* TRIGGER_TR_GROUP2_INPUT41 */ + 14, /* TRIGGER_TR_GROUP2_INPUT42 */ + 10, /* TRIGGER_TR_GROUP3_INPUT1 */ + 10, /* TRIGGER_TR_GROUP3_INPUT2 */ + 10, /* TRIGGER_TR_GROUP3_INPUT3 */ + 10, /* TRIGGER_TR_GROUP3_INPUT4 */ + 10, /* TRIGGER_TR_GROUP3_INPUT5 */ + 10, /* TRIGGER_TR_GROUP3_INPUT6 */ + 10, /* TRIGGER_TR_GROUP3_INPUT7 */ + 10, /* TRIGGER_TR_GROUP3_INPUT8 */ + 11, /* TRIGGER_TR_GROUP3_INPUT9 */ + 11, /* TRIGGER_TR_GROUP3_INPUT10 */ + 11, /* TRIGGER_TR_GROUP3_INPUT11 */ + 11, /* TRIGGER_TR_GROUP3_INPUT12 */ + 11, /* TRIGGER_TR_GROUP3_INPUT13 */ + 11, /* TRIGGER_TR_GROUP3_INPUT14 */ + 11, /* TRIGGER_TR_GROUP3_INPUT15 */ + 11, /* TRIGGER_TR_GROUP3_INPUT16 */ + 11, /* TRIGGER_TR_GROUP3_INPUT17 */ + 11, /* TRIGGER_TR_GROUP3_INPUT18 */ + 11, /* TRIGGER_TR_GROUP3_INPUT19 */ + 11, /* TRIGGER_TR_GROUP3_INPUT20 */ + 11, /* TRIGGER_TR_GROUP3_INPUT21 */ + 11, /* TRIGGER_TR_GROUP3_INPUT22 */ + 11, /* TRIGGER_TR_GROUP3_INPUT23 */ + 11, /* TRIGGER_TR_GROUP3_INPUT24 */ + 12, /* TRIGGER_TR_GROUP3_INPUT25 */ + 12, /* TRIGGER_TR_GROUP3_INPUT26 */ + 12, /* TRIGGER_TR_GROUP3_INPUT27 */ + 12, /* TRIGGER_TR_GROUP3_INPUT28 */ + 12, /* TRIGGER_TR_GROUP3_INPUT29 */ + 12, /* TRIGGER_TR_GROUP3_INPUT30 */ + 12, /* TRIGGER_TR_GROUP3_INPUT31 */ + 12, /* TRIGGER_TR_GROUP3_INPUT32 */ + 13, /* TRIGGER_TR_GROUP3_INPUT33 */ + 13, /* TRIGGER_TR_GROUP3_INPUT34 */ + 14, /* TRIGGER_TR_GROUP3_INPUT35 */ + 14, /* TRIGGER_TR_GROUP3_INPUT36 */ + 14, /* TRIGGER_TR_GROUP3_INPUT37 */ + 14, /* TRIGGER_TR_GROUP3_INPUT38 */ + 14, /* TRIGGER_TR_GROUP3_INPUT39 */ + 14, /* TRIGGER_TR_GROUP3_INPUT40 */ + 14, /* TRIGGER_TR_GROUP3_INPUT41 */ + 14, /* TRIGGER_TR_GROUP3_INPUT42 */ + 10, /* TRIGGER_TR_GROUP4_INPUT1 */ + 10, /* TRIGGER_TR_GROUP4_INPUT2 */ + 10, /* TRIGGER_TR_GROUP4_INPUT3 */ + 10, /* TRIGGER_TR_GROUP4_INPUT4 */ + 10, /* TRIGGER_TR_GROUP4_INPUT5 */ + 10, /* TRIGGER_TR_GROUP4_INPUT6 */ + 10, /* TRIGGER_TR_GROUP4_INPUT7 */ + 10, /* TRIGGER_TR_GROUP4_INPUT8 */ + 11, /* TRIGGER_TR_GROUP4_INPUT9 */ + 11, /* TRIGGER_TR_GROUP4_INPUT10 */ + 11, /* TRIGGER_TR_GROUP4_INPUT11 */ + 11, /* TRIGGER_TR_GROUP4_INPUT12 */ + 11, /* TRIGGER_TR_GROUP4_INPUT13 */ + 11, /* TRIGGER_TR_GROUP4_INPUT14 */ + 11, /* TRIGGER_TR_GROUP4_INPUT15 */ + 11, /* TRIGGER_TR_GROUP4_INPUT16 */ + 11, /* TRIGGER_TR_GROUP4_INPUT17 */ + 11, /* TRIGGER_TR_GROUP4_INPUT18 */ + 11, /* TRIGGER_TR_GROUP4_INPUT19 */ + 11, /* TRIGGER_TR_GROUP4_INPUT20 */ + 11, /* TRIGGER_TR_GROUP4_INPUT21 */ + 11, /* TRIGGER_TR_GROUP4_INPUT22 */ + 11, /* TRIGGER_TR_GROUP4_INPUT23 */ + 11, /* TRIGGER_TR_GROUP4_INPUT24 */ + 12, /* TRIGGER_TR_GROUP4_INPUT25 */ + 12, /* TRIGGER_TR_GROUP4_INPUT26 */ + 12, /* TRIGGER_TR_GROUP4_INPUT27 */ + 12, /* TRIGGER_TR_GROUP4_INPUT28 */ + 12, /* TRIGGER_TR_GROUP4_INPUT29 */ + 12, /* TRIGGER_TR_GROUP4_INPUT30 */ + 12, /* TRIGGER_TR_GROUP4_INPUT31 */ + 12, /* TRIGGER_TR_GROUP4_INPUT32 */ + 13, /* TRIGGER_TR_GROUP4_INPUT33 */ + 13, /* TRIGGER_TR_GROUP4_INPUT34 */ + 14, /* TRIGGER_TR_GROUP4_INPUT35 */ + 14, /* TRIGGER_TR_GROUP4_INPUT36 */ + 14, /* TRIGGER_TR_GROUP4_INPUT37 */ + 14, /* TRIGGER_TR_GROUP4_INPUT38 */ + 14, /* TRIGGER_TR_GROUP4_INPUT39 */ + 14, /* TRIGGER_TR_GROUP4_INPUT40 */ + 14, /* TRIGGER_TR_GROUP4_INPUT41 */ + 14, /* TRIGGER_TR_GROUP4_INPUT42 */ + 10, /* TRIGGER_TR_GROUP5_INPUT1 */ + 10, /* TRIGGER_TR_GROUP5_INPUT2 */ + 10, /* TRIGGER_TR_GROUP5_INPUT3 */ + 10, /* TRIGGER_TR_GROUP5_INPUT4 */ + 10, /* TRIGGER_TR_GROUP5_INPUT5 */ + 10, /* TRIGGER_TR_GROUP5_INPUT6 */ + 10, /* TRIGGER_TR_GROUP5_INPUT7 */ + 10, /* TRIGGER_TR_GROUP5_INPUT8 */ + 11, /* TRIGGER_TR_GROUP5_INPUT9 */ + 11, /* TRIGGER_TR_GROUP5_INPUT10 */ + 11, /* TRIGGER_TR_GROUP5_INPUT11 */ + 11, /* TRIGGER_TR_GROUP5_INPUT12 */ + 11, /* TRIGGER_TR_GROUP5_INPUT13 */ + 11, /* TRIGGER_TR_GROUP5_INPUT14 */ + 11, /* TRIGGER_TR_GROUP5_INPUT15 */ + 11, /* TRIGGER_TR_GROUP5_INPUT16 */ + 11, /* TRIGGER_TR_GROUP5_INPUT17 */ + 11, /* TRIGGER_TR_GROUP5_INPUT18 */ + 11, /* TRIGGER_TR_GROUP5_INPUT19 */ + 11, /* TRIGGER_TR_GROUP5_INPUT20 */ + 11, /* TRIGGER_TR_GROUP5_INPUT21 */ + 11, /* TRIGGER_TR_GROUP5_INPUT22 */ + 11, /* TRIGGER_TR_GROUP5_INPUT23 */ + 11, /* TRIGGER_TR_GROUP5_INPUT24 */ + 12, /* TRIGGER_TR_GROUP5_INPUT25 */ + 12, /* TRIGGER_TR_GROUP5_INPUT26 */ + 12, /* TRIGGER_TR_GROUP5_INPUT27 */ + 12, /* TRIGGER_TR_GROUP5_INPUT28 */ + 12, /* TRIGGER_TR_GROUP5_INPUT29 */ + 12, /* TRIGGER_TR_GROUP5_INPUT30 */ + 12, /* TRIGGER_TR_GROUP5_INPUT31 */ + 12, /* TRIGGER_TR_GROUP5_INPUT32 */ + 13, /* TRIGGER_TR_GROUP5_INPUT33 */ + 13, /* TRIGGER_TR_GROUP5_INPUT34 */ + 14, /* TRIGGER_TR_GROUP5_INPUT35 */ + 14, /* TRIGGER_TR_GROUP5_INPUT36 */ + 14, /* TRIGGER_TR_GROUP5_INPUT37 */ + 14, /* TRIGGER_TR_GROUP5_INPUT38 */ + 14, /* TRIGGER_TR_GROUP5_INPUT39 */ + 14, /* TRIGGER_TR_GROUP5_INPUT40 */ + 14, /* TRIGGER_TR_GROUP5_INPUT41 */ + 14, /* TRIGGER_TR_GROUP5_INPUT42 */ + 10, /* TRIGGER_TR_GROUP6_INPUT1 */ + 10, /* TRIGGER_TR_GROUP6_INPUT2 */ + 10, /* TRIGGER_TR_GROUP6_INPUT3 */ + 10, /* TRIGGER_TR_GROUP6_INPUT4 */ + 10, /* TRIGGER_TR_GROUP6_INPUT5 */ + 10, /* TRIGGER_TR_GROUP6_INPUT6 */ + 10, /* TRIGGER_TR_GROUP6_INPUT7 */ + 10, /* TRIGGER_TR_GROUP6_INPUT8 */ + 11, /* TRIGGER_TR_GROUP6_INPUT9 */ + 11, /* TRIGGER_TR_GROUP6_INPUT10 */ + 11, /* TRIGGER_TR_GROUP6_INPUT11 */ + 11, /* TRIGGER_TR_GROUP6_INPUT12 */ + 11, /* TRIGGER_TR_GROUP6_INPUT13 */ + 11, /* TRIGGER_TR_GROUP6_INPUT14 */ + 11, /* TRIGGER_TR_GROUP6_INPUT15 */ + 11, /* TRIGGER_TR_GROUP6_INPUT16 */ + 11, /* TRIGGER_TR_GROUP6_INPUT17 */ + 11, /* TRIGGER_TR_GROUP6_INPUT18 */ + 11, /* TRIGGER_TR_GROUP6_INPUT19 */ + 11, /* TRIGGER_TR_GROUP6_INPUT20 */ + 11, /* TRIGGER_TR_GROUP6_INPUT21 */ + 11, /* TRIGGER_TR_GROUP6_INPUT22 */ + 11, /* TRIGGER_TR_GROUP6_INPUT23 */ + 11, /* TRIGGER_TR_GROUP6_INPUT24 */ + 12, /* TRIGGER_TR_GROUP6_INPUT25 */ + 12, /* TRIGGER_TR_GROUP6_INPUT26 */ + 12, /* TRIGGER_TR_GROUP6_INPUT27 */ + 12, /* TRIGGER_TR_GROUP6_INPUT28 */ + 12, /* TRIGGER_TR_GROUP6_INPUT29 */ + 12, /* TRIGGER_TR_GROUP6_INPUT30 */ + 12, /* TRIGGER_TR_GROUP6_INPUT31 */ + 12, /* TRIGGER_TR_GROUP6_INPUT32 */ + 13, /* TRIGGER_TR_GROUP6_INPUT33 */ + 13, /* TRIGGER_TR_GROUP6_INPUT34 */ + 14, /* TRIGGER_TR_GROUP6_INPUT35 */ + 14, /* TRIGGER_TR_GROUP6_INPUT36 */ + 14, /* TRIGGER_TR_GROUP6_INPUT37 */ + 14, /* TRIGGER_TR_GROUP6_INPUT38 */ + 14, /* TRIGGER_TR_GROUP6_INPUT39 */ + 14, /* TRIGGER_TR_GROUP6_INPUT40 */ + 14, /* TRIGGER_TR_GROUP6_INPUT41 */ + 14, /* TRIGGER_TR_GROUP6_INPUT42 */ + 10, /* TRIGGER_TR_GROUP7_INPUT1 */ + 10, /* TRIGGER_TR_GROUP7_INPUT2 */ + 10, /* TRIGGER_TR_GROUP7_INPUT3 */ + 10, /* TRIGGER_TR_GROUP7_INPUT4 */ + 10, /* TRIGGER_TR_GROUP7_INPUT5 */ + 10, /* TRIGGER_TR_GROUP7_INPUT6 */ + 10, /* TRIGGER_TR_GROUP7_INPUT7 */ + 10, /* TRIGGER_TR_GROUP7_INPUT8 */ + 11, /* TRIGGER_TR_GROUP7_INPUT9 */ + 11, /* TRIGGER_TR_GROUP7_INPUT10 */ + 11, /* TRIGGER_TR_GROUP7_INPUT11 */ + 11, /* TRIGGER_TR_GROUP7_INPUT12 */ + 11, /* TRIGGER_TR_GROUP7_INPUT13 */ + 11, /* TRIGGER_TR_GROUP7_INPUT14 */ + 11, /* TRIGGER_TR_GROUP7_INPUT15 */ + 11, /* TRIGGER_TR_GROUP7_INPUT16 */ + 11, /* TRIGGER_TR_GROUP7_INPUT17 */ + 11, /* TRIGGER_TR_GROUP7_INPUT18 */ + 11, /* TRIGGER_TR_GROUP7_INPUT19 */ + 11, /* TRIGGER_TR_GROUP7_INPUT20 */ + 11, /* TRIGGER_TR_GROUP7_INPUT21 */ + 11, /* TRIGGER_TR_GROUP7_INPUT22 */ + 11, /* TRIGGER_TR_GROUP7_INPUT23 */ + 11, /* TRIGGER_TR_GROUP7_INPUT24 */ + 12, /* TRIGGER_TR_GROUP7_INPUT25 */ + 12, /* TRIGGER_TR_GROUP7_INPUT26 */ + 12, /* TRIGGER_TR_GROUP7_INPUT27 */ + 12, /* TRIGGER_TR_GROUP7_INPUT28 */ + 12, /* TRIGGER_TR_GROUP7_INPUT29 */ + 12, /* TRIGGER_TR_GROUP7_INPUT30 */ + 12, /* TRIGGER_TR_GROUP7_INPUT31 */ + 12, /* TRIGGER_TR_GROUP7_INPUT32 */ + 13, /* TRIGGER_TR_GROUP7_INPUT33 */ + 13, /* TRIGGER_TR_GROUP7_INPUT34 */ + 14, /* TRIGGER_TR_GROUP7_INPUT35 */ + 14, /* TRIGGER_TR_GROUP7_INPUT36 */ + 14, /* TRIGGER_TR_GROUP7_INPUT37 */ + 14, /* TRIGGER_TR_GROUP7_INPUT38 */ + 14, /* TRIGGER_TR_GROUP7_INPUT39 */ + 14, /* TRIGGER_TR_GROUP7_INPUT40 */ + 14, /* TRIGGER_TR_GROUP7_INPUT41 */ + 14, /* TRIGGER_TR_GROUP7_INPUT42 */ + 10, /* TRIGGER_TR_GROUP8_INPUT1 */ + 10, /* TRIGGER_TR_GROUP8_INPUT2 */ + 10, /* TRIGGER_TR_GROUP8_INPUT3 */ + 10, /* TRIGGER_TR_GROUP8_INPUT4 */ + 10, /* TRIGGER_TR_GROUP8_INPUT5 */ + 10, /* TRIGGER_TR_GROUP8_INPUT6 */ + 10, /* TRIGGER_TR_GROUP8_INPUT7 */ + 10, /* TRIGGER_TR_GROUP8_INPUT8 */ + 11, /* TRIGGER_TR_GROUP8_INPUT9 */ + 11, /* TRIGGER_TR_GROUP8_INPUT10 */ + 11, /* TRIGGER_TR_GROUP8_INPUT11 */ + 11, /* TRIGGER_TR_GROUP8_INPUT12 */ + 11, /* TRIGGER_TR_GROUP8_INPUT13 */ + 11, /* TRIGGER_TR_GROUP8_INPUT14 */ + 11, /* TRIGGER_TR_GROUP8_INPUT15 */ + 11, /* TRIGGER_TR_GROUP8_INPUT16 */ + 11, /* TRIGGER_TR_GROUP8_INPUT17 */ + 11, /* TRIGGER_TR_GROUP8_INPUT18 */ + 11, /* TRIGGER_TR_GROUP8_INPUT19 */ + 11, /* TRIGGER_TR_GROUP8_INPUT20 */ + 11, /* TRIGGER_TR_GROUP8_INPUT21 */ + 11, /* TRIGGER_TR_GROUP8_INPUT22 */ + 11, /* TRIGGER_TR_GROUP8_INPUT23 */ + 11, /* TRIGGER_TR_GROUP8_INPUT24 */ + 12, /* TRIGGER_TR_GROUP8_INPUT25 */ + 12, /* TRIGGER_TR_GROUP8_INPUT26 */ + 12, /* TRIGGER_TR_GROUP8_INPUT27 */ + 12, /* TRIGGER_TR_GROUP8_INPUT28 */ + 12, /* TRIGGER_TR_GROUP8_INPUT29 */ + 12, /* TRIGGER_TR_GROUP8_INPUT30 */ + 12, /* TRIGGER_TR_GROUP8_INPUT31 */ + 12, /* TRIGGER_TR_GROUP8_INPUT32 */ + 13, /* TRIGGER_TR_GROUP8_INPUT33 */ + 13, /* TRIGGER_TR_GROUP8_INPUT34 */ + 14, /* TRIGGER_TR_GROUP8_INPUT35 */ + 14, /* TRIGGER_TR_GROUP8_INPUT36 */ + 14, /* TRIGGER_TR_GROUP8_INPUT37 */ + 14, /* TRIGGER_TR_GROUP8_INPUT38 */ + 14, /* TRIGGER_TR_GROUP8_INPUT39 */ + 14, /* TRIGGER_TR_GROUP8_INPUT40 */ + 14, /* TRIGGER_TR_GROUP8_INPUT41 */ + 14, /* TRIGGER_TR_GROUP8_INPUT42 */ + 10, /* TRIGGER_UDB_TR_DW_ACK0 */ + 10, /* TRIGGER_UDB_TR_DW_ACK1 */ + 10, /* TRIGGER_UDB_TR_DW_ACK2 */ + 10, /* TRIGGER_UDB_TR_DW_ACK3 */ + 10, /* TRIGGER_UDB_TR_DW_ACK4 */ + 10, /* TRIGGER_UDB_TR_DW_ACK5 */ + 10, /* TRIGGER_UDB_TR_DW_ACK6 */ + 10, /* TRIGGER_UDB_TR_DW_ACK7 */ + 7, /* TRIGGER_UDB_TR_IN0 */ + 7, /* TRIGGER_UDB_TR_IN1 */ + 9, /* TRIGGER_USB_DMA_BURSTEND0 */ + 9, /* TRIGGER_USB_DMA_BURSTEND1 */ + 9, /* TRIGGER_USB_DMA_BURSTEND2 */ + 9, /* TRIGGER_USB_DMA_BURSTEND3 */ + 9, /* TRIGGER_USB_DMA_BURSTEND4 */ + 9, /* TRIGGER_USB_DMA_BURSTEND5 */ + 9, /* TRIGGER_USB_DMA_BURSTEND6 */ + 9, /* TRIGGER_USB_DMA_BURSTEND7 */ +}; + +const uint8_t cyhal_mux_dest_index[479] = +{ + 0, /* TRIGGER_CPUSS_CTI_TR_IN0 */ + 1, /* TRIGGER_CPUSS_CTI_TR_IN1 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN0 */ + 1, /* TRIGGER_CPUSS_DW0_TR_IN1 */ + 2, /* TRIGGER_CPUSS_DW0_TR_IN2 */ + 3, /* TRIGGER_CPUSS_DW0_TR_IN3 */ + 4, /* TRIGGER_CPUSS_DW0_TR_IN4 */ + 5, /* TRIGGER_CPUSS_DW0_TR_IN5 */ + 6, /* TRIGGER_CPUSS_DW0_TR_IN6 */ + 7, /* TRIGGER_CPUSS_DW0_TR_IN7 */ + 8, /* TRIGGER_CPUSS_DW0_TR_IN8 */ + 9, /* TRIGGER_CPUSS_DW0_TR_IN9 */ + 10, /* TRIGGER_CPUSS_DW0_TR_IN10 */ + 11, /* TRIGGER_CPUSS_DW0_TR_IN11 */ + 12, /* TRIGGER_CPUSS_DW0_TR_IN12 */ + 13, /* TRIGGER_CPUSS_DW0_TR_IN13 */ + 14, /* TRIGGER_CPUSS_DW0_TR_IN14 */ + 15, /* TRIGGER_CPUSS_DW0_TR_IN15 */ + 0, /* TRIGGER_CPUSS_DW1_TR_IN0 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN1 */ + 2, /* TRIGGER_CPUSS_DW1_TR_IN2 */ + 3, /* TRIGGER_CPUSS_DW1_TR_IN3 */ + 4, /* TRIGGER_CPUSS_DW1_TR_IN4 */ + 5, /* TRIGGER_CPUSS_DW1_TR_IN5 */ + 6, /* TRIGGER_CPUSS_DW1_TR_IN6 */ + 7, /* TRIGGER_CPUSS_DW1_TR_IN7 */ + 8, /* TRIGGER_CPUSS_DW1_TR_IN8 */ + 9, /* TRIGGER_CPUSS_DW1_TR_IN9 */ + 10, /* TRIGGER_CPUSS_DW1_TR_IN10 */ + 11, /* TRIGGER_CPUSS_DW1_TR_IN11 */ + 12, /* TRIGGER_CPUSS_DW1_TR_IN12 */ + 13, /* TRIGGER_CPUSS_DW1_TR_IN13 */ + 14, /* TRIGGER_CPUSS_DW1_TR_IN14 */ + 15, /* TRIGGER_CPUSS_DW1_TR_IN15 */ + 0, /* TRIGGER_PASS_TR_SAR_IN */ + 0, /* TRIGGER_PERI_TR_IO_OUTPUT0 */ + 1, /* TRIGGER_PERI_TR_IO_OUTPUT1 */ + 0, /* TRIGGER_PROFILE_TR_START */ + 1, /* TRIGGER_PROFILE_TR_STOP */ + 0, /* TRIGGER_TCPWM0_TR_IN0 */ + 1, /* TRIGGER_TCPWM0_TR_IN1 */ + 2, /* TRIGGER_TCPWM0_TR_IN2 */ + 3, /* TRIGGER_TCPWM0_TR_IN3 */ + 4, /* TRIGGER_TCPWM0_TR_IN4 */ + 5, /* TRIGGER_TCPWM0_TR_IN5 */ + 6, /* TRIGGER_TCPWM0_TR_IN6 */ + 7, /* TRIGGER_TCPWM0_TR_IN7 */ + 8, /* TRIGGER_TCPWM0_TR_IN8 */ + 9, /* TRIGGER_TCPWM0_TR_IN9 */ + 10, /* TRIGGER_TCPWM0_TR_IN10 */ + 11, /* TRIGGER_TCPWM0_TR_IN11 */ + 12, /* TRIGGER_TCPWM0_TR_IN12 */ + 13, /* TRIGGER_TCPWM0_TR_IN13 */ + 0, /* TRIGGER_TCPWM1_TR_IN0 */ + 1, /* TRIGGER_TCPWM1_TR_IN1 */ + 2, /* TRIGGER_TCPWM1_TR_IN2 */ + 3, /* TRIGGER_TCPWM1_TR_IN3 */ + 4, /* TRIGGER_TCPWM1_TR_IN4 */ + 5, /* TRIGGER_TCPWM1_TR_IN5 */ + 6, /* TRIGGER_TCPWM1_TR_IN6 */ + 7, /* TRIGGER_TCPWM1_TR_IN7 */ + 8, /* TRIGGER_TCPWM1_TR_IN8 */ + 9, /* TRIGGER_TCPWM1_TR_IN9 */ + 10, /* TRIGGER_TCPWM1_TR_IN10 */ + 11, /* TRIGGER_TCPWM1_TR_IN11 */ + 12, /* TRIGGER_TCPWM1_TR_IN12 */ + 13, /* TRIGGER_TCPWM1_TR_IN13 */ + 0, /* TRIGGER_TR_GROUP0_INPUT1 */ + 1, /* TRIGGER_TR_GROUP0_INPUT2 */ + 2, /* TRIGGER_TR_GROUP0_INPUT3 */ + 3, /* TRIGGER_TR_GROUP0_INPUT4 */ + 4, /* TRIGGER_TR_GROUP0_INPUT5 */ + 5, /* TRIGGER_TR_GROUP0_INPUT6 */ + 6, /* TRIGGER_TR_GROUP0_INPUT7 */ + 7, /* TRIGGER_TR_GROUP0_INPUT8 */ + 0, /* TRIGGER_TR_GROUP0_INPUT9 */ + 1, /* TRIGGER_TR_GROUP0_INPUT10 */ + 2, /* TRIGGER_TR_GROUP0_INPUT11 */ + 3, /* TRIGGER_TR_GROUP0_INPUT12 */ + 4, /* TRIGGER_TR_GROUP0_INPUT13 */ + 5, /* TRIGGER_TR_GROUP0_INPUT14 */ + 6, /* TRIGGER_TR_GROUP0_INPUT15 */ + 7, /* TRIGGER_TR_GROUP0_INPUT16 */ + 8, /* TRIGGER_TR_GROUP0_INPUT17 */ + 9, /* TRIGGER_TR_GROUP0_INPUT18 */ + 10, /* TRIGGER_TR_GROUP0_INPUT19 */ + 11, /* TRIGGER_TR_GROUP0_INPUT20 */ + 12, /* TRIGGER_TR_GROUP0_INPUT21 */ + 13, /* TRIGGER_TR_GROUP0_INPUT22 */ + 14, /* TRIGGER_TR_GROUP0_INPUT23 */ + 15, /* TRIGGER_TR_GROUP0_INPUT24 */ + 8, /* TRIGGER_TR_GROUP0_INPUT25 */ + 9, /* TRIGGER_TR_GROUP0_INPUT26 */ + 0, /* TRIGGER_TR_GROUP0_INPUT27 */ + 1, /* TRIGGER_TR_GROUP0_INPUT28 */ + 2, /* TRIGGER_TR_GROUP0_INPUT29 */ + 3, /* TRIGGER_TR_GROUP0_INPUT30 */ + 4, /* TRIGGER_TR_GROUP0_INPUT31 */ + 5, /* TRIGGER_TR_GROUP0_INPUT32 */ + 6, /* TRIGGER_TR_GROUP0_INPUT33 */ + 7, /* TRIGGER_TR_GROUP0_INPUT34 */ + 8, /* TRIGGER_TR_GROUP0_INPUT35 */ + 9, /* TRIGGER_TR_GROUP0_INPUT36 */ + 10, /* TRIGGER_TR_GROUP0_INPUT37 */ + 11, /* TRIGGER_TR_GROUP0_INPUT38 */ + 12, /* TRIGGER_TR_GROUP0_INPUT39 */ + 13, /* TRIGGER_TR_GROUP0_INPUT40 */ + 14, /* TRIGGER_TR_GROUP0_INPUT41 */ + 15, /* TRIGGER_TR_GROUP0_INPUT42 */ + 0, /* TRIGGER_TR_GROUP0_INPUT43 */ + 1, /* TRIGGER_TR_GROUP0_INPUT44 */ + 2, /* TRIGGER_TR_GROUP0_INPUT45 */ + 3, /* TRIGGER_TR_GROUP0_INPUT46 */ + 4, /* TRIGGER_TR_GROUP0_INPUT47 */ + 5, /* TRIGGER_TR_GROUP0_INPUT48 */ + 6, /* TRIGGER_TR_GROUP0_INPUT49 */ + 7, /* TRIGGER_TR_GROUP0_INPUT50 */ + 0, /* TRIGGER_TR_GROUP1_INPUT1 */ + 1, /* TRIGGER_TR_GROUP1_INPUT2 */ + 2, /* TRIGGER_TR_GROUP1_INPUT3 */ + 3, /* TRIGGER_TR_GROUP1_INPUT4 */ + 4, /* TRIGGER_TR_GROUP1_INPUT5 */ + 5, /* TRIGGER_TR_GROUP1_INPUT6 */ + 6, /* TRIGGER_TR_GROUP1_INPUT7 */ + 7, /* TRIGGER_TR_GROUP1_INPUT8 */ + 0, /* TRIGGER_TR_GROUP1_INPUT9 */ + 1, /* TRIGGER_TR_GROUP1_INPUT10 */ + 2, /* TRIGGER_TR_GROUP1_INPUT11 */ + 3, /* TRIGGER_TR_GROUP1_INPUT12 */ + 4, /* TRIGGER_TR_GROUP1_INPUT13 */ + 5, /* TRIGGER_TR_GROUP1_INPUT14 */ + 6, /* TRIGGER_TR_GROUP1_INPUT15 */ + 7, /* TRIGGER_TR_GROUP1_INPUT16 */ + 8, /* TRIGGER_TR_GROUP1_INPUT17 */ + 9, /* TRIGGER_TR_GROUP1_INPUT18 */ + 10, /* TRIGGER_TR_GROUP1_INPUT19 */ + 11, /* TRIGGER_TR_GROUP1_INPUT20 */ + 12, /* TRIGGER_TR_GROUP1_INPUT21 */ + 13, /* TRIGGER_TR_GROUP1_INPUT22 */ + 14, /* TRIGGER_TR_GROUP1_INPUT23 */ + 15, /* TRIGGER_TR_GROUP1_INPUT24 */ + 8, /* TRIGGER_TR_GROUP1_INPUT25 */ + 9, /* TRIGGER_TR_GROUP1_INPUT26 */ + 0, /* TRIGGER_TR_GROUP1_INPUT27 */ + 1, /* TRIGGER_TR_GROUP1_INPUT28 */ + 2, /* TRIGGER_TR_GROUP1_INPUT29 */ + 3, /* TRIGGER_TR_GROUP1_INPUT30 */ + 4, /* TRIGGER_TR_GROUP1_INPUT31 */ + 5, /* TRIGGER_TR_GROUP1_INPUT32 */ + 6, /* TRIGGER_TR_GROUP1_INPUT33 */ + 7, /* TRIGGER_TR_GROUP1_INPUT34 */ + 8, /* TRIGGER_TR_GROUP1_INPUT35 */ + 9, /* TRIGGER_TR_GROUP1_INPUT36 */ + 10, /* TRIGGER_TR_GROUP1_INPUT37 */ + 11, /* TRIGGER_TR_GROUP1_INPUT38 */ + 12, /* TRIGGER_TR_GROUP1_INPUT39 */ + 13, /* TRIGGER_TR_GROUP1_INPUT40 */ + 14, /* TRIGGER_TR_GROUP1_INPUT41 */ + 15, /* TRIGGER_TR_GROUP1_INPUT42 */ + 0, /* TRIGGER_TR_GROUP1_INPUT43 */ + 1, /* TRIGGER_TR_GROUP1_INPUT44 */ + 2, /* TRIGGER_TR_GROUP1_INPUT45 */ + 3, /* TRIGGER_TR_GROUP1_INPUT46 */ + 4, /* TRIGGER_TR_GROUP1_INPUT47 */ + 5, /* TRIGGER_TR_GROUP1_INPUT48 */ + 6, /* TRIGGER_TR_GROUP1_INPUT49 */ + 7, /* TRIGGER_TR_GROUP1_INPUT50 */ + 0, /* TRIGGER_TR_GROUP2_INPUT1 */ + 1, /* TRIGGER_TR_GROUP2_INPUT2 */ + 2, /* TRIGGER_TR_GROUP2_INPUT3 */ + 3, /* TRIGGER_TR_GROUP2_INPUT4 */ + 4, /* TRIGGER_TR_GROUP2_INPUT5 */ + 5, /* TRIGGER_TR_GROUP2_INPUT6 */ + 6, /* TRIGGER_TR_GROUP2_INPUT7 */ + 7, /* TRIGGER_TR_GROUP2_INPUT8 */ + 0, /* TRIGGER_TR_GROUP2_INPUT9 */ + 1, /* TRIGGER_TR_GROUP2_INPUT10 */ + 2, /* TRIGGER_TR_GROUP2_INPUT11 */ + 3, /* TRIGGER_TR_GROUP2_INPUT12 */ + 4, /* TRIGGER_TR_GROUP2_INPUT13 */ + 5, /* TRIGGER_TR_GROUP2_INPUT14 */ + 6, /* TRIGGER_TR_GROUP2_INPUT15 */ + 7, /* TRIGGER_TR_GROUP2_INPUT16 */ + 8, /* TRIGGER_TR_GROUP2_INPUT17 */ + 9, /* TRIGGER_TR_GROUP2_INPUT18 */ + 10, /* TRIGGER_TR_GROUP2_INPUT19 */ + 11, /* TRIGGER_TR_GROUP2_INPUT20 */ + 12, /* TRIGGER_TR_GROUP2_INPUT21 */ + 13, /* TRIGGER_TR_GROUP2_INPUT22 */ + 14, /* TRIGGER_TR_GROUP2_INPUT23 */ + 15, /* TRIGGER_TR_GROUP2_INPUT24 */ + 0, /* TRIGGER_TR_GROUP2_INPUT25 */ + 1, /* TRIGGER_TR_GROUP2_INPUT26 */ + 2, /* TRIGGER_TR_GROUP2_INPUT27 */ + 3, /* TRIGGER_TR_GROUP2_INPUT28 */ + 4, /* TRIGGER_TR_GROUP2_INPUT29 */ + 5, /* TRIGGER_TR_GROUP2_INPUT30 */ + 6, /* TRIGGER_TR_GROUP2_INPUT31 */ + 7, /* TRIGGER_TR_GROUP2_INPUT32 */ + 16, /* TRIGGER_TR_GROUP2_INPUT33 */ + 17, /* TRIGGER_TR_GROUP2_INPUT34 */ + 8, /* TRIGGER_TR_GROUP2_INPUT35 */ + 9, /* TRIGGER_TR_GROUP2_INPUT36 */ + 10, /* TRIGGER_TR_GROUP2_INPUT37 */ + 11, /* TRIGGER_TR_GROUP2_INPUT38 */ + 12, /* TRIGGER_TR_GROUP2_INPUT39 */ + 13, /* TRIGGER_TR_GROUP2_INPUT40 */ + 14, /* TRIGGER_TR_GROUP2_INPUT41 */ + 15, /* TRIGGER_TR_GROUP2_INPUT42 */ + 0, /* TRIGGER_TR_GROUP3_INPUT1 */ + 1, /* TRIGGER_TR_GROUP3_INPUT2 */ + 2, /* TRIGGER_TR_GROUP3_INPUT3 */ + 3, /* TRIGGER_TR_GROUP3_INPUT4 */ + 4, /* TRIGGER_TR_GROUP3_INPUT5 */ + 5, /* TRIGGER_TR_GROUP3_INPUT6 */ + 6, /* TRIGGER_TR_GROUP3_INPUT7 */ + 7, /* TRIGGER_TR_GROUP3_INPUT8 */ + 0, /* TRIGGER_TR_GROUP3_INPUT9 */ + 1, /* TRIGGER_TR_GROUP3_INPUT10 */ + 2, /* TRIGGER_TR_GROUP3_INPUT11 */ + 3, /* TRIGGER_TR_GROUP3_INPUT12 */ + 4, /* TRIGGER_TR_GROUP3_INPUT13 */ + 5, /* TRIGGER_TR_GROUP3_INPUT14 */ + 6, /* TRIGGER_TR_GROUP3_INPUT15 */ + 7, /* TRIGGER_TR_GROUP3_INPUT16 */ + 8, /* TRIGGER_TR_GROUP3_INPUT17 */ + 9, /* TRIGGER_TR_GROUP3_INPUT18 */ + 10, /* TRIGGER_TR_GROUP3_INPUT19 */ + 11, /* TRIGGER_TR_GROUP3_INPUT20 */ + 12, /* TRIGGER_TR_GROUP3_INPUT21 */ + 13, /* TRIGGER_TR_GROUP3_INPUT22 */ + 14, /* TRIGGER_TR_GROUP3_INPUT23 */ + 15, /* TRIGGER_TR_GROUP3_INPUT24 */ + 0, /* TRIGGER_TR_GROUP3_INPUT25 */ + 1, /* TRIGGER_TR_GROUP3_INPUT26 */ + 2, /* TRIGGER_TR_GROUP3_INPUT27 */ + 3, /* TRIGGER_TR_GROUP3_INPUT28 */ + 4, /* TRIGGER_TR_GROUP3_INPUT29 */ + 5, /* TRIGGER_TR_GROUP3_INPUT30 */ + 6, /* TRIGGER_TR_GROUP3_INPUT31 */ + 7, /* TRIGGER_TR_GROUP3_INPUT32 */ + 16, /* TRIGGER_TR_GROUP3_INPUT33 */ + 17, /* TRIGGER_TR_GROUP3_INPUT34 */ + 8, /* TRIGGER_TR_GROUP3_INPUT35 */ + 9, /* TRIGGER_TR_GROUP3_INPUT36 */ + 10, /* TRIGGER_TR_GROUP3_INPUT37 */ + 11, /* TRIGGER_TR_GROUP3_INPUT38 */ + 12, /* TRIGGER_TR_GROUP3_INPUT39 */ + 13, /* TRIGGER_TR_GROUP3_INPUT40 */ + 14, /* TRIGGER_TR_GROUP3_INPUT41 */ + 15, /* TRIGGER_TR_GROUP3_INPUT42 */ + 0, /* TRIGGER_TR_GROUP4_INPUT1 */ + 1, /* TRIGGER_TR_GROUP4_INPUT2 */ + 2, /* TRIGGER_TR_GROUP4_INPUT3 */ + 3, /* TRIGGER_TR_GROUP4_INPUT4 */ + 4, /* TRIGGER_TR_GROUP4_INPUT5 */ + 5, /* TRIGGER_TR_GROUP4_INPUT6 */ + 6, /* TRIGGER_TR_GROUP4_INPUT7 */ + 7, /* TRIGGER_TR_GROUP4_INPUT8 */ + 0, /* TRIGGER_TR_GROUP4_INPUT9 */ + 1, /* TRIGGER_TR_GROUP4_INPUT10 */ + 2, /* TRIGGER_TR_GROUP4_INPUT11 */ + 3, /* TRIGGER_TR_GROUP4_INPUT12 */ + 4, /* TRIGGER_TR_GROUP4_INPUT13 */ + 5, /* TRIGGER_TR_GROUP4_INPUT14 */ + 6, /* TRIGGER_TR_GROUP4_INPUT15 */ + 7, /* TRIGGER_TR_GROUP4_INPUT16 */ + 8, /* TRIGGER_TR_GROUP4_INPUT17 */ + 9, /* TRIGGER_TR_GROUP4_INPUT18 */ + 10, /* TRIGGER_TR_GROUP4_INPUT19 */ + 11, /* TRIGGER_TR_GROUP4_INPUT20 */ + 12, /* TRIGGER_TR_GROUP4_INPUT21 */ + 13, /* TRIGGER_TR_GROUP4_INPUT22 */ + 14, /* TRIGGER_TR_GROUP4_INPUT23 */ + 15, /* TRIGGER_TR_GROUP4_INPUT24 */ + 0, /* TRIGGER_TR_GROUP4_INPUT25 */ + 1, /* TRIGGER_TR_GROUP4_INPUT26 */ + 2, /* TRIGGER_TR_GROUP4_INPUT27 */ + 3, /* TRIGGER_TR_GROUP4_INPUT28 */ + 4, /* TRIGGER_TR_GROUP4_INPUT29 */ + 5, /* TRIGGER_TR_GROUP4_INPUT30 */ + 6, /* TRIGGER_TR_GROUP4_INPUT31 */ + 7, /* TRIGGER_TR_GROUP4_INPUT32 */ + 16, /* TRIGGER_TR_GROUP4_INPUT33 */ + 17, /* TRIGGER_TR_GROUP4_INPUT34 */ + 8, /* TRIGGER_TR_GROUP4_INPUT35 */ + 9, /* TRIGGER_TR_GROUP4_INPUT36 */ + 10, /* TRIGGER_TR_GROUP4_INPUT37 */ + 11, /* TRIGGER_TR_GROUP4_INPUT38 */ + 12, /* TRIGGER_TR_GROUP4_INPUT39 */ + 13, /* TRIGGER_TR_GROUP4_INPUT40 */ + 14, /* TRIGGER_TR_GROUP4_INPUT41 */ + 15, /* TRIGGER_TR_GROUP4_INPUT42 */ + 0, /* TRIGGER_TR_GROUP5_INPUT1 */ + 1, /* TRIGGER_TR_GROUP5_INPUT2 */ + 2, /* TRIGGER_TR_GROUP5_INPUT3 */ + 3, /* TRIGGER_TR_GROUP5_INPUT4 */ + 4, /* TRIGGER_TR_GROUP5_INPUT5 */ + 5, /* TRIGGER_TR_GROUP5_INPUT6 */ + 6, /* TRIGGER_TR_GROUP5_INPUT7 */ + 7, /* TRIGGER_TR_GROUP5_INPUT8 */ + 0, /* TRIGGER_TR_GROUP5_INPUT9 */ + 1, /* TRIGGER_TR_GROUP5_INPUT10 */ + 2, /* TRIGGER_TR_GROUP5_INPUT11 */ + 3, /* TRIGGER_TR_GROUP5_INPUT12 */ + 4, /* TRIGGER_TR_GROUP5_INPUT13 */ + 5, /* TRIGGER_TR_GROUP5_INPUT14 */ + 6, /* TRIGGER_TR_GROUP5_INPUT15 */ + 7, /* TRIGGER_TR_GROUP5_INPUT16 */ + 8, /* TRIGGER_TR_GROUP5_INPUT17 */ + 9, /* TRIGGER_TR_GROUP5_INPUT18 */ + 10, /* TRIGGER_TR_GROUP5_INPUT19 */ + 11, /* TRIGGER_TR_GROUP5_INPUT20 */ + 12, /* TRIGGER_TR_GROUP5_INPUT21 */ + 13, /* TRIGGER_TR_GROUP5_INPUT22 */ + 14, /* TRIGGER_TR_GROUP5_INPUT23 */ + 15, /* TRIGGER_TR_GROUP5_INPUT24 */ + 0, /* TRIGGER_TR_GROUP5_INPUT25 */ + 1, /* TRIGGER_TR_GROUP5_INPUT26 */ + 2, /* TRIGGER_TR_GROUP5_INPUT27 */ + 3, /* TRIGGER_TR_GROUP5_INPUT28 */ + 4, /* TRIGGER_TR_GROUP5_INPUT29 */ + 5, /* TRIGGER_TR_GROUP5_INPUT30 */ + 6, /* TRIGGER_TR_GROUP5_INPUT31 */ + 7, /* TRIGGER_TR_GROUP5_INPUT32 */ + 16, /* TRIGGER_TR_GROUP5_INPUT33 */ + 17, /* TRIGGER_TR_GROUP5_INPUT34 */ + 8, /* TRIGGER_TR_GROUP5_INPUT35 */ + 9, /* TRIGGER_TR_GROUP5_INPUT36 */ + 10, /* TRIGGER_TR_GROUP5_INPUT37 */ + 11, /* TRIGGER_TR_GROUP5_INPUT38 */ + 12, /* TRIGGER_TR_GROUP5_INPUT39 */ + 13, /* TRIGGER_TR_GROUP5_INPUT40 */ + 14, /* TRIGGER_TR_GROUP5_INPUT41 */ + 15, /* TRIGGER_TR_GROUP5_INPUT42 */ + 0, /* TRIGGER_TR_GROUP6_INPUT1 */ + 1, /* TRIGGER_TR_GROUP6_INPUT2 */ + 2, /* TRIGGER_TR_GROUP6_INPUT3 */ + 3, /* TRIGGER_TR_GROUP6_INPUT4 */ + 4, /* TRIGGER_TR_GROUP6_INPUT5 */ + 5, /* TRIGGER_TR_GROUP6_INPUT6 */ + 6, /* TRIGGER_TR_GROUP6_INPUT7 */ + 7, /* TRIGGER_TR_GROUP6_INPUT8 */ + 0, /* TRIGGER_TR_GROUP6_INPUT9 */ + 1, /* TRIGGER_TR_GROUP6_INPUT10 */ + 2, /* TRIGGER_TR_GROUP6_INPUT11 */ + 3, /* TRIGGER_TR_GROUP6_INPUT12 */ + 4, /* TRIGGER_TR_GROUP6_INPUT13 */ + 5, /* TRIGGER_TR_GROUP6_INPUT14 */ + 6, /* TRIGGER_TR_GROUP6_INPUT15 */ + 7, /* TRIGGER_TR_GROUP6_INPUT16 */ + 8, /* TRIGGER_TR_GROUP6_INPUT17 */ + 9, /* TRIGGER_TR_GROUP6_INPUT18 */ + 10, /* TRIGGER_TR_GROUP6_INPUT19 */ + 11, /* TRIGGER_TR_GROUP6_INPUT20 */ + 12, /* TRIGGER_TR_GROUP6_INPUT21 */ + 13, /* TRIGGER_TR_GROUP6_INPUT22 */ + 14, /* TRIGGER_TR_GROUP6_INPUT23 */ + 15, /* TRIGGER_TR_GROUP6_INPUT24 */ + 0, /* TRIGGER_TR_GROUP6_INPUT25 */ + 1, /* TRIGGER_TR_GROUP6_INPUT26 */ + 2, /* TRIGGER_TR_GROUP6_INPUT27 */ + 3, /* TRIGGER_TR_GROUP6_INPUT28 */ + 4, /* TRIGGER_TR_GROUP6_INPUT29 */ + 5, /* TRIGGER_TR_GROUP6_INPUT30 */ + 6, /* TRIGGER_TR_GROUP6_INPUT31 */ + 7, /* TRIGGER_TR_GROUP6_INPUT32 */ + 16, /* TRIGGER_TR_GROUP6_INPUT33 */ + 17, /* TRIGGER_TR_GROUP6_INPUT34 */ + 8, /* TRIGGER_TR_GROUP6_INPUT35 */ + 9, /* TRIGGER_TR_GROUP6_INPUT36 */ + 10, /* TRIGGER_TR_GROUP6_INPUT37 */ + 11, /* TRIGGER_TR_GROUP6_INPUT38 */ + 12, /* TRIGGER_TR_GROUP6_INPUT39 */ + 13, /* TRIGGER_TR_GROUP6_INPUT40 */ + 14, /* TRIGGER_TR_GROUP6_INPUT41 */ + 15, /* TRIGGER_TR_GROUP6_INPUT42 */ + 0, /* TRIGGER_TR_GROUP7_INPUT1 */ + 1, /* TRIGGER_TR_GROUP7_INPUT2 */ + 2, /* TRIGGER_TR_GROUP7_INPUT3 */ + 3, /* TRIGGER_TR_GROUP7_INPUT4 */ + 4, /* TRIGGER_TR_GROUP7_INPUT5 */ + 5, /* TRIGGER_TR_GROUP7_INPUT6 */ + 6, /* TRIGGER_TR_GROUP7_INPUT7 */ + 7, /* TRIGGER_TR_GROUP7_INPUT8 */ + 0, /* TRIGGER_TR_GROUP7_INPUT9 */ + 1, /* TRIGGER_TR_GROUP7_INPUT10 */ + 2, /* TRIGGER_TR_GROUP7_INPUT11 */ + 3, /* TRIGGER_TR_GROUP7_INPUT12 */ + 4, /* TRIGGER_TR_GROUP7_INPUT13 */ + 5, /* TRIGGER_TR_GROUP7_INPUT14 */ + 6, /* TRIGGER_TR_GROUP7_INPUT15 */ + 7, /* TRIGGER_TR_GROUP7_INPUT16 */ + 8, /* TRIGGER_TR_GROUP7_INPUT17 */ + 9, /* TRIGGER_TR_GROUP7_INPUT18 */ + 10, /* TRIGGER_TR_GROUP7_INPUT19 */ + 11, /* TRIGGER_TR_GROUP7_INPUT20 */ + 12, /* TRIGGER_TR_GROUP7_INPUT21 */ + 13, /* TRIGGER_TR_GROUP7_INPUT22 */ + 14, /* TRIGGER_TR_GROUP7_INPUT23 */ + 15, /* TRIGGER_TR_GROUP7_INPUT24 */ + 0, /* TRIGGER_TR_GROUP7_INPUT25 */ + 1, /* TRIGGER_TR_GROUP7_INPUT26 */ + 2, /* TRIGGER_TR_GROUP7_INPUT27 */ + 3, /* TRIGGER_TR_GROUP7_INPUT28 */ + 4, /* TRIGGER_TR_GROUP7_INPUT29 */ + 5, /* TRIGGER_TR_GROUP7_INPUT30 */ + 6, /* TRIGGER_TR_GROUP7_INPUT31 */ + 7, /* TRIGGER_TR_GROUP7_INPUT32 */ + 16, /* TRIGGER_TR_GROUP7_INPUT33 */ + 17, /* TRIGGER_TR_GROUP7_INPUT34 */ + 8, /* TRIGGER_TR_GROUP7_INPUT35 */ + 9, /* TRIGGER_TR_GROUP7_INPUT36 */ + 10, /* TRIGGER_TR_GROUP7_INPUT37 */ + 11, /* TRIGGER_TR_GROUP7_INPUT38 */ + 12, /* TRIGGER_TR_GROUP7_INPUT39 */ + 13, /* TRIGGER_TR_GROUP7_INPUT40 */ + 14, /* TRIGGER_TR_GROUP7_INPUT41 */ + 15, /* TRIGGER_TR_GROUP7_INPUT42 */ + 0, /* TRIGGER_TR_GROUP8_INPUT1 */ + 1, /* TRIGGER_TR_GROUP8_INPUT2 */ + 2, /* TRIGGER_TR_GROUP8_INPUT3 */ + 3, /* TRIGGER_TR_GROUP8_INPUT4 */ + 4, /* TRIGGER_TR_GROUP8_INPUT5 */ + 5, /* TRIGGER_TR_GROUP8_INPUT6 */ + 6, /* TRIGGER_TR_GROUP8_INPUT7 */ + 7, /* TRIGGER_TR_GROUP8_INPUT8 */ + 0, /* TRIGGER_TR_GROUP8_INPUT9 */ + 1, /* TRIGGER_TR_GROUP8_INPUT10 */ + 2, /* TRIGGER_TR_GROUP8_INPUT11 */ + 3, /* TRIGGER_TR_GROUP8_INPUT12 */ + 4, /* TRIGGER_TR_GROUP8_INPUT13 */ + 5, /* TRIGGER_TR_GROUP8_INPUT14 */ + 6, /* TRIGGER_TR_GROUP8_INPUT15 */ + 7, /* TRIGGER_TR_GROUP8_INPUT16 */ + 8, /* TRIGGER_TR_GROUP8_INPUT17 */ + 9, /* TRIGGER_TR_GROUP8_INPUT18 */ + 10, /* TRIGGER_TR_GROUP8_INPUT19 */ + 11, /* TRIGGER_TR_GROUP8_INPUT20 */ + 12, /* TRIGGER_TR_GROUP8_INPUT21 */ + 13, /* TRIGGER_TR_GROUP8_INPUT22 */ + 14, /* TRIGGER_TR_GROUP8_INPUT23 */ + 15, /* TRIGGER_TR_GROUP8_INPUT24 */ + 0, /* TRIGGER_TR_GROUP8_INPUT25 */ + 1, /* TRIGGER_TR_GROUP8_INPUT26 */ + 2, /* TRIGGER_TR_GROUP8_INPUT27 */ + 3, /* TRIGGER_TR_GROUP8_INPUT28 */ + 4, /* TRIGGER_TR_GROUP8_INPUT29 */ + 5, /* TRIGGER_TR_GROUP8_INPUT30 */ + 6, /* TRIGGER_TR_GROUP8_INPUT31 */ + 7, /* TRIGGER_TR_GROUP8_INPUT32 */ + 16, /* TRIGGER_TR_GROUP8_INPUT33 */ + 17, /* TRIGGER_TR_GROUP8_INPUT34 */ + 8, /* TRIGGER_TR_GROUP8_INPUT35 */ + 9, /* TRIGGER_TR_GROUP8_INPUT36 */ + 10, /* TRIGGER_TR_GROUP8_INPUT37 */ + 11, /* TRIGGER_TR_GROUP8_INPUT38 */ + 12, /* TRIGGER_TR_GROUP8_INPUT39 */ + 13, /* TRIGGER_TR_GROUP8_INPUT40 */ + 14, /* TRIGGER_TR_GROUP8_INPUT41 */ + 15, /* TRIGGER_TR_GROUP8_INPUT42 */ + 0, /* TRIGGER_UDB_TR_DW_ACK0 */ + 1, /* TRIGGER_UDB_TR_DW_ACK1 */ + 2, /* TRIGGER_UDB_TR_DW_ACK2 */ + 3, /* TRIGGER_UDB_TR_DW_ACK3 */ + 4, /* TRIGGER_UDB_TR_DW_ACK4 */ + 5, /* TRIGGER_UDB_TR_DW_ACK5 */ + 6, /* TRIGGER_UDB_TR_DW_ACK6 */ + 7, /* TRIGGER_UDB_TR_DW_ACK7 */ + 0, /* TRIGGER_UDB_TR_IN0 */ + 1, /* TRIGGER_UDB_TR_IN1 */ + 0, /* TRIGGER_USB_DMA_BURSTEND0 */ + 1, /* TRIGGER_USB_DMA_BURSTEND1 */ + 2, /* TRIGGER_USB_DMA_BURSTEND2 */ + 3, /* TRIGGER_USB_DMA_BURSTEND3 */ + 4, /* TRIGGER_USB_DMA_BURSTEND4 */ + 5, /* TRIGGER_USB_DMA_BURSTEND5 */ + 6, /* TRIGGER_USB_DMA_BURSTEND6 */ + 7, /* TRIGGER_USB_DMA_BURSTEND7 */ +}; +#endif /* CY_DEVICE_PSOC6ABLE2 */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/triggers/cyhal_triggers_psoc6_02.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/triggers/cyhal_triggers_psoc6_02.c new file mode 100644 index 00000000000..7ee8b540151 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/triggers/cyhal_triggers_psoc6_02.c @@ -0,0 +1,255 @@ +/***************************************************************************//** +* \file cyhal_triggers_psoc6_02.c +* +* \brief +* PSoC6_02 family HAL triggers header +* +* \note +* Generator version: 1.5.7254.19579 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include "cy_device_headers.h" +#include "cyhal_hw_types.h" + +#ifdef CY_DEVICE_PSOC6A2M +#include "triggers/cyhal_triggers_psoc6_02.h" + +const uint8_t cyhal_dest_to_mux[107] = +{ + 5, /* TRIGGER_CPUSS_CTI_TR_IN0 */ + 5, /* TRIGGER_CPUSS_CTI_TR_IN1 */ + 6, /* TRIGGER_CPUSS_DMAC_TR_IN0 */ + 6, /* TRIGGER_CPUSS_DMAC_TR_IN1 */ + 6, /* TRIGGER_CPUSS_DMAC_TR_IN2 */ + 6, /* TRIGGER_CPUSS_DMAC_TR_IN3 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN0 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN1 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN2 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN3 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN4 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN5 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN6 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN7 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN8 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN9 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN10 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN11 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN12 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN13 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN14 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN15 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN16 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN17 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN18 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN19 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN20 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN21 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN22 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN23 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN24 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN25 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN26 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN27 */ + 130, /* TRIGGER_CPUSS_DW0_TR_IN28 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN0 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN1 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN2 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN3 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN4 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN5 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN6 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN7 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN8 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN9 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN10 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN11 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN12 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN13 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN14 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN15 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN16 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN17 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN18 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN19 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN20 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN21 */ + 131, /* TRIGGER_CPUSS_DW1_TR_IN22 */ + 131, /* TRIGGER_CPUSS_DW1_TR_IN23 */ + 132, /* TRIGGER_CPUSS_DW1_TR_IN24 */ + 132, /* TRIGGER_CPUSS_DW1_TR_IN25 */ + 132, /* TRIGGER_CPUSS_DW1_TR_IN26 */ + 132, /* TRIGGER_CPUSS_DW1_TR_IN27 */ + 132, /* TRIGGER_CPUSS_DW1_TR_IN28 */ + 8, /* TRIGGER_CSD_DSI_START */ + 9, /* TRIGGER_PASS_TR_SAR_IN */ + 7, /* TRIGGER_PERI_TR_DBG_FREEZE */ + 4, /* TRIGGER_PERI_TR_IO_OUTPUT0 */ + 4, /* TRIGGER_PERI_TR_IO_OUTPUT1 */ + 5, /* TRIGGER_PROFILE_TR_START */ + 5, /* TRIGGER_PROFILE_TR_STOP */ + 2, /* TRIGGER_TCPWM0_TR_IN0 */ + 2, /* TRIGGER_TCPWM0_TR_IN1 */ + 2, /* TRIGGER_TCPWM0_TR_IN2 */ + 2, /* TRIGGER_TCPWM0_TR_IN3 */ + 2, /* TRIGGER_TCPWM0_TR_IN4 */ + 2, /* TRIGGER_TCPWM0_TR_IN5 */ + 2, /* TRIGGER_TCPWM0_TR_IN6 */ + 2, /* TRIGGER_TCPWM0_TR_IN7 */ + 2, /* TRIGGER_TCPWM0_TR_IN8 */ + 2, /* TRIGGER_TCPWM0_TR_IN9 */ + 2, /* TRIGGER_TCPWM0_TR_IN10 */ + 2, /* TRIGGER_TCPWM0_TR_IN11 */ + 2, /* TRIGGER_TCPWM0_TR_IN12 */ + 2, /* TRIGGER_TCPWM0_TR_IN13 */ + 3, /* TRIGGER_TCPWM1_TR_IN0 */ + 3, /* TRIGGER_TCPWM1_TR_IN1 */ + 3, /* TRIGGER_TCPWM1_TR_IN2 */ + 3, /* TRIGGER_TCPWM1_TR_IN3 */ + 3, /* TRIGGER_TCPWM1_TR_IN4 */ + 3, /* TRIGGER_TCPWM1_TR_IN5 */ + 3, /* TRIGGER_TCPWM1_TR_IN6 */ + 3, /* TRIGGER_TCPWM1_TR_IN7 */ + 3, /* TRIGGER_TCPWM1_TR_IN8 */ + 3, /* TRIGGER_TCPWM1_TR_IN9 */ + 3, /* TRIGGER_TCPWM1_TR_IN10 */ + 3, /* TRIGGER_TCPWM1_TR_IN11 */ + 3, /* TRIGGER_TCPWM1_TR_IN12 */ + 3, /* TRIGGER_TCPWM1_TR_IN13 */ + 134, /* TRIGGER_USB_DMA_BURSTEND0 */ + 134, /* TRIGGER_USB_DMA_BURSTEND1 */ + 134, /* TRIGGER_USB_DMA_BURSTEND2 */ + 134, /* TRIGGER_USB_DMA_BURSTEND3 */ + 134, /* TRIGGER_USB_DMA_BURSTEND4 */ + 134, /* TRIGGER_USB_DMA_BURSTEND5 */ + 134, /* TRIGGER_USB_DMA_BURSTEND6 */ + 134, /* TRIGGER_USB_DMA_BURSTEND7 */ +}; + +const uint8_t cyhal_mux_dest_index[107] = +{ + 0, /* TRIGGER_CPUSS_CTI_TR_IN0 */ + 1, /* TRIGGER_CPUSS_CTI_TR_IN1 */ + 0, /* TRIGGER_CPUSS_DMAC_TR_IN0 */ + 1, /* TRIGGER_CPUSS_DMAC_TR_IN1 */ + 2, /* TRIGGER_CPUSS_DMAC_TR_IN2 */ + 3, /* TRIGGER_CPUSS_DMAC_TR_IN3 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN0 */ + 1, /* TRIGGER_CPUSS_DW0_TR_IN1 */ + 2, /* TRIGGER_CPUSS_DW0_TR_IN2 */ + 3, /* TRIGGER_CPUSS_DW0_TR_IN3 */ + 4, /* TRIGGER_CPUSS_DW0_TR_IN4 */ + 5, /* TRIGGER_CPUSS_DW0_TR_IN5 */ + 6, /* TRIGGER_CPUSS_DW0_TR_IN6 */ + 7, /* TRIGGER_CPUSS_DW0_TR_IN7 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN8 */ + 1, /* TRIGGER_CPUSS_DW0_TR_IN9 */ + 2, /* TRIGGER_CPUSS_DW0_TR_IN10 */ + 3, /* TRIGGER_CPUSS_DW0_TR_IN11 */ + 4, /* TRIGGER_CPUSS_DW0_TR_IN12 */ + 5, /* TRIGGER_CPUSS_DW0_TR_IN13 */ + 6, /* TRIGGER_CPUSS_DW0_TR_IN14 */ + 7, /* TRIGGER_CPUSS_DW0_TR_IN15 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN16 */ + 1, /* TRIGGER_CPUSS_DW0_TR_IN17 */ + 2, /* TRIGGER_CPUSS_DW0_TR_IN18 */ + 3, /* TRIGGER_CPUSS_DW0_TR_IN19 */ + 4, /* TRIGGER_CPUSS_DW0_TR_IN20 */ + 5, /* TRIGGER_CPUSS_DW0_TR_IN21 */ + 6, /* TRIGGER_CPUSS_DW0_TR_IN22 */ + 7, /* TRIGGER_CPUSS_DW0_TR_IN23 */ + 8, /* TRIGGER_CPUSS_DW0_TR_IN24 */ + 9, /* TRIGGER_CPUSS_DW0_TR_IN25 */ + 10, /* TRIGGER_CPUSS_DW0_TR_IN26 */ + 11, /* TRIGGER_CPUSS_DW0_TR_IN27 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN28 */ + 0, /* TRIGGER_CPUSS_DW1_TR_IN0 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN1 */ + 2, /* TRIGGER_CPUSS_DW1_TR_IN2 */ + 3, /* TRIGGER_CPUSS_DW1_TR_IN3 */ + 4, /* TRIGGER_CPUSS_DW1_TR_IN4 */ + 5, /* TRIGGER_CPUSS_DW1_TR_IN5 */ + 6, /* TRIGGER_CPUSS_DW1_TR_IN6 */ + 7, /* TRIGGER_CPUSS_DW1_TR_IN7 */ + 0, /* TRIGGER_CPUSS_DW1_TR_IN8 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN9 */ + 2, /* TRIGGER_CPUSS_DW1_TR_IN10 */ + 3, /* TRIGGER_CPUSS_DW1_TR_IN11 */ + 4, /* TRIGGER_CPUSS_DW1_TR_IN12 */ + 5, /* TRIGGER_CPUSS_DW1_TR_IN13 */ + 6, /* TRIGGER_CPUSS_DW1_TR_IN14 */ + 7, /* TRIGGER_CPUSS_DW1_TR_IN15 */ + 8, /* TRIGGER_CPUSS_DW1_TR_IN16 */ + 9, /* TRIGGER_CPUSS_DW1_TR_IN17 */ + 10, /* TRIGGER_CPUSS_DW1_TR_IN18 */ + 11, /* TRIGGER_CPUSS_DW1_TR_IN19 */ + 12, /* TRIGGER_CPUSS_DW1_TR_IN20 */ + 13, /* TRIGGER_CPUSS_DW1_TR_IN21 */ + 0, /* TRIGGER_CPUSS_DW1_TR_IN22 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN23 */ + 0, /* TRIGGER_CPUSS_DW1_TR_IN24 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN25 */ + 2, /* TRIGGER_CPUSS_DW1_TR_IN26 */ + 3, /* TRIGGER_CPUSS_DW1_TR_IN27 */ + 4, /* TRIGGER_CPUSS_DW1_TR_IN28 */ + 0, /* TRIGGER_CSD_DSI_START */ + 0, /* TRIGGER_PASS_TR_SAR_IN */ + 0, /* TRIGGER_PERI_TR_DBG_FREEZE */ + 0, /* TRIGGER_PERI_TR_IO_OUTPUT0 */ + 1, /* TRIGGER_PERI_TR_IO_OUTPUT1 */ + 2, /* TRIGGER_PROFILE_TR_START */ + 3, /* TRIGGER_PROFILE_TR_STOP */ + 0, /* TRIGGER_TCPWM0_TR_IN0 */ + 1, /* TRIGGER_TCPWM0_TR_IN1 */ + 2, /* TRIGGER_TCPWM0_TR_IN2 */ + 3, /* TRIGGER_TCPWM0_TR_IN3 */ + 4, /* TRIGGER_TCPWM0_TR_IN4 */ + 5, /* TRIGGER_TCPWM0_TR_IN5 */ + 6, /* TRIGGER_TCPWM0_TR_IN6 */ + 7, /* TRIGGER_TCPWM0_TR_IN7 */ + 8, /* TRIGGER_TCPWM0_TR_IN8 */ + 9, /* TRIGGER_TCPWM0_TR_IN9 */ + 10, /* TRIGGER_TCPWM0_TR_IN10 */ + 11, /* TRIGGER_TCPWM0_TR_IN11 */ + 12, /* TRIGGER_TCPWM0_TR_IN12 */ + 13, /* TRIGGER_TCPWM0_TR_IN13 */ + 0, /* TRIGGER_TCPWM1_TR_IN0 */ + 1, /* TRIGGER_TCPWM1_TR_IN1 */ + 2, /* TRIGGER_TCPWM1_TR_IN2 */ + 3, /* TRIGGER_TCPWM1_TR_IN3 */ + 4, /* TRIGGER_TCPWM1_TR_IN4 */ + 5, /* TRIGGER_TCPWM1_TR_IN5 */ + 6, /* TRIGGER_TCPWM1_TR_IN6 */ + 7, /* TRIGGER_TCPWM1_TR_IN7 */ + 8, /* TRIGGER_TCPWM1_TR_IN8 */ + 9, /* TRIGGER_TCPWM1_TR_IN9 */ + 10, /* TRIGGER_TCPWM1_TR_IN10 */ + 11, /* TRIGGER_TCPWM1_TR_IN11 */ + 12, /* TRIGGER_TCPWM1_TR_IN12 */ + 13, /* TRIGGER_TCPWM1_TR_IN13 */ + 0, /* TRIGGER_USB_DMA_BURSTEND0 */ + 1, /* TRIGGER_USB_DMA_BURSTEND1 */ + 2, /* TRIGGER_USB_DMA_BURSTEND2 */ + 3, /* TRIGGER_USB_DMA_BURSTEND3 */ + 4, /* TRIGGER_USB_DMA_BURSTEND4 */ + 5, /* TRIGGER_USB_DMA_BURSTEND5 */ + 6, /* TRIGGER_USB_DMA_BURSTEND6 */ + 7, /* TRIGGER_USB_DMA_BURSTEND7 */ +}; +#endif /* CY_DEVICE_PSOC6A2M */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/triggers/cyhal_triggers_psoc6_03.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/triggers/cyhal_triggers_psoc6_03.c new file mode 100644 index 00000000000..2dcccdbd5a1 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/source/triggers/cyhal_triggers_psoc6_03.c @@ -0,0 +1,257 @@ +/***************************************************************************//** +* \file cyhal_triggers_psoc6_03.c +* +* \brief +* PSoC6_03 family HAL triggers header +* +* \note +* Generator version: 1.5.7254.19579 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#include "cy_device_headers.h" +#include "cyhal_hw_types.h" + +#ifdef CY_DEVICE_PSOC6A512K +#include "triggers/cyhal_triggers_psoc6_03.h" + +const uint8_t cyhal_dest_to_mux[108] = +{ + 135, /* TRIGGER_CANFD0_TR_DBG_DMA_ACK0 */ + 10, /* TRIGGER_CANFD0_TR_EVT_SWT_IN0 */ + 5, /* TRIGGER_CPUSS_CTI_TR_IN0 */ + 5, /* TRIGGER_CPUSS_CTI_TR_IN1 */ + 6, /* TRIGGER_CPUSS_DMAC_TR_IN0 */ + 6, /* TRIGGER_CPUSS_DMAC_TR_IN1 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN0 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN1 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN2 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN3 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN4 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN5 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN6 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN7 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN8 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN9 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN10 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN11 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN12 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN13 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN14 */ + 133, /* TRIGGER_CPUSS_DW0_TR_IN15 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN16 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN17 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN18 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN19 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN20 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN21 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN22 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN23 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN24 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN25 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN26 */ + 128, /* TRIGGER_CPUSS_DW0_TR_IN27 */ + 130, /* TRIGGER_CPUSS_DW0_TR_IN28 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN0 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN1 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN2 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN3 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN4 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN5 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN6 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN7 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN8 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN9 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN10 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN11 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN12 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN13 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN14 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN15 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN16 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN17 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN18 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN19 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN20 */ + 129, /* TRIGGER_CPUSS_DW1_TR_IN21 */ + 131, /* TRIGGER_CPUSS_DW1_TR_IN22 */ + 131, /* TRIGGER_CPUSS_DW1_TR_IN23 */ + 131, /* TRIGGER_CPUSS_DW1_TR_IN24 */ + 131, /* TRIGGER_CPUSS_DW1_TR_IN25 */ + 131, /* TRIGGER_CPUSS_DW1_TR_IN26 */ + 131, /* TRIGGER_CPUSS_DW1_TR_IN27 */ + 131, /* TRIGGER_CPUSS_DW1_TR_IN28 */ + 132, /* TRIGGER_CPUSS_DW1_TR_IN29 */ + 132, /* TRIGGER_CPUSS_DW1_TR_IN30 */ + 132, /* TRIGGER_CPUSS_DW1_TR_IN31 */ + 8, /* TRIGGER_CSD_DSI_START */ + 9, /* TRIGGER_PASS_TR_SAR_IN */ + 7, /* TRIGGER_PERI_TR_DBG_FREEZE */ + 4, /* TRIGGER_PERI_TR_IO_OUTPUT0 */ + 4, /* TRIGGER_PERI_TR_IO_OUTPUT1 */ + 2, /* TRIGGER_TCPWM0_TR_IN0 */ + 2, /* TRIGGER_TCPWM0_TR_IN1 */ + 2, /* TRIGGER_TCPWM0_TR_IN2 */ + 2, /* TRIGGER_TCPWM0_TR_IN3 */ + 2, /* TRIGGER_TCPWM0_TR_IN4 */ + 2, /* TRIGGER_TCPWM0_TR_IN5 */ + 2, /* TRIGGER_TCPWM0_TR_IN6 */ + 2, /* TRIGGER_TCPWM0_TR_IN7 */ + 2, /* TRIGGER_TCPWM0_TR_IN8 */ + 2, /* TRIGGER_TCPWM0_TR_IN9 */ + 2, /* TRIGGER_TCPWM0_TR_IN10 */ + 2, /* TRIGGER_TCPWM0_TR_IN11 */ + 2, /* TRIGGER_TCPWM0_TR_IN12 */ + 2, /* TRIGGER_TCPWM0_TR_IN13 */ + 3, /* TRIGGER_TCPWM1_TR_IN0 */ + 3, /* TRIGGER_TCPWM1_TR_IN1 */ + 3, /* TRIGGER_TCPWM1_TR_IN2 */ + 3, /* TRIGGER_TCPWM1_TR_IN3 */ + 3, /* TRIGGER_TCPWM1_TR_IN4 */ + 3, /* TRIGGER_TCPWM1_TR_IN5 */ + 3, /* TRIGGER_TCPWM1_TR_IN6 */ + 3, /* TRIGGER_TCPWM1_TR_IN7 */ + 3, /* TRIGGER_TCPWM1_TR_IN8 */ + 3, /* TRIGGER_TCPWM1_TR_IN9 */ + 3, /* TRIGGER_TCPWM1_TR_IN10 */ + 3, /* TRIGGER_TCPWM1_TR_IN11 */ + 3, /* TRIGGER_TCPWM1_TR_IN12 */ + 3, /* TRIGGER_TCPWM1_TR_IN13 */ + 134, /* TRIGGER_USB_DMA_BURSTEND0 */ + 134, /* TRIGGER_USB_DMA_BURSTEND1 */ + 134, /* TRIGGER_USB_DMA_BURSTEND2 */ + 134, /* TRIGGER_USB_DMA_BURSTEND3 */ + 134, /* TRIGGER_USB_DMA_BURSTEND4 */ + 134, /* TRIGGER_USB_DMA_BURSTEND5 */ + 134, /* TRIGGER_USB_DMA_BURSTEND6 */ + 134, /* TRIGGER_USB_DMA_BURSTEND7 */ +}; + +const uint8_t cyhal_mux_dest_index[108] = +{ + 0, /* TRIGGER_CANFD0_TR_DBG_DMA_ACK0 */ + 0, /* TRIGGER_CANFD0_TR_EVT_SWT_IN0 */ + 0, /* TRIGGER_CPUSS_CTI_TR_IN0 */ + 1, /* TRIGGER_CPUSS_CTI_TR_IN1 */ + 0, /* TRIGGER_CPUSS_DMAC_TR_IN0 */ + 1, /* TRIGGER_CPUSS_DMAC_TR_IN1 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN0 */ + 1, /* TRIGGER_CPUSS_DW0_TR_IN1 */ + 2, /* TRIGGER_CPUSS_DW0_TR_IN2 */ + 3, /* TRIGGER_CPUSS_DW0_TR_IN3 */ + 4, /* TRIGGER_CPUSS_DW0_TR_IN4 */ + 5, /* TRIGGER_CPUSS_DW0_TR_IN5 */ + 6, /* TRIGGER_CPUSS_DW0_TR_IN6 */ + 7, /* TRIGGER_CPUSS_DW0_TR_IN7 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN8 */ + 1, /* TRIGGER_CPUSS_DW0_TR_IN9 */ + 2, /* TRIGGER_CPUSS_DW0_TR_IN10 */ + 3, /* TRIGGER_CPUSS_DW0_TR_IN11 */ + 4, /* TRIGGER_CPUSS_DW0_TR_IN12 */ + 5, /* TRIGGER_CPUSS_DW0_TR_IN13 */ + 6, /* TRIGGER_CPUSS_DW0_TR_IN14 */ + 7, /* TRIGGER_CPUSS_DW0_TR_IN15 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN16 */ + 1, /* TRIGGER_CPUSS_DW0_TR_IN17 */ + 2, /* TRIGGER_CPUSS_DW0_TR_IN18 */ + 3, /* TRIGGER_CPUSS_DW0_TR_IN19 */ + 4, /* TRIGGER_CPUSS_DW0_TR_IN20 */ + 5, /* TRIGGER_CPUSS_DW0_TR_IN21 */ + 6, /* TRIGGER_CPUSS_DW0_TR_IN22 */ + 7, /* TRIGGER_CPUSS_DW0_TR_IN23 */ + 8, /* TRIGGER_CPUSS_DW0_TR_IN24 */ + 9, /* TRIGGER_CPUSS_DW0_TR_IN25 */ + 10, /* TRIGGER_CPUSS_DW0_TR_IN26 */ + 11, /* TRIGGER_CPUSS_DW0_TR_IN27 */ + 0, /* TRIGGER_CPUSS_DW0_TR_IN28 */ + 0, /* TRIGGER_CPUSS_DW1_TR_IN0 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN1 */ + 2, /* TRIGGER_CPUSS_DW1_TR_IN2 */ + 3, /* TRIGGER_CPUSS_DW1_TR_IN3 */ + 4, /* TRIGGER_CPUSS_DW1_TR_IN4 */ + 5, /* TRIGGER_CPUSS_DW1_TR_IN5 */ + 6, /* TRIGGER_CPUSS_DW1_TR_IN6 */ + 7, /* TRIGGER_CPUSS_DW1_TR_IN7 */ + 0, /* TRIGGER_CPUSS_DW1_TR_IN8 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN9 */ + 2, /* TRIGGER_CPUSS_DW1_TR_IN10 */ + 3, /* TRIGGER_CPUSS_DW1_TR_IN11 */ + 4, /* TRIGGER_CPUSS_DW1_TR_IN12 */ + 5, /* TRIGGER_CPUSS_DW1_TR_IN13 */ + 6, /* TRIGGER_CPUSS_DW1_TR_IN14 */ + 7, /* TRIGGER_CPUSS_DW1_TR_IN15 */ + 8, /* TRIGGER_CPUSS_DW1_TR_IN16 */ + 9, /* TRIGGER_CPUSS_DW1_TR_IN17 */ + 10, /* TRIGGER_CPUSS_DW1_TR_IN18 */ + 11, /* TRIGGER_CPUSS_DW1_TR_IN19 */ + 12, /* TRIGGER_CPUSS_DW1_TR_IN20 */ + 13, /* TRIGGER_CPUSS_DW1_TR_IN21 */ + 0, /* TRIGGER_CPUSS_DW1_TR_IN22 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN23 */ + 2, /* TRIGGER_CPUSS_DW1_TR_IN24 */ + 3, /* TRIGGER_CPUSS_DW1_TR_IN25 */ + 4, /* TRIGGER_CPUSS_DW1_TR_IN26 */ + 5, /* TRIGGER_CPUSS_DW1_TR_IN27 */ + 6, /* TRIGGER_CPUSS_DW1_TR_IN28 */ + 0, /* TRIGGER_CPUSS_DW1_TR_IN29 */ + 1, /* TRIGGER_CPUSS_DW1_TR_IN30 */ + 2, /* TRIGGER_CPUSS_DW1_TR_IN31 */ + 0, /* TRIGGER_CSD_DSI_START */ + 0, /* TRIGGER_PASS_TR_SAR_IN */ + 0, /* TRIGGER_PERI_TR_DBG_FREEZE */ + 0, /* TRIGGER_PERI_TR_IO_OUTPUT0 */ + 1, /* TRIGGER_PERI_TR_IO_OUTPUT1 */ + 0, /* TRIGGER_TCPWM0_TR_IN0 */ + 1, /* TRIGGER_TCPWM0_TR_IN1 */ + 2, /* TRIGGER_TCPWM0_TR_IN2 */ + 3, /* TRIGGER_TCPWM0_TR_IN3 */ + 4, /* TRIGGER_TCPWM0_TR_IN4 */ + 5, /* TRIGGER_TCPWM0_TR_IN5 */ + 6, /* TRIGGER_TCPWM0_TR_IN6 */ + 7, /* TRIGGER_TCPWM0_TR_IN7 */ + 8, /* TRIGGER_TCPWM0_TR_IN8 */ + 9, /* TRIGGER_TCPWM0_TR_IN9 */ + 10, /* TRIGGER_TCPWM0_TR_IN10 */ + 11, /* TRIGGER_TCPWM0_TR_IN11 */ + 12, /* TRIGGER_TCPWM0_TR_IN12 */ + 13, /* TRIGGER_TCPWM0_TR_IN13 */ + 0, /* TRIGGER_TCPWM1_TR_IN0 */ + 1, /* TRIGGER_TCPWM1_TR_IN1 */ + 2, /* TRIGGER_TCPWM1_TR_IN2 */ + 3, /* TRIGGER_TCPWM1_TR_IN3 */ + 4, /* TRIGGER_TCPWM1_TR_IN4 */ + 5, /* TRIGGER_TCPWM1_TR_IN5 */ + 6, /* TRIGGER_TCPWM1_TR_IN6 */ + 7, /* TRIGGER_TCPWM1_TR_IN7 */ + 8, /* TRIGGER_TCPWM1_TR_IN8 */ + 9, /* TRIGGER_TCPWM1_TR_IN9 */ + 10, /* TRIGGER_TCPWM1_TR_IN10 */ + 11, /* TRIGGER_TCPWM1_TR_IN11 */ + 12, /* TRIGGER_TCPWM1_TR_IN12 */ + 13, /* TRIGGER_TCPWM1_TR_IN13 */ + 0, /* TRIGGER_USB_DMA_BURSTEND0 */ + 1, /* TRIGGER_USB_DMA_BURSTEND1 */ + 2, /* TRIGGER_USB_DMA_BURSTEND2 */ + 3, /* TRIGGER_USB_DMA_BURSTEND3 */ + 4, /* TRIGGER_USB_DMA_BURSTEND4 */ + 5, /* TRIGGER_USB_DMA_BURSTEND5 */ + 6, /* TRIGGER_USB_DMA_BURSTEND6 */ + 7, /* TRIGGER_USB_DMA_BURSTEND7 */ +}; +#endif /* CY_DEVICE_PSOC6A512K */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_pwm.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_pwm.c deleted file mode 100644 index 844ea2239df..00000000000 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/src/cyhal_pwm.c +++ /dev/null @@ -1,239 +0,0 @@ -/***************************************************************************//** -* \file cyhal_pwm.c -* -* \brief -* Provides a high level interface for interacting with the Cypress PWM. This is -* a wrapper around the lower level PDL API. -* -******************************************************************************** -* \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ - -#include -#include "cyhal_pwm_impl.h" -#include "cyhal_gpio.h" -#include "cyhal_hwmgr.h" -#include "cyhal_interconnect.h" -#include "cyhal_utils.h" - -#ifdef CY_IP_MXTCPWM - -#if defined(__cplusplus) -extern "C" { -#endif - -#define CYHAL_TCPWM_MAX_WIDTH 32 - -static const cyhal_resource_pin_mapping_t* try_alloc_pwm(cyhal_gpio_t pin, const cyhal_resource_pin_mapping_t *pin_map, size_t count) -{ - for (uint32_t i = 0; i < count; i++) - { - if (pin == pin_map[i].pin) - { - if (CY_RSLT_SUCCESS == cyhal_hwmgr_reserve(pin_map[i].inst)) - { - return &pin_map[i]; - } - } - } - return NULL; -} - -cy_rslt_t cyhal_pwm_init(cyhal_pwm_t *obj, cyhal_gpio_t pin, const cyhal_clock_divider_t *clk) -{ - CY_ASSERT(NULL != obj); - - cy_rslt_t result = CY_RSLT_SUCCESS; - /* Explicitly marked not allocated resources as invalid to prevent freeing them. */ - obj->resource.type = CYHAL_RSC_INVALID; - obj->pin = CYHAL_NC_PIN_VALUE; - obj->dedicated_clock = false; - - const cyhal_resource_pin_mapping_t* map = try_alloc_pwm(pin, cyhal_pin_map_tcpwm_line, sizeof(cyhal_pin_map_tcpwm_line) / sizeof(cyhal_resource_pin_mapping_t)); - if (map == NULL) - { - map = try_alloc_pwm(pin, cyhal_pin_map_tcpwm_line_compl, sizeof(cyhal_pin_map_tcpwm_line_compl) / sizeof(cyhal_resource_pin_mapping_t)); - } - if (map == NULL) - { - result = CYHAL_PWM_RSLT_BAD_ARGUMENT; - } - - if(CY_RSLT_SUCCESS == result) - { - obj->resource = *map->inst; - obj->base = CYHAL_TCPWM_DATA[obj->resource.block_num].base; - result = cyhal_gpio_init(pin, CYHAL_GPIO_DIR_OUTPUT, CYHAL_GPIO_DRIVE_STRONG, true); - } - - if (CY_RSLT_SUCCESS == result) - { - obj->pin = pin; - result = cyhal_connect_pin(map); - } - if (CY_RSLT_SUCCESS == result) - { - en_clk_dst_t pclk = (en_clk_dst_t)(CYHAL_TCPWM_DATA[obj->resource.block_num].clock_dst + obj->resource.channel_num); - if (NULL != clk) - { - obj->clock_hz = Cy_SysClk_ClkPeriGetFrequency() / (1 + Cy_SysClk_PeriphGetDivider(clk->div_type, clk->div_num)); - if (CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(pclk, clk->div_type, clk->div_num)) - result = CYHAL_PWM_RSLT_FAILED_CLOCK_INIT; - } - else if (CY_RSLT_SUCCESS == (result = cyhal_hwmgr_allocate_clock(&(obj->clock), CY_SYSCLK_DIV_16_BIT, false))) - { - obj->dedicated_clock = true; - uint32_t div = (uint32_t)(1 << (CYHAL_TCPWM_MAX_WIDTH - CYHAL_TCPWM_DATA[obj->resource.block_num].max_count)); - if (0 == div || - CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphSetDivider(obj->clock.div_type, obj->clock.div_num, div - 1) || - CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphEnableDivider(obj->clock.div_type, obj->clock.div_num) || - CY_SYSCLK_SUCCESS != Cy_SysClk_PeriphAssignDivider(pclk, obj->clock.div_type, obj->clock.div_num)) - result = CYHAL_PWM_RSLT_FAILED_CLOCK_INIT; - else - { - obj->clock_hz = Cy_SysClk_ClkPeriGetFrequency() / div; - } - } - } - - if (CY_RSLT_SUCCESS == result) - { - static const cy_stc_tcpwm_pwm_config_t config = - { - .pwmMode = CY_TCPWM_PWM_MODE_PWM, - .clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_1, - .pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN, - .deadTimeClocks = 0UL, - .runMode = CY_TCPWM_PWM_CONTINUOUS, - .period0 = 0UL, - .period1 = 0UL, - .enablePeriodSwap = false, - .compare0 = 0UL, - .compare1 = 0UL, - .enableCompareSwap = false, - .interruptSources = CY_TCPWM_INT_NONE, - .invertPWMOut = CY_TCPWM_PWM_INVERT_DISABLE, - .invertPWMOutN = CY_TCPWM_PWM_INVERT_ENABLE, - .killMode = CY_TCPWM_PWM_STOP_ON_KILL, - .swapInputMode = CY_TCPWM_INPUT_RISINGEDGE, - .swapInput = CY_TCPWM_INPUT_0, - .reloadInputMode = CY_TCPWM_INPUT_RISINGEDGE, - .reloadInput = CY_TCPWM_INPUT_0, - .startInputMode = CY_TCPWM_INPUT_RISINGEDGE, - .startInput = CY_TCPWM_INPUT_0, - .killInputMode = CY_TCPWM_INPUT_RISINGEDGE, - .killInput = CY_TCPWM_INPUT_0, - .countInputMode = CY_TCPWM_INPUT_LEVEL, - .countInput = CY_TCPWM_INPUT_1 - }; - result = Cy_TCPWM_PWM_Init(obj->base, obj->resource.channel_num, &config); - } - - if (CY_RSLT_SUCCESS == result) - { - cyhal_tcpwm_init_callback_data(&(obj->resource), &(obj->callback_data)); - Cy_TCPWM_PWM_Enable(obj->base, obj->resource.channel_num); - } - else - { - cyhal_pwm_free(obj); - } - - return result; -} - -void cyhal_pwm_free(cyhal_pwm_t *obj) -{ - CY_ASSERT(NULL != obj); - - IRQn_Type irqn = (IRQn_Type)(CYHAL_TCPWM_DATA[obj->resource.block_num].isr_offset + obj->resource.channel_num); - NVIC_DisableIRQ(irqn); - - if (CYHAL_NC_PIN_VALUE != obj->pin) - { - cyhal_gpio_free(obj->pin); - obj->pin = CYHAL_NC_PIN_VALUE; - } - - if (NULL != obj->base) - { - Cy_TCPWM_PWM_Disable(obj->base, obj->resource.channel_num); - - cyhal_hwmgr_free(&(obj->resource)); - obj->base = NULL; - obj->resource.type = CYHAL_RSC_INVALID; - } - - if (obj->dedicated_clock) - { - cy_en_sysclk_status_t rslt = Cy_SysClk_PeriphDisableDivider(obj->clock.div_type, obj->clock.div_num); - CY_ASSERT(CY_SYSCLK_SUCCESS == rslt); - cyhal_hwmgr_free_clock(&(obj->clock)); - obj->dedicated_clock = false; - } -} - -static cy_rslt_t cyhal_pwm_set_period_and_compare(cyhal_pwm_t *obj, uint32_t period, uint32_t compare) -{ - if (period < 1 || period > (uint32_t)((1 << CYHAL_TCPWM_DATA[obj->resource.block_num].max_count)) - 1) - return CYHAL_PWM_RSLT_BAD_ARGUMENT; - if (compare > period) - compare = period; - Cy_TCPWM_PWM_SetCompare0(obj->base, obj->resource.channel_num, 0u); - Cy_TCPWM_PWM_SetPeriod0(obj->base, obj->resource.channel_num, period - 1u); - Cy_TCPWM_PWM_SetCompare0(obj->base, obj->resource.channel_num, compare); - return CY_RSLT_SUCCESS; -} - -cy_rslt_t cyhal_pwm_set_period(cyhal_pwm_t *obj, uint32_t period_us, uint32_t pulse_width_us) -{ - static const uint32_t US_PER_SEC = 1000000u; - CY_ASSERT(NULL != obj); - uint32_t period = (uint32_t)((uint64_t)period_us * obj->clock_hz / US_PER_SEC); - uint32_t width = (uint32_t)((uint64_t)pulse_width_us * obj->clock_hz / US_PER_SEC); - return cyhal_pwm_set_period_and_compare(obj, period, width); -} - -cy_rslt_t cyhal_pwm_set_duty_cycle(cyhal_pwm_t *obj, float duty_cycle, uint32_t frequencyhal_hz) -{ - CY_ASSERT(NULL != obj); - if (duty_cycle < 0.0f || duty_cycle > 100.0f || frequencyhal_hz < 1) - return CYHAL_PWM_RSLT_BAD_ARGUMENT; - uint32_t period = obj->clock_hz / frequencyhal_hz; - uint32_t width = (uint32_t)(duty_cycle * 0.01f * period); - return cyhal_pwm_set_period_and_compare(obj, period, width); -} - -cy_rslt_t cyhal_pwm_start(cyhal_pwm_t *obj) -{ - CY_ASSERT(NULL != obj); - Cy_TCPWM_TriggerReloadOrIndex(obj->base, 1u << obj->resource.channel_num); - return CY_RSLT_SUCCESS; -} - -cy_rslt_t cyhal_pwm_stop(cyhal_pwm_t *obj) -{ - CY_ASSERT(NULL != obj); - Cy_TCPWM_TriggerStopOrKill(obj->base, 1u << obj->resource.channel_num); - return CY_RSLT_SUCCESS; -} - -#if defined(__cplusplus) -} -#endif - -#endif /* CY_IP_MXTCPWM */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/version.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/version.xml new file mode 100644 index 00000000000..3d2fa6b4cbd --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6csp/hal/version.xml @@ -0,0 +1 @@ +1.1.1.11145 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/README.md b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/README.md index 5f1875379b5..f5b45dfb310 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/README.md +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/README.md @@ -41,4 +41,4 @@ See the [PDL API Reference Manual Getting Started section](https://cypresssemico * [Cypress Semiconductor](http://www.cypress.com) --- -© Cypress Semiconductor Corporation, 2019. \ No newline at end of file +© Cypress Semiconductor Corporation, 2020. \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/RELEASE.md b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/RELEASE.md index 246c6bdffd6..1bb6397e98a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/RELEASE.md +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/RELEASE.md @@ -1,37 +1,35 @@ -# PSoC 6 Peripheral Driver Library v1.4.0 +# PSoC 6 Peripheral Driver Library v1.4.1 Please refer to the [README.md](./README.md) and the [PDL API Reference Manual](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/index.html) for a complete description of the Peripheral Driver Library. ### New Features -* The structure of BSP startup templates directory (devices/templates) is updated to match the BSP layout. * The updated core-lib is reused - see [SysLib changelog](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syslib.html) for details. -* Removed redundant legacy PSoC Creator-compatibility macros. -* The startup code reuses sysclk driver API - see [Startup changelog](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__system__config.html) for details. + Updated Personalities -* CSD -* Power -* SegLCD -* WiFi -Updated the configurators launch parameters in CSD and SegLCD personalities: switched from GUI to console applications for regenerating the source code without opening the configurator itself. This improves the user experience, performance, and enables using machines without a GUI. -The Power personality code generation is corrected due to the customer's request. -The TCP Keepalive Offload feature support is added to the WiFi Low Power Assistant (LPA) personality. +* CAN FD - Fix filter configuration issue. +* DMA - Fixed the Trigger Input parameter behaviour. +* WiFi - Update for LPA TCP keepalive offload. +* I2S - Fixed the IRQn generation for all supported devices. +* PDM-PCM - Fixed the IRQn generation for all supported devices. +* QSPI - Data terminals UI enhancement. +* SegLCD - Added the ability to route output signals to Smart I/O. +* Smart I/O - GUI improvement. +* SysClocks - Disable ILO in Hibernate. Updated Drivers -* [BLE_CLK 3.30](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__ble__clk.html) -* [SCB 2.40](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__system__scb.html) -* [Startup 2.70](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__system__config.html) -* [SysClk 1.50](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sysclk.html) -* [SysLib 2.50](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syslib.html) -* [SysPm 4.50](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syspm.html) -* [WDT 1.20](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__wdt.html) +* [BLE_CLK 3.40](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__ble__clk.html) +* [CAN FD 1.10](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__canfd.html) +* [RTC 2.30](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__rtc.html) +* [SMIF 1.50](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__smif.html) +* [SysClk 1.60](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sysclk.html) +* [SysPm 5.0](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syspm.html) Drivers with patch version updates -* [Flash 3.30.3](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__flash.html) -* [SAR 1.20.2](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__sar.html) -* [SegLCD 1.0.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__seglcd.html) -* [SMIF 1.40.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__smif.html) -* [TrigMux 1.20.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__trigmux.html) +* [eFuse 1.10.2](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__efuse.html) +* [Flash 3.30.4](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__flash.html) +* [Prot 1.30.2](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__prot.html) +* [SysLib 2.50.1](https://cypresssemiconductorco.github.io/psoc6pdl/pdl_api_reference_manual/html/group__group__syslib.html) ### Known Issues None @@ -44,11 +42,12 @@ This version of PDL was validated for compatibility with the following Software | Software and Tools | Version | | :--- | :---- | +| [Cypress Core Library](https://github.com/cypresssemiconductorco/core-lib) | 1.1.1 | +| [Cypress HAL](https://github.com/cypresssemiconductorco/psoc6hal) | 1.1.1 | | CMSIS-Core(M) | 5.2.1 | -| GCC Compiler | 7.2.1 | +| GCC Compiler | 9.2.1 | | IAR Compiler | 8.32 | -| ARM Compiler 6 | 6.11 | -| MBED OS | 5.13.1 | +| ARM Compiler 6 | 6.13 | | FreeRTOS | 10.0.1 | ### More information @@ -62,4 +61,4 @@ This version of PDL was validated for compatibility with the following Software * [Cypress Semiconductor](http://www.cypress.com) --- -© Cypress Semiconductor Corporation, 2019. \ No newline at end of file +© Cypress Semiconductor Corporation, 2020. \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d11.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d11.h index da1cc41e2c9..e9ec4b4b808 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d11.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d11.h @@ -5,7 +5,7 @@ * CY8C6245FNI-S3D11 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.1.36 * ******************************************************************************** * \copyright @@ -489,9 +489,6 @@ typedef enum { #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u @@ -1103,16 +1100,6 @@ typedef enum { #define LCD0_BASE 0x403B0000UL #define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ -/******************************************************************************* -* USBFS -*******************************************************************************/ - -#define USBFS0_BASE 0x403F0000UL -#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ -#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ -#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ -#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ - /******************************************************************************* * SMIF *******************************************************************************/ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d41.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d41.h index 770c0186cb9..5b1fe6c31d8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d41.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d41.h @@ -5,7 +5,7 @@ * CY8C6245FNI-S3D41 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.1.36 * ******************************************************************************** * \copyright @@ -492,9 +492,6 @@ typedef enum { #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u @@ -1113,16 +1110,6 @@ typedef enum { #define LCD0_BASE 0x403B0000UL #define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ -/******************************************************************************* -* USBFS -*******************************************************************************/ - -#define USBFS0_BASE 0x403F0000UL -#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ -#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ -#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ -#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ - /******************************************************************************* * SMIF *******************************************************************************/ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d71.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d71.h index 4192d7bf9a2..0c7af9deef1 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d71.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy8c6245fni_s3d71.h @@ -5,7 +5,7 @@ * CY8C6245FNI-S3D71 device header * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.1.36 * ******************************************************************************** * \copyright @@ -492,9 +492,6 @@ typedef enum { #define CY_IP_MXS40IOSS 1u #define CY_IP_MXS40IOSS_INSTANCES 1u #define CY_IP_MXS40IOSS_VERSION 2u -#define CY_IP_MXUSBFS 1u -#define CY_IP_MXUSBFS_INSTANCES 1u -#define CY_IP_MXUSBFS_VERSION 1u #define CY_IP_MXS40PASS 1u #define CY_IP_MXS40PASS_INSTANCES 1u #define CY_IP_MXS40PASS_VERSION 1u @@ -1113,16 +1110,6 @@ typedef enum { #define LCD0_BASE 0x403B0000UL #define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ -/******************************************************************************* -* USBFS -*******************************************************************************/ - -#define USBFS0_BASE 0x403F0000UL -#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ -#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ -#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ -#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ - /******************************************************************************* * SMIF *******************************************************************************/ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_headers.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_headers.h index 4a0d2bdfb5d..8f1be62fddb 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_headers.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cy_device_headers.h @@ -5,11 +5,11 @@ * Common header file to be included by the drivers. * * \note -* Generator version: 1.5.0.1292 +* Generator version: 1.6.0.81 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -184,6 +184,8 @@ #include "cy8c624alqi_d42.h" #elif defined (CYB0644ABZI_S2D44) #include "cyb0644abzi_s2d44.h" +#elif defined (CYS0644ABZI_S2D44) + #include "cys0644abzi_s2d44.h" #elif defined (CY8C624ABZI_S2D44A0) #include "cy8c624abzi_s2d44a0.h" #elif defined (CY8C624ABZI_S2D44) @@ -236,6 +238,8 @@ #include "cy8c6245lqi_s3d02.h" #elif defined (CY8C6245W_S3D72) #include "cy8c6245w_s3d72.h" +#elif defined (PSoC6A256K) + #include "psoc6a256k.h" #else #include "cy_device_common.h" #endif diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb0644abzi_s2d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb0644abzi_s2d44.h index e5a3c7c1c1f..fae778ff483 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb0644abzi_s2d44.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cyb0644abzi_s2d44.h @@ -5,11 +5,11 @@ * CYB0644ABZI-S2D44 device header * * \note -* Generator version: 1.5.0.1292 +* Generator version: 1.6.0.81 * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -572,7 +572,7 @@ typedef enum { #include "gpio_psoc6_02_124_bga.h" #define CY_DEVICE_PSOC6A2M -#define CY_SILICON_ID 0xE4301102UL +#define CY_SILICON_ID 0xE4701202UL #define CY_HF_CLK_MAX_FREQ 150000000UL #define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cys0644abzi_s2d44.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cys0644abzi_s2d44.h new file mode 100644 index 00000000000..1894820ddfe --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/cys0644abzi_s2d44.h @@ -0,0 +1,1329 @@ +/***************************************************************************//** +* \file cys0644abzi_s2d44.h +* +* \brief +* CYS0644ABZI-S2D44 device header +* +* \note +* Generator version: 1.6.0.81 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYS0644ABZI_S2D44_H_ +#define _CYS0644ABZI_S2D44_H_ + +/** +* \addtogroup group_device CYS0644ABZI-S2D44 +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CYS0644ABZI-S2D44 User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* CYS0644ABZI-S2D44 Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* CYS0644ABZI-S2D44 Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* CYS0644ABZI-S2D44 interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_1_IRQn = 1, /*!< 1 [DeepSleep] GPIO Port Interrupt #1 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_4_IRQn = 4, /*!< 4 [DeepSleep] GPIO Port Interrupt #4 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_13_IRQn = 13, /*!< 13 [DeepSleep] GPIO Port Interrupt #13 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_8_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #8 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + scb_0_interrupt_IRQn = 39, /*!< 39 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 40, /*!< 40 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 41, /*!< 41 [Active] Serial Communication Block #2 */ + scb_3_interrupt_IRQn = 42, /*!< 42 [Active] Serial Communication Block #3 */ + scb_4_interrupt_IRQn = 43, /*!< 43 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 44, /*!< 44 [Active] Serial Communication Block #5 */ + scb_6_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #6 */ + scb_7_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #7 */ + scb_9_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #9 */ + scb_10_interrupt_IRQn = 48, /*!< 48 [Active] Serial Communication Block #10 */ + scb_11_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #11 */ + scb_12_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #12 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dmac_2_IRQn = 54, /*!< 54 [Active] CPUSS DMAC, Channel #2 */ + cpuss_interrupts_dmac_3_IRQn = 55, /*!< 55 [Active] CPUSS DMAC, Channel #3 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_4_IRQn = 127, /*!< 127 [Active] TCPWM #0, Counter #4 */ + tcpwm_0_interrupts_5_IRQn = 128, /*!< 128 [Active] TCPWM #0, Counter #5 */ + tcpwm_0_interrupts_6_IRQn = 129, /*!< 129 [Active] TCPWM #0, Counter #6 */ + tcpwm_0_interrupts_7_IRQn = 130, /*!< 130 [Active] TCPWM #0, Counter #7 */ + tcpwm_1_interrupts_0_IRQn = 131, /*!< 131 [Active] TCPWM #1, Counter #0 */ + tcpwm_1_interrupts_1_IRQn = 132, /*!< 132 [Active] TCPWM #1, Counter #1 */ + tcpwm_1_interrupts_2_IRQn = 133, /*!< 133 [Active] TCPWM #1, Counter #2 */ + tcpwm_1_interrupts_3_IRQn = 134, /*!< 134 [Active] TCPWM #1, Counter #3 */ + tcpwm_1_interrupts_4_IRQn = 135, /*!< 135 [Active] TCPWM #1, Counter #4 */ + tcpwm_1_interrupts_5_IRQn = 136, /*!< 136 [Active] TCPWM #1, Counter #5 */ + tcpwm_1_interrupts_6_IRQn = 137, /*!< 137 [Active] TCPWM #1, Counter #6 */ + tcpwm_1_interrupts_7_IRQn = 138, /*!< 138 [Active] TCPWM #1, Counter #7 */ + tcpwm_1_interrupts_8_IRQn = 139, /*!< 139 [Active] TCPWM #1, Counter #8 */ + tcpwm_1_interrupts_9_IRQn = 140, /*!< 140 [Active] TCPWM #1, Counter #9 */ + tcpwm_1_interrupts_10_IRQn = 141, /*!< 141 [Active] TCPWM #1, Counter #10 */ + tcpwm_1_interrupts_11_IRQn = 142, /*!< 142 [Active] TCPWM #1, Counter #11 */ + tcpwm_1_interrupts_12_IRQn = 143, /*!< 143 [Active] TCPWM #1, Counter #12 */ + tcpwm_1_interrupts_13_IRQn = 144, /*!< 144 [Active] TCPWM #1, Counter #13 */ + tcpwm_1_interrupts_14_IRQn = 145, /*!< 145 [Active] TCPWM #1, Counter #14 */ + tcpwm_1_interrupts_15_IRQn = 146, /*!< 146 [Active] TCPWM #1, Counter #15 */ + tcpwm_1_interrupts_16_IRQn = 147, /*!< 147 [Active] TCPWM #1, Counter #16 */ + tcpwm_1_interrupts_17_IRQn = 148, /*!< 148 [Active] TCPWM #1, Counter #17 */ + tcpwm_1_interrupts_18_IRQn = 149, /*!< 149 [Active] TCPWM #1, Counter #18 */ + tcpwm_1_interrupts_19_IRQn = 150, /*!< 150 [Active] TCPWM #1, Counter #19 */ + tcpwm_1_interrupts_20_IRQn = 151, /*!< 151 [Active] TCPWM #1, Counter #20 */ + tcpwm_1_interrupts_21_IRQn = 152, /*!< 152 [Active] TCPWM #1, Counter #21 */ + tcpwm_1_interrupts_22_IRQn = 153, /*!< 153 [Active] TCPWM #1, Counter #22 */ + tcpwm_1_interrupts_23_IRQn = 154, /*!< 154 [Active] TCPWM #1, Counter #23 */ + pass_interrupt_sar_IRQn = 155, /*!< 155 [Active] SAR ADC interrupt */ + audioss_0_interrupt_i2s_IRQn = 156, /*!< 156 [Active] I2S0 Audio interrupt */ + audioss_0_interrupt_pdm_IRQn = 157, /*!< 157 [Active] PDM0/PCM0 Audio interrupt */ + audioss_1_interrupt_i2s_IRQn = 158, /*!< 158 [Active] I2S1 Audio interrupt */ + profile_interrupt_IRQn = 159, /*!< 159 [Active] Energy Profiler interrupt */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + sdhc_0_interrupt_wakeup_IRQn = 164, /*!< 164 [Active] SDIO wakeup interrupt for mxsdhc */ + sdhc_0_interrupt_general_IRQn = 165, /*!< 165 [Active] Consolidated interrupt for mxsdhc for everything else */ + sdhc_1_interrupt_wakeup_IRQn = 166, /*!< 166 [Active] EEMC wakeup interrupt for mxsdhc, not used */ + sdhc_1_interrupt_general_IRQn = 167, /*!< 167 [Active] Consolidated interrupt for mxsdhc for everything else */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00100000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x001D0000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00008000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTCPWM 1u +#define CY_IP_MXTCPWM_INSTANCES 2u +#define CY_IP_MXTCPWM_VERSION 1u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 13u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXSDHC 1u +#define CY_IP_MXSDHC_INSTANCES 2u +#define CY_IP_MXSDHC_VERSION 1u +#define CY_IP_MXAUDIOSS 1u +#define CY_IP_MXAUDIOSS_INSTANCES 2u +#define CY_IP_MXAUDIOSS_VERSION 1u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u +#define CY_IP_MXS40PASS 1u +#define CY_IP_MXS40PASS_INSTANCES 1u +#define CY_IP_MXS40PASS_VERSION 1u +#define CY_IP_MXS40PASS_SAR 1u +#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +#define CY_IP_MXS40PASS_SAR_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXPROFILE 1u +#define CY_IP_MXPROFILE_INSTANCES 1u +#define CY_IP_MXPROFILE_VERSION 1u + +#include "psoc6_02_config.h" +#include "gpio_psoc6_02_124_bga.h" + +#define CY_DEVICE_PSOC6A2M +#define CY_SILICON_ID 0xE4A01202UL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_GR10 ((PERI_GR_Type*) &PERI->GR[10]) /* 0x40004140 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR10_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU5_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU6_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_FLASHC_EXT_MS1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_DMAC_CH2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_DMAC_CH3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_PROFILE ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_SDHC0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_SDHC1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SCB3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB8 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB9 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB10 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB11 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB12 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ +#define PERI_MS_PPU_FX_PDM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[226]) /* 0x40014080 */ +#define PERI_MS_PPU_FX_I2S0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[227]) /* 0x400140C0 */ +#define PERI_MS_PPU_FX_I2S1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[228]) /* 0x40014100 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU5_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[0]) /* 0x40235600 */ +#define PROT_MPU5_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[1]) /* 0x40235620 */ +#define PROT_MPU5_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[2]) /* 0x40235640 */ +#define PROT_MPU5_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[3]) /* 0x40235660 */ +#define PROT_MPU5_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[4]) /* 0x40235680 */ +#define PROT_MPU5_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[5]) /* 0x402356A0 */ +#define PROT_MPU5_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[6]) /* 0x402356C0 */ +#define PROT_MPU5_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[5].MPU_STRUCT[7]) /* 0x402356E0 */ +#define PROT_MPU6_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[0]) /* 0x40235A00 */ +#define PROT_MPU6_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[1]) /* 0x40235A20 */ +#define PROT_MPU6_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[2]) /* 0x40235A40 */ +#define PROT_MPU6_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[3]) /* 0x40235A60 */ +#define PROT_MPU6_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[4]) /* 0x40235A80 */ +#define PROT_MPU6_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[5]) /* 0x40235AA0 */ +#define PROT_MPU6_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[6]) /* 0x40235AC0 */ +#define PROT_MPU6_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[6].MPU_STRUCT[7]) /* 0x40235AE0 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ +#define DMAC_CH2 ((DMAC_CH_Type*) &DMAC->CH[2]) /* 0x402A1200 */ +#define DMAC_CH3 ((DMAC_CH_Type*) &DMAC->CH[3]) /* 0x402A1300 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* PROFILE +*******************************************************************************/ + +#define PROFILE_BASE 0x402D0000UL +#define PROFILE ((PROFILE_Type*) PROFILE_BASE) /* 0x402D0000 */ +#define PROFILE_CNT_STRUCT0 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[0]) /* 0x402D0800 */ +#define PROFILE_CNT_STRUCT1 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[1]) /* 0x402D0810 */ +#define PROFILE_CNT_STRUCT2 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[2]) /* 0x402D0820 */ +#define PROFILE_CNT_STRUCT3 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[3]) /* 0x402D0830 */ +#define PROFILE_CNT_STRUCT4 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[4]) /* 0x402D0840 */ +#define PROFILE_CNT_STRUCT5 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[5]) /* 0x402D0850 */ +#define PROFILE_CNT_STRUCT6 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[6]) /* 0x402D0860 */ +#define PROFILE_CNT_STRUCT7 ((PROFILE_CNT_STRUCT_Type*) &PROFILE->CNT_STRUCT[7]) /* 0x402D0870 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT8 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[8]) /* 0x40320800 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM1_BASE 0x40390000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM1 ((TCPWM_Type*) TCPWM1_BASE) /* 0x40390000 */ +#define TCPWM0_CNT0 ((TCPWM_CNT_Type*) &TCPWM0->CNT[0]) /* 0x40380100 */ +#define TCPWM0_CNT1 ((TCPWM_CNT_Type*) &TCPWM0->CNT[1]) /* 0x40380140 */ +#define TCPWM0_CNT2 ((TCPWM_CNT_Type*) &TCPWM0->CNT[2]) /* 0x40380180 */ +#define TCPWM0_CNT3 ((TCPWM_CNT_Type*) &TCPWM0->CNT[3]) /* 0x403801C0 */ +#define TCPWM0_CNT4 ((TCPWM_CNT_Type*) &TCPWM0->CNT[4]) /* 0x40380200 */ +#define TCPWM0_CNT5 ((TCPWM_CNT_Type*) &TCPWM0->CNT[5]) /* 0x40380240 */ +#define TCPWM0_CNT6 ((TCPWM_CNT_Type*) &TCPWM0->CNT[6]) /* 0x40380280 */ +#define TCPWM0_CNT7 ((TCPWM_CNT_Type*) &TCPWM0->CNT[7]) /* 0x403802C0 */ +#define TCPWM1_CNT0 ((TCPWM_CNT_Type*) &TCPWM1->CNT[0]) /* 0x40390100 */ +#define TCPWM1_CNT1 ((TCPWM_CNT_Type*) &TCPWM1->CNT[1]) /* 0x40390140 */ +#define TCPWM1_CNT2 ((TCPWM_CNT_Type*) &TCPWM1->CNT[2]) /* 0x40390180 */ +#define TCPWM1_CNT3 ((TCPWM_CNT_Type*) &TCPWM1->CNT[3]) /* 0x403901C0 */ +#define TCPWM1_CNT4 ((TCPWM_CNT_Type*) &TCPWM1->CNT[4]) /* 0x40390200 */ +#define TCPWM1_CNT5 ((TCPWM_CNT_Type*) &TCPWM1->CNT[5]) /* 0x40390240 */ +#define TCPWM1_CNT6 ((TCPWM_CNT_Type*) &TCPWM1->CNT[6]) /* 0x40390280 */ +#define TCPWM1_CNT7 ((TCPWM_CNT_Type*) &TCPWM1->CNT[7]) /* 0x403902C0 */ +#define TCPWM1_CNT8 ((TCPWM_CNT_Type*) &TCPWM1->CNT[8]) /* 0x40390300 */ +#define TCPWM1_CNT9 ((TCPWM_CNT_Type*) &TCPWM1->CNT[9]) /* 0x40390340 */ +#define TCPWM1_CNT10 ((TCPWM_CNT_Type*) &TCPWM1->CNT[10]) /* 0x40390380 */ +#define TCPWM1_CNT11 ((TCPWM_CNT_Type*) &TCPWM1->CNT[11]) /* 0x403903C0 */ +#define TCPWM1_CNT12 ((TCPWM_CNT_Type*) &TCPWM1->CNT[12]) /* 0x40390400 */ +#define TCPWM1_CNT13 ((TCPWM_CNT_Type*) &TCPWM1->CNT[13]) /* 0x40390440 */ +#define TCPWM1_CNT14 ((TCPWM_CNT_Type*) &TCPWM1->CNT[14]) /* 0x40390480 */ +#define TCPWM1_CNT15 ((TCPWM_CNT_Type*) &TCPWM1->CNT[15]) /* 0x403904C0 */ +#define TCPWM1_CNT16 ((TCPWM_CNT_Type*) &TCPWM1->CNT[16]) /* 0x40390500 */ +#define TCPWM1_CNT17 ((TCPWM_CNT_Type*) &TCPWM1->CNT[17]) /* 0x40390540 */ +#define TCPWM1_CNT18 ((TCPWM_CNT_Type*) &TCPWM1->CNT[18]) /* 0x40390580 */ +#define TCPWM1_CNT19 ((TCPWM_CNT_Type*) &TCPWM1->CNT[19]) /* 0x403905C0 */ +#define TCPWM1_CNT20 ((TCPWM_CNT_Type*) &TCPWM1->CNT[20]) /* 0x40390600 */ +#define TCPWM1_CNT21 ((TCPWM_CNT_Type*) &TCPWM1->CNT[21]) /* 0x40390640 */ +#define TCPWM1_CNT22 ((TCPWM_CNT_Type*) &TCPWM1->CNT[22]) /* 0x40390680 */ +#define TCPWM1_CNT23 ((TCPWM_CNT_Type*) &TCPWM1->CNT[23]) /* 0x403906C0 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ +#define SMIF0_DEVICE3 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[3]) /* 0x40420980 */ + +/******************************************************************************* +* SDHC +*******************************************************************************/ + +#define SDHC0_BASE 0x40460000UL +#define SDHC1_BASE 0x40470000UL +#define SDHC0 ((SDHC_Type*) SDHC0_BASE) /* 0x40460000 */ +#define SDHC1 ((SDHC_Type*) SDHC1_BASE) /* 0x40470000 */ +#define SDHC0_WRAP ((SDHC_WRAP_Type*) &SDHC0->WRAP) /* 0x40460000 */ +#define SDHC1_WRAP ((SDHC_WRAP_Type*) &SDHC1->WRAP) /* 0x40470000 */ +#define SDHC0_CORE ((SDHC_CORE_Type*) &SDHC0->CORE) /* 0x40461000 */ +#define SDHC1_CORE ((SDHC_CORE_Type*) &SDHC1->CORE) /* 0x40471000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB3_BASE 0x40630000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB7_BASE 0x40670000UL +#define SCB8_BASE 0x40680000UL +#define SCB9_BASE 0x40690000UL +#define SCB10_BASE 0x406A0000UL +#define SCB11_BASE 0x406B0000UL +#define SCB12_BASE 0x406C0000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB3 ((CySCB_Type*) SCB3_BASE) /* 0x40630000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ +#define SCB7 ((CySCB_Type*) SCB7_BASE) /* 0x40670000 */ +#define SCB8 ((CySCB_Type*) SCB8_BASE) /* 0x40680000 */ +#define SCB9 ((CySCB_Type*) SCB9_BASE) /* 0x40690000 */ +#define SCB10 ((CySCB_Type*) SCB10_BASE) /* 0x406A0000 */ +#define SCB11 ((CySCB_Type*) SCB11_BASE) /* 0x406B0000 */ +#define SCB12 ((CySCB_Type*) SCB12_BASE) /* 0x406C0000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_BASE 0x409D0000UL +#define SAR ((SAR_Type*) SAR_BASE) /* 0x409D0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_AREF ((PASS_AREF_Type*) &PASS->AREF) /* 0x409F0E00 */ + +/******************************************************************************* +* PDM +*******************************************************************************/ + +#define PDM0_BASE 0x40A00000UL +#define PDM0 ((PDM_Type*) PDM0_BASE) /* 0x40A00000 */ + +/******************************************************************************* +* I2S +*******************************************************************************/ + +#define I2S0_BASE 0x40A10000UL +#define I2S1_BASE 0x40A11000UL +#define I2S0 ((I2S_Type*) I2S0_BASE) /* 0x40A10000 */ +#define I2S1 ((I2S_Type*) I2S1_BASE) /* 0x40A11000 */ + +/** \} CYS0644ABZI-S2D44 */ + +#endif /* _CYS0644ABZI_S2D44_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_04_68_qfn.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_04_68_qfn.h new file mode 100644 index 00000000000..fb586f7d650 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/gpio_psoc6_04_68_qfn.h @@ -0,0 +1,1166 @@ +/***************************************************************************//** +* \file gpio_psoc6_04_68_qfn.h +* +* \brief +* PSoC6_04 device GPIO header for 68-QFN package +* +* \note +* Generator version: 1.5.1.36 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _GPIO_PSOC6_04_68_QFN_H_ +#define _GPIO_PSOC6_04_68_QFN_H_ + +/* Package type */ +enum +{ + CY_GPIO_PACKAGE_QFN, + CY_GPIO_PACKAGE_BGA, + CY_GPIO_PACKAGE_CSP, + CY_GPIO_PACKAGE_WLCSP, + CY_GPIO_PACKAGE_LQFP, + CY_GPIO_PACKAGE_TQFP, + CY_GPIO_PACKAGE_SMT, +}; + +#define CY_GPIO_PACKAGE_TYPE CY_GPIO_PACKAGE_QFN +#define CY_GPIO_PIN_COUNT 68u + +/* AMUXBUS Segments */ +enum +{ + AMUXBUS_ANALOG_VDDD, + AMUXBUS_CSD0, + AMUXBUS_CSD1, + AMUXBUS_MAIN, + AMUXBUS_SAR, + AMUXBUS_VDDIO_1, + AMUXBUS_VSSA, + AMUXBUS_SRSS_AMUXBUSA_ADFT_VDDD, + AMUXBUS_SRSS_AMUXBUSB_ADFT_VDDD, +}; + +/* AMUX Splitter Controls */ +typedef enum +{ + AMUX_SPLIT_CTL_1 = 0x0001u, /* Left = AMUXBUS_VDDIO_1; Right = AMUXBUS_MAIN */ + AMUX_SPLIT_CTL_2 = 0x0002u, /* Left = AMUXBUS_CSD1; Right = AMUXBUS_CSD0 */ + AMUX_SPLIT_CTL_3 = 0x0003u, /* Left = AMUXBUS_SAR; Right = AMUXBUS_CSD1 */ + AMUX_SPLIT_CTL_5 = 0x0005u /* Left = AMUXBUS_SAR; Right = AMUXBUS_MAIN */ +} cy_en_amux_split_t; + +/* Port List */ +/* PORT 0 (GPIO) */ +#define P0_0_PORT GPIO_PRT0 +#define P0_0_PIN 0u +#define P0_0_NUM 0u +#define P0_1_PORT GPIO_PRT0 +#define P0_1_PIN 1u +#define P0_1_NUM 1u +#define P0_2_PORT GPIO_PRT0 +#define P0_2_PIN 2u +#define P0_2_NUM 2u +#define P0_3_PORT GPIO_PRT0 +#define P0_3_PIN 3u +#define P0_3_NUM 3u +#define P0_4_PORT GPIO_PRT0 +#define P0_4_PIN 4u +#define P0_4_NUM 4u +#define P0_5_PORT GPIO_PRT0 +#define P0_5_PIN 5u +#define P0_5_NUM 5u + +/* PORT 2 (GPIO) */ +#define P2_0_PORT GPIO_PRT2 +#define P2_0_PIN 0u +#define P2_0_NUM 0u +#define P2_1_PORT GPIO_PRT2 +#define P2_1_PIN 1u +#define P2_1_NUM 1u +#define P2_2_PORT GPIO_PRT2 +#define P2_2_PIN 2u +#define P2_2_NUM 2u +#define P2_3_PORT GPIO_PRT2 +#define P2_3_PIN 3u +#define P2_3_NUM 3u +#define P2_4_PORT GPIO_PRT2 +#define P2_4_PIN 4u +#define P2_4_NUM 4u +#define P2_5_PORT GPIO_PRT2 +#define P2_5_PIN 5u +#define P2_5_NUM 5u +#define P2_6_PORT GPIO_PRT2 +#define P2_6_PIN 6u +#define P2_6_NUM 6u +#define P2_7_PORT GPIO_PRT2 +#define P2_7_PIN 7u +#define P2_7_NUM 7u + +/* PORT 3 (GPIO_OVT) */ +#define P3_0_PORT GPIO_PRT3 +#define P3_0_PIN 0u +#define P3_0_NUM 0u +#define P3_0_AMUXSEGMENT AMUXBUS_VSSA +#define P3_1_PORT GPIO_PRT3 +#define P3_1_PIN 1u +#define P3_1_NUM 1u +#define P3_1_AMUXSEGMENT AMUXBUS_VSSA + +/* PORT 5 (GPIO) */ +#define P5_0_PORT GPIO_PRT5 +#define P5_0_PIN 0u +#define P5_0_NUM 0u +#define P5_1_PORT GPIO_PRT5 +#define P5_1_PIN 1u +#define P5_1_NUM 1u +#define P5_6_PORT GPIO_PRT5 +#define P5_6_PIN 6u +#define P5_6_NUM 6u +#define P5_7_PORT GPIO_PRT5 +#define P5_7_PIN 7u +#define P5_7_NUM 7u + +/* PORT 6 (GPIO) */ +#define P6_2_PORT GPIO_PRT6 +#define P6_2_PIN 2u +#define P6_2_NUM 2u +#define P6_3_PORT GPIO_PRT6 +#define P6_3_PIN 3u +#define P6_3_NUM 3u +#define P6_4_PORT GPIO_PRT6 +#define P6_4_PIN 4u +#define P6_4_NUM 4u +#define P6_5_PORT GPIO_PRT6 +#define P6_5_PIN 5u +#define P6_5_NUM 5u +#define P6_6_PORT GPIO_PRT6 +#define P6_6_PIN 6u +#define P6_6_NUM 6u +#define P6_7_PORT GPIO_PRT6 +#define P6_7_PIN 7u +#define P6_7_NUM 7u + +/* PORT 7 (GPIO) */ +#define P7_0_PORT GPIO_PRT7 +#define P7_0_PIN 0u +#define P7_0_NUM 0u +#define P7_0_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_1_PORT GPIO_PRT7 +#define P7_1_PIN 1u +#define P7_1_NUM 1u +#define P7_1_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_2_PORT GPIO_PRT7 +#define P7_2_PIN 2u +#define P7_2_NUM 2u +#define P7_2_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_3_PORT GPIO_PRT7 +#define P7_3_PIN 3u +#define P7_3_NUM 3u +#define P7_3_AMUXSEGMENT AMUXBUS_CSD0 +#define P7_7_PORT GPIO_PRT7 +#define P7_7_PIN 7u +#define P7_7_NUM 7u +#define P7_7_AMUXSEGMENT AMUXBUS_CSD0 + +/* PORT 8 (GPIO) */ +#define P8_0_PORT GPIO_PRT8 +#define P8_0_PIN 0u +#define P8_0_NUM 0u +#define P8_0_AMUXSEGMENT AMUXBUS_CSD0 +#define P8_1_PORT GPIO_PRT8 +#define P8_1_PIN 1u +#define P8_1_NUM 1u +#define P8_1_AMUXSEGMENT AMUXBUS_CSD0 + +/* PORT 9 (GPIO) */ +#define P9_0_PORT GPIO_PRT9 +#define P9_0_PIN 0u +#define P9_0_NUM 0u +#define P9_0_AMUXSEGMENT AMUXBUS_SAR +#define P9_1_PORT GPIO_PRT9 +#define P9_1_PIN 1u +#define P9_1_NUM 1u +#define P9_1_AMUXSEGMENT AMUXBUS_SAR +#define P9_2_PORT GPIO_PRT9 +#define P9_2_PIN 2u +#define P9_2_NUM 2u +#define P9_2_AMUXSEGMENT AMUXBUS_SAR +#define P9_3_PORT GPIO_PRT9 +#define P9_3_PIN 3u +#define P9_3_NUM 3u +#define P9_3_AMUXSEGMENT AMUXBUS_SAR + +/* PORT 10 (GPIO) */ +#define P10_0_PORT GPIO_PRT10 +#define P10_0_PIN 0u +#define P10_0_NUM 0u +#define P10_0_AMUXSEGMENT AMUXBUS_SAR +#define P10_1_PORT GPIO_PRT10 +#define P10_1_PIN 1u +#define P10_1_NUM 1u +#define P10_1_AMUXSEGMENT AMUXBUS_SAR +#define P10_2_PORT GPIO_PRT10 +#define P10_2_PIN 2u +#define P10_2_NUM 2u +#define P10_2_AMUXSEGMENT AMUXBUS_SAR +#define P10_3_PORT GPIO_PRT10 +#define P10_3_PIN 3u +#define P10_3_NUM 3u +#define P10_3_AMUXSEGMENT AMUXBUS_SAR +#define P10_4_PORT GPIO_PRT10 +#define P10_4_PIN 4u +#define P10_4_NUM 4u +#define P10_4_AMUXSEGMENT AMUXBUS_SAR +#define P10_5_PORT GPIO_PRT10 +#define P10_5_PIN 5u +#define P10_5_NUM 5u +#define P10_5_AMUXSEGMENT AMUXBUS_SAR +#define P10_6_PORT GPIO_PRT10 +#define P10_6_PIN 6u +#define P10_6_NUM 6u +#define P10_6_AMUXSEGMENT AMUXBUS_SAR +#define P10_7_PORT GPIO_PRT10 +#define P10_7_PIN 7u +#define P10_7_NUM 7u +#define P10_7_AMUXSEGMENT AMUXBUS_SAR + +/* PORT 11 (GPIO) */ +#define P11_2_PORT GPIO_PRT11 +#define P11_2_PIN 2u +#define P11_2_NUM 2u +#define P11_3_PORT GPIO_PRT11 +#define P11_3_PIN 3u +#define P11_3_NUM 3u +#define P11_4_PORT GPIO_PRT11 +#define P11_4_PIN 4u +#define P11_4_NUM 4u +#define P11_5_PORT GPIO_PRT11 +#define P11_5_PIN 5u +#define P11_5_NUM 5u +#define P11_6_PORT GPIO_PRT11 +#define P11_6_PIN 6u +#define P11_6_NUM 6u +#define P11_7_PORT GPIO_PRT11 +#define P11_7_PIN 7u +#define P11_7_NUM 7u + +/* PORT 12 (GPIO) */ +#define P12_6_PORT GPIO_PRT12 +#define P12_6_PIN 6u +#define P12_6_NUM 6u +#define P12_7_PORT GPIO_PRT12 +#define P12_7_PIN 7u +#define P12_7_NUM 7u + +/* PORT 14 (AUX) */ +#define USBDP_PORT GPIO_PRT14 +#define USBDP_PIN 0u +#define USBDP_NUM 0u +#define USBDM_PORT GPIO_PRT14 +#define USBDM_PIN 1u +#define USBDM_NUM 1u + +/* Analog Connections */ +#define CSD_CMODPADD_PORT 7u +#define CSD_CMODPADD_PIN 1u +#define CSD_CMODPADS_PORT 7u +#define CSD_CMODPADS_PIN 1u +#define CSD_CSH_TANKPADD_PORT 7u +#define CSD_CSH_TANKPADD_PIN 2u +#define CSD_CSH_TANKPADS_PORT 7u +#define CSD_CSH_TANKPADS_PIN 2u +#define CSD_CSHIELDPADS_PORT 8u +#define CSD_CSHIELDPADS_PIN 1u +#define CSD_VREF_EXT_PORT 7u +#define CSD_VREF_EXT_PIN 3u +#define IOSS_ADFT0_NET_PORT 10u +#define IOSS_ADFT0_NET_PIN 0u +#define IOSS_ADFT1_NET_PORT 10u +#define IOSS_ADFT1_NET_PIN 1u +#define LPCOMP_INN_COMP0_PORT 5u +#define LPCOMP_INN_COMP0_PIN 7u +#define LPCOMP_INN_COMP1_PORT 6u +#define LPCOMP_INN_COMP1_PIN 3u +#define LPCOMP_INP_COMP0_PORT 5u +#define LPCOMP_INP_COMP0_PIN 6u +#define LPCOMP_INP_COMP1_PORT 6u +#define LPCOMP_INP_COMP1_PIN 2u +#define PASS_CTB_OA0_OUT_10X_PORT 9u +#define PASS_CTB_OA0_OUT_10X_PIN 2u +#define PASS_CTB_OA1_OUT_10X_PORT 9u +#define PASS_CTB_OA1_OUT_10X_PIN 3u +#define PASS_CTB_PADS0_PORT 9u +#define PASS_CTB_PADS0_PIN 0u +#define PASS_CTB_PADS1_PORT 9u +#define PASS_CTB_PADS1_PIN 1u +#define PASS_CTB_PADS2_PORT 9u +#define PASS_CTB_PADS2_PIN 2u +#define PASS_CTB_PADS3_PORT 9u +#define PASS_CTB_PADS3_PIN 3u +#define PASS_SARMUX_PADS0_PORT 10u +#define PASS_SARMUX_PADS0_PIN 0u +#define PASS_SARMUX_PADS1_PORT 10u +#define PASS_SARMUX_PADS1_PIN 1u +#define PASS_SARMUX_PADS10_PORT 10u +#define PASS_SARMUX_PADS10_PIN 2u +#define PASS_SARMUX_PADS11_PORT 10u +#define PASS_SARMUX_PADS11_PIN 3u +#define PASS_SARMUX_PADS12_PORT 10u +#define PASS_SARMUX_PADS12_PIN 4u +#define PASS_SARMUX_PADS13_PORT 10u +#define PASS_SARMUX_PADS13_PIN 5u +#define PASS_SARMUX_PADS14_PORT 10u +#define PASS_SARMUX_PADS14_PIN 6u +#define PASS_SARMUX_PADS15_PORT 10u +#define PASS_SARMUX_PADS15_PIN 7u +#define PASS_SARMUX_PADS2_PORT 10u +#define PASS_SARMUX_PADS2_PIN 2u +#define PASS_SARMUX_PADS3_PORT 10u +#define PASS_SARMUX_PADS3_PIN 3u +#define PASS_SARMUX_PADS4_PORT 10u +#define PASS_SARMUX_PADS4_PIN 4u +#define PASS_SARMUX_PADS5_PORT 10u +#define PASS_SARMUX_PADS5_PIN 5u +#define PASS_SARMUX_PADS6_PORT 10u +#define PASS_SARMUX_PADS6_PIN 6u +#define PASS_SARMUX_PADS7_PORT 10u +#define PASS_SARMUX_PADS7_PIN 7u +#define PASS_SARMUX_PADS8_PORT 10u +#define PASS_SARMUX_PADS8_PIN 0u +#define PASS_SARMUX_PADS9_PORT 10u +#define PASS_SARMUX_PADS9_PIN 1u +#define SRSS_ADFT_PIN0_PORT 10u +#define SRSS_ADFT_PIN0_PIN 0u +#define SRSS_ADFT_PIN1_PORT 10u +#define SRSS_ADFT_PIN1_PIN 1u +#define SRSS_ECO_IN_PORT 12u +#define SRSS_ECO_IN_PIN 6u +#define SRSS_ECO_OUT_PORT 12u +#define SRSS_ECO_OUT_PIN 7u +#define SRSS_WCO_IN_PORT 0u +#define SRSS_WCO_IN_PIN 0u +#define SRSS_WCO_OUT_PORT 0u +#define SRSS_WCO_OUT_PIN 1u + +/* HSIOM Connections */ +typedef enum +{ + /* Generic HSIOM connections */ + HSIOM_SEL_GPIO = 0, /* N/A */ + HSIOM_SEL_GPIO_DSI = 1, /* N/A */ + HSIOM_SEL_DSI_DSI = 2, /* N/A */ + HSIOM_SEL_DSI_GPIO = 3, /* N/A */ + HSIOM_SEL_AMUXA = 4, /* AMUXBUS A */ + HSIOM_SEL_AMUXB = 5, /* AMUXBUS B */ + HSIOM_SEL_AMUXA_DSI = 6, /* N/A */ + HSIOM_SEL_AMUXB_DSI = 7, /* N/A */ + HSIOM_SEL_ACT_0 = 8, /* Active peripherals 0 */ + HSIOM_SEL_ACT_1 = 9, /* Active peripherals 1 */ + HSIOM_SEL_ACT_2 = 10, /* Active peripherals 2 */ + HSIOM_SEL_ACT_3 = 11, /* Active peripherals 4 */ + HSIOM_SEL_DS_0 = 12, /* Deep Sleep peripherals 0 */ + HSIOM_SEL_DS_1 = 13, /* Deep Sleep peripherals 1 */ + HSIOM_SEL_DS_2 = 14, /* Deep Sleep peripherals 2 */ + HSIOM_SEL_DS_3 = 15, /* Deep Sleep peripherals 3 */ + HSIOM_SEL_ACT_4 = 16, /* Active peripherals 4 */ + HSIOM_SEL_ACT_5 = 17, /* Active peripherals 5 */ + HSIOM_SEL_ACT_6 = 18, /* Active peripherals 6 */ + HSIOM_SEL_ACT_7 = 19, /* Active peripherals 7 */ + HSIOM_SEL_ACT_8 = 20, /* Active peripherals 8 */ + HSIOM_SEL_ACT_9 = 21, /* Active peripherals 9 */ + HSIOM_SEL_ACT_10 = 22, /* Active peripherals 10 */ + HSIOM_SEL_ACT_11 = 23, /* Active peripherals 11 */ + HSIOM_SEL_ACT_12 = 24, /* Active peripherals 12 */ + HSIOM_SEL_ACT_13 = 25, /* Active peripherals 13 */ + HSIOM_SEL_ACT_14 = 26, /* Active peripherals 14 */ + HSIOM_SEL_ACT_15 = 27, /* Active peripherals 15 */ + HSIOM_SEL_DS_4 = 28, /* N/A */ + HSIOM_SEL_DS_5 = 29, /* N/A */ + HSIOM_SEL_DS_6 = 30, /* N/A */ + HSIOM_SEL_DS_7 = 31, /* N/A */ + + /* P0.0 */ + P0_0_GPIO = 0, /* N/A */ + P0_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:0 */ + P0_0_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:0 */ + P0_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:0 */ + P0_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:0 */ + P0_0_LCD_COM0 = 12, /* Digital Deep Sleep - lcd.com[0]:0 */ + P0_0_LCD_SEG0 = 13, /* Digital Deep Sleep - lcd.seg[0]:0 */ + P0_0_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:0 */ + P0_0_SCB0_SPI_SELECT1 = 20, /* Digital Active - scb[0].spi_select1:0 */ + P0_0_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:0 */ + P0_0_PERI_TR_IO_INPUT0 = 24, /* Digital Active - peri.tr_io_input[0]:0 */ + + /* P0.1 */ + P0_1_GPIO = 0, /* N/A */ + P0_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:0 */ + P0_1_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:0 */ + P0_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:1 */ + P0_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:1 */ + P0_1_LCD_COM1 = 12, /* Digital Deep Sleep - lcd.com[1]:0 */ + P0_1_LCD_SEG1 = 13, /* Digital Deep Sleep - lcd.seg[1]:0 */ + P0_1_SCB0_SPI_SELECT2 = 20, /* Digital Active - scb[0].spi_select2:0 */ + P0_1_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:0 */ + P0_1_PERI_TR_IO_INPUT1 = 24, /* Digital Active - peri.tr_io_input[1]:0 */ + P0_1_CPUSS_SWJ_TRSTN = 29, /* Digital Deep Sleep - cpuss.swj_trstn */ + + /* P0.2 */ + P0_2_GPIO = 0, /* N/A */ + P0_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:0 */ + P0_2_TCPWM0_LINE257 = 9, /* Digital Active - tcpwm[0].line[257]:0 */ + P0_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:2 */ + P0_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:2 */ + P0_2_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:0 */ + P0_2_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:0 */ + P0_2_SCB0_UART_RX = 18, /* Digital Active - scb[0].uart_rx:0 */ + P0_2_SCB0_I2C_SCL = 19, /* Digital Active - scb[0].i2c_scl:0 */ + P0_2_SCB0_SPI_MOSI = 20, /* Digital Active - scb[0].spi_mosi:0 */ + P0_2_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:0 */ + + /* P0.3 */ + P0_3_GPIO = 0, /* N/A */ + P0_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:0 */ + P0_3_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:0 */ + P0_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:3 */ + P0_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:3 */ + P0_3_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:0 */ + P0_3_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:0 */ + P0_3_SCB0_UART_TX = 18, /* Digital Active - scb[0].uart_tx:0 */ + P0_3_SCB0_I2C_SDA = 19, /* Digital Active - scb[0].i2c_sda:0 */ + P0_3_SCB0_SPI_MISO = 20, /* Digital Active - scb[0].spi_miso:0 */ + P0_3_TCPWM0_TR_ONE_CNT_IN3 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:0 */ + + /* P0.4 */ + P0_4_GPIO = 0, /* N/A */ + P0_4_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:0 */ + P0_4_TCPWM0_LINE258 = 9, /* Digital Active - tcpwm[0].line[258]:0 */ + P0_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:4 */ + P0_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:4 */ + P0_4_LCD_COM4 = 12, /* Digital Deep Sleep - lcd.com[4]:0 */ + P0_4_LCD_SEG4 = 13, /* Digital Deep Sleep - lcd.seg[4]:0 */ + P0_4_SCB0_UART_RTS = 18, /* Digital Active - scb[0].uart_rts:0 */ + P0_4_SCB0_SPI_CLK = 20, /* Digital Active - scb[0].spi_clk:0 */ + P0_4_TCPWM0_TR_ONE_CNT_IN256 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[256]:0 */ + P0_4_PERI_TR_IO_INPUT2 = 24, /* Digital Active - peri.tr_io_input[2]:0 */ + P0_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:2 */ + + /* P0.5 */ + P0_5_GPIO = 0, /* N/A */ + P0_5_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:0 */ + P0_5_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:0 */ + P0_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:5 */ + P0_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:5 */ + P0_5_LCD_COM5 = 12, /* Digital Deep Sleep - lcd.com[5]:0 */ + P0_5_LCD_SEG5 = 13, /* Digital Deep Sleep - lcd.seg[5]:0 */ + P0_5_SRSS_EXT_CLK = 16, /* Digital Active - srss.ext_clk:1 */ + P0_5_SCB0_UART_CTS = 18, /* Digital Active - scb[0].uart_cts:0 */ + P0_5_SCB0_SPI_SELECT0 = 20, /* Digital Active - scb[0].spi_select0:0 */ + P0_5_TCPWM0_TR_ONE_CNT_IN257 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[257]:0 */ + P0_5_PERI_TR_IO_INPUT3 = 24, /* Digital Active - peri.tr_io_input[3]:0 */ + P0_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:2 */ + + /* USBDM */ + USBDM_GPIO = 0, /* N/A */ + + /* USBDP */ + USBDP_GPIO = 0, /* N/A */ + + /* P2.0 */ + P2_0_GPIO = 0, /* N/A */ + P2_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:0 */ + P2_0_TCPWM0_LINE259 = 9, /* Digital Active - tcpwm[0].line[259]:0 */ + P2_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:9 */ + P2_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:9 */ + P2_0_LCD_COM6 = 12, /* Digital Deep Sleep - lcd.com[6]:0 */ + P2_0_LCD_SEG6 = 13, /* Digital Deep Sleep - lcd.seg[6]:0 */ + P2_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:1 */ + P2_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:1 */ + P2_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:1 */ + P2_0_TCPWM0_TR_ONE_CNT_IN261 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[261]:0 */ + P2_0_PERI_TR_IO_INPUT4 = 24, /* Digital Active - peri.tr_io_input[4]:0 */ + + /* P2.1 */ + P2_1_GPIO = 0, /* N/A */ + P2_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:0 */ + P2_1_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:0 */ + P2_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:10 */ + P2_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:10 */ + P2_1_LCD_COM7 = 12, /* Digital Deep Sleep - lcd.com[7]:0 */ + P2_1_LCD_SEG7 = 13, /* Digital Deep Sleep - lcd.seg[7]:0 */ + P2_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:1 */ + P2_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:1 */ + P2_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:1 */ + P2_1_TCPWM0_TR_ONE_CNT_IN262 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[262]:0 */ + P2_1_PERI_TR_IO_INPUT5 = 24, /* Digital Active - peri.tr_io_input[5]:0 */ + + /* P2.2 */ + P2_2_GPIO = 0, /* N/A */ + P2_2_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:1 */ + P2_2_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:0 */ + P2_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:11 */ + P2_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:11 */ + P2_2_LCD_COM8 = 12, /* Digital Deep Sleep - lcd.com[8]:0 */ + P2_2_LCD_SEG8 = 13, /* Digital Deep Sleep - lcd.seg[8]:0 */ + P2_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:1 */ + P2_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:1 */ + P2_2_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:0 */ + + /* P2.3 */ + P2_3_GPIO = 0, /* N/A */ + P2_3_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:1 */ + P2_3_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:0 */ + P2_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:12 */ + P2_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:12 */ + P2_3_LCD_COM9 = 12, /* Digital Deep Sleep - lcd.com[9]:0 */ + P2_3_LCD_SEG9 = 13, /* Digital Deep Sleep - lcd.seg[9]:0 */ + P2_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:1 */ + P2_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:1 */ + P2_3_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:1 */ + + /* P2.4 */ + P2_4_GPIO = 0, /* N/A */ + P2_4_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:1 */ + P2_4_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:0 */ + P2_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:13 */ + P2_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:13 */ + P2_4_LCD_COM10 = 12, /* Digital Deep Sleep - lcd.com[10]:0 */ + P2_4_LCD_SEG10 = 13, /* Digital Deep Sleep - lcd.seg[10]:0 */ + P2_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:1 */ + P2_4_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:1 */ + + /* P2.5 */ + P2_5_GPIO = 0, /* N/A */ + P2_5_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:1 */ + P2_5_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:0 */ + P2_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:14 */ + P2_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:14 */ + P2_5_LCD_COM11 = 12, /* Digital Deep Sleep - lcd.com[11]:0 */ + P2_5_LCD_SEG11 = 13, /* Digital Deep Sleep - lcd.seg[11]:0 */ + P2_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:1 */ + P2_5_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:1 */ + + /* P2.6 */ + P2_6_GPIO = 0, /* N/A */ + P2_6_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:1 */ + P2_6_TCPWM0_LINE262 = 9, /* Digital Active - tcpwm[0].line[262]:0 */ + P2_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:15 */ + P2_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:15 */ + P2_6_LCD_COM12 = 12, /* Digital Deep Sleep - lcd.com[12]:0 */ + P2_6_LCD_SEG12 = 13, /* Digital Deep Sleep - lcd.seg[12]:0 */ + P2_6_LPCOMP_DSI_COMP0 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp0:0 */ + P2_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:1 */ + P2_6_TCPWM0_TR_ONE_CNT_IN3 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:1 */ + P2_6_PERI_TR_IO_INPUT8 = 24, /* Digital Active - peri.tr_io_input[8]:0 */ + + /* P2.7 */ + P2_7_GPIO = 0, /* N/A */ + P2_7_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:1 */ + P2_7_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:0 */ + P2_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:16 */ + P2_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:16 */ + P2_7_LCD_COM13 = 12, /* Digital Deep Sleep - lcd.com[13]:0 */ + P2_7_LCD_SEG13 = 13, /* Digital Deep Sleep - lcd.seg[13]:0 */ + P2_7_LPCOMP_DSI_COMP1 = 15, /* Digital Deep Sleep - lpcomp.dsi_comp1:0 */ + P2_7_TCPWM0_TR_ONE_CNT_IN256 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[256]:1 */ + P2_7_PERI_TR_IO_INPUT9 = 24, /* Digital Active - peri.tr_io_input[9]:0 */ + + /* P3.0 */ + P3_0_GPIO = 0, /* N/A */ + P3_0_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:1 */ + P3_0_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:0 */ + P3_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:17 */ + P3_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:17 */ + P3_0_LCD_COM14 = 12, /* Digital Deep Sleep - lcd.com[14]:0 */ + P3_0_LCD_SEG14 = 13, /* Digital Deep Sleep - lcd.seg[14]:0 */ + P3_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:1 */ + P3_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:1 */ + P3_0_TCPWM0_TR_ONE_CNT_IN257 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[257]:1 */ + P3_0_PERI_TR_IO_INPUT6 = 24, /* Digital Active - peri.tr_io_input[6]:0 */ + + /* P3.1 */ + P3_1_GPIO = 0, /* N/A */ + P3_1_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:1 */ + P3_1_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:0 */ + P3_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:18 */ + P3_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:18 */ + P3_1_LCD_COM15 = 12, /* Digital Deep Sleep - lcd.com[15]:0 */ + P3_1_LCD_SEG15 = 13, /* Digital Deep Sleep - lcd.seg[15]:0 */ + P3_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:1 */ + P3_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:1 */ + P3_1_TCPWM0_TR_ONE_CNT_IN258 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[258]:1 */ + P3_1_PERI_TR_IO_INPUT7 = 24, /* Digital Active - peri.tr_io_input[7]:0 */ + + /* P5.0 */ + P5_0_GPIO = 0, /* N/A */ + P5_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:2 */ + P5_0_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:1 */ + P5_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:19 */ + P5_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:19 */ + P5_0_LCD_COM16 = 12, /* Digital Deep Sleep - lcd.com[16]:0 */ + P5_0_LCD_SEG16 = 13, /* Digital Deep Sleep - lcd.seg[16]:0 */ + P5_0_SCB5_UART_RX = 18, /* Digital Active - scb[5].uart_rx:0 */ + P5_0_SCB5_I2C_SCL = 19, /* Digital Active - scb[5].i2c_scl:0 */ + P5_0_SCB5_SPI_MOSI = 20, /* Digital Active - scb[5].spi_mosi:0 */ + P5_0_CANFD0_TTCAN_RX0 = 22, /* Digital Active - canfd[0].ttcan_rx[0] */ + P5_0_TCPWM0_TR_ONE_CNT_IN259 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[259]:1 */ + P5_0_PERI_TR_IO_INPUT10 = 24, /* Digital Active - peri.tr_io_input[10]:0 */ + + /* P5.1 */ + P5_1_GPIO = 0, /* N/A */ + P5_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:2 */ + P5_1_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:1 */ + P5_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:20 */ + P5_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:20 */ + P5_1_LCD_COM17 = 12, /* Digital Deep Sleep - lcd.com[17]:0 */ + P5_1_LCD_SEG17 = 13, /* Digital Deep Sleep - lcd.seg[17]:0 */ + P5_1_SCB5_UART_TX = 18, /* Digital Active - scb[5].uart_tx:0 */ + P5_1_SCB5_I2C_SDA = 19, /* Digital Active - scb[5].i2c_sda:0 */ + P5_1_SCB5_SPI_MISO = 20, /* Digital Active - scb[5].spi_miso:0 */ + P5_1_CANFD0_TTCAN_TX0 = 22, /* Digital Active - canfd[0].ttcan_tx[0] */ + P5_1_TCPWM0_TR_ONE_CNT_IN260 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[260]:1 */ + P5_1_PERI_TR_IO_INPUT11 = 24, /* Digital Active - peri.tr_io_input[11]:0 */ + + /* P5.6 */ + P5_6_GPIO = 0, /* N/A */ + P5_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:2 */ + P5_6_TCPWM0_LINE257 = 9, /* Digital Active - tcpwm[0].line[257]:1 */ + P5_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:22 */ + P5_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:22 */ + P5_6_LCD_COM18 = 12, /* Digital Deep Sleep - lcd.com[18]:0 */ + P5_6_LCD_SEG18 = 13, /* Digital Deep Sleep - lcd.seg[18]:0 */ + P5_6_TCPWM0_TR_ONE_CNT_IN262 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[262]:1 */ + + /* P5.7 */ + P5_7_GPIO = 0, /* N/A */ + P5_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:2 */ + P5_7_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:1 */ + P5_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:23 */ + P5_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:23 */ + P5_7_LCD_COM19 = 12, /* Digital Deep Sleep - lcd.com[19]:0 */ + P5_7_LCD_SEG19 = 13, /* Digital Deep Sleep - lcd.seg[19]:0 */ + P5_7_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:1 */ + + /* P6.2 */ + P6_2_GPIO = 0, /* N/A */ + P6_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:2 */ + P6_2_TCPWM0_LINE259 = 9, /* Digital Active - tcpwm[0].line[259]:1 */ + P6_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:24 */ + P6_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:24 */ + P6_2_LCD_COM22 = 12, /* Digital Deep Sleep - lcd.com[22]:0 */ + P6_2_LCD_SEG22 = 13, /* Digital Deep Sleep - lcd.seg[22]:0 */ + P6_2_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:2 */ + P6_2_CPUSS_FAULT_OUT0 = 25, /* Digital Active - cpuss.fault_out[0] */ + + /* P6.3 */ + P6_3_GPIO = 0, /* N/A */ + P6_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:2 */ + P6_3_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:1 */ + P6_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:25 */ + P6_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:25 */ + P6_3_LCD_COM23 = 12, /* Digital Deep Sleep - lcd.com[23]:0 */ + P6_3_LCD_SEG23 = 13, /* Digital Deep Sleep - lcd.seg[23]:0 */ + P6_3_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:2 */ + P6_3_CPUSS_FAULT_OUT1 = 25, /* Digital Active - cpuss.fault_out[1] */ + + /* P6.4 */ + P6_4_GPIO = 0, /* N/A */ + P6_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:3 */ + P6_4_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:1 */ + P6_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:26 */ + P6_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:26 */ + P6_4_LCD_COM24 = 12, /* Digital Deep Sleep - lcd.com[24]:0 */ + P6_4_LCD_SEG24 = 13, /* Digital Deep Sleep - lcd.seg[24]:0 */ + P6_4_SCB6_I2C_SCL = 14, /* Digital Deep Sleep - scb[6].i2c_scl:0 */ + P6_4_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:2 */ + P6_4_PERI_TR_IO_INPUT12 = 24, /* Digital Active - peri.tr_io_input[12]:0 */ + P6_4_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:1 */ + P6_4_CPUSS_SWJ_SWO_TDO = 29, /* Digital Deep Sleep - cpuss.swj_swo_tdo */ + P6_4_SCB6_SPI_MOSI = 30, /* Digital Deep Sleep - scb[6].spi_mosi:0 */ + P6_4_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:0 */ + + /* P6.5 */ + P6_5_GPIO = 0, /* N/A */ + P6_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:3 */ + P6_5_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:1 */ + P6_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:27 */ + P6_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:27 */ + P6_5_LCD_COM25 = 12, /* Digital Deep Sleep - lcd.com[25]:0 */ + P6_5_LCD_SEG25 = 13, /* Digital Deep Sleep - lcd.seg[25]:0 */ + P6_5_SCB6_I2C_SDA = 14, /* Digital Deep Sleep - scb[6].i2c_sda:0 */ + P6_5_TCPWM0_TR_ONE_CNT_IN3 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:2 */ + P6_5_PERI_TR_IO_INPUT13 = 24, /* Digital Active - peri.tr_io_input[13]:0 */ + P6_5_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:1 */ + P6_5_CPUSS_SWJ_SWDOE_TDI = 29, /* Digital Deep Sleep - cpuss.swj_swdoe_tdi */ + P6_5_SCB6_SPI_MISO = 30, /* Digital Deep Sleep - scb[6].spi_miso:0 */ + P6_5_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:0 */ + + /* P6.6 */ + P6_6_GPIO = 0, /* N/A */ + P6_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:3 */ + P6_6_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:1 */ + P6_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:28 */ + P6_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:28 */ + P6_6_LCD_COM26 = 12, /* Digital Deep Sleep - lcd.com[26]:0 */ + P6_6_LCD_SEG26 = 13, /* Digital Deep Sleep - lcd.seg[26]:0 */ + P6_6_TCPWM0_TR_ONE_CNT_IN256 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[256]:2 */ + P6_6_CPUSS_SWJ_SWDIO_TMS = 29, /* Digital Deep Sleep - cpuss.swj_swdio_tms */ + P6_6_SCB6_SPI_CLK = 30, /* Digital Deep Sleep - scb[6].spi_clk:0 */ + + /* P6.7 */ + P6_7_GPIO = 0, /* N/A */ + P6_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:3 */ + P6_7_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:1 */ + P6_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:29 */ + P6_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:29 */ + P6_7_LCD_COM27 = 12, /* Digital Deep Sleep - lcd.com[27]:0 */ + P6_7_LCD_SEG27 = 13, /* Digital Deep Sleep - lcd.seg[27]:0 */ + P6_7_TCPWM0_TR_ONE_CNT_IN257 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[257]:2 */ + P6_7_CPUSS_SWJ_SWCLK_TCLK = 29, /* Digital Deep Sleep - cpuss.swj_swclk_tclk */ + P6_7_SCB6_SPI_SELECT0 = 30, /* Digital Deep Sleep - scb[6].spi_select0:0 */ + + /* P7.0 */ + P7_0_GPIO = 0, /* N/A */ + P7_0_AMUXA = 4, /* AMUXBUS A */ + P7_0_AMUXB = 5, /* AMUXBUS B */ + P7_0_AMUXA_DSI = 6, /* N/A */ + P7_0_AMUXB_DSI = 7, /* N/A */ + P7_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:2 */ + P7_0_TCPWM0_LINE262 = 9, /* Digital Active - tcpwm[0].line[262]:1 */ + P7_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:30 */ + P7_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:30 */ + P7_0_LCD_COM28 = 12, /* Digital Deep Sleep - lcd.com[28]:0 */ + P7_0_LCD_SEG28 = 13, /* Digital Deep Sleep - lcd.seg[28]:0 */ + P7_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:0 */ + P7_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:0 */ + P7_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:0 */ + P7_0_TCPWM0_TR_ONE_CNT_IN258 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[258]:2 */ + P7_0_PERI_TR_IO_INPUT14 = 24, /* Digital Active - peri.tr_io_input[14]:0 */ + P7_0_CPUSS_TRACE_CLOCK = 26, /* Digital Active - cpuss.trace_clock */ + + /* P7.1 */ + P7_1_GPIO = 0, /* N/A */ + P7_1_AMUXA = 4, /* AMUXBUS A */ + P7_1_AMUXB = 5, /* AMUXBUS B */ + P7_1_AMUXA_DSI = 6, /* N/A */ + P7_1_AMUXB_DSI = 7, /* N/A */ + P7_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:2 */ + P7_1_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:1 */ + P7_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:31 */ + P7_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:31 */ + P7_1_LCD_COM29 = 12, /* Digital Deep Sleep - lcd.com[29]:0 */ + P7_1_LCD_SEG29 = 13, /* Digital Deep Sleep - lcd.seg[29]:0 */ + P7_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:0 */ + P7_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:0 */ + P7_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:0 */ + P7_1_TCPWM0_TR_ONE_CNT_IN259 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[259]:2 */ + P7_1_PERI_TR_IO_INPUT15 = 24, /* Digital Active - peri.tr_io_input[15]:0 */ + + /* P7.2 */ + P7_2_GPIO = 0, /* N/A */ + P7_2_AMUXA = 4, /* AMUXBUS A */ + P7_2_AMUXB = 5, /* AMUXBUS B */ + P7_2_AMUXA_DSI = 6, /* N/A */ + P7_2_AMUXB_DSI = 7, /* N/A */ + P7_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:3 */ + P7_2_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:1 */ + P7_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:32 */ + P7_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:32 */ + P7_2_LCD_COM30 = 12, /* Digital Deep Sleep - lcd.com[30]:0 */ + P7_2_LCD_SEG30 = 13, /* Digital Deep Sleep - lcd.seg[30]:0 */ + P7_2_SCB4_UART_RTS = 18, /* Digital Active - scb[4].uart_rts:0 */ + P7_2_SCB4_SPI_CLK = 20, /* Digital Active - scb[4].spi_clk:0 */ + P7_2_TCPWM0_TR_ONE_CNT_IN260 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[260]:2 */ + + /* P7.3 */ + P7_3_GPIO = 0, /* N/A */ + P7_3_AMUXA = 4, /* AMUXBUS A */ + P7_3_AMUXB = 5, /* AMUXBUS B */ + P7_3_AMUXA_DSI = 6, /* N/A */ + P7_3_AMUXB_DSI = 7, /* N/A */ + P7_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:3 */ + P7_3_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:1 */ + P7_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:33 */ + P7_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:33 */ + P7_3_LCD_COM31 = 12, /* Digital Deep Sleep - lcd.com[31]:0 */ + P7_3_LCD_SEG31 = 13, /* Digital Deep Sleep - lcd.seg[31]:0 */ + P7_3_SCB4_UART_CTS = 18, /* Digital Active - scb[4].uart_cts:0 */ + P7_3_SCB4_SPI_SELECT0 = 20, /* Digital Active - scb[4].spi_select0:0 */ + P7_3_TCPWM0_TR_ONE_CNT_IN261 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[261]:2 */ + + /* P7.7 */ + P7_7_GPIO = 0, /* N/A */ + P7_7_AMUXA = 4, /* AMUXBUS A */ + P7_7_AMUXB = 5, /* AMUXBUS B */ + P7_7_AMUXA_DSI = 6, /* N/A */ + P7_7_AMUXB_DSI = 7, /* N/A */ + P7_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:36 */ + P7_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:36 */ + P7_7_LCD_COM35 = 12, /* Digital Deep Sleep - lcd.com[35]:0 */ + P7_7_LCD_SEG35 = 13, /* Digital Deep Sleep - lcd.seg[35]:0 */ + P7_7_CPUSS_CLK_FM_PUMP = 21, /* Digital Active - cpuss.clk_fm_pump */ + P7_7_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:3 */ + + /* P8.0 */ + P8_0_GPIO = 0, /* N/A */ + P8_0_AMUXA = 4, /* AMUXBUS A */ + P8_0_AMUXB = 5, /* AMUXBUS B */ + P8_0_AMUXA_DSI = 6, /* N/A */ + P8_0_AMUXB_DSI = 7, /* N/A */ + P8_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:3 */ + P8_0_TCPWM0_LINE258 = 9, /* Digital Active - tcpwm[0].line[258]:1 */ + P8_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:37 */ + P8_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:37 */ + P8_0_LCD_COM36 = 12, /* Digital Deep Sleep - lcd.com[36]:0 */ + P8_0_LCD_SEG36 = 13, /* Digital Deep Sleep - lcd.seg[36]:0 */ + P8_0_SCB4_UART_RX = 18, /* Digital Active - scb[4].uart_rx:1 */ + P8_0_SCB4_I2C_SCL = 19, /* Digital Active - scb[4].i2c_scl:1 */ + P8_0_SCB4_SPI_MOSI = 20, /* Digital Active - scb[4].spi_mosi:1 */ + P8_0_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:3 */ + P8_0_PERI_TR_IO_INPUT16 = 24, /* Digital Active - peri.tr_io_input[16]:0 */ + + /* P8.1 */ + P8_1_GPIO = 0, /* N/A */ + P8_1_AMUXA = 4, /* AMUXBUS A */ + P8_1_AMUXB = 5, /* AMUXBUS B */ + P8_1_AMUXA_DSI = 6, /* N/A */ + P8_1_AMUXB_DSI = 7, /* N/A */ + P8_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:3 */ + P8_1_TCPWM0_LINE_COMPL258 = 9, /* Digital Active - tcpwm[0].line_compl[258]:1 */ + P8_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:38 */ + P8_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:38 */ + P8_1_LCD_COM37 = 12, /* Digital Deep Sleep - lcd.com[37]:0 */ + P8_1_LCD_SEG37 = 13, /* Digital Deep Sleep - lcd.seg[37]:0 */ + P8_1_SCB4_UART_TX = 18, /* Digital Active - scb[4].uart_tx:1 */ + P8_1_SCB4_I2C_SDA = 19, /* Digital Active - scb[4].i2c_sda:1 */ + P8_1_SCB4_SPI_MISO = 20, /* Digital Active - scb[4].spi_miso:1 */ + P8_1_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:3 */ + P8_1_PERI_TR_IO_INPUT17 = 24, /* Digital Active - peri.tr_io_input[17]:0 */ + + /* P9.0 */ + P9_0_GPIO = 0, /* N/A */ + P9_0_AMUXA = 4, /* AMUXBUS A */ + P9_0_AMUXB = 5, /* AMUXBUS B */ + P9_0_AMUXA_DSI = 6, /* N/A */ + P9_0_AMUXB_DSI = 7, /* N/A */ + P9_0_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:4 */ + P9_0_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:2 */ + P9_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:39 */ + P9_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:39 */ + P9_0_LCD_COM40 = 12, /* Digital Deep Sleep - lcd.com[40]:0 */ + P9_0_LCD_SEG40 = 13, /* Digital Deep Sleep - lcd.seg[40]:0 */ + P9_0_SCB2_UART_RX = 18, /* Digital Active - scb[2].uart_rx:0 */ + P9_0_SCB2_I2C_SCL = 19, /* Digital Active - scb[2].i2c_scl:0 */ + P9_0_SCB2_SPI_MOSI = 20, /* Digital Active - scb[2].spi_mosi:0 */ + P9_0_TCPWM0_TR_ONE_CNT_IN3 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:3 */ + P9_0_PERI_TR_IO_INPUT18 = 24, /* Digital Active - peri.tr_io_input[18]:0 */ + P9_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:1 */ + + /* P9.1 */ + P9_1_GPIO = 0, /* N/A */ + P9_1_AMUXA = 4, /* AMUXBUS A */ + P9_1_AMUXB = 5, /* AMUXBUS B */ + P9_1_AMUXA_DSI = 6, /* N/A */ + P9_1_AMUXB_DSI = 7, /* N/A */ + P9_1_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:4 */ + P9_1_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:2 */ + P9_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:40 */ + P9_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:40 */ + P9_1_LCD_COM41 = 12, /* Digital Deep Sleep - lcd.com[41]:0 */ + P9_1_LCD_SEG41 = 13, /* Digital Deep Sleep - lcd.seg[41]:0 */ + P9_1_SCB2_UART_TX = 18, /* Digital Active - scb[2].uart_tx:0 */ + P9_1_SCB2_I2C_SDA = 19, /* Digital Active - scb[2].i2c_sda:0 */ + P9_1_SCB2_SPI_MISO = 20, /* Digital Active - scb[2].spi_miso:0 */ + P9_1_TCPWM0_TR_ONE_CNT_IN256 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[256]:3 */ + P9_1_PERI_TR_IO_INPUT19 = 24, /* Digital Active - peri.tr_io_input[19]:0 */ + P9_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:1 */ + P9_1_SRSS_DDFT_PIN_IN0 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[0]:1 */ + + /* P9.2 */ + P9_2_GPIO = 0, /* N/A */ + P9_2_AMUXA = 4, /* AMUXBUS A */ + P9_2_AMUXB = 5, /* AMUXBUS B */ + P9_2_AMUXA_DSI = 6, /* N/A */ + P9_2_AMUXB_DSI = 7, /* N/A */ + P9_2_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:4 */ + P9_2_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:2 */ + P9_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:41 */ + P9_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:41 */ + P9_2_LCD_COM42 = 12, /* Digital Deep Sleep - lcd.com[42]:0 */ + P9_2_LCD_SEG42 = 13, /* Digital Deep Sleep - lcd.seg[42]:0 */ + P9_2_SCB2_UART_RTS = 18, /* Digital Active - scb[2].uart_rts:0 */ + P9_2_SCB2_SPI_CLK = 20, /* Digital Active - scb[2].spi_clk:0 */ + P9_2_PASS_DSI_CTB_CMP0 = 22, /* Digital Active - pass.dsi_ctb_cmp0:1 */ + P9_2_TCPWM0_TR_ONE_CNT_IN257 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[257]:3 */ + P9_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:1 */ + + /* P9.3 */ + P9_3_GPIO = 0, /* N/A */ + P9_3_AMUXA = 4, /* AMUXBUS A */ + P9_3_AMUXB = 5, /* AMUXBUS B */ + P9_3_AMUXA_DSI = 6, /* N/A */ + P9_3_AMUXB_DSI = 7, /* N/A */ + P9_3_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:4 */ + P9_3_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:3 */ + P9_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:42 */ + P9_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:42 */ + P9_3_LCD_COM43 = 12, /* Digital Deep Sleep - lcd.com[43]:0 */ + P9_3_LCD_SEG43 = 13, /* Digital Deep Sleep - lcd.seg[43]:0 */ + P9_3_SCB2_UART_CTS = 18, /* Digital Active - scb[2].uart_cts:0 */ + P9_3_SCB2_SPI_SELECT0 = 20, /* Digital Active - scb[2].spi_select0:0 */ + P9_3_PASS_DSI_CTB_CMP1 = 22, /* Digital Active - pass.dsi_ctb_cmp1:1 */ + P9_3_TCPWM0_TR_ONE_CNT_IN258 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[258]:3 */ + P9_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:1 */ + P9_3_SRSS_DDFT_PIN_IN1 = 31, /* Digital Deep Sleep - srss.ddft_pin_in[1]:1 */ + + /* P10.0 */ + P10_0_GPIO = 0, /* N/A */ + P10_0_AMUXA = 4, /* AMUXBUS A */ + P10_0_AMUXB = 5, /* AMUXBUS B */ + P10_0_AMUXA_DSI = 6, /* N/A */ + P10_0_AMUXB_DSI = 7, /* N/A */ + P10_0_TCPWM0_LINE2 = 8, /* Digital Active - tcpwm[0].line[2]:4 */ + P10_0_TCPWM0_LINE262 = 9, /* Digital Active - tcpwm[0].line[262]:2 */ + P10_0_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:45 */ + P10_0_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:45 */ + P10_0_LCD_COM44 = 12, /* Digital Deep Sleep - lcd.com[44]:0 */ + P10_0_LCD_SEG44 = 13, /* Digital Deep Sleep - lcd.seg[44]:0 */ + P10_0_SCB1_UART_RX = 18, /* Digital Active - scb[1].uart_rx:0 */ + P10_0_SCB1_I2C_SCL = 19, /* Digital Active - scb[1].i2c_scl:0 */ + P10_0_SCB1_SPI_MOSI = 20, /* Digital Active - scb[1].spi_mosi:0 */ + P10_0_TCPWM0_TR_ONE_CNT_IN261 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[261]:3 */ + P10_0_PERI_TR_IO_INPUT20 = 24, /* Digital Active - peri.tr_io_input[20]:0 */ + P10_0_CPUSS_TRACE_DATA3 = 27, /* Digital Active - cpuss.trace_data[3]:0 */ + + /* P10.1 */ + P10_1_GPIO = 0, /* N/A */ + P10_1_AMUXA = 4, /* AMUXBUS A */ + P10_1_AMUXB = 5, /* AMUXBUS B */ + P10_1_AMUXA_DSI = 6, /* N/A */ + P10_1_AMUXB_DSI = 7, /* N/A */ + P10_1_TCPWM0_LINE_COMPL2 = 8, /* Digital Active - tcpwm[0].line_compl[2]:4 */ + P10_1_TCPWM0_LINE_COMPL262 = 9, /* Digital Active - tcpwm[0].line_compl[262]:2 */ + P10_1_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:46 */ + P10_1_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:46 */ + P10_1_LCD_COM45 = 12, /* Digital Deep Sleep - lcd.com[45]:0 */ + P10_1_LCD_SEG45 = 13, /* Digital Deep Sleep - lcd.seg[45]:0 */ + P10_1_SCB1_UART_TX = 18, /* Digital Active - scb[1].uart_tx:0 */ + P10_1_SCB1_I2C_SDA = 19, /* Digital Active - scb[1].i2c_sda:0 */ + P10_1_SCB1_SPI_MISO = 20, /* Digital Active - scb[1].spi_miso:0 */ + P10_1_TCPWM0_TR_ONE_CNT_IN262 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[262]:3 */ + P10_1_PERI_TR_IO_INPUT21 = 24, /* Digital Active - peri.tr_io_input[21]:0 */ + P10_1_CPUSS_TRACE_DATA2 = 27, /* Digital Active - cpuss.trace_data[2]:0 */ + + /* P10.2 */ + P10_2_GPIO = 0, /* N/A */ + P10_2_AMUXA = 4, /* AMUXBUS A */ + P10_2_AMUXB = 5, /* AMUXBUS B */ + P10_2_AMUXA_DSI = 6, /* N/A */ + P10_2_AMUXB_DSI = 7, /* N/A */ + P10_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:4 */ + P10_2_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:2 */ + P10_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:47 */ + P10_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:47 */ + P10_2_LCD_COM46 = 12, /* Digital Deep Sleep - lcd.com[46]:0 */ + P10_2_LCD_SEG46 = 13, /* Digital Deep Sleep - lcd.seg[46]:0 */ + P10_2_SCB1_UART_RTS = 18, /* Digital Active - scb[1].uart_rts:0 */ + P10_2_SCB1_SPI_CLK = 20, /* Digital Active - scb[1].spi_clk:0 */ + P10_2_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:3 */ + P10_2_CPUSS_TRACE_DATA1 = 27, /* Digital Active - cpuss.trace_data[1]:0 */ + + /* P10.3 */ + P10_3_GPIO = 0, /* N/A */ + P10_3_AMUXA = 4, /* AMUXBUS A */ + P10_3_AMUXB = 5, /* AMUXBUS B */ + P10_3_AMUXA_DSI = 6, /* N/A */ + P10_3_AMUXB_DSI = 7, /* N/A */ + P10_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:4 */ + P10_3_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:2 */ + P10_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:48 */ + P10_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:48 */ + P10_3_LCD_COM47 = 12, /* Digital Deep Sleep - lcd.com[47]:0 */ + P10_3_LCD_SEG47 = 13, /* Digital Deep Sleep - lcd.seg[47]:0 */ + P10_3_SCB1_UART_CTS = 18, /* Digital Active - scb[1].uart_cts:0 */ + P10_3_SCB1_SPI_SELECT0 = 20, /* Digital Active - scb[1].spi_select0:0 */ + P10_3_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:4 */ + P10_3_CPUSS_TRACE_DATA0 = 27, /* Digital Active - cpuss.trace_data[0]:0 */ + + /* P10.4 */ + P10_4_GPIO = 0, /* N/A */ + P10_4_AMUXA = 4, /* AMUXBUS A */ + P10_4_AMUXB = 5, /* AMUXBUS B */ + P10_4_AMUXA_DSI = 6, /* N/A */ + P10_4_AMUXB_DSI = 7, /* N/A */ + P10_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:5 */ + P10_4_TCPWM0_LINE256 = 9, /* Digital Active - tcpwm[0].line[256]:2 */ + P10_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:49 */ + P10_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:49 */ + P10_4_LCD_COM48 = 12, /* Digital Deep Sleep - lcd.com[48]:0 */ + P10_4_LCD_SEG48 = 13, /* Digital Deep Sleep - lcd.seg[48]:0 */ + P10_4_SCB1_SPI_SELECT1 = 20, /* Digital Active - scb[1].spi_select1:0 */ + P10_4_TCPWM0_TR_ONE_CNT_IN1 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:4 */ + + /* P10.5 */ + P10_5_GPIO = 0, /* N/A */ + P10_5_AMUXA = 4, /* AMUXBUS A */ + P10_5_AMUXB = 5, /* AMUXBUS B */ + P10_5_AMUXA_DSI = 6, /* N/A */ + P10_5_AMUXB_DSI = 7, /* N/A */ + P10_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:5 */ + P10_5_TCPWM0_LINE_COMPL256 = 9, /* Digital Active - tcpwm[0].line_compl[256]:2 */ + P10_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:50 */ + P10_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:50 */ + P10_5_LCD_COM49 = 12, /* Digital Deep Sleep - lcd.com[49]:0 */ + P10_5_LCD_SEG49 = 13, /* Digital Deep Sleep - lcd.seg[49]:0 */ + P10_5_SCB1_SPI_SELECT2 = 20, /* Digital Active - scb[1].spi_select2:0 */ + P10_5_TCPWM0_TR_ONE_CNT_IN2 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[2]:4 */ + + /* P10.6 */ + P10_6_GPIO = 0, /* N/A */ + P10_6_AMUXA = 4, /* AMUXBUS A */ + P10_6_AMUXB = 5, /* AMUXBUS B */ + P10_6_AMUXA_DSI = 6, /* N/A */ + P10_6_AMUXB_DSI = 7, /* N/A */ + P10_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:5 */ + P10_6_TCPWM0_LINE257 = 9, /* Digital Active - tcpwm[0].line[257]:2 */ + P10_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:51 */ + P10_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:51 */ + P10_6_LCD_COM50 = 12, /* Digital Deep Sleep - lcd.com[50]:0 */ + P10_6_LCD_SEG50 = 13, /* Digital Deep Sleep - lcd.seg[50]:0 */ + P10_6_SCB1_SPI_SELECT3 = 20, /* Digital Active - scb[1].spi_select3:0 */ + P10_6_TCPWM0_TR_ONE_CNT_IN3 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[3]:4 */ + P10_6_PERI_TR_IO_INPUT22 = 24, /* Digital Active - peri.tr_io_input[22]:0 */ + + /* P10.7 */ + P10_7_GPIO = 0, /* N/A */ + P10_7_AMUXA = 4, /* AMUXBUS A */ + P10_7_AMUXB = 5, /* AMUXBUS B */ + P10_7_AMUXA_DSI = 6, /* N/A */ + P10_7_AMUXB_DSI = 7, /* N/A */ + P10_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:5 */ + P10_7_TCPWM0_LINE_COMPL257 = 9, /* Digital Active - tcpwm[0].line_compl[257]:2 */ + P10_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:52 */ + P10_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:52 */ + P10_7_LCD_COM51 = 12, /* Digital Deep Sleep - lcd.com[51]:0 */ + P10_7_LCD_SEG51 = 13, /* Digital Deep Sleep - lcd.seg[51]:0 */ + P10_7_SMIF_SPI_SELECT2 = 17, /* Digital Active - smif.spi_select2 */ + P10_7_TCPWM0_TR_ONE_CNT_IN256 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[256]:4 */ + P10_7_PERI_TR_IO_INPUT23 = 24, /* Digital Active - peri.tr_io_input[23]:0 */ + + /* P11.2 */ + P11_2_GPIO = 0, /* N/A */ + P11_2_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:5 */ + P11_2_TCPWM0_LINE259 = 9, /* Digital Active - tcpwm[0].line[259]:2 */ + P11_2_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:54 */ + P11_2_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:54 */ + P11_2_LCD_COM54 = 12, /* Digital Deep Sleep - lcd.com[54]:0 */ + P11_2_LCD_SEG54 = 13, /* Digital Deep Sleep - lcd.seg[54]:0 */ + P11_2_SMIF_SPI_SELECT0 = 17, /* Digital Active - smif.spi_select0 */ + P11_2_SCB5_UART_RTS = 18, /* Digital Active - scb[5].uart_rts:0 */ + P11_2_SCB5_SPI_CLK = 20, /* Digital Active - scb[5].spi_clk:0 */ + P11_2_TCPWM0_TR_ONE_CNT_IN258 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[258]:4 */ + + /* P11.3 */ + P11_3_GPIO = 0, /* N/A */ + P11_3_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:5 */ + P11_3_TCPWM0_LINE_COMPL259 = 9, /* Digital Active - tcpwm[0].line_compl[259]:2 */ + P11_3_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:55 */ + P11_3_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:55 */ + P11_3_LCD_COM55 = 12, /* Digital Deep Sleep - lcd.com[55]:0 */ + P11_3_LCD_SEG55 = 13, /* Digital Deep Sleep - lcd.seg[55]:0 */ + P11_3_SMIF_SPI_DATA3 = 17, /* Digital Active - smif.spi_data3 */ + P11_3_SCB5_UART_CTS = 18, /* Digital Active - scb[5].uart_cts:0 */ + P11_3_SCB5_SPI_SELECT0 = 20, /* Digital Active - scb[5].spi_select0:0 */ + P11_3_TCPWM0_TR_ONE_CNT_IN259 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[259]:4 */ + P11_3_PERI_TR_IO_OUTPUT0 = 25, /* Digital Active - peri.tr_io_output[0]:0 */ + + /* P11.4 */ + P11_4_GPIO = 0, /* N/A */ + P11_4_TCPWM0_LINE0 = 8, /* Digital Active - tcpwm[0].line[0]:6 */ + P11_4_TCPWM0_LINE260 = 9, /* Digital Active - tcpwm[0].line[260]:3 */ + P11_4_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:56 */ + P11_4_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:56 */ + P11_4_LCD_COM56 = 12, /* Digital Deep Sleep - lcd.com[56]:0 */ + P11_4_LCD_SEG56 = 13, /* Digital Deep Sleep - lcd.seg[56]:0 */ + P11_4_SMIF_SPI_DATA2 = 17, /* Digital Active - smif.spi_data2 */ + P11_4_SCB5_SPI_SELECT1 = 20, /* Digital Active - scb[5].spi_select1:0 */ + P11_4_TCPWM0_TR_ONE_CNT_IN260 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[260]:4 */ + P11_4_PERI_TR_IO_OUTPUT1 = 25, /* Digital Active - peri.tr_io_output[1]:0 */ + + /* P11.5 */ + P11_5_GPIO = 0, /* N/A */ + P11_5_TCPWM0_LINE_COMPL0 = 8, /* Digital Active - tcpwm[0].line_compl[0]:6 */ + P11_5_TCPWM0_LINE_COMPL260 = 9, /* Digital Active - tcpwm[0].line_compl[260]:3 */ + P11_5_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:57 */ + P11_5_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:57 */ + P11_5_LCD_COM57 = 12, /* Digital Deep Sleep - lcd.com[57]:0 */ + P11_5_LCD_SEG57 = 13, /* Digital Deep Sleep - lcd.seg[57]:0 */ + P11_5_SMIF_SPI_DATA1 = 17, /* Digital Active - smif.spi_data1 */ + P11_5_SCB5_SPI_SELECT2 = 20, /* Digital Active - scb[5].spi_select2:0 */ + P11_5_TCPWM0_TR_ONE_CNT_IN261 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[261]:4 */ + + /* P11.6 */ + P11_6_GPIO = 0, /* N/A */ + P11_6_TCPWM0_LINE1 = 8, /* Digital Active - tcpwm[0].line[1]:6 */ + P11_6_TCPWM0_LINE261 = 9, /* Digital Active - tcpwm[0].line[261]:3 */ + P11_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:58 */ + P11_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:58 */ + P11_6_LCD_COM58 = 12, /* Digital Deep Sleep - lcd.com[58]:0 */ + P11_6_LCD_SEG58 = 13, /* Digital Deep Sleep - lcd.seg[58]:0 */ + P11_6_SMIF_SPI_DATA0 = 17, /* Digital Active - smif.spi_data0 */ + P11_6_SCB5_SPI_SELECT3 = 20, /* Digital Active - scb[5].spi_select3:0 */ + P11_6_TCPWM0_TR_ONE_CNT_IN262 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[262]:4 */ + + /* P11.7 */ + P11_7_GPIO = 0, /* N/A */ + P11_7_TCPWM0_LINE_COMPL1 = 8, /* Digital Active - tcpwm[0].line_compl[1]:6 */ + P11_7_TCPWM0_LINE_COMPL261 = 9, /* Digital Active - tcpwm[0].line_compl[261]:2 */ + P11_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:59 */ + P11_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:59 */ + P11_7_LCD_COM59 = 12, /* Digital Deep Sleep - lcd.com[59]:0 */ + P11_7_LCD_SEG59 = 13, /* Digital Deep Sleep - lcd.seg[59]:0 */ + P11_7_SMIF_SPI_CLK = 17, /* Digital Active - smif.spi_clk */ + P11_7_TCPWM0_TR_ONE_CNT_IN263 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[263]:4 */ + + /* P12.6 */ + P12_6_GPIO = 0, /* N/A */ + P12_6_TCPWM0_LINE3 = 8, /* Digital Active - tcpwm[0].line[3]:6 */ + P12_6_TCPWM0_LINE263 = 9, /* Digital Active - tcpwm[0].line[263]:3 */ + P12_6_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:60 */ + P12_6_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:60 */ + P12_6_LCD_COM2 = 12, /* Digital Deep Sleep - lcd.com[2]:1 */ + P12_6_LCD_SEG2 = 13, /* Digital Deep Sleep - lcd.seg[2]:1 */ + P12_6_TCPWM0_TR_ONE_CNT_IN0 = 23, /* Digital Active - tcpwm[0].tr_one_cnt_in[0]:5 */ + + /* P12.7 */ + P12_7_GPIO = 0, /* N/A */ + P12_7_TCPWM0_LINE_COMPL3 = 8, /* Digital Active - tcpwm[0].line_compl[3]:6 */ + P12_7_TCPWM0_LINE_COMPL263 = 9, /* Digital Active - tcpwm[0].line_compl[263]:3 */ + P12_7_CSD_CSD_TX = 10, /* Digital Active - csd.csd_tx:61 */ + P12_7_CSD_CSD_TX_N = 11, /* Digital Active - csd.csd_tx_n:61 */ + P12_7_LCD_COM3 = 12, /* Digital Deep Sleep - lcd.com[3]:1 */ + P12_7_LCD_SEG3 = 13, /* Digital Deep Sleep - lcd.seg[3]:1 */ + P12_7_TCPWM0_TR_ONE_CNT_IN1 = 23 /* Digital Active - tcpwm[0].tr_one_cnt_in[1]:5 */ +} en_hsiom_sel_t; + +#endif /* _GPIO_PSOC6_04_68_QFN_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ctbm_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ctbm_v2.h new file mode 100644 index 00000000000..54b84f2af65 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_ctbm_v2.h @@ -0,0 +1,271 @@ +/***************************************************************************//** +* \file cyip_ctbm_v2.h +* +* \brief +* CTBM IP definitions +* +* \note +* Generator version: 1.5.1.36 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYIP_CTBM_V2_H_ +#define _CYIP_CTBM_V2_H_ + +#include "cyip_headers.h" + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM_V2_SECTION_SIZE 0x00010000UL + +/** + * \brief Continuous Time Block Mini (CTBM) + */ +typedef struct { + __IOM uint32_t CTB_CTRL; /*!< 0x00000000 global CTB and power control */ + __IOM uint32_t OA_RES0_CTRL; /*!< 0x00000004 Opamp0 and resistor0 control */ + __IOM uint32_t OA_RES1_CTRL; /*!< 0x00000008 Opamp1 and resistor1 control */ + __IM uint32_t COMP_STAT; /*!< 0x0000000C Comparator status */ + __IM uint32_t RESERVED[4]; + __IOM uint32_t INTR; /*!< 0x00000020 Interrupt request register */ + __IOM uint32_t INTR_SET; /*!< 0x00000024 Interrupt request set register */ + __IOM uint32_t INTR_MASK; /*!< 0x00000028 Interrupt request mask */ + __IM uint32_t INTR_MASKED; /*!< 0x0000002C Interrupt request masked */ + __IM uint32_t RESERVED1[20]; + __IOM uint32_t OA0_SW; /*!< 0x00000080 Opamp0 switch control */ + __IOM uint32_t OA0_SW_CLEAR; /*!< 0x00000084 Opamp0 switch control clear */ + __IOM uint32_t OA1_SW; /*!< 0x00000088 Opamp1 switch control */ + __IOM uint32_t OA1_SW_CLEAR; /*!< 0x0000008C Opamp1 switch control clear */ + __IM uint32_t RESERVED2[4]; + __IOM uint32_t CTD_SW; /*!< 0x000000A0 CTDAC connection switch control */ + __IOM uint32_t CTD_SW_CLEAR; /*!< 0x000000A4 CTDAC connection switch control clear */ + __IM uint32_t RESERVED3[6]; + __IOM uint32_t CTB_SW_DS_CTRL; /*!< 0x000000C0 CTB bus switch control */ + __IOM uint32_t CTB_SW_SQ_CTRL; /*!< 0x000000C4 CTB bus switch Sar Sequencer control */ + __IM uint32_t CTB_SW_STATUS; /*!< 0x000000C8 CTB bus switch control status */ +} CTBM_V2_Type; /*!< Size = 204 (0xCC) */ + + +/* CTBM.CTB_CTRL */ +#define CTBM_V2_CTB_CTRL_DEEPSLEEP_ON_Pos 30UL +#define CTBM_V2_CTB_CTRL_DEEPSLEEP_ON_Msk 0x40000000UL +#define CTBM_V2_CTB_CTRL_ENABLED_Pos 31UL +#define CTBM_V2_CTB_CTRL_ENABLED_Msk 0x80000000UL +/* CTBM.OA_RES0_CTRL */ +#define CTBM_V2_OA_RES0_CTRL_OA0_PWR_MODE_Pos 0UL +#define CTBM_V2_OA_RES0_CTRL_OA0_PWR_MODE_Msk 0x7UL +#define CTBM_V2_OA_RES0_CTRL_OA0_DRIVE_STR_SEL_Pos 3UL +#define CTBM_V2_OA_RES0_CTRL_OA0_DRIVE_STR_SEL_Msk 0x8UL +#define CTBM_V2_OA_RES0_CTRL_OA0_COMP_EN_Pos 4UL +#define CTBM_V2_OA_RES0_CTRL_OA0_COMP_EN_Msk 0x10UL +#define CTBM_V2_OA_RES0_CTRL_OA0_HYST_EN_Pos 5UL +#define CTBM_V2_OA_RES0_CTRL_OA0_HYST_EN_Msk 0x20UL +#define CTBM_V2_OA_RES0_CTRL_OA0_BYPASS_DSI_SYNC_Pos 6UL +#define CTBM_V2_OA_RES0_CTRL_OA0_BYPASS_DSI_SYNC_Msk 0x40UL +#define CTBM_V2_OA_RES0_CTRL_OA0_DSI_LEVEL_Pos 7UL +#define CTBM_V2_OA_RES0_CTRL_OA0_DSI_LEVEL_Msk 0x80UL +#define CTBM_V2_OA_RES0_CTRL_OA0_COMPINT_Pos 8UL +#define CTBM_V2_OA_RES0_CTRL_OA0_COMPINT_Msk 0x300UL +#define CTBM_V2_OA_RES0_CTRL_OA0_PUMP_EN_Pos 11UL +#define CTBM_V2_OA_RES0_CTRL_OA0_PUMP_EN_Msk 0x800UL +#define CTBM_V2_OA_RES0_CTRL_OA0_BOOST_EN_Pos 12UL +#define CTBM_V2_OA_RES0_CTRL_OA0_BOOST_EN_Msk 0x1000UL +/* CTBM.OA_RES1_CTRL */ +#define CTBM_V2_OA_RES1_CTRL_OA1_PWR_MODE_Pos 0UL +#define CTBM_V2_OA_RES1_CTRL_OA1_PWR_MODE_Msk 0x7UL +#define CTBM_V2_OA_RES1_CTRL_OA1_DRIVE_STR_SEL_Pos 3UL +#define CTBM_V2_OA_RES1_CTRL_OA1_DRIVE_STR_SEL_Msk 0x8UL +#define CTBM_V2_OA_RES1_CTRL_OA1_COMP_EN_Pos 4UL +#define CTBM_V2_OA_RES1_CTRL_OA1_COMP_EN_Msk 0x10UL +#define CTBM_V2_OA_RES1_CTRL_OA1_HYST_EN_Pos 5UL +#define CTBM_V2_OA_RES1_CTRL_OA1_HYST_EN_Msk 0x20UL +#define CTBM_V2_OA_RES1_CTRL_OA1_BYPASS_DSI_SYNC_Pos 6UL +#define CTBM_V2_OA_RES1_CTRL_OA1_BYPASS_DSI_SYNC_Msk 0x40UL +#define CTBM_V2_OA_RES1_CTRL_OA1_DSI_LEVEL_Pos 7UL +#define CTBM_V2_OA_RES1_CTRL_OA1_DSI_LEVEL_Msk 0x80UL +#define CTBM_V2_OA_RES1_CTRL_OA1_COMPINT_Pos 8UL +#define CTBM_V2_OA_RES1_CTRL_OA1_COMPINT_Msk 0x300UL +#define CTBM_V2_OA_RES1_CTRL_OA1_PUMP_EN_Pos 11UL +#define CTBM_V2_OA_RES1_CTRL_OA1_PUMP_EN_Msk 0x800UL +#define CTBM_V2_OA_RES1_CTRL_OA1_BOOST_EN_Pos 12UL +#define CTBM_V2_OA_RES1_CTRL_OA1_BOOST_EN_Msk 0x1000UL +/* CTBM.COMP_STAT */ +#define CTBM_V2_COMP_STAT_OA0_COMP_Pos 0UL +#define CTBM_V2_COMP_STAT_OA0_COMP_Msk 0x1UL +#define CTBM_V2_COMP_STAT_OA1_COMP_Pos 16UL +#define CTBM_V2_COMP_STAT_OA1_COMP_Msk 0x10000UL +/* CTBM.INTR */ +#define CTBM_V2_INTR_COMP0_Pos 0UL +#define CTBM_V2_INTR_COMP0_Msk 0x1UL +#define CTBM_V2_INTR_COMP1_Pos 1UL +#define CTBM_V2_INTR_COMP1_Msk 0x2UL +/* CTBM.INTR_SET */ +#define CTBM_V2_INTR_SET_COMP0_SET_Pos 0UL +#define CTBM_V2_INTR_SET_COMP0_SET_Msk 0x1UL +#define CTBM_V2_INTR_SET_COMP1_SET_Pos 1UL +#define CTBM_V2_INTR_SET_COMP1_SET_Msk 0x2UL +/* CTBM.INTR_MASK */ +#define CTBM_V2_INTR_MASK_COMP0_MASK_Pos 0UL +#define CTBM_V2_INTR_MASK_COMP0_MASK_Msk 0x1UL +#define CTBM_V2_INTR_MASK_COMP1_MASK_Pos 1UL +#define CTBM_V2_INTR_MASK_COMP1_MASK_Msk 0x2UL +/* CTBM.INTR_MASKED */ +#define CTBM_V2_INTR_MASKED_COMP0_MASKED_Pos 0UL +#define CTBM_V2_INTR_MASKED_COMP0_MASKED_Msk 0x1UL +#define CTBM_V2_INTR_MASKED_COMP1_MASKED_Pos 1UL +#define CTBM_V2_INTR_MASKED_COMP1_MASKED_Msk 0x2UL +/* CTBM.OA0_SW */ +#define CTBM_V2_OA0_SW_OA0P_A00_Pos 0UL +#define CTBM_V2_OA0_SW_OA0P_A00_Msk 0x1UL +#define CTBM_V2_OA0_SW_OA0P_A20_Pos 2UL +#define CTBM_V2_OA0_SW_OA0P_A20_Msk 0x4UL +#define CTBM_V2_OA0_SW_OA0P_A30_Pos 3UL +#define CTBM_V2_OA0_SW_OA0P_A30_Msk 0x8UL +#define CTBM_V2_OA0_SW_OA0M_A11_Pos 8UL +#define CTBM_V2_OA0_SW_OA0M_A11_Msk 0x100UL +#define CTBM_V2_OA0_SW_OA0M_A81_Pos 14UL +#define CTBM_V2_OA0_SW_OA0M_A81_Msk 0x4000UL +#define CTBM_V2_OA0_SW_OA0O_D51_Pos 18UL +#define CTBM_V2_OA0_SW_OA0O_D51_Msk 0x40000UL +#define CTBM_V2_OA0_SW_OA0O_D81_Pos 21UL +#define CTBM_V2_OA0_SW_OA0O_D81_Msk 0x200000UL +/* CTBM.OA0_SW_CLEAR */ +#define CTBM_V2_OA0_SW_CLEAR_OA0P_A00_Pos 0UL +#define CTBM_V2_OA0_SW_CLEAR_OA0P_A00_Msk 0x1UL +#define CTBM_V2_OA0_SW_CLEAR_OA0P_A20_Pos 2UL +#define CTBM_V2_OA0_SW_CLEAR_OA0P_A20_Msk 0x4UL +#define CTBM_V2_OA0_SW_CLEAR_OA0P_A30_Pos 3UL +#define CTBM_V2_OA0_SW_CLEAR_OA0P_A30_Msk 0x8UL +#define CTBM_V2_OA0_SW_CLEAR_OA0M_A11_Pos 8UL +#define CTBM_V2_OA0_SW_CLEAR_OA0M_A11_Msk 0x100UL +#define CTBM_V2_OA0_SW_CLEAR_OA0M_A81_Pos 14UL +#define CTBM_V2_OA0_SW_CLEAR_OA0M_A81_Msk 0x4000UL +#define CTBM_V2_OA0_SW_CLEAR_OA0O_D51_Pos 18UL +#define CTBM_V2_OA0_SW_CLEAR_OA0O_D51_Msk 0x40000UL +#define CTBM_V2_OA0_SW_CLEAR_OA0O_D81_Pos 21UL +#define CTBM_V2_OA0_SW_CLEAR_OA0O_D81_Msk 0x200000UL +/* CTBM.OA1_SW */ +#define CTBM_V2_OA1_SW_OA1P_A03_Pos 0UL +#define CTBM_V2_OA1_SW_OA1P_A03_Msk 0x1UL +#define CTBM_V2_OA1_SW_OA1P_A13_Pos 1UL +#define CTBM_V2_OA1_SW_OA1P_A13_Msk 0x2UL +#define CTBM_V2_OA1_SW_OA1P_A43_Pos 4UL +#define CTBM_V2_OA1_SW_OA1P_A43_Msk 0x10UL +#define CTBM_V2_OA1_SW_OA1P_A73_Pos 7UL +#define CTBM_V2_OA1_SW_OA1P_A73_Msk 0x80UL +#define CTBM_V2_OA1_SW_OA1M_A22_Pos 8UL +#define CTBM_V2_OA1_SW_OA1M_A22_Msk 0x100UL +#define CTBM_V2_OA1_SW_OA1M_A82_Pos 14UL +#define CTBM_V2_OA1_SW_OA1M_A82_Msk 0x4000UL +#define CTBM_V2_OA1_SW_OA1O_D52_Pos 18UL +#define CTBM_V2_OA1_SW_OA1O_D52_Msk 0x40000UL +#define CTBM_V2_OA1_SW_OA1O_D62_Pos 19UL +#define CTBM_V2_OA1_SW_OA1O_D62_Msk 0x80000UL +#define CTBM_V2_OA1_SW_OA1O_D82_Pos 21UL +#define CTBM_V2_OA1_SW_OA1O_D82_Msk 0x200000UL +/* CTBM.OA1_SW_CLEAR */ +#define CTBM_V2_OA1_SW_CLEAR_OA1P_A03_Pos 0UL +#define CTBM_V2_OA1_SW_CLEAR_OA1P_A03_Msk 0x1UL +#define CTBM_V2_OA1_SW_CLEAR_OA1P_A13_Pos 1UL +#define CTBM_V2_OA1_SW_CLEAR_OA1P_A13_Msk 0x2UL +#define CTBM_V2_OA1_SW_CLEAR_OA1P_A43_Pos 4UL +#define CTBM_V2_OA1_SW_CLEAR_OA1P_A43_Msk 0x10UL +#define CTBM_V2_OA1_SW_CLEAR_OA1P_A73_Pos 7UL +#define CTBM_V2_OA1_SW_CLEAR_OA1P_A73_Msk 0x80UL +#define CTBM_V2_OA1_SW_CLEAR_OA1M_A22_Pos 8UL +#define CTBM_V2_OA1_SW_CLEAR_OA1M_A22_Msk 0x100UL +#define CTBM_V2_OA1_SW_CLEAR_OA1M_A82_Pos 14UL +#define CTBM_V2_OA1_SW_CLEAR_OA1M_A82_Msk 0x4000UL +#define CTBM_V2_OA1_SW_CLEAR_OA1O_D52_Pos 18UL +#define CTBM_V2_OA1_SW_CLEAR_OA1O_D52_Msk 0x40000UL +#define CTBM_V2_OA1_SW_CLEAR_OA1O_D62_Pos 19UL +#define CTBM_V2_OA1_SW_CLEAR_OA1O_D62_Msk 0x80000UL +#define CTBM_V2_OA1_SW_CLEAR_OA1O_D82_Pos 21UL +#define CTBM_V2_OA1_SW_CLEAR_OA1O_D82_Msk 0x200000UL +/* CTBM.CTD_SW */ +#define CTBM_V2_CTD_SW_CTDD_CRD_Pos 1UL +#define CTBM_V2_CTD_SW_CTDD_CRD_Msk 0x2UL +#define CTBM_V2_CTD_SW_CTDS_CRS_Pos 4UL +#define CTBM_V2_CTD_SW_CTDS_CRS_Msk 0x10UL +#define CTBM_V2_CTD_SW_CTDS_COR_Pos 5UL +#define CTBM_V2_CTD_SW_CTDS_COR_Msk 0x20UL +#define CTBM_V2_CTD_SW_CTDO_C6H_Pos 8UL +#define CTBM_V2_CTD_SW_CTDO_C6H_Msk 0x100UL +#define CTBM_V2_CTD_SW_CTDO_COS_Pos 9UL +#define CTBM_V2_CTD_SW_CTDO_COS_Msk 0x200UL +#define CTBM_V2_CTD_SW_CTDH_COB_Pos 10UL +#define CTBM_V2_CTD_SW_CTDH_COB_Msk 0x400UL +#define CTBM_V2_CTD_SW_CTDH_CHD_Pos 12UL +#define CTBM_V2_CTD_SW_CTDH_CHD_Msk 0x1000UL +#define CTBM_V2_CTD_SW_CTDH_CA0_Pos 13UL +#define CTBM_V2_CTD_SW_CTDH_CA0_Msk 0x2000UL +#define CTBM_V2_CTD_SW_CTDH_CIS_Pos 14UL +#define CTBM_V2_CTD_SW_CTDH_CIS_Msk 0x4000UL +#define CTBM_V2_CTD_SW_CTDH_ILR_Pos 15UL +#define CTBM_V2_CTD_SW_CTDH_ILR_Msk 0x8000UL +/* CTBM.CTD_SW_CLEAR */ +#define CTBM_V2_CTD_SW_CLEAR_CTDD_CRD_Pos 1UL +#define CTBM_V2_CTD_SW_CLEAR_CTDD_CRD_Msk 0x2UL +#define CTBM_V2_CTD_SW_CLEAR_CTDS_CRS_Pos 4UL +#define CTBM_V2_CTD_SW_CLEAR_CTDS_CRS_Msk 0x10UL +#define CTBM_V2_CTD_SW_CLEAR_CTDS_COR_Pos 5UL +#define CTBM_V2_CTD_SW_CLEAR_CTDS_COR_Msk 0x20UL +#define CTBM_V2_CTD_SW_CLEAR_CTDO_C6H_Pos 8UL +#define CTBM_V2_CTD_SW_CLEAR_CTDO_C6H_Msk 0x100UL +#define CTBM_V2_CTD_SW_CLEAR_CTDO_COS_Pos 9UL +#define CTBM_V2_CTD_SW_CLEAR_CTDO_COS_Msk 0x200UL +#define CTBM_V2_CTD_SW_CLEAR_CTDH_COB_Pos 10UL +#define CTBM_V2_CTD_SW_CLEAR_CTDH_COB_Msk 0x400UL +#define CTBM_V2_CTD_SW_CLEAR_CTDH_CHD_Pos 12UL +#define CTBM_V2_CTD_SW_CLEAR_CTDH_CHD_Msk 0x1000UL +#define CTBM_V2_CTD_SW_CLEAR_CTDH_CA0_Pos 13UL +#define CTBM_V2_CTD_SW_CLEAR_CTDH_CA0_Msk 0x2000UL +#define CTBM_V2_CTD_SW_CLEAR_CTDH_CIS_Pos 14UL +#define CTBM_V2_CTD_SW_CLEAR_CTDH_CIS_Msk 0x4000UL +#define CTBM_V2_CTD_SW_CLEAR_CTDH_ILR_Pos 15UL +#define CTBM_V2_CTD_SW_CLEAR_CTDH_ILR_Msk 0x8000UL +/* CTBM.CTB_SW_DS_CTRL */ +#define CTBM_V2_CTB_SW_DS_CTRL_P2_DS_CTRL23_Pos 10UL +#define CTBM_V2_CTB_SW_DS_CTRL_P2_DS_CTRL23_Msk 0x400UL +#define CTBM_V2_CTB_SW_DS_CTRL_P3_DS_CTRL23_Pos 11UL +#define CTBM_V2_CTB_SW_DS_CTRL_P3_DS_CTRL23_Msk 0x800UL +#define CTBM_V2_CTB_SW_DS_CTRL_CTD_COS_DS_CTRL_Pos 31UL +#define CTBM_V2_CTB_SW_DS_CTRL_CTD_COS_DS_CTRL_Msk 0x80000000UL +/* CTBM.CTB_SW_SQ_CTRL */ +#define CTBM_V2_CTB_SW_SQ_CTRL_P2_SQ_CTRL23_Pos 10UL +#define CTBM_V2_CTB_SW_SQ_CTRL_P2_SQ_CTRL23_Msk 0x400UL +#define CTBM_V2_CTB_SW_SQ_CTRL_P3_SQ_CTRL23_Pos 11UL +#define CTBM_V2_CTB_SW_SQ_CTRL_P3_SQ_CTRL23_Msk 0x800UL +/* CTBM.CTB_SW_STATUS */ +#define CTBM_V2_CTB_SW_STATUS_OA0O_D51_STAT_Pos 28UL +#define CTBM_V2_CTB_SW_STATUS_OA0O_D51_STAT_Msk 0x10000000UL +#define CTBM_V2_CTB_SW_STATUS_OA1O_D52_STAT_Pos 29UL +#define CTBM_V2_CTB_SW_STATUS_OA1O_D52_STAT_Msk 0x20000000UL +#define CTBM_V2_CTB_SW_STATUS_OA1O_D62_STAT_Pos 30UL +#define CTBM_V2_CTB_SW_STATUS_OA1O_D62_STAT_Msk 0x40000000UL +#define CTBM_V2_CTB_SW_STATUS_CTD_COS_STAT_Pos 31UL +#define CTBM_V2_CTB_SW_STATUS_CTD_COS_STAT_Msk 0x80000000UL + + +#endif /* _CYIP_CTBM_V2_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse_data_psoc6_04.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse_data_psoc6_04.h new file mode 100644 index 00000000000..9e2a5d929a6 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_efuse_data_psoc6_04.h @@ -0,0 +1,250 @@ +/***************************************************************************//** +* \file cyip_efuse_data_psoc6_04.h +* +* \brief +* EFUSE_DATA IP definitions +* +* \note +* Generator version: 1.5.1.21 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYIP_EFUSE_DATA_PSOC6_04_H_ +#define _CYIP_EFUSE_DATA_PSOC6_04_H_ + +#include "cyip_headers.h" + +/** + * \brief Access restrictions for DEAD life cycle stage (DEAD_ACCESS_RESTRICT0) + */ +typedef struct { + uint8_t CM0_DISABLE; + uint8_t CM4_DISABLE; + uint8_t SYS_DISABLE; + uint8_t SYS_AP_MPU_ENABLE; + uint8_t SFLASH_ALLOWED[2]; + uint8_t MMIO_ALLOWED[2]; +} cy_stc_dead_access_restrict0_t; + +/** + * \brief Access restrictions for DEAD life cycle stage (DEAD_ACCESS_RESTRICT1) + */ +typedef struct { + uint8_t FLASH_ALLOWED[3]; + uint8_t SRAM_ALLOWED[3]; + uint8_t UNUSED; + uint8_t DIRECT_EXECUTE_DISABLE; +} cy_stc_dead_access_restrict1_t; + +/** + * \brief Access restrictions for SECURE life cycle stage (SECURE_ACCESS_RESTRICT0) + */ +typedef struct { + uint8_t CM0_DISABLE; + uint8_t CM4_DISABLE; + uint8_t SYS_DISABLE; + uint8_t SYS_AP_MPU_ENABLE; + uint8_t SFLASH_ALLOWED[2]; + uint8_t MMIO_ALLOWED[2]; +} cy_stc_secure_access_restrict0_t; + +/** + * \brief Access restrictions for SECURE life cycle stage (SECURE_ACCESS_RESTRICT1) + */ +typedef struct { + uint8_t FLASH_ALLOWED[3]; + uint8_t SRAM_ALLOWED[3]; + uint8_t UNUSED; + uint8_t DIRECT_EXECUTE_DISABLE; +} cy_stc_secure_access_restrict1_t; + +/** + * \brief NORMAL, SECURE_WITH_DEBUG, SECURE, and RMA fuse bits (LIFECYCLE_STAGE) + */ +typedef struct { + uint8_t NORMAL; + uint8_t SECURE_WITH_DEBUG; + uint8_t SECURE; + uint8_t RMA; + uint8_t RESERVED[4]; +} cy_stc_lifecycle_stage_t; + +/** + * \brief Cypress asset hash byte 0 (CY_ASSET_HASH0) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash0_t; + +/** + * \brief Cypress asset hash byte 1 (CY_ASSET_HASH1) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash1_t; + +/** + * \brief Cypress asset hash byte 2 (CY_ASSET_HASH2) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash2_t; + +/** + * \brief Cypress asset hash byte 3 (CY_ASSET_HASH3) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash3_t; + +/** + * \brief Cypress asset hash byte 4 (CY_ASSET_HASH4) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash4_t; + +/** + * \brief Cypress asset hash byte 5 (CY_ASSET_HASH5) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash5_t; + +/** + * \brief Cypress asset hash byte 6 (CY_ASSET_HASH6) + */ +typedef struct { + uint8_t CY_ASSET_HASH[8]; +} cy_stc_cy_asset_hash6_t; + +/** + * \brief Cypress asset hash byte 7 (CY_ASSET_HASH7) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash7_t; + +/** + * \brief Cypress asset hash byte 8 (CY_ASSET_HASH8) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash8_t; + +/** + * \brief Cypress asset hash byte 9 (CY_ASSET_HASH9) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash9_t; + +/** + * \brief Cypress asset hash byte 10 (CY_ASSET_HASH10) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash10_t; + +/** + * \brief Cypress asset hash byte 11 (CY_ASSET_HASH11) + */ +typedef struct { + uint8_t CY_ASSET_HASH[8]; +} cy_stc_cy_asset_hash11_t; + +/** + * \brief Cypress asset hash byte 12 (CY_ASSET_HASH12) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash12_t; + +/** + * \brief Cypress asset hash byte 13 (CY_ASSET_HASH13) + */ +typedef struct { + uint8_t CY_ASSET_HASH[8]; +} cy_stc_cy_asset_hash13_t; + +/** + * \brief Cypress asset hash byte 14 (CY_ASSET_HASH14) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash14_t; + +/** + * \brief Cypress asset hash byte 15 (CY_ASSET_HASH15) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash15_t; + +/** + * \brief Number of zeros in Cypress asset hash (CY_ASSET_HASH_ZEROS) + */ +typedef struct { + uint8_t HASH_BYTE[8]; +} cy_stc_cy_asset_hash_zeros_t; + +/** + * \brief Customer data (CUSTOMER_DATA) + */ +typedef struct { + uint8_t CUSTOMER_USE[8]; +} cy_stc_customer_data_t; + + +/** + * \brief eFUSE memory (EFUSE_DATA) + */ +typedef struct { + uint8_t RESERVED[312]; + cy_stc_dead_access_restrict0_t DEAD_ACCESS_RESTRICT0; + cy_stc_dead_access_restrict1_t DEAD_ACCESS_RESTRICT1; + cy_stc_secure_access_restrict0_t SECURE_ACCESS_RESTRICT0; + cy_stc_secure_access_restrict1_t SECURE_ACCESS_RESTRICT1; + cy_stc_lifecycle_stage_t LIFECYCLE_STAGE; + uint8_t RESERVED1[160]; + cy_stc_cy_asset_hash0_t CY_ASSET_HASH0; + cy_stc_cy_asset_hash1_t CY_ASSET_HASH1; + cy_stc_cy_asset_hash2_t CY_ASSET_HASH2; + cy_stc_cy_asset_hash3_t CY_ASSET_HASH3; + cy_stc_cy_asset_hash4_t CY_ASSET_HASH4; + cy_stc_cy_asset_hash5_t CY_ASSET_HASH5; + cy_stc_cy_asset_hash6_t CY_ASSET_HASH6; + cy_stc_cy_asset_hash7_t CY_ASSET_HASH7; + cy_stc_cy_asset_hash8_t CY_ASSET_HASH8; + cy_stc_cy_asset_hash9_t CY_ASSET_HASH9; + cy_stc_cy_asset_hash10_t CY_ASSET_HASH10; + cy_stc_cy_asset_hash11_t CY_ASSET_HASH11; + cy_stc_cy_asset_hash12_t CY_ASSET_HASH12; + cy_stc_cy_asset_hash13_t CY_ASSET_HASH13; + cy_stc_cy_asset_hash14_t CY_ASSET_HASH14; + cy_stc_cy_asset_hash15_t CY_ASSET_HASH15; + cy_stc_cy_asset_hash_zeros_t CY_ASSET_HASH_ZEROS; + cy_stc_customer_data_t CUSTOMER_DATA[47]; +} cy_stc_efuse_data_t; + + +#endif /* _CYIP_EFUSE_DATA_PSOC6_04_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_pass_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_pass_v2.h new file mode 100644 index 00000000000..5d104f621d2 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_pass_v2.h @@ -0,0 +1,342 @@ +/***************************************************************************//** +* \file cyip_pass_v2.h +* +* \brief +* PASS IP definitions +* +* \note +* Generator version: 1.6.0.81 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYIP_PASS_V2_H_ +#define _CYIP_PASS_V2_H_ + +#include "cyip_headers.h" + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_TIMER_V2_SECTION_SIZE 0x00000100UL +#define PASS_LPOSC_V2_SECTION_SIZE 0x00000100UL +#define PASS_FIFO_V2_SECTION_SIZE 0x00000100UL +#define PASS_AREFV2_V2_SECTION_SIZE 0x00000100UL +#define PASS_V2_SECTION_SIZE 0x00010000UL + +/** + * \brief Programmable Analog Subsystem (PASS_TIMER) + */ +typedef struct { + __IOM uint32_t CTRL; /*!< 0x00000000 Timer control register */ + __IOM uint32_t CONFIG; /*!< 0x00000004 Timer configuration register */ + __IOM uint32_t TIMER_PERIOD; /*!< 0x00000008 Timer period register */ + __IM uint32_t RESERVED[61]; +} PASS_TIMER_V2_Type; /*!< Size = 256 (0x100) */ + +/** + * \brief LPOSC configuration (PASS_LPOSC) + */ +typedef struct { + __IOM uint32_t CTRL; /*!< 0x00000000 Low Power Oscillator control */ + __IOM uint32_t CONFIG; /*!< 0x00000004 Low Power Oscillator configuration register */ + __IOM uint32_t ADFT; /*!< 0x00000008 Retention */ + __IM uint32_t RESERVED[61]; +} PASS_LPOSC_V2_Type; /*!< Size = 256 (0x100) */ + +/** + * \brief FIFO configuration (PASS_FIFO) + */ +typedef struct { + __IOM uint32_t CTRL; /*!< 0x00000000 FIFO control register */ + __IOM uint32_t CONFIG; /*!< 0x00000004 FIFO configuration register */ + __IM uint32_t STATUS; /*!< 0x00000008 FIFO status register */ + __IM uint32_t RD_DATA; /*!< 0x0000000C FIFO read data register */ + __IOM uint32_t INTR; /*!< 0x00000010 Interrupt register */ + __IOM uint32_t INTR_SET; /*!< 0x00000014 Interrupt set register */ + __IOM uint32_t INTR_MASK; /*!< 0x00000018 Interrupt mask register */ + __IM uint32_t INTR_MASKED; /*!< 0x0000001C Interrupt masked register */ + __IM uint32_t RESERVED[56]; +} PASS_FIFO_V2_Type; /*!< Size = 256 (0x100) */ + +/** + * \brief AREF configuration (PASS_AREFV2) + */ +typedef struct { + __IOM uint32_t AREF_CTRL; /*!< 0x00000000 global AREF control */ + __IM uint32_t RESERVED[63]; +} PASS_AREFV2_V2_Type; /*!< Size = 256 (0x100) */ + +/** + * \brief PASS top-level MMIO (AREF, LPOSC, FIFO, INTR, Trigger) (PASS) + */ +typedef struct { + __IM uint32_t INTR_CAUSE; /*!< 0x00000000 Interrupt cause register */ + __IM uint32_t RESERVED[3]; + __IOM uint32_t DPSLP_CLOCK_SEL; /*!< 0x00000010 Deepsleep clock select */ + __IOM uint32_t PWR_WAKE_CTRL; /*!< 0x00000014 Deepsleep wakeup control */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t CTBM_CLOCK_SEL; /*!< 0x00000020 Clock select for CTBm */ + __IM uint32_t RESERVED2[3]; + __IOM uint32_t SAR_DPSLP_CTRL[2]; /*!< 0x00000030 Deepsleep control for SARv3 */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t SAR_DPSLP_CONFIG[2]; /*!< 0x00000040 Deepsleep configuration for SARv3 */ + __IM uint32_t RESERVED4[2]; + __IOM uint32_t SAR_HW_TR_SMP_CNT; /*!< 0x00000050 SAR HW trigger sample control */ + __IOM uint32_t SAR_HW_TR_CTRL; /*!< 0x00000054 SAR HW trigger override */ + __IOM uint32_t SAR_SIMULT_HW_TR_CTRL; /*!< 0x00000058 SAR simultaneous trigger control */ + __IOM uint32_t SAR_SIMULT_FW_START_CTRL; /*!< 0x0000005C SAR simultaneous start control */ + __IOM uint32_t SAR_TR_OUT_CTRL; /*!< 0x00000060 SAR trigger out control */ + __IM uint32_t RESERVED5[39]; + PASS_TIMER_V2_Type TIMER; /*!< 0x00000100 Programmable Analog Subsystem */ + PASS_LPOSC_V2_Type LPOSC; /*!< 0x00000200 LPOSC configuration */ + PASS_FIFO_V2_Type FIFO[2]; /*!< 0x00000300 FIFO configuration */ + __IM uint32_t RESERVED6[576]; + PASS_AREFV2_V2_Type AREFV2; /*!< 0x00000E00 AREF configuration */ + __IOM uint32_t VREF_TRIM0; /*!< 0x00000F00 VREF Trim bits */ + __IOM uint32_t VREF_TRIM1; /*!< 0x00000F04 VREF Trim bits */ + __IOM uint32_t VREF_TRIM2; /*!< 0x00000F08 VREF Trim bits */ + __IOM uint32_t VREF_TRIM3; /*!< 0x00000F0C VREF Trim bits */ + __IOM uint32_t IZTAT_TRIM0; /*!< 0x00000F10 VREF Trim bits */ + __IOM uint32_t IZTAT_TRIM1; /*!< 0x00000F14 IZTAT Trim bits */ + __IOM uint32_t IPTAT_TRIM0; /*!< 0x00000F18 IPTAT Trim bits */ + __IOM uint32_t ICTAT_TRIM0; /*!< 0x00000F1C ICTAT Trim bits */ +} PASS_V2_Type; /*!< Size = 3872 (0xF20) */ + + +/* PASS_TIMER.CTRL */ +#define PASS_TIMER_V2_CTRL_ENABLED_Pos 31UL +#define PASS_TIMER_V2_CTRL_ENABLED_Msk 0x80000000UL +/* PASS_TIMER.CONFIG */ +#define PASS_TIMER_V2_CONFIG_CLOCK_SEL_Pos 0UL +#define PASS_TIMER_V2_CONFIG_CLOCK_SEL_Msk 0x3UL +/* PASS_TIMER.TIMER_PERIOD */ +#define PASS_TIMER_V2_TIMER_PERIOD_PER_VAL_Pos 0UL +#define PASS_TIMER_V2_TIMER_PERIOD_PER_VAL_Msk 0xFFFFUL + + +/* PASS_LPOSC.CTRL */ +#define PASS_LPOSC_V2_CTRL_ENABLED_Pos 31UL +#define PASS_LPOSC_V2_CTRL_ENABLED_Msk 0x80000000UL +/* PASS_LPOSC.CONFIG */ +#define PASS_LPOSC_V2_CONFIG_DEEPSLEEP_MODE_Pos 0UL +#define PASS_LPOSC_V2_CONFIG_DEEPSLEEP_MODE_Msk 0x1UL +/* PASS_LPOSC.ADFT */ +#define PASS_LPOSC_V2_ADFT_ADFT_SEL_Pos 0UL +#define PASS_LPOSC_V2_ADFT_ADFT_SEL_Msk 0x3UL + + +/* PASS_FIFO.CTRL */ +#define PASS_FIFO_V2_CTRL_ENABLED_Pos 31UL +#define PASS_FIFO_V2_CTRL_ENABLED_Msk 0x80000000UL +/* PASS_FIFO.CONFIG */ +#define PASS_FIFO_V2_CONFIG_LEVEL_Pos 0UL +#define PASS_FIFO_V2_CONFIG_LEVEL_Msk 0xFFUL +#define PASS_FIFO_V2_CONFIG_CHAN_ID_EN_Pos 8UL +#define PASS_FIFO_V2_CONFIG_CHAN_ID_EN_Msk 0x100UL +#define PASS_FIFO_V2_CONFIG_CHAIN_EN_Pos 9UL +#define PASS_FIFO_V2_CONFIG_CHAIN_EN_Msk 0x200UL +/* PASS_FIFO.STATUS */ +#define PASS_FIFO_V2_STATUS_USED_Pos 0UL +#define PASS_FIFO_V2_STATUS_USED_Msk 0xFFUL +#define PASS_FIFO_V2_STATUS_RD_PTR_Pos 16UL +#define PASS_FIFO_V2_STATUS_RD_PTR_Msk 0xFF0000UL +#define PASS_FIFO_V2_STATUS_WR_PTR_Pos 24UL +#define PASS_FIFO_V2_STATUS_WR_PTR_Msk 0xFF000000UL +/* PASS_FIFO.RD_DATA */ +#define PASS_FIFO_V2_RD_DATA_RESULT_Pos 0UL +#define PASS_FIFO_V2_RD_DATA_RESULT_Msk 0xFFFFUL +#define PASS_FIFO_V2_RD_DATA_CHAN_ID_Pos 16UL +#define PASS_FIFO_V2_RD_DATA_CHAN_ID_Msk 0xF0000UL +/* PASS_FIFO.INTR */ +#define PASS_FIFO_V2_INTR_FIFO_LEVEL_Pos 0UL +#define PASS_FIFO_V2_INTR_FIFO_LEVEL_Msk 0x1UL +#define PASS_FIFO_V2_INTR_FIFO_OVERFLOW_Pos 1UL +#define PASS_FIFO_V2_INTR_FIFO_OVERFLOW_Msk 0x2UL +#define PASS_FIFO_V2_INTR_FIFO_UNDERFLOW_Pos 2UL +#define PASS_FIFO_V2_INTR_FIFO_UNDERFLOW_Msk 0x4UL +/* PASS_FIFO.INTR_SET */ +#define PASS_FIFO_V2_INTR_SET_FIFO_LEVEL_Pos 0UL +#define PASS_FIFO_V2_INTR_SET_FIFO_LEVEL_Msk 0x1UL +#define PASS_FIFO_V2_INTR_SET_FIFO_OVERFLOW_Pos 1UL +#define PASS_FIFO_V2_INTR_SET_FIFO_OVERFLOW_Msk 0x2UL +#define PASS_FIFO_V2_INTR_SET_FIFO_UNDERFLOW_Pos 2UL +#define PASS_FIFO_V2_INTR_SET_FIFO_UNDERFLOW_Msk 0x4UL +/* PASS_FIFO.INTR_MASK */ +#define PASS_FIFO_V2_INTR_MASK_FIFO_LEVEL_Pos 0UL +#define PASS_FIFO_V2_INTR_MASK_FIFO_LEVEL_Msk 0x1UL +#define PASS_FIFO_V2_INTR_MASK_FIFO_OVERFLOW_Pos 1UL +#define PASS_FIFO_V2_INTR_MASK_FIFO_OVERFLOW_Msk 0x2UL +#define PASS_FIFO_V2_INTR_MASK_FIFO_UNDERFLOW_Pos 2UL +#define PASS_FIFO_V2_INTR_MASK_FIFO_UNDERFLOW_Msk 0x4UL +/* PASS_FIFO.INTR_MASKED */ +#define PASS_FIFO_V2_INTR_MASKED_FIFO_LEVEL_Pos 0UL +#define PASS_FIFO_V2_INTR_MASKED_FIFO_LEVEL_Msk 0x1UL +#define PASS_FIFO_V2_INTR_MASKED_FIFO_OVERFLOW_Pos 1UL +#define PASS_FIFO_V2_INTR_MASKED_FIFO_OVERFLOW_Msk 0x2UL +#define PASS_FIFO_V2_INTR_MASKED_FIFO_UNDERFLOW_Pos 2UL +#define PASS_FIFO_V2_INTR_MASKED_FIFO_UNDERFLOW_Msk 0x4UL + + +/* PASS_AREFV2.AREF_CTRL */ +#define PASS_AREFV2_V2_AREF_CTRL_AREF_MODE_Pos 0UL +#define PASS_AREFV2_V2_AREF_CTRL_AREF_MODE_Msk 0x1UL +#define PASS_AREFV2_V2_AREF_CTRL_AREF_BIAS_SCALE_Pos 2UL +#define PASS_AREFV2_V2_AREF_CTRL_AREF_BIAS_SCALE_Msk 0xCUL +#define PASS_AREFV2_V2_AREF_CTRL_AREF_RMB_Pos 4UL +#define PASS_AREFV2_V2_AREF_CTRL_AREF_RMB_Msk 0x70UL +#define PASS_AREFV2_V2_AREF_CTRL_CTB_IPTAT_SCALE_Pos 7UL +#define PASS_AREFV2_V2_AREF_CTRL_CTB_IPTAT_SCALE_Msk 0x80UL +#define PASS_AREFV2_V2_AREF_CTRL_CTB_IPTAT_REDIRECT_Pos 8UL +#define PASS_AREFV2_V2_AREF_CTRL_CTB_IPTAT_REDIRECT_Msk 0xFF00UL +#define PASS_AREFV2_V2_AREF_CTRL_IZTAT_SEL_Pos 16UL +#define PASS_AREFV2_V2_AREF_CTRL_IZTAT_SEL_Msk 0x10000UL +#define PASS_AREFV2_V2_AREF_CTRL_CLOCK_PUMP_PERI_SEL_Pos 19UL +#define PASS_AREFV2_V2_AREF_CTRL_CLOCK_PUMP_PERI_SEL_Msk 0x80000UL +#define PASS_AREFV2_V2_AREF_CTRL_VREF_SEL_Pos 20UL +#define PASS_AREFV2_V2_AREF_CTRL_VREF_SEL_Msk 0x300000UL +#define PASS_AREFV2_V2_AREF_CTRL_LP_VREF_EN_Pos 22UL +#define PASS_AREFV2_V2_AREF_CTRL_LP_VREF_EN_Msk 0x400000UL +#define PASS_AREFV2_V2_AREF_CTRL_IZTAT_SCALE_Pos 23UL +#define PASS_AREFV2_V2_AREF_CTRL_IZTAT_SCALE_Msk 0x800000UL +#define PASS_AREFV2_V2_AREF_CTRL_DEEPSLEEP_MODE_Pos 28UL +#define PASS_AREFV2_V2_AREF_CTRL_DEEPSLEEP_MODE_Msk 0x30000000UL +#define PASS_AREFV2_V2_AREF_CTRL_DEEPSLEEP_ON_Pos 30UL +#define PASS_AREFV2_V2_AREF_CTRL_DEEPSLEEP_ON_Msk 0x40000000UL +#define PASS_AREFV2_V2_AREF_CTRL_ENABLED_Pos 31UL +#define PASS_AREFV2_V2_AREF_CTRL_ENABLED_Msk 0x80000000UL + + +/* PASS.INTR_CAUSE */ +#define PASS_V2_INTR_CAUSE_CTB0_INT_Pos 0UL +#define PASS_V2_INTR_CAUSE_CTB0_INT_Msk 0x1UL +#define PASS_V2_INTR_CAUSE_CTB1_INT_Pos 1UL +#define PASS_V2_INTR_CAUSE_CTB1_INT_Msk 0x2UL +#define PASS_V2_INTR_CAUSE_CTB2_INT_Pos 2UL +#define PASS_V2_INTR_CAUSE_CTB2_INT_Msk 0x4UL +#define PASS_V2_INTR_CAUSE_CTB3_INT_Pos 3UL +#define PASS_V2_INTR_CAUSE_CTB3_INT_Msk 0x8UL +#define PASS_V2_INTR_CAUSE_CTDAC0_INT_Pos 4UL +#define PASS_V2_INTR_CAUSE_CTDAC0_INT_Msk 0x10UL +#define PASS_V2_INTR_CAUSE_CTDAC1_INT_Pos 5UL +#define PASS_V2_INTR_CAUSE_CTDAC1_INT_Msk 0x20UL +#define PASS_V2_INTR_CAUSE_CTDAC2_INT_Pos 6UL +#define PASS_V2_INTR_CAUSE_CTDAC2_INT_Msk 0x40UL +#define PASS_V2_INTR_CAUSE_CTDAC3_INT_Pos 7UL +#define PASS_V2_INTR_CAUSE_CTDAC3_INT_Msk 0x80UL +#define PASS_V2_INTR_CAUSE_SAR0_INT_Pos 8UL +#define PASS_V2_INTR_CAUSE_SAR0_INT_Msk 0x100UL +#define PASS_V2_INTR_CAUSE_SAR1_INT_Pos 9UL +#define PASS_V2_INTR_CAUSE_SAR1_INT_Msk 0x200UL +#define PASS_V2_INTR_CAUSE_SAR2_INT_Pos 10UL +#define PASS_V2_INTR_CAUSE_SAR2_INT_Msk 0x400UL +#define PASS_V2_INTR_CAUSE_SAR3_INT_Pos 11UL +#define PASS_V2_INTR_CAUSE_SAR3_INT_Msk 0x800UL +#define PASS_V2_INTR_CAUSE_FIFO0_INT_Pos 12UL +#define PASS_V2_INTR_CAUSE_FIFO0_INT_Msk 0x1000UL +#define PASS_V2_INTR_CAUSE_FIFO1_INT_Pos 13UL +#define PASS_V2_INTR_CAUSE_FIFO1_INT_Msk 0x2000UL +#define PASS_V2_INTR_CAUSE_FIFO2_INT_Pos 14UL +#define PASS_V2_INTR_CAUSE_FIFO2_INT_Msk 0x4000UL +#define PASS_V2_INTR_CAUSE_FIFO3_INT_Pos 15UL +#define PASS_V2_INTR_CAUSE_FIFO3_INT_Msk 0x8000UL +/* PASS.DPSLP_CLOCK_SEL */ +#define PASS_V2_DPSLP_CLOCK_SEL_DPSLP_CLOCK_SEL_Pos 0UL +#define PASS_V2_DPSLP_CLOCK_SEL_DPSLP_CLOCK_SEL_Msk 0x1UL +#define PASS_V2_DPSLP_CLOCK_SEL_DPSLP_CLOCK_DIV_Pos 4UL +#define PASS_V2_DPSLP_CLOCK_SEL_DPSLP_CLOCK_DIV_Msk 0x70UL +/* PASS.PWR_WAKE_CTRL */ +#define PASS_V2_PWR_WAKE_CTRL_WAKE_DELAY_Pos 0UL +#define PASS_V2_PWR_WAKE_CTRL_WAKE_DELAY_Msk 0x3FUL +/* PASS.CTBM_CLOCK_SEL */ +#define PASS_V2_CTBM_CLOCK_SEL_PUMP_CLOCK_SEL_Pos 0UL +#define PASS_V2_CTBM_CLOCK_SEL_PUMP_CLOCK_SEL_Msk 0x1UL +/* PASS.SAR_DPSLP_CTRL */ +#define PASS_V2_SAR_DPSLP_CTRL_ENABLED_Pos 31UL +#define PASS_V2_SAR_DPSLP_CTRL_ENABLED_Msk 0x80000000UL +/* PASS.SAR_DPSLP_CONFIG */ +#define PASS_V2_SAR_DPSLP_CONFIG_DEEPSLEEP_ON_Pos 30UL +#define PASS_V2_SAR_DPSLP_CONFIG_DEEPSLEEP_ON_Msk 0x40000000UL +/* PASS.SAR_HW_TR_SMP_CNT */ +#define PASS_V2_SAR_HW_TR_SMP_CNT_SMP_CNT_Pos 0UL +#define PASS_V2_SAR_HW_TR_SMP_CNT_SMP_CNT_Msk 0x3FUL +/* PASS.SAR_HW_TR_CTRL */ +#define PASS_V2_SAR_HW_TR_CTRL_HW_TR_TIMER_SEL_Pos 0UL +#define PASS_V2_SAR_HW_TR_CTRL_HW_TR_TIMER_SEL_Msk 0xFUL +#define PASS_V2_SAR_HW_TR_CTRL_HW_TR_SMP_CNT_SEL_Pos 4UL +#define PASS_V2_SAR_HW_TR_CTRL_HW_TR_SMP_CNT_SEL_Msk 0xF0UL +/* PASS.SAR_SIMULT_HW_TR_CTRL */ +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_TR_EN_Pos 0UL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_TR_EN_Msk 0xFUL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_TR_SRC_Pos 4UL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_TR_SRC_Msk 0x30UL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_TR_TIMER_SEL_Pos 8UL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_TR_TIMER_SEL_Msk 0x100UL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_TR_LEVEL_Pos 18UL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_TR_LEVEL_Msk 0x40000UL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_SYNC_TR_Pos 19UL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_SYNC_TR_Msk 0x80000UL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_TR_SMP_CNT_SEL_Pos 20UL +#define PASS_V2_SAR_SIMULT_HW_TR_CTRL_SIMULT_HW_TR_SMP_CNT_SEL_Msk 0x100000UL +/* PASS.SAR_SIMULT_FW_START_CTRL */ +#define PASS_V2_SAR_SIMULT_FW_START_CTRL_FW_TRIGGER_Pos 0UL +#define PASS_V2_SAR_SIMULT_FW_START_CTRL_FW_TRIGGER_Msk 0xFUL +#define PASS_V2_SAR_SIMULT_FW_START_CTRL_CONTINUOUS_Pos 16UL +#define PASS_V2_SAR_SIMULT_FW_START_CTRL_CONTINUOUS_Msk 0xF0000UL +/* PASS.SAR_TR_OUT_CTRL */ +#define PASS_V2_SAR_TR_OUT_CTRL_SAR0_TR_OUT_SEL_Pos 0UL +#define PASS_V2_SAR_TR_OUT_CTRL_SAR0_TR_OUT_SEL_Msk 0x1UL +#define PASS_V2_SAR_TR_OUT_CTRL_SAR1_TR_OUT_SEL_Pos 1UL +#define PASS_V2_SAR_TR_OUT_CTRL_SAR1_TR_OUT_SEL_Msk 0x2UL +#define PASS_V2_SAR_TR_OUT_CTRL_SAR2_TR_OUT_SEL_Pos 2UL +#define PASS_V2_SAR_TR_OUT_CTRL_SAR2_TR_OUT_SEL_Msk 0x4UL +#define PASS_V2_SAR_TR_OUT_CTRL_SAR3_TR_OUT_SEL_Pos 3UL +#define PASS_V2_SAR_TR_OUT_CTRL_SAR3_TR_OUT_SEL_Msk 0x8UL +/* PASS.VREF_TRIM0 */ +#define PASS_V2_VREF_TRIM0_VREF_ABS_TRIM_Pos 0UL +#define PASS_V2_VREF_TRIM0_VREF_ABS_TRIM_Msk 0xFFUL +/* PASS.VREF_TRIM1 */ +#define PASS_V2_VREF_TRIM1_VREF_TEMPCO_TRIM_Pos 0UL +#define PASS_V2_VREF_TRIM1_VREF_TEMPCO_TRIM_Msk 0xFFUL +/* PASS.VREF_TRIM2 */ +#define PASS_V2_VREF_TRIM2_VREF_CURV_TRIM_Pos 0UL +#define PASS_V2_VREF_TRIM2_VREF_CURV_TRIM_Msk 0xFFUL +/* PASS.VREF_TRIM3 */ +#define PASS_V2_VREF_TRIM3_VREF_ATTEN_TRIM_Pos 0UL +#define PASS_V2_VREF_TRIM3_VREF_ATTEN_TRIM_Msk 0xFUL +/* PASS.IZTAT_TRIM0 */ +#define PASS_V2_IZTAT_TRIM0_IZTAT_ABS_TRIM_Pos 0UL +#define PASS_V2_IZTAT_TRIM0_IZTAT_ABS_TRIM_Msk 0xFFUL +/* PASS.IZTAT_TRIM1 */ +#define PASS_V2_IZTAT_TRIM1_IZTAT_TC_TRIM_Pos 0UL +#define PASS_V2_IZTAT_TRIM1_IZTAT_TC_TRIM_Msk 0xFFUL +/* PASS.IPTAT_TRIM0 */ +#define PASS_V2_IPTAT_TRIM0_IPTAT_CORE_TRIM_Pos 0UL +#define PASS_V2_IPTAT_TRIM0_IPTAT_CORE_TRIM_Msk 0xFUL +#define PASS_V2_IPTAT_TRIM0_IPTAT_CTBM_TRIM_Pos 4UL +#define PASS_V2_IPTAT_TRIM0_IPTAT_CTBM_TRIM_Msk 0xF0UL +/* PASS.ICTAT_TRIM0 */ +#define PASS_V2_ICTAT_TRIM0_ICTAT_TRIM_Pos 0UL +#define PASS_V2_ICTAT_TRIM0_ICTAT_TRIM_Msk 0xFUL + + +#endif /* _CYIP_PASS_V2_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sar_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sar_v2.h new file mode 100644 index 00000000000..40d096bbebf --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sar_v2.h @@ -0,0 +1,563 @@ +/***************************************************************************//** +* \file cyip_sar_v2.h +* +* \brief +* SAR IP definitions +* +* \note +* Generator version: 1.5.1.36 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYIP_SAR_V2_H_ +#define _CYIP_SAR_V2_H_ + +#include "cyip_headers.h" + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR_V2_SECTION_SIZE 0x00010000UL + +/** + * \brief SAR ADC with Sequencer (SAR) + */ +typedef struct { + __IOM uint32_t CTRL; /*!< 0x00000000 Analog control register. */ + __IOM uint32_t SAMPLE_CTRL; /*!< 0x00000004 Sample control register. */ + __IM uint32_t RESERVED[2]; + __IOM uint32_t SAMPLE_TIME01; /*!< 0x00000010 Sample time specification ST0 and ST1 */ + __IOM uint32_t SAMPLE_TIME23; /*!< 0x00000014 Sample time specification ST2 and ST3 */ + __IOM uint32_t RANGE_THRES; /*!< 0x00000018 Global range detect threshold register. */ + __IOM uint32_t RANGE_COND; /*!< 0x0000001C Global range detect mode register. */ + __IOM uint32_t CHAN_EN; /*!< 0x00000020 Enable bits for the channels */ + __IOM uint32_t START_CTRL; /*!< 0x00000024 Start control register (firmware trigger). */ + __IM uint32_t RESERVED1[22]; + __IOM uint32_t CHAN_CONFIG[16]; /*!< 0x00000080 Channel configuration register. */ + __IM uint32_t RESERVED2[16]; + __IM uint32_t CHAN_WORK[16]; /*!< 0x00000100 Channel working data register */ + __IM uint32_t RESERVED3[16]; + __IM uint32_t CHAN_RESULT[16]; /*!< 0x00000180 Channel result data register */ + __IM uint32_t RESERVED4[16]; + __IM uint32_t CHAN_WORK_UPDATED; /*!< 0x00000200 Channel working data register 'updated' bits */ + __IM uint32_t CHAN_RESULT_UPDATED; /*!< 0x00000204 Channel result data register 'updated' bits */ + __IM uint32_t CHAN_WORK_NEWVALUE; /*!< 0x00000208 Channel working data register 'new value' bits */ + __IM uint32_t CHAN_RESULT_NEWVALUE; /*!< 0x0000020C Channel result data register 'new value' bits */ + __IOM uint32_t INTR; /*!< 0x00000210 Interrupt request register. */ + __IOM uint32_t INTR_SET; /*!< 0x00000214 Interrupt set request register */ + __IOM uint32_t INTR_MASK; /*!< 0x00000218 Interrupt mask register. */ + __IM uint32_t INTR_MASKED; /*!< 0x0000021C Interrupt masked request register */ + __IOM uint32_t SATURATE_INTR; /*!< 0x00000220 Saturate interrupt request register. */ + __IOM uint32_t SATURATE_INTR_SET; /*!< 0x00000224 Saturate interrupt set request register */ + __IOM uint32_t SATURATE_INTR_MASK; /*!< 0x00000228 Saturate interrupt mask register. */ + __IM uint32_t SATURATE_INTR_MASKED; /*!< 0x0000022C Saturate interrupt masked request register */ + __IOM uint32_t RANGE_INTR; /*!< 0x00000230 Range detect interrupt request register. */ + __IOM uint32_t RANGE_INTR_SET; /*!< 0x00000234 Range detect interrupt set request register */ + __IOM uint32_t RANGE_INTR_MASK; /*!< 0x00000238 Range detect interrupt mask register. */ + __IM uint32_t RANGE_INTR_MASKED; /*!< 0x0000023C Range interrupt masked request register */ + __IM uint32_t INTR_CAUSE; /*!< 0x00000240 Interrupt cause register */ + __IM uint32_t RESERVED5[23]; + __IM uint32_t STATUS; /*!< 0x000002A0 Current status of internal SAR registers (mostly for debug) */ + __IM uint32_t AVG_STAT; /*!< 0x000002A4 Current averaging status (for debug) */ + __IM uint32_t RESERVED6[22]; + __IOM uint32_t MUX_SWITCH0; /*!< 0x00000300 SARMUX Firmware switch controls */ + __IOM uint32_t MUX_SWITCH_CLEAR0; /*!< 0x00000304 SARMUX Firmware switch control clear */ + __IM uint32_t RESERVED7[15]; + __IOM uint32_t MUX_SWITCH_SQ_CTRL; /*!< 0x00000344 SARMUX switch Sar Sequencer control */ + __IM uint32_t MUX_SWITCH_STATUS; /*!< 0x00000348 SARMUX switch status */ +} SAR_V2_Type; /*!< Size = 844 (0x34C) */ + + +/* SAR.CTRL */ +#define SAR_V2_CTRL_PWR_CTRL_VREF_Pos 0UL +#define SAR_V2_CTRL_PWR_CTRL_VREF_Msk 0x7UL +#define SAR_V2_CTRL_VREF_SEL_Pos 4UL +#define SAR_V2_CTRL_VREF_SEL_Msk 0x70UL +#define SAR_V2_CTRL_VREF_BYP_CAP_EN_Pos 7UL +#define SAR_V2_CTRL_VREF_BYP_CAP_EN_Msk 0x80UL +#define SAR_V2_CTRL_NEG_SEL_Pos 9UL +#define SAR_V2_CTRL_NEG_SEL_Msk 0xE00UL +#define SAR_V2_CTRL_SAR_HW_CTRL_NEGVREF_Pos 13UL +#define SAR_V2_CTRL_SAR_HW_CTRL_NEGVREF_Msk 0x2000UL +#define SAR_V2_CTRL_COMP_DLY_Pos 14UL +#define SAR_V2_CTRL_COMP_DLY_Msk 0xC000UL +#define SAR_V2_CTRL_SPARE_Pos 16UL +#define SAR_V2_CTRL_SPARE_Msk 0xF0000UL +#define SAR_V2_CTRL_BOOSTPUMP_EN_Pos 20UL +#define SAR_V2_CTRL_BOOSTPUMP_EN_Msk 0x100000UL +#define SAR_V2_CTRL_REFBUF_EN_Pos 21UL +#define SAR_V2_CTRL_REFBUF_EN_Msk 0x200000UL +#define SAR_V2_CTRL_COMP_PWR_Pos 24UL +#define SAR_V2_CTRL_COMP_PWR_Msk 0x7000000UL +#define SAR_V2_CTRL_DEEPSLEEP_ON_Pos 27UL +#define SAR_V2_CTRL_DEEPSLEEP_ON_Msk 0x8000000UL +#define SAR_V2_CTRL_DSI_SYNC_CONFIG_Pos 28UL +#define SAR_V2_CTRL_DSI_SYNC_CONFIG_Msk 0x10000000UL +#define SAR_V2_CTRL_DSI_MODE_Pos 29UL +#define SAR_V2_CTRL_DSI_MODE_Msk 0x20000000UL +#define SAR_V2_CTRL_SWITCH_DISABLE_Pos 30UL +#define SAR_V2_CTRL_SWITCH_DISABLE_Msk 0x40000000UL +#define SAR_V2_CTRL_ENABLED_Pos 31UL +#define SAR_V2_CTRL_ENABLED_Msk 0x80000000UL +/* SAR.SAMPLE_CTRL */ +#define SAR_V2_SAMPLE_CTRL_LEFT_ALIGN_Pos 1UL +#define SAR_V2_SAMPLE_CTRL_LEFT_ALIGN_Msk 0x2UL +#define SAR_V2_SAMPLE_CTRL_SINGLE_ENDED_SIGNED_Pos 2UL +#define SAR_V2_SAMPLE_CTRL_SINGLE_ENDED_SIGNED_Msk 0x4UL +#define SAR_V2_SAMPLE_CTRL_DIFFERENTIAL_SIGNED_Pos 3UL +#define SAR_V2_SAMPLE_CTRL_DIFFERENTIAL_SIGNED_Msk 0x8UL +#define SAR_V2_SAMPLE_CTRL_AVG_CNT_Pos 4UL +#define SAR_V2_SAMPLE_CTRL_AVG_CNT_Msk 0x70UL +#define SAR_V2_SAMPLE_CTRL_AVG_SHIFT_Pos 7UL +#define SAR_V2_SAMPLE_CTRL_AVG_SHIFT_Msk 0x80UL +#define SAR_V2_SAMPLE_CTRL_AVG_MODE_Pos 8UL +#define SAR_V2_SAMPLE_CTRL_AVG_MODE_Msk 0x100UL +#define SAR_V2_SAMPLE_CTRL_CONTINUOUS_Pos 16UL +#define SAR_V2_SAMPLE_CTRL_CONTINUOUS_Msk 0x10000UL +#define SAR_V2_SAMPLE_CTRL_DSI_TRIGGER_EN_Pos 17UL +#define SAR_V2_SAMPLE_CTRL_DSI_TRIGGER_EN_Msk 0x20000UL +#define SAR_V2_SAMPLE_CTRL_DSI_TRIGGER_LEVEL_Pos 18UL +#define SAR_V2_SAMPLE_CTRL_DSI_TRIGGER_LEVEL_Msk 0x40000UL +#define SAR_V2_SAMPLE_CTRL_DSI_SYNC_TRIGGER_Pos 19UL +#define SAR_V2_SAMPLE_CTRL_DSI_SYNC_TRIGGER_Msk 0x80000UL +#define SAR_V2_SAMPLE_CTRL_UAB_SCAN_MODE_Pos 22UL +#define SAR_V2_SAMPLE_CTRL_UAB_SCAN_MODE_Msk 0x400000UL +#define SAR_V2_SAMPLE_CTRL_REPEAT_INVALID_Pos 23UL +#define SAR_V2_SAMPLE_CTRL_REPEAT_INVALID_Msk 0x800000UL +#define SAR_V2_SAMPLE_CTRL_VALID_SEL_Pos 24UL +#define SAR_V2_SAMPLE_CTRL_VALID_SEL_Msk 0x7000000UL +#define SAR_V2_SAMPLE_CTRL_VALID_SEL_EN_Pos 27UL +#define SAR_V2_SAMPLE_CTRL_VALID_SEL_EN_Msk 0x8000000UL +#define SAR_V2_SAMPLE_CTRL_VALID_IGNORE_Pos 28UL +#define SAR_V2_SAMPLE_CTRL_VALID_IGNORE_Msk 0x10000000UL +#define SAR_V2_SAMPLE_CTRL_TRIGGER_OUT_EN_Pos 30UL +#define SAR_V2_SAMPLE_CTRL_TRIGGER_OUT_EN_Msk 0x40000000UL +#define SAR_V2_SAMPLE_CTRL_EOS_DSI_OUT_EN_Pos 31UL +#define SAR_V2_SAMPLE_CTRL_EOS_DSI_OUT_EN_Msk 0x80000000UL +/* SAR.SAMPLE_TIME01 */ +#define SAR_V2_SAMPLE_TIME01_SAMPLE_TIME0_Pos 0UL +#define SAR_V2_SAMPLE_TIME01_SAMPLE_TIME0_Msk 0x3FFUL +#define SAR_V2_SAMPLE_TIME01_SAMPLE_TIME1_Pos 16UL +#define SAR_V2_SAMPLE_TIME01_SAMPLE_TIME1_Msk 0x3FF0000UL +/* SAR.SAMPLE_TIME23 */ +#define SAR_V2_SAMPLE_TIME23_SAMPLE_TIME2_Pos 0UL +#define SAR_V2_SAMPLE_TIME23_SAMPLE_TIME2_Msk 0x3FFUL +#define SAR_V2_SAMPLE_TIME23_SAMPLE_TIME3_Pos 16UL +#define SAR_V2_SAMPLE_TIME23_SAMPLE_TIME3_Msk 0x3FF0000UL +/* SAR.RANGE_THRES */ +#define SAR_V2_RANGE_THRES_RANGE_LOW_Pos 0UL +#define SAR_V2_RANGE_THRES_RANGE_LOW_Msk 0xFFFFUL +#define SAR_V2_RANGE_THRES_RANGE_HIGH_Pos 16UL +#define SAR_V2_RANGE_THRES_RANGE_HIGH_Msk 0xFFFF0000UL +/* SAR.RANGE_COND */ +#define SAR_V2_RANGE_COND_RANGE_COND_Pos 30UL +#define SAR_V2_RANGE_COND_RANGE_COND_Msk 0xC0000000UL +/* SAR.CHAN_EN */ +#define SAR_V2_CHAN_EN_CHAN_EN_Pos 0UL +#define SAR_V2_CHAN_EN_CHAN_EN_Msk 0xFFFFUL +/* SAR.START_CTRL */ +#define SAR_V2_START_CTRL_FW_TRIGGER_Pos 0UL +#define SAR_V2_START_CTRL_FW_TRIGGER_Msk 0x1UL +/* SAR.CHAN_CONFIG */ +#define SAR_V2_CHAN_CONFIG_POS_PIN_ADDR_Pos 0UL +#define SAR_V2_CHAN_CONFIG_POS_PIN_ADDR_Msk 0x7UL +#define SAR_V2_CHAN_CONFIG_POS_PORT_ADDR_Pos 4UL +#define SAR_V2_CHAN_CONFIG_POS_PORT_ADDR_Msk 0x70UL +#define SAR_V2_CHAN_CONFIG_DIFFERENTIAL_EN_Pos 8UL +#define SAR_V2_CHAN_CONFIG_DIFFERENTIAL_EN_Msk 0x100UL +#define SAR_V2_CHAN_CONFIG_AVG_EN_Pos 10UL +#define SAR_V2_CHAN_CONFIG_AVG_EN_Msk 0x400UL +#define SAR_V2_CHAN_CONFIG_SAMPLE_TIME_SEL_Pos 12UL +#define SAR_V2_CHAN_CONFIG_SAMPLE_TIME_SEL_Msk 0x3000UL +#define SAR_V2_CHAN_CONFIG_NEG_PIN_ADDR_Pos 16UL +#define SAR_V2_CHAN_CONFIG_NEG_PIN_ADDR_Msk 0x70000UL +#define SAR_V2_CHAN_CONFIG_NEG_PORT_ADDR_Pos 20UL +#define SAR_V2_CHAN_CONFIG_NEG_PORT_ADDR_Msk 0x700000UL +#define SAR_V2_CHAN_CONFIG_NEG_ADDR_EN_Pos 24UL +#define SAR_V2_CHAN_CONFIG_NEG_ADDR_EN_Msk 0x1000000UL +#define SAR_V2_CHAN_CONFIG_DSI_OUT_EN_Pos 31UL +#define SAR_V2_CHAN_CONFIG_DSI_OUT_EN_Msk 0x80000000UL +/* SAR.CHAN_WORK */ +#define SAR_V2_CHAN_WORK_WORK_Pos 0UL +#define SAR_V2_CHAN_WORK_WORK_Msk 0xFFFFUL +#define SAR_V2_CHAN_WORK_CHAN_WORK_NEWVALUE_MIR_Pos 27UL +#define SAR_V2_CHAN_WORK_CHAN_WORK_NEWVALUE_MIR_Msk 0x8000000UL +#define SAR_V2_CHAN_WORK_CHAN_WORK_UPDATED_MIR_Pos 31UL +#define SAR_V2_CHAN_WORK_CHAN_WORK_UPDATED_MIR_Msk 0x80000000UL +/* SAR.CHAN_RESULT */ +#define SAR_V2_CHAN_RESULT_RESULT_Pos 0UL +#define SAR_V2_CHAN_RESULT_RESULT_Msk 0xFFFFUL +#define SAR_V2_CHAN_RESULT_CHAN_RESULT_NEWVALUE_MIR_Pos 27UL +#define SAR_V2_CHAN_RESULT_CHAN_RESULT_NEWVALUE_MIR_Msk 0x8000000UL +#define SAR_V2_CHAN_RESULT_SATURATE_INTR_MIR_Pos 29UL +#define SAR_V2_CHAN_RESULT_SATURATE_INTR_MIR_Msk 0x20000000UL +#define SAR_V2_CHAN_RESULT_RANGE_INTR_MIR_Pos 30UL +#define SAR_V2_CHAN_RESULT_RANGE_INTR_MIR_Msk 0x40000000UL +#define SAR_V2_CHAN_RESULT_CHAN_RESULT_UPDATED_MIR_Pos 31UL +#define SAR_V2_CHAN_RESULT_CHAN_RESULT_UPDATED_MIR_Msk 0x80000000UL +/* SAR.CHAN_WORK_UPDATED */ +#define SAR_V2_CHAN_WORK_UPDATED_CHAN_WORK_UPDATED_Pos 0UL +#define SAR_V2_CHAN_WORK_UPDATED_CHAN_WORK_UPDATED_Msk 0xFFFFUL +/* SAR.CHAN_RESULT_UPDATED */ +#define SAR_V2_CHAN_RESULT_UPDATED_CHAN_RESULT_UPDATED_Pos 0UL +#define SAR_V2_CHAN_RESULT_UPDATED_CHAN_RESULT_UPDATED_Msk 0xFFFFUL +/* SAR.CHAN_WORK_NEWVALUE */ +#define SAR_V2_CHAN_WORK_NEWVALUE_CHAN_WORK_NEWVALUE_Pos 0UL +#define SAR_V2_CHAN_WORK_NEWVALUE_CHAN_WORK_NEWVALUE_Msk 0xFFFFUL +/* SAR.CHAN_RESULT_NEWVALUE */ +#define SAR_V2_CHAN_RESULT_NEWVALUE_CHAN_RESULT_NEWVALUE_Pos 0UL +#define SAR_V2_CHAN_RESULT_NEWVALUE_CHAN_RESULT_NEWVALUE_Msk 0xFFFFUL +/* SAR.INTR */ +#define SAR_V2_INTR_EOS_INTR_Pos 0UL +#define SAR_V2_INTR_EOS_INTR_Msk 0x1UL +#define SAR_V2_INTR_OVERFLOW_INTR_Pos 1UL +#define SAR_V2_INTR_OVERFLOW_INTR_Msk 0x2UL +#define SAR_V2_INTR_FW_COLLISION_INTR_Pos 2UL +#define SAR_V2_INTR_FW_COLLISION_INTR_Msk 0x4UL +#define SAR_V2_INTR_DSI_COLLISION_INTR_Pos 3UL +#define SAR_V2_INTR_DSI_COLLISION_INTR_Msk 0x8UL +#define SAR_V2_INTR_INJ_EOC_INTR_Pos 4UL +#define SAR_V2_INTR_INJ_EOC_INTR_Msk 0x10UL +#define SAR_V2_INTR_INJ_SATURATE_INTR_Pos 5UL +#define SAR_V2_INTR_INJ_SATURATE_INTR_Msk 0x20UL +#define SAR_V2_INTR_INJ_RANGE_INTR_Pos 6UL +#define SAR_V2_INTR_INJ_RANGE_INTR_Msk 0x40UL +#define SAR_V2_INTR_INJ_COLLISION_INTR_Pos 7UL +#define SAR_V2_INTR_INJ_COLLISION_INTR_Msk 0x80UL +/* SAR.INTR_SET */ +#define SAR_V2_INTR_SET_EOS_SET_Pos 0UL +#define SAR_V2_INTR_SET_EOS_SET_Msk 0x1UL +#define SAR_V2_INTR_SET_OVERFLOW_SET_Pos 1UL +#define SAR_V2_INTR_SET_OVERFLOW_SET_Msk 0x2UL +#define SAR_V2_INTR_SET_FW_COLLISION_SET_Pos 2UL +#define SAR_V2_INTR_SET_FW_COLLISION_SET_Msk 0x4UL +#define SAR_V2_INTR_SET_DSI_COLLISION_SET_Pos 3UL +#define SAR_V2_INTR_SET_DSI_COLLISION_SET_Msk 0x8UL +#define SAR_V2_INTR_SET_INJ_EOC_SET_Pos 4UL +#define SAR_V2_INTR_SET_INJ_EOC_SET_Msk 0x10UL +#define SAR_V2_INTR_SET_INJ_SATURATE_SET_Pos 5UL +#define SAR_V2_INTR_SET_INJ_SATURATE_SET_Msk 0x20UL +#define SAR_V2_INTR_SET_INJ_RANGE_SET_Pos 6UL +#define SAR_V2_INTR_SET_INJ_RANGE_SET_Msk 0x40UL +#define SAR_V2_INTR_SET_INJ_COLLISION_SET_Pos 7UL +#define SAR_V2_INTR_SET_INJ_COLLISION_SET_Msk 0x80UL +/* SAR.INTR_MASK */ +#define SAR_V2_INTR_MASK_EOS_MASK_Pos 0UL +#define SAR_V2_INTR_MASK_EOS_MASK_Msk 0x1UL +#define SAR_V2_INTR_MASK_OVERFLOW_MASK_Pos 1UL +#define SAR_V2_INTR_MASK_OVERFLOW_MASK_Msk 0x2UL +#define SAR_V2_INTR_MASK_FW_COLLISION_MASK_Pos 2UL +#define SAR_V2_INTR_MASK_FW_COLLISION_MASK_Msk 0x4UL +#define SAR_V2_INTR_MASK_DSI_COLLISION_MASK_Pos 3UL +#define SAR_V2_INTR_MASK_DSI_COLLISION_MASK_Msk 0x8UL +#define SAR_V2_INTR_MASK_INJ_EOC_MASK_Pos 4UL +#define SAR_V2_INTR_MASK_INJ_EOC_MASK_Msk 0x10UL +#define SAR_V2_INTR_MASK_INJ_SATURATE_MASK_Pos 5UL +#define SAR_V2_INTR_MASK_INJ_SATURATE_MASK_Msk 0x20UL +#define SAR_V2_INTR_MASK_INJ_RANGE_MASK_Pos 6UL +#define SAR_V2_INTR_MASK_INJ_RANGE_MASK_Msk 0x40UL +#define SAR_V2_INTR_MASK_INJ_COLLISION_MASK_Pos 7UL +#define SAR_V2_INTR_MASK_INJ_COLLISION_MASK_Msk 0x80UL +/* SAR.INTR_MASKED */ +#define SAR_V2_INTR_MASKED_EOS_MASKED_Pos 0UL +#define SAR_V2_INTR_MASKED_EOS_MASKED_Msk 0x1UL +#define SAR_V2_INTR_MASKED_OVERFLOW_MASKED_Pos 1UL +#define SAR_V2_INTR_MASKED_OVERFLOW_MASKED_Msk 0x2UL +#define SAR_V2_INTR_MASKED_FW_COLLISION_MASKED_Pos 2UL +#define SAR_V2_INTR_MASKED_FW_COLLISION_MASKED_Msk 0x4UL +#define SAR_V2_INTR_MASKED_DSI_COLLISION_MASKED_Pos 3UL +#define SAR_V2_INTR_MASKED_DSI_COLLISION_MASKED_Msk 0x8UL +#define SAR_V2_INTR_MASKED_INJ_EOC_MASKED_Pos 4UL +#define SAR_V2_INTR_MASKED_INJ_EOC_MASKED_Msk 0x10UL +#define SAR_V2_INTR_MASKED_INJ_SATURATE_MASKED_Pos 5UL +#define SAR_V2_INTR_MASKED_INJ_SATURATE_MASKED_Msk 0x20UL +#define SAR_V2_INTR_MASKED_INJ_RANGE_MASKED_Pos 6UL +#define SAR_V2_INTR_MASKED_INJ_RANGE_MASKED_Msk 0x40UL +#define SAR_V2_INTR_MASKED_INJ_COLLISION_MASKED_Pos 7UL +#define SAR_V2_INTR_MASKED_INJ_COLLISION_MASKED_Msk 0x80UL +/* SAR.SATURATE_INTR */ +#define SAR_V2_SATURATE_INTR_SATURATE_INTR_Pos 0UL +#define SAR_V2_SATURATE_INTR_SATURATE_INTR_Msk 0xFFFFUL +/* SAR.SATURATE_INTR_SET */ +#define SAR_V2_SATURATE_INTR_SET_SATURATE_SET_Pos 0UL +#define SAR_V2_SATURATE_INTR_SET_SATURATE_SET_Msk 0xFFFFUL +/* SAR.SATURATE_INTR_MASK */ +#define SAR_V2_SATURATE_INTR_MASK_SATURATE_MASK_Pos 0UL +#define SAR_V2_SATURATE_INTR_MASK_SATURATE_MASK_Msk 0xFFFFUL +/* SAR.SATURATE_INTR_MASKED */ +#define SAR_V2_SATURATE_INTR_MASKED_SATURATE_MASKED_Pos 0UL +#define SAR_V2_SATURATE_INTR_MASKED_SATURATE_MASKED_Msk 0xFFFFUL +/* SAR.RANGE_INTR */ +#define SAR_V2_RANGE_INTR_RANGE_INTR_Pos 0UL +#define SAR_V2_RANGE_INTR_RANGE_INTR_Msk 0xFFFFUL +/* SAR.RANGE_INTR_SET */ +#define SAR_V2_RANGE_INTR_SET_RANGE_SET_Pos 0UL +#define SAR_V2_RANGE_INTR_SET_RANGE_SET_Msk 0xFFFFUL +/* SAR.RANGE_INTR_MASK */ +#define SAR_V2_RANGE_INTR_MASK_RANGE_MASK_Pos 0UL +#define SAR_V2_RANGE_INTR_MASK_RANGE_MASK_Msk 0xFFFFUL +/* SAR.RANGE_INTR_MASKED */ +#define SAR_V2_RANGE_INTR_MASKED_RANGE_MASKED_Pos 0UL +#define SAR_V2_RANGE_INTR_MASKED_RANGE_MASKED_Msk 0xFFFFUL +/* SAR.INTR_CAUSE */ +#define SAR_V2_INTR_CAUSE_EOS_MASKED_MIR_Pos 0UL +#define SAR_V2_INTR_CAUSE_EOS_MASKED_MIR_Msk 0x1UL +#define SAR_V2_INTR_CAUSE_OVERFLOW_MASKED_MIR_Pos 1UL +#define SAR_V2_INTR_CAUSE_OVERFLOW_MASKED_MIR_Msk 0x2UL +#define SAR_V2_INTR_CAUSE_FW_COLLISION_MASKED_MIR_Pos 2UL +#define SAR_V2_INTR_CAUSE_FW_COLLISION_MASKED_MIR_Msk 0x4UL +#define SAR_V2_INTR_CAUSE_DSI_COLLISION_MASKED_MIR_Pos 3UL +#define SAR_V2_INTR_CAUSE_DSI_COLLISION_MASKED_MIR_Msk 0x8UL +#define SAR_V2_INTR_CAUSE_INJ_EOC_MASKED_MIR_Pos 4UL +#define SAR_V2_INTR_CAUSE_INJ_EOC_MASKED_MIR_Msk 0x10UL +#define SAR_V2_INTR_CAUSE_INJ_SATURATE_MASKED_MIR_Pos 5UL +#define SAR_V2_INTR_CAUSE_INJ_SATURATE_MASKED_MIR_Msk 0x20UL +#define SAR_V2_INTR_CAUSE_INJ_RANGE_MASKED_MIR_Pos 6UL +#define SAR_V2_INTR_CAUSE_INJ_RANGE_MASKED_MIR_Msk 0x40UL +#define SAR_V2_INTR_CAUSE_INJ_COLLISION_MASKED_MIR_Pos 7UL +#define SAR_V2_INTR_CAUSE_INJ_COLLISION_MASKED_MIR_Msk 0x80UL +#define SAR_V2_INTR_CAUSE_SATURATE_MASKED_RED_Pos 30UL +#define SAR_V2_INTR_CAUSE_SATURATE_MASKED_RED_Msk 0x40000000UL +#define SAR_V2_INTR_CAUSE_RANGE_MASKED_RED_Pos 31UL +#define SAR_V2_INTR_CAUSE_RANGE_MASKED_RED_Msk 0x80000000UL +/* SAR.STATUS */ +#define SAR_V2_STATUS_CUR_CHAN_Pos 0UL +#define SAR_V2_STATUS_CUR_CHAN_Msk 0x1FUL +#define SAR_V2_STATUS_SW_VREF_NEG_Pos 30UL +#define SAR_V2_STATUS_SW_VREF_NEG_Msk 0x40000000UL +#define SAR_V2_STATUS_BUSY_Pos 31UL +#define SAR_V2_STATUS_BUSY_Msk 0x80000000UL +/* SAR.AVG_STAT */ +#define SAR_V2_AVG_STAT_CUR_AVG_ACCU_Pos 0UL +#define SAR_V2_AVG_STAT_CUR_AVG_ACCU_Msk 0xFFFFFUL +#define SAR_V2_AVG_STAT_INTRLV_BUSY_Pos 23UL +#define SAR_V2_AVG_STAT_INTRLV_BUSY_Msk 0x800000UL +#define SAR_V2_AVG_STAT_CUR_AVG_CNT_Pos 24UL +#define SAR_V2_AVG_STAT_CUR_AVG_CNT_Msk 0xFF000000UL +/* SAR.MUX_SWITCH0 */ +#define SAR_V2_MUX_SWITCH0_MUX_FW_P0_VPLUS_Pos 0UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P0_VPLUS_Msk 0x1UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P1_VPLUS_Pos 1UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P1_VPLUS_Msk 0x2UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P2_VPLUS_Pos 2UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P2_VPLUS_Msk 0x4UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P3_VPLUS_Pos 3UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P3_VPLUS_Msk 0x8UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P4_VPLUS_Pos 4UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P4_VPLUS_Msk 0x10UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P5_VPLUS_Pos 5UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P5_VPLUS_Msk 0x20UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P6_VPLUS_Pos 6UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P6_VPLUS_Msk 0x40UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P7_VPLUS_Pos 7UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P7_VPLUS_Msk 0x80UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P0_VMINUS_Pos 8UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P0_VMINUS_Msk 0x100UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P1_VMINUS_Pos 9UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P1_VMINUS_Msk 0x200UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P2_VMINUS_Pos 10UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P2_VMINUS_Msk 0x400UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P3_VMINUS_Pos 11UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P3_VMINUS_Msk 0x800UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P4_VMINUS_Pos 12UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P4_VMINUS_Msk 0x1000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P5_VMINUS_Pos 13UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P5_VMINUS_Msk 0x2000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P6_VMINUS_Pos 14UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P6_VMINUS_Msk 0x4000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P7_VMINUS_Pos 15UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P7_VMINUS_Msk 0x8000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_VSSA_VMINUS_Pos 16UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_VSSA_VMINUS_Msk 0x10000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_TEMP_VPLUS_Pos 17UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_TEMP_VPLUS_Msk 0x20000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSA_VPLUS_Pos 18UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSA_VPLUS_Msk 0x40000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSB_VPLUS_Pos 19UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSB_VPLUS_Msk 0x80000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSA_VMINUS_Pos 20UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSA_VMINUS_Msk 0x100000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSB_VMINUS_Pos 21UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_AMUXBUSB_VMINUS_Msk 0x200000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS0_VPLUS_Pos 22UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS0_VPLUS_Msk 0x400000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS1_VPLUS_Pos 23UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS1_VPLUS_Msk 0x800000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS0_VMINUS_Pos 24UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS0_VMINUS_Msk 0x1000000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS1_VMINUS_Pos 25UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_SARBUS1_VMINUS_Msk 0x2000000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P4_COREIO0_Pos 26UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P4_COREIO0_Msk 0x4000000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P5_COREIO1_Pos 27UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P5_COREIO1_Msk 0x8000000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P6_COREIO2_Pos 28UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P6_COREIO2_Msk 0x10000000UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P7_COREIO3_Pos 29UL +#define SAR_V2_MUX_SWITCH0_MUX_FW_P7_COREIO3_Msk 0x20000000UL +/* SAR.MUX_SWITCH_CLEAR0 */ +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P0_VPLUS_Pos 0UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P0_VPLUS_Msk 0x1UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P1_VPLUS_Pos 1UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P1_VPLUS_Msk 0x2UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P2_VPLUS_Pos 2UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P2_VPLUS_Msk 0x4UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P3_VPLUS_Pos 3UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P3_VPLUS_Msk 0x8UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P4_VPLUS_Pos 4UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P4_VPLUS_Msk 0x10UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P5_VPLUS_Pos 5UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P5_VPLUS_Msk 0x20UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P6_VPLUS_Pos 6UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P6_VPLUS_Msk 0x40UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P7_VPLUS_Pos 7UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P7_VPLUS_Msk 0x80UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P0_VMINUS_Pos 8UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P0_VMINUS_Msk 0x100UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P1_VMINUS_Pos 9UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P1_VMINUS_Msk 0x200UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P2_VMINUS_Pos 10UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P2_VMINUS_Msk 0x400UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P3_VMINUS_Pos 11UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P3_VMINUS_Msk 0x800UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P4_VMINUS_Pos 12UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P4_VMINUS_Msk 0x1000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P5_VMINUS_Pos 13UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P5_VMINUS_Msk 0x2000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P6_VMINUS_Pos 14UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P6_VMINUS_Msk 0x4000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P7_VMINUS_Pos 15UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P7_VMINUS_Msk 0x8000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_VSSA_VMINUS_Pos 16UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_VSSA_VMINUS_Msk 0x10000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_TEMP_VPLUS_Pos 17UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_TEMP_VPLUS_Msk 0x20000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VPLUS_Pos 18UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VPLUS_Msk 0x40000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VPLUS_Pos 19UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VPLUS_Msk 0x80000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VMINUS_Pos 20UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSA_VMINUS_Msk 0x100000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VMINUS_Pos 21UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_AMUXBUSB_VMINUS_Msk 0x200000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VPLUS_Pos 22UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VPLUS_Msk 0x400000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VPLUS_Pos 23UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VPLUS_Msk 0x800000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VMINUS_Pos 24UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS0_VMINUS_Msk 0x1000000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VMINUS_Pos 25UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_SARBUS1_VMINUS_Msk 0x2000000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P4_COREIO0_Pos 26UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P4_COREIO0_Msk 0x4000000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P5_COREIO1_Pos 27UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P5_COREIO1_Msk 0x8000000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P6_COREIO2_Pos 28UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P6_COREIO2_Msk 0x10000000UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P7_COREIO3_Pos 29UL +#define SAR_V2_MUX_SWITCH_CLEAR0_MUX_FW_P7_COREIO3_Msk 0x20000000UL +/* SAR.MUX_SWITCH_SQ_CTRL */ +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P0_Pos 0UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P0_Msk 0x1UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P1_Pos 1UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P1_Msk 0x2UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P2_Pos 2UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P2_Msk 0x4UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P3_Pos 3UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P3_Msk 0x8UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P4_Pos 4UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P4_Msk 0x10UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P5_Pos 5UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P5_Msk 0x20UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P6_Pos 6UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P6_Msk 0x40UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P7_Pos 7UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_P7_Msk 0x80UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_VSSA_Pos 16UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_VSSA_Msk 0x10000UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_TEMP_Pos 17UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_TEMP_Msk 0x20000UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSA_Pos 18UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSA_Msk 0x40000UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSB_Pos 19UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_AMUXBUSB_Msk 0x80000UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS0_Pos 22UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS0_Msk 0x400000UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS1_Pos 23UL +#define SAR_V2_MUX_SWITCH_SQ_CTRL_MUX_SQ_CTRL_SARBUS1_Msk 0x800000UL +/* SAR.MUX_SWITCH_STATUS */ +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P0_VPLUS_Pos 0UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P0_VPLUS_Msk 0x1UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P1_VPLUS_Pos 1UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P1_VPLUS_Msk 0x2UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P2_VPLUS_Pos 2UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P2_VPLUS_Msk 0x4UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P3_VPLUS_Pos 3UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P3_VPLUS_Msk 0x8UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P4_VPLUS_Pos 4UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P4_VPLUS_Msk 0x10UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P5_VPLUS_Pos 5UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P5_VPLUS_Msk 0x20UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P6_VPLUS_Pos 6UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P6_VPLUS_Msk 0x40UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P7_VPLUS_Pos 7UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P7_VPLUS_Msk 0x80UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P0_VMINUS_Pos 8UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P0_VMINUS_Msk 0x100UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P1_VMINUS_Pos 9UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P1_VMINUS_Msk 0x200UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P2_VMINUS_Pos 10UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P2_VMINUS_Msk 0x400UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P3_VMINUS_Pos 11UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P3_VMINUS_Msk 0x800UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P4_VMINUS_Pos 12UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P4_VMINUS_Msk 0x1000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P5_VMINUS_Pos 13UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P5_VMINUS_Msk 0x2000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P6_VMINUS_Pos 14UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P6_VMINUS_Msk 0x4000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P7_VMINUS_Pos 15UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_P7_VMINUS_Msk 0x8000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_VSSA_VMINUS_Pos 16UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_VSSA_VMINUS_Msk 0x10000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_TEMP_VPLUS_Pos 17UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_TEMP_VPLUS_Msk 0x20000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VPLUS_Pos 18UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VPLUS_Msk 0x40000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VPLUS_Pos 19UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VPLUS_Msk 0x80000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VMINUS_Pos 20UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSA_VMINUS_Msk 0x100000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VMINUS_Pos 21UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_AMUXBUSB_VMINUS_Msk 0x200000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VPLUS_Pos 22UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VPLUS_Msk 0x400000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VPLUS_Pos 23UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VPLUS_Msk 0x800000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VMINUS_Pos 24UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS0_VMINUS_Msk 0x1000000UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VMINUS_Pos 25UL +#define SAR_V2_MUX_SWITCH_STATUS_MUX_FW_SARBUS1_VMINUS_Msk 0x2000000UL + + +#endif /* _CYIP_SAR_V2_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sflash.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sflash.h index f8240086719..16fcf8f4449 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sflash.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_sflash.h @@ -5,7 +5,7 @@ * SFLASH IP definitions * * \note -* Generator version: 1.5.0.1287 +* Generator version: 1.5.1.36 * ******************************************************************************** * \copyright @@ -47,7 +47,14 @@ typedef struct { __IOM uint16_t FAMILY_ID; /*!< 0x0000000C Indicates Family ID of the device */ __IM uint16_t RESERVED2[3]; __IOM uint32_t CPUSS_WOUNDING; /*!< 0x00000014 CPUSS Wounding */ - __IM uint32_t RESERVED3[378]; + __IM uint32_t RESERVED3[2]; + __IOM uint8_t SORT_REV[3]; /*!< 0x00000020 SORT Revision */ + __IOM uint8_t CRI_BB_REV; /*!< 0x00000023 CRI BB Revision */ + __IOM uint8_t CRI_AB_REV; /*!< 0x00000024 CRI AB Revision */ + __IOM uint8_t CHI_AB_REV; /*!< 0x00000025 CHI AB Revision */ + __IM uint16_t RESERVED4[43]; + __IOM uint32_t FB_FLAGS; /*!< 0x0000007C Flash boot flags */ + __IM uint32_t RESERVED5[352]; __IOM uint8_t DIE_LOT[3]; /*!< 0x00000600 Lot Number (3 bytes) */ __IOM uint8_t DIE_WAFER; /*!< 0x00000603 Wafer Number */ __IOM uint8_t DIE_X; /*!< 0x00000604 X Position on Wafer, CRI Pass/Fail Bin */ @@ -57,20 +64,20 @@ typedef struct { __IOM uint8_t DIE_DAY; /*!< 0x00000608 Day number */ __IOM uint8_t DIE_MONTH; /*!< 0x00000609 Month number */ __IOM uint8_t DIE_YEAR; /*!< 0x0000060A Year number */ - __IM uint8_t RESERVED4[61]; + __IM uint8_t RESERVED6[61]; __IOM uint16_t SAR_TEMP_MULTIPLIER; /*!< 0x00000648 SAR Temperature Sensor Multiplication Factor */ __IOM uint16_t SAR_TEMP_OFFSET; /*!< 0x0000064A SAR Temperature Sensor Offset */ - __IM uint32_t RESERVED5[8]; + __IM uint32_t RESERVED7[8]; __IOM uint32_t CSP_PANEL_ID; /*!< 0x0000066C CSP Panel Id to record panel ID of CSP die */ - __IM uint32_t RESERVED6[52]; + __IM uint32_t RESERVED8[52]; __IOM uint8_t LDO_0P9V_TRIM; /*!< 0x00000740 LDO_0P9V_TRIM */ __IOM uint8_t LDO_1P1V_TRIM; /*!< 0x00000741 LDO_1P1V_TRIM */ - __IM uint16_t RESERVED7[95]; + __IM uint16_t RESERVED9[95]; __IOM uint32_t BLE_DEVICE_ADDRESS[128]; /*!< 0x00000800 BLE_DEVICE_ADDRESS */ __IOM uint32_t USER_FREE_ROW1[128]; /*!< 0x00000A00 USER_FREE_ROW1 */ __IOM uint32_t USER_FREE_ROW2[128]; /*!< 0x00000C00 USER_FREE_ROW2 */ __IOM uint32_t USER_FREE_ROW3[128]; /*!< 0x00000E00 USER_FREE_ROW3 */ - __IM uint32_t RESERVED8[302]; + __IM uint32_t RESERVED10[302]; __IOM uint8_t DEVICE_UID[16]; /*!< 0x000014B8 Unique Identifier Number for each device */ __IOM uint8_t MASTER_KEY[16]; /*!< 0x000014C8 Master key to change other keys */ __IOM uint32_t STANDARD_SMPU_STRUCT_SLAVE_ADDR[16]; /*!< 0x000014D8 Standard SMPU STRUCT Slave Address value */ @@ -78,36 +85,36 @@ typedef struct { __IOM uint32_t STANDARD_SMPU_STRUCT_MASTER_ATTR[16]; /*!< 0x00001558 Standard SMPU STRUCT Master Attribute value */ __IOM uint32_t STANDARD_MPU_STRUCT[16]; /*!< 0x00001598 Standard MPU STRUCT */ __IOM uint32_t STANDARD_PPU_STRUCT[16]; /*!< 0x000015D8 Standard PPU STRUCT */ - __IM uint32_t RESERVED9[122]; + __IM uint32_t RESERVED11[122]; __IOM uint16_t PILO_FREQ_STEP; /*!< 0x00001800 Resolution step for PILO at class in BCD format */ - __IM uint16_t RESERVED10; + __IM uint16_t RESERVED12; __IOM uint32_t CSDV2_CSD0_ADC_VREF0; /*!< 0x00001804 CSD 1p2 & 1p6 voltage levels for accuracy */ __IOM uint32_t CSDV2_CSD0_ADC_VREF1; /*!< 0x00001808 CSD 2p1 & 0p8 voltage levels for accuracy */ __IOM uint32_t CSDV2_CSD0_ADC_VREF2; /*!< 0x0000180C CSD calibration spare voltage level for accuracy */ __IOM uint32_t PWR_TRIM_WAKE_CTL; /*!< 0x00001810 Wakeup delay */ - __IM uint16_t RESERVED11; + __IM uint16_t RESERVED13; __IOM uint16_t RADIO_LDO_TRIMS; /*!< 0x00001816 Radio LDO Trims */ __IOM uint32_t CPUSS_TRIM_ROM_CTL_ULP; /*!< 0x00001818 CPUSS TRIM ROM CTL ULP value */ __IOM uint32_t CPUSS_TRIM_RAM_CTL_ULP; /*!< 0x0000181C CPUSS TRIM RAM CTL ULP value */ __IOM uint32_t CPUSS_TRIM_ROM_CTL_LP; /*!< 0x00001820 CPUSS TRIM ROM CTL LP value */ __IOM uint32_t CPUSS_TRIM_RAM_CTL_LP; /*!< 0x00001824 CPUSS TRIM RAM CTL LP value */ - __IM uint32_t RESERVED12[7]; + __IM uint32_t RESERVED14[7]; __IOM uint32_t CPUSS_TRIM_ROM_CTL_HALF_ULP; /*!< 0x00001844 CPUSS TRIM ROM CTL HALF ULP value */ __IOM uint32_t CPUSS_TRIM_RAM_CTL_HALF_ULP; /*!< 0x00001848 CPUSS TRIM RAM CTL HALF ULP value */ __IOM uint32_t CPUSS_TRIM_ROM_CTL_HALF_LP; /*!< 0x0000184C CPUSS TRIM ROM CTL HALF LP value */ __IOM uint32_t CPUSS_TRIM_RAM_CTL_HALF_LP; /*!< 0x00001850 CPUSS TRIM RAM CTL HALF LP value */ - __IM uint32_t RESERVED13[491]; + __IM uint32_t RESERVED15[491]; __IOM uint32_t FLASH_BOOT_OBJECT_SIZE; /*!< 0x00002000 Flash Boot - Object Size */ __IOM uint32_t FLASH_BOOT_APP_ID; /*!< 0x00002004 Flash Boot - Application ID/Version */ __IOM uint32_t FLASH_BOOT_ATTRIBUTE; /*!< 0x00002008 N/A */ __IOM uint32_t FLASH_BOOT_N_CORES; /*!< 0x0000200C Flash Boot - Number of Cores(N) */ __IOM uint32_t FLASH_BOOT_VT_OFFSET; /*!< 0x00002010 Flash Boot - Core Vector Table offset */ __IOM uint32_t FLASH_BOOT_CORE_CPUID; /*!< 0x00002014 Flash Boot - Core CPU ID/Core Index */ - __IM uint32_t RESERVED14[48]; + __IM uint32_t RESERVED16[48]; __IOM uint8_t FLASH_BOOT_CODE[14632]; /*!< 0x000020D8 Flash Boot - Code and Data */ __IOM uint8_t PUBLIC_KEY[3072]; /*!< 0x00005A00 Public key for signature verification (max RSA key size 4096) */ __IOM uint32_t BOOT_PROT_SETTINGS[384]; /*!< 0x00006600 Boot protection settings (not present in PSOC6ABLE2) */ - __IM uint32_t RESERVED15[768]; + __IM uint32_t RESERVED17[768]; __IOM uint32_t TOC1_OBJECT_SIZE; /*!< 0x00007800 Object size in bytes for CRC calculation starting from offset 0x00 */ __IOM uint32_t TOC1_MAGIC_NUMBER; /*!< 0x00007804 Magic number(0x01211219) */ @@ -118,7 +125,7 @@ typedef struct { __IOM uint32_t TOC1_FB_OBJECT_ADDR; /*!< 0x00007814 Addresss of FLASH Boot(FB) object that include FLASH patch also */ __IOM uint32_t TOC1_SYSCALL_TABLE_ADDR_UNUSED; /*!< 0x00007818 Unused (Address is Hardcoded in ROM) */ __IOM uint32_t TOC1_OBJECT_ADDR_UNUSED; /*!< 0x0000781C Unused (Address is Hardcoded in ROM) */ - __IM uint32_t RESERVED16[119]; + __IM uint32_t RESERVED18[119]; __IOM uint32_t TOC1_CRC_ADDR; /*!< 0x000079FC Upper 2 bytes contain CRC16-CCITT and lower 2 bytes are 0 */ __IOM uint32_t RTOC1_OBJECT_SIZE; /*!< 0x00007A00 Redundant Object size in bytes for CRC calculation starting from offset 0x00 */ @@ -131,7 +138,7 @@ typedef struct { patch also */ __IOM uint32_t RTOC1_SYSCALL_TABLE_ADDR_UNUSED; /*!< 0x00007A18 Redundant Unused (Address is Hardcoded in ROM) */ __IOM uint32_t RTOC1_OBJECT_ADDR_UNUSED; /*!< 0x00007A1C Redundant Unused (Address is Hardcoded in ROM) */ - __IM uint32_t RESERVED17[119]; + __IM uint32_t RESERVED19[119]; __IOM uint32_t RTOC1_CRC_ADDR; /*!< 0x00007BFC Redundant CRC,Upper 2 bytes contain CRC16-CCITT and lower 2 bytes are 0 */ __IOM uint32_t TOC2_OBJECT_SIZE; /*!< 0x00007C00 Object size in bytes for CRC calculation starting from offset @@ -151,7 +158,7 @@ typedef struct { SECURE_HASH(SHASH) */ __IOM uint32_t TOC2_SIGNATURE_VERIF_KEY; /*!< 0x00007C24 Address of signature verification key (0 if none).The object is signature specific key. It is the public key in case of RSA */ - __IM uint32_t RESERVED18[115]; + __IM uint32_t RESERVED20[115]; __IOM uint32_t TOC2_REVISION; /*!< 0x00007DF4 Indicates TOC2 Revision. It is not used now. */ __IOM uint32_t TOC2_FLAGS; /*!< 0x00007DF8 TOC2_FLAGS */ __IOM uint32_t TOC2_CRC_ADDR; /*!< 0x00007DFC CRC,Upper 2 bytes contain CRC16-CCITT and lower 2 bytes are 0 */ @@ -173,7 +180,7 @@ typedef struct { __IOM uint32_t RTOC2_SIGNATURE_VERIF_KEY; /*!< 0x00007E24 Redundant Address of signature verification key (0 if none).The object is signature specific key. It is the public key in case of RSA */ - __IM uint32_t RESERVED19[115]; + __IM uint32_t RESERVED21[115]; __IOM uint32_t RTOC2_REVISION; /*!< 0x00007FF4 Indicates RTOC2 Revision. It is not used now. */ __IOM uint32_t RTOC2_FLAGS; /*!< 0x00007FF8 RTOC2_FLAGS */ __IOM uint32_t RTOC2_CRC_ADDR; /*!< 0x00007FFC Redundant CRC,Upper 2 bytes contain CRC16-CCITT and lower 2 @@ -193,6 +200,25 @@ typedef struct { /* SFLASH.CPUSS_WOUNDING */ #define SFLASH_CPUSS_WOUNDING_CPUSS_WOUNDING_Pos 0UL #define SFLASH_CPUSS_WOUNDING_CPUSS_WOUNDING_Msk 0xFFFFFFFFUL +/* SFLASH.SORT_REV */ +#define SFLASH_SORT_REV_DATA_Pos 0UL +#define SFLASH_SORT_REV_DATA_Msk 0xFFUL +/* SFLASH.CRI_BB_REV */ +#define SFLASH_CRI_BB_REV_DATA_Pos 0UL +#define SFLASH_CRI_BB_REV_DATA_Msk 0xFFUL +/* SFLASH.CRI_AB_REV */ +#define SFLASH_CRI_AB_REV_DATA_Pos 0UL +#define SFLASH_CRI_AB_REV_DATA_Msk 0xFFUL +/* SFLASH.CHI_AB_REV */ +#define SFLASH_CHI_AB_REV_DATA_Pos 0UL +#define SFLASH_CHI_AB_REV_DATA_Msk 0xFFUL +/* SFLASH.FB_FLAGS */ +#define SFLASH_FB_FLAGS_FB_PIN_CTL_Pos 0UL +#define SFLASH_FB_FLAGS_FB_PIN_CTL_Msk 0x3UL +#define SFLASH_FB_FLAGS_FB_RSA3K_CTL_Pos 2UL +#define SFLASH_FB_FLAGS_FB_RSA3K_CTL_Msk 0xCUL +#define SFLASH_FB_FLAGS_FB_RSA4K_CTL_Pos 4UL +#define SFLASH_FB_FLAGS_FB_RSA4K_CTL_Msk 0x30UL /* SFLASH.DIE_LOT */ #define SFLASH_DIE_LOT_LOT_Pos 0UL #define SFLASH_DIE_LOT_LOT_Msk 0xFFUL diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_tcpwm_v2.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_tcpwm_v2.h new file mode 100644 index 00000000000..fadb32dcaf5 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_tcpwm_v2.h @@ -0,0 +1,272 @@ +/***************************************************************************//** +* \file cyip_tcpwm_v2.h +* +* \brief +* TCPWM IP definitions +* +* \note +* Generator version: 1.5.1.36 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _CYIP_TCPWM_V2_H_ +#define _CYIP_TCPWM_V2_H_ + +#include "cyip_headers.h" + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM_GRP_CNT_V2_SECTION_SIZE 0x00000080UL +#define TCPWM_GRP_V2_SECTION_SIZE 0x00008000UL +#define TCPWM_V2_SECTION_SIZE 0x00020000UL + +/** + * \brief Timer/Counter/PWM Counter Module (TCPWM_GRP_CNT) + */ +typedef struct { + __IOM uint32_t CTRL; /*!< 0x00000000 Counter control register */ + __IM uint32_t STATUS; /*!< 0x00000004 Counter status register */ + __IOM uint32_t COUNTER; /*!< 0x00000008 Counter count register */ + __IM uint32_t RESERVED; + __IOM uint32_t CC0; /*!< 0x00000010 Counter compare/capture 0 register */ + __IOM uint32_t CC0_BUFF; /*!< 0x00000014 Counter buffered compare/capture 0 register */ + __IOM uint32_t CC1; /*!< 0x00000018 Counter compare/capture 1 register */ + __IOM uint32_t CC1_BUFF; /*!< 0x0000001C Counter buffered compare/capture 1 register */ + __IOM uint32_t PERIOD; /*!< 0x00000020 Counter period register */ + __IOM uint32_t PERIOD_BUFF; /*!< 0x00000024 Counter buffered period register */ + __IOM uint32_t LINE_SEL; /*!< 0x00000028 Counter line selection register */ + __IOM uint32_t LINE_SEL_BUFF; /*!< 0x0000002C Counter buffered line selection register */ + __IOM uint32_t DT; /*!< 0x00000030 Counter PWM dead time register */ + __IM uint32_t RESERVED1[3]; + __IOM uint32_t TR_CMD; /*!< 0x00000040 Counter trigger command register */ + __IOM uint32_t TR_IN_SEL0; /*!< 0x00000044 Counter input trigger selection register 0 */ + __IOM uint32_t TR_IN_SEL1; /*!< 0x00000048 Counter input trigger selection register 1 */ + __IOM uint32_t TR_IN_EDGE_SEL; /*!< 0x0000004C Counter input trigger edge selection register */ + __IOM uint32_t TR_PWM_CTRL; /*!< 0x00000050 Counter trigger PWM control register */ + __IOM uint32_t TR_OUT_SEL; /*!< 0x00000054 Counter output trigger selection register */ + __IM uint32_t RESERVED2[6]; + __IOM uint32_t INTR; /*!< 0x00000070 Interrupt request register */ + __IOM uint32_t INTR_SET; /*!< 0x00000074 Interrupt set request register */ + __IOM uint32_t INTR_MASK; /*!< 0x00000078 Interrupt mask register */ + __IM uint32_t INTR_MASKED; /*!< 0x0000007C Interrupt masked request register */ +} TCPWM_GRP_CNT_V2_Type; /*!< Size = 128 (0x80) */ + +/** + * \brief Group of counters (TCPWM_GRP) + */ +typedef struct { + TCPWM_GRP_CNT_V2_Type CNT[256]; /*!< 0x00000000 Timer/Counter/PWM Counter Module */ +} TCPWM_GRP_V2_Type; /*!< Size = 32768 (0x8000) */ + +/** + * \brief Timer/Counter/PWM (TCPWM) + */ +typedef struct { + TCPWM_GRP_V2_Type GRP[4]; /*!< 0x00000000 Group of counters */ +} TCPWM_V2_Type; /*!< Size = 131072 (0x20000) */ + + +/* TCPWM_GRP_CNT.CTRL */ +#define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC0_Pos 0UL +#define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC0_Msk 0x1UL +#define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC1_Pos 1UL +#define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_CC1_Msk 0x2UL +#define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_PERIOD_Pos 2UL +#define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_PERIOD_Msk 0x4UL +#define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_LINE_SEL_Pos 3UL +#define TCPWM_GRP_CNT_V2_CTRL_AUTO_RELOAD_LINE_SEL_Msk 0x8UL +#define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_UP_EN_Pos 4UL +#define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_UP_EN_Msk 0x10UL +#define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_DOWN_EN_Pos 5UL +#define TCPWM_GRP_CNT_V2_CTRL_CC0_MATCH_DOWN_EN_Msk 0x20UL +#define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_UP_EN_Pos 6UL +#define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_UP_EN_Msk 0x40UL +#define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_DOWN_EN_Pos 7UL +#define TCPWM_GRP_CNT_V2_CTRL_CC1_MATCH_DOWN_EN_Msk 0x80UL +#define TCPWM_GRP_CNT_V2_CTRL_PWM_IMM_KILL_Pos 8UL +#define TCPWM_GRP_CNT_V2_CTRL_PWM_IMM_KILL_Msk 0x100UL +#define TCPWM_GRP_CNT_V2_CTRL_PWM_STOP_ON_KILL_Pos 9UL +#define TCPWM_GRP_CNT_V2_CTRL_PWM_STOP_ON_KILL_Msk 0x200UL +#define TCPWM_GRP_CNT_V2_CTRL_PWM_SYNC_KILL_Pos 10UL +#define TCPWM_GRP_CNT_V2_CTRL_PWM_SYNC_KILL_Msk 0x400UL +#define TCPWM_GRP_CNT_V2_CTRL_PWM_DISABLE_MODE_Pos 12UL +#define TCPWM_GRP_CNT_V2_CTRL_PWM_DISABLE_MODE_Msk 0x3000UL +#define TCPWM_GRP_CNT_V2_CTRL_UP_DOWN_MODE_Pos 16UL +#define TCPWM_GRP_CNT_V2_CTRL_UP_DOWN_MODE_Msk 0x30000UL +#define TCPWM_GRP_CNT_V2_CTRL_ONE_SHOT_Pos 18UL +#define TCPWM_GRP_CNT_V2_CTRL_ONE_SHOT_Msk 0x40000UL +#define TCPWM_GRP_CNT_V2_CTRL_QUAD_ENCODING_MODE_Pos 20UL +#define TCPWM_GRP_CNT_V2_CTRL_QUAD_ENCODING_MODE_Msk 0x300000UL +#define TCPWM_GRP_CNT_V2_CTRL_MODE_Pos 24UL +#define TCPWM_GRP_CNT_V2_CTRL_MODE_Msk 0x7000000UL +#define TCPWM_GRP_CNT_V2_CTRL_DBG_FREEZE_EN_Pos 30UL +#define TCPWM_GRP_CNT_V2_CTRL_DBG_FREEZE_EN_Msk 0x40000000UL +#define TCPWM_GRP_CNT_V2_CTRL_ENABLED_Pos 31UL +#define TCPWM_GRP_CNT_V2_CTRL_ENABLED_Msk 0x80000000UL +/* TCPWM_GRP_CNT.STATUS */ +#define TCPWM_GRP_CNT_V2_STATUS_DOWN_Pos 0UL +#define TCPWM_GRP_CNT_V2_STATUS_DOWN_Msk 0x1UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE0_Pos 4UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE0_Msk 0x10UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_COUNT_Pos 5UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_COUNT_Msk 0x20UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_RELOAD_Pos 6UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_RELOAD_Msk 0x40UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_STOP_Pos 7UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_STOP_Msk 0x80UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_START_Pos 8UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_START_Msk 0x100UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE1_Pos 9UL +#define TCPWM_GRP_CNT_V2_STATUS_TR_CAPTURE1_Msk 0x200UL +#define TCPWM_GRP_CNT_V2_STATUS_LINE_OUT_Pos 10UL +#define TCPWM_GRP_CNT_V2_STATUS_LINE_OUT_Msk 0x400UL +#define TCPWM_GRP_CNT_V2_STATUS_LINE_COMPL_OUT_Pos 11UL +#define TCPWM_GRP_CNT_V2_STATUS_LINE_COMPL_OUT_Msk 0x800UL +#define TCPWM_GRP_CNT_V2_STATUS_RUNNING_Pos 15UL +#define TCPWM_GRP_CNT_V2_STATUS_RUNNING_Msk 0x8000UL +#define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_L_Pos 16UL +#define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_L_Msk 0xFF0000UL +#define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_H_Pos 24UL +#define TCPWM_GRP_CNT_V2_STATUS_DT_CNT_H_Msk 0xFF000000UL +/* TCPWM_GRP_CNT.COUNTER */ +#define TCPWM_GRP_CNT_V2_COUNTER_COUNTER_Pos 0UL +#define TCPWM_GRP_CNT_V2_COUNTER_COUNTER_Msk 0xFFFFFFFFUL +/* TCPWM_GRP_CNT.CC0 */ +#define TCPWM_GRP_CNT_V2_CC0_CC_Pos 0UL +#define TCPWM_GRP_CNT_V2_CC0_CC_Msk 0xFFFFFFFFUL +/* TCPWM_GRP_CNT.CC0_BUFF */ +#define TCPWM_GRP_CNT_V2_CC0_BUFF_CC_Pos 0UL +#define TCPWM_GRP_CNT_V2_CC0_BUFF_CC_Msk 0xFFFFFFFFUL +/* TCPWM_GRP_CNT.CC1 */ +#define TCPWM_GRP_CNT_V2_CC1_CC_Pos 0UL +#define TCPWM_GRP_CNT_V2_CC1_CC_Msk 0xFFFFFFFFUL +/* TCPWM_GRP_CNT.CC1_BUFF */ +#define TCPWM_GRP_CNT_V2_CC1_BUFF_CC_Pos 0UL +#define TCPWM_GRP_CNT_V2_CC1_BUFF_CC_Msk 0xFFFFFFFFUL +/* TCPWM_GRP_CNT.PERIOD */ +#define TCPWM_GRP_CNT_V2_PERIOD_PERIOD_Pos 0UL +#define TCPWM_GRP_CNT_V2_PERIOD_PERIOD_Msk 0xFFFFFFFFUL +/* TCPWM_GRP_CNT.PERIOD_BUFF */ +#define TCPWM_GRP_CNT_V2_PERIOD_BUFF_PERIOD_Pos 0UL +#define TCPWM_GRP_CNT_V2_PERIOD_BUFF_PERIOD_Msk 0xFFFFFFFFUL +/* TCPWM_GRP_CNT.LINE_SEL */ +#define TCPWM_GRP_CNT_V2_LINE_SEL_OUT_SEL_Pos 0UL +#define TCPWM_GRP_CNT_V2_LINE_SEL_OUT_SEL_Msk 0x7UL +#define TCPWM_GRP_CNT_V2_LINE_SEL_COMPL_OUT_SEL_Pos 4UL +#define TCPWM_GRP_CNT_V2_LINE_SEL_COMPL_OUT_SEL_Msk 0x70UL +/* TCPWM_GRP_CNT.LINE_SEL_BUFF */ +#define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_OUT_SEL_Pos 0UL +#define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_OUT_SEL_Msk 0x7UL +#define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_COMPL_OUT_SEL_Pos 4UL +#define TCPWM_GRP_CNT_V2_LINE_SEL_BUFF_COMPL_OUT_SEL_Msk 0x70UL +/* TCPWM_GRP_CNT.DT */ +#define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_L_Pos 0UL +#define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_L_Msk 0xFFUL +#define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_H_Pos 8UL +#define TCPWM_GRP_CNT_V2_DT_DT_LINE_OUT_H_Msk 0xFF00UL +#define TCPWM_GRP_CNT_V2_DT_DT_LINE_COMPL_OUT_Pos 16UL +#define TCPWM_GRP_CNT_V2_DT_DT_LINE_COMPL_OUT_Msk 0xFFFF0000UL +/* TCPWM_GRP_CNT.TR_CMD */ +#define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE0_Pos 0UL +#define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE0_Msk 0x1UL +#define TCPWM_GRP_CNT_V2_TR_CMD_RELOAD_Pos 2UL +#define TCPWM_GRP_CNT_V2_TR_CMD_RELOAD_Msk 0x4UL +#define TCPWM_GRP_CNT_V2_TR_CMD_STOP_Pos 3UL +#define TCPWM_GRP_CNT_V2_TR_CMD_STOP_Msk 0x8UL +#define TCPWM_GRP_CNT_V2_TR_CMD_START_Pos 4UL +#define TCPWM_GRP_CNT_V2_TR_CMD_START_Msk 0x10UL +#define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE1_Pos 5UL +#define TCPWM_GRP_CNT_V2_TR_CMD_CAPTURE1_Msk 0x20UL +/* TCPWM_GRP_CNT.TR_IN_SEL0 */ +#define TCPWM_GRP_CNT_V2_TR_IN_SEL0_CAPTURE0_SEL_Pos 0UL +#define TCPWM_GRP_CNT_V2_TR_IN_SEL0_CAPTURE0_SEL_Msk 0xFFUL +#define TCPWM_GRP_CNT_V2_TR_IN_SEL0_COUNT_SEL_Pos 8UL +#define TCPWM_GRP_CNT_V2_TR_IN_SEL0_COUNT_SEL_Msk 0xFF00UL +#define TCPWM_GRP_CNT_V2_TR_IN_SEL0_RELOAD_SEL_Pos 16UL +#define TCPWM_GRP_CNT_V2_TR_IN_SEL0_RELOAD_SEL_Msk 0xFF0000UL +#define TCPWM_GRP_CNT_V2_TR_IN_SEL0_STOP_SEL_Pos 24UL +#define TCPWM_GRP_CNT_V2_TR_IN_SEL0_STOP_SEL_Msk 0xFF000000UL +/* TCPWM_GRP_CNT.TR_IN_SEL1 */ +#define TCPWM_GRP_CNT_V2_TR_IN_SEL1_START_SEL_Pos 0UL +#define TCPWM_GRP_CNT_V2_TR_IN_SEL1_START_SEL_Msk 0xFFUL +#define TCPWM_GRP_CNT_V2_TR_IN_SEL1_CAPTURE1_SEL_Pos 8UL +#define TCPWM_GRP_CNT_V2_TR_IN_SEL1_CAPTURE1_SEL_Msk 0xFF00UL +/* TCPWM_GRP_CNT.TR_IN_EDGE_SEL */ +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Pos 0UL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE0_EDGE_Msk 0x3UL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_COUNT_EDGE_Pos 2UL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_COUNT_EDGE_Msk 0xCUL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_RELOAD_EDGE_Pos 4UL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_RELOAD_EDGE_Msk 0x30UL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_STOP_EDGE_Pos 6UL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_STOP_EDGE_Msk 0xC0UL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_START_EDGE_Pos 8UL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_START_EDGE_Msk 0x300UL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Pos 10UL +#define TCPWM_GRP_CNT_V2_TR_IN_EDGE_SEL_CAPTURE1_EDGE_Msk 0xC00UL +/* TCPWM_GRP_CNT.TR_PWM_CTRL */ +#define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC0_MATCH_MODE_Pos 0UL +#define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC0_MATCH_MODE_Msk 0x3UL +#define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_OVERFLOW_MODE_Pos 2UL +#define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_OVERFLOW_MODE_Msk 0xCUL +#define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_UNDERFLOW_MODE_Pos 4UL +#define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_UNDERFLOW_MODE_Msk 0x30UL +#define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC1_MATCH_MODE_Pos 6UL +#define TCPWM_GRP_CNT_V2_TR_PWM_CTRL_CC1_MATCH_MODE_Msk 0xC0UL +/* TCPWM_GRP_CNT.TR_OUT_SEL */ +#define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT0_Pos 0UL +#define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT0_Msk 0x7UL +#define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT1_Pos 4UL +#define TCPWM_GRP_CNT_V2_TR_OUT_SEL_OUT1_Msk 0x70UL +/* TCPWM_GRP_CNT.INTR */ +#define TCPWM_GRP_CNT_V2_INTR_TC_Pos 0UL +#define TCPWM_GRP_CNT_V2_INTR_TC_Msk 0x1UL +#define TCPWM_GRP_CNT_V2_INTR_CC0_MATCH_Pos 1UL +#define TCPWM_GRP_CNT_V2_INTR_CC0_MATCH_Msk 0x2UL +#define TCPWM_GRP_CNT_V2_INTR_CC1_MATCH_Pos 2UL +#define TCPWM_GRP_CNT_V2_INTR_CC1_MATCH_Msk 0x4UL +/* TCPWM_GRP_CNT.INTR_SET */ +#define TCPWM_GRP_CNT_V2_INTR_SET_TC_Pos 0UL +#define TCPWM_GRP_CNT_V2_INTR_SET_TC_Msk 0x1UL +#define TCPWM_GRP_CNT_V2_INTR_SET_CC0_MATCH_Pos 1UL +#define TCPWM_GRP_CNT_V2_INTR_SET_CC0_MATCH_Msk 0x2UL +#define TCPWM_GRP_CNT_V2_INTR_SET_CC1_MATCH_Pos 2UL +#define TCPWM_GRP_CNT_V2_INTR_SET_CC1_MATCH_Msk 0x4UL +/* TCPWM_GRP_CNT.INTR_MASK */ +#define TCPWM_GRP_CNT_V2_INTR_MASK_TC_Pos 0UL +#define TCPWM_GRP_CNT_V2_INTR_MASK_TC_Msk 0x1UL +#define TCPWM_GRP_CNT_V2_INTR_MASK_CC0_MATCH_Pos 1UL +#define TCPWM_GRP_CNT_V2_INTR_MASK_CC0_MATCH_Msk 0x2UL +#define TCPWM_GRP_CNT_V2_INTR_MASK_CC1_MATCH_Pos 2UL +#define TCPWM_GRP_CNT_V2_INTR_MASK_CC1_MATCH_Msk 0x4UL +/* TCPWM_GRP_CNT.INTR_MASKED */ +#define TCPWM_GRP_CNT_V2_INTR_MASKED_TC_Pos 0UL +#define TCPWM_GRP_CNT_V2_INTR_MASKED_TC_Msk 0x1UL +#define TCPWM_GRP_CNT_V2_INTR_MASKED_CC0_MATCH_Pos 1UL +#define TCPWM_GRP_CNT_V2_INTR_MASKED_CC0_MATCH_Msk 0x2UL +#define TCPWM_GRP_CNT_V2_INTR_MASKED_CC1_MATCH_Pos 2UL +#define TCPWM_GRP_CNT_V2_INTR_MASKED_CC1_MATCH_Msk 0x4UL + + +#endif /* _CYIP_TCPWM_V2_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_usbfs.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_usbfs.h index 2c2d5df640c..8ea26a2fe0a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_usbfs.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/ip/cyip_usbfs.h @@ -5,7 +5,7 @@ * USBFS IP definitions * * \note -* Generator version: 1.5.0.1286 +* Generator version: 1.5.1.36 * ******************************************************************************** * \copyright @@ -99,10 +99,10 @@ typedef struct { __IOM uint32_t ARB_EP1_INT_EN; /*!< 0x00000204 Endpoint Interrupt Enable Register *1 */ __IOM uint32_t ARB_EP1_SR; /*!< 0x00000208 Endpoint Interrupt Enable Register *1 */ __IM uint32_t RESERVED13; - __IOM uint32_t ARB_RW1_WA; /*!< 0x00000210 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW1_WA_MSB; /*!< 0x00000214 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW1_RA; /*!< 0x00000218 Endpoint Read Address value *1 */ - __IOM uint32_t ARB_RW1_RA_MSB; /*!< 0x0000021C Endpoint Read Address value *1 */ + __IOM uint32_t ARB_RW1_WA; /*!< 0x00000210 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW1_WA_MSB; /*!< 0x00000214 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW1_RA; /*!< 0x00000218 Endpoint Read Address value *1, *2 */ + __IOM uint32_t ARB_RW1_RA_MSB; /*!< 0x0000021C Endpoint Read Address value *1, *2 */ __IOM uint32_t ARB_RW1_DR; /*!< 0x00000220 Endpoint Data Register */ __IM uint32_t RESERVED14[3]; __IOM uint32_t BUF_SIZE; /*!< 0x00000230 Dedicated Endpoint Buffer Size Register *1 */ @@ -113,10 +113,10 @@ typedef struct { __IOM uint32_t ARB_EP2_INT_EN; /*!< 0x00000244 Endpoint Interrupt Enable Register *1 */ __IOM uint32_t ARB_EP2_SR; /*!< 0x00000248 Endpoint Interrupt Enable Register *1 */ __IM uint32_t RESERVED16; - __IOM uint32_t ARB_RW2_WA; /*!< 0x00000250 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW2_WA_MSB; /*!< 0x00000254 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW2_RA; /*!< 0x00000258 Endpoint Read Address value *1 */ - __IOM uint32_t ARB_RW2_RA_MSB; /*!< 0x0000025C Endpoint Read Address value *1 */ + __IOM uint32_t ARB_RW2_WA; /*!< 0x00000250 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW2_WA_MSB; /*!< 0x00000254 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW2_RA; /*!< 0x00000258 Endpoint Read Address value *1, *2 */ + __IOM uint32_t ARB_RW2_RA_MSB; /*!< 0x0000025C Endpoint Read Address value *1, *2 */ __IOM uint32_t ARB_RW2_DR; /*!< 0x00000260 Endpoint Data Register */ __IM uint32_t RESERVED17[3]; __IOM uint32_t ARB_CFG; /*!< 0x00000270 Arbiter Configuration Register *1 */ @@ -127,10 +127,10 @@ typedef struct { __IOM uint32_t ARB_EP3_INT_EN; /*!< 0x00000284 Endpoint Interrupt Enable Register *1 */ __IOM uint32_t ARB_EP3_SR; /*!< 0x00000288 Endpoint Interrupt Enable Register *1 */ __IM uint32_t RESERVED18; - __IOM uint32_t ARB_RW3_WA; /*!< 0x00000290 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW3_WA_MSB; /*!< 0x00000294 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW3_RA; /*!< 0x00000298 Endpoint Read Address value *1 */ - __IOM uint32_t ARB_RW3_RA_MSB; /*!< 0x0000029C Endpoint Read Address value *1 */ + __IOM uint32_t ARB_RW3_WA; /*!< 0x00000290 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW3_WA_MSB; /*!< 0x00000294 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW3_RA; /*!< 0x00000298 Endpoint Read Address value *1, *2 */ + __IOM uint32_t ARB_RW3_RA_MSB; /*!< 0x0000029C Endpoint Read Address value *1, *2 */ __IOM uint32_t ARB_RW3_DR; /*!< 0x000002A0 Endpoint Data Register */ __IM uint32_t RESERVED19[3]; __IOM uint32_t CWA; /*!< 0x000002B0 Common Area Write Address *1 */ @@ -140,10 +140,10 @@ typedef struct { __IOM uint32_t ARB_EP4_INT_EN; /*!< 0x000002C4 Endpoint Interrupt Enable Register *1 */ __IOM uint32_t ARB_EP4_SR; /*!< 0x000002C8 Endpoint Interrupt Enable Register *1 */ __IM uint32_t RESERVED21; - __IOM uint32_t ARB_RW4_WA; /*!< 0x000002D0 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW4_WA_MSB; /*!< 0x000002D4 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW4_RA; /*!< 0x000002D8 Endpoint Read Address value *1 */ - __IOM uint32_t ARB_RW4_RA_MSB; /*!< 0x000002DC Endpoint Read Address value *1 */ + __IOM uint32_t ARB_RW4_WA; /*!< 0x000002D0 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW4_WA_MSB; /*!< 0x000002D4 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW4_RA; /*!< 0x000002D8 Endpoint Read Address value *1, *2 */ + __IOM uint32_t ARB_RW4_RA_MSB; /*!< 0x000002DC Endpoint Read Address value *1, *2 */ __IOM uint32_t ARB_RW4_DR; /*!< 0x000002E0 Endpoint Data Register */ __IM uint32_t RESERVED22[3]; __IOM uint32_t DMA_THRES; /*!< 0x000002F0 DMA Burst / Threshold Configuration */ @@ -153,10 +153,10 @@ typedef struct { __IOM uint32_t ARB_EP5_INT_EN; /*!< 0x00000304 Endpoint Interrupt Enable Register *1 */ __IOM uint32_t ARB_EP5_SR; /*!< 0x00000308 Endpoint Interrupt Enable Register *1 */ __IM uint32_t RESERVED24; - __IOM uint32_t ARB_RW5_WA; /*!< 0x00000310 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW5_WA_MSB; /*!< 0x00000314 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW5_RA; /*!< 0x00000318 Endpoint Read Address value *1 */ - __IOM uint32_t ARB_RW5_RA_MSB; /*!< 0x0000031C Endpoint Read Address value *1 */ + __IOM uint32_t ARB_RW5_WA; /*!< 0x00000310 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW5_WA_MSB; /*!< 0x00000314 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW5_RA; /*!< 0x00000318 Endpoint Read Address value *1, *2 */ + __IOM uint32_t ARB_RW5_RA_MSB; /*!< 0x0000031C Endpoint Read Address value *1, *2 */ __IOM uint32_t ARB_RW5_DR; /*!< 0x00000320 Endpoint Data Register */ __IM uint32_t RESERVED25[3]; __IOM uint32_t BUS_RST_CNT; /*!< 0x00000330 Bus Reset Count Register */ @@ -165,30 +165,30 @@ typedef struct { __IOM uint32_t ARB_EP6_INT_EN; /*!< 0x00000344 Endpoint Interrupt Enable Register *1 */ __IOM uint32_t ARB_EP6_SR; /*!< 0x00000348 Endpoint Interrupt Enable Register *1 */ __IM uint32_t RESERVED27; - __IOM uint32_t ARB_RW6_WA; /*!< 0x00000350 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW6_WA_MSB; /*!< 0x00000354 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW6_RA; /*!< 0x00000358 Endpoint Read Address value *1 */ - __IOM uint32_t ARB_RW6_RA_MSB; /*!< 0x0000035C Endpoint Read Address value *1 */ + __IOM uint32_t ARB_RW6_WA; /*!< 0x00000350 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW6_WA_MSB; /*!< 0x00000354 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW6_RA; /*!< 0x00000358 Endpoint Read Address value *1, *2 */ + __IOM uint32_t ARB_RW6_RA_MSB; /*!< 0x0000035C Endpoint Read Address value *1, *2 */ __IOM uint32_t ARB_RW6_DR; /*!< 0x00000360 Endpoint Data Register */ __IM uint32_t RESERVED28[7]; __IOM uint32_t ARB_EP7_CFG; /*!< 0x00000380 Endpoint Configuration Register *1 */ __IOM uint32_t ARB_EP7_INT_EN; /*!< 0x00000384 Endpoint Interrupt Enable Register *1 */ __IOM uint32_t ARB_EP7_SR; /*!< 0x00000388 Endpoint Interrupt Enable Register *1 */ __IM uint32_t RESERVED29; - __IOM uint32_t ARB_RW7_WA; /*!< 0x00000390 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW7_WA_MSB; /*!< 0x00000394 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW7_RA; /*!< 0x00000398 Endpoint Read Address value *1 */ - __IOM uint32_t ARB_RW7_RA_MSB; /*!< 0x0000039C Endpoint Read Address value *1 */ + __IOM uint32_t ARB_RW7_WA; /*!< 0x00000390 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW7_WA_MSB; /*!< 0x00000394 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW7_RA; /*!< 0x00000398 Endpoint Read Address value *1, *2 */ + __IOM uint32_t ARB_RW7_RA_MSB; /*!< 0x0000039C Endpoint Read Address value *1, *2 */ __IOM uint32_t ARB_RW7_DR; /*!< 0x000003A0 Endpoint Data Register */ __IM uint32_t RESERVED30[7]; __IOM uint32_t ARB_EP8_CFG; /*!< 0x000003C0 Endpoint Configuration Register *1 */ __IOM uint32_t ARB_EP8_INT_EN; /*!< 0x000003C4 Endpoint Interrupt Enable Register *1 */ __IOM uint32_t ARB_EP8_SR; /*!< 0x000003C8 Endpoint Interrupt Enable Register *1 */ __IM uint32_t RESERVED31; - __IOM uint32_t ARB_RW8_WA; /*!< 0x000003D0 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW8_WA_MSB; /*!< 0x000003D4 Endpoint Write Address value *1 */ - __IOM uint32_t ARB_RW8_RA; /*!< 0x000003D8 Endpoint Read Address value *1 */ - __IOM uint32_t ARB_RW8_RA_MSB; /*!< 0x000003DC Endpoint Read Address value *1 */ + __IOM uint32_t ARB_RW8_WA; /*!< 0x000003D0 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW8_WA_MSB; /*!< 0x000003D4 Endpoint Write Address value *1, *2 */ + __IOM uint32_t ARB_RW8_RA; /*!< 0x000003D8 Endpoint Read Address value *1, *2 */ + __IOM uint32_t ARB_RW8_RA_MSB; /*!< 0x000003DC Endpoint Read Address value *1, *2 */ __IOM uint32_t ARB_RW8_DR; /*!< 0x000003E0 Endpoint Data Register */ __IM uint32_t RESERVED32[7]; __IOM uint32_t MEM_DATA[512]; /*!< 0x00000400 DATA */ @@ -197,55 +197,55 @@ typedef struct { __IM uint32_t RESERVED34[7]; __IM uint32_t OSCLK_DR16; /*!< 0x00001080 Oscillator lock data register */ __IM uint32_t RESERVED35[99]; - __IOM uint32_t ARB_RW1_WA16; /*!< 0x00001210 Endpoint Write Address value */ + __IOM uint32_t ARB_RW1_WA16; /*!< 0x00001210 Endpoint Write Address value *3 */ __IM uint32_t RESERVED36; - __IOM uint32_t ARB_RW1_RA16; /*!< 0x00001218 Endpoint Read Address value */ + __IOM uint32_t ARB_RW1_RA16; /*!< 0x00001218 Endpoint Read Address value *3 */ __IM uint32_t RESERVED37; __IOM uint32_t ARB_RW1_DR16; /*!< 0x00001220 Endpoint Data Register */ __IM uint32_t RESERVED38[11]; - __IOM uint32_t ARB_RW2_WA16; /*!< 0x00001250 Endpoint Write Address value */ + __IOM uint32_t ARB_RW2_WA16; /*!< 0x00001250 Endpoint Write Address value *3 */ __IM uint32_t RESERVED39; - __IOM uint32_t ARB_RW2_RA16; /*!< 0x00001258 Endpoint Read Address value */ + __IOM uint32_t ARB_RW2_RA16; /*!< 0x00001258 Endpoint Read Address value *3 */ __IM uint32_t RESERVED40; __IOM uint32_t ARB_RW2_DR16; /*!< 0x00001260 Endpoint Data Register */ __IM uint32_t RESERVED41[11]; - __IOM uint32_t ARB_RW3_WA16; /*!< 0x00001290 Endpoint Write Address value */ + __IOM uint32_t ARB_RW3_WA16; /*!< 0x00001290 Endpoint Write Address value *3 */ __IM uint32_t RESERVED42; - __IOM uint32_t ARB_RW3_RA16; /*!< 0x00001298 Endpoint Read Address value */ + __IOM uint32_t ARB_RW3_RA16; /*!< 0x00001298 Endpoint Read Address value *3 */ __IM uint32_t RESERVED43; __IOM uint32_t ARB_RW3_DR16; /*!< 0x000012A0 Endpoint Data Register */ __IM uint32_t RESERVED44[3]; __IOM uint32_t CWA16; /*!< 0x000012B0 Common Area Write Address */ __IM uint32_t RESERVED45[7]; - __IOM uint32_t ARB_RW4_WA16; /*!< 0x000012D0 Endpoint Write Address value */ + __IOM uint32_t ARB_RW4_WA16; /*!< 0x000012D0 Endpoint Write Address value *3 */ __IM uint32_t RESERVED46; - __IOM uint32_t ARB_RW4_RA16; /*!< 0x000012D8 Endpoint Read Address value */ + __IOM uint32_t ARB_RW4_RA16; /*!< 0x000012D8 Endpoint Read Address value *3 */ __IM uint32_t RESERVED47; __IOM uint32_t ARB_RW4_DR16; /*!< 0x000012E0 Endpoint Data Register */ __IM uint32_t RESERVED48[3]; __IOM uint32_t DMA_THRES16; /*!< 0x000012F0 DMA Burst / Threshold Configuration */ __IM uint32_t RESERVED49[7]; - __IOM uint32_t ARB_RW5_WA16; /*!< 0x00001310 Endpoint Write Address value */ + __IOM uint32_t ARB_RW5_WA16; /*!< 0x00001310 Endpoint Write Address value *3 */ __IM uint32_t RESERVED50; - __IOM uint32_t ARB_RW5_RA16; /*!< 0x00001318 Endpoint Read Address value */ + __IOM uint32_t ARB_RW5_RA16; /*!< 0x00001318 Endpoint Read Address value *3 */ __IM uint32_t RESERVED51; __IOM uint32_t ARB_RW5_DR16; /*!< 0x00001320 Endpoint Data Register */ __IM uint32_t RESERVED52[11]; - __IOM uint32_t ARB_RW6_WA16; /*!< 0x00001350 Endpoint Write Address value */ + __IOM uint32_t ARB_RW6_WA16; /*!< 0x00001350 Endpoint Write Address value *3 */ __IM uint32_t RESERVED53; - __IOM uint32_t ARB_RW6_RA16; /*!< 0x00001358 Endpoint Read Address value */ + __IOM uint32_t ARB_RW6_RA16; /*!< 0x00001358 Endpoint Read Address value *3 */ __IM uint32_t RESERVED54; __IOM uint32_t ARB_RW6_DR16; /*!< 0x00001360 Endpoint Data Register */ __IM uint32_t RESERVED55[11]; - __IOM uint32_t ARB_RW7_WA16; /*!< 0x00001390 Endpoint Write Address value */ + __IOM uint32_t ARB_RW7_WA16; /*!< 0x00001390 Endpoint Write Address value *3 */ __IM uint32_t RESERVED56; - __IOM uint32_t ARB_RW7_RA16; /*!< 0x00001398 Endpoint Read Address value */ + __IOM uint32_t ARB_RW7_RA16; /*!< 0x00001398 Endpoint Read Address value *3 */ __IM uint32_t RESERVED57; __IOM uint32_t ARB_RW7_DR16; /*!< 0x000013A0 Endpoint Data Register */ __IM uint32_t RESERVED58[11]; - __IOM uint32_t ARB_RW8_WA16; /*!< 0x000013D0 Endpoint Write Address value */ + __IOM uint32_t ARB_RW8_WA16; /*!< 0x000013D0 Endpoint Write Address value *3 */ __IM uint32_t RESERVED59; - __IOM uint32_t ARB_RW8_RA16; /*!< 0x000013D8 Endpoint Read Address value */ + __IOM uint32_t ARB_RW8_RA16; /*!< 0x000013D8 Endpoint Read Address value *3 */ __IM uint32_t RESERVED60; __IOM uint32_t ARB_RW8_DR16; /*!< 0x000013E0 Endpoint Data Register */ __IM uint32_t RESERVED61[775]; diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_04_config.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_04_config.h new file mode 100644 index 00000000000..d4ebde4806d --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6_04_config.h @@ -0,0 +1,2972 @@ +/***************************************************************************//** +* \file psoc6_04_config.h +* +* \brief +* PSoC6_04 device configuration header +* +* \note +* Generator version: 1.6.0.76 +* +******************************************************************************** +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _PSOC6_04_CONFIG_H_ +#define _PSOC6_04_CONFIG_H_ + +/* Clock Connections */ +typedef enum +{ + PCLK_SCB0_CLOCK = 0x0000u, /* scb[0].clock */ + PCLK_SCB1_CLOCK = 0x0001u, /* scb[1].clock */ + PCLK_SCB2_CLOCK = 0x0002u, /* scb[2].clock */ + PCLK_SCB4_CLOCK = 0x0003u, /* scb[4].clock */ + PCLK_SCB5_CLOCK = 0x0004u, /* scb[5].clock */ + PCLK_SCB6_CLOCK = 0x0005u, /* scb[6].clock */ + PCLK_SMARTIO9_CLOCK = 0x0006u, /* smartio[9].clock */ + PCLK_TCPWM0_CLOCKS0 = 0x0007u, /* tcpwm[0].clocks[0] */ + PCLK_TCPWM0_CLOCKS1 = 0x0008u, /* tcpwm[0].clocks[1] */ + PCLK_TCPWM0_CLOCKS2 = 0x0009u, /* tcpwm[0].clocks[2] */ + PCLK_TCPWM0_CLOCKS3 = 0x000Au, /* tcpwm[0].clocks[3] */ + PCLK_TCPWM0_CLOCKS256 = 0x000Bu, /* tcpwm[0].clocks[256] */ + PCLK_TCPWM0_CLOCKS257 = 0x000Cu, /* tcpwm[0].clocks[257] */ + PCLK_TCPWM0_CLOCKS258 = 0x000Du, /* tcpwm[0].clocks[258] */ + PCLK_TCPWM0_CLOCKS259 = 0x000Eu, /* tcpwm[0].clocks[259] */ + PCLK_TCPWM0_CLOCKS260 = 0x000Fu, /* tcpwm[0].clocks[260] */ + PCLK_TCPWM0_CLOCKS261 = 0x0010u, /* tcpwm[0].clocks[261] */ + PCLK_TCPWM0_CLOCKS262 = 0x0011u, /* tcpwm[0].clocks[262] */ + PCLK_TCPWM0_CLOCKS263 = 0x0012u, /* tcpwm[0].clocks[263] */ + PCLK_CSD_CLOCK = 0x0013u, /* csd.clock */ + PCLK_LCD_CLOCK = 0x0014u, /* lcd.clock */ + PCLK_CPUSS_CLOCK_TRACE_IN = 0x0015u, /* cpuss.clock_trace_in */ + PCLK_PASS_CLOCK_PUMP_PERI = 0x0016u, /* pass.clock_pump_peri */ + PCLK_PASS_CLOCK_SAR0 = 0x0017u, /* pass.clock_sar[0] */ + PCLK_CANFD0_CLOCK_CAN0 = 0x0018u, /* canfd[0].clock_can[0] */ + PCLK_USB_CLOCK_DEV_BRS = 0x0019u, /* usb.clock_dev_brs */ + PCLK_PASS_CLOCK_CTDAC = 0x001Au, /* pass.clock_ctdac */ + PCLK_PASS_CLOCK_SAR1 = 0x001Bu /* pass.clock_sar[1] */ +} en_clk_dst_t; + +/* Trigger Group */ +/* This section contains the enums related to the Trigger multiplexer (TrigMux) driver. +* Refer to the Cypress Peripheral Driver Library Documentation, section Trigger multiplexer (TrigMux) -> Enumerated Types for details. +*/ +/* Trigger Group Inputs */ +/* Trigger Input Group 0 - PDMA0 Request Assignments */ +typedef enum +{ + TRIG_IN_MUX_0_PDMA0_TR_OUT0 = 0x00000001u, /* cpuss.dw0_tr_out[0] */ + TRIG_IN_MUX_0_PDMA0_TR_OUT1 = 0x00000002u, /* cpuss.dw0_tr_out[1] */ + TRIG_IN_MUX_0_PDMA0_TR_OUT2 = 0x00000003u, /* cpuss.dw0_tr_out[2] */ + TRIG_IN_MUX_0_PDMA0_TR_OUT3 = 0x00000004u, /* cpuss.dw0_tr_out[3] */ + TRIG_IN_MUX_0_PDMA0_TR_OUT4 = 0x00000005u, /* cpuss.dw0_tr_out[4] */ + TRIG_IN_MUX_0_PDMA0_TR_OUT5 = 0x00000006u, /* cpuss.dw0_tr_out[5] */ + TRIG_IN_MUX_0_PDMA0_TR_OUT6 = 0x00000007u, /* cpuss.dw0_tr_out[6] */ + TRIG_IN_MUX_0_PDMA0_TR_OUT7 = 0x00000008u, /* cpuss.dw0_tr_out[7] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT0 = 0x00000009u, /* cpuss.dw1_tr_out[0] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT1 = 0x0000000Au, /* cpuss.dw1_tr_out[1] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT2 = 0x0000000Bu, /* cpuss.dw1_tr_out[2] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT3 = 0x0000000Cu, /* cpuss.dw1_tr_out[3] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT4 = 0x0000000Du, /* cpuss.dw1_tr_out[4] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT5 = 0x0000000Eu, /* cpuss.dw1_tr_out[5] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT6 = 0x0000000Fu, /* cpuss.dw1_tr_out[6] */ + TRIG_IN_MUX_0_PDMA1_TR_OUT7 = 0x00000010u, /* cpuss.dw1_tr_out[7] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT00 = 0x00000011u, /* tcpwm[0].tr_out0[0] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT10 = 0x00000012u, /* tcpwm[0].tr_out1[0] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT01 = 0x00000014u, /* tcpwm[0].tr_out0[1] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT11 = 0x00000015u, /* tcpwm[0].tr_out1[1] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT02 = 0x00000017u, /* tcpwm[0].tr_out0[2] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT12 = 0x00000018u, /* tcpwm[0].tr_out1[2] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT03 = 0x0000001Au, /* tcpwm[0].tr_out0[3] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT13 = 0x0000001Bu, /* tcpwm[0].tr_out1[3] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT0256 = 0x0000001Du, /* tcpwm[0].tr_out0[256] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT1256 = 0x0000001Eu, /* tcpwm[0].tr_out1[256] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT0257 = 0x00000020u, /* tcpwm[0].tr_out0[257] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT1257 = 0x00000021u, /* tcpwm[0].tr_out1[257] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT0258 = 0x00000023u, /* tcpwm[0].tr_out0[258] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT1258 = 0x00000024u, /* tcpwm[0].tr_out1[258] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT0259 = 0x00000026u, /* tcpwm[0].tr_out0[259] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT1259 = 0x00000027u, /* tcpwm[0].tr_out1[259] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT0260 = 0x00000029u, /* tcpwm[0].tr_out0[260] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT1260 = 0x0000002Au, /* tcpwm[0].tr_out1[260] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT0261 = 0x0000002Cu, /* tcpwm[0].tr_out0[261] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT1261 = 0x0000002Du, /* tcpwm[0].tr_out1[261] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT0262 = 0x0000002Fu, /* tcpwm[0].tr_out0[262] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT1262 = 0x00000030u, /* tcpwm[0].tr_out1[262] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT0263 = 0x00000032u, /* tcpwm[0].tr_out0[263] */ + TRIG_IN_MUX_0_TCPWM0_TR_OUT1263 = 0x00000033u, /* tcpwm[0].tr_out1[263] */ + TRIG_IN_MUX_0_MDMA_TR_OUT0 = 0x00000041u, /* cpuss.dmac_tr_out[0] */ + TRIG_IN_MUX_0_MDMA_TR_OUT1 = 0x00000042u, /* cpuss.dmac_tr_out[1] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT0 = 0x00000045u, /* peri.tr_io_input[0] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT1 = 0x00000046u, /* peri.tr_io_input[1] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT2 = 0x00000047u, /* peri.tr_io_input[2] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT3 = 0x00000048u, /* peri.tr_io_input[3] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT4 = 0x00000049u, /* peri.tr_io_input[4] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT5 = 0x0000004Au, /* peri.tr_io_input[5] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT6 = 0x0000004Bu, /* peri.tr_io_input[6] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT7 = 0x0000004Cu, /* peri.tr_io_input[7] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT8 = 0x0000004Du, /* peri.tr_io_input[8] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT9 = 0x0000004Eu, /* peri.tr_io_input[9] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT10 = 0x0000004Fu, /* peri.tr_io_input[10] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT11 = 0x00000050u, /* peri.tr_io_input[11] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT12 = 0x00000051u, /* peri.tr_io_input[12] */ + TRIG_IN_MUX_0_HSIOM_TR_OUT13 = 0x00000052u, /* peri.tr_io_input[13] */ + TRIG_IN_MUX_0_CTI_TR_OUT0 = 0x00000053u, /* cpuss.cti_tr_out[0] */ + TRIG_IN_MUX_0_CTI_TR_OUT1 = 0x00000054u, /* cpuss.cti_tr_out[1] */ + TRIG_IN_MUX_0_FAULT_TR_OUT0 = 0x00000055u, /* cpuss.tr_fault[0] */ + TRIG_IN_MUX_0_FAULT_TR_OUT1 = 0x00000056u /* cpuss.tr_fault[1] */ +} en_trig_input_pdma0_tr_t; + +/* Trigger Input Group 1 - PDMA1 Request Assignments */ +typedef enum +{ + TRIG_IN_MUX_1_PDMA0_TR_OUT0 = 0x00000101u, /* cpuss.dw0_tr_out[0] */ + TRIG_IN_MUX_1_PDMA0_TR_OUT1 = 0x00000102u, /* cpuss.dw0_tr_out[1] */ + TRIG_IN_MUX_1_PDMA0_TR_OUT2 = 0x00000103u, /* cpuss.dw0_tr_out[2] */ + TRIG_IN_MUX_1_PDMA0_TR_OUT3 = 0x00000104u, /* cpuss.dw0_tr_out[3] */ + TRIG_IN_MUX_1_PDMA0_TR_OUT4 = 0x00000105u, /* cpuss.dw0_tr_out[4] */ + TRIG_IN_MUX_1_PDMA0_TR_OUT5 = 0x00000106u, /* cpuss.dw0_tr_out[5] */ + TRIG_IN_MUX_1_PDMA0_TR_OUT6 = 0x00000107u, /* cpuss.dw0_tr_out[6] */ + TRIG_IN_MUX_1_PDMA0_TR_OUT7 = 0x00000108u, /* cpuss.dw0_tr_out[7] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT0 = 0x00000109u, /* cpuss.dw1_tr_out[0] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT1 = 0x0000010Au, /* cpuss.dw1_tr_out[1] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT2 = 0x0000010Bu, /* cpuss.dw1_tr_out[2] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT3 = 0x0000010Cu, /* cpuss.dw1_tr_out[3] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT4 = 0x0000010Du, /* cpuss.dw1_tr_out[4] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT5 = 0x0000010Eu, /* cpuss.dw1_tr_out[5] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT6 = 0x0000010Fu, /* cpuss.dw1_tr_out[6] */ + TRIG_IN_MUX_1_PDMA1_TR_OUT7 = 0x00000110u, /* cpuss.dw1_tr_out[7] */ + TRIG_IN_MUX_1_MDMA_TR_OUT0 = 0x00000141u, /* cpuss.dmac_tr_out[0] */ + TRIG_IN_MUX_1_MDMA_TR_OUT1 = 0x00000142u, /* cpuss.dmac_tr_out[1] */ + TRIG_IN_MUX_1_CSD_ADC_DONE = 0x00000145u, /* csd.tr_adc_done */ + TRIG_IN_MUX_1_HSIOM_TR_OUT14 = 0x00000146u, /* peri.tr_io_input[14] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT15 = 0x00000147u, /* peri.tr_io_input[15] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT16 = 0x00000148u, /* peri.tr_io_input[16] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT17 = 0x00000149u, /* peri.tr_io_input[17] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT18 = 0x0000014Au, /* peri.tr_io_input[18] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT19 = 0x0000014Bu, /* peri.tr_io_input[19] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT20 = 0x0000014Cu, /* peri.tr_io_input[20] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT21 = 0x0000014Du, /* peri.tr_io_input[21] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT22 = 0x0000014Eu, /* peri.tr_io_input[22] */ + TRIG_IN_MUX_1_HSIOM_TR_OUT23 = 0x0000014Fu, /* peri.tr_io_input[23] */ + TRIG_IN_MUX_1_LPCOMP_DSI_COMP0 = 0x00000154u, /* lpcomp.dsi_comp0 */ + TRIG_IN_MUX_1_LPCOMP_DSI_COMP1 = 0x00000155u, /* lpcomp.dsi_comp1 */ + TRIG_IN_MUX_1_CANFD_TT_TR_OUT0 = 0x00000156u /* canfd[0].tr_tmp_rtp_out[0] */ +} en_trig_input_pdma1_tr_t; + +/* Trigger Input Group 2 - TCPWM0 trigger multiplexer */ +typedef enum +{ + TRIG_IN_MUX_2_PDMA0_TR_OUT0 = 0x00000201u, /* cpuss.dw0_tr_out[0] */ + TRIG_IN_MUX_2_PDMA0_TR_OUT1 = 0x00000202u, /* cpuss.dw0_tr_out[1] */ + TRIG_IN_MUX_2_PDMA0_TR_OUT2 = 0x00000203u, /* cpuss.dw0_tr_out[2] */ + TRIG_IN_MUX_2_PDMA0_TR_OUT3 = 0x00000204u, /* cpuss.dw0_tr_out[3] */ + TRIG_IN_MUX_2_PDMA0_TR_OUT4 = 0x00000205u, /* cpuss.dw0_tr_out[4] */ + TRIG_IN_MUX_2_PDMA0_TR_OUT5 = 0x00000206u, /* cpuss.dw0_tr_out[5] */ + TRIG_IN_MUX_2_PDMA0_TR_OUT6 = 0x00000207u, /* cpuss.dw0_tr_out[6] */ + TRIG_IN_MUX_2_PDMA0_TR_OUT7 = 0x00000208u, /* cpuss.dw0_tr_out[7] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT00 = 0x00000209u, /* tcpwm[0].tr_out0[0] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT10 = 0x0000020Au, /* tcpwm[0].tr_out1[0] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT01 = 0x0000020Cu, /* tcpwm[0].tr_out0[1] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT11 = 0x0000020Du, /* tcpwm[0].tr_out1[1] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT02 = 0x0000020Fu, /* tcpwm[0].tr_out0[2] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT12 = 0x00000210u, /* tcpwm[0].tr_out1[2] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT03 = 0x00000212u, /* tcpwm[0].tr_out0[3] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT13 = 0x00000213u, /* tcpwm[0].tr_out1[3] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT0256 = 0x00000221u, /* tcpwm[0].tr_out0[256] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT1256 = 0x00000222u, /* tcpwm[0].tr_out1[256] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT0257 = 0x00000224u, /* tcpwm[0].tr_out0[257] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT1257 = 0x00000225u, /* tcpwm[0].tr_out1[257] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT0258 = 0x00000227u, /* tcpwm[0].tr_out0[258] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT1258 = 0x00000228u, /* tcpwm[0].tr_out1[258] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT0259 = 0x0000022Au, /* tcpwm[0].tr_out0[259] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT1259 = 0x0000022Bu, /* tcpwm[0].tr_out1[259] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT0260 = 0x0000022Du, /* tcpwm[0].tr_out0[260] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT1260 = 0x0000022Eu, /* tcpwm[0].tr_out1[260] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT0261 = 0x00000230u, /* tcpwm[0].tr_out0[261] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT1261 = 0x00000231u, /* tcpwm[0].tr_out1[261] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT0262 = 0x00000233u, /* tcpwm[0].tr_out0[262] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT1262 = 0x00000234u, /* tcpwm[0].tr_out1[262] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT0263 = 0x00000236u, /* tcpwm[0].tr_out0[263] */ + TRIG_IN_MUX_2_TCPWM0_TR_OUT1263 = 0x00000237u, /* tcpwm[0].tr_out1[263] */ + TRIG_IN_MUX_2_MDMA_TR_OUT0 = 0x00000239u, /* cpuss.dmac_tr_out[0] */ + TRIG_IN_MUX_2_MDMA_TR_OUT1 = 0x0000023Au, /* cpuss.dmac_tr_out[1] */ + TRIG_IN_MUX_2_SCB_I2C_SCL0 = 0x0000023Du, /* scb[0].tr_i2c_scl_filtered */ + TRIG_IN_MUX_2_SCB_TX0 = 0x0000023Eu, /* scb[0].tr_tx_req */ + TRIG_IN_MUX_2_SCB_RX0 = 0x0000023Fu, /* scb[0].tr_rx_req */ + TRIG_IN_MUX_2_SCB_I2C_SCL1 = 0x00000240u, /* scb[1].tr_i2c_scl_filtered */ + TRIG_IN_MUX_2_SCB_TX1 = 0x00000241u, /* scb[1].tr_tx_req */ + TRIG_IN_MUX_2_SCB_RX1 = 0x00000242u, /* scb[1].tr_rx_req */ + TRIG_IN_MUX_2_SCB_I2C_SCL2 = 0x00000243u, /* scb[2].tr_i2c_scl_filtered */ + TRIG_IN_MUX_2_SCB_TX2 = 0x00000244u, /* scb[2].tr_tx_req */ + TRIG_IN_MUX_2_SCB_RX2 = 0x00000245u, /* scb[2].tr_rx_req */ + TRIG_IN_MUX_2_SCB_I2C_SCL4 = 0x00000249u, /* scb[4].tr_i2c_scl_filtered */ + TRIG_IN_MUX_2_SCB_TX4 = 0x0000024Au, /* scb[4].tr_tx_req */ + TRIG_IN_MUX_2_SCB_RX4 = 0x0000024Bu, /* scb[4].tr_rx_req */ + TRIG_IN_MUX_2_SCB_I2C_SCL5 = 0x0000024Cu, /* scb[5].tr_i2c_scl_filtered */ + TRIG_IN_MUX_2_SCB_TX5 = 0x0000024Du, /* scb[5].tr_tx_req */ + TRIG_IN_MUX_2_SCB_RX5 = 0x0000024Eu, /* scb[5].tr_rx_req */ + TRIG_IN_MUX_2_SCB_I2C_SCL6 = 0x0000024Fu, /* scb[6].tr_i2c_scl_filtered */ + TRIG_IN_MUX_2_SCB_TX6 = 0x00000250u, /* scb[6].tr_tx_req */ + TRIG_IN_MUX_2_SCB_RX6 = 0x00000251u, /* scb[6].tr_rx_req */ + TRIG_IN_MUX_2_SMIF_TX = 0x00000264u, /* smif.tr_tx_req */ + TRIG_IN_MUX_2_SMIF_RX = 0x00000265u, /* smif.tr_rx_req */ + TRIG_IN_MUX_2_USB_DMA0 = 0x00000266u, /* usb.dma_req[0] */ + TRIG_IN_MUX_2_USB_DMA1 = 0x00000267u, /* usb.dma_req[1] */ + TRIG_IN_MUX_2_USB_DMA2 = 0x00000268u, /* usb.dma_req[2] */ + TRIG_IN_MUX_2_USB_DMA3 = 0x00000269u, /* usb.dma_req[3] */ + TRIG_IN_MUX_2_USB_DMA4 = 0x0000026Au, /* usb.dma_req[4] */ + TRIG_IN_MUX_2_USB_DMA5 = 0x0000026Bu, /* usb.dma_req[5] */ + TRIG_IN_MUX_2_USB_DMA6 = 0x0000026Cu, /* usb.dma_req[6] */ + TRIG_IN_MUX_2_USB_DMA7 = 0x0000026Du, /* usb.dma_req[7] */ + TRIG_IN_MUX_2_PASS_SAR0_DONE = 0x00000273u, /* pass.tr_sar_out[0] */ + TRIG_IN_MUX_2_CSD_SENSE = 0x00000274u, /* csd.dsi_sense_out */ + TRIG_IN_MUX_2_HSIOM_TR_OUT0 = 0x00000275u, /* peri.tr_io_input[0] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT1 = 0x00000276u, /* peri.tr_io_input[1] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT2 = 0x00000277u, /* peri.tr_io_input[2] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT3 = 0x00000278u, /* peri.tr_io_input[3] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT4 = 0x00000279u, /* peri.tr_io_input[4] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT5 = 0x0000027Au, /* peri.tr_io_input[5] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT6 = 0x0000027Bu, /* peri.tr_io_input[6] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT7 = 0x0000027Cu, /* peri.tr_io_input[7] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT8 = 0x0000027Du, /* peri.tr_io_input[8] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT9 = 0x0000027Eu, /* peri.tr_io_input[9] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT10 = 0x0000027Fu, /* peri.tr_io_input[10] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT11 = 0x00000280u, /* peri.tr_io_input[11] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT12 = 0x00000281u, /* peri.tr_io_input[12] */ + TRIG_IN_MUX_2_HSIOM_TR_OUT13 = 0x00000282u, /* peri.tr_io_input[13] */ + TRIG_IN_MUX_2_CTI_TR_OUT0 = 0x00000283u, /* cpuss.cti_tr_out[0] */ + TRIG_IN_MUX_2_CTI_TR_OUT1 = 0x00000284u, /* cpuss.cti_tr_out[1] */ + TRIG_IN_MUX_2_LPCOMP_DSI_COMP0 = 0x00000285u, /* lpcomp.dsi_comp0 */ + TRIG_IN_MUX_2_LPCOMP_DSI_COMP1 = 0x00000286u, /* lpcomp.dsi_comp1 */ + TRIG_IN_MUX_2_CANFD_TT_TR_OUT0 = 0x00000287u, /* canfd[0].tr_tmp_rtp_out[0] */ + TRIG_IN_MUX_2_PASS_CTDAC_EMPTY = 0x00000288u, /* pass.tr_ctdac_empty */ + TRIG_IN_MUX_2_PASS_CTB_CMP0 = 0x00000289u, /* pass.dsi_ctb_cmp0 */ + TRIG_IN_MUX_2_PASS_SAR1_DONE = 0x0000028Au /* pass.tr_sar_out[1] */ +} en_trig_input_tcpwm0_t; + +/* Trigger Input Group 3 - TCPWM0 trigger multiplexer - 2nd */ +typedef enum +{ + TRIG_IN_MUX_3_PDMA1_TR_OUT0 = 0x00000301u, /* cpuss.dw1_tr_out[0] */ + TRIG_IN_MUX_3_PDMA1_TR_OUT1 = 0x00000302u, /* cpuss.dw1_tr_out[1] */ + TRIG_IN_MUX_3_PDMA1_TR_OUT2 = 0x00000303u, /* cpuss.dw1_tr_out[2] */ + TRIG_IN_MUX_3_PDMA1_TR_OUT3 = 0x00000304u, /* cpuss.dw1_tr_out[3] */ + TRIG_IN_MUX_3_PDMA1_TR_OUT4 = 0x00000305u, /* cpuss.dw1_tr_out[4] */ + TRIG_IN_MUX_3_PDMA1_TR_OUT5 = 0x00000306u, /* cpuss.dw1_tr_out[5] */ + TRIG_IN_MUX_3_PDMA1_TR_OUT6 = 0x00000307u, /* cpuss.dw1_tr_out[6] */ + TRIG_IN_MUX_3_PDMA1_TR_OUT7 = 0x00000308u, /* cpuss.dw1_tr_out[7] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT00 = 0x00000309u, /* tcpwm[0].tr_out0[0] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT10 = 0x0000030Au, /* tcpwm[0].tr_out1[0] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT01 = 0x0000030Cu, /* tcpwm[0].tr_out0[1] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT11 = 0x0000030Du, /* tcpwm[0].tr_out1[1] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT02 = 0x0000030Fu, /* tcpwm[0].tr_out0[2] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT12 = 0x00000310u, /* tcpwm[0].tr_out1[2] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT03 = 0x00000312u, /* tcpwm[0].tr_out0[3] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT13 = 0x00000313u, /* tcpwm[0].tr_out1[3] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT0256 = 0x00000321u, /* tcpwm[0].tr_out0[256] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT1256 = 0x00000322u, /* tcpwm[0].tr_out1[256] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT0257 = 0x00000324u, /* tcpwm[0].tr_out0[257] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT1257 = 0x00000325u, /* tcpwm[0].tr_out1[257] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT0258 = 0x00000327u, /* tcpwm[0].tr_out0[258] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT1258 = 0x00000328u, /* tcpwm[0].tr_out1[258] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT0259 = 0x0000032Au, /* tcpwm[0].tr_out0[259] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT1259 = 0x0000032Bu, /* tcpwm[0].tr_out1[259] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT0260 = 0x0000032Du, /* tcpwm[0].tr_out0[260] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT1260 = 0x0000032Eu, /* tcpwm[0].tr_out1[260] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT0261 = 0x00000330u, /* tcpwm[0].tr_out0[261] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT1261 = 0x00000331u, /* tcpwm[0].tr_out1[261] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT0262 = 0x00000333u, /* tcpwm[0].tr_out0[262] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT1262 = 0x00000334u, /* tcpwm[0].tr_out1[262] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT0263 = 0x00000336u, /* tcpwm[0].tr_out0[263] */ + TRIG_IN_MUX_3_TCPWM0_TR_OUT1263 = 0x00000337u, /* tcpwm[0].tr_out1[263] */ + TRIG_IN_MUX_3_MDMA_TR_OUT0 = 0x00000339u, /* cpuss.dmac_tr_out[0] */ + TRIG_IN_MUX_3_MDMA_TR_OUT1 = 0x0000033Au, /* cpuss.dmac_tr_out[1] */ + TRIG_IN_MUX_3_SCB_I2C_SCL0 = 0x0000033Du, /* scb[0].tr_i2c_scl_filtered */ + TRIG_IN_MUX_3_SCB_TX0 = 0x0000033Eu, /* scb[0].tr_tx_req */ + TRIG_IN_MUX_3_SCB_RX0 = 0x0000033Fu, /* scb[0].tr_rx_req */ + TRIG_IN_MUX_3_SCB_I2C_SCL1 = 0x00000340u, /* scb[1].tr_i2c_scl_filtered */ + TRIG_IN_MUX_3_SCB_TX1 = 0x00000341u, /* scb[1].tr_tx_req */ + TRIG_IN_MUX_3_SCB_RX1 = 0x00000342u, /* scb[1].tr_rx_req */ + TRIG_IN_MUX_3_SCB_I2C_SCL2 = 0x00000343u, /* scb[2].tr_i2c_scl_filtered */ + TRIG_IN_MUX_3_SCB_TX2 = 0x00000344u, /* scb[2].tr_tx_req */ + TRIG_IN_MUX_3_SCB_RX2 = 0x00000345u, /* scb[2].tr_rx_req */ + TRIG_IN_MUX_3_SCB_I2C_SCL4 = 0x00000349u, /* scb[4].tr_i2c_scl_filtered */ + TRIG_IN_MUX_3_SCB_TX4 = 0x0000034Au, /* scb[4].tr_tx_req */ + TRIG_IN_MUX_3_SCB_RX4 = 0x0000034Bu, /* scb[4].tr_rx_req */ + TRIG_IN_MUX_3_SCB_I2C_SCL5 = 0x0000034Cu, /* scb[5].tr_i2c_scl_filtered */ + TRIG_IN_MUX_3_SCB_TX5 = 0x0000034Du, /* scb[5].tr_tx_req */ + TRIG_IN_MUX_3_SCB_RX5 = 0x0000034Eu, /* scb[5].tr_rx_req */ + TRIG_IN_MUX_3_SCB_I2C_SCL6 = 0x0000034Fu, /* scb[6].tr_i2c_scl_filtered */ + TRIG_IN_MUX_3_SCB_TX6 = 0x00000350u, /* scb[6].tr_tx_req */ + TRIG_IN_MUX_3_SCB_RX6 = 0x00000351u, /* scb[6].tr_rx_req */ + TRIG_IN_MUX_3_SMIF_TX = 0x00000364u, /* smif.tr_tx_req */ + TRIG_IN_MUX_3_SMIF_RX = 0x00000365u, /* smif.tr_rx_req */ + TRIG_IN_MUX_3_USB_DMA0 = 0x00000366u, /* usb.dma_req[0] */ + TRIG_IN_MUX_3_USB_DMA1 = 0x00000367u, /* usb.dma_req[1] */ + TRIG_IN_MUX_3_USB_DMA2 = 0x00000368u, /* usb.dma_req[2] */ + TRIG_IN_MUX_3_USB_DMA3 = 0x00000369u, /* usb.dma_req[3] */ + TRIG_IN_MUX_3_USB_DMA4 = 0x0000036Au, /* usb.dma_req[4] */ + TRIG_IN_MUX_3_USB_DMA5 = 0x0000036Bu, /* usb.dma_req[5] */ + TRIG_IN_MUX_3_USB_DMA6 = 0x0000036Cu, /* usb.dma_req[6] */ + TRIG_IN_MUX_3_USB_DMA7 = 0x0000036Du, /* usb.dma_req[7] */ + TRIG_IN_MUX_3_PASS_SAR0_DONE = 0x00000373u, /* pass.tr_sar_out[0] */ + TRIG_IN_MUX_3_CSD_SENSE = 0x00000374u, /* csd.dsi_sense_out */ + TRIG_IN_MUX_3_HSIOM_TR_OUT14 = 0x00000375u, /* peri.tr_io_input[14] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT15 = 0x00000376u, /* peri.tr_io_input[15] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT16 = 0x00000377u, /* peri.tr_io_input[16] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT17 = 0x00000378u, /* peri.tr_io_input[17] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT18 = 0x00000379u, /* peri.tr_io_input[18] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT19 = 0x0000037Au, /* peri.tr_io_input[19] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT20 = 0x0000037Bu, /* peri.tr_io_input[20] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT21 = 0x0000037Cu, /* peri.tr_io_input[21] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT22 = 0x0000037Du, /* peri.tr_io_input[22] */ + TRIG_IN_MUX_3_HSIOM_TR_OUT23 = 0x0000037Eu, /* peri.tr_io_input[23] */ + TRIG_IN_MUX_3_FAULT_TR_OUT0 = 0x00000383u, /* cpuss.tr_fault[0] */ + TRIG_IN_MUX_3_FAULT_TR_OUT1 = 0x00000384u, /* cpuss.tr_fault[1] */ + TRIG_IN_MUX_3_LPCOMP_DSI_COMP0 = 0x00000385u, /* lpcomp.dsi_comp0 */ + TRIG_IN_MUX_3_LPCOMP_DSI_COMP1 = 0x00000386u, /* lpcomp.dsi_comp1 */ + TRIG_IN_MUX_3_CANFD_TT_TR_OUT0 = 0x00000387u, /* canfd[0].tr_tmp_rtp_out[0] */ + TRIG_IN_MUX_3_PASS_CTDAC_EMPTY = 0x00000388u, /* pass.tr_ctdac_empty */ + TRIG_IN_MUX_3_PASS_CTB_CMP0 = 0x00000389u, /* pass.dsi_ctb_cmp1 */ + TRIG_IN_MUX_3_PASS_SAR1_DONE = 0x0000038Au /* pass.tr_sar_out[1] */ +} en_trig_input_tcpwm0_2_t; + +/* Trigger Input Group 4 - HSIOM trigger multiplexer */ +typedef enum +{ + TRIG_IN_MUX_4_PDMA0_TR_OUT0 = 0x00000401u, /* cpuss.dw0_tr_out[0] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT1 = 0x00000402u, /* cpuss.dw0_tr_out[1] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT2 = 0x00000403u, /* cpuss.dw0_tr_out[2] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT3 = 0x00000404u, /* cpuss.dw0_tr_out[3] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT4 = 0x00000405u, /* cpuss.dw0_tr_out[4] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT5 = 0x00000406u, /* cpuss.dw0_tr_out[5] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT6 = 0x00000407u, /* cpuss.dw0_tr_out[6] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT7 = 0x00000408u, /* cpuss.dw0_tr_out[7] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT8 = 0x00000409u, /* cpuss.dw0_tr_out[8] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT9 = 0x0000040Au, /* cpuss.dw0_tr_out[9] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT10 = 0x0000040Bu, /* cpuss.dw0_tr_out[10] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT11 = 0x0000040Cu, /* cpuss.dw0_tr_out[11] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT12 = 0x0000040Du, /* cpuss.dw0_tr_out[12] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT13 = 0x0000040Eu, /* cpuss.dw0_tr_out[13] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT14 = 0x0000040Fu, /* cpuss.dw0_tr_out[14] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT15 = 0x00000410u, /* cpuss.dw0_tr_out[15] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT16 = 0x00000411u, /* cpuss.dw0_tr_out[16] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT17 = 0x00000412u, /* cpuss.dw0_tr_out[17] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT18 = 0x00000413u, /* cpuss.dw0_tr_out[18] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT19 = 0x00000414u, /* cpuss.dw0_tr_out[19] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT20 = 0x00000415u, /* cpuss.dw0_tr_out[20] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT21 = 0x00000416u, /* cpuss.dw0_tr_out[21] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT22 = 0x00000417u, /* cpuss.dw0_tr_out[22] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT23 = 0x00000418u, /* cpuss.dw0_tr_out[23] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT24 = 0x00000419u, /* cpuss.dw0_tr_out[24] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT25 = 0x0000041Au, /* cpuss.dw0_tr_out[25] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT26 = 0x0000041Bu, /* cpuss.dw0_tr_out[26] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT27 = 0x0000041Cu, /* cpuss.dw0_tr_out[27] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT28 = 0x0000041Du, /* cpuss.dw0_tr_out[28] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT0 = 0x0000041Eu, /* cpuss.dw1_tr_out[0] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT1 = 0x0000041Fu, /* cpuss.dw1_tr_out[1] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT2 = 0x00000420u, /* cpuss.dw1_tr_out[2] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT3 = 0x00000421u, /* cpuss.dw1_tr_out[3] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT4 = 0x00000422u, /* cpuss.dw1_tr_out[4] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT5 = 0x00000423u, /* cpuss.dw1_tr_out[5] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT6 = 0x00000424u, /* cpuss.dw1_tr_out[6] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT7 = 0x00000425u, /* cpuss.dw1_tr_out[7] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT8 = 0x00000426u, /* cpuss.dw1_tr_out[8] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT9 = 0x00000427u, /* cpuss.dw1_tr_out[9] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT10 = 0x00000428u, /* cpuss.dw1_tr_out[10] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT11 = 0x00000429u, /* cpuss.dw1_tr_out[11] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT12 = 0x0000042Au, /* cpuss.dw1_tr_out[12] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT13 = 0x0000042Bu, /* cpuss.dw1_tr_out[13] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT14 = 0x0000042Cu, /* cpuss.dw1_tr_out[14] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT15 = 0x0000042Du, /* cpuss.dw1_tr_out[15] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT16 = 0x0000042Eu, /* cpuss.dw1_tr_out[16] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT17 = 0x0000042Fu, /* cpuss.dw1_tr_out[17] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT18 = 0x00000430u, /* cpuss.dw1_tr_out[18] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT19 = 0x00000431u, /* cpuss.dw1_tr_out[19] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT20 = 0x00000432u, /* cpuss.dw1_tr_out[20] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT21 = 0x00000433u, /* cpuss.dw1_tr_out[21] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT22 = 0x00000434u, /* cpuss.dw1_tr_out[22] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT23 = 0x00000435u, /* cpuss.dw1_tr_out[23] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT24 = 0x00000436u, /* cpuss.dw1_tr_out[24] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT25 = 0x00000437u, /* cpuss.dw1_tr_out[25] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT26 = 0x00000438u, /* cpuss.dw1_tr_out[26] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT27 = 0x00000439u, /* cpuss.dw1_tr_out[27] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT28 = 0x0000043Au, /* cpuss.dw1_tr_out[28] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT00 = 0x0000043Bu, /* tcpwm[0].tr_out0[0] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT10 = 0x0000043Cu, /* tcpwm[0].tr_out1[0] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT01 = 0x0000043Eu, /* tcpwm[0].tr_out0[1] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT11 = 0x0000043Fu, /* tcpwm[0].tr_out1[1] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT02 = 0x00000441u, /* tcpwm[0].tr_out0[2] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT12 = 0x00000442u, /* tcpwm[0].tr_out1[2] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT03 = 0x00000444u, /* tcpwm[0].tr_out0[3] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT13 = 0x00000445u, /* tcpwm[0].tr_out1[3] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT0256 = 0x00000453u, /* tcpwm[0].tr_out0[256] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT1256 = 0x00000454u, /* tcpwm[0].tr_out1[256] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT0257 = 0x00000456u, /* tcpwm[0].tr_out0[257] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT1257 = 0x00000457u, /* tcpwm[0].tr_out1[257] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT0258 = 0x00000459u, /* tcpwm[0].tr_out0[258] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT1258 = 0x0000045Au, /* tcpwm[0].tr_out1[258] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT0259 = 0x0000045Cu, /* tcpwm[0].tr_out0[259] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT1259 = 0x0000045Du, /* tcpwm[0].tr_out1[259] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT0260 = 0x0000045Fu, /* tcpwm[0].tr_out0[260] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT1260 = 0x00000460u, /* tcpwm[0].tr_out1[260] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT0261 = 0x00000462u, /* tcpwm[0].tr_out0[261] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT1261 = 0x00000463u, /* tcpwm[0].tr_out1[261] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT0262 = 0x00000465u, /* tcpwm[0].tr_out0[262] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT1262 = 0x00000466u, /* tcpwm[0].tr_out1[262] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT0263 = 0x00000468u, /* tcpwm[0].tr_out0[263] */ + TRIG_IN_MUX_4_TCPWM0_TR_OUT1263 = 0x00000469u, /* tcpwm[0].tr_out1[263] */ + TRIG_IN_MUX_4_MDMA_TR_OUT0 = 0x0000049Bu, /* cpuss.dmac_tr_out[0] */ + TRIG_IN_MUX_4_MDMA_TR_OUT1 = 0x0000049Cu, /* cpuss.dmac_tr_out[1] */ + TRIG_IN_MUX_4_SCB_I2C_SCL0 = 0x0000049Fu, /* scb[0].tr_i2c_scl_filtered */ + TRIG_IN_MUX_4_SCB_TX0 = 0x000004A0u, /* scb[0].tr_tx_req */ + TRIG_IN_MUX_4_SCB_RX0 = 0x000004A1u, /* scb[0].tr_rx_req */ + TRIG_IN_MUX_4_SCB_I2C_SCL1 = 0x000004A2u, /* scb[1].tr_i2c_scl_filtered */ + TRIG_IN_MUX_4_SCB_TX1 = 0x000004A3u, /* scb[1].tr_tx_req */ + TRIG_IN_MUX_4_SCB_RX1 = 0x000004A4u, /* scb[1].tr_rx_req */ + TRIG_IN_MUX_4_SCB_I2C_SCL2 = 0x000004A5u, /* scb[2].tr_i2c_scl_filtered */ + TRIG_IN_MUX_4_SCB_TX2 = 0x000004A6u, /* scb[2].tr_tx_req */ + TRIG_IN_MUX_4_SCB_RX2 = 0x000004A7u, /* scb[2].tr_rx_req */ + TRIG_IN_MUX_4_SCB_I2C_SCL4 = 0x000004ABu, /* scb[4].tr_i2c_scl_filtered */ + TRIG_IN_MUX_4_SCB_TX4 = 0x000004ACu, /* scb[4].tr_tx_req */ + TRIG_IN_MUX_4_SCB_RX4 = 0x000004ADu, /* scb[4].tr_rx_req */ + TRIG_IN_MUX_4_SCB_I2C_SCL5 = 0x000004AEu, /* scb[5].tr_i2c_scl_filtered */ + TRIG_IN_MUX_4_SCB_TX5 = 0x000004AFu, /* scb[5].tr_tx_req */ + TRIG_IN_MUX_4_SCB_RX5 = 0x000004B0u, /* scb[5].tr_rx_req */ + TRIG_IN_MUX_4_SCB_I2C_SCL6 = 0x000004B1u, /* scb[6].tr_i2c_scl_filtered */ + TRIG_IN_MUX_4_SCB_TX6 = 0x000004B2u, /* scb[6].tr_tx_req */ + TRIG_IN_MUX_4_SCB_RX6 = 0x000004B3u, /* scb[6].tr_rx_req */ + TRIG_IN_MUX_4_SMIF_TX = 0x000004C6u, /* smif.tr_tx_req */ + TRIG_IN_MUX_4_SMIF_RX = 0x000004C7u, /* smif.tr_rx_req */ + TRIG_IN_MUX_4_USB_DMA0 = 0x000004C8u, /* usb.dma_req[0] */ + TRIG_IN_MUX_4_USB_DMA1 = 0x000004C9u, /* usb.dma_req[1] */ + TRIG_IN_MUX_4_USB_DMA2 = 0x000004CAu, /* usb.dma_req[2] */ + TRIG_IN_MUX_4_USB_DMA3 = 0x000004CBu, /* usb.dma_req[3] */ + TRIG_IN_MUX_4_USB_DMA4 = 0x000004CCu, /* usb.dma_req[4] */ + TRIG_IN_MUX_4_USB_DMA5 = 0x000004CDu, /* usb.dma_req[5] */ + TRIG_IN_MUX_4_USB_DMA6 = 0x000004CEu, /* usb.dma_req[6] */ + TRIG_IN_MUX_4_USB_DMA7 = 0x000004CFu, /* usb.dma_req[7] */ + TRIG_IN_MUX_4_CSD_SENSE = 0x000004D5u, /* csd.dsi_sense_out */ + TRIG_IN_MUX_4_CSD_SAMPLE = 0x000004D6u, /* csd.dsi_sample_out */ + TRIG_IN_MUX_4_CSD_ADC_DONE = 0x000004D7u, /* csd.tr_adc_done */ + TRIG_IN_MUX_4_PASS_SAR0_DONE = 0x000004D8u, /* pass.tr_sar_out[0] */ + TRIG_IN_MUX_4_FAULT_TR_OUT0 = 0x000004D9u, /* cpuss.tr_fault[0] */ + TRIG_IN_MUX_4_FAULT_TR_OUT1 = 0x000004DAu, /* cpuss.tr_fault[1] */ + TRIG_IN_MUX_4_CTI_TR_OUT0 = 0x000004DBu, /* cpuss.cti_tr_out[0] */ + TRIG_IN_MUX_4_CTI_TR_OUT1 = 0x000004DCu, /* cpuss.cti_tr_out[1] */ + TRIG_IN_MUX_4_LPCOMP_DSI_COMP0 = 0x000004DDu, /* lpcomp.dsi_comp0 */ + TRIG_IN_MUX_4_LPCOMP_DSI_COMP1 = 0x000004DEu, /* lpcomp.dsi_comp1 */ + TRIG_IN_MUX_4_CANFD_TT_TR_OUT0 = 0x000004DFu, /* canfd[0].tr_tmp_rtp_out[0] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT29 = 0x000004E0u, /* cpuss.dw1_tr_out[29] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT30 = 0x000004E1u, /* cpuss.dw1_tr_out[30] */ + TRIG_IN_MUX_4_PDMA1_TR_OUT31 = 0x000004E2u, /* cpuss.dw1_tr_out[31] */ + TRIG_IN_MUX_4_PASS_SAR1_DONE = 0x000004E3u, /* pass.tr_sar_out[1] */ + TRIG_IN_MUX_4_PDMA0_TR_OUT29 = 0x000004E4u /* cpuss.dw0_tr_out[29] */ +} en_trig_input_hsiom_t; + +/* Trigger Input Group 5 - CPUSS Debug trigger multiplexer */ +typedef enum +{ + TRIG_IN_MUX_5_PDMA0_TR_OUT0 = 0x00000501u, /* cpuss.dw0_tr_out[0] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT1 = 0x00000502u, /* cpuss.dw0_tr_out[1] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT2 = 0x00000503u, /* cpuss.dw0_tr_out[2] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT3 = 0x00000504u, /* cpuss.dw0_tr_out[3] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT4 = 0x00000505u, /* cpuss.dw0_tr_out[4] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT5 = 0x00000506u, /* cpuss.dw0_tr_out[5] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT6 = 0x00000507u, /* cpuss.dw0_tr_out[6] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT7 = 0x00000508u, /* cpuss.dw0_tr_out[7] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT8 = 0x00000509u, /* cpuss.dw0_tr_out[8] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT9 = 0x0000050Au, /* cpuss.dw0_tr_out[9] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT10 = 0x0000050Bu, /* cpuss.dw0_tr_out[10] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT11 = 0x0000050Cu, /* cpuss.dw0_tr_out[11] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT12 = 0x0000050Du, /* cpuss.dw0_tr_out[12] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT13 = 0x0000050Eu, /* cpuss.dw0_tr_out[13] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT14 = 0x0000050Fu, /* cpuss.dw0_tr_out[14] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT15 = 0x00000510u, /* cpuss.dw0_tr_out[15] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT16 = 0x00000511u, /* cpuss.dw0_tr_out[16] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT17 = 0x00000512u, /* cpuss.dw0_tr_out[17] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT18 = 0x00000513u, /* cpuss.dw0_tr_out[18] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT19 = 0x00000514u, /* cpuss.dw0_tr_out[19] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT20 = 0x00000515u, /* cpuss.dw0_tr_out[20] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT21 = 0x00000516u, /* cpuss.dw0_tr_out[21] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT22 = 0x00000517u, /* cpuss.dw0_tr_out[22] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT23 = 0x00000518u, /* cpuss.dw0_tr_out[23] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT24 = 0x00000519u, /* cpuss.dw0_tr_out[24] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT25 = 0x0000051Au, /* cpuss.dw0_tr_out[25] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT26 = 0x0000051Bu, /* cpuss.dw0_tr_out[26] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT27 = 0x0000051Cu, /* cpuss.dw0_tr_out[27] */ + TRIG_IN_MUX_5_PDMA0_TR_OUT28 = 0x0000051Du, /* cpuss.dw0_tr_out[28] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT0 = 0x0000051Eu, /* cpuss.dw1_tr_out[0] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT1 = 0x0000051Fu, /* cpuss.dw1_tr_out[1] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT2 = 0x00000520u, /* cpuss.dw1_tr_out[2] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT3 = 0x00000521u, /* cpuss.dw1_tr_out[3] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT4 = 0x00000522u, /* cpuss.dw1_tr_out[4] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT5 = 0x00000523u, /* cpuss.dw1_tr_out[5] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT6 = 0x00000524u, /* cpuss.dw1_tr_out[6] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT7 = 0x00000525u, /* cpuss.dw1_tr_out[7] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT8 = 0x00000526u, /* cpuss.dw1_tr_out[8] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT9 = 0x00000527u, /* cpuss.dw1_tr_out[9] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT10 = 0x00000528u, /* cpuss.dw1_tr_out[10] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT11 = 0x00000529u, /* cpuss.dw1_tr_out[11] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT12 = 0x0000052Au, /* cpuss.dw1_tr_out[12] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT13 = 0x0000052Bu, /* cpuss.dw1_tr_out[13] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT14 = 0x0000052Cu, /* cpuss.dw1_tr_out[14] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT15 = 0x0000052Du, /* cpuss.dw1_tr_out[15] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT16 = 0x0000052Eu, /* cpuss.dw1_tr_out[16] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT17 = 0x0000052Fu, /* cpuss.dw1_tr_out[17] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT18 = 0x00000530u, /* cpuss.dw1_tr_out[18] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT19 = 0x00000531u, /* cpuss.dw1_tr_out[19] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT20 = 0x00000532u, /* cpuss.dw1_tr_out[20] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT21 = 0x00000533u, /* cpuss.dw1_tr_out[21] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT22 = 0x00000534u, /* cpuss.dw1_tr_out[22] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT23 = 0x00000535u, /* cpuss.dw1_tr_out[23] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT24 = 0x00000536u, /* cpuss.dw1_tr_out[24] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT25 = 0x00000537u, /* cpuss.dw1_tr_out[25] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT26 = 0x00000538u, /* cpuss.dw1_tr_out[26] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT27 = 0x00000539u, /* cpuss.dw1_tr_out[27] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT28 = 0x0000053Au, /* cpuss.dw1_tr_out[28] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT00 = 0x0000053Bu, /* tcpwm[0].tr_out0[0] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT10 = 0x0000053Cu, /* tcpwm[0].tr_out1[0] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT01 = 0x0000053Eu, /* tcpwm[0].tr_out0[1] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT11 = 0x0000053Fu, /* tcpwm[0].tr_out1[1] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT02 = 0x00000541u, /* tcpwm[0].tr_out0[2] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT12 = 0x00000542u, /* tcpwm[0].tr_out1[2] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT03 = 0x00000544u, /* tcpwm[0].tr_out0[3] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT13 = 0x00000545u, /* tcpwm[0].tr_out1[3] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT0256 = 0x00000553u, /* tcpwm[0].tr_out0[256] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT1256 = 0x00000554u, /* tcpwm[0].tr_out1[256] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT0257 = 0x00000556u, /* tcpwm[0].tr_out0[257] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT1257 = 0x00000557u, /* tcpwm[0].tr_out1[257] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT0258 = 0x00000559u, /* tcpwm[0].tr_out0[258] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT1258 = 0x0000055Au, /* tcpwm[0].tr_out1[258] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT0259 = 0x0000055Cu, /* tcpwm[0].tr_out0[259] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT1259 = 0x0000055Du, /* tcpwm[0].tr_out1[259] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT0260 = 0x0000055Fu, /* tcpwm[0].tr_out0[260] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT1260 = 0x00000560u, /* tcpwm[0].tr_out1[260] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT0261 = 0x00000562u, /* tcpwm[0].tr_out0[261] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT1261 = 0x00000563u, /* tcpwm[0].tr_out1[261] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT0262 = 0x00000565u, /* tcpwm[0].tr_out0[262] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT1262 = 0x00000566u, /* tcpwm[0].tr_out1[262] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT0263 = 0x00000568u, /* tcpwm[0].tr_out0[263] */ + TRIG_IN_MUX_5_TCPWM0_TR_OUT1263 = 0x00000569u, /* tcpwm[0].tr_out1[263] */ + TRIG_IN_MUX_5_MDMA_TR_OUT0 = 0x0000059Bu, /* cpuss.dmac_tr_out[0] */ + TRIG_IN_MUX_5_MDMA_TR_OUT1 = 0x0000059Cu, /* cpuss.dmac_tr_out[1] */ + TRIG_IN_MUX_5_SCB_I2C_SCL0 = 0x0000059Fu, /* scb[0].tr_i2c_scl_filtered */ + TRIG_IN_MUX_5_SCB_TX0 = 0x000005A0u, /* scb[0].tr_tx_req */ + TRIG_IN_MUX_5_SCB_RX0 = 0x000005A1u, /* scb[0].tr_rx_req */ + TRIG_IN_MUX_5_SCB_I2C_SCL1 = 0x000005A2u, /* scb[1].tr_i2c_scl_filtered */ + TRIG_IN_MUX_5_SCB_TX1 = 0x000005A3u, /* scb[1].tr_tx_req */ + TRIG_IN_MUX_5_SCB_RX1 = 0x000005A4u, /* scb[1].tr_rx_req */ + TRIG_IN_MUX_5_SCB_I2C_SCL2 = 0x000005A5u, /* scb[2].tr_i2c_scl_filtered */ + TRIG_IN_MUX_5_SCB_TX2 = 0x000005A6u, /* scb[2].tr_tx_req */ + TRIG_IN_MUX_5_SCB_RX2 = 0x000005A7u, /* scb[2].tr_rx_req */ + TRIG_IN_MUX_5_SCB_I2C_SCL4 = 0x000005ABu, /* scb[4].tr_i2c_scl_filtered */ + TRIG_IN_MUX_5_SCB_TX4 = 0x000005ACu, /* scb[4].tr_tx_req */ + TRIG_IN_MUX_5_SCB_RX4 = 0x000005ADu, /* scb[4].tr_rx_req */ + TRIG_IN_MUX_5_SCB_I2C_SCL5 = 0x000005AEu, /* scb[5].tr_i2c_scl_filtered */ + TRIG_IN_MUX_5_SCB_TX5 = 0x000005AFu, /* scb[5].tr_tx_req */ + TRIG_IN_MUX_5_SCB_RX5 = 0x000005B0u, /* scb[5].tr_rx_req */ + TRIG_IN_MUX_5_SCB_I2C_SCL6 = 0x000005B1u, /* scb[6].tr_i2c_scl_filtered */ + TRIG_IN_MUX_5_SCB_TX6 = 0x000005B2u, /* scb[6].tr_tx_req */ + TRIG_IN_MUX_5_SCB_RX6 = 0x000005B3u, /* scb[6].tr_rx_req */ + TRIG_IN_MUX_5_SMIF_TX = 0x000005C6u, /* smif.tr_tx_req */ + TRIG_IN_MUX_5_SMIF_RX = 0x000005C7u, /* smif.tr_rx_req */ + TRIG_IN_MUX_5_USB_DMA0 = 0x000005C8u, /* usb.dma_req[0] */ + TRIG_IN_MUX_5_USB_DMA1 = 0x000005C9u, /* usb.dma_req[1] */ + TRIG_IN_MUX_5_USB_DMA2 = 0x000005CAu, /* usb.dma_req[2] */ + TRIG_IN_MUX_5_USB_DMA3 = 0x000005CBu, /* usb.dma_req[3] */ + TRIG_IN_MUX_5_USB_DMA4 = 0x000005CCu, /* usb.dma_req[4] */ + TRIG_IN_MUX_5_USB_DMA5 = 0x000005CDu, /* usb.dma_req[5] */ + TRIG_IN_MUX_5_USB_DMA6 = 0x000005CEu, /* usb.dma_req[6] */ + TRIG_IN_MUX_5_USB_DMA7 = 0x000005CFu, /* usb.dma_req[7] */ + TRIG_IN_MUX_5_CSD_SENSE = 0x000005D5u, /* csd.dsi_sense_out */ + TRIG_IN_MUX_5_CSD_SAMPLE = 0x000005D6u, /* csd.dsi_sample_out */ + TRIG_IN_MUX_5_CSD_ADC_DONE = 0x000005D7u, /* csd.tr_adc_done */ + TRIG_IN_MUX_5_PASS_SAR0_DONE = 0x000005D8u, /* pass.tr_sar_out[0] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT0 = 0x000005D9u, /* peri.tr_io_input[0] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT1 = 0x000005DAu, /* peri.tr_io_input[1] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT2 = 0x000005DBu, /* peri.tr_io_input[2] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT3 = 0x000005DCu, /* peri.tr_io_input[3] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT4 = 0x000005DDu, /* peri.tr_io_input[4] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT5 = 0x000005DEu, /* peri.tr_io_input[5] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT6 = 0x000005DFu, /* peri.tr_io_input[6] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT7 = 0x000005E0u, /* peri.tr_io_input[7] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT8 = 0x000005E1u, /* peri.tr_io_input[8] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT9 = 0x000005E2u, /* peri.tr_io_input[9] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT10 = 0x000005E3u, /* peri.tr_io_input[10] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT11 = 0x000005E4u, /* peri.tr_io_input[11] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT12 = 0x000005E5u, /* peri.tr_io_input[12] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT13 = 0x000005E6u, /* peri.tr_io_input[13] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT14 = 0x000005E7u, /* peri.tr_io_input[14] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT15 = 0x000005E8u, /* peri.tr_io_input[15] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT16 = 0x000005E9u, /* peri.tr_io_input[16] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT17 = 0x000005EAu, /* peri.tr_io_input[17] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT18 = 0x000005EBu, /* peri.tr_io_input[18] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT19 = 0x000005ECu, /* peri.tr_io_input[19] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT20 = 0x000005EDu, /* peri.tr_io_input[20] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT21 = 0x000005EEu, /* peri.tr_io_input[21] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT22 = 0x000005EFu, /* peri.tr_io_input[22] */ + TRIG_IN_MUX_5_HSIOM_TR_OUT23 = 0x000005F0u, /* peri.tr_io_input[23] */ + TRIG_IN_MUX_5_FAULT_TR_OUT0 = 0x000005F5u, /* cpuss.tr_fault[0] */ + TRIG_IN_MUX_5_FAULT_TR_OUT1 = 0x000005F6u, /* cpuss.tr_fault[1] */ + TRIG_IN_MUX_5_CTI_TR_OUT0 = 0x000005F7u, /* cpuss.cti_tr_out[0] */ + TRIG_IN_MUX_5_CTI_TR_OUT1 = 0x000005F8u, /* cpuss.cti_tr_out[1] */ + TRIG_IN_MUX_5_LPCOMP_DSI_COMP0 = 0x000005F9u, /* lpcomp.dsi_comp0 */ + TRIG_IN_MUX_5_LPCOMP_DSI_COMP1 = 0x000005FAu, /* lpcomp.dsi_comp1 */ + TRIG_IN_MUX_5_CANFD_TT_TR_OUT0 = 0x000005FBu, /* canfd[0].tr_tmp_rtp_out[0] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT29 = 0x000005FCu, /* cpuss.dw1_tr_out[29] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT30 = 0x000005FDu, /* cpuss.dw1_tr_out[30] */ + TRIG_IN_MUX_5_PDMA1_TR_OUT31 = 0x000005FEu, /* cpuss.dw1_tr_out[31] */ + TRIG_IN_MUX_5_PASS_SAR1_DONE = 0x000005FFu /* pass.tr_sar_out[1] */ +} en_trig_input_cpuss_cti_t; + +/* Trigger Input Group 6 - MDMA trigger multiplexer */ +typedef enum +{ + TRIG_IN_MUX_6_TCPWM0_TR_OUT0256 = 0x00000601u, /* tcpwm[0].tr_out0[256] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT1256 = 0x00000602u, /* tcpwm[0].tr_out1[256] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT0257 = 0x00000604u, /* tcpwm[0].tr_out0[257] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT1257 = 0x00000605u, /* tcpwm[0].tr_out1[257] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT0258 = 0x00000607u, /* tcpwm[0].tr_out0[258] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT1258 = 0x00000608u, /* tcpwm[0].tr_out1[258] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT0259 = 0x0000060Au, /* tcpwm[0].tr_out0[259] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT1259 = 0x0000060Bu, /* tcpwm[0].tr_out1[259] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT0260 = 0x0000060Du, /* tcpwm[0].tr_out0[260] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT1260 = 0x0000060Eu, /* tcpwm[0].tr_out1[260] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT0261 = 0x00000610u, /* tcpwm[0].tr_out0[261] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT1261 = 0x00000611u, /* tcpwm[0].tr_out1[261] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT0262 = 0x00000613u, /* tcpwm[0].tr_out0[262] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT1262 = 0x00000614u, /* tcpwm[0].tr_out1[262] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT0263 = 0x00000616u, /* tcpwm[0].tr_out0[263] */ + TRIG_IN_MUX_6_TCPWM0_TR_OUT1263 = 0x00000617u, /* tcpwm[0].tr_out1[263] */ + TRIG_IN_MUX_6_SMIF_TX = 0x00000619u, /* smif.tr_tx_req */ + TRIG_IN_MUX_6_SMIF_RX = 0x0000061Au /* smif.tr_rx_req */ +} en_trig_input_mdma_t; + +/* Trigger Input Group 7 - PERI Freeze trigger multiplexer */ +typedef enum +{ + TRIG_IN_MUX_7_CTI_TR_OUT0 = 0x00000701u, /* cpuss.cti_tr_out[0] */ + TRIG_IN_MUX_7_CTI_TR_OUT1 = 0x00000702u /* cpuss.cti_tr_out[1] */ +} en_trig_input_peri_freeze_t; + +/* Trigger Input Group 8 - Capsense trigger multiplexer */ +typedef enum +{ + TRIG_IN_MUX_8_TCPWM0_TR_OUT00 = 0x00000801u, /* tcpwm[0].tr_out0[0] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT10 = 0x00000802u, /* tcpwm[0].tr_out1[0] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT01 = 0x00000804u, /* tcpwm[0].tr_out0[1] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT11 = 0x00000805u, /* tcpwm[0].tr_out1[1] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT02 = 0x00000807u, /* tcpwm[0].tr_out0[2] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT12 = 0x00000808u, /* tcpwm[0].tr_out1[2] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT03 = 0x0000080Au, /* tcpwm[0].tr_out0[3] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT13 = 0x0000080Bu, /* tcpwm[0].tr_out1[3] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT0256 = 0x00000819u, /* tcpwm[0].tr_out0[256] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT1256 = 0x0000081Au, /* tcpwm[0].tr_out1[256] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT0257 = 0x0000081Cu, /* tcpwm[0].tr_out0[257] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT1257 = 0x0000081Du, /* tcpwm[0].tr_out1[257] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT0258 = 0x0000081Fu, /* tcpwm[0].tr_out0[258] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT1258 = 0x00000820u, /* tcpwm[0].tr_out1[258] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT0259 = 0x00000822u, /* tcpwm[0].tr_out0[259] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT1259 = 0x00000823u, /* tcpwm[0].tr_out1[259] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT0260 = 0x00000825u, /* tcpwm[0].tr_out0[260] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT1260 = 0x00000826u, /* tcpwm[0].tr_out1[260] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT0261 = 0x00000828u, /* tcpwm[0].tr_out0[261] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT1261 = 0x00000829u, /* tcpwm[0].tr_out1[261] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT0262 = 0x0000082Bu, /* tcpwm[0].tr_out0[262] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT1262 = 0x0000082Cu, /* tcpwm[0].tr_out1[262] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT0263 = 0x0000082Eu, /* tcpwm[0].tr_out0[263] */ + TRIG_IN_MUX_8_TCPWM0_TR_OUT1263 = 0x0000082Fu, /* tcpwm[0].tr_out1[263] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT0 = 0x0000086Du, /* peri.tr_io_input[0] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT1 = 0x0000086Eu, /* peri.tr_io_input[1] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT2 = 0x0000086Fu, /* peri.tr_io_input[2] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT3 = 0x00000870u, /* peri.tr_io_input[3] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT4 = 0x00000871u, /* peri.tr_io_input[4] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT5 = 0x00000872u, /* peri.tr_io_input[5] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT6 = 0x00000873u, /* peri.tr_io_input[6] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT7 = 0x00000874u, /* peri.tr_io_input[7] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT8 = 0x00000875u, /* peri.tr_io_input[8] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT9 = 0x00000876u, /* peri.tr_io_input[9] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT10 = 0x00000877u, /* peri.tr_io_input[10] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT11 = 0x00000878u, /* peri.tr_io_input[11] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT12 = 0x00000879u, /* peri.tr_io_input[12] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT13 = 0x0000087Au, /* peri.tr_io_input[13] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT14 = 0x0000087Bu, /* peri.tr_io_input[14] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT15 = 0x0000087Cu, /* peri.tr_io_input[15] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT16 = 0x0000087Du, /* peri.tr_io_input[16] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT17 = 0x0000087Eu, /* peri.tr_io_input[17] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT18 = 0x0000087Fu, /* peri.tr_io_input[18] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT19 = 0x00000880u, /* peri.tr_io_input[19] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT20 = 0x00000881u, /* peri.tr_io_input[20] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT21 = 0x00000882u, /* peri.tr_io_input[21] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT22 = 0x00000883u, /* peri.tr_io_input[22] */ + TRIG_IN_MUX_8_HSIOM_TR_OUT23 = 0x00000884u, /* peri.tr_io_input[23] */ + TRIG_IN_MUX_8_LPCOMP_DSI_COMP0 = 0x00000889u, /* lpcomp.dsi_comp0 */ + TRIG_IN_MUX_8_LPCOMP_DSI_COMP1 = 0x0000088Au /* lpcomp.dsi_comp1 */ +} en_trig_input_csd_t; + +/* Trigger Input Group 9 - ADC trigger multiplexer */ +typedef enum +{ + TRIG_IN_MUX_9_TCPWM0_TR_OUT00 = 0x00000901u, /* tcpwm[0].tr_out0[0] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT10 = 0x00000902u, /* tcpwm[0].tr_out1[0] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT01 = 0x00000904u, /* tcpwm[0].tr_out0[1] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT11 = 0x00000905u, /* tcpwm[0].tr_out1[1] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT02 = 0x00000907u, /* tcpwm[0].tr_out0[2] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT12 = 0x00000908u, /* tcpwm[0].tr_out1[2] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT03 = 0x0000090Au, /* tcpwm[0].tr_out0[3] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT13 = 0x0000090Bu, /* tcpwm[0].tr_out1[3] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT0256 = 0x00000919u, /* tcpwm[0].tr_out0[256] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT1256 = 0x0000091Au, /* tcpwm[0].tr_out1[256] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT0257 = 0x0000091Cu, /* tcpwm[0].tr_out0[257] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT1257 = 0x0000091Du, /* tcpwm[0].tr_out1[257] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT0258 = 0x0000091Fu, /* tcpwm[0].tr_out0[258] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT1258 = 0x00000920u, /* tcpwm[0].tr_out1[258] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT0259 = 0x00000922u, /* tcpwm[0].tr_out0[259] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT1259 = 0x00000923u, /* tcpwm[0].tr_out1[259] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT0260 = 0x00000925u, /* tcpwm[0].tr_out0[260] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT1260 = 0x00000926u, /* tcpwm[0].tr_out1[260] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT0261 = 0x00000928u, /* tcpwm[0].tr_out0[261] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT1261 = 0x00000929u, /* tcpwm[0].tr_out1[261] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT0262 = 0x0000092Bu, /* tcpwm[0].tr_out0[262] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT1262 = 0x0000092Cu, /* tcpwm[0].tr_out1[262] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT0263 = 0x0000092Eu, /* tcpwm[0].tr_out0[263] */ + TRIG_IN_MUX_9_TCPWM0_TR_OUT1263 = 0x0000092Fu, /* tcpwm[0].tr_out1[263] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT0 = 0x00000961u, /* peri.tr_io_input[0] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT1 = 0x00000962u, /* peri.tr_io_input[1] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT2 = 0x00000963u, /* peri.tr_io_input[2] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT3 = 0x00000964u, /* peri.tr_io_input[3] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT4 = 0x00000965u, /* peri.tr_io_input[4] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT5 = 0x00000966u, /* peri.tr_io_input[5] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT6 = 0x00000967u, /* peri.tr_io_input[6] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT7 = 0x00000968u, /* peri.tr_io_input[7] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT8 = 0x00000969u, /* peri.tr_io_input[8] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT9 = 0x0000096Au, /* peri.tr_io_input[9] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT10 = 0x0000096Bu, /* peri.tr_io_input[10] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT11 = 0x0000096Cu, /* peri.tr_io_input[11] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT12 = 0x0000096Du, /* peri.tr_io_input[12] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT13 = 0x0000096Eu, /* peri.tr_io_input[13] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT14 = 0x0000096Fu, /* peri.tr_io_input[14] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT15 = 0x00000970u, /* peri.tr_io_input[15] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT16 = 0x00000971u, /* peri.tr_io_input[16] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT17 = 0x00000972u, /* peri.tr_io_input[17] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT18 = 0x00000973u, /* peri.tr_io_input[18] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT19 = 0x00000974u, /* peri.tr_io_input[19] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT20 = 0x00000975u, /* peri.tr_io_input[20] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT21 = 0x00000976u, /* peri.tr_io_input[21] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT22 = 0x00000977u, /* peri.tr_io_input[22] */ + TRIG_IN_MUX_9_HSIOM_TR_OUT23 = 0x00000978u, /* peri.tr_io_input[23] */ + TRIG_IN_MUX_9_LPCOMP_DSI_COMP0 = 0x0000097Du, /* lpcomp.dsi_comp0 */ + TRIG_IN_MUX_9_LPCOMP_DSI_COMP1 = 0x0000097Eu /* lpcomp.dsi_comp1 */ +} en_trig_input_sar_adc_start_t; + +/* Trigger Input Group 10 - CAN TT Synchronization triggers */ +typedef enum +{ + TRIG_IN_MUX_10_CAN_TT_TR_OUT0 = 0x00000A01u /* canfd[0].tr_tmp_rtp_out[0] */ +} en_trig_input_cantt_t; + +/* Trigger Group Outputs */ +/* Trigger Output Group 0 - PDMA0 Request Assignments */ +typedef enum +{ + TRIG_OUT_MUX_0_PDMA0_TR_IN0 = 0x40000000u, /* cpuss.dw0_tr_in[0] */ + TRIG_OUT_MUX_0_PDMA0_TR_IN1 = 0x40000001u, /* cpuss.dw0_tr_in[1] */ + TRIG_OUT_MUX_0_PDMA0_TR_IN2 = 0x40000002u, /* cpuss.dw0_tr_in[2] */ + TRIG_OUT_MUX_0_PDMA0_TR_IN3 = 0x40000003u, /* cpuss.dw0_tr_in[3] */ + TRIG_OUT_MUX_0_PDMA0_TR_IN4 = 0x40000004u, /* cpuss.dw0_tr_in[4] */ + TRIG_OUT_MUX_0_PDMA0_TR_IN5 = 0x40000005u, /* cpuss.dw0_tr_in[5] */ + TRIG_OUT_MUX_0_PDMA0_TR_IN6 = 0x40000006u, /* cpuss.dw0_tr_in[6] */ + TRIG_OUT_MUX_0_PDMA0_TR_IN7 = 0x40000007u /* cpuss.dw0_tr_in[7] */ +} en_trig_output_pdma0_tr_t; + +/* Trigger Output Group 1 - PDMA1 Request Assignments */ +typedef enum +{ + TRIG_OUT_MUX_1_PDMA1_TR_IN0 = 0x40000100u, /* cpuss.dw1_tr_in[0] */ + TRIG_OUT_MUX_1_PDMA1_TR_IN1 = 0x40000101u, /* cpuss.dw1_tr_in[1] */ + TRIG_OUT_MUX_1_PDMA1_TR_IN2 = 0x40000102u, /* cpuss.dw1_tr_in[2] */ + TRIG_OUT_MUX_1_PDMA1_TR_IN3 = 0x40000103u, /* cpuss.dw1_tr_in[3] */ + TRIG_OUT_MUX_1_PDMA1_TR_IN4 = 0x40000104u, /* cpuss.dw1_tr_in[4] */ + TRIG_OUT_MUX_1_PDMA1_TR_IN5 = 0x40000105u, /* cpuss.dw1_tr_in[5] */ + TRIG_OUT_MUX_1_PDMA1_TR_IN6 = 0x40000106u, /* cpuss.dw1_tr_in[6] */ + TRIG_OUT_MUX_1_PDMA1_TR_IN7 = 0x40000107u /* cpuss.dw1_tr_in[7] */ +} en_trig_output_pdma1_tr_t; + +/* Trigger Output Group 2 - TCPWM0 trigger multiplexer */ +typedef enum +{ + TRIG_OUT_MUX_2_TCPWM0_TR_IN0 = 0x40000200u, /* tcpwm[0].tr_all_cnt_in[0] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN1 = 0x40000201u, /* tcpwm[0].tr_all_cnt_in[1] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN2 = 0x40000202u, /* tcpwm[0].tr_all_cnt_in[2] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN3 = 0x40000203u, /* tcpwm[0].tr_all_cnt_in[3] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN4 = 0x40000204u, /* tcpwm[0].tr_all_cnt_in[4] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN5 = 0x40000205u, /* tcpwm[0].tr_all_cnt_in[5] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN6 = 0x40000206u, /* tcpwm[0].tr_all_cnt_in[6] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN7 = 0x40000207u, /* tcpwm[0].tr_all_cnt_in[7] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN8 = 0x40000208u, /* tcpwm[0].tr_all_cnt_in[8] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN9 = 0x40000209u, /* tcpwm[0].tr_all_cnt_in[9] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN10 = 0x4000020Au, /* tcpwm[0].tr_all_cnt_in[10] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN11 = 0x4000020Bu, /* tcpwm[0].tr_all_cnt_in[11] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN12 = 0x4000020Cu, /* tcpwm[0].tr_all_cnt_in[12] */ + TRIG_OUT_MUX_2_TCPWM0_TR_IN13 = 0x4000020Du /* tcpwm[0].tr_all_cnt_in[13] */ +} en_trig_output_tcpwm0_t; + +/* Trigger Output Group 3 - TCPWM0 trigger multiplexer - 2nd */ +typedef enum +{ + TRIG_OUT_MUX_3_TCPWM1_TR_IN0 = 0x40000300u, /* tcpwm[0].tr_all_cnt_in[14] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN1 = 0x40000301u, /* tcpwm[0].tr_all_cnt_in[15] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN2 = 0x40000302u, /* tcpwm[0].tr_all_cnt_in[16] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN3 = 0x40000303u, /* tcpwm[0].tr_all_cnt_in[17] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN4 = 0x40000304u, /* tcpwm[0].tr_all_cnt_in[18] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN5 = 0x40000305u, /* tcpwm[0].tr_all_cnt_in[19] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN6 = 0x40000306u, /* tcpwm[0].tr_all_cnt_in[20] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN7 = 0x40000307u, /* tcpwm[0].tr_all_cnt_in[21] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN8 = 0x40000308u, /* tcpwm[0].tr_all_cnt_in[22] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN9 = 0x40000309u, /* tcpwm[0].tr_all_cnt_in[23] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN10 = 0x4000030Au, /* tcpwm[0].tr_all_cnt_in[24] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN11 = 0x4000030Bu, /* tcpwm[0].tr_all_cnt_in[25] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN12 = 0x4000030Cu, /* tcpwm[0].tr_all_cnt_in[26] */ + TRIG_OUT_MUX_3_TCPWM1_TR_IN13 = 0x4000030Du /* tcpwm[0].tr_all_cnt_in[27] */ +} en_trig_output_tcpwm0_2_t; + +/* Trigger Output Group 4 - HSIOM trigger multiplexer */ +typedef enum +{ + TRIG_OUT_MUX_4_HSIOM_TR_IO_OUTPUT0 = 0x40000400u, /* peri.tr_io_output[0] */ + TRIG_OUT_MUX_4_HSIOM_TR_IO_OUTPUT1 = 0x40000401u /* peri.tr_io_output[1] */ +} en_trig_output_hsiom_t; + +/* Trigger Output Group 5 - CPUSS Debug trigger multiplexer */ +typedef enum +{ + TRIG_OUT_MUX_5_CPUSS_CTI_TR_IN0 = 0x40000500u, /* cpuss.cti_tr_in[0] */ + TRIG_OUT_MUX_5_CPUSS_CTI_TR_IN1 = 0x40000501u /* cpuss.cti_tr_in[1] */ +} en_trig_output_cpuss_cti_t; + +/* Trigger Output Group 6 - MDMA trigger multiplexer */ +typedef enum +{ + TRIG_OUT_MUX_6_MDMA_TR_IN0 = 0x40000600u, /* cpuss.dmac_tr_in[0] */ + TRIG_OUT_MUX_6_MDMA_TR_IN1 = 0x40000601u /* cpuss.dmac_tr_in[1] */ +} en_trig_output_mdma_t; + +/* Trigger Output Group 7 - PERI Freeze trigger multiplexer */ +typedef enum +{ + TRIG_OUT_MUX_7_DEBUG_FREEZE_TR_IN = 0x40000700u, /* peri.tr_dbg_freeze */ + TRIG_OUT_MUX_7_TCPWM_DEBUG_FREEZE_TR_IN = 0x40000701u /* tcpwm[0].tr_debug_freeze */ +} en_trig_output_peri_freeze_t; + +/* Trigger Output Group 8 - Capsense trigger multiplexer */ +typedef enum +{ + TRIG_OUT_MUX_8_CSD_DSI_START = 0x40000800u /* csd.dsi_start */ +} en_trig_output_csd_t; + +/* Trigger Output Group 9 - ADC trigger multiplexer */ +typedef enum +{ + TRIG_OUT_MUX_9_PASS_TR_SAR_IN0 = 0x40000900u, /* pass.tr_sar_in[0] */ + TRIG_OUT_MUX_9_PASS_TR_SAR_IN1 = 0x40000901u /* pass.tr_sar_in[1] */ +} en_trig_output_sar_adc_start_t; + +/* Trigger Output Group 10 - CAN TT Synchronization triggers */ +typedef enum +{ + TRIG_OUT_MUX_10_CAN_TT_TR_IN0 = 0x40000A00u /* canfd[0].tr_evt_swt_in[0] */ +} en_trig_output_cantt_t; + +/* Trigger Output Group 0 - SCB PDMA0 Triggers (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_0_SCB0_TX_TO_PDMA0_TR_IN16 = 0x40001000u, /* From scb[0].tr_tx_req to cpuss.dw0_tr_in[16] */ + TRIG_OUT_1TO1_0_SCB0_RX_TO_PDMA0_TR_IN17 = 0x40001001u, /* From scb[0].tr_rx_req to cpuss.dw0_tr_in[17] */ + TRIG_OUT_1TO1_0_SCB1_TX_TO_PDMA0_TR_IN18 = 0x40001002u, /* From scb[1].tr_tx_req to cpuss.dw0_tr_in[18] */ + TRIG_OUT_1TO1_0_SCB1_RX_TO_PDMA0_TR_IN19 = 0x40001003u, /* From scb[1].tr_rx_req to cpuss.dw0_tr_in[19] */ + TRIG_OUT_1TO1_0_SCB2_TX_TO_PDMA0_TR_IN20 = 0x40001004u, /* From scb[2].tr_tx_req to cpuss.dw0_tr_in[20] */ + TRIG_OUT_1TO1_0_SCB2_RX_TO_PDMA0_TR_IN21 = 0x40001005u, /* From scb[2].tr_rx_req to cpuss.dw0_tr_in[21] */ + TRIG_OUT_1TO1_0_DUMMY_TO_PDMA0_TR_IN22 = 0x40001006u, /* From cpuss.zero to cpuss.dw0_tr_in[22] */ + TRIG_OUT_1TO1_0_DUMMY_TO_PDMA0_TR_IN23 = 0x40001007u, /* From cpuss.zero to cpuss.dw0_tr_in[23] */ + TRIG_OUT_1TO1_0_SCB4_TX_TO_PDMA0_TR_IN24 = 0x40001008u, /* From scb[4].tr_tx_req to cpuss.dw0_tr_in[24] */ + TRIG_OUT_1TO1_0_SCB4_RX_TO_PDMA0_TR_IN25 = 0x40001009u, /* From scb[4].tr_rx_req to cpuss.dw0_tr_in[25] */ + TRIG_OUT_1TO1_0_SCB5_TX_TO_PDMA0_TR_IN26 = 0x4000100Au, /* From scb[5].tr_tx_req to cpuss.dw0_tr_in[26] */ + TRIG_OUT_1TO1_0_SCB5_RX_TO_PDMA0_TR_IN27 = 0x4000100Bu /* From scb[5].tr_rx_req to cpuss.dw0_tr_in[27] */ +} en_trig_output_1to1_scb_pdma0_tr_t; + +/* Trigger Output Group 1 - SCB PDMA1 Triggers (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_1_SCB6_TX_TO_PDMA1_TR_IN8 = 0x40001100u, /* From scb[6].tr_tx_req to cpuss.dw1_tr_in[8] */ + TRIG_OUT_1TO1_1_SCB6_RX_TO_PDMA1_TR_IN9 = 0x40001101u, /* From scb[6].tr_rx_req to cpuss.dw1_tr_in[9] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN10 = 0x40001102u, /* From cpuss.zero to cpuss.dw1_tr_in[10] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN11 = 0x40001103u, /* From cpuss.zero to cpuss.dw1_tr_in[11] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN12 = 0x40001104u, /* From cpuss.zero to cpuss.dw1_tr_in[12] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN13 = 0x40001105u, /* From cpuss.zero to cpuss.dw1_tr_in[13] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN14 = 0x40001106u, /* From cpuss.zero to cpuss.dw1_tr_in[14] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN15 = 0x40001107u, /* From cpuss.zero to cpuss.dw1_tr_in[15] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN16 = 0x40001108u, /* From cpuss.zero to cpuss.dw1_tr_in[16] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN17 = 0x40001109u, /* From cpuss.zero to cpuss.dw1_tr_in[17] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN18 = 0x4000110Au, /* From cpuss.zero to cpuss.dw1_tr_in[18] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN19 = 0x4000110Bu, /* From cpuss.zero to cpuss.dw1_tr_in[19] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN20 = 0x4000110Cu, /* From cpuss.zero to cpuss.dw1_tr_in[20] */ + TRIG1_OUT_1TO1_CPUSS_DW1_TR_IN21 = 0x4000110Du /* From cpuss.zero to cpuss.dw1_tr_in[21] */ +} en_trig_output_1to1_scb_pdma1_tr_t; + +/* Trigger Output Group 2 - PASS to PDMA0 direct connect (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_2_PASS_SAR0_DONE_TO_PDMA0_TR_IN28 = 0x40001200u /* From pass.tr_sar_out[0] to cpuss.dw0_tr_in[28] */ +} en_trig_output_1to1_sar0_to_pdma1_t; + +/* Trigger Output Group 3 - (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_3_SMIF_TX_TO_PDMA1_TR_IN22 = 0x40001300u, /* From smif.tr_tx_req to cpuss.dw1_tr_in[22] */ + TRIG_OUT_1TO1_3_SMIF_RX_TO_PDMA1_TR_IN23 = 0x40001301u, /* From smif.tr_rx_req to cpuss.dw1_tr_in[23] */ + TRIG3_OUT_1TO1_CPUSS_DW1_TR_IN24 = 0x40001302u, /* From cpuss.zero to cpuss.dw1_tr_in[24] */ + TRIG3_OUT_1TO1_CPUSS_DW1_TR_IN25 = 0x40001303u, /* From cpuss.zero to cpuss.dw1_tr_in[25] */ + TRIG3_OUT_1TO1_CPUSS_DW1_TR_IN26 = 0x40001304u, /* From cpuss.zero to cpuss.dw1_tr_in[26] */ + TRIG3_OUT_1TO1_CPUSS_DW1_TR_IN27 = 0x40001305u, /* From cpuss.zero to cpuss.dw1_tr_in[27] */ + TRIG3_OUT_1TO1_CPUSS_DW1_TR_IN28 = 0x40001306u /* From cpuss.zero to cpuss.dw1_tr_in[28] */ +} en_trig_output_1to1_smif_to_pdma1_t; + +/* Trigger Output Group 4 - CAN DW triggers (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_4_CAN_DBG_TO_PDMA1_TR_IN29 = 0x40001400u, /* From canfd[0].tr_dbg_dma_req[0] to cpuss.dw1_tr_in[29] */ + TRIG_OUT_1TO1_4_CAN_FIFO0_TO_PDMA1_TR_IN30 = 0x40001401u, /* From canfd[0].tr_fifo0[0] to cpuss.dw1_tr_in[30] */ + TRIG_OUT_1TO1_4_CAN_FIFO1_TO_PDMA1_TR_IN31 = 0x40001402u /* From canfd[0].tr_fifo1[0] to cpuss.dw1_tr_in[31] */ +} en_trig_output_1to1_can_dw_tr_t; + +/* Trigger Output Group 5 - USB PDMA0 Triggers (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_5_USB_DMA0_TO_PDMA0_TR_IN8 = 0x40001500u, /* From usb.dma_req[0] to cpuss.dw0_tr_in[8] */ + TRIG_OUT_1TO1_5_USB_DMA1_TO_PDMA0_TR_IN9 = 0x40001501u, /* From usb.dma_req[1] to cpuss.dw0_tr_in[9] */ + TRIG_OUT_1TO1_5_USB_DMA2_TO_PDMA0_TR_IN10 = 0x40001502u, /* From usb.dma_req[2] to cpuss.dw0_tr_in[10] */ + TRIG_OUT_1TO1_5_USB_DMA3_TO_PDMA0_TR_IN11 = 0x40001503u, /* From usb.dma_req[3] to cpuss.dw0_tr_in[11] */ + TRIG_OUT_1TO1_5_USB_DMA4_TO_PDMA0_TR_IN12 = 0x40001504u, /* From usb.dma_req[4] to cpuss.dw0_tr_in[12] */ + TRIG_OUT_1TO1_5_USB_DMA5_TO_PDMA0_TR_IN13 = 0x40001505u, /* From usb.dma_req[5] to cpuss.dw0_tr_in[13] */ + TRIG_OUT_1TO1_5_USB_DMA6_TO_PDMA0_TR_IN14 = 0x40001506u, /* From usb.dma_req[6] to cpuss.dw0_tr_in[14] */ + TRIG_OUT_1TO1_5_USB_DMA7_TO_PDMA0_TR_IN15 = 0x40001507u /* From usb.dma_req[7] to cpuss.dw0_tr_in[15] */ +} en_trig_output_1to1_usb_pdma0_tr_t; + +/* Trigger Output Group 6 - USB PDMA0 Acknowledge Triggers (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT8_TO_USB_ACK0 = 0x40001600u, /* From cpuss.dw0_tr_out[8] to usb.dma_burstend[0] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT9_TO_USB_ACK1 = 0x40001601u, /* From cpuss.dw0_tr_out[9] to usb.dma_burstend[1] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT10_TO_USB_ACK2 = 0x40001602u, /* From cpuss.dw0_tr_out[10] to usb.dma_burstend[2] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT11_TO_USB_ACK3 = 0x40001603u, /* From cpuss.dw0_tr_out[11] to usb.dma_burstend[3] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT12_TO_USB_ACK4 = 0x40001604u, /* From cpuss.dw0_tr_out[12] to usb.dma_burstend[4] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT13_TO_USB_ACK5 = 0x40001605u, /* From cpuss.dw0_tr_out[13] to usb.dma_burstend[5] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT14_TO_USB_ACK6 = 0x40001606u, /* From cpuss.dw0_tr_out[14] to usb.dma_burstend[6] */ + TRIG_OUT_1TO1_6_PDMA0_TR_OUT15_TO_USB_ACK7 = 0x40001607u /* From cpuss.dw0_tr_out[15] to usb.dma_burstend[7] */ +} en_trig_output_1to1_usb_pdma0_ack_tr_t; + +/* Trigger Output Group 7 - Acknowledge dma request triggers from DW0 to CAN (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_7_PDMA1_TR_OUT29_ACK_TO_CAN_0 = 0x40001700u /* From cpuss.dw1_tr_out[29] to canfd[0].tr_dbg_dma_ack[0] */ +} en_trig_output_1to1_can0_dw_ack_t; + +/* Trigger Output Group 8 - PASS SAR1 to PDMA0 direct connect (OneToOne) */ +typedef enum +{ + TRIG_OUT_1TO1_8_PASS_SAR1_DONE_TO_PDMA0_TR_IN29 = 0x40001800u /* From pass.tr_sar_out[1] to cpuss.dw0_tr_in[29] */ +} en_trig_output_1to1_sar1_to_pdma1_t; + +/* Level or edge detection setting for a trigger mux */ +typedef enum +{ + /* The trigger is a simple level output */ + TRIGGER_TYPE_LEVEL = 0u, + /* The trigger is synchronized to the consumer blocks clock + and a two cycle pulse is generated on this clock */ + TRIGGER_TYPE_EDGE = 1u +} en_trig_type_t; + +/* Trigger Type Defines */ +/* CANFD Trigger Types */ +#define TRIGGER_TYPE_CANFD_TR_DBG_DMA_ACK TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CANFD_TR_DBG_DMA_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CANFD_TR_EVT_SWT_IN TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CANFD_TR_FIFO0 TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CANFD_TR_FIFO1 TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CANFD_TR_TMP_RTP_OUT TRIGGER_TYPE_EDGE +/* CPUSS Trigger Types */ +#define TRIGGER_TYPE_CPUSS_CTI_TR_IN TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_CTI_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CPUSS_DMAC_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DMAC_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CPUSS_DW0_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW0_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_CPUSS_DW1_TR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_DW1_TR_OUT TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_CPUSS_TR_FAULT TRIGGER_TYPE_EDGE +/* CSD Trigger Types */ +#define TRIGGER_TYPE_CSD_DSI_SAMPLE_OUT TRIGGER_TYPE_EDGE +/* LPCOMP Trigger Types */ +#define TRIGGER_TYPE_LPCOMP_DSI_COMP0 TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_LPCOMP_DSI_COMP1 TRIGGER_TYPE_LEVEL +/* PASS Trigger Types */ +#define TRIGGER_TYPE_PASS_DSI_CTB_CMP0__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PASS_DSI_CTB_CMP0__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PASS_DSI_CTB_CMP1__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PASS_DSI_CTB_CMP1__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PASS_TR_CTDAC_EMPTY TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PASS_TR_SAR_IN__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PASS_TR_SAR_IN__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PASS_TR_SAR_OUT TRIGGER_TYPE_EDGE +/* PERI Trigger Types */ +#define TRIGGER_TYPE_PERI_TR_DBG_FREEZE TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PERI_TR_IO_INPUT__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PERI_TR_IO_INPUT__EDGE TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__LEVEL TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_PERI_TR_IO_OUTPUT__EDGE TRIGGER_TYPE_EDGE +/* SCB Trigger Types */ +#define TRIGGER_TYPE_SCB_TR_I2C_SCL_FILTERED TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SCB_TR_RX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SCB_TR_TX_REQ TRIGGER_TYPE_LEVEL +/* SMIF Trigger Types */ +#define TRIGGER_TYPE_SMIF_TR_RX_REQ TRIGGER_TYPE_LEVEL +#define TRIGGER_TYPE_SMIF_TR_TX_REQ TRIGGER_TYPE_LEVEL +/* TCPWM Trigger Types */ +#define TRIGGER_TYPE_TCPWM_TR_DEBUG_FREEZE TRIGGER_TYPE_LEVEL +/* USB Trigger Types */ +#define TRIGGER_TYPE_USB_DMA_BURSTEND TRIGGER_TYPE_EDGE +#define TRIGGER_TYPE_USB_DMA_REQ TRIGGER_TYPE_EDGE + +/* Bus masters */ +typedef enum +{ + CPUSS_MS_ID_CM0 = 0, + CPUSS_MS_ID_CRYPTO = 1, + CPUSS_MS_ID_DW0 = 2, + CPUSS_MS_ID_DW1 = 3, + CPUSS_MS_ID_DMAC = 4, + CPUSS_MS_ID_SLOW0 = 5, + CPUSS_MS_ID_SLOW1 = 6, + CPUSS_MS_ID_CM4 = 14, + CPUSS_MS_ID_TC = 15 +} en_prot_master_t; + +/* Pointer to device configuration structure */ +#define CY_DEVICE_CFG (&cy_deviceIpBlockCfgPSoC6_04) + +/* Include IP definitions */ +#include "ip/cyip_sflash.h" +#include "ip/cyip_peri_v2.h" +#include "ip/cyip_peri_ms_v2.h" +#include "ip/cyip_crypto_v2.h" +#include "ip/cyip_cpuss_v2.h" +#include "ip/cyip_fault_v2.h" +#include "ip/cyip_ipc_v2.h" +#include "ip/cyip_prot_v2.h" +#include "ip/cyip_flashc_v2.h" +#include "ip/cyip_srss.h" +#include "ip/cyip_backup.h" +#include "ip/cyip_dw_v2.h" +#include "ip/cyip_dmac_v2.h" +#include "ip/cyip_efuse.h" +#include "ip/cyip_efuse_data_psoc6_04.h" +#include "ip/cyip_hsiom_v2.h" +#include "ip/cyip_gpio_v2.h" +#include "ip/cyip_smartio_v2.h" +#include "ip/cyip_lpcomp.h" +#include "ip/cyip_csd.h" +#include "ip/cyip_tcpwm_v2.h" +#include "ip/cyip_lcd_v2.h" +#include "ip/cyip_usbfs.h" +#include "ip/cyip_smif.h" +#include "ip/cyip_canfd.h" +#include "ip/cyip_scb.h" +#include "ip/cyip_scb.h" +#include "ip/cyip_ctbm_v2.h" +#include "ip/cyip_ctdac.h" +#include "ip/cyip_sar_v2.h" +#include "ip/cyip_pass_v2.h" + +/* IP type definitions */ +typedef SFLASH_V1_Type SFLASH_Type; +typedef PERI_GR_V2_Type PERI_GR_Type; +typedef PERI_TR_GR_V2_Type PERI_TR_GR_Type; +typedef PERI_TR_1TO1_GR_V2_Type PERI_TR_1TO1_GR_Type; +typedef PERI_V2_Type PERI_Type; +typedef PERI_MS_PPU_PR_V2_Type PERI_MS_PPU_PR_Type; +typedef PERI_MS_PPU_FX_V2_Type PERI_MS_PPU_FX_Type; +typedef PERI_MS_V2_Type PERI_MS_Type; +typedef CRYPTO_V2_Type CRYPTO_Type; +typedef CPUSS_V2_Type CPUSS_Type; +typedef FAULT_STRUCT_V2_Type FAULT_STRUCT_Type; +typedef FAULT_V2_Type FAULT_Type; +typedef IPC_STRUCT_V2_Type IPC_STRUCT_Type; +typedef IPC_INTR_STRUCT_V2_Type IPC_INTR_STRUCT_Type; +typedef IPC_V2_Type IPC_Type; +typedef PROT_SMPU_SMPU_STRUCT_V2_Type PROT_SMPU_SMPU_STRUCT_Type; +typedef PROT_SMPU_V2_Type PROT_SMPU_Type; +typedef PROT_MPU_MPU_STRUCT_V2_Type PROT_MPU_MPU_STRUCT_Type; +typedef PROT_MPU_V2_Type PROT_MPU_Type; +typedef PROT_V2_Type PROT_Type; +typedef FLASHC_FM_CTL_V2_Type FLASHC_FM_CTL_Type; +typedef FLASHC_V2_Type FLASHC_Type; +typedef MCWDT_STRUCT_V1_Type MCWDT_STRUCT_Type; +typedef SRSS_V1_Type SRSS_Type; +typedef BACKUP_V1_Type BACKUP_Type; +typedef DW_CH_STRUCT_V2_Type DW_CH_STRUCT_Type; +typedef DW_V2_Type DW_Type; +typedef DMAC_CH_V2_Type DMAC_CH_Type; +typedef DMAC_V2_Type DMAC_Type; +typedef EFUSE_V1_Type EFUSE_Type; +typedef HSIOM_PRT_V2_Type HSIOM_PRT_Type; +typedef HSIOM_V2_Type HSIOM_Type; +typedef GPIO_PRT_V2_Type GPIO_PRT_Type; +typedef GPIO_V2_Type GPIO_Type; +typedef SMARTIO_PRT_V2_Type SMARTIO_PRT_Type; +typedef SMARTIO_V2_Type SMARTIO_Type; +typedef LPCOMP_V1_Type LPCOMP_Type; +typedef CSD_V1_Type CSD_Type; +typedef TCPWM_GRP_CNT_V2_Type TCPWM_GRP_CNT_Type; +typedef TCPWM_GRP_V2_Type TCPWM_GRP_Type; +typedef TCPWM_V2_Type TCPWM_Type; +typedef LCD_V2_Type LCD_Type; +typedef USBFS_USBDEV_V1_Type USBFS_USBDEV_Type; +typedef USBFS_USBLPM_V1_Type USBFS_USBLPM_Type; +typedef USBFS_USBHOST_V1_Type USBFS_USBHOST_Type; +typedef USBFS_V1_Type USBFS_Type; +typedef SMIF_DEVICE_V1_Type SMIF_DEVICE_Type; +typedef SMIF_V1_Type SMIF_Type; +typedef CANFD_CH_M_TTCAN_V1_Type CANFD_CH_M_TTCAN_Type; +typedef CANFD_CH_V1_Type CANFD_CH_Type; +typedef CANFD_V1_Type CANFD_Type; +typedef CySCB_V1_Type CySCB_Type; +typedef CTBM_V2_Type CTBM_Type; +typedef CTDAC_V1_Type CTDAC_Type; +typedef SAR_V2_Type SAR_Type; +typedef PASS_TIMER_V2_Type PASS_TIMER_Type; +typedef PASS_LPOSC_V2_Type PASS_LPOSC_Type; +typedef PASS_FIFO_V2_Type PASS_FIFO_Type; +typedef PASS_AREFV2_V2_Type PASS_AREFV2_Type; +typedef PASS_V2_Type PASS_Type; + +/* Parameter Defines */ +/* Number of TTCAN instances */ +#define CANFD_CAN_NR 1u +/* ECC logic present or not */ +#define CANFD_ECC_PRESENT 0u +/* address included in ECC logic or not */ +#define CANFD_ECC_ADDR_PRESENT 0u +/* Time Stamp counter present or not (required for instance 0, otherwise not + allowed) */ +#define CANFD_TS_PRESENT 1u +/* Message RAM size in KB */ +#define CANFD_MRAM_SIZE 4u +/* Message RAM address width */ +#define CANFD_MRAM_ADDR_WIDTH 10u +/* UDB present or not ('0': no, '1': yes) */ +#define CPUSS_UDB_PRESENT 0u +/* MBIST MMIO for Synopsys MBIST ('0': no, '1': yes). Set this to '1' only for the + chips which doesn't use mxdft. */ +#define CPUSS_MBIST_MMIO_PRESENT 1u +/* System RAM 0 size in kilobytes */ +#define CPUSS_SRAM0_SIZE 128u +/* Number of macros used to implement System RAM 0. Example: 8 if 256 KB System + SRAM0 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC0_MACRO_NR 4u +/* System RAM 1 present or not (0=No, 1=Yes) */ +#define CPUSS_RAMC1_PRESENT 0u +/* System RAM 1 size in kilobytes */ +#define CPUSS_SRAM1_SIZE 1u +/* Number of macros used to implement System RAM 1. Example: 8 if 256 KB System + RAM 1 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC1_MACRO_NR 1u +/* System RAM 2 present or not (0=No, 1=Yes) */ +#define CPUSS_RAMC2_PRESENT 0u +/* System RAM 2 size in kilobytes */ +#define CPUSS_SRAM2_SIZE 1u +/* Number of macros used to implement System RAM 2. Example: 8 if 256 KB System + RAM 2 is implemented with 8 32KB macros. */ +#define CPUSS_RAMC2_MACRO_NR 1u +/* System SRAM(s) ECC present or not ('0': no, '1': yes) */ +#define CPUSS_RAMC_ECC_PRESENT 0u +/* System SRAM(s) address ECC present or not ('0': no, '1': yes) */ +#define CPUSS_RAMC_ECC_ADDR_PRESENT 0u +/* ECC present in either system RAM or interrupt handler (RAMC_ECC_PRESENT) */ +#define CPUSS_ECC_PRESENT 0u +/* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ +#define CPUSS_DW_ECC_PRESENT 0u +/* DataWire SRAMs address ECC present or not ('0': no, '1': yes) */ +#define CPUSS_DW_ECC_ADDR_PRESENT 0u +/* System ROM size in KB */ +#define CPUSS_ROM_SIZE 64u +/* Number of macros used to implement system ROM. Example: 4 if 512 KB system ROM + is implemented with 4 128KB macros. */ +#define CPUSS_ROMC_MACRO_NR 1u +/* Flash memory present or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_PRESENT 1u +/* Flash memory type ('0' : SONOS, '1': ECT) */ +#define CPUSS_FLASHC_ECT 0u +/* Flash main region size in KB */ +#define CPUSS_FLASH_SIZE 256u +/* Flash work region size in KB (EEPROM emulation, data) */ +#define CPUSS_WFLASH_SIZE 0u +/* Flash supervisory region size in KB */ +#define CPUSS_SFLASH_SIZE 32u +/* Flash data output word size (in Bytes) */ +#define CPUSS_FLASHC_MAIN_DATA_WIDTH 16u +/* SONOS Flash RWW present or not ('0': no, '1': yes) When RWW is '0', No special + sectors present in Flash. Part of main sector 0 is allowcated for Supervisory + Flash, and no Work Flash present. */ +#define CPUSS_FLASHC_SONOS_RWW 1u +/* SONOS Flash, number of main sectors. */ +#define CPUSS_FLASHC_SONOS_MAIN_SECTORS 2u +/* SONOS Flash, number of rows per main sector. */ +#define CPUSS_FLASHC_SONOS_MAIN_ROWS 256u +/* SONOS Flash, number of words per row of main sector. */ +#define CPUSS_FLASHC_SONOS_MAIN_WORDS 128u +/* SONOS Flash, number of special sectors. */ +#define CPUSS_FLASHC_SONOS_SPL_SECTORS 1u +/* SONOS Flash, number of rows per special sector. */ +#define CPUSS_FLASHC_SONOS_SPL_ROWS 64u +/* Flash memory ECC present or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_FLASH_ECC_PRESENT 0u +/* Flash cache SRAM(s) ECC present or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_RAM_ECC_PRESENT 0u +/* Number of external slaves directly connected to slow AHB-Lite infrastructure. + Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. + 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave + 0 and slave 1 are present. Note: The SLOW_SLx_ADDR and SLOW_SLx_MASK + parameters (for the slaves present) should be derived from the Memory Map. */ +#define CPUSS_SLOW_SL_PRESENT 1u +/* Number of external slaves directly connected to fast AHB-Lite infrastructure. + Maximum nubmer of slave supported is 4. Width of this parameter is 4-bits. + 1-bit mask for each slave indicating present or not. Example: 4'b0011 - slave + 0 and slave 1 are present. Note: The FAST_SLx_ADDR and FAST_SLx_MASK + parameters (for the slaves present) should be derived from the Memory Map. */ +#define CPUSS_FAST_SL_PRESENT 1u +/* Number of external masters driving the slow AHB-Lite infrastructure. Maximum + number of masters supported is 2. Width of this parameter is 2-bits. 1-bit + mask for each master indicating present or not. Example: 2'b01 - master 0 is + present. */ +#define CPUSS_SLOW_MS_PRESENT 0u +/* System interrupt functionality present or not ('0': no; '1': yes). Not used for + CM0+ PCU, which always uses system interrupt functionality. */ +#define CPUSS_SYSTEM_IRQ_PRESENT 0u +/* Number of total interrupt request inputs to CPUSS */ +#define CPUSS_SYSTEM_INT_NR 175u +/* Number of DeepSleep wakeup interrupt inputs to CPUSS */ +#define CPUSS_SYSTEM_DPSLP_INT_NR 45u +/* CM4 CPU present or not ('0': no, '1': yes) */ +#define CPUSS_CM4_PRESENT 1u +/* Width of the CM4 interrupt priority bits. Legal range [3,8] Example: 3 = 8 + levels of priority 8 = 256 levels of priority */ +#define CPUSS_CM4_LVL_WIDTH 3u +/* CM4 Floating point unit present or not (0=No, 1=Yes) */ +#define CPUSS_CM4_FPU_PRESENT 1u +/* Debug level. Legal range [0,3] (0= No support, 1= Minimum: CM0/4 both 2 + breakpoints +1 watchpoint, 2= Full debug: CM0/4 have 4/6 breakpoints, 2/4 + watchpoints and 0/2 literal compare, 3= Full debug + data matching) */ +#define CPUSS_DEBUG_LVL 3u +/* Trace level. Legal range [0,2] (0= No tracing, 1= ITM + TPIU + SWO, 2= ITM + + ETM + TPIU + SWO) Note: CM4 HTM is not supported. Hence vaule 3 for trace + level is not supported in CPUSS. */ +#define CPUSS_TRACE_LVL 2u +/* Embedded Trace Buffer present or not (0=No, 1=Yes) */ +#define CPUSS_ETB_PRESENT 0u +/* CM0+ MTB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ +#define CPUSS_MTB_SRAM_SIZE 4u +/* CM4 ETB SRAM buffer size in kilobytes. Legal vaules 4, 8 or 16 */ +#define CPUSS_ETB_SRAM_SIZE 8u +/* PTM interface present (0=No, 1=Yes) */ +#define CPUSS_PTM_PRESENT 0u +/* Width of the PTM interface in bits ([2,32]) */ +#define CPUSS_PTM_WIDTH 1u +/* Width of the TPIU interface in bits ([1,4]) */ +#define CPUSS_TPIU_WIDTH 4u +/* CoreSight Part Identification Number */ +#define CPUSS_JEPID 52u +/* CoreSight Part Identification Number */ +#define CPUSS_JEPCONTINUATION 0u +/* CoreSight Part Identification Number */ +#define CPUSS_FAMILYID 270u +/* ROM trim register width (for ARM 3, for Synopsys 5) */ +#define CPUSS_ROM_TRIM_WIDTH 5u +/* ROM trim register default (for both ARM and Synopsys 0x0000_0012) */ +#define CPUSS_ROM_TRIM_DEFAULT 18u +/* RAM trim register width (for ARM 8, for Synopsys 15) */ +#define CPUSS_RAM_TRIM_WIDTH 15u +/* RAM trim register default (for ARM 0x0000_0062 and for Synopsys 0x0000_6012) */ +#define CPUSS_RAM_TRIM_DEFAULT 24594u +/* Cryptography IP present or not (0=No, 1=Yes) */ +#define CPUSS_CRYPTO_PRESENT 1u +/* DataWire and DMAC SW trigger per channel present or not ('0': no, '1': yes) */ +#define CPUSS_SW_TR_PRESENT 0u +/* DataWire 0 present or not (0=No, 1=Yes) */ +#define CPUSS_DW0_PRESENT 1u +/* Number of DataWire 0 channels (8, 16 or 32) */ +#define CPUSS_DW0_CH_NR 30u +/* DataWire 1 present or not (0=No, 1=Yes) */ +#define CPUSS_DW1_PRESENT 1u +/* Number of DataWire 1 channels (8, 16 or 32) */ +#define CPUSS_DW1_CH_NR 32u +/* DMA controller present or not ('0': no, '1': yes) */ +#define CPUSS_DMAC_PRESENT 1u +/* Number of DMA controller channels ([1, 8]) */ +#define CPUSS_DMAC_CH_NR 2u +/* DMAC SW trigger per channel present or not ('0': no, '1': yes) */ +#define CPUSS_CH_SW_TR_PRESENT 0u +/* Copy value from Globals */ +#define CPUSS_CHIP_TOP_PROFILER_PRESENT 0u +/* ETAS Calibration support pin out present (automotive only) */ +#define CPUSS_CHIP_TOP_CAL_SUP_NZ_PRESENT 0u +/* TRACE_LVL>0 */ +#define CPUSS_CHIP_TOP_TRACE_PRESENT 1u +/* DataWire SW trigger per channel present or not ('0': no, '1': yes) */ +#define CPUSS_CH_STRUCT_SW_TR_PRESENT 0u +/* Number of DataWire controllers present (max 2) (same as DW.NR above) */ +#define CPUSS_CPUSS_DW_DW_NR 2u +/* Number of channels in each DataWire controller */ +#define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR 30u +/* Width of a channel number in bits */ +#define CPUSS_CPUSS_DW_DW_NR0_DW_CH_NR_WIDTH 5u +/* Number of channels in each DataWire controller */ +#define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR 32u +/* Width of a channel number in bits */ +#define CPUSS_CPUSS_DW_DW_NR1_DW_CH_NR_WIDTH 5u +/* Cryptography SRAMs ECC present or not ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_ECC_PRESENT 0u +/* Cryptography SRAMs address ECC present or not ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_ECC_ADDR_PRESENT 0u +/* AES cipher support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_AES 1u +/* (Tripple) DES cipher support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_DES 1u +/* Chacha support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_CHACHA 1u +/* Pseudo random number generation support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_PR 1u +/* SHA1 hash support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_SHA1 1u +/* SHA2 hash support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_SHA2 1u +/* SHA3 hash support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_SHA3 1u +/* Cyclic Redundancy Check support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_CRC 1u +/* True random number generation support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_TR 1u +/* Vector unit support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_VU 1u +/* Galios/Counter Mode (GCM) support ('0': no, '1': yes) */ +#define CPUSS_CRYPTO_GCM 1u +/* Number of 32-bit words in the IP internal memory buffer (from the set [64, 128, + 256, 512, 1024, 2048, 4096], to allow for a 256 B, 512 B, 1 kB, 2 kB, 4 kB, 8 + kB and 16 kB memory buffer) */ +#define CPUSS_CRYPTO_BUFF_SIZE 1024u +/* Number of DMA controller channels ([1, 8]) */ +#define CPUSS_DMAC_CH_NR 2u +/* Number of DataWire controllers present (max 2) */ +#define CPUSS_DW_NR 2u +/* DataWire SRAMs ECC present or not ('0': no, '1': yes) */ +#define CPUSS_DW_ECC_PRESENT 0u +/* Number of fault structures. Legal range [1, 4] */ +#define CPUSS_FAULT_FAULT_NR 2u +/* Number of Flash BIST_DATA registers */ +#define CPUSS_FLASHC_FLASHC_BIST_DATA_NR 4u +/* Page size in # of 32-bit words (1: 4 bytes, 2: 8 bytes, ... */ +#define CPUSS_FLASHC_PA_SIZE 128u +/* SONOS Flash is used or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_FLASHC_IS_SONOS 1u +/* eCT Flash is used or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_FLASHC_IS_ECT 0u +/* CM4 CPU present or not ('0': no, '1': yes) */ +#define CPUSS_FLASHC_CM4_PRESENT 1u +/* Number of IPC structures. Legal range [1, 16] */ +#define CPUSS_IPC_IPC_NR 16u +/* Number of IPC interrupt structures. Legal range [1, 16] */ +#define CPUSS_IPC_IPC_IRQ_NR 16u +/* Master 0 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS0_PC_NR_MINUS1 7u +/* Master 1 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS1_PC_NR_MINUS1 0u +/* Master 2 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS2_PC_NR_MINUS1 0u +/* Master 3 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS3_PC_NR_MINUS1 0u +/* Master 4 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS4_PC_NR_MINUS1 0u +/* Master 5 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS5_PC_NR_MINUS1 0u +/* Master 6 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS6_PC_NR_MINUS1 0u +/* Master 7 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS7_PC_NR_MINUS1 0u +/* Master 8 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS8_PC_NR_MINUS1 0u +/* Master 9 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS9_PC_NR_MINUS1 0u +/* Master 10 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS10_PC_NR_MINUS1 0u +/* Master 11 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS11_PC_NR_MINUS1 0u +/* Master 12 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS12_PC_NR_MINUS1 0u +/* Master 13 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS13_PC_NR_MINUS1 0u +/* Master 14 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS14_PC_NR_MINUS1 7u +/* Master 15 protect contexts minus one */ +#define CPUSS_PROT_SMPU_MS15_PC_NR_MINUS1 7u +/* Number of SMPU protection structures */ +#define CPUSS_PROT_SMPU_STRUCT_NR 16u +/* Number of protection contexts supported minus 1. Legal range [1,16] */ +#define CPUSS_SMPU_STRUCT_PC_NR_MINUS1 7u +/* Number of instantiated eFUSE macros (256 bit macros). Legal range [1, 16] */ +#define EFUSE_EFUSE_NR 4u +/* Number of GPIO ports in range 0..31 */ +#define IOSS_GPIO_GPIO_PORT_NR_0_31 15u +/* Number of GPIO ports in range 32..63 */ +#define IOSS_GPIO_GPIO_PORT_NR_32_63 0u +/* Number of GPIO ports in range 64..95 */ +#define IOSS_GPIO_GPIO_PORT_NR_64_95 0u +/* Number of GPIO ports in range 96..127 */ +#define IOSS_GPIO_GPIO_PORT_NR_96_127 0u +/* Number of ports in device */ +#define IOSS_GPIO_GPIO_PORT_NR 15u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO3 1u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO4 1u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO5 1u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR0_GPIO_PRT_SLOW_IO7 0u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR1_GPIO_PRT_SLOW_IO7 0u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO3 1u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO4 1u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO5 1u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO6 1u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR2_GPIO_PRT_SLOW_IO7 1u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO2 0u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR3_GPIO_PRT_SLOW_IO7 0u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_GPIO 0u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO0 0u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO1 0u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO2 0u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR4_GPIO_PRT_SLOW_IO7 0u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO6 1u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR5_GPIO_PRT_SLOW_IO7 1u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO0 0u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO1 0u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO3 1u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO4 1u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO5 1u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO6 1u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR6_GPIO_PRT_SLOW_IO7 1u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO3 1u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO4 1u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO5 1u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR7_GPIO_PRT_SLOW_IO7 1u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO2 0u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR8_GPIO_PRT_SLOW_IO7 0u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO3 1u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO4 1u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO5 1u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR9_GPIO_PRT_SLOW_IO7 0u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO3 1u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO4 1u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO5 1u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO6 1u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR10_GPIO_PRT_SLOW_IO7 1u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO0 0u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO2 1u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO3 1u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO4 1u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO5 1u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO6 1u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR11_GPIO_PRT_SLOW_IO7 1u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_GPIO 1u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO0 0u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO1 0u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO2 0u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO6 1u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR12_GPIO_PRT_SLOW_IO7 1u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_GPIO 0u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO0 0u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO1 0u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO2 0u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR13_GPIO_PRT_SLOW_IO7 0u +/* Indicates port is either GPIO or SIO (i.e. all GPIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_GPIO 0u +/* Indicates port is an SIO port (i.e. both GPIO and SIO registers present) */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SIO 0u +/* Indicates port is a GPIO port including the "AUTO" input threshold */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_AUTOLVL 0u +/* Indicates that pin #0 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO0 1u +/* Indicates that pin #1 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO1 1u +/* Indicates that pin #2 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO2 0u +/* Indicates that pin #3 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO3 0u +/* Indicates that pin #4 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO4 0u +/* Indicates that pin #5 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO5 0u +/* Indicates that pin #6 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO6 0u +/* Indicates that pin #7 exists for this port with slew control feature */ +#define IOSS_GPIO_GPIO_PORT_NR14_GPIO_PRT_SLOW_IO7 0u +/* Number of AMUX splitter cells */ +#define IOSS_HSIOM_AMUX_SPLIT_NR 6u +/* Number of HSIOM ports in device (same as GPIO.GPIO_PRT_NR) */ +#define IOSS_HSIOM_HSIOM_PORT_NR 15u +/* Number of PWR/GND MONITOR CELLs in the device */ +#define IOSS_HSIOM_MONITOR_NR 0u +/* Number of PWR/GND MONITOR CELLs in range 0..31 */ +#define IOSS_HSIOM_MONITOR_NR_0_31 0u +/* Number of PWR/GND MONITOR CELLs in range 32..63 */ +#define IOSS_HSIOM_MONITOR_NR_32_63 0u +/* Number of PWR/GND MONITOR CELLs in range 64..95 */ +#define IOSS_HSIOM_MONITOR_NR_64_95 0u +/* Number of PWR/GND MONITOR CELLs in range 96..127 */ +#define IOSS_HSIOM_MONITOR_NR_96_127 0u +/* Indicates the presence of alternate JTAG interface */ +#define IOSS_HSIOM_ALTJTAG_PRESENT 0u +/* Mask of SMARTIO instances presence */ +#define IOSS_SMARTIO_SMARTIO_MASK 512u +/* Number of ports supoprting up to 4 COMs */ +#define LCD_NUMPORTS 8u +/* Number of ports supporting up to 8 COMs */ +#define LCD_NUMPORTS8 8u +/* Number of ports supporting up to 16 COMs */ +#define LCD_NUMPORTS16 0u +/* Max number of LCD commons supported */ +#define LCD_CHIP_TOP_COM_NR 8u +/* Max number of LCD pins (total) supported */ +#define LCD_CHIP_TOP_PIN_NR 60u +/* Number of CTBs in the Subsystem */ +#define PASS_NR_CTBS 1u +/* Number of CTDACs in the Subsystem */ +#define PASS_NR_CTDACS 1u +/* Number of SARs in the Subsystem */ +#define PASS_NR_SARS 2u +/* Number of IREF outputs from AREF */ +#define PASS_NR_IREFS 4u +/* CTB0 Exists */ +#define PASS_CTB0_EXISTS 1u +/* CTB1 Exists */ +#define PASS_CTB1_EXISTS 0u +/* CTB2 Exists */ +#define PASS_CTB2_EXISTS 0u +/* CTB3 Exists */ +#define PASS_CTB3_EXISTS 0u +/* CTDAC0 Exists */ +#define PASS_CTDAC0_EXISTS 1u +/* CTDAC1 Exists */ +#define PASS_CTDAC1_EXISTS 0u +/* CTDAC2 Exists */ +#define PASS_CTDAC2_EXISTS 0u +/* CTDAC3 Exists */ +#define PASS_CTDAC3_EXISTS 0u +/* SAR0 Exists */ +#define PASS_SAR0_EXISTS 1u +/* SAR1 Exists */ +#define PASS_SAR1_EXISTS 1u +/* SAR2 Exists */ +#define PASS_SAR2_EXISTS 0u +/* SAR3 Exists */ +#define PASS_SAR3_EXISTS 0u +/* NR_SARS*UDB_PRESENT */ +#define PASS_SAR_UDB_IF 0u +/* NR_CTBS*UDB_PRESENT */ +#define PASS_CTB_UDB_IF 0u +/* NR_CTDACS*UDB_PRESENT */ +#define PASS_CTDAC_UDB_IF 0u +#define PASS_CTBM_CTDAC_PRESENT 1u +#define PASS_CTBM_UDB_PRESENT 0u +/* Number of SAR channels */ +#define PASS_SAR_SAR_CHANNELS 16u +/* Averaging logic present in SAR */ +#define PASS_SAR_SAR_AVERAGE 1u +/* Range detect logic present in SAR */ +#define PASS_SAR_SAR_RANGEDET 1u +/* Support for UAB sampling */ +#define PASS_SAR_SAR_UAB 0u +#define PASS_SAR_CTB0_EXISTS 1u +#define PASS_SAR_UDB_PRESENT 0u +/* The number of protection contexts ([2, 16]). */ +#define PERI_PC_NR 8u +/* Master interface presence mask (4 bits) */ +#define PERI_MS_PRESENT 15u +/* Protection structures SRAM ECC present or not ('0': no, '1': yes) */ +#define PERI_ECC_PRESENT 0u +/* Protection structures SRAM address ECC present or not ('0': no, '1': yes) */ +#define PERI_ECC_ADDR_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL1_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT0_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT1_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_CLOCK_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL1_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL2_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL3_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL4_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL6_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL7_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL8_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL9_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL10_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL12_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT2_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL1_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL2_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL5_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL6_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL8_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL11_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT3_PERI_GROUP_STRUCT_SL15_PRESENT 1u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL2_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT4_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL2_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT5_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL1_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL2_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL4_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL5_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL6_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT6_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT7_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT8_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL0_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT9_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT10_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT11_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT12_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT13_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT14_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Clock control functionality present ('0': no, '1': yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_CLOCK_PRESENT 1u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL0_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL1_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL2_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL3_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL4_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL5_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL6_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL7_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL8_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL9_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL10_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL11_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL12_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL13_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL14_PRESENT 0u +/* Slave present (0:No, 1:Yes) */ +#define PERI_GROUP_PRESENT15_PERI_GROUP_STRUCT_SL15_PRESENT 0u +/* Number of programmable clocks (outputs) */ +#define PERI_CLOCK_NR 28u +/* Number of 8.0 dividers */ +#define PERI_DIV_8_NR 4u +/* Number of 16.0 dividers */ +#define PERI_DIV_16_NR 8u +/* Number of 16.5 (fractional) dividers */ +#define PERI_DIV_16_5_NR 2u +/* Number of 24.5 (fractional) dividers */ +#define PERI_DIV_24_5_NR 1u +/* Divider number width: max(1,roundup(log2(max(DIV_*_NR))) */ +#define PERI_DIV_ADDR_WIDTH 3u +/* Timeout functionality present ('0': no, '1': yes) */ +#define PERI_TIMEOUT_PRESENT 1u +/* Trigger module present (0=No, 1=Yes) */ +#define PERI_TR 1u +/* Number of trigger groups */ +#define PERI_TR_GROUP_NR 11u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR0_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR1_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR2_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR3_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR4_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR5_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR6_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR7_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR8_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR9_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_GROUP_NR10_TR_GROUP_TR_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR0_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR1_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR2_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR3_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR4_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR5_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR6_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR7_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Trigger 1-to-1 group trigger manipulation logic present ('0': no, '1': yes) */ +#define PERI_TR_1TO1_GROUP_NR8_TR_1TO1_GROUP_TR_1TO1_MANIPULATION_PRESENT 1u +/* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ +#define PERI_MASTER_WIDTH 8u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB0_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB0_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB0_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB0_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB0_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB0_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB0_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB0_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB0_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB0_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB0_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB0_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB0_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB0_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB0_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB0_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB0_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB0_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB0_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB0_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB0_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB0_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB0_I2C_FAST_PLUS 1u +/* Number of used spi_select signals (max 4) */ +#define SCB0_CHIP_TOP_SPI_SEL_NR 3u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB1_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB1_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB1_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB1_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB1_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB1_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB1_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB1_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB1_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB1_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB1_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB1_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB1_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB1_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB1_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB1_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB1_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB1_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB1_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB1_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB1_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB1_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB1_I2C_FAST_PLUS 1u +/* Number of used spi_select signals (max 4) */ +#define SCB1_CHIP_TOP_SPI_SEL_NR 4u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB2_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB2_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB2_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB2_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB2_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB2_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB2_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB2_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB2_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB2_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB2_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB2_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB2_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB2_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB2_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB2_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB2_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB2_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB2_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB2_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB2_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB2_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB2_I2C_FAST_PLUS 1u +/* Number of used spi_select signals (max 4) */ +#define SCB2_CHIP_TOP_SPI_SEL_NR 3u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB3_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB3_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB3_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB3_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB3_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB3_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB3_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB3_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB3_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB3_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB3_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB3_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB3_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB3_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB3_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB3_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB3_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB3_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB3_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB3_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB3_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB3_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB3_I2C_FAST_PLUS 1u +/* Number of used spi_select signals (max 4) */ +#define SCB3_CHIP_TOP_SPI_SEL_NR 3u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB4_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB4_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB4_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB4_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB4_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB4_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB4_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB4_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB4_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB4_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB4_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB4_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB4_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB4_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB4_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB4_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB4_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB4_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB4_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB4_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB4_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB4_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB4_I2C_FAST_PLUS 1u +/* Number of used spi_select signals (max 4) */ +#define SCB4_CHIP_TOP_SPI_SEL_NR 3u +/* DeepSleep support ('0':no, '1': yes) */ +#define SCB5_DEEPSLEEP 0u +/* Externally clocked support? ('0': no, '1': yes) */ +#define SCB5_EC 0u +/* I2C master support? ('0': no, '1': yes) */ +#define SCB5_I2C_M 1u +/* I2C slave support? ('0': no, '1': yes) */ +#define SCB5_I2C_S 1u +/* I2C support? (I2C_M | I2C_S) */ +#define SCB5_I2C 1u +/* I2C glitch filters present? ('0': no, '1': yes) */ +#define SCB5_I2C_GLITCH 1u +/* I2C externally clocked support? ('0': no, '1': yes) */ +#define SCB5_I2C_EC 0u +/* I2C master and slave support? (I2C_M & I2C_S) */ +#define SCB5_I2C_M_S 1u +/* I2C slave with EC? (I2C_S & I2C_EC) */ +#define SCB5_I2C_S_EC 0u +/* SPI master support? ('0': no, '1': yes) */ +#define SCB5_SPI_M 1u +/* SPI slave support? ('0': no, '1': yes) */ +#define SCB5_SPI_S 1u +/* SPI support? (SPI_M | SPI_S) */ +#define SCB5_SPI 1u +/* SPI externally clocked support? ('0': no, '1': yes) */ +#define SCB5_SPI_EC 0u +/* SPI slave with EC? (SPI_S & SPI_EC) */ +#define SCB5_SPI_S_EC 0u +/* UART support? ('0': no, '1': yes) */ +#define SCB5_UART 1u +/* SPI or UART (SPI | UART) */ +#define SCB5_SPI_UART 1u +/* Number of EZ memory Bytes ([32, 256, 512]). This memory is used in EZ mode, + CMD_RESP mode and FIFO mode. Note that in EZ mode, if EZ_DATA_NR is 512, only + 256 B are used. This is because the EZ mode uses 8-bit addresses. */ +#define SCB5_EZ_DATA_NR 256u +/* Command/response mode support? ('0': no, '1': yes) */ +#define SCB5_CMD_RESP 0u +/* EZ mode support? ('0': no, '1': yes) */ +#define SCB5_EZ 0u +/* Command/response mode or EZ mode support? (CMD_RESP | EZ) */ +#define SCB5_EZ_CMD_RESP 0u +/* I2C slave with EZ mode (I2C_S & EZ) */ +#define SCB5_I2C_S_EZ 0u +/* SPI slave with EZ mode (SPI_S & EZ) */ +#define SCB5_SPI_S_EZ 0u +/* Support I2C FM+/1Mbps speed ('0': no, '1': yes) */ +#define SCB5_I2C_FAST_PLUS 1u +/* Number of used spi_select signals (max 4) */ +#define SCB5_CHIP_TOP_SPI_SEL_NR 4u +/* SONOS Flash is used or not ('0': no, '1': yes) */ +#define SFLASH_FLASHC_IS_SONOS 1u +/* CPUSS_WOUNDING_PRESENT or not ('0': no, '1': yes) */ +#define SFLASH_CPUSS_WOUNDING_PRESENT 0u +/* Base address of the SMIF XIP memory region. This address must be a multiple of + the SMIF XIP memory capacity. This address must be a multiple of 64 KB. This + address must be in the [0x0000:0000, 0x1fff:ffff] memory region. The XIP + memory region should NOT overlap with other memory regions. */ +#define SMIF_SMIF_XIP_ADDR 402653184u +/* Capacity of the SMIF XIP memory region. The more significant bits of this + parameter must be '1' and the lesser significant bits of this paramter must + be '0'. E.g., 0xfff0:0000 specifies a 1 MB memory region. Legal values are + {0xffff:0000, 0xfffe:0000, 0xfffc:0000, 0xfff8:0000, 0xfff0:0000, + 0xffe0:0000, ..., 0xe000:0000}. */ +#define SMIF_SMIF_XIP_MASK 4160749568u +/* Cryptography (AES) support ('0' = no support, '1' = support) */ +#define SMIF_CRYPTO 1u +/* Number of external devices supported ([1,4]) */ +#define SMIF_DEVICE_NR 3u +/* External device write support. This is a 4-bit field. Each external device has + a dedicated bit. E.g., if bit 2 is '1', external device 2 has write support. */ +#define SMIF_DEVICE_WR_EN 15u +/* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ +#define SMIF_MASTER_WIDTH 8u +/* Chip top connect all 8 data pins (0= connect 4 or 6 data pins based on + DATA6_PRESENT, 1= connect 8 data pins) */ +#define SMIF_CHIP_TOP_DATA8_PRESENT 0u +/* Number of used spi_select signals (max 4) */ +#define SMIF_CHIP_TOP_SPI_SEL_NR 3u +/* Number of regulator modules instantiated within SRSS, start with estimate, + update after CMR feedback */ +#define SRSS_NUM_ACTREG_PWRMOD 2u +/* Number of shorting switches between vccd and vccact (target dynamic voltage + drop < 10mV) */ +#define SRSS_NUM_ACTIVE_SWITCH 3u +/* ULP linear regulator system is present */ +#define SRSS_ULPLINREG_PRESENT 1u +/* HT linear regulator system is present */ +#define SRSS_HTLINREG_PRESENT 0u +/* Low-current buck regulator present. Can be derived from S40S_SISOBUCKLC_PRESENT + or SIMOBUCK_PRESENT. */ +#define SRSS_BUCKCTL_PRESENT 1u +/* Low-current SISO buck core regulator is present. Only compatible with ULP + linear regulator system (ULPLINREG_PRESENT==1). */ +#define SRSS_S40S_SISOBUCKLC_PRESENT 1u +/* SIMO buck core regulator is present. Only compatible with ULP linear regulator + system (ULPLINREG_PRESENT==1). */ +#define SRSS_SIMOBUCK_PRESENT 0u +/* Precision ILO (PILO) is present */ +#define SRSS_PILO_PRESENT 0u +/* External Crystal Oscillator is present (high frequency) */ +#define SRSS_ECO_PRESENT 1u +/* System Buck-Boost is present */ +#define SRSS_SYSBB_PRESENT 0u +/* Number of clock paths. Must be > 0 */ +#define SRSS_NUM_CLKPATH 5u +/* Number of PLLs present. Must be <= NUM_CLKPATH */ +#define SRSS_NUM_PLL 1u +/* Number of HFCLK roots present. Must be > 0 */ +#define SRSS_NUM_HFROOT 4u +/* Number of PWR_HIB_DATA registers, should not be needed if BACKUP_PRESENT */ +#define SRSS_NUM_HIBDATA 1u +/* Backup domain is present (includes RTC and WCO) */ +#define SRSS_BACKUP_PRESENT 1u +/* Mask of HFCLK root clock supervisors (CSV). For each clock root i, bit[i] of + mask indicates presence of a CSV. */ +#define SRSS_MASK_HFCSV 0u +/* Clock supervisor is present on WCO. Must be 0 if BACKUP_PRESENT==0. */ +#define SRSS_WCOCSV_PRESENT 0u +/* Number of software watchdog timers. */ +#define SRSS_NUM_MCWDT 2u +/* Number of DSI inputs into clock muxes. This is used for logic optimization. */ +#define SRSS_NUM_DSI 0u +/* Alternate high-frequency clock is present. This is used for logic optimization. */ +#define SRSS_ALTHF_PRESENT 0u +/* Alternate low-frequency clock is present. This is used for logic optimization. */ +#define SRSS_ALTLF_PRESENT 0u +/* Use the hardened clkactfllmux block */ +#define SRSS_USE_HARD_CLKACTFLLMUX 1u +/* Number of clock paths, including direct paths in hardened clkactfllmux block + (Must be >= NUM_CLKPATH) */ +#define SRSS_HARD_CLKPATH 6u +/* Number of clock paths with muxes in hardened clkactfllmux block (Must be >= + NUM_PLL+1) */ +#define SRSS_HARD_CLKPATHMUX 6u +/* Number of HFCLKS present in hardened clkactfllmux block (Must be >= NUM_HFROOT) */ +#define SRSS_HARD_HFROOT 6u +/* ECO mux is present in hardened clkactfllmux block (Must be >= ECO_PRESENT) */ +#define SRSS_HARD_ECOMUX_PRESENT 1u +/* ALTHF mux is present in hardened clkactfllmux block (Must be >= ALTHF_PRESENT) */ +#define SRSS_HARD_ALTHFMUX_PRESENT 1u +/* SRSS version is at least SRSS_VER1P3. Set to 1 for new products. Set to 0 for + PSoC6ABLE2, PSoC6A2M. */ +#define SRSS_SRSS_VER1P3 1u +/* Backup memory is present (only used when BACKUP_PRESENT==1) */ +#define SRSS_BACKUP_BMEM_PRESENT 0u +/* Number of Backup registers to include (each is 32b). Only used when + BACKUP_PRESENT==1. */ +#define SRSS_BACKUP_NUM_BREG 16u +/* Number of input triggers per counter only routed to one counter (0..8) */ +#define TCPWM_TR_ONE_CNT_NR 1u +/* Number of input triggers routed to all counters (0..254), TR_ONE_CNT_NR+TR_ALL + CNT_NR <= 254 */ +#define TCPWM_TR_ALL_CNT_NR 28u +/* Number of TCPWM counter groups (1..4) */ +#define TCPWM_GRP_NR 2u +/* Counter width in number of bits per TCPWM group (16: 16-bits, 32: 32-bits) */ +#define TCPWM_GRP_NR0_CNT_GRP_CNT_WIDTH 32u +/* Second Capture / Compare Unit is present (0, 1) */ +#define TCPWM_GRP_NR0_CNT_GRP_CC1_PRESENT 0u +/* Advanced Motor Control features are present (0, 1). Should only be 1 when + GRP_CC1_PRESENT = 1 */ +#define TCPWM_GRP_NR0_CNT_GRP_AMC_PRESENT 0u +/* Stepper Motor Control features are present (0, 1). */ +#define TCPWM_GRP_NR0_CNT_GRP_SMC_PRESENT 0u +/* Number of counters per TCPWM group (1..256) */ +#define TCPWM_GRP_NR0_GRP_GRP_CNT_NR 4u +/* Counter width in number of bits per TCPWM group (16: 16-bits, 32: 32-bits) */ +#define TCPWM_GRP_NR1_CNT_GRP_CNT_WIDTH 16u +/* Second Capture / Compare Unit is present (0, 1) */ +#define TCPWM_GRP_NR1_CNT_GRP_CC1_PRESENT 1u +/* Advanced Motor Control features are present (0, 1). Should only be 1 when + GRP_CC1_PRESENT = 1 */ +#define TCPWM_GRP_NR1_CNT_GRP_AMC_PRESENT 1u +/* Stepper Motor Control features are present (0, 1). */ +#define TCPWM_GRP_NR1_CNT_GRP_SMC_PRESENT 0u +/* Number of counters per TCPWM group (1..256) */ +#define TCPWM_GRP_NR1_GRP_GRP_CNT_NR 8u +/* Number of AHB-Lite "hmaster[]" bits ([1, 8]). */ +#define TCPWM_MASTER_WIDTH 8u + +/* MMIO Targets Defines */ +#define CY_MMIO_CRYPTO_GROUP_NR 1u +#define CY_MMIO_CRYPTO_SLAVE_NR 0u +#define CY_MMIO_CPUSS_GROUP_NR 2u +#define CY_MMIO_CPUSS_SLAVE_NR 0u +#define CY_MMIO_FAULT_GROUP_NR 2u +#define CY_MMIO_FAULT_SLAVE_NR 1u +#define CY_MMIO_IPC_GROUP_NR 2u +#define CY_MMIO_IPC_SLAVE_NR 2u +#define CY_MMIO_PROT_GROUP_NR 2u +#define CY_MMIO_PROT_SLAVE_NR 3u +#define CY_MMIO_FLASHC_GROUP_NR 2u +#define CY_MMIO_FLASHC_SLAVE_NR 4u +#define CY_MMIO_SRSS_GROUP_NR 2u +#define CY_MMIO_SRSS_SLAVE_NR 6u +#define CY_MMIO_BACKUP_GROUP_NR 2u +#define CY_MMIO_BACKUP_SLAVE_NR 7u +#define CY_MMIO_DW_GROUP_NR 2u +#define CY_MMIO_DW_SLAVE_NR 8u +#define CY_MMIO_DMAC_GROUP_NR 2u +#define CY_MMIO_DMAC_SLAVE_NR 10u +#define CY_MMIO_EFUSE_GROUP_NR 2u +#define CY_MMIO_EFUSE_SLAVE_NR 12u +#define CY_MMIO_HSIOM_GROUP_NR 3u +#define CY_MMIO_HSIOM_SLAVE_NR 0u +#define CY_MMIO_GPIO_GROUP_NR 3u +#define CY_MMIO_GPIO_SLAVE_NR 1u +#define CY_MMIO_SMARTIO_GROUP_NR 3u +#define CY_MMIO_SMARTIO_SLAVE_NR 2u +#define CY_MMIO_LPCOMP_GROUP_NR 3u +#define CY_MMIO_LPCOMP_SLAVE_NR 5u +#define CY_MMIO_CSD0_GROUP_NR 3u +#define CY_MMIO_CSD0_SLAVE_NR 6u +#define CY_MMIO_TCPWM0_GROUP_NR 3u +#define CY_MMIO_TCPWM0_SLAVE_NR 8u +#define CY_MMIO_LCD0_GROUP_NR 3u +#define CY_MMIO_LCD0_SLAVE_NR 11u +#define CY_MMIO_USBFS0_GROUP_NR 3u +#define CY_MMIO_USBFS0_SLAVE_NR 15u +#define CY_MMIO_SMIF0_GROUP_NR 4u +#define CY_MMIO_SMIF0_SLAVE_NR 2u +#define CY_MMIO_CANFD0_GROUP_NR 5u +#define CY_MMIO_CANFD0_SLAVE_NR 2u +#define CY_MMIO_SCB0_GROUP_NR 6u +#define CY_MMIO_SCB0_SLAVE_NR 0u +#define CY_MMIO_SCB1_GROUP_NR 6u +#define CY_MMIO_SCB1_SLAVE_NR 1u +#define CY_MMIO_SCB2_GROUP_NR 6u +#define CY_MMIO_SCB2_SLAVE_NR 2u +#define CY_MMIO_SCB04_GROUP_NR 6u +#define CY_MMIO_SCB04_SLAVE_NR 4u +#define CY_MMIO_SCB05_GROUP_NR 6u +#define CY_MMIO_SCB05_SLAVE_NR 5u +#define CY_MMIO_SCB06_GROUP_NR 6u +#define CY_MMIO_SCB06_SLAVE_NR 6u +#define CY_MMIO_PASS_GROUP_NR 9u +#define CY_MMIO_PASS_SLAVE_NR 0u + +/* Backward compatibility definitions */ +#define CPUSS_IRQ_NR CPUSS_SYSTEM_INT_NR +#define CPUSS_DPSLP_IRQ_NR CPUSS_SYSTEM_DPSLP_INT_NR + +#endif /* _PSOC6_04_CONFIG_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6a256k.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6a256k.h new file mode 100644 index 00000000000..c0284864daf --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/devices/include/psoc6a256k.h @@ -0,0 +1,1197 @@ +/***************************************************************************//** +* \file psoc6a256k.h +* +* \brief +* PSoC6A256K device header +* +* \note +* Generator version: 1.5.1.42 +* +******************************************************************************** +* \copyright +* Copyright 2016-2019 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +*******************************************************************************/ + +#ifndef _PSOC6A256K_H_ +#define _PSOC6A256K_H_ + +/** +* \addtogroup group_device PSoC6A256K +* \{ +*/ + +/** +* \addtogroup Configuration_of_CMSIS +* \{ +*/ + +/******************************************************************************* +* Interrupt Number Definition +*******************************************************************************/ + +typedef enum { +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + /* ARM Cortex-M0+ Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* PSoC6A256K User Interrupt Numbers */ + NvicMux0_IRQn = 0, /*!< 0 [DeepSleep] CPU User Interrupt #0 */ + NvicMux1_IRQn = 1, /*!< 1 [DeepSleep] CPU User Interrupt #1 */ + NvicMux2_IRQn = 2, /*!< 2 [DeepSleep] CPU User Interrupt #2 */ + NvicMux3_IRQn = 3, /*!< 3 [DeepSleep] CPU User Interrupt #3 */ + NvicMux4_IRQn = 4, /*!< 4 [DeepSleep] CPU User Interrupt #4 */ + NvicMux5_IRQn = 5, /*!< 5 [DeepSleep] CPU User Interrupt #5 */ + NvicMux6_IRQn = 6, /*!< 6 [DeepSleep] CPU User Interrupt #6 */ + NvicMux7_IRQn = 7, /*!< 7 [DeepSleep] CPU User Interrupt #7 */ + /* PSoC6A256K Internal SW Interrupt Numbers */ + Internal0_IRQn = 8, /*!< 8 [Active] Internal SW Interrupt #0 */ + Internal1_IRQn = 9, /*!< 9 [Active] Internal SW Interrupt #1 */ + Internal2_IRQn = 10, /*!< 10 [Active] Internal SW Interrupt #2 */ + Internal3_IRQn = 11, /*!< 11 [Active] Internal SW Interrupt #3 */ + Internal4_IRQn = 12, /*!< 12 [Active] Internal SW Interrupt #4 */ + Internal5_IRQn = 13, /*!< 13 [Active] Internal SW Interrupt #5 */ + Internal6_IRQn = 14, /*!< 14 [Active] Internal SW Interrupt #6 */ + Internal7_IRQn = 15, /*!< 15 [Active] Internal SW Interrupt #7 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#else + /* ARM Cortex-M4 Core Interrupt Numbers */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + /* PSoC6A256K Peripheral Interrupt Numbers */ + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + unconnected_IRQn =1023 /*!< 1023 Unconnected */ +#endif +} IRQn_Type; + + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* PSoC6A256K interrupts that can be routed to the CM0+ NVIC */ +typedef enum { + ioss_interrupts_gpio_0_IRQn = 0, /*!< 0 [DeepSleep] GPIO Port Interrupt #0 */ + ioss_interrupts_gpio_2_IRQn = 2, /*!< 2 [DeepSleep] GPIO Port Interrupt #2 */ + ioss_interrupts_gpio_3_IRQn = 3, /*!< 3 [DeepSleep] GPIO Port Interrupt #3 */ + ioss_interrupts_gpio_5_IRQn = 5, /*!< 5 [DeepSleep] GPIO Port Interrupt #5 */ + ioss_interrupts_gpio_6_IRQn = 6, /*!< 6 [DeepSleep] GPIO Port Interrupt #6 */ + ioss_interrupts_gpio_7_IRQn = 7, /*!< 7 [DeepSleep] GPIO Port Interrupt #7 */ + ioss_interrupts_gpio_8_IRQn = 8, /*!< 8 [DeepSleep] GPIO Port Interrupt #8 */ + ioss_interrupts_gpio_9_IRQn = 9, /*!< 9 [DeepSleep] GPIO Port Interrupt #9 */ + ioss_interrupts_gpio_10_IRQn = 10, /*!< 10 [DeepSleep] GPIO Port Interrupt #10 */ + ioss_interrupts_gpio_11_IRQn = 11, /*!< 11 [DeepSleep] GPIO Port Interrupt #11 */ + ioss_interrupts_gpio_12_IRQn = 12, /*!< 12 [DeepSleep] GPIO Port Interrupt #12 */ + ioss_interrupts_gpio_14_IRQn = 14, /*!< 14 [DeepSleep] GPIO Port Interrupt #14 */ + ioss_interrupt_gpio_IRQn = 15, /*!< 15 [DeepSleep] GPIO All Ports */ + ioss_interrupt_vdd_IRQn = 16, /*!< 16 [DeepSleep] GPIO Supply Detect Interrupt */ + lpcomp_interrupt_IRQn = 17, /*!< 17 [DeepSleep] Low Power Comparator Interrupt */ + scb_6_interrupt_IRQn = 18, /*!< 18 [DeepSleep] Serial Communication Block #6 (DeepSleep capable) */ + srss_interrupt_mcwdt_0_IRQn = 19, /*!< 19 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_mcwdt_1_IRQn = 20, /*!< 20 [DeepSleep] Multi Counter Watchdog Timer interrupt */ + srss_interrupt_backup_IRQn = 21, /*!< 21 [DeepSleep] Backup domain interrupt */ + srss_interrupt_IRQn = 22, /*!< 22 [DeepSleep] Other combined Interrupts for SRSS (LVD, WDT, CLKCAL) */ + cpuss_interrupts_ipc_0_IRQn = 23, /*!< 23 [DeepSleep] CPUSS Inter Process Communication Interrupt #0 */ + cpuss_interrupts_ipc_1_IRQn = 24, /*!< 24 [DeepSleep] CPUSS Inter Process Communication Interrupt #1 */ + cpuss_interrupts_ipc_2_IRQn = 25, /*!< 25 [DeepSleep] CPUSS Inter Process Communication Interrupt #2 */ + cpuss_interrupts_ipc_3_IRQn = 26, /*!< 26 [DeepSleep] CPUSS Inter Process Communication Interrupt #3 */ + cpuss_interrupts_ipc_4_IRQn = 27, /*!< 27 [DeepSleep] CPUSS Inter Process Communication Interrupt #4 */ + cpuss_interrupts_ipc_5_IRQn = 28, /*!< 28 [DeepSleep] CPUSS Inter Process Communication Interrupt #5 */ + cpuss_interrupts_ipc_6_IRQn = 29, /*!< 29 [DeepSleep] CPUSS Inter Process Communication Interrupt #6 */ + cpuss_interrupts_ipc_7_IRQn = 30, /*!< 30 [DeepSleep] CPUSS Inter Process Communication Interrupt #7 */ + cpuss_interrupts_ipc_8_IRQn = 31, /*!< 31 [DeepSleep] CPUSS Inter Process Communication Interrupt #8 */ + cpuss_interrupts_ipc_9_IRQn = 32, /*!< 32 [DeepSleep] CPUSS Inter Process Communication Interrupt #9 */ + cpuss_interrupts_ipc_10_IRQn = 33, /*!< 33 [DeepSleep] CPUSS Inter Process Communication Interrupt #10 */ + cpuss_interrupts_ipc_11_IRQn = 34, /*!< 34 [DeepSleep] CPUSS Inter Process Communication Interrupt #11 */ + cpuss_interrupts_ipc_12_IRQn = 35, /*!< 35 [DeepSleep] CPUSS Inter Process Communication Interrupt #12 */ + cpuss_interrupts_ipc_13_IRQn = 36, /*!< 36 [DeepSleep] CPUSS Inter Process Communication Interrupt #13 */ + cpuss_interrupts_ipc_14_IRQn = 37, /*!< 37 [DeepSleep] CPUSS Inter Process Communication Interrupt #14 */ + cpuss_interrupts_ipc_15_IRQn = 38, /*!< 38 [DeepSleep] CPUSS Inter Process Communication Interrupt #15 */ + pass_interrupt_sar_0_IRQn = 39, /*!< 39 [DeepSleep] SAR ADC0 interrupt */ + pass_interrupt_sar_1_IRQn = 40, /*!< 40 [DeepSleep] SAR ADC1 interrupt */ + pass_interrupt_ctb_IRQn = 41, /*!< 41 [DeepSleep] individual interrupt per CTB */ + pass_interrupt_fifo_0_IRQn = 43, /*!< 43 [DeepSleep] PASS FIFO0 */ + pass_interrupt_fifo_1_IRQn = 44, /*!< 44 [DeepSleep] PASS FIFO1 */ + scb_0_interrupt_IRQn = 45, /*!< 45 [Active] Serial Communication Block #0 */ + scb_1_interrupt_IRQn = 46, /*!< 46 [Active] Serial Communication Block #1 */ + scb_2_interrupt_IRQn = 47, /*!< 47 [Active] Serial Communication Block #2 */ + scb_4_interrupt_IRQn = 49, /*!< 49 [Active] Serial Communication Block #4 */ + scb_5_interrupt_IRQn = 50, /*!< 50 [Active] Serial Communication Block #5 */ + csd_interrupt_IRQn = 51, /*!< 51 [Active] CSD (Capsense) interrupt */ + cpuss_interrupts_dmac_0_IRQn = 52, /*!< 52 [Active] CPUSS DMAC, Channel #0 */ + cpuss_interrupts_dmac_1_IRQn = 53, /*!< 53 [Active] CPUSS DMAC, Channel #1 */ + cpuss_interrupts_dw0_0_IRQn = 56, /*!< 56 [Active] CPUSS DataWire #0, Channel #0 */ + cpuss_interrupts_dw0_1_IRQn = 57, /*!< 57 [Active] CPUSS DataWire #0, Channel #1 */ + cpuss_interrupts_dw0_2_IRQn = 58, /*!< 58 [Active] CPUSS DataWire #0, Channel #2 */ + cpuss_interrupts_dw0_3_IRQn = 59, /*!< 59 [Active] CPUSS DataWire #0, Channel #3 */ + cpuss_interrupts_dw0_4_IRQn = 60, /*!< 60 [Active] CPUSS DataWire #0, Channel #4 */ + cpuss_interrupts_dw0_5_IRQn = 61, /*!< 61 [Active] CPUSS DataWire #0, Channel #5 */ + cpuss_interrupts_dw0_6_IRQn = 62, /*!< 62 [Active] CPUSS DataWire #0, Channel #6 */ + cpuss_interrupts_dw0_7_IRQn = 63, /*!< 63 [Active] CPUSS DataWire #0, Channel #7 */ + cpuss_interrupts_dw0_8_IRQn = 64, /*!< 64 [Active] CPUSS DataWire #0, Channel #8 */ + cpuss_interrupts_dw0_9_IRQn = 65, /*!< 65 [Active] CPUSS DataWire #0, Channel #9 */ + cpuss_interrupts_dw0_10_IRQn = 66, /*!< 66 [Active] CPUSS DataWire #0, Channel #10 */ + cpuss_interrupts_dw0_11_IRQn = 67, /*!< 67 [Active] CPUSS DataWire #0, Channel #11 */ + cpuss_interrupts_dw0_12_IRQn = 68, /*!< 68 [Active] CPUSS DataWire #0, Channel #12 */ + cpuss_interrupts_dw0_13_IRQn = 69, /*!< 69 [Active] CPUSS DataWire #0, Channel #13 */ + cpuss_interrupts_dw0_14_IRQn = 70, /*!< 70 [Active] CPUSS DataWire #0, Channel #14 */ + cpuss_interrupts_dw0_15_IRQn = 71, /*!< 71 [Active] CPUSS DataWire #0, Channel #15 */ + cpuss_interrupts_dw0_16_IRQn = 72, /*!< 72 [Active] CPUSS DataWire #0, Channel #16 */ + cpuss_interrupts_dw0_17_IRQn = 73, /*!< 73 [Active] CPUSS DataWire #0, Channel #17 */ + cpuss_interrupts_dw0_18_IRQn = 74, /*!< 74 [Active] CPUSS DataWire #0, Channel #18 */ + cpuss_interrupts_dw0_19_IRQn = 75, /*!< 75 [Active] CPUSS DataWire #0, Channel #19 */ + cpuss_interrupts_dw0_20_IRQn = 76, /*!< 76 [Active] CPUSS DataWire #0, Channel #20 */ + cpuss_interrupts_dw0_21_IRQn = 77, /*!< 77 [Active] CPUSS DataWire #0, Channel #21 */ + cpuss_interrupts_dw0_22_IRQn = 78, /*!< 78 [Active] CPUSS DataWire #0, Channel #22 */ + cpuss_interrupts_dw0_23_IRQn = 79, /*!< 79 [Active] CPUSS DataWire #0, Channel #23 */ + cpuss_interrupts_dw0_24_IRQn = 80, /*!< 80 [Active] CPUSS DataWire #0, Channel #24 */ + cpuss_interrupts_dw0_25_IRQn = 81, /*!< 81 [Active] CPUSS DataWire #0, Channel #25 */ + cpuss_interrupts_dw0_26_IRQn = 82, /*!< 82 [Active] CPUSS DataWire #0, Channel #26 */ + cpuss_interrupts_dw0_27_IRQn = 83, /*!< 83 [Active] CPUSS DataWire #0, Channel #27 */ + cpuss_interrupts_dw0_28_IRQn = 84, /*!< 84 [Active] CPUSS DataWire #0, Channel #28 */ + cpuss_interrupts_dw1_0_IRQn = 85, /*!< 85 [Active] CPUSS DataWire #1, Channel #0 */ + cpuss_interrupts_dw1_1_IRQn = 86, /*!< 86 [Active] CPUSS DataWire #1, Channel #1 */ + cpuss_interrupts_dw1_2_IRQn = 87, /*!< 87 [Active] CPUSS DataWire #1, Channel #2 */ + cpuss_interrupts_dw1_3_IRQn = 88, /*!< 88 [Active] CPUSS DataWire #1, Channel #3 */ + cpuss_interrupts_dw1_4_IRQn = 89, /*!< 89 [Active] CPUSS DataWire #1, Channel #4 */ + cpuss_interrupts_dw1_5_IRQn = 90, /*!< 90 [Active] CPUSS DataWire #1, Channel #5 */ + cpuss_interrupts_dw1_6_IRQn = 91, /*!< 91 [Active] CPUSS DataWire #1, Channel #6 */ + cpuss_interrupts_dw1_7_IRQn = 92, /*!< 92 [Active] CPUSS DataWire #1, Channel #7 */ + cpuss_interrupts_dw1_8_IRQn = 93, /*!< 93 [Active] CPUSS DataWire #1, Channel #8 */ + cpuss_interrupts_dw1_9_IRQn = 94, /*!< 94 [Active] CPUSS DataWire #1, Channel #9 */ + cpuss_interrupts_dw1_10_IRQn = 95, /*!< 95 [Active] CPUSS DataWire #1, Channel #10 */ + cpuss_interrupts_dw1_11_IRQn = 96, /*!< 96 [Active] CPUSS DataWire #1, Channel #11 */ + cpuss_interrupts_dw1_12_IRQn = 97, /*!< 97 [Active] CPUSS DataWire #1, Channel #12 */ + cpuss_interrupts_dw1_13_IRQn = 98, /*!< 98 [Active] CPUSS DataWire #1, Channel #13 */ + cpuss_interrupts_dw1_14_IRQn = 99, /*!< 99 [Active] CPUSS DataWire #1, Channel #14 */ + cpuss_interrupts_dw1_15_IRQn = 100, /*!< 100 [Active] CPUSS DataWire #1, Channel #15 */ + cpuss_interrupts_dw1_16_IRQn = 101, /*!< 101 [Active] CPUSS DataWire #1, Channel #16 */ + cpuss_interrupts_dw1_17_IRQn = 102, /*!< 102 [Active] CPUSS DataWire #1, Channel #17 */ + cpuss_interrupts_dw1_18_IRQn = 103, /*!< 103 [Active] CPUSS DataWire #1, Channel #18 */ + cpuss_interrupts_dw1_19_IRQn = 104, /*!< 104 [Active] CPUSS DataWire #1, Channel #19 */ + cpuss_interrupts_dw1_20_IRQn = 105, /*!< 105 [Active] CPUSS DataWire #1, Channel #20 */ + cpuss_interrupts_dw1_21_IRQn = 106, /*!< 106 [Active] CPUSS DataWire #1, Channel #21 */ + cpuss_interrupts_dw1_22_IRQn = 107, /*!< 107 [Active] CPUSS DataWire #1, Channel #22 */ + cpuss_interrupts_dw1_23_IRQn = 108, /*!< 108 [Active] CPUSS DataWire #1, Channel #23 */ + cpuss_interrupts_dw1_24_IRQn = 109, /*!< 109 [Active] CPUSS DataWire #1, Channel #24 */ + cpuss_interrupts_dw1_25_IRQn = 110, /*!< 110 [Active] CPUSS DataWire #1, Channel #25 */ + cpuss_interrupts_dw1_26_IRQn = 111, /*!< 111 [Active] CPUSS DataWire #1, Channel #26 */ + cpuss_interrupts_dw1_27_IRQn = 112, /*!< 112 [Active] CPUSS DataWire #1, Channel #27 */ + cpuss_interrupts_dw1_28_IRQn = 113, /*!< 113 [Active] CPUSS DataWire #1, Channel #28 */ + cpuss_interrupts_fault_0_IRQn = 114, /*!< 114 [Active] CPUSS Fault Structure Interrupt #0 */ + cpuss_interrupts_fault_1_IRQn = 115, /*!< 115 [Active] CPUSS Fault Structure Interrupt #1 */ + cpuss_interrupt_crypto_IRQn = 116, /*!< 116 [Active] CRYPTO Accelerator Interrupt */ + cpuss_interrupt_fm_IRQn = 117, /*!< 117 [Active] FLASH Macro Interrupt */ + cpuss_interrupts_cm4_fp_IRQn = 118, /*!< 118 [Active] Floating Point operation fault */ + cpuss_interrupts_cm0_cti_0_IRQn = 119, /*!< 119 [Active] CM0+ CTI #0 */ + cpuss_interrupts_cm0_cti_1_IRQn = 120, /*!< 120 [Active] CM0+ CTI #1 */ + cpuss_interrupts_cm4_cti_0_IRQn = 121, /*!< 121 [Active] CM4 CTI #0 */ + cpuss_interrupts_cm4_cti_1_IRQn = 122, /*!< 122 [Active] CM4 CTI #1 */ + tcpwm_0_interrupts_0_IRQn = 123, /*!< 123 [Active] TCPWM #0, Counter #0 */ + tcpwm_0_interrupts_1_IRQn = 124, /*!< 124 [Active] TCPWM #0, Counter #1 */ + tcpwm_0_interrupts_2_IRQn = 125, /*!< 125 [Active] TCPWM #0, Counter #2 */ + tcpwm_0_interrupts_3_IRQn = 126, /*!< 126 [Active] TCPWM #0, Counter #3 */ + tcpwm_0_interrupts_256_IRQn = 131, /*!< 131 [Active] TCPWM #0, Counter #256 */ + tcpwm_0_interrupts_257_IRQn = 132, /*!< 132 [Active] TCPWM #0, Counter #257 */ + tcpwm_0_interrupts_258_IRQn = 133, /*!< 133 [Active] TCPWM #0, Counter #258 */ + tcpwm_0_interrupts_259_IRQn = 134, /*!< 134 [Active] TCPWM #0, Counter #259 */ + tcpwm_0_interrupts_260_IRQn = 135, /*!< 135 [Active] TCPWM #0, Counter #260 */ + tcpwm_0_interrupts_261_IRQn = 136, /*!< 136 [Active] TCPWM #0, Counter #261 */ + tcpwm_0_interrupts_262_IRQn = 137, /*!< 137 [Active] TCPWM #0, Counter #262 */ + tcpwm_0_interrupts_263_IRQn = 138, /*!< 138 [Active] TCPWM #0, Counter #263 */ + pass_interrupt_dacs_IRQn = 146, /*!< 146 [Active] Consolidated interrrupt for all DACs */ + smif_interrupt_IRQn = 160, /*!< 160 [Active] Serial Memory Interface interrupt */ + usb_interrupt_hi_IRQn = 161, /*!< 161 [Active] USB Interrupt */ + usb_interrupt_med_IRQn = 162, /*!< 162 [Active] USB Interrupt */ + usb_interrupt_lo_IRQn = 163, /*!< 163 [Active] USB Interrupt */ + canfd_0_interrupt0_IRQn = 168, /*!< 168 [Active] Can #0, Consolidated interrupt #0 */ + canfd_0_interrupts0_0_IRQn = 169, /*!< 169 [Active] CAN #0, Interrupt #0, Channel #0 */ + canfd_0_interrupts1_0_IRQn = 170, /*!< 170 [Active] CAN #0, Interrupt #1, Channel #0 */ + cpuss_interrupts_dw1_29_IRQn = 171, /*!< 171 [Active] CPUSS DataWire #1, Channel #29 */ + cpuss_interrupts_dw1_30_IRQn = 172, /*!< 172 [Active] CPUSS DataWire #1, Channel #30 */ + cpuss_interrupts_dw1_31_IRQn = 173, /*!< 173 [Active] CPUSS DataWire #1, Channel #31 */ + cpuss_interrupts_dw0_29_IRQn = 174, /*!< 174 [Active] CPUSS DataWire #0, Channel #29 */ + disconnected_IRQn =1023 /*!< 1023 Disconnected */ +} cy_en_intr_t; + +#endif + +/******************************************************************************* +* Processor and Core Peripheral Section +*******************************************************************************/ + +#if ((defined(__GNUC__) && (__ARM_ARCH == 6) && (__ARM_ARCH_6M__ == 1)) || \ + (defined(__ICCARM__) && (__CORE__ == __ARM6M__)) || \ + (defined(__ARMCC_VERSION) && (__TARGET_ARCH_THUMB == 3)) || \ + (defined(__ghs__) && defined(__CORE_CORTEXM0PLUS__))) + +/* Configuration of the ARM Cortex-M0+ Processor and Core Peripherals */ +#define __CM0PLUS_REV 0x0001U /*!< CM0PLUS Core Revision */ +#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm0plus.h" /*!< ARM Cortex-M0+ processor and core peripherals */ + +#else + +/* Configuration of the ARM Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM0P_PRESENT 1 /*!< CM0P present or not */ +#define __DTCM_PRESENT 0 /*!< DTCM present or not */ +#define __ICACHE_PRESENT 0 /*!< ICACHE present or not */ +#define __DCACHE_PRESENT 0 /*!< DCACHE present or not */ + +/** \} Configuration_of_CMSIS */ + +#include "core_cm4.h" /*!< ARM Cortex-M4 processor and core peripherals */ + +#endif + +/* Memory Blocks */ +#define CY_ROM_BASE 0x00000000UL +#define CY_ROM_SIZE 0x00010000UL +#define CY_SRAM_BASE 0x08000000UL +#define CY_SRAM_SIZE 0x00020000UL +#define CY_FLASH_BASE 0x10000000UL +#define CY_FLASH_SIZE 0x00040000UL +#define CY_EM_EEPROM_BASE 0x14000000UL +#define CY_EM_EEPROM_SIZE 0x00000000UL +#define CY_XIP_BASE 0x18000000UL +#define CY_XIP_SIZE 0x08000000UL +#define CY_CAN0MRAM_BASE 0x40530000UL +#define CY_CAN0MRAM_SIZE 0x00010000UL +#define CY_SFLASH_BASE 0x16000000UL +#define CY_SFLASH_SIZE 0x00008000UL +#define CY_EFUSE_BASE 0x402C0800UL +#define CY_EFUSE_SIZE 0x00000200UL + +#include "system_psoc6.h" /*!< PSoC 6 System */ + +/* IP List */ +#define CY_IP_MXTTCANFD 1u +#define CY_IP_MXTTCANFD_INSTANCES 1u +#define CY_IP_MXTTCANFD_VERSION 1u +#define CY_IP_M4CPUSS 1u +#define CY_IP_M4CPUSS_INSTANCES 1u +#define CY_IP_M4CPUSS_VERSION 2u +#define CY_IP_M4CPUSS_DMAC 1u +#define CY_IP_M4CPUSS_DMAC_INSTANCES 1u +#define CY_IP_M4CPUSS_DMAC_VERSION 2u +#define CY_IP_M4CPUSS_DMA 1u +#define CY_IP_M4CPUSS_DMA_INSTANCES 2u +#define CY_IP_M4CPUSS_DMA_VERSION 2u +#define CY_IP_MXCRYPTO 1u +#define CY_IP_MXCRYPTO_INSTANCES 1u +#define CY_IP_MXCRYPTO_VERSION 2u +#define CY_IP_MXCSDV2 1u +#define CY_IP_MXCSDV2_INSTANCES 1u +#define CY_IP_MXCSDV2_VERSION 1u +#define CY_IP_MXEFUSE 1u +#define CY_IP_MXEFUSE_INSTANCES 1u +#define CY_IP_MXEFUSE_VERSION 1u +#define CY_IP_MXS40IOSS 1u +#define CY_IP_MXS40IOSS_INSTANCES 1u +#define CY_IP_MXS40IOSS_VERSION 2u +#define CY_IP_MXLCD 1u +#define CY_IP_MXLCD_INSTANCES 1u +#define CY_IP_MXLCD_VERSION 2u +#define CY_IP_MXLPCOMP 1u +#define CY_IP_MXLPCOMP_INSTANCES 1u +#define CY_IP_MXLPCOMP_VERSION 1u +//#define CY_IP_MXS40PASS 1u +//#define CY_IP_MXS40PASS_INSTANCES 1u +//#define CY_IP_MXS40PASS_VERSION 2u +//#define CY_IP_MXS40PASS_SAR 1u +//#define CY_IP_MXS40PASS_SAR_INSTANCES 1u +//#define CY_IP_MXS40PASS_SAR_VERSION 2u +#define CY_IP_MXPERI 1u +#define CY_IP_MXPERI_INSTANCES 1u +#define CY_IP_MXPERI_VERSION 2u +#define CY_IP_MXPERI_TR 1u +#define CY_IP_MXPERI_TR_INSTANCES 1u +#define CY_IP_MXPERI_TR_VERSION 2u +#define CY_IP_MXSCB 1u +#define CY_IP_MXSCB_INSTANCES 6u +#define CY_IP_MXSCB_VERSION 1u +#define CY_IP_MXSMIF 1u +#define CY_IP_MXSMIF_INSTANCES 1u +#define CY_IP_MXSMIF_VERSION 1u +#define CY_IP_MXS40SRSS 1u +#define CY_IP_MXS40SRSS_INSTANCES 1u +#define CY_IP_MXS40SRSS_VERSION 1u +#define CY_IP_MXS40SRSS_RTC 1u +#define CY_IP_MXS40SRSS_RTC_INSTANCES 1u +#define CY_IP_MXS40SRSS_RTC_VERSION 1u +#define CY_IP_MXS40SRSS_MCWDT 1u +#define CY_IP_MXS40SRSS_MCWDT_INSTANCES 2u +#define CY_IP_MXS40SRSS_MCWDT_VERSION 1u +//#define CY_IP_MXTCPWM 1u +//#define CY_IP_MXTCPWM_INSTANCES 1u +//#define CY_IP_MXTCPWM_VERSION 2u +#define CY_IP_MXUSBFS 1u +#define CY_IP_MXUSBFS_INSTANCES 1u +#define CY_IP_MXUSBFS_VERSION 1u + +#include "psoc6_04_config.h" +#include "gpio_psoc6_04_68_qfn.h" + +#define CY_DEVICE_PSOC6A256K +#define CY_SILICON_ID 0xFFFFFFFFUL +#define CY_HF_CLK_MAX_FREQ 150000000UL + +#define CPUSS_FLASHC_PA_SIZE_LOG2 0x7UL + +/******************************************************************************* +* SFLASH +*******************************************************************************/ + +#define SFLASH_BASE 0x16000000UL +#define SFLASH ((SFLASH_Type*) SFLASH_BASE) /* 0x16000000 */ + +/******************************************************************************* +* PERI +*******************************************************************************/ + +#define PERI_BASE 0x40000000UL +#define PERI ((PERI_Type*) PERI_BASE) /* 0x40000000 */ +#define PERI_GR0 ((PERI_GR_Type*) &PERI->GR[0]) /* 0x40004000 */ +#define PERI_GR1 ((PERI_GR_Type*) &PERI->GR[1]) /* 0x40004020 */ +#define PERI_GR2 ((PERI_GR_Type*) &PERI->GR[2]) /* 0x40004040 */ +#define PERI_GR3 ((PERI_GR_Type*) &PERI->GR[3]) /* 0x40004060 */ +#define PERI_GR4 ((PERI_GR_Type*) &PERI->GR[4]) /* 0x40004080 */ +#define PERI_GR5 ((PERI_GR_Type*) &PERI->GR[5]) /* 0x400040A0 */ +#define PERI_GR6 ((PERI_GR_Type*) &PERI->GR[6]) /* 0x400040C0 */ +#define PERI_GR9 ((PERI_GR_Type*) &PERI->GR[9]) /* 0x40004120 */ +#define PERI_TR_GR0 ((PERI_TR_GR_Type*) &PERI->TR_GR[0]) /* 0x40008000 */ +#define PERI_TR_GR1 ((PERI_TR_GR_Type*) &PERI->TR_GR[1]) /* 0x40008400 */ +#define PERI_TR_GR2 ((PERI_TR_GR_Type*) &PERI->TR_GR[2]) /* 0x40008800 */ +#define PERI_TR_GR3 ((PERI_TR_GR_Type*) &PERI->TR_GR[3]) /* 0x40008C00 */ +#define PERI_TR_GR4 ((PERI_TR_GR_Type*) &PERI->TR_GR[4]) /* 0x40009000 */ +#define PERI_TR_GR5 ((PERI_TR_GR_Type*) &PERI->TR_GR[5]) /* 0x40009400 */ +#define PERI_TR_GR6 ((PERI_TR_GR_Type*) &PERI->TR_GR[6]) /* 0x40009800 */ +#define PERI_TR_GR7 ((PERI_TR_GR_Type*) &PERI->TR_GR[7]) /* 0x40009C00 */ +#define PERI_TR_GR8 ((PERI_TR_GR_Type*) &PERI->TR_GR[8]) /* 0x4000A000 */ +#define PERI_TR_GR9 ((PERI_TR_GR_Type*) &PERI->TR_GR[9]) /* 0x4000A400 */ +#define PERI_TR_GR10 ((PERI_TR_GR_Type*) &PERI->TR_GR[10]) /* 0x4000A800 */ +#define PERI_TR_1TO1_GR0 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[0]) /* 0x4000C000 */ +#define PERI_TR_1TO1_GR1 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[1]) /* 0x4000C400 */ +#define PERI_TR_1TO1_GR2 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[2]) /* 0x4000C800 */ +#define PERI_TR_1TO1_GR3 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[3]) /* 0x4000CC00 */ +#define PERI_TR_1TO1_GR4 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[4]) /* 0x4000D000 */ +#define PERI_TR_1TO1_GR5 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[5]) /* 0x4000D400 */ +#define PERI_TR_1TO1_GR6 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[6]) /* 0x4000D800 */ +#define PERI_TR_1TO1_GR7 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[7]) /* 0x4000DC00 */ +#define PERI_TR_1TO1_GR8 ((PERI_TR_1TO1_GR_Type*) &PERI->TR_1TO1_GR[8]) /* 0x4000E000 */ + +/******************************************************************************* +* PERI_MS +*******************************************************************************/ + +#define PERI_MS_BASE 0x40010000UL +#define PERI_MS ((PERI_MS_Type*) PERI_MS_BASE) /* 0x40010000 */ +#define PERI_MS_PPU_PR0 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[0]) /* 0x40010000 */ +#define PERI_MS_PPU_PR1 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[1]) /* 0x40010040 */ +#define PERI_MS_PPU_PR2 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[2]) /* 0x40010080 */ +#define PERI_MS_PPU_PR3 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[3]) /* 0x400100C0 */ +#define PERI_MS_PPU_PR4 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[4]) /* 0x40010100 */ +#define PERI_MS_PPU_PR5 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[5]) /* 0x40010140 */ +#define PERI_MS_PPU_PR6 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[6]) /* 0x40010180 */ +#define PERI_MS_PPU_PR7 ((PERI_MS_PPU_PR_Type*) &PERI_MS->PPU_PR[7]) /* 0x400101C0 */ +#define PERI_MS_PPU_FX_PERI_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[0]) /* 0x40010800 */ +#define PERI_MS_PPU_FX_PERI_GR0_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[1]) /* 0x40010840 */ +#define PERI_MS_PPU_FX_PERI_GR1_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[2]) /* 0x40010880 */ +#define PERI_MS_PPU_FX_PERI_GR2_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[3]) /* 0x400108C0 */ +#define PERI_MS_PPU_FX_PERI_GR3_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[4]) /* 0x40010900 */ +#define PERI_MS_PPU_FX_PERI_GR4_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[5]) /* 0x40010940 */ +#define PERI_MS_PPU_FX_PERI_GR5_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[6]) /* 0x40010980 */ +#define PERI_MS_PPU_FX_PERI_GR6_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[7]) /* 0x400109C0 */ +#define PERI_MS_PPU_FX_PERI_GR9_GROUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[8]) /* 0x40010A00 */ +#define PERI_MS_PPU_FX_PERI_TR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[9]) /* 0x40010A40 */ +#define PERI_MS_PPU_FX_CRYPTO_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[10]) /* 0x40010A80 */ +#define PERI_MS_PPU_FX_CRYPTO_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[11]) /* 0x40010AC0 */ +#define PERI_MS_PPU_FX_CRYPTO_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[12]) /* 0x40010B00 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[13]) /* 0x40010B40 */ +#define PERI_MS_PPU_FX_CRYPTO_KEY1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[14]) /* 0x40010B80 */ +#define PERI_MS_PPU_FX_CRYPTO_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[15]) /* 0x40010BC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[16]) /* 0x40010C00 */ +#define PERI_MS_PPU_FX_CPUSS_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[17]) /* 0x40010C40 */ +#define PERI_MS_PPU_FX_CPUSS_BOOT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[18]) /* 0x40010C80 */ +#define PERI_MS_PPU_FX_CPUSS_CM0_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[19]) /* 0x40010CC0 */ +#define PERI_MS_PPU_FX_CPUSS_CM4_INT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[20]) /* 0x40010D00 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[21]) /* 0x40010D40 */ +#define PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[22]) /* 0x40010D80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT0_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[23]) /* 0x40010DC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT1_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[24]) /* 0x40010E00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT2_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[25]) /* 0x40010E40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT3_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[26]) /* 0x40010E80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT4_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[27]) /* 0x40010EC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT5_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[28]) /* 0x40010F00 */ +#define PERI_MS_PPU_FX_IPC_STRUCT6_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[29]) /* 0x40010F40 */ +#define PERI_MS_PPU_FX_IPC_STRUCT7_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[30]) /* 0x40010F80 */ +#define PERI_MS_PPU_FX_IPC_STRUCT8_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[31]) /* 0x40010FC0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT9_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[32]) /* 0x40011000 */ +#define PERI_MS_PPU_FX_IPC_STRUCT10_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[33]) /* 0x40011040 */ +#define PERI_MS_PPU_FX_IPC_STRUCT11_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[34]) /* 0x40011080 */ +#define PERI_MS_PPU_FX_IPC_STRUCT12_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[35]) /* 0x400110C0 */ +#define PERI_MS_PPU_FX_IPC_STRUCT13_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[36]) /* 0x40011100 */ +#define PERI_MS_PPU_FX_IPC_STRUCT14_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[37]) /* 0x40011140 */ +#define PERI_MS_PPU_FX_IPC_STRUCT15_IPC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[38]) /* 0x40011180 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[39]) /* 0x400111C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[40]) /* 0x40011200 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[41]) /* 0x40011240 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[42]) /* 0x40011280 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[43]) /* 0x400112C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[44]) /* 0x40011300 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[45]) /* 0x40011340 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[46]) /* 0x40011380 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT8_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[47]) /* 0x400113C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT9_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[48]) /* 0x40011400 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT10_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[49]) /* 0x40011440 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT11_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[50]) /* 0x40011480 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT12_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[51]) /* 0x400114C0 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT13_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[52]) /* 0x40011500 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT14_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[53]) /* 0x40011540 */ +#define PERI_MS_PPU_FX_IPC_INTR_STRUCT15_INTR ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[54]) /* 0x40011580 */ +#define PERI_MS_PPU_FX_PROT_SMPU_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[55]) /* 0x400115C0 */ +#define PERI_MS_PPU_FX_PROT_MPU0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[56]) /* 0x40011600 */ +#define PERI_MS_PPU_FX_PROT_MPU14_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[57]) /* 0x40011640 */ +#define PERI_MS_PPU_FX_PROT_MPU15_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[58]) /* 0x40011680 */ +#define PERI_MS_PPU_FX_FLASHC_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[59]) /* 0x400116C0 */ +#define PERI_MS_PPU_FX_FLASHC_CMD ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[60]) /* 0x40011700 */ +#define PERI_MS_PPU_FX_FLASHC_DFT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[61]) /* 0x40011740 */ +#define PERI_MS_PPU_FX_FLASHC_CM0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[62]) /* 0x40011780 */ +#define PERI_MS_PPU_FX_FLASHC_CM4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[63]) /* 0x400117C0 */ +#define PERI_MS_PPU_FX_FLASHC_CRYPTO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[64]) /* 0x40011800 */ +#define PERI_MS_PPU_FX_FLASHC_DW0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[65]) /* 0x40011840 */ +#define PERI_MS_PPU_FX_FLASHC_DW1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[66]) /* 0x40011880 */ +#define PERI_MS_PPU_FX_FLASHC_DMAC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[67]) /* 0x400118C0 */ +#define PERI_MS_PPU_FX_FLASHC_FM ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[68]) /* 0x40011900 */ +#define PERI_MS_PPU_FX_SRSS_MAIN1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[69]) /* 0x40011940 */ +#define PERI_MS_PPU_FX_SRSS_MAIN2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[70]) /* 0x40011980 */ +#define PERI_MS_PPU_FX_WDT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[71]) /* 0x400119C0 */ +#define PERI_MS_PPU_FX_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[72]) /* 0x40011A00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN3 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[73]) /* 0x40011A40 */ +#define PERI_MS_PPU_FX_SRSS_MAIN4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[74]) /* 0x40011A80 */ +#define PERI_MS_PPU_FX_SRSS_MAIN5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[75]) /* 0x40011AC0 */ +#define PERI_MS_PPU_FX_SRSS_MAIN6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[76]) /* 0x40011B00 */ +#define PERI_MS_PPU_FX_SRSS_MAIN7 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[77]) /* 0x40011B40 */ +#define PERI_MS_PPU_FX_BACKUP_BACKUP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[78]) /* 0x40011B80 */ +#define PERI_MS_PPU_FX_DW0_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[79]) /* 0x40011BC0 */ +#define PERI_MS_PPU_FX_DW1_DW ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[80]) /* 0x40011C00 */ +#define PERI_MS_PPU_FX_DW0_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[81]) /* 0x40011C40 */ +#define PERI_MS_PPU_FX_DW1_DW_CRC ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[82]) /* 0x40011C80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[83]) /* 0x40011CC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[84]) /* 0x40011D00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[85]) /* 0x40011D40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[86]) /* 0x40011D80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[87]) /* 0x40011DC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[88]) /* 0x40011E00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[89]) /* 0x40011E40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[90]) /* 0x40011E80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[91]) /* 0x40011EC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[92]) /* 0x40011F00 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[93]) /* 0x40011F40 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[94]) /* 0x40011F80 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[95]) /* 0x40011FC0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[96]) /* 0x40012000 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[97]) /* 0x40012040 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[98]) /* 0x40012080 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[99]) /* 0x400120C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[100]) /* 0x40012100 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[101]) /* 0x40012140 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[102]) /* 0x40012180 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[103]) /* 0x400121C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[104]) /* 0x40012200 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[105]) /* 0x40012240 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[106]) /* 0x40012280 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[107]) /* 0x400122C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[108]) /* 0x40012300 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[109]) /* 0x40012340 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[110]) /* 0x40012380 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[111]) /* 0x400123C0 */ +#define PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[112]) /* 0x40012400 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[113]) /* 0x40012440 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[114]) /* 0x40012480 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[115]) /* 0x400124C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[116]) /* 0x40012500 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[117]) /* 0x40012540 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[118]) /* 0x40012580 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[119]) /* 0x400125C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[120]) /* 0x40012600 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[121]) /* 0x40012640 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[122]) /* 0x40012680 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[123]) /* 0x400126C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[124]) /* 0x40012700 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[125]) /* 0x40012740 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[126]) /* 0x40012780 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[127]) /* 0x400127C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[128]) /* 0x40012800 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[129]) /* 0x40012840 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[130]) /* 0x40012880 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[131]) /* 0x400128C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[132]) /* 0x40012900 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[133]) /* 0x40012940 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[134]) /* 0x40012980 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[135]) /* 0x400129C0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[136]) /* 0x40012A00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[137]) /* 0x40012A40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[138]) /* 0x40012A80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[139]) /* 0x40012AC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[140]) /* 0x40012B00 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[141]) /* 0x40012B40 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[142]) /* 0x40012B80 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[143]) /* 0x40012BC0 */ +#define PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[144]) /* 0x40012C00 */ +#define PERI_MS_PPU_FX_DMAC_TOP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[145]) /* 0x40012C40 */ +#define PERI_MS_PPU_FX_DMAC_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[146]) /* 0x40012C80 */ +#define PERI_MS_PPU_FX_DMAC_CH1_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[147]) /* 0x40012CC0 */ +#define PERI_MS_PPU_FX_EFUSE_CTL ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[148]) /* 0x40012D00 */ +#define PERI_MS_PPU_FX_EFUSE_DATA ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[149]) /* 0x40012D40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[150]) /* 0x40012D80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[151]) /* 0x40012DC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[152]) /* 0x40012E00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[153]) /* 0x40012E40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[154]) /* 0x40012E80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[155]) /* 0x40012EC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[156]) /* 0x40012F00 */ +#define PERI_MS_PPU_FX_HSIOM_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[157]) /* 0x40012F40 */ +#define PERI_MS_PPU_FX_HSIOM_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[158]) /* 0x40012F80 */ +#define PERI_MS_PPU_FX_HSIOM_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[159]) /* 0x40012FC0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[160]) /* 0x40013000 */ +#define PERI_MS_PPU_FX_HSIOM_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[161]) /* 0x40013040 */ +#define PERI_MS_PPU_FX_HSIOM_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[162]) /* 0x40013080 */ +#define PERI_MS_PPU_FX_HSIOM_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[163]) /* 0x400130C0 */ +#define PERI_MS_PPU_FX_HSIOM_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[164]) /* 0x40013100 */ +#define PERI_MS_PPU_FX_HSIOM_AMUX ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[165]) /* 0x40013140 */ +#define PERI_MS_PPU_FX_HSIOM_MON ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[166]) /* 0x40013180 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[167]) /* 0x400131C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[168]) /* 0x40013200 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[169]) /* 0x40013240 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[170]) /* 0x40013280 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[171]) /* 0x400132C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[172]) /* 0x40013300 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[173]) /* 0x40013340 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[174]) /* 0x40013380 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[175]) /* 0x400133C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[176]) /* 0x40013400 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[177]) /* 0x40013440 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[178]) /* 0x40013480 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[179]) /* 0x400134C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[180]) /* 0x40013500 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[181]) /* 0x40013540 */ +#define PERI_MS_PPU_FX_GPIO_PRT0_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[182]) /* 0x40013580 */ +#define PERI_MS_PPU_FX_GPIO_PRT1_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[183]) /* 0x400135C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT2_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[184]) /* 0x40013600 */ +#define PERI_MS_PPU_FX_GPIO_PRT3_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[185]) /* 0x40013640 */ +#define PERI_MS_PPU_FX_GPIO_PRT4_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[186]) /* 0x40013680 */ +#define PERI_MS_PPU_FX_GPIO_PRT5_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[187]) /* 0x400136C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT6_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[188]) /* 0x40013700 */ +#define PERI_MS_PPU_FX_GPIO_PRT7_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[189]) /* 0x40013740 */ +#define PERI_MS_PPU_FX_GPIO_PRT8_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[190]) /* 0x40013780 */ +#define PERI_MS_PPU_FX_GPIO_PRT9_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[191]) /* 0x400137C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT10_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[192]) /* 0x40013800 */ +#define PERI_MS_PPU_FX_GPIO_PRT11_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[193]) /* 0x40013840 */ +#define PERI_MS_PPU_FX_GPIO_PRT12_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[194]) /* 0x40013880 */ +#define PERI_MS_PPU_FX_GPIO_PRT13_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[195]) /* 0x400138C0 */ +#define PERI_MS_PPU_FX_GPIO_PRT14_CFG ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[196]) /* 0x40013900 */ +#define PERI_MS_PPU_FX_GPIO_GPIO ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[197]) /* 0x40013940 */ +#define PERI_MS_PPU_FX_GPIO_TEST ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[198]) /* 0x40013980 */ +#define PERI_MS_PPU_FX_SMARTIO_PRT9_PRT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[199]) /* 0x400139C0 */ +#define PERI_MS_PPU_FX_LPCOMP ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[200]) /* 0x40013A00 */ +#define PERI_MS_PPU_FX_CSD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[201]) /* 0x40013A40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[202]) /* 0x40013A80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[203]) /* 0x40013AC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[204]) /* 0x40013B00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP0_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[205]) /* 0x40013B40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[206]) /* 0x40013B80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[207]) /* 0x40013BC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[208]) /* 0x40013C00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT3_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[209]) /* 0x40013C40 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT4_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[210]) /* 0x40013C80 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT5_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[211]) /* 0x40013CC0 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT6_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[212]) /* 0x40013D00 */ +#define PERI_MS_PPU_FX_TCPWM0_GRP1_CNT7_CNT ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[213]) /* 0x40013D40 */ +#define PERI_MS_PPU_FX_LCD0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[214]) /* 0x40013D80 */ +#define PERI_MS_PPU_FX_USBFS0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[215]) /* 0x40013DC0 */ +#define PERI_MS_PPU_FX_SMIF0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[216]) /* 0x40013E00 */ +#define PERI_MS_PPU_FX_CANFD0_CH0_CH ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[217]) /* 0x40013E40 */ +#define PERI_MS_PPU_FX_CANFD0_MAIN ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[218]) /* 0x40013E80 */ +#define PERI_MS_PPU_FX_CANFD0_BUF ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[219]) /* 0x40013EC0 */ +#define PERI_MS_PPU_FX_SCB0 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[220]) /* 0x40013F00 */ +#define PERI_MS_PPU_FX_SCB1 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[221]) /* 0x40013F40 */ +#define PERI_MS_PPU_FX_SCB2 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[222]) /* 0x40013F80 */ +#define PERI_MS_PPU_FX_SCB4 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[223]) /* 0x40013FC0 */ +#define PERI_MS_PPU_FX_SCB5 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[224]) /* 0x40014000 */ +#define PERI_MS_PPU_FX_SCB6 ((PERI_MS_PPU_FX_Type*) &PERI_MS->PPU_FX[225]) /* 0x40014040 */ + +/******************************************************************************* +* CRYPTO +*******************************************************************************/ + +#define CRYPTO_BASE 0x40100000UL +#define CRYPTO ((CRYPTO_Type*) CRYPTO_BASE) /* 0x40100000 */ + +/******************************************************************************* +* CPUSS +*******************************************************************************/ + +#define CPUSS_BASE 0x40200000UL +#define CPUSS ((CPUSS_Type*) CPUSS_BASE) /* 0x40200000 */ + +/******************************************************************************* +* FAULT +*******************************************************************************/ + +#define FAULT_BASE 0x40210000UL +#define FAULT ((FAULT_Type*) FAULT_BASE) /* 0x40210000 */ +#define FAULT_STRUCT0 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[0]) /* 0x40210000 */ +#define FAULT_STRUCT1 ((FAULT_STRUCT_Type*) &FAULT->STRUCT[1]) /* 0x40210100 */ + +/******************************************************************************* +* IPC +*******************************************************************************/ + +#define IPC_BASE 0x40220000UL +#define IPC ((IPC_Type*) IPC_BASE) /* 0x40220000 */ +#define IPC_STRUCT0 ((IPC_STRUCT_Type*) &IPC->STRUCT[0]) /* 0x40220000 */ +#define IPC_STRUCT1 ((IPC_STRUCT_Type*) &IPC->STRUCT[1]) /* 0x40220020 */ +#define IPC_STRUCT2 ((IPC_STRUCT_Type*) &IPC->STRUCT[2]) /* 0x40220040 */ +#define IPC_STRUCT3 ((IPC_STRUCT_Type*) &IPC->STRUCT[3]) /* 0x40220060 */ +#define IPC_STRUCT4 ((IPC_STRUCT_Type*) &IPC->STRUCT[4]) /* 0x40220080 */ +#define IPC_STRUCT5 ((IPC_STRUCT_Type*) &IPC->STRUCT[5]) /* 0x402200A0 */ +#define IPC_STRUCT6 ((IPC_STRUCT_Type*) &IPC->STRUCT[6]) /* 0x402200C0 */ +#define IPC_STRUCT7 ((IPC_STRUCT_Type*) &IPC->STRUCT[7]) /* 0x402200E0 */ +#define IPC_STRUCT8 ((IPC_STRUCT_Type*) &IPC->STRUCT[8]) /* 0x40220100 */ +#define IPC_STRUCT9 ((IPC_STRUCT_Type*) &IPC->STRUCT[9]) /* 0x40220120 */ +#define IPC_STRUCT10 ((IPC_STRUCT_Type*) &IPC->STRUCT[10]) /* 0x40220140 */ +#define IPC_STRUCT11 ((IPC_STRUCT_Type*) &IPC->STRUCT[11]) /* 0x40220160 */ +#define IPC_STRUCT12 ((IPC_STRUCT_Type*) &IPC->STRUCT[12]) /* 0x40220180 */ +#define IPC_STRUCT13 ((IPC_STRUCT_Type*) &IPC->STRUCT[13]) /* 0x402201A0 */ +#define IPC_STRUCT14 ((IPC_STRUCT_Type*) &IPC->STRUCT[14]) /* 0x402201C0 */ +#define IPC_STRUCT15 ((IPC_STRUCT_Type*) &IPC->STRUCT[15]) /* 0x402201E0 */ +#define IPC_INTR_STRUCT0 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[0]) /* 0x40221000 */ +#define IPC_INTR_STRUCT1 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[1]) /* 0x40221020 */ +#define IPC_INTR_STRUCT2 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[2]) /* 0x40221040 */ +#define IPC_INTR_STRUCT3 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[3]) /* 0x40221060 */ +#define IPC_INTR_STRUCT4 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[4]) /* 0x40221080 */ +#define IPC_INTR_STRUCT5 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[5]) /* 0x402210A0 */ +#define IPC_INTR_STRUCT6 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[6]) /* 0x402210C0 */ +#define IPC_INTR_STRUCT7 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[7]) /* 0x402210E0 */ +#define IPC_INTR_STRUCT8 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[8]) /* 0x40221100 */ +#define IPC_INTR_STRUCT9 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[9]) /* 0x40221120 */ +#define IPC_INTR_STRUCT10 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[10]) /* 0x40221140 */ +#define IPC_INTR_STRUCT11 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[11]) /* 0x40221160 */ +#define IPC_INTR_STRUCT12 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[12]) /* 0x40221180 */ +#define IPC_INTR_STRUCT13 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[13]) /* 0x402211A0 */ +#define IPC_INTR_STRUCT14 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[14]) /* 0x402211C0 */ +#define IPC_INTR_STRUCT15 ((IPC_INTR_STRUCT_Type*) &IPC->INTR_STRUCT[15]) /* 0x402211E0 */ + +/******************************************************************************* +* PROT +*******************************************************************************/ + +#define PROT_BASE 0x40230000UL +#define PROT ((PROT_Type*) PROT_BASE) /* 0x40230000 */ +#define PROT_SMPU_SMPU_STRUCT0 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[0]) /* 0x40232000 */ +#define PROT_SMPU_SMPU_STRUCT1 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[1]) /* 0x40232040 */ +#define PROT_SMPU_SMPU_STRUCT2 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[2]) /* 0x40232080 */ +#define PROT_SMPU_SMPU_STRUCT3 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[3]) /* 0x402320C0 */ +#define PROT_SMPU_SMPU_STRUCT4 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[4]) /* 0x40232100 */ +#define PROT_SMPU_SMPU_STRUCT5 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[5]) /* 0x40232140 */ +#define PROT_SMPU_SMPU_STRUCT6 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[6]) /* 0x40232180 */ +#define PROT_SMPU_SMPU_STRUCT7 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[7]) /* 0x402321C0 */ +#define PROT_SMPU_SMPU_STRUCT8 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[8]) /* 0x40232200 */ +#define PROT_SMPU_SMPU_STRUCT9 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[9]) /* 0x40232240 */ +#define PROT_SMPU_SMPU_STRUCT10 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[10]) /* 0x40232280 */ +#define PROT_SMPU_SMPU_STRUCT11 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[11]) /* 0x402322C0 */ +#define PROT_SMPU_SMPU_STRUCT12 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[12]) /* 0x40232300 */ +#define PROT_SMPU_SMPU_STRUCT13 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[13]) /* 0x40232340 */ +#define PROT_SMPU_SMPU_STRUCT14 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[14]) /* 0x40232380 */ +#define PROT_SMPU_SMPU_STRUCT15 ((PROT_SMPU_SMPU_STRUCT_Type*) &PROT->SMPU.SMPU_STRUCT[15]) /* 0x402323C0 */ +#define PROT_SMPU ((PROT_SMPU_Type*) &PROT->SMPU) /* 0x40230000 */ +#define PROT_MPU15_MPU_STRUCT0 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[0]) /* 0x40237E00 */ +#define PROT_MPU15_MPU_STRUCT1 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[1]) /* 0x40237E20 */ +#define PROT_MPU15_MPU_STRUCT2 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[2]) /* 0x40237E40 */ +#define PROT_MPU15_MPU_STRUCT3 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[3]) /* 0x40237E60 */ +#define PROT_MPU15_MPU_STRUCT4 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[4]) /* 0x40237E80 */ +#define PROT_MPU15_MPU_STRUCT5 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[5]) /* 0x40237EA0 */ +#define PROT_MPU15_MPU_STRUCT6 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[6]) /* 0x40237EC0 */ +#define PROT_MPU15_MPU_STRUCT7 ((PROT_MPU_MPU_STRUCT_Type*) &PROT->CYMPU[15].MPU_STRUCT[7]) /* 0x40237EE0 */ +#define PROT_MPU0 ((PROT_MPU_Type*) &PROT->CYMPU[0]) /* 0x40234000 */ +#define PROT_MPU1 ((PROT_MPU_Type*) &PROT->CYMPU[1]) /* 0x40234400 */ +#define PROT_MPU2 ((PROT_MPU_Type*) &PROT->CYMPU[2]) /* 0x40234800 */ +#define PROT_MPU3 ((PROT_MPU_Type*) &PROT->CYMPU[3]) /* 0x40234C00 */ +#define PROT_MPU4 ((PROT_MPU_Type*) &PROT->CYMPU[4]) /* 0x40235000 */ +#define PROT_MPU5 ((PROT_MPU_Type*) &PROT->CYMPU[5]) /* 0x40235400 */ +#define PROT_MPU6 ((PROT_MPU_Type*) &PROT->CYMPU[6]) /* 0x40235800 */ +#define PROT_MPU7 ((PROT_MPU_Type*) &PROT->CYMPU[7]) /* 0x40235C00 */ +#define PROT_MPU8 ((PROT_MPU_Type*) &PROT->CYMPU[8]) /* 0x40236000 */ +#define PROT_MPU9 ((PROT_MPU_Type*) &PROT->CYMPU[9]) /* 0x40236400 */ +#define PROT_MPU10 ((PROT_MPU_Type*) &PROT->CYMPU[10]) /* 0x40236800 */ +#define PROT_MPU11 ((PROT_MPU_Type*) &PROT->CYMPU[11]) /* 0x40236C00 */ +#define PROT_MPU12 ((PROT_MPU_Type*) &PROT->CYMPU[12]) /* 0x40237000 */ +#define PROT_MPU13 ((PROT_MPU_Type*) &PROT->CYMPU[13]) /* 0x40237400 */ +#define PROT_MPU14 ((PROT_MPU_Type*) &PROT->CYMPU[14]) /* 0x40237800 */ +#define PROT_MPU15 ((PROT_MPU_Type*) &PROT->CYMPU[15]) /* 0x40237C00 */ + +/******************************************************************************* +* FLASHC +*******************************************************************************/ + +#define FLASHC_BASE 0x40240000UL +#define FLASHC ((FLASHC_Type*) FLASHC_BASE) /* 0x40240000 */ +#define FLASHC_FM_CTL ((FLASHC_FM_CTL_Type*) &FLASHC->FM_CTL) /* 0x4024F000 */ + +/******************************************************************************* +* SRSS +*******************************************************************************/ + +#define SRSS_BASE 0x40260000UL +#define SRSS ((SRSS_Type*) SRSS_BASE) /* 0x40260000 */ +#define MCWDT_STRUCT0 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[0]) /* 0x40260200 */ +#define MCWDT_STRUCT1 ((MCWDT_STRUCT_Type*) &SRSS->MCWDT_STRUCT[1]) /* 0x40260240 */ + +/******************************************************************************* +* BACKUP +*******************************************************************************/ + +#define BACKUP_BASE 0x40270000UL +#define BACKUP ((BACKUP_Type*) BACKUP_BASE) /* 0x40270000 */ + +/******************************************************************************* +* DW +*******************************************************************************/ + +#define DW0_BASE 0x40280000UL +#define DW1_BASE 0x40290000UL +#define DW0 ((DW_Type*) DW0_BASE) /* 0x40280000 */ +#define DW1 ((DW_Type*) DW1_BASE) /* 0x40290000 */ +#define DW0_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[0]) /* 0x40288000 */ +#define DW0_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[1]) /* 0x40288040 */ +#define DW0_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[2]) /* 0x40288080 */ +#define DW0_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[3]) /* 0x402880C0 */ +#define DW0_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[4]) /* 0x40288100 */ +#define DW0_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[5]) /* 0x40288140 */ +#define DW0_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[6]) /* 0x40288180 */ +#define DW0_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[7]) /* 0x402881C0 */ +#define DW0_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[8]) /* 0x40288200 */ +#define DW0_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[9]) /* 0x40288240 */ +#define DW0_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[10]) /* 0x40288280 */ +#define DW0_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[11]) /* 0x402882C0 */ +#define DW0_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[12]) /* 0x40288300 */ +#define DW0_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[13]) /* 0x40288340 */ +#define DW0_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[14]) /* 0x40288380 */ +#define DW0_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[15]) /* 0x402883C0 */ +#define DW0_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[16]) /* 0x40288400 */ +#define DW0_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[17]) /* 0x40288440 */ +#define DW0_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[18]) /* 0x40288480 */ +#define DW0_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[19]) /* 0x402884C0 */ +#define DW0_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[20]) /* 0x40288500 */ +#define DW0_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[21]) /* 0x40288540 */ +#define DW0_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[22]) /* 0x40288580 */ +#define DW0_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[23]) /* 0x402885C0 */ +#define DW0_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[24]) /* 0x40288600 */ +#define DW0_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[25]) /* 0x40288640 */ +#define DW0_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[26]) /* 0x40288680 */ +#define DW0_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[27]) /* 0x402886C0 */ +#define DW0_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[28]) /* 0x40288700 */ +#define DW0_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW0->CH_STRUCT[29]) /* 0x40288740 */ +#define DW1_CH_STRUCT0 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[0]) /* 0x40298000 */ +#define DW1_CH_STRUCT1 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[1]) /* 0x40298040 */ +#define DW1_CH_STRUCT2 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[2]) /* 0x40298080 */ +#define DW1_CH_STRUCT3 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[3]) /* 0x402980C0 */ +#define DW1_CH_STRUCT4 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[4]) /* 0x40298100 */ +#define DW1_CH_STRUCT5 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[5]) /* 0x40298140 */ +#define DW1_CH_STRUCT6 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[6]) /* 0x40298180 */ +#define DW1_CH_STRUCT7 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[7]) /* 0x402981C0 */ +#define DW1_CH_STRUCT8 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[8]) /* 0x40298200 */ +#define DW1_CH_STRUCT9 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[9]) /* 0x40298240 */ +#define DW1_CH_STRUCT10 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[10]) /* 0x40298280 */ +#define DW1_CH_STRUCT11 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[11]) /* 0x402982C0 */ +#define DW1_CH_STRUCT12 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[12]) /* 0x40298300 */ +#define DW1_CH_STRUCT13 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[13]) /* 0x40298340 */ +#define DW1_CH_STRUCT14 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[14]) /* 0x40298380 */ +#define DW1_CH_STRUCT15 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[15]) /* 0x402983C0 */ +#define DW1_CH_STRUCT16 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[16]) /* 0x40298400 */ +#define DW1_CH_STRUCT17 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[17]) /* 0x40298440 */ +#define DW1_CH_STRUCT18 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[18]) /* 0x40298480 */ +#define DW1_CH_STRUCT19 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[19]) /* 0x402984C0 */ +#define DW1_CH_STRUCT20 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[20]) /* 0x40298500 */ +#define DW1_CH_STRUCT21 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[21]) /* 0x40298540 */ +#define DW1_CH_STRUCT22 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[22]) /* 0x40298580 */ +#define DW1_CH_STRUCT23 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[23]) /* 0x402985C0 */ +#define DW1_CH_STRUCT24 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[24]) /* 0x40298600 */ +#define DW1_CH_STRUCT25 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[25]) /* 0x40298640 */ +#define DW1_CH_STRUCT26 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[26]) /* 0x40298680 */ +#define DW1_CH_STRUCT27 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[27]) /* 0x402986C0 */ +#define DW1_CH_STRUCT28 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[28]) /* 0x40298700 */ +#define DW1_CH_STRUCT29 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[29]) /* 0x40298740 */ +#define DW1_CH_STRUCT30 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[30]) /* 0x40298780 */ +#define DW1_CH_STRUCT31 ((DW_CH_STRUCT_Type*) &DW1->CH_STRUCT[31]) /* 0x402987C0 */ + +/******************************************************************************* +* DMAC +*******************************************************************************/ + +#define DMAC_BASE 0x402A0000UL +#define DMAC ((DMAC_Type*) DMAC_BASE) /* 0x402A0000 */ +#define DMAC_CH0 ((DMAC_CH_Type*) &DMAC->CH[0]) /* 0x402A1000 */ +#define DMAC_CH1 ((DMAC_CH_Type*) &DMAC->CH[1]) /* 0x402A1100 */ + +/******************************************************************************* +* EFUSE +*******************************************************************************/ + +#define EFUSE_BASE 0x402C0000UL +#define EFUSE ((EFUSE_Type*) EFUSE_BASE) /* 0x402C0000 */ + +/******************************************************************************* +* HSIOM +*******************************************************************************/ + +#define HSIOM_BASE 0x40300000UL +#define HSIOM ((HSIOM_Type*) HSIOM_BASE) /* 0x40300000 */ +#define HSIOM_PRT0 ((HSIOM_PRT_Type*) &HSIOM->PRT[0]) /* 0x40300000 */ +#define HSIOM_PRT1 ((HSIOM_PRT_Type*) &HSIOM->PRT[1]) /* 0x40300010 */ +#define HSIOM_PRT2 ((HSIOM_PRT_Type*) &HSIOM->PRT[2]) /* 0x40300020 */ +#define HSIOM_PRT3 ((HSIOM_PRT_Type*) &HSIOM->PRT[3]) /* 0x40300030 */ +#define HSIOM_PRT4 ((HSIOM_PRT_Type*) &HSIOM->PRT[4]) /* 0x40300040 */ +#define HSIOM_PRT5 ((HSIOM_PRT_Type*) &HSIOM->PRT[5]) /* 0x40300050 */ +#define HSIOM_PRT6 ((HSIOM_PRT_Type*) &HSIOM->PRT[6]) /* 0x40300060 */ +#define HSIOM_PRT7 ((HSIOM_PRT_Type*) &HSIOM->PRT[7]) /* 0x40300070 */ +#define HSIOM_PRT8 ((HSIOM_PRT_Type*) &HSIOM->PRT[8]) /* 0x40300080 */ +#define HSIOM_PRT9 ((HSIOM_PRT_Type*) &HSIOM->PRT[9]) /* 0x40300090 */ +#define HSIOM_PRT10 ((HSIOM_PRT_Type*) &HSIOM->PRT[10]) /* 0x403000A0 */ +#define HSIOM_PRT11 ((HSIOM_PRT_Type*) &HSIOM->PRT[11]) /* 0x403000B0 */ +#define HSIOM_PRT12 ((HSIOM_PRT_Type*) &HSIOM->PRT[12]) /* 0x403000C0 */ +#define HSIOM_PRT13 ((HSIOM_PRT_Type*) &HSIOM->PRT[13]) /* 0x403000D0 */ +#define HSIOM_PRT14 ((HSIOM_PRT_Type*) &HSIOM->PRT[14]) /* 0x403000E0 */ + +/******************************************************************************* +* GPIO +*******************************************************************************/ + +#define GPIO_BASE 0x40310000UL +#define GPIO ((GPIO_Type*) GPIO_BASE) /* 0x40310000 */ +#define GPIO_PRT0 ((GPIO_PRT_Type*) &GPIO->PRT[0]) /* 0x40310000 */ +#define GPIO_PRT1 ((GPIO_PRT_Type*) &GPIO->PRT[1]) /* 0x40310080 */ +#define GPIO_PRT2 ((GPIO_PRT_Type*) &GPIO->PRT[2]) /* 0x40310100 */ +#define GPIO_PRT3 ((GPIO_PRT_Type*) &GPIO->PRT[3]) /* 0x40310180 */ +#define GPIO_PRT4 ((GPIO_PRT_Type*) &GPIO->PRT[4]) /* 0x40310200 */ +#define GPIO_PRT5 ((GPIO_PRT_Type*) &GPIO->PRT[5]) /* 0x40310280 */ +#define GPIO_PRT6 ((GPIO_PRT_Type*) &GPIO->PRT[6]) /* 0x40310300 */ +#define GPIO_PRT7 ((GPIO_PRT_Type*) &GPIO->PRT[7]) /* 0x40310380 */ +#define GPIO_PRT8 ((GPIO_PRT_Type*) &GPIO->PRT[8]) /* 0x40310400 */ +#define GPIO_PRT9 ((GPIO_PRT_Type*) &GPIO->PRT[9]) /* 0x40310480 */ +#define GPIO_PRT10 ((GPIO_PRT_Type*) &GPIO->PRT[10]) /* 0x40310500 */ +#define GPIO_PRT11 ((GPIO_PRT_Type*) &GPIO->PRT[11]) /* 0x40310580 */ +#define GPIO_PRT12 ((GPIO_PRT_Type*) &GPIO->PRT[12]) /* 0x40310600 */ +#define GPIO_PRT13 ((GPIO_PRT_Type*) &GPIO->PRT[13]) /* 0x40310680 */ +#define GPIO_PRT14 ((GPIO_PRT_Type*) &GPIO->PRT[14]) /* 0x40310700 */ + +/******************************************************************************* +* SMARTIO +*******************************************************************************/ + +#define SMARTIO_BASE 0x40320000UL +#define SMARTIO ((SMARTIO_Type*) SMARTIO_BASE) /* 0x40320000 */ +#define SMARTIO_PRT9 ((SMARTIO_PRT_Type*) &SMARTIO->PRT[9]) /* 0x40320900 */ + +/******************************************************************************* +* LPCOMP +*******************************************************************************/ + +#define LPCOMP_BASE 0x40350000UL +#define LPCOMP ((LPCOMP_Type*) LPCOMP_BASE) /* 0x40350000 */ + +/******************************************************************************* +* CSD +*******************************************************************************/ + +#define CSD0_BASE 0x40360000UL +#define CSD0 ((CSD_Type*) CSD0_BASE) /* 0x40360000 */ + +/******************************************************************************* +* TCPWM +*******************************************************************************/ + +#define TCPWM0_BASE 0x40380000UL +#define TCPWM0 ((TCPWM_Type*) TCPWM0_BASE) /* 0x40380000 */ +#define TCPWM0_GRP0_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[0]) /* 0x40380000 */ +#define TCPWM0_GRP0_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[1]) /* 0x40380080 */ +#define TCPWM0_GRP0_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[2]) /* 0x40380100 */ +#define TCPWM0_GRP0_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[0].CNT[3]) /* 0x40380180 */ +#define TCPWM0_GRP1_CNT0 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[0]) /* 0x40388000 */ +#define TCPWM0_GRP1_CNT1 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[1]) /* 0x40388080 */ +#define TCPWM0_GRP1_CNT2 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[2]) /* 0x40388100 */ +#define TCPWM0_GRP1_CNT3 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[3]) /* 0x40388180 */ +#define TCPWM0_GRP1_CNT4 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[4]) /* 0x40388200 */ +#define TCPWM0_GRP1_CNT5 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[5]) /* 0x40388280 */ +#define TCPWM0_GRP1_CNT6 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[6]) /* 0x40388300 */ +#define TCPWM0_GRP1_CNT7 ((TCPWM_GRP_CNT_Type*) &TCPWM0->GRP[1].CNT[7]) /* 0x40388380 */ +#define TCPWM0_GRP0 ((TCPWM_GRP_Type*) &TCPWM0->GRP[0]) /* 0x40380000 */ +#define TCPWM0_GRP1 ((TCPWM_GRP_Type*) &TCPWM0->GRP[1]) /* 0x40388000 */ + +/******************************************************************************* +* LCD +*******************************************************************************/ + +#define LCD0_BASE 0x403B0000UL +#define LCD0 ((LCD_Type*) LCD0_BASE) /* 0x403B0000 */ + +/******************************************************************************* +* USBFS +*******************************************************************************/ + +#define USBFS0_BASE 0x403F0000UL +#define USBFS0 ((USBFS_Type*) USBFS0_BASE) /* 0x403F0000 */ +#define USBFS0_USBDEV ((USBFS_USBDEV_Type*) &USBFS0->USBDEV) /* 0x403F0000 */ +#define USBFS0_USBLPM ((USBFS_USBLPM_Type*) &USBFS0->USBLPM) /* 0x403F2000 */ +#define USBFS0_USBHOST ((USBFS_USBHOST_Type*) &USBFS0->USBHOST) /* 0x403F4000 */ + +/******************************************************************************* +* SMIF +*******************************************************************************/ + +#define SMIF0_BASE 0x40420000UL +#define SMIF0 ((SMIF_Type*) SMIF0_BASE) /* 0x40420000 */ +#define SMIF0_DEVICE0 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[0]) /* 0x40420800 */ +#define SMIF0_DEVICE1 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[1]) /* 0x40420880 */ +#define SMIF0_DEVICE2 ((SMIF_DEVICE_Type*) &SMIF0->DEVICE[2]) /* 0x40420900 */ + +/******************************************************************************* +* CANFD +*******************************************************************************/ + +#define CANFD0_BASE 0x40520000UL +#define CANFD0 ((CANFD_Type*) CANFD0_BASE) /* 0x40520000 */ +#define CANFD0_CH0_M_TTCAN ((CANFD_CH_M_TTCAN_Type*) &CANFD0->CH[0].M_TTCAN) /* 0x40520000 */ +#define CANFD0_CH0 ((CANFD_CH_Type*) &CANFD0->CH[0]) /* 0x40520000 */ + +/******************************************************************************* +* SCB +*******************************************************************************/ + +#define SCB0_BASE 0x40600000UL +#define SCB1_BASE 0x40610000UL +#define SCB2_BASE 0x40620000UL +#define SCB4_BASE 0x40640000UL +#define SCB5_BASE 0x40650000UL +#define SCB6_BASE 0x40660000UL +#define SCB0 ((CySCB_Type*) SCB0_BASE) /* 0x40600000 */ +#define SCB1 ((CySCB_Type*) SCB1_BASE) /* 0x40610000 */ +#define SCB2 ((CySCB_Type*) SCB2_BASE) /* 0x40620000 */ +#define SCB4 ((CySCB_Type*) SCB4_BASE) /* 0x40640000 */ +#define SCB5 ((CySCB_Type*) SCB5_BASE) /* 0x40650000 */ +#define SCB6 ((CySCB_Type*) SCB6_BASE) /* 0x40660000 */ + +/******************************************************************************* +* CTBM +*******************************************************************************/ + +#define CTBM0_BASE 0x40900000UL +#define CTBM0 ((CTBM_Type*) CTBM0_BASE) /* 0x40900000 */ + +/******************************************************************************* +* SAR +*******************************************************************************/ + +#define SAR0_BASE 0x409D0000UL +#define SAR1_BASE 0x409E0000UL +#define SAR0 ((SAR_Type*) SAR0_BASE) /* 0x409D0000 */ +#define SAR1 ((SAR_Type*) SAR1_BASE) /* 0x409E0000 */ + +/******************************************************************************* +* PASS +*******************************************************************************/ + +#define PASS_BASE 0x409F0000UL +#define PASS ((PASS_Type*) PASS_BASE) /* 0x409F0000 */ +#define PASS_TIMER ((PASS_TIMER_Type*) &PASS->TIMER) /* 0x409F0100 */ +#define PASS_LPOSC ((PASS_LPOSC_Type*) &PASS->LPOSC) /* 0x409F0200 */ +#define PASS_FIFO0 ((PASS_FIFO_Type*) &PASS->FIFO[0]) /* 0x409F0300 */ +#define PASS_FIFO1 ((PASS_FIFO_Type*) &PASS->FIFO[1]) /* 0x409F0400 */ +#define PASS_AREFV2 ((PASS_AREFV2_Type*) &PASS->AREFV2) /* 0x409F0E00 */ + +/** \} PSoC6A256K */ + +#endif /* _PSOC6A256K_H_ */ + + +/* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ble_clk.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ble_clk.h index b75868e107c..c23e6316f9e 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ble_clk.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_ble_clk.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_ble_clk.h -* \version 3.30 +* \version 3.40 * * The header file of the BLE ECO clock driver. * ******************************************************************************** * \copyright -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2017-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -70,6 +70,11 @@ * * * +* +* +* +* +* * * * @@ -127,7 +132,7 @@ extern "C" { #define CY_BLE_CLK_DRV_VERSION_MAJOR (3) /** Driver minor version */ -#define CY_BLE_CLK_DRV_VERSION_MINOR (20) +#define CY_BLE_CLK_DRV_VERSION_MINOR (40) /** Driver ID */ #define CY_BLE_CLK_ID (0x05UL << 18U) @@ -272,10 +277,28 @@ typedef struct * \{ */ cy_en_ble_eco_status_t Cy_BLE_EcoConfigure(cy_en_ble_eco_freq_t freq, - cy_en_ble_eco_sys_clk_div_t sysClkDiv, - uint32_t cLoad, uint32_t xtalStartUpTime, - cy_en_ble_eco_voltage_reg_t voltageReg); + cy_en_ble_eco_sys_clk_div_t sysClkDiv, + uint32_t cLoad, + uint32_t xtalStartUpTime, + cy_en_ble_eco_voltage_reg_t voltageReg); void Cy_BLE_EcoReset(void); +__STATIC_INLINE bool Cy_BLE_EcoIsEnabled(void); + + +/******************************************************************************* +* Function Name: Cy_BLE_EcoIsEnabled +****************************************************************************//** +* +* Reports the Enabled/Disabled BLE ECO status. +* +* \return Boolean status of BLE ECO: true - Enabled, false - Disabled. +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_BLE_EcoIsEnabled(void) +{ + return (((BLE_BLESS_MT_CFG & BLE_BLESS_MT_CFG_ENABLE_BLERD_Msk) != 0u) && + ((BLE_BLESS_MT_STATUS & BLE_BLESS_MT_STATUS_BLESS_STATE_Msk) != 0u)); +} /** \} */ /** \cond INTERNAL */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_canfd.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_canfd.h index 09dd4119d6d..d551291f59b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_canfd.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_canfd.h @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_canfd.h -* \version 1.0.1 +* \version 1.10 * * This file provides constants and parameter values for * the CAN FD driver. * ******************************************************************************** * \copyright -* Copyright 2019 Cypress Semiconductor Corporation +* Copyright 2019-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -217,6 +217,11 @@ *
VersionChangesReason of Change
3.40A new API function \ref Cy_BLE_EcoIsEnabled() is added.API enhancement.
3.30Updated the \ref Cy_BLE_EcoConfigure() to reuse the \ref Cy_SysClk_ClkPeriGetFrequency().API enhancement.
* * +* +* +* +* +* * * * @@ -266,7 +271,7 @@ extern "C" { #define CY_CANFD_DRV_VERSION_MAJOR 1U /** Driver minor version */ -#define CY_CANFD_DRV_VERSION_MINOR 0U +#define CY_CANFD_DRV_VERSION_MINOR 10U /** CAN FD driver ID */ #define CY_CANFD_ID CY_PDL_DRV_ID (0x45U) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_device.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_device.h index 1f2060bf82a..d438e510a19 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_device.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_device.h @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2019 Cypress Semiconductor Corporation +* Copyright 2018-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -200,6 +200,7 @@ typedef struct extern const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_01; extern const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_02; extern const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_03; +extern const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_04; extern const cy_stc_device_t * cy_device; @@ -1084,26 +1085,26 @@ void Cy_PDL_Init(const cy_stc_device_t * device); * BLE *******************************************************************************/ -#define BLE_RCB_INTR (((BLE_V1_Type *) BLE)->RCB.INTR) -#define BLE_RCB_TX_FIFO_WR (((BLE_V1_Type *) BLE)->RCB.TX_FIFO_WR) -#define BLE_RCB_RX_FIFO_RD (((BLE_V1_Type *) BLE)->RCB.RX_FIFO_RD) -#define BLE_RCB_CTRL (((BLE_V1_Type *) BLE)->RCB.CTRL) -#define BLE_RCB_RCBLL_CTRL (((BLE_V1_Type *) BLE)->RCB.RCBLL.CTRL) -#define BLE_BLESS_XTAL_CLK_DIV_CONFIG (((BLE_V1_Type *) BLE)->BLESS.XTAL_CLK_DIV_CONFIG) -#define BLE_BLESS_MT_CFG (((BLE_V1_Type *) BLE)->BLESS.MT_CFG) -#define BLE_BLESS_MT_STATUS (((BLE_V1_Type *) BLE)->BLESS.MT_STATUS) -#define BLE_BLESS_MT_DELAY_CFG (((BLE_V1_Type *) BLE)->BLESS.MT_DELAY_CFG) -#define BLE_BLESS_MT_DELAY_CFG2 (((BLE_V1_Type *) BLE)->BLESS.MT_DELAY_CFG2) -#define BLE_BLESS_MT_DELAY_CFG3 (((BLE_V1_Type *) BLE)->BLESS.MT_DELAY_CFG3) -#define BLE_BLESS_MT_VIO_CTRL (((BLE_V1_Type *) BLE)->BLESS.MT_VIO_CTRL) -#define BLE_BLESS_LL_CLK_EN (((BLE_V1_Type *) BLE)->BLESS.LL_CLK_EN) -#define BLE_BLESS_MISC_EN_CTRL (((BLE_V1_Type *) BLE)->BLESS.MISC_EN_CTRL) -#define BLE_BLESS_INTR_STAT (((BLE_V1_Type *) BLE)->BLESS.INTR_STAT) -#define BLE_BLELL_EVENT_INTR (((BLE_V1_Type *) BLE)->BLELL.EVENT_INTR) -#define BLE_BLELL_CONN_INTR (((BLE_V1_Type *) BLE)->BLELL.CONN_INTR) -#define BLE_BLELL_CONN_EXT_INTR (((BLE_V1_Type *) BLE)->BLELL.CONN_EXT_INTR) -#define BLE_BLELL_SCAN_INTR (((BLE_V1_Type *) BLE)->BLELL.SCAN_INTR) -#define BLE_BLELL_ADV_INTR (((BLE_V1_Type *) BLE)->BLELL.ADV_INTR) +#define BLE_RCB_INTR (((BLE_V1_Type *) BLE_BASE)->RCB.INTR) +#define BLE_RCB_TX_FIFO_WR (((BLE_V1_Type *) BLE_BASE)->RCB.TX_FIFO_WR) +#define BLE_RCB_RX_FIFO_RD (((BLE_V1_Type *) BLE_BASE)->RCB.RX_FIFO_RD) +#define BLE_RCB_CTRL (((BLE_V1_Type *) BLE_BASE)->RCB.CTRL) +#define BLE_RCB_RCBLL_CTRL (((BLE_V1_Type *) BLE_BASE)->RCB.RCBLL.CTRL) +#define BLE_BLESS_XTAL_CLK_DIV_CONFIG (((BLE_V1_Type *) BLE_BASE)->BLESS.XTAL_CLK_DIV_CONFIG) +#define BLE_BLESS_MT_CFG (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_CFG) +#define BLE_BLESS_MT_STATUS (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_STATUS) +#define BLE_BLESS_MT_DELAY_CFG (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_DELAY_CFG) +#define BLE_BLESS_MT_DELAY_CFG2 (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_DELAY_CFG2) +#define BLE_BLESS_MT_DELAY_CFG3 (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_DELAY_CFG3) +#define BLE_BLESS_MT_VIO_CTRL (((BLE_V1_Type *) BLE_BASE)->BLESS.MT_VIO_CTRL) +#define BLE_BLESS_LL_CLK_EN (((BLE_V1_Type *) BLE_BASE)->BLESS.LL_CLK_EN) +#define BLE_BLESS_MISC_EN_CTRL (((BLE_V1_Type *) BLE_BASE)->BLESS.MISC_EN_CTRL) +#define BLE_BLESS_INTR_STAT (((BLE_V1_Type *) BLE_BASE)->BLESS.INTR_STAT) +#define BLE_BLELL_EVENT_INTR (((BLE_V1_Type *) BLE_BASE)->BLELL.EVENT_INTR) +#define BLE_BLELL_CONN_INTR (((BLE_V1_Type *) BLE_BASE)->BLELL.CONN_INTR) +#define BLE_BLELL_CONN_EXT_INTR (((BLE_V1_Type *) BLE_BASE)->BLELL.CONN_EXT_INTR) +#define BLE_BLELL_SCAN_INTR (((BLE_V1_Type *) BLE_BASE)->BLELL.SCAN_INTR) +#define BLE_BLELL_ADV_INTR (((BLE_V1_Type *) BLE_BASE)->BLELL.ADV_INTR) /******************************************************************************* diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_efuse.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_efuse.h index cb14d9c97fb..caa6a62517c 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_efuse.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_efuse.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_efuse.h -* \version 1.10.1 +* \version 1.10.2 * * Provides the API declarations of the eFuse driver. * @@ -85,6 +85,11 @@ *
VersionChangesReason for Change
1.10Updated of the \ref Cy_CANFD_Init() functionsAllow initing CANFD with 0 number of SID/XID filters
1.0.1Updated description of the \ref Cy_CANFD_Init() and \ref Cy_CANFD_DeInit() functionsDocumentation update and clarification
* * +* +* +* +* +* * * * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_flash.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_flash.h index f39679c5a6b..582734bbe55 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_flash.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_flash.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_flash.h -* \version 3.30.3 +* \version 3.30.4 * * Provides the API declarations of the Flash driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -42,8 +42,8 @@ * or modify the SROM code. The driver API requests the system call by acquiring * the Inter-processor communication (IPC) and writing the SROM function opcode * and parameters to its input registers. As a result, an NMI interrupt is invoked -* and the requested SROM API is executed. The operation status is returned to the -* driver context and a release interrupt is triggered. +* and the requested SROM function is executed. The operation status is returned +* to the driver context and a release interrupt is triggered. * * Writing to flash can take up to 20 milliseconds. During this time, * the device should not be reset (including XRES pin, software reset, and @@ -55,7 +55,7 @@ * in the same or neighboring (neighboring restriction is applicable just for the * CY8C6xx6, CY8C6xx7 devices) flash sector where the flash Write, Erase, or * Program operation is working. This violation may cause a HardFault exception. -* To avoid the Read while Write violation, the user must carefully split the +* To avoid the Read while Write violation, carefully split the * Read and Write operation on flash sectors which are not neighboring, * considering both cores in the multi-processor device. If the flash is divided * into four equal sectors, you may edit the linker script to place the code @@ -66,18 +66,18 @@ * * \subsection group_flash_config_intro Introduction: * The PSoC 6 MCU user-programmable Flash consists of: -* - User Flash sectors (from 4 to 8) - 256KB each. -* - EEPROM emulation sector - 32KB. +* - Application flash memory (from 2 to 8 sectors) - 128KB/256KB each. +* - EE emulation flash memory - 32KB. * -* Write operations are performed on a per-sector basis and may be done as -* Blocking or Partially Blocking, defined as follows: +* Write operation may be done as Blocking or Partially Blocking, +* defined as follows: * * \subsection group_flash_config_blocking Blocking: * In this case, the entire Flash block is not available for the duration of the * Write (∼16ms). Therefore, no Flash accesses (from any Bus Master) can * occur during that time. CPU execution can be performed from SRAM. All -* pre-fetching must be disabled. Application code execution from Flash is -* blocked for the Flash Write duration for both cores. +* pre-fetching must be disabled. Code execution from Flash is blocked for the +* Flash Write duration for both cores. * * \subsection group_flash_config_block_const Constraints for Blocking Flash operations: * -# During write to flash, the device should not be reset (including XRES pin, @@ -85,16 +85,16 @@ * of the flash. * -# The low-voltage detect circuits should be configured to generate an * interrupt instead of a reset. -* -# Flash write operation is allowed only in one of the following CM4 states: +* -# Flash rite operation is allowed only in one of the following CM4 states: * -# CM4 is Active and initialized:
* call \ref Cy_SysEnableCM4 "Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR)". * Note: If desired user may put CM4 core in Deep Sleep any time * after calling Cy_SysEnableCM4(). -* -# CM4 is Off:
+* -# CM4 is Off and disabled:
* call Cy_SysDisableCM4(). Note: In this state Debug mode is not * supported. * . -* -# Flash write cannot be performed in ULP (core voltage 0.9V) mode. +* -# Flash Write cannot be performed in Ultra Low Power (core voltage 0.9V) mode. * -# Interrupts must be enabled on both active cores. Do not enter a critical * section during flash operation. * -# For the CY8C6xx6, CY8C6xx7 devices user must guarantee that system pipe @@ -115,8 +115,7 @@ * sequence used. * * For API sequence Cy_Flash_StartEraseRow() + Cy_Flash_StartProgram() there are -* four block-out regions during which the read is blocked using the software -* driver (PDL). See Figure 1. +* four block-out regions during which Read is blocked. See Figure 1. * *
*
VersionChangesReason for Change
1.10.2Fix driver header path.Folder structure changed.
1.10.1Added header guard CY_IP_MXEFUSE.To enable the PDL compilation with wounded out IP blocks.
@@ -150,7 +149,7 @@ *
* * -* This allows both cores to execute an application for about 80% of Flash Write +* This allows both cores to execute for about 80% of Flash Write * operation - see Figure 1. * This capability is important for communication protocols that rely on fast * response. @@ -167,9 +166,9 @@ * The core that performs read/execute is blocked identically to the previous * scenario - see Figure 1. * -* This allows the core that initiates Cy_Flash_StartWrite() to execute an -* application for about 20% of the Flash Write operation. The other core executes -* the application for about 80% of the Flash Write operation. +* This allows the core that initiates Cy_Flash_StartWrite() to execute for about +* 20% of Flash Write operation. The other core executes for about 80% of Flash +* Write operation. * * Some constraints must be planned for in the Partially Blocking mode which are * described in detail below. @@ -190,7 +189,7 @@ * call \ref Cy_SysEnableCM4 "Cy_SysEnableCM4(CY_CORTEX_M4_APPL_ADDR)". * Note: If desired user may put CM4 core in Deep Sleep any time * after calling Cy_SysEnableCM4(). -* -# CM4 is Off:
+* -# CM4 is Off and disabled:
* call Cy_SysDisableCM4(). Note: In this state Debug mode is not * supported. * . @@ -198,8 +197,8 @@ * read of any bus master: CM0+, CM4, DMA, Crypto, etc.) * -# Do not write to and read/execute from the same flash sector at the same * time. This is true for all sectors. -* -# Writing rules in User Flash (this restriction is applicable just for the -* CY8C6xx6, CY8C6xx7 devices): +* -# Writing rules in application flash (this restriction is applicable just +* for CY8C6xx6, CY8C6xx7 devices): * -# Any bus master can read/execute from UFLASH S0 and/or S1, during * flash write to UFLASH S2 or S3. * -# Any bus master can read/execute from UFLASH S2 and/or S3, during @@ -209,16 +208,13 @@ * code for CM4 in either S0 or S1. CM0+ code resides in S0. Write data * to S2 and S3 sections. * . -* -# Flash write cannot be performed in ULP mode (core voltage 0.9V). +* -# Flash Write cannot be performed in Ultra Low Power mode (core voltage 0.9V). * -# Interrupts must be enabled on both active cores. Do not enter a critical * section during flash operation. * -# For the CY8C6xx6, CY8C6xx7 devices user must guarantee that system pipe * interrupts (IPC interrupts 3 and 4) have the highest priority, or at * least that pipe interrupts are not interrupted or in a pending state * for more than 700 µs. -* -# User must guarantee that during flash write operation no flash read -* operations are performed by bus masters other than CM0+ and CM4 -* (DMA and Crypto). * -# If you do not use the default startup, perform the following steps * before any flash write/erase operations: * \snippet flash/snippet/main.c Flash Initialization @@ -260,6 +256,11 @@ * * * +* +* +* +* +* * * * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_prot.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_prot.h index c51985c4211..b4ba383adfc 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_prot.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_prot.h @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_prot.h -* \version 1.30.1 +* \version 1.30.2 * * \brief * Provides an API declaration of the Protection Unit driver * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -390,6 +390,12 @@ *
VersionChangesReason for Change
3.30.4Improved documentation.User experience enhancement.
3.30.3Updated documentation to limit devices with the restrictions. Improved calculation of the CY_FLASH_DELAY_CORRECTIVE macro.User experience enhancement.
* * +* +* +* +* +* * * * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_rtc.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_rtc.h index 36cac15f575..f8b90ae8a7a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_rtc.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_rtc.h @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_rtc.h -* \version 2.20.1 +* \version 2.30 * * This file provides constants and parameter values for the APIs for the * Real-Time Clock (RTC). * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -228,6 +228,18 @@ *
VersionChangesReason for Change
1.30.2Clarified the description of the next API functions: \ref Cy_Prot_ConfigPpuProgMasterAtt,\n +* \ref Cy_Prot_ConfigPpuProgSlaveAtt, \ref Cy_Prot_ConfigPpuFixedMasterAtt, \ref Cy_Prot_ConfigPpuFixedSlaveAtt.API enhancement based on usability feedback.
1.30.1Snippet updated.Old snippet outdated.
* * +* +* +* +* +* * * * @@ -326,7 +338,7 @@ extern "C" { #define CY_RTC_DRV_VERSION_MAJOR 2 /** Driver minor version */ -#define CY_RTC_DRV_VERSION_MINOR 20 +#define CY_RTC_DRV_VERSION_MINOR 30 /** \} group_rtc_macros */ /******************************************************************************* @@ -548,8 +560,6 @@ cy_en_rtc_status_t Cy_RTC_SetAlarmDateAndTimeDirect(uint32_t sec, uint32_t min, * \{ */ cy_en_rtc_status_t Cy_RTC_EnableDstTime(cy_stc_rtc_dst_t const *dstTime, cy_stc_rtc_config_t const *timeDate); -cy_en_rtc_status_t Cy_RTC_SetNextDstTime(cy_stc_rtc_dst_format_t const *nextDst); -bool Cy_RTC_GetDstStatus(cy_stc_rtc_dst_t const *dstTime, cy_stc_rtc_config_t const *timeDate); /** \} group_rtc_dst_functions */ /** @@ -594,6 +604,9 @@ __STATIC_INLINE bool Cy_RTC_IsExternalResetOccurred(void); __STATIC_INLINE void Cy_RTC_SyncToRtcAhbDateAndTime(uint32_t timeBcd, uint32_t dateBcd); __STATIC_INLINE void Cy_RTC_SyncToRtcAhbAlarm(uint32_t alarmTimeBcd, uint32_t alarmDateBcd, cy_en_rtc_alarm_t alarmIndex); + +cy_en_rtc_status_t Cy_RTC_SetNextDstTime(cy_stc_rtc_dst_format_t const *nextDst); +bool Cy_RTC_GetDstStatus(cy_stc_rtc_dst_t const *dstTime, cy_stc_rtc_config_t const *timeDate); /** \} group_rtc_low_level_functions */ /** \} group_rtc_functions */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif.h index c109bac0450..606d8204c57 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_smif.h -* \version 1.40.1 +* \version 1.50 * * Provides an API declaration of the Cypress SMIF driver. * @@ -214,6 +214,15 @@ *
VersionChangesReason for Change
2.30 +* * Corrected the Cy_RTC_GetDstStatus() and Cy_RTC_SetNextDstTime() +* documentation. +* * Fixed the Cy_RTC_GetDstStatus() behaviour in the 'an hour before/after the DST stop event' period. +* +* * Collateral Review: user experience enhancement. +* * Bug fix. +*
2.20.1Modified header guard CY_IP_MXS40SRSS_RTC.To enable the PDL compilation with wounded out IP blocks.
* * +* +* +* +* +* * * * @@ -450,7 +459,7 @@ extern "C" { #define CY_SMIF_DRV_VERSION_MAJOR 1 /** The driver minor version */ -#define CY_SMIF_DRV_VERSION_MINOR 40 +#define CY_SMIF_DRV_VERSION_MINOR 50 /** One microsecond timeout for Cy_SMIF_TimeoutRun() */ #define CY_SMIF_WAIT_1_UNIT (1U) @@ -679,6 +688,8 @@ typedef enum CY_SMIF_NO_QE_BIT = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x03U, CY_SMIF_BAD_PARAM = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x04U, /**< The SMIF API received the wrong parameter */ CY_SMIF_NO_SFDP_SUPPORT = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x05U, /**< The external memory does not support SFDP (JESD216B). */ + CY_SMIF_NOT_HYBRID_MEM = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x06U, /**< The external memory is not hybrid */ + CY_SMIF_SFDP_CORRUPTED_TABLE = CY_SMIF_ID |CY_PDL_STATUS_ERROR | 0x07U, /**< The SFDP table is corrupted */ /** Failed to initialize the slave select 0 external memory by auto detection (SFDP). */ CY_SMIF_SFDP_SS0_FAILED = CY_SMIF_ID |CY_PDL_STATUS_ERROR | ((uint32_t)CY_SMIF_SFDP_FAIL << CY_SMIF_SFDP_FAIL_SS0_POS), diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif_memslot.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif_memslot.h index b4f1d2760de..69341a275f7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif_memslot.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_smif_memslot.h @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_smif_memslot.h -* \version 1.40.1 +* \version 1.50 * * \brief * This file provides the constants and parameter values for the memory-level @@ -201,11 +201,24 @@ extern "C" { #define CY_SMIF_SFDP_BFPT_BYTE_23 (0x23U) /**< The byte 0x23 of the JEDEC Basic Flash Parameter Table */ #define CY_SMIF_SFDP_BFPT_BYTE_28 (0x28U) /**< The byte 0x28 of the JEDEC Basic Flash Parameter Table */ #define CY_SMIF_SFDP_BFPT_BYTE_3A (0x3AU) /**< The byte 0x3A of the JEDEC Basic Flash Parameter Table */ +#define CY_SMIF_SFDP_BFPT_BYTE_3C (0x3CU) /**< The byte 0x3C of the JEDEC Basic Flash Parameter Table */ #define CY_SMIF_SFDP_BFPT_ERASE_BYTE (36U) /**< The byte 36 of the JEDEC Basic Flash Parameter Table */ #define CY_SMIF_JEDEC_BFPT_10TH_DWORD (9U) /**< Offset to JEDEC Basic Flash Parameter Table: 10th DWORD */ #define CY_SMIF_JEDEC_BFPT_11TH_DWORD (10U) /**< Offset to JEDEC Basic Flash Parameter Table: 11th DWORD */ + +#define CY_SMIF_SFDP_SECTOR_MAP_CMD_OFFSET (1UL) /**< The offset for the detection command instruction in the Sector Map command descriptor */ +#define CY_SMIF_SFDP_SECTOR_MAP_ADDR_CODE_OFFSET (2UL) /**< The offset for the detection command address length in the Sector Map command descriptor */ +#define CY_SMIF_SFDP_SECTOR_MAP_REG_MSK_OFFSET (3UL) /**< The offset for the read data mask in the Sector Map command descriptor */ +#define CY_SMIF_SFDP_SECTOR_MAP_REG_ADDR_OFFSET (4UL) /**< The offset for the detection command address in the Sector Map command descriptor */ +#define CY_SMIF_SFDP_SECTOR_MAP_REGION_COUNT_OFFSET (2UL) /**< The offset for the regions count in the Sector Map descriptor */ +#define CY_SMIF_SFDP_SECTOR_MAP_CONFIG_ID_OFFSET (2UL) /**< The offset for the configuration ID in the Sector Map descriptor */ +#define CY_SMIF_SFDP_SECTOR_MAP_SUPPORTED_ET_MASK (0xFU) /**< The mask for the supported erase type code in the Sector Map descriptor */ +#define CY_SMIF_SFDP_SECTOR_MAP_ADDR_BYTES_Msk (0xC0UL) /**< The mask for the configuration detection command address bytes in the Sector Map descriptor */ +#define CY_SMIF_SFDP_SECTOR_MAP_ADDR_BYTES_Pos (6UL) /**< The position of the configuration detection command address bytes in the Sector Map descriptor */ + + /* ---------------------------- 1st DWORD ---------------------------- */ #define CY_SMIF_SFDP_FAST_READ_1_1_4_Pos (6UL) /**< The SFDP 1-1-4 fast read support (Bit 6) */ #define CY_SMIF_SFDP_FAST_READ_1_1_4_Msk (0x40UL) /**< The SFDP 1-1-4 fast read support (Bitfield-Mask: 0x01) */ @@ -268,6 +281,14 @@ extern "C" { #define CY_SMIF_SFDP_QE_REQUIREMENTS_Pos (4UL) /**< The SFDP quad enable requirements field (Bit 4) */ #define CY_SMIF_SFDP_QE_REQUIREMENTS_Msk (0x70UL) /**< The SFDP quad enable requirements field (Bitfield-Mask: 0x07) */ + +/* ---------------------------- 16th DWORD --------------------------- */ +#define CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_B7 (1U) /**< Issue 0xB7 instruction */ +#define CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_WR_EN_B7 (2U) /**< Issue write enable instruction followed with 0xB7 */ +#define CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_ALWAYS_4_BYTE (0x40U) /**< Memory always operates in 4-byte mode */ +#define CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_B7_CMD (0xB7U) /**< The instruction required to enter 4-byte addressing mode */ + + /** \cond INTERNAL */ /******************************************************************************* * These are legacy constants and API. They are left here just @@ -327,6 +348,16 @@ typedef struct cy_en_smif_txfr_width_t dataWidth; /**< The width of the data transfer */ } cy_stc_smif_mem_cmd_t; +/** This structure specifies data used for memory with hybrid sectors */ +typedef struct +{ + uint32_t regionAddress; /**< This specifies the address where a region starts */ + uint32_t sectorsCount; /**< This specifies the number of sectors in the region */ + uint32_t eraseCmd; /**< This specifies the region specific erase instruction*/ + uint32_t eraseSize; /**< This specifies the size of one sector */ + uint32_t eraseTime; /**< Max time for sector erase type 1 cycle time in ms*/ +} cy_stc_smif_hybrid_region_info_t; + /** * @@ -337,31 +368,33 @@ typedef struct */ typedef struct { - uint32_t numOfAddrBytes; /**< This specifies the number of address bytes used by the - * memory slave device, valid values 1-4 */ - uint32_t memSize; /**< The memory size: For densities of 2 gigabits or less - the size in bytes; - * For densities 4 gigabits and above - bit-31 is set to 1b to define that - * this memory is 4 gigabits and above; and other 30:0 bits define N where - * the density is computed as 2^N bytes. - * For example, 0x80000021 corresponds to 2^30 = 1 gigabyte. - */ - cy_stc_smif_mem_cmd_t* readCmd; /**< This specifies the Read command */ - cy_stc_smif_mem_cmd_t* writeEnCmd; /**< This specifies the Write Enable command */ - cy_stc_smif_mem_cmd_t* writeDisCmd; /**< This specifies the Write Disable command */ - cy_stc_smif_mem_cmd_t* eraseCmd; /**< This specifies the Erase command */ - uint32_t eraseSize; /**< This specifies the sector size of each Erase */ - cy_stc_smif_mem_cmd_t* chipEraseCmd; /**< This specifies the Chip Erase command */ - cy_stc_smif_mem_cmd_t* programCmd; /**< This specifies the Program command */ - uint32_t programSize; /**< This specifies the page size for programming */ - cy_stc_smif_mem_cmd_t* readStsRegWipCmd; /**< This specifies the command to read the WIP-containing status register */ - cy_stc_smif_mem_cmd_t* readStsRegQeCmd; /**< This specifies the command to read the QE-containing status register */ - cy_stc_smif_mem_cmd_t* writeStsRegQeCmd; /**< This specifies the command to write into the QE-containing status register */ - cy_stc_smif_mem_cmd_t* readSfdpCmd; /**< This specifies the read SFDP command */ - uint32_t stsRegBusyMask; /**< The Busy mask for the status registers */ - uint32_t stsRegQuadEnableMask; /**< The QE mask for the status registers */ - uint32_t eraseTime; /**< Max time for erase type 1 cycle time in ms */ - uint32_t chipEraseTime; /**< Max time for chip erase cycle time in ms */ - uint32_t programTime; /**< Max time for page program cycle time in us */ + uint32_t numOfAddrBytes; /**< This specifies the number of address bytes used by the + * memory slave device, valid values 1-4 */ + uint32_t memSize; /**< The memory size: For densities of 2 gigabits or less - the size in bytes; + * For densities 4 gigabits and above - bit-31 is set to 1b to define that + * this memory is 4 gigabits and above; and other 30:0 bits define N where + * the density is computed as 2^N bytes. + * For example, 0x80000021 corresponds to 2^30 = 1 gigabyte. + */ + cy_stc_smif_mem_cmd_t* readCmd; /**< This specifies the Read command */ + cy_stc_smif_mem_cmd_t* writeEnCmd; /**< This specifies the Write Enable command */ + cy_stc_smif_mem_cmd_t* writeDisCmd; /**< This specifies the Write Disable command */ + cy_stc_smif_mem_cmd_t* eraseCmd; /**< This specifies the Erase command */ + uint32_t eraseSize; /**< This specifies the sector size of each Erase */ + cy_stc_smif_mem_cmd_t* chipEraseCmd; /**< This specifies the Chip Erase command */ + cy_stc_smif_mem_cmd_t* programCmd; /**< This specifies the Program command */ + uint32_t programSize; /**< This specifies the page size for programming */ + cy_stc_smif_mem_cmd_t* readStsRegWipCmd; /**< This specifies the command to read the WIP-containing status register */ + cy_stc_smif_mem_cmd_t* readStsRegQeCmd; /**< This specifies the command to read the QE-containing status register */ + cy_stc_smif_mem_cmd_t* writeStsRegQeCmd; /**< This specifies the command to write into the QE-containing status register */ + cy_stc_smif_mem_cmd_t* readSfdpCmd; /**< This specifies the read SFDP command */ + uint32_t stsRegBusyMask; /**< The Busy mask for the status registers */ + uint32_t stsRegQuadEnableMask; /**< The QE mask for the status registers */ + uint32_t eraseTime; /**< Max time for erase type 1 cycle time in ms */ + uint32_t chipEraseTime; /**< Max time for chip erase cycle time in ms */ + uint32_t programTime; /**< Max time for page program cycle time in us */ + uint32_t hybridRegionCount; /**< This specifies the number of regions for memory with hybrid sectors */ + cy_stc_smif_hybrid_region_info_t** hybridRegionInfo; /**< This specifies data for memory with hybrid sectors */ } cy_stc_smif_mem_device_cfg_t; @@ -490,7 +523,8 @@ cy_en_smif_status_t Cy_SMIF_MemEraseSector(SMIF_Type *base, cy_stc_smif_mem_conf cy_stc_smif_context_t const *context); cy_en_smif_status_t Cy_SMIF_MemEraseChip(SMIF_Type *base, cy_stc_smif_mem_config_t const *memConfig, cy_stc_smif_context_t const *context); - +cy_en_smif_status_t Cy_SMIF_MemLocateHybridRegion(cy_stc_smif_mem_config_t const *memDevice, + cy_stc_smif_hybrid_region_info_t** regionInfo, uint32_t address); /** \} group_smif_mem_slot_functions */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysclk.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysclk.h index f49264089bf..9123dbccfb0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysclk.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_sysclk.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_sysclk.h -* \version 1.50 +* \version 1.60 * * Provides an API declaration of the sysclk driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -43,8 +43,8 @@ * clock system. * * The PDL defines clock system capabilities in:\n -* devices\//include\_config.h. (E.g. -* devices/psoc6/include/psoc6_01_config.h). +* devices/include/\_config.h. (E.g. +* devices/include/psoc6_01_config.h). * User-configurable clock speeds are defined in the file system_.h. * * As an illustration of the clocking system, the following diagram shows the @@ -104,6 +104,15 @@ *
VersionChangesReason for Change
1.50Added a new function: \ref Cy_SMIF_MemLocateHybridRegion.\n +* Added a new structure \ref cy_stc_smif_hybrid_region_info_t.\n +* Updated the \ref Cy_SMIF_MemEraseSector and \ref Cy_SMIF_MemCmdSectorErase functions.\n +* Updated the \ref Cy_SMIF_MemSfdpDetect function. \n +* Updated the \ref cy_stc_smif_mem_device_cfg_t structure.Support for memories with hybrid regions.
1.40.1The \ref Cy_SMIF_MemInit is changed. Corrected a false assertion during initialization in SFDP mode.
* * +* +* +* +* +* * * * @@ -277,7 +286,7 @@ * - IMO: 8 MHz Internal Main Oscillator (Default) * - EXTCLK: External clock (signal brought in through dedicated pins) * - ECO: External Crystal Oscillator (requires external crystal on dedicated pins) -* - ALTHF: Select on-chip signals (e.g. BLE ECO) +* - ALTHF: Select on-chip signals (e.g. \ref group_ble_clk) * - Digital Signal (DSI): Digital signal from a UDB source * * Some clock paths such as path 0 and path 1 have additional resources @@ -559,6 +568,13 @@ * ![](sysclk_slow.png) * * \defgroup group_sysclk_clk_slow_funcs Functions +* \} + * \defgroup group_sysclk_alt_hf Alternative High-Frequency Clock +* \{ +* In the BLE-enabled PSoC6 devices, the \ref group_ble_clk clock is +* connected to the system Alternative High-Frequency Clock input. +* +* \defgroup group_sysclk_alt_hf_funcs Functions * \} * \defgroup group_sysclk_clk_lf Low-Frequency Clock * \{ @@ -642,7 +658,7 @@ extern "C" { /** Driver major version */ #define CY_SYSCLK_DRV_VERSION_MAJOR 1 /** Driver minor version */ -#define CY_SYSCLK_DRV_VERSION_MINOR 40 +#define CY_SYSCLK_DRV_VERSION_MINOR 60 /** Sysclk driver identifier */ #define CY_SYSCLK_ID CY_PDL_DRV_ID(0x12U) @@ -685,6 +701,7 @@ typedef enum * \{ */ void Cy_SysClk_ExtClkSetFrequency(uint32_t freq); +uint32_t Cy_SysClk_ExtClkGetFrequency(void); /** \} group_sysclk_ext_funcs */ /* ========================================================================== */ @@ -719,6 +736,7 @@ void Cy_SysClk_ExtClkSetFrequency(uint32_t freq); */ cy_en_sysclk_status_t Cy_SysClk_EcoConfigure(uint32_t freq, uint32_t cLoad, uint32_t esr, uint32_t driveLevel); cy_en_sysclk_status_t Cy_SysClk_EcoEnable(uint32_t timeoutus); +uint32_t Cy_SysClk_EcoGetFrequency(void); __STATIC_INLINE void Cy_SysClk_EcoDisable(void); __STATIC_INLINE uint32_t Cy_SysClk_EcoGetStatus(void); @@ -802,6 +820,8 @@ typedef enum */ cy_en_sysclk_status_t Cy_SysClk_ClkPathSetSource(uint32_t clkPath, cy_en_clkpath_in_sources_t source); cy_en_clkpath_in_sources_t Cy_SysClk_ClkPathGetSource(uint32_t clkPath); +uint32_t Cy_SysClk_ClkPathMuxGetFrequency(uint32_t clkPath); +uint32_t Cy_SysClk_ClkPathGetFrequency(uint32_t clkPath); /** \} group_sysclk_path_src_funcs */ @@ -1121,9 +1141,11 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_PllDisable(uint32_t clkPath) * \{ */ __STATIC_INLINE void Cy_SysClk_IloEnable(void); +__STATIC_INLINE bool Cy_SysClk_IloIsEnabled(void); __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_IloDisable(void); __STATIC_INLINE void Cy_SysClk_IloHibernateOn(bool on); + /******************************************************************************* * Function Name: Cy_SysClk_IloEnable ****************************************************************************//** @@ -1142,6 +1164,24 @@ __STATIC_INLINE void Cy_SysClk_IloEnable(void) } +/******************************************************************************* +* Function Name: Cy_SysClk_IloIsEnabled +****************************************************************************//** +* +* Reports the Enabled/Disabled status of the ILO. +* +* \return Boolean status of ILO: true - Enabled, false - Disabled. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_IloDisable +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SysClk_IloIsEnabled(void) +{ + return (_FLD2BOOL(SRSS_CLK_ILO_CONFIG_ENABLE, SRSS_CLK_ILO_CONFIG)); +} + + /******************************************************************************* * Function Name: Cy_SysClk_IloDisable ****************************************************************************//** @@ -1204,6 +1244,7 @@ __STATIC_INLINE void Cy_SysClk_IloHibernateOn(bool on) * \{ */ __STATIC_INLINE void Cy_SysClk_PiloEnable(void); +__STATIC_INLINE bool Cy_SysClk_PiloIsEnabled(void); __STATIC_INLINE void Cy_SysClk_PiloDisable(void); __STATIC_INLINE void Cy_SysClk_PiloSetTrim(uint32_t trimVal); __STATIC_INLINE uint32_t Cy_SysClk_PiloGetTrim(void); @@ -1223,7 +1264,7 @@ __STATIC_INLINE uint32_t Cy_SysClk_PiloGetTrim(void); *******************************************************************************/ __STATIC_INLINE void Cy_SysClk_PiloEnable(void) { - SRSS_CLK_PILO_CONFIG |= _VAL2FLD(SRSS_CLK_PILO_CONFIG_PILO_EN, 1U); /* 1 = enable */ + SRSS_CLK_PILO_CONFIG |= SRSS_CLK_PILO_CONFIG_PILO_EN_Msk; /* 1 = enable */ Cy_SysLib_Delay(1U/*msec*/); /* release the reset and enable clock output */ SRSS_CLK_PILO_CONFIG |= SRSS_CLK_PILO_CONFIG_PILO_RESET_N_Msk | @@ -1231,6 +1272,24 @@ __STATIC_INLINE void Cy_SysClk_PiloEnable(void) } +/******************************************************************************* +* Function Name: Cy_SysClk_PiloIsEnabled +****************************************************************************//** +* +* Reports the Enabled/Disabled status of the PILO. +* +* \return Boolean status of PILO: true - Enabled, false - Disabled. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloDisable +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SysClk_PiloIsEnabled(void) +{ + return (_FLD2BOOL(SRSS_CLK_PILO_CONFIG_PILO_CLK_EN, SRSS_CLK_PILO_CONFIG)); +} + + /******************************************************************************* * Function Name: Cy_SysClk_PiloDisable ****************************************************************************//** @@ -1275,7 +1334,7 @@ __STATIC_INLINE void Cy_SysClk_PiloSetTrim(uint32_t trimVal) * Reports the current PILO trim bits value. * * \funcusage -* Refer to the Cy_SysClk_PiloSetTrim() function usage. +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_PiloSetTrim * *******************************************************************************/ __STATIC_INLINE uint32_t Cy_SysClk_PiloGetTrim(void) @@ -1285,6 +1344,53 @@ __STATIC_INLINE uint32_t Cy_SysClk_PiloGetTrim(void) /** \} group_sysclk_pilo_funcs */ +/* ========================================================================== */ +/* ========================== ALTHF SECTION =========================== */ +/* ========================================================================== */ +/** +* \addtogroup group_sysclk_alt_hf_funcs +* \{ +*/ +__STATIC_INLINE uint32_t Cy_SysClk_AltHfGetFrequency(void); + + +/******************************************************************************* +* Function Name: Cy_SysClk_AltHfGetFrequency +****************************************************************************//** +* +* Reports the frequency of the Alternative High-Frequency Clock +* +* \funcusage +* \snippet bleclk/snippet/main.c BLE ECO clock API: Cy_BLE_EcoConfigure() +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SysClk_AltHfGetFrequency(void) +{ + #if defined(CY_IP_MXBLESS) + return (cy_BleEcoClockFreqHz); + #else /* CY_IP_MXBLESS */ + return (0UL); + #endif /* CY_IP_MXBLESS */ +} +/** \} group_sysclk_alt_hf_funcs */ + + +/* ========================================================================== */ +/* ========================== ALTLF SECTION =========================== */ +/* ========================================================================== */ +/** \cond For future usage */ +__STATIC_INLINE uint32_t Cy_SysClk_AltLfGetFrequency(void) +{ + return (0UL); +} + +__STATIC_INLINE bool Cy_SysClk_AltLfIsEnabled(void) +{ + return (false); +} +/** \endcond */ + + /* ========================================================================== */ /* ==================== CLOCK MEASUREMENT SECTION ===================== */ /* ========================================================================== */ @@ -1845,6 +1951,7 @@ typedef struct * \{ */ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfEnable(uint32_t clkHf); +__STATIC_INLINE bool Cy_SysClk_ClkHfIsEnabled(uint32_t clkHf); __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfDisable(uint32_t clkHf); __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfSetSource(uint32_t clkHf, cy_en_clkhf_in_sources_t source); __STATIC_INLINE cy_en_clkhf_in_sources_t Cy_SysClk_ClkHfGetSource(uint32_t clkHf); @@ -1879,6 +1986,31 @@ __STATIC_INLINE cy_en_sysclk_status_t Cy_SysClk_ClkHfEnable(uint32_t clkHf) } +/******************************************************************************* +* Function Name: Cy_SysClk_ClkHfIsEnabled +****************************************************************************//** +* +* Reports the Enabled/Disabled status of clkHf. +* +* \param clkHf Selects which clkHf to check. +* +* \return Boolean status of clkHf: true - Enabled, false - Disabled. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkHfDisable +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SysClk_ClkHfIsEnabled(uint32_t clkHf) +{ + bool retVal = false; + if (clkHf < CY_SRSS_NUM_HFROOT) + { + retVal = _FLD2BOOL(SRSS_CLK_ROOT_SELECT_ENABLE, SRSS_CLK_ROOT_SELECT[clkHf]); + } + return (retVal); +} + + /******************************************************************************* * Function Name: Cy_SysClk_ClkHfDisable ****************************************************************************//** @@ -2853,7 +2985,9 @@ __STATIC_INLINE cy_en_clktimer_in_sources_t Cy_SysClk_ClkTimerGetSource(void); __STATIC_INLINE void Cy_SysClk_ClkTimerSetDivider(uint8_t divider); __STATIC_INLINE uint8_t Cy_SysClk_ClkTimerGetDivider(void); __STATIC_INLINE void Cy_SysClk_ClkTimerEnable(void); +__STATIC_INLINE bool Cy_SysClk_ClkTimerIsEnabled(void); __STATIC_INLINE void Cy_SysClk_ClkTimerDisable(void); + uint32_t Cy_SysClk_ClkTimerGetFrequency(void); /******************************************************************************* * Function Name: Cy_SysClk_ClkTimerSetSource @@ -2953,6 +3087,24 @@ __STATIC_INLINE void Cy_SysClk_ClkTimerEnable(void) } +/******************************************************************************* +* Function Name: Cy_SysClk_ClkTimerIsEnabled +****************************************************************************//** +* +* Reports the Enabled/Disabled status of the Timer. +* +* \return Boolean status of Timer: true - Enabled, false - Disabled. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerDisable +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SysClk_ClkTimerIsEnabled(void) +{ + return (_FLD2BOOL(SRSS_CLK_TIMER_CTL_ENABLE, SRSS_CLK_TIMER_CTL)); +} + + /******************************************************************************* * Function Name: Cy_SysClk_ClkTimerDisable ****************************************************************************//** @@ -2984,22 +3136,22 @@ __STATIC_INLINE void Cy_SysClk_ClkTimerDisable(void) */ typedef enum { - CY_SYSCLK_PUMP_IN_CLKPATH0, /**< Pump clock input is clock path 0 */ - CY_SYSCLK_PUMP_IN_CLKPATH1, /**< Pump clock input is clock path 1 */ - CY_SYSCLK_PUMP_IN_CLKPATH2, /**< Pump clock input is clock path 2 */ - CY_SYSCLK_PUMP_IN_CLKPATH3, /**< Pump clock input is clock path 3 */ - CY_SYSCLK_PUMP_IN_CLKPATH4, /**< Pump clock input is clock path 4 */ - CY_SYSCLK_PUMP_IN_CLKPATH5, /**< Pump clock input is clock path 5 */ - CY_SYSCLK_PUMP_IN_CLKPATH6, /**< Pump clock input is clock path 6 */ - CY_SYSCLK_PUMP_IN_CLKPATH7, /**< Pump clock input is clock path 7 */ - CY_SYSCLK_PUMP_IN_CLKPATH8, /**< Pump clock input is clock path 8 */ - CY_SYSCLK_PUMP_IN_CLKPATH9, /**< Pump clock input is clock path 9 */ - CY_SYSCLK_PUMP_IN_CLKPATH10, /**< Pump clock input is clock path 10 */ - CY_SYSCLK_PUMP_IN_CLKPATH11, /**< Pump clock input is clock path 11 */ - CY_SYSCLK_PUMP_IN_CLKPATH12, /**< Pump clock input is clock path 12 */ - CY_SYSCLK_PUMP_IN_CLKPATH13, /**< Pump clock input is clock path 13 */ - CY_SYSCLK_PUMP_IN_CLKPATH14, /**< Pump clock input is clock path 14 */ - CY_SYSCLK_PUMP_IN_CLKPATH15 /**< Pump clock input is clock path 15 */ + CY_SYSCLK_PUMP_IN_CLKPATH0 = 0UL, /**< Pump clock input is clock path 0 */ + CY_SYSCLK_PUMP_IN_CLKPATH1 = 1UL, /**< Pump clock input is clock path 1 */ + CY_SYSCLK_PUMP_IN_CLKPATH2 = 2UL, /**< Pump clock input is clock path 2 */ + CY_SYSCLK_PUMP_IN_CLKPATH3 = 3UL, /**< Pump clock input is clock path 3 */ + CY_SYSCLK_PUMP_IN_CLKPATH4 = 4UL, /**< Pump clock input is clock path 4 */ + CY_SYSCLK_PUMP_IN_CLKPATH5 = 5UL, /**< Pump clock input is clock path 5 */ + CY_SYSCLK_PUMP_IN_CLKPATH6 = 6UL, /**< Pump clock input is clock path 6 */ + CY_SYSCLK_PUMP_IN_CLKPATH7 = 7UL, /**< Pump clock input is clock path 7 */ + CY_SYSCLK_PUMP_IN_CLKPATH8 = 8UL, /**< Pump clock input is clock path 8 */ + CY_SYSCLK_PUMP_IN_CLKPATH9 = 9UL, /**< Pump clock input is clock path 9 */ + CY_SYSCLK_PUMP_IN_CLKPATH10 = 10UL, /**< Pump clock input is clock path 10 */ + CY_SYSCLK_PUMP_IN_CLKPATH11 = 11UL, /**< Pump clock input is clock path 11 */ + CY_SYSCLK_PUMP_IN_CLKPATH12 = 12UL, /**< Pump clock input is clock path 12 */ + CY_SYSCLK_PUMP_IN_CLKPATH13 = 13UL, /**< Pump clock input is clock path 13 */ + CY_SYSCLK_PUMP_IN_CLKPATH14 = 14UL, /**< Pump clock input is clock path 14 */ + CY_SYSCLK_PUMP_IN_CLKPATH15 = 15UL /**< Pump clock input is clock path 15 */ } cy_en_clkpump_in_sources_t; @@ -3035,7 +3187,9 @@ __STATIC_INLINE cy_en_clkpump_in_sources_t Cy_SysClk_ClkPumpGetSource(void); __STATIC_INLINE void Cy_SysClk_ClkPumpSetDivider(cy_en_clkpump_divide_t divider); __STATIC_INLINE cy_en_clkpump_divide_t Cy_SysClk_ClkPumpGetDivider(void); __STATIC_INLINE void Cy_SysClk_ClkPumpEnable(void); +__STATIC_INLINE bool Cy_SysClk_ClkPumpIsEnabled(void); __STATIC_INLINE void Cy_SysClk_ClkPumpDisable(void); +__STATIC_INLINE uint32_t Cy_SysClk_ClkPumpGetFrequency(void); /******************************************************************************* @@ -3136,6 +3290,24 @@ __STATIC_INLINE void Cy_SysClk_ClkPumpEnable(void) } +/******************************************************************************* +* Function Name: Cy_SysClk_ClkPumpIsEnabled +****************************************************************************//** +* +* Reports the Enabled/Disabled status of the ClkPump. +* +* \return Boolean status of ClkPump: true - Enabled, false - Disabled. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpDisable +* +*******************************************************************************/ +__STATIC_INLINE bool Cy_SysClk_ClkPumpIsEnabled(void) +{ + return (_FLD2BOOL(SRSS_CLK_SELECT_PUMP_ENABLE, SRSS_CLK_SELECT)); +} + + /******************************************************************************* * Function Name: Cy_SysClk_ClkPumpDisable ****************************************************************************//** @@ -3150,6 +3322,26 @@ __STATIC_INLINE void Cy_SysClk_ClkPumpDisable(void) { SRSS_CLK_SELECT &= ~SRSS_CLK_SELECT_PUMP_ENABLE_Msk; } + + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkPumpGetFrequency +****************************************************************************//** +* +* Reports the frequency of the pump clock (clk_pump). +* \note If the the pump clock is not enabled - a zero frequency is reported. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPumpEnable +* +*******************************************************************************/ +__STATIC_INLINE uint32_t Cy_SysClk_ClkPumpGetFrequency(void) +{ + /* Divide the input frequency down and return the result */ + return (Cy_SysClk_ClkPumpIsEnabled() ? + (Cy_SysClk_ClkPathGetFrequency((uint32_t)Cy_SysClk_ClkPumpGetSource()) / + (1UL << (uint32_t)Cy_SysClk_ClkPumpGetDivider())) : 0UL); +} /** \} group_sysclk_clk_pump_funcs */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syslib.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syslib.h index 0d7777895b3..2cc53537a0b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syslib.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syslib.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_syslib.h -* \version 2.50 +* \version 2.50.1 * * Provides an API declaration of the SysLib driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -139,6 +139,11 @@ *
VersionChangesReason for Change
1.60Added the following functions: \ref Cy_SysClk_ExtClkGetFrequency, \ref Cy_SysClk_EcoGetFrequency,\n +* \ref Cy_SysClk_ClkPathMuxGetFrequency, \ref Cy_SysClk_ClkPathGetFrequency, \ref Cy_SysClk_IloIsEnabled.\n +* \ref Cy_SysClk_PiloIsEnabled, \ref Cy_SysClk_AltHfGetFrequency, \ref Cy_SysClk_ClkHfIsEnabled,\n +* \ref Cy_SysClk_ClkTimerIsEnabled, \ref Cy_SysClk_ClkTimerGetFrequency, \ref Cy_SysClk_ClkPumpIsEnabled and\n +* \ref Cy_SysClk_ClkPumpGetFrequency.API enhancement.
1.50\ref Cy_SysClk_ClkHfGetFrequency is updated to reuse the \ref cy_BleEcoClockFreqHz global system variable.API enhancement.
* * +* +* +* +* * *
VersionChangesReason for Change
2.50.1Used the core library defines for the message codes forming. +* Improve PDL code base.
2.50Moved following macros to the core library: * CY_LO8,CY_HI8,CY_LO16,CY_HI16,CY_SWAP_ENDIAN16,CY_SWAP_ENDIAN32, @@ -250,6 +255,7 @@ #include #include #include "cy_utils.h" +#include "cy_result.h" #include "cy_device.h" #include "cy_device_headers.h" @@ -290,13 +296,13 @@ extern "C" { * \{ * Function status type codes */ -#define CY_PDL_STATUS_CODE_Pos (0U) /**< The module status code position in the status code */ -#define CY_PDL_STATUS_TYPE_Pos (16U) /**< The status type position in the status code */ -#define CY_PDL_MODULE_ID_Pos (18U) /**< The software module ID position in the status code */ -#define CY_PDL_STATUS_INFO (0UL << CY_PDL_STATUS_TYPE_Pos) /**< The information status type */ -#define CY_PDL_STATUS_WARNING (1UL << CY_PDL_STATUS_TYPE_Pos) /**< The warning status type */ -#define CY_PDL_STATUS_ERROR (2UL << CY_PDL_STATUS_TYPE_Pos) /**< The error status type */ -#define CY_PDL_MODULE_ID_Msk (0x3FFFU) /**< The software module ID mask */ +#define CY_PDL_STATUS_CODE_Pos (CY_RSLT_CODE_POSITION) /**< The module status code position in the status code */ +#define CY_PDL_STATUS_TYPE_Pos (CY_RSLT_TYPE_POSITION) /**< The status type position in the status code */ +#define CY_PDL_MODULE_ID_Pos (CY_RSLT_MODULE_POSITION) /**< The software module ID position in the status code */ +#define CY_PDL_STATUS_INFO ((uint32_t)CY_RSLT_TYPE_INFO << CY_PDL_STATUS_TYPE_Pos) /**< The information status type */ +#define CY_PDL_STATUS_WARNING ((uint32_t)CY_RSLT_TYPE_WARNING << CY_PDL_STATUS_TYPE_Pos) /**< The warning status type */ +#define CY_PDL_STATUS_ERROR ((uint32_t)CY_RSLT_TYPE_ERROR << CY_PDL_STATUS_TYPE_Pos) /**< The error status type */ +#define CY_PDL_MODULE_ID_Msk (CY_RSLT_MODULE_MASK) /**< The software module ID mask */ /** Get the software PDL module ID */ #define CY_PDL_DRV_ID(id) ((uint32_t)((uint32_t)((id) & CY_PDL_MODULE_ID_Msk) << CY_PDL_MODULE_ID_Pos)) #define CY_SYSLIB_ID CY_PDL_DRV_ID(0x11U) /**< SYSLIB PDL ID */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syspm.h b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syspm.h index 85cd16688b1..6d071770b23 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syspm.h +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/include/cy_syspm.h @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_syspm.h -* \version 4.50 +* \version 5.0 * * Provides the function definitions for the power management API. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -724,6 +724,23 @@ * * * +* +* +* +* +* * * *
VersionChangesReason for Change
5.0 +* Updated the internal IsVoltageChangePossible() function +* (\ref Cy_SysPm_LdoSetVoltage(), \ref Cy_SysPm_BuckEnable(), +* \ref Cy_SysPm_BuckSetVoltage1(), \ref Cy_SysPm_SystemEnterUlp() +* and \ref Cy_SysPm_SystemEnterLp() functions are affected). +* For all the devices except CY8C6xx6 and CY8C6xx7 added the check if +* modifying the RAM trim register is allowed. +* +* Protecting the system from a possible CPU hard-fault cause. If you +* are using PC > 0 in your project and you want to switch the power +* modes (LP<->ULP), you need to unprotect the CPUSS_TRIM_RAM_CTL and +* CPUSS_TRIM_ROM_CTL registers and can use a programmable PPU for that. +*
4.50Updated the \ref Cy_SysPm_CpuEnterDeepSleep() function. @@ -1239,10 +1256,10 @@ extern "C" { */ /** Driver major version */ -#define CY_SYSPM_DRV_VERSION_MAJOR 4 +#define CY_SYSPM_DRV_VERSION_MAJOR 5 /** Driver minor version */ -#define CY_SYSPM_DRV_VERSION_MINOR 50 +#define CY_SYSPM_DRV_VERSION_MINOR 0 /** SysPm driver identifier */ #define CY_SYSPM_ID (CY_PDL_DRV_ID(0x10U)) diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.S b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.S index 16e71def22a..52069c48566 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_ARM/cy_syslib_mdk.S @@ -1,11 +1,11 @@ ;------------------------------------------------------------------------------- ; \file cy_syslib_mdk.s -; \version 2.50 +; \version 2.50.1 ; ; \brief Assembly routines for ARMCC. ; ;------------------------------------------------------------------------------- -; Copyright 2016-2019 Cypress Semiconductor Corporation +; Copyright 2016-2020 Cypress Semiconductor Corporation ; SPDX-License-Identifier: Apache-2.0 ; ; Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_A_Clang/cy_syslib_a_clang.S b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_A_Clang/cy_syslib_a_clang.S index 68249d70779..62b526c4012 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_A_Clang/cy_syslib_a_clang.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_A_Clang/cy_syslib_a_clang.S @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_syslib_a_clang.S -* \version 2.50 +* \version 2.50.1 * * \brief Assembly routines for Apple Clang. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S index 1d6e16eba26..9af4ce1a614 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_GCC_ARM/cy_syslib_gcc.S @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_syslib_gcc.S -* \version 2.50 +* \version 2.50.1 * * \brief Assembly routines for GNU GCC. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_IAR/cy_syslib_iar.S b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_IAR/cy_syslib_iar.S index 88477491007..ff7f89d5ac8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_IAR/cy_syslib_iar.S +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/TOOLCHAIN_IAR/cy_syslib_iar.S @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_syslib_iar.s -* \version 2.50 +* \version 2.50.1 * * \brief Assembly routines for IAR Embedded Workbench IDE. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ble_clk.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ble_clk.c index 8f92bd1df26..b9aefd80891 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ble_clk.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_ble_clk.c @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_ble_clk.c -* \version 3.30 +* \version 3.40 * * \brief * This driver provides the source code for API BLE ECO clock. * ******************************************************************************** * \copyright -* Copyright 2017-2019 Cypress Semiconductor Corporation +* Copyright 2017-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -235,8 +235,7 @@ cy_en_ble_eco_status_t Cy_BLE_EcoConfigure(cy_en_ble_eco_freq_t freq, cy_en_ble_ Cy_SysPm_IoUnfreeze(); } - if(((BLE_BLESS_MT_CFG & BLE_BLESS_MT_CFG_ENABLE_BLERD_Msk) != 0u) && - ((BLE_BLESS_MT_STATUS & BLE_BLESS_MT_STATUS_BLESS_STATE_Msk) != 0u)) + if(Cy_BLE_EcoIsEnabled()) { status = CY_BLE_ECO_ALREADY_STARTED; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_canfd.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_canfd.c index 4a8098fae67..1fd40285697 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_canfd.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_canfd.c @@ -1,13 +1,13 @@ /******************************************************************************* * \file cy_canfd.c -* \version 1.0.1 +* \version 1.10 * * \brief * Provides an API implementation of the CAN FD driver. * ******************************************************************************** * \copyright -* Copyright 2019 Cypress Semiconductor Corporation +* Copyright 2019-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -269,11 +269,8 @@ cy_en_canfd_status_t Cy_CANFD_Init(CANFD_Type *base, uint32_t chan, (NULL != config->bitrate) && (NULL != config->globalFilterConfig) && (NULL != config->rxFIFO0Config) && - (NULL != config->rxFIFO1Config) && - ((0U != config->sidFilterConfig->numberOfSIDFilters) && - (NULL != config->sidFilterConfig->sidFilter)) && - ((0U != config->extidFilterConfig->numberOfEXTIDFilters) && - (NULL != config->extidFilterConfig->extidFilter)) ) + (NULL != config->rxFIFO1Config) + ) { CY_ASSERT_L2(CY_CANFD_IS_CHANNEL_VALID(chan)); CY_ASSERT_L2(CY_CANFD_IS_NOM_PRESCALER_VALID(config->bitrate->prescaler)); @@ -318,25 +315,42 @@ cy_en_canfd_status_t Cy_CANFD_Init(CANFD_Type *base, uint32_t chan, context->messageRAMaddress = config->messageRAMaddress; context->messageRAMsize = config->messageRAMsize; - /* Configure a standard ID filter: - * The number of SID filters and Start address (word) of the SID filter - * configuration in Message RAM - */ - CANFD_SIDFC(base, chan) = - _VAL2FLD(CANFD_CH_M_TTCAN_SIDFC_LSS, config->sidFilterConfig->numberOfSIDFilters) | - _VAL2FLD(CANFD_CH_M_TTCAN_SIDFC_FLSSA, config->messageRAMaddress >> CY_CANFD_MRAM_SIGNIFICANT_BYTES_SHIFT); + if ((0U != config->sidFilterConfig->numberOfSIDFilters) && + (NULL != config->sidFilterConfig->sidFilter)) + { + /* Configure a standard ID filter: + * The number of SID filters and Start address (word) of the SID filter + * configuration in Message RAM + */ + CANFD_SIDFC(base, chan) = + _VAL2FLD(CANFD_CH_M_TTCAN_SIDFC_LSS, config->sidFilterConfig->numberOfSIDFilters) | + _VAL2FLD(CANFD_CH_M_TTCAN_SIDFC_FLSSA, config->messageRAMaddress >> CY_CANFD_MRAM_SIGNIFICANT_BYTES_SHIFT); + } + else + { + CANFD_SIDFC(base, chan) = 0U; + } - /* Configure an extended ID filter: - * The number of XID filters and start address (word) of the ext id - * filter configuration in Message RAM - */ - CANFD_XIDFC(base, chan) = - _VAL2FLD(CANFD_CH_M_TTCAN_XIDFC_LSE, config->extidFilterConfig->numberOfEXTIDFilters) | - _VAL2FLD(CANFD_CH_M_TTCAN_XIDFC_FLESA, _FLD2VAL(CANFD_CH_M_TTCAN_SIDFC_FLSSA, CANFD_SIDFC(base, chan)) + + if((0U != config->extidFilterConfig->numberOfEXTIDFilters) && + (NULL != config->extidFilterConfig->extidFilter)) + { + /* Configure an extended ID filter: + * The number of XID filters and start address (word) of the ext id + * filter configuration in Message RAM + */ + CANFD_XIDFC(base, chan) = + _VAL2FLD(CANFD_CH_M_TTCAN_XIDFC_LSE, config->extidFilterConfig->numberOfEXTIDFilters) | + _VAL2FLD(CANFD_CH_M_TTCAN_XIDFC_FLESA, _FLD2VAL(CANFD_CH_M_TTCAN_SIDFC_FLSSA, CANFD_SIDFC(base, chan)) + (config->sidFilterConfig->numberOfSIDFilters)); - /* Update the extended ID AND Mask */ - CANFD_XIDAM(base, chan) = _VAL2FLD(CANFD_CH_M_TTCAN_XIDAM_EIDM, config->extidFilterConfig->extIDANDMask); + /* Update the extended ID AND Mask */ + CANFD_XIDAM(base, chan) = _VAL2FLD(CANFD_CH_M_TTCAN_XIDAM_EIDM, config->extidFilterConfig->extIDANDMask); + } + else + { + CANFD_XIDFC(base, chan) = 0U; + CANFD_XIDAM(base, chan) = 0U; + } /* Configuration of Rx Buffer and Rx FIFO */ CANFD_RXESC(base, chan) = @@ -476,11 +490,17 @@ cy_en_canfd_status_t Cy_CANFD_Init(CANFD_Type *base, uint32_t chan, _VAL2FLD(CANFD_CH_M_TTCAN_GFC_RRFS, ((config->globalFilterConfig->rejectRemoteFramesStandard) ? 1UL : 0UL))| _VAL2FLD(CANFD_CH_M_TTCAN_GFC_RRFE, ((config->globalFilterConfig->rejectRemoteFramesExtended) ? 1UL : 0UL)); - /* Standard Message ID filters */ - Cy_CANFD_SidFiltersSetup(base, chan, config->sidFilterConfig, context); + if (0U != config->sidFilterConfig->numberOfSIDFilters) + { + /* Standard Message ID filters */ + Cy_CANFD_SidFiltersSetup(base, chan, config->sidFilterConfig, context); + } - /* Extended Message ID filters */ - Cy_CANFD_XidFiltersSetup(base, chan, config->extidFilterConfig, context); + if(0U != config->extidFilterConfig->numberOfEXTIDFilters) + { + /* Extended Message ID filters */ + Cy_CANFD_XidFiltersSetup(base, chan, config->extidFilterConfig, context); + } /* Configure the interrupt */ Cy_CANFD_SetInterruptMask(base, chan, CY_CANFD_INTERRUPT_ENABLE_DEFAULT); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_device.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_device.c index c89104a36d0..a3358e3ddee 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_device.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_device.c @@ -357,6 +357,113 @@ const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_03 = /* ipcLockStatusOffset */ offsetof(IPC_STRUCT_V2_Type, LOCK_STATUS), }; +const cy_stc_device_t cy_deviceIpBlockCfgPSoC6_04 = +{ + /* Base HW addresses */ + /* cpussBase */ 0x40200000UL, + /* flashcBase */ 0x40240000UL, + /* periBase */ 0x40000000UL, + /* udbBase */ 0UL, + /* protBase */ 0x40230000UL, + /* hsiomBase */ 0x40300000UL, + /* gpioBase */ 0x40310000UL, + /* passBase */ 0x409F0000UL, + /* ipcBase */ 0x40220000UL, + /* cryptoBase */ 0x40100000UL, + + /* IP block versions [7:4] major, [3:0] minor */ + /* cpussVersion */ 0x20U, + /* cryptoVersion */ 0x20U, + /* dwVersion */ 0x20U, + /* ipcVersion */ 0x20U, + /* periVersion */ 0x20U, + /* srssVersion */ 0x13U, + + /* Parameters */ + /* cpussIpcNr */ 16U, + /* cpussIpcIrqNr */ 16U, + /* cpussDw0ChNr */ 30U, + /* cpussDw1ChNr */ 32U, + /* cpussFlashPaSize */ 128U, + /* cpussIpc0Irq */ 23, + /* cpussFmIrq */ 117, + /* cpussNotConnectedIrq */ 1023, + /* srssNumClkpath */ 5U, + /* srssNumPll */ 1U, + /* srssNumHfroot */ 4U, + /* periClockNr */ 28U, + /* smifDeviceNr */ 3U, + /* passSarChannels */ 16U, + /* epMonitorNr */ 0u, + /* udbPresent */ 0U, + /* sysPmSimoPresent */ 1U, + /* protBusMasterMask */ 0xC01FUL, + /* cryptoMemSize */ 1024u, + /* flashRwwRequired */ 0U, + /* flashPipeRequired */ 0U, + /* flashWriteDelay */ 0U, + /* flashProgramDelay */ 0U, + /* flashEraseDelay */ 0U, + /* flashCtlMainWs0Freq */ 25U, + /* flashCtlMainWs1Freq */ 50U, + /* flashCtlMainWs2Freq */ 75U, + /* flashCtlMainWs3Freq */ 100U, + /* flashCtlMainWs4Freq */ 125U, + + /* Peripheral register offsets */ + + /* DW registers */ + /* dwChOffset */ (uint16_t)offsetof(DW_V2_Type, CH_STRUCT), + /* dwChSize */ sizeof(DW_CH_STRUCT_V2_Type), + /* dwChCtlPrioPos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PRIO_Pos, + /* dwChCtlPreemptablePos */ (uint8_t)DW_CH_STRUCT_V2_CH_CTL_PREEMPTABLE_Pos, + /* dwStatusChIdxPos */ (uint8_t)DW_V2_STATUS_CH_IDX_Pos, + /* dwStatusChIdxMsk */ DW_V2_STATUS_CH_IDX_Msk, + + /* PERI registers */ + /* periTrCmdOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_CMD), + /* periTrCmdGrSelMsk */ (uint16_t)PERI_V2_TR_CMD_GROUP_SEL_Msk, + /* periTrGrOffset */ (uint16_t)offsetof(PERI_V2_Type, TR_GR), + /* periTrGrSize */ sizeof(PERI_TR_GR_V2_Type), + + /* periDivCmdDivSelMsk */ (uint8_t)PERI_V2_DIV_CMD_DIV_SEL_Msk, + /* periDivCmdTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_TYPE_SEL_Pos, + /* periDivCmdPaDivSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_DIV_SEL_Pos, + /* periDivCmdPaTypeSelPos */ (uint8_t)PERI_V2_DIV_CMD_PA_TYPE_SEL_Pos, + + /* periDiv8CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_8_CTL), + /* periDiv16CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_CTL), + /* periDiv16_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_16_5_CTL), + /* periDiv24_5CtlOffset */ (uint16_t)offsetof(PERI_V2_Type, DIV_24_5_CTL), + + /* GPIO registers */ + /* gpioPrtIntrCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, INTR_CFG), + /* gpioPrtCfgOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG), + /* gpioPrtCfgInOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_IN), + /* gpioPrtCfgOutOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_OUT), + /* gpioPrtCfgSioOffset */ (uint8_t)offsetof(GPIO_PRT_V2_Type, CFG_SIO), + + /* CPUSS registers */ + /* cpussCm0ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM0_CLOCK_CTL), + /* cpussCm4ClockCtlOffset */ offsetof(CPUSS_V2_Type, CM4_CLOCK_CTL), + /* cpussCm4StatusOffset */ offsetof(CPUSS_V2_Type, CM4_STATUS), + /* cpussCm0StatusOffset */ offsetof(CPUSS_V2_Type, CM0_STATUS), + /* cpussCm4PwrCtlOffset */ offsetof(CPUSS_V2_Type, CM4_PWR_CTL), + /* cpussTrimRamCtlOffset */ offsetof(CPUSS_V2_Type, TRIM_RAM_CTL), + /* cpussTrimRomCtlOffset */ offsetof(CPUSS_V2_Type, TRIM_ROM_CTL), + /* cpussSysTickCtlOffset */ offsetof(CPUSS_V2_Type, SYSTICK_CTL), + /* cpussCm0NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V2_Type, CM0_NMI_CTL), + /* cpussCm4NmiCtlOffset */ (uint16_t)offsetof(CPUSS_V2_Type, CM4_NMI_CTL), + /* cpussRomCtl */ (uint16_t)offsetof(CPUSS_V2_Type, ROM_CTL), + /* cpussRam0Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM0_CTL0), + /* cpussRam1Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM1_CTL0), + /* cpussRam2Ctl0 */ (uint16_t)offsetof(CPUSS_V2_Type, RAM2_CTL0), + + /* IPC registers */ + /* ipcStructSize */ sizeof(IPC_STRUCT_V2_Type), + /* ipcLockStatusOffset */ offsetof(IPC_STRUCT_V2_Type, LOCK_STATUS), +}; + /****************************************************************************** * Function Name: Cy_PDL_Init diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_efuse.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_efuse.c index 308166311ce..55e985f7617 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_efuse.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_efuse.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_efuse.c -* \version 1.10.1 +* \version 1.10.2 * * \brief * Provides API implementation of the eFuse driver. @@ -62,7 +62,7 @@ static cy_en_efuse_status_t ProcessOpcode(void); * - 8 is a number of fuse bits in the byte. * * The EFUSE_EFUSE_NR macro is defined in the series-specific header file, e.g -* \e \/devices/psoc6/include/psoc6_01_config.\e h +* \e \/devices/include/psoc6_01_config.\e h * * \param bitVal * The pointer to the location to store the bit value. @@ -119,7 +119,7 @@ cy_en_efuse_status_t Cy_EFUSE_GetEfuseBit(uint32_t bitNum, bool *bitVal) * - 32 is a number of fuse bytes in one efuse macro. * * The EFUSE_EFUSE_NR macro is defined in the series-specific header file, e.g -* \e \/devices/psoc6/include/psoc6_01_config.\e h +* \e \/devices/include/psoc6_01_config.\e h * * \param byteVal * The pointer to the location to store eFuse data. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_flash.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_flash.c index f5bd30c9d4f..1911b97783a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_flash.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_flash.c @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_flash.c -* \version 3.30.3 +* \version 3.30.4 * * \brief * Provides the public functions for the API for the PSoC 6 Flash Driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -668,8 +668,9 @@ cy_en_flashdrv_status_t Cy_Flash_EraseRow(uint32_t rowAddr) * XRES pin, a software reset, and watchdog reset sources. Also, the low-voltage * detect circuits should be configured to generate an interrupt instead of a reset. * Otherwise, portions of flash may undergo unexpected changes. -* \note Before reading data from previously programmed/erased flash rows, the -* user must clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer() +* \note To avoid situation of reading data from cache memory - before +* reading data from previously programmed/erased flash rows, the user must +* clear the flash cache with the Cy_SysLib_ClearFlashCacheAndBuffer() * function. * * \param rowAddr Address of the flash row number. @@ -719,7 +720,7 @@ cy_en_flashdrv_status_t Cy_Flash_StartEraseRow(uint32_t rowAddr) * Function Name: Cy_Flash_EraseSector ****************************************************************************//** * -* This function erases a 256KB sector of flash. Reports success or +* This function erases a sector of flash. Reports success or * a reason for failure. Does not return until the Erase operation is * complete. Returns immediately and reports a \ref CY_FLASH_DRV_IPC_BUSY error in * the case when another process is writing to flash or erasing the row. @@ -772,7 +773,7 @@ cy_en_flashdrv_status_t Cy_Flash_EraseSector(uint32_t sectorAddr) * Function Name: Cy_Flash_StartEraseSector ****************************************************************************//** * -* Starts erasing a 256KB sector of flash. Returns immediately +* Starts erasing a sector of flash. Returns immediately * and reports a successful start or reason for failure. * Reports a \ref CY_FLASH_DRV_IPC_BUSY error in the case when IPC structure is locked * by another process. User firmware should not enter the Hibernate or Deep Sleep mode until diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_prot.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_prot.c index 4731fa74024..6ea05a012ad 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_prot.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_prot.c @@ -1,13 +1,13 @@ /***************************************************************************//** * \file cy_prot.c -* \version 1.30.1 +* \version 1.30.2 * * \brief * Provides an API implementation of the Protection Unit driver * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -776,11 +776,12 @@ cy_en_prot_status_t Cy_Prot_GetSmpuStruct(PROT_SMPU_SMPU_STRUCT_Type** base, * The register to update attributes in. * * \param pcMask -* The protection context mask. This is a 16-bit value of the allowed contexts. -* It is an OR'ed (|) field of the * provided defines in cy_prot.h. -* For example: (CY_PROT_PCMASK1 | CY_PROT_PCMASK3 | CY_PROT_PCMASK4). -* \note The function accepts pcMask values from CY_PROT_PCMASK1 to CY_PROT_PCMASK5. -* But each device has its own number of available protection contexts. +* The protection context mask. It specifies the protection context or a set of +* multiple protection contexts to be configured. +* It is a value of OR'd (|) items of \ref cy_en_prot_pcmask_t. +* For example: (\ref CY_PROT_PCMASK1 | \ref CY_PROT_PCMASK3 | \ref CY_PROT_PCMASK4). +* \note The function accepts pcMask values from \ref CY_PROT_PCMASK1 to \ref CY_PROT_PCMASK15. +* But each device has its own number of available protection contexts. * That number is defined by PERI_PC_NR in the config file. * * \param userPermission @@ -888,11 +889,12 @@ static cy_en_prot_status_t Prot_ConfigPpuAtt(volatile uint32_t * reg, uint16_t p * The register base address of the protection structure is being configured. * * \param pcMask -* The protection context mask. This is a 16-bit value of the allowed contexts, -* it is an OR'ed (|) field of the * provided defines in cy_prot.h. -* For example: (CY_PROT_PCMASK1 | CY_PROT_PCMASK3 | CY_PROT_PCMASK4). -* \note The function accepts pcMask values from CY_PROT_PCMASK1 to CY_PROT_PCMASK15. -* But each device has its own number of available protection contexts. +* The protection context mask. It specifies the protection context or a set of +* multiple protection contexts to be configured. +* It is a value of OR'd (|) items of \ref cy_en_prot_pcmask_t. +* For example: (\ref CY_PROT_PCMASK1 | \ref CY_PROT_PCMASK3 | \ref CY_PROT_PCMASK4). +* \note The function accepts pcMask values from \ref CY_PROT_PCMASK1 to \ref CY_PROT_PCMASK15. +* But each device has its own number of available protection contexts. * That number is defined by PERI_PC_NR in the config file. * * \param userPermission @@ -1013,11 +1015,12 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuProgSlaveAddr(PERI_MS_PPU_PR_Type* base, ui * The register base address of the protection structure is being configured. * * \param pcMask -* The protection context mask. This is a 16-bit value of the allowed contexts, -* it is an OR'ed (|) field of the * provided defines in cy_prot.h. -* For example: (CY_PROT_PCMASK1 | CY_PROT_PCMASK3 | CY_PROT_PCMASK4). -* \note The function accepts pcMask values from CY_PROT_PCMASK1 to CY_PROT_PCMASK15. -* But each device has its own number of available protection contexts. +* The protection context mask. It specifies the protection context or a set of +* multiple protection contexts to be configured. +* It is a value of OR'd (|) items of \ref cy_en_prot_pcmask_t. +* For example: (\ref CY_PROT_PCMASK1 | \ref CY_PROT_PCMASK3 | \ref CY_PROT_PCMASK4). +* \note The function accepts pcMask values from \ref CY_PROT_PCMASK1 to \ref CY_PROT_PCMASK15. +* But each device has its own number of available protection contexts. * That number is defined by PERI_PC_NR in the config file. * * \param userPermission @@ -1167,11 +1170,12 @@ cy_en_prot_status_t Cy_Prot_DisablePpuProgSlaveRegion(PERI_MS_PPU_PR_Type* base) * The register base address of the protection structure is being configured. * * \param pcMask -* The protection context mask. This is a 16-bit value of the allowed contexts, -* it is an OR'ed (|) field of the * provided defines in cy_prot.h. -* For example: (CY_PROT_PCMASK1 | CY_PROT_PCMASK3 | CY_PROT_PCMASK4). -* \note The function accepts pcMask values from CY_PROT_PCMASK1 to CY_PROT_PCMASK15. -* But each device has its own number of available protection contexts. +* The protection context mask. It specifies the protection context or a set of +* multiple protection contexts to be configured. +* It is a value of OR'd (|) items of \ref cy_en_prot_pcmask_t. +* For example: (\ref CY_PROT_PCMASK1 | \ref CY_PROT_PCMASK3 | \ref CY_PROT_PCMASK4). +* \note The function accepts pcMask values from \ref CY_PROT_PCMASK1 to \ref CY_PROT_PCMASK15. +* But each device has its own number of available protection contexts. * That number is defined by PERI_PC_NR in the config file. * * \param userPermission @@ -1232,11 +1236,12 @@ cy_en_prot_status_t Cy_Prot_ConfigPpuFixedMasterAtt(PERI_MS_PPU_FX_Type* base, u * The register base address of the protection structure is being configured. * * \param pcMask -* The protection context mask. This is a 16-bit value of the allowed contexts, -* it is an OR'ed (|) field of the * provided defines in cy_prot.h. -* For example: (CY_PROT_PCMASK1 | CY_PROT_PCMASK3 | CY_PROT_PCMASK4). -* \note The function accepts pcMask values from CY_PROT_PCMASK1 to CY_PROT_PCMASK15. -* But each device has its own number of available protection contexts. +* The protection context mask. It specifies the protection context or a set of +* multiple protection contexts to be configured. +* It is a value of OR'd (|) items of \ref cy_en_prot_pcmask_t. +* For example: (\ref CY_PROT_PCMASK1 | \ref CY_PROT_PCMASK3 | \ref CY_PROT_PCMASK4). +* \note The function accepts pcMask values from \ref CY_PROT_PCMASK1 to \ref CY_PROT_PCMASK15. +* But each device has its own number of available protection contexts. * That number is defined by PERI_PC_NR in the config file. * * \param userPermission diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_rtc.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_rtc.c index 35951666fc4..8c9f953ee60 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_rtc.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_rtc.c @@ -1,12 +1,13 @@ /***************************************************************************//** * \file cy_rtc.c -* \version 2.20.1 +* \version 2.30 * * This file provides constants and parameter values for the APIs for the * Real-Time Clock (RTC). * ******************************************************************************** -* Copyright 2016-2019 Cypress Semiconductor Corporation +* \copyright +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -886,9 +887,10 @@ cy_en_rtc_status_t Cy_RTC_EnableDstTime(cy_stc_rtc_dst_t const *dstTime, cy_stc_ * Function Name: Cy_RTC_SetNextDstTime ****************************************************************************//** * -* Set the next time of the DST. This function sets the time to ALARM2 for a next -* DST event. If Cy_RTC_GetDSTStatus() is true(=1), the next DST event should be -* the DST stop, then this function should be called with the DST stop time. +* A low-level DST function sets ALARM2 for a next DST event. +* If Cy_RTC_GetDSTStatus() is true(=1), the next DST event should be +* the DST stop, then this function should be called with the DST stop time. +* Used by the \ref Cy_RTC_EnableDstTime and \ref Cy_RTC_DstInterrupt functions. * * If the time format(.format) is relative option(=0), the * RelativeToFixed() is called to convert to a fixed date. @@ -959,9 +961,11 @@ cy_en_rtc_status_t Cy_RTC_SetNextDstTime(cy_stc_rtc_dst_format_t const *nextDst) * Function Name: Cy_RTC_GetDstStatus ****************************************************************************//** * -* Returns the current DST status using given time information. This function -* is used in the initial state of a system. If the DST is enabled, the system -* sets the DST start or stop as a result of this function. +* A low-level DST function returns the current DST status using given time +* information. This function is used in the initial state of a system. +* If the DST is enabled, the system sets the DST start or stop as a result of +* this function. +* Used by the \ref Cy_RTC_EnableDstTime and \ref Cy_RTC_DstInterrupt functions. * * \param dstTime The DST configuration structure, see \ref cy_stc_rtc_dst_t. * @@ -981,6 +985,7 @@ bool Cy_RTC_GetDstStatus(cy_stc_rtc_dst_t const *dstTime, cy_stc_rtc_config_t co uint32_t dstStopTime; uint32_t dstStartDayOfMonth; uint32_t dstStopDayOfMonth; + bool status = false; CY_ASSERT_L1(NULL != dstTime); CY_ASSERT_L1(NULL != timeDate); @@ -1019,11 +1024,41 @@ bool Cy_RTC_GetDstStatus(cy_stc_rtc_dst_t const *dstTime, cy_stc_rtc_config_t co currentTime = ((uint32_t) (timeDate->month << CY_RTC_DST_MONTH_POSITION) | (timeDate->date << CY_RTC_DST_DAY_OF_MONTH_POSITION) | (timeDate->hour)); - + dstStopTime = ((uint32_t) (dstTime->stopDst.month << CY_RTC_DST_MONTH_POSITION) | (dstStopDayOfMonth << CY_RTC_DST_DAY_OF_MONTH_POSITION) | (dstTime->stopDst.hour)); - return((dstStartTime <= currentTime) && (dstStopTime > currentTime)); + if ((dstStartTime <= currentTime) && (dstStopTime > currentTime)) + { + status = true; + + if (1UL == (dstStopTime - currentTime)) /* Check for the 'an hour before/after stop DST event' period */ + { + cy_stc_rtc_alarm_t alarm; + uint32_t locDate = (CY_RTC_DST_FIXED != dstTime->startDst.format) ? RelativeToFixed(&dstTime->startDst) : dstTime->startDst.dayOfMonth; + Cy_RTC_GetAlarmDateAndTime(&alarm, CY_RTC_ALARM_2); + + /* If Alarm2 is set for the "Start DST" event - the "Stop DST" event is already passed: */ + if ((alarm.almEn == CY_RTC_ALARM_ENABLE ) && + (alarm.monthEn == CY_RTC_ALARM_ENABLE ) && + (alarm.month == dstTime->startDst.month) && + (alarm.dateEn == CY_RTC_ALARM_ENABLE ) && + (alarm.date == locDate ) && + (alarm.dayOfWeekEn == CY_RTC_ALARM_DISABLE ) && + (alarm.hourEn == CY_RTC_ALARM_ENABLE ) && + (alarm.hour == dstTime->startDst.hour ) && + (alarm.minEn == CY_RTC_ALARM_ENABLE ) && + (alarm.min == 0UL ) && + (alarm.secEn == CY_RTC_ALARM_ENABLE ) && + (alarm.sec == 0UL )) + { + status = false; + } + /* Otherwise, including the case when Alarm2 is not set at all (DST is not enabled yet) - return true. */ + } + } + + return (status); } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif.c index 30cad1e32a5..875573ab630 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_smif.c -* \version 1.40.1 +* \version 1.50 * * \brief * This file provides the source code for the SMIF driver APIs. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif_memslot.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif_memslot.c index 114c5e5d932..5a28464ea38 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif_memslot.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_smif_memslot.c @@ -1,6 +1,6 @@ /***************************************************************************//** * \file cy_smif_memslot.c -* \version 1.40.1 +* \version 1.50 * * \brief * This file provides the source code for the memory-level APIs of the SMIF driver. @@ -66,10 +66,15 @@ extern "C" { #define INSTRUCTION_NOT_SUPPORTED (0XFFU) /* The code for the not supported instruction */ #define BASIC_SPI_ID_LSB (0X00UL) /* The JEDEC SFDP Basic SPI Flash Parameter ID LSB */ #define BASIC_SPI_ID_MSB (0XFFUL) /* The JEDEC SFDP Basic SPI Flash Parameter ID MSB */ +#define SECTOR_MAP_ID_LSB (0x81UL) /* The JEDEC SFDP Sector Map ID LSB */ +#define SECTOR_MAP_ID_MSB (0xFFUL) /* The JEDEC SFDP Sector Map ID MSB */ +#define SECTOR_MAP_DESCRIPTOR_MASK (0x2U) /* The mask for the type bit of the Sector Map descriptor */ +#define SECTOR_MAP_COMAND_DESCRIPTOR_TYPE (0U) /* Code for the command descriptor type */ +#define SECTOR_MAP_REGION_SIZE_MULTIPLIER (256UL) /* The multiplier for region size units */ #define FOUR_BYTE_ADDR_ID_LSB (0X84UL) /* The 4-byte Address Instruction Table is assigned the ID LSB of 84h */ #define FOUR_BYTE_ADDR_ID_MSB (0XFFUL) /* The 4-byte Address Instruction Table is assigned the ID MSB of FFh */ -#define FOUR_BYTE_ADDR_ERASE_TYPE_1 (0X4UL) /* The Erase Type 1 offset in 4-byte Address Instruction Table */ -#define FOUR_BYTE_ADDR_ERASE_TYPE_4 (0X7UL) /* The Erase Type 4 offset in 4-byte Address Instruction Table */ +#define FOUR_BYTE_ADDR_ERASE_TYPE_1 (0X4UL) /* The Erase Type 1 offset in 4-byte Address Instruction Table */ +#define FOUR_BYTE_ADDR_ERASE_TYPE_4 (0X7UL) /* The Erase Type 4 offset in 4-byte Address Instruction Table */ #define ERASE_T_COUNT_Pos (0UL) /* Erase Type X Erase, Typical time: count (Bits 4:0) */ #define ERASE_T_COUNT_Msk (0x1FUL) /* Erase Type X Erase, Typical time: count (Bitfield-Mask) */ #define ERASE_T_UNITS_Pos (5UL) /* Erase Type X Erase, Typical time: units (Bits 6:5) */ @@ -178,6 +183,21 @@ typedef enum /** \endcond*/ +/*************************************** +* Internal Structures +***************************************/ + +/** +* This internal structure is used to store data for erase types. +*/ +typedef struct +{ + uint8_t eraseCmd; /**< The instruction used for erase transaction*/ + uint32_t eraseSize; /**< The number of bytes to be erased at one erase transaction*/ + uint32_t eraseTime; /**< The maximum erase time for one erase transaction */ +} cy_stc_smif_erase_type_t; + + /*************************************** * Internal Function Prototypes ***************************************/ @@ -214,7 +234,7 @@ static void SfdpGetReadFourBytesCmd(uint8_t const sfdpBuffer[], cy_en_smif_protocol_mode_t protocolMode, cy_stc_smif_mem_cmd_t* cmdRead); static uint32_t SfdpGetPageSize(uint8_t const sfdpBuffer[]); -static uint32_t SfdpGetEraseTime(uint32_t const eraseOffset, uint8_t const sfdpBuffer[]); +static uint32_t SfdpGetEraseTime(uint32_t const eraseOffset, uint8_t const sfdpBuffer[], cy_stc_smif_erase_type_t eraseType[]); static uint32_t SfdpGetChipEraseTime(uint8_t const sfdpBuffer[]); static uint32_t SfdpGetPageProgramTime(uint8_t const sfdpBuffer[]); static void SfdpSetWriteEnableCommand(cy_stc_smif_mem_cmd_t* cmdWriteEnable); @@ -230,11 +250,25 @@ static void SfdpGetQuadEnableParameters(cy_stc_smif_mem_device_cfg_t *device, uint8_t const sfdpBuffer[]); static void SfdpSetChipEraseCommand(cy_stc_smif_mem_cmd_t* cmdChipErase); static uint32_t SfdpGetSectorEraseCommand(cy_stc_smif_mem_device_cfg_t *device, - uint8_t const sfdpBuffer[]); + uint8_t const sfdpBuffer[], + cy_stc_smif_erase_type_t eraseTypeStc[]); +static cy_en_smif_status_t ReadAnyReg(SMIF_Type *base, cy_en_smif_slave_select_t slaveSelect, + uint8_t *value, uint8_t command, uint8_t const *address, + uint32_t addressSize, cy_stc_smif_context_t const *context); +static cy_en_smif_status_t SfdpEnterFourByteAddressing(SMIF_Type *base, uint8_t entryMethodByte, + cy_stc_smif_mem_device_cfg_t *device, + cy_en_smif_slave_select_t slaveSelect, + cy_stc_smif_context_t const *context); +static void SfdpGetEraseSizeAndCmd(uint8_t const sfdpBuffer[], cy_stc_smif_erase_type_t eraseType[]); +static cy_en_smif_status_t SfdpPopulateRegionInfo(SMIF_Type *base, uint8_t const sectorMapBuff[], + uint32_t const buffLength, cy_stc_smif_mem_device_cfg_t *device, + cy_en_smif_slave_select_t slaveSelect, const cy_stc_smif_context_t *context, + cy_stc_smif_erase_type_t eraseType[]); static void SfdpSetWipStatusRegisterCommand(cy_stc_smif_mem_cmd_t* readStsRegWipCmd); static cy_en_smif_status_t PollTransferStatus(SMIF_Type const *base, cy_en_smif_txfr_status_t transferStatus, cy_stc_smif_context_t const *context); static void ValueToByteArray(uint32_t value, uint8_t *byteArray, uint32_t startPos, uint32_t size); +static uint32_t ByteArrayToValue(uint8_t const *byteArray, uint32_t size); /******************************************************************************* * Function Name: Cy_SMIF_MemInit @@ -269,7 +303,10 @@ static void ValueToByteArray(uint32_t value, uint8_t *byteArray, uint32_t startP * mapped into the PSoC memory map. \ref cy_stc_smif_mem_config_t * * \param context -* The SMIF internal context structure of the block. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return The memory slot initialization status. * - \ref CY_SMIF_SUCCESS @@ -496,7 +533,10 @@ void Cy_SMIF_MemDeInit(SMIF_Type *base) * The device to which the command is sent. * * \param context -* The internal SMIF context data. \ref cy_stc_smif_context_t +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the command transmission. * - \ref CY_SMIF_SUCCESS @@ -523,7 +563,7 @@ cy_en_smif_status_t Cy_SMIF_MemCmdWriteEnable(SMIF_Type *base, memDevice->slaveSelect, CY_SMIF_TX_LAST_BYTE, context); - } + } return result; } @@ -546,7 +586,10 @@ cy_en_smif_status_t Cy_SMIF_MemCmdWriteEnable(SMIF_Type *base, * The device to which the command is sent. * * \param context -* The internal SMIF context data. \ref cy_stc_smif_context_t +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the command transmission. * - \ref CY_SMIF_SUCCESS @@ -597,7 +640,10 @@ cy_en_smif_status_t Cy_SMIF_MemCmdWriteDisable(SMIF_Type *base, * The device to which the command is sent. * * \param context -* The internal SMIF context data. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the memory device. * - True - The device is busy or a timeout occurs. @@ -647,7 +693,10 @@ bool Cy_SMIF_MemIsBusy(SMIF_Type *base, cy_stc_smif_mem_config_t const *memDevic * The device to which the command is sent. * * \param context -* The internal SMIF context data. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the command. * - \ref CY_SMIF_SUCCESS @@ -750,7 +799,10 @@ cy_en_smif_status_t Cy_SMIF_MemQuadEnable(SMIF_Type *base, * The command required to read the status/configuration register. * * \param context -* The internal SMIF context data. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the command reception. * - \ref CY_SMIF_SUCCESS @@ -809,7 +861,10 @@ cy_en_smif_status_t Cy_SMIF_MemCmdReadStatus(SMIF_Type *base, * The command to write into the status/configuration register. * * \param context -* The internal SMIF context data. \ref cy_stc_smif_context_t +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the command transmission. * - \ref CY_SMIF_SUCCESS @@ -863,7 +918,10 @@ cy_en_smif_status_t Cy_SMIF_MemCmdWriteStatus(SMIF_Type *base, * The device to which the command is sent * * \param context -* The internal SMIF context data. \ref cy_stc_smif_context_t +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the command transmission. * - \ref CY_SMIF_SUCCESS @@ -911,7 +969,10 @@ cy_en_smif_status_t Cy_SMIF_MemCmdChipErase(SMIF_Type *base, * The sector address to erase. * * \param context -* The internal SMIF context data. \ref cy_stc_smif_context_t +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the command transmission. * - \ref CY_SMIF_SUCCESS @@ -927,15 +988,21 @@ cy_en_smif_status_t Cy_SMIF_MemCmdSectorErase(SMIF_Type *base, { cy_en_smif_status_t result = CY_SMIF_BAD_PARAM; + CY_ASSERT_L1(NULL != memDevice); + if (NULL != sectorAddr) { - cy_stc_smif_mem_device_cfg_t *device = memDevice->deviceCfg; cy_stc_smif_mem_cmd_t *cmdErase = device->eraseCmd; - - if ((NULL != cmdErase) && (CY_SMIF_WIDTH_NA != cmdErase->cmdWidth)) + cy_stc_smif_hybrid_region_info_t* hybrInfo = NULL; + + result = Cy_SMIF_MemLocateHybridRegion(memDevice, &hybrInfo, + ByteArrayToValue(sectorAddr, device->numOfAddrBytes)); + + if ((NULL != cmdErase) && (CY_SMIF_WIDTH_NA != cmdErase->cmdWidth) && (result != CY_SMIF_BAD_PARAM)) { - result = Cy_SMIF_TransmitCommand( base, (uint8_t)cmdErase->command, + uint8_t eraseCommand = (uint8_t)((result == CY_SMIF_SUCCESS) ? (hybrInfo->eraseCmd) : (cmdErase->command)); + result = Cy_SMIF_TransmitCommand( base, eraseCommand, cmdErase->cmdWidth, sectorAddr, device->numOfAddrBytes, cmdErase->cmdWidth, memDevice->slaveSelect, CY_SMIF_TX_LAST_BYTE, context); @@ -987,7 +1054,10 @@ cy_en_smif_status_t Cy_SMIF_MemCmdSectorErase(SMIF_Type *base, * as no callback. * * \param context -* The internal SMIF context data. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of a transmission. * - \ref CY_SMIF_SUCCESS @@ -1092,7 +1162,10 @@ cy_en_smif_status_t Cy_SMIF_MemCmdProgram(SMIF_Type *base, * as no callback. * * \param context -* The internal SMIF context data. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the transmission. * - \ref CY_SMIF_SUCCESS @@ -1160,6 +1233,72 @@ cy_en_smif_status_t Cy_SMIF_MemCmdRead(SMIF_Type *base, } +/******************************************************************************* +* Function Name: Cy_SMIF_MemLocateHybridRegion +****************************************************************************//** +* +* This function locates the region structure by the address which belongs to it. +* +* \note This function is valid for the memories with hybrid sectors. +* +* \param memDevice +* The memory device configuration. +* +* \param regionInfo +* Places a hybrid region configuration structure that contains the region +* specific parameters. See \ref cy_stc_smif_hybrid_region_info_t for +* reference. +* +* \param address +* The address for which a region is searched. +* +* \return A status of the region location. +* - \ref CY_SMIF_SUCCESS +* - \ref CY_SMIF_NOT_HYBRID_MEM +* - \ref CY_SMIF_BAD_PARAM +* +* \funcusage +* \snippet smif/snippet/main.c snippet_Cy_SMIF_MemLocateHybridRegion +* +*******************************************************************************/ +cy_en_smif_status_t Cy_SMIF_MemLocateHybridRegion(cy_stc_smif_mem_config_t const *memDevice, + cy_stc_smif_hybrid_region_info_t** regionInfo, + uint32_t address) +{ + cy_en_smif_status_t result = CY_SMIF_BAD_PARAM; + cy_stc_smif_hybrid_region_info_t* currInfo = NULL; + CY_ASSERT_L1(NULL != memDevice); + cy_stc_smif_mem_device_cfg_t *device = memDevice->deviceCfg; + + /* Check if the address exceeds the memory size */ + if(address <= device->memSize) + { + result = CY_SMIF_NOT_HYBRID_MEM; + /* Check if the memory is hybrid */ + if(NULL != device->hybridRegionInfo) + { + uint32_t idx; + uint32_t regionStartAddr; + uint32_t regionEndAddr; + for(idx = 0UL; idx < device->hybridRegionCount; idx++) + { + currInfo = device->hybridRegionInfo[idx]; + regionStartAddr = currInfo->regionAddress; + regionEndAddr = regionStartAddr + (currInfo->sectorsCount * currInfo->eraseSize); + if ((address >= regionStartAddr) && (address < regionEndAddr)) + { + *regionInfo = currInfo; + result = CY_SMIF_SUCCESS; + break; + } + } + } + } + + return result; +} + + /******************************************************************************* * Function Name: SfdpReadBuffer ****************************************************************************//** @@ -1192,7 +1331,10 @@ cy_en_smif_status_t Cy_SMIF_MemCmdRead(SMIF_Type *base, * The pointer to an array with the SDFP buffer. * * \param context -* Internal SMIF context data. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the transmission. * - \ref CY_SMIF_SUCCESS @@ -1828,48 +1970,53 @@ static uint32_t SfdpGetPageSize(uint8_t const sfdpBuffer[]) * \param sfdpBuffer * The pointer to an array with the SDFP buffer. * -* \return Erase time in us. +* \param eraseTypeTime +* The pointer to an array with the erase time in us for different erase types. +* +* \return Default erase time in us. * *******************************************************************************/ -static uint32_t SfdpGetEraseTime(uint32_t const eraseOffset, uint8_t const sfdpBuffer[]) +static uint32_t SfdpGetEraseTime(uint32_t const eraseOffset, uint8_t const sfdpBuffer[], cy_stc_smif_erase_type_t eraseType[]) { /* Get the value of 10th DWORD from the JEDEC basic flash parameter table */ uint32_t readEraseTime = ((uint32_t*)sfdpBuffer)[CY_SMIF_JEDEC_BFPT_10TH_DWORD]; - uint32_t eraseTimeMax; - uint32_t eraseTimeIndex = (((eraseOffset - CY_SMIF_SFDP_BFPT_BYTE_1D) + TYPE_STEP) / TYPE_STEP); - uint32_t eraseUnits = _FLD2VAL(ERASE_T_UNITS, - (readEraseTime >> ((eraseTimeIndex - 1UL) * ERASE_T_LENGTH)) - >> ERASE_T_COUNT_OFFSET); - uint32_t eraseCount = _FLD2VAL(ERASE_T_COUNT, - (readEraseTime >> ((eraseTimeIndex - 1UL) * ERASE_T_LENGTH)) - >> ERASE_T_COUNT_OFFSET); + uint32_t eraseTimeDefaultIndex = (((eraseOffset - CY_SMIF_SFDP_BFPT_BYTE_1D) + TYPE_STEP) / TYPE_STEP); uint32_t eraseMul = _FLD2VAL(CY_SMIF_SFDP_ERASE_MUL_COUNT, readEraseTime); + uint32_t eraseUnits = 0UL; + uint32_t eraseCount = 0UL; uint32_t eraseMs = 0UL; + uint32_t eraseTypeTypicalTime; - switch (eraseUnits) - { - case CY_SMIF_SFDP_UNIT_0: - eraseMs = CY_SMIF_SFDP_ERASE_TIME_1MS; - break; - case CY_SMIF_SFDP_UNIT_1: - eraseMs = CY_SMIF_SFDP_ERASE_TIME_16MS; - break; - case CY_SMIF_SFDP_UNIT_2: - eraseMs = CY_SMIF_SFDP_ERASE_TIME_128MS; - break; - case CY_SMIF_SFDP_UNIT_3: - eraseMs = CY_SMIF_SFDP_ERASE_TIME_1S; - break; - default: - /* An unsupported SFDP value */ - break; + for (uint32_t idx = 0UL; idx < ERASE_TYPE_COUNT; idx++){ + eraseTypeTypicalTime = (readEraseTime >> (idx * ERASE_T_LENGTH))>> ERASE_T_COUNT_OFFSET; + eraseUnits = _FLD2VAL(ERASE_T_UNITS, eraseTypeTypicalTime); + eraseCount = _FLD2VAL(ERASE_T_COUNT, eraseTypeTypicalTime); + + switch (eraseUnits) + { + case CY_SMIF_SFDP_UNIT_0: + eraseMs = CY_SMIF_SFDP_ERASE_TIME_1MS; + break; + case CY_SMIF_SFDP_UNIT_1: + eraseMs = CY_SMIF_SFDP_ERASE_TIME_16MS; + break; + case CY_SMIF_SFDP_UNIT_2: + eraseMs = CY_SMIF_SFDP_ERASE_TIME_128MS; + break; + case CY_SMIF_SFDP_UNIT_3: + eraseMs = CY_SMIF_SFDP_ERASE_TIME_1S; + break; + default: + /* An unsupported SFDP value */ + break; + } + + /* Convert typical time to max time */ + eraseType[idx].eraseTime = ((eraseCount + 1UL) * eraseMs) * (2UL * (eraseMul + 1UL)); } - /* Convert typical time to max time */ - eraseTimeMax = ((eraseCount + 1UL) * eraseMs) * (2UL * (eraseMul + 1UL)); - - return(eraseTimeMax); + return(eraseType[eraseTimeDefaultIndex - 1UL].eraseTime); } @@ -2328,12 +2475,16 @@ static void SfdpSetChipEraseCommand(cy_stc_smif_mem_cmd_t* cmdChipErase) * \param sfdpBuffer * The pointer to an array with the SDFP buffer. * +* \param eraseTypeCmd +* The pointer to an array with the erase commands for different erase types. +* * \return The offset of the Sector Erase command in the SFDP buffer. * Returns 0 when the Sector Erase command is not found. * *******************************************************************************/ static uint32_t SfdpGetSectorEraseCommand(cy_stc_smif_mem_device_cfg_t *device, - uint8_t const sfdpBuffer[]) + uint8_t const sfdpBuffer[], + cy_stc_smif_erase_type_t eraseTypeStc[]) { uint32_t eraseOffset; if (FOUR_BYTE_ADDRESS == device->numOfAddrBytes) @@ -2364,6 +2515,11 @@ static uint32_t SfdpGetSectorEraseCommand(cy_stc_smif_mem_device_cfg_t *device, /* Calculate the offset for the sector Erase command in the 4-byte Address Instruction Table, DWORD 2 */ eraseOffset = FOUR_BYTE_ADDR_ERASE_TYPE_1 + eraseType; + /* Update all erase commands for 4-bytes*/ + for(uint32_t i = 0UL; i< ERASE_TYPE_COUNT; i++) + { + eraseTypeStc[i].eraseCmd = sfdpBuffer[FOUR_BYTE_ADDR_ERASE_TYPE_1 + i]; + } /* Get the sector Erase command * from the 4-byte Address Instruction Table, DWORD 2 */ @@ -2413,6 +2569,371 @@ static uint32_t SfdpGetSectorEraseCommand(cy_stc_smif_mem_device_cfg_t *device, } +/******************************************************************************* +* Function Name: ReadAnyReg +****************************************************************************//** +* +* This function reads any registers by address. This function is a blocking +* function, it will block the execution flow until the status register is read. +* +* \param base +* Holds the base address of the SMIF block registers. +* +* \param slaveSelect +* The slave select line for the device. +* +* \param value +* The value of the register. +* +* \param command +* The command required to read the status/configuration register. +* +* \param address +* The register address array. +* +* \param addressSize +* The size of the address array. +* +* \param context +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. +* +* \return A status of the command reception. +* - \ref CY_SMIF_SUCCESS +* - \ref CY_SMIF_CMD_FIFO_FULL +* - \ref CY_SMIF_EXCEED_TIMEOUT +* - \ref CY_SMIF_CMD_NOT_FOUND +* +*******************************************************************************/ +static cy_en_smif_status_t ReadAnyReg(SMIF_Type *base, + cy_en_smif_slave_select_t slaveSelect, + uint8_t *value, + uint8_t command, + uint8_t const *address, + uint32_t addressSize, + cy_stc_smif_context_t const *context) +{ + cy_en_smif_status_t result = CY_SMIF_CMD_NOT_FOUND; + + /* Read the memory register */ + result = Cy_SMIF_TransmitCommand(base, command, CY_SMIF_WIDTH_SINGLE, + address, addressSize, + CY_SMIF_WIDTH_SINGLE, slaveSelect, + CY_SMIF_TX_NOT_LAST_BYTE, context); + + if (CY_SMIF_SUCCESS == result) + { + result = Cy_SMIF_ReceiveDataBlocking( base, value, + CY_SMIF_READ_ONE_BYTE, CY_SMIF_WIDTH_SINGLE, context); + } + + return(result); +} + + +/******************************************************************************* +* Function Name: SfdpEnterFourByteAddressing +****************************************************************************//** +* +* This function sets 4-byte address mode for a memory device as defined in +* 16th DWORD of JEDEC Basic Flash Parameter Table. +* +* \note The entry methods which do not support the required +* operation of writing into the register. +* +* \param base +* Holds the base address of the SMIF block registers. +* +* \param entryMethodByte +* The byte which defines the supported method to enter 4-byte addressing mode. +* +* \param device +* The device structure instance declared by the user. This is where the detected +* parameters are stored and returned. +* +* \param slaveSelect +* The slave select line for the device. +* +* \param context +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. +* +* \return A status of 4-byte addressing mode command transmit. +* - \ref CY_SMIF_SUCCESS +* - \ref CY_SMIF_EXCEED_TIMEOUT +* - \ref CY_SMIF_CMD_NOT_FOUND +*******************************************************************************/ +static cy_en_smif_status_t SfdpEnterFourByteAddressing(SMIF_Type *base, uint8_t entryMethodByte, + cy_stc_smif_mem_device_cfg_t *device, + cy_en_smif_slave_select_t slaveSelect, + cy_stc_smif_context_t const *context) +{ + cy_en_smif_status_t result = CY_SMIF_CMD_NOT_FOUND; + if ((entryMethodByte & CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_ALWAYS_4_BYTE) != 0U) + { + /* Memory always operates in 4-byte mode */ + result = CY_SMIF_SUCCESS; + } + if ((entryMethodByte & CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_B7) != 0U) + { + if ((entryMethodByte & CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_WR_EN_B7) != 0U) + { + /* To enter a 4-byte addressing write enable is required */ + cy_stc_smif_mem_cmd_t* writeEn = device->writeEnCmd; + if(NULL != writeEn) + { + result = Cy_SMIF_TransmitCommand(base, + (uint8_t) writeEn->command, + writeEn->cmdWidth, + CY_SMIF_CMD_WITHOUT_PARAM, + CY_SMIF_CMD_WITHOUT_PARAM, + CY_SMIF_WIDTH_NA, + slaveSelect, + CY_SMIF_TX_LAST_BYTE, + context); + } + } + if ((CY_SMIF_CMD_NOT_FOUND == result) || (CY_SMIF_SUCCESS == result)) + { + /* To enter a 4-byte addressing B7 instruction is required*/ + result = Cy_SMIF_TransmitCommand(base, + CY_SMIF_SFDP_ENTER_4_BYTE_METHOD_B7_CMD, + CY_SMIF_WIDTH_SINGLE, + CY_SMIF_CMD_WITHOUT_PARAM, + CY_SMIF_CMD_WITHOUT_PARAM, + CY_SMIF_WIDTH_NA, + slaveSelect, + CY_SMIF_TX_LAST_BYTE, + context); + } + } + + return result; +} + + +/******************************************************************************* +* Function Name: SfdpGetEraseSizeAndCmd +****************************************************************************//** +* +* Fills arrays with an erase size and cmd for all erase types. +* +* \param sfdpBuffer +* The pointer to an array with the Basic Flash Parameter table buffer. +* +* \param eraseTypeCmd +* The pointer to an array with the erase commands for all erase types. +* +* \param eraseTypeSize +* The pointer to an array with the erase size for all erase types. +* +*******************************************************************************/ +static void SfdpGetEraseSizeAndCmd(uint8_t const sfdpBuffer[], + cy_stc_smif_erase_type_t eraseType[]) +{ + uint32_t idx = 0UL; + for (uint32_t currET = 0UL; currET < ERASE_TYPE_COUNT; currET++) + { + /* The erase size in the SFDP buffer defined as power of two */ + eraseType[currET].eraseSize = 1UL << sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_1C + idx]; + eraseType[currET].eraseCmd = sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_1D + idx]; + idx += TYPE_STEP; + } +} + + +/******************************************************************************* +* Function Name: SfdpPopulateRegionInfo +****************************************************************************//** +* +* Reads the current configuration for regions and populates regionInfo +* structures. +* +* \param base +* Holds the base address of the SMIF block registers. +* +* \param sectorMapBuff +* The pointer to an array with the Sector Map Parameter Table buffer. +* +* \param device +* The device structure instance declared by the user. This is where the detected +* parameters are stored and returned. +* +* \param slaveSelect +* The slave select line for the device. +* +* \param context +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. +* +* \param eraseTypeSize +* The pointer to an array with the erase size for all erase types. +* +* \param eraseTypeCmd +* The pointer to an array with the erase commands for all erase types. +* +* \param eraseTypeTime +* The pointer to an array with the erase time for all erase types. +* +* \return A status of the Sector Map Parameter Table parsing. +* - \ref CY_SMIF_SUCCESS +* - \ref CY_SMIF_SFDP_CORRUPTED_TABLE +* - \ref CY_SMIF_NOT_HYBRID_MEM +* +*******************************************************************************/ +static cy_en_smif_status_t SfdpPopulateRegionInfo(SMIF_Type *base, + uint8_t const sectorMapBuff[], + uint32_t const buffLength, + cy_stc_smif_mem_device_cfg_t *device, + cy_en_smif_slave_select_t slaveSelect, + const cy_stc_smif_context_t *context, + cy_stc_smif_erase_type_t eraseType[]) +{ + uint8_t currCmd; + uint8_t regMask; + uint8_t regValue; + uint8_t currRegisterAddr[ERASE_TYPE_COUNT] = {0U}; + uint8_t regionInfoIdx = 0U; + uint32_t currTableIdx = 0UL; + uint32_t addrBytesNum = 0UL; + uint32_t addrCode = 0UL; + cy_en_smif_status_t result = CY_SMIF_NOT_HYBRID_MEM; + + /* Loop across all command descriptors to find current configuration */ + while(SECTOR_MAP_COMAND_DESCRIPTOR_TYPE == (sectorMapBuff[currTableIdx] & SECTOR_MAP_DESCRIPTOR_MASK)) + { + currCmd = sectorMapBuff[currTableIdx + CY_SMIF_SFDP_SECTOR_MAP_CMD_OFFSET]; + regMask = sectorMapBuff[currTableIdx + CY_SMIF_SFDP_SECTOR_MAP_REG_MSK_OFFSET]; + regValue = 0U; + + /* Get the address length for configuration detection */ + addrCode = _FLD2VAL(CY_SMIF_SFDP_SECTOR_MAP_ADDR_BYTES, sectorMapBuff[currTableIdx + CY_SMIF_SFDP_SECTOR_MAP_ADDR_CODE_OFFSET]); + switch(addrCode) + { + case CY_SMIF_SFDP_THREE_BYTES_ADDR_CODE: + /* No address cycle */ + addrBytesNum = 0UL; + break; + case CY_SMIF_SFDP_THREE_OR_FOUR_BYTES_ADDR_CODE: + addrBytesNum = CY_SMIF_THREE_BYTES_ADDR; + break; + case CY_SMIF_SFDP_FOUR_BYTES_ADDR_CODE: + addrBytesNum = CY_SMIF_FOUR_BYTES_ADDR; + break; + default: + /* Use the current settings */ + addrBytesNum = device->numOfAddrBytes; + break; + } + + /* Get the control register address */ + for(uint32_t i = 0UL; i < addrBytesNum; i++) + { + /* Offset for control register in SFDP has little-endian byte order, need to swap it */ + currRegisterAddr[i] = sectorMapBuff[(currTableIdx + CY_SMIF_SFDP_SECTOR_MAP_REG_ADDR_OFFSET + addrBytesNum) - i - 1UL]; + } + + /* Read the value of the register for the current configuration detection*/ + result = ReadAnyReg(base, slaveSelect, ®Value, currCmd, &currRegisterAddr[0], addrBytesNum, context); + + if (CY_SMIF_SUCCESS == result) + { + /* Set the bit of the region idx to 1 if the config matches */ + regionInfoIdx = ((uint8_t)(regionInfoIdx << 1U)) | (((regValue & regMask) == 0U)?(0U):(1U)); + } + + currTableIdx += HEADER_LENGTH; + if (currTableIdx > buffLength) + { + result = CY_SMIF_SFDP_CORRUPTED_TABLE; + break; + } + } + + if (CY_SMIF_SUCCESS == result) + { + /* Find the matching configuration map descriptor */ + while(regionInfoIdx != sectorMapBuff[currTableIdx + 1UL]) + { + /* Increment the table index to the next map */ + currTableIdx += (sectorMapBuff[currTableIdx + CY_SMIF_SFDP_SECTOR_MAP_CONFIG_ID_OFFSET] + 2UL) * BYTES_IN_DWORD; + if (currTableIdx > buffLength) + { + result = CY_SMIF_SFDP_CORRUPTED_TABLE; + break; + } + } + } + + if (CY_SMIF_SUCCESS == result) + { + /* Populate region data from the sector map */ + uint8_t numOfRegions = sectorMapBuff[currTableIdx + CY_SMIF_SFDP_SECTOR_MAP_REGION_COUNT_OFFSET] + 1U; + device->hybridRegionCount = (uint32_t) numOfRegions; + + if(numOfRegions <= 1U) + { + result = CY_SMIF_NOT_HYBRID_MEM; + } + else + { + uint8_t eraseTypeCode; + uint32_t currRegionAddr = 0UL; + uint32_t regionSize = 0UL; + uint8_t supportedEraseType; + uint8_t eraseTypeMask; + cy_stc_smif_hybrid_region_info_t *currRegionPtr; + for(uint8_t currRegion = 0U; currRegion< numOfRegions; currRegion++) + { + currRegionAddr = currRegionAddr + regionSize; + currTableIdx += BYTES_IN_DWORD; + + supportedEraseType = 0U; + eraseTypeMask = 1U; + eraseTypeCode = sectorMapBuff[currTableIdx] & CY_SMIF_SFDP_SECTOR_MAP_SUPPORTED_ET_MASK; + while(0U == (eraseTypeCode & eraseTypeMask)) + { + /* Erase type number defined as a bit position */ + eraseTypeMask = eraseTypeMask << 1; + supportedEraseType++; + if(supportedEraseType > ERASE_TYPE_COUNT) + { + result = CY_SMIF_SFDP_CORRUPTED_TABLE; + break; + } + } + + /* The region size as a zero-based count of 256 byte units */ + regionSize = ((*( (uint32_t*) §orMapBuff[currTableIdx]) >> BITS_IN_BYTE) + 1UL) * SECTOR_MAP_REGION_SIZE_MULTIPLIER; + currRegionPtr = device->hybridRegionInfo[currRegion]; + + currRegionPtr->regionAddress = currRegionAddr; + currRegionPtr->eraseCmd = (uint32_t)eraseType[supportedEraseType].eraseCmd; + currRegionPtr->eraseTime = eraseType[supportedEraseType].eraseTime; + if(regionSize < eraseType[supportedEraseType].eraseSize) + { + /* One region with a single sector */ + currRegionPtr->eraseSize = regionSize; + currRegionPtr->sectorsCount = 1UL; + } + else + { + currRegionPtr->eraseSize = eraseType[supportedEraseType].eraseSize; + currRegionPtr->sectorsCount = regionSize / eraseType[supportedEraseType].eraseSize; + } + } + } + } + return result; +} + + /******************************************************************************* * Function Name: Cy_SMIF_MemSfdpDetect ****************************************************************************//** @@ -2457,7 +2978,10 @@ static uint32_t SfdpGetSectorEraseCommand(cy_stc_smif_mem_device_cfg_t *device, * The data line selection options for a slave device. * * \param context -* Internal SMIF context data. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return A status of the transmission. * - \ref CY_SMIF_SUCCESS @@ -2478,8 +3002,10 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, uint8_t sfdpBuffer[CY_SMIF_SFDP_LENGTH]; uint8_t sfdpAddress[CY_SMIF_SFDP_ADDRESS_LENGTH] = {0x00U, 0x00U, 0x00U}; uint8_t addr4ByteAddress[CY_SMIF_SFDP_ADDRESS_LENGTH] = {0x00U, 0x00U, 0x00U}; + uint8_t sectorMapAddr[CY_SMIF_SFDP_ADDRESS_LENGTH] = {0x00U, 0x00U, 0x00U}; cy_en_smif_status_t result = CY_SMIF_NO_SFDP_SUPPORT; cy_stc_smif_mem_cmd_t *cmdSfdp = device->readSfdpCmd; + cy_stc_smif_erase_type_t eraseType[ERASE_TYPE_COUNT]; /* Initialize the SFDP buffer */ for (uint32_t i = 0U; i < CY_SMIF_SFDP_LENGTH; i++) @@ -2522,11 +3048,21 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, uint32_t id = (FOUR_BYTE_ADDR_ID_MSB << BITS_IN_BYTE) | FOUR_BYTE_ADDR_ID_LSB; uint32_t addr4ByteTableLength = 0UL; result = SfdpFindParameterTableAddress(id, sfdpBuffer, addr4ByteAddress, &addr4ByteTableLength); - + + /* Find the Sector Map Parameter Header */ + id = (SECTOR_MAP_ID_MSB << BITS_IN_BYTE) | SECTOR_MAP_ID_LSB; + uint32_t sectorMapTableLength = 0UL; + result = SfdpFindParameterTableAddress(id, sfdpBuffer, sectorMapAddr, §orMapTableLength); + if (CY_SMIF_CMD_NOT_FOUND == result) + { + device->hybridRegionCount = 0UL; + device->hybridRegionInfo = NULL; + } + /* Find the JEDEC SFDP Basic SPI Flash Parameter Header */ id = (BASIC_SPI_ID_MSB << BITS_IN_BYTE) | BASIC_SPI_ID_LSB; uint32_t basicSpiTableLength = 0UL; - result = SfdpFindParameterTableAddress(id, sfdpBuffer, sfdpAddress, &basicSpiTableLength); + result = SfdpFindParameterTableAddress(id, sfdpBuffer, sfdpAddress, &basicSpiTableLength); if (CY_SMIF_SUCCESS == result) { @@ -2536,10 +3072,10 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, CY_ASSERT_L1(NULL != device->eraseCmd); CY_ASSERT_L1(NULL != device->chipEraseCmd); CY_ASSERT_L1(NULL != device->programCmd); - CY_ASSERT_L1(NULL != device->readStsRegWipCmd); + CY_ASSERT_L1(NULL != device->readStsRegWipCmd); /* Get the JEDEC basic flash parameter table content into sfdpBuffer[] */ - result = SfdpReadBuffer(base, + result = SfdpReadBuffer(base, cmdSfdp, sfdpAddress, slaveSelect, @@ -2547,24 +3083,27 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, sfdpBuffer, context); + /* The erase size and erase time for all 4 erase types */ + SfdpGetEraseSizeAndCmd(sfdpBuffer, eraseType); + /* The number of address bytes used by the memory slave device */ device->numOfAddrBytes = SfdpGetNumOfAddrBytes(sfdpBuffer); /* The external memory size */ device->memSize = SfdpGetMemoryDensity(sfdpBuffer); - + /* The page size */ device->programSize = SfdpGetPageSize(sfdpBuffer); /* The Write Enable command */ - SfdpSetWriteEnableCommand(device->writeEnCmd); + SfdpSetWriteEnableCommand(device->writeEnCmd); /* The Write Disable command */ SfdpSetWriteDisableCommand(device->writeDisCmd); /* The busy mask for the status registers */ device->stsRegBusyMask = CY_SMIF_STATUS_REG_BUSY_MASK; - + /* The command to read the WIP-containing status register */ SfdpSetWipStatusRegisterCommand(device->readStsRegWipCmd); @@ -2573,13 +3112,13 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, /* Chip Erase command */ SfdpSetChipEraseCommand(device->chipEraseCmd); - + /* Chip Erase Time */ device->chipEraseTime = SfdpGetChipEraseTime(sfdpBuffer); /* Page Program Time */ device->programTime = SfdpGetPageProgramTime(sfdpBuffer); - + /* The Read command for 3-byte addressing. The preference order quad > dual > single SPI */ cy_stc_smif_mem_cmd_t *cmdRead = device->readCmd; cy_en_smif_protocol_mode_t pMode = SfdpGetReadCmdParams(sfdpBuffer, dataSelect, cmdRead); @@ -2588,11 +3127,15 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, uint32_t eraseTypeOffset = 1UL; if (FOUR_BYTE_ADDRESS == device->numOfAddrBytes) { - /* Get the JEDEC 4-byte Address Instruction Table content into sfdpBuffer[] */ + /* Enter 4-byte addressing mode */ + result = SfdpEnterFourByteAddressing(base, sfdpBuffer[CY_SMIF_SFDP_BFPT_BYTE_3C], device, slaveSelect, context); uint8_t fourByteAddressBuffer[CY_SMIF_SFDP_LENGTH]; - result = SfdpReadBuffer(base, cmdSfdp, addr4ByteAddress, slaveSelect, - addr4ByteTableLength, fourByteAddressBuffer, context); - + if (CY_SMIF_SUCCESS == result) + { + /* Get the JEDEC 4-byte Address Instruction Table content into sfdpBuffer[] */ + result = SfdpReadBuffer(base, cmdSfdp, addr4ByteAddress, slaveSelect, + addr4ByteTableLength, fourByteAddressBuffer, context); + } if (CY_SMIF_SUCCESS == result) { /* Rewrite the Read command instruction for 4-byte addressing mode */ @@ -2601,8 +3144,8 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, /* Get the Program command instruction for 4-byte addressing mode */ SfdpGetProgramFourBytesCmd(fourByteAddressBuffer, pMode, device->programCmd); - /* Find the sector Erase command type with 4-byte addressing */ - eraseTypeOffset = SfdpGetSectorEraseCommand(device, fourByteAddressBuffer); + /* Find the sector Erase command type with 4-byte addressing */ + eraseTypeOffset = SfdpGetSectorEraseCommand(device, fourByteAddressBuffer, eraseType); } } else @@ -2611,7 +3154,7 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, SfdpSetProgramCommand_1_1_1(device->programCmd); /* Find the sector Erase command type with 3-byte addressing */ - eraseTypeOffset = SfdpGetSectorEraseCommand(device, sfdpBuffer); + eraseTypeOffset = SfdpGetSectorEraseCommand(device, sfdpBuffer, eraseType); } if (COMMAND_IS_NOT_FOUND != eraseTypeOffset) @@ -2620,7 +3163,24 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, device->eraseSize = 0x01UL << sfdpBuffer[eraseTypeOffset - 1UL]; /* Erase Time Type (from the JEDEC basic flash parameter table) */ - device->eraseTime = SfdpGetEraseTime(eraseTypeOffset, sfdpBuffer); + device->eraseTime = SfdpGetEraseTime(eraseTypeOffset, sfdpBuffer, eraseType); + } + + if (NULL != device->hybridRegionInfo) + { + /* Get the Sector Map Parameter Table into sfdpBuffer[] */ + result = SfdpReadBuffer(base, cmdSfdp, sectorMapAddr, slaveSelect, + sectorMapTableLength, sfdpBuffer, context); + if (CY_SMIF_SUCCESS == result) + { + result = SfdpPopulateRegionInfo(base, sfdpBuffer, sectorMapTableLength, device, slaveSelect, context, eraseType); + if(result == CY_SMIF_NOT_HYBRID_MEM) + { + device->hybridRegionCount = 0UL; + device->hybridRegionInfo = NULL; + result = CY_SMIF_SUCCESS; + } + } } } } @@ -2653,8 +3213,10 @@ cy_en_smif_status_t Cy_SMIF_MemSfdpDetect(SMIF_Type *base, * The timeout value in microseconds to apply while polling the memory. * * \param context -* Passes a configuration structure that contains the transfer parameters of the -* SMIF block. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return The status of the operation. * \ref CY_SMIF_SUCCESS - Memory is ready to accept new commands. @@ -2721,8 +3283,10 @@ cy_en_smif_status_t Cy_SMIF_MemIsReady(SMIF_Type *base, cy_stc_smif_mem_config_t * CY_SMIF_SUCCESS. * * \param context -* Passes a configuration structure that contains the transfer parameters of the -* SMIF block. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return The status of the operation. See \ref cy_en_smif_status_t. * @@ -2771,8 +3335,10 @@ cy_en_smif_status_t Cy_SMIF_MemIsQuadEnabled(SMIF_Type *base, cy_stc_smif_mem_co * The timeout value in microseconds to apply while polling the memory. * * \param context -* Passes a configuration structure that contains the transfer parameters of the -* SMIF block. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return The status of the operation. See \ref cy_en_smif_status_t. * @@ -2821,8 +3387,10 @@ cy_en_smif_status_t Cy_SMIF_MemEnableQuadMode(SMIF_Type *base, cy_stc_smif_mem_c * Transfer status value to be checked. * * \param context -* Passes a configuration structure that contains the transfer parameters of the -* SMIF block. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return The status of the operation. * \ref CY_SMIF_SUCCESS - SMIF block has completed the transfer @@ -2881,6 +3449,36 @@ static void ValueToByteArray(uint32_t value, uint8_t *byteArray, uint32_t startP } +/******************************************************************************* +* Function Name: ByteArrayToValue +****************************************************************************//** +* +* Packs the byte array into a single value. +* +* \param byteArray +* The byte array to unpack. +* +* \param size +* The size of the array. +* +* \return +* The 4-byte value filled from the array. +* +* +*******************************************************************************/ +static uint32_t ByteArrayToValue(uint8_t const *byteArray, uint32_t size) +{ + uint32_t value = 0UL; + uint32_t idx = 0UL; + for (idx = 0UL; idx < size; idx++) + { + value <<= 8; + value |= ((uint32_t) byteArray[idx]); + } + return value; +} + + /******************************************************************************* * Function Name: Cy_SMIF_MemRead ****************************************************************************//** @@ -2906,8 +3504,10 @@ static void ValueToByteArray(uint32_t value, uint8_t *byteArray, uint32_t startP * The size of data to read. * * \param context -* Passes a configuration structure that contains the transfer parameters of the -* SMIF block. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return The status of the operation. See \ref cy_en_smif_status_t. * @@ -2986,8 +3586,10 @@ cy_en_smif_status_t Cy_SMIF_MemRead(SMIF_Type *base, cy_stc_smif_mem_config_t co * The size of data to write. * * \param context -* Passes a configuration structure that contains the transfer parameters of the -* SMIF block. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return The status of the operation. See \ref cy_en_smif_status_t. * @@ -3084,67 +3686,120 @@ cy_en_smif_status_t Cy_SMIF_MemWrite(SMIF_Type *base, cy_stc_smif_mem_config_t c * The size of data to erase. * * \param context -* Passes a configuration structure that contains the transfer parameters of the -* SMIF block. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return The status of the operation. See \ref cy_en_smif_status_t. * +* \note The address should be aligned with the start address of the sector. \n +* The length should be equal to the sum of all erased sectors. +* * \funcusage * \snippet smif/snippet/main.c snippet_Cy_SMIF_MemEraseSector * *******************************************************************************/ -cy_en_smif_status_t Cy_SMIF_MemEraseSector(SMIF_Type *base, cy_stc_smif_mem_config_t const *memConfig, - uint32_t address, uint32_t length, +cy_en_smif_status_t Cy_SMIF_MemEraseSector(SMIF_Type *base, cy_stc_smif_mem_config_t const *memConfig, + uint32_t address, uint32_t length, cy_stc_smif_context_t const *context) { cy_en_smif_status_t status = CY_SMIF_BAD_PARAM; - uint32_t offset = 0UL; - uint32_t chunk = 0UL; + uint32_t endAddress = address + length; + uint32_t eraseEnd = 0UL; + uint32_t hybridRegionStart = 0UL; uint8_t addrArray[CY_SMIF_FOUR_BYTES_ADDR] = {0U}; + cy_stc_smif_hybrid_region_info_t* hybrInfo = NULL; CY_ASSERT_L1(NULL != memConfig); - uint32_t eraseSectorSize = memConfig->deviceCfg->eraseSize; + cy_stc_smif_mem_device_cfg_t *device = memConfig->deviceCfg; + uint32_t eraseSectorSize = device->eraseSize; + uint32_t maxEraseTime = device->eraseTime; - if(((address + length) <= memConfig->deviceCfg->memSize) && /* Check if the address exceeds the memory size */ - (0UL == (address % eraseSectorSize)) && /* Check if the start address and the sector size are aligned */ - (0UL == ((address + length) % eraseSectorSize))) /* Check if the end address and the sector size are aligned */ + /* In case of hybrid memory - update sector size and offset for first sector */ + status = Cy_SMIF_MemLocateHybridRegion(memConfig, &hybrInfo, address); + if (CY_SMIF_SUCCESS == status) { - while(length > 0UL) - { - /* Get the number of bytes which can be erase during one operation */ - offset = address % eraseSectorSize; - chunk = ((offset + length) < eraseSectorSize) ? length : (eraseSectorSize - offset); + hybridRegionStart = hybrInfo->regionAddress; + eraseSectorSize = hybrInfo->eraseSize; + eraseEnd = (hybrInfo->sectorsCount * eraseSectorSize) + hybridRegionStart; + } - /* The Write Enable bit may be cleared by the memory after every successful - * operation of write/erase operations. Therefore, it must be set for - * every loop. - */ - status = Cy_SMIF_MemCmdWriteEnable(base, memConfig, context); + /* Check if the end address not equal to start address */ + if(length == 0UL) + { + status = CY_SMIF_BAD_PARAM; + } - if(CY_SMIF_SUCCESS == status) + /* Check if the start address and the sector size are aligned */ + if((0UL == ((address - hybridRegionStart) % eraseSectorSize)) && (status != CY_SMIF_BAD_PARAM)) + { + /* If the memory is hybrid and there is more than one region to + * erase - update the sector size and offset for the last sector */ + if(endAddress < eraseEnd) + { + status = Cy_SMIF_MemLocateHybridRegion(memConfig, &hybrInfo, (endAddress - 1UL)); + if (CY_SMIF_SUCCESS == status) { - ValueToByteArray(address, &addrArray[0], 0UL, - memConfig->deviceCfg->numOfAddrBytes); + hybridRegionStart = hybrInfo->regionAddress; + eraseSectorSize = hybrInfo->eraseSize; + } + } - /* Send the command to erase one sector */ - status = Cy_SMIF_MemCmdSectorErase(base, (cy_stc_smif_mem_config_t* )memConfig, - (const uint8_t *)addrArray, context); + /* Check if the end address and the sector size are aligned */ + if((0UL == ((endAddress - hybridRegionStart) % eraseSectorSize)) && (status != CY_SMIF_BAD_PARAM)) + { + while(length > 0UL) + { + /* In case of hybrid memory - update erase size and time for current region */ + status = Cy_SMIF_MemLocateHybridRegion(memConfig, &hybrInfo, address); + if (CY_SMIF_SUCCESS == status) + { + maxEraseTime = hybrInfo->eraseTime; + eraseSectorSize = hybrInfo->eraseSize; + hybridRegionStart = hybrInfo->regionAddress; + eraseEnd = (hybrInfo->sectorsCount * eraseSectorSize) + hybridRegionStart; + if(endAddress < eraseEnd) + { + eraseEnd = endAddress; + } + } + else + { + eraseEnd = endAddress; + } - if(CY_SMIF_SUCCESS == status) + while (address < eraseEnd) { - /* Wait until the erase operation is completed or a timeout occurs. eraseTime is in milliseconds */ - status = Cy_SMIF_MemIsReady(base, memConfig, - (memConfig->deviceCfg->eraseTime * ONE_MILLI_IN_MICRO), context); + /* The Write Enable bit may be cleared by the memory after every successful + * operation of write/erase operations. Therefore, it must be set for + * every loop. + */ + status = Cy_SMIF_MemCmdWriteEnable(base, memConfig, context); + if(CY_SMIF_SUCCESS == status) + { + ValueToByteArray(address, &addrArray[0], 0UL, device->numOfAddrBytes); + + /* Send the command to erase one sector */ + status = Cy_SMIF_MemCmdSectorErase(base, (cy_stc_smif_mem_config_t* )memConfig, + (const uint8_t *)addrArray, context); + if(CY_SMIF_SUCCESS == status) + { + /* Wait until the erase operation is completed or a timeout occurs. + * Note: eraseTime is in milliseconds */ + status = Cy_SMIF_MemIsReady(base, memConfig, (maxEraseTime * ONE_MILLI_IN_MICRO), context); - /* Recalculate the next sector address offset */ - address += chunk; - length -= chunk; + /* Recalculate the next sector address offset */ + address += eraseSectorSize; + length -= eraseSectorSize; + } + } + + if(CY_SMIF_SUCCESS != status) + { + break; + } } } - - if(CY_SMIF_SUCCESS != status) - { - break; - } } } @@ -3167,8 +3822,10 @@ cy_en_smif_status_t Cy_SMIF_MemEraseSector(SMIF_Type *base, cy_stc_smif_mem_conf * The memory device configuration. * * \param context -* Passes a configuration structure that contains the transfer parameters of the -* SMIF block. +* This is the pointer to the context structure \ref cy_stc_smif_context_t +* allocated by the user. The structure is used during the SMIF +* operation for internal configuration and data retention. The user must not +* modify anything in this structure. * * \return The status of the operation. See \ref cy_en_smif_status_t. * diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysclk.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysclk.c index 73688148e58..e1c6b4de03a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysclk.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_sysclk.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_sysclk.c -* \version 1.50 +* \version 1.60 * * Provides an API implementation of the sysclk driver. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -63,6 +63,25 @@ void Cy_SysClk_ExtClkSetFrequency(uint32_t freq) extFreq = freq; } } + + +/******************************************************************************* +* Function Name: Cy_SysClk_ExtClkGetFrequency +****************************************************************************//** +* +* Returns the frequency of the External Clock Source (EXTCLK) from the +* internal storage. +* +* \return The frequency of the External Clock Source. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ExtClkSetFrequency +* +*******************************************************************************/ +uint32_t Cy_SysClk_ExtClkGetFrequency(void) +{ + return (extFreq); +} /** \} group_sysclk_ext_funcs */ @@ -280,6 +299,27 @@ cy_en_sysclk_status_t Cy_SysClk_EcoEnable(uint32_t timeoutus) return (retVal); } + + +/******************************************************************************* +* Function Name: Cy_SysClk_EcoGetFrequency +****************************************************************************//** +* +* Returns the frequency of the external crystal oscillator (ECO). +* +* \return The frequency of the ECO. +* +* \note If the ECO is not enabled or stable - a zero is returned. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_EcoEnable +* +*******************************************************************************/ +uint32_t Cy_SysClk_EcoGetFrequency(void) +{ + return ((CY_SYSCLK_ECOSTAT_STABLE == Cy_SysClk_EcoGetStatus()) ? ecoFreq : 0UL); +} + /** \} group_sysclk_eco_funcs */ @@ -372,6 +412,131 @@ cy_en_clkpath_in_sources_t Cy_SysClk_ClkPathGetSource(uint32_t clkPath) } return (retVal); } + + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkPathMuxGetFrequency +****************************************************************************//** +* +* Returns the output frequency of the clock path mux. +* +* \return The output frequency of the path mux. +* +* \note If the return value equals zero, that means either: +* - the selected path mux source signal frequency is unknown (e.g. dsi_out, etc.) or +* - the selected path mux source is not configured/enabled/stable (e.g. ECO, EXTCLK, etc.). +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkPathSetSource +* +*******************************************************************************/ +uint32_t Cy_SysClk_ClkPathMuxGetFrequency(uint32_t clkPath) +{ + CY_ASSERT_L1(clkPath < CY_SRSS_NUM_CLKPATH); + + uint32_t freq = 0UL; /* The path mux output frequency in Hz, 0 = an unknown frequency */ + + /* Get the frequency of the source, i.e., the path mux input */ + switch(Cy_SysClk_ClkPathGetSource(clkPath)) + { + case CY_SYSCLK_CLKPATH_IN_IMO: /* The IMO frequency is fixed at 8 MHz */ + freq = CY_SYSCLK_IMO_FREQ; + break; + + case CY_SYSCLK_CLKPATH_IN_EXT: + freq = Cy_SysClk_ExtClkGetFrequency(); + break; + + case CY_SYSCLK_CLKPATH_IN_ECO: + freq = Cy_SysClk_EcoGetFrequency(); + break; + + case CY_SYSCLK_CLKPATH_IN_ALTHF: + freq = Cy_SysClk_AltHfGetFrequency(); + break; + + case CY_SYSCLK_CLKPATH_IN_ILO: + freq = (0UL != (SRSS_CLK_ILO_CONFIG & SRSS_CLK_ILO_CONFIG_ENABLE_Msk)) ? CY_SYSCLK_ILO_FREQ : 0UL; + break; + + case CY_SYSCLK_CLKPATH_IN_WCO: + freq = (Cy_SysClk_WcoOkay()) ? CY_SYSCLK_WCO_FREQ : 0UL; + break; + + case CY_SYSCLK_CLKPATH_IN_PILO: + freq = (0UL != (SRSS_CLK_PILO_CONFIG & SRSS_CLK_PILO_CONFIG_PILO_EN_Msk)) ? CY_SYSCLK_PILO_FREQ : 0UL; + break; + + case CY_SYSCLK_CLKPATH_IN_ALTLF: + freq = Cy_SysClk_AltLfGetFrequency(); + break; + + default: + /* Don't know the frequency of dsi_out, leave freq = 0UL */ + break; + } + + return (freq); +} + + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkPathGetFrequency +****************************************************************************//** +* +* Returns the output frequency of the clock path mux. +* +* \return The output frequency of the path mux. +* +* \note If the return value equals zero, that means either: +* - the selected path mux source signal frequency is unknown (e.g. dsi_out, etc.) or +* - the selected path mux source is not configured/enabled/stable (e.g. ECO, EXTCLK, etc.). +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_FllEnable +* +*******************************************************************************/ +uint32_t Cy_SysClk_ClkPathGetFrequency(uint32_t clkPath) +{ + CY_ASSERT_L1(clkPath < CY_SRSS_NUM_CLKPATH); + + uint32_t freq = Cy_SysClk_ClkPathMuxGetFrequency(clkPath); + uint32_t fDiv = 0UL; /* FLL/PLL multiplier/feedback divider */ + uint32_t rDiv = 0UL; /* FLL/PLL reference divider */ + uint32_t oDiv = 0UL; /* FLL/PLL output divider */ + bool enabled = false; /* FLL or PLL enable status; n/a for direct */ + + if (clkPath == (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH0) /* FLL? (always path 0) */ + { + cy_stc_fll_manual_config_t fllCfg = {0UL,0U,CY_SYSCLK_FLL_CCO_RANGE0,false,0U,0U,0U,0U,CY_SYSCLK_FLLPLL_OUTPUT_AUTO,0U}; + Cy_SysClk_FllGetConfiguration(&fllCfg); + enabled = (Cy_SysClk_FllIsEnabled()) && (CY_SYSCLK_FLLPLL_OUTPUT_INPUT != fllCfg.outputMode); + fDiv = fllCfg.fllMult; + rDiv = fllCfg.refDiv; + oDiv = (fllCfg.enableOutputDiv) ? 2UL : 1UL; + } + else if (clkPath <= CY_SRSS_NUM_PLL) /* PLL? (always path 1...N)*/ + { + cy_stc_pll_manual_config_t pllcfg = {0U,0U,0U,false,CY_SYSCLK_FLLPLL_OUTPUT_AUTO}; + (void)Cy_SysClk_PllGetConfiguration(clkPath, &pllcfg); + enabled = (Cy_SysClk_PllIsEnabled(clkPath)) && (CY_SYSCLK_FLLPLL_OUTPUT_INPUT != pllcfg.outputMode); + fDiv = pllcfg.feedbackDiv; + rDiv = pllcfg.referenceDiv; + oDiv = pllcfg.outputDiv; + } + else + { + /* Do nothing with the path mux frequency */ + } + + if (enabled) /* If FLL or PLL is enabled and not bypassed */ + { + freq = (uint32_t)CY_SYSLIB_DIV_ROUND(((uint64_t)freq * (uint64_t)fDiv), + ((uint64_t)rDiv * (uint64_t)oDiv)); + } + + return (freq); +} /** \} group_sysclk_path_src_funcs */ @@ -1816,82 +1981,9 @@ cy_en_syspm_status_t Cy_SysClk_DeepSleepCallback(cy_stc_syspm_callback_params_t uint32_t Cy_SysClk_ClkHfGetFrequency(uint32_t clkHf) { /* variables holding intermediate clock frequencies, dividers and FLL/PLL settings */ - bool enabled = false; /* FLL or PLL enable status; n/a for direct */ - uint32_t freq = 0UL; /* path (FLL, PLL, or direct) frequency, in Hz, 0 = unknown frequency */ - uint32_t fDiv = 0UL; /* FLL/PLL multiplier/feedback divider */ - uint32_t rDiv = 0UL; /* FLL/PLL reference divider */ - uint32_t oDiv = 0UL; /* FLL/PLL output divider */ uint32_t pDiv = 1UL << (uint32_t)Cy_SysClk_ClkHfGetDivider(clkHf); /* root prescaler (1/2/4/8) */ uint32_t path = (uint32_t) Cy_SysClk_ClkHfGetSource(clkHf); /* path input for root 0 (clkHf[0]) */ - cy_en_clkpath_in_sources_t source = Cy_SysClk_ClkPathGetSource((uint32_t)path); /* source input for path (FLL, PLL, or direct) */ - - /* get the frequency of the source, i.e., the path mux input */ - switch(source) - { - case CY_SYSCLK_CLKPATH_IN_IMO: /* IMO frequency is fixed at 8 MHz */ - freq = CY_SYSCLK_IMO_FREQ; - break; - - case CY_SYSCLK_CLKPATH_IN_EXT: - freq = extFreq; - break; - - case CY_SYSCLK_CLKPATH_IN_ECO: - freq = (CY_SYSCLK_ECOSTAT_STABLE == Cy_SysClk_EcoGetStatus()) ? ecoFreq : 0UL; - break; - - #if defined(CY_IP_MXBLESS) - case CY_SYSCLK_CLKPATH_IN_ALTHF: - freq = cy_BleEcoClockFreqHz; - break; - #endif /* CY_IP_MXBLESS */ - - case CY_SYSCLK_CLKPATH_IN_ILO: - freq = (0UL != (SRSS_CLK_ILO_CONFIG & SRSS_CLK_ILO_CONFIG_ENABLE_Msk)) ? CY_SYSCLK_ILO_FREQ : 0UL; - break; - - case CY_SYSCLK_CLKPATH_IN_WCO: - freq = (Cy_SysClk_WcoOkay()) ? CY_SYSCLK_WCO_FREQ : 0UL; - break; - - case CY_SYSCLK_CLKPATH_IN_PILO: - freq = (0UL != (SRSS_CLK_PILO_CONFIG & SRSS_CLK_PILO_CONFIG_PILO_EN_Msk)) ? CY_SYSCLK_PILO_FREQ : 0UL; - break; - - default: - /* don't know the frequency of dsi_out, or clk_altlf */ - freq = 0UL; /* unknown frequency */ - break; - } - - if (path == (uint32_t)CY_SYSCLK_CLKHF_IN_CLKPATH0) /* FLL? (always path 0) */ - { - cy_stc_fll_manual_config_t fllCfg = {0UL,0U,CY_SYSCLK_FLL_CCO_RANGE0,false,0U,0U,0U,0U,CY_SYSCLK_FLLPLL_OUTPUT_AUTO,0U}; - Cy_SysClk_FllGetConfiguration(&fllCfg); - enabled = (Cy_SysClk_FllIsEnabled()) && (CY_SYSCLK_FLLPLL_OUTPUT_INPUT != fllCfg.outputMode); - fDiv = fllCfg.fllMult; - rDiv = fllCfg.refDiv; - oDiv = (fllCfg.enableOutputDiv) ? 2UL : 1UL; - } - else if (path <= CY_SRSS_NUM_PLL) /* PLL? (always path 1...N)*/ - { - cy_stc_pll_manual_config_t pllcfg = {0U,0U,0U,false,CY_SYSCLK_FLLPLL_OUTPUT_AUTO}; - (void)Cy_SysClk_PllGetConfiguration(path, &pllcfg); - enabled = (Cy_SysClk_PllIsEnabled(path)) && (CY_SYSCLK_FLLPLL_OUTPUT_INPUT != pllcfg.outputMode); - fDiv = pllcfg.feedbackDiv; - rDiv = pllcfg.referenceDiv; - oDiv = pllcfg.outputDiv; - } - else - { - /* Direct select path */ - } - - if (enabled) /* if FLL or PLL enabled and not bypassed */ - { - freq = (uint32_t)CY_SYSLIB_DIV_ROUND(((uint64_t)freq * (uint64_t)fDiv), - ((uint64_t)rDiv * (uint64_t)oDiv)); - } + uint32_t freq = Cy_SysClk_ClkPathGetFrequency(path); /* Divide the path input frequency down and return the result */ return (CY_SYSLIB_DIV_ROUND(freq, pDiv)); @@ -1900,7 +1992,6 @@ uint32_t Cy_SysClk_ClkHfGetFrequency(uint32_t clkHf) /** \} group_sysclk_clk_hf_funcs */ - /* ========================================================================== */ /* ===================== clk_peripherals SECTION ====================== */ /* ========================================================================== */ @@ -1971,4 +2062,63 @@ uint32_t Cy_SysClk_PeriphGetFrequency(cy_en_divider_types_t dividerType, uint32_ /** \} group_sysclk_clk_peripheral_funcs */ +/** +* \addtogroup group_sysclk_clk_timer_funcs +* \{ +*/ + + +/******************************************************************************* +* Function Name: Cy_SysClk_ClkTimerGetFrequency +****************************************************************************//** +* +* Reports the frequency of the timer clock (clk_timer). +* \note If the the timer clock is not enabled - a zero frequency is reported. +* +* \funcusage +* \snippet sysclk/snippet/main.c snippet_Cy_SysClk_ClkTimerEnable +* +*******************************************************************************/ +uint32_t Cy_SysClk_ClkTimerGetFrequency(void) +{ + uint32_t freq = 0UL; + + if (Cy_SysClk_ClkTimerIsEnabled()) + { + freq = Cy_SysClk_ClkHfGetFrequency(0UL); + + switch (Cy_SysClk_ClkTimerGetSource()) + { + case CY_SYSCLK_CLKTIMER_IN_IMO: + freq = CY_SYSCLK_IMO_FREQ; + break; + + case CY_SYSCLK_CLKTIMER_IN_HF0_NODIV: + break; + + case CY_SYSCLK_CLKTIMER_IN_HF0_DIV2: + freq /= 2UL; + break; + + case CY_SYSCLK_CLKTIMER_IN_HF0_DIV4: + freq /= 4UL; + break; + + case CY_SYSCLK_CLKTIMER_IN_HF0_DIV8: + freq /= 8UL; + break; + + default: + freq = 0UL; + break; + } + } + + /* Divide the input frequency down and return the result */ + return (CY_SYSLIB_DIV_ROUND(freq, 1UL + (uint32_t)Cy_SysClk_ClkTimerGetDivider())); +} + +/** \} group_sysclk_clk_timer_funcs */ + + /* [] END OF FILE */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syslib.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syslib.c index f2a231fd48f..3121c7665b8 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syslib.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syslib.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_syslib.c -* \version 2.50 +* \version 2.50.1 * * Description: * Provides system API implementation for the SysLib driver. * ******************************************************************************** -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syspm.c b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syspm.c index 828d53fcfc2..a2d7434da00 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syspm.c +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/drivers/source/cy_syspm.c @@ -1,12 +1,12 @@ /***************************************************************************//** * \file cy_syspm.c -* \version 4.50 +* \version 5.0 * * This driver provides the source code for API power management. * ******************************************************************************** * \copyright -* Copyright 2016-2019 Cypress Semiconductor Corporation +* Copyright 2016-2020 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -189,6 +189,9 @@ typedef void (*cy_cb_syspm_deep_sleep_t)(cy_en_syspm_waitfor_t waitFor, bool *wa /* Mask for the RAM read assist bits */ #define CPUSS_TRIM_RAM_CTL_RA_MASK ((uint32_t) 0x3U << 8U) +/* Mask for the RAM write check bits */ +#define CPUSS_TRIM_RAM_CTL_WC_MASK (0x3UL << 10U) + /* The define for SROM opcode to set the flash voltage bit */ #define FLASH_VOLTAGE_BIT_ULP_OPCODE (0x0C000003U) @@ -1057,7 +1060,7 @@ he LP mode * are registered. * * \return -* - CY_SYSPM_SUCCESS - Entered the system LP mode. +* - CY_SYSPM_SUCCESS - Entered the system LP mode or the device is already in LP mode. * - CY_SYSPM_INVALID_STATE - The system LP mode was not set. The system LP mode * was not set because the protection context value is higher than zero * (PC > 0) or the device revision does not support modifying registers @@ -1199,7 +1202,7 @@ cy_en_syspm_status_t Cy_SysPm_SystemEnterLp(void) * are registered. * * \return -* - CY_SYSPM_SUCCESS - Entered system ULP mode. +* - CY_SYSPM_SUCCESS - Entered the system ULP mode or the device is already in ULP mode. * - CY_SYSPM_INVALID_STATE - System ULP mode was not set. The ULP mode was not * set because the protection context value is higher than zero (PC > 0) or the * device revision does not support modifying registers (to enter system @@ -1687,7 +1690,8 @@ void Cy_SysPm_ClearHibernateWakeupSource(uint32_t wakeupSource) * See \ref cy_en_syspm_buck_voltage1_t. * * \return -* - CY_SYSPM_SUCCESS - The voltage is set. +* - CY_SYSPM_SUCCESS - The voltage is set as requested. +* (There is no change if the new voltage is the same as the previous voltage.) * - CY_SYSPM_INVALID_STATE - The voltage was not set. The voltage cannot be set * because the protection context value is higher than zero (PC > 0) or the * device revision does not support modifying registers via syscall. @@ -3143,7 +3147,9 @@ static void SetWriteAssistTrimLp(void) *******************************************************************************/ static bool IsVoltageChangePossible(void) { - bool retVal = true; + bool retVal = false; + uint32_t trimRamCheckVal = (CPUSS_TRIM_RAM_CTL & CPUSS_TRIM_RAM_CTL_WC_MASK); + if (Cy_SysLib_GetDevice() == CY_SYSLIB_DEVICE_PSOC6ABLE2) { @@ -3151,6 +3157,13 @@ static bool IsVoltageChangePossible(void) retVal = ((Cy_SysLib_GetDeviceRevision() > SYSPM_DEVICE_PSOC6ABLE2_REV_0B) || (curProtContext == 0U)); } + else + { + CPUSS_TRIM_RAM_CTL &= ~CPUSS_TRIM_RAM_CTL_WC_MASK; + CPUSS_TRIM_RAM_CTL |= ((~trimRamCheckVal) & CPUSS_TRIM_RAM_CTL_WC_MASK); + + retVal = (trimRamCheckVal != (CPUSS_TRIM_RAM_CTL & CPUSS_TRIM_RAM_CTL_WC_MASK)); + } return retVal; } diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/.cymigration b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/.cymigration index af97141caa6..e7a0834a726 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/.cymigration +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/.cymigration @@ -61,7 +61,7 @@ - + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/canfd-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/canfd-1.0.cypersonality index f0350f9baec..ef801e10d06 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/canfd-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/canfd-1.0.cypersonality @@ -3,14 +3,14 @@ @@ -378,7 +381,7 @@ treated."> ((sfid2_10_9_SidFilter$idx << 9U) | sfid2_5_0_SidFilter$idx)}`U, \ .sfid1 = `${sfid1_SidFilter$idx}`U, \ .sfec = `${sfecSidFilter$idx}`, \ - .sft = `${sftSidFilter$idx}`, \ + .sft = `${sftSidFilterVal$idx}`, \ }" /> ((sfid2_10_9_SidFilter$idx << 9U) | sfid2_5_0_SidFilter$idx)}`U" /> - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/connectivity_wifi-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/connectivity_wifi-1.0.cypersonality index b6af7770d73..766a22504ef 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/connectivity_wifi-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/connectivity_wifi-1.0.cypersonality @@ -3,14 +3,14 @@ + @@ -296,8 +297,9 @@ - - + + + @@ -335,7 +337,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/pdm_pcm-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/pdm_pcm-1.0.cypersonality index 99503b3fd4d..754a0f6fa02 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/pdm_pcm-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/pdm_pcm-1.0.cypersonality @@ -3,14 +3,14 @@ + @@ -192,8 +193,9 @@ - - + + + @@ -218,7 +220,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/seglcd-1.1.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/seglcd-1.1.cypersonality index 2b6285774ee..8c5c631cca3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/seglcd-1.1.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/seglcd-1.1.cypersonality @@ -3,14 +3,14 @@ - - + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/smif-1.1.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/smif-1.1.cypersonality index 4eacb689b1e..9079ed46d1b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/smif-1.1.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/peripheral/smif-1.1.cypersonality @@ -3,14 +3,14 @@ - + @@ -70,7 +70,7 @@ - + @@ -78,7 +78,7 @@ - + @@ -86,7 +86,7 @@ - + @@ -94,7 +94,7 @@ - + @@ -102,7 +102,7 @@ - + @@ -110,7 +110,7 @@ - + @@ -118,7 +118,7 @@ - + @@ -128,7 +128,7 @@ - + @@ -136,7 +136,7 @@ - + @@ -144,7 +144,7 @@ - + @@ -152,7 +152,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/dma-1.0.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/dma-1.0.cypersonality index 14847f18b3a..4014dd92ec6 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/dma-1.0.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/dma-1.0.cypersonality @@ -3,14 +3,14 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/sysclock-1.2.cypersonality b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/sysclock-1.2.cypersonality index 4e4b6e146cf..66c39e46968 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/sysclock-1.2.cypersonality +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/personalities/platform/sysclock-1.2.cypersonality @@ -343,6 +343,7 @@ + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/001-91989.revision b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/001-91989.revision new file mode 100644 index 00000000000..b5f91032683 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/001-91989.revision @@ -0,0 +1 @@ +CG \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/MXS40.revision b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/MXS40.revision new file mode 100644 index 00000000000..3cafba36f13 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/MXS40.revision @@ -0,0 +1 @@ +258628 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/base/view.xml new file mode 100644 index 00000000000..3900a174c79 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/base/view.xml @@ -0,0 +1,16 @@ + + + 0x00000000 + 0x000 + 0 + 0 + CortexM4 + Cypress + 0 + 1310720 + 251-WLCSP + 251 + 3200 + 4400 + The CYW43012C0WKWBG device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/info.xml new file mode 100644 index 00000000000..9203713583c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/info.xml @@ -0,0 +1,6 @@ + + + CYW43012C0WKWBG + The CYW43012C0WKWBG devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/studio/presentation new file mode 100644 index 00000000000..c4e820824c4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/studio/presentation @@ -0,0 +1,2 @@ +Connectivity +43012 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/studio/view.xml new file mode 100644 index 00000000000..6edfd810af3 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012C0WKWBG/studio/view.xml @@ -0,0 +1,23 @@ + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0EKUBG/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0EKUBG/studio/presentation index 3d4d778bec5..c4e820824c4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0EKUBG/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0EKUBG/studio/presentation @@ -1,2 +1,2 @@ -Connectivity -43012 +Connectivity +43012 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0KFFBH/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0KFFBH/studio/presentation index 3d4d778bec5..c4e820824c4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0KFFBH/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012TC0KFFBH/studio/presentation @@ -1,2 +1,2 @@ -Connectivity -43012 +Connectivity +43012 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012WKWBG/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012WKWBG/studio/presentation index 3d4d778bec5..c4e820824c4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012WKWBG/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/43012C0/CYW43012WKWBG/studio/presentation @@ -1,2 +1,2 @@ -Connectivity -43012 +Connectivity +43012 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW43438KUBG/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW43438KUBG/studio/presentation index 5ec34f1652b..8d1f11ae896 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW43438KUBG/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW43438KUBG/studio/presentation @@ -1,2 +1,2 @@ -Connectivity -43438 +Connectivity +43438 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKUBG/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKUBG/studio/presentation index ffe87890355..2dfac14f37b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKUBG/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKUBG/studio/presentation @@ -1,2 +1,2 @@ -Connectivity -4343W +Connectivity +4343W diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKWBG/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKWBG/studio/presentation index ffe87890355..2dfac14f37b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKWBG/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/Connectivity/4343A1/CYW4343WKWBG/studio/presentation @@ -1,2 +1,2 @@ -Connectivity -4343W +Connectivity +4343W diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A256K/PSoC6A256K/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A256K/PSoC6A256K/base/view.xml new file mode 100644 index 00000000000..1c0dee34624 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A256K/PSoC6A256K/base/view.xml @@ -0,0 +1,16 @@ + + + 0xFFFF + 0xFF + F + F + CortexM0p,CortexM4 + Cypress + 262144 + 131072 + 68-QFN + 68 + 1700 + 3600 + The PSoC6A256K device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A256K/PSoC6A256K/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A256K/PSoC6A256K/info.xml new file mode 100644 index 00000000000..bd1a5977c8c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A256K/PSoC6A256K/info.xml @@ -0,0 +1,6 @@ + + + PSoC6A256K + The PSoC6A256K devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A256K/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A256K/info.xml new file mode 100644 index 00000000000..9b82c14cd4b --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A256K/info.xml @@ -0,0 +1,5 @@ + + + PSoC6A256K + The PSoC6A256K devices + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D14/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D14/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D14/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D14/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D44/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D44/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248AZI-S2D44/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248BZI-S2D44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248BZI-S2D44/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248BZI-S2D44/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248BZI-S2D44/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248FNI-S2D43/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248FNI-S2D43/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248FNI-S2D43/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C6248FNI-S2D43/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-D44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-D44/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-D44/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-D44/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D14/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D14/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D14/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D14/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D44/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D44/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AAZI-S2D44/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-D44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-D44/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-D44/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-D44/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D04/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D04/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D04/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D04/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D14/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D14/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D14/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D14/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44A0/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44A0/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44A0/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ABZI-S2D44A0/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-D43/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-D43/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-D43/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-D43/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-S2D43/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-S2D43/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-S2D43/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624AFNI-S2D43/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ALQI-D42/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ALQI-D42/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ALQI-D42/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CY8C624ALQI-D42/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/base/view.xml index 9e4a8b3ad5a..a4d7d4e022d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/base/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/base/view.xml @@ -1,9 +1,9 @@  - 0xE430 + 0xE470 0x102 1 - 1 + 2 CortexM0p,CortexM4 Cypress 1900544 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/presentation index 6a8bdde3e3d..6cd221015f4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 64 +PSoC 6 +PSoC 64 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/view.xml index 9b8bed892c9..d3c5001c8e2 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYB0644ABZI-S2D44/studio/view.xml @@ -49,7 +49,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/base/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/base/view.xml new file mode 100644 index 00000000000..229a90da03c --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/base/view.xml @@ -0,0 +1,16 @@ + + + 0xE4A0 + 0x102 + 1 + 2 + CortexM0p,CortexM4 + Cypress + 1900544 + 1048576 + 124-BGA + 124 + 1700 + 3600 + The CYS0644ABZI-S2D44 device. + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/info.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/info.xml new file mode 100644 index 00000000000..a89889b763a --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/info.xml @@ -0,0 +1,6 @@ + + + CYS0644ABZI-S2D44 + The CYS0644ABZI-S2D44 devices + true + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/studio/presentation new file mode 100644 index 00000000000..6cd221015f4 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/studio/presentation @@ -0,0 +1,2 @@ +PSoC 6 +PSoC 64 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/studio/view.xml new file mode 100644 index 00000000000..1ca4a73beca --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/CYS0644ABZI-S2D44/studio/view.xml @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/studio/clocks.cysem b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/studio/clocks.cysem index 44caf60459c..25ec63fbdb3 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/studio/clocks.cysem +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A2M/studio/clocks.cysem @@ -468,7 +468,7 @@ 2 - Watch Crystal Oscillator: This source is driven from an off-chip watch crystal that provides an extremely accurate source. This clock is stopped in the hibernate power mode. + Watch Crystal Oscillator: This source is driven from an off-chip watch crystal that provides an extremely accurate source. This clock runs in hibernate power mode. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D02/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D02/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D02/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D02/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D12/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D12/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D12/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D12/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D42/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D42/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D42/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D42/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D62/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D62/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D62/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D62/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D72/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D72/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D72/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245AZI-S3D72/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D11/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D11/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D11/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D11/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D11/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D11/studio/view.xml index 37705405931..f99a653de31 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D11/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D11/studio/view.xml @@ -33,7 +33,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D41/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D41/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D41/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D41/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D41/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D41/studio/view.xml index a3fb55c953d..9201578557d 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D41/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D41/studio/view.xml @@ -33,7 +33,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D71/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D71/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D71/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D71/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D71/studio/view.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D71/studio/view.xml index 08aaff161bd..2e28ce6934f 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D71/studio/view.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245FNI-S3D71/studio/view.xml @@ -33,7 +33,7 @@ - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D02/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D02/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D02/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D02/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D12/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D12/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D12/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D12/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D42/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D42/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D42/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D42/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D62/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D62/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D62/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D62/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D72/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D72/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D72/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245LQI-S3D72/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CY8C6245W-S3D72/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/studio/presentation index 6a8bdde3e3d..6cd221015f4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/CYB06445LQI-S3D42/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 64 +PSoC 6 +PSoC 64 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/studio/clocks.cysem b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/studio/clocks.cysem index f160ae144a7..b8d28ed2dc7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/studio/clocks.cysem +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6A512K/studio/clocks.cysem @@ -433,7 +433,7 @@ 2 - Watch Crystal Oscillator: This source is driven from an off-chip watch crystal that provides an extremely accurate source. This clock is stopped in the hibernate power mode. + Watch Crystal Oscillator: This source is driven from an off-chip watch crystal that provides an extremely accurate source. This clock runs in hibernate power mode. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6016BZI-F04/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6016BZI-F04/studio/presentation index 976b687d88c..23e88077a48 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6016BZI-F04/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6016BZI-F04/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 60 +PSoC 6 +PSoC 60 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6036BZI-F04/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6036BZI-F04/studio/presentation index 976b687d88c..23e88077a48 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6036BZI-F04/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6036BZI-F04/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 60 +PSoC 6 +PSoC 60 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6116BZI-F54/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6116BZI-F54/studio/presentation index 7e90374eb12..5a9f775be91 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6116BZI-F54/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6116BZI-F54/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 61 +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117BZI-F34/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117BZI-F34/studio/presentation index 7e90374eb12..5a9f775be91 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117BZI-F34/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117BZI-F34/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 61 +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117FDI-F02/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117FDI-F02/studio/presentation index 7e90374eb12..5a9f775be91 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117FDI-F02/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117FDI-F02/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 61 +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117WI-F34/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117WI-F34/studio/presentation index 7e90374eb12..5a9f775be91 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117WI-F34/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6117WI-F34/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 61 +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F14/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F14/studio/presentation index 7e90374eb12..5a9f775be91 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F14/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F14/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 61 +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F34/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F34/studio/presentation index 7e90374eb12..5a9f775be91 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F34/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136BZI-F34/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 61 +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FDI-F42/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FDI-F42/studio/presentation index 7e90374eb12..5a9f775be91 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FDI-F42/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FDI-F42/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 61 +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FTI-F42/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FTI-F42/studio/presentation index 7e90374eb12..5a9f775be91 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FTI-F42/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6136FTI-F42/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 61 +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F14/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F14/studio/presentation index 7e90374eb12..5a9f775be91 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F14/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F14/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 61 +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F34/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F34/studio/presentation index 7e90374eb12..5a9f775be91 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F34/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F34/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 61 +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F54/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F54/studio/presentation index 7e90374eb12..5a9f775be91 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F54/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137BZI-F54/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 61 +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137FDI-F02/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137FDI-F02/studio/presentation index 7e90374eb12..5a9f775be91 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137FDI-F02/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137FDI-F02/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 61 +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137WI-F54/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137WI-F54/studio/presentation index 7e90374eb12..5a9f775be91 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137WI-F54/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6137WI-F54/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 61 +PSoC 6 +PSoC 61 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6246BZI-D04/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6246BZI-D04/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6246BZI-D04/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6246BZI-D04/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BFI-D54/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BFI-D54/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BFI-D54/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BFI-D54/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-AUD54/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-AUD54/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-AUD54/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-AUD54/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D34/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D34/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D34/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D34/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D44/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D44/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D44/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D54/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D54/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D54/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247BZI-D54/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D02/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D02/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D02/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D02/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D32/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D32/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D32/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D32/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D52/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D52/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D52/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FDI-D52/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FTI-D52/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FTI-D52/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FTI-D52/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247FTI-D52/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247WI-D54/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247WI-D54/studio/presentation index 2d84ef27e9f..33e940a6d9a 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247WI-D54/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6247WI-D54/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 62 +PSoC 6 +PSoC 62 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF03/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF03/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF03/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF03/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF04/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF04/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF04/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF04/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF53/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF53/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF53/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF53/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF54/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF54/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF54/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6316BZI-BLF54/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD13/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD13/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD13/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD13/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD14/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD14/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD14/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLD14/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF03/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF03/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF03/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF03/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF04/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF04/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF04/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BLF04/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BUD13/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BUD13/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BUD13/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336BZI-BUD13/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF02/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF02/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF02/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF02/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF42/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF42/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF42/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6336LQI-BLF42/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6337BZI-BLF13/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6337BZI-BLF13/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6337BZI-BLF13/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6337BZI-BLF13/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD33/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD33/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD33/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD33/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD34/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD34/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD34/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD34/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD43/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD43/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD43/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD43/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD44/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD44/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD44/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD44/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD53/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD53/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD53/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD53/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD54/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD54/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD54/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BLD54/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD33/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD33/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD33/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD33/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD43/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD43/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD43/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD43/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD53/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD53/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD53/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347BZI-BUD53/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD13/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD13/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD13/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD13/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD33/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD33/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD33/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD33/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD43/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD43/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD43/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD43/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD53/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD53/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD53/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BLD53/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD13/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD13/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD13/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD13/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD33/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD33/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD33/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD33/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD43/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD43/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD43/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD43/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD53/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD53/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD53/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347FMI-BUD53/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347LQI-BLD52/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347LQI-BLD52/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347LQI-BLD52/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C6347LQI-BLD52/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-BLD74/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-BLD74/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-BLD74/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-BLD74/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-MD76/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-MD76/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-MD76/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637BZI-MD76/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637FMI-BLD73/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637FMI-BLD73/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637FMI-BLD73/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C637FMI-BLD73/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237BZ-BLE/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237BZ-BLE/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237BZ-BLE/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237BZ-BLE/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237FM-BLE/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237FM-BLE/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237FM-BLE/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CY8C68237FM-BLE/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD53/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD53/studio/presentation index 6a8bdde3e3d..6cd221015f4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD53/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD53/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 64 +PSoC 6 +PSoC 64 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/studio/presentation index 6a8bdde3e3d..6cd221015f4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-BLD54/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 64 +PSoC 6 +PSoC 64 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/studio/presentation index 6a8bdde3e3d..6cd221015f4 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYB06447BZI-D54/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 64 +PSoC 6 +PSoC 64 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYBLE-416045-02/studio/presentation b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYBLE-416045-02/studio/presentation index d3b5d7b9fab..1bcadca24c7 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYBLE-416045-02/studio/presentation +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/CYBLE-416045-02/studio/presentation @@ -1,2 +1,2 @@ -PSoC 6 -PSoC 63 +PSoC 6 +PSoC 63 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/clocks.cysem b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/clocks.cysem index fa25ded8e91..19d1b2f0523 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/clocks.cysem +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/clocks.cysem @@ -1,5 +1,5 @@  - + @@ -1082,7 +1082,7 @@ SYS_TICK 2 - Watch Crystal Oscillator: This source is driven from an off-chip watch crystal that provides an extremely accurate source. This clock is stopped in the hibernate power mode. + Watch Crystal Oscillator: This source is driven from an off-chip watch crystal that provides an extremely accurate source. This clock runs in hibernate power mode. @@ -1628,8 +1628,8 @@ SYS_TICK - + @@ -1866,17 +1866,17 @@ SYS_TICK - + - - - + + - - + + + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/clocks.cyvis b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/clocks.cyvis index 709240dc826..a0265f82a97 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/clocks.cyvis +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/PSoC6ABLE2/studio/clocks.cyvis @@ -1,5 +1,5 @@  - + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxprofile_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxprofile_v1.cydata index 6b0476263f4..9f3fb6a694b 100644 Binary files a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxprofile_v1.cydata and b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxprofile_v1.cydata differ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxs40srss_v1-power.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxs40srss_v1-power.cydata deleted file mode 100644 index a9be78bedbe..00000000000 Binary files a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxs40srss_v1-power.cydata and /dev/null differ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxs40srss_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxs40srss_v1.cydata index 4c796d89b36..6546bc53b44 100644 Binary files a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxs40srss_v1.cydata and b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxs40srss_v1.cydata differ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxsdhc_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxsdhc_v1.cydata index 06b597a9e2b..0974ae86069 100644 Binary files a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxsdhc_v1.cydata and b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxsdhc_v1.cydata differ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxtcpwm_v1.cydata b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxtcpwm_v1.cydata index 25d4895ca6f..83d0cdbe93c 100644 Binary files a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxtcpwm_v1.cydata and b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/connectivity/mxtcpwm_v1.cydata differ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/features.mk b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/features.mk index dc60a1a3edb..093c829b3ae 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/features.mk +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/devices/MXS40/studio/features.mk @@ -1,47 +1,50 @@ -# This file defines variables for various sets of devices. Each variable is a -# list of the MPNs that have that capability or feature. - -# Major device capabilities. -CY_DEVICES_WITH_M0P=CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6247FDI-D52 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6347LQI-BLD52 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 -CY_DEVICES_WITH_BLE=CY8C6336BZI-BLF03 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 -CY_DEVICES_WITH_UDBS=CY8C6116BZI-F54 CY8C6136BZI-F34 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6316BZI-BLF53 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C6247FDI-D32 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6247FDI-D52 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6316BZI-BLF54 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6347LQI-BLD52 -CY_DEVICES_WITH_FS_USB=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C637BZI-MD76 CY8C6137FDI-F02 CY8C6117FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-D54 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 -CY_DEVICES_WITH_CAPSENSE=CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245W-S3D72 -CY_DEVICES_WITH_CRYPTO=CY8C6116BZI-F54 CY8C6137BZI-F54 CY8C6247BZI-D44 CY8C6247BZI-D54 CY8C6316BZI-BLF53 CY8C6347BZI-BLD43 CY8C6347BZI-BLD53 CY8C6347FMI-BLD43 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6347BZI-BUD43 CY8C6347BZI-BUD53 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6316BZI-BLF54 CY8C6347BZI-BLD44 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD43 CY8C6137WI-F54 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245W-S3D72 - -# Different classifications of devices. -CY_DEVICES_WITH_DIE_PSOC6ABLE2=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6336BZI-BLF03 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6137FDI-F02 CY8C6117FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 -CY_DEVICES_WITH_DIE_PSOC6A2M=CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 -CY_DEVICES_WITH_DIE_PSOC6A512K=CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 - -CY_DEVICES_WITH_FLASH_KB_512=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6246BZI-D04 CY8C6336BZI-BLF03 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6336BZI-BUD13 CY8C6136FDI-F42 CY8C6136FTI-F42 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 -CY_DEVICES_WITH_FLASH_KB_1024=CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6137FDI-F02 CY8C6117FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6247FDI-D52 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CY8C6347LQI-BLD52 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 -CY_DEVICES_WITH_FLASH_KB_832=CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 -CY_DEVICES_WITH_FLASH_KB_2048=CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C624ALQI-D42 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 -CY_DEVICES_WITH_FLASH_KB_1856=CYB0644ABZI-S2D44 -CY_DEVICES_WITH_FLASH_KB_448=CYB06445LQI-S3D42 - -CY_DEVICES_WITH_SRAM_KB_128=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6246BZI-D04 CY8C6336BZI-BLF03 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6336BZI-BUD13 CY8C6136FDI-F42 CY8C6136FTI-F42 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 -CY_DEVICES_WITH_SRAM_KB_288=CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6137FDI-F02 CY8C6117FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6247FDI-D52 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6347LQI-BLD52 -CY_DEVICES_WITH_SRAM_KB_1024=CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 -CY_DEVICES_WITH_SRAM_KB_512=CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 -CY_DEVICES_WITH_SRAM_KB_256=CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 - -CY_DEVICES_WITH_MAX_SPEED_MHZ_150=CY8C6036BZI-F04 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6336BZI-BLF03 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6137FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6336BZI-BLF04 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 -CY_DEVICES_WITH_MAX_SPEED_MHZ_50=CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6117BZI-F34 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6117FDI-F02 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6117WI-F34 - -CY_DEVICES_WITH_PACKAGE_124-BGA=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C637BZI-MD76 CY8C6247BZI-AUD54 CY8C6247BFI-D54 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-D54 CY8C624ABZI-D44 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C6248BZI-D44 CYB0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C6248BZI-S2D44 -CY_DEVICES_WITH_PACKAGE_116-BGA-BLE=CY8C6336BZI-BLF03 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C637BZI-BLD74 CY8C68237BZ-BLE CY8C6337BZI-BLF13 CYB06447BZI-BLD53 -CY_DEVICES_WITH_PACKAGE_104-M-CSP-BLE=CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637FMI-BLD73 CY8C68237FM-BLE -CY_DEVICES_WITH_PACKAGE_80-WLCSP=CY8C6137FDI-F02 CY8C6117FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 -CY_DEVICES_WITH_PACKAGE_116-BGA-USB=CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 -CY_DEVICES_WITH_PACKAGE_124-BGA-SIP=CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CYB06447BZI-BLD54 -CY_DEVICES_WITH_PACKAGE_43-SMT=CYBLE-416045-02 -CY_DEVICES_WITH_PACKAGE_104-M-CSP-BLE-USB=CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 -CY_DEVICES_WITH_PACKAGE_68-QFN-BLE=CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 -CY_DEVICES_WITH_PACKAGE_128-TQFP=CY8C624AAZI-D44 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248AZI-D44 CY8C624AAZI-S2D44 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248AZI-S2D44 -CY_DEVICES_WITH_PACKAGE_100-WLCSP=CY8C624AFNI-D43 CY8C6248FNI-D43 CY8C624AFNI-S2D43 CY8C6248FNI-S2D43 -CY_DEVICES_WITH_PACKAGE_68-QFN=CY8C624ALQI-D42 CY8C6245LQI-S3D72 CY8C6245LQI-S3D62 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245LQI-S3D12 CY8C6245LQI-S3D02 -CY_DEVICES_WITH_PACKAGE_100-TQFP=CY8C6245AZI-S3D72 CY8C6245AZI-S3D62 CY8C6245AZI-S3D42 CY8C6245AZI-S3D12 CY8C6245AZI-S3D02 CY8C6245W-S3D72 -CY_DEVICES_WITH_PACKAGE_49-WLCSP=CY8C6245FNI-S3D71 CY8C6245FNI-S3D41 CY8C6245FNI-S3D11 - +# This file defines variables for various sets of devices. Each variable is a +# list of the MPNs that have that capability or feature. + +# Major device capabilities. +CY_DEVICES_WITH_M0P=CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6247FDI-D52 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6347LQI-BLD52 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 PSoC6A256K +CY_DEVICES_WITH_BLE=CY8C6336BZI-BLF03 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 +CY_DEVICES_WITH_UDBS=CY8C6116BZI-F54 CY8C6136BZI-F34 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6316BZI-BLF53 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C6247FDI-D32 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6247FDI-D52 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6316BZI-BLF54 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6347LQI-BLD52 +CY_DEVICES_WITH_FS_USB=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C637BZI-MD76 CY8C6137FDI-F02 CY8C6117FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-D54 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 PSoC6A256K +CY_DEVICES_WITH_CAPSENSE=CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245W-S3D72 +CY_DEVICES_WITH_CRYPTO=CY8C6116BZI-F54 CY8C6137BZI-F54 CY8C6247BZI-D44 CY8C6247BZI-D54 CY8C6316BZI-BLF53 CY8C6347BZI-BLD43 CY8C6347BZI-BLD53 CY8C6347FMI-BLD43 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6347BZI-BUD43 CY8C6347BZI-BUD53 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6316BZI-BLF54 CY8C6347BZI-BLD44 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD43 CY8C6137WI-F54 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245W-S3D72 +CY_DEVICES_SECURE=CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CYB06445LQI-S3D42 + +# Different classifications of devices. +CY_DEVICES_WITH_DIE_PSOC6ABLE2=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 CY8C6136BZI-F14 CY8C6136BZI-F34 CY8C6137BZI-F14 CY8C6137BZI-F34 CY8C6137BZI-F54 CY8C6117BZI-F34 CY8C6246BZI-D04 CY8C6247BZI-D44 CY8C6247BZI-D34 CY8C6247BZI-D54 CY8C6336BZI-BLF03 CY8C6316BZI-BLF03 CY8C6316BZI-BLF53 CY8C6336BZI-BLD13 CY8C6347BZI-BLD43 CY8C6347BZI-BLD33 CY8C6347BZI-BLD53 CY8C6347FMI-BLD13 CY8C6347FMI-BLD43 CY8C6347FMI-BLD33 CY8C6347FMI-BLD53 CY8C637BZI-MD76 CY8C637BZI-BLD74 CY8C637FMI-BLD73 CY8C68237BZ-BLE CY8C68237FM-BLE CY8C6137FDI-F02 CY8C6117FDI-F02 CY8C6247FDI-D02 CY8C6247FDI-D32 CY8C6336BZI-BUD13 CY8C6347BZI-BUD43 CY8C6347BZI-BUD33 CY8C6347BZI-BUD53 CY8C6337BZI-BLF13 CY8C6136FDI-F42 CY8C6247FDI-D52 CY8C6136FTI-F42 CY8C6247FTI-D52 CY8C6247BZI-AUD54 CY8C6336BZI-BLF04 CY8C6316BZI-BLF04 CY8C6316BZI-BLF54 CY8C6336BZI-BLD14 CY8C6347BZI-BLD44 CY8C6347BZI-BLD34 CY8C6347BZI-BLD54 CY8C6247BFI-D54 CYBLE-416045-02 CY8C6347FMI-BUD53 CY8C6347FMI-BUD13 CY8C6347FMI-BUD43 CY8C6347FMI-BUD33 CY8C6137WI-F54 CY8C6117WI-F34 CY8C6247WI-D54 CYB06447BZI-BLD54 CYB06447BZI-BLD53 CYB06447BZI-D54 CY8C6336LQI-BLF02 CY8C6336LQI-BLF42 CY8C6347LQI-BLD52 +CY_DEVICES_WITH_DIE_PSOC6A2M=CY8C624ABZI-D44 CY8C624AAZI-D44 CY8C624AFNI-D43 CY8C624ABZI-D04 CY8C624ABZI-D14 CY8C624AAZI-D14 CY8C6248AZI-D14 CY8C6248BZI-D44 CY8C6248AZI-D44 CY8C6248FNI-D43 CY8C624ALQI-D42 CYB0644ABZI-S2D44 CYS0644ABZI-S2D44 CY8C624ABZI-S2D44A0 CY8C624ABZI-S2D44 CY8C624AAZI-S2D44 CY8C624AFNI-S2D43 CY8C624ABZI-S2D04 CY8C624ABZI-S2D14 CY8C624AAZI-S2D14 CY8C6248AZI-S2D14 CY8C6248BZI-S2D44 CY8C6248AZI-S2D44 CY8C6248FNI-S2D43 +CY_DEVICES_WITH_DIE_PSOC6A512K=CY8C6245AZI-S3D72 CY8C6245LQI-S3D72 CY8C6245FNI-S3D71 CY8C6245AZI-S3D62 CY8C6245LQI-S3D62 CY8C6245AZI-S3D42 CY8C6245LQI-S3D42 CYB06445LQI-S3D42 CY8C6245FNI-S3D41 CY8C6245AZI-S3D12 CY8C6245LQI-S3D12 CY8C6245FNI-S3D11 CY8C6245AZI-S3D02 CY8C6245LQI-S3D02 CY8C6245W-S3D72 +CY_DEVICES_WITH_DIE_PSOC6A256K=PSoC6A256K + +CY_DEVICES_WITH_FLASH_KB_512=CY8C6036BZI-F04 CY8C6016BZI-F04 CY8C6116BZI-F54 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CY8C6245W-S3D72 +CY_DEVICES_WITH_PACKAGE_49-WLCSP=CY8C6245FNI-S3D71 CY8C6245FNI-S3D41 CY8C6245FNI-S3D11 + diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.dat b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.dat index c7973f67375..ad49616d539 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.dat +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.dat @@ -1 +1 @@ -1.1.3.51 +1.1.3.98 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.xml index b1f03ef7600..5e023aea7ec 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/udd/version.xml @@ -1 +1 @@ -1.1.3.51 +1.1.3.98 diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/version.xml b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/version.xml index 909bd30c581..eda4fd96d1b 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/version.xml +++ b/targets/TARGET_Cypress/TARGET_PSOC6/psoc6pdl/version.xml @@ -1 +1 @@ -1.4.0.1889 +1.4.1.2240 diff --git a/targets/targets.json b/targets/targets.json index 32617dbc4e3..02ebdeb554c 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -2160,7 +2160,7 @@ "secure-ram-start": "0x30000000", "secure-ram-size": "0x22000" } - }, + }, "HANI_IOT": { "inherits": ["LPC55S69_NS"], "detect_code": ["0360"], @@ -9164,7 +9164,7 @@ "macros_add": ["MCU_PSOC6_M4", "CY_RTOS_AWARE", "CY_USING_HAL", "MBED_TICKLESS"], "public": false }, - "CY8CMOD_062_4343W": { + "CY8CPROTO_062_4343W": { "inherits": ["MCU_PSOC6_M4"], "features": ["BLE"], "components_add": ["WHD", "4343W", "CYW43XXX"], @@ -9175,28 +9175,42 @@ "CORDIO" ], "macros_add": ["CY8C624ABZI_D44", "CYBSP_WIFI_CAPABLE"], - "public": false, + "detect_code": [ + "1901" + ], + "bootloader_supported": false, + "sectors": [ + [ + 268435456, + 512 + ] + ], "overrides": { "network-default-interface-type": "WIFI" } }, - "CY8CMOD_062S2_43012": { + "CY8CKIT_062S2_43012": { "inherits": ["MCU_PSOC6_M4"], "features": ["BLE"], "components_add": ["WHD", "43012", "CYW43XXX"], "device_has_remove": ["ANALOGOUT"], + "supported_form_factors": [ + "ARDUINO" + ], "extra_labels_add": [ "PSOC6_02", "MXCRYPTO_02", "CORDIO" ], "macros_add": ["CY8C624ABZI_D44", "CYBSP_WIFI_CAPABLE"], - "public": false, + "detect_code": [ + "190B" + ], "overrides": { "network-default-interface-type": "WIFI" } }, - "CY8CMOD_062S3_4343W": { + "CY8CPROTO_062S3_4343W": { "inherits": ["MCU_PSOC6_M4"], "features": ["BLE"], "components_add": ["WHD", "4343W", "CYW43XXX"], @@ -9212,7 +9226,9 @@ "CY_ENABLE_XIP_PROGRAM", "CY_STORAGE_WIFI_DATA=\".cy_xip\"" ], - "public": false, + "detect_code": [ + "190E" + ], "overrides": { "network-default-interface-type": "WIFI", "xip-enable": true @@ -9253,9 +9269,6 @@ ], "macros_add": ["CY8C6247BZI_D54", "CYHAL_UDB_SDIO", "CYBSP_WIFI_CAPABLE"], "detect_code": ["1900"], - "post_binary_hook": { - "function": "PSOC6Code.complete" - }, "bootloader_supported": false, "sectors": [[268435456, 512]], "overrides": { @@ -9263,30 +9276,6 @@ }, "program_cycle_s": 10 }, - "CY8CPROTO_062_4343W": { - "inherits": ["CY8CMOD_062_4343W"], - "detect_code": ["1901"], - "post_binary_hook": { - "function": "PSOC6Code.complete" - }, - "bootloader_supported": false, - "sectors": [[268435456, 512]] - }, - "CY8CPROTO_062S3_4343W": { - "inherits": ["CY8CMOD_062S3_4343W"], - "detect_code": ["190E"], - "post_binary_hook": { - "function": "PSOC6Code.complete" - } - }, - "CY8CKIT_062S2_43012": { - "inherits": ["CY8CMOD_062S2_43012"], - "supported_form_factors": ["ARDUINO"], - "detect_code": ["190B"], - "post_binary_hook": { - "function": "PSOC6Code.complete" - } - }, "CY8CKIT_062_BLE": { "inherits": ["MCU_PSOC6_M4"], "device_has_remove": ["USBDEVICE"], @@ -9297,9 +9286,6 @@ ], "macros_add": ["CY8C6347BZI_BLD53"], "detect_code": ["1902"], - "post_binary_hook": { - "function": "PSOC6Code.complete" - }, "sectors": [[268443648, 512]], "bootloader_supported": false }, @@ -9313,9 +9299,6 @@ ], "macros_add": ["CYBLE_416045_02"], "detect_code": ["1904"], - "post_binary_hook": { - "function": "PSOC6Code.complete" - }, "sectors": [[268443648, 512]], "bootloader_supported": false }, @@ -9348,9 +9331,6 @@ ], "macros_add": ["CY8C6247BZI_D54", "CYHAL_UDB_SDIO", "CYBSP_WIFI_CAPABLE"], "detect_code": ["1900"], - "post_binary_hook": { - "function": "PSOC6Code.complete" - }, "bootloader_supported": false, "sectors": [[268435456, 512]], "overrides": { @@ -9369,9 +9349,6 @@ ], "macros_add": ["CY8C6247BZI_D54", "CYHAL_UDB_SDIO", "CYBSP_WIFI_CAPABLE"], "detect_code": ["1906"], - "post_binary_hook": { - "function": "PSOC6Code.complete" - }, "overrides": { "network-default-interface-type": "WIFI" } @@ -9383,22 +9360,66 @@ "components_add": ["WHD", "43012", "CYW43XXX"], "components_remove": ["QSPIF"], "device_has_remove": ["ANALOGOUT", "QSPI"], - "macros_remove": ["MBEDTLS_CONFIG_HW_SUPPORT"], "extra_labels_add": [ "PSOC6_01", "MXCRYPTO_01", "CORDIO" ], - "extra_labels_remove": ["MXCRYPTO"], "macros_add": ["CY8C6247FDI_D52", "CYHAL_UDB_SDIO", "CYBSP_WIFI_CAPABLE"], "detect_code": ["1903"], - "post_binary_hook": { - "function": "PSOC6Code.complete" - }, "overrides": { "network-default-interface-type": "WIFI" } }, + "CYSBSYSKIT_01": { + "inherits": [ + "MCU_PSOC6_M4" + ], + "components_add": [ + "SCL", + "43012", + "CYW43XXX" + ], + "device_has_remove": [ + "ANALOGOUT" + ], + "components_remove": [ + "CM0P_SLEEP" + ], + "extra_labels_add": [ + "PSOC6_02", + "MXCRYPTO_02" + ], + "macros_add": [ + "CY8C624AFNI_D43", + "CYBSP_WIFI_CAPABLE" + ], + "overrides": { + "network-default-interface-type": "WIFI", + "deep-sleep-latency": 0 + }, + "detect_code": [ + "1912" + ], + "macros_remove": [ + "CYBSP_WIFI_CAPABLE", + "MBED_TICKLESS" + ], + "config": { + "np_cloud_disable": { + "help": "Value: Tells the np to connect to cloud or not", + "value": false + }, + "np_wifi_enable": { + "help": "Value: Tells the np to connect to wifi with its network credentials or wait till cp provides network credentials to it", + "value": false + } + }, + "forced_reset_timeout": 5, + "post_binary_hook": { + "function": "PSOC6Code.complete" + } + }, "FUTURE_SEQUANA_M0": { "inherits": ["MCU_PSOC6_M0"], "supported_form_factors": ["ARDUINO"],